Sim PE User's Manual
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ModelSim® PE User’s Manual
Software Version 10.0d
© 1991-2011 Mentor Graphics Corporation
All rights reserved.
This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
document may duplicate this document in whole or in part for internal business purposes only, provided that this entire
notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable
effort to prevent the unauthorized use and distribution of the proprietary information.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make
changes in specifications and other information contained in this publication without prior notice, and the
reader should, in all cases, consult Mentor Graphics to determine whether any changes have been
made.
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written agreements between Mentor Graphics and its customers. No representation or other affirmation
of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor
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MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.
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EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
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U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely
at private expense and are commercial computer software provided with restricted rights. Use,
duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the
restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.72023(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted
Rights clause at FAR 52.227-19, as applicable.
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Mentor Graphics Corporation
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Table of Contents
Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Structure and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Steps for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1 — Collect Files and Map Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2 — Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3 — Load the Design for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4 — Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5 — Debug the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Line Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of an Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installation Directory Pathnames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Where to Find ModelSim Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deprecated Features, Commands, and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 2
Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Design Object Icons and Their Meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Setting Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the Find and Filter Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Using the Find Options Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
User-Defined Radices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Using the radix define Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Saving and Reloading Formats and Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Active Time Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Elements of the Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Selecting the Active Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Rearranging the Main Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Navigating in the Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Main Window Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Main Window Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Call Stack Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Related Commands of the Call Stack Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Table of Contents
GUI Elements of the Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacity Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Capacity Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Graph Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Graph Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Class Graph Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Tree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Class Tree Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Coverage Analysis Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Code Coverage Data and Current Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage Details Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dataflow Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the FSM List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Viewer Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the FSM Viewer Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instance Coverage Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instance Coverage Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Instance Coverage Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Library Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Locals Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Locals Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Locals Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory List Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Memory List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Data Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Memory Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Viewer Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Message Viewer Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Objects Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Objects Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processes Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Profiling Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Profile Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ModelSim PE User’s Manual, v10.0d
Table of Contents
Opening Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dragging and Dropping Objects into the Wave and List Windows . . . . . . . . . . . . . . . . . .
Setting your Context by Navigating Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage Data in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging with Source Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting File-Line Breakpoints with the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding File-Line Breakpoints with the bp Command . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing File-Line Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Conditional Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Checking Object Values and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Lines with Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performing Incremental Search for Specific Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customizing the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Structure Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Coverage in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verification Management Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controlling the Verification Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Verification Browser Column and Filter Settings . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Verification Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying the Transcript Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Data in the Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transcript Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUI Elements of the Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects to the Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanding Objects to Show Individual Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving and Reloading Format Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Add Objects to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Objects You Can View in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wave Window Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 3
Protecting Your Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Encryption Envelopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring the Encryption Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the `include Compiler Directive (Verilog only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling with +protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Runtime Encryption Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Language-Specific Usage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Usage Models for Protecting Verilog Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Usage Models for Protecting VHDL Source Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Proprietary Source Code Encryption Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Proprietary Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protecting Source Code Using -nodebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Encryption Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Encryption and Encoding Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How Encryption Envelopes Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Public Encryption Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Mentor Graphics Public Encryption Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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245
250
257
258
259
260
261
262
263
263
265
Chapter 4
Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What are Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What are the Benefits of Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Project Conversion Between Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Started with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1 — Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2 — Adding Items to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3 — Compiling the Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4 — Simulating a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Basic Project Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sorting the List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Simulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Organizing Projects with Folders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding a Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying File Properties and Project Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
File Compilation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accessing Projects from the Command Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
267
267
267
268
268
269
270
271
274
276
276
277
277
279
279
281
281
283
284
Chapter 5
Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Unit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working Library Versus Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Archives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working with Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Managing Library Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assigning a Logical Name to a Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Moving a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up Libraries for Group Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Resource Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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VHDL Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Predefined Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate IEEE Libraries Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regenerating Your Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Importing FPGA Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protecting Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
291
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Chapter 6
VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic VHDL Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compilation and Simulation of VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Design Library for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling a VHDL Design—the vcom Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating a VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Naming Behavior of VHDL For Generate Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differences Between Versions of VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator Resolution Limit for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Binding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delta Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the TextIO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syntax for File Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using STD_INPUT and STD_OUTPUT Within ModelSim . . . . . . . . . . . . . . . . . . . . . . .
TextIO Implementation Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing Strings and Aggregates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading and Writing Hexadecimal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dangling Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The ENDLINE Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The ENDFILE Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Alternative Input/Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flushing the TEXTIO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Providing Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VITAL Usage and Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VITAL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VITAL 1995 and 2000 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VITAL Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling and Simulating with Accelerated VITAL Packages . . . . . . . . . . . . . . . . . . . . .
VHDL Utilities Package (util) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
get_resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
init_signal_driver() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
init_signal_spy() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal_force() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal_release() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
to_real(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
to_time() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modeling Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Different Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Affecting Performance by Cancelling Scheduled Events. . . . . . . . . . . . . . . . . . . . . . . . . .
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295
295
295
296
300
301
301
304
305
306
309
309
310
310
310
311
311
312
312
312
313
313
313
313
314
314
314
315
315
316
316
316
316
317
317
318
319
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Chapter 7
Verilog and SystemVerilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standards, Nomenclature, and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Verilog Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Working Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Invoking the Verilog Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initializing enum Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemVerilog Multi-File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog-XL Compatible Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog-XL uselib Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Generate Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initializing Registers and Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator Resolution Limit (Verilog). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Ordering in Verilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging Event Order Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging Signal Segmentation Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Timing Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Force and Release Statements in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog-XL Compatible Simulator Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Escaped Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF Timing Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE Std 1364 System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemVerilog System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator-Specific System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog-XL Compatible System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE Std 1364 Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiler Directives for vlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog-XL Compatible Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog PLI/VPI and SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standards, Nomenclature, and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extensions to SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
329
329
331
331
331
332
335
335
337
339
340
341
343
344
345
347
347
349
352
354
356
365
365
365
367
367
367
368
369
371
372
378
380
381
381
383
384
384
384
Chapter 8
SystemC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Platforms and Compiler Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Building gcc with Custom Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Usage Flow for SystemC-Only Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommendations for using sc_main at the Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Shared Object Files for SystemC Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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387
388
389
390
393
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Binding to Verilog or SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limitations of Bind Support for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling SystemC Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Design Library for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Invoking the SystemC Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling Optimized and/or Debug Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying an Alternate g++ Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintaining Portability Between OSCI and the Simulator. . . . . . . . . . . . . . . . . . . . . . . . .
Using sccom in Addition to the Raw C++ Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling Changed Files Only (Incremental Compilation). . . . . . . . . . . . . . . . . . . . . . . .
Issues with C++ Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linking the Compiled Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating SystemC Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loading the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Time Unit and Simulator Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization and Cleanup of SystemC State-Based Code . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewable SystemC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewable SystemC Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveform Compare with SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging Source-Level Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Object and Type Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for Globals and Statics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for Aggregates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Dynamic Module Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing SystemC Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Properly Recognizing Derived Module Class Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Debugging of SystemC Channels and Variables. . . . . . . . . . . . . . . . . . . . . . . . . .
Modifying SystemC Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Modification Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differences Between the Simulator and OSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixed-Point Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Algorithmic C Datatype Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for cin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OSCI 2.2 Feature Implementation Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for OSCI TLM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Callback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accessing Command-Line Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
sc_stop Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Construction Parameters for SystemC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Troubleshooting SystemC Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unexplained Behaviors During Loading or Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Errors During Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents
Chapter 9
Mixed-Language Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Mixed-Language Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Separate Compilers with Common Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Hierarchical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using SystemVerilog bind Construct in Mixed-Language Designs . . . . . . . . . . . . . . . . . . .
Syntax of bind Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What Can Be Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical References to a VHDL Object from a Verilog/SystemVerilog Scope. . . . . .
Mapping of Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Binding to VHDL Enumerated Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Binding to a VHDL Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limitations to Bind Support for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator Resolution Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Runtime Modeling Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical References to SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical References In Mixed HDL and SystemC Designs. . . . . . . . . . . . . . . . . . . . .
Signal Connections Between Mixed HDL and SystemC Designs . . . . . . . . . . . . . . . . . . .
Mapping Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog and SystemVerilog to VHDL Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL To Verilog and SystemVerilog Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog or SystemVerilog and SystemC Signal Interaction And Mappings . . . . . . . . . . .
VHDL and SystemC Signal Interaction And Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Instantiating Verilog or SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog/SystemVerilog Instantiation Criteria Within VHDL. . . . . . . . . . . . . . . . . . . . . . .
Component Declaration for VHDL Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . .
vgencomp Component Declaration when VHDL Instantiates Verilog . . . . . . . . . . . . . . .
Modules with Bidirectional Pass Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modules with Unnamed Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog or SystemVerilog Instantiating VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Instantiation Criteria Within Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entity and Architecture Names and Escaped Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . .
Named Port Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sharing User-Defined Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Instantiating Verilog or SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Instantiation Criteria Within SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Foreign Module (Verilog) Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Support for SystemC Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog or SystemVerilog Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Instantiation Criteria for Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exporting SystemC Modules for Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Support for Verilog Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Instantiating VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Instantiation Criteria Within SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Foreign Module (VHDL) Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic Support for SystemC Instantiating VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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VHDL Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Instantiation Criteria for VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component Declaration for VHDL Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . .
vgencomp Component Declaration when VHDL Instantiates SystemC . . . . . . . . . . . . . .
Exporting SystemC Modules for VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Procedural Interface to SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC DPI Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Import Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calling SystemVerilog Export Tasks / Functions from SystemC . . . . . . . . . . . . . . . . . . .
SystemC Data Type Support in SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC Function Prototype Header File (sc_dpiheader.h). . . . . . . . . . . . . . . . . . . . . . . .
Support for Multiple SystemVerilog Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemC DPI Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Recording and Viewing Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What is a Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About the Source Code for Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About Transaction Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Transactions in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Viewing Commonalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Transaction Objects in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Transactions in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing a Transaction in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing a Transaction in the Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging with Tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Recording Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Recording Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Names of Streams and Substreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stream Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction UIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attribute Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Uses of the Same Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Anonymous Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Relationship in Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Life-cycle of a Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Handles and Memory Leaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Recording Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recording Transactions in Verilog and VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recording Transactions in SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCV Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLI Debugging Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog and VHDL API System Task Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
add_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
add_relation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
begin_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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create_transaction_stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
delete_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
end_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
free_transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 11
Recording Simulation Results With Datasets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving a Simulation to a WLF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WLF File Parameter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting the WLF File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multithreading on Linux and Solaris Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opening Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Dataset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Managing Multiple Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Managing Multiple Datasets in the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Restricting the Dataset Prefix Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving at Intervals with Dataset Snapshot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collapsing Time and Delta Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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574
575
576
577
578
578
579
580
580
580
581
582
583
584
585
586
587
587
Chapter 12
Waveform Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Objects You Can View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wave Window Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects to the Wave or List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects with Mouse Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects with Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects with a Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects with a Window Format File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cursor and Timeline Toolbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumping to a Signal Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measuring Time with Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syncing All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linking Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding Cursor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shortcuts for Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Time Markers in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working with Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanded Time in the Wave and List Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
589
589
590
590
591
592
592
592
593
593
593
593
596
597
597
598
598
599
599
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600
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Table of Contents
Expanded Time Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recording Expanded Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Expanded Time Information in the Wave Window . . . . . . . . . . . . . . . . . . . . . . .
Selecting the Expanded Time Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Between Time Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanding and Collapsing Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanded Time Viewing in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zooming the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zooming with the Menu, Toolbar and Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Zoom Range and Scroll Position with Bookmarks. . . . . . . . . . . . . . . . . . . . . . . . .
Searching in the Wave and List Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Searching for Values or Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Expression Builder for Expression Searches . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filtering the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Formatting the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Wave Window Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Formatting Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dividing the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Splitting Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wave Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deleting or Ungrouping a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Items to an Existing Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Removing Items from an Existing Wave Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Wave Group Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Composite Signals or Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Formatting the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting List Window Display Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Formatting Objects in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving the Window Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exporting Waveforms from the Wave window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exporting the Wave Window as a Bitmap Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Printing the Wave Window to a Postscript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Printing the Wave Window on the Windows Platform . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Waveforms Between Two Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving List Window Data to a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing SystemVerilog Class Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combining Objects into Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Virtual Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring New Line Triggering in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Gating Expressions to Control Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sampling Signals at a Clock Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examining Waveform Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Drivers of the Selected Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sorting a Group of Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating and Managing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
File-Line Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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601
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606
607
607
608
610
611
612
613
614
614
617
617
617
620
623
625
626
626
628
628
628
629
629
630
630
631
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634
634
635
635
635
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642
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Table of Contents
Saving and Restoring Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveform Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixed-Language Waveform Compare Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three Options for Setting up a Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up a Comparison with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting a Waveform Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Signals, Regions, and Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying the Comparison Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Compare Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Differences in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Differences in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Differences in Textual Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving and Reloading Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparing Hierarchical and Flattened Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
652
652
653
653
655
655
657
658
660
661
663
664
664
665
Chapter 13
Debugging with the Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dataflow Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dataflow Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Post-Simulation Debug Flow Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Tasks for Dataflow Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Objects to the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exploring the Connectivity of the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exploring Designs with the Embedded Wave Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tracing Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tracing the Source of an Unknown State (StX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Finding Objects by Name in the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatically Tracing All Paths Between Two Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dataflow Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Symbol Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current vs. Post-Simulation Command Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dataflow Window Graphic Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What Can I View in the Dataflow Window? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How is the Dataflow Window Linked to Other Windows? . . . . . . . . . . . . . . . . . . . . . . . .
How Can I Print and Save the Display? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How Do I Configure Window Options? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
667
667
668
668
670
670
671
674
675
676
678
678
680
680
682
683
683
683
684
686
Chapter 14
Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating and Editing Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating New Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opening Existing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Searching for Code in the Source Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Navigating Through Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data and Objects in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Determining Object Values and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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687
687
688
689
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692
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Table of Contents
Displaying Object Values with Source Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dragging Source Window Objects Into Other Windows . . . . . . . . . . . . . . . . . . . . . . . . . .
Highlighted Text in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hyperlinked Text in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Coverage Data in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Individual Breakpoints in a Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Breakpoints with the bp Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting SystemC Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving and Restoring Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Conditional Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting and Removing Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Source Window Preferences.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
695
697
697
698
698
700
701
701
701
702
704
705
707
707
707
Chapter 15
Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of Code Coverage Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Language and Datatype Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Usage Flow for Code Coverage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Coverage Types for Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling Simulation for Code Coverage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Code Coverage in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Coverage in the UCDB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Coverage in the Graphic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding Unexpected Coverage Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Coverage Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statement Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branch Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case and Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AllFalse Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Missing Branches in VHDL and Clock Optimizations. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition and Expression Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effect of Short-circuiting on Expression and Condition Coverage . . . . . . . . . . . . . . . . . .
Reporting Condition and Expression Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FEC Coverage Detailed Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UDP Coverage Details and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Condition and Expression Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog/SV Condition and Expression Type Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Toggle Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Toggle Coverage and Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Toggle Coverage Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog/SV Toggle Coverage Type Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Toggle Ports Only Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Toggle Coverage Data in the Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding Toggle Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting Toggle Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
709
710
710
711
712
712
713
715
715
717
718
718
718
719
720
720
720
722
722
723
729
732
732
733
733
733
734
735
735
736
740
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Finite State Machine Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What Objects can be Excluded? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Methods for Excluding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Toggle Exclusion Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exclude Nodes from Toggle Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Coverage Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving and Recalling Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the coverage report Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the toggle report Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Coverage Report Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting a Default Coverage Reporting Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XML Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HTML Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage Reporting on a Specific Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes on Coverage and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customizing Optimization Level for Coverage Runs. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interaction of Optimization and Coverage Arguments. . . . . . . . . . . . . . . . . . . . . . . . . . . .
741
741
742
742
742
750
751
753
755
757
758
759
761
761
761
762
762
762
762
763
Chapter 16
Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported FSM Design Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Design Style Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Multi-State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collecting FSM Coverage Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Coverage Metrics for FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Coverage Metrics Available in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Command Arguments for FSMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consolidated FSM Recognition Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recognized FSM Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Recognition Info Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM Coverage Text Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
765
765
766
766
769
769
770
771
772
774
774
775
775
777
Chapter 17
Coverage and Verification Management in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage and Verification Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What is the Unified Coverage Database? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of Total Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage and Simulator Use Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage View Mode and the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Tests and Collecting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collecting and Saving Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding Stored Test Data in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rerunning Tests and Executing Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
779
780
781
782
785
786
786
786
788
792
16
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Managing Test Data in UCDBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Merging Coverage Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warnings During Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ranking Coverage Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modifying UCDBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About the Merge Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Merge Usage Scenarios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing and Analyzing Verification Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storing User Attributes in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Test Data in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Test Data in the Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating Coverage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filtering Data in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retrieving Test Attribute Record Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
794
795
797
798
800
801
802
804
804
804
805
807
813
815
Chapter 18
C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Platforms and gdb Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running C Debug on Windows Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running C Debug from a DO File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stepping in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging Active or Suspended Threads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Known Problems With Stepping in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quitting C Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Finding Function Entry Points with Auto Find bp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identifying All Registered Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling Auto Step Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Find bp Versus Auto Step Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging Functions During Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLI Functions in Initialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VPI Functions in Initialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Completing Design Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging Functions when Quitting Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Debug Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
817
818
818
818
819
820
821
822
822
822
823
823
824
825
825
827
829
829
829
830
Chapter 19
Profiling Performance and Memory Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introducing Performance and Memory Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statistical Sampling Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Allocation Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Started with the Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling the Memory Allocation Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling the Statistical Sampling Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collecting Memory Allocation and Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running the Profiler on Windows with PLI/VPI Code . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interpreting Profiler Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
833
833
834
834
834
834
836
836
837
837
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Viewing Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Ranked Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Design Units Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Calltree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Structural Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Viewing Profile Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Integration with Source Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Analyzing C Code Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
In addition, the Verilog PLI/VPI requires maintenance of the simulator’s internal data structures
as well as the PLI/VPI data structures for portability. Searching Profiler Results . . 845
Reporting Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Enabling or Disabling Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Levels of Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Obtaining a Graphical Interface (GUI) Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Writing a Text-Based Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Chapter 20
Signal Spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Spy Formatting Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Spy Supported Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
disable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
enable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
init_signal_driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
init_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal_force. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal_release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
857
858
858
859
861
863
867
871
875
Chapter 21
Generating Stimulus with Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Started with the Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Waveform Editor Prior to Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Waveform Editor After Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Waveforms from Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Waveforms with Wave Create Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stretching and Moving Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating Directly from Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exporting Waveforms to a Stimulus File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driving Simulation with the Saved Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Mapping and Importing EVCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Waveform Compare with Created Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving the Waveform Editor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
877
877
877
878
879
880
881
882
884
884
884
885
886
886
887
Chapter 22
Standard Delay Format (SDF) Timing Annotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Specifying SDF Files for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
18
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Table of Contents
Instance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF Specification with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL VITAL SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF to VHDL Generic Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolving Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
$sdf_annotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF to Verilog Construct Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retain Delay Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Edge Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rounded Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF for Mixed VHDL and Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interconnect Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying the Wrong Instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Matching a Single Timing Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mistaking a Component or Module Name for an Instance Label. . . . . . . . . . . . . . . . . . . .
Forgetting to Specify the Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
890
890
891
891
891
892
893
894
895
898
900
901
901
902
902
902
903
903
904
904
904
Chapter 23
Value Change Dump (VCD) Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four-State VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended VCD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCD Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Extended VCD as Stimulus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating with Input Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replacing Instances with Output Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . .
VCD Commands and VCD Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using VCD Commands with SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compressing Files with VCD Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCD File from Source to Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCD Simulator Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCD to WLF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capturing Port Driver Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identifier Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolving Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
907
907
907
908
908
908
909
910
912
913
914
914
914
915
916
917
917
917
918
918
919
Chapter 24
Tcl and Macros (DO Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
Tcl Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
ModelSim PE User’s Manual, v10.0d
19
Table of Contents
Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tcl Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
If Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple-Line Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Evaluation Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tcl Relational Expression Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Variable Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Referencing Simulator State Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Considerations for the now Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulator Tcl Time Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Macros (DO Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Parameters with DO Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deleting a File from a .do Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Making Macro Parameters Optional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Useful Commands for Handling Breakpoints and Errors . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Action in DO Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
923
924
924
927
927
928
928
928
928
929
929
929
931
931
932
932
933
934
934
935
935
937
937
938
938
939
940
941
Appendix A
modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Organization of the modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Making Changes to the modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing the modelsim.ini Read-Only Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Runtime Options Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overriding the Default Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AmsStandard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AssertFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AutoExclusionsDisable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BindAtCompile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BreakOnAssertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CheckPlusargs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CheckpointCompressMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CheckSynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CodeCoverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CommandHistory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
943
943
943
944
944
948
948
949
949
950
950
951
951
951
952
952
952
953
20
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Table of Contents
CompilerTempDir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ConcurrentFileLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverCells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverClkOptBuiltins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverCountAll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverExcludeDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverFEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverMaxFECRows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverMaxUDPRows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverOpt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverRespectHandL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverReportCancelled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverShortCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverSub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoverUDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CppOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CppPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DatasetSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DefaultForceKind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DefaultRadix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DefaultRestartOptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DelayFileOpen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
displaymsgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DpiCppPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DpiOutOfTheBlue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DumpportsCollapse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EnumBaseInit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ErrorFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Explicit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExtendedToggleMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
fatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
floatfixlib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ForceSigNextIter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ForceUnsignedIntegerToVHDLInteger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FsmImplicitTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FsmResetTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FsmSingle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FsmXAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GenerateFormat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GenerateLoopIterationMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GenerateRecursionDepthMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GenerousIdentifierParsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GlobalSharedObjectsList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hazard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IgnoreError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IgnoreFailure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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IgnoreNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ignoreStandardRealVector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IgnoreVitalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IgnoreWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ImmediateContinuousAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
InitOutCompositeParam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IncludeRecursionDepthMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IterationLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LibrarySearchPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MaxReportRhsCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatBreak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatBreakLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatError. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatFail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MessageFormatWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MixedAnsiPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
modelsim_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
msgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mtiAvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mtiOvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiFileCompilationUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoCaseStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoDeferSubpgmCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoIndexCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoOthersStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoRangeCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoVital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NoVitalCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NumericStdNoWarnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OldVHDLConfigurationVisibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OldVhdlForGenNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OnFinish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimize_1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PedanticErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PliCompatDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PreserveCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PrintSimStats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RequireConfigForAllDefaultBinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RunLength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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977
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977
978
978
978
979
979
979
980
980
980
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981
981
982
982
982
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Table of Contents
SccomLogfile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
SccomVerbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
ScEnableScSignalWriteCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
ScMainFinishOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
ScMainStackSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
ScShowIeeeDeprecationWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
ScTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
ScvPhaseRelationName . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
SeparateConfigLibrary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Show_BadOptionWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Show_Lint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Show_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Show_VitalChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Show_Warning1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Show_Warning2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Show_Warning3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Show_Warning4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Show_Warning5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
ShowFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
ShowUnassociatedScNameWarning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
ShowUndebuggableScTypeWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
ShutdownFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
SignalSpyPathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
std_developerskit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
StdArithNoWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
suppress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
sv_std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
SVFileExtensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Svlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
synopsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
SyncCompilerFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
SynthPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
ToggleCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
ToggleFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
ToggleMaxFixedSizeArray. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
ToggleMaxIntValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
ToggleMaxRealValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
ToggleNoIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
TogglePackedAsVec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
TogglePortsOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
ToggleVlogEnumBits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
ToggleVlogIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
ToggleVlogReal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
ToggleWidthLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
TranscriptFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
UCDBFilename. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
UCDBTestStatusMessageFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
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UnbufferedOutput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
UserTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
UseScv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Veriuser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
VHDL93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
VhdlVariableLogging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
vital2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
vlog95compat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
WarnConstantChange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
WaveSignalNameWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
WLFCacheSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
WLFCollapseMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
WLFCompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
WLFDeleteOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
WLFFileLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
WLFFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
WLFOptimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
WLFSaveAllRegions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
WLFSimCacheSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
WLFSizeLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
WLFTimeLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
WLFUseThreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
Commonly Used modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Common Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Hierarchical Library Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Creating a Transcript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
Using a Startup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
Turning Off Assertion Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Turning off Warnings from Arithmetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Force Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Restart Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
VHDL Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Opening VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Appendix B
Location Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Referencing Source Files with Location Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Using Location Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Pathname Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
How Location Mapping Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Mapping with TCL Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Appendix C
Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Message System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
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Getting More Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Changing Message Severity Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Suppressing Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Suppressing VCOM Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Suppressing VLOG Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Suppressing VSIM Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
sccom Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Enforcing Strict 1076 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Appendix D
Verilog Interfaces to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
GCC Compiler Support for use with C Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Registering PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Registering VPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Registering DPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
DPI Use Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
DPI and the vlog Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
When Your DPI Export Function is Not Getting Called . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Troubleshooting a Missing DPI Import Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Simplified Import of Library Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Optimizing DPI Import Call Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Making Verilog Function Calls from non-DPI C Models . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Calling C/C++ Functions Defined in PLI Shared Objects from DPI Code . . . . . . . . . . . . 1046
Compiling and Linking C Applications for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
For all UNIX Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Windows Platforms — C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
32-bit Linux Platform — C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
64-bit Linux Platform — C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Compiling and Linking C++ Applications for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Windows Platforms — C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
32-bit Linux Platform — C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
64-bit Linux Platform — C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Specifying Application Files to Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
PLI and VPI File Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
DPI File Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Loading Shared Objects with Global Symbol Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
PLI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
VPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
DPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
The PLI Callback reason Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
The sizetf Callback Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
PLI Object Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Third Party PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Support for VHDL Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
IEEE Std 1364 ACC Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
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Table of Contents
IEEE Std 1364 TF Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
SystemVerilog DPI Access Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Verilog-XL Compatible Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
64-bit Support for PLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Using 64-bit ModelSim with 32-bit Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
PLI/VPI Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
The Purpose of Tracing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Invoking a Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Debugging Interface Application Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Appendix E
Command and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Command Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Command History Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Main and Source Window Mouse and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . 1068
List Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Wave Window Mouse and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Appendix F
Setting GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Customizing the Simulator GUI Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Layout Mode Loading Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Configure Window Layouts Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Creating a Custom Layout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Changing Layout Mode Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Resetting a Layout Mode to its Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Deleting a Custom Layout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Configuring Default Windows for Restored Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Configuring the Column Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
Simulator GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Setting Preference Variables from the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Saving GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
The modelsim.tcl File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Appendix G
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Files Accessed During Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Environment Variable Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Creating Environment Variables in Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Referencing Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Removing Temp Files (VSOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Appendix H
Third-Party Model Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Synopsys SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
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VHDL SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Verilog SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
Index
Third-Party Information
End-User License Agreement
ModelSim PE User’s Manual, v10.0d
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List of Examples
Example 2-1. Using the radix define Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Example 2-2. Using radix define to Specify Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Example 3-1. Encryption Envelope Contains Verilog IP Code to be Protected . . . . . . . . . . 237
Example 3-2. Encryption Envelope Contains `include Compiler Directives . . . . . . . . . . . . 238
Example 3-3. Results After Compiling with vlog +protect . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Example 3-4. Using the Mentor Graphics Public Encryption Key in Verilog/SystemVerilog 264
Example 6-1. Memory Model Using VHDL87 and VHDL93 Architectures . . . . . . . . . . . . 320
Example 6-2. Conversions Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Example 6-3. Memory Model Using VHDL02 Architecture . . . . . . . . . . . . . . . . . . . . . . . . 324
Example 7-1. Invocation of the Verilog Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Example 7-2. Incremental Compilation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Example 7-3. Sub-Modules with Common Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Example 8-1. Simple SystemC-only sc_main(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Example 8-2. Generating SCV Extensions for a Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Example 8-3. Generating SCV Extensions for a Class without Friend
(Private Data Not Generated). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Example 8-4. Generating SCV Extensions for a Class with Friend
(Private Data Generated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Example 8-5. Generating SCV Extensions for an Enumerated Type . . . . . . . . . . . . . . . . . . 405
Example 8-6. User-Defined Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Example 8-7. Use of mti_set_typename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Example 8-8. Using the Custom Interface on Different Objects . . . . . . . . . . . . . . . . . . . . . . 425
Example 8-9. Converting sc_main to a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Example 8-10. Using sc_main and Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Example 8-11. Using an SCV Transaction Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Example 9-1. Binding with -cuname and -mfcu Arguments . . . . . . . . . . . . . . . . . . . . . . . . . 454
Example 9-2. SystemC Instantiating Verilog - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Example 9-3. SystemC Instantiating Verilog - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Example 9-4. Sample Foreign Module Declaration, with Constructor Arguments for Parameters
501
Example 9-5. Passing Parameters as Constructor Arguments - 1 . . . . . . . . . . . . . . . . . . . . . 501
Example 9-6. SystemC Instantiating Verilog, Passing Integer Parameters as Template
Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Example 9-7. Passing Integer Parameters as Template Arguments and Non-integer Parameters
as Constructor Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Example 9-8. Verilog/SystemVerilog Instantiating SystemC, Parameter Information. . . . . 506
Example 9-9. SystemC Design Instantiating a VHDL Design Unit . . . . . . . . . . . . . . . . . . . 510
Example 9-10. SystemC Instantiating VHDL, Generic Information. . . . . . . . . . . . . . . . . . . 511
Example 9-11. Passing Parameters as Constructor Arguments - 2 . . . . . . . . . . . . . . . . . . . . 511
Example 9-12. SystemC Instantiating VHDL, Passing Integer Generics as Template Arguments
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Example 9-13. Passing Integer Generics as Template Arguments and Non-integer Generics as
Constructor Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Example 9-14. Global Import Function Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Example 9-15. SystemVerilog Global Import Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Example 9-16. Registering a Global Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Example 9-17. Usage of scSetScopeByName and scGetScopeName . . . . . . . . . . . . . . . . . . 521
Example 10-1. Transactions in List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Example 10-2. Verilog API Code Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Example 10-3. SCV Initialization and WLF Database Creation . . . . . . . . . . . . . . . . . . . . . . 557
Example 10-4. SCV API Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Example 15-1. Branch Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Example 15-2. Coverage Report for Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Example 15-3. FEC Coverage - Simple Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Example 15-4. FEC Coverage - Bimodal Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Example 15-5. UDP Condition Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Example 15-6. Vectors in UDP Condition Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Example 15-7. Expression UDP Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Example 15-8. Creating Coverage Exclusions with a .do File . . . . . . . . . . . . . . . . . . . . . . . 745
Example 15-9. Excluding, Merging and Reporting on Several Runs . . . . . . . . . . . . . . . . . . 756
Example 15-10. Reporting Coverage Data from the Command Line . . . . . . . . . . . . . . . . . . 759
Example 16-1. Verilog Single-State Variable FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Example 16-2. VHDL Single-State Variable FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Example 16-3. Verilog Current-State Variable with a Single Next-State Variable FSM . . . 768
Example 16-4. VHDL Current-State Variable and Single Next-State Variable FSM. . . . . . 768
Example 17-1. Dividing a UCDB by Module/DU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Example 23-1. Verilog Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Example 23-2. VHDL Adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Example 23-3. Mixed-HDL Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
Example 23-4. Replacing Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
Example 23-5. VCD Output from vcd dumpports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Example 24-1. Tcl while Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Example 24-2. Tcl for Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Example 24-3. Tcl foreach Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Example 24-4. Tcl break Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Example 24-5. Tcl continue Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Example 24-6. Access and Transfer System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Example 24-7. Tcl Used to Specify Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Example 24-8. Tcl Used to Specify Compiler Arguments—Enhanced . . . . . . . . . . . . . . . . 937
Example 24-9. Specifying Files to Compile With argc Macro . . . . . . . . . . . . . . . . . . . . . . . 939
Example 24-10. Specifying Compiler Arguments With Macro . . . . . . . . . . . . . . . . . . . . . . 939
Example 24-11. Specifying Compiler Arguments With Macro—Enhanced. . . . . . . . . . . . . 939
Example D-1. VPI Application Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
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List of Figures
Figure 1-1. Operational Structure and Flow of ModelSim PE . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-1. Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-2. Find Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-3. Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-4. Find Options Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-5. User-Defined Radix “States” in the Wave Window . . . . . . . . . . . . . . . . . . . . . .
Figure 2-6. User-Defined Radix “States” in the List Window . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-7. Setting the Global Signal Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-8. Fixed Point Radix Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-9. Active Cursor Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-10. Enter Active Time Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-11. Main Window of the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-12. Main Window — Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-13. Main Window — Toolbar Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-14. Main Window — Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-15. GUI Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-16. GUI Tab Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-17. Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-18. Main Window Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-19. Window Header Handle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-20. Tab Handle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-21. Window Undock Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-22. Analysis Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-23. Column Layout Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-24. Compile Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-25. Coverage Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-26. Dataflow Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-27. FSM Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-28. Help Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-29. Layout Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-30. Memory Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-31. Mode Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-32. Objectfilter Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-33. Process Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-34. Profile Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-35. Schematic Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-36. Simulate Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-37. Source Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-38. Standard Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-39. The Add Selected to Window Dropdown Menu. . . . . . . . . . . . . . . . . . . . . . . .
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Figure 2-40. Wave Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-41. Wave Bookmark Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-42. Wave Compare Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-43. Wave Cursor Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-44. Wave Edit Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-45. Wave Expand Time Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-46. Zoom Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-47. Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-48. Capacity Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-49. Class Graph Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-50. Class Tree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-51. Code Coverage Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-52. Missed Coverage in Code Coverage Analysis Windows . . . . . . . . . . . . . . . . .
Figure 2-53. Coverage Details Window Showing Expression Truth Table . . . . . . . . . . . . .
Figure 2-54. Coverage Details Window Showing Toggle Details . . . . . . . . . . . . . . . . . . . .
Figure 2-55. Coverage Details Window Showing FSM Details . . . . . . . . . . . . . . . . . . . . . .
Figure 2-56. Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-57. Dataflow Window and Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-58. Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-59. FSM List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-60. FSM Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-61. Combining Common Transition Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-62. Instance Coverage Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-63. Filter Instance List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-64. Library Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-65. List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-66. Locals Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-67. Change Selected Variable Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-68. Memory LIst Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-69. Memory Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-70. Split Screen View of Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-71. Message Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-72. Message Viewer Window — Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-73. Message Viewer Filter Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-74. Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-75. Setting the Global Signal Radix from the Objects Window . . . . . . . . . . . . . . .
Figure 2-76. Objects Window - Toggle Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-77. Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-78. Column Heading Changes When States are Filtered . . . . . . . . . . . . . . . . . . . .
Figure 2-79. Next Active Process Displayed in Order Column. . . . . . . . . . . . . . . . . . . . . . .
Figure 2-80. Sample Process Report in the Transcript Window . . . . . . . . . . . . . . . . . . . . . .
Figure 2-81. Profile Calltree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-82. Profile Design Unit Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-83. Profile Ranked Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-84. Profile Structural Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure 2-85. Profile Details Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-86. Source Window Showing Language Templates . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-87. Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-88. Setting Context from Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-89. Coverage in Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-90. Source Annotation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-91. Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-92. Create New Design Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-93. Inserting Module Statement from Verilog Language Template . . . . . . . . . . . .
Figure 2-94. Language Template Context Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-95. Breakpoint in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-96. Modifying Existing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-97. Source Code for source.sv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-98. Source Window Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-99. Source Window with Find Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-100. Preferences Dialog for Customizing Source Window . . . . . . . . . . . . . . . . . .
Figure 2-101. Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-102. Find Mode Popup Displays Matches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-103. Code Coverage Data in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-104. Browser Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-105. Transcript Window with Find Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-106. Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-107. Scrollable Hierarchical Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-108. Expanded Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-109. Grouping Objects in the Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-110. Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-111. Pathnames Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-112. Setting the Global Signal Radix from the Wave Window . . . . . . . . . . . . . . .
Figure 2-113. Values Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-114. Waveform Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-115. Analog Sidebar Toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-116. Cursor Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-117. Toolbox for Cursors and Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-118. Editing Grid and Timeline Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-119. Cursor Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-120. Wave Window - Message Bar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-121. View Objects Window Dropdown Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1. Create an Encryption Envelope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2. Verilog/SystemVerilog Encryption Usage Flow . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-3. Delivering IP Code with User-Defined Macros . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-4. Delivering IP with `protect Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1. Create Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-2. Project Window Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-3. Add items to the Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4. Create Project File Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure 4-5. Add file to Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-6. Right-click Compile Menu in Project Window . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-7. Click Plus Sign to Show Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-8. Setting Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-9. Grouping Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-10. Start Simulation Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-11. Structure WIndow with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-12. Project Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-13. Add Simulation Configuration Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-14. Simulation Configuration in the Project Window. . . . . . . . . . . . . . . . . . . . . . .
Figure 4-15. Add Folder Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-16. Specifying a Project Folder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-17. Project Compiler Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-18. Specifying File Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-19. Project Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-1. Creating a New Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-2. Design Unit Information in the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-3. Edit Library Mapping Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-4. Import Library Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-1. VHDL Delta Delay Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-1. Fatal Signal Segmentation Violation (SIGSEGV) . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2. Current Process Where Error Occurred . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-3. Blue Arrow Indicating Where Code Stopped Executing . . . . . . . . . . . . . . . . . .
Figure 7-4. Null Values in the Locals Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-1. SystemC Objects in GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-2. Breakpoint in SystemC Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-3. Setting the Allow lib step Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-4. SystemC Objects and Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-5. Aggregate Data Displayed in Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-1. Transaction Anatomy in Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-2. Transaction Stream in Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-3. Viewing Transactions and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-4. Concurrent Parallel Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-5. Transaction in Wave Window - Viewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-6. Transaction Stream Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-7. Changing Appearance of Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-8. Transactions in Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-9. Recording Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-1. Displaying Two Datasets in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-2. Open Dataset Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-3. Structure Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-4. The Dataset Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-5. Dataset Snapshot Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-6. Virtual Objects Indicated by Orange Diamond. . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-1. Wave Window Object Pathnames Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure 12-2. Wave Window Object Values Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-3. Wave Window Waveform Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-4. Wave Window Cursor Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-5. Wave Window Messages Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-6. Tabular Format of the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-7. Cursor and Timeline Toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-8. Grid and Timeline Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-9. Cursor Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-10. Find Previous and Next Transition Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-11. Original Names of Wave Window Cursors . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-12. Sync All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-13. Cursor Linking Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-14. Configure Cursor Links Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-15. Time Markers in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-16. Waveform Pane with Collapsed Event and Delta Time . . . . . . . . . . . . . . . . .
Figure 12-17. Waveform Pane with Expanded Time at a Specific Time . . . . . . . . . . . . . . .
Figure 12-18. Waveform Pane with Event Not Logged . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-19. Waveform Pane with Expanded Time Over a Time Range . . . . . . . . . . . . . .
Figure 12-20. List Window After configure list -delta none Option is Used . . . . . . . . . . . .
Figure 12-21. List Window After configure list -delta collapse Option is Used. . . . . . . . . .
Figure 12-22. List Window After write list -delta all Option is Used . . . . . . . . . . . . . . . . . .
Figure 12-23. List Window After write list -event Option is Used . . . . . . . . . . . . . . . . . . . .
Figure 12-24. Bookmark Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-25. Wave Signal Search Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-26. Expression Builder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-27. Selecting Signals for Expression Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-28. Display Tab of the Wave Window Preferences Dialog Box. . . . . . . . . . . . . .
Figure 12-29. Grid and Timeline Tab of Wave Window Preferences Dialog Box . . . . . . . .
Figure 12-30. Clock Cycles in Timeline of Wave Window . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-31. Wave Format Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-32. Format Tab of Wave Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-33. Changing Signal Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-34. Global Signal Radix Dialog in Wave Window . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-35. Separate Signals with Wave Window Dividers . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-36. Splitting Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-37. Wave Groups Denoted by Red Diamond . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-38. Modifying List Window Display Properties . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-39. List Signal Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-40. Changing the Radix in the List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-41. Save Format Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-42. Waveform Save Between Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-43. Wave Filter Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-44. Wave Filter Dataset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-45. Class Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-46. Class Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures
Figure 12-47. Class Information Popup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-48. Waveforms for Class Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-49. Signals Combined to Create Virtual Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-50. Virtual Expression Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-51. Line Triggering in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-52. Setting Trigger Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-53. Trigger Gating Using Expression Builder. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-54. Modifying the Breakpoints Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-55. Signal Breakpoint Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-56. Breakpoints in the Source Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-57. File Breakpoint Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-58. Waveform Comparison Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-59. Start Comparison Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-60. Compare Tab in the Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-61. Structure Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-62. Add Comparison by Region Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-63. Comparison Methods Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-64. Adding a Clock for a Clocked Comparison . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-65. Waveform Comparison Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-66. Viewing Waveform Differences in the Wave Window . . . . . . . . . . . . . . . . .
Figure 12-67. Waveform Differences in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-68. Reloading and Redisplaying Compare Differences . . . . . . . . . . . . . . . . . . . .
Figure 13-1. The Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-2. Dataflow Debugging Usage Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-3. Dot Indicates Input in Process Sensitivity List . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-4. Controlling Display of Redundant Buffers and Inverters . . . . . . . . . . . . . . . . .
Figure 13-5. Green Highlighting Shows Your Path Through the Design . . . . . . . . . . . . . . .
Figure 13-6. Highlight Selected Trace with Custom Color . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-7. Wave Viewer Displays Inputs and Outputs of Selected Process . . . . . . . . . . .
Figure 13-8. Unknown States Shown as Red Lines in Wave Window . . . . . . . . . . . . . . . . .
Figure 13-9. Dataflow: Point-to-Point Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-10. The Print Postscript Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-11. The Print Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-12. The Page Setup Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-13. Configuring Dataflow Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-1. Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-2. Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-3. Create New Design Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-4. Language Template Context Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-5. Bookmark All Instances of a Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-6. Setting Context from Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-7. Source Annotation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-8. Time Indicator in Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-9. Enter an Event Time Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-10. Coverage in Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures
Figure 14-11. Breakpoint in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-12. Editing Existing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-13. Source Code for source.sv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-14. Preferences By - Window Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-1. Enabling Code Coverage in the Start Simulation Dialog . . . . . . . . . . . . . . . . .
Figure 15-2. Selecting Code Coverage Analysis Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-3. Focused Expression Report Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-4. Toggle Coverage Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-5. Toggle Coverage Data in the Objects Window. . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-6. Sample Toggle Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-1. Verification of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-2. Aggregated Coverage Data in the Structure Window. . . . . . . . . . . . . . . . . . . .
Figure 17-3. Command Setup Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-4. File Merge Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-5. original.ucdb, dut.ucdb and tb.ucdb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-6. Test Data in Verification Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-7. Coverage Report Text Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-8. Coverage HTML Report Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-9. HTML Coverage Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-10. Coverage Exclusions Report Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-11. Filtering Displayed UCDB Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-1. Specifying Path in C Debug setup Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-2. Setting Breakpoints in Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-3. Right Click Pop-up Menu on Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-4. Simulation Stopped at Breakpoint on PLI Task . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-5. Stepping into Next File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-6. Function Pointer to Foreign Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-7. Highlighted Line in Associated File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-8. Stop on quit Button in Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-1. Status Bar: Profile Samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-2. Ranked Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-3. Design Units Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-4. Calltree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-5. Structural Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-6. Expand and Collapse Selections in Popup Menu . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-7. Profile Details Window: Function Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-8. Profile Details Window: Instance Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-9. Profile Details Window: Callers and Callees . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-10. Accessing Source from Profile Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-11. Profile Report Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-12. Profile Report Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-13. Displaying Capacity Objects in the Wave Window . . . . . . . . . . . . . . . . . . . .
Figure 21-1. Waveform Editor: Library Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21-2. Opening Waveform Editor from Structure or Objects Windows . . . . . . . . . . .
Figure 21-3. Create Pattern Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures
Figure 21-4. Wave Edit Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 21-5. Manipulating Waveforms with the Wave Edit Toolbar and Cursors . . . . . . . . 883
Figure 21-6. Export Waveform Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Figure 21-7. Evcd Import Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 22-1. SDF Tab in Start Simulation Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Figure A-1. Runtime Options Dialog: Defaults Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure A-2. Runtime Options Dialog Box: Severity Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure A-3. Runtime Options Dialog Box: WLF Files Tab . . . . . . . . . . . . . . . . . . . . . . . . . 947
Figure D-1. DPI Use Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Figure F-1. Configure Column Layout Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
Figure F-2. Edit Column Layout Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Figure F-3. Create Column Layout Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Figure F-4. Change Text Fonts for Selected Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Figure F-5. Making Global Font Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
ModelSim PE User’s Manual, v10.0d
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List of Tables
Table 1-1. Simulation Tasks — ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-2. Use Modes for ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-3. Possible Definitions of an Object, by Language . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-4. Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-5. Documentation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-6. Deprecated Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-7. Deprecated Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-8. Deprecated Command Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-1. GUI Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-2. Design Object Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-3. Icon Shapes and Design Object Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-4. Graphic Elements of Toolbar in Find Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-5. Graphic Elements of Toolbar in Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-6. Information Displayed in Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-7. File Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-8. Edit Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-9. View Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-10. Compile Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-11. Simulate Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-12. Add Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-13. Tools Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-14. Layout Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-15. Window Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-16. Help Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-17. Analysis Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-18. Change Column Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-19. Compile Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-20. Coverage Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-21. Dataflow Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-22. FSM Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-23. Help Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-24. Layout Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-25. Memory Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-26. Mode Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-27. Objectfilter Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-28. Process Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-29. Profile Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-30. Schematic Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-31. Simulate Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-32. Source Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables
Table 2-33. Standard Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-34. Wave Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-35. Wave Bookmark Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-36. Wave Compare Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-37. Wave Cursor Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-38. Wave Edit Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-39. Wave Expand Time Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-40. Zoom Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-41. Commands Related to the Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-42. Call Stack Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-43. Capacity Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-44. Class Graph Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-45. Class Tree Window Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-46. Class Tree Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-47. Class Tree Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-48. Actions in Code Coverage Analysis Title Bar . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-49. Files Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-50. Files Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-51. Files Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-52. FSM List Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-53. FSM List Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-54. FSM List Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-55. FSM Viewer Window — Graphical Elements . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-56. FSM View Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-57. FSM View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-58. Instance Coverage Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-59. Library Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-60. Library Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-61. List Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-62. Locals Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-63. Locals Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-64. Memory Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-65. Memory List Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-66. Memory List Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-67. Memories Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-68. Memory Data Popup Menu — Address Pane . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-69. Memory Data Popup Menu — Data Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-70. Memory Data Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-71. Message Viewer Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-72. Message Viewer Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-73. Message Viewer Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-74. Objects Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-75. Toggle Coverage Columns in the Objects Window . . . . . . . . . . . . . . . . . . . . .
Table 2-76. Processes Window Column Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-77. Profile Calltree Window Column Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables
Table 2-78. Source Window Code Coverage Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-79. Columns in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-80. Verification Browser Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-81. Analog Sidebar Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-82. Icons and Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-1. Compile Options for the -nodebug Compiling . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-1. Evaluation 1 of always Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-2. Evaluation 2 of always Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-3. IEEE Std 1364 System Tasks and Functions - 1 . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-4. IEEE Std 1364 System Tasks and Functions - 2 . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-5. IEEE Std 1364 System Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-6. IEEE Std 1364 File I/O Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-7. SystemVerilog System Tasks and Functions - 1 . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-8. SystemVerilog System Tasks and Functions - 2 . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-9. SystemVerilog System Tasks and Functions - 4 . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-10. Simulator-Specific Verilog System Tasks and Functions . . . . . . . . . . . . . . . . .
Table 8-1. Supported Platforms for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-2. Custom gcc Platform Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-3. Generated Extensions for Each Object Type . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-4. Time Unit and Simulator Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-5. Viewable SystemC Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-6. Mixed-language Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-7. Simple Conversion: sc_main to Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-8. Using sc_main and Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-9. Modifications Using SCV Transaction Database . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-1. VHDL Types Mapped To SystemVerilog Port Vectors . . . . . . . . . . . . . . . . . . .
Table 9-2. SystemVerilog-to-VHDL Data Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-3. Verilog Parameter to VHDL Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-4. Verilog States Mapped to std_logic and bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-5. VHDL to SystemVerilog Data Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-6. VHDL Generics to Verilog Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-7. Mapping VHDL bit to Verilog States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-8. Mapping VHDL std_logic Type to Verilog States . . . . . . . . . . . . . . . . . . . . . . .
Table 9-9. Mapping Table for Verilog-style Declarations . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-10. Mapping Table for SystemVerilog-style Declarations . . . . . . . . . . . . . . . . . . .
Table 9-11. Channel and Port Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-12. Data Type Mapping – SystemC to Verilog or SystemVerilog . . . . . . . . . . . . .
Table 9-13. Data Type Mapping – Verilog or SystemVerilog to SystemC . . . . . . . . . . . . .
Table 9-14. Mapping Verilog Port Directions to SystemC . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-15. Mapping Verilog States to SystemC States . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-16. Mapping SystemC bool to Verilog States . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-17. Mapping SystemC sc_bit to Verilog States . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-18. Mapping SystemC sc_logic to Verilog States . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-19. SystemC Port Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-20. Mapping Between SystemC sc_signal and VHDL Types . . . . . . . . . . . . . . . . .
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List of Tables
Table 9-21. Mapping VHDL Port Directions to SystemC . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-22. Mapping VHDL std_logic States to SystemC States . . . . . . . . . . . . . . . . . . . .
Table 9-23. Mapping SystemC bool to VHDL Boolean States . . . . . . . . . . . . . . . . . . . . . .
Table 9-24. Mapping SystemC sc_bit to VHDL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-25. Mapping SystemC sc_logic to VHDL std_logic . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-26. Mapping Literals from VHDL to SystemVerilog . . . . . . . . . . . . . . . . . . . . . . .
Table 9-27. Supported Types Inside VHDL Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-28. Supported Types Inside SystemVerilog Structure . . . . . . . . . . . . . . . . . . . . . .
Table 9-29. SystemC Types as Represented in SystemVerilog . . . . . . . . . . . . . . . . . . . . . .
Table 10-1. System Tasks and API for Recording Transactions . . . . . . . . . . . . . . . . . . . . .
Table 11-1. WLF File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-2. Structure Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-3. vsim Arguments for Collapsing Time and Delta Steps . . . . . . . . . . . . . . . . . . .
Table 12-1. Actions for Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-2. Actions for Time Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-3. Recording Delta and Event Time Information . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-4. Menu Selections for Expanded Time Display Modes . . . . . . . . . . . . . . . . . . . .
Table 12-5. Actions for Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-6. Actions for Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-7. Triggering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-8. Mixed-Language Waveform Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-1. Icon and Menu Selections for Exploring Design Connectivity . . . . . . . . . . . . .
Table 13-2. Dataflow Window Links to Other Windows and Panes . . . . . . . . . . . . . . . . . .
Table 15-1. Code Coverage in Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-2. AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-3. XOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-4. Condition UDP Truth Table for Line 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-5. Condition UDP Truth Table for Line 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-6. Expression UDP Truth Table for line 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-1. Commands Used for FSM Coverage Collection . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-2. FSM Coverage Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-3. Additional FSM-Related Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-4. Recognized FSM Note Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-5. FSM Recognition Info Note Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-1. Coverage Calculation for each Coverage Type . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-2. Coverage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-3. Predefined Fields in UCDB Test Attribute Record . . . . . . . . . . . . . . . . . . . . . .
Table 18-1. Supported Platforms and gdb Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-2. Simulation Stepping Options in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-3. Command Reference for C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-1. How to Enable and View Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 20-1. Signal Spy Reference Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21-1. Signal Attributes in Create Pattern Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21-2. Waveform Editing Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21-3. Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table 21-4. Wave Editor Mouse/Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21-5. Formats for Saving Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21-6. Examples for Loading a Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-1. Matching SDF to VHDL Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-2. Matching SDF IOPATH to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-3. Matching SDF INTERCONNECT and PORT to Verilog . . . . . . . . . . . . . . . .
Table 22-4. Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog . . . . . .
Table 22-5. Matching SDF DEVICE to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-6. Matching SDF SETUP to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-7. Matching SDF HOLD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-8. Matching SDF SETUPHOLD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-9. Matching SDF RECOVERY to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-10. Matching SDF REMOVAL to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-11. Matching SDF RECREM to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-12. Matching SDF SKEW to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-13. Matching SDF WIDTH to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-14. Matching SDF PERIOD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-15. Matching SDF NOCHANGE to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-16. RETAIN Delay Usage (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-17. RETAIN Delay Usage (with +vlog_retain_same2same_on) . . . . . . . . . . . . .
Table 22-18. Matching Verilog Timing Checks to SDF SETUP . . . . . . . . . . . . . . . . . . . . .
Table 22-19. SDF Data May Be More Accurate Than Model . . . . . . . . . . . . . . . . . . . . . . .
Table 22-20. Matching Explicit Verilog Edge Transitions to Verilog . . . . . . . . . . . . . . . . .
Table 22-21. SDF Timing Check Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-22. SDF Path Delay Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22-23. Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-1. VCD Commands and SystemTasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-2. VCD Dumpport Commands and System Tasks . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-3. VCD Commands and System Tasks for Multiple VCD Files . . . . . . . . . . . . . .
Table 23-4. SystemC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-5. Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-6. State When Direction is Unknown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-7. Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-8. VCD Values When Force Command is Used . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-9. Values for file_format Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23-10. Sample Driver Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-1. Changes to ModelSim Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-2. Tcl Backslash Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-3. Tcl List Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-4. Simulator-Specific Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-5. Tcl Time Conversion Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-6. Tcl Time Relation Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-7. Tcl Time Arithmetic Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24-8. Commands for Handling Breakpoints and Errors in Macros . . . . . . . . . . . . . .
Table A-1. Runtime Option Dialog: Defaults Tab Contents . . . . . . . . . . . . . . . . . . . . . . . .
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Table A-2. Runtime Option Dialog: Severity Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . 947
Table A-3. Runtime Option Dialog: WLF Files Tab Contents . . . . . . . . . . . . . . . . . . . . . . . 947
Table A-4. Commands for Overriding the Default Initialization File . . . . . . . . . . . . . . . . . 949
Table A-5. License Variable: License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Table A-6. MessageFormat Variable: Accepted Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Table C-1. Severity Level Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Table C-2. Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Table D-1. VPI Compatibility Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
Table D-2. vsim Arguments for DPI Application Using External Compilation Flows . . . . 1053
Table D-3. Supported VHDL Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Table D-4. Supported ACC Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Table D-5. Supported TF Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Table D-6. Values for action Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Table E-1. Command History Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Table E-2. Mouse Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Table E-3. Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Table E-4. List Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Table E-5. Wave Window Mouse Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Table E-6. Wave Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Table F-1. Global Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Table G-1. Files Accessed During Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Table G-2. Add Library Mappings to modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
ModelSim PE User’s Manual, v10.0d
43
List of Tables
44
ModelSim PE User’s Manual, v10.0d
Chapter 1
Introduction
Documentation for ModelSim is intended for users of UNIX, Linux, and Microsoft Windows.
Not all versions of ModelSim are supported on all platforms. For more information on your
platform or operating system, contact your Mentor Graphics sales representative.
Operational Structure and Flow
Figure 1-1 illustrates the structure and general usage flow for verifying a design with
ModelSim.
ModelSim PE User’s Manual, v10.0d
45
Introduction
Simulation Task Overview
Figure 1-1. Operational Structure and Flow of ModelSim PE
VHDL
Design
Libraries
vlib
Vendor
vmap
Design
files
vlog/
vcom/
sccom
.ini or
.mpf file
Analyze/
Compile
Libraries
Map libraries
local work
library
HDL/SystemC
Analyze/
Compile
compiled
database
vsim
Simulate
Interactive Debugging
activities
Debug
Simulation Output
(for example, vcd)
Post-processing Debug
Simulation Task Overview
The following table provides a reference for the tasks required for compiling, loading, and
simulating a design in ModelSim.
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ModelSim PE User’s Manual, v10.0d
Introduction
Basic Steps for Simulation
Table 1-1. Simulation Tasks — ModelSim
Task
Example Command Line
Entry
Step 1:
Map libraries
vlib
a. File > New > Project
vmap work b. Enter library name
c. Add design files to
project
Step 2:
Compile the
design
vlog file1.v file2.v ...
(Verilog)
vcom file1.vhd file2.vhd ...
(VHDL)
vsim
Step 3:
Load the
design into the
simulator
GUI Menu Pull-down
GUI Icons
N/A
a. Compile > Compile
or
Compile > Compile All
Compile or
Compile All
a. Simulate > Start
Simulation
b. Click on top design
module or optimized
design unit name
c. Click OK
This action loads the
design for simulation
Simulate icon:
Step 4:
Run the
simulation
run
step
Simulate > Run
Run, or
Run continue, or
Run -all
Step 5:
Debug the
design
Common debugging
commands:
bp
describe
drivers
examine
force
log
show
N/A
N/A
Basic Steps for Simulation
This section describes the basic procedure for simulating your design using ModelSim.
ModelSim PE User’s Manual, v10.0d
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Introduction
Basic Steps for Simulation
Step 1 — Collect Files and Map Libraries
Files needed to run ModelSim on your design:
•
•
•
design files (VHDL, Verilog, and/or SystemC), including stimulus for the design
libraries, both working and resource
modelsim.ini file (automatically created by the library mapping command)
For detailed information on the files accessed during system startup (including the modelsim.ini
file), initialization sequences, and system environment variables, see the Appendix entitled
“System Initialization”.
Providing Stimulus to the Design
You can provide stimulus to your design in several ways:
•
•
•
Language-based test bench
Tcl-based ModelSim interactive command, force
VCD files / commands
See Creating a VCD File and Using Extended VCD as Stimulus
•
Third-party test bench generation tools
What is a Library?
A library is a location on your file system where ModelSim stores data to be used for
simulation. ModelSim uses one or more libraries to manage the creation of data before it is
needed for use in simulation. A library also helps to streamline simulation invocation. Instead of
compiling all design data each time you simulate, ModelSim uses binary pre-compiled data
from its libraries. For example, if you make changes to a single Verilog module, ModelSim
recompiles only that module, rather than all modules in the design.
Work and Resource Libraries
You can use design libraries in two ways:
•
•
As a local working library that contains the compiled version of your design
As a resource library
The contents of your working library will change as you update your design and recompile. A
resource library is typically unchanging, and serves as a parts source for your design. Examples
of resource libraries are shared information within your group, vendor libraries, packages, or
previously compiled elements of your own working design. You can create your own resource
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Introduction
Basic Steps for Simulation
libraries, or they may be supplied by another design team or a third party (for example, a silicon
vendor).
For more information on resource libraries and working libraries, refer to Working Library
Versus Resource Libraries, Managing Library Contents, Working with Design Libraries, and
Specifying Resource Libraries.
Creating the Logical Library (vlib)
Before you can compile your source files, you must create a library in which to store the
compilation results. You can create the logical library using the GUI, by choosing File > New >
Library from the main menu (see Creating a Library), or you can use the vlib command. For
example, the following command:
vlib work
creates a library named work. By default, compilation results are stored in the work library.
Mapping the Logical Work to the Physical Work Directory (vmap)
VHDL uses logical library names that can be mapped to ModelSim library directories. If
libraries are not mapped properly, and you invoke your simulation, necessary components will
not be loaded and simulation will fail. Similarly, compilation can also depend on proper library
mapping.
By default, ModelSim can find libraries in your current directory (assuming they have the right
name), but for it to find libraries located elsewhere, you need to map a logical library name to
the pathname of the library.
You can use the GUI (Library Mappings with the GUI, a command (Library Mapping from the
Command Line), or a project (Getting Started with Projects to assign a logical name to a design
library.
The format for command line entry is:
vmap
This command sets the mapping between a logical library name and a directory.
Step 2 — Compile the Design
To compile a design, run one of the following ModelSim commands, depending on the
language used to create the design:
•
•
vlog — Verilog
vcom — VHDL
ModelSim PE User’s Manual, v10.0d
49
Introduction
Basic Steps for Simulation
•
sccom — SystemC
Compiling Verilog (vlog)
The vlog command compiles Verilog modules in your design. You can compile Verilog files in
any order, since they are not order dependent. See Verilog Compilation for details.
Compiling VHDL (vcom)
The vcom command compiles VHDL design units. You must compile VHDL files in the order
necessitate to any design requirements. Projects may assist you in determining the compile
order: for more information, see Auto-Generating Compile Order. See Compilation and
Simulation of VHDL for details on VHDL compilation.
Compiling SystemC (sccom)
The sccom command compiles SystemC design units. Use this command only if you have
SystemC components in your design. See Compiling SystemC Files for details.
Step 3 — Load the Design for Simulation
Running the vsim Command on the Top Level of the Design
After you have compiled your design, it is ready for simulation. You can then run the vsim
command using the names of any top-level modules (many designs contain only one top-level
module). For example, if your top-level modules are named “testbench” and “globals,” then
invoke the simulator as follows:
vsim testbench globals
After the simulator loads the top-level modules, it iteratively loads the instantiated modules and
UDPs in the design hierarchy, linking the design together by connecting the ports and resolving
hierarchical references.
Using Standard Delay Format Files
You can incorporate actual delay values to the simulation by applying standard delay format
(SDF) back-annotation files to the design. For more information on how SDF is used in the
design, see Specifying SDF Files for Simulation.
Step 4 — Simulate the Design
Once you have successfully loaded the design, simulation time is set to zero, and you must enter
a run command to begin simulation. For more information, see Verilog and SystemVerilog
Simulation, SystemC Simulation, and VHDL Simulation.
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Introduction
Modes of Operation
The basic commands you use to run simulation are:
•
•
•
•
•
add wave
bp
force
run
step
Step 5 — Debug the Design
The ModelSim GUI provides numerous commands, operations, and windows useful in
debugging your design. In addition, you can also use the command line to run the following
basic simulation commands for debugging:
•
•
•
•
•
•
describe
drivers
examine
force
log
show
Modes of Operation
Many users run ModelSim interactively with the graphical user interface (GUI)—using the
mouse to perform actions from the main menu or in dialog boxes. However, there are really
three modes of ModelSim operation, as described in Table 1-2.
Table 1-2. Use Modes for ModelSim
Mode
Characteristics
How ModelSim is invoked
GUI
interactive; has graphical from a desktop icon or from the OS command
windows, push-buttons, shell prompt. Example:
OS> vsim
menus, and a command
line in the transcript.
Default mode
Command-line
interactive command
line; no GUI
with -c argument at the OS command prompt.
Example:
OS> vsim -c
ModelSim PE User’s Manual, v10.0d
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Introduction
Modes of Operation
Table 1-2. Use Modes for ModelSim (cont.)
Mode
Characteristics
How ModelSim is invoked
Batch
at OS command shell prompt using redirection
non-interactive batch
of standard input. Example:
script; no windows or
C:\ vsim vfiles.v outfile
interactive command line
The ModelSim User’s Manual focuses primarily on the GUI mode of operation. However, this
section provides an introduction to the Command-line and Batch modes.
A command is available to help batch users access commands not available for use in batch
mode. Refer to the batch_mode command in the ModelSim Reference Manual for more details.
Command Line Mode
In command line mode ModelSim executes any startup command specified by the Startup
variable in the modelsim.ini file. If vsim is invoked with the -do "command_string" option, a
DO file (macro) is called. A DO file executed in this manner will override any startup command
in the modelsim.ini file.
During simulation a transcript file is created containing any messages to stdout. A transcript file
created in command line mode may be used as a DO file if you invoke the transcript on
command after the design loads (see the example below). The transcript on command writes all
of the commands you invoke to the transcript file.
For example, the following series of commands results in a transcript file that can be used for
command input if top is re-simulated (remove the quit -f command from the transcript file if
you want to remain in the simulator).
vsim -c top
library and design loading messages… then execute:
transcript on
force clk 1 50, 0 100 -repeat 100
run 500
run @5000
quit -f
Rename a transcript file that you intend to use as a DO file—if you do not rename it, ModelSim
will overwrite it the next time you run vsim. Also, simulator messages are already commented
out, but any messages generated from your design (and subsequently written to the transcript
file) will cause the simulator to pause. A transcript file that contains only valid simulator
commands will work fine; comment out anything else with a pound sign (#).
Refer to Creating a Transcript File for more information about creating, locating, and saving a
transcript file.
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Introduction
Definition of an Object
Stand-alone tools pick up project settings in command-line mode if you invoke them in the
project's root directory. If invoked outside the project directory, stand-alone tools pick up
project settings only if you set the MODELSIM environment variable to the path to the project
file (/.mpf).
Basic Command Line Editing and Navigation
While in command line mode you can use basic command line editing and navigation
techniques similar to other command line environments, such as:
•
History navigation — use the up and down arrows to select commands you have already
used.
•
Command line editing — use the left and right arrows to edit your current command
line.
•
Filename completion — use the Tab key to expand filenames.
Batch Mode
Batch mode is an operational mode that provides neither an interactive command line nor
interactive windows. In a Windows environment, you run vsim from a Windows command
prompt and standard input and output are redirected to and from files.
Here is an example of a batch mode simulation using redirection of std input and output:
vsim counter outfile
where “yourfile” represents a script containing various ModelSim commands, and the angle
brackets (< >) are redirection indicators.
You can use the CTRL-C keyboard interrupt to terminate batch simulation in UNIX and
Windows environments.
Definition of an Object
Because ModelSim supports a variety of design languages (SystemC, Verilog, VHDL,
SystemVerilog), the word “object” is used to refer to any valid design element in those
languages, whenever a specific language reference is not needed. Table 1-3 summarizes the
language constructs that an object can refer to.
Table 1-3. Possible Definitions of an Object, by Language
Design Language
An object can be
VHDL
block statement, component instantiation, constant,
generate statement, generic, package, signal, alias,
variable
ModelSim PE User’s Manual, v10.0d
53
Introduction
Standards Supported
Table 1-3. Possible Definitions of an Object, by Language
Design Language
An object can be
Verilog
function, module instantiation, named fork, named
begin, net, task, register, variable
SystemVerilog
In addition to those listed above for Verilog:
class, package, program, interface, array, directive,
property, sequence
SystemC
module, channel, port, variable, aggregate
PSL
property, sequence, directive, endpoint
Standards Supported
Standards documents are sometimes informally referred to as the Language Reference Manual
(LRM). This standards listed here are the complete name of each manual. Elsewhere in this
manual the individual standards are referenced using the IEEE Std number.
The following standards are supported for the ModelSim products:
•
VHDL —
o
IEEE Std 1076-2008, IEEE Standard VHDL Language Reference Manual.
ModelSim supports a subset of the VHDL 2008 standard features. For detailed
standard support information see the vhdl2008 technote available at
/docs/technotes/vhdl2008.note, or from the GUI menu pull-down Help
> Technotes > vhdl2008.
Potential migration issues and mixing use of VHDL 2008 with older VHDL code are
addressed in the vhdl2008migration technote.
o
IEEE Std 1164-1993, Standard Multivalue Logic System for VHDL Model
Interoperability
o
IEEE Std 1076.2-1996, Standard VHDL Mathematical Packages
Any design developed with ModelSim will be compatible with any other VHDL system
that is compliant with the 1076 specifications.
•
Verilog/SystemVerilog —
o
IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description Language
o
IEEE Std 1800-2009. IEEE Standard for SystemVerilog -- Unified Hardware
Design, Specification, and Verification Language
Both PLI (Programming Language Interface) and VCD (Value Change Dump) are
supported for ModelSim users.
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ModelSim PE User’s Manual, v10.0d
Introduction
Assumptions
•
•
SDF and VITAL —
o
SDF – IEEE Std 1497-2001, IEEE Standard for Standard Delay Format (SDF) for
the Electronic Design Process
o
VITAL 2000 – IEEE Std 1076.4-2000, IEEE Standard for VITAL ASIC Modeling
Specification
SystemC —
o
IEEE Std 1666-2005, SystemC Language Reference Manual
Assumptions
Using the ModelSim product and its documentation is based on the following assumptions:
•
•
You are familiar with how to use your operating system and its graphical interface.
•
You have worked through the appropriate lessons in the ModelSim Tutorial and are
familiar with the basic functionality of ModelSim. You can find the ModelSim Tutorial
by choosing Help from the main menu.
You have a working knowledge of the design languages. Although ModelSim is an
excellent application to use while learning HDL concepts and practices, this document is
not written to support that goal.
Text Conventions
Table 1-4 lists the text conventions used in this manual.
Table 1-4. Text Conventions
Text Type
Description
italic text
provides emphasis and sets off filenames,
pathnames, and design unit names
bold text
indicates commands, command options, menu
choices, package and library logical names, as
well as variables, dialog box selections, and
language keywords
monospace type
monospace type is used for program and
command examples
The right angle (>)
is used to connect menu choices when
traversing menus as in: File > Quit
UPPER CASE
denotes file types used by ModelSim (such as
DO, WLF, INI, MPF, PDF.)
ModelSim PE User’s Manual, v10.0d
55
Introduction
Installation Directory Pathnames
Installation Directory Pathnames
When referring to installation paths, this manual uses “” as a generic representation
of the installation directory for all versions of ModelSim. The actual installation directory on
your system may contain version information.
Where to Find ModelSim Documentation
Table 1-5. Documentation List
Document
Format
How to get it
Installation & Licensing
Guide
PDF
Help > PDF Bookcase
HTML and PDF
Help > InfoHub
Quick Guide
(command and feature
quick-reference)
PDF
Help > PDF Bookcase
and
Help > InfoHub
Tutorial
PDF
Help > PDF Bookcase
HTML and PDF
Help > InfoHub
PDF
Help > PDF Bookcase
HTML and PDF
Help > InfoHub
PDF
Help > PDF Bookcase
HTML and PDF
Help > InfoHub
Command Help
ASCII
type help [command name] at the prompt in
the Transcript pane
Error message help
ASCII
type verror at the Transcript or
shell prompt
Tcl Man Pages (Tcl
manual)
HTML
select Help > Tcl Man Pages, or find
contents.htm in \modeltech\docs\tcl_help_html
Technotes
HTML
available from the support site
User’s Manual
Reference Manual
Mentor Graphics Support
Mentor Graphics product support includes software enhancements, technical support, access to
comprehensive online services with SupportNet, and the optional On-Site Mentoring service.
For details, refer to the following location on the Worldwide Web:
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ModelSim PE User’s Manual, v10.0d
Introduction
Deprecated Features, Commands, and Variables
http://supportnet.mentor.com/about/
If you have questions about this software release, please log in to the SupportNet web site. You
can search thousands of technical solutions, view documentation, or open a Service Request
online at:
http://supportnet.mentor.com/
If your site is under current support and you do not have a SupportNet login, you can register for
SupportNet by filling out the short form at:
http://supportnet.mentor.com/user/register.cfm
For any customer support contact information, refer to the following web site location:
http://supportnet.mentor.com/contacts/supportcenters/
Deprecated Features, Commands, and Variables
This section provides tables of features, commands, command arguments, and modelsim.ini
variables that have been superseded by new versions. Although you can still use superseded
features, commands, arguments, or variables, Mentor Graphics deprecates their usage—you
should use the corresponding new version whenever possible or convenient.
The following tables indicate the in which the item was superseded and a link to the new item
that replaces it, where applicable.
Table 1-6. Deprecated Features
Feature
Version
New Feature / Information
vopt -covercells/-nocovercells
10.0d
Use vlog -covercells/-nocovercells instead.
Table 1-7. Deprecated Commands
Command
Version
New Command / Information
vdbg
10.0
No longer necessary. Use vopt -debugdb and vsim
-debugdb for pre-simulation debug analysis.
ModelSim PE User’s Manual, v10.0d
57
Introduction
Deprecated Features, Commands, and Variables
Table 1-8. Deprecated Command Arguments
Argument
58
Version
New Argument / Information
coverage exclude -condrow 10.0
-udpcondrow, name change only.
coverage exclude -exprrow
10.0
-udpexprrow, name change only.
vsim -dpiexportcheckref
10.0b
No longer necessary for using locked work
libraries. Using this argument has no effect
on simulation, which will continue and
generate a warning message.
vsim -dpiexportonly
10.0b
No longer necessary for using locked work
libraries. Using this argument terminates
simulation immediately without doing
anything.
vsim -dpiexportobj
10.0c
No longer necessary on Unix/Linux
platforms. No longer required on Windows
platforms if DPI C/C++ source code is
compiled using the Questa SIM DPI autocompile capability.
ModelSim PE User’s Manual, v10.0d
Chapter 2
Graphical User Interface
The ModelSim graphical user interface (GUI) provides access to numerous debugging tools and
windows that enable you to analyze different parts of your design. All windows initially display
within the ModelSim Main window.
Figure 2-1. Graphical User Interface
The following table summarizes all of the available windows.
Table 2-1. GUI Windows
Window name
Description
More details
Main
central GUI access point
Main Window
ModelSim PE User’s Manual, v10.0d
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Graphical User Interface
Table 2-1. GUI Windows (cont.)
60
Window name
Description
More details
Call Stack
displays the current call stack, allowing Call Stack Window
you to debug your design by analyzing
the depth of function calls
Capacity
displays capacity data (memory usage)
about SystemVerilog constructs
Capacity Window
Class Graph
displays interactive relationships of
SystemVerilog classes in graphical
form
Class Graph Window
Class Tree
displays interactive relationships of
SystemVerilog classes in tabular form.
Class Tree Window
Code Coverage
Analysis
displays missing code coverage, details, Code Coverage Analysis
and code coverage exclusions
Window
Coverage Details
contains details about coverage metrics Coverage Details Window
based on selections in other coverage
windows
Dataflow
displays "physical" connectivity and
lets you trace events (causality)
Dataflow Window
Files
displays the source files and their
locations for the loaded simulation
Files Window
FSM List
lists all recognized FSMs in the design
FSM List Window
FSM View
graphical representation of a recognized FSM Viewer Window
FSM
Instance Coverage
displays coverage statistics for each
Instance Coverage Window
instance in a flat, non-hierarchical view
Library
lists design libraries and compiled
design units
Library Window
List
shows waveform data in a tabular
format
List Window
Locals
displays data objects that are
immediately visible at the current
execution point of the selected process
Locals Window
Memory
windows that show memories and their Memory List Window
contents
Memory Data Window
Message Viewer
allows easy access, organization, and
analysis of Note, Warning, Errors or
other messages written to transcript
during simulation
Message Viewer Window
ModelSim PE User’s Manual, v10.0d
Graphical User Interface
Design Object Icons and Their Meaning
Table 2-1. GUI Windows (cont.)
Window name
Description
More details
Objects
displays all declared data objects in the
current scope
Objects Window
Process
displays all processes that are scheduled Processes Window
to run during the current simulation
cycle
Profile
windows that display performance and
memory profiling data
Profiling Windows
Project
provides access to information about
Projects
Projects
Source
Source Window
a text editor for viewing and editing
files, such as Verilog, VHDL, SystemC,
and DO files
Structure (sim)
displays hierarchical view of active
simulation. Name of window is either
“sim” or “”
Transcript
Transcript Window
keeps a running history of commands
and messages and provides a commandline interface
Watch
displays signal or variable values at the Watch Window
current simulation time
Wave
displays waveforms
Structure Window
Wave Window
The windows are customizable in that you can position and size them as you see fit, and
ModelSim will remember your settings upon subsequent invocations. You can restore
ModelSim windows and panes to their original settings by selecting Layout > Reset in the
menu bar.
You can copy the title text in a window or pane header by selecting it and right-clicking to
display a popup menu. This is useful for copying the file name of a source file for use elsewhere
(see Figure 2-60 for an example of this in an FSM Viewer window).
Design Object Icons and Their Meaning
The color and shape of icons convey information about the language and type of a design
object. Table 2-2 shows the icon colors and the languages they indicate.
Table 2-2. Design Object Icons
Icon color
Design Language
light blue
Verilog or SystemVerilog
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Graphical User Interface
Design Object Icons and Their Meaning
Table 2-2. Design Object Icons (cont.)
Icon color
Design Language
dark blue
VHDL
green
SystemC
orange
virtual object
Here is a list of icon shapes and the design object types they indicate:
Table 2-3. Icon Shapes and Design Object Types
Icon shape
Example
Design Object Type
Square
any scope (VHDL block, Verilog named block, SC
module, class, interface, task, function, and so forth.)
Square and red
asterix
abstract scope (VHDL block, Verilog named block, SC
module, class, interface, task, function, and so forth.)
Circle
process
Diamond
valued object (signals, nets, registers, SystemC channel,
and so forth.)
Diamond and
yellow pulse on
red dot
an editable waveform created with the waveform editor
Diamond and
red asterix
valued object (abstract)
Diamond and
green arrow
indicates mode (In, Inout, Out) of an object port
Triangle
caution sign on comparison object
Star
transaction; The color of the star for each transaction
depends on the language of the region in which the
transaction stream occurs: dark blue for VHDL, light blue
for Verilog and SystemVerilog, green for SystemC.
Arrowhead
antecedent match, eval
Setting Fonts
You may need to adjust font settings to accommodate the aspect ratios of wide screen and
double screen displays or to handle launching ModelSim from an X-session. Refer to Making
Global Font Changes for more information.
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Graphical User Interface
Using the Find and Filter Functions
Font Scaling
To change font scaling, select the Transcript window, then Transcript > Adjust Font Scaling.
You will need a ruler to complete the instructions in the lower right corner of the dialog. When
you have entered the pixel and inches information, click OK to close the dialog. Then, restart
ModelSim to see the change. This is a one time setting; you should not need to set it again
unless you change display resolution or the hardware (monitor or video card). The font scaling
applies to Windows and UNIX operating systems. On UNIX systems, the font scaling is stored
based on the $DISPLAY environment variable.
Using the Find and Filter Functions
Finding and/or filtering capabilities are available for most windows. The Find mode toolbar is
shown in Figure 2-2. The filtering function is denoted by a “Contains” field (Figure 2-3).
Figure 2-2. Find Mode
Figure 2-3. Filter Mode
Windows that support both Find (Figure 2-2) and Filter modes (Figure 2-3) allow you to toggle
between the two modes by doing any one of the following:
•
•
•
Use the Ctrl+M hotkey.
Click the “Find” or “Contains” words in the toolbar at the bottom of the window.
Select the mode from the Find Options popup menu (see Using the Find Options Popup
Menu).
The last selected mode is remembered between sessions.
A “Find” toolbar will appear along the bottom edge of the active window when you do either of
the following:
•
•
Select Edit > Find in the menu bar.
Click the Find icon in the Standard Toolbar.
All of the above actions are toggles - repeat the action and the Find toolbar will close.
The Find or Filter entry fields prefill as you type, based on the context of the current window
selection. The find or filter action begins as you type.
There is a simple history mechanism that saves find or filter strings for later use. The keyboard
shortcuts to use this feature are:
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Graphical User Interface
Using the Find and Filter Functions
•
•
Ctrl+P — retrieve previous search string
Ctrl+N — retrieve next search string
Other hotkey actions include:
•
•
•
Esc — closes the Find toolbar
Enter (Windows) or Return (UNIX or Linux) — initiates a “Find Next” action
Ctrl+T — search while typing (default is on)
The entry field turns red if no matches are found.
The graphic elements associated with the Find toolbar are shown in Table 2-4.
Table 2-4. Graphic Elements of Toolbar in Find Mode
Graphic Element
Action
Find
opens the find toolbar in the active
window
Close
closes the find toolbar
Find entry field
Find Options
opens the Find Options popup menu at
the bottom of the active window. The
contents of the menu changes for each
window.
Clear Entry Field
clears the entry field
Execute Search
initiates the search
Toggle Search Direction
toggles search direction upward or
downward through the active window
Find All Matches;
Bookmark All Matches (for Source
window only)
highlights every occurrence of the find
item; for the Source window only,
places a blue flag (bookmark) at every
occurrence of the find item
Search For
64
allows entry of find parameters
Click and hold the button to open a
drop down menu with the following
options:
• Instance
• Design Unit
• Design Unit Type
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Using the Find and Filter Functions
Table 2-4. Graphic Elements of Toolbar in Find Mode (cont.)
Graphic Element
Action
Match Case
search must match the case of the text
entered in the Find field
Exact (whole word)
searches for whole words that match
those entered in the Find field
Regular Expression
searches for a regular expression
Wrap Search
searches from cursor to bottom of
window then continues search from top
of the window
Using the Filter Mode
By entering a string in the “Contains” text entry box you can filter the view of the selected
window down to the specific information you are looking for. The Search bar changes color
when a filter is applied to the window. You can change the color with the preference variable
PrefDefault(searchbarFiltered).
Table 2-5. Graphic Elements of Toolbar in Filter Mode
Button
Name
Shortcuts
Description
Filter Regular Expression
None
A drop down menu that allows
you to set the wildcard mode.
A text entry box for your filter
string.
Clear Filter
None
Clears the text entry box and
removes the filter from the
active window.
Wildcard Usage
There are three wildcard modes:
•
glob-style — Allows you to use the following special wildcard characters:
o
* — matches any sequence of characters in the string
o
? — matches any single character in the string
o
[] — matches any character in the set .
o
\ — matches the single character , which allows you to match on any special
characters (*, ?, [, ], and \)
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User-Defined Radices
For more information refer to the Tcl documentation:
Help > Tcl Man Pages
Tcl Commands > string > string match
•
regular-expression — allows you to use wildcard characters based on Tcl regular
expressions. For more information refer to the Tcl documentation:
Help > Tcl Man Pages
Tcl Commands > re_syntax
•
exact — indicates that no characters have special meaning, thus disabling wildcard
features.
The string entry field of the Contains toolbar item is case-insensitive, If you need to search for
case-sensitive strings use “regular-expression” and prepend the string with (?c)
Using the Find Options Popup Menu
When you click the Find Options icon
popup menu (Figure 2-4).
in the Find entry field it will open a Find Options
Figure 2-4. Find Options Popup Menu
The Find Options menu displays the options available to you as well as hot keys for initiating
the actions without the menu.
User-Defined Radices
A user definable radix is used to map bit patterns to a set of enumeration labels. After defining a
new radix, the radix will be available for use in the List, Watch, and Wave windows or with the
examine command.
There are four commands used to manage user defined radices:
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User-Defined Radices
•
•
•
•
radix define
radix names
radix list
radix delete
Using the radix define Command
The radix define command is used to create or modify a radix. It must include a radix name and
a definition body, which consists of a list of number pattern, label pairs. Optionally, it may
include the -color argument for setting the radix color (see Example 2-2).
{
,
-default
}
A is any legitimate HDL integer numeric literal. To be more specific:
# ---
' --- is an integer, is any arbitrary string. It
should be quoted (""), especially if it contains spaces.
The -default entry is optional. If present, it defines the radix to use if a match is not found for a
given value. The -default entry can appear anywhere in the list, it does not have to be at the end.
Example 2-1 shows the radix define command used to create a radix called “States,” which
will display state values in the List, Watch, and Wave windows instead of numeric values.
Example 2-1. Using the radix define Command
radix define States
11'b00000000001
11'b00000000010
11'b00000000100
11'b00000001000
11'b00000010000
11'b00000100000
11'b00001000000
11'b00010000000
11'b00100000000
11'b01000000000
11'b10000000000
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{
"IDLE",
"CTRL",
"WT_WD_1",
"WT_WD_2",
"WT_BLK_1",
"WT_BLK_2",
"WT_BLK_3",
"WT_BLK_4",
"WT_BLK_5",
"RD_WD_1",
"RD_WD_2",
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User-Defined Radices
-default hex
}
Figure 2-5 shows an FSM signal called /test-sm/sm_seq0/sm_0/state in the Wave window with
a binary radix and with the user-defined “States” radix (as defined in Example 2-1).
Figure 2-5. User-Defined Radix “States” in the Wave Window
Figure 2-6 shows an FSM signal called /test-sm/sm_seq0/sm_0/state in the List window with a
binary radix and with the user-defined “States” radix (as defined in Example 2-1)
Figure 2-6. User-Defined Radix “States” in the List Window
Using radix define to Specify Radix Color
The following example illustrates how to use the radix define command to specify the radix
color:
Example 2-2. Using radix define to Specify Color
radix define States {
11'b00000000001 "IDLE" -color yellow,
11'b00000000010 "CTRL" -color #ffee00,
11'b00000000100 "WT_WD_1" -color orange,
11'b00000001000 "WT_WD_2" -color orange,
11'b00000010000 "WT_BLK_1",
11'b00000100000 "WT_BLK_2",
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11'b00001000000 "WT_BLK_3",
11'b00010000000 "WT_BLK_4",
11'b00100000000 "WT_BLK_5",
11'b01000000000 "RD_WD_1" -color green,
11'b10000000000 "RD_WD_2" -color green,
-default hex
-defaultcolor white
}
If a pattern/label pair does not specify a color, the normal wave window colors will be used. If
the value of the waveform does not match any pattern, then the -default radix and -defaultcolor
will be used.
To specify a range of values, wildcards may be specified for bits or characters of the value. The
wildcard character is '?', similar to the iteration character in a Verilog UDP, for example:
radix define {
6'b01??00 "Write" -color orange,
6'b10??00 "Read" -color green
}
In this example, the first pattern will match "010000", "010100", "011000", and "011100". In
case of overlaps, the first matching pattern is used, going from top to bottom.
Setting Global Signal Radix
The Global Signal Radix feature allows you to set the radix for a selected signal or signals in the
active window and in other windows where the signal appears. The Global Signal Radix can be
set from the Locals, Objects, Schematic, or Wave windows as follows:
•
•
Select a signal or group of signals.
Right-click the selected signal(s) and click Global Signal Radix from the popup menu
(in the Wave window, select Radix > Global Signal Radix).
This opens the Global Signal Radix dialog box (Figure 2-7), where you may select a
radix. This sets the radix for the selected signal(s) in the active window and every other
window where the signal appears.
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User-Defined Radices
Figure 2-7. Setting the Global Signal Radix
Setting a Fixed Point Radix
Fixed point types are used in VHDL and SystemC to represents non-integer numbers without
using a floating point format. ModelSim automatically recognizes VHDL sfixed and ufixeda
types as well as SystemC SC_FIXED and SC_UFIXED types and displays them correctly with
a fixed point format.
In addition, a general purpose fixed point radix feature is available for displaying any vector,
regardless of type, in a fixed point format in the Wave window. You simply have to specify how
many bits to use as fraction bits from the whole vector.
With the Wave window active:
1. Select (LMB) a signal or signals in the Pathnames pane of the Wave window.
2. Right-click the selected signal(s) and select Radix > Fixed Point from the popup menu.
This opens the Fixed Point Radix dialog.
Figure 2-8. Fixed Point Radix Dialog
3. Type the number of bits you want to appear as the fraction and click OK.
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Saving and Reloading Formats and Content
Saving and Reloading Formats and Content
You can use the write format restart command to create a single .do file that will recreate all
debug windows and breakpoints (see Saving and Restoring Breakpoints) when invoked with the
do command in subsequent simulation runs. The syntax is:
write format restart
If the ShutdownFile modelsim.ini variable is set to this .do filename, it will call the write
format restart command upon exit.
Active Time Label
The Active Time Label displays the current time of the active cursor or the Now (end of
simulation) time in the Schematic, Source, and FSM windows. This is the time used to control
state values displayed or annotated in the window.
Figure 2-9. Active Cursor Time
When you run a simulation and it comes to an end, the Active Time Label displays the Now
time - which is the end-of-simulation time. When you select a cursor in the Wave window, or in
the Wave viewer of the Schematic window, the Active Time Label automatically changes to
display the time of the current active cursor.
The Active Time label includes a minimize/maximize button that allows you to hide or display
the label.
When a signal or net is selected, you can jump to the previous or next transition of that signal,
with respect to the active time, by clicking the Find Previous/Next Transition buttons.
To change the display from showing the Active Time to showing the Now time, or vice versa,
do the following:
•
•
Make the Source, Schematic, or FSM window the active window by clicking on it.
•
Select either “Examine Now” or “Examine Current Cursor.”
Open the dedicated menu for the selected window (i.e., if the Schematic window is
active, open the Schematic menu in the menu bar).
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Main Window
You can also change the Active Time by simply clicking on the Active Time Label to open the
Enter Value dialog box (Figure 2-10), where you can change the value.
Figure 2-10. Enter Active Time Value
Main Window
The primary access point in the ModelSim GUI is called the Main window. It provides
convenient access to design libraries and objects, source files, debugging commands, simulation
status messages, and so forth. When you load a design, or bring up debugging tools, ModelSim
opens windows appropriate for your debugging environment.
Elements of the Main Window
The following sections outline the GUI terminology used in this manual.
Menu Bar
Toolbar Frame
Toolbar
Window
Tab Group
Pane
The Main window is the primary access point in the GUI. Figure 2-11 shows an example of the
Main window during a simulation run.
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Main Window
Figure 2-11. Main Window of the GUI
The Main window contains a menu bar, toolbar frame, windows, tab groups, and a status bar,
which are described in the following sections.
Menu Bar
The menu bar provides access to many tasks available for your workflow. Figure 2-12 shows
the selection in the menu bar that changes based on whichever window is currently active.
The menu items that are available and how certain menu items behave depend on which
window is active. For example, if the Structure window is active and you choose Edit from the
menu bar, the Clear command is disabled. However, if you click in the Transcript window and
choose Edit, the Clear command is enabled. The active window is denoted by a blue title bar
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Main Window
Figure 2-12. Main Window — Menu Bar
Toolbar Frame
The toolbar frame contains several toolbars that provide quick access to various commands and
functions.
Figure 2-13. Main Window — Toolbar Frame
Toolbar
A toolbar is a collection of GUI elements in the toolbar frame and grouped by similarity of task.
There are many toolbars available within the GUI, refer to the section “Main Window Toolbar”
for more information about each toolbar. Figure 2-14 highlights the Compile toolbar in the
toolbar frame.
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Main Window
Figure 2-14. Main Window — Toolbar
Window
ModelSim can display over 40 different windows you can use with your workflow. This manual
refers to all of these objects as windows, even though you can rearrange them such that they
appear as a single window with tabs identifying each window.
Figure 2-15 shows an example of a layout with five windows visible; the Structure, Objects,
Processes, Wave and Transcript windows.
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Main Window
Figure 2-15. GUI Windows
Tab Group
You can group any number of windows into a single space called a tab group, allowing you to
show and hide windows by selecting their tabs. Figure 2-16 shows a tab group of the Library,
Files, Capacity and Structure windows, with the Structure (sim) window visible.
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Main Window
Figure 2-16. GUI Tab Group
Pane
Some windows contain panes, which are separate areas of a window display containing distinct
information within that window. One way to tell if a window has panes is whether you receive
different popup menus (right-click menu) in different areas. Windows that have panes include
the Wave, Source, and List windows. Figure 2-17 shows the Wave window with its the three
panes.
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Main Window
Figure 2-17. Wave Window Panes
Main Window Status Bar
Fields at the bottom of the Main window provide the following information about the current
simulation:
Figure 2-18. Main Window Status Bar
Table 2-6. Information Displayed in Status Bar
78
Field
Description
Project
name of the current project
Now
the current simulation time
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Main Window
Table 2-6. Information Displayed in Status Bar (cont.)
Field
Description
Delta
the current simulation iteration number
Profile Samples
the number of profile samples collected during the
current simulation
Memory
the total memory used during the current simulation
environment
name of the current context (object selected in the
active Structure window)
line/column
line and column numbers of the cursor in the active
Source window
Total Coverage
the aggregated coverage, as a percent, of the top level
object in the design
coverage mode
recursive or non-recursive
Selecting the Active Window
When the title bar of a window is highlighted - solid blue - it is the active window. All menu
selections will correspond to this active window. You can change the active window in the
following ways.
•
•
(default) Click anywhere in a window or on its title bar.
Move the mouse pointer into the window.
To turn on this feature, select Window > FocusFollowsMouse. Default time delay
for activating a window after the mouse cursor has entered the window is 300ms.
You can change the time delay with the PrefMain(FFMDelay) preference variable.
Rearranging the Main Window
You can alter the layout of the Main window using any of the following methods.
•
•
•
Moving a Window or Tab Group
Moving a Tab out of a Tab Group
Undocking a Window from the Main Window
When you exit ModelSim, the current layout is saved for a given design so that it appears the
same the next time you invoke the tool.
Moving a Window or Tab Group
1. Click on the header handle in the title bar of the window or tab group.
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Main Window
Figure 2-19. Window Header Handle
2. Drag, without releasing the mouse button, the window or tab group to a different area of
the Main window
Wherever you move your mouse you will see a dark blue outline that previews where
the window will be placed.
If the preview outline is a rectangle centered within a window, it indicates that you will
convert the window or tab group into new tabs within the highlighted window.
3. Release the mouse button to complete the move.
Moving a Tab out of a Tab Group
1. Click on the tab handle that you want to move.
Figure 2-20. Tab Handle
2. Drag, without releasing the mouse button, the tab to a different area of the Main window
Wherever you move your mouse you will see a dark blue outline that previews where
the tab will be placed.
If the preview outline is a rectangle centered within a window, it indicates that you will
move the tab into the highlighted window.
3. Release the mouse button to complete the move.
Undocking a Window from the Main Window
•
Follow the steps in Moving a Window or Tab Group, but drag the window outside of the
Main window, or
•
Click on the Dock/Undock button for the window.
Figure 2-21. Window Undock Button
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Navigating in the Main Window
Navigating in the Main Window
The Main window can contain of a number of windows that display various types of
information about your design, simulation, or debugging session.
Main Window Menu Bar
The main window menu bar is dynamic based on which window is selected, resulting in some
menu items changing name or becoming unavailable (greyed out). This section describes the
menu items at the highest-possible level.
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Navigating in the Main Window
File Menu
Table 2-7. File Menu — Item Description
Menu Item
New
Description
•
•
•
•
•
Open
Open a file of any type.
Load
Load and run a macro file (.do or .tcl)
Close
Close an opened file
Import
•
•
•
•
Export
•
•
•
•
•
•
•
•
•
82
Folder — create a new folder in the current directory
Source — create a new VHDL, Verilog or other source file
Project — create a new project
Library — create a new library and mapping
Library — import FPGA libraries
EVCD — import an extended VCD file previously created
with the ModelSim Waveform Editor. This item is enabled
only when a Wave window is active
Memory Data — initialize a memory by reloading a
previously saved memory file.
Column Layout — apply a previously saved column layout
to the active window
Waveform — export a created waveform
Tabular list — writes List window data to a file in tabular
format
Event list — writes List window data to a file as a series of
transitions that occurred during simulation
TSSI list — writes List window data to a file in TSSI
format
Image — saves an image of the active window
Memory Data — saves data from the selected memory in
the Memory List window or an active Memory Data
window to a text file
Column Layout — saves a column layout from the active
window
Save
Save as
These menu items change based on the active window.
Report
Produce a textual report based on the active window
Change Directory
Opens a browser for you to change your current directory. Not
available during a simulation, or if you have a dataset open.
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Navigating in the Main Window
Table 2-7. File Menu — Item Description (cont.)
Menu Item
Description
Use Source
Specifies an alternative file to use for the current source file.
This mapping only exists for the current simulation. This
option is only available from the Structure window.
Source Directory
Control which directories are searched for source files.
Datasets
Manage datasets for the current session.
Environment
Set up how different windows should be updated, by dataset,
process, and/or context. This is only available when the
Structure, Locals, Processes, and Objects windows are active.
Page Setup
Print
Print Postscript
Manage the printing of information from the selected window.
Recent Directories
Display a list of recently opened working directories
Recent Projects
Display a list of recently opened projects
Close Window
Close the active window
Quit
Quit the application
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Navigating in the Main Window
Edit Menu
Table 2-8. Edit Menu — Item Description
Menu Item
Description
Undo
Redo
Alter your previous edit in a Source window.
Cut
Copy
Paste
Use or remove selected text.
Delete
Remove an object from the Wave and List windows
Clear
Clear the Transcript window
Select All
Unselect All
Change the selection of items in a window
Expand
Expand or collapse hierarchy information
Goto
Goto a specific line number in the Source window
Find
Open the find toolbar. Refer to the section “Using the Find and
Filter Functions” for more information
Replace
Find and replace text in a Source window.
Signal Search
Search the Wave or List windows for a specified value, or the
next transition for the selected object
Find in Files
search for text in saved files
Previous Coverage Miss
Next Coverage Miss
Find the previous or next line with missed coverage in the
active Source window
View Menu
Table 2-9. View Menu — Item Description
84
Menu Item
Description
window name
Displays the selected window
New Window
Open additional instances of the Wave, List, or Dataflow
windows
Sort
Change the sort order of the Wave window
Filter
Filters information from the Objects and Structure windows.
Justify
Change the alignment of data in the selected window.
Properties
Displays file property information from the Files or Source
windows.
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Navigating in the Main Window
Compile Menu
Table 2-10. Compile Menu — Item Description
Menu Item
Description
Compile
Compile source files
Compile Options
Set various compile options.
SystemC Link
Collect the object files created in the different design libraries,
and uses them to build a shared library (.so) in the current work
library
Compile All
Compile all files in the open project. Disabled if you don’t
have a project open
Compile Selected
Compile the files selected in the project tab. Disabled if you
don’t have a project open
Compile Order
Set the compile order of the files in the open project. Disabled
if you don’t have a project open
Compile Report
report on the compilation history of the selected file(s) in the
project. Disabled if you don’t have a project open
Compile Summary
report on the compilation history of all files in the project.
Disabled if you don’t have a project open
Simulate menu
Table 2-11. Simulate Menu — Item Description
Menu item
Description
Design Optimization
Open the Design Optimization dialog to configure simulation
optimizations
Start Simulation
Load the selected design unit
Runtime Options
Set various simulation runtime options
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Navigating in the Main Window
Table 2-11. Simulate Menu — Item Description (cont.)
Menu item
Run
Description
•
•
•
•
•
•
•
86
Run — run simulation for one default run length;
change the run length with Simulate > Runtime Options,
or use the Run Length text box on the toolbar
Run -All — run simulation until you stop it
Continue — continue the simulation
Run -Next — run to the next event time
Step — single-step the simulator
Step -Over — execute without single-stepping through a
subprogram call
Restart — reload the design elements and reset the
simulation time to zero; only design elements that have
changed are reloaded; you specify whether to maintain
various objects (logged signals, breakpoints, etc.)
Break
Stop the current simulation run
End Simulation
Quit the current simulation run
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Navigating in the Main Window
Add Menu
Table 2-12. Add Menu — Item Description
Menu Item
Description
To Wave
Add information to the Wave window
To List
Add information to the List window
To Log
Add information to the Log file
To Dataflow
Add information to the Dataflow window
Window Pane
Add an additional pane to the Wave window. You can remove
this pane by selecting Wave > Delete Window Pane.
Tools Menu
Table 2-13. Tools Menu — Item Description
Menu Item
Description
Waveform Compare
Access tasks for waveform comparison. Refer to the section
“Waveform Compare” for more information.
Code Coverage
Access tasks for code coverage. Refer to the chapter “Code
Coverage” for more information.
Toggle Coverage
Add toggle coverage tracking. Refer to the section “Toggle
Coverage” for more information.
Coverage Save
Save the coverage metrics to a UCDB file.
Coverage Report
Save the coverage metrics to report file.
Profile
Access tasks for the memory and performance profilers. Refer
to the chapter “Profiling Performance and Memory Use” for
more information.
Breakpoints
Manage breakpoints
Dataset Snapshot
Enable periodic saving of simulation data to a .wlf file.
C Debug
Access tasks for the C Debug interface. Refer to the chapter “C
Debug” for more information.
Tcl
Execute or debug a Tcl macro.
Wildcard Filter
Refer to the section “Using the WildcardFilter Preference
Variable” for more information
Edit Preferences
Set GUI preference variables. Refer to the section “Simulator
GUI Preferences” for more information.
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Navigating in the Main Window
Layout Menu
Table 2-14. Layout Menu — Item Description
88
Menu Item
Description
Reset
Reset the GUI to the default appearance for the selected layout.
Save Layout As
Save your reorganized view to a custom layout. Refer to the
section “Customizing the Simulator GUI Layout” for more
information.
Configure
Configure the layout-specific behavior of the GUI. Refer to the
section “Configure Window Layouts Dialog Box” for more
information.
Delete
Delete a customized layout. You can not delete any of the five
standard layouts.
layout name
Select a standard or customized layout.
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Navigating in the Main Window
Window Menu
Table 2-15. Window Menu — Item Description
Menu Item
Description
Cascade
Tile Horizontally
Tile Vertically
Arrange all undocked windows. These options do not impact
any docked windows.
Icon Children
Icon All
Deicon All
Minimize (Icon) or Maximize (Deicon) undocked windows.
These options do not impact any docked windows.
Show Toolbar
Toggle the appearance of the Toolbar frame of the Main
window
Show Window Headers
Toggle the appearance of the window headers. Note that you
will be unable to rearrange windows if you do not show the
window headers.
FocusFollowsMouse
Mouse pointer makes window active when pointer hovers in
the window briefly. Refer to Navigating in the Main
Windowfor more information.
Customize
Add a button to the toolbar frame.
Toolbars
toggle the appearance of available toolbars. Similar behavior to
right-clicking in the toolbar frame.
window name
Make the selected window active.
Windows
Display the Windows dialog box, which allows you to activate,
close or undock the selected window(s).
Help Menu
Table 2-16. Help Menu — Item Description
Menu Item
Description
About
Display ModelSim application information.
Release Notes
Display the current Release Notes in the ModelSim Notepad
editor. You can find past release notes in the
/docs/rlsnotes/ directory.
Welcome Window
Display the Important Information splash screen. By default
this window is displayed on startup. You can disable the
automatic display by toggling the Don’t show this dialog
again radio button.
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Table 2-16. Help Menu — Item Description (cont.)
Menu Item
Description
Command Completion
Toggles the command completion dropdown box in the
transcript window.
When you start typing a command at the Transcript prompt, a
dropdown box appears which lists the available commands
matching what has been typed so far. You may use the Up and
Down arrow keys or the mouse to select the desired command.
When a unique command has been entered, the command
usage is presented in the drop down box.
Register File Types
Associate files types (such as .v, .vhd, .do) with the product.
These associations are typically made upon install, but this
option allows you to update your system in case changes have
been made since installation.
ModelSim
Documentation InfoHub
Open the HTML-based portal for all PDF and HTML
documentation.
ModelSim
Documentation - PDF
Bookcase
Open the PDF-based portal for the most commonly used PDF
documents.
Tcl Help
Open the Tcl command reference (man pages) in Windows
help format.
Tcl Syntax
Open the Tcl syntax documentation in your web browser.
Tcl Man pages
Open the Tcl/Tk manual in your web browser.
Technotes
Open a technical note in the ModelSim Notepad editor.
Main Window Toolbar
The Main window contains a toolbar frame that displays context-specific toolbars. The
following sections describe the toolbars and their associated buttons.
•
•
•
•
•
•
•
90
Analysis Toolbar
Column Layout Toolbar
Compile Toolbar
Coverage Toolbar
Dataflow Toolbar
FSM Toolbar
Help Toolbar
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Graphical User Interface
Navigating in the Main Window
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Layout Toolbar
Memory Toolbar
Mode Toolbar
Objectfilter Toolbar
Process Toolbar
Profile Toolbar
Schematic Toolbar
Simulate Toolbar
Source Toolbar
Standard Toolbar
Wave Bookmark Toolbar
Wave Compare Toolbar
Wave Cursor Toolbar
Wave Edit Toolbar
Wave Expand Time Toolbar
Wave Toolbar
Zoom Toolbar
Analysis Toolbar
The Analysis (coverage) toolbar allows you to control aspects of the Code Coverage Analysis
window.
Figure 2-22. Analysis Toolbar
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Table 2-17. Analysis Toolbar Buttons
Button
Name
Shortcuts
Description
Type
Command: view A dropdown box that
canalysis
allows you to specify the
type of code coverage to
view in the Code
Coverage Analysis
Window.
Covered
Menu: N/A
All covered (hit) items are
displayed.
Missed
Menu: N/A
All missed items (not
executed) are displayed.
Excluded
Menu: N/A
Restores the precision to
the default value (2).
Column Layout Toolbar
The Column Layout toolbar allows you to specify the column layout for the active window.
Figure 2-23. Column Layout Toolbar
Table 2-18. Change Column Toolbar Buttons
Button
•
92
Name
Shortcuts
Description
Column
Layout
Menu:
Verification
Browser >
Configure Column
Layout
A dropdown box that
allows you to specify the
column layout for the
active window. .
The Column Layout dropdown menu allows you to select pre-defined column layouts
for the active window. For example,AllColumns — displays all available columns.
ModelSim PE User’s Manual, v10.0d
Graphical User Interface
Navigating in the Main Window
•
•
Default — displays only columns that are displayed by default.
[Configure ColumnLayout . . .] — opens the Configure Column Layout dialog, which
allows you to create, edit, remove, copy, or rename a column layout. See Configuring
the Column Layout.
Compile Toolbar
The Compile toolbar provides access to compile and simulation actions.
Figure 2-24. Compile Toolbar
Table 2-19. Compile Toolbar Buttons
Button
Name
Shortcuts
Description
Compile
Command: vcom or vlog
Menu: Compile > Compile
Opens the Compile Source
Files dialog box.
Compile All
Command: vcom or vlog
Menu: Compile > Compile
all
Compiles all files in the open
project.
Simulate
Command: vsim
Menu: Simulate > Start
Simulation
Opens the Start Simulation
dialog box.
Break
Menu: Simulate > Break
Hotkey: Break
Stop a compilation,
elaboration, or the current
simulation run.
Coverage Toolbar
The Coverage toolbar provides tools for filtering code coverage data in the Structure and
Instance Coverage windows.
Figure 2-25. Coverage Toolbar
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Table 2-20. Coverage Toolbar Buttons
Button
Name
Shortcuts
Description
Enable
Filtering
None
Enables display filtering of
coverage statistics in the
Structure and Instance
Coverage windows.
Threshold
Above
None
Displays all coverage statistics
above the Filter Threshold for
selected columns.
Threshold
Below
None
Displays all coverage statistics
below the Filter Threshold for
selected columns
Filter
Threshold
None
Specifies the display coverage
percentage for the selected
coverage columns
Statement
None
Applies the display filter to all
Statement coverage columns in
the Structure and Instance
Coverage windows.
Branch
None
Applies the display filter to all
Branch coverage columns in
the Structure and Instance
Coverage windows.
Condition
None
Applies the display filter to all
Condition coverage columns in
the Structure and Instance
Coverage windows.
Expression
None
Applies the display filter to all
Expression coverage columns
in the Structure and Instance
Coverage windows.
Toggle
None
Applies the display filter to all
Toggle coverage columns in
the Structure and Instance
Coverage windows.
Dataflow Toolbar
The Dataflow toolbar provides access to various tools to use in the Dataflow window.
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Navigating in the Main Window
Figure 2-26. Dataflow Toolbar
Table 2-21. Dataflow Toolbar Buttons
Button
Name
Shortcuts
Description
Trace Input
Net to Event
Menu: Tools > Trace >
Trace next event
Move the next event cursor to
the next input event driving the
selected output.
Trace Set
Menu: Tools > Trace >
Trace event set
Jump to the source of the
selected input event.
Trace Reset
Menu: Tools > Trace >
Trace event reset
Return the next event cursor to
the selected output.
Trace Net to
Driver of X
Menu: Tools > Trace >
TraceX
Step back to the last driver of
an unknown value.
Expand Net None
to all Drivers
Display driver(s) of the
selected signal, net, or register.
Expand Net None
to all Drivers
and Readers
Display driver(s) and reader(s)
of the selected signal, net, or
register.
Expand Net None
to all Readers
Display reader(s) of the
selected signal, net, or register.
Show Wave
Display the embedded wave
viewer pane.
Menu: Dataflow >
Show Wave
FSM Toolbar
The FSM toolbar provides access to tools that control the information displayed in the FSM
Viewer window.
Figure 2-27. FSM Toolbar
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Table 2-22. FSM Toolbar Buttons
Button
Name
Shortcuts
Description
Show State
Counts
Menu: FSM View > Show
State Counts
(only available when
simulating with -coverage)
Displays the coverage count
over each state.
Show
Transition
Counts
Menu: FSM View > Show
Transition Counts
(only available when
simulating with -coverage)
Displays the coverage count
for each transition.
Show
Transition
Conditions
Menu: FSM View > Show
Transition Conditions
Displays the conditions of each
transition.
Track Wave
Cursor
Menu: FSM View > Track
Wave Cursor
The FSM Viewer tracks your
current cursor location.
Enable Info
Menu: FSM View > Enable
Mode Popups Info Mode Popups
Displays information when
you mouse over each state or
transition
Previous
State
None
Steps to the previous state in
the FSM Viewer window.
Next State
None
Steps to the next state in the
FSM Viewer window.
Help Toolbar
The Help toolbar provides a way for you to search the HTML documentation for a specified
string. The HTML documentation will be displayed in a web browser.
Figure 2-28. Help Toolbar
Table 2-23. Help Toolbar Buttons
Button
96
Name
Shortcuts
Description
Search
Documentation
None
A text entry box for your
search string.
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Graphical User Interface
Navigating in the Main Window
Table 2-23. Help Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Search
Documentation
Hotkey: Enter
Activates the search for the
term you entered into the text
entry box.
Layout Toolbar
The Layout toolbar allows you to select a predefined or user-defined layout of the graphical
user interface. Refer to the section “Customizing the Simulator GUI Layout” for more
information.
Figure 2-29. Layout Toolbar
Table 2-24. Layout Toolbar Buttons
Button
Name
Shortcuts
Description
Change
Layout
Menu: Layout >
A dropdown box that allows
you to select a GUI layout.
• NoDesign
• Simulate
• Coverage
• VMgmt
Memory Toolbar
The Memory toolbar provides access to common functions.
Figure 2-30. Memory Toolbar
Table 2-25. Memory Toolbar Buttons
Button
Name
Shortcuts
Description
Split Screen
Menu: Memory >
Split Screen
Splits the memory window.
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Table 2-25. Memory Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Goto Address
Highlights the first element of
the specified address.
Mode Toolbar
The Mode toolbar provides access to tools for controlling the mode of mouse navigation.
Figure 2-31. Mode Toolbar
Table 2-26. Mode Toolbar Buttons
Button
Name
Shortcuts
Description
Select Mode
Menu: Dataflow >
Mouse Mode > Select Mode
Set the left mouse button to
select mode and middle mouse
button to zoom mode.
Zoom Mode
Menu: Dataflow >
Mouse Mode > Zoom Mode
Set left mouse button to zoom
mode and middle mouse
button to pan mode.
Pan Mode
Menu: Dataflow >
Mouse Mode > Pan Mode
Set left mouse button to pan
mode and middle mouse
button to zoom mode.
Edit Mode
Menu: Wave or Dataflow >
Mouse Mode > Edit Mode
Set mouse to Edit Mode,
where you drag the left mouse
button to select a range and
drag the middle mouse button
to zoom.
Stop
Drawing
None
Halt any drawing currently
happening in the window.
Objectfilter Toolbar
The Objectfilter toolbar provides filtering of design objects appearing in the Objects window.
Figure 2-32. Objectfilter Toolbar
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Navigating in the Main Window
Table 2-27. Objectfilter Toolbar Buttons
Button
Name
Shortcuts
Description
View Inputs
Only
None
Changes the view of the Objects Window
to show inputs.
View
None
Outputs Only
Changes the view of the Objects Window
to show outputs.
View Inouts
Only
None
Changes the view of the Objects Window
to show inouts.
Vies Internal
Signals
None
Changes the view of the Objects Window
to show Internal Signals.
Reset All
Filters
None
Clears the filtering of Objects Window
entries and displays all objects.
Change Filter None
Opens the Filter Objects dialog box.
Process Toolbar
The Process toolbar contains three toggle buttons (only one can be active at any time) that
controls the view of the Process window.
Figure 2-33. Process Toolbar
Table 2-28. Process Toolbar Buttons
Button
Name
Shortcuts
Description
View Active
Processes
Menu: Process > Active
Changes the view of the
Processes Window to only
show active processes.
View
Processes in
Region
Menu: Process > In Region
Changes the view of the
Processes window to only
show processes in the active
region.
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Navigating in the Main Window
Table 2-28. Process Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Menu: Process > Design
View
Processes for
the Design
Changes the view of the
Processes window to show
processes in the design.
View Process Menu: Process > Hierarchy
hierarchy
Changes the view of the
Processes window to show
process hierarchy.
Profile Toolbar
The Profile toolbar provides access to tools related to the profiling windows (Ranked, Calltree,
Design Unit, and Structural.
Figure 2-34. Profile Toolbar
Table 2-29. Profile Toolbar Buttons
Button
Name
Shortcuts
Description
Collapse
Sections
Menu: Tools > Profile >
Collapse Sections
Toggle the reporting for
collapsed processes and
functions.
Profile
Cutoff
None
Display performance and
memory profile data equal to
or greater than set percentage.
Refresh
Profile Data
None
Refresh profile performance
and memory data after
changing profile cutoff.
Save Profile
Results
Menu: Tools > Profile >
Profile Report
Save profile data to output file
(prompts for file name).
Profile Find
None
Search for the named string.
Schematic Toolbar
The Schematic toolbar provides access to tools for manipulating highlights and signals in the
Dataflow and Schematic windows.
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Figure 2-35. Schematic Toolbar
Table 2-30. Schematic Toolbar Buttons
Button
Name
Shortcuts
Description
Remove All
Highlights
Menu: Dataflow >
Remove Highlight
or
Schematic > Edit > Remove
Highlight
Clear the green highlighting
identifying the path you’ve
traversed through the design.
Menu:
Dataflow > Delete
or
Schematic > Edit > Delete
Schematic > Edit > Delete
All
Delete the selected signal.
Menu: Dataflow >
Regenerate
or
Schematic > Edit >
Regenerate
Clear and redraw the display
using an optimal layout.
Delete
Content
Regenerate
Click and hold the button to
open a drop down menu with
the following options:
• Remove All Highlights
• Remove Selected
Highlights
Click and hold the button to
open a drop down menu with
the following options:
• Delete Selected
• Delete All
Simulate Toolbar
The Simulate toolbar provides various tools for controlling your active simulation.
Figure 2-36. Simulate Toolbar
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Navigating in the Main Window
Table 2-31. Simulate Toolbar Buttons
Button
102
Name
Shortcuts
Description
Source
Navigation
None
Toggles display of hyperlinks
in design source files.
Environment Command: env ..
Up
Menu: File > Environment
Changes your environment up
one level of hierarchy.
Environment Command: env -back
Back
Menu: File > Environment
Change your environment to
its previous location.
Environment Command: env -forward
Forward
Menu: File > Environment
Change your environment
forward to a previously
selected environment.
Restart
Command: restart
Menu: Simulate > Run >
Restart
Reload the design elements
and reset the simulation time to
zero, with the option of
maintaining various settings
and objects.
Run Length
Command: run
Menu: Simulate >
Runtime Options
Specify the run length for the
current simulation.
Run
Command: run
Menu: Simulate > Run >
Run default_run_length
Run the current simulation for
the specified run length.
Continue
Run
Command: run
-continue
Menu: Simulate > Run >
Continue
Continue the current
simulation run until the end of
the specified run length or until
it hits a breakpoint or specified
break event.
Run All
Command: run -all
Menu: Simulate > Run >
Run -All
Run the current simulation
forever, or until it hits a
breakpoint or specified break
event.
Break
Menu: Simulate > Break
Hotkey: Break
Immediate stop of a
compilation, elaboration, or
simulation run. Similar to
hitting a breakpoint if the
simulator is in the middle of a
process.
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Graphical User Interface
Navigating in the Main Window
Table 2-31. Simulate Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Stop -sync
None
Stop simulation the next time
time/delta is advanced.
Step
Command: step
Menu: Simulate > Run >
Step
Step the current simulation to
the next statement.
Step Over
Command: step -over
Menu: Simulate > Run >
Step -Over
Execute HDL statements,
treating them as simple
statements instead of entered
and traced line by line.
Step Out
Command: step -out
Step the current simulation out
of the current function or
procedure.
Step Current
Command: step -inst
Step the current simulation
into an instance, process or
thread.
Click and hold the button to
open a drop down menu with
the following options:
• Into current
• Over current
• Out current
C Interrupt
Command: cdbg interrupt
Menu: Tools > C Debug >
C Interrupt
Reactivate the C debugger
when stopped in HDL code.
Performance
Profiling
Menu: Tools > Profile >
Performance
Enable collection of statistical
performance data.
Memory
Profiling
Menu: Tools > Profile >
Memory
Enable collection of memory
usage data.
Edit
Breakpoints
Menu: Tools > Breakpoint
Enable breakpoint editing,
loading, and saving.
Source Toolbar
The Source toolbar allows you to perform several activities on Source windows.
Figure 2-37. Source Toolbar
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Table 2-32. Source Toolbar Buttons
Button
Name
Shortcuts
Description
Previous
Zero Hits
None
Jump to previous line with
zero coverage.
Next Zero
Hits
None
Jump to next line with zero
coverage.
Show
Language
Templates
Menu: Source >
Show Language Templates
Display language templates in
the left hand side of every open
source file.
Source
Annotation
Menu: Source >
Show Annotation
Allows Debugging with
Source Annotation in every
open source file.
Clear
Bookmarks
Menu: Source >
Clear Bookmarks
Removes any bookmarks in
the active source file.
Standard Toolbar
The Standard toolbar contains common buttons that apply to most windows.
Figure 2-38. Standard Toolbar
Table 2-33. Standard Toolbar Buttons
Button
104
Name
Shortcuts
Description
New File
Menu: File > New > Source
Opens a new Source text file.
Open
Menu: File > Open
Opens the Open File dialog
Save
Menu: File > Save
Saves the contents of the active
window or
Saves the current wave
window display and signal
preferences to a macro file
(DO fie).
ModelSim PE User’s Manual, v10.0d
Graphical User Interface
Navigating in the Main Window
Table 2-33. Standard Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Reload
Command: Dataset Restart
Menu: File > Datasets
Reload the current dataset.
Print
Menu: File > Print
Opens the Print dialog box.
Cut
Menu: Edit > Cut
Hotkey: Ctrl+x
Copy
Menu: Edit > Copy
Hotkey: Ctrl+c
Paste
Menu: Edit > Paste
Hotkey: Ctrl+v
Undo
Menu: Edit > Undo
Hotkey: Ctrl+z
Redo
Menu: Edit > Redo
Hotkey: Ctrl+y
Add Selected Menu: Add > to Wave
to Window
Clicking adds selected objects
to the Wave window. Refer to
“Add Selected to Window
Button” for more information
about the dropdown menu
selections.
Find
Menu: Edit > Find
Hotkey: Ctrl+f (Windows)
or Ctrl+s (UNIX)
Opens the Find dialog box.
Collapse All
Menu: Edit > Expand >
Collapse All
Expand All
Menu: Edit > Expand >
Expand All
Add Selected to Window Button
This button is available when you have selected an object in any of the following windows:
Dataflow, List, Locals, Memory, Objects, Process, Structure, Watch, and Wave windows.
Using a single click, the objects are added to the Wave window. However, if you click-and-hold
the button you can access additional options via a dropdown menu, as shown in Figure 2-39.
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Figure 2-39. The Add Selected to Window Dropdown Menu
•
Add to Wave (Anchor Location) — Adds selected signals above the currently selected
signal, or the first signal if no selection has been made, in the Pathname Pane.
•
•
•
•
•
Add to Wave (End) — Adds selected signals after the last signal in the Wave Window.
Add to Wave (Top) — Adds selected signals above the first signal in the Wave window.
Add to List — Adds selected objects to the List Window.
Add to Dataflow — Adds selected objects to the Dataflow Window.
Add to Watch — Adds selected objects to the Watch Window.
Wave Toolbar
The Wave toolbar allows you to perform specific actions in the Wave window.
Figure 2-40. Wave Toolbar
Table 2-34. Wave Toolbar Buttons
Button
Name
Shortcuts
Description
Show Drivers None
Display driver(s) of the
selected signal, net, or register
in the Dataflow, or Wave
window.
Export
Waveform
Export a created waveform.
Menu: File > Export >
Waveform
Wave Bookmark Toolbar
The Wave Bookmark toolbar allows you to manage your bookmarks of the Wave window
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Navigating in the Main Window
Figure 2-41. Wave Bookmark Toolbar
Table 2-35. Wave Bookmark Toolbar Buttons
Button
Name
Shortcuts
Description
Add
Bookmark
Command: bookmark add
wave
Menu: Add > To Wave >
Bookmark
Clicking this button
bookmarks the current view of
the Wave window.
Click and hold the button to
open a drop down menu with
the following options:
• Add Current View
• Add Custom ...
Delete All
Bookmarks
Command: bookmark delete Removes all bookmarks, after
wave -all
prompting for your
confirmation.
Manage
Bookmarks
Jump to
Bookmark
Displays the Bookmark
Selection dialog box for
managing your bookmarks.
Command: bookmark goto
wave
Displays a selection group for
you to pick which bookmark
you want to display.
Wave Compare Toolbar
The Wave Compare toolbar allows you to quickly find differences in a waveform comparison.
Figure 2-42. Wave Compare Toolbar
Table 2-36. Wave Compare Toolbar Buttons
Button
Name
Shortcuts
Description
Find First
Difference
None
Find the first difference in a
waveform comparison
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Table 2-36. Wave Compare Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Find
Previous
Annotated
Difference
None
Find the previous annotated
difference in a waveform
comparison
Find
Previous
Difference
None
Find the previous difference in
a waveform comparison
Find Next
Difference
None
Find the next difference in a
waveform comparison
Find Next
Annotated
Difference
None
Find the next annotated
difference in a waveform
comparison
Find Last
Difference
None
Find the last difference in a
waveform comparison
Wave Cursor Toolbar
The Wave Cursor toolbar provides various tools for manipulating cursors in the Wave window.
Figure 2-43. Wave Cursor Toolbar
Table 2-37. Wave Cursor Toolbar Buttons
Button
108
Name
Shortcuts
Description
Insert Cursor None
Adds a new cursor to the active
Wave window.
Delete
Cursor
Menu: Wave >
Delete Cursor
Deletes the active cursor.
Find
Previous
Transition
Menu: Edit > Signal Search
Hotkey: Shift + Tab
Moves the active cursor to the
previous signal value change
for the selected signal.
Find Next
Transition
Menu: Edit > Signal Search
Hotkey: Tab
Moves the active cursor to the
next signal value change for
the selected signal.
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Graphical User Interface
Navigating in the Main Window
Table 2-37. Wave Cursor Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Find
Previous
Falling Edge
Menu: Edit > Signal Search
Moves the active cursor to the
previous falling edge for the
selected signal.
Find Next
Falling Edge
Menu: Edit > Signal Search
Moves the active cursor to the
next falling edge for the
selected signal.
Find
Previous
Rising Edge
Menu: Edit > Signal Search
Moves the active cursor to the
previous rising edge for the
selected signal.
Find Next
Rising Edge
Menu: Edit > Signal Search
Moves the active cursor to the
next rising edge for the
selected signal.
Wave Edit Toolbar
The Wave Edit toolbar provides easy access to tools for modifying an editable wave.
Figure 2-44. Wave Edit Toolbar
Table 2-38. Wave Edit Toolbar Buttons
Button
Name
Shortcuts
Description
Insert Pulse
Menu: Wave >
Wave Editor > Insert Pulse
Command: wave edit
insert_pulse
Insert a transition at the
selected time.
Delete Edge
Delete the selected transition.
Menu: Wave >
Wave Editor > Delete Edge
Command: wave edit delete
Invert
Invert the selected section of
Menu: Wave >
the waveform.
Wave Editor > Invert
Command: wave edit invert
Mirror
Mirror the selected section of
Menu: Wave >
the waveform.
Wave Editor > Mirror
Command: wave edit mirror
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Table 2-38. Wave Edit Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Change
Value
Menu: Wave >
Wave Editor > Value
Command: wave edit
change_value
Change the value of the
selected section of the
waveform.
Stretch Edge
Move the selected edge by
Menu: Wave >
Wave Editor > Stretch Edge increasing/decreasing
Command: wave edit stretch waveform duration.
Move Edge
Menu: Wave >
Wave Editor > Move Edge
Command: wave edit move
Extend All
Waves
Increase the duration of all
Menu: Wave >
editable waves.
Wave Editor >
Extend All Waves
Command: wave edit extend
Move the selected edge
without increasing/decreasing
waveform duration.
Wave Expand Time Toolbar
The Wave Expand Time toolbar provides access to enabling and controlling wave expansion
features.
Figure 2-45. Wave Expand Time Toolbar
Table 2-39. Wave Expand Time Toolbar Buttons
Button
110
Name
Shortcuts
Description
Expanded
Time Off
Menu: Wave > Expanded
Time > Off
turns off the expanded time
display (default mode)
Expanded
Time Deltas
Mode
Menu: Wave > Expanded
Time > Deltas Mode
displays delta time steps
Expanded
Time Events
Mode
Menu: Wave > Expanded
Time > Events Mode
displays event time steps
Expand All
Time
Menu: Wave > Expanded
Time > Expand All
expands simulation time over
the entire simulation time
range, from 0 to current time
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Graphical User Interface
Call Stack Window
Table 2-39. Wave Expand Time Toolbar Buttons (cont.)
Button
Name
Shortcuts
Description
Expand Time Menu: Wave > Expanded
Time > Expand Cursor
at Active
Cursor
expands simulation time at the
simulation time of the active
cursor
Collapse All
Time
Menu: Wave > Expanded
Time > Collapse All
collapses simulation time over
entire simulation time range
Collapse
Time at
Active
Cursor
Menu: Wave > Expanded
Time > Collapse Cursor
collapses simulation time at
the simulation time of the
active cursor
Zoom Toolbar
The Zoom toolbar allows you to change the view of the Wave window.
Figure 2-46. Zoom Toolbar
Table 2-40. Zoom Toolbar Buttons
Button
Name
Shortcuts
Description
Zoom In
Menu: Wave > Zoom >
Zoom In
Hotkey: i, I, or +
Zooms in by a factor of 2x
Zoom Out
Menu: Wave > Zoom >
Zoom Out
Hotkey: o, O, or -
Zooms out by a factor of 2x
Zoom Full
Menu: Wave > Zoom >
Zoom Full
Hotkey: f or F
Zooms to show the full length
of the simulation.
Zoom in
on Active
Cursor
Menu: Wave > Zoom >
Zoom Cursor
Hotkey: c or C
Zooms in by a factor of 2x,
centered on the active cursor
Call Stack Window
The Call Stack window displays the current call stack when:
•
you single step the simulation.
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Call Stack Window
•
•
the simulation has encountered a breakpoint.
you select any process in either the Structure or Processes windows.
When debugging your design you can use the call stack data to analyze the depth of function
calls that led up to the current point of the simulation, which include:
•
•
•
•
Verilog functions and tasks
VHDL functions and procedures
SystemC methods and threads
C/C++ functions
The Call Stack window also supports C Debug mode.
Accessing
View > Call Stack
Figure 2-47. Call Stack Window
Call Stack Window Tasks
This window allows you to perform the following actions:
•
112
Double-click on the line of any function call:
o
Displays the local variables at that level in the Locals Window.
o
Displays the corresponding source code in the Source Window.
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Capacity Window
Related Commands of the Call Stack Window
Table 2-41. Commands Related to the Call Stack Window
Command Name
Description
stack down
this command moves down the call stack.
stack frame
this command selects the specified call frame.
stack level
this command reports the current call frame number.
stack tb
this command is an alias for the tb command.
stack up
this command moves up the call stack.
GUI Elements of the Call Stack Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-42. Call Stack Window Columns
Column Title
Description
#
indicates the depth of the function call, with the most recent
at the top.
In
indicates the function. If you see “unknown” in this column,
you have most likely optimized the design such that the
information is not available during the simulation.
Line
indicates the line number containing the function call.
File
indicates the location of the file containing the function call.
Address
indicates the address of the execution in a foreign
subprogram, such as C.
Capacity Window
Use this window to display memory capacity data about your simulation. Refer to the section
“Capacity Analysis” for more information.
Accessing
Access the window using either of the following:
•
Menu item: View > Capacity
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Capacity Window
•
Command: view capacity
Figure 2-48. Capacity Window
GUI Elements of the Capacity Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-43. Capacity Window Columns
Column Title
Description
Type/Object
Refer to the section “Type/Object Listing”
Count
Quantity of design objects analyzed
Current Memory
Current amount of memory allocated, in bytes
Peak Memory
Peak amount of memory allocated, in bytes
Peak Time
The time, in ns, at which the peak memory was reached
Type/Object Listing
When your design contains Verilog design units you will see the following entries in the
Type/Object column
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•
•
Always blocks
•
•
Blocks
•
•
•
•
•
•
•
•
•
Continuous assignment
•
•
•
•
•
•
Registers
Assertions — When using fine-grained analysis (vsim -capacity) this entry expands and
provides information for each assertion.
Classes — When using fine-grained analysis (vsim -capacity) this entry expands and
provides information for each class.
Covergroups
Function instances
Initial
Initial blocks
Module instances
Nets
Parameters
QDAs — When using fine-grained analysis (vsim -capacity) this entry expands and
provides information for Queues, Dynamic Arrays, and Associative Arrays.
Solver
System task instances
Task instances
Verilog Memories
Verilog Ports
When your design contains VHDL design units you will see the following entries in the
Type/Object column
•
•
•
•
Instances
Ports
Signals
Processes
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Class Graph Window
Class Graph Window
The Class Graph window provides a graphical view of your SystemVerilog classes, including
any extensions of other classes and related methods and properties.
Accessing
•
•
Menu item: View > Class Browser > Class Graph
Command: view classgraph
Figure 2-49. Class Graph Window
Class Graph Window Tasks
This section describes tasks for using the Cover Directives window.
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Class Graph Window
Navigating in the Class Graph Window
You can change the view of the Class Graph window with your mouse or the arrow keys on
your keyboard.
•
•
•
•
Left click-drag — allows you to move the contents around in the window.
Middle Mouse scroll — zooms in and out.
Middle mouse button strokes:
o
Upper left — zoom full
o
Upper right — zoom out. The length of the stroke changes the zoom factor.
o
Lower right — zoom area.
Arrow Keys — scrolls the window in the specified direction.
o
Unmodified — scrolls by a small amount.
o
Ctrl+ — scrolls by a larger amount
o
Shift+ — shifts the view to the edge of the display
GUI Elements of the Class Graph Window
This section describes the GUI elements specific to the Class Graph window.
Popup Menu Items
Table 2-44. Class Graph Window Popup Menu
Popup Menu Item
Description
Filter
Controls the display of methods and properties from
the class boxes.
Zoom Full
View Entire Design
Reloads the view to show the class hierarchy of the
complete design.
Print to Postscript
Organize by Base/Extended Class
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reorganizes the window so that the base or extended
(default) classes are at the top of the hierarchy.
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Class Tree Window
Class Tree Window
The Class Tree window provides a hierarchical view of your SystemVerilog classes, including
any extensions of other classes, related methods and properties, as well as any covergroups.
Figure 2-50. Class Tree Window
Accessing
•
•
Select View > Class Browser > Class Tree
Use the command:
view classtree
GUI Elements of the Class Tree Window
This section describes the GUI elements specific to the Class Tree window.
Icons
Table 2-45. Class Tree Window Icons
Icon
Description
Class
Parameterized Class
Function
Task
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Class Tree Window
Table 2-45. Class Tree Window Icons (cont.)
Icon
Description
Variable
Virtual Interface
Covergroup
Structure
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Code Coverage Analysis Window
Column Descriptions
Table 2-46. Class Tree Window Columns
Column
Description
Class
The name of the item
Type
The type of item
File
The source location of the item
Unique Id
The internal name of the parameterized class
(only available with parameterized classes)
Scope
The scope of the covergroup
(only available with covergroups
Popup Menu Items
Table 2-47. Class Tree Window Popup Menu
Popup Menu Item
Description
View Declaration
Highlights the line of code where the item is declared,
opening the source file if necessary.
View as Graph
Displays the class and any dependent classes in the
Class Graph window.
(only available for classes)
Filter
allows you to filter out methods and or properties
Organize by Base/Extended Class
reorganizes the window so that the base or extended
(default) classes are at the top of the hierarchy.
Code Coverage Analysis Window
Use this window to view covered (executed), uncovered (missed), and/or excluded statements,
branches, conditions, expressions, FSM states and transitions, as well as signals that have and
have not toggled.
The Code Coverage Analysis window replaces all functionality previously found in the Missing
and Current Exclusions windows.
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Code Coverage Analysis Window
Prerequisites
This window is specific to the collection of coverage metrics, therefore you must have run your
simulation with coverage collection enabled. Refer to the “Code Coverage” chapter for more
information.
Accessing
Access the window using either of the following:
•
Menu item: View > Coverage > Code Coverage Analysis
Then, select the desired analysis type from the Code Coverage Analysis window’s title
bar, detailed in Table 2-48.
•
Command: view canalysis
Figure 2-51. Code Coverage Analysis
The selection of icons on the right side of the banner of the Code Coverage Analysis window
function as described below. By default, the icons are selected (active).
Table 2-48. Actions in Code Coverage Analysis Title Bar
Icon
Action
Analysis Type button: Specifies the type of coverage
analysis currently selected in the sub-window inside the
Code Coverage Analysis window. Six selections are
available when you click on the type, as shown in the
image to the left.
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Code Coverage Analysis Window
Table 2-48. Actions in Code Coverage Analysis Title Bar
Icon
Action
Covered items button: When selected (default, as shown in
image), all covered (hit) items are displayed in the window.
When not selected, all items are filtered from view.
Missed items button: When selected (default), all missed
items (not executed) are displayed in the window. When
not selected, all missed items are filtered from view.
Excluded items button: When selected (default), all
excluded items are displayed in window. When not
selected, excluded items are filtered from view.
Viewing Code Coverage Data and Current Exclusions
To view executed or missed statements, branches, conditions, expressions, or FSMs, as well as
items excluded from coverage, do the following:
1. Select a file in the Files window, or an instance or design unit in the Structure window
whose coverage you wish to analyze.
2. With the Code Coverage Analysis window active. select the type of coverage to view
(Branch Analysis, Condition analysis, etc.) from the pulldown menu in the Analysis
toolbar (Figure 2-51).
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Code Coverage Analysis Window
Figure 2-52. Missed Coverage in Code Coverage Analysis Windows
Each coverage type window includes a column for the line number and a column for statement,
branch, condition, expression, or toggle on that line. An icon indicates whether the object was
executed (green check mark), not executed (red X), or excluded (green E). See Table 2-78 for a
complete list of icons.
In the banner for all Coverage Analysis window types, the following information appears:
•
•
name of the window
•
•
scope of the coverage item (in parentheses) being displayed
whether the coverage is by file or by instance (depending on whether a file was selected
in the Files tab or an instance or du from the sim tab)
Analysis Type button, Covered Items button, Missed Coverage buttons, Excluded Items
button (see Table 2-48)
You can change the scope displayed (for all Code Coverage Analysis windows) by selecting a
new scope in the Structure or Files windows.
When you select (left-click) any item in the Statement, Branch, Condition, Expression, FSM or
Toggle Analysis windows, the Coverage Details Window populates with related details
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Coverage Details Window
(coverage statistic details, truth tables, exclusions and so on) about that object. In the case of a
multi-line statement, branch, condition or expression, select the object on the last line of the
item.
The Branch Analysis window includes a column for branch code (conditional "if/then/else" and
"case" statements). "XT" indicates that the true condition of the branch was not executed. "XF"
indicates that the false condition of the branch was not executed. Fractional numbers indicate
how many case statement labels were executed.
When you right-click any item in the window, a menu appears with options to control adding or
removing coverage exclusions.
Note
Multi-line objects are rooted in the last line, and exclusions must be applied on that line #
in order to take effect.
See “Coverage Details Window” for a description of the type of detailed information viewed in
the Details window for each coverage type.\
See “Source Window” for a description of adding comments with exclusions,
Coverage Details Window
Use this window to view detailed results about coverage metrics from your simulation.
Prerequisites
This window is specific to the collection of coverage metrics, therefore you must have run your
simulation with coverage collection enabled. Refer to the chapter “Code Coverage” for more
information.
Accessing
Access the window using either of the following:
•
•
Menu item: View > Coverage > Details
Command: view details
You can populate this window by selecting an item in one of the panes of the Code Coverage
Analysis Window: either Statement, Branch, Expression, Condition, FSM or Toggle.
Coverage Details of Statement Coverage
The Coverage Details window displays the following information about Statement Coverage
metrics:
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Coverage Details Window
•
Instance — the dataset name followed by the hierarchical location of the statement.
Only appears when you are analyzing coverage metrics by instance.
•
•
File — the name of the file containing the statement.
•
•
Statement Coverage for — name of the statement itself.
Line — the line number of the statement. In the case of a multi-line statement, this is the
last line of the statement.
Hits — the number of times the statement was hit during the simulation.
If a line number contains multiple statements, the coverage details window contains the metrics
for each statement.
Coverage Details of Branch Coverage
The Coverage Details window displays the following information about Branch Coverage
metrics:
•
Instance — the dataset name followed by the hierarchical location of the branch. Only
appears when you are analyzing coverage metrics by instance.
•
•
File — the name of the file containing the statement.
•
•
Branch Coverage for — the statement itself.
Line — the line number of the statement. In the case of a multi-line branch statement,
this is the last line of the statement.
Branch if — the number of times the branch resolved as True or False.
Coverage Details of Condition and Expression Coverage
The Coverage Details window displays the following information about Condition and
Expression Coverage metrics:
•
Instance — the dataset name followed by the hierarchical location of the condition. Only
appears when you are analyzing coverage metrics by instance.
•
•
File — the filename containing the condition.
•
•
Condition/Expression Coverage for — the syntax of the condition.
Line — the line number of the filename containing the condition or expression. In the
case of a multi-line condition statement, this is the last line of the statement.
FEC Coverage — a tabular representation of the focused expression coverage metrics to
satisfy the condition. Refer to the section “FEC Coverage Detailed Examples” for more
information about FEC condition/expression coverage. You can exclude rows or rows
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Coverage Details Window
by instance through a popup menu accessible by right-clicking on a row in the table (see
Figure 2-53).
•
UDP Coverage — not included in the Details window, unless -coverudp was specified
with vcom/vlog/vopt.
Refer to the section “UDP Coverage Details and Examples” for more information about
UDP condition/expression coverage.
Figure 2-53. Coverage Details Window Showing Expression Truth Table
Coverage Details of Toggle Coverage
The Coverage Details window displays the following information about Toggle Coverage
metrics:
•
Instance — the dataset name followed by the hierarchical location of the signal. Only
appears when you are analyzing coverage metrics by instance.
•
•
•
Signal — the name of the signal (data[6]) or (data).
Node Count — The size of the signal.
Toggle List — the list of toggles analyzed during simulation. This list will differ
depending on whether you specified extended toggle coverage. Refer to the section
“Standard and Extended Toggle Coverage” for more information.
o
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Toggle coverage shows toggle metrics between 0 and 1
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Coverage Details Window
o
•
•
•
•
Extended toggle coverage shows toggle metrics between 0, 1 and Z.
Toggle Coverage — The percentage of nodes that were covered.
0/1 Coverage — The percentage of standard toggles that were covered.
Full Coverage — The percentage of extended toggles that were covered.
Z Coverage — The percentage of toggles involving Z that were covered.
Toggle details are displayed as follows:
Figure 2-54. Coverage Details Window Showing Toggle Details
Coverage Details of FSM Coverage
The Coverage Details window displays the following information about Finite State Machine
Coverage metrics:
•
•
Finite State Machine — the name of the finite state machine
•
•
•
•
State Coverage — a list of all the states, followed by the number of hits.
Instance — the dataset name followed by the hierarchical location of the FSM. Only
appears when you are analyzing coverage metrics by instance.
Transition Coverage — a list of all the transitions, followed by the number hits.
State Coverage — the coverage percentage for the states.
Transition Coverage — the coverage percentage for the transitions.
FSM details are displayed as shown in Figure 2-55:
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Dataflow Window
Figure 2-55. Coverage Details Window Showing FSM Details
Dataflow Window
Use this window to explore the "physical" connectivity of your design. You can also use it to
trace events that propagate through the design; and to identify the cause of unexpected outputs.
The Dataflow window displays:
•
•
•
128
processes
signals, nets, and registers
interconnects
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Dataflow Window
The window has built-in mappings for all Verilog primitive gates (that is, AND, OR, PMOS,
NMOS, and so forth.). For components other than Verilog primitives, you can define a mapping
between processes and built-in symbols. See Symbol Mapping for details.
Note
You cannot view SystemC objects in the Dataflow window.
Note
ModelSim versions operating without a dataflow license feature have limited Dataflow
functionality. Without the license feature, the window will show only one process and its
attached signals or one signal and its attached processes.
Accessing
Access the window using either of the following:
•
•
Menu item: View > Dataflow
Command: view dataflow
Figure 2-56. Dataflow Window
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Dataflow Window
Dataflow Window Tasks
This section describes tasks for using the Dataflow window.
You can interact with the Dataflow in one of three different Mouse modes, which you can
change through the DataFlow menu or the Zoom Toolbar:
•
Select Mode — your left mouse button is used for selecting objects and your middle
mouse button is used for zooming the window. This is the default mode.
•
Zoom Mode — your left mouse button is used for zooming the window and your middle
mouse button is used for panning the window.
•
Pan Mode — your left mouse button is used for panning the window and your middle
mouse button is used for zooming the window.
Selecting Objects in the Dataflow Window
When you select an object, or objects, it will be highlighted an orange color.
•
•
Select a single object — Single click.
Select multiple objects — Shift-click on all objects you want to select or click and drag
around all objects in a defined area. Only available in Select Mode.
Zooming the View of the Dataflow Window
Several zoom controls are available for changing the view of the Dataflow window, including
mouse strokes, toolbar icons and a mouse scroll wheel.
•
•
•
130
Zoom Full — Fills the Dataflow window with all visible data.
o
Mouse stroke — Up/Left. Middle mouse button in Select and Pan mode, Left mouse
button in Zoom mode.
o
Menu — DataFlow > Zoom Full
o
Zoom Toolbar — Zoom Full
Zoom Out
o
Mouse stroke — Up/Right. Middle mouse button in Select and Pan mode, Left
mouse button in Zoom mode.
o
Menu — DataFlow > Zoom Out
o
Zoom Toolbar — Zoom Out
o
Mouse Scroll — Push forward on the scroll wheel.
Zoom In
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Dataflow Window
•
o
Menu — DataFlow > Zoom In
o
Zoom Toolbar — Zoom In
o
Mouse Scroll — Pull back on the scroll wheel.
Zoom Area — Fills the Dataflow window with the data within the bounding box.
o
•
Mouse stroke — Down/Right
Zoom Selected — Fills the Dataflow window so that all selected objects are visible.
o
Mouse stroke — Down/Left
Panning the View of the Dataflow Window
You can pan the view of the Dataflow window with the mouse or keyboard.
•
Pan with the Mouse — In Zoom mode, pan with the middle mouse button. In Pan mode,
pan with the left mouse button. In Select mode, pan with the Ctrl key and the middle
mouse button.
•
Pan with the Keyboard — Use the arrow keys to pan the view. Shift+ pans
to the far edge of the view. Ctrl+ pans by a moderate amount.
Displaying the Wave Viewer Pane
You can embed a miniature wave viewer in the Dataflow window (Figure 2-57.
1. Select the DataFlow > Show Wave menu item.
2. Select a process in the Dataflow pane to populate the Wave pane with signal
information.
Refer to the section “Exploring Designs with the Embedded Wave Viewer” for more
information.
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Files Window
Figure 2-57. Dataflow Window and Panes
Files Window
Use this window to display the source files and their locations for the loaded simulation.
Prerequisites
You must have executed the vsim command before this window will contain any information
about your simulation environment.
Accessing
Access the window using either of the following:
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Files Window
•
•
Menu item: View > Files
Command: view files
Figure 2-58. Files Window
GUI Elements of the Files Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-49. Files Window Columns
Column Title
Description
Name
The name of the file
Specified Path
The location of the file as specified in the
design files.
Full Path
The full-path location of the design files.
Type
The file type.
Branch info
A series of columns reporting branch
coverage
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Files Window
Table 2-49. Files Window Columns (cont.)
Column Title
Description
Condition info
A series of columns reporting condition
coverage
Expression info
A series of columns reporting expression
coverage
FEC condition info
A series of columns reporting condition
coverage based on Focused Expression
Coverage
FEC expression info
A series of columns reporting expression
coverage based on Focused Expression
Coverage
States info
A series of columns reporting finite state
machine coverage
Statement info
A series of columns reporting statement
coverage
Toggles info
A series of columns reporting toggle
coverage
Transition info
A series of columns reporting transition
coverage
Refer to Table 2-79 “Columns in the Structure Window” for detailed information about the
coverage metric columns.
Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:
Table 2-50. Files Window Popup Menu
134
Menu Item
Description
View Source
Opens the selected file in a Source window
Open in external editor
Opens the selected file in an external editor.
Only available if you have set the Editor preference:
• set PrefMain(Editor) {}
• Tools > Edit Preferences; by Name tab, Main group.
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FSM List Window
Table 2-50. Files Window Popup Menu (cont.)
Menu Item
Description
Code Coverage >
These menu items are only available if you ran the
simulation with the -coverage switch.
• Code Coverage Reports — Opens the Coverage Text
Report dialog box, allowing you to create a coverage
report for the selected file.
• Exclude Selected File — Executes the coverage
exclude command for the selected file(s).
• Clear Code Coverage Data — Clears all code coverage
information collected during simulation
Properties
Displays the File Properties dialog box, containing
information about the selected file.
Files Menu
This menu becomes available in the Main menu when the Files window is active.
Table 2-51. Files Menu
Files Menu Item
Description
View Source
Opens the selected file in a Source window
Open in external editor
Opens the selected file in an external editor.
Only available if you have set the Editor preference:
• set PrefMain(Editor) {}
• Tools > Edit Preferences; by Name tab, Main
group.
Save Files
Saves a text file containing a sorted list of unique
files, one per line. The default name is summary.txt.
FSM List Window
Use this window to view a list of finite state machines in your design.
Prerequisites
This window is populated when you specify any of the following switches during compilation
(vcom/vlog).
•
•
+cover or +cover=f
+acc or +acc=f
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FSM List Window
Accessing
Access the window using either of the following:
•
•
Menu item: View > FSM List
Command: view fsmlist
Figure 2-59. FSM List Window
GUI Elements of the FSM List Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-52. FSM List Window Columns
136
Column Title
Description
Instance
Lists the FSM instances.
You can reduce the number of path elements in this
column by selecting the FSM List > Options menu
item and altering the Number of Path Elements
selection box.
States
The number of states in the FSM.
Transitions
The number of transitions in the FSM.
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Graphical User Interface
FSM Viewer Window
Popup Menu
Right-click on one of the FSMs in the window to display the popup menu and select one of the
following options:
Table 2-53. FSM List Window Popup Menu
Popup Menu Item
Description
View FSM
Opens the FSM in the FSM Viewer window.
View Declaration
Opens the source file for the FSM instance.
Set Context
Changes the context to the FSM instance.
Add to
Adds FSM information to the specified window.
Properties
Displays the FSM Properties dialog box containing
detailed information about the FSM.
FSM List Menu
This menu becomes available in the Main menu when the FSM List window is active.
Table 2-54. FSM List Menu
Popup Menu Item
Description
View FSM
Opens the FSM in the FSM Viewer window.
View Declaration
Opens the source file for the FSM instance.
Add to
Adds FSM information to the specified window.
Options
Displays the FSM Display Options dialog box,
which allows you to control:
• how FSM information is added to the Wave
Window.
• how much information is shown in the Instance
Column
FSM Viewer Window
Use this window to graphically analyze finite state machines in your design.
Prerequisites
•
Analyze FSMs and their coverage data — you must specify +cover, or explicitly
+cover=f, during compilation and -coverage on the vsim command line to fully analyze
FSMs with coverage data.
•
Analyze FSMs without coverage data — you must specify +acc, or explicitly +acc=f,
during compilation (vcom/vlog) to analyze FSMs with the FSM Viewer window.
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FSM Viewer Window
Accessing
Access the window:
•
•
From the FSM List window, double-click on the FSM you want to analyze.
From the Objects, Locals, Wave, or Code Coverage Analyze’s FSM Analysis windows,
click on the FSM button
for the FSM you want to analyze.
Figure 2-60. FSM Viewer Window
FSM Viewer Window Tasks
This section describes tasks for using the FSM Viewer window.
Using the Mouse in the FSM Viewer
These mouse operations are defined for the FSM Viewer:
•
138
The mouse wheel performs zoom & center operations on the diagram.
o
Mouse wheel up — zoom out.
o
Mouse wheel down — zoom in.
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FSM Viewer Window
Whether zooming in or out, the view will re-center towards the mouse location.
•
•
Left mouse button — click and drag to move the view of the FSM.
Middle mouse button — click and drag to perform the following stroke actions:
o
Up and left — Zoom Full.
o
Up and right — Zoom Out. The amount is determined by the distance dragged.
o
Down and right — Zoom In on the area of the bounding box.
Using the Keyboard in the FSM Viewer
These keyboard operations are defined for the FSM Viewer:
•
Arrow Keys — scrolls the window in the specified direction.
o
Unmodified — scrolls by a small amount.
o
Ctrl+ — scrolls by a larger amount.
o
Shift+ — shifts the view to the edge of the display.
Exporting the FSM Viewer Window as an Image
Save the FSM view as an image for use in other applications.
1. Select the FSM Viewer window.
2. Export to one of the following formats:
o
Postscript — File > Print Postscript
o
Bitmap (.bmp) — File > Export > Image
JPEG (.jpg)
PNG (.png)
GIF (.gif)
Combining Common Transitions to Reset
By default, the FSM Viewer window combines transitions to reset that are based upon common
conditions. This reduces the amount of information drawn in the window and eases your FSM
debugging tasks.
Figure 2-61 shows two versions of the same FSM. The top image shows all of the transitions
and the bottom image combines the common conditions (rst) into a single transition, as
referenced by the gray diamond placeholder.
You control the level of detail for transitions with the FSM View > Transitions to “reset”
menu items.
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FSM Viewer Window
Figure 2-61. Combining Common Transition Conditions
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FSM Viewer Window
GUI Elements of the FSM Viewer Window
This section describes GUI elements specific to this Window.
Table 2-55. FSM Viewer Window — Graphical Elements
Graphical Element Description
Blue state bubble
Definition
Default appearance for non-reset states.
Tan state bubble with Indicates a reset state.
double outline.
Gray diamond
Indicates there are several transitions to reset
with the same expression. This is a placeholder
to reduce the number of objects drawn in the
window. You can view all common
expressions by selecting:
FSM View > Transitions to “reset” > Show
All
Transition box
Contains information about the transition,
• Cond: specifies the transition condition1
• Count: specifies the coverage count
Black transition line. Indicates a transition.
Red transition line.
Indicates a transition that has zero (0) coverage.
1. The condition format is based on the GUI_expression_format Operators.
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FSM Viewer Window
Popup Menu
Right-click in the window to display the popup menu and select one of the following options:
Table 2-56. FSM View Window Popup Menu
Popup Menu Item
Description
Transition
Only available when right-clicking on a transition.
• Goto Source — Opens the source file containing
the state machine and highlights the transition
code.
• View Full Text — Opens the View Transition
dialog box, which contains the full text of the
condition.
View Declaration
Opens the source file and bookmarks the file line
containing the declaration of the state machine
Zoom Full
Displays the FSM completely within the window.
Set Context
Executes the env command to change the context to
that of the state machine.
Add to ...
Adds information about the state machine to the
specific window.
Properties
Displays the FSM Properties dialog box containing
detailed information about the FSM.
FSM View Menu
This menu becomes available in the Main menu when the FSM View window is active.
Table 2-57. FSM View Menu
FSM View Menu Item
Description
Show State Counts
Displays the coverage counts for each state in the
state bubble.
Show Transition Counts
Displays the coverage counts for each transition.
Show Transition Conditions Displays the condition for each transition.
The condition format is based on the
GUI_expression_format Operators.
142
Enable Info Mode Popups
Displays popup information when you hover over a
state or transition.
Track Wave Cursor
Displays current and previous state information
based on the cursor location in the Wave window.
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Instance Coverage Window
Table 2-57. FSM View Menu
FSM View Menu Item
Description
Transitions to “Reset”
Controls the display of transitions to a reset state:
• Show All
• Show None — will also add a “hide all” note to
the lower-right hand corner.
• Hide Asynchronous Only
• Combine Common Transitions — (default)
creates a single transition for any transitions to
reset that use the same condition. The transition
is shown from a gray diamond that acts as a
placeholder.
Options
Displays the FSM Display Options dialog box,
which allows you to control:
• how FSM information is added to the Wave
Window.
• how much information is shown in the Instance
Column
Instance Coverage Window
Use this window to analyze coverage statistics for each instance in a flat, non-hierarchical view.
You can sort data columns to be more meaningful, and not be confused by hierarchy. This
window contains the same code coverage statistics columns as in the Files and Structure
windows.
Prerequisites
This window is specific to the collection of coverage metrics, therefore you must have run your
simulation with coverage collection enabled. Refer to the chapter “Code Coverage” for more
information.
Accessing
Access the window using either of the following:
•
•
Menu item: View > Coverage > Instance Coverage
Command: view instance
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Instance Coverage Window
Figure 2-62. Instance Coverage Window
Instance Coverage Window Tasks
This section describes tasks for using the Instance Coverage window.
Setting a Coverage Threshold
You can specify a percentage above or below which you don’t want to see coverage statistics.
For example, you might set a threshold of 85% such that only objects with coverage below that
percentage are displayed. Anything above that percentage is filtered.
Procedure
1. Right-click any object in the Instance Coverage window.
2. Select Set filter. The “Filter instance list” dialog appears as in Figure 2-63.
Figure 2-63. Filter Instance List Dialog Box
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Library Window
GUI Elements of the Instance Coverage Window
This section describes GUI elements specific to this Window.
Column Descriptions
Refer to the section “GUI Elements of the Structure Window” for a description of the Instance
Coverage window columns.
Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:
Table 2-58. Instance Coverage Popup Menu
Popup Menu Item
Description
Code coverage reports
Displays the Coverage Text Report dialog box,
which allows you to create reports based on your
code coverage metrics.
Set Filter
Displays the Filter Instance List Dialog Box
Clear code coverage data
clears all of the code coverage data from the GUI.
XML Import Hint
Displays the XML Import Hint dialog box with
information about the data for you to cut and paste.
Library Window
Use this window to view design libraries and compiled design units.
Accessing
Access the window using either of the following:
•
•
Menu item: View > Library
Command: view library
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Library Window
Figure 2-64. Library Window
GUI Elements of the Library Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-59. Library Window Columns
Column Title
Description
Name
Name of the library or design unit
Path
Full pathname to the file
Type
Type of file
Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:
Table 2-60. Library Window Popup Menu
146
Popup Menu Item
Description
Simulate
Loads a simulation of the selected design unit
Simulate with Coverage
Loads a simulation of the selected design unity,
enabling coverage (-coverage)
Edit
Opens the selected file in your editor window.
Refresh
Reloads the contents of the window
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Graphical User Interface
List Window
Table 2-60. Library Window Popup Menu
Popup Menu Item
Description
Recompile
Compiles the selected file.
Update
Create Wave
Runs the wave create command for any ports in the
selected design unit.
Delete
Removes a design unit from the library or runs the
vdel command on a selected library.
Copy
Copies the directory location of libraries or the
library location of design units within the library.
New
Allows you to create a new library with the Create a
New Library dialog box.
Properties
Displays information about the selected library or
design unit.
List Window
Use this window to display a textual representation of waveforms, which you can configure to
show events and delta events for the signals or objects you have added to the window.
You can view the following object types in the List window:
•
•
•
•
•
VHDL — signals, aliases, process variables, and shared variables
Verilog — nets, registers, and variables
SystemC — primitive channels, ports, and transactions
Comparisons — comparison objects; see Waveform Compare for more information
Virtuals — virtual signals and functions
Accessing
Access the window using either of the following:
•
•
Menu item: View > List
Command: view list
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List Window
Figure 2-65. List Window
List Window Tasks
This section describes tasks for using the List window.
Adding Data to the List Window
You can add objects to the List window in any of the following ways:
•
right-clicking on signals and objects in the Objects window or the Structure window and
selecting Add > to List.
•
•
using the add list command.
using the “Add Selected to Window Button“.
Selecting Multiple Signals
To create a larger group of signals and assign a new name to this group, do the following:
1. Select a group of signals
o
Shift-click on signal columns to select a range of signals.
o
Control-click on signal columns to select a group of specific signals.
2. Select List > Combine Signals
3. Complete the Combine Selected Signals dialog box
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o
Name — Specify the name you want to appear as the name of the new signal.
o
Order of Indexes — Specify the order of the new signal as ascending or descending.
o
Remove selected signals after combining — Specify whether the grouped signals
should remain in the List window.
This process creates virtual signals. For more information, refer to the section Virtual Signals.
Other List Window Tasks
•
•
List > List Preferences — Allows you to specify the preferences of the List window.
File > Export > Tabular List — Exports the information in the List window to a file in
tabular format. Equivalent to the command:
write list
•
File > Export > Event List — Exports the information in the List window to a file in
print-on-change format. Equivalent to the command:
write list -event
•
File > Export > TSSI List — Exports the information in the List window to a file in
TSSI. Equivalent to the command:
write tssi -event
•
Edit > Signal Search — Allows you to search the List window for activity on the
selected signal.
GUI Elements of the List Window
This section describes the GUI elements specific to the List window.
Window Panes
The List window is divided into two adjustable panes, which allow you to scroll horizontally
through the listing on the right, while keeping time and delta visible on the left.
•
•
The left pane shows the time and any deltas that exist for a given time.
The right pane contains the data for the signals and objects you have added for each time
shown in the left pane. The top portion of the window contains the names of the signals.
The bottom portion shows the signal values for the related time.
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List Window
Note
The display of time values in the left column is limited to 10 characters. Any time value
of more than 10 characters is replaced with the following:
too narrow
Markers
The markers in the List window are analogous to cursors in the Wave window. You can add,
delete and move markers in the List window similarly to the Wave window. You will notice two
different types of markers:
•
•
Active Marker — The most recently selected marker shows as a black highlight.
Non-active Marker — Any markers you have added that are not active are shown with a
green border.
You can manipulate the markers in the following ways:
•
Setting a marker — When you click in the right-hand portion of the List window, you
will highlight a given time (black horizontal highlight) and a given signal or object
(green vertical highlight).
•
Moving the active marker — List window markers behave the same as Wave window
cursors. There is one active marker which is where you click along with inactive
markers generated by the Add Marker command. Markers move based on where you
click. The closest marker (either active or inactive) will become the active marker, and
the others remain inactive.
•
Adding a marker — You can add an additional marker to the List window by rightclicking at a location in the right-hand side and selecting Add Marker.
•
Deleting a marker — You can delete a marker by right-clicking in the List window and
selecting Delete Marker. The marker closest to where you clicked is the marker that will
be deleted.
Popup Menu
Right-click in the right-hand pane to display the popup menu and select one of the following
options:
Table 2-61. List Window Popup Menu
150
Popup Menu Item
Description
Examine
Displays the value of the signal over which you used
the right mouse button, at the time selected with the
Active Marker
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Locals Window
Table 2-61. List Window Popup Menu
Popup Menu Item
Description
Annotate Diff
Allows you to annotate a waveform comparison
difference with additional information. For more
information refer to the compare annotate command.
Available only during a Waveform Comparison.
Ignore Diff
Flags the waveform compare difference as
“ignored”. For more information refer to the
compare annotate command. Available only during a
Waveform Comparison
Add Marker
Adds a marker at the location of the Active Marker
Delete Marker
Deletes the closest marker to your mouse location
The following menu items are available when the List window is active:
Locals Window
Use this window to display data objects declared in the current, or local, scope of the active
process. These data objects are immediately visible from the statement that will be executed
next, which is denoted by a blue arrow in a Source window. The contents of the window change
from one statement to the next.
When encountering a C breakpoint, the Locals window displays automatic local variables and
their value in current C/C++ function scope.
Accessing
Access the window using either of the following:
•
•
Menu item: View > locals
Command: view locals
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Locals Window
Figure 2-66. Locals Window
Locals Window Tasks
This section describes tasks for using the Locals window.
Viewing Data in the Locals Window
You cannot actively place information in the Locals window, it is updated as you go through
your simulation. However, there are several ways you can trigger the Locals window to be
updated.
•
•
•
Run your simulation while debugging.
Select a Process from the Processes Window.
Select a Verilog function or task or VHDL function or procedure from the Call Stack
Window.
GUI Elements of the Locals Window
This section describes the GUI elements specific to the Locals Window.
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Column Descriptions
Table 2-62. Locals Window Columns
Column
Description
Name
lists the names of the immediately visible data objects.
This column also includes design object icons for the
objects, refer to the section “Design Object Icons and
Their Meaning” for more information.
Value
lists the current value(s) associated with each name.
State Count
Not shown by default. This column, State Hits, and
State % are all specific to coverage analysis
State Hits
Not shown by default.
State %
Not shown by default.
Popup Menu
Right-click anywhere in the Locals window to open a popup menu.
Table 2-63. Locals Window Popup Menu
Popup Menu Item
Description
View Declaration
Displays, in the Source window, the declaration
of the object.
Add
Adds the selected object(s) to the specified
window (Wave, List, Log, Dataflow, ).
Copy
Copies selected item to clipboard
Find
Opens the Find toolbar at the bottom of the
window
Expand/Collapse
Expands or collapses data in the window
Global Signal Radix
Sets radix for selected signal(s) in all windows
Change
Displays the Change Selected Variable Dialog
Box, which allows you to alter the value of the
object.
Change Selected Variable Dialog Box
This dialog box allows you to change the value of the object you selected. When you click
Change, the tool executes the change command on the object.
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Memory List Window
Figure 2-67. Change Selected Variable Dialog Box
The Change Selected Variable dialog is prepopulated with the following information about the
object you had selected in the Locals window:
•
•
Variable Name — contains the complete name of the object.
Value — contains the current value of the object.
When you change the value of the object, you can enter any value that is valid for the variable.
An array value must be specified as a string (without surrounding quotation marks). To modify
the values in a record, you need to change each field separately.
Memory List Window
Use this window to view a list of all memories in your design.
Single dimensional arrays of integers are interpreted as 2D memory arrays. In these cases, the
word width listed in the Memory window is equal to the integer size, and the depth is the size of
the array itself.
Memories with three or more dimensions display with a plus sign ’+’ next to their names in the
Memory window. Click the ’+’ to show the array indices under that level. When you finally
expand down to the 2D level, you can double-click on the index, and the data for the selected
2D slice of the memory will appear in a memory contents window.
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Memory List Window
Prerequisites
The simulator identifies certain kinds of arrays in various scopes as memories. Memory
identification depends on the array element kind as well as the overall array kind (that is,
associative array, unpacked array, and so forth.).
Table 2-64. Memory Identification
VHDL
Verilog/SystemVerilog
Element Kind1
•
•
•
•
•
•
enum2
any integral type (that is,
integer_type):
bit_vector
floating point type • shortint
std_logic_vector
• int
std_ulogic_vector
• longint
integer type
• byte
• bit (2 state)
• logic
• reg
• integer
• time (4 state)
• packed_struct/
packed_union (2 state)
• packed_struct/
packed_union (4 state)
• packed_array
(single-Dim, multi-D, 2
state and 4 state)
• enum
• string
Scope:
Recognizable
in
•
•
•
architecture
process
record
•
•
•
•
•
•
Array Kind
•
•
single-dimensional
multi-dimensional
•
•
•
SystemC
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
unsigned char
unsigned short
unsigned int
unsigned long
unsigned long long
char
short
int
float
double
enum
sc_bigint
sc_biguint
sc_int
sc_uint
sc_signed
sc_unsigned
module
interface
package
compilation unit
struct
static variables within a
• task
• function
• named block
• class
•
sc_module
any combination of
unpacked, dynamic and
associative arrays3
real/shortreal
float
•
•
single-dimensional
multi-dimensional
1. The element can be "bit" or "std_ulogic" if the array has dimensionality >= 2.
2. These enumerated types must have at least one enumeration literal that is not a character literal. The listed
width is the number of entries in the enumerated type definition and the depth is the size of the array itself.
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Memory List Window
3. Any combination of unpacked, dynamic, and associative arrays is considered a memory, provided the leaf
level of the data structure is a string or an integral type.
Accessing
Access the window using either of the following:
•
•
Menu item: View > Memory List
Command: view memory list
Figure 2-68. Memory LIst Window
Memory List Window Tasks
This section describes tasks for using the Memory List window.
Viewing Packed Arrays
By default, packed dimensions are treated as single vectors in the Memory List window. To
expand packed dimensions of packed arrays, select Memories > Expand Packed Memories.
To change the permanent default, edit the PrefMemory(ExpandPackedMem) variable. This
variable affects only packed arrays. If the variable is set to 1, the packed arrays are treated as
unpacked arrays and are expanded along the packed dimensions such that they appear as a
linearized bit vector. Refer to the section “Simulator GUI Preferences” for details on setting
preference variables.
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Memory List Window
Viewing Memory Contents
When you double-click an instance on the Memory List window, ModelSim automatically
displays a Memory Data window, where the name used on the tab is taken from the name of the
instance, as seen in the Memory window. You can also enter the command add mem
at the vsim command prompt.
Viewing Multiple Memory Instances
You can view multiple memory instances simultaneously. A Memory Data window appears for
each instance you double-click in the Memory List window. When you open more than one
window for the same memory, the name of the tab receives an numerical identifier after the
name, such as “(2)”.
Saving Memory Formats in a DO File
You can save all open memory instances and their formats (for example, address radix, data
radix, and so forth) by creating a DO file.
1. Select the Memory List window
2. Select File > Save Format
displays the Save Memory Format dialog box
3. Enter the file name in the “Save memory format” dialog box
By default it is named mem.do. The file will contain all open memory instances and their
formats.
To load it at a later time, select File > Load.
GUI Elements of the Memory List Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-65. Memory List Window Columns
Column Title
Description
Instance
Hierarchical name of the memory
Range
Memory range
Depth
Memory depth
Width
Word width
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Memory Data Window
Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:
Table 2-66. Memory List Popup Menu
Popup Menu Item
Description
View Contents
Opens a Memory Data window for the selected
memory.
Memory Declaration
Opens a Source window to the file and line number
where the memory is declared.
Compare Contents
Allows you to compare the selected memory against
another memory in the design or an external file.
Import Data Patterns
Allows you to import data patterns into the selected
memory through the Import Memory dialog box.
Export Data Patterns
Allows you to export data patterns from the selected
memory through the Export Memory dialog box.
Memory List Menu
This menu becomes available in the Main menu when the Memory List window is active.
Table 2-67. Memories Menu
Popup Menu Item
Description
View Contents
Refer to items in the Memory List Popup Menu
Memory Declaration
Compare Contents
Import Data Patterns
Export Data Patterns
Expand Packed Memories
Toggle the expansion of packed memories.
Identify Memories Within
Cells
Toggle the identification of memories within Verilog
cells.
Show VHDL String as
Memory
Toggle the identification of VHDL strings as
memories.
Memory Data Window
Use this window to view the contents of a memory.
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Memory Data Window
Accessing
Access the window by:
•
Double-clicking on a memory in the Memory List window.
Figure 2-69. Memory Data Window
Memory Data Window Tasks
This section describes tasks for using the Memory Data window.
Direct Address Navigation
You can navigate to any address location directly by editing the address in the address column.
Double-click on any address, type in the desired address, and hit Enter. The address display
scrolls to the specified location.
Splitting the Memory Contents Window
To split a memory contents window into two screens displaying the contents of a single
memory instance select Memory Data > Split Screen.
This allows you to view different address locations within the same memory instance
simultaneously.
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Memory Data Window
Figure 2-70. Split Screen View of Memory Contents
GUI Elements of the Memory Data Window
This section describes GUI elements specific to this Window.
Popup Menu
Right-click in the window to display the popup menu and select one of the following options:
Table 2-68. Memory Data Popup Menu — Address Pane
Popup Menu Item
Description
Goto
Allows you to go to a specific address
Split Screen
Splits the Memory Data window to allow you to
view different parts of the memory simultaneously.
Properties
Allows you to set various properties for the Memory
Data window.
Close Instance
Closes the active Memory Data window.
Close All
Closes all Memory Data windows.
Table 2-69. Memory Data Popup Menu — Data Pane
160
Popup Menu Item
Description
Edit
Allows you to edit the value of the selected data.
Change
Allows you to change data within the memory
through the use of the Change Memory dialog box.
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Message Viewer Window
Table 2-69. Memory Data Popup Menu — Data Pane
Popup Menu Item
Description
Import Data Patterns
Allows you to import data patterns into the selected
memory through the Import Memory dialog box.
Export Data Patterns
Allows you to export data patterns from the selected
memory through the Export Memory dialog box.
Split Screen
Refer to items in the Memory Data Popup Menu —
Address Pane
Properties
Close Instance
Close All
Memory Data Menu
This menu becomes available in the Main menu when the Memory Data window is active.
Table 2-70. Memory Data Menu
Popup Menu Item
Description
Memory Declaration
Opens a Source window to the file and line number
where the memory is declared.
Compare Contents
Allows you to compare the selected memory against
another memory in the design or an external file.
Import Data Patterns
Refer to items in the Memory Data Popup Menu —
Data Pane
Export Data Patterns
Expand Packed Memories
Toggle the expansion of packed memories.
Identify Memories Within
Cells
Toggle the identification of memories within Verilog
cells.
Show VHDL String as
Memory
Toggle the identification of VHDL strings as
memories.
Split Screen
Refer to items in the Memory Data Popup Menu —
Address Pane
Message Viewer Window
Use this window to easily access, organize, and analyze any Note, Warning, Error or other
elaboration and runtime messages written to the transcript during the simulation run.
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Message Viewer Window
Prerequisites
By default, the tool writes transcripted messages during elaboration and runtime to both the
transcript and the WLF file. By writing messages to the WLF file, the Message Viewer window
is able to organize the messages for your analysis during the current simulation as well as
during post simulation.
You can control what messages are available in the transcript, WLF file, or both with the
following switches:
•
displaymsgmode messages — User generated messages resulting from calls to Verilog
Display System Tasks and PLI/FLI print function calls. By default, these messages are
written only to the transcript, which means you cannot access them through the Message
Viewer window. In many cases, these user generated messages are intended to be output
as a group of transcripted messages, thus the default of transcript only. The Message
Viewer treats each message individually, therefore you could lose the context of these
grouped messages by modifying the view or sort order of the Message Viewer.
To change this default behavior you can use the -displaymsgmode argument to vsim.
The syntax is:
vsim -displaymsgmode {both | tran | wlf}
You can also use the displaymsgmode variable in the modelsim.ini file.
The message transcripting methods that are controlled by -displaymsgmode include:
•
o
Verilog Display System Tasks — $write, $display, $monitor, and $strobe. The
following also apply if they are sent to STDOUT: $fwrite, $fdisplay, $fmonitor, and
$fstrobe.
o
FLI Print Function Calls — mti_PrintFormatted and mti_PrintMessage.
o
PLI Print Function Calls — io_printf and vpi_printf.
msgmode messages — All elaboration and runtime messages not part of the
displaymsgmode messages. By default, these messages are written to the transcript and
the WLF file, which provides access to the messages through the Message Viewer
window. To change this default behavior you can use the -msgmode argument to vsim.
The syntax is:
vsim -msgmode {both | tran | wlf}
You can also use the msgmode variable in the modelsim.ini file.
Accessing
Access the window using either of the following:
•
162
Menu item: View > Message Viewer
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Message Viewer Window
•
Command: view msgviewer
Figure 2-71. Message Viewer Window
Message Viewer Window Tasks
Figure 2-72 and Table 2-71 provide an overview of the Message Viewer and several tasks you
can perform.
Figure 2-72. Message Viewer Window — Tasks
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Table 2-71. Message Viewer Tasks
Icon Task
Action
1
Display a detailed description of the
message.
right click the message text then
select View Verbose Message.
2
Open the source file and add a bookmark to double click the object name(s).
the location of the object(s).
3
Change the focus of the Structure and
Objects windows.
4
Open the source file and set a marker at the double click the file name.
line number.
double click the hierarchical
reference.
GUI Elements of the Message Viewer Window
This section describes the GUI elements specific to this window.
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Column Descriptions
Table 2-72. Message Viewer Window Columns
Column
Description
Assertion Expression
Assertion Name
Assertion Start Time
Category
Keyword for the various categories of messages:
• DISPLAY
• FLI
• PA
• PLI
• SDF
• TCHK
• VCD
• VITAL
• WLF
• MISC
•
Effective Time
File Info
Filename related to the cause of the message, and in
some cases the line number in parentheses.
Id
Message number
Messages
Organized tree-structure of the sorted messages, as well
as, when expanded, the text of the messages.
Objects
Object(s) related to the message, if any.
Process
Region
Hierarchical region related to the message, if any.
Severity
Message severity, such as Warning, Note or Error.
Time
Time of simulation when the message was issued.
Timing Check Kind
Information about timing checks
Verbosity
Verbosity information from $messagelog system tasks.
Popup Menu
Right-click anywhere in the window to open a popup menu that contains the following
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Message Viewer Window
selections:
Table 2-73. Message Viewer Window Popup Menu
Popup Menu Item
Description
View Source
Opens a Source window for the file, and in some cases
takes you to the associated line number.
View Verbose Message
Displays the Verbose Message dialog box containing
further details about the selected message.
Object Declaration
Opens and highlights the object declaration related to the
selected message.
Goto Wave
Opens the Wave window and places the cursor at the
simulation time for the selected message.
Display Reset
Resets the display of the window.
Display Options
Displays the Message Viewer Display Options dialog
box, which allows you to further control which messages
appear in the window.
Filter
Displays the Message Viewer Filter Dialog Box, which
allows you to create specialized rules for filtering the
Message Viewer.
Clear Filter
Restores the Message Viewer to an unfiltered view by
issuing the messages clearfilter command.
Expand/Collapse
Selected/All
Manipulates the expansion of the Messages column.
Related GUI Features
•
The Messages Bar in the Wave window provides indicators as to when a message
occurred.
Message Viewer Display Options Dialog Box
This dialog box allows you to control display options for the message viewer tab of the
transcript window.
•
•
166
Hierarchy Selection — This field allows you to control the appearance of message
hierarchy, if any.
o
Display with Hierarchy — enables or disables a hierarchical view of messages.
o
First by, Then by — specifies the organization order of the hierarchy, if enabled.
Time Range — Allows you to filter which messages appear according to simulation
time. The default is to display messages for the complete simulation time.
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Message Viewer Window
•
Displayed Objects — Allows you to filter which messages appear according to the
values in the Objects column. The default is to display all messages, regardless of the
values in the Objects column. The Objects in the list text entry box allows you to specify
filter strings, where each string must be on a new line.
Message Viewer Filter Dialog Box
This dialog box allows you to create filter rules that specify which messages should be shown in
the message viewer. It contains a series of dropdown and text entry boxes for creating the filter
rules and supports the addition of additional rule (rows) to create logical groupings.
From left to right, each filter rule is made up of the following:
•
Add and Remove buttons — either add a rule filter row below the current row or remove
that rule filter row.
•
Logic field — specifies a logical argument for combining adjacent rules. Your choices
are: AND, OR, NAND, and NOR. This field is greyed out for the first rule filter row.
•
Open Parenthesis field — controls rule groupings by specifying, if necessary, any open
parentheses. The up and down arrows increase or decrease the number of parentheses in
the field.
•
Column field — specifies that your filter value applies to a specific column of the
Message Viewer.
•
Inclusion field — specifies whether the Column field should or should not contain a
given value.
o
For text-based filter values your choices are: Contains, Doesn’t Contain, or Exact.
o
For numeric- and time-based filter values your choices are: ==, !=, <, <=, >, and >=.
•
Case Sensitivity field — specifies whether your filter rule should treat your filter value
as Case Sensitive or Case Insensitive. This field only applies to text-based filter values.
•
•
Filter Value field — specifies the filter value associated with your filter rule.
•
Closed Parenthesis field — controls rule groupings by specifying, if necessary, any
closed parentheses. The up and down arrows increase or decrease the number of
parentheses in the field.
Time Unit field — specifies the time unit. Your choices are: fs, ps, ns, us, ms. This field
only applies to the Time selection from the Column field.
Figure 2-73 shows an example where you want to show all messages, either errors or warnings,
that reference the 15th line of the file cells.v.
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Objects Window
Figure 2-73. Message Viewer Filter Dialog Box
When you select OK or Apply, the Message Viewer is updated to contain only those messages
that meet the criteria defined in the Message Viewer Filter dialog box.
Also, when selecting OK or Apply, the Transcript window will contain an echo of the messages
setfilter command, where the argument is a Tcl definition of the filter. You can then cut/paste
this command for reuse at another time.
Objects Window
Use this window to view the names and current values of declared data objects in the current
region, as selected in the Structure window. Data objects include:
•
•
•
•
•
•
•
•
signals
nets
registers
constants and variables not declared in a process
generics
parameters
transactions
SystemC member data variables
Accessing
Access the window using either of the following:
•
•
•
168
Menu item: View > Objects
Command: view objects
Wave window: View Objects Window Button
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Objects Window
Figure 2-74. Objects Window
Objects Window Tasks
This section describes tasks for using the Objects window.
Interacting with Other Windows
1. Click an entry in the window to highlight that object in the Dataflow, and Wave
windows.
2. Double-click an entry to highlights that object in a Source window
Setting Signal Radix
You can set the signal radix for a selected signal or signals in the Objects window as follows:
1. Click (LMB) a signal to select it or use Ctrl-Click Shift-Click to select a group of
signals.
2. Select Objects > Global Signal Radix from the menu bar; or right-click the selected
signal(s) and select Global Signal Radix from the popup menu.
This opens the Global Signal Radix dialog box (Figure 2-75), where you may select a
radix. This sets the radix for the selected signal(s) in the Objects window and every
other window where the signal appears.
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Figure 2-75. Setting the Global Signal Radix from the Objects Window
Finding Contents of the Objects Window
You can filter the contents of the Objects window by either the Name or Value columns.
1. Ctrl-F to display the Find box at the bottom of the window.
2. Click the “Search For” button and select the column to filter on.
3. Enter a string in the Find text box
4. Enter
Refer to the section “Using the Find and Filter Functions” for more information.
Filtering Contents of the Objects Window
You can filter the contents of the Objects window by the Name column.
1. Ctrl-F to display the Find box at the bottom of the window.
2. Ctrl-M to change to “Contains” mode.
3. Enter a string in the Contains text box
The filtering will occur as you begin typing. You can disable this feature with ctrl-T.
Filters are stored relative to the region selected in the Structure window. If you re-select a
region that had a filter applied, that filter is restored and the search bar changes color to indicate
that a filter has been applied. This allows you to apply different filters to different regions.
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Objects Window
The Search bar changes color when a filter is applied to the Objects window. You can change
the color with the preference variable PrefDefault(searchbarFiltered).
Refer to the section “Using the Find and Filter Functions” for more information.
Filtering by Signal Type
The View > Filter menu selection allows you to specify which signal types to display in the
Objects window. Multiple options can be selected.
Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:
Table 2-74. Objects Window Popup Menu
Popup Menu Item
Description
View Declaration
Opens a Source window to the declaration of the
object
View Memory Contents
Add
Adds the object to a specified window
Copy
Copies information about the object to the clipboard
Find
Opens the Find box
Insert Breakpoint
Adds a breakpoint for the selected object
Toggle Coverage
Control toggle coverage of the selected object
Force
Apply stimulus to the selected signal through the use
of the Force Selected Signal dialog box
NoForce
Remove the effect of any force command on the
selected signal.
Clock
Define clock signals through the use of the Define
Clock dialog box.
Change
Change the value of the selected variable through the
use of the Change Selected Variable dialog box.
Global Signal Radix
Sets radix of selected signal(s) in all windows
Create Wave
Allows you to create a waveform for the object
through the use of the Create Pattern Wizard.
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Viewing Toggle Coverage in the Objects Window
Toggle coverage data can be displayed in the Objects window in multiple columns, as shown in
Figure 2-76. Right-click the column title bar and select Show All Columns to make sure all
Toggle coverage columns are displayed. There is a column for each transition type.
Figure 2-76. Objects Window - Toggle Coverage
GUI Elements of the Objects Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-75. Toggle Coverage Columns in the Objects Window
172
Column name
Description
Name
the name of each object in the current region
Value
the current value of each object
Kind
the object type
Mode
the object mode (internal, in, out, and so forth.)
1H -> 0L
the number of times each object has transitioned from a 1 or a
High state to a 0 or a Low state
0L -> 1H
the number of times each object has transitioned from a 0 or a
Low state to 1 or a High state
0L -> Z
the number of times each object has transitioned from a 0 or a
Low state to a high impedance (Z) state
Z -> 0L
the number of times each object has transitioned from a high
impedance state to a 0 or a Low state
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Processes Window
Table 2-75. Toggle Coverage Columns in the Objects Window
Column name
Description
1H -> Z
the number of times each object has transitioned from a 1 or a
High state to a high impedance state
Z -> 1H
the number of times each object has transitioned from a high
impedance state to 1 or a High state
State Count
the number of values a state machine variable can have
State Hits
the number of state machine variable values that have been hit
State %
the current ration of State Hits to State Count
# Nodes
the number of scalar bits in each object
# Toggled
the number of nodes that have transitioned at least once. A
signal is considered toggled if and only if:
• it has 0- >1 and 1->0 transitions and NO Z transitions, or
• if there are ANY Z transitions, it must have ALL four of the
Z transitions.
Otherwise, the counts are place in % 01 or % Z columns.
For more specifics on what is considered “toggled”, see
“Understanding Toggle Counts”
% Toggled
the current ratio of the # Toggled to the # Nodes for each object
% 01
the percentage of 1H -> 0L and 0L -> 1H transitions that have
occurred (transitions in the first two columns)
% Full
the percentage of all transitions that have occurred (all six
columns)
%Z
the percentage of 0L -> Z, Z -> 0L, 1H -> Z, and Z -> 1H
transitions that have occurred (last four columns)
Processes Window
Use this window to view a list of HDL and SystemC processes in one of four viewing modes:
•
•
•
Active (default) — active processes in your simulation.
•
Hierarchy — a tree view of any SystemVerilog nested fork-joins.
In Region — process in the selected region.
Design — intended for primary navigation of ESL (Electronic System Level) designs
where processes are a foremost consideration.
In addition, the data in this window will change as you run your simulation and processes
change states or become inactive.
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Accessing
Access the window using either of the following:
•
•
Menu item: View > Process
Command: view process
Figure 2-77. Processes Window
Processes Window Tasks
This section describes tasks for using the Processes window.
Changing Your Viewing Mode
You can change the display to show all the processes in a region or in the entire design by doing
any one of the following:
•
•
•
Select Process > In Region, Design, Active, or Hierarchy.
Use the Process Toolbar
Right-click in the Process window and select In Region, Design, Active, or Hierarchy.
The view mode you select is persistent and is “remembered” when you exit the simulation. The
next time you bring up the tool, this window will initialize in the last view mode used.
Filtering Processes
You can control which processes are visible in the Processes window as follows:
1. Right-click in the Processes window and select Display Options.
2. In the Process Display Options dialog box select the Type or States you want to include
or exclude from the window.
3. OK
When you filter the window according to specific process states, the heading of the State
column changes to “State (filtered)” as shown in Figure 2-78.
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Figure 2-78. Column Heading Changes When States are Filtered
The default “No Implicit & Primitive” selection causes the Process window to display all
process types except implicit and primitive types. When you filter the display according to
specific process types, the heading of the Type column becomes “Type (filtered)”.
Once you select the options, data will update as the simulation runs and processes change their
states. When the In Region view mode is selected, data will update according to the region
selected in the Structure window.
Viewing the Full Path of the Process
By default, all processes are displayed without the full hierarchical context (path). You can
display processes with the full path by selecting Process > Show Full Path
Viewing Processes in Post-Processing Mode
This window also shows data in the post-processing (WLF view or Coverage view) mode. You
will need to log processes in the simulation mode to be able to view them in post-processing
mode.
In the post-processing mode, the default selection values will be same as the default values in
the live simulation mode.
Things to remember about the post-processing mode:
•
There are no active processes, so the Active view mode selection will not show
anything.
•
•
All processes will have same ‘Done’ state in the post-processing mode.
There is no order information, so the Order column will show ‘-‘ for all processes.
Setting a Ready Process as the Next Active Process
You can select any “Ready” process and set it to be the next Active process executed by the
simulator, ahead of any other queued processes. To do this, simply right-click any “Ready”
process and select Set Next Active from the popup context menu.
When you set a process as the next active process, you will see “(Next Active)” in the Order
column of that process (Figure 2-79).
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Figure 2-79. Next Active Process Displayed in Order Column
Creating Textual Process Report
You can create a textual report of all processes by using the process report command.
Figure 2-80. Sample Process Report in the Transcript Window
GUI Elements of the Processes Window
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-76. Processes Window Column Descriptions
176
Column Title
Description
Name
Name of the process.
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Table 2-76. Processes Window Column Descriptions
Column Title
Description
Order
Execution order of all processes in the
Active and Ready states. Refer to the
section “Process Order Description” for
more information.
Parent Path
Hierarchical parent pathname of the process
State
Process state. Refer to the section “Process
State Definitions” for more information.
Type
Process type, according to the language.
Refer to the section “Process Type
Definitions” for more information.
Process State Definitions
•
Idle — Indicates an inactive SystemC Method, or a process that has never been active.
The Idle state will occur only for SC processes or methods. It will never occur for HDL
processes.
•
Wait — Indicates the process is waiting for a wake up trigger (change in VHDL signal,
Verilog net, SystemC signal, or a time period).
•
Ready — Indicates the process is scheduled to be executed in current simulation phase
(or in active simulation queue) of current delta cycle.
•
•
Active – Indicates the process is currently active and being executed.
•
Done — Indicates the process has been terminated, and will never restart during current
simulation run.
Queued — Indicates the process is scheduled to be executed in current delta cycle, but
not in current simulation phase (or in active simulation queue).
Processes in the Idle and Wait states are distinguished as follows. Idle processes (except for
ScMethods) have never been executed before in the simulation, and therefore have never been
suspended. Idle processes will become Active, Ready, or Queued when a trigger occurs. A
process in the Wait state has been executed before but has been suspended, and is now waiting
for a trigger.
SystemC methods can have one of the four states: Active, Ready, Idle or Queued. When
ScMethods are not being executed (Active), or scheduled (Ready or Queued), they are inactive
(Idle). ScMethods execute in 0 time, whenever they get triggered. They are never suspended or
terminated.
Process Type Definitions
The Type column displays the process type according to the language used. It includes the
following types:
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Profiling Windows
•
•
•
•
•
•
•
•
•
•
Always
Assign
Final
Fork-Join (dynamic process like fork-join, sc_spawn, and so forth.)
Initial
Implicit (internal processes created by simulator like Implicit wires, and so forth.)
Primitive (UDP, Gates, and so forth.)
ScMethod
ScThread (SC Thread and SC CThread processes)
VHDL Process
Process Order Description
The Order column displays the execution order of all processes in the Active and Ready states
in the active kernel queue. Processes that are not in the Active or Ready states do not yet have
any order, in which case the column displays a dash (-). The Process window updates the
execution order automatically as simulation proceeds.
Profiling Windows
Use these five windows to view performance or memory profiling information about your
simulation.
•
Calltree — Displays information in a hierarchical form that indicates the call order
dependencies of functions or routines.
•
•
•
•
Design Units — Displays information aggregated for the different design units.
Ranked — Displays information for each function or instance.
Structural — Displays information aggregated for different instances.
Profile Details — Displays detailed profiling information based on selections in the
other Profile Windows
Prerequisites
You must have enabled performance or memory profiling. Refer to the chapter “Profiling
Performance and Memory Use” for more information.
Accessing
Access the Profile Calltree window using either of the following:
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Profiling Windows
•
•
Menu item: View > Profiling > Call Tree Profile
Command: view calltree
Figure 2-81. Profile Calltree Window
Access the Profile Design Unit window using either of the following:
•
•
Menu item: View > Profiling > Design Unit Profile
Command: view du
Figure 2-82. Profile Design Unit Window
Access the Profile Ranked window using either of the following:
•
•
Menu item: View > Profiling > Ranked Profile
Command: view ranked
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Figure 2-83. Profile Ranked Window
Access the Profile Structural window using either of the following:
•
•
Menu item: View > Profiling > Structural Profile
Command: view structural
Figure 2-84. Profile Structural Window
Access the Profile Structural window using either of the following:
•
•
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Menu item: View > Profiling > Profile Details
Command: view profiledetails
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Profiling Windows
Figure 2-85. Profile Details Window
GUI Elements of the Profile Windows
This section describes GUI elements specific to this Window.
Column Descriptions
Table 2-77. Profile Calltree Window Column Descriptions
Column Title
Description
%Parent
lists the ratio, as a percentage, of the samples collected during
the execution of a function or instance to the samples collected
in the parent function or instance.
(Not available in the Profile Ranked window.)
Count
(Only available in the Profile Design Unit window.)
In%
lists the ratio (as a percentage) of the total samples collected
during a function or instance.
In(raw)
lists the raw number of Profiler samples collected during a
function or instance.
MemIn
lists the amount of memory allocated to a function or instance.
MemIn(%)
lists the ratio (as a percentage) of the amount of memory
allocated to a function or instance to the total memory available.
MemUnder
lists the amount of memory allocated to a function, including all
support routines under that function; or, the amount of memory
allocated to an instance, including all instances beneath it in the
structural hierarchy.
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Table 2-77. Profile Calltree Window Column Descriptions
Column Title
Description
MemUnder(%)
lists the ratio (as a percentage) of the amount of memory
allocated to a function and all of its support routines to the total
memory available; or, the ratio of the amount of memory
allocated to an instance, including all instances beneath it in the
structural hierarchy, to the total memory available.
Name
lists the parts of the design for which profiling information was
captured.
sum(MemIn(%))
lists the ratio of the cumulative memory allocated.
(Only available in the Profile Ranked and Profile Design Unit
windows.)
sum(MemIn)
lists the cumulative memory allocated.
(Only available in the Profile Ranked and Profile Design Unit
windows.)
Under (raw)
lists the raw number of Profiler samples collected during the
execution of a function, including all support routines under that
function; or, the number of samples collected for an instance,
including all instances beneath it in the structural hierarchy.
Under(%)
lists the ratio (as a percentage) of the samples collected during
the execution of a function and all support routines under that
function to the total number of samples collected; or, the ratio of
the samples collected during an instance, including all instances
beneath it in the structural hierarchy, to the total number of
samples collected.
•
•
Redundant inverters — Displays redundant inverters.
•
Max hierarchy limit — specifies the maximum number of hierarchy levels the
fanin/fanout should go through before stopping. The default value is 32.
Max gate limit — Specifies the maximum number of gates the fanin/fanout should
go through before stopping. The default value is 1024.
Source Window
The Source window allows you to view and edit source files as well as set breakpoints, step
through design files, and view code coverage statistics.
By default, the Source window displays your source code with line numbers. You may also see
the following graphic elements:
•
182
Red line numbers — denote executable lines, where you can set a breakpoint
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Source Window
•
Blue arrow — denotes the currently active line or a process that you have selected in the
Processes Window
•
Red ball in line number column — denotes file-line breakpoints; gray ball denotes
breakpoints that are currently disabled
•
•
Blue flag in line number column — denotes line bookmarks
Language Templates pane — displays templates for writing code in VHDL, Verilog,
SystemC, Verilog 95, and SystemVerilog (Figure 2-86). See Using Language
Templates.
Figure 2-86. Source Window Showing Language Templates
•
Underlined text — denotes a hypertext link that jumps to a linked location, either in the
same file or to another Source window file. Display is toggled on and off by the Source
Navigation button.
•
Active Time Label — Displays the current Active Time or the Now (end of simulation)
time. This is the time used to control state values annotated in the window. (For details,
see Active Time Label.)
Also, you will see various code coverage indicator icons (see “Coverage Data in the Source
Window” for details):
•
Green check mark — denotes statements, branches (true), or expressions in a particular
line that have been covered.
•
Red X with no subscripts denotes that multiple kinds of coverage on the line are not
covered.
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•
Red X with subscripts — denotes a statement, branch (false or true), condition or
expression was not covered.
•
Green E with no subscripts— denotes a line of code to which active coverage exclusions
have been applied. Every item on line is excluded; none are hit.
•
Green E with subscripts — denotes a line of codes with various degrees of exclusion.
Opening Source Files
You can open source files using the File > Open command or by clicking the Open icon.
Alternatively, you can open source files by double-clicking objects in other windows. For
example, if you double-click an item in the Objects window or in the structure tab (sim tab), the
underlying source file for the object will open in the Source window and scroll to the line where
the object is defined.
From the command line you can use the edit command.
By default, files you open from within the design (such as when you double-click an object in
the Objects window) open in Read Only mode. To make the file editable, right-click in the
Source window and select (uncheck) Read Only. To change this default behavior, set the
PrefSource(ReadOnly) variable to 0. See Simulator GUI Preferences for details on setting
preference variables.
Displaying Multiple Source Files
By default each file you open or create is marked by a window tab, as shown in the graphic
below.
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Figure 2-87. Displaying Multiple Source Files
Dragging and Dropping Objects into the Wave and List
Windows
ModelSim allows you to drag and drop objects from the Source window to the Wave and List
windows. Double-click an object to highlight it, then drag the object to the Wave or List
window. To place a group of objects into the Wave and List windows, drag and drop any
section of highlighted code. When an object is dragged and dropped into the Wave window, the
add wave command will be reflected in the Transcript window.
Setting your Context by Navigating Source Files
When debugging your design from within the GUI, you can change your context while
analyzing your source files. Figure 2-88 shows the pop-up menu the tool displays after you
select then right-click an instance name in a source file.
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Figure 2-88. Setting Context from Source Files
This functionality allows you to easily navigate your design for debugging purposes by
remembering where you have been, similar to the functionality in most web browsers. The
navigation options in the pop-up menu function as follows:
•
Open Instance — changes your context to the instance you have selected within the
source file. This is not available if you have not placed your cursor in, or highlighted the
name of, an instance within your source file.
If any ambiguities exists, most likely due to generate statements, this option opens a
dialog box allowing you to choose from all available instances.
•
Ascend Env — changes your context to the file and line number in the parent region
where the current region is instantiated. This is not available if you are at the top-level of
your design.
•
Forward/Back — allows you to change to previously selected contexts. This is not
available if you have not changed your context.
The Open Instance option is essentially executing an environment command to change your
context, therefore any time you use this command manually at the command prompt, that
information is also saved for use with the Forward/Back options.
Highlighted Text in a Source Window
The Source window can display text that is highlighted as a result of various conditions or
operations, such as the following:
•
•
Double-clicking an error message in the transcript shown during compilation
Coverage-related operations.
In these cases, the relevant text in the source code is shown with a persistent highlighting. To
remove this highlighted display, choose More > Clear Highlights from the right-click popup
menu of the Source window. If the Source window is docked, you can also perform this action
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by selecting Source > More > Clear Highlights from the Main menu. If the window is
undocked, select Edit > Advanced > Clear Highlights.
Note
Clear Highlights does not affect text that you have selected with the mouse cursor.
Example
To produce a compile error that displays highlighted text in the Source window, do the
following:
1. Choose Compile > Compile Options
2. In the Compiler Options dialog box, click either the VHDL tab or the Verilog &
SystemVerilog tab.
3. Enable Show source lines with errors and click OK.
4. Open a design file and create a known compile error (such as changing the word “entity”
to “entry” or “module” to “nodule”).
5. Choose Compile > Compile and then complete the Compile Source Files dialog box to
finish compiling the file.
6. When the compile error appears in the Transcript window, double-click on it.
7. The source window is opened (if needed), and the text containing the error is
highlighted.
8. To remove the highlighting, choose Source > More > Clear Highlights.
Hyperlinked (Underlined) Text in a Source Window
The Source window supports hyperlinked navigation, providing links displayed as underlined
text. To turn hyperlinked text on or off in the Source window, do the following:
1. Click anywhere in the Source window. This enables the display of the Simulate toolbar
(see Table 2-31).
2. Click the Source Navigation button.
When you double-click on hyperlinked text, the selection jumps from the usage of an object to
its declaration. This provides the following operations:
•
•
•
Jump from the usage of a signal, parameter, macro, or a variable to its declaration.
Jump from a module declaration to its instantiation, and vice versa.
Navigate back and forth between visited source files.
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Coverage Data in the Source Window
The Source Window includes two columns for code coverage statistics – the Hits column and
the BC (Branch Coverage) column. These columns provide an immediate visual indication
about how your source code is executing. The code coverage indicator icons include check
marks, ‘X’s and ‘E’s. A description of each code coverage indicator icon is provided in
Table 2-78.
Figure 2-89. Coverage in Source Window
To see more information about any coverage item, click on the indicator icon, or in the Hits or
BC column for the line of interest. In the case of a multiple-line item, this would be last line of
the item. If the Coverage Details window is open, this brings up detailed coverage information
for that line. If the window is not open, a right click menu option is available to open it.
For example, when you select an expression in the Code Coverage Analysis’ Expression
Analysis window, and you click in the column of a line containing an expression, the associated
truth tables appear in the Coverage Details window. Each line in the truth table is one of the
possible combinations for the expression. The expression is considered to be covered (gets a
green check mark) if the entire truth table is covered.
When you hover over statements, conditions or branches in the Source window, the Hits and
BC columns display the coverage numbers for that line of code. For example, in Figure 2-89,
the blue highlighted line shows that the expression (b=b’b1) was hit 1 time. The value in the
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Hits column shows the total coverage for all items in the truth table (as shown in the Coverage
Details window when you click the specific line in the hits column).
In the BC count column, only the "true" counts are given, with the exception of the AllFalse
branch (if any). The AllFalse count is given next to the first "if" condition in an if-else tree that
does not contain a terminating catch-all "else" branch.
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Source Window Code Coverage Indicator Icons
Table 2-78. Source Window Code Coverage Indicators
Icon
Description/Indication
All statements, branches (true), conditions, or expressions
on a particular line have been executed
Multiple kinds of coverage on the line were not executed
True branch not executed (BC column)
False branch not executed (BC column)
Condition not executed (Hits column)
Expression not executed (Hits column)
Branch not executed (Hits column)
Statement not executed (Hits column)
Indicates a line of code to which active coverage exclusions
have been applied. Every item on the line is excluded; none
are hit.
Some excluded items are hit.
Some items are excluded, and all items not excluded are hit
Some items are excluded, and some items not excluded
have missing coverage
Auto exclusions have been applied to this line. Hover the
cursor over the EA and a tool tip balloon appears with the
reason for exclusion,
Coverage data presented in the Source window is either calculated “by file” or “by instance”, as
indicated just after the source file name. If coverage numbers are mismatched between Code
Coverage Analysis windows and the Source window, check to make sure that both are being
calculated the same — either “by file” or “by instance”.
To display only numbers in Hits and BC columns, select Tools > Code Coverage > Show
Coverage Numbers.
When the source window is active, you can skip to "missed lines" three ways:
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•
select Edit > Previous Coverage Miss and Edit > Next Coverage Miss from the menu
bar
•
•
click the Previous zero hits and Next zero hits icons on the toolbar
press Shift-Tab (previous miss) or Tab (next miss)
Controlling Data Displayed in a Source Window
The Tools > Code Coverage menu contains several commands for controlling coverage data
display in a Source window.
•
•
•
Hide/Show coverage data toggles the Hits column off and on.
•
Show coverage By Instance displays only the number of executions for the currently
selected instance in the Main window workspace.
Hide/Show branch coverage toggles the BC column off and on.
Hide/Show coverage numbers displays the number of executions in the Hits and BC
columns rather than check marks and Xs. When multiple statements occur on a single
line an ellipsis ("...") replaces the Hits number. In such cases, hover the cursor over each
statement to highlight it and display the number of executions for that statement.
Debugging with Source Annotation
With source annotation you can interactively debug your design by analyzing your source files
in addition to using the Wave and Signal windows. Source annotation displays simulation
values, including transitions, for each signal in your source file. Figure 2-90 shows an example
of source annotation, where the red values are added below the signals.
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Figure 2-90. Source Annotation Example
Turn on source annotation by selecting Source > Show Source Annotation or by right-clicking
a source file and selecting Show Source Annotation. Note that transitions are displayed only
for those signals that you have logged.
To analyze the values at a given time of the simulation you can either:
•
Show the signal values at the current simulation time. This is the default behavior. The
window automatically updates the values as you perform a run or a single-step action.
•
Show the signal values at current cursor position in the Wave window.
You can switch between these two settings by performing the following actions:
•
•
When Docked:
o
Source > Examine Now
o
Source > Examine Current Cursor
When Undocked:
o
Tools > Options > Examine Now
o
Tools > Options > Examine Current Cursor
You can highlight a specific signal in the Wave window by double-clicking on an annotation
value in the source file.
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Using Language Templates
ModelSim language templates help you write code. They are a collection of wizards, menus,
and dialogs that produce code for new designs, test benches, language constructs, logic blocks,
and so forth.
Note
The language templates are not intended to replace thorough knowledge of coding. They
are intended as an interactive reference for creating small sections of code. If you are
unfamiliar with a particular language, you should attend a training class or consult one of
the many available books.
To use the templates, either open an existing file, or select File > New > Source to create a new
file. Once the file is open, select Source > Show Language Templates if the Source window is
docked in the Main window; select View > Show Language Templates of the Source window
is undocked. This displays a pane that shows the available templates.
Figure 2-91. Language Templates
The templates that appear depend on the type of file you create. For example Module and
Primitive templates are available for Verilog files, and Entity and Architecture templates are
available for VHDL files.
Double-click an object in the list to open a wizard or to begin creating code. Some of the objects
bring up wizards while others insert code into your source file. The dialog below is part of the
wizard for creating a new design. Simply follow the directions in the wizards.
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Figure 2-92. Create New Design Wizard
Code inserted into your source contains a variety of highlighted fields. The example below
shows a module statement inserted from the Verilog template.
Figure 2-93. Inserting Module Statement from Verilog Language Template
Some of the fields, such as module_name in the example above, are to be replaced with names
you type. Other fields can be expanded by double-clicking and still others offer a context menu
of options when double-clicked. The example below shows the menu that appears when you
double-click module_item then select gate_instantiation.
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Figure 2-94. Language Template Context Menus
Setting File-Line Breakpoints with the GUI
You can easily set file-line breakpoints in your source code by clicking your mouse cursor in
the line number column of a Source window. Click the left mouse button in the line number
column next to a red line number and a red ball denoting a breakpoint will appear (Figure 2-95).
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Figure 2-95. Breakpoint in the Source Window
The breakpoint markers are toggles. Click once to create the breakpoint; click again to disable
or enable the breakpoint.
To delete the breakpoint completely, right click the red breakpoint marker, and select Remove
Breakpoint. Other options on the context menu include:
•
•
•
•
Disable Breakpoint — Deactivate the selected breakpoint.
Edit Breakpoint — Open the File Breakpoint dialog to change breakpoint arguments.
Edit All Breakpoints — Open the Modify Breakpoints dialog
Add/Remove Bookmark — Add or remove a file-line bookmark.
Adding File-Line Breakpoints with the bp Command
Use the bp command to add a file-line breakpoint from the VSIM> prompt.
For example:
bp top.vhd 147
sets a breakpoint in the source file top.vhd at line 147.
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Editing File-Line Breakpoints
To modify (or add) a breakpoint according to the line number in a source file, do any one of the
following:
•
•
•
Select Tools > Breakpoints from the Main menu.
Right-click a breakpoint and select Edit All Breakpoints from the popup menu.
Click the Edit Breakpoints toolbar button. See Simulate Toolbar.
This displays the Modify Breakpoints dialog box shown in Figure 2-96.
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Figure 2-96. Modifying Existing Breakpoints
The Modify Breakpoints dialog box provides a list of all breakpoints in the design. To modify a
breakpoint, do the following:
1. Select a file-line breakpoint from the list.
2. Click Modify, which opens the File Breakpoint dialog box shown in Figure 2-96.
3. Fill out any of the following fields to modify the selected breakpoint:
•
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Breakpoint Label — Designates a label for the breakpoint.
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Instance Name — The full pathname to an instance that sets a SystemC breakpoint
so it applies only to that specified instance.
•
Breakpoint Condition — One or more conditions that determine whether the
breakpoint is observed. If the condition is true, the simulation stops at the
breakpoint. If false, the simulation bypasses the breakpoint. A condition cannot refer
to a VHDL variable (only a signal). Refer to the tip below for more information on
proper syntax for breakpoints entered in the GUI.
•
Breakpoint Command — A string, enclosed in braces ({}) that specifies one or more
commands to be executed at the breakpoint. Use a semicolon (;) to separate multiple
commands.
Tip: All fields in the File Breakpoint dialog box, except the Breakpoint Condition field,
use the same syntax and format as the -inst switch and the command string of the bp
command. Do not enclose the expression entered in the Breakpoint Condition field in
quotation marks (“ ”). For more information on these command options, refer to the bp
command in the Questa SV/AFV Reference Manual.
Click OK to close the File Breakpoints dialog box.
1. Click OK to close the Modify Breakpoints dialog box.
Loading and Saving Breakpoints
The Modify Breakpoints dialog (Figure 2-96) includes Load and Save buttons that allow you to
load or save breakpoints.
Setting Conditional Breakpoints
In dynamic class-based code, an expression can be executed by more than one object or class
instance during the simulation of a design. You set a conditional breakpoint on the line in the
source file that defines the expression and specifies a condition of the expression or instance
you want to examine. You can write conditional breakpoints to evaluate an absolute expression
or a relative expression.
You can use the SystemVerilog keyword this when writing conditional breakpoints to refer to
properties, parameters or methods of an instance. The value of this changes every time the
expression is evaluated based on the properties of the current instance. Your context must be
within a local method of the same class when specifying the keyword this in the condition for a
breakpoint. Strings are not allowed.
The conditional breakpoint examples below refer to the following SystemVerilog source code
file source.sv:
Figure 2-97. Source Code for source.sv
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class Simple;
integer cnt;
integer id;
Simple next;
function new(int x);
id=x;
cnt=0
next=null
endfunction
task up;
cnt=cnt+1;
if (next) begin
next.up;
end
endtask
endclass
module test;
reg clk;
Simple a;
Simple b;
initial
begin
a = new(7);
b = new(5);
end
always @(posedge clk)
begin
a.up;
b.up;
a.up
end;
endmodule
Prerequisites
Compile and load your simulation.
Setting a Breakpoint For a Specific Instance
Enter the following on the command line:
bp simple.sv 13 -cond {this.id==7}
Results
The simulation breaks at line 13 of the simple.sv source file (Figure 2-97) the first time module
a hits the expression because the breakpoint is evaluating for an id of 7 (refer to line 27).
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Setting a Breakpoint For a Specified Value of Any Instance.
Enter the following on the command line:
bp simple.sv 13 -cond {this.cnt==8}
Results
The simulation evaluates the expression at line 13 in the simple.sv source file (Figure 2-97),
continuing the simulation run if the breakpoint evaluates to false. When an instance evaluates to
true the simulation stops, the source is opened and highlights line 13 with a blue arrow. The first
time cnt=8 evaluates to true, the simulation breaks for an instance of module Simple b. When
you resume the simulation, the expression evaluates to cnt=8 again, but this time for an instance
of module Simple a.
You can also set this breakpoint with the GUI:
1. Right-click on line 13 of the simple.sv source file.
2. Select Edit Breakpoint 13 from the drop menu.
3. Enter
this.cnt==8
in the Breakpoint Condition field of the Modify Breakpoint dialog box. (Refer to
Figure 2-96) Note that the file name and line number are automatically entered.
Checking Object Values and Descriptions
You can check the value or description of signals, indexes, and other objects in the Source
window.There are two quick methods to determine the value and description of an object:
•
Select an object, then right-click and select Examine or Describe from the context
menu.
•
Pause the cursor over an object to see an examine pop-up
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Figure 2-98. Source Window Description
You can select Source > Examine Now or Source > Examine Current Cursor to choose at
what simulation time the object is examined or described.
You can also invoke the examine and/or describe commands on the command line or in a
macro.
Marking Lines with Bookmarks
Source window bookmarks are blue flags that mark lines in a source file. These graphical icons
may ease navigation through a large source file by highlighting certain lines.
As noted above in the discussion about finding text in the Source window, you can insert
bookmarks on any line containing the text for which you are searching. The other method for
inserting bookmarks is to right-click a line number and select Add/Remove Bookmark. To
remove a bookmark, right-click the line number and select Add/Remove Bookmark again.
To remove all bookmarks from the Source window, select Source > Clear Bookmarks from
the menu bar when the Source window is active.
Performing Incremental Search for Specific Code
The Source window includes a Find function that allows you to do an incremental
search for specific code. To activate the Find bar (Figure 2-99) in the Source window
select Edit > Find from the Main menus or click the Find icon in the Main toolbar. For
more information see Using the Find and Filter Functions.
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Figure 2-99. Source Window with Find Toolbar
Customizing the Source Window
You can customize a variety of settings for Source windows. For example, you can change
fonts, spacing, colors, syntax highlighting, and so forth. To customize Source window settings,
select Tools > Edit Preferences. This opens the Preferences dialog. Select Source Windows
from the Window List.
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Figure 2-100. Preferences Dialog for Customizing Source Window
Select an item from the Category list and then edit the available properties on the right. Click
OK or Apply to accept the changes.
The changes will be active for the next Source window you open. The changes are saved
automatically when you quit ModelSim. See Setting Preference Variables from the GUI for
details.
Structure Window
Use this window to view the hierarchical structure of the active simulation.
The name of the structure window, as shown in the title bar or in the tab if grouped with other
windows, can vary:
•
•
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sim — This is the name shown for the Structure window for the active simulation.
dataset_name — The Structure window takes the name of any dataset you load through
the File > Datasets menu item or the dataset open command.
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Viewing the Structure Window
By default, the Structure window opens in a tab group with the Library windows after starting a
simulation. You can also open the Structure window with the “View Objects Window Button”.
The hierarchical view includes an entry for each object within the design. When you select an
object in a Structure window, it becomes the current region.
By default, the coverage statistics displayed in the columns within the Structure window are
recursive. You can select to view coverage statistics for local instances by deselecting Code
Coverage > Enable Recursive Coverage Sums. See “Coverage Aggregation in the Structure
Window” for details on coverage numbers.
The contents of several windows automatically update based on which object you select,
including the Source window, Objects window, Processes window, and Locals window.
Accessing
Access the window using any of the following:
•
•
•
Menu item: View > Structure
Command: view structure
Button: View Objects Window Button
Figure 2-101. Structure Window
Structure Window Tasks
This section describes tasks for using the Structure window.
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Display Source Code of a Structure Window Object
You can highlight the line of code that declares a given object in the following ways:
1. Double-click on an object — Opens the file in a new Source window, or activates the
file if it is already open.
2. Single-click on an object — Highlights the code if the file is already showing in an
active Source window.
Add Structure Window Objects to Other Windows
You can add objects from the Structure window to the Dataflow window, List window, Watch
window or Wave window in the following ways:
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•
•
•
Mouse — Drag and drop
Menu Selection — Add > To window
Toolbar — Add Selected to Window Button > Add to window
Command — add list, add wave, add dataflow
When you drag and drop objects from the Structure window to the Wave, Dataflow, or
Schematic windows, the add wave, add dataflow, and add schematic (respectively) commands
will be reflected in the Transcript window.
Finding Items in the Structure Window
To find items in the Structure window, press Ctrl-F on your keyboard with the Structure
window active. This opens the Find bar at the bottom of the window. As you type in the Find
field, a popup window opens to display a list of matches (Figure 2-102).
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Figure 2-102. Find Mode Popup Displays Matches
When you double-click any item in the match list that item is highlighted in the Structure
window and the popup is removed. The search can be canceled by clicking on the ‘x’ button or
by pressing the key on your keyboard.
With 'Search While Typing' enabled (the default) each keypress that changes the pattern restarts
the search immediately.
Refer to the Using the Find and Filter Functions section for details.
Filtering Structure Window Objects
You can control the types of information available in the Structure window through the View >
Filter menu items.
Processes — Implicit wire processes
Functions — Verilog and VHDL Functions
Packages — VHDL Packages
Tasks — Verilog Tasks
Statement — Verilog Statements
VlPackage — Verilog Packages
VlTypedef — Verilog Type Definitions
Capacity —
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The Search bar changes color when a filter is applied to the Structure window. You can change
the color with the preference variable PrefDefault(searchbarFiltered).
GUI Elements of the Structure Window
This section describes GUI elements specific to this Window. For a complete list of all columns
in the Structure window and a description of their contents, see Table 2-79.
Column Descriptions
The table below summarizes the columns in the Structure window. For a complete list of all
columns in the Structure window with a description of their contents, see Table 2-79.
Table 2-79. Columns in the Structure Window
Column name
Description
Design Unit
The name of the design unit
Design Unit Type
The type of design unit
Visibility
The +acc settings used for compilation/optimization of that design unit
Cover Options
The +cover settings used for compilation/simulation of that design unit
Total Coverage
The weighted average of all the coverage types (functional coverage and
code coverage) is recursive. Deselect Code Coverage > Enable
Recursive Coverage Sums to view results for the local instance. See
“Calculation of Total Coverage” for coverage statistics details.
Covergroup %
the number of hits from the total number of covergroups, as a percentage
Cover hits
the number of cover directives whose count values are greater than or
equal to the at_least value.
Cover misses
the number of cover directives whose count values are less than the
at_least value
Cover %
the number of hits from the total number of cover directives, as a
percentage
Cover graph
a bar chart displaying the Cover directive %; if the percentage is below
90%, the bar is red; 90% or more, the bar is green; you can change this
threshold percentage by editing the PrefCoverage(cutoff) preference
variable
Assertion hits
Assertion hits shows different counts based on whether the -assertdebug
is used:
• with -assertdebug argument to vsim command: number of assertions
whose pass count is greater than 0, and fail count is equal to 0.
• without -assertdebug: number of assertions whose fail count is equal
to 0.
Assertion misses
the number of assertions whose fail counts are greater than 0
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Table 2-79. Columns in the Structure Window
Column name
Description
Assertion %
the number of hits from the total number of assertions, as a percentage
Assertion graph
a bar chart displaying the Assertion %; if the percentage is below 90%,
the bar is red; 90% or more, the bar is green; you can change this
threshold percentage by editing the PrefCoverage(cutoff) preference
variable
Stmt count
the number of executable statements in each level and all levels under that
level
Stmts hit
the number of executable statements that were executed in each level and
all levels under that level
Stmts missed
the number of executable statements that were not executed in each level
and all levels under that level
Stmt %
the current ratio of Stmt hits to Stmt count
Stmt graph
a bar chart displaying the Stmt %; if the percentage is below 90%, the bar
is red; 90% or more, the bar is green; you can change this threshold
percentage by editing the PrefCoverage(cutoff) preference variable
Branch count
Files window — the number of executable branches in each file
Structure window — the number of executable branches in each level and
all levels under that level
Branches hit
the number of executable branches that have been executed in the current
simulation
Branches missed
the number of executable branches that were not executed in the current
simulation
Branch %
the current ratio of Branch hits to Branch count
Branch graph
a bar chart displaying the Branch %; if the percentage is below 90%, the
bar is red; 90% or more, the bar is green; you can change this threshold
percentage by editing the PrefCoverage(cutoff) preference variable
Condition rows
Files window — the number of conditions in each file
Structure window — the number of conditions in each level and all levels
under that level
Conditions hit
Files window — the number of times the conditions in a file have been
executed
Structure window — the number of times the conditions in a level, and all
levels under that level, have been executed
Conditions missed
Files window — the number of conditions in a file that were not executed
Structure window — the number of conditions in a level, and all levels
under that level, that were not executed
Condition %
the current ratio of Condition hits to Condition rows
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Table 2-79. Columns in the Structure Window
Column name
Description
Condition graph
a bar chart displaying the Condition %; if the percentage is below 90%,
the bar is red; 90% or more, the bar is green; you can change this
threshold percentage by editing the PrefCoverage(cutoff) preference
variable
Expression rows
the number of executable expressions in each level and all levels
subsumed under that level
Expressions hit
the number of times expressions in a level, and each level under that level,
have been executed
Expressions missed the number of executable expressions in a level, and all levels under that
level, that were not executed
Expression %
the current ratio of Expression hits to Expression rows
Expression graph
a bar chart displaying the Expression %; if the percentage is below 90%,
the bar is red; 90% or more, the bar is green; you can change this
threshold percentage by editing the PrefCoverage(cutoff) preference
variable
Toggle nodes
the number of points in each instance where the logic will transition from
one state to another
Toggles hit
the number of nodes in each instance that have transitioned at least once
Toggles missed
the number of nodes in each instance that have not transitioned at least
once
Toggle %
the current ratio of Toggle hits to Toggle nodes
Toggle graph
a bar chart displaying the Toggle %; if the percentage is below 90%, the
bar is red; 90% or more, the bar is green; you can change this threshold
percentage by editing the PrefCoverage(cutoff) preference variable
States
Files window — the number of states encountered in each file
Structure window — the number of states encountered in each level and
all levels subsumed under that level
States hit
Files window — the number of times the states were hit
Structure window — the number of times states in a level, and each level
under that level, have been hit
States missed
Files window — the number of states in a file that were not hit
Structure window — the number of states in a level, and all levels under
that level, that were not hit
State %
the current ratio of State hits to State rows
State graph
a bar chart displaying the State %; if the percentage is below 90%, the bar
is red; 90% or more, the bar is green; you can change this threshold
percentage by editing the PrefCoverage(cutoff) preference variable
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Table 2-79. Columns in the Structure Window
Column name
Description
Transitions
Files window — the number of transitions encountered in each file
Structure window — the number of states encountered in each level and
all levels subsumed under that level
Transitions hit
Files window — the number of times the transitions were hit
Structure window — the number of times transitions in a level, and each
level under that level, have been hit
Transitions missed
Files window — the number of transitions in a file that were not hit
Structure window — the number of transitions in a level, and all levels
under that level, that were not hit
Transition %
the current ratio of Transition hits to Transition rows
Transition graph
a bar chart displaying the State %; if the percentage is below 90%, the bar
is red; 90% or more, the bar is green; you can change this threshold
percentage by editing the PrefCoverage(cutoff) preference variable
FEC Condition
rows
Files window — the number of FEC conditions in each file
Structure window — the number of conditions in each level and all levels
under that level
FEC Conditions hit Files window — the number of times the FEC conditions in a file have
been executed
Structure window — the number of times the conditions in a level, and all
levels under that level, have been executed
FEC Conditions
missed
Files window — the number of FEC conditions in a file that were not
executed
Structure window — the number of conditions in a level, and all levels
under that level, that were not executed
FEC Condition %
the current ratio of FEC Condition hits to FEC Condition rows
FEC Condition
graph
a bar chart displaying the FEC Condition %; if the percentage is below
90%, the bar is red; 90% or more, the bar is green; you can change this
threshold percentage by editing the PrefCoverage(cutoff) preference
variable
FEC Expression
rows
Files window — the number of executable expressions in each file
Structure window — the number of executable expressions in each level
and all levels subsumed under that level
FEC Expressions
hit
Files window — the number of times expressions in a file have been
executed
Structure window — the number of times expressions in a level, and each
level under that level, have been executed
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Structure Window
Table 2-79. Columns in the Structure Window
Column name
Description
FEC Expressions
missed
Files window — the number of executable expressions in a file that were
not executed
Structure window — the number of executable expressions in a level, and
all levels under that level, that were not executed
FEC Expression % the current ratio of FEC Expression hits to FEC Expression rows
FEC Expression
graph
a bar chart displaying the FEC Expression %; if the percentage is below
90%, the bar is red; 90% or more, the bar is green; you can change this
threshold percentage by editing the PrefCoverage(cutoff) preference
variable
Code Coverage in the Structure Window
The Structure window displays code coverage information in the Structure (sim) window for
any datasets being simulated. When coverage is invoked, several columns for displaying
coverage data are added to these windows. You can toggle columns on/off by right-clicking on
a column name and selecting from the context menu that appears. Figure 2-103 shows a portion
of the Structure window with code coverage data displayed.
Figure 2-103. Code Coverage Data in the Structure Window
You can sort code coverage information for any column by clicking the column heading.
Clicking the column heading again will reverse the order.
Coverage information in the Structure window is dynamically linked to the Code Coverage
Analysis windows. Click the left mouse button on any file in the Files window to display that
file’s un-executed statements, branches, conditions, expressions, and toggles in the Code
Coverage Analysis windows. Lines from the selected file that are excluded from coverage
statistics are also displayed in the Code Coverage Analysis windows.
For details on how the Total Coverage column statistics are calculated, see “Calculation of
Total Coverage”.
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Verification Management Browser Window
Verification Management Browser Window
The Verification Management Browser window displays summary information for original test
results in UCDBs, ranking files, and merged test results in a UCDB. It has a feature for
customizing and saving the organization of the tabs. It also supports features for re-running
tests, generating HTML reports from test results, and executing merges and test ranking.
For details on how the Total Coverage column statistics are calculated, see “Calculation of
Total Coverage”.
Accessing
Access the window using either of the following:
•
•
Select View > Verification Management> Browser
Execute the view command, as shown:
view testbrowser
Figure 2-104 shows the Verification Browser window using the Code Coverage column view
setting, refer to Controlling the Verification Browser Columns for more information.
Figure 2-104. Browser Tab
Verification Browser Icons
The Browser uses the following icons to identify the type of file loaded into the browser:
Table 2-80. Verification Browser Icons
Browser Icon
Description
Indicates the file is an unmerged UCDB file. A
“P” notation in the upper right hand corner of the
icon indicates that a Verification Plan is included
in UCDB.
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Table 2-80. Verification Browser Icons
Browser Icon
Description
Indicates the file is a rank file.
Indicates the file is a merged UCDB file.
Notations on right hand side mean the following:
• P - verification (test) plan is included in
merged UCDB
• 1 - Totals merge
• 2 - Test-associated merge
See “Test-Associated Merge versus Totals Merge
Algorithm” for more information.
Controlling the Verification Browser Columns
You can customize the appearance of the Browser using either of the following methods:
•
Use the “Column Layout Toolbar” to select from several pre-defined column
arrangements.
•
Right-click in the column headings to display a list of all column headings which allows
you to toggle the columns on or off.
Saving Verification Browser Column and Filter Settings
Save your column layout and any filter settings to an external file (browser_column_layout.do)
by selecting File > Export > Column Layout while the window is active. You can reload these
settings with the do command. This export does not retain changes to column width.
GUI Elements of the Verification Browser Window
This section provides an overview of the GUI elements specific to this window.
Toolbar
The Browser allows access to the Column Layout Toolbar and the Help Toolbar.
Menu Items
The following menu items are related to the Verification Management Browser window:
214
•
Add File — adds UCDB (.ucdb) and ranking results (.rank) files to the browser. Refer
to the section Viewing Test Data in the GUI for more information.
•
Remove File — removes an entry from this window (From Browser Only), as well as
from the file system (Browser and File System).
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•
Remove Non-Contributing Test(s) — operates only on ranked (.rank) files; menu
selection is grayed out unless a ranked file is selected. Removes any tests that do not
contribute toward the coverage.
•
Merge — displays the Merge Files Dialog Box, which allows you to merge any selected
UCDB files. Refer to the section Merging Coverage Test Data for more information.
•
Rank — displays the Rank Files Dialog Box, which allows you to create a ranking
results file based on the selected UCDB files. Refer to the section Ranking Coverage
Test Data for more information.
•
HTML Report — displays the HTML Coverage Report Dialog Box, which allows you
to view your coverage statistics in an HTML viewer.
•
Command Execution — allows you to re-run simulations based on the resultant UCDB
file based on the simulation settings to create the file. You can rerun any test whose test
record appears in an individual .ucdb file, a merged .ucdb file, or ranking results (.rank)
file. See Test Attribute Records in the UCDB for more information on test records.
•
o
Setup — Displays the Command Setup Dialog box, which allows you to create and
edit your own setups which can be used to control the execution of commands.
“Restore All Defaults” removes any changes you make to the list of setups and the
associated commands.
o
Execute on all — Executes the specified command(s) on all .ucdb files in the
browser (through TestReRun), even those used in merged .ucdb files and .rank
files.
o
Execute on selected — Executes the specified command(s) on the selected .ucdb
file(s) through TestReRun.
Filter — either opens the Filter Setup Dialog Box, or applies desired filter setups.
•
Setup — opens the Filter Setup dialog that allows you to save and edit filters to
apply to the data.
•
•
•
Create button — opens the Create Filter dialog which allows you to select
filtering criteria, and select the tests for application of the specified filters. When
you enter a Filter Name, and select “Add”, the Add/Modify Selection Criteria
dialog box is displayed, where you can select the actual criteria to filter.
Apply — applies the selected filter(s) on the data.
Generate Vrun Config — generates Verification Run Management configuration file
(.rmdb) including selected tests or all tests in the directory. Selecting either option
brings up a dialog to enter the name to be used for the .rmdb file.
o
Save Selected Tests — Saves selected tests into a .rmdb file to be executed by vrun
command.
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o
Save All Tests — Saves all tests in the directory into a .rmdb file to be executed by
vrun command.
•
Show Full Path — toggles whether the FileName column shows only the filename or
its full path.
•
Set Precision — allows you to control the decimal point precision of the data in the
Verification Browser window.
•
Configure Colorization — opens the Colorization Threshold dialog box which allows
you to off the colorization of coverage results displayed in the “Coverage” column, as
well as set the low and high threshold coverage values for highlighting coverage values:
•
•
•
•
•
o
< low threshold — RED
o
> high threshold — GREEN
o
> low and < high — YELLOW
Expand / Collapse Selected — Expand or collapse selected UCDBs.
Expand / Collapse All — Expand or collapse all UCDBs.
Save Format — saves the current contents of the browser to a .do file.
Load — loads a .do file that contains a previously saved browser layout.
Invoke CoverageView Mode — opens the selected UCDB in viewcov mode, creating a
new dataset. Refer to the section Invoking Coverage View Mode for more information.
Transcript Window
The Transcript window maintains a running history of commands that are invoked and
messages that occur as you work with ModelSim. When a simulation is running, the Transcript
displays a VSIM prompt, allowing you to enter command-line commands from within the
graphic interface.
You can scroll backward and forward through the current work history by using the vertical
scrollbar. You can also use arrow keys to recall previous commands, or copy and paste using
the mouse within the window (see Main and Source Window Mouse and Keyboard Shortcuts
for details).
Displaying the Transcript Window
The Transcript window is always open in the Main window and cannot be closed.
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Transcript Window
Viewing Data in the Transcript Window
The Transcript tab contains the command line interface, identified by the ModelSim prompt,
and the simulation interface, identified by the VSIM prompt.
Transcript Window Tasks
This section introduces you to several tasks you can perform, related to the Transcript tab.
Saving the Transcript File
Variable settings determine the filename used for saving the transcript. If either PrefMain(file)
in the .modelsim file or TranscriptFile in the modelsim.ini file is set, then the transcript output
is logged to the specified file. By default the TranscriptFile variable in modelsim.ini is set to
transcript. If either variable is set, the transcript contents are always saved and no explicit
saving is necessary.
If you would like to save an additional copy of the transcript with a different filename, click in
the Transcript window and then select File > Save As, or File > Save. The initial save must be
made with the Save As selection, which stores the filename in the Tcl variable
PrefMain(saveFile). Subsequent saves can be made with the Save selection. Since no
automatic saves are performed for this file, it is written only when you invoke a Save command.
The file is written to the specified directory and records the contents of the transcript at the time
of the save.
Refer to Creating a Transcript File for more information about creating, locating, and saving a
transcript file.
Saving a Transcript File as a Macro (DO file)
1. Open a saved transcript file in a text editor.
2. Remove all commented lines leaving only the lines with commands.
3. Save the file as .do.
Refer to the do command for information about executing a DO file.
Changing the Number of Lines Saved in the Transcript Window
By default, the Transcript window retains the last 5000 lines of output from the transcript. You
can change this default by selecting Transcript > Saved Lines. Setting this variable to 0
instructs the tool to retain all lines of the transcript.
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Disabling Creation of the Transcript File
You can disable the creation of the transcript file by using the following ModelSim command
immediately after ModelSim starts:
transcript file ""
Performing an Incremental Search
The Transcript tab includes a Find function (Figure 2-105) that allows you to do an incremental
search for specific text. To activate the Find bar select Edit > Find from the menus or click the
Find icon in the toolbar. For more information see Using the Find and Filter Functions.
Figure 2-105. Transcript Window with Find Toolbar
GUI Elements of the Transcript Window
This section describes the GUI elements specific to the Transcript window.
Automatic Command Help
When you start typing a command at the prompt, a dropdown box appears which lists the
available commands matching what has been typed so far. You may use the Up and Down
arrow keys or the mouse to select the desired command. When a unique command has been
entered, the command usage is presented in the drop down box.
You can toggle this feature on and off by selecting Help > Command Completion.
Transcript Menu Items
218
•
Adjust Font Scaling — Displays the Adjust Scaling dialog box, which allows you to
adjust how fonts appear for your display environment. Directions are available in the
dialog box.
•
Transcript File — Allows you to change the default name used when saving the
transcript file. The saved transcript file will contain all the text in the current transcript
file.
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Watch Window
•
Command History — Allows you to change the default name used when saving
command history information. This file is saved at the same time as the transcript file.
•
Save File — Allows you to change the default name used when selecting File > Save
As.
•
Saved Lines — Allows you to change how many lines of text are saved in the transcript
window. Setting this value to zero (0) saves all lines.
•
Line Prefix — Allows you to change the character(s) that precedes the lines in the
transcript.
•
Update Rate — Allows you to change the length of time (in ms) between transcript
refreshes.
•
ModelSim Prompt — Allows you to change the string used for the command line
prompt.
•
•
VSIM Prompt — Allows you to change the string used for the simulation prompt.
Paused Prompt — Allows you to change the string used for when the simulation is
paused.
Transcript Toolbar Items
When undocked, the Transcript window allows access to the following toolbars:
•
•
•
Standard Toolbar
Help Toolbar
Help Toolbar
Watch Window
The Watch window shows values for signals and variables at the current simulation time, allows
you to explore the hierarchy of object oriented designs. Unlike the Objects or Locals windows,
the Watch window allows you to view any signal or variable in the design regardless of the
current context. You can view the following objects:
•
•
•
•
VHDL objects — signals, aliases, generics, constants, and variables
Verilog objects — nets, registers, variables, named events, and module parameters
SystemC objects — primitive channels and ports
Virtual objects — virtual signals and virtual functions
The address of an object, if one can be obtained, is displayed in the title in parentheses as shown
in Figure 2-106.
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Watch Window
Items displayed in red are values that have changed during the previous Run command. You can
change the radix of displayed values by selecting an item, right-clicking to open a popup
context menu, then selecting Properties.
Figure 2-106. Watch Window
Items are displayed in a scrollable, hierarchical list, such as in Figure 2-107 where extended
SystemVerilog classes hierarchically display their super members.
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Figure 2-107. Scrollable Hierarchical Display
Two Ref handles that refer to the same object will point to the same Watch window box, even if
the name used to reach the object is different. This means circular references will be draw as
circular.
Selecting a line item in the window adds the item’s full name to the global selection. This
allows you to paste the full name in the Transcript (by simply clicking the middle mouse button)
or other external application that accepts text from the global selection.
Adding Objects to the Watch Window
To add objects to the Watch window, drag -and-drop objects from the Structure window or from
any of the following windows: List, Locals, Objects, Source, and Wave. You can also use the
“Add Selected to Window Button”. You can also use the add watch command.
Expanding Objects to Show Individual Bits
If you add an array or record to the window, you can view individual bit values by doubleclicking the array or record. As shown in Figure 2-108, /ram_tb/spram4/mem has been
expanded to show all the individual bit values. Notice the arrow that "ties" the array to the
individual bit display.
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Figure 2-108. Expanded Array
Grouping and Ungrouping Objects
You can group objects in the window so they display and move together. Select the objects,
then right click one of the objects and choose Group.
In Figure 2-109, two different sets of objects have been grouped together.
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Figure 2-109. Grouping Objects in the Watch Window
To ungroup them, right-click the group and select Ungroup.
Saving and Reloading Format Files
You can save a format file (a DO file, actually) that will redraw the contents of the window.
Right-click anywhere in the window and select Save Format. The default name of the format
file is watch.do.
Once you have saved the file, you can reload it by right-clicking and selecting Load Format.
Wave Window
The Wave window, like the List window, allows you to view the results of your simulation. In
the Wave window, however, you can see the results as waveforms and their values.
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Figure 2-110. Wave Window
Add Objects to the Wave Window
You can add objects to the Wave window from the Dataflow Window, List Window, Objects
Window, or Processes Window in the following ways:
•
•
Mouse — Drag and drop.
•
Toolbar — Click-and-hold the “Add Selected to Window Button” to specify where
selected signals are placed: at the top of the Pathnames Pane, at the end of the
Pathnames Pane, or above the currently selected signal in the Wave Window.
Mouse — Click the middle mouse button when the cursor is over an object or group of
objects. The specified object(s) are added to the Wave Window.
When you drag and drop objects into the Wave window, the add wave command is reflected in
the Transcript window.
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Wave Window
Wave Window Panes
The Wave window is divided into a number of window panes. All window panes in the Wave
window can be resized by clicking and dragging the bar between any two panes.
Pathname Pane
The pathname pane displays signal pathnames. Signals can be displayed with full pathnames, as
shown here, or with any number of path elements. You can increase the size of the pane by
clicking and dragging on the right border. The selected signal is highlighted.
The white bar along the left margin indicates the selected dataset (see Splitting Wave Window
Panes).
Figure 2-111. Pathnames Pane
Values Pane
The values pane displays the values of the displayed signals.
The radix for each signal can be symbolic, binary, octal, decimal, unsigned, hexadecimal,
ASCII, or default. The default radix for all signals can be set by selecting Simulate > Runtime
Options.
Note
When the symbolic radix is chosen for SystemVerilog reg and integer types, the values
are treated as binary. When the symbolic radix is chosen for SystemVerilog bit and int
types, the values are considered to be decimal.
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Wave Window
To change the radix for just the selected signal or signals, select Wave > Format > Radix >
Global Signal Radix from the menus, or right-click the selected signal(s) and select Radix >
Global Signal Radix from the popup menu. This opens the Global Signal Radix dialog
(Figure 2-112), where you may select a radix. This sets the radix for the selected signal(s) in the
Wave window and every other window where the signal appears.
Figure 2-112. Setting the Global Signal Radix from the Wave Window
The data in this pane is similar to that shown in the Objects Window, except that the values
change dynamically whenever a cursor in the waveform pane is moved.
Figure 2-113. Values Pane
Waveform Pane
Figure 2-114 shows waveform pane, which displays waveforms that correspond to the
displayed signal pathnames. It can also display as many as 20 user-defined cursors. Signal
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values can be displayed in analog step, analog interpolated, analog backstep, literal, logic, and
event formats. You can set the format of each signal individually by right-clicking the signal in
the pathname or values panes and choosing Format from the popup menu. The default format is
Logic.
If you place your mouse pointer on a signal in the waveform pane, a popup menu displays with
information about the signal. You can toggle this popup on and off in the Wave Window
Properties dialog box.
Dashed signal lines in the waveform pane indicate weak or ambiguous strengths of Verilog
states. See Verilog States in the Mixed-Language Simulation chapter.
Figure 2-114. Waveform Pane
Analog Sidebar Toolbox
When the waveform pane contains an analog waveform, you can hover your mouse pointer over
the left edge of the waveform to display the Analog Sidebar toolbox (see Figure 2-115). This
toolbox shows a group of icons that gives you quick access to actions you can perform on the
waveform display, as described in Table 2-81.
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Figure 2-115. Analog Sidebar Toolbox
Table 2-81. Analog Sidebar Icons
Icon
228
Action
Description
Open Wave Properties
Opens the Format tab of the Wave Properties
dialog box, with the Analog format already
selected. This dialog box duplicates the Wave
Analog dialog box displayed by choosing
Format > Format... > Analog (custom)
from the main menu.
Toggle Row Height
Changes the height of the row that contains the
analog waveform. Toggles the height between
the Min and Max values (in pixels) you specified
in the Open Wave Properties dialog box under
Analog Display.
Rescale to fit Y data
Changes the waveform height so that it fits topto-bottom within the current height of the row.
Show menu of other actions
Displays
• View Min Y
• View Max Y
• Overlay Above
• Overlay Below
• Colorize All
• Colorize Selected
Drag to resize waveform height
Creates an up/down dragging arrow that you can
use to temporarily change the height of the row
containing the analog waveform.
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Wave Window
Cursor Pane
Figure 2-116 shows the Cursor Pane, which displays cursor names, cursor values and the cursor
locations on the timeline. You can link cursors so that they move across the timeline together.
See Linking Cursors in the Waveform Analysis chapter.
Figure 2-116. Cursor Pane
On the left side of this pane is a group of icons called the Cursor and Timeline Toolbox (see
Figure 2-117). This toolbox gives you quick access to cursor and timeline features and
configurations. See Measuring Time with Cursors in the Wave Window for more information.
Cursor and Timeline Toolbox
The Cursor and Timeline Toolbox displays several icons that give you quick access to cursor
and timeline features.
Figure 2-117. Toolbox for Cursors and Timeline
The action for each toolbox icon is shown in Table 2-82.
Table 2-82. Icons and Actions
Icon
Action
Toggle leaf name <-> full names
Edit grid and timeline properties
Insert cursor
Toggle lock on cursor to prevent it from moving
Edit this cursor
Remove this cursor
The Toggle leaf names <-> full names icon allows you to switch from displaying full
pathnames (the default) in the Pathnames Pane to displaying leaf or short names. You can also
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control the number of path elements in the Wave Window Preferences dialog. Refer to
Hiding/Showing Path Hierarchy.
The Edit grid and timeline properties icon opens the Wave Window Properties dialog to the
Grid & Timeline tab (Figure 2-118).
Figure 2-118. Editing Grid and Timeline Properties
The Grid Configuration selections allow you to set grid offset, minimum grid spacing, and grid
period; or you can reset the grid configuration to default values.
The Timeline Configuration selections give you a user-definable time scale. You can display
simulation time on the timeline or a clock cycle count. The time value is scaled appropriately
for the selected unit.
By default, the timeline will display time delta between any two adjacent cursors. By clicking
the Show frequency in cursor delta box, you can display the cursor delta as a frequency
instead.
Adding Cursors to the Wave Window
You can add cursors when the Wave window is active by:
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•
•
•
•
clicking the Insert Cursor icon.
choosing Add > Wave > Cursor from the menu bar
pressing the “A” key while the mouse cursor is in the cursor pane.
right clicking in the cursor pane at the time you want place a cursor, then selecting New
Cursor.
Each added cursor is given a default cursor name (Cursor 2, Cursor 3, and so forth.) which you
can be change by right-clicking the cursor name, then typing in a new name, or by clicking the
Edit this cursor icon. The Edit this cursor icon opens the Cursor Properties dialog box
(Figure 2-119), where you assign a cursor name and time. You can also lock the cursor to the
specified time.
Figure 2-119. Cursor Properties Dialog
Messages Bar
The messages bar, located at the top of the Wave window, contains indicators pointing to the
times at which a message was output from the simulator.
Figure 2-120. Wave Window - Message Bar
The message indicators (the down-pointing arrows) are color-coded as follows:
•
•
•
•
Red — Indicates an error.
Yellow — Indicates a warning.
Green — Indicates a note.
Grey — Indicates any other type of message.
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You can use the Message bar in the following ways.
•
Move the cursor to the next message — You can do this in two ways:
o
Click on the word “Messages” in the message bar to cycle the cursor to the next
message after the current cursor location.
o
Click anywhere in the message bar, then use Tab or Shift+Tab to cycle the cursor
between error messages either forward or backward, respectively.
•
Display the Message Viewer Window — Double-click anywhere amongst the message
indicators.
•
Display, in the Message Viewer window, the message entry related to a specific
indicator — Double-click on any message indicator.
This function only works if you are using the Message Viewer in flat mode. To display
your messages in flat mode:
a. Right-click in the Message Viewer and select Display Options
b. In the Message Viewer Display Options dialog box, deselect Display with
Hierarchy.
View Objects Window Button
This button opens the Objects window with a single click. However, if you click-and-hold the
button you can access additional options via a dropdown menu, as shown in Figure 2-121
Figure 2-121. View Objects Window Dropdown Menu
Objects You Can View in the Wave Window
The following types of objects can be viewed in the Wave window
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•
VHDL objects (indicated by a dark blue diamond) — signals, aliases, process variables,
and shared variables
•
Verilog objects (indicated by a light blue diamond) — nets, registers, variables, and
named events
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Wave Window
The GUI displays inout variables of a clocking block separately, where the output of the
inout variable is appended with “__o”, for example you would see following two
objects:
clock1.c1
clock1.c1__o
/input portion of the inout c1
/output portion of the inout c1
This display technique also applies to the Objects window
•
•
Verilog transactions (indicated by a blue four point star) — see for more information
•
Virtual objects (indicated by an orange diamond) — virtual signals, buses, and
functions, see; Virtual Objects for more information
•
Comparison objects (indicated by a yellow triangle) — comparison region and
comparison signals; see Waveform Compare for more information
SystemC objects
(indicated by a green diamond) — primitive channels and ports
(indicated by a green four point star) — transaction streams and their element
The data in the object values pane is very similar to the Objects window, except that the values
change dynamically whenever a cursor in the waveform pane is moved.
At the bottom of the waveform pane you can see a time line, tick marks, and the time value of
each cursor’s position. As you click and drag to move a cursor, the time value at the cursor
location is updated at the bottom of the cursor.
You can resize the window panes by clicking on the bar between them and dragging the bar to a
new location.
Waveform and signal-name formatting are easily changed via the Format menu. You can reuse
any formatting changes you make by saving a Wave window format file (see Saving the
Window Format).
Wave Window Toolbar
The Wave window (in the undocked Wave window) gives you quick access to the following
toolbars:
•
•
•
•
•
•
Standard Toolbar
Compile Toolbar
Simulate Toolbar
Wave Cursor Toolbar
Wave Edit Toolbar
Wave Toolbar
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•
•
•
234
Wave Compare Toolbar
Zoom Toolbar
Wave Expand Time Toolbar
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Chapter 3
Protecting Your Source Code
As today’s IC designs increase in complexity, silicon manufacturers are leveraging third-party
intellectual property (IP) to maintain or shorten design cycle times. This third-party IP is often
sourced from several IP authors, each of whom may require different levels of protection in
EDA tool flows. The number of protection/encryption schemes developed by IP authors has
complicated the use of protected IP in design flows made up of tools from different EDA
providers.
ModelSim’s encryption solution allows IP authors to deliver encrypted IP code for a wide range
of EDA tools and design flows. You can, for example, make module ports, parameters, and
specify blocks publicly visible while keeping the implementation private.
ModelSim supports VHDL, Verilog, and SystemVerilog IP code encryption by means of
protected encryption envelopes. VHDL encryption is defined by the IEEE Std 1076-2008,
section 24.1 (titled “Protect tool directives”) and Annex H, section H.3 (titled “Digital
envelopes”). Verilog/SystemVerilog encryption is defined by the IEEE Std 1364-2005, section
28 (titled “Protected envelopes”) and Annex H, section H.3 (titled “Digital envelopes”). The
protected envelopes usage model, as presented in Annex H section H.3 of both standards, is the
recommended methodology for users of VHDL’s `protect and Verilog's `pragma protect
compiler directives. We recommend that you obtain these specifications for reference.
In addition, Questa supports the recommendations from the IEEE P1735 working group for
encryption interoperability between different encryption and decryption tools. The current
recommendations are denoted as “version 1” by P1735. They address use model, algorithm
choices, conventions, and minor corrections to the HDL standards to achieve useful
interoperability.
ModelSim also supports encryption using the vcom/vlog -nodebug command.
Creating Encryption Envelopes
Encryption envelopes define a region of code to be protected with Protection Expressions. The
protection expressions (`protect for VHDL and `pragma protect for Verilog/SystemVerilog)
specify the encryption algorithm used to protect the source code, the encryption key owner, the
key name, and envelope attributes.
Creating encryption envelopes requires that you:
•
•
identify the region(s) of code to be encrypted,
enclose the code to be encrypted within protection directives, and
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Creating Encryption Envelopes
•
compile your code with ModelSim encryption utilities - vencrypt for
Verilog/SystemVerilog or vhencrypt for VHDL - or with the vcom/vlog +protect
command.
The flow diagram for creating encryption envelopes is shown in Figure 3-1.
Figure 3-1. Create an Encryption Envelope
Symmetric and asymmetric keys can be combined in encryption envelopes to provide the safety
of asymmetric keys with the efficiency of symmetric keys (see Encryption and Encoding
Methods). Encryption envelopes can also be used by the IP author to produce encrypted source
files that can be safely decrypted by multiple authors. For these reasons, encryption envelopes
are the preferred method of protection.
Configuring the Encryption Envelope
The encryption envelope may be configured two ways:
1. The encryption envelope may contain the textual design data to be encrypted
(Example 3-1).
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2. The encryption envelope may contain `include compiler directives that point to files
containing the textual design data to be encrypted (Example 3-2). See Using the `include
Compiler Directive (Verilog only).
Example 3-1. Encryption Envelope Contains Verilog IP Code to be Protected
module test_dff4(output [3:0] q, output err);
parameter WIDTH = 4;
parameter DEBUG = 0;
reg [3:0] d;
reg
clk;
dff4 d4(q, clk, d);
assign
err = 0;
initial
begin
$dump_all_vpi;
$dump_tree_vpi(test_dff4);
$dump_tree_vpi(test_dff4.d4);
$dump_tree_vpi("test_dff4");
$dump_tree_vpi("test_dff4.d4");
$dump_tree_vpi("test_dff4.d", "test_dff4.clk", "test_dff4.q");
$dump_tree_vpi("test_dff4.d4.d0", "test_dff4.d4.d3");
$dump_tree_vpi("test_dff4.d4.q", "test_dff4.d4.clk");
end
endmodule
module dff4(output [3:0] q, input clk, input [3:0] d);
`pragma protect data_method = "aes128-cbc"
`pragma protect author = "IP Provider"
`pragma protect author_info = "Widget 5 version 3.2"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect begin
dff_gate d0(q[0], clk, d[0]);
dff_gate d1(q[1], clk, d[1]);
dff_gate d2(q[2], clk, d[2]);
dff_gate d3(q[3], clk, d[3]);
endmodule // dff4
module dff_gate(output q, input clk, input d);
wire preset = 1;
wire clear = 1;
nand #5
g1(l1,preset,l4,l2),
g2(l2,l1,clear,clk),
g3(l3,l2,clk,l4),
g4(l4,l3,clear,d),
g5(q,preset,l2,qbar),
g6(qbar,q,clear,l3);
endmodule
`pragma protect end
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Creating Encryption Envelopes
In this example, the Verilog code to be encrypted follows the `pragma protect begin
expression and ends with the `pragma protect end expression. If the code had been written in
VHDL, the code to be protected would follow a `protect BEGIN PROTECTED expression
and would end with a `protect END PROTECTED expression.
Example 3-2. Encryption Envelope Contains `include Compiler Directives
`timescale 1ns / 1ps
`cell define
module dff (q, d, clear, preset, clock);
output q;
input d, clear, preset, clock;
reg q;
`pragma
`pragma
`pragma
`pragma
`pragma
`pragma
protect
protect
protect
protect
protect
protect
data_method = "aes128-cbc"
author = "IP Provider", author_info = "Widget 5 v3.2"
key_keyowner = "Mentor Graphics Corporation"
key_method = "rsa"
key_keyname = "MGC-VERIF-SIM-RSA-1"
begin
`include diff.v
`include prim.v
`include top.v
`pragma protect end
always @(posedge clock)
q = d;
endmodule
`endcelldefine
In Example 3-2, the entire contents of diff.v, prim.v, and top.v will be encrypted.
For a more technical explanation, see How Encryption Envelopes Work.
Protection Expressions
The encryption envelope contains a number of `pragma protect (Verilog/SystemVerilog) or
`protect (VHDL) expressions. The following protection expressions are expected when
creating an encryption envelope:
238
•
data_method — defines the encryption algorithm that will be used to encrypt the
designated source text. ModelSim supports the following encryption algorithms: descbc, 3des-cbc, aes128-cbc, aes256-cbc, blowfish-cbc, cast128-cbc, and rsa.
•
key_keyowner — designates the owner of the encryption key.
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•
•
key_keyname — specifies the keyowner’s key name.
key_method — specifies an encryption algorithm that will be used to encrypt the key.
Note
The combination of key_keyowner and key_keyname expressions uniquely identify a
key. The key_method is required with these two expressions to complete the definition of
the key.
•
•
begin — designates the beginning of the source code to be encrypted.
end — designates the end of the source code to be encrypted
Note
Encryption envelopes cannot be nested. A `pragma protect begin/end pair cannot bracket
another `pragma protect begin/end pair.
Optional `protect (VHDL) or `pragma protect (Verilog/SystemVerilog) expressions that may
be included are as follows:
•
•
•
author — designates the IP provider.
author_info — designates optional author information.
encoding — specifies an encoding method. The default encoding method, if none is
specified, is “base 64.”
If a number of protection expressions occur in a single protection directive, the expressions are
evaluated in sequence from left to right. In addition, the interpretation of protected envelopes is
not dependent on this sequence occurring in a single protection expression or a sequence of
protection expressions. However, the most recent value assigned to a protection expression
keyword will be the one used.
Unsupported Protection Expressions
Optional protection expressions that are not currently supported include:
•
•
•
•
any digest_* expression
decrypt_license
runtime_license
viewport
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Creating Encryption Envelopes
Using the `include Compiler Directive (Verilog only)
If any `include directives occur within a protected region of Verilog code and you use vlog
+protect to compile, the compiler generates a copy of the include file with a “.vp” or a “.svp”
extension and encrypts the entire contents of the include file. For example, if we have a header
file, header.v, with the following source code:
initial begin
a <= b;
b <= c;
end
and the file we want to encrypt, top.v, contains the following source code:
module top;
`pragma protect begin
`include "header.v"
`pragma protect end
endmodule
then, when we use the vlog +protect command to compile, the source code of the header file
will be encrypted. If we could decrypt the resulting work/top.vp file it would look like:
module top;
`pragma protect begin
initial begin
a <= b;
b <= c;
end
`pragma protect end
endmodule
In addition, vlog +protect creates an encrypted version of header.v in work/header.vp.
When using the vencrypt compile utility (see Delivering IP Code with Undefined Macros), any
`include statements will be treated as text just like any other source code and will be encrypted
with the other Verilog/SystemVerilog source code. So, if we used the vencrypt utility on the
top.v file above, the resulting work/top.vp file would look like the following (if we could
decrypt it):
module top;
`protect
`include "header.v"
`endprotect
endmodule
The vencrypt utility will not create an encrypted version of header.h.
When you use vlog +protect to generate encrypted files, the original source files must all be
complete Verilog or SystemVerilog modules or packages. Compiler errors will result if you
attempt to perform compilation of a set of parameter declarations within a module. (See also
Compiling with +protect.)
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You can avoid such errors by creating a dummy module that includes the parameter
declarations. For example, if you have a file that contains your parameter declarations and a file
that uses those parameters, you can do the following:
module dummy;
`protect
`include "params.v" // contains various parameters
`include "tasks.v" // uses parameters defined in params.v
`endprotect
endmodule
Then, compile the dummy module with the +protect switch to generate an encrypted output file
with no compile errors.
vlog +protect dummy.v
After compilation, the work library will contain encrypted versions of params.v and tasks.v,
called params.vp and tasks.vp. You may then copy these encrypted files out of the work
directory to more convenient locations. These encrypted files can be included within your
design files; for example:
module main
'include "params.vp"
'include "tasks.vp"
...
Using Portable Encryption for Multiple Tools
An IP author can use the concept of multiple key blocks to produce code that is secure and
portable across any tool that supports Version 1 recommendations from the IEEE P1735
working group. This capability is not language-specific - it can be used for VHDL or Verilog.
To illustrate, suppose the author wants to modify the following VHDL sample file so the
encrypted model can be decrypted and simulated by both ModelSim and by a hypothetical
company named XYZ inc.
========== sample file ==========
-- The entity "ip1" is not protected
...
entity ip1 is
...
end ip1;
-- The architecture "a" is protected
-- The internals of "a" are hidden from the user
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
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architecture a of ip1 is
...
end a;
`protect end
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
library ieee;
use ieee.std_logic_1164.all;
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end
========== end of sample file ==========
The author does this by writing a key block for each decrypting tool. If XYZ publishes a public
key, the two key blocks in the IP source code might look like the following:
`protect
`protect
`protect
`protect
`protect
`protect
`protect
`protect
`protect
key_keyowner = "Mentor Graphics Corporation"
key_method = "rsa"
key_keyname = "MGC-VERIF-SIM-RSA-1"
KEY_BLOCK
key_keyowner = "XYZ inc"
key_method = "rsa"
key_keyname = "XYZ-keyPublicKey"
key_public_key =
KEY_BLOCK
The encrypted code would look very much like the sample file, with the addition of another key
block:
`protect key_keyowner = "XYZ inc"
`protect key_method = "rsa"
`protect key_keyname = "XYZ-keyPublicKey"
`protect KEY_BLOCK
ModelSim uses its key block to determine the encrypted session key and XYZ Incorporated
uses the second key block to determine the same key. Consequently, both implementations
could successfully decrypt the code.
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Note
The IP owner is responsible for obtaining the appropriate key for the specific tool(s)
protected IP is intended for, and should validate the encrypted results with those tools to
insure his IP is protected and will function as intended in those tools.
Compiling with +protect
To encrypt IP code with ModelSim, the +protect argument must be used with either the vcom
command (for VHDL) or the vlog command (for Verilog and SystemVerilog). For example, if a
Verilog source code file containing encryption envelopes is named encrypt.v, it would be
compiled as follows:
vlog +protect encrypt.v
When +protect is used with vcom or vlog, encryption envelope expressions are transformed into
decryption envelope expressions and decryption content expressions. Source text within
encryption envelopes is encrypted using the specified key and is recorded in the decryption
envelope within a data_block. The new encrypted file is created with the same name as the
original unencrypted file but with a ‘p’ added to the filename extension. For Verilog, the
filename extension for the encrypted file is .vp; for SystemVerilog it is .svp, and for VHDL it is
.vhdp. This encrypted file is placed in the current work library directory.
You can designate the name of the encrypted file using the +protect= argument
with vcom or vlog as follows:
vlog +protect=encrypt.vp encrypt.v
Example 3-3 shows the resulting source code when the Verilog IP code used in Example 3-1 is
compiled with vlog +protect.
Example 3-3. Results After Compiling with vlog +protect
module test_dff4(output [3:0] q, output err);
parameter WIDTH = 4;
parameter DEBUG = 0;
reg [3:0] d;
reg
clk;
dff4 d4(q, clk, d);
assign
err = 0;
initial
begin
$dump_all_vpi;
$dump_tree_vpi(test_dff4);
$dump_tree_vpi(test_dff4.d4);
$dump_tree_vpi("test_dff4");
$dump_tree_vpi("test_dff4.d4");
$dump_tree_vpi("test_dff4.d", "test_dff4.clk", "test_dff4.q");
$dump_tree_vpi("test_dff4.d4.d0", "test_dff4.d4.d3");
$dump_tree_vpi("test_dff4.d4.q", "test_dff4.d4.clk");
end
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The Runtime Encryption Model
endmodule
module dff4(output [3:0] q, input clk, input [3:0] d);
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "Model Technology"
`pragma protect encrypt_agent_info = "6.6a"
`pragma protect author = "IP Provider"
`pragma protect author_info = "Widget 5 version 3.2"
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect key_method = "rsa"
`pragma protect key_block encoding = (enctype = "base64", line_length =
64, bytes = 128)
SdI6t9ewd9GE4va+2BgfnRuBNc45wVwjyPeSD/5qnojnbAHdpjWa/O/Tyhw0aq1T
NbDGrDg6I5dbzbLs5UQGFtB2lgOBMnE4JTpGRfV0sEqUdibBHiTpsNrbLpp1iJLi
7l4kQhnivnUuCx87GuqXIf5AaoLGBz5rCxKyA47ElQM=
`pragma protect data_block encoding = (enctype = "base64", line_length =
64, bytes = 496)
efkkPz4gJSO6zZfYdr37fqEoxgLZ3oTgu8y34GTYkO0ZZGKkyonE9zDQct5d0dfe
/BZwoHCWnq4xqUp2dxF4x6cw6qBJcSEifCPDY1hJASoVX+7owIPGnLh5U0P/Wohp
LvkfhIuk2FENGZh+y3rWZAC1vFYKXwDakSJ3neSglHkwYr+T8vGviohIPKet+CPC
d/RxXOi2ChI64KaMY2/fKlerXrnXV7o9ZIrJRHL/CtQ/uxY7aMioR3/WobFrnuoz
P8fH7x/I30taK25KiL6qvuN0jf7g4LiozSTvcT6iTTHXOmB0fZiC1eREMF835q8D
K5lzU+rcb17Wyt8utm71WSu+2gtwvEp39G6R60fkQAuVGw+xsqtmWyyIOdM+PKWl
sqeoVOsBUHFY3x85F534PQNVIVAT1VzFeioMxmJWV+pfT3OlrcJGqX1AxAG25CkY
M1zF77caF8LAsKbvCTgOVsHb7NEqOVTVJZZydVy23VswClYcrxroOhPzmqNgn4pf
zqcFpP+yBnt4UELa63Os6OfsAu7DZ/4kWPAwExyvaahI2ciWs3HREcZEO+aveuLT
gxEFSm0TvBBsMwLc7UvjjC0aF1vUWhDxhwQDAjYT89r2h1G7Y0PGlGOo24s0/A2+
TjdCcOogiGsTDKx6Bxf91g==
`pragma protect end_protected
In this example, the `pragma protect data_method expression designates the encryption
algorithm used to encrypt the Verilog IP code. The key for this encryption algorithm is also
encrypted – in this case, with the RSA public key. The key is recorded in the key_block of the
protected envelope. The encrypted IP code is recorded in the data_block of the envelope.
ModelSim allows more than one key_block to be included so that a single protected envelope
can be encrypted by ModelSim then decrypted by tools from different users.
The Runtime Encryption Model
After you compile with the +protect compile argument, all source text, identifiers, and line
number information are hidden from the end user in the resulting compiled object. ModelSim
cannot locate or display any information of the encrypted regions. Specifically, this means that:
•
•
•
•
244
a Source window will not display the design units’ source code
a Structure window will not display the internal structure
the Objects window will not display internal signals
the Processes window will not display internal processes
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Language-Specific Usage Models
•
•
the Locals window will not display internal variables
none of the hidden objects may be accessed through the Dataflow window or with
ModelSim commands.
Language-Specific Usage Models
This section includes the following usage models that are language-specific:
•
•
Usage Models for Protecting Verilog Source Code
o
Delivering IP Code with Undefined Macros
o
Delivering IP Code with User-Defined Macros
Usage Models for Protecting VHDL Source Code
o
Using the vhencrypt Utility
o
Using ModelSim Default Encryption for VHDL
o
User-Selected Encryption for VHDL
o
Using raw Encryption for VHDL
o
Encrypting Several Parts of a VHDL Source File
o
Using Portable Encryption for Multiple Tools
Usage Models for Protecting Verilog Source Code
ModelSim’s encryption capabilities support the following Verilog and SystemVerilog usage
models for IP authors and their customers.
•
IP authors may use the vencrypt utility to deliver Verilog and SystemVerilog code
containing undefined macros and `directives. The IP user can then define the macros and
`directives and use the code in a wide range of EDA tools and design flows. See
Delivering IP Code with Undefined Macros.
•
IP authors may use `pragma protect directives to protect Verilog and SystemVerilog
code containing user-defined macros and `directives. The IP code can be delivered to IP
customers for use in a wide range of EDA tools and design flows. See Delivering IP
Code with User-Defined Macros.
Delivering IP Code with Undefined Macros
The vencrypt utility enables IP authors to deliver VHDL and Verilog/ SystemVerilog IP code
(respectively) that contains undefined macros and `directives. The resulting encrypted IP code
can then be used in a wide range of EDA tools and design flows.
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The recommended encryption usage flow is shown in Figure 3-2.
Figure 3-2. Verilog/SystemVerilog Encryption Usage Flow
1. The IP author creates code that contains undefined macros and `directives.
2. The IP author creates encryption envelopes (see Creating Encryption Envelopes) to
protect selected regions of code or entire files (see Protection Expressions).
3. The IP author uses ModelSim’s vencrypt utility to encrypt Verilog and SystemVerilog
code contained within encryption envelopes. Macros are not pre-processed before
encryption so macros and other `directives are unchanged.
The vencrypt utility produces a file with a .vp or a .svp extension to distinguish it from
non-encrypted Verilog and SystemVerilog files, respectively. The file extension may be
changed for use with simulators other than ModelSim. The original file extension is
preserved if the -d argument is used with vencrypt, or if a `directive is used
in the file to be encrypted.
With the -h argument for vencrypt the IP author may specify a header file
that can be used to encrypt a large number of files that do not contain the `pragma
protect (or proprietary `protect information - see Proprietary Source Code Encryption
Tools) about how to encrypt the file. Instead, encryption information is provided in the
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specified by -h . This argument essentially concatenates the
header file onto the beginning of each file and saves the user from having to edit
hundreds of files in order to add in the same `pragma protect to every file. For
example,
vencrypt -h encrypt_head top.v cache.v gates.v memory.v
concatenates the information in the encrypt_head file into each verilog file listed. The
encrypt_head file may look like the following:
`pragma
`pragma
`pragma
`pragma
`pragma
`pragma
`pragma
protect
protect
protect
protect
protect
protect
protect
data_method = "aes128-cbc"
author = "IP Provider"
key_keyowner = "Mentor Graphics Corporation"
key_method = "rsa"
key_keyname = "MGC-VERIF-SIM-RSA-1"
encoding = (enctype = "base64")
begin
Notice, there is no `pragma protect end expression in the header file, just the header
block that starts the encryption. The `pragma protect end expression is implied by the
end of the file.
4. The IP author delivers encrypted IP with undefined macros and `directives.
5. The IP user defines macros and `directives.
6. The IP user compiles the design with vlog.
7. The IP user simulates the design with ModelSim or other simulation tools.
Delivering IP Code with User-Defined Macros
IP authors may use `pragma protect expressions to protect proprietary code containing userdefined macros and `directives. The resulting encrypted IP code can be delivered to customers
for use in a wide range of EDA tools and design flows. An example of the recommended usage
flow for Verilog and SystemVerilog IP is shown in Figure 3-3.
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Language-Specific Usage Models
Figure 3-3. Delivering IP Code with User-Defined Macros
1. The IP author creates proprietary code that contains user-defined macros and `directives.
2. The IP author creates encryption envelopes with `pragma protect expressions to protect
regions of code or entire files. See Creating Encryption Envelopes and Protection
Expressions.
3. The IP author uses the +protect argument for the vlog command to encrypt IP code
contained within encryption envelopes. The `pragma protect expressions are ignored
unless the +protect argument is used during compile. (See Compiling with +protect.)
The vlog +protect command produces a .vp or a .svp extension for the encrypted file to
distinguish it from non-encrypted Verilog and SystemVerilog files, respectively. The
file extension may be changed for use with simulators other than ModelSim. The
original file extension is preserved if a `directive is used in the file to be encrypted. For
more information, see Compiling with +protect.
4. The IP author delivers the encrypted IP.
5. The IP user simulates the code like any other file.
When encrypting source text, any macros without parameters defined on the command line are
substituted (not expanded) into the encrypted file. This makes certain macros unavailable in the
encrypted source text.
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ModelSim takes every simple macro that is defined with the compile command (vlog) and
substitutes it into the encrypted text. This prevents third party users of the encrypted blocks
from having access to or modifying these macros.
Note
Macros not specified with vlog via the +define+ option are unmodified in the encrypted
block.
For example, the code below is an example of an file that might be delivered by an IP provider.
The filename for this module is example00.sv.
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect author = "Mentor", author_info = "Mentor_author"
`pragma protect begin
`timescale 1 ps / 1 ps
module example00 ();
`ifdef IPPROTECT
reg `IPPROTECT ;
reg otherReg ;
initial begin
`IPPROTECT = 1;
otherReg
= 0;
$display("ifdef defined as true");
`define FOO 0
$display("FOO is defined as: ", `FOO);
$display("reg IPPROTECT has the value: ", `IPPROTECT );
end
`else
initial begin
$display("ifdef defined as false");
end
`endif
endmodule
`pragma protect end
We encrypt the example00.sv module with the vlog command as follows:
vlog +define+IPPROTECT=ip_value +protect=encrypted00.sv example00.sv
This creates an encrypted file called encrypted00.sv. We can then compile this file with a macro
override for the macro “FOO” as follows:
vlog +define+FOO=99 encrypted00.sv
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The macro FOO can be overridden by a customer while the macro IPPROTECT retains the
value specified at the time of encryption, and the macro IPPROTECT no longer exists in the
encrypted file.
Usage Models for Protecting VHDL Source Code
ModelSim’s encryption capabilities support the following VHDL usage models.
•
IP authors may use `protect directives to create an encryption envelope (see Creating
Encryption Envelopes) for the VHDL code to be protected and use ModelSim’s
vhencrypt utility to encrypt the code. The encrypted IP code can be delivered to IP
customers for use in a wide range of EDA tools and design flows. See Using the
vhencrypt Utility.
•
IP authors may use `protect directives to create an encryption envelope (see Creating
Encryption Envelopes) for the VHDL code to be protected and use ModelSim’s default
encryption and decryption actions. The IP code can be delivered to IP customers for use
in a wide range of EDA tools and design flows. See Using ModelSim Default
Encryption for VHDL.
•
IP authors may use `protect directives to create an encryption envelope for VHDL code
and select encryption methods and encoding other than ModelSim’s default methods.
See User-Selected Encryption for VHDL.
•
IP authors may use “raw” encryption and encoding to aid debugging. See Using raw
Encryption for VHDL.
•
IP authors may encrypt several parts of the source file, choose the encryption method for
encrypting the source (the data_method), and use a key automatically provided by
ModelSim. See Encrypting Several Parts of a VHDL Source File.
•
IP authors can use the concept of multiple key blocks to produce code that is secure and
portable across different simulators. See Using Portable Encryption for Multiple Tools.
The usage models are illustrated by examples in the sections below.
Note
VHDL encryption requires that the KEY_BLOCK (the sequence of key_keyowner,
key_keyname, and key_method directives) end with a `protect KEY_BLOCK directive.
Using the vhencrypt Utility
The vhencrypt utility enables IP authors to deliver encrypted VHDL IP code to users. The
resulting encrypted IP code can then be used in a wide range of EDA tools and design flows.
1. The IP author creates code.
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2. The IP author creates encryption envelopes (see Creating Encryption Envelopes) to
protect selected regions of code or entire files (see Protection Expressions).
3. The IP author uses ModelSim’s vhencrypt utility to encrypt code contained within
encryption envelopes.
The vhencrypt utility produces a file with a .vhdp or a .vhdlp extension to distinguish it
from non-encrypted VHDL files. The file extension may be changed for use with
simulators other than ModelSim. The original file extension is preserved if the
-d argument is used with vhencrypt.
With the -h argument for vencrypt the IP author may specify a header file
that can be used to encrypt a large number of files that do not contain the `protect
information about how to encrypt the file. Instead, encryption information is provided in
the specified by -h . This argument essentially concatenates the
header file onto the beginning of each file and saves the user from having to edit
hundreds of files in order to add in the same `protect to every file. For example,
vhencrypt -h encrypt_head top.vhd cache.vhd gates.vhd memory.vhd
concatenates the information in the encrypt_head file into each VHDL file listed. The
encrypt_head file may look like the following:
`protect
`protect
`protect
`protect
`protect
`protect
`protect
`protect
data_method = "aes128-cbc"
author = "IP Provider"
encoding = (enctype = "base64")
key_keyowner = "Mentor Graphics Corporation"
key_method = "rsa"
key_keyname = "MGC-VERIF-SIM-RSA-1"
KEY_BLOCK
begin
Notice, there is no `protect end expression in the header file, just the header block that
starts the encryption. The `protect end expression is implied by the end of the file.
4. The IP author delivers encrypted IP.
5. The IP user compiles the design with vcom.
6. The IP user simulates the design with ModelSim or other simulation tools.
Using ModelSim Default Encryption for VHDL
Suppose an IP author needs to make a design entity, called IP1, visible to the user, so the user
can instantiate the design; but the author wants to hide the architecture implementation from the
user. In addition, suppose that IP1 instantiates entity IP2, which the author wants to hide
completely from the user. The easiest way to accomplish this is to surround the regions to be
protected with `protect begin and `protect end directives and let ModelSim choose default
actions. For this example, all the source code exists in a single file, example1.vhd:
========== file example1.vhd ==========
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-- The entity "ip1" is not protected
...
entity ip1 is
...
end ip1;
-- The architecture "a" is protected
-- The internals of "a" are hidden from the user
`protect begin
architecture a of ip1 is
...
end a;
`protect end
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect begin
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end
========== end of file example1.vhd ==========
The IP author compiles this file with the vcom +protect command as follows:
vcom +protect=example1.vhdp example1.vhd
The compiler produces an encrypted file, example1.vhdp which looks like the following:
========== file example1.vhdp ==========
-- The entity "ip1" is not protected
...
entity ip1 is
...
end ip1;
-- The architecture "a" is protected
-- The internals of "a" are hidden from the user
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect encoding = ( enctype = "base64" )
`protect KEY_BLOCK
`protect data_method="aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 224 )
`protect DATA_BLOCK
`protect END_PROTECTED
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-- Both the entity "ip2" and its architecture "a" are completely protected
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect encoding = ( enctype = "base64" )
`protect KEY_BLOCK
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 224 )
`protect DATA_BLOCK
`protect END_PROTECTED
========== end of file example1.vhdp ==========
When the IP author surrounds a text region using only `protect begin and `protect end,
ModelSim uses default values for both encryption and encoding. The first few lines following
the `protect BEGIN_PROTECTED region in file example1.vhdp contain the key_keyowner,
key_keyname, key_method and KEY_BLOCK directives. The session key is generated into the
key block and that key block is encrypted using the “rsa” method. The data_method indicates
that the default data encryption method is aes128-cbc and the “enctype” value shows that the
default encoding is base64.
Alternatively, the IP author can compile file example1.vhd with the command:
vcom +protect example1.vhd
Here, the author does not supply the name of the file to contain the protected source. Instead,
ModelSim creates a protected file, gives it the name of the original source file with a 'p' placed
at the end of the file extension, and puts the new file in the current work library directory. With
the command described above, ModelSim creates file work/example1.vhdp. (See Compiling
with +protect.)
The IP user compiles the encrypted file work/example1.vhdp the ordinary way. The +protect
switch is not needed and the IP user does not have to treat the .vhdp file in any special manner.
ModelSim automatically decrypts the file internally and keeps track of protected regions.
If the IP author compiles the file example1.vhd and does not use the +protect argument, then the
file is compiled, various `protect directives are checked for correct syntax, but no protected file
is created and no protection is supplied.
Encryptions done using ModelSim’s default encryption methods are portable to other
decryption tools if they support the “rsa” method and if they have access to the Mentor Graphics
public encryption key. See Using the Mentor Graphics Public Encryption Key.
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User-Selected Encryption for VHDL
Suppose that the IP author wants to produce the same code as in the example1.vhd file used
above, but wants to provide specific values and not use any default values. To do this the author
adds `protect directives for keys, encryption methods, and encoding, and places them before
each `protect begin directive. The input file would look like the following:
========== file example2.vhd ==========
-- The entity "ip1" is not protected
...
entity ip1 is
...
end ip1;
-- The architecture "a" is protected
-- The internals of "a" are hidden from the user
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
architecture a of ip1 is
...
end a;
`protect end
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
library ieee;
use ieee.std_logic_1164.all;
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end
========== end of file example2.vhd ==========
The data_method directive indicates that the encryption algorithm “aes128-cbc” should be used
to encrypt the source code (data). The encoding directive selects the “base64” encoding method,
and the various key directives specify that the Mentor Graphic key named “MGC-VERIF-SIMRSA-1” and the “RSA” encryption method are to be used to produce a key block containing a
randomly generated session key to be used with the “aes128-cbc” method to encrypt the source
code. See Using the Mentor Graphics Public Encryption Key.
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Using raw Encryption for VHDL
Suppose that the IP author wants to use “raw” encryption and encoding to help with debugging
the following entity:
entity example3_ent is
port (
in1 : in bit;
out1 : out bit);
end example3_ent;
Then the architecture the author wants to encrypt might be this:
========== File example3_arch.vhd
`protect data_method = "raw"
`protect encoding = ( enctype = "raw")
`protect begin
architecture arch of example3_ent is
begin
out1 <= in1 after 1 ns;
end arch;
`protect end
========== End of file example3_arch.vhd ==========
If (after compiling the entity) the example3_arch.vhd file were compiled using the command:
vcom +protect example3_arch.vhd
Then the following file would be produced in the work directory
========== File work/example3_arch.vhdp ==========
`protect data_method = "raw"
`protect encoding = ( enctype = "raw")
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect data_method = "raw"
`protect encoding = ( enctype = "raw", bytes = 81 )
`protect DATA_BLOCK
architecture arch of example3_ent is
begin
out1 <= in1 after 1 ns;
end arch;
`protect END_PROTECTED
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========== End of file work/example3_arch.vhdp
Notice that the protected file is very similar to the original file. The differences are that `protect
begin is replaced by `protect BEGIN_PROTECTED, `protect end is replaced by `protect
END_PROTECTED, and some additional encryption information is supplied after the BEGIN
PROTECTED directive.
See Encryption and Encoding Methods for more information about raw encryption and
encoding.
Encrypting Several Parts of a VHDL Source File
This example shows the use of symmetric encryption. (See Encryption and Encoding Methods
for more information on symmetric and asymmetric encryption and encoding.) It also
demonstrates another common use model, in which the IP author encrypts several parts of a
source file, chooses the encryption method for encrypting the source code (the data_method),
and uses a key automatically provided by ModelSim. (This is very similar to the proprietary
`protect method in Verilog - see Proprietary Source Code Encryption Tools.)
========== file example4.vhd ==========
entity ex4_ent is
end ex4_ent;
architecture ex4_arch of ex4_ent is
signal s1: bit;
`protect data_method = "aes128-cbc"
`protect begin
signal s2: bit;
`protect end
signal s3: bit;
begin
-- ex4_arch
`protect
`protect
s2 <= s1
`protect
data_method = "aes128-cbc"
begin
after 1 ns;
end
s3 <= s2 after 1 ns;
end ex4_arch;
========== end of file example4.vhd
If this file were compiled using the command:
vcom +protect example4.vhd
Then the following file would be produced in the work directory:
========== File work/example4.vhdp ==========
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entity ex4_ent is
end ex4_ent;
architecture ex4_arch of ex4_ent is
signal s1: bit;
`protect data_method = "aes128-cbc"
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 18 )
`protect DATA_BLOCK
`protect END_PROTECTED
signal s3: bit;
begin
-- ex4_arch
`protect
`protect
`protect
`protect
`protect
`protect
`protect
END_PROTECTED
s3 <= s2 after 1 ns;
end ex4_arch;
========== End of file work/example4.vhdp
The encrypted example4.vhdp file shows that an IP author can encrypt both declarations and
statements. Also, note that the signal assignment
s3 <= s2 after 1 ns;
is not protected. This assignment compiles and simulates even though signal s2 is protected. In
general, executable VHDL statements and declarations simulate the same whether or not they
refer to protected objects.
Proprietary Source Code Encryption Tools
Mentor Graphics provides two proprietary methods for encrypting source code.
•
The `protect / `endprotect compiler directives allow you to encrypt regions within
Verilog and SystemVerilog files.
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•
The -nodebug argument for the vcom and vlog compile commands allows you to
encrypt entire VHDL, Verilog, or SystemVerilog source files.
Using Proprietary Compiler Directives
The proprietary `protect vlog compiler directive is not compatible with other simulators.
Though other simulators have a `protect directive, the algorithm ModelSim uses to encrypt
Verilog and SystemVerilog source files is different. Therefore, even though an uncompiled
source file with `protect is compatible with another simulator, once the source is compiled in
ModelSim, the resulting .vp or .svp source file is not compatible.
IP authors and IP users may use the `protect compiler directive to define regions of Verilog and
SystemVerilog code to be protected. The code is then compiled with the vlog +protect
command and simulated with ModelSim. The vencrypt utility may be used if the code contains
undefined macros or `directives, but the code must then be compiled and simulated with
ModelSim.
Note
While ModelSim supports both `protect and `pragma protect encryption directives,
these two approaches to encryption are incompatible. Code encrypted by one type of
directive cannot be decrypted by another.
The usage flow for delivering IP with the Mentor Graphics proprietary `protect compiler
directive is as follows:
Figure 3-4. Delivering IP with `protect Compiler Directives
1. The IP author protects selected regions of Verilog or SystemVerilog IP with the
`protect / `endprotect directive pair. The code in `protect / `endprotect encryption
envelopes has all debug information stripped out. This behaves exactly as if using
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vlog -nodebug=ports+pli
except that it applies to selected regions of code rather than the whole file.
2. The IP author uses the vlog +protect command to encrypt IP code contained within
encryption envelopes. The `protect / `endprotect directives are ignored by default
unless the +protect argument is used with vlog.
Once compiled, the original source file is copied to a new file in the current work
directory. The vlog +protect command produces a .vp or a .svp extension to distinguish
it from other non-encrypted Verilog and SystemVerilog files, respectively. For example,
top.v becomes top.vp and cache.sv becomes cache.svp. This new file can be delivered
and used as a replacement for the original source file. (See Compiling with +protect.)
Note
The vencrypt utility may be used if the code also contains undefined macros or
`directives, but the code must then be compiled and simulated with ModelSim.
You can use vlog +protect= to create an encrypted output file, with the
designated filename, in the current directory (not in the work directory, as in the default
case where [=] is not specified). For example:
vlog test.v +protect=test.vp
If the filename is specified in this manner, all source files on the command line will be
concatenated together into a single output file. Any `include files will also be inserted
into the output file.
Caution
`protect and `endprotect directives cannot be nested.
If errors are detected in a protected region, the error message always reports the first line of the
protected block.
Protecting Source Code Using -nodebug
Verilog/SystemVerilog and VHDL IP authors and users may use the proprietary vlog -nodebug
or vcom -nodebug command, respectively, to protect entire files. The -nodebug argument for
both vcom and vlog hides internal model data, allowing you to provide pre-compiled libraries
without providing source code and without revealing internal model variables and structure.
Note
The -nodebug argument encrypts entire files. The `protect compiler directive allows you
to encrypt regions within a file. Refer to Compiler Directives for details.
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When you compile with -nodebug, all source text, identifiers, and line number information are
stripped from the resulting compiled object, so ModelSim cannot locate or display any
information of the model except for the external pins.
You can access the design units comprising your model via the library, and you may invoke
vsim directly on any of these design units to see the ports. To restrict even this access in the
lower levels of your design, you can use the following -nodebug options when you compile:
Table 3-1. Compile Options for the -nodebug Compiling
Command and Switch
Result
vcom -nodebug=ports
makes the ports of a VHDL design unit
invisible
vlog -nodebug=ports
makes the ports of a Verilog design unit
invisible
vlog -nodebug=pli
prevents the use of PLI functions to
interrogate the module for information
vlog -nodebug=ports+pli
combines the functions of -nodebug=ports
and -nodebug=pli
Note
Do not use the =ports option on a design without hierarchy, or on the top level of a
hierarchical design. If you do, no ports will be visible for simulation. Rather, compile all
lower portions of the design with -nodebug=ports first, then compile the top level with
-nodebug alone.
Design units or modules compiled with -nodebug can only instantiate design units or modules
that are also compiled -nodebug.
Do not use -nodebug=ports for mixed language designs, especially for Verilog modules to be
instantiated inside VHDL.
Encryption Reference
This section includes reference details on:
•
•
•
•
260
Encryption and Encoding Methods
How Encryption Envelopes Work
Using Public Encryption Keys
Using the Mentor Graphics Public Encryption Key
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Encryption and Encoding Methods
There are two basic encryption techniques: symmetric and asymmetric.
•
Symmetric encryption uses the same key for both encrypting and decrypting the code
region.
•
Asymmetric encryption methods use two keys: a public key for encryption, and a private
key for decryption.
Symmetric Encryption
For symmetric encryption, security of the key is critical and information about the key must be
supplied to ModelSim. Under certain circumstances, ModelSim will generate a random key for
use with a symmetric encryption method or will use an internal key.
The symmetric encryption algorithms ModelSim supports are:
•
•
•
•
•
•
•
des-cbc
3des-cbc
aes128-cbc
aes192-cbc
aes256-cbc
blowfish-cbc
cast128-cbc
The default symmetric encryption method ModelSim uses for encrypting IP source code is
aes128-cbc.
Asymmetric Encryption
For asymmetric encryption, the public key is openly available and is published using some form
of key distribution system. The private key is secret and is used by the decrypting tool, such as
ModelSim. Asymmetric methods are more secure than symmetric methods, but take much
longer to encrypt and decrypt data.
The only asymmetric method ModelSim supports is:
rsa
This method is only supported for specifying key information, not for encrypting IP source code
(i.e., only for key methods, not for data methods).
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For testing purposes, ModelSim also supports raw encryption, which doesn't change the
protected source code (the simulator still hides information about the protected region).
All encryption algorithms (except raw) produce byte streams that contain non-graphic
characters, so there needs to be an encoding mechanism to transform arbitrary byte streams into
portable sequences of graphic characters which can be used to put encrypted text into source
files. The encoding methods supported by ModelSim are:
•
•
•
uuencode
base64
raw
Base 64 encoding, which is technically superior to uuencode, is the default encoding used by
ModelSim, and is the recommended encoding for all applications.
Raw encoding must only be used in conjunction with raw encryption for testing purposes.
How Encryption Envelopes Work
Encryption envelopes work as follows:
1. The encrypting tool generates a random key for use with a symmetric method, called a
“session key.”
2. The IP protected source code is encrypted using this session key.
3. The encrypting tool communicates the session key to the decrypting tool —which could
be ModelSim or some other tool — by means of a KEY_BLOCK.
4. For each potential decrypting tool, information about that tool must be provided in the
encryption envelope. This information includes the owner of the key (key_keyowner),
the name of the key (key_keyname), the asymmetric method for encrypting/decrypting
the key (key_method), and sometimes the key itself (key_public_key).
5. The encrypting tool uses this information to encrypt and encode the session key into a
KEY_BLOCK. The occurrence of a KEY_BLOCK in the source code tells the
encrypting tool to generate an encryption envelope.
6. The decrypting tool reads each KEY_BLOCK until it finds one that specifies a key it
knows about. It then decrypts the associated KEY_BLOCK data to determine the
original session key and uses that session key to decrypt the IP source code.
Note
VHDL encryption requires that the KEY_BLOCK (the sequence of key_keyowner,
key_keyname, and key_method directives) end with a `protect KEY_BLOCK directive.
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Using Public Encryption Keys
If IP authors want to encrypt for third party EDA tools, other public keys need to be specified
with the key_public_key directive as follows.
For Verilog and SystemVerilog:
`pragma protect key_keyowner="Acme"
`pragma protect key_keyname="AcmeKeyName"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
For VHDL:
`protect key_keyowner="Acme"
`protect key_keyname="AcmeKeyName"
`protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
This defines a new key named “AcmeKeyName” with a key owner of “Acme.” The data block
following key_public_key directive is an example of a base64 encoded version of a public key
that should be provided by a tool vendor.
Using the Mentor Graphics Public Encryption Key
The Mentor Graphics base64 encoded RSA public key is:
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
For Verilog and SystemVerilog applications, copy and paste the entire Mentor Graphics key
block, as follows, into your code:
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
The vencrypt utility will recognize the Mentor Graphics public key. If vencrypt is not used, you
must use the +protect switch with the vlog command during compile.
For VHDL applications, copy and paste the entire Mentor Graphics key block, as follows, into
your code:
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`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_method = "rsa"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
The vhencrypt utility will recognize the Mentor Graphics public key. If vhencrypt is not used,
you must use the +protect switch with the vcom command during compile.
Example 3-4 illustrates the encryption envelope methodology for using this key in
Verilog/SystemVerilog. With this methodology you can collect the public keys from the various
companies whose tools process your IP, then create a template that can be included into the files
you want encrypted. During the encryption phase a new key is created for the encryption
algorithm each time the source is compiled. These keys are never seen by a human. They are
encrypted using the supplied RSA public keys.
Example 3-4. Using the Mentor Graphics Public Encryption Key in
Verilog/SystemVerilog
//
// Copyright 1991-2009 Mentor Graphics Corporation
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE
PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
//
`timescale 1ns / 1ps
`celldefine
module dff (q, d, clear, preset, clock); output q; input d, clear, preset, clock;
reg q;
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvIf9Tif2em
i4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT80Xs0QgRqkrGYxW1
RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
`pragma protect key_keyowner = "XYZ inc"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "XYZ-keyPublicKey"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQDZQTj5T5jO1og8ykyaxVg9B+4V+smyCJGW36ZjoqEGq
6jXHxfqB2VAmIC/j9x4xRxtCaOeBxRpcrnIKTP13Y3ydHqpYW0s0+R4h5+cMwCzWqB18Fn0ibSEW+8gW/
/BP4dHzaJApEz2Ryj+IG3UinvvWVNheZd+j0ULHGMgrOQqrwIDAQAB
`pragma protect begin
always @(clear or preset)
if (!clear)
assign q = 0;
else if (!preset)
assign q = 1;
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else
deassign q;
`pragma protect end
always @(posedge clock)
q = d;
endmodule
`endcelldefine
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Chapter 4
Projects
Projects simplify the process of compiling and simulating a design and are a great tool for
getting started with ModelSim.
What are Projects?
Projects are collection entities for designs under specification or test. At a minimum, projects
have a root directory, a work library, and "metadata" which are stored in an .mpf file located in
a project's root directory. The metadata include compiler switch settings, compile order, and file
mappings. Projects may also include:
•
•
•
•
•
•
Source files or references to source files
other files such as READMEs or other project documentation
local libraries
references to global libraries
Simulation Configurations (see Creating a Simulation Configuration)
Folders (see Organizing Projects with Folders)
Note
Project metadata are updated and stored only for actions taken within the project itself.
For example, if you have a file in a project, and you compile that file from the command
line rather than using the project menu commands, the project will not update to reflect
any new compile settings.
What are the Benefits of Projects?
Projects offer benefits to both new and advanced users. Projects
•
simplify interaction with ModelSim; you don’t need to understand the intricacies of
compiler switches and library mappings
•
eliminate the need to remember a conceptual model of the design; the compile order is
maintained for you in the project. Compile order is maintained for HDL-only designs.
•
remove the necessity to re-establish compiler switches and settings at each session; these
are stored in the project metadata as are mappings to source files
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•
allow users to share libraries without copying files to a local directory; you can establish
references to source files that are stored remotely or locally
•
allow you to change individual parameters across multiple files; in previous versions
you could only set parameters one file at a time
•
enable "what-if" analysis; you can copy a project, manipulate the settings, and rerun it to
observe the new results
•
reload the initial settings from the project .mpf file every time the project is opened
Project Conversion Between Versions
Projects are generally not backwards compatible for either number or letter releases. When you
open a project created in an earlier version, you will see a message warning that the project will
be converted to the newer version. You have the option of continuing with the conversion or
cancelling the operation.
As stated in the warning message, a backup of the original project is created before the
conversion occurs. The backup file is named .mpf.bak and is created in the
same directory in which the original project is located.
Getting Started with Projects
This section describes the four basic steps to working with a project.
•
Step 1 — Creating a New Project
This creates an .mpf file and a working library.
•
Step 2 — Adding Items to the Project
Projects can reference or include source files, folders for organization, simulations, and
any other files you want to associate with the project. You can copy files into the project
directory or simply create mappings to files in other locations.
•
Step 3 — Compiling the Files
This checks syntax and semantics and creates the pseudo machine code ModelSim uses
for simulation.
•
Step 4 — Simulating a Design
This specifies the design unit you want to simulate and opens a structure tab in the
Workspace pane.
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Getting Started with Projects
Step 1 — Creating a New Project
Select File > New > Project to create a new project. This opens the Create Project dialog
where you can specify a project name, location, and default library name. You can generally
leave the Default Library Name set to "work." The name you specify will be used to create a
working library subdirectory within the Project Location. This dialog also allows you to
reference library settings from a selected .ini file or copy them directly into the project.
Figure 4-1. Create Project Dialog
After selecting OK, you will see a blank Project window in the Main window (Figure 4-2)
Figure 4-2. Project Window Detail
and the Add Items to the Project dialog (Figure 4-3).
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Figure 4-3. Add items to the Project Dialog
The name of the current project is shown at the bottom left corner of the Main window.
Step 2 — Adding Items to the Project
The Add Items to the Project dialog includes these options:
•
Create New File — Create a new VHDL, Verilog, SystemC, Tcl, or text file using the
Source editor. See below for details.
•
•
Add Existing File — Add an existing file. See below for details.
•
Create New Folder — Create an organization folder. See Organizing Projects with
Folders for details.
Create Simulation — Create a Simulation Configuration that specifies source files and
simulator options. See Creating a Simulation Configuration for details.
Create New File
The File > New > Source menu selections allow you to create a new VHDL, Verilog, SystemC,
Tcl, or text file using the Source editor.
You can also create a new project file by selecting Project > Add to Project > New File (the
Project tab in the Workspace must be active) or right-clicking in the Project tab and selecting
Add to Project > New File. This will open the Create Project File dialog (Figure 4-4).
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Figure 4-4. Create Project File Dialog
Specify a name, file type, and folder location for the new file.
When you select OK, the file is listed in the Project tab. Double-click the name of the new file
and a Source editor window will open, allowing you to create source code.
Add Existing File
You can add an existing file to the project by selecting Project > Add to Project > Existing
File or by right-clicking in the Project tab and selecting Add to Project > Existing File.
Figure 4-5. Add file to Project Dialog
When you select OK, the file(s) is added to the Project tab.
Step 3 — Compiling the Files
The question marks in the Status column in the Project tab denote either the files haven’t been
compiled into the project or the source has changed since the last compile. To compile the files,
select Compile > Compile All or right click in the Project tab and select Compile > Compile
All (Figure 4-6).
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Figure 4-6. Right-click Compile Menu in Project Window
Once compilation is finished, click the Library window, expand library work by clicking the
"+", and you will see the compiled design units.
Figure 4-7. Click Plus Sign to Show Design Hierarchy
Changing Compile Order
The Compile Order dialog box is functional for HDL-only designs. When you compile all files
in a project, ModelSim by default compiles the files in the order in which they were added to the
project. You have two alternatives for changing the default compile order: 1) select and compile
each file individually; 2) specify a custom compile order.
To specify a custom compile order, follow these steps:
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1. Select Compile > Compile Order or select it from the context menu in the Project tab.
Figure 4-8. Setting Compile Order
2. Drag the files into the correct order or use the up and down arrow buttons. Note that you
can select multiple files and drag them simultaneously.
Auto-Generating Compile Order
Auto Generate is supported for HDL-only designs. The Auto Generate button in the Compile
Order dialog (see above) "determines" the correct compile order by making multiple passes
over the files. It starts compiling from the top; if a file fails to compile due to dependencies, it
moves that file to the bottom and then recompiles it after compiling the rest of the files. It
continues in this manner until all files compile successfully or until a file(s) can’t be compiled
for reasons other than dependency.
Files can be displayed in the Project window in alphabetical or compile order (by clicking the
column headings). Keep in mind that the order you see in the Project tab is not necessarily the
order in which the files will be compiled.
Grouping Files
You can group two or more files in the Compile Order dialog so they are sent to the compiler at
the same time. For example, you might have one file with a bunch of Verilog define statements
and a second file that is a Verilog module. You would want to compile these two files together.
To group files, follow these steps:
1. Select the files you want to group.
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Figure 4-9. Grouping Files
2. Click the Group button.
To ungroup files, select the group and click the Ungroup button.
Step 4 — Simulating a Design
To simulate a design, do one of the following:
274
•
double-click the Name of an appropriate design object (such as a test bench module or
entity) in the Library window
•
right-click the Name of an appropriate design object and select Simulate from the
popup menu
•
select Simulate > Start Simulation from the menus to open the Start Simulation dialog
(Figure 4-10). Select a design unit in the Design tab. Set other options in the VHDL,
Verilog, Libraries, SDF, and Others tabs. Then click OK to start the simulation.
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Figure 4-10. Start Simulation Dialog
A new Structure window, named sim, appears that shows the structure of the active simulation
(Figure 4-11).
Figure 4-11. Structure WIndow with Projects
At this point you are ready to run the simulation and analyze your results. You often do this by
adding signals to the Wave window and running the simulation for a given period of time. See
the ModelSim Tutorial for examples.
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The Project Window
Other Basic Project Operations
Open an Existing Project
If you previously exited ModelSim with a project open, ModelSim automatically will open that
same project upon startup. You can open a different project by selecting File > Open and
choosing Project Files from the Files of type drop-down.
Print the Absolute Pathnames For All Files
You can send a list of all project filenames to the transcript window by entering the command
project filenames. This command only works when a project is open.
Close a Project
Right-click in the Project window and select Close Project. This closes the Project window but
leaves the Library window open. Note that you cannot close a project while a simulation is in
progress.
The Project Window
The Project window contains information about the objects in your project. By default the
window is divided into five columns.
Figure 4-12. Project Window Overview
•
•
276
Name – The name of a file or object.
Status – Identifies whether a source file has been successfully compiled. Applies only to
VHDL or Verilog files. A question mark means the file hasn’t been compiled or the
source file has changed since the last successful compile; an X means the compile
failed; a check mark means the compile succeeded; a checkmark with a yellow triangle
behind it means the file compiled but there were warnings generated.
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•
Type – The file type as determined by registered file types on Windows or the type you
specify when you add the file to the project.
•
Order – The order in which the file will be compiled when you execute a Compile All
command.
•
Modified – The date and time of the last modification to the file.
You can hide or show columns by right-clicking on a column title and selecting or deselecting
entries.
Sorting the List
You can sort the list by any of the five columns. Click on a column heading to sort by that
column; click the heading again to invert the sort order. An arrow in the column heading
indicates which field the list is sorted by and whether the sort order is descending (down arrow)
or ascending (up arrow).
Creating a Simulation Configuration
A Simulation Configuration associates a design unit(s) and its simulation options. For example,
assume you routinely load a particular design and you also have to specify the simulator
resolution limit, generics, and SDF timing files. Ordinarily you would have to specify those
options each time you load the design. With a Simulation Configuration, you would specify the
design and those options and then save the configuration with a name (for example, top_config).
The name is then listed in the Project tab and you can double-click it to load the design along
with its options.
To create a Simulation Configuration, follow these steps:
1. Select Project > Add to Project > Simulation Configuration from the main menu, or
right-click the Project tab and select Add to Project > Simulation Configuration from
the popup context menu in the Project window.
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Figure 4-13. Add Simulation Configuration Dialog
2. Specify a name in the Simulation Configuration Name field.
3. Specify the folder in which you want to place the configuration (see Organizing Projects
with Folders).
4. Select one or more design unit(s). Use the Control and/or Shift keys to select more than
one design unit. The design unit names appear in the Simulate field when you select
them.
5. Use the other tabs in the dialog to specify any required simulation options.
Click OK and the simulation configuration is added to the Project window.
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Organizing Projects with Folders
Figure 4-14. Simulation Configuration in the Project Window
Double-click the Simulation Configuration verilog_sim to load the design.
Organizing Projects with Folders
The more files you add to a project, the harder it can be to locate the item you need. You can
add "folders" to the project to organize your files. These folders are akin to directories in that
you can have multiple levels of folders and sub-folders. However, no actual directories are
created via the file system–the folders are present only within the project file.
Adding a Folder
To add a folder to your project, select Project > Add to Project > Folder or right-click in the
Project window and select Add to Project > Folder (Figure 4-15).
Figure 4-15. Add Folder Dialog
Specify the Folder Name, the location for the folder, and click OK. The folder will be displayed
in the Project tab.
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Organizing Projects with Folders
You use the folders when you add new objects to the project. For example, when you add a file,
you can select which folder to place it in.
Figure 4-16. Specifying a Project Folder
If you want to move a file into a folder later on, you can do so using the Properties dialog for the
file. Simply right-click on the filename in the Project window and select Properties from the
context menu that appears. This will open the Project Compiler Settings Dialog (Figure 4-17).
Use the Place in Folder field to specify a folder.
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Specifying File Properties and Project Settings
Figure 4-17. Project Compiler Settings Dialog
On Windows platforms, you can also just drag-and-drop a file into a folder.
Specifying File Properties and Project Settings
You can set two types of properties in a project: file properties and project settings. File
properties affect individual files; project settings affect the entire project.
File Compilation Properties
The VHDL and Verilog compilers (vcom and vlog, respectively) have numerous options that
affect how a design is compiled and subsequently simulated. You can customize the settings on
individual files or a group of files.
Note
Any changes you make to the compile properties outside of the project, whether from the
command line, the GUI, or the modelsim.ini file, will not affect the properties of files
already in the project.
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Specifying File Properties and Project Settings
To customize specific files, select the file(s) in the Project window, right click on the file names,
and select Properties. The resulting Project Compiler Settings dialog (Figure 4-18) varies
depending on the number and type of files you have selected. If you select a single VHDL or
Verilog file, you will see the General tab, Coverage tab, and the VHDL or Verilog tab,
respectively. If you select a SystemC file, you will see only the General tab. On the General tab,
you will see file properties such as Type, Location, and Size. If you select multiple files, the file
properties on the General tab are not listed. Finally, if you select both a VHDL file and a
Verilog file, you will see all tabs but no file information on the General tab.
Figure 4-18. Specifying File Properties
When setting options on a group of files, keep in mind the following:
282
•
If two or more files have different settings for the same option, the checkbox in the
dialog will be "grayed out." If you change the option, you cannot change it back to a
"multi- state setting" without cancelling out of the dialog. Once you click OK,
ModelSim will set the option the same for all selected files.
•
If you select a combination of VHDL and Verilog files, the options you set on the
VHDL and Verilog tabs apply only to those file types.
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Specifying File Properties and Project Settings
Project Settings
To modify project settings, right-click anywhere within the Project tab and select Project
Settings.
Figure 4-19. Project Settings Dialog
Converting Pathnames to Softnames for Location Mapping
If you are using location mapping, you can convert the following into a soft pathname:
•
•
•
a relative pathname
full pathname
pathname with an environment variable
Tip: A softname is a term for a pathname that uses location mapping with
MGC_LOCATION_MAP. The soft pathname looks like a pathname containing an
environment variable, it locates the source using the location map rather than the
environment.
To convert the pathname to a softname for projects using location mapping, follow these steps:
1. Right-click anywhere within the Project tab and select Project Settings
2. Enable the Convert pathnames to softnames within the Location map area of the
Project Settings dialog box (Figure 4-19).
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Once enabled, all pathnames currently in the project and any that are added later are then
converted to softnames.
During conversion, if there is no softname in the mgc location map matching the entry, the
pathname is converted in to a full (hardened) pathname. A pathname is hardened by removing
the environment variable or the relative portion of the path. If this happens, any existing
pathnames that are either relative or use environment variables are also changed: either to
softnames if possible, or to hardened pathnames if not.
For more information on location mapping and pathnames, see Using Location Mapping.
Accessing Projects from the Command Line
Generally, projects are used from within the ModelSim GUI. However, standalone tools will
use the project file if they are invoked in the project's root directory. If you want to invoke
outside the project directory, set the MODELSIM environment variable with the path to the
project file (/.mpf).
You can also use the project command from the command line to perform common operations
on projects.
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Chapter 5
Design Libraries
VHDL designs are associated with libraries, which are objects that contain compiled design
units. SystemC, Verilog and SystemVerilog designs simulated within ModelSim are compiled
into libraries as well.
Design Library Overview
A design library is a directory or archive that serves as a repository for compiled design units.
The design units contained in a design library consist of VHDL entities, packages, architectures,
and configurations; Verilog modules and UDPs (user-defined primitives); and SystemC
modules. The design units are classified as follows:
•
Primary design units — Consist of entities, package declarations, configuration
declarations, modules, UDPs, and SystemC modules. Primary design units within a
given library must have unique names.
•
Secondary design units — Consist of architecture bodies package bodies. Secondary
design units are associated with a primary design unit. Architectures by the same name
can exist if they are associated with different entities or modules.
Design Unit Information
The information stored for each design unit in a design library is:
•
•
•
retargetable, executable code
debugging information
dependency information
Working Library Versus Resource Libraries
Design libraries can be used in two ways:
1. as a local working library that contains the compiled version of your design;
2. as a resource library.
The contents of your working library will change as you update your design and recompile. A
resource library is typically static and serves as a parts source for your design. You can create
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Working with Design Libraries
your own resource libraries or they may be supplied by another design team or a third party (for
example, a silicon vendor).
Only one library can be the working library.
Any number of libraries can be resource libraries during a compilation. You specify which
resource libraries will be used when the design is compiled, and there are rules to specify in
which order they are searched (refer to Specifying Resource Libraries).
A common example of using both a working library and a resource library is one in which your
gate-level design and test bench are compiled into the working library and the design references
gate-level models in a separate resource library.
The Library Named "work"
The library named "work" has special attributes within ModelSim — it is predefined in the
compiler and need not be declared explicitly (that is, library work). It is also the library name
used by the compiler as the default destination of compiled design units (that is, it does not need
to be mapped). In other words, the work library is the default working library.
Archives
By default, design libraries are stored in a directory structure with a sub-directory for each
design unit in the library. Alternatively, you can configure a design library to use archives. In
this case, each design unit is stored in its own archive file. To create an archive, use the -archive
argument to the vlib command.
Generally you would do this only in the rare case that you hit the reference count limit on Inodes due to the ".." entries in the lower-level directories (the maximum number of subdirectories on UNIX and Linux is 65533). An example of an error message that is produced
when this limit is hit is:
mkdir: cannot create directory `65534': Too many links
Archives may also have limited value to customers seeking disk space savings.
Working with Design Libraries
The implementation of a design library is not defined within standard VHDL or Verilog. Within
ModelSim, design libraries are implemented as directories and can have any legal name allowed
by the operating system, with one exception: extended identifiers are not supported for library
names.
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Working with Design Libraries
Creating a Library
When you create a project (refer to Getting Started with Projects), ModelSim automatically
creates a working design library. If you don’t create a project, you need to create a working
design library before you run the compiler. This can be done from either the command line or
from the ModelSim graphic interface.
From the ModelSim prompt or a UNIX/DOS prompt, use this vlib command:
vlib
To create a new library with the graphic interface, select File > New > Library.
Figure 5-1. Creating a New Library
When you click OK, ModelSim creates the specified library directory and writes a speciallyformatted file named _info into that directory. The _info file must remain in the directory to
distinguish it as a ModelSim library.
The new map entry is written to the modelsim.ini file in the [Library] section. Refer to
modelsim.ini Variables for more information.
Note
Remember that a design library is a special kind of directory. The only way to create a
library is to use the ModelSim GUI or the vlib command. Do not try to create libraries
using UNIX, DOS, or Windows commands.
Managing Library Contents
Library contents can be viewed, deleted, recompiled, edited and so on using either the graphic
interface or command line.
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Working with Design Libraries
The Library window provides access to design units (configurations, modules, packages,
entities, architectures, and SystemC modules) in a library. Various information about the design
units is displayed in columns to the right of the design unit name.
Figure 5-2. Design Unit Information in the Workspace
The Library window has a popup menu with various commands that you access by clicking
your right mouse button.
The context menu includes the following commands:
•
Simulate — Loads the selected design unit(s) and opens Structure (sim) and Files
windows. Related command line command is vsim.
•
Simulate with Coverage — Loads the selected design unit(s) and collects code
coverage data. Related command line command is vsim -coverage.
•
Edit — Opens the selected design unit(s) in the Source window; or, if a library is
selected, opens the Edit Library Mapping dialog (refer to Library Mappings with the
GUI).
•
Refresh — Rebuilds the library image of the selected library without using source code.
Related command line command is vcom or vlog with the -refresh argument.
•
Recompile — Recompiles the selected design unit(s). Related command line command
is vcom or vlog.
•
Update — Updates the display of available libraries and design units.
Assigning a Logical Name to a Design Library
VHDL uses logical library names that can be mapped to ModelSim library directories. By
default, ModelSim can find libraries in your current directory (assuming they have the right
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Working with Design Libraries
name), but for it to find libraries located elsewhere, you need to map a logical library name to
the pathname of the library.
You can use the GUI, a command, or a project to assign a logical name to a design library.
Library Mappings with the GUI
To associate a logical name with a library, select the library in the Library window, right-click
your mouse, and select Edit from the context menu that appears. This brings up a dialog box
that allows you to edit the mapping.
Figure 5-3. Edit Library Mapping Dialog
The dialog box includes these options:
•
•
Library Mapping Name — The logical name of the library.
Library Pathname — The pathname to the library.
Library Mapping from the Command Line
You can set the mapping between a logical library name and a directory with the vmap
command using the following syntax:
vmap
You may invoke this command from either a UNIX/DOS prompt or from the command line
within ModelSim.
The vmap command adds the mapping to the library section of the modelsim.ini file. You can
also modify modelsim.ini manually by adding a mapping line. To do this, use a text editor and
add a line under the [Library] section heading using the syntax:
=
More than one logical name can be mapped to a single directory. For example, suppose the
modelsim.ini file in the current working directory contains following lines:
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Working with Design Libraries
[Library]
work = /usr/rick/design
my_asic = /usr/rick/design
This would allow you to use either the logical name work or my_asic in a library or use clause
to refer to the same design library.
Unix Symbolic Links
You can also create a UNIX symbolic link to the library using the host platform command:
ln -s
The vmap command can also be used to display the mapping of a logical library name to a
directory. To do this, enter the shortened form of the command:
vmap
Library Search Rules
The system searches for the mapping of a logical name in the following order:
•
•
First the system looks for a modelsim.ini file.
If the system doesn’t find a modelsim.ini file, or if the specified logical name does not
exist in the modelsim.ini file, the system searches the current working directory for a
subdirectory that matches the logical name.
An error is generated by the compiler if you specify a logical name that does not resolve to an
existing directory.
Moving a Library
Individual design units in a design library cannot be moved. An entire design library can be
moved, however, by using standard operating system commands for moving a directory or an
archive.
Setting Up Libraries for Group Use
By adding an “others” clause to your modelsim.ini file, you can have a hierarchy of library
mappings. If the tool does not find a mapping in the modelsim.ini file, then it will search the
[library] section of the initialization file specified by the “others” clause. For example:
[library]
asic_lib = /cae/asic_lib
work = my_work
others = /usr/modeltech/modelsim.ini
You can specify only one "others" clause in the library section of a given modelsim.ini file.
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Specifying Resource Libraries
The “others” clause only instructs the tool to look in the specified modelsim.ini file for a library.
It does not load any other part of the specified file.
If there are two libraries with the same name mapped to two different locations – one in the
current modelsim.ini file and the other specified by the "others" clause – the mapping specified
in the current .ini file will take effect.
Specifying Resource Libraries
Verilog Resource Libraries
ModelSim supports separate compilation of distinct portions of a Verilog design. The vlog
compiler is used to compile one or more source files into a specified library. The library thus
contains pre-compiled modules and UDPs that are referenced by the simulator as it loads the
design.
Resource libraries are specified differently for Verilog and VHDL. For Verilog you use either
the -L or -Lf argument to vlog. Refer to Library Usage for more information.
The LibrarySearchPath variable in the modelsim.ini file (in the [vlog] section) can be used to
define a space-separated list of resource library paths and/or library path variables. This
behavior is identical with the -L argument for the vlog command.
LibrarySearchPath = /lib1 /lib2 /lib3
The default for LibrarySearchPath is:
LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
VHDL Resource Libraries
Within a VHDL source file, you use the VHDL library clause to specify logical names of one
or more resource libraries to be referenced in the subsequent design unit. The scope of a library
clause includes the text region that starts immediately after the library clause and extends to the
end of the declarative region of the associated design unit. It does not extend to the next design
unit in the file.
Note that the library clause is not used to specify the working library into which the design unit
is placed after compilation. The vcom command adds compiled design units to the current
working library. By default, this is the library named work. To change the current working
library, you can use vcom -work and specify the name of the desired target library.
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Predefined Libraries
Certain resource libraries are predefined in standard VHDL. The library named std contains the
packages standard, env, and textio, which should not be modified. The contents of these
packages and other aspects of the predefined language environment are documented in the IEEE
Standard VHDL Language Reference Manual, Std 1076. Refer also to, Using the TextIO
Package.
A VHDL use clause can be specified to select particular declarations in a library or package that
are to be visible within a design unit during compilation. A use clause references the compiled
version of the package—not the source.
By default, every VHDL design unit is assumed to contain the following declarations:
LIBRARY std, work;
USE std.standard.all
To specify that all declarations in a library or package can be referenced, add the suffix .all to
the library/package name. For example, the use clause above specifies that all declarations in
the package standard, in the design library named std, are to be visible to the VHDL design unit
immediately following the use clause. Other libraries or packages are not visible unless they are
explicitly specified using a library or use clause.
Another predefined library is work, the library where a design unit is stored after it is compiled
as described earlier. There is no limit to the number of libraries that can be referenced, but only
one library is modified during compilation.
Alternate IEEE Libraries Supplied
The installation directory may contain two or more versions of the IEEE library:
•
•
ieeepure — Contains only IEEE approved packages (accelerated for ModelSim).
ieee — Contains precompiled Synopsys and IEEE arithmetic packages which have been
accelerated for ModelSim including math_complex, math_real, numeric_bit,
numeric_std, std_logic_1164, std_logic_misc, std_logic_textio, std_logic_arith,
std_logic_signed, std_logic_unsigned, vital_primitives, and vital_timing.
You can select which library to use by changing the mapping in the modelsim.ini file. The
modelsim.ini file in the installation directory defaults to the ieee library.
Regenerating Your Design Libraries
Depending on your current ModelSim version, you may need to regenerate your design libraries
before running a simulation. Check the installation README file to see if your libraries require
an update. You can regenerate your design libraries using the Refresh command from the
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Library tab context menu (refer to Managing Library Contents), or by using the -refresh
argument to vcom and vlog.
From the command line, you would use vcom with the -refresh argument to update VHDL
design units in a library, and vlog with the -refresh argument to update Verilog design units. By
default, the work library is updated. Use either vcom or vlog with the -work
argument to update a different library. For example, if you have a library named mylib that
contains both VHDL and Verilog design units:
vcom -work mylib -refresh
vlog -work mylib -refresh
Note
You may specify a specific design unit name with the -refresh argument to vcom and
vlog in order to regenerate a library image for only that design, but you may not specify a
file name.
An important feature of -refresh is that it rebuilds the library image without using source code.
This means that models delivered as compiled libraries without source code can be rebuilt for a
specific release of ModelSim. In general, this works for moving forwards or backwards on a
release. Moving backwards on a release may not work if the models used compiler switches,
directives, language constructs, or features that do not exist in the older release.
Note
You don't need to regenerate the std, ieee, vital22b, and verilog libraries. Also, you
cannot use the -refresh option to update libraries that were built before the 4.6 release.
Importing FPGA Libraries
ModelSim includes an import wizard for referencing and using vendor FPGA libraries. The
wizard scans for and enforces dependencies in the libraries and determines the correct mappings
and target directories.
Note
The FPGA libraries you import must be pre-compiled. Most FPGA vendors supply precompiled libraries configured for use with ModelSim.
To import an FPGA library, select File > Import > Library.
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Figure 5-4. Import Library Wizard
Follow the instructions in the wizard to complete the import.
Protecting Source Code
The Protecting Your Source Code chapter provides details about protecting your internal model
data. This allows a model supplier to provide pre-compiled libraries without providing source
code and without revealing internal model variables and structure.
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Chapter 6
VHDL Simulation
This chapter covers the following topics related to using VHDL in a ModelSim design:
•
Basic VHDL Usage — A brief outline of the steps for using VHDL in a ModelSim
design.
•
Compilation and Simulation of VHDL — How to compile, optimize, and simulate a
VHDL design
•
•
Using the TextIO Package — Using the TextIO package provided with ModelSim
•
VHDL Utilities Package (util) — Using the special built-in utilities package (Util
Package) provided with ModelSim
•
Modeling Memory — The advantages of using VHDL variables or protected types
instead of signals for memory designs.
VITAL Usage and Compliance — Implementation of the VITAL (VHDL Initiative
Towards ASIC Libraries) specification for ASIC modeling
Basic VHDL Usage
Simulating VHDL designs with ModelSim consists of the following general steps:
1. Compile your VHDL code into one or more libraries using the vcom command. Refer to
Compiling a VHDL Design—the vcom Command for more information.
2. Load your design with the vsim command. Refer to Simulating a VHDL Design.
3. Simulate the loaded design, then debug as needed.
Compilation and Simulation of VHDL
Creating a Design Library for VHDL
Before you can compile your VHDL source files, you must create a library in which to store the
compilation results. Use vlib to create a new library. For example:
vlib work
This creates a library named work. By default, compilation results are stored in the work library.
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The work library is actually a subdirectory named work. This subdirectory contains a special
file named _info. Do not create a VHDL library as a directory by using a UNIX, Linux,
Windows, or DOS command—always use the vlib command.
See Design Libraries for additional information on working with VHDL libraries.
Compiling a VHDL Design—the vcom Command
ModelSim compiles one or more VHDL design units with a single invocation of the vcom
command, the VHDL compiler. The design units are compiled in the order that they appear on
the command line. For VHDL, the order of compilation is important—you must compile any
entities or configurations before an architecture that references them.
You can simulate a design written with the following versions of VHDL:
•
•
•
•
1076-1987
1076-1993
1076-2002
1076-2008
To do so you need to compile units from each VHDL version separately.
The vcom command compiles using 1076 -2002 rules by default; use the -87, -93, or -2008
arguments to vcom to compile units written with version 1076-1987, 1076 -1993, or 1076-2008
respectively. You can also change the default by modifying the VHDL93 variable in the
modelsim.ini file (see modelsim.ini Variables for more information).
Note
Only a limited number of VHDL 1076-2008 constructs are currently supported.
Dependency Checking
You must re-analyze dependent design units when you change the design units they depend on
in the library. The vcom command determines whether or not the compilation results have
changed.
For example, if you keep an entity and its architectures in the same source file and you modify
only an architecture and recompile the source file, the entity compilation results will remain
unchanged. This means you do not have to recompile design units that depend on the entity.
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VHDL Case Sensitivity
VHDL is a case-insensitive language for all basic identifiers. For example, clk and CLK are
regarded as the same name for a given signal or variable. This differs from Verilog and
SystemVerilog, which are case-sensitive.
The vcom command preserves both uppercase and lowercase letters of all user-defined object
names in a VHDL source file.
Usage Notes
•
You can make the vcom command convert uppercase letters to lowercase by either of
the following methods:
o
Use the -lower argument with the vcom command.
o
Set the PreserveCase variable to 0 in your modelsim.ini file.
•
The supplied precompiled packages in STD and IEEE have their case preserved. This
results in slightly different version numbers for these packages. As a result, you may
receive out-of-date reference messages when refreshing to the current release. To
resolve this, use vcom -force_refresh instead of vcom -refresh.
•
Mixed language interactions
o
Design unit names — Because VHDL and Verilog design units are mixed in the
same library, VHDL design units are treated as if they are lowercase. This is for
compatibility with previous releases. This also to provide consistent filenames in the
file system for make files and scripts.
o
Verilog packages compiled with -mixedsvvh — not affected by VHDL uppercase
conversion.
o
VHDL packages compiled with -mixedsvvh — not affected by VHDL uppercase
conversion; VHDL basic identifiers are still converted to lowercase for compatibility
with previous releases.
o
FLI — Functions that return names of an object will not have the original case
unless the source is compiled using vcom -lower. Port and Generic names in the
mtiInterfaceListT structure are converted to lowercase to provide compatibility with
programs doing case sensitive comparisons (strcmp) on the generic and port names.
How Case Affects Default Binding
The following rules describe how ModelSim handles uppercase and lowercase names in default
bindings.
1. All VHDL names are case-insensitive, so ModelSim always stores them in the library in
lowercase to be consistent and compatible with older releases.
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2. When looking for a design unit in a library, ModelSim ignores the VHDL case and looks
first for the name in lowercase. If present, ModelSim uses it.
3. If no lowercase version of the design unit name exists in the library, then ModelSim
checks the library, ignoring case.
a. If ONE match is found this way, ModelSim selects that design unit.
b. If NO matches or TWO or more matches are found, ModelSim does not select
anything.
The following examples demonstrate these rules. Here, the VHDL compiler needs to find a
design unit named Test. Because VHDL is case-insensitive, ModelSim looks for "test" because
previous releases always converted identifiers to lowercase.
Example 1
Consider the following library:
work
entity test
Module TEST
The VHDL entity test is selected because it is stored in the library in lowercase. The original
VHDL could have contained TEST, Test, or TeSt, but the library always has the entity as "test."
Example 2
Consider the following library:
work
Module Test
No design unit named "test" exists, but "Test" matches when case is ignored, so ModelSim
selects it.
Example 3
Consider the following library:
work
Module Test
Module TEST
No design unit named "test" exists, but both "Test" and "TEST" match when case is ignored, so
ModelSim does not select either one.
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Range and Index Checking
A range check verifies that a scalar value defined with a range subtype is always assigned a
value within its range. An index check verifies that whenever an array subscript expression is
evaluated, the subscript will be within the array's range.
Range and index checks are performed by default when you compile your design. You can
disable range checks (potentially offering a performance advantage) and index checks using
arguments to the vcom command. Or, you can use the NoRangeCheck and NoIndexCheck
variables in the modelsim.ini file to specify whether or not they are performed. See
modelsim.ini Variables.
Range checks in ModelSim are slightly more restrictive than those specified by the VHDL
Language Reference Manual (LRM). ModelSim requires any assignment to a signal to also be
in range whereas the LRM requires only that range checks be done whenever a signal is
updated. Most assignments to signals update the signal anyway, and the more restrictive
requirement allows ModelSim to generate better error messages.
Subprogram Inlining
ModelSim attempts to inline subprograms at compile time to improve simulation performance.
This happens automatically and should be largely transparent. However, you can disable
automatic inlining two ways:
•
•
Invoke vcom with the -O0 or -O1 argument
Use the mti_inhibit_inline attribute as described below
Single-stepping through a simulation varies slightly, depending on whether inlining occurred.
When single-stepping to a subprogram call that has not been inlined, the simulator stops first at
the line of the call, and then proceeds to the line of the first executable statement in the called
subprogram. If the called subprogram has been inlined, the simulator does not first stop at the
subprogram call, but stops immediately at the line of the first executable statement.
mti_inhibit_inline Attribute
You can disable inlining for individual design units (a package, architecture, or entity) or
subprograms with the mti_inhibit_inline attribute. Follow these rules to use the attribute:
•
Declare the attribute within the design unit's scope as follows:
attribute mti_inhibit_inline : boolean;
•
Assign the value true to the attribute for the appropriate scope. For example, to inhibit
inlining for a particular function (for example, "foo"), add the following attribute
assignment:
attribute mti_inhibit_inline of foo : procedure is true;
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To inhibit inlining for a particular package (for example, "pack"), add the following
attribute assignment:
attribute mti_inhibit_inline of pack : package is true;
Do similarly for entities and architectures.
Simulating a VHDL Design
A VHDL design is ready for simulation after it has been compiled with vcom. You can then use
the vsim command to invoke the simulator with the name of the configuration or
entity/architecture pair.
Note
This section discusses simulation from the UNIX or Windows/DOS command line. You
can also use a project to simulate (see Getting Started with Projects) or the Start
Simulation dialog box (open with Simulate > Start Simulation menu selection).
This example begins simulation on a design unit with an entity named my_asic and an
architecture named structure:
vsim my_asic structure
Timing Specification
The vsim command can annotate a design using VITAL-compliant models with timing data
from an SDF file. You can specify delay by invoking vsim with the -sdfmin, -sdftyp, or -sdfmax
arguments. The following example uses an SDF file named f1.sdf in the current work directory,
and an invocation of vsim annotating maximum timing values for the design unit my_asic:
vsim -sdfmax /my_asic=f1.sdf my_asic
By default, the timing checks within VITAL models are enabled. You can disable them with the
+notimingchecks argument. For example:
vsim +notimingchecks topmod
If you specify vsim +notimingchecks, the generic TimingChecksOn is set to FALSE for all
VITAL models with the Vital_level0 or Vital_level1 attribute (refer to VITAL Usage and
Compliance). Setting this generic to FALSE disables the actual calls to the timing checks along
with anything else that is present in the model's timing check block. In addition, if these models
use the generic TimingChecksOn to control behavior beyond timing checks, this behavior will
not occur. This can cause designs to simulate differently and provide different results.
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Naming Behavior of VHDL For Generate Blocks
A VHDL for … generate statement, when elaborated in a design, places a given number of
for … generate equivalent blocks into the scope in which the statement exists; either an
architecture, a block, or another generate block. The simulator constructs a design path name for
each of these for … generate equivalent blocks based on the original generate statement's label
and the value of the generate parameter for that particular iteration. For example, given the
following code:
g1: for I in 1 to Depth generate
L: BLK port map (A(I), B(I+1));
end generate g1
the default names of the blocks in the design hierarchy would be:
g1(1), g1(2), ...
This name appears in the GUI to identify the blocks. You should use this name with any
commands when referencing a block that is part of the simulation environment. The format of
the name is based on the VHDL Language Reference Manual P1076-2008 section 16.2.5
Predefined Attributes of Named Entities.
If the type of the generate parameter is an enumeration type, the value within the parenthesis
will be an enumeration literal of that type; such as: g1(red).
For mixed-language designs, in which a Verilog hierarchical reference is used to reference
something inside a VHDL for … generate equivalent block, the parentheses are replaced with
brackets ( [] ) to match Verilog syntax. If the name is dependent upon enumeration literals, the
literal will be replaced with its position number because Verilog does not support using
enumerated literals in its for … generate equivalent block.
In releases prior to the 6.6 series, this default name was controlled by the GenerateFormat
modelsim.ini file variable would have appeared as:
g1__1, g1__2, ...
All previously-generated scripts using this old format should work by default. However, if not,
you can use the GenerateFormat and OldVhdlForGenNames modelsim.ini variables to ensure
that the old and current names are mapped correctly.
Differences Between Versions of VHDL
There are four versions of the VHDL standard (IEEE Std 1076): 1076-1987, 1076-1993,
1076-2002, and 1076-2008. The default language version supported for ModelSim is 10762002.
If your code was written according to the 1987, 1993, or 2008 version, you may need to update
your code or instruct ModelSim to use rules for different version.
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To select a specific language version, do one of the following:
•
•
•
Select the appropriate version from the compiler options menu in the GUI
Invoke vcom using the argument -87, -93, -2002, or -2008.
Set the VHDL93 variable in the [vcom] section of the modelsim.ini file to one of the
following values:
- 0, 87, or 1987 for 1076-1987
- 1, 93, or 1993 for 1076-1993
- 2, 02, or 2002 for 1076-2002
- 3, 08, or 2008 for 1076-2008
The following is a list of language incompatibilities that may cause problems when compiling a
design.
Tip: Please refer to ModelSim Release Notes for the most current and comprehensive
description of differences between supported versions of the VHDL standard.
•
VHDL-93 and VHDL-2002 — The only major problem between VHDL-93 and VHDL2002 is the addition of the keyword "PROTECTED". VHDL-93 programs which use
this as an identifier should choose a different name.
All other incompatibilities are between VHDL-87 and VHDL-93.
•
VITAL and SDF — It is important to use the correct language version for VITAL.
VITAL2000 must be compiled with VHDL-93 or VHDL-2002. VITAL95 must be
compiled with VHDL-87. A typical error message that indicates the need to compile
under language version VHDL-87 is:
"VITALPathDelay DefaultDelay parameter must be locally static"
•
Purity of NOW — In VHDL-93 the function "now" is impure. Consequently, any
function that invokes "now" must also be declared to be impure. Such calls to "now"
occur in VITAL. A typical error message:
"Cannot call impure function 'now' from inside pure function
''"
•
Files — File syntax and usage changed between VHDL-87 and VHDL-93. In many
cases vcom issues a warning and continues:
"Using 1076-1987 syntax for file declaration."
In addition, when files are passed as parameters, the following warning message is
produced:
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"Subprogram parameter name is declared using VHDL 1987 syntax."
This message often involves calls to endfile() where is a file parameter.
•
Files and packages — Each package header and body should be compiled with the same
language version. Common problems in this area involve files as parameters and the size
of type CHARACTER. For example, consider a package header and body with a
procedure that has a file parameter:
procedure proc1 ( out_file : out std.textio.text) ...
If you compile the package header with VHDL-87 and the body with VHDL-93 or
VHDL-2002, you will get an error message such as:
"** Error: mixed_package_b.vhd(4): Parameter kinds do not conform
between declarations in package header and body: 'out_file'."
•
Direction of concatenation — To solve some technical problems, the rules for direction
and bounds of concatenation were changed from VHDL-87 to VHDL-93. You won't see
any difference in simple variable/signal assignments such as:
v1 := a & b;
But if you (1) have a function that takes an unconstrained array as a parameter, (2) pass
a concatenation expression as a formal argument to this parameter, and (3) the body of
the function makes assumptions about the direction or bounds of the parameter, then you
will get unexpected results. This may be a problem in environments that assume all
arrays have "downto" direction.
•
xnor — "xnor" is a reserved word in VHDL-93. If you declare an xnor function in
VHDL-87 (without quotes) and compile it under VHDL-2002, you will get an error
message like the following:
** Error: xnor.vhd(3): near "xnor": expecting: STRING IDENTIFIER
•
'FOREIGN attribute — In VHDL-93 package STANDARD declares an attribute
'FOREIGN. If you declare your own attribute with that name in another package, then
ModelSim issues a warning such as the following:
-- Compiling package foopack
** Warning: foreign.vhd(9): (vcom-1140) VHDL-1993 added a definition
of the attribute foreign to package std.standard. The attribute is
also defined in package 'standard'. Using the definition from
package 'standard'.
•
Size of CHARACTER type — In VHDL-87 type CHARACTER has 128 values; in
VHDL-93 it has 256 values. Code which depends on this size will behave incorrectly.
This situation occurs most commonly in test suites that check VHDL functionality. It's
unlikely to occur in practical designs. A typical instance is the replacement of warning
message:
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"range nul downto del is null"
by
"range nul downto 'ÿ' is null" -- range is nul downto y(umlaut)
•
bit string literals — In VHDL-87 bit string literals are of type bit_vector. In VHDL-93
they can also be of type STRING or STD_LOGIC_VECTOR. This implies that some
expressions that are unambiguous in VHDL-87 now become ambiguous is VHDL-93. A
typical error message is:
** Error: bit_string_literal.vhd(5): Subprogram '=' is ambiguous.
Suitable definitions exist in packages 'std_logic_1164' and
'standard'.
•
Sub-element association — In VHDL-87 when using individual sub-element association
in an association list, associating individual sub-elements with NULL is discouraged. In
VHDL-93 such association is forbidden. A typical message is:
"Formal '' must not be associated with OPEN when subelements
are associated individually."
•
VHDL-2008 packages — ModelSim does not provide VHDL source for VHDL-2008
IEEE-defined standard packages because of copyright restrictions. You can obtain
VHDL source from http://standards.ieee.org//downloads/1076/1076-2008/ for the
following packages:
IEEE.fixed_float_types
IEEE.fixed_generic_pkg
IEEE.fixed_pkg
IEEE.float_generic_pkg
IEEE.float_pkg
IEEE.MATH_REAL
IEEE.MATH_COMPLEX
IEEE.NUMERIC_BIT
IEEE.NUMERIC_BIT_UNSIGNED
IEEE.NUMERIC_STD
IEEE.NUMERIC_STD_UNSIGNED
IEEE.std_logic_1164
IEEE.std_logic_textio
Simulator Resolution Limit for VHDL
The simulator internally represents time as a 64-bit integer in units equivalent to the smallest
unit of simulation time, also known as the simulator resolution limit. The default resolution
limit is set to the value specified by the Resolution variable in the modelsim.ini file. You can
view the current resolution by invoking the report command with the simulator state argument.
Note
In Verilog, this representation of time units is referred to as precision or timescale.
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Overriding the Resolution
To override the default resolution of ModelSim, specify a value for the -t argument of the vsim
command line or select a different Simulator Resolution in the Simulate dialog box. Available
values of simulator resolution are:
1 fs, 10 fs, 100 fs
1 ps, 10 ps, 100 ps
1 ns, 10 ns, 100 ns
1 us, 10 us, 100 us
1 ms, 10 ms, 100 ms
1 s, 10 s, 100 s
For example, the following command sets resolution to 10 ps:
vsim -t 10ps topmod
Note that you need to take care in specifying a resolution value larger than a delay value in your
design—delay values in that design unit are rounded to the closest multiple of the resolution. In
the example above, a delay of 4 ps would be rounded down to 0 ps.
Choosing the Resolution for VHDL
You should specify the coarsest value for time resolution that does not result in undesired
rounding of your delay times. The resolution value should not be unnecessarily small because it
decreases the maximum simulation time limit and can cause longer simulations.
Default Binding
By default, ModelSim performs binding when you load the design with vsim. The advantage of
this default binding at load time is that it provides more flexibility for compile order. Namely,
VHDL entities don't necessarily have to be compiled before other entities/architectures that
instantiate them.
However, you can force ModelSim to perform default binding at compile time instead. This
may allow you to catch design errors (for example, entities with incorrect port lists) earlier in
the flow. Use one of these two methods to change when default binding occurs:
•
•
Specify the -bindAtCompile argument to vcom
Set the BindAtCompile variable in the modelsim.ini to 1 (true)
Default Binding Rules
When searching for a VHDL entity to bind with, ModelSim searches the currently visible
libraries for an entity with the same name as the component. ModelSim does this because IEEE
Std 1076-1987 contained a flaw that made it almost impossible for an entity to be directly
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visible if it had the same name as the component. This meant if a component was declared in an
architecture, any entity with the same name above that declaration would be hidden because
component/entity names cannot be overloaded. As a result, ModelSim observes the following
rules for determining default binding:
•
If performing default binding at load time, search the libraries specified with the -Lf
argument to vsim.
•
•
•
If a directly visible entity has the same name as the component, use it.
If an entity would be directly visible in the absence of the component declaration, use it.
If the component is declared in a package, search the library that contained the package
for an entity with the same name.
If none of these methods is successful, ModelSim then does the following:
•
•
•
Search the work library.
Search all other libraries that are currently visible by means of the library clause.
If performing default binding at load time, search the libraries specified with the -L
argument to vsim.
Note that these last three searches are an extension to the 1076 standard.
Disabling Default Binding
If you want default binding to occur using only configurations, you can disable normal default
binding methods by setting the RequireConfigForAllDefaultBinding variable in the
modelsim.ini file to 1 (true).
Delta Delays
Event-based simulators such as ModelSim may process many events at a given simulation time.
Multiple signals may need updating, statements that are sensitive to these signals must be
executed, and any new events that result from these statements must then be queued and
executed as well. The steps taken to evaluate the design without advancing simulation time are
referred to as "delta times" or just "deltas."
The diagram below represents the process for VHDL designs. This process continues until the
end of simulation time.
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Figure 6-1. VHDL Delta Delay Process
Execute concurrent
statements at
current time
Advance simulation
time
Advance delta time
No
Any transactions to
process?
Yes
Any events to
process?
No
Yes
Execute concurrent
statements that are
sensitive to events
This mechanism in event-based simulators may cause unexpected results. Consider the
following code fragment:
clk2 <= clk;
process (rst, clk)
begin
if(rst = '0')then
s0 <= '0';
elsif(clk'event and clk='1') then
s0 <= inp;
end if;
end process;
process (rst, clk2)
begin
if(rst = '0')then
s1 <= '0';
elsif(clk2'event and clk2='1') then
s1 <= s0;
end if;
end process;
In this example you have two synchronous processes, one triggered with clk and the other with
clk2. To your surprise, the signals change in the clk2 process on the same edge as they are set in
the clk process. As a result, the value of inp appears at s1 rather than s0.
During simulation an event on clk occurs (from the test bench). From this event ModelSim
performs the "clk2 <= clk" assignment and the process which is sensitive to clk. Before
advancing the simulation time, ModelSim finds that the process sensitive to clk2 can also be
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run. Since there are no delays present, the effect is that the value of inp appears at s1 in the same
simulation cycle.
In order to get the expected results, you must do one of the following:
•
•
•
Insert a delay at every output
Make certain to use the same clock
Insert a delta delay
To insert a delta delay, you would modify the code like this:
process (rst, clk)
begin
if(rst = ’0’)then
s0 <= ’0’;
elsif(clk’event and clk=’1’) then
s0 <= inp;
end if;
end process;
s0_delayed <= s0;
process (rst, clk2)
begin
if(rst = ’0’)then
s1 <= ’0’;
elsif(clk2’event and clk2=’1’) then
s1 <= s0_delayed;
end if;
end process;
The best way to debug delta delay problems is observe your signals in the List window. There
you can see how values change at each delta time.
Detecting Infinite Zero-Delay Loops
If a large number of deltas occur without advancing time, it is usually a symptom of an infinite
zero-delay loop in the design. In order to detect the presence of these loops, ModelSim defines a
limit, the “iteration limit", on the number of successive deltas that can occur. When ModelSim
reaches the iteration limit, it issues a warning message.
The iteration limit default value is 1000. If you receive an iteration limit warning, first increase
the iteration limit and try to continue simulation. You can set the iteration limit from the
Simulate > Runtime Options menu or by modifying the IterationLimit variable in the
modelsim.ini. See modelsim.ini Variables for more information on modifying the modelsim.ini
file.
If the problem persists, look for zero-delay loops. Run the simulation and look at the source
code when the error occurs. Use the step button to step through the code and see which signals
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or variables are continuously oscillating. Two common causes are a loop that has no exit, or a
series of gates with zero delay where the outputs are connected back to the inputs.
Using the TextIO Package
The TextIO package is defined within the IEEE Std 1076-2002, IEEE Standard VHDL
Language Reference Manual. This package allows human-readable text input from a declared
source within a VHDL file during simulation.
To access the routines in TextIO, include the following statement in your VHDL source code:
USE std.textio.all;
A simple example using the package TextIO is:
USE std.textio.all;
ENTITY simple_textio IS
END;
ARCHITECTURE simple_behavior OF simple_textio IS
BEGIN
PROCESS
VARIABLE i: INTEGER:= 42;
VARIABLE LLL: LINE;
BEGIN
WRITE (LLL, i);
WRITELINE (OUTPUT, LLL);
WAIT;
END PROCESS;
END simple_behavior;
Syntax for File Declaration
The VHDL 1987 syntax for a file declaration is:
file identifier : subtype_indication is [ mode ]
file_logical_name ;
where "file_logical_name" must be a string expression.
In newer versions of the 1076 spec, syntax for a file declaration is:
file identifier_list : subtype_indication [ file_open_information ] ;
where "file_open_information" is:
[open file_open_kind_expression] is file_logical_name
You can specify a full or relative path as the file_logical_name; for example (VHDL 1987):
file filename : TEXT is in "usr\rick\myfile";
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Normally if a file is declared within an architecture, process, or package, the file is opened when
you start the simulator and is closed when you exit from it. If a file is declared in a subprogram,
the file is opened when the subprogram is called and closed when execution RETURNs from
the subprogram. Alternatively, the opening of files can be delayed until the first read or write by
setting the DelayFileOpen variable in the modelsim.ini file. Also, the number of concurrently
open files can be controlled by the ConcurrentFileLimit variable. These variables help you
manage a large number of files during simulation. See modelsim.ini Variables for more details.
Using STD_INPUT and STD_OUTPUT Within ModelSim
The standard VHDL1987 TextIO package contains the following file declarations:
file input: TEXT is in "STD_INPUT";
file output: TEXT is out "STD_OUTPUT";
Updated versions of the TextIO package contain these file declarations:
file input: TEXT open read_mode is "STD_INPUT";
file output: TEXT open write_mode is "STD_OUTPUT";
STD_INPUT is a file_logical_name that refers to characters that are entered interactively from
the keyboard, and STD_OUTPUT refers to text that is displayed on the screen.
In ModelSim, reading from the STD_INPUT file allows you to enter text into the current buffer
from a prompt in the Transcript pane. The lines written to the STD_OUTPUT file appear in the
Transcript.
TextIO Implementation Issues
Writing Strings and Aggregates
A common error in VHDL source code occurs when a call to a WRITE procedure does not
specify whether the argument is of type STRING or BIT_VECTOR. For example, the VHDL
procedure:
WRITE (L, "hello");
will cause the following error:
ERROR: Subprogram "WRITE" is ambiguous.
In the TextIO package, the WRITE procedure is overloaded for the types STRING and
BIT_VECTOR. These lines are reproduced here:
procedure WRITE(L: inout LINE; VALUE: in BIT_VECTOR;
JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
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procedure WRITE(L: inout LINE; VALUE: in STRING;
JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
The error occurs because the argument "hello" could be interpreted as a string or a bit vector,
but the compiler is not allowed to determine the argument type until it knows which function is
being called.
The following procedure call also generates an error:
WRITE (L, "010101");
This call is even more ambiguous, because the compiler could not determine, even if allowed to,
whether the argument "010101" should be interpreted as a string or a bit vector.
There are two possible solutions to this problem:
•
Use a qualified expression to specify the type, as in:
WRITE (L, string’("hello"));
•
Call a procedure that is not overloaded, as in:
WRITE_STRING (L, "hello");
The WRITE_STRING procedure simply defines the value to be a STRING and calls the
WRITE procedure, but it serves as a shell around the WRITE procedure that solves the
overloading problem. For further details, refer to the WRITE_STRING procedure in the io_utils
package, which is located in the file
/modeltech/examples/vhdl/io_utils/io_utils.vhd.
Reading and Writing Hexadecimal Numbers
The reading and writing of hexadecimal numbers is not specified in standard VHDL. The Issues
Screening and Analysis Committee of the VHDL Analysis and Standardization Group (ISACVASG) has specified that the TextIO package reads and writes only decimal numbers.
To expand this functionality, ModelSim supplies hexadecimal routines in the package io_utils,
which is located in the file /modeltech/examples/gui/io_utils.vhd. To use these
routines, compile the io_utils package and then include the following use clauses in your VHDL
source code:
use std.textio.all;
use work.io_utils.all;
Dangling Pointers
Dangling pointers are easily created when using the TextIO package, because WRITELINE deallocates the access type (pointer) that is passed to it. Following are examples of good and bad
VHDL coding styles:
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Bad VHDL (because L1 and L2 both point to the same buffer):
READLINE (infile, L1);
L2 := L1;
WRITELINE (outfile, L1);
-- Read and allocate buffer
-- Copy pointers
-- Deallocate buffer
Good VHDL (because L1 and L2 point to different buffers):
READLINE (infile, L1);
L2 := new string’(L1.all);
WRITELINE (outfile, L1);
-- Read and allocate buffer
-- Copy contents
-- Deallocate buffer
The ENDLINE Function
The ENDLINE function — described in the IEEE Std 1076-2002, IEEE Standard VHDL
Language Reference Manual — contains invalid VHDL syntax and cannot be implemented in
VHDL. This is because access values must be passed as variables, but functions do not allow
variable parameters.
Based on an ISAC-VASG recommendation the ENDLINE function has been removed from the
TextIO package. The following test may be substituted for this function:
(L = NULL) OR (L’LENGTH = 0)
The ENDFILE Function
In the VHDL Language Reference Manuals, the ENDFILE function is listed as:
-- function ENDFILE (L: in TEXT) return BOOLEAN;
As you can see, this function is commented out of the standard TextIO package. This is because
the ENDFILE function is implicitly declared, so it can be used with files of any type, not just
files of type TEXT.
Using Alternative Input/Output Files
You can use the TextIO package to read and write to your own files. To do this, just declare an
input or output file of type TEXT. For example, for an input file:
The VHDL1987 declaration is:
file myinput : TEXT is in "pathname.dat";
The VHDL1993 declaration is:
file myinput : TEXT open read_mode is "pathname.dat";
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Then include the identifier for this file ("myinput" in this example) in the READLINE or
WRITELINE procedure call.
Flushing the TEXTIO Buffer
Flushing of the TEXTIO buffer is controlled by the UnbufferedOutput variable in the
modelsim.ini file.
Providing Stimulus
You can provide an input stimulus to a design by reading data vectors from a file and assigning
their values to signals. You can then verify the results of this input. A VHDL test bench has
been included with the ModelSim install files as an example. Check for this file:
/examples/gui/stimulus.vhd
VITAL Usage and Compliance
The VITAL (VHDL Initiative Towards ASIC Libraries) modeling specification is sponsored by
the IEEE to promote the development of highly accurate, efficient simulation models for ASIC
(Application-Specific Integrated Circuit) components in VHDL.
The IEEE Std 1076.4-2000, IEEE Standard for VITAL ASIC Modeling Specification is available
from the Institute of Electrical and Electronics Engineers, Inc.
IEEE Customer Service
445 Hoes Lane
Piscataway, NJ 08854-1331
Tel: (732) 981-0060
Fax: (732) 981-1721
http://www.ieee.org
VITAL Source Code
The source code for VITAL packages is provided in the following ModelSim installation
directories:
//vhdl_src/vital22b
/vital95
/vital2000
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VITAL 1995 and 2000 Packages
VITAL 2000 accelerated packages are pre-compiled into the ieee library in the installation
directory. VITAL 1995 accelerated packages are pre-compiled into the vital1995 library. If you
need to use the older library, you either need to change the ieee library mapping or add a use
clause to your VHDL code to access the VITAL 1995 packages.
To change the ieee library mapping, issue the following command:
vmap ieee /vital1995
Or, alternatively, add use clauses to your code:
LIBRARY vital1995;
USE vital1995.vital_primitives.all;
USE vital1995.vital_timing.all;
USE vital1995.vital_memory.all;
Note that if your design uses two libraries—one that depends on vital95 and one that depends
on vital2000—then you will have to change the references in the source code to vital2000.
Changing the library mapping will not work.
ModelSim VITAL built-ins are generally updated as new releases of the VITAL packages
become available.
VITAL Compliance
A simulator is VITAL-compliant if it implements the SDF mapping and if it correctly simulates
designs using the VITAL packages—as outlined in the VITAL Model Development
Specification. ModelSim is compliant with IEEE Std 1076.4-2002, IEEE Standard for VITAL
ASIC Modeling Specification. In addition, ModelSim accelerates the VITAL_Timing,
VITAL_Primitives, and VITAL_memory packages. The optimized procedures are functionally
equivalent to the IEEE Std 1076.4 VITAL ASIC Modeling Specification (VITAL 1995 and
2000).
VITAL Compliance Checking
If you are using VITAL 2.2b, you must turn off the compliance checking either by not setting
the attributes, or by invoking vcom with the argument -novitalcheck.
Compiling and Simulating with Accelerated VITAL
Packages
The vcom command automatically recognizes that a VITAL function is being referenced from
the ieee library and generates code to call the optimized built-in routines.
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Invoke vcom with the -novital argument if you do not want to use the built-in VITAL routines
(when debugging for instance). To exclude all VITAL functions, use -novital all:
vcom -novital all design.vhd
To exclude selected VITAL functions, use one or more -novital arguments:
vcom -novital VitalTimingCheck -novital VitalAND design.vhd
The -novital switch only affects calls to VITAL functions from the design units currently being
compiled. Pre-compiled design units referenced from the current design units will still call the
built-in functions unless they too are compiled with the -novital argument.
VHDL Utilities Package (util)
The util package contains various VHDL utilities that you can run as commands. The package is
part of the modelsim_lib library, which is located in the /modeltech tree and is mapped in the
default modelsim.ini file.
To include the utilities in this package, add the following lines similar to your VHDL code:
library modelsim_lib;
use modelsim_lib.util.all;
get_resolution
The get_resolution utility returns the current simulator resolution as a real number. For
example, a resolution of 1 femtosecond (1 fs) corresponds to 1e-15.
Syntax
resval := get_resolution;
Returns
Name
Type
Description
resval
real
The simulator resolution represented as a
real
Arguments
None
Related functions
•
•
to_real()
to_time()
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Example
If the simulator resolution is set to 10ps, and you invoke the command:
resval := get_resolution;
the value returned to resval would be 1e-11.
init_signal_driver()
The init_signal_driver() utility drives the value of a VHDL signal or Verilog net onto an
existing VHDL signal or Verilog net. This allows you to drive signals or nets at any level of the
design hierarchy from within a VHDL architecture (such as a test bench).
See init_signal_driver for complete details.
init_signal_spy()
The init_signal_spy() utility mirrors the value of a VHDL signal or Verilog register/net onto an
existing VHDL signal or Verilog register. This allows you to reference signals, registers, or nets
at any level of hierarchy from within a VHDL architecture (such as a test bench).
See init_signal_spy for complete details.
signal_force()
The signal_force() utility forces the value specified onto an existing VHDL signal or Verilog
register or net. This allows you to force signals, registers, or nets at any level of the design
hierarchy from within a VHDL architecture (such as a test bench). A signal_force works the
same as the force command when you set the modelsim.ini variable named ForceSigNextIter to
1. The variable ForceSigNextIter in the modelsim.ini file can be set to honor the signal update
event in next iteration for all force types. Note that the signal_force utility cannot issue a
repeating force.
See signal_force for complete details.
signal_release()
The signal_release() utility releases any force that was applied to an existing VHDL signal or
Verilog register or net. This allows you to release signals, registers, or nets at any level of the
design hierarchy from within a VHDL architecture (such as a test bench). A signal_release
works the same as the noforce command.
See signal_release for complete details.
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to_real()
The to_real() utility converts the physical type time value into a real value with respect to the
current value of simulator resolution. The precision of the converted value is determined by the
simulator resolution. For example, if you were converting 1900 fs to a real and the simulator
resolution was ps, then the real value would be rounded to 2.0 (that is, 2 ps).
Syntax
realval := to_real(timeval);
Returns
Name
Type
Description
realval
real
The time value represented as a real with
respect to the simulator resolution
Name
Type
Description
timeval
time
The value of the physical type time
Arguments
Related functions
•
•
get_resolution
to_time()
Example
If the simulator resolution is set to ps, and you enter the following function:
realval := to_real(12.99 ns);
then the value returned to realval would be 12990.0. If you wanted the returned value to be in
units of nanoseconds (ns) instead, you would use the get_resolution function to recalculate the
value:
realval := 1e+9 * (to_real(12.99 ns)) * get_resolution();
If you wanted the returned value to be in units of femtoseconds (fs), you would enter the
function this way:
realval := 1e+15 * (to_real(12.99 ns)) * get_resolution();
to_time()
The to_time() utility converts a real value into a time value with respect to the current simulator
resolution. The precision of the converted value is determined by the simulator resolution. For
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example, if you converted 5.9 to a time and the simulator resolution was 1 ps, then the time
value would be rounded to 6 ps.
Syntax
timeval := to_time(realval);
Returns
Name
Type
Description
timeval
time
The real value represented as a physical
type time with respect to the simulator
resolution
Name
Type
Description
realval
real
The value of the type real
Arguments
Related functions
•
•
get_resolution
to_real()
Example
If the simulator resolution is set to 1 ps, and you enter the following function:
timeval := to_time(72.49);
then the value returned to timeval would be 72 ps.
Modeling Memory
If you want to model a memory with VHDL using signals, you may encounter either of the
following common problems with simulation:
•
Memory allocation error, which typically means the simulator ran out of memory and
failed to allocate enough storage.
•
Very long times to load, elaborate, or run.
These problems usually result from the fact that signals consume a substantial amount of
memory (many dozens of bytes per bit), all of which must be loaded or initialized before your
simulation starts.
As an alternative, you can model a memory design using variables or protected types instead of
signals, which provides the following performance benefits:
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•
Reduced storage required to model the memory, by as much as one or two orders of
magnitude
•
•
Reduced startup and run times
Elimination of associated memory allocation errors
Examples of Different Memory Models
Example 6-1 shown below uses different VHDL architectures for the entity named memory to
provide the following models for storing RAM:
•
•
•
bad_style_87 — uses a VHDL signal
style_87 — uses variables in the memory process
style_93 — uses variables in the architecture
For large memories, the run time for architecture bad_style_87 is many times longer than the
other two and uses much more memory. Because of this, you should avoid using VHDL signals
to model memory.
To implement this model, you will need functions that convert vectors to integers. To use it, you
will probably need to convert integers to vectors.
Converting an Integer Into a bit_vector
The following code shows how to convert an integer variable into a bit_vector.
library ieee;
use ieee.numeric_bit.ALL;
entity test is
end test;
architecture only of test is
signal s1 : bit_vector(7 downto 0);
signal int : integer := 45;
begin
p:process
begin
wait for 10 ns;
s1 <= bit_vector(to_signed(int,8));
end process p;
end only;
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Examples Using VHDL1987, VHDL1993, VHDL2002 Architectures
•
Example 6-1 contains two VHDL architectures that demonstrate recommended memory
models: style_93 uses shared variables as part of a process, style_87 uses For
comparison, a third architecture, bad_style_87, shows the use of signals.
The style_87 and style_93 architectures work with equal efficiency for this example.
However, VHDL 1993 offers additional flexibility because the RAM storage can be
shared among multiple processes. In the example, a second process is shown that
initializes the memory; you could add other processes to create a multi-ported memory.
•
Example 6-2 is a package (named conversions) that is included by the memory model in
Example 6-1.
•
For completeness, Example 6-3 shows protected types using VHDL 2002. Note that
using protected types offers no advantage over shared variables.
Example 6-1. Memory Model Using VHDL87 and VHDL93 Architectures
Example functions are provided below in package “conversions.”
-------------------------------------------------------------------------- Source:
memory.vhd
-- Component: VHDL synchronous, single-port RAM
-- Remarks:
Provides three different architectures
------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use work.conversions.all;
entity memory is
generic(add_bits : integer := 12;
data_bits : integer := 32);
port(add_in : in std_ulogic_vector(add_bits-1 downto 0);
data_in : in std_ulogic_vector(data_bits-1 downto 0);
data_out : out std_ulogic_vector(data_bits-1 downto 0);
cs, mwrite : in std_ulogic;
do_init : in std_ulogic);
subtype word is std_ulogic_vector(data_bits-1 downto 0);
constant nwords : integer := 2 ** add_bits;
type ram_type is array(0 to nwords-1) of word;
end;
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architecture style_93 of memory is
-----------------------------shared variable ram : ram_type;
-----------------------------begin
memory:
process (cs)
variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) := data_in;
end if;
data_out <= ram(address);
end if;
end process memory;
-- illustrates a second process using the shared variable
initialize:
process (do_init)
variable address : natural;
begin
if rising_edge(do_init) then
for address in 0 to nwords-1 loop
ram(address) := data_in;
end loop;
end if;
end process initialize;
end architecture style_93;
architecture style_87 of memory is
begin
memory:
process (cs)
----------------------variable ram : ram_type;
----------------------variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) := data_in;
end if;
data_out <= ram(address);
end if;
end process;
end style_87;
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architecture bad_style_87 of memory is
---------------------signal ram : ram_type;
---------------------begin
memory:
process (cs)
variable address : natural := 0;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) <= data_in;
data_out <= data_in;
else
data_out <= ram(address);
end if;
end if;
end process;
end bad_style_87;
Example 6-2. Conversions Package
library ieee;
use ieee.std_logic_1164.all;
package conversions is
function sulv_to_natural(x : std_ulogic_vector) return
natural;
function natural_to_sulv(n, bits : natural) return
std_ulogic_vector;
end conversions;
package body conversions is
function sulv_to_natural(x : std_ulogic_vector) return
natural is
variable n : natural := 0;
variable failure : boolean := false;
begin
assert (x'high - x'low + 1) <= 31
report "Range of sulv_to_natural argument exceeds
natural range"
severity error;
for i in x'range loop
n := n * 2;
case x(i) is
when '1' | 'H' => n := n + 1;
when '0' | 'L' => null;
when others
=> failure := true;
end case;
end loop;
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assert not failure
report "sulv_to_natural cannot convert indefinite
std_ulogic_vector"
severity error;
if failure then
return 0;
else
return n;
end if;
end sulv_to_natural;
function natural_to_sulv(n, bits : natural) return
std_ulogic_vector is
variable x : std_ulogic_vector(bits-1 downto 0) :=
(others => '0');
variable tempn : natural := n;
begin
for i in x'reverse_range loop
if (tempn mod 2) = 1 then
x(i) := '1';
end if;
tempn := tempn / 2;
end loop;
return x;
end natural_to_sulv;
end conversions;
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Example 6-3. Memory Model Using VHDL02 Architecture
-------------------------------------------------------------------------- Source:
sp_syn_ram_protected.vhd
-- Component: VHDL synchronous, single-port RAM
-- Remarks:
Various VHDL examples: random access memory (RAM)
------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sp_syn_ram_protected IS
GENERIC (
data_width : positive := 8;
addr_width : positive := 3
);
PORT (
inclk
: IN std_logic;
outclk
: IN std_logic;
we
: IN std_logic;
addr
: IN unsigned(addr_width-1 DOWNTO 0);
data_in : IN std_logic_vector(data_width-1 DOWNTO 0);
data_out : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END sp_syn_ram_protected;
ARCHITECTURE intarch OF sp_syn_ram_protected IS
TYPE mem_type IS PROTECTED
PROCEDURE write ( data : IN std_logic_vector(data_width-1 downto 0);
addr : IN unsigned(addr_width-1 DOWNTO 0));
IMPURE FUNCTION read ( addr : IN unsigned(addr_width-1 DOWNTO 0))
RETURN
std_logic_vector;
END PROTECTED mem_type;
TYPE mem_type IS PROTECTED BODY
TYPE mem_array IS ARRAY (0 TO 2**addr_width-1) OF
std_logic_vector(data_width-1 DOWNTO 0);
VARIABLE mem : mem_array;
PROCEDURE write ( data : IN std_logic_vector(data_width-1 downto 0);
addr : IN unsigned(addr_width-1 DOWNTO 0)) IS
BEGIN
mem(to_integer(addr)) := data;
END;
IMPURE FUNCTION read ( addr : IN unsigned(addr_width-1 DOWNTO 0))
RETURN
std_logic_vector IS
BEGIN
return mem(to_integer(addr));
END;
END PROTECTED BODY mem_type;
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SHARED VARIABLE memory : mem_type;
BEGIN
ASSERT data_width <= 32
REPORT "### Illegal data width detected"
SEVERITY failure;
control_proc : PROCESS (inclk, outclk)
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
memory.write(data_in, addr);
END IF;
END IF;
IF (outclk'event AND outclk = '1') THEN
data_out <= memory.read(addr);
END IF;
END PROCESS;
END intarch;
-------------------------------------------------------------------------- Source:
ram_tb.vhd
-- Component: VHDL test bench for RAM memory example
-- Remarks:
Simple VHDL example: random access memory (RAM)
------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram_tb IS
END ram_tb;
ARCHITECTURE testbench OF ram_tb IS
-------------------------------------------- Component declaration single-port RAM
------------------------------------------COMPONENT sp_syn_ram_protected
GENERIC (
data_width : positive := 8;
addr_width : positive := 3
);
PORT (
inclk
: IN std_logic;
outclk
: IN std_logic;
we
: IN std_logic;
addr
: IN unsigned(addr_width-1 DOWNTO 0);
data_in : IN std_logic_vector(data_width-1 DOWNTO 0);
data_out : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END COMPONENT;
-------------------------------------------
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-- Intermediate signals and constants
------------------------------------------SIGNAL
addr
: unsigned(19 DOWNTO 0);
SIGNAL
inaddr
: unsigned(3 DOWNTO 0);
SIGNAL
outaddr : unsigned(3 DOWNTO 0);
SIGNAL
data_in : unsigned(31 DOWNTO 0);
SIGNAL
data_in1 : std_logic_vector(7 DOWNTO 0);
SIGNAL
data_sp1 : std_logic_vector(7 DOWNTO 0);
SIGNAL
we
: std_logic;
SIGNAL
clk
: std_logic;
CONSTANT clk_pd
: time := 100 ns;
BEGIN
---------------------------------------------------- instantiations of single-port RAM architectures.
-- All architectures behave equivalently, but they
-- have different implementations. The signal-based
-- architecture (rtl) is not a recommended style.
--------------------------------------------------spram1 : entity work.sp_syn_ram_protected
GENERIC MAP (
data_width => 8,
addr_width => 12)
PORT MAP (
inclk
=> clk,
outclk
=> clk,
we
=> we,
addr
=> addr(11 downto 0),
data_in => data_in1,
data_out => data_sp1);
-------------------------------------------- clock generator
------------------------------------------clock_driver : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_pd / 2;
LOOP
clk <= '1', '0' AFTER clk_pd / 2;
WAIT FOR clk_pd;
END LOOP;
END PROCESS;
-------------------------------------------- data-in process
------------------------------------------datain_drivers : PROCESS(data_in)
BEGIN
data_in1 <= std_logic_vector(data_in(7 downto 0));
END PROCESS;
-------------------------------------------- simulation control process
------------------------------------------ctrl_sim : PROCESS
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BEGIN
FOR i IN 0 TO 1023 LOOP
we
<= '1';
data_in <= to_unsigned(9000 + i, data_in'length);
addr
<= to_unsigned(i, addr'length);
inaddr
<= to_unsigned(i, inaddr'length);
outaddr <= to_unsigned(i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';
data_in <= to_unsigned(7 + i,
addr
<= to_unsigned(1 + i,
inaddr
<= to_unsigned(1 + i,
WAIT UNTIL clk'EVENT AND clk =
WAIT UNTIL clk'EVENT AND clk =
data_in'length);
addr'length);
inaddr'length);
'0';
'0';
data_in <= to_unsigned(3, data_in'length);
addr
<= to_unsigned(2 + i, addr'length);
inaddr
<= to_unsigned(2 + i, inaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';
data_in <= to_unsigned(30330,
addr
<= to_unsigned(3 + i,
inaddr
<= to_unsigned(3 + i,
WAIT UNTIL clk'EVENT AND clk =
WAIT UNTIL clk'EVENT AND clk =
data_in'length);
addr'length);
inaddr'length);
'0';
'0';
we
<= '0';
addr
<= to_unsigned(i, addr'length);
outaddr <= to_unsigned(i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';
addr
<= to_unsigned(1 + i,
outaddr <= to_unsigned(1 + i,
WAIT UNTIL clk'EVENT AND clk =
WAIT UNTIL clk'EVENT AND clk =
addr'length);
outaddr'length);
'0';
'0';
addr
<= to_unsigned(2 + i,
outaddr <= to_unsigned(2 + i,
WAIT UNTIL clk'EVENT AND clk =
WAIT UNTIL clk'EVENT AND clk =
addr'length);
outaddr'length);
'0';
'0';
addr
<= to_unsigned(3 + i,
outaddr <= to_unsigned(3 + i,
WAIT UNTIL clk'EVENT AND clk =
WAIT UNTIL clk'EVENT AND clk =
addr'length);
outaddr'length);
'0';
'0';
END LOOP;
ASSERT false
REPORT "### End of Simulation!"
SEVERITY failure;
END PROCESS;
END testbench;
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Affecting Performance by Cancelling Scheduled Events
Simulation performance is likely to get worse if events are scheduled far into the future but then
cancelled before they take effect. This situation acts like a memory leak and slows down
simulation.
In VHDL, this situation can occur several ways. The most common are waits with time-out
clauses and projected waveforms in signal assignments.
The following shows a wait with a time-out:
signals synch : bit := '0';
...
p: process
begin
wait for 10 ms until synch = 1;
end process;
synch <= not synch after 10 ns;
At time 0, process p makes an event for time 10ms. When synch goes to 1 at 10 ns, the event at
10 ms is marked as cancelled but not deleted, and a new event is scheduled at 10ms + 10ns. The
cancelled events are not reclaimed until time 10ms is reached and the cancelled event is
processed. As a result, there will be 500000 (10ms/20ns) cancelled but un-deleted events. Once
10ms is reached, memory will no longer increase because the simulator will be reclaiming
events as fast as they are added.
For projected waveforms, the following would behave the same way:
signals synch : bit := '0';
...
p: process(synch)
begin
output <= '0', '1' after 10ms;
end process;
synch <= not synch after 10 ns;
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Chapter 7
Verilog and SystemVerilog Simulation
This chapter describes how to compile and simulate Verilog and SystemVerilog designs with
ModelSim. This chapter covers the following topics:
•
Basic Verilog Usage — A brief outline of the steps for using Verilog in a ModelSim
design.
•
Verilog Compilation — Information on the requirements for compiling Verilog designs
and libraries.
•
•
Verilog Simulation — Information on the requirements for running simulation.
•
System Tasks and Functions — System tasks and functions that are built into the
simulator.
•
•
Compiler Directives — Verilog compiler directives supported for ModelSim.
Cell Libraries — Criteria for using Verilog cell libraries from ASIC and FPGA vendors
that are compatible with ModelSim.
Verilog PLI/VPI and SystemVerilog DPI — Verilog and SystemVerilog interfaces that
you can use to define tasks and functions that communicate with the simulator through a
C procedural interface.
Standards, Nomenclature, and Conventions
ModelSim implements the Verilog and SystemVerilog languages as defined by the following
standards:
•
•
IEEE 1364-2005 and 1364-1995 (Verilog)
IEEE 1800-2009 and 1800-2005 (SystemVerilog)
Note
ModelSim supports partial implementation of SystemVerilog IEEE Std 1800-2009.
For release-specific information on currently supported implementation, refer to the
following text file located in the ModelSim installation directory:
/docs/technotes/sysvlog.note
SystemVerilog is built “on top of” IEEE Std 1364 for the Verilog HDL and improves the
productivity, readability, and reusability of Verilog-based code. The language enhancements in
SystemVerilog provide more concise hardware descriptions, while still providing an easy route
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with existing design and verification products into current hardware implementation flows. The
enhancements also provide extensive support for directed and constrained random testbench
development, coverage-driven verification, and assertion-based verification.
The standard for SystemVerilog specifies extensions for a higher level of abstraction for
modeling and verification with the Verilog hardware description language (HDL). This
standard includes design specification methods, embedded assertions language, testbench
language including coverage and assertions application programming interface (API), and a
direct programming interface (DPI).
In this chapter, the following terms apply:
•
•
•
•
•
“Verilog” refers to IEEE Std 1364 for the Verilog HDL.
“Verilog-1995” refers to IEEE Std 1364-1995 for the Verilog HDL.
“Verilog-2001” refers to IEEE Std 1364-2001 for the Verilog HDL.
“Verilog-2005” refers to IEEE Std 1364-2005 for the Verilog HDL.
“SystemVerilog” refers to the extensions to the Verilog standard (IEEE Std 1364) as
defined in IEEE Std 1800-2009.
Note
The term “Language Reference Manual” (or LRM) is often used informally to refer to the
current IEEE standard for Verilog or SystemVerilog.
Supported Variations in Source Code
It is possible to use syntax variations of constructs that are not explicitly defined as being
supported in the Verilog LRM (such as “shortcuts” supported for similar constructs in another
language).
for Loops
ModelSim allows using Verilog syntax that omits any or all three specifications of a for loop:
initialization, termination, increment. This is similar to allowed usage in C and is shown in the
following examples.
Note
If you use this variation, a suppressible warning (2252) is displayed, which you can
change to an error if you use the vlog -pedanticerrors command.
•
Missing initializer (in order to continue where you left off):
for (; incr < foo; incr++) begin ... end
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•
Missing incrementer (in order to increment in the loop body):
for (ii = 0; ii <= foo; ) begin ... end
•
Missing initializer and terminator (in order to implement a while loop):
for (; goo < foo; ) begin ... end
•
Missing all specifications (in order to create an infinite loop):
for (;;) begin ... end
Basic Verilog Usage
Simulating Verilog designs with ModelSim consists of the following general steps:
1. Compile your Verilog code into one or more libraries using the vlog command. See
Verilog Compilation for details.
2. Load your design with the vsim command. Refer to Verilog Simulation.
3. Simulate the loaded design and debug as needed.
Verilog Compilation
The first time you compile a design there is a two-step process:
1. Create a working library with vlib or select File > New > Library.
2. Compile the design using vlog or select Compile > Compile.
Creating a Working Library
Before you can compile your design, you must create a library in which to store the compilation
results. Use the vlib command or select File > New > Library to create a new library. For
example:
vlib work
This creates a library named work. By default compilation results are stored in the work
library.
The work library is actually a subdirectory named work. This subdirectory contains a special
file named _info. Do not create libraries using UNIX commands – always use the vlib
command.
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Verilog Compilation
See Design Libraries for additional information on working with libraries.
Invoking the Verilog Compiler
The vlog command invokes the Verilog compiler, which compiles Verilog source code into
retargetable, executable code. You can simulate your design on any supported platform without
having to recompile your design; the library format is also compatible across all platforms.
As the design compiles, the resulting object code for modules and user-defined primitives
(UDPs) is generated into a library. As noted above, the compiler places results into the work
library by default. You can specify an alternate library with the -work argument of the vlog
command.
Example 7-1. Invocation of the Verilog Compiler
The following example shows how to use the vlog command to invoke the Verilog compiler:
vlog top.v +libext+.v+.u -y vlog_lib
After compiling top.v, vlog searches the vlog_lib library for files with modules with the same
name as primitives referenced, but undefined in top.v. The use of +libext+.v+.u implies
filenames with a .v or .u suffix (any combination of suffixes may be used). Only referenced
definitions are compiled.
Verilog Case Sensitivity
Note that Verilog and SystemVerilog are case-sensitive languages. For example, clk and CLK
are regarded as different names that you can apply to different signals or variables. This differs
from VHDL, which is case-insensitive.
Parsing SystemVerilog Keywords
With standard Verilog files (.v), vlog does not automatically parse SystemVerilog
keywords. SystemVerilog keywords are parsed when either of the following situations exists:
•
•
Any file within the design contains the .sv file extension
You use the -sv argument with the vlog command
The following examples of the vlog command show how to enable SystemVerilog features and
keywords in ModelSim:
vlog testbench.sv top.v memory.v cache.v
vlog -sv testbench.v proc.v
In the first example, the .sv extension for testbench automatically causes ModelSim to parse
SystemVerilog keywords. In the second example, the -sv argument enables SystemVerilog
features and keywords.
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Keyword Compatibility
One of the primary goals of SystemVerilog standardization has been to ensure full backward
compatibility with the Verilog standard. Questa recognizes all reserved keywords listed in
Table B-1 in Annex B of IEEE Std 1800-2009.
In previous ModelSim releases, the vlog command read some IEEE Std 1800-2009 keywords
and treated them as IEEE Std 1800-2005 keywords. However, those keywords are no longer
recognized in the IEEE Std 1800-2005 keyword set.
The following reserved keywords have been added since IEEE Std 1800-2005:
accept_on
reject_on
sync_accept_on
checker
restrict
sync_reject_on
endchecker
s_always
unique0
eventually
s_eventually
until
global
s_nexttime
until_with
implies
s_until
untyped
let
s_until_with
weak
nexttime
strong
If you use or produce SystemVerilog code that uses any of these strings as identifiers from a
previous release in which they were not considered reserved keywords, you can do either of the
following to avoid a compilation error:
•
Use a different set of strings in your design. You can add one or more characters as a
prefix or suffix (such as an underscore, _) to the string, which will cause the string to be
read in as an identifier and not as a reserved keyword.
•
Use the SystemVerilog pragmas `begin_keywords and `end_keywords to define
regions where only IEEE Std 1800-2005 keywords are recognized.
Recognizing SystemVerilog Files by File Name Extension
If you use the -sv argument with the vlog command, then ModelSim assumes that all input files
are SystemVerilog, regardless of their respective filename extensions.
If you do not use the -sv argument with the vlog command, then ModelSim assumes that only
files with the extension .sv, .svh, or .svp are SystemVerilog.
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File extensions of include files
Similarly, if you do not use the -sv argument while reading in a file that uses an `include
statement to specify an include file, then the file extension of the include file is ignored and the
language is assumed to be the same as the file containing the `include. For example, if you do
not use the -sv argument:
If a.v included b.sv, then b.sv would be read as a Verilog file.
If c.sv included d.v, then d.v would be read as a SystemVerilog file.
File extension settings in modelsim.ini
You can define which file extensions indicate SystemVerilog files with the SVFileExtensions
variable in the modelsim.ini file. By default, this variable is defined in modelsim.ini as follows:
; SVFileExtensions = sv svp svh
For example, the following command:
vlog a.v b.sv c.svh d.v
reads in a.v and d.v as a Verilog files and reads in b.sv and c.svh as SystemVerilog files.
File types affecting compilation units
Note that whether a file is Verilog or SystemVerilog can affect when ModelSim changes from
one compilation unit to another.
By default, ModelSim instructs the compiler to treat all files within a compilation command line
as separate compilation units (single-file compilation unit mode, which is the equivalent of
using vlog -sfcu).
vlog a.v aa.v b.sv c.svh d.v
ModelSim would group these source files into three compilation units:
Files in first unit — a.v, aa.v, b.sv
File in second unit — c.svh
File in third unit — d.v
This behavior is governed by two basic rules:
•
•
334
Anything read in is added to the current compilation unit.
A compilation unit ends at the close of a SystemVerilog file.
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Initializing enum Variables
By default, ModelSim initializes enum variables using the default value of the base type instead
of the leftmost value. However, you can change this so that ModelSim sets the initial value of
an enum variable to the left most value in the following ways:
•
•
Run vlog -enumfirstinit when compiling and run vsim -enumbaseinit when simulating.
Set EnumBaseInit = 0 in the modelsim.ini file.
Incremental Compilation
ModelSim supports incremental compilation of Verilog designs—there is no requirement to
compile an entire design in one invocation of the compiler.
You are not required to compile your design in any particular order (unless you are using
SystemVerilog packages; see Note below) because all module and UDP instantiations and
external hierarchical references are resolved when the design is loaded by the simulator.
Note
Compilation order may matter when using SystemVerilog packages. As stated in the
section Referencing data in packages of IEEE Std 1800-2005: “Packages must exist in
order for the items they define to be recognized by the scopes in which they are
imported.”
Incremental compilation is made possible by deferring these bindings, and as a result some
errors cannot be detected during compilation. Commonly, these errors include: modules that
were referenced but not compiled, incorrect port connections, and incorrect hierarchical
references.
Example 7-2. Incremental Compilation Example
Contents of testbench.sv
module testbench;
timeunit 1ns;
timeprecision 10ps;
bit d=1, clk = 0;
wire q;
initial
for (int cycles=0; cycles < 100; cycles++)
#100 clk = !clk;
design dut(q, d, clk);
endmodule
Contents of design.v:
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module design(output bit q, input bit d, clk);
timeunit 1ns;
timeprecision 10ps;
always @(posedge clk)
q = d;
endmodule
Compile the design incrementally as follows:
ModelSim> vlog testbench.sv
.
# Top level modules:
#
testbench
ModelSim> vlog -sv test1.v
.
# Top level modules:
#
dut
Note that the compiler lists each module as a top-level module, although, ultimately, only
testbench is a top-level module. If a module is not referenced by another module compiled in
the same invocation of the compiler, then it is listed as a top-level module. This is just an
informative message that you can ignore during incremental compilation.
The message is more useful when you compile an entire design in one invocation of the
compiler and need to know the top-level module names for the simulator. For example,
% vlog top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2
Top level modules:
top
Automatic Incremental Compilation with -incr
The most efficient method of incremental compilation is to manually compile only the modules
that have changed. However, this is not always convenient, especially if your source files have
compiler directive interdependencies (such as macros). In this case, you may prefer to compile
your entire design along with the -incr argument. This causes the compiler to automatically
determine which modules have changed and generate code only for those modules.
The following is an example of how to compile a design with automatic incremental
compilation:
% vlog -incr top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2
Top level modules:
top
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Now, suppose that you modify the functionality of the or2 module:
% vlog -incr top.v and2.v or2.v
-- Skipping module top
-- Skipping module and2
-- Compiling module or2
Top level modules:
top
The compiler informs you that it skipped the modules top and and2, and compiled or2.
Automatic incremental compilation is intelligent about when to compile a module. For
example, changing a comment in your source code does not result in a recompile; however,
changing the compiler command line arguments results in a recompile of all modules.
Note
Changes to your source code that do not change functionality but that do affect source
code line numbers (such as adding a comment line) will cause all affected modules to be
recompiled. This happens because debug information must be kept current so that
ModelSim can trace back to the correct areas of the source code.
Library Usage
All modules and UDPs in a Verilog design must be compiled into one or more libraries. One
library is usually sufficient for a simple design, but you may want to organize your modules into
various libraries for a complex design. If your design uses different modules having the same
name, then you need to put those modules in different libraries because design unit names must
be unique within a library.
The following is an example of how to organize your ASIC cells into one library and the rest of
your design into another:
% vlib work
% vlib asiclib
% vlog -work asiclib and2.v or2.v
-- Compiling module and2
-- Compiling module or2
Top level modules:
and2
or2
% vlog top.v
-- Compiling module top
Top level modules:
top
Note that the first compilation uses the -work asiclib argument to instruct the compiler to place
the results in the asiclib library rather than the default work library.
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Library Search Rules for the vlog Command
Because instantiation bindings are not determined at compile time, you must instruct the
simulator to search your libraries when loading the design. The top-level modules are loaded
from the library named work unless you prefix the modules with the . option. All
other Verilog instantiations are resolved in the following order:
•
Search libraries specified with -Lf arguments in the order they appear on the command
line.
•
•
Search the library specified in the Verilog-XL uselib Compiler Directive section.
•
•
Search the work library.
Search libraries specified with -L arguments in the order they appear on the command
line.
Search the library explicitly named in the special escaped identifier instance name.
Handling Sub-Modules with Common Names
Sometimes in one design you need to reference two different modules that have the same name.
This situation can occur if you have hierarchical modules organized into separate libraries, and
you have commonly-named sub-modules in the libraries that have different definitions. This
may happen if you are using vendor-supplied libraries.
For example, say you have the following design configuration:
Example 7-3. Sub-Modules with Common Names
top
modA
modB
lib2:
lib1:
modA
cellX
modB
cellX
The normal library search rules fail in this situation. For example, if you load the design as
follows:
vsim -L lib1 -L lib2 top
both instantiations of cellX resolve to the lib1 version of cellX. On the other hand, if you specify
-L lib2 -L lib1, both instantiations of cellX resolve to the lib2 version of cellX.
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To handle this situation, ModelSim implements a special interpretation of the expression -L
work. When you specify -L work first in the search library arguments you are directing vsim to
search for the instantiated module or UDP in the library that contains the module that does the
instantiation.
In the example above you would invoke vsim as follows:
vsim -L work -L lib1 -L lib2 top
SystemVerilog Multi-File Compilation
Declarations in Compilation Unit Scope
SystemVerilog allows the declaration of types, variables, functions, tasks, and other constructs
in compilation unit scope ($unit). The visibility of declarations in $unit scope does not extend
outside the current compilation unit. Thus, it is important to understand how compilation units
are defined by the simulator during compilation.
By default, vlog operates in Single File Compilation Unit mode (SFCU). This means the
visibility of declarations in $unit scope terminates at the end of each source file. Visibility does
not carry forward from one file to another, except when a module, interface, or package
declaration begins in one file and ends in another file. In that case, the compilation unit spans
from the file containing the beginning of the declaration to the file containing the end of the
declaration.
The vlog command also supports a non-default mode called Multi File Compilation Unit
(MFCU). In MFCU mode, vlog compiles all files on the command line into one compilation
unit. You can invoke vlog in MFCU mode as follows:
•
•
For a specific, one-time compilation: vlog -mfcu.
For all compilations: set the variable MultiFileCompilationUnit = 1 in the
modelsim.ini file.
By using either of these methods, you allow declarations in $unit scope to remain in effect
throughout the compilation of all files.
If you have made MFCU the default behavior by setting MultiFileCompilationUnit = 1 in
your modelsim.ini file, you can override this default behavior on a specific compilation by
using vlog -sfcu.
Macro Definitions and Compiler Directives in Compilation Unit
Scope
According to the IEEE Std 1800-2005, the visibility of macro definitions and compiler
directives span the lifetime of a single compilation unit. By default, this means the definitions of
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macros and settings of compiler directives terminate at the end of each source file. They do not
carry forward from one file to another, except when a module, interface, or package declaration
begins in one file and ends in another file. In that case, the compilation unit spans from the file
containing the beginning of the definition to the file containing the end of the definition.
See Declarations in Compilation Unit Scope for instructions on how to control vlog's handling
of compilation units.
Note
Compiler directives revert to their default values at the end of a compilation unit.
If a compiler directive is specified as an option to the compiler, this setting is used for all
compilation units present in the current compilation.
Verilog-XL Compatible Compiler Arguments
The compiler arguments listed below are equivalent to Verilog-XL arguments and may ease the
porting of a design to ModelSim. See the vlog command for a description of each argument.
+define+[=]
+delay_mode_distributed
+delay_mode_path
+delay_mode_unit
+delay_mode_zero
-f
+incdir+
+mindelays
+maxdelays
+nowarn
+typdelays
-u
Arguments Supporting Source Libraries
The compiler arguments listed below support source libraries in the same manner as VerilogXL. See the vlog command for a description of each argument.
Note that these source libraries are very different from the libraries that the ModelSim compiler
uses to store compilation results. You may find it convenient to use these arguments if you are
porting a design to ModelSim or if you are familiar with these arguments and prefer to use
them.
Source libraries are searched after the source files on the command line are compiled. If there
are any unresolved references to modules or UDPs, then the compiler searches the source
libraries to satisfy them. The modules compiled from source libraries may in turn have
additional unresolved references that cause the source libraries to be searched again. This
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process is repeated until all references are resolved or until no new unresolved references are
found. Source libraries are searched in the order they appear on the command line.
-v
-y
+libext+
+librescan
+nolibcell
-R []
Verilog-XL uselib Compiler Directive
The `uselib compiler directive is an alternative source library management scheme to the -v, -y,
and +libext compiler arguments. It has the advantage that a design may reference different
modules having the same name. You compile designs that contain `uselib directive statements
using the -compile_uselibs argument (described below) to vlog.
The syntax for the `uselib directive is:
`uselib ...
where can be one or more of the following:
•
dir=, which is equivalent to the command line argument:
-y
•
file=, which is equivalent to the command line argument:
-v
•
libext=, which is equivalent to the command line argument:
+libext+
•
lib=, which references a library for instantiated objects, specifically
modules, interfaces and program blocks, but not packages. You must ensure the correct
mappings are set up if the library does not exist in the current working directory. The
-compile_uselibs argument does not affect this usage of `uselib.
For example, the following directive
`uselib dir=/h/vendorA libext=.v
is equivalent to the following command line arguments:
-y /h/vendorA +libext+.v
Since the `uselib directives are embedded in the Verilog source code, there is more flexibility in
defining the source libraries for the instantiations in the design. The appearance of a `uselib
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directive in the source code explicitly defines how instantiations that follow it are resolved,
completely overriding any previous `uselib directives.
An important feature of ‘uselib is to allow a design to reference multiple modules having the
same name, therefore independent compilation of the source libraries referenced by the `uselib
directives is required.
Each source library should be compiled into its own object library. The compilation of the code
containing the `uselib directives only records which object libraries to search for each module
instantiation when the design is loaded by the simulator.
Because the `uselib directive is intended to reference source libraries, the simulator must infer
the object libraries from the library references. The rule is to assume an object library named
work in the directory defined in the library reference:
dir=
or the directory containing the file in the library reference
file=
The simulator will ignore a library reference libext=. For example, the
following `uselib directives infer the same object library:
‘uselib dir=/h/vendorA
‘uselib file=/h/vendorA/libcells.v
In both cases the simulator assumes that the library source is compiled into the object library:
/h/vendorA/work
The simulator also extends the `uselib directive to explicitly specify the object library with the
library reference lib=. For example:
‘uselib lib=/h/vendorA/work
The library name can be a complete path to a library, or it can be a logical library name defined
with the vmap command.
-compile_uselibs Argument
Use the -compile_uselibs argument to vlog to reference `uselib directives. The argument finds
the source files referenced in the directive, compiles them into automatically created object
libraries, and updates the modelsim.ini file with the logical mappings to the libraries.
When using -compile_uselibs, ModelSim determines into which directory to compile the object
libraries by choosing, in order, from the following three values:
•
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The directory name specified by the -compile_uselibs argument. For example,
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-compile_uselibs=./mydir
•
The directory specified by the MTI_USELIB_DIR environment variable (see
Environment Variables)
•
A directory named mti_uselibs that is created in the current working directory
The following code fragment and compiler invocation show how two different modules that
have the same name can be instantiated within the same design:
module top;
`uselib dir=/h/vendorA libext=.v
NAND2 u1(n1, n2, n3);
`uselib dir=/h/vendorB libext=.v
NAND2 u2(n4, n5, n6);
endmodule
vlog -compile_uselibs top
This allows the NAND2 module to have different definitions in the vendorA and vendorB
libraries.
uselib is Persistent
As mentioned above, the appearance of a `uselib directive in the source code explicitly defines
how instantiations that follow it are resolved. This may result in unexpected consequences. For
example, consider the following compile command:
vlog -compile_uselibs dut.v srtr.v
Assume that dut.v contains a `uselib directive. Since srtr.v is compiled after dut.v, the `uselib
directive is still in effect. When srtr is loaded it is using the `uselib directive from dut.v to
decide where to locate modules. If this is not what you intend, then you need to put an empty
`uselib at the end of dut.v to “close” the previous `uselib statement.
Verilog Configurations
The Verilog 2001 specification added configurations. Configurations specify how a design is
“assembled” during the elaboration phase of simulation. Configurations actually consist of two
pieces: the library mapping and the configuration itself. The library mapping is used at compile
time to determine into which libraries the source files are to be compiled. Here is an example of
a simple library map file:
library
library
library
library
work
rtlLib
gateLib
aLib
../top.v;
lrm_ex_top.v;
lrm_ex_adder.vg;
lrm_ex_adder.v;
Here is an example of a library map file that uses -incdir:
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library lib1 src_dir/*.v -incdir ../include_dir2, ../, my_incdir;
The name of the library map file is arbitrary. You specify the library map file using the -libmap
argument to the vlog command. Alternatively, you can specify the file name as the first item on
the vlog command line, and the compiler reads it as a library map file.
The library map file must be compiled along with the Verilog source files. Multiple map files
are allowed but each must be preceded by the -libmap argument.
The library map file and the configuration can exist in the same or different files. If they are
separate, only the map file needs the -libmap argument. The configuration is treated as any
other Verilog source file.
Configurations and the Library Named work
The library named “work” is treated specially by ModelSim (see The Library Named "work" for
details) for Verilog configurations.
Consider the following code example:
config cfg;
design top;
instance top.u1 use work.u1;
endconfig
In this case, work.u1 indicates to load u1 from the current library.
To create a configuration that loads an instance from a library other than the default work
library, do the following:
1. Make sure the library has been created using the vlib command. For example:
vlib mylib
2. Define this library (mylib) as the new current (working) library:
vlog -work mylib
3. Load instance u1 from the current library, which is now mylib:
config cfg;
design top;
instance top.u1 use mylib.u1;
endconfig
Verilog Generate Statements
ModelSim implements the rules adopted for Verilog 2005, because the Verilog 2001 rules for
generate statements had numerous inconsistencies and ambiguities. Most of the 2005 rules are
backwards compatible, but there is one key difference related to name visibility.
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Name Visibility in Generate Statements
Consider the following code example:
module m;
parameter p = 1;
generate
if (p)
integer x = 1;
else
real x = 2.0;
endgenerate
initial $display(x);
endmodule
This example is legal under 2001 rules. However, it is illegal under the 2005 rules and causes an
error in ModelSim. Under the new rules, you cannot hierarchically reference a name in an
anonymous scope from outside that scope. In the example above, x does not propagate its
visibility upwards, and each condition alternative is considered to be an anonymous scope.
For this example to simulate properly in ModelSim, change it to the following:
module m;
parameter p = 1;
if (p) begin:s
integer x = 1;
end
else begin:s
real x = 2.0;
end
initial $display(s.x);
endmodule
Because the scope is named in this example (begin:s), normal hierarchical resolution rules
apply and the code runs without error.
In addition, note that the keyword pair generate - endgenerate is optional under the 2005
rules and are excluded in the second example.
Initializing Registers and Memories
For Verilog designs you can initialize registers and memories with specific values or randomly
generated values. This functionality is controlled from the vlog and vsim command lines with
the following switches:
•
•
Registers: vlog +initreg and vsim +initreg
Memories: vlog +initmem and vsim +initmem
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Initialization Concepts
•
Random stability — From run to run, it is reasonable to expect that simulation results
will be consistent with the same seed value, even when the design is recompiled or
different optimization switches are specified.
However, if the design changes in any way, random stability can not be ensured. These
design changes include:
o
Changing the source code (except for comment editing).
o
Changing parameter values with vsim -G. This forces a different topology during
design elaboration.
o
Changing a +define switch such that different source code is compiled.
o
Changing design hierarchy of the design units due to the random initial value being
dependent upon the full path name of the instance.
For sequential UDPs, the simulator guarantees repeatable initial values only if the
design is compiled and run with the same vlog, vopt, and vsim options.
•
Sequential UDPs — An initial statement in a sequential UDP overrides all +initreg
functionality.
Limitations
•
The following are not initialized with +initmem or +initreg:
o
Variables in dynamic types, dynamic arrays, queues, or associative arrays.
o
Unpacked structs, or unpacked or tagged unions.
Requirements
•
Prepare your libraries with vlib and vmap as you would normally.
Initializing with Specific Values — Enabled During Compilation
1. Compile the design unit with the +initreg or +initmem switches to the vlog command.
Refer to the vlog command reference page for descriptions of the following options.
a. Specify which datatypes should be initialized: +{r | b | e | u}.
b. Specify the initialization value: +{0 | 1 | X | Z}.
2. Simulate as you would normally.
Initializing with Random Values — Enabled During Compilation
1. Compile the design unit with the +initreg or +initmem switches to the vlog command.
Refer to the vlog command reference page for descriptions of the following options.
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a. Specify which datatypes should be initialized: +{r | b | e | u}.
b. Do not specify the initialization value. This enables the specification of a random
seed during simulation.
2. Simulate as you would normally, except for adding the +initmem+ or
+initreg+ switches. Refer to the vsim command reference page for a description
of this switch. The random values will only include 0 or 1.
If no +initreg is present on the vsim command line, a random seed of 0 is used during
initialization.
Verilog Simulation
A Verilog design is ready for simulation after it has been compiled with vlog. The simulator
may then be invoked with the names of the top-level modules (many designs contain only one
top-level module). For example, if your top-level modules are “testbench” and “globals”, then
invoke the simulator as follows:
vsim testbench globals
After the simulator loads the top-level modules, it iteratively loads the instantiated modules and
UDPs in the design hierarchy, linking the design together by connecting the ports and resolving
hierarchical references. By default all modules and UDPs are loaded from the library named
work. Modules and UDPs from other libraries can be specified using the -L or -Lf arguments to
vsim (see Library Usage for details).
On successful loading of the design, the simulation time is set to zero, and you must enter a run
command to begin simulation. Commonly, you enter run -all to run until there are no more
simulation events or until $finish is executed in the Verilog code. You can also run for specific
time periods (for example, run 100 ns). Enter the quit command to exit the simulator.
Simulator Resolution Limit (Verilog)
The simulator internally represents time as a 64-bit integer in units equivalent to the smallest
unit of simulation time (also known as the simulator resolution limit). The resolution limit
defaults to the smallest time units that you specify among all of the `timescale compiler
directives in the design.
Here is an example of a `timescale directive:
`timescale 1 ns / 100 ps
The first number (1 ns) is the time units; the second number (100 ps) is the time precision,
which is the rounding factor for the specified time units. The directive above causes time values
to be read as nanoseconds and rounded to the nearest 100 picoseconds.
Time units and precision can also be specified with SystemVerilog keywords as follows:
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timeunit 1 ns
timeprecision 100 ps
Modules Without Timescale Directives
Unexpected behavior may occur if your design contains some modules with timescale directives
and others without. An elaboration error is issued in this situation and it is highly recommended
that all modules having delays also have timescale directives to make sure that the timing of the
design operates as intended.
Timescale elaboration errors may be suppressed or reduced to warnings however, there is a risk
of improper design behavior and reduced performance. The vsim +nowarnTSCALE or
-suppress options may be used to ignore the error, while the -warning option may be used to
reduce the severity to a warning.
-timescale Option
The -timescale option can be used with the vlog command to specify the default timescale in
effect during compilation for modules that do not have an explicit `timescale directive. The
format of the -timescale argument is the same as that of the `timescale directive:
-timescale /
where is . The value of must be 1, 10, or 100. The value of
must be fs, ps, ns, us, ms, or s. In addition, the must be greater than or
equal to the .
For example:
-timescale "1ns / 1ps"
The argument above needs quotes because it contains white space.
Multiple Timescale Directives
As alluded to above, your design can have multiple timescale directives. The timescale directive
takes effect where it appears in a source file and applies to all source files which follow in the
same vlog command. Separately compiled modules can also have different timescales. The
simulator determines the smallest timescale of all the modules in a design and uses that as the
simulator resolution.
timescale, -t, and Rounding
The optional vsim argument -t sets the simulator resolution limit for the overall simulation. If
the resolution set by -t is larger than the precision set in a module, the time values in that
module are rounded up. If the resolution set by -t is smaller than the precision of the module, the
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precision of that module remains whatever is specified by the `timescale directive. Consider the
following code:
`timescale 1 ns / 100 ps
module foo;
initial
#12.536 $display
The list below shows three possibilities for -t and how the delays in the module are handled in
each case:
•
-t not set
The delay is rounded to 12.5 as directed by the module’s ‘timescale directive.
•
-t is set to 1 fs
The delay is rounded to 12.5. Again, the module’s precision is determined by the
‘timescale directive. ModelSim does not override the module’s precision.
•
-t is set to 1 ns
The delay will be rounded to 13. The module’s precision is determined by the -t setting.
ModelSim can only round the module’s time values because the entire simulation is
operating at 1 ns.
Choosing the Resolution for Verilog
You should choose the coarsest resolution limit possible that does not result in undesired
rounding of your delays. The time precision should not be unnecessarily small because it limits
the maximum simulation time limit, and it degrades performance in some cases.
Event Ordering in Verilog Designs
Event-based simulators such as ModelSim may process multiple events at a given simulation
time. The Verilog language is defined such that you cannot explicitly control the order in which
simultaneous events are processed. Unfortunately, some designs rely on a particular event
order, and these designs may behave differently than you expect.
Event Queues
Section 11 of IEEE Std 1364-2005 defines several event queues that determine the order in
which events are evaluated. At the current simulation time, the simulator has the following
pending events:
•
•
active events
inactive events
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•
•
•
non-blocking assignment update events
monitor events
future events
o
inactive events
o
non-blocking assignment update events
The Standard (LRM) dictates that events are processed as follows:
1. All active events are processed.
2. Inactive events are moved to the active event queue and then processed.
3. Non-blocking events are moved to the active event queue and then processed.
4. Monitor events are moved to the active queue and then processed.
5. Simulation advances to the next time where there is an inactive event or a non-blocking
assignment update event.
Within the active event queue, the events can be processed in any order, and new active events
can be added to the queue in any order. In other words, you cannot control event order within
the active queue. The example below illustrates potential ramifications of this situation.
Assume that you have these four statements:
•
•
•
•
always@(q) p = q;
always @(q) p2 = not q;
always @(p or p2) clk = p and p2;
always @(posedge clk)
with current variable values: q = 0, p = 0, p2=1
The tables below show two of the many valid evaluations of these statements. Evaluation events
are denoted by a number where the number is the statement to be evaluated. Update events are
denoted (old->new) where indicates the reg being updated and new is the
updated value.\
Table 7-1. Evaluation 1 of always Statements
Event being processed
Active event queue
q(0 -> 1)
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q(0 -> 1)
1, 2
1
p(0 -> 1), 2
p(0 -> 1)
3, 2
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Table 7-1. Evaluation 1 of always Statements (cont.)
Event being processed
Active event queue
3
clk(0 -> 1), 2
clk(0 -> 1)
4, 2
4
2
2
p2(1 -> 0)
p2(1 -> 0)
3
3
clk(1 -> 0)
clk(1 -> 0)
Table 7-2. Evaluation 2 of always Statement
Event being processed
Active event queue
q(0 -> 1)
q(0 -> 1)
1, 2
1
p(0 -> 1), 2
2
p2(1 -> 0), p(0 -> 1)
p(0 -> 1)
3, p2(1 -> 0)
p2(1 −> 0)
3
3
(clk does not change)
Again, both evaluations are valid. However, in Evaluation 1, clk has a glitch on it; in Evaluation
2, clk does not. This indicates that the design has a zero-delay race condition on clk.
Controlling Event Queues with Blocking or Non-Blocking
Assignments
The only control you have over event order is to assign an event to a particular queue. You do
this by using blocking or non-blocking assignments.
Blocking Assignments
Blocking assignments place an event in the active, inactive, or future queues depending on what
type of delay they have:
•
•
a blocking assignment without a delay goes in the active queue
a blocking assignment with an explicit delay of 0 goes in the inactive queue
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•
a blocking assignment with a non-zero delay goes in the future queue
Non-Blocking Assignments
A non-blocking assignment goes into either the non-blocking assignment update event queue or
the future non-blocking assignment update event queue. (Non-blocking assignments with no
delays and those with explicit zero delays are treated the same.)
Non-blocking assignments should be used only for outputs of flip-flops. This insures that all
outputs of flip-flops do not change until after all flip-flops have been evaluated. Attempting to
use non-blocking assignments in combinational logic paths to remove race conditions may only
cause more problems. (In the preceding example, changing all statements to non-blocking
assignments would not remove the race condition.) This includes using non-blocking
assignments in the generation of gated clocks.
The following is an example of how to properly use non-blocking assignments.
gen1: always @(master)
clk1 = master;
gen2: always @(clk1)
clk2 = clk1;
f1 : always @(posedge clk1)
begin
q1 <= d1;
end
f2:
always @(posedge clk2)
begin
q2 <= q1;
end
If written this way, a value on d1 always takes two clock cycles to get from d1 to q2.
If you change clk1 = master and clk2 = clk1 to non-blocking assignments or q2 <= q1 and q1
<= d1 to blocking assignments, then d1 may get to q2 is less than two clock cycles.
Debugging Event Order Issues
Since many models have been developed on Verilog-XL, ModelSim tries to duplicate VerilogXL event ordering to ease the porting of those models to ModelSim. However, ModelSim does
not match Verilog-XL event ordering in all cases, and if a model ported to ModelSim does not
behave as expected, then you should suspect that there are event order dependencies.
ModelSim helps you track down event order dependencies with the following compiler
arguments: -compat, -hazards, and -keep_delta.
See the vlog command for descriptions of -compat and -hazards.
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Hazard Detection
The -hazards argument to vsim detects event order hazards involving simultaneous reading and
writing of the same register in concurrently executing processes. vsim detects the following
kinds of hazards:
•
•
WRITE/WRITE — Two processes writing to the same variable at the same time.
•
WRITE/READ — Same as a READ/WRITE hazard except that ModelSim executed the
write first.
READ/WRITE — One process reading a variable at the same time it is being written to
by another process. ModelSim calls this a READ/WRITE hazard if it executed the read
first.
vsim issues an error message when it detects a hazard. The message pinpoints the variable and
the two processes involved. You can have the simulator break on the statement where the
hazard is detected by setting the break on assertion level to Error.
To enable hazard detection you must invoke vlog with the -hazards argument when you compile
your source code and you must also invoke vsim with the -hazards argument when you
simulate.
Note
Enabling -hazards implicitly enables the -compat argument. As a result, using this
argument may affect your simulation results.
Hazard Detection and Optimization Levels
In certain cases hazard detection results are affected by the optimization level used in the
simulation. Some optimizations change the read/write operations performed on a variable if the
transformation is determined to yield equivalent results. Because the hazard detection algorithm
cannot determine whether the read/write operations can affect the simulation results, the
optimizations can result in different hazard detection results. Generally, the optimizations
reduce the number of false hazards by eliminating unnecessary reads and writes, but there are
also optimizations that can produce additional false hazards.
Limitations of Hazard Detection
•
Reads and writes involving bit and part selects of vectors are not considered for hazard
detection. The overhead of tracking the overlap between the bit and part selects is too
high.
•
•
A WRITE/WRITE hazard is flagged even if the same value is written by both processes.
A WRITE/READ or READ/WRITE hazard is flagged even if the write does not modify
the variable's value.
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•
•
Glitches on nets caused by non-guaranteed event ordering are not detected.
•
Hazards caused by simultaneous forces are not detected.
A non-blocking assignment is not treated as a WRITE for hazard detection purposes.
This is because non-blocking assignments are not normally involved in hazards. (In fact,
they should be used to avoid hazards.)
Debugging Signal Segmentation Violations
If you attempt to access a SystemVerilog object that has not been constructed with the new
operator, you will receive a fatal error called a signal segmentation violation (SIGSEGV). For
example, the following code produces a SIGSEGV fatal error:
class C;
int x;
endclass
C obj;
initial obj.x = 5;
This attempts to initialize a property of obj, but obj has not been constructed. The code is
missing the following:
C obj = new;
The new operator performs three distinct operations:
•
•
Allocates storage for an object of type C
•
Assigns the handle of the newly constructed object to “obj”
Calls the “new” method in the class or uses a default method if the class does not define
“new”
If the object handle obj is not initialized with new, there will be nothing to reference. ModelSim
sets the variable to the value null and the SIGSEGV fatal error will occur.
To debug a SIGSEGV error, first look in the transcript. Figure 7-1 shows an example of a
SIGSEGV error message in the Transcript window.
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Figure 7-1. Fatal Signal Segmentation Violation (SIGSEGV)
The Fatal error message identifies the filename and line number where the code violation
occurred (in this example, the file is top.sv and the line number is 19).
ModelSim sets the active scope to the location where the error occurred. In the Processes
window, the current process is highlighted (Figure 7-2).
Figure 7-2. Current Process Where Error Occurred
Double-click the highlighted process to open a Source window. A blue arrow will point to the
statement where the simulation stopped executing (Figure 7-3).
Figure 7-3. Blue Arrow Indicating Where Code Stopped Executing
Next, look for null values in the ModelSim Locals window (Figure 7-4), which displays data
objects declared in the local (current) scope of the active process.
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Figure 7-4. Null Values in the Locals Window
The null value in Figure 7-4 indicates that the object handle for obj was not properly
constructed with the new operator.
Negative Timing Checks
ModelSim automatically detects cells with negative timing checks and causes timing checks to
be performed on the delayed versions of input ports (used when there are negative timing check
limits). This is the equivalent of applying the +delayed_timing_checks switch with the vsim
command.
vsim +delayed_timing_checks
Appropriately applying +delayed_timing_checks will significantly improve simulation
performance.
To turn off this feature, specify +no_autodtc with vsim.
Negative Timing Check Limits
By default, ModelSim supports negative timing check limits in Verilog $setuphold and $recrem
system tasks. Using the +no_neg_tcheck argument with the vsim command causes all negative
timing check limits to be set to zero.
Models that support negative timing check limits must be written properly if they are to be
evaluated correctly. These timing checks specify delayed versions of the input ports, which are
used for functional evaluation. The correct syntax for $setuphold and $recrem is as follows.
$setuphold
Syntax
$setuphold(clk_event, data_event, setup_limit, hold_limit, [notifier], [tstamp_cond],
[tcheck_cond], [delayed_clk], [delayed_data])
Arguments
•
356
The clk_event argument is required. It is a transition in a clock signal that establishes the
reference time for tracking timing violations on the data_event. Since $setuphold
combines the functionality of the $setup and $hold system tasks, the clk_event sets the
lower bound event for $hold and the upper bound event for $setup.
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•
The data_event argument is required. It is a transition of a data signal that initiates the
timing check. The data_event sets the upper bound event for $hold and the lower bound
limit for $setup.
•
The setup_limit argument is required. It is a constant expression or specparam that
specifies the minimum interval between the data_event and the clk_event. Any change
to the data signal within this interval results in a timing violation.
•
The hold_limit argument is required. It is a constant expression or specparam that
specifies the interval between the clk_event and the data_event. Any change to the data
signal within this interval results in a timing violation.
•
The notifier argument is optional. It is a register whose value is updated whenever a
timing violation occurs. The notifier can be used to define responses to timing
violations.
•
The tstamp_cond argument is optional. It conditions the data_event for the setup check
and the clk_event for the hold check. This alternate method of conditioning precludes
specifying conditions in the clk_event and data_event arguments.
•
The tcheck_cond argument is optional. It conditions the data_event for the hold check
and the clk_event for the setup check. This alternate method of conditioning precludes
specifying conditions in the clk_event and data_event arguments.
•
The delayed_clk argument is optional. It is a net that is continuously assigned the value
of the net specified in the clk_event. The delay is determined by the simulator and may
be non-zero depending on all the timing check limits.
•
The delayed_data argument is optional. It is a net that is continuously assigned the value
of the net specified in the data_event. The delay is determined by the simulator and may
be non-zero depending on all the timing check limits.
You can specify negative times for either the setup_limit or the hold_limit, but the sum of the
two arguments must be zero or greater. If this condition is not met, ModelSim zeroes the
negative limit during elaboration or SDF annotation. To see messages about this kind of
problem, use the +ntc_warn argument with the vsim command. A typical warning looks like
the following:
** Warning: (vsim-3616) cells.v(x): Instance 'dff0' - Bad $setuphold
constraints: 5 ns and -6 ns. Negative limit(s) set to zero.
The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that
may have negative timing constraints. The model's logic should reference the delayed_clk and
delayed_data nets in place of the normal clk and data nets. This ensures that the correct data is
latched in the presence of negative constraints. The simulator automatically calculates the
delays for delayed_clk and delayed_data such that the correct data is latched as long as a timing
constraint has not been violated. See Using Delayed Inputs for Timing Checks for more
information.
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Optional arguments not included in the task must be indicated as null arguments by using
commas. For example:
$setuphold(posedge CLK, D, 2, 4, , , tcheck_cond);
The $setuphold task does not specify notifier or tstamp_cond but does include a tcheck_cond
argument. Notice that there are no commas after the tcheck_cond argument. Using one or more
commas after the last argument results in an error.
Note
Do not condition a $setuphold timing check using the tstamp_cond or tcheck_cond
arguments and a conditioned event. If this is attempted, only the parameters in the
tstamp_cond or tcheck_cond arguments will be effective, and a warning will be issued.
$recrem
Syntax
$recrem(control_event, data_event, recovery_limit, removal_limit, [notifier], [tstamp_cond],
[tcheck_cond], [delayed_ctrl, [delayed_data])
Arguments
358
•
The control_event argument is required. It is an asynchronous control signal with an
edge identifier to indicate the release from an active state.
•
The data_event argument is required. It is clock or gate signal with an edge identifier to
indicate the active edge of the clock or the closing edge of the gate.
•
The recovery_limit argument is required. It is the minimum interval between the release
of the asynchronous control signal and the active edge of the clock event. Any change to
a signal within this interval results in a timing violation.
•
The removal_limit argument is required. It is the minimum interval between the active
edge of the clock event and the release of the asynchronous control signal. Any change
to a signal within this interval results in a timing violation.
•
The notifier argument is optional. It is a register whose value is updated whenever a
timing violation occurs. The notifier can be used to define responses to timing
violations.
•
The tstamp_cond argument is optional. It conditions the data_event for the removal
check and the control_event for the recovery check. This alternate method of
conditioning precludes specifying conditions in the control_event and data_event
arguments.
•
The tcheck_cond argument is optional. It conditions the data_event for the recovery
check and the clk_event for the removal check. This alternate method of conditioning
precludes specifying conditions in the control_event and data_event arguments.
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•
The delayed_ctrl argument is optional. It is a net that is continuously assigned the value
of the net specified in the control_event. The delay is determined by the simulator and
may be non-zero depending on all the timing check limits.
•
The delayed_data argument is optional. It is a net that is continuously assigned the value
of the net specified in the data_event. The delay is determined by the simulator and may
be non-zero depending on all the timing check limits.
You can specify negative times for either the recovery_limit or the removal_limit, but the sum
of the two arguments must be zero or greater. If this condition is not met, ModelSim zeroes the
negative limit during elaboration or SDF annotation. To see messages about this kind of
problem, use the +ntc_warn argument with the vsim command.
The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that
may have negative timing constraints. The model's logic should reference the delayed_clk and
delayed_data nets in place of the normal control and data nets. This ensures that the correct
data is latched in the presence of negative constraints. The simulator automatically calculates
the delays for delayed_clk and delayed_data such that the correct data is latched as long as a
timing constraint has not been violated.
Optional arguments not included in the task must be indicated as null arguments by using
commas. For example:
$recrem(posedge CLK, D, 2, 4, , , tcheck_cond);
The $recrem task does not specify notifier or tstamp_cond but does include a tcheck_cond
argument. Notice that there are no commas after the tcheck_cond argument. Using one or more
commas after the last argument results in an error.
Negative Timing Constraint Algorithm
The ModelSim negative timing constraint algorithm attempts to find a set of delays such that
the data net is valid when the clock or control nets transition and the timing checks are satisfied.
The algorithm is iterative because a set of delays that satisfies all timing checks for a pair of
inputs can cause mis-ordering of another pair (where both pairs of inputs share a common
input). When a set of delays that satisfies all timing checks is found, the delays are said to
converge.
When none of the delay sets cause convergence, the algorithm pessimistically changes the
timing check limits to force convergence. Basically, the algorithm zeroes the smallest negative
$setup/$recovery limit. If a negative $setup/$recovery doesn't exist, then the algorithm zeros the
smallest negative $hold/$removal limit. After zeroing a negative limit, the delay calculation
procedure is repeated. If the delays do not converge, the algorithm zeros another negative limit,
repeating the process until convergence is found.
For example, in this timing check,
$setuphold(posedge CLK, D, -10, 20, notifier,,, dCLK, dD);
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dCLK is the delayed version of the input CLK and dD is the delayed version of D. By default,
the timing checks are performed on the inputs while the model's functional evaluation uses the
delayed versions of the inputs. This posedge D-Flipflop module has a negative setup limit of -10
time units, which allows posedge CLK to occur up to 10 time units before the stable value of D
is latched.
-10
D violation
region
20
XXXXXXXXXX
0
CLK
Without delaying CLK by 11, an old value for D could be latched. Note that an additional time
unit of delay is added to prevent race conditions.
The inputs look like this:
9
D
0
CLK
. . . resulting in delayed inputs of . . .
9
dD
11
dCLK
Because the posedge CLK transition is delayed by the amount of the negative setup limit (plus
one time unit to prevent race conditions) no timing violation is reported and the new value of D
is latched.
However, the effect of this delay could also affect other inputs with a specified timing
relationship to CLK. The simulator is responsible for calculating the delay between all inputs
and their delayed versions. The complete set of delays (delay solution convergence) must
consider all timing check limits together so that whenever timing is met the correct data value is
latched.
Consider the following timing checks specified relative to CLK:
$setuphold(posedge CLK, D, -10, 20, notifier,,, dCLK, dD);
$setuphold(posedge CLK, negedge RST, -40, 50, notifier,,, dCLK, dRST);
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0
RST violation
D violation
-10
-30
20
40
\\\\\\\\\\\\
XXXXXXXXXX
CLK
To solve the timing checks specified relative to CLK the following delay values are necessary:
Rising
Falling
dCLK
31
31
dD
20
20
dRST
0
0
The simulator's intermediate delay solution shifts the violation regions to overlap the reference
events.
0
-10
20
-30
dRST violation
dD violation
40 45
\\\\\\\\\\\\\\\\
XXXXXXXXXX
dCLK
Notice that no timing is specified relative to negedge CLK, but the dCLK falling delay is set to
the dCLK rising delay to minimize pulse rejection on dCLK. Pulse rejection that occurs due to
delayed input delays is reported by:
"WARNING[3819] : Scheduled event on delay net dCLK was cancelled"
Now, consider the following case where a new timing check is added between D and RST and
the simulator cannot find a delay solution. Some timing checks are set to zero. In this case, the
new timing check is not annotated from an SDF file and a default $setuphold limit of 1, 1 is
used:
$setuphold(posedge CLK, D, -10, 20, notifier,,, dCLK, dD);
$setuphold(posedge CLK, negedge RST, -40, 50, notifier,,, dCLK, dRST);
$setuphold(negedge RST, D, 1, 1, notifier,,, dRST, dD);
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0
RST violation
D violation
-10
-30
20
40 45
\\\\\\\\\\\\\\\\
XXXXXXXXXX
CLK
D violation
1 1
XX
RST
As illustrated earlier, to solve timing checks on CLK, delays of 20 and 31 time units were
necessary on dD and dCLK, respectively.
Rising
Falling
dCLK
31
31
dD
20
20
dRST
0
0
The simulator's intermediate delay solution is:
0
-10
21 23
RST violation
D violation
-30
40 45
\\\\\\\\\\\\\\\\
XXXXXXXXXX
CLK
D violation
XX
RST
But this is not consistent with the timing check specified between RST and D. The falling RST
signal can be delayed by additional 10, but that is still not enough for the delay solution to
converge.
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Rising
Falling
dCLK
31
31
dD
20
20
dRST
0
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0
-10
-30
21 23
RST violation
D violation
40
55
\\\\\\\\\\\\
XXXXXXXXXX
CLK
D violation
XX
RST
As stated above, if a delay solution cannot be determined with the specified timing check limits
the smallest negative $setup/$recovery limit is zeroed and the calculation of delays repeated. If
no negative $setup/$recovery limits exist, then the smallest negative $hold/$removal limit is
zeroed. This process is repeated until a delay solution is found.
If a timing check in the design was zeroed because a delay solution was not found, a summary
message like the following will be issued:
# ** Warning: (vsim-3316) No solution possible for some delayed timing
check nets. 1 negative limits were zeroed. Use +ntc_warn for more info.
Invoking vsim with the +ntc_warn option identifies the timing check that is being zeroed.
Finally consider the case where the RST and D timing check is specified on the posedge RST.
$setuphold(posedge CLK, D, -10, 20, notifier,,, dCLK, dD);
$setuphold(posedge CLK, negedge RST, -40, 50, notifier,,, dCLK, dRST);
$setuphold(posedge RST, D, 1, 1, notifier,,, dRST, dD);
0
RST violation
D violation
-10
20
-30
45
\\\\\\\\\\\\\\\\
XXXXXXXXXX
CLK
D violation
1 1
XX
RST
In this case the delay solution converges when an rising delay on dRST is used.
dCLK
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Falling
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31
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Rising
Falling
dD
20
20
dRST
20
10
-10
0
21 23
RST violation
D violation
-30
40 45
\\\\\\\\\\\\\\\
XXXXXXXXXX
CLK
D violation
XX
RST
Using Delayed Inputs for Timing Checks
By default ModelSim performs timing checks on inputs specified in the timing check. If you
want timing checks performed on the delayed inputs, use the +delayed_timing_checks
argument to vsim.
Consider an example. This timing check:
$setuphold(posedge clk, posedge t, 20, -12, NOTIFIER,,, clk_dly, t_dly);
reports a timing violation when posedge t occurs in the violation region:
20
-12
t
0
clk
With the +delayed_timing_checks argument, the violation region between the delayed inputs
is:
7
1
t_dly
0
clk_dly
Although the check is performed on the delayed inputs, the timing check violation message is
adjusted to reference the undelayed inputs. Only the report time of the violation message is
noticeably different between the delayed and undelayed timing checks.
By far the greatest difference between these modes is evident when there are conditions on a
delayed check event because the condition is not implicitly delayed. Also, timing checks
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specified without explicit delayed signals are delayed, if necessary, when they reference an
input that is delayed for a negative timing check limit.
Other simulators perform timing checks on the delayed inputs. To be compatible, ModelSim
supports both methods.
Force and Release Statements in Verilog
The Verilog Language Reference Manual IEEE Std 1800-2009. drvyopm 10.6.2, states that the
left-hand side of a force statement cannot be a bit-select or part-select. Questa deviates from the
LRM standard by supporting forcing of bit-selects, part-selects, and field-selects in your source
code. The right-hand side of these force statements may not be a variable. Refer to the force
command for more information.
Verilog-XL Compatible Simulator Arguments
The simulator arguments listed below are equivalent to Verilog-XL arguments and may ease the
porting of a design to ModelSim. See the vsim command for a description of each argument.
+alt_path_delays
-l
+maxdelays
+mindelays
+multisource_int_delays
+no_cancelled_e_msg
+no_neg_tchk
+no_notifier
+no_path_edge
+no_pulse_msg
-no_risefall_delaynets
+no_show_cancelled_e
+nosdfwarn
+nowarn
+ntc_warn
+pulse_e/
+pulse_e_style_ondetect
+pulse_e_style_onevent
+pulse_int_e/
+pulse_int_r/
+pulse_r/
+sdf_nocheck_celltype
+sdf_verbose
+show_cancelled_e
+transport_int_delays
+transport_path_delays
+typdelays
Using Escaped Identifiers
ModelSim recognizes and maintains Verilog escaped identifier syntax. Prior to version 6.3,
Verilog escaped identifiers were converted to VHDL-style extended identifiers with a backslash
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at the end of the identifier. Verilog escaped identifiers then appeared as VHDL extended
identifiers in simulation output and in command line interface (CLI) commands. For example, a
Verilog escaped identifier like the following:
\/top/dut/03
had to be displayed as follows:
\/top/dut/03\
Starting in version 6.3, all object names inside the simulator appear identical to their names in
original HDL source files.
Sometimes, in mixed language designs, hierarchical identifiers might refer to both VHDL
extended identifiers and Verilog escaped identifiers in the same fullpath. For example,
top/\VHDL*ext\/\Vlog*ext /bottom (assuming the PathSeparator variable is set to '/'), or
top.\VHDL*ext\.\Vlog*ext .bottom (assuming the PathSeparator variable is set to '.') Any
fullpath that appears as user input to the simulator (such as on the vsim command line, in a .do
file) should be composed of components with valid escaped identifier syntax.
A modelsim.ini variable called GenerousIdentifierParsing can control parsing of identifiers. If
this variable is on (the variable is on by default: value = 1), either VHDL extended identifiers or
Verilog escaped identifier syntax may be used for objects of either language kind. This provides
backward compatibility with older .do files, which often contain pure VHDL extended identifier
syntax, even for escaped identifiers in Verilog design regions.
Note that SDF files are always parsed in “generous mode.” SignalSpy function arguments are
also parsed in “generous mode.”
Tcl and Escaped Identifiers
In Tcl, the backslash is one of a number of characters that have a special meaning. For example,
\n
creates a new line.
When a Tcl command is used in the command line interface, the TCL backslash should be
escaped by adding another backslash. For example:
force -freeze /top/ix/iy/\\yw\[1\]\\ 10 0, 01 {50 ns} -r 100
The Verilog identifier, in this example, is \yw[1]. Here, backslashes are used to escape the
square brackets ([]), which have a special meaning in Tcl.
For a more detailed description of special characters in Tcl and how backslashes should be used
with those characters, click Help > Tcl Syntax in the menu bar, or simply open the
docs/tcl_help_html/TclCmd directory in your QuestaSim installation.
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Cell Libraries
Cell Libraries
Mentor Graphics has passed the Verilog test bench from the ASIC Council and achieved the
“Library Tested and Approved” designation from Si2 Labs. This test bench is designed to
ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete
on the way to achieving full ASIC vendor support. As a consequence, many ASIC and FPGA
vendors’ Verilog cell libraries are compatible with ModelSim Verilog.
The cell models generally contain Verilog “specify blocks” that describe the path delays and
timing constraints for the cells. See Section 14 in the IEEE Std 1364-2005 for details on specify
blocks, and Section 15 for details on timing constraints. ModelSim Verilog fully implements
specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog-XL
compatible extensions.
SDF Timing Annotation
ModelSim Verilog supports timing annotation from Standard Delay Format (SDF) files. See
Standard Delay Format (SDF) Timing Annotation for details.
Delay Modes
Verilog models may contain both distributed delays and path delays. The delays on primitives,
UDPs, and continuous assignments are the distributed delays, whereas the port-to-port delays
specified in specify blocks are the path delays. These delays interact to determine the actual
delay observed. Most Verilog cells use path delays exclusively, with the distributed delays set
to zero. For example,
module and2(y, a, b);
input a, b;
output y;
and(y, a, b);
specify
(a => y) = 5;
(b => y) = 5;
endspecify
endmodule
In this two-input AND gate cell, the distributed delay for the AND primitive is zero, and the
actual delays observed on the module ports are taken from the path delays. This is typical for
most cells, but a complex cell may require non-zero distributed delays to work properly. Even
so, these delays are usually small enough that the path delays take priority over the distributed
delays. The rule is that if a module contains both path delays and distributed delays, then the
larger of the two delays for each path shall be used (as defined by the IEEE Std 1364). This is
the default behavior, but you can specify alternate delay modes with compiler directives and
arguments. These arguments and directives are compatible with Verilog-XL. Compiler delay
mode arguments take precedence over delay mode directives in the source code.
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Distributed Delay Mode
In distributed delay mode, the specify path delays are ignored in favor of the distributed delays.
You can specify this delay mode with the +delay_mode_distributed compiler argument or the
`delay_mode_distributed compiler directive.
Path Delay Mode
In path delay mode, the distributed delays are set to zero in any module that contains a path
delay. You can specify this delay mode with the +delay_mode_path compiler argument or the
`delay_mode_path compiler directive.
Unit Delay Mode
In unit delay mode, the non-zero distributed delays are set to one unit of simulation resolution
(determined by the minimum time_precision argument in all ‘timescale directives in your
design or the value specified with the -t argument to vsim), and the specify path delays and
timing constraints are ignored. You can specify this delay mode with the +delay_mode_unit
compiler argument or the `delay_mode_unit compiler directive.
Zero Delay Mode
In zero delay mode, the distributed delays are set to zero, and the specify path delays and timing
constraints are ignored. You can specify this delay mode with the +delay_mode_zero compiler
argument or the `delay_mode_zero compiler directive.
System Tasks and Functions
ModelSim supports system tasks and functions as follows:
•
•
•
•
All system tasks and functions defined in IEEE Std 1364
Some system tasks and functions defined in SystemVerilog IEEE Std 1800-2005
Several system tasks and functions that are specific to ModelSim
Several non-standard, Verilog-XL system tasks
The system tasks and functions listed in this section are built into the simulator, although some
designs depend on user-defined system tasks implemented with the Programming Language
Interface (PLI), Verilog Procedural Interface (VPI), or the SystemVerilog DPI (Direct
Programming Interface). If the simulator issues warnings regarding undefined system tasks or
functions, then it is likely that these tasks or functions are defined by a PLI/VPI application that
must be loaded by the simulator.
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IEEE Std 1364 System Tasks and Functions
The following supported system tasks and functions are described in detail in the IEEE Std
1364.
Note
You can use the change command to modify local variables in Verilog and
SystemVerilog tasks and functions.
Table 7-3. IEEE Std 1364 System Tasks and Functions - 1
Timescale tasks
Simulator control
tasks
Simulation time
functions
Command line input
$printtimescale
$finish
$realtime
$test$plusargs
$timeformat
$stop
$stime
$value$plusargs
$time
Table 7-4. IEEE Std 1364 System Tasks and Functions - 2
Probabilistic
distribution
functions
Conversion
functions
Stochastic analysis
tasks
Timing check tasks
$dist_chi_square
$bitstoreal
$q_add
$hold
$dist_erlang
$itor
$q_exam
$nochange
$dist_exponential
$realtobits
$q_full
$period
$dist_normal
$rtoi
$q_initialize
$recovery
$dist_poisson
$signed
$q_remove
$setup
$dist_t
$unsigned
$setuphold
$dist_uniform
$skew
$random
$width1
$removal
$recrem
1. Verilog-XL ignores the threshold argument even though it is part of the Verilog spec. ModelSim does not
ignore this argument. Be careful that you do not set the threshold argument greater-than-or-equal to the limit
argument as that essentially disables the $width check. Also, note that you cannot override the threshold
argument by using SDF annotation.
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Table 7-5. IEEE Std 1364 System Tasks
Display tasks
PLA modeling tasks
Value change dump
(VCD) file tasks
$display
$async$and$array
$dumpall
$displayb
$async$nand$array
$dumpfile
$displayh
$async$or$array
$dumpflush
$displayo
$async$nor$array
$dumplimit
$monitor
$async$and$plane
$dumpoff
$monitorb
$async$nand$plane
$dumpon
$monitorh
$async$or$plane
$dumpvars
$monitoro
$async$nor$plane
$monitoroff
$sync$and$array
$monitoron
$sync$nand$array
$strobe
$sync$or$array
$strobeb
$sync$nor$array
$strobeh
$sync$and$plane
$strobeo
$sync$nand$plane
$write
$sync$or$plane
$writeb
$sync$nor$plane
$writeh
$writeo
Table 7-6. IEEE Std 1364 File I/O Tasks
File I/O tasks
370
$fclose
$fmonitoro
$fwriteh
$fdisplay
$fopen
$fwriteo
$fdisplayb
$fread
$readmemb
$fdisplayh
$fscanf
$readmemh
$fdisplayo
$fseek
$rewind
$feof
$fstrobe
$sdf_annotate
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Table 7-6. IEEE Std 1364 File I/O Tasks (cont.)
File I/O tasks
$ferror
$fstrobeb
$sformat
$fflush
$fstrobeh
$sscanf
$fgetc
$fstrobeo
$swrite
$fgets
$ftell
$swriteb
$fmonitor
$fwrite
$swriteh
$fmonitorb
$fwriteb
$swriteo
$fmonitorh
$ungetc
SystemVerilog System Tasks and Functions
The following system tasks and functions are supported by ModelSim and are described more
completely in the Language Reference Manual (LRM) for SystemVerilog, IEEE Std
1800-2005.
Table 7-7. SystemVerilog System Tasks and Functions - 1
Expression size function
Range function
$bits
$isunbounded
Table 7-8. SystemVerilog System Tasks and Functions - 2
Shortreal
conversions
Array querying
functions
$shortrealbits
$dimensions
$bitstoshortreal
$left
$right
$low
$high
$increment
$size
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Table 7-9. SystemVerilog System Tasks and Functions - 4
Reading packed data
functions
Writing packed data
functions
Other functions
$readmemb
$writememb
$root
$readmemh
$writememh
$unit
Simulator-Specific System Tasks and Functions
Table 7-10 lists system tasks and functions that are specific to ModelSim. They are not included
in the IEEE Std 1364, nor are they likely supported in other simulators. Their use may limit the
portability of your code.
Table 7-10. Simulator-Specific Verilog System Tasks and Functions
$disable_signal_spy
$psprintf()
$enable_signal_spy
$sdf_done
$init_signal_driver
$signal_force
$init_signal_spy
$signal_release
$messagelog
$wlfdumpvars()
$coverage_save_mti
$coverage_save_mti
Note
$coverage_save is deprecated in this usage, please use $coverage_save_mti
Syntax
$coverage_save_mti(, [], [])
Description
The $coverage_save() system function is defined in IEEE Std 1800. The pre-standardization,
non-compliant behavior of $coverage_save() is deprecated prior to full standard alignment. The
pre-standardization behavior is retained for backwards-compatibility by the
$coverage_save_mti() system function.
The $coverage_save_mti() system function saves only Code Coverage information to a file
during a batch run that typically would terminate with the $finish call. It returns a “0” to
indicate that the coverage information was saved successfully or a “-1” to indicate an error
(unable to open file, instance name not found, and so forth.)
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If you do not specify , ModelSim saves all coverage data in the current design to
the specified file. If you do specify , ModelSim saves data on that instance, and
all instances below it (recursively), to the specified file.
If set to 1, the [] argument specifies that the output be saved in XML format.
See Code Coverage for more information on Code Coverage.
$messagelog
Syntax
$messagelog({"", ...}[, ...]);
Arguments
•
— Your message, enclosed in quotation marks ("), using text and specifiers
to define the output.
•
— A scope, object, or literal value that corresponds to the specifiers in the
. You must specify one for each specifier in the .
Specifiers
The $messagelog task supports all specifiers available with the $display system task. For more
information about $display, refer to section 17.1 of the IEEE std 1364-2005.
The following specifiers are specific to $messagelog.
Note
The format of these custom specifiers differ from the $display specifiers. Specifically,
“%:” denotes a $messagelog specifier and the letter denotes the type of specifier.
•
%:C — Group/Category
A string argument, enclosed in quotation marks ("). This attribute defines a group or
category used by the message system. If you do not specify %:C, the message system logs
User as the default.
•
%:F — Filename
A string argument specifying a simple filename, relative path to a filename, or a full path to
a filename. In the case of a simple filename or relative path to a filename, the simulator
accepts what you specify in the message output, but internally it uses the current directory to
complete these paths to form a full path—this allows the message viewer to link to the
specified file.
If you do not include %:F, the simulator automatically logs the value of the filename in
which the $messagelog is called.
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If you do include %:R, %:F, or %:L, or a combination of any two of these, the simulator
does not automatically log values for the undefined specifier(s).
•
%:I — Message ID
A string argument. The Message Viewer displays this value in the ID column. This attribute
is not used internally, therefore you do not need to be concerned about uniqueness or
conflict with other message IDs.
•
%:L — Line number
An integer argument.
If you do not include %:L, the simulator automatically logs the value of the line number on
which the $messagelog is called.
If you do include %:R, %:F, or %:L, or a combination of any two of these, the simulator
does not automatically log values for the undefined specifier(s).
•
%:O — Object/Signal Name
A hierarchical reference to a variable or net, such as sig1 or top.sigx[0]. You can specify
multiple %:O for each $messagelog, which effectively forms a list of attributes of that kind,
for example:
$messagelog("The signals are %:O, %:O, and %:O.",
sig1, top.sigx[0], ar [3].sig);
•
%:R — Instance/Region name
A hierarchical reference to a scope, such as top.sub1 or sub1. You can also specify a string
argument, such as “top.mychild”, where the identifier inside the quotes does not need to
correlate with an actual scope, it can be an artificial scope.
If you do not include %:R, the simulator automatically logs the instance or region in which
the $messagelog is called.
If you do include %:R, %:F, or %:L, or a combination of any two of these, the simulator
does not automatically log values for the undefined specifier(s).
•
%:S — Severity Level
A case-insensitive string argument, enclosed in quotes ("), that is one of the following:
Note — This is the default if you do not specify %:S
Warning
Error
Fatal
Info — The error message system recognizes this as a Note
Message — The error message system recognizes this as a Note
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•
%:V — Verbosity Rating
An integer argument, where the default is zero (0). The verbosity rating allows you to
specify a field you can use to sort or filter messages in the Message Viewer. In most cases
you specify that this attribute is not printed, using the tilde (~) character.
Description
•
Non-printing attributes (~) — You can specify that an attribute value is not to be printed
in the transcripted message by placing the tilde (~) character after the percent (%)
character, for example:
$messagelog("%:~S Do not print the Severity Level", "Warning");
However, the value of %:S is logged for use in the Message Viewer.
•
Logging of simulation time — For each call to $messagelog, the simulation time is
logged, however the simulation time is not considered an attribute of the message
system. This time is available in the Message Viewer.
•
Minimum field-width specifiers — are accepted before each specifier character, for
example:
%:0I
%:10I
•
•
Left-right justification specifier (-) — is accepted as it is for $display.
Macros — You can use the macros ‘__LINE__ (returns line number information) and
‘__FILE__ (returns filename information) when creating your $messagelog tasks. For
example:
module top;
function void wrapper(string file, int line);
$messagelog("Hello: The caller was at %:F,%:0L", file, line);
endfunction
initial begin
wrapper(`__FILE__, `__LINE__);
wrapper(`__FILE__, `__LINE__);
end
endmodule
which would produce the following output
# Hello: The caller was at test.sv,7
# Hello: The caller was at test.sv,8
Examples
•
The following $messagelog task:
$messagelog("hello world");
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transcripts the message:
hello world
while logging all default attributes, but does not log a category.
•
The following $messagelog task:
$messagelog("%:~S%0t: PCI-X burst read started in transactor %:R",
"Note", $time - 50, top.sysfixture.pcix);
transcripts the message:
150: PCI-X burst read started in transactor top.sysfixture.pcix
while silently logging the severity level of “Note”, and uses a direct reference to the
Verilog scope for the %:R specifier, and does not log any attributes for %:F (filename)
or %:L (line number).
•
The following $messagelog task:
$messagelog("%:~V%:S %:C-%:I,%:L: Unexpected AHB interrupt received
in transactor %:R", 1, "Error", "AHB", "UNEXPINTRPT", `__LINE__,
ahbtop.c190);
transcripts the message:
** Error: AHB-UNEXPINTRPT,238: Unexpected AHB interrupt received in
transactor ahbtop.c190
where the verbosity level (%:V) is “1”, severity level (%:S) is “Error”, the category
(%:C) is “AHB”, and the message identifier (%:I) is “UNEXPINTRPT”. There is a
direct reference for the region (%:R) and the macro ‘__LINE__ is used for line number
(%:L), resulting in no attribute logged for %:F (filename).
$psprintf()
Syntax
$psprintf()
Description
The $psprintf() system function behaves like the $sformat() file I/O task except that the string
result is passed back to the user as the function return value for $psprintf(), not placed in the
first argument as for $sformat(). Thus $psprintf() can be used where a string is valid. Note that
at this time, unlike other system tasks and functions, $psprintf() cannot be overridden by a userdefined system function in the PLI.
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$sdf_done
Syntax
$sdf_done
Description
This task is a “cleanup” function that removes internal buffers, called MIPDs, that have a delay
value of zero. These MIPDs are inserted in response to the -v2k_int_delay argument to the vsim
command. In general, the simulator automatically removes all zero delay MIPDs. However, if
you have $sdf_annotate() calls in your design that are not getting executed, the zero-delay
MIPDs are not removed. Adding the $sdf_done task after your last $sdf_annotate() removes any
zero-delay MIPDs that have been created.
$wlfdumpvars()
This Verilog system task specifies variables to be logged in the current simulation's WLF file
(default, vsim.wlf) and is called from within a Verilog design. It is equivalent to the Verilog
system task $dumpvars, except it dumps values to the current simulation's WLF file instead of
a VCD file. While it can not be called directly from within VHDL, it can log VHDL variables
contained under a Verilog scope that is referenced by $wlfdumpvars. The modelsim.ini
variable WildcardFilter will be used to filter types when a scope is logged by $wlfdumpvars.
Multiple scopes and variables are specified as a comma separated list.
Syntax
$wlfdumpvars(, { | }[, | ]);
Arguments
•
Specifies the number of hierarchical levels to log, if a scope is specified. Specified as a nonnegative integer.
•
Specifies a Verilog pathname to a scope, under which all variables are logged.
•
Specifies a variable to log.
Examples
•
Log variable "addr_bus" in the current scope
$wlfdumpvars(0, addr_bus);
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•
Log all variables within the scope "alu", and in any submodules
$wlfdumpvars(2, alu);
•
Log all variables within the scope regfile
$wlfdumpvars(1, $root.top.alu.regfile)
Verilog-XL Compatible System Tasks and Functions
ModelSim supports a number of Verilog-XL specific system tasks and functions.
Supported Tasks and Functions Mentioned in IEEE Std 1364
The following supported system tasks and functions, though not part of the IEEE standard, are
described in an annex of the IEEE Std 1364.
$countdrivers
$getpattern
$sreadmemb
$sreadmemh
Supported Tasks and Functions Not Described in IEEE Std 1364
The following system tasks are also provided for compatibility with Verilog-XL, though they
are not described in the IEEE Std 1364.
$deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is the
register or net to be changed; value is the new value for the register or net. The value
remains until there is a subsequent driver transaction or another $deposit task for the
same register or net. This system task operates identically to the ModelSim
force -deposit command.
$disable_warnings(""[,...]);
This system task instructs ModelSim to disable warnings about timing check violations
or triregs that acquire a value of ‘X’ due to charge decay. may be decay or
timing. You can specify one or more module instance names. If you do not specify a
module instance, ModelSim disables warnings for the entire simulation.
$enable_warnings(""[,...]);
This system task enables warnings about timing check violations or triregs that acquire a
value of ‘X’ due to charge decay. may be decay or timing. You can specify
one or more module instance names. If you do not specify a module_instance,
ModelSim enables warnings for the entire simulation.
$system("command");
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This system function takes a literal string argument, executes the specified operating
system command, and displays the status of the underlying OS process. Double quotes
are required for the OS command. For example, to list the contents of the working
directory on Unix:
$system("ls -l");
Return value of the $system function is a 32-bit integer that is set to the exit status code
of the underlying OS process.
Note
There is a known issue in the return value of this system function on the win32 platform.
If the OS command is built with a cygwin compiler, the exit status code may not be
reported correctly when an exception is thrown, and thus the return code may be wrong.
The workaround is to avoid building the application using cygwin or to use the switch
-mno-cygwin in cygwin on the gcc command line.
$systemf(list_of_args)
This system function can take any number of arguments. The list_of_args is treated
exactly the same as with the $display() function. The OS command that runs is the final
output from $display() given the same list_of_args. Return value of the $systemf
function is a 32-bit integer that is set to the exit status code of the underlying OS
process.
Note
There is a known issue in the return value of this system function on the win32 platform.
If the OS command is built with a cygwin compiler, the exit status code may not be
reported correctly when an exception is thrown, and thus the return code may be wrong.
The workaround is to avoid building the application using cygwin or to use the switch
-mno-cygwin in cygwin on the gcc command line.
Supported Tasks that Have Been Extended
The $setuphold and $recrem system tasks have been extended to provide additional
functionality for negative timing constraints and an alternate method of conditioning, as in
Verilog-XL. See Negative Timing Check Limits.
Unsupported Verilog-XL System Tasks
The following system tasks are Verilog-XL system tasks that are not implemented in ModelSim
Verilog, but have equivalent simulator commands.
$input("filename")
This system task reads commands from the specified filename. The equivalent simulator
command is do .
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$list[(hierarchical_name)]
This system task lists the source code for the specified scope. The equivalent
functionality is provided by selecting a module in the Structure (sim) window. The
corresponding source code is displayed in a Source window.
$reset
This system task resets the simulation back to its time 0 state. The equivalent simulator
command is restart.
$restart("filename")
This system task sets the simulation to the state specified by filename, saved in a
previous call to $save. The equivalent simulator command is restore .
$save("filename")
This system task saves the current simulation state to the file specified by filename. The
equivalent simulator command is checkpoint .
$scope(hierarchical_name)
This system task sets the interactive scope to the scope specified by hierarchical_name.
The equivalent simulator command is environment .
$showscopes
This system task displays a list of scopes defined in the current interactive scope. The
equivalent simulator command is show.
$showvars
This system task displays a list of registers and nets defined in the current interactive
scope. The equivalent simulator command is show.
Compiler Directives
ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364, some
Verilog-XL compiler directives, and some that are proprietary.
Many of the compiler directives (such as `timescale) take effect at the point they are defined in
the source code and stay in effect until the directive is redefined or until it is reset to its default
by a `resetall directive. The effect of compiler directives spans source files, so the order of
source files on the compilation command line could be significant. For example, if you have a
file that defines some common macros for the entire design, then you might need to place it first
in the list of files to be compiled.
The `resetall directive affects only the following directives by resetting them back to their
default settings (this information is not provided in the IEEE Std 1364):
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`celldefine
‘default_decay_time
`default_nettype
`delay_mode_distributed
`delay_mode_path
`delay_mode_unit
`delay_mode_zero
`protect
`timescale
`unconnected_drive
`uselib
ModelSim Verilog implicitly defines the following macro:
`define MODEL_TECH
IEEE Std 1364 Compiler Directives
The following compiler directives are described in detail in the IEEE Std 1364.
`celldefine
`default_nettype
`define
`else
`elsif
`endcelldefine
`endif
`ifdef
‘ifndef
`include
‘line
`nounconnected_drive
`resetall
`timescale
`unconnected_drive
`undef
Compiler Directives for vlog
The following directives are specific to ModelSim and are not compatible with other simulators.
`protect ... `endprotect
This directive pair allows you to encrypt selected regions of your source code. The code
in `protect regions has all debug information stripped out. This behaves exactly as if
using:
vlog -nodebug=ports+pli
except that it applies to selected regions of code rather than the whole file. This enables
usage scenarios such as making module ports, parameters, and specify blocks publicly
visible while keeping the implementation private.
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The `protect directive is ignored by default unless you use the +protect argument to
vlog. Once compiled, the original source file is copied to a new file in the current work
directory. The name of the new file is the same as the original file with a “p” appended
to the suffix. For example, “top.v” is copied to “top.vp”. This new file can be delivered
and used as a replacement for the original source file.
A usage scenario might be that a vendor uses the `protect / `endprotect directives on a
module or a portion of a module in a file named encrypt.v. They compile it with vlog
+protect encrypt.v to produce a new file named encrypt.vp. You can compile
encrypt.vp just like any other verilog file. The protection is not compatible among
different simulators, so the vendor must ship you a different encrypt.vp than they ship to
someone who uses a different simulator.
You can use vlog +protect= to create an encrypted output file, with the
designated filename, in the current directory (not in the work directory, as in the default
case where [=] is not specified). For example:
vlog test.v +protect=test.vp
If the filename is specified in this manner, all source files on the command line are
concatenated together into a single output file. Any `include files are also inserted into
the output file.
`protect and `endprotect directives cannot be nested.
If errors are detected in a protected region, the error message always reports the first line
of the protected block.
`include
If any `include directives occur within a protected region, the compiler generates a copy
of the include file with a .vp suffix and protects the entire contents of the include file.
However, when you use vlog +protect to generate encrypted files, the original source
files must all be complete Verilog modules or packages. Compiler errors result if you
attempt to perform compilation of a set of parameter declarations within a module.
You can avoid such errors by creating a dummy module that includes the parameter
declarations. For example, if you have a file that contains your parameter declarations
and a file that uses those parameters, you can do the following:
module dummy;
`protect
`include "params.v" // contains various parameters
`include "tasks.v" // uses parameters defined in params.v
`endprotect
endmodule
Then, compile the dummy module with the +protect switch to generate an encrypted
output file with no compile errors.
vlog +protect dummy
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After compilation, the work library contains encrypted versions of params.v and tasts.v,
called params.vp and tasks.vp. You may then copy these encrypted files out of the work
directory to more convenient locations. These encrypted files can be included within
your design files; for example:
module main
`include "params.vp"
`include "tasks.vp"
...
Though other simulators have a `protect directive, the algorithm ModelSim uses to encrypt
source files is different. As a result, even though an uncompiled source file with `protect is
compatible with another simulator, once the source is compiled in ModelSim, you could not
simulate it elsewhere.
Verilog-XL Compatible Compiler Directives
The following compiler directives are provided for compatibility with Verilog-XL.
‘default_decay_time