NTC GR8 User Manual V1.0

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GR8

User

Manual
Version 1.0
2017-2-15
Copyright © 2017 Next Thing Co. All Rights Reserved.

Declaration

Copyright © 2017 Next Thing Co. All Rights Reserved.

Revision HIstory

Revision History
Revision

Date

Description

v0.1

Sep.01, 2016

Initial Internal Release

v1.0

Feb.15, 2017

Initial Public Release

Copyright © 2017 Next Thing Co. All Rights Reserved.

Declaration

This page left intentionally blank. \(•◡•)/

Copyright © 2017 Next Thing Co. All Rights Reserved.

Contents
Chapter 1. About This Documentation ...................................................................................................................... 5
1.1. Purpose ....................................................................................................................................................... 5
1.2. Acronyms and Abbreviations ...................................................................................................................... 5
Chapter 2. Overview .................................................................................................................................................. 7
2.1. Processor Overview .................................................................................................................................... 8
2.2. Processor Features...................................................................................................................................... 9
2.2.1. CPU .................................................................................................................................................. 9
2.2.2. GPU .................................................................................................................................................. 9
2.2.3. Memory ........................................................................................................................................... 9
2.2.3.1. Boot ROM ............................................................................................................................. 9
2.2.3.2. SDRAM .................................................................................................................................. 9
2.2.3.3. NAND Flash ........................................................................................................................... 9
2.2.3.4. SD/MMC ............................................................................................................................. 10
2.2.4. System Peripherals ......................................................................................................................... 10
2.2.4.1. CCM..................................................................................................................................... 10
2.2.4.2. DMA .................................................................................................................................... 10
2.2.4.3. PWM ................................................................................................................................... 10
2.2.4.4. Asynchronous Timer ........................................................................................................... 10
2.2.4.5. Synchronic Timer ................................................................................................................ 11
2.2.4.6. Interrupt Controller............................................................................................................. 11
2.2.4.7. LRADC.................................................................................................................................. 11
2.2.4.8. Touch Panel ......................................................................................................................... 11
2.2.4.9. Crypto Engine ...................................................................................................................... 11
2.2.5. Video Engine .................................................................................................................................. 12
2.2.6. Display Processing.......................................................................................................................... 12
2.2.7. Display Output ............................................................................................................................... 12
2.2.8. Image Input .................................................................................................................................... 12
2.2.9. Audio Subsystem............................................................................................................................ 12
2.2.9.1. Audio Codec ........................................................................................................................ 12
2.2.9.2. I2S/PCM .............................................................................................................................. 13
2.2.9.3. OWA .................................................................................................................................... 13
2.2.10. External Peripherals ..................................................................................................................... 13
Copyright © 2017 Next Thing Co. All Rights Reserved.

Contents
2.2.10.1. USB.................................................................................................................................... 13
2.2.10.2. TWI .................................................................................................................................... 14
2.2.10.3. UART ................................................................................................................................. 14
2.2.10.4. SPI ..................................................................................................................................... 14
2.2.10.5. CIR ..................................................................................................................................... 14
2.2.11. Package ........................................................................................................................................ 14
2.3. Block Diagram ........................................................................................................................................... 15
Chapter 3. System .................................................................................................................................................... 17
3.1. Memory Mapping ..................................................................................................................................... 18
3.2. Boot System .............................................................................................................................................. 21
3.2.1. Overview ........................................................................................................................................ 21
3.2.2. Boot Diagram ................................................................................................................................. 21
3.3. PMU .......................................................................................................................................................... 22
3.3.1. Overview ........................................................................................................................................ 22
3.3.2. PMU Register List ........................................................................................................................... 22
3.3.3. PMU Register Description .............................................................................................................. 23
3.3.3.1. PMU DVFS Control Register 0 (Default Value: 0x0000_0000) ............................................. 23
3.3.3.2. PMU DVFS Control Register 1(Default Value: 0x0000_1010).............................................. 25
3.3.3.3. PMU DVFS Control Register 2 (Default Value: 0x0000_0000) ............................................. 25
3.3.3.4. PMU AXI Clock Range Register0 (Default Value: 0x0000_0000) ......................................... 25
3.3.3.5. PMU AXI Clock Range Register1 (Default Value: 0x0000_0000) ......................................... 25
3.3.3.6. PMU DVFS Control Register 3 ............................................................................................. 26
3.3.3.7. PMU DVFS Timeout Control Register(Default Value: 0x0000_0027) .................................. 26
3.3.3.8. PMU IRQ En Register (Default Value: 0x0000_0000) .......................................................... 26
3.3.3.9. PMU IRQ Status Register (Default Value: 0x00000000) ...................................................... 28
3.3.3.10. PMU Status Register (Default Value: 0x0000_0000) ......................................................... 30
3.3.3.11. PMU CPUVDD DCDC Control Register Address(Default Value: 0x0000_0023) ................. 30
3.3.3.12. PMU TWI Address(Default Value: 0x0000_0068) ............................................................. 30
3.3.3.13. PMU CPUVDD Value(Default Value: 0x0000_0016) .......................................................... 30
3.3.3.14. PMU CPUVDD Voltage Ramp Control in DVM (Default Value: 0x0000_0000) .................. 31
3.3.3.15. PMU 32KHz CPUVDD Minimum Value(Default Value: 0x0000_000C) .............................. 32
3.3.3.16. PMU VF Table Register 0 ................................................................................................... 32
3.3.3.17. PMU VF Table Register 1 ................................................................................................... 33
3.3.3.18. PMU VF Table Register 2 ................................................................................................... 33
3.3.3.19. PMU VF Table Register 3 ................................................................................................... 33
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Contents
3.3.3.20. PMU VF Table Register 4 ................................................................................................... 33
3.3.3.21. PMU VF Table Register 5 ................................................................................................... 33
3.3.3.22. PMU VF Table Register 6 ................................................................................................... 34
3.3.3.23. PMU VF Table Register 7 ................................................................................................... 34
3.3.3.24. PMU VF Table Register 8 ................................................................................................... 34
3.3.3.25. PMU VF Table Register 9 ................................................................................................... 34
3.3.3.26. PMU VF Table Register 10 ................................................................................................. 35
3.3.3.27. PMU VF Table Register 11 ................................................................................................. 35
3.3.3.28. PMU VF Table Register 12 ................................................................................................. 35
3.3.3.29. PMU VF Table Register 13 ................................................................................................. 35
3.3.3.30. PMU VF Table Register 14 ................................................................................................. 36
3.3.3.31. PMU VF Table Register 15 ................................................................................................. 36
3.3.3.32. PMU VF Table Register 16 ................................................................................................. 36
3.3.3.33. PMU VF Table Register 17 ................................................................................................. 36
3.3.3.34. PMU VF Table Register 18 ................................................................................................. 36
3.3.3.35. PMU VF Table Valid Register (Default Value: 0x0000_003C) ............................................ 37
3.3.3.36. PMU VF Table Index Register (Default Value: 0x0000_0000) ........................................... 38
3.3.3.37. PMU VF Table Range Register (Default Value: 0x0000_0000) .......................................... 38
3.3.3.38. PMU Speed Factor Register 0 (Default Value: 0x0000_0000) ........................................... 38
3.3.3.39. PMU Speed Factor Register 1 (Default Value: 0x0000_0000) ........................................... 39
3.3.3.40. PMU Speed Factor Register 2 (Default Value: 0x0000_0000) ........................................... 40
3.3.3.41. CPU Idle Counter Low Register (Default Value: 0x0000_0000)......................................... 41
3.3.3.42. CPU Idle Counter High Register (Default Value: 0x0000_0000) ........................................ 41
3.3.3.43. CPU Idle Control Register (Default Value: 0x0000_0000) ................................................. 42
3.3.3.44. CPU Idle Status Register (Default Value: 0x0000_0000) ................................................... 43
3.4. Clock Control Module (CCM) .................................................................................................................... 44
3.4.1. Overview ........................................................................................................................................ 44
3.4.2. Clock Tree Diagram ........................................................................................................................ 45
3.4.3. CCM Register List ........................................................................................................................... 47
3.4.4. CCM Register Description .............................................................................................................. 49
3.4.4.1. PLL1-Core Register (Default Value: 0x2100_5000) ............................................................. 49
3.4.4.2. PLL1-Tuning Register (Default Value: 0x0A10_1000) .......................................................... 50
3.4.4.3. PLL2-Audio Register (Default Value: 0x0810_0010) ........................................................... 51
3.4.4.4. PLL2-Tuning Register (Default Value: 0x0000_0000) .......................................................... 52
3.4.4.5. PLL3-Video Register (Default Value: 0x0010_D063) ........................................................... 52
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Contents
3.4.4.6. PLL4-VE Register (Default Value: 0x2108_1000) ................................................................. 53
3.4.4.7. PLL5-DDR Register (Default Value: 0x1104_9280) .............................................................. 54
3.4.4.8. PLL5-Tuning Register (Default Value: 0x1488_0000) .......................................................... 56
3.4.4.9. PLL6 Register (Default Value: 0x2100_9931) ...................................................................... 56
3.4.4.10. PLL7 Register (Default Value: 0x0010_D063) .................................................................... 57
3.4.4.11. PLL1-Tuning2 Register (Default Value: 0x0000_0000) ...................................................... 58
3.4.4.12. PLL5-Tuning2 Register (Default Value: 0x0000_0000) ...................................................... 58
3.4.4.13. OSC24M Register (Default Value: 0x0013_8013).............................................................. 59
3.4.4.14. CPU/AHB/APB0 Clock Ratio Register (Default Value: 0x0001_0010) ................................ 60
3.4.4.15. APB1 Clock Divide Ratio Register (Default Value: 0x0000_0000) ..................................... 61
3.4.4.16. AXI Module Clock Gating Register (Default Value: 0x0000_0000) .................................... 62
3.4.4.17. AHB Module Clock Gating Register 0(Default Value: 0x0000_0000) ................................ 62
3.4.4.18. AHB Module Clock Gating Register 1(Default Value: 0x0000_0000) ................................ 63
3.4.4.19. APB0 Module Clock Gating Register (Default Value: 0x0000_0000)................................. 64
3.4.4.20. APB1 Module Clock Gating Register (Default Value: 0x0000_0000)................................. 64
3.4.4.21. NAND Clock Register (Default Value: 0x0000_0000) ........................................................ 65
3.4.4.22. SD0 Clock Register (Default Value: 0x0000_0000) ............................................................ 66
3.4.4.23. SD1 Clock Register (Default Value: 0x0000_0000) ............................................................ 67
3.4.4.24. SD2 Clock Register (Default Value: 0x0000_0000) ............................................................ 68
3.4.4.25. CE Clock Register (Default Value: 0x0000_0000) .............................................................. 68
3.4.4.26. SPI0 Clock Register (Default Value: 0x0000_0000) ........................................................... 69
3.4.4.27. SPI2 Clock Register (Default Value: 0x0000_0000) ........................................................... 70
3.4.4.28. IR Clock Register (Default Value: 0x0000_0000) ............................................................... 71
3.4.4.29. I2S/PCM Clock Register (Default Value: 0x0000_0000) .................................................... 72
3.4.4.30. I2S/PCM Clock Register (Default Value: 0x0001_0000) .................................................... 72
3.4.4.31. USB PHY Clock Register (Default Value: 0x0000_0000) .................................................... 73
3.4.4.32. DRAM Clock Register (Default Value: 0x0000_0000) ........................................................ 73
3.4.4.33. DE-BE Clock Register (Default Value: 0x0000_0000) ........................................................ 74
3.4.4.34. DE-FE Clock Register (Default Value: 0x0000_0000) ......................................................... 75
3.4.4.35. LCD CH0 Clock Register (Default Value: 0x0000_0000) .................................................... 76
3.4.4.36. LCD CH1 Clock Register (Default Value: 0x0000_0000) .................................................... 77
3.4.4.37. CSI Clock Register (Default Value: 0x0000_0000) ............................................................. 78
3.4.4.38. VE Clock Register (Default Value: 0x0000_0000) .............................................................. 79
3.4.4.39. Audio Codec Clock Register (Default Value: 0x0000_0000) .............................................. 79
3.4.4.40. AVS Clock Register (Default Value: 0x0000_0000) ............................................................ 80
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Contents
3.4.4.41. Mali-400 Clock Register(Default Value: 0x0000_0000)..................................................... 80
3.4.4.42. MBUS Clock Control Register (Default Value: 0x0000_0000) ........................................... 81
3.4.4.43. IEP Clock Control Register (Default Value: 0x0000_0000) ................................................ 82
3.5. System Control .......................................................................................................................................... 83
3.5.1. Overview ........................................................................................................................................ 83
3.5.2. System Control Register List........................................................................................................... 83
3.5.3. System Control Register Description.............................................................................................. 83
3.5.3.1. SRAM Configuration Register 0(Default Value: 0x7FFF_FFFF) ............................................ 83
3.5.3.2. SRAM Configuration Register 1(Default Value: 0x0000_1000) ........................................... 84
3.6. CPU Control............................................................................................................................................... 85
3.6.1. CPU Register List ............................................................................................................................ 85
3.6.2. CPU Control Register Description .................................................................................................. 85
3.6.2.1. CPU Control Register(Default Value:0x0000_0002) ............................................................ 85
3.7. PWM ......................................................................................................................................................... 86
3.7.1. Overview ........................................................................................................................................ 86
3.7.2. PWM Register List .......................................................................................................................... 86
3.7.3. PWM Register Description ............................................................................................................. 86
3.7.3.1. PWM Control Register (Default Value: 0x0000_0000) ........................................................ 86
3.7.3.2. PWM Channel 0 Period Register ......................................................................................... 90
3.7.3.3. PWM Channel 1 Period Register ......................................................................................... 90
3.8. Asynchronous Timer ................................................................................................................................. 92
3.8.1. Overview ........................................................................................................................................ 92
3.8.2. ASYNC Timer Register List .............................................................................................................. 92
3.8.3. ASYNC Timer Register Description ................................................................................................. 93
3.8.3.1. ASYNC Timer IRQ Enable Register (Default Value: 0x0000_0000) ...................................... 93
3.8.3.2. ASYNC Timer IRQ Status Register(Default Value: 0x0000_0000) ........................................ 94
3.8.3.3. ASYNC Timer 0 Control Register (Default Value: 0x0000_0004) ......................................... 95
3.8.3.4. ASYNC Timer 0 Interval Value Register ............................................................................... 97
3.8.3.5. ASYNC Timer 0 Current Value Register (Default Value: 0x0000_0000) ............................... 97
3.8.3.6. ASYNC Timer 1 Control Register (Default Value: 0x0000_0004) ......................................... 97
3.8.3.7. ASYNC Timer 1 Interval Value Register ............................................................................... 99
3.8.3.8. ASYNC Timer 1 Current Value Register ............................................................................... 99
3.8.3.9. ASYNC Timer 2 Control Register (Default Value: 0x0000_0004) ......................................... 99
3.8.3.10. ASYNC Timer 2 Interval Value Register ........................................................................... 100
3.8.3.11. ASYNC Timer 2 Current Value Register ........................................................................... 101
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Contents
3.8.3.12. ASYNC Timer 3 Control Register (Default Value: 0x0000_0000) ..................................... 101
3.8.3.13. ASYNC Timer 3 Interval Value ......................................................................................... 102
3.8.3.14. ASYNC Timer 4 Control Register (Default Value: 0x0000_0004) ..................................... 102
3.8.3.15. ASYNC Timer 4 Interval Value Register ........................................................................... 103
3.8.3.16. ASYNC Timer 4 Current Value Register ........................................................................... 104
3.8.3.17. ASYNC Timer 5 Control Register (Default Value: 0x0000_0004) ..................................... 104
3.8.3.18. ASYNC Timer 5 Interval Value Register ........................................................................... 105
3.8.3.19. ASYNC Timer 5 Current Value Register ........................................................................... 106
3.8.3.20. AVS Counter Control Register (Default Value: 0x0000_0000) ......................................... 106
3.8.3.21. AVS Counter 0 Register (Default Value: 0x0000_0000)................................................... 107
3.8.3.22. AVS Counter 1 Register (Default Value: 0x0000_0000)................................................... 107
3.8.3.23. AVS Counter Divisor Register (Default Value: 0x05DB_05DB) ........................................ 107
3.8.3.24. Watchdog Control Register ............................................................................................. 108
3.8.3.25. Watchdog Mode Register (Default Value: 0x0000_0000) ............................................... 108
3.8.3.26. 64-bit Counter Low Register (Default Value: 0x0000_0000)........................................... 110
3.8.3.27. 64-bit Counter High Register (Default Value: 0x0000_0000) .......................................... 110
3.8.3.28. 64-bit Counter Control Register (Default Value: 0x0000_0000) ..................................... 110
3.8.3.29. CPU Config Register (Default Value: 0x0000_0000) ........................................................ 111
3.9. Synchronic Timer .................................................................................................................................... 112
3.9.1. Overview ...................................................................................................................................... 112
3.9.2. Sync Timer Register List ............................................................................................................... 112
3.9.3. Sync Timer Register Description .................................................................................................. 112
3.9.3.1. Sync Timer IRQ Enable Register (Default Value: 0x0000_0000) ....................................... 112
3.9.3.2. Sync Timer IRQ Status Register(Default Value: 0x0000_0000) ......................................... 113
3.9.3.3. Sync Timer 0 Control Register (Default Value: 0x0000_0004) .......................................... 113
3.9.3.4. Sync Timer 0 Interval Value Low Register ......................................................................... 114
3.9.3.5. Sync Timer 0 Interval Value High Register ........................................................................ 115
3.9.3.6. Sync Timer 0 Current Value Lo Register ............................................................................ 115
3.9.3.7. Sync Timer 0 Current Value Hi Register ............................................................................ 115
3.9.3.8. Sync Timer 1 Control Register (Default Value: 0x0000_0004) .......................................... 115
3.9.3.9. Sync Timer 1 Interval Value Low Register ......................................................................... 117
3.9.3.10. Sync Timer 1 Interval Value High Register ...................................................................... 117
3.9.3.11. Sync Timer 1 Current Value Low Register ....................................................................... 117
3.9.3.12. Sync Timer 1 Current Value High Register ...................................................................... 117
3.10. Interrupt Controller .............................................................................................................................. 119
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Contents
3.10.1. Overview .................................................................................................................................... 119
3.10.2. Interrupt Source ......................................................................................................................... 119
3.10.3. Interrupt Register List ................................................................................................................ 122
3.10.4. Interrupt Register Description ................................................................................................... 123
3.10.4.1. Interrupt Vector Register (Default Value: 0x0000_0000)................................................ 123
3.10.4.2. Interrupt Base Address Register (Default Value: 0x0000_0000) ..................................... 123
3.10.4.3. Interrupt Protection Register (Default Value: 0x0000_0000) ......................................... 123
3.10.4.4. NMI Interrupt Control Register (Default Value: 0x0000_0000) ...................................... 124
3.10.4.5. Interrupt IRQ Pending Register 0(Default Value: 0x0000_0000) .................................... 124
3.10.4.6. Interrupt IRQ Pending Register 1(Default Value: 0x0000_0000) .................................... 124
3.10.4.7. Interrupt IRQ Pending Register 2(Default Value: 0x0000_0000) .................................... 125
3.10.4.8. Interrupt FIQ Pending/Clear Register 0 (Default Value: 0x0000_0000) .......................... 125
3.10.4.9. Interrupt FIQ Pending/Clear Register 1(Default Value: 0x0000_0000) ........................... 125
3.10.4.10. Interrupt FIQ Pending/Clear Register 2(Default Value: 0x0000_0000) ......................... 125
3.10.4.11. Interrupt Select Register 0(Default Value: 0x0000_0000) ............................................ 126
3.10.4.12. Interrupt Select Register 1(Default Value: 0x0000_0000) ............................................ 126
3.10.4.13. Interrupt Select Register 2(Default Value: 0x0000_0000) ............................................ 126
3.10.4.14. Interrupt Enable Register 0(Default Value: 0x0000_0000) ........................................... 127
3.10.4.15. Interrupt Enable Register 1(Default Value: 0x0000_0000) ........................................... 127
3.10.4.16. Interrupt Enable Register 2(Default Value: 0x0000_0000) ........................................... 127
3.10.4.17. Interrupt Mask Register 0(Default Value: 0x0000_0000) ............................................. 127
3.10.4.18. Interrupt Mask Register 1(Default Value: 0x0000_0000) ............................................. 128
3.10.4.19. Interrupt Mask Register 2(Default Value: 0x0000_0000) ............................................. 128
3.10.4.20. Interrupt Response Register 0(Default Value: 0x0000_0000) ....................................... 128
3.10.4.21. Interrupt Response Register 1(Default Value: 0x0000_0000) ....................................... 129
3.10.4.22. Interrupt Response Register 2(Default Value: 0x0000_0000) ....................................... 129
3.10.4.23. Interrupt Fast Forcing Register 0(Default Value: 0x0000_0000) ................................... 129
3.10.4.24. Interrupt Fast Forcing Register 1(Default Value: 0x0000_0000) ................................... 129
3.10.4.25. Interrupt Fast Forcing Register 2(Default Value: 0x0000_0000) ................................... 130
3.10.4.26. Interrupt Source Priority 0 Register (Default Value: 0x0000_0000) ............................. 130
3.10.4.27. Interrupt Source Priority 1 Register (Default Value: 0x0000_0000) ............................. 134
3.10.4.28. Interrupt Source Priority 2 Register (Default Value: 0x0000_0000) ............................. 138
3.10.4.29. Interrupt Source Priority 3 Register (Default Value: 0x0000_0000) ............................. 141
3.10.4.30. Interrupt Source Priority 4 Register (Default Value: 0x0000_0000) ............................. 145
3.10.4.31. Interrupt Source Priority 5 Register (Default Value: 0x0000_0000) ............................. 149
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Contents
3.11. DMA ...................................................................................................................................................... 154
3.11.1. Overview .................................................................................................................................... 154
3.11.2. DMA Description ........................................................................................................................ 154
3.11.3. DMA Register List ....................................................................................................................... 154
3.11.4. DMA Register Description .......................................................................................................... 155
3.11.4.1. DMA IRQ Enable Register (Default Value: 0x0000_0000) ............................................... 155
3.11.4.2. DMA IRQ Pending Status Register (Default Value: 0x0000_0000) .................................. 159
3.11.4.3. Normal DMA Configuration Register (Default Value: 0x0000_0000) .............................. 165
3.11.4.4. Normal DMA Source Address Register............................................................................ 169
3.11.4.5. Normal DMA Destination Address Register .................................................................... 169
3.11.4.6. Normal DMA Byte Counter Register ............................................................................... 169
3.11.4.7. Dedicated DMA Configuration Register (Default Value: 0x0000_0000) ......................... 169
3.11.4.8. Dedicated DMA Source Start Address Register............................................................... 173
3.11.4.9. Dedicated DMA Destination Start Address Register ....................................................... 174
3.11.4.10. Dedicated DMA Byte Counter Register ......................................................................... 174
3.11.4.11. Dedicated DMA Parameter Register ............................................................................. 174
3.12. LRADC ................................................................................................................................................... 175
3.12.1. Overview .................................................................................................................................... 175
3.12.2. Block Diagram ............................................................................................................................ 175
3.12.3. LRADC Control Logic................................................................................................................... 176
3.12.4. LRADC Register List .................................................................................................................... 176
3.12.5. LRADC Register Description ....................................................................................................... 177
3.12.5.1. LRADC Control Register(Default Value: 0x0100_0168) ................................................... 177
3.12.5.2. LRADC Interrupt Control Register(Default Value: 0x0000_0000) ................................... 178
3.12.5.3. LRADC Interrupt Status Register(Default Value: 0x0000_0000) ..................................... 180
3.12.5.4. LRADC Data 0 Register(Default Value: 0x0000_0000) .................................................... 183
3.12.5.5. LRADC Data 1 Register(Default Value: 0x0000_0000) .................................................... 183
3.13. Touch Panel ........................................................................................................................................... 184
3.13.1. Overview .................................................................................................................................... 184
3.13.2. Typical Application Circuit .......................................................................................................... 184
3.13.3. Clock Tree and ADC Time ........................................................................................................... 185
3.13.3.1. Clock Tree ........................................................................................................................ 185
3.13.3.2. A/D Conversion Time ...................................................................................................... 185
3.13.4. Principle of Operation ................................................................................................................ 186
3.13.4.1. The Basic Principle .......................................................................................................... 186
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Contents
3.13.4.2. Single-ended Mode ......................................................................................................... 186
3.13.4.3. Differential Mode ............................................................................................................ 187
3.13.4.4. Single Touch Detection ................................................................................................... 188
3.13.4.5. Touch-Pressure Measurement ........................................................................................ 188
3.13.4.6. Pen Down Detection ....................................................................................................... 189
3.13.4.7. Median and Averaging Filter ........................................................................................... 190
3.13.5. TP Register List ........................................................................................................................... 191
3.13.6. TP Register Description .............................................................................................................. 191
3.13.6.1. TP Control Register 0(Default Value: 0x0F80_0000) ....................................................... 191
3.13.6.2. TP Control Register 1(Default Value: 0x0000_0008) ....................................................... 192
3.13.6.3. TP Control Register 2(Default Value: 0x8000_0FFF) ....................................................... 194
3.13.6.4. Median Filter Control Register(Default Value: 0x0000_0001) ........................................ 194
3.13.6.5. TP Interrupt& FIFO Control Register(Default Value: 0x0000_0F00) ............................... 195
3.13.6.6. TP Interrupt& FIFO Status Register(Default Value: 0x0000_0000) ................................. 196
3.13.6.7. Common Data Register(Default Value: 0x0000_0000) ................................................... 198
3.13.6.8. TP Data Register(Default Value: 0x0000_0000) .............................................................. 198
3.13.6.9. TP Port IO Configure Register(Default Value: 0x0000_2222) .......................................... 198
3.13.6.10. TP Port Data Register(Default Value: 0x0000_0000) .................................................... 199
3.14. Crypto Engine........................................................................................................................................ 200
3.14.1. Overview .................................................................................................................................... 200
3.14.2. Crypto Engine Block Diagram..................................................................................................... 200
3.14.3. Crypto Engine Register List ........................................................................................................ 200
3.14.4. Crypto Engine Register Description ........................................................................................... 201
3.14.4.1. Crypto Engine Control Register(Default Value: 0x0000_0000) ....................................... 201
3.14.4.2. Crypto Engine Key [n] Register(Default Value: 0x0000_0000) ........................................ 203
3.14.4.3. Crypto Engine IV[n] Register(Default Value: 0x0000_0000) ........................................... 203
3.14.4.4. Crypto Engine FIFO Control/ Status Register(Default Value: 0x6000_0F0F) ................... 203
3.14.4.5. Crypto Engine Interrupt Control/Status Register(Default Value: 0x0000_0000) ............ 204
3.14.4.6. Crypto Engine Message Digest[n] Register(Default Value: 0x0000_0000) ..................... 205
3.14.4.7. Crypto Engine RX FIFO Register(Default Value: 0x0000_0000) ....................................... 205
3.14.4.8. Crypto Engine TX FIFO Register(Default Value: 0x0000_0000) ....................................... 205
3.14.5. Crypto Engine Clock Requirement ............................................................................................. 205
3.15. Security ID ............................................................................................................................................. 207
3.15.1. Overview .................................................................................................................................... 207
3.16. Port Controller ...................................................................................................................................... 208
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Contents
3.16.1. Overview .................................................................................................................................... 208
3.16.2. Port Configuration Table ............................................................................................................ 208
3.16.3. Port Register List ........................................................................................................................ 210
3.16.4. Port Register Description ........................................................................................................... 210
3.16.4.1. PB Configure Register 0(Default Value: 0x0000_0000) ................................................... 210
3.16.4.2. PB Configure Register 1(Default Value: 0x0000_0000) ................................................... 212
3.16.4.3. PB Configure Register 2(Default Value: 0x0000_0000) ................................................... 214
3.16.4.4. PB Configure Register 3(Default Value: 0x0000_0000) ................................................... 215
3.16.4.5. PB Data Register(Default Value: 0x00000000) ................................................................ 215
3.16.4.6. PB Multi-Driving Register 0(Default Value: 0x5555_5555) ............................................. 215
3.16.4.7. PB Multi-Driving Register 1(Default Value: 0x0000_0155) ............................................. 215
3.16.4.8. PB Pull Register 0(Default Value: 0x0000_0000) ............................................................ 216
3.16.4.9. PB Pull Register 1(Default Value: 0x0000_0000) ............................................................ 216
3.16.4.10. PC Configure Register 0(Default Value: 0x0000_0000) ................................................. 216
3.16.4.11. PC Configure Register 1(Default Value: 0x0000_0000) ................................................. 218
3.16.4.12. PC Configure Register 2(Default Value: 0x0000_0000) ................................................. 220
3.16.4.13. PC Configure Register 3(Default Value: 0x0000_0000) ................................................. 220
3.16.4.14. PC Data Register(Default Value: 0x0000_0000) ............................................................ 220
3.16.4.15. PC Multi-Driving Register 0(Default Value: 0x5555_5555) ........................................... 220
3.16.4.16. PC Multi-Driving Register 1(Default Value: 0x0000_0055) ........................................... 221
3.16.4.17. PC Pull Register 0(Default Value: 0x0000_5140) .......................................................... 221
3.16.4.18. PC Pull Register 1(Default Value: 0x0000_0016) .......................................................... 221
3.16.4.19. PD Configure Register 0(Default Value: 0x0000_0000) ................................................ 221
3.16.4.20. PD Configure Register 1(Default Value: 0x0000_0000) ................................................ 223
3.16.4.21. PD Configure Register 2(Default Value: 0x0000_0000) ................................................ 224
3.16.4.22. PD Configure Register 3(Default Value: 0x00000000) .................................................. 226
3.16.4.23. PD Data Register(Default Value: 0x0000_0000)............................................................ 227
3.16.4.24. PD Multi-Driving Register 0(Default Value: 0x5555_5555) ........................................... 227
3.16.4.25. PD Multi-Driving Register 1(Default Value: 0x0055_5555) ........................................... 227
3.16.4.26. PD Pull Register 0(Default Value: 0x0000_0000) .......................................................... 227
3.16.4.27. PD Pull Register 1(Default Value: 0x0000_0000) .......................................................... 228
3.16.4.28. PE Configure Register 0(Default Value: 0x0000_0000) ................................................. 228
3.16.4.29. PE Configure Register 1(Default Value: 0x0000_0000) ................................................. 230
3.16.4.30. PE Configure Register 2(Default Value: 0x0000_0000) ................................................. 231
3.16.4.31. PE Configure Register 3(Default Value: 0x0000_0000) ................................................. 231
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Contents
3.16.4.32. PE Data Register(Default Value: 0x0000_0000) ............................................................ 231
3.16.4.33. PE Multi-Driving Register 0(Default Value: 0x0055_5555) ........................................... 231
3.16.4.34. PE Multi-Driving Register 1(Default Value: 0x0000_0000) ........................................... 231
3.16.4.35. PE Pull Register 0(Default Value: 0x0000_0000) ........................................................... 231
3.16.4.36. PE Pull Register 1(Default Value: 0x0000_0000) ........................................................... 232
3.16.4.37. PF Configure Register 0(Default Value: 0x0040_4044) ................................................. 232
3.16.4.38. PF Configure Register 1(Default Value: 0x0000_0000) ................................................. 233
3.16.4.39. PF Configure Register 2(Default Value: 0x0000_0000) ................................................. 233
3.16.4.40. PF Configure Register 3(Default Value: 0x0000_0000) ................................................. 234
3.16.4.41. PF Data Register(Default Value: 0x0000_0000) ............................................................ 234
3.16.4.42. PF Multi-Driving Register 0(Default Value: 0x0000_0555)............................................ 234
3.16.4.43. PF Multi-Driving Register 1(Default Value: 0x0000_0000)............................................ 234
3.16.4.44. PF Pull Register 0(Default Value: 0x0000_0000) ........................................................... 234
3.16.4.45. PF Pull Register 1(Default Value: 0x0000_0000) ........................................................... 235
3.16.4.46. PG Configure Register 0(Default Value: 0x0000_0000) ................................................ 235
3.16.4.47. PG Configure Register 1(Default Value: 0x0000_0000) ................................................ 236
3.16.4.48. PG Configure Register 2(Default Value: 0x0000_0000) ................................................ 238
3.16.4.49. PG Configure Register 3(Default Value: 0x0000_0000) ................................................ 238
3.16.4.50. PG Data Register(Default Value: 0x0000_0000) ........................................................... 238
3.16.4.51. PG Multi-Driving Register 0(Default Value: 0x0555_5555) ........................................... 238
3.16.4.52. PG Multi-Driving Register 1(Default Value: 0x0000_0000) ........................................... 239
3.16.4.53. PG Pull Register 0(Default Value: 0x0000_0000) .......................................................... 239
3.16.4.54. PG Pull Register 1(Default Value: 0x0000_0000) .......................................................... 239
3.16.4.55. PIO Interrupt Configure Register 0(Default Value: 0x0000_0000) ................................ 239
3.16.4.56. PIO Interrupt Configure Register 1(Default Value: 0x0000_0000) ................................ 240
3.16.4.57. PIO Interrupt Configure Register 2(Default Value: 0x0000_0000) ................................ 240
3.16.4.58. PIO Interrupt Configure Register 3(Default Value: 0x0000_0000) ................................ 240
3.16.4.59. PIO Interrupt Control Register(Default Value: 0x0000_0000) ...................................... 241
3.16.4.60. PIO Interrupt Status Register(Default Value: 0x0000_0000) ........................................ 241
3.16.4.61. PIO Interrupt Debounce Register(Default Value: 0x0000_0000) .................................. 241
Chapter 4. Memory................................................................................................................................................ 242
4.1. SDRAM Controller ................................................................................................................................... 243
4.1.1. Overview ...................................................................................................................................... 243
4.2. NAND Flash ............................................................................................................................................. 244
4.2.1. Overview ...................................................................................................................................... 244
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Contents
4.2.2. Block Diagram .............................................................................................................................. 245
4.2.3. NFC Timing Diagram .................................................................................................................... 245
4.2.4. NFC Read and Write Diagram ...................................................................................................... 250
4.3. SD/MMC Controller ................................................................................................................................ 252
4.3.1. Overview ...................................................................................................................................... 252
4.3.2. SD/MMC Timing Diagram ............................................................................................................ 252
Chapter 5. Image.................................................................................................................................................... 253
5.1. CSI ........................................................................................................................................................... 254
5.1.1. Overview ...................................................................................................................................... 254
5.1.2. CSI Block Diagram ........................................................................................................................ 254
5.1.3. CCIR656 Format ........................................................................................................................... 254
5.1.3.1. Header Data Bit Definition ................................................................................................ 254
5.1.3.2. CCIR656 Header Decode ................................................................................................... 255
5.1.4. CSI Timing Diagram ...................................................................................................................... 255
5.1.5. CSI Register List ............................................................................................................................ 255
5.1.6. CSI Register Description ............................................................................................................... 256
5.1.6.1. CSI Enable Register(Default Value: 0x0000_0000) ............................................................ 256
5.1.6.2. CSI Configuration Register(Default Value: 0x0000_0200) ................................................ 256
5.1.6.3. CSI Capture Control Register(Default Value: 0x0000_0000) ............................................. 258
5.1.6.4. CSI FIFO0 Buffer A Register(Default Value: 0x0000_0000) ............................................... 259
5.1.6.5. CSI FIFO0 Buffer B Register(Default Value: 0x0000_0000) ............................................... 259
5.1.6.6. CSI FIFO1 Buffer A Register(Default Value: 0x0000_0000) ............................................... 259
5.1.6.7. CSI FIFO1 Buffer B Register(Default Value: 0x0000_0000) ............................................... 260
5.1.6.8. CSI Buffer Control Register(Default Value: 0x0000_0000)................................................ 260
5.1.6.9. CSI Status Register(Default Value: 0x0000_0000) ............................................................ 260
5.1.6.10. CSI Interrupt Enable Register(Default Value: 0x0000_0000) .......................................... 261
5.1.6.11. CSI Interrupt Status Register(Default Value: 0x0000_0000) ........................................... 262
5.1.6.12. CSI Window Width Control Register(Default Value: 0x0500_0000) ............................... 263
5.1.6.13. CSI Window Height Control Register(Default Value: 0x01E0_0000) .............................. 263
5.1.6.14. CSI Buffer Length Register(Default Value: 0x0000_0280)............................................... 263
Chapter 6. Display .................................................................................................................................................. 264
6.1. Display Engine Front End (DEFE) ............................................................................................................. 265
6.1.1. Overview ...................................................................................................................................... 265
6.1.2. DEFE Block Diagram ..................................................................................................................... 265
6.1.3. DEFE Register List ......................................................................................................................... 266
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Contents
6.1.4. DEFE Register Description ............................................................................................................ 267
6.1.4.1. DEFE_EN_REG(Default Value: 0x0000_0000) ................................................................... 267
6.1.4.2. DEFE_FRM_CTRL_REG(Default Value: 0x0000_0000) ...................................................... 268
6.1.4.3. DEFE_BYPASS_REG(Default Value: 0x0000_0000) ............................................................ 269
6.1.4.4. DEFE_AGTH_SEL_REG(Default Value: 0x0000_0000) ....................................................... 269
6.1.4.5. DEFE_LINT_CTRL_REG(Default Value: 0x0000_0000) ....................................................... 270
6.1.4.6. DEFE_BUF_ADDR0_REG(Default Value: 0x0000_0000) .................................................... 270
6.1.4.7. DEFE_BUF_ADDR1_REG(Default Value: 0x0000_0000) .................................................... 271
6.1.4.8. DEFE_BUF_ADDR2_REG(Default Value: 0x0000_0000) .................................................... 271
6.1.4.9. DEFE_FIELD_CTRL_REG(Default Value: 0x0000_0000) ..................................................... 271
6.1.4.10. DEFE_TB_OFF0_REG(Default Value: 0x0000_0000) ....................................................... 272
6.1.4.11. DEFE_TB_OFF1_REG(Default Value: 0x0000_0000) ....................................................... 272
6.1.4.12. DEFE_TB_OFF2_REG(Default Value: 0x0000_0000) ....................................................... 272
6.1.4.13. DEFE_LINESTRD0_REG(Default Value: 0x0000_0000) .................................................... 273
6.1.4.14. DEFE_LINESTRD1_REG(Default Value: 0x0000_0000) .................................................... 273
6.1.4.15. DEFE_LINESTRD2_REG(Default Value: 0x0000_0000) .................................................... 273
6.1.4.16. DEFE_INPUT_FMT_REG(Default Value: 0x0000_0000) .................................................. 274
6.1.4.17. DEFE_WB_ADDR0_REG(Default Value: 0x0000_0000) ................................................... 276
6.1.4.18. DEFE_OUTPUT_FMT_REG(Default Value: 0x0000_0000) ............................................... 276
6.1.4.19. DEFE_INT_EN_REG(Default Value: 0x0000_0000) .......................................................... 278
6.1.4.20. DEFE_INT_STATUS_REG(Default Value: 0x0000_0000) .................................................. 278
6.1.4.21. DEFE_STATUS_REG(Default Value: 0x0000_0000) ......................................................... 278
6.1.4.22. DEFE_CSC_COEF00_REG(Default Value: 0x0000_0000) ................................................. 280
6.1.4.23. DEFE_CSC_COEF01_REG(Default Value: 0x0000_0000) ................................................. 280
6.1.4.24. DEFE_CSC_COEF02_REG(Default Value: 0x0000_0000) ................................................. 281
6.1.4.25. DEFE_CSC_COEF03_REG(Default Value: 0x0000_0000) ................................................. 281
6.1.4.26. DEFE_CSC_COEF10_REG(Default Value: 0x0000_0000) ................................................. 281
6.1.4.27. DEFE_CSC_COEF11_REG(Default Value: 0x0000_0000) ................................................. 281
6.1.4.28. DEFE_CSC_COEF12_REG(Default Value: 0x0000_0000) ................................................. 282
6.1.4.29. DEFE_CSC_COEF13_REG(Default Value: 0x0000_0000) ................................................. 282
6.1.4.30. DEFE_CSC_COEF20_REG(Default Value: 0x0000_0000) ................................................. 282
6.1.4.31. DEFE_CSC_COEF21_REG(Default Value: 0x0000_0000) ................................................. 282
6.1.4.32. DEFE_CSC_COEF22_REG(Default Value: 0x0000_0000) ................................................. 283
6.1.4.33. DEFE_CSC_COEF23_REG(Default Value: 0x0000_0000) ................................................. 283
6.1.4.34. DEFE_WB_LINESTRD_EN_REG(Default Value: 0x0000_0000) ........................................ 283
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Contents
6.1.4.35. DEFE_WB_LINESTRD0_REG(Default Value: 0x0000_0000) ............................................ 283
6.1.4.36. DEFE_CH0_INSIZE_REG(Default Value: 0x0000_0000) ................................................... 284
6.1.4.37. DEFE_CH0_OUTSIZE_REG(Default Value: 0x0000_0000) ............................................... 284
6.1.4.38. DEFE_CH0_HORZFACT_REG(Default Value: 0x0000_0000) ............................................ 284
6.1.4.39. DEFE_CH0_VERTFACT_REG(Default Value: 0x0000_0000) ............................................. 285
6.1.4.40. DEFE_CH0_HORZPHASE_REG(Default Value: 0x0000_0000) ......................................... 285
6.1.4.41. DEFE_CH0_VERTPHASE0_REG(Default Value: 0x0000_0000) ........................................ 285
6.1.4.42. DEFE_CH0_VERTPHASE1_REG(Default Value: 0x0000_0000) ........................................ 285
6.1.4.43. DEFE_CH1_INSIZE_REG(Default Value: 0x0000_0000) ................................................... 286
6.1.4.44. DEFE_CH1_OUTSIZE_REG(Default Value: 0x0000_0000) ............................................... 286
6.1.4.45. DEFE_CH1_HORZFACT_REG(Default Value: 0x0000_0000) ............................................ 286
6.1.4.46. DEFE_CH1_VERTFACT_REG(Default Value: 0x0000_0000) ............................................. 287
6.1.4.47. DEFE_CH1_HORZPHASE_REG(Default Value: 0x0000_0000) ......................................... 287
6.1.4.48. DEFE_CH1_VERTPHASE0_REG(Default Value: 0x0000_0000) ........................................ 287
6.1.4.49. DEFE_CH1_VERTPHASE1_REG(Default Value: 0x0000_0000) ........................................ 288
6.1.4.50. DEFE_CH0_HORZCOEF0_REGN (N=0:31) (Default Value: 0x0000_0000) ....................... 288
6.1.4.51. DEFE_CH0_VERTCOEF_REGN (N=0:31) (Default Value: 0x0000_0000) .......................... 288
6.1.4.52. DEFE_CH1_HORZCOEF0_REGN (N=0:31) (Default Value: 0x0000_0000) ....................... 289
6.1.4.53. DEFE_CH1_VERTCOEF_REGN (N=0:31) (Default Value: 0x0000_0000) .......................... 289
6.2. Display Engine Back End (DEBE).............................................................................................................. 291
6.2.1. Overview ...................................................................................................................................... 291
6.2.2. DEBE Block Diagram ..................................................................................................................... 291
6.2.3. DEBE Register list ......................................................................................................................... 292
6.2.4. DEBE Register Description ........................................................................................................... 293
6.2.4.1. DEBE Mode Control Register (Default Value: 0x0000_0000) ............................................ 293
6.2.4.2. DE-Back Color Control Register ......................................................................................... 295
6.2.4.3. DE-Back Display Size Setting Register ............................................................................... 295
6.2.4.4. DE-Layer Size Register ....................................................................................................... 295
6.2.4.5. DE-Layer Coordinate Control Register .............................................................................. 296
6.2.4.6. DE-Layer Frame Buffer Line Width Register ...................................................................... 296
6.2.4.7. DE-Layer Frame Buffer Low 32 Bit Address Register......................................................... 297
6.2.4.8. DE-Layer Frame Buffer High 4 Bit Address Register .......................................................... 297
6.2.4.9. DE-Register Buffer Control Register (Default Value: 0x0000_0000) ................................. 298
6.2.4.10. DE-Color Key MAX Register ............................................................................................. 298
6.2.4.11. DE-Color Key MIN Register.............................................................................................. 299
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Contents
6.2.4.12. DE-Color Key Configuration Register .............................................................................. 299
6.2.4.13. DE-Layer Attribute Control Register0 .............................................................................. 300
6.2.4.14. DE-Layer Attribute Control Register1 .............................................................................. 302
6.2.4.15. Pixels Sequence Table ..................................................................................................... 304
6.2.4.16. DE-HWC Coordinate Control Register ............................................................................. 308
6.2.4.17. DE-HWC Frame Buffer Format Register .......................................................................... 309
6.2.4.18. DEBE Write Back Control Register................................................................................... 309
6.2.4.19. DEBE Write Back Address Register.................................................................................. 311
6.2.4.20. DEBE Write Back Buffer Line Width Register .................................................................. 311
6.2.4.21. DEBE Input YUV Channel Control Register ...................................................................... 311
6.2.4.22. DEBE YUV Channel Frame Buffer Address Register ........................................................ 313
6.2.4.23. DEBE YUV Channel Buffer Line Width Register ............................................................... 313
6.2.4.24. DEBE Y/G Coefficient Register ......................................................................................... 314
6.2.4.25. DEBE Y/G Constant Register ............................................................................................ 314
6.2.4.26. DEBE U/R Coefficient Register ........................................................................................ 314
6.2.4.27. DEBE U/R Constant Register ........................................................................................... 315
6.2.4.28. DEBE V/B Coefficient Register ......................................................................................... 315
6.2.4.29. DEBE V/B Constant Register ............................................................................................ 315
6.2.4.30. DEBE Output Color Control Register ............................................................................... 316
6.2.4.31. DEBE Output Color R Coefficient Register ...................................................................... 316
6.2.4.32. DEBE Output Color R Constant Register ......................................................................... 317
6.2.4.33. DEBE Output Color G Coefficient Register ...................................................................... 317
6.2.4.34. DEBE Output Color G Constant Register ......................................................................... 317
6.2.4.35. DEBE Output Color B Coefficient Register ...................................................................... 318
6.2.4.36. DEBE Output Color B Constant Register ......................................................................... 318
6.2.4.37. DE-HWC Pattern Memory Block ..................................................................................... 318
6.2.4.38. DE-HWC Palette Table ..................................................................................................... 319
6.2.4.39. Palette Mode .................................................................................................................. 320
6.2.4.40. Internal Frame Buffer Mode ........................................................................................... 321
6.2.4.41. Internal Frame Buffer Mode Palette Table...................................................................... 322
6.2.4.42. Gamma Correction Mode ............................................................................................... 323
6.3. TCON ....................................................................................................................................................... 325
6.3.1. Block Diagram .............................................................................................................................. 325
6.3.2. TCON Register List ........................................................................................................................ 325
6.3.3. TCON Register Description ........................................................................................................... 327
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Contents
6.3.3.1. TCON Global Control Register(Default Value: 0x0000_0000) ........................................... 327
6.3.3.2. TCON Global Interrupt Register0(Default Value: 0x0000_0000) ...................................... 327
6.3.3.3. TCON Global Interrupt Register1(Default Value: 0x0000_0000) ...................................... 328
6.3.3.4. TCON FRM Control Register(Default Value: 0x0000_0000) .............................................. 329
6.3.3.5. TCON FRM Pixel Seed Register(Default Value: 0x0000_0000) .......................................... 329
6.3.3.6. TCON FRM Line Seed Register(Default Value: 0x0000_0000) ........................................... 330
6.3.3.7. TCON FRM Table Register(Default Value: 0x0000_0000) .................................................. 330
6.3.3.8. TCON0 Control Register(Default Value: 0x0000_0000) .................................................... 330
6.3.3.9. TCON0 Data Clock Register(Default Value: 0x0000_0000) ............................................... 332
6.3.3.10. TCON0 Basic Timing Register0(Default Value: 0x0000_0000) ........................................ 332
6.3.3.11. TCON0 Basic Timing Register1(Default Value: 0x0000_0000) ........................................ 332
6.3.3.12. TCON0 Basic Timing Register2(Default Value: 0x0000_0000) ........................................ 333
6.3.3.13. TCON0 Basic Timing Register3(Default Value: 0x0000_0000) ........................................ 333
6.3.3.14. TCON0 HV Panel Interface Register(Default Value: 0x0000_0000)................................. 333
6.3.3.15. TCON0 CPU Panel Interface Register(Default Value: 0x0000_0000)............................... 335
6.3.3.16. TCON0 CPU Panel Write Data Register(Default Value: 0x0000_0000)............................ 336
6.3.3.17. TCON0 CPU Panel Read Data Register0(Default Value: 0x0000_0000)........................... 336
6.3.3.18. TCON0 CPU Panel Read Data Register1(Default Value: 0x0000_0000)........................... 336
6.3.3.19. TCON0 IO Polarity Register(Default Value: 0x0000_0000).............................................. 336
6.3.3.20. TCON0 IO Control Register(Default Value: 0x0FFF_FFFF) ............................................... 337
6.3.3.21. TCON1 Control Register(Default Value: 0x0000_0000) .................................................. 338
6.3.3.22. TCON1 Basic Timing Register0(Default Value: 0x0000_0000) ........................................ 339
6.3.3.23. TCON1 Basic Timing Register1(Default Value: 0x0000_0000) ........................................ 339
6.3.3.24. TCON1 Basic Timing Register2(Default Value: 0x0000_0000) ........................................ 339
6.3.3.25. TCON1 Basic Timing Register3(Default Value: 0x0000_0000) ........................................ 339
6.3.3.26. TCON1 Basic Timing Register4(Default Value: 0x0000_0000) ........................................ 340
6.3.3.27. TCON1 Basic Timing Register5(Default Value: 0x0000_0000) ........................................ 340
6.3.3.28. TCON1 IO Polarity Register(Default Value: 0x0000_0000).............................................. 341
6.3.3.29. TCON1 IO Control Register(Default Value: 0x0FFF_FFFF) ............................................... 341
6.3.3.30. TCON CEU Control Register(Default Value: 0x0000_0000) ............................................. 342
6.3.3.31. TCON CEU Multiplier Coefficient Register(Default Value: 0x0000_0000) ....................... 342
6.3.3.32. TCON CEU Add Coefficient Register(Default Value: 0x0000_0000) ................................ 343
6.3.3.33. TCON CEU Range Coefficient Register(Default Value: 0x0000_0000)............................. 343
6.3.3.34. TCON1 Fill Data Control Register(Default Value: 0x0000_0000)..................................... 343
6.3.3.35. TCON1 Fill Data Begin Register(Default Value: 0x0000_0000)........................................ 343
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Contents
6.3.3.36. TCON1 Fill Data End Register(Default Value: 0x0000_0000) .......................................... 344
6.3.3.37. TCON1 Fill Data Value Register(Default Value: 0x0000_0000)........................................ 344
6.4. IEP ........................................................................................................................................................... 345
6.4.1. Overview ...................................................................................................................................... 345
6.4.2. IEP Register List ............................................................................................................................ 345
6.4.3. IEP Register Description ............................................................................................................... 346
6.4.3.1. General Control Register(Default Value: 0x0000_0000) ................................................... 346
6.4.3.2. DRC Size Setting Register(Default Value: 0x0000_0000)................................................... 346
6.4.3.3. DRC Control Register(Default Value: 0x0000_0000) ......................................................... 347
6.4.3.4. DRC External LGC Start Address Register(Default Value: 0x0000_0000) .......................... 347
6.4.3.5. DRC Setting Register(Default Value: 0x0000_8000).......................................................... 348
6.4.3.6. DRC Window Position Register0(Default Value: 0x0000_0000) ....................................... 348
6.4.3.7. DRC Window Position Register1(Default Value: 0x0000_0000) ....................................... 349
6.4.3.8. DRC Write Back Control Register(Default Value: 0x0000_0000) ....................................... 349
6.4.3.9. DRC Write Back Address Register(Default Value: 0x0000_0000) ...................................... 350
6.4.3.10. DRC Write Back Buffer Line Width Register(Default Value: 0x0000_0000) .................... 350
6.4.3.11. Luminance Histogram Control Register(Default Value: 0x0000_0000)........................... 351
6.4.3.12. Luminance Histogram Threshold Setting Register 0(Default Value: 0x8060_4020) ....... 351
6.4.3.13. Luminance Histogram Threshold Setting Register 1(Default Value: 0x00E0_C0A0) ....... 351
6.4.3.14. Luminance Histogram Statistics Lum Recording Register(Default Value: 0x0000_0000) 352
6.4.3.15. Luminance Histogram Statistics Counter Recording Register(Default Value: 0x0000_0000)
....................................................................................................................................................... 352
6.4.3.16. CSC Y/G Coefficient Register ........................................................................................... 353
6.4.3.17. CSC Y/G Constant Register(Default Value: 0x0000_0877) .............................................. 353
6.4.3.18. CSC U/R Coefficient Register ........................................................................................... 353
6.4.3.19. CSC U/R Constant Register(Default Value: 0x0000_3211) .............................................. 353
6.4.3.20. CSC V/B Coefficient Register ........................................................................................... 354
6.4.3.21. CSC V/B Constant Register(Default Value: 0x0000_2EB1) .............................................. 354
6.4.3.22. DRC Spatial Coefficient Register(Default Value: 0x0000_0000) ...................................... 354
6.4.3.23. DRC Intensity Coefficient Register(Default Value: 0x0000_0000)................................... 355
6.4.3.24. DRC Luminance Gain Coefficient Register(Default Value: 0x0000_0000) ....................... 355
Chapter 7. Audio .................................................................................................................................................... 356
7.1. Audio Codec ............................................................................................................................................ 357
7.1.1. Overview ...................................................................................................................................... 357
7.1.2. Audio Codec Block Diagram ......................................................................................................... 357
7.1.3. Audio Codec Register List............................................................................................................. 358
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Contents
7.1.4. Audio Codec Register Description................................................................................................ 358
7.1.4.1. DAC Digital Part Control Register(Default Value: 0x0000_0000) ...................................... 358
7.1.4.2. DAC FIFO Control Register(Default Value: 0x0000_0000) ................................................. 359
7.1.4.3. DAC FIFO Status Register(Default Value: 0x0080_8008) ................................................... 361
7.1.4.4. DAC TX DATA Register(Default Value: 0x0000_0000)........................................................ 362
7.1.4.5. DAC Analog Control Register(Default Value: 0x05B0_0000) ............................................. 363
7.1.4.6. ADC FIFO Control Register(Default Value: 0x0000_0F00) ................................................. 366
7.1.4.7. ADC FIFO Status Register(Default Value: 0x0000_0000)................................................... 368
7.1.4.8. ADC RX DATA Register(Default Value: 0x0000_0000) ....................................................... 369
7.1.4.9. ADC Analog Control Register(Default Value: 0x0534_814C)............................................. 369
7.1.4.10. DAC TX Counter Register(Default Value: 0x0000_0000) ................................................. 372
7.1.4.11. ADC RX Counter Register(Default Value: 0x0000_0000)................................................. 372
7.2. I2S/PCM .................................................................................................................................................. 374
7.2.1. Overview ...................................................................................................................................... 374
7.2.2. I2S/PCM Block Diagram ............................................................................................................... 374
7.2.3. I2S/PCM Timing Diagram ............................................................................................................. 375
7.2.4. I2S/PCM Register List ................................................................................................................... 376
7.2.5. I2S/PCM Register Description ...................................................................................................... 377
7.2.5.1. I2S/PCM Control Register(Default Value: 0x0000_0000) .................................................. 377
7.2.5.2. I2S/PCM Format Register0(Default Value: 0x0000_000C) ................................................ 378
7.2.5.3. I2S/PCM Format Register1(Default Value: 0x0000_4020) ................................................ 379
7.2.5.4. I2S/PCM TX FIFO Register(Default Value: 0x0000_0000) ................................................. 381
7.2.5.5. I2S/PCM RX FIFO Register(Default Value: 0x0000_0000) ................................................. 381
7.2.5.6. I2S/PCM FIFO Control Register(Default Value: 0x0004_00F0) .......................................... 382
7.2.5.7. I2S/PCM FIFO Status Register(Default Value: 0x1080_0000)............................................ 383
7.2.5.8. I2S/PCM DMA&Interrupt Control Register(Default Value: 0x0000_0000) ....................... 384
7.2.5.9. I2S/PCM Interrupt Status Register(Default Value: 0x0000_0010) .................................... 385
7.2.5.10. I2S/PCM Clock Divide Register(Default Value: 0x0000_0000) ........................................ 386
7.2.5.11. I2S/PCM TX Counter Register(Default Value: 0x0000_0000) .......................................... 387
7.2.5.12. I2S/PCM RX Counter Register(Default Value: 0x0000_0000) ......................................... 387
7.2.5.13. I2S/PCM TX Channel Select Register(Default Value: 0x0000_0001) ............................... 388
7.2.5.14. I2S/PCM TX Channel Mapping Register(Default Value: 0x7654_3210) .......................... 388
7.2.5.15. I2S/PCM RX Channel Select Register(Default Value: 0x0000_0001) ............................... 389
7.2.5.16. I2S/PCM RX Channel Mapping Register(Default Value: 0x0000_3210) .......................... 389
7.3. OWA ........................................................................................................................................................ 390
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Contents
7.3.1. Overview ...................................................................................................................................... 390
7.3.2. OWA Block Diagram ..................................................................................................................... 390
7.3.3. OWA Frame Format ..................................................................................................................... 391
7.3.4. OWA Register List ......................................................................................................................... 392
7.3.5. OWA Register Description ............................................................................................................ 392
7.3.5.1. OWA General Control Register(Default Value: 0x0000_0080) .......................................... 392
7.3.5.2. OWA TX Configure Register(Default Value: 0x0000_00F0) ............................................... 393
7.3.5.3. OWA TX FIFO Register(Default Value: 0x0000_0000) ....................................................... 394
7.3.5.4. OWA FIFO Control Register(Default Value: 0x0000_1078) ............................................... 394
7.3.5.5. OWA FIFO Status Register(Default Value: 0x0000_6000) ................................................. 395
7.3.5.6. OWA Interrupt Control Register(Default Value: 0x0000_0000) ........................................ 396
7.3.5.7. OWA Interrupt Status Register(Default Value: 0x0000_0010) .......................................... 396
7.3.5.8. OWA TX Counter Register(Default Value: 0x0000_0000) ................................................. 397
7.3.5.9. OWA TX Channel Status Register0(Default Value: 0x0000_0000) .................................... 397
7.3.5.10. OWA TX Channel Status Register1(Default Value: 0x0000_0000) .................................. 399
Chapter 8. Interfaces ............................................................................................................................................. 402
8.1. TWI .......................................................................................................................................................... 403
8.1.1. Overview ...................................................................................................................................... 403
8.1.2. TWI Timing Diagram .................................................................................................................... 403
8.1.3. TWI Controller Special Requirement ........................................................................................... 404
8.1.3.1. TWI Pin List ....................................................................................................................... 404
8.1.3.2. TWI Controller Operation ................................................................................................. 404
8.1.4. TWI Controller Register List ......................................................................................................... 404
8.1.5. TWI Controller Register Description ............................................................................................ 405
8.1.5.1. TWI Slave Address Register(Default Value: 0x0000_0000) ............................................... 405
8.1.5.2. TWI Extend Address Register(Default Value: 0x0000_0000) ............................................ 406
8.1.5.3. TWI Data Register(Default Value: 0x0000_0000).............................................................. 406
8.1.5.4. TWI Control Register(Default Value: 0x0000_0000) ......................................................... 406
8.1.5.5. TWI Status Register(Default Value: 0x0000_00F8) ........................................................... 408
8.1.5.6. TWI Clock Register(Default Value: 0x0000_0000) ............................................................ 409
8.1.5.7. TWI Soft Reset Register(Default Value: 0x0000_0000) ..................................................... 410
8.1.5.8. TWI Enhance Feature Register(Default Value: 0x0000_0000) .......................................... 410
8.1.5.9. TWI Line Control Register(Default Value: 0x0000_003A) ................................................. 410
8.1.5.10. TWI DVFS Control Register(Default Value: 0x0000_0000) .............................................. 411
8.2. SPI ........................................................................................................................................................... 413
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Contents
8.2.1. Overview ...................................................................................................................................... 413
8.2.2. SPI Timing Diagram ...................................................................................................................... 413
8.2.3. Functional Descriptions ............................................................................................................... 414
8.2.3.1. SPI Pin List ......................................................................................................................... 414
8.2.3.2. SPI Module Clock Source and Frequency .......................................................................... 415
8.2.4. SPI Register List ............................................................................................................................ 415
8.2.5. SPI Register Description ............................................................................................................... 415
8.2.5.1. SPI RX Data Register(Default Value: 0x0000_0000) .......................................................... 415
8.2.5.2. SPI TX Data Register(Default Value: 0x0000_0000) .......................................................... 415
8.2.5.3. SPI Control Register(Default Value: 0x0002_001C) ........................................................... 416
8.2.5.4. SPI Interrupt Control Register(Default Value: 0x0000_0000) ........................................... 419
8.2.5.5. SPI Interrupt Status Register(Default Value: 0x0000_1B00) ............................................. 421
8.2.5.6. SPI DMA Control Register(Default Value: 0x0000_0000) .................................................. 424
8.2.5.7. SPI Wait Clock Register(Default Value: 0x0000_0000)...................................................... 425
8.2.5.8. SPI Clock Control Register(Default Value: 0x0000_0002) ................................................. 426
8.2.5.9. SPI Burst Counter Register(Default Value: 0x0000_0000) ................................................ 426
8.2.5.10. SPI Transmit Counter Register(Default Value: 0x0000_0000) ......................................... 427
8.2.5.11. SPI FIFO Status Register(Default Value: 0x0000_0000)................................................... 427
8.3. UART ....................................................................................................................................................... 429
8.3.1. Overview ...................................................................................................................................... 429
8.3.2. UART Timing Diagram .................................................................................................................. 429
8.3.3. UART Special Requirement .......................................................................................................... 430
8.3.4. UART Register List ........................................................................................................................ 430
8.3.5. UART Register Description ........................................................................................................... 431
8.3.5.1. UART Receiver Buffer Register(Default Value: 0x0000_0000) .......................................... 431
8.3.5.2. UART Transmit Holding Register(Default Value: 0x0000_0000) ....................................... 431
8.3.5.3. UART Divisor Latch Low Register(Default Value: 0x0000_0000) ....................................... 431
8.3.5.4. UART Divisor Latch High Register(Default Value: 0x0000_0000) ...................................... 432
8.3.5.5. UART Interrupt Enable Register(Default Value: 0x0000_0000) ........................................ 432
8.3.5.6. UART Interrupt Identity Register(Default Value: 0x0000_0000) ....................................... 434
8.3.5.7. UART FIFO Control Register(Default Value: 0x0000_0000) ............................................... 435
8.3.5.8. UART Line Control Register(Default Value: 0x0000_0000) ............................................... 436
8.3.5.9. UART Modem Control Register(Default Value: 0x0000_0000) ......................................... 438
8.3.5.10. UART Line Status Register(Default Value: 0x0000_0060) ............................................... 440
8.3.5.11. UART Modem Status Register(Default Value: 0x0000_0000) ......................................... 442
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Contents
8.3.5.12. UART Scratch Register(Default Value: 0x0000_0000) ..................................................... 444
8.3.5.13. UART Status Register(Default Value: 0x0000_0006) ....................................................... 445
8.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x0000_0000) ................................. 446
8.3.5.15. UART Receive FIFO Level Register(Default Value: 0x0000_0000) ................................... 446
8.3.5.16. UART Halt TX Register(Default Value: 0x0000_0000) ..................................................... 446
8.4. CIR ........................................................................................................................................................... 448
8.4.1. Overview ...................................................................................................................................... 448
8.4.2. CIR Register List ............................................................................................................................ 448
8.4.3. CIR Regsiter Description............................................................................................................... 448
8.4.3.1. CIR Control Register(Default Value: 0x0000_0000) .......................................................... 448
8.4.3.2. CIR Receiver Configure Register(Default Value: 0x0000_0004) ........................................ 449
8.4.3.3. CIR Receiver FIFO Register(Default Value: 0x0000_0000) ................................................ 450
8.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x0000_0000) ............................ 450
8.4.3.5. CIR Receiver Status Register(Default Value: 0x0000_0000) .............................................. 451
8.4.3.6. CIR Configure Register(Default Value: 0x0000_1828) ....................................................... 452
8.5. USB OTG .................................................................................................................................................. 454
8.5.1. Overview ...................................................................................................................................... 454
8.5.2. USB OTG Timing Diagram............................................................................................................. 454
8.6. USB Host ................................................................................................................................................. 455
8.6.1. Overview ...................................................................................................................................... 455
8.6.2. USB Host Block Diagram .............................................................................................................. 455
8.6.3. USB Host Timing Diagram ............................................................................................................ 456
8.6.4. USB Host Special Requirement .................................................................................................... 456
8.6.5. USB Host Register List .................................................................................................................. 456
8.6.6. EHCI Register Description ............................................................................................................ 457
8.6.6.1. EHCI Identification Register(Default Value: Implementation Dependent)........................ 457
8.6.6.2. EHCI Host Interface Version Number Register(Default Value:0x0000_0100) ................... 457
8.6.6.3. EHCI Host Control Structural Parameter Register(Default Value: Implementation
Dependent) .................................................................................................................................... 457
8.6.6.4. EHCI Host Control Capability Parameter Register(Default Value: Implementation
Dependent) .................................................................................................................................... 458
8.6.6.5. EHCI Companion Port Route Description .......................................................................... 459
8.6.6.6. EHCI USB Command Register(Default Value: 0x0008_0000) ............................................ 460
8.6.6.7. EHCI USB Status Register(Default Value: 0x0000_1000) ................................................... 463
8.6.6.8. EHCI USB Interrupt Enable Register(Default Value: 0x0000_0000) .................................. 465
8.6.6.9. EHCI Frame Index Register(Default Value: 0x0000_0000) ................................................ 466
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Contents
8.6.6.10. EHCI Periodic Frame List Base Address Register ............................................................. 466
8.6.6.11. EHCI Current Asynchronous List Address Register .......................................................... 467
8.6.6.12. EHCI Configure Flag Register(Default Value: 0x0000_0000) ........................................... 467
8.6.6.13. EHCI Port Status and Control Register(Default Value: 0x00002000(w/PPC set to one)) 467
8.6.7. OHCI Register Description ............................................................................................................ 472
8.6.7.1. HcRevision Register(Default Value: 0x0000_0010) ........................................................... 472
8.6.7.2. HcControl Register(Default Value: 0x0000_0000) ............................................................ 472
8.6.7.3. HcCommandStatus Register(Default Value: 0x0000_0000) .............................................. 474
8.6.7.4. HcInterruptStatus Register(Default Value: 0x0000_0000) ................................................ 475
8.6.7.5. HcInterruptEnable Register(Default Value: 0x0000_0000) ............................................... 476
8.6.7.6. HcInterruptDisable Register(Default Value: 0x0000_0000) .............................................. 477
8.6.7.7. HcHCCA Register(Default Value: 0x0000_0000) ............................................................... 478
8.6.7.8. HcPeriodCurrentED Register(Default Value: 0x0000_0000) ............................................. 478
8.6.7.9. HcControlHeadED Register(Default Value: 0x0000_0000)................................................ 479
8.6.7.10. HcControlCurrentED Register(Default Value: 0x0000_0000) .......................................... 479
8.6.7.11. HcBulkHeadED Register(Default Value: 0x0000_0000) .................................................. 480
8.6.7.12. HcBulkCurrentED Register(Default Value: 0x0000_0000) ............................................... 480
8.6.7.13. HcDoneHead Register(Default Value: 0x0000_0000) ..................................................... 480
8.6.7.14. HcFmInterval Register(Default Value: 0x0000_2EDF) ..................................................... 481
8.6.7.15. HcFmRemaining Register(Default Value: 0x0000_0000) ................................................ 481
8.6.7.16. HcFmNumber Register(Default Value: 0x0000_0000) .................................................... 482
8.6.7.17. HcPeriodicStart Register(Default Value: 0x0000_0000).................................................. 482
8.6.7.18. HcLSThreshold Register(Default Value: 0x0000_0628) ................................................... 482
8.6.7.19. HcRhDescriptorA Register(Default Value: 0x0200_1201) ............................................... 483
8.6.7.20. HcRhDescriptorB Register(Default Value: 0x0000_0000) ............................................... 484
8.6.7.21. HcRhStatus Register(Default Value: 0x0000_0000) ........................................................ 485
8.6.7.22. HcRhPortStatus Register(Default Value: 0x0000_0100) ................................................. 486

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Figures
Figure 2-1. GR8 Block Diagram ................................................................................................................................ 15
Figure 2-2. GR8 Typical Application Diagram .......................................................................................................... 16
Figure 3-1. Boot Diagram ......................................................................................................................................... 21
Figure 3-2. Clock Generation from PLL Outputs ...................................................................................................... 45
Figure 3-3. Bus Clock Generation Part 1 .................................................................................................................. 46
Figure 3-4. Bus Clock Generation Part 2 .................................................................................................................. 47
Figure 3-5. LRADC Block Diagram .......................................................................................................................... 175
Figure 3-6. LRADC Control Logic Diagram .............................................................................................................. 176
Figure 3-7. TP Typical Application Circuit .............................................................................................................. 184
Figure 3-8. TP Clock Tree ....................................................................................................................................... 185
Figure 3-9. Single Touch and Pressure Measurement ........................................................................................... 185
Figure 3-10. Single Touch No Pressure Measurement Mode ................................................................................ 186
Figure 3-11. General ADC Mode ............................................................................................................................ 186
Figure 3-12. Simplified Diagram of Single-Ended Reference ................................................................................. 187
Figure 3-13. Simplified Diagram of Differential Reference.................................................................................... 187
Figure 3-14. Single Touch X-Position Measurement.............................................................................................. 188
Figure 3-15. Pressure Measurement Block Diagram ............................................................................................. 189
Figure 3-16. Example of Pen Touch Interrupt via Pen Down IRQ .......................................................................... 189
Figure 3-17. Median and Averaging Filter Example ............................................................................................... 190
Figure 3-18. Crypto Engine Block Diagram ............................................................................................................ 200
Figure 4-1. NFC Block Diagram .............................................................................................................................. 245
Figure 4-2. Conventional Serial Access Cycle Diagram (SAM0) ............................................................................. 246
Figure 4-3. EDO Type Serial Access after Read Cycle (SAM1) ................................................................................ 246
Figure 4-4. Extending EDO Type Serial Access Mode (SAM2) ............................................................................... 247
Figure 4-5. Command Latch Cycle ......................................................................................................................... 247
Figure 4-6. Address Latch Cycle ............................................................................................................................. 248
Figure 4-7. Write Data to Flash Cycle .................................................................................................................... 248
Figure 4-8. Waiting R/B# Ready Diagram .............................................................................................................. 249
Figure 4-9. WE # High to RE# Low Timing Diagram ............................................................................................... 249
Figure 4-10. RE # High to WE# Low Timing Diagram ............................................................................................. 249
Figure 4-11. Address to Data Loading Timing Diagram ......................................................................................... 249
Figure 4-12. Page Read Command Diagram .......................................................................................................... 250
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Figure 4-13. Page Program Diagram ...................................................................................................................... 251
Figure 4-14. EF-NAND Page Read Diagram ............................................................................................................ 251
Figure 4-15. Interleave Page Read Diagram .......................................................................................................... 251
Figure 5-1. CSI Block Diagram ................................................................................................................................ 254
Figure 5-2. Vref= Positive; Href= Positive .............................................................................................................. 255
Figure 5-3. Vertical Size Setting ............................................................................................................................. 255
Figure 5-4. Horizontal Size Setting and Pixel Clock Timing (Href= positive) .......................................................... 255
Figure 6-1. DEFE Block Diagram ............................................................................................................................. 265
Figure 6-2. Display Engine Block Diagram ............................................................................................................. 292
Figure 6-3. LCD/TV Timing Controller Block Diagram ............................................................................................ 325
Figure 7-1. Audio Codec Block Diagram................................................................................................................. 358
Figure 7-2. I2S/PCM Block Diagram ....................................................................................................................... 375
Figure 7-3. I2S Timing Diagram .............................................................................................................................. 375
Figure 7-4. I2S Left-justified Timing Diagram ........................................................................................................ 375
Figure 7-5. I2S Right-justified Timing Diagram ...................................................................................................... 375
Figure 7-6. PCM Long Frame SYNC Timing Diagram .............................................................................................. 376

Figure 7-7. PCM Short Frame SYNC Timing Diagram ............................................................................................. 376
Figure 7-8. OWA Block Diagram ............................................................................................................................ 391
Figure 7-9. Sub-Frame Format ............................................................................................................................... 391
Figure 7-10. Frame/Block Format .......................................................................................................................... 391
Figure 7-11. Biphase-Mark Encoding ..................................................................................................................... 392
Figure 8-1. TWI Timing Diagram ............................................................................................................................ 404
Figure 8-2. SPI Phase 0 Timing Diagram ................................................................................................................ 414
Figure 8-3. SPI Phase 1 Timing Diagram ................................................................................................................ 414
Figure 8-4. UART Serial Data Format ..................................................................................................................... 429
Figure 8-5. Serial IrDA Data Format ....................................................................................................................... 430
Figure 8-6. USB Host Block Diagram ...................................................................................................................... 455

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Tables
Table 3-1. Median Filter Size ................................................................................................................................. 190

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Chapter 1. About This Documentation
1.1. Purpose
This documentation provides an overall description of Allwinner’s GR8 application processor. It describes the
overview, features, logical structures, functions and register listings of each module. This documentation is
intended to provide guidance to programmers writing code for the GR8 processor. This documentation assumes
that the reader has a background in computer engineering and/or software engineering, with the goal to aid
anyone in understanding and potentially modifying the provided code.

1.2. Acronyms and Abbreviations
NO.

Abbreviation

Full Name

Description

1

ARM Cortex™-A8

ARM Cortex™-A8

2

Audio Codec

Audio Codec

3

CSI

CMOS Sensor Interface

4

DMA

Direct Memory Access

5

EHCI

Enhanced
Interface

6

I2S

Inter IC Sound

7

LRADC

Low Resolution Analog to Digital
Converter

GR8 User Manual(Version1.0)

Host

Controller

A processor core designed by ARM Holdings
implementing the ARM v7 instruction set
architecture.
A computer program implementing an
algorithm
that
compresses
and
decompresses digital audio data according to
a given audio file format or streaming media
audio format.
The hardware block that interfaces with
different image sensor interfaces and
provides a standard output that can be used
for subsequent image processing.
A feature of modern computers that allow
certain hardware subsystems within the
computer to access system memory
independently of the CPU.
A high-speed controller standard that is
publicly specified
An electrical serial bus interface standard
used for connecting digital audio devices
together.
A module which can transfer analog signal to
digital signal.

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Page 5

About This Documentation
8

Mali-400

Mali-400

9

OHCI

Open Host Controller Interface

10

PCM

Pulse Code Modulation

11

PWM

Pulse Width Modulator

12

SDRAM

Synchronous Dynamic Random
Access Memory

13

SPI

Serial Peripheral Interface

14

SD 3.0

Security Digital 3.0

15

TP

Touch Panel

16

UART

Universal Asynchronous Receiver
/ Transmitter

17

USB OTG

USB On-The-Go

GR8 User Manual(Version1.0)

A 2D/3D graphic processor unit designed by
ARM Holdings.
A register-level interface that enables a host
controller for USB or FireWire hardware to
communicate with a host controller driver in
software.
Method used to digitally represent sampled
analog signals.
A commonly used technique for controlling
power to inertial electrical devices, made
practical by modern electronic power
switches.
Dynamic random access memory (DRAM)
that is synchronized with the system bus.
A synchronous serial data link standard
named by Motorola that operates in full
duplex mode. Devices communicate in
master/slave mode where the master device
initiates the data frame.
A non-volatile memory card format
developed by the SD Card Association for use
in portable devices.
A human-machine interactive interface.
Used for serial communication with a
peripheral, modem (data carrier equipment,
DCE) or data set.
A dual-role controller which supports both
host and device functions and is fully
compliant with the On-The-Go Supplement
to the USB 2.0 Specification, Revision 1.0a.

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Page 6

Chapter 2. Overview
This part gives an overview of the GR8 processor and its applications.
 Processor Overview
 Processor Features
 Block Diagram

GR8 User Manual(Version1.0)

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Page 7

Overview

2.1. Processor Overview
The GR8 is designed to provide low-power capabilities and high performance. All within an FBGA252 package
which integrates an ARM CortexTM-A8 implementing the ARM V7-A architecture with supporting numerous
popular peripherals.
The processor has a fully hardware implemented video engine which supports H.264 MP encoding up to
720p@30fps and multi-format decoding up to 1080p@30fps. It also includes a graphic engine that provides 3-D
graphics acceleration, as well as an audio codec that supports 44.1kHz, 48 kHz, 96 kHz, and 192 kHz sample rates.
Has on-chip 24-bit DAC for playback and ADC for recording, stereo microphone input and supports analog/digital
volume control.
GR8 comes with internal DDR3 memory and is packed with connectivity options including UART, SPI, USB, CIR, a
CMOS sensor interface and an LCD controller. All of these features make GR8 an ideal platform to develop a
portfolio of smart devices with.
Applications:
●

IoT Intelligent Computing

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Overview

2.2. Processor Features
2.2.1. CPU
●

1GHz

●

ARM CortexTM-A8 Core

●

ARMv7 Instruction set plus Thumb-2 Instruction Set

●

32 KB Instruction Cache and 32 KB Data Cache

●

256 KB L2 Cache

●

NEONTM SIMD Coprocessor

●

Jazelle RCT Acceleration

2.2.2. GPU
●

Mali400

●

Supports OpenGL ES 1.1/ 2.0 and OpenVG 1.1

2.2.3. Memory
2.2.3.1. Boot ROM
●

On-chip boot ROM

●

Supports boot from NAND Flash, SPI NOR Flash, SD Card and USB OTG

2.2.3.2. SDRAM
●

Embedded 16-bit DDR3 memory

2.2.3.3. NAND Flash
●

Compliant with ONFI 2.3 and Toggle 1.0

●

Up to 8-bit data bus width

●

Supports 2 chip selects, and 2 ready/busy signals

●

Up to 64-bit ECC per 512 bytes or 1024 bytes

●

Supports 1K/2K/4K/8K/16KB page size

●

Supports SLC/MLC NAND and EF-NAND

●

Supports SDR/Toggle DDR/ONFI DDR NAND interface

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Overview
2.2.3.4. SD/MMC
●

3 SD/MMC Host Controllers(SMHC)

●

Compatible with eMMC standard specification V4.4, SD physical layer specification V2.0, SDIO card
specification V2.0

●

1-/4-/8-bit bus width

●

Supports block size of 1 to 65535 bytes

●

Embedded special DMA to do data transfer

2.2.4. System Peripherals
2.2.4.1. CCM
●

7 PLLs, a main external oscillator and an on-chip RC oscillator

●

Supports clock configuration and clock generation for corresponding modules

●

Supports software-controlled clock gating and software-controlled reset for corresponding modules

2.2.4.2. DMA
●

8 channels normal DMA and 8 channels dedicated DMA

●

Supports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory

●

Transfer data width of 8/16/32-bit

●

Programs the DMA burst size

2.2.4.3. PWM
●

Supports outputting two kinds of waveforms: continuous waveform and pulse waveform

●

0% to 100% adjustable duty cycle

●

Up to 24 MHz output frequency

2.2.4.4. Asynchronous Timer
●

6 Asynchronous Timers with interrupt-based operation

●

1 Watchdog to generate reset signal or interrupt

●

Two 33-bit Audio/Video Sync(AVS) Counter to synchronize video and audio in the player

●

One 64-bit Counter

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Overview
2.2.4.5. Synchronic Timer
●

2 Synchronic timers with interrupt-based operation

2.2.4.6. Interrupt Controller
●

Controls the nIRQ and FIQ of a RISC processor

●

Supports 96 interrupt sources

●

4-Level priority controller

●

External sources of edge-sensitive or level-sensitive

2.2.4.7. LRADC
●

Analog to digital converter with 6-bit resolution for key application

●

Supports general key, hold key and already hold key

●

Supports single, normal and continuous work mode

●

Maximum sampling frequency up to 250 Hz

2.2.4.8. Touch Panel
●

12-bit SAR type A/D converter

●

4-wire I/F

●

Touch-pressure measurement

●

Maximum sampling frequency: 2 MHz

●

Single-ended conversion of touch screen inputs and ratiometric conversion of touch screen inputs

●

TACQ up to 262 ms

●

Median and averaging filter to reduce noise

●

Pen down detection, with programmable sensitivity

●

Support X, Y change

2.2.4.9. Crypto Engine
●

Supports AES, DES, 3DES, SHA-1, MD5

●

Supports ECB, CBC modes for AES/DES/3DES

●

128 bits, 192 bits and 256 bits key size for AES

●

160 bits hardware PRNG with 175 bits seed

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 11

Overview

2.2.5. Video Engine
●

Video Decoding
➢

Supports multi-format video decoding, including VP6/8, AVS, H.264, H.263, MPEG-1/2/4, etc.

➢

Up to 1080p@30fps resolution in all formats

●

Video Encoding
➢

Supports encoding in H.264 MP format

➢

Up to 720p@30fps resolution

2.2.6. Display Processing
●

Four moveable and size-adjustable layers

●

Supports multi-format image input

●

Supports image enhancement processor

●

Supports alpha blending /anti-flicker

●

Supports hardware cursor

●

Supports output color correction (luminance/hue/saturation)

2.2.7. Display Output
●

LCD interface (CPU/Sync RGB)

●

Supports CVBS output

2.2.8. Image Input
●

Supports 8-bit CMOS sensor parallel interface

●

Supports BT656 interface

●

Maximum still capture resolution for parallel interface up to 5M

●

Maximum video capture resolution for parallel interface up to 1080p@30fps

●

Maximum pixel clock up to 150MHz

2.2.9. Audio Subsystem
2.2.9.1. Audio Codec
●

On-chip 24-bit DAC for play-back

GR8 User Manual(Version1.0)

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Page 12

Overview
●

On-chip 24-bit ADC for recorder

●

Supports analog/digital volume control

●

Supports 48 kHz and 44.1 kHz sample family

●

Supports 192 kHz and 96 kHz sample

●

Supports microphone recorder

●

Stereo headphone amplifier that can be operated in capless headphone mode

2.2.9.2. I2S/PCM
●

I2S or PCM configured by software

●

Full-duplex synchronous serial interface

●

Master/slave mode operation configured by software

●

Audio data resolutions of 16, 20, 24

●

I2S Audio data sample rate from 8 kHz to 192 kHz

●

I2S data format for standard I2S, left justified and right justified

●

PCM supports linear sample (8-bit or 16-bit), 8-bit Mu-law and A-law companding sample

●

One 128x24 bits FIFO for data transmit, one 64x24 bits FIFO for data receive

●

Programmable FIFO thresholds

2.2.9.3. OWA
●

IEC-60958 transmitter functionality

●

Supports channel status insertion for the transmitter

●

Hardware parity generation on the transmitter

●

One 32×24 bits FIFO (TX) for audio data transfer

●

Programmable FIFO thresholds

●

S/PDIF compatible

2.2.10. External Peripherals
2.2.10.1. USB
●

One USB 2.0 OTG controller
➢

Complies with USB2.0 Specification

➢

Supports High-Speed (HS,480 Mbit/s), Full-Speed (FS,12 Mbit/s) and Low-Speed (LS,1.5 Mbit/s) in host
mode

➢

Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) in device mode

GR8 User Manual(Version1.0)

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Overview
➢
●

Up to 10 user-configurable endpoints in device mode
One USB Host controller

➢

Complies with Enhanced Host Controller Interface(EHCI)Specification, Version 1.0, and the Open Host
Controller Interface(OHCI) Specification, Version 1.0a

➢

Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s), and Low-Speed (LS, 1.5 Mbit/s) Device

2.2.10.2. TWI
●

Three TWI (Two-Wire Interface) controllers

●

Supports Standard mode (up to 100 kbit/s) and Fast mode (up to 400 kbit/s)

●

Master/slave configurable

●

Allows 10-bit addressing transactions

2.2.10.3. UART
●

Four UART controllers, UART0 with 2 wires, UART1 with 4 wires, UART2 with 4 wires, UART3 with 4 wires

●

Compatible with industry-standard 16550 UARTs

●

Supports word length from 5 to 8 bits, an optional parity bit, and 1, 1.5 or 2 stop bits

●

Programmable parity (even, odd and no parity)

2.2.10.4. SPI
●

Two SPI controllers, each SPI controller with one CS signal

●

Full-duplex synchronous serial interface

●

Master/slave configurable

●

Polarity and phase are configurable

●

SPI clock is configurable

2.2.10.5. CIR
●

One flexible receiver for consumer IR remote control

●

Programmable FIFO thresholds

2.2.11. Package
●

FBGA 252 balls, 14 mm x 14 mm, 0.8 mm pitch

GR8 User Manual(Version1.0)

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Page 14

Overview

2.3. Block Diagram
Figure 2-1 shows the block diagram of GR8 processor.

Figure 2-1. GR8 Block Diagram

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 15

Overview
Figure 2-2 shows the typical application diagram of GR8 processor.

Figure 2-2. GR8 Typical Application Diagram

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 16

Chapter 3. System
This chapter describes the GR8 system broken out in the following sections:
 Memory Mapping
 Boot System
 PMU
 Clock Control Module (CCM)
 System Control
 CPU Control
 PWM
 Asynchronous Timer
 Synchronic Timer
 Interrupt Controller
 DMA
 LRADC
 Touch Panel
 Crypto Engine
 Security ID
 Port Controller

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 17

System

3.1. Memory Mapping
Module
SRAM A1
SRAM A2
SRAM A3
SRAM A4
SRAM NAND
SRAM D
SRAM Controller
DRAM Controller
DMA
NFC
/
SPI 0
/
/
/
CSI
/
EMAC
LCD
/
VE
SD/MMC 0
SD/MMC 1
SD/MMC 2
/
USB OTG
USB HCI
CE
/
SPI 2
/
/
/
/
/
/
/
/
CCM
INTC
PIO
ASYNC Timer
OWA
/
IR
/
/
GR8 User Manual(Version1.0)

Address
0x0000 0000---0x0000 3FFF
0x0000 4000---0x0000 7FFF
0x0000 8000---0x0000 B3FF
0x0000 B400---0x0000 BFFF
/
0x0001 0000---0x0001 0FFF
0x01C0 0000---0x01C0 0FFF
0x01C0 1000---0x01C0 1FFF
0x01C0 2000---0x01C0 2FFF
0x01C0 3000---0x01C0 3FFF
0x01C0 4000---0x01C0 4FFF
0x01C0 5000---0x01C0 5FFF
0x01C0 6000---0x01C0 6FFF
0x01C0 7000---0x01C0 7FFF
0x01C0 8000---0x01C0 8FFF
0x01C0 9000---0x01C0 9FFF
0x01C0 A000---0x01C0 AFFF
0x01C0 B000---0x01C0 BFFF
0x01C0 C000---0x01C0 CFFF
0x01C0 D000---0x01C0 DFFF
0x01C0 E000---0x01C0 EFFF
0x01C0 F000---0x01C0 FFFF
0x01C1 0000---0x01C1 0FFF
0x01C1 1000---0x01C1 1FFF
0x01C1 2000---0x01C1 2FFF
0x01C1 3000---0x01C1 3FFF
0x01C1 4000---0x01C1 4FFF
0x01C1 5000---0x01C1 5FFF
0x01C1 6000---0x01C1 6FFF
0x01C1 7000---0x01C1 7FFF
0x01C1 8000---0x01C1 8FFF
0x01C1 9000---0x01C1 9FFF
0x01C1 A000---0x01C1 AFFF
0x01C1 B000---0x01C1 BFFF
0x01C1 C000---0x01C1 CFFF
0x01C1 D000---0x01C1 DFFF
0x01C1 E000---0x01C1 EFFF
0x01C1 F000---0x01C1 FFFF
0x01C2 0000---0x01C2 03FF
0x01C2 0400---0x01C2 07FF
0x01C2 0800---0x01C2 0BFF
0x01C2 0C00---0x01C2 0FFF
0x01C2 1000---0x01C2 13FF
0x01C2 1400---0x01C2 17FF
0x01C2 1800---0x01C2 1BFF
0x01C2 1C00---0x01C2 1FFF
0x01C2 2000---0x01C2 23FF

Size(Bytes)
16K
16K
13K
3K
2K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
/
/
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
/
4K
4K
4K
4K
4K
4K
4K
4K
4K
1K
1K
1K
1K
1K
1K
1K
1K
1K

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 18

System
I2S/PCM
LRADC
Audio Codec
KEYPAD
CPU Control
SID
/
/
/
/
/
TP
PMU
/
/
/
/
/
/
/
/
/
/
UART 0
UART 1
UART 2
UART 3
/
/
/
/
/
/
/
TWI 0
TWI 1
TWI 2
/
/
/
/
/
/
/
Mali-400
Sync Timer
SRAM C
DE_FE
/
DE_BE

GR8 User Manual(Version1.0)

0x01C2 2400---0x01C2 27FF
0x01C2 2800---0x01C2 2BFF
0x01C2 2C00---0x01C2 2FFF
0x01C2 3000---0x01C2 33FF
0x01C2 3400---0x01C2 37FF
0x01C2 3800---0x01C2 3BFF
0x01C2 3C00---0x01C2 3FFF
0x01C2 4000---0x01C2 43FF
0x01C2 4400---0x01C2 47FF
0x01C2 4800---0x01C2 4BFF
0x01C2 4C00---0x01C2 4FFF
0x01C2 5000---0x01C2 53FF
0x01C2 5400---0x01C2 57FF
0x01C2 5800---0x01C2 5BFF
0x01C2 5C00---0x01C2 5FFF
0x01C2 6000---0x01C2 63FF
0x01C2 6400---0x01C2 67FF
0x01C2 6800---0x01C2 6BFF
0x01C2 6C00---0x01C2 6FFF
0x01C2 7000---0x01C2 73FF
0x01C2 7400---0x01C2 77FF
0x01C2 7800---0x01C2 7BFF
0x01C2 7C00---0x01C2 7FFF
0x01C2 8000---0x01C2 83FF
0x01C2 8400---0x01C2 87FF
0x01C2 8800---0x01C2 8BFF
0x01C2 8C00---0x01C2 8FFF
0x01C2 9000---0x01C2 93FF
0x01C2 9400---0x01C2 97FF
0x01C2 9800---0x01C2 9BFF
0x01C2 9C00---0x01C2 9FFF
0x01C2 A000---0x01C2 A3FF
0x01C2 A300---0x01C2 A7FF
0x01C2 A800---0x01C2 ABFF
0x01C2 AC00---0x01C2 AFFF
0x01C2 B000---0x01C2 B3FF
0x01C2 B400---0x01C2 B7FF
0x01C2 B800---0x01C2 BBFF
0x01C2 BC00---0x01C2 BFFF
0x01C2 C000---0x01C2 C3FF
0x01C2 C400---0x01C2 C7FF
0x01C2 C800---0x01C2 CBFF
0x01C2 CC00---0x01C2 CFFF
0x01C3 0000---0x01C3 FFFF
0x01C4 0000---0x01C4 FFFF
0x01C6 0000—0x01C6 0FFF
0x01D0 0000---0x01DF FFFF
0x01E0 0000---0x01E1 FFFF
0x01E2 0000---0x01E3 FFFF
0x01E6 0000---0x01E6 FFFF

1K
1K
1K
/
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
64K
64K
4K
Module SRAM
128K
128K
64K

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 19

System
IEP
/
/
/
/
DDR-II/DDR-III
BROM

GR8 User Manual(Version1.0)

0x01E7 0000---0x01E7 FFFF
0x01E4 0000---0x01E5 FFFF
0x01E8 0000---0x01E9 FFFF
0x01EA 0000---0x01EB FFFF
0x3F50 0000---0x3F50 FFFF
0x4000 0000---0xBFFF FFFF
0xFFFF 0000—0xFFFF 7FFF

64K
128K
128K
128K
64K
2G
32K

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 20

System

3.2. Boot System
3.2.1. Overview
With one 32KB ROM, the GR8 supports five boot methods. The system can boot sequentially from NAND Flash,
SPI NOR Flash, SD Card and USB. However, if the external boot select pin, which is pulled up by an internal 50K
resistor in normal state, is checked by boot code to be on low-level state after system power-on, the system will
directly jump to boot from USB.

3.2.2. Boot Diagram

Figure 3-1. Boot Diagram

GR8 User Manual(Version1.0)

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Page 21

System

3.3. PMU
3.3.1. Overview
The Power Management Unit (PMU) aims to reduce dynamic power consumption and static leakage current to
extend the life of batteries in end products. This module is the central control module for the CPU clock and power
management signals.

3.3.2. PMU Register List
Module Name
PMU

Base Address
0x01C25400

Register Name

Offset

Description

PMU_DVFS_CTRL_REG0
PMU_DVFS_CTRL_REG1
/
PMU_DVFS_CTRL_REG2
/
/
PMU_DVFS_CTRL_REG3
PMU_DVFS_TIMEOUT_CTRL_REG
PMU_AXI_AUTO_SWT_REG0
PMU_AXI_AUTO_SWT_REG1
PMU_IRQ_EN_REG
PMU_IRQ_STATUS_REG
PMU_STATUS_REG
PMU_CPUVDD_CTRL_REG_ADDR
PMU_TWI_ADDR_REG
PMU_CPUVDD_VALUE_REG
PMU_CPUVDD_RAMP_CTRL_REG
PMU_32K_CPUVDD_MIN_REG
PMU_VF_TABLE_REG0
PMU_VF_TABLE_REG1
PMU_VF_TABLE_REG2
PMU_VF_TABLE_REG3
PMU_VF_TABLE_REG4
PMU_VF_TABLE_REG5
PMU_VF_TABLE_REG6
PMU_VF_TABLE_REG7
PMU_VF_TABLE_REG8
PMU_VF_TABLE_REG9
PMU_VF_TABLE_REG10

0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0080
0x0084
0x0088
0x008C
0x0090
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8

PMU Control Register 0
PMU Control Register 1
/
PMU Control Register 2
/
/
PMU Control Register 3
PMU Timeout Control Register
PMU AXI Auto Switch CLK Register0
PMU AXI Auto Switch CLK Register1
PMU IRQ Enable Register
PMU IRQ Status Register
PMU Status Register
PMU CPUVDD Register Address
PMU TWI Address
PMU CPUVDD Value
PMU CPUVDD Voltage Ramp Control
PMU 32KHz CPUVDD Minimum Value
CPU Speed Max if VDDCPU=0.70V
CPU Speed Max if VDDCPU =0.75V
CPU Speed Max if VDDCPU =0.80V
CPU Speed Max if VDDCPU =0.85V
CPU Speed Max if VDDCPU =0.90V
CPU Speed Max if VDDCPU =0.95V
CPU Speed Max if VDDCPU =1.00 V
CPU Speed Max if VDDCPU =1.05V
CPU Speed Max if VDDCPU =1.10V
CPU Speed Max if VDDCPU =1.15 v
CPU Speed Max if VDDCPU =1.20V

GR8 User Manual(Version1.0)

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Page 22

System
PMU_VF_TABLE_REG11
PMU_VF_TABLE_REG12
PMU_VF_TABLE_REG13
PMU_VF_TABLE_REG14
PMU_VF_TABLE_REG15
PMU_VF_TABLE_REG16
PMU_VF_TABLE_REG17
PMU_VF_TABLE_REG18
PMU_VF_TABLE_VALID_REG
PMU_VF_TABLE_INDEX_REG
PMU_VF_TABLE_RANGE_REG
PMU_SPEED_FACTOR_REG0
PMU_SPEED_FACTOR_REG1
PMU_SPEED_FACTOR_REG2
CPU_IDLE_CNT_LOW_REG
CPU_IDLE_CNT_HIGH_REG
CPU_IDLE_COUNTER_CTRL_REG
CPU_IDLE_STATUS_REG

0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0
0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x00E0
0x00E4
0x00E8
0x00F0
0x00F4
0x00F8
0x00FC

CPU Speed Max if VDDCPU =1.25V
CPU Speed Max if VDDCPU =1.30 V
CPU Speed Max if VDDCPU =1.35V
CPU Speed Max if VDDCPU =1.40V
CPU Speed Max if VDDCPU =1.45V
CPU Speed Max if VDDCPU =1.50V
CPU Speed Max if VDDCPU =1.55V
CPU Speed Max if VDDCPU =1.60V
PMU VF Table Valid Control
PMU VF Table Index
PMU VF Table Range
PMU Speed Factor Register 0
PMU Speed Factor Register 1
PMU Speed Factor Register 2
CPU Idle Counter Low
CPU Idle Counter High
CPU Idle Counter Control
CPU Idle Status Register

3.3.3. PMU Register Description
3.3.3.1. PMU DVFS Control Register 0 (Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write
31:18
/

Default/Hex
/

Register Name: PMU_DVFS_CTRL_REG0
Description
/
DVFS_MODE_SEL
DVFS Mode Select

17:16

R/W

0x0

00: Mode 0
01: Mode 1
10: Mode 2
11: /
AXI_DIV_AUTO_SWITCH
AXICLK Auto Switch Enable

15

R/W

0x0
0: Disable
1: Enable

14:13

/

/

12

R/W

0x0

GR8 User Manual(Version1.0)

/
VOLT_CHANGE_MODE
Voltage Change Mode

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Page 23

System

0: Normal mode
1: Maximum mode
11:9

/

/

/
CLK_CHANGE_SM_MODE
Clock Change Smooth Mode

8

R/W

0x0
0: Divide mode
1: Gating mode
SM_EN
Smooth Enable

7

R/W

0x0
0: Disable
1: Enable
CLK_SWTH_EN
Clock Switch Enable

6

R/W

0x0
0: Disable
1: Enable
VOLT_CHANGE_EN
Voltage Change Enable

5

R/W

0x0
0: Disable
1: Enable
SPD_DET_EN
Speed Detect Enable

4

R/W

0x0
0: Disable
1: Enable

3:1

/

/

/
DVFS_EN
PMU DVFS Enable

0

R/W

0x0
0: Disable
1: Enable

GR8 User Manual(Version1.0)

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Page 24

System

3.3.3.2. PMU DVFS Control Register 1(Default Value: 0x0000_1010)
Offset: 0x0004
Bit
Read/Write

Default/Hex

31:24

/

/

23:8

R/W

0x10

7:0

R/W

0x10

Register Name: PMU_DVFS_CTRL_REG1
Description
/
PLL_STAB_TIME
PLL stable time.
SM_INTV_VALUE
Smooth interval value

3.3.3.3. PMU DVFS Control Register 2 (Default Value: 0x0000_0000)
Offset: 0x000C
Bit
Read/Write

Default/Hex

Register Name: PMU_DVFS_CTRL_REG2
Description

31:1

/

/

/

VOLT_SET_EN.
Voltage Set Enable.
0

R/W

It will be automatically cleared after the voltage setting command is
sent successfully.

0x0

Setting this bit to 1 will start the voltage setting (set the CPUVDD
register value to the external PMU IC through the TWI interface).
Note: This bit cannot be set to one if the Voltage Change Enable bit in the PMU_DVFS_CTRL_REG0 is set to 1.

3.3.3.4. PMU AXI Clock Range Register0 (Default Value: 0x0000_0000)
Offset: 0x0020
Bit
Read/Write

Default/Hex

31:27

/

/

26:16

R/W

0x0

15:11

/

/

10:0

R/W

0x0

Register Name: PMU_AXI_AUTO_SWT_REG0
Description
/
AXI_CLK_LEVEL1
AXICLK Level 1
/
AXI_CLK_LEVEL0
AXICLK Level 0

3.3.3.5. PMU AXI Clock Range Register1 (Default Value: 0x0000_0000)
Offset: 0x0024

GR8 User Manual(Version1.0)

Register Name: PMU_AXI_AUTO_SWT_REG1

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 25

System
Bit

Read/Write

Default/Hex

Description

31:27

/

/

/

26:16

R/W

0x0

15:11

/

/

10:0

R/W

0x0

AXI_CLK_LEVE3
AXICLK Level 3
/
AXI_CLK_LEVEL2
AXICLK Level 2

3.3.3.6. PMU DVFS Control Register 3
Offset: 0x0018
Bit
Read/Write
31:0
/

Default/Hex
/

Register Name: PMU_DVFS_CTRL_REG3
Description
/

3.3.3.7. PMU DVFS TimeOut Control Register(Default Value: 0x0000_0027)
Offset: 0x001C
Bit
Read/Write
31:6
/

Default/Hex
/

Register Name: PMU_DVFS_TIMEOUT_CTRL_REG
Description
/
DVFS_TIMEOUT.
DVFS operate on TWI timeout cycles in TWI peripheral clock.

000000: 1 cycle
5:0

R/W

0x27

……
100111: 40 cycles
……
111111: 64 cycles

3.3.3.8. PMU IRQ En Register (Default Value: 0x0000_0000)
Offset: 0x0040
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: PMU_IRQ_EN_REG
Description
/
VOLT_DET_ERR_IRQ_EN
Voltage Detect Error IRQ Enable

12

R/W

0x0
0: Disable
1: Enable

GR8 User Manual(Version1.0)

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Page 26

System
DVFS_CLK_SWTH_ERR_IRQ_EN
DVFS Clock Switch Operation Error IRQ Enable
11

R/W

0x0
0: Disable
1: Enable
DVFS_VOLT_CHANGE_ERR_EN
DVFS Voltage Change Error Enable

10

R/W

0x0
0: Disable
1: Enable
DVFS_SPD_DET_ERR_IRQ_EN
DVFS Speed Detect Error IRQ Enable

9

R/W

0x0
0: Disable
1: Enable

8:5

/

/

/
VOLT_DET_FIN_IRQ_EN
Voltage Detect Finished IRQ Enable

4

R/W

0x0
0: Disable
1: Enable
DVFS_CLK_SWT_FIN_IRQ_EN
DVFS Clock Switch Operation Finished IRQ Enable

3

R/W

0x0
0: Disable
1: Enable
DVFS_VOLT_CHANGE_FIN_EN
DVFS Voltage Change Finished Enable

2

R/W

0x0
0: Disable
1: Enable
DVFS_SPD_DET_FIN_IRQ_EN

1

R/W

0x0

DVFS Speed Detect Finished IRQ Enable

0: Disable

GR8 User Manual(Version1.0)

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System
1: Enable
DVFS_FIN_IRQ_EN
DVFS Finished IRQ Enable
0

R/W

0x0
0: Disable
1: Enable

3.3.3.9. PMU IRQ Status Register (Default Value: 0x00000000)
Offset: 0x0044
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: PMU_IRQ_STATUS_REG
Description
/
VOLT_DET_ERR_IRQ_PEND.
Voltage Detect Error IRQ Pending.

12

R/W

0x0

0: No effect
1: Pending.

Setting 1 to this bit will clear it.
DVFS_CLK_SWT_ERR_IRQ_PEND.
DVFS Clock Switch Operation Error IRQ Pending.

11

R/W

0x0

0: No effect
1: Pending

Setting 1 to this bit will clear it.
DVFS_VOLT_CHANGE_ERR_PEND.
DVFS Voltage Change Error Pending.

10

R/W

0x0

0: No effect
1: Pending.

Setting 1 to this bit will clear it.
DVFS_SPD_DET_ERR_IRQ_PEND.
9

R/W

0x0

GR8 User Manual(Version1.0)

DVFS Speed Detect Error IRQ Pending.

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 28

System
0: No effect
1: Pending.

Setting 1 to this bit will clear it.
8:5

/

/

/
VOLT_DET_FIN_IRQ_PEND.
Voltage Detect Finished IRQ Pending.

4

R/W

0x0

0: No effect
1: Pending.

Setting 1 to this bit will clear it.
DVFS_CLK_SWT_FIN_IRQ_PEND.
DVFS Clock Switch Operation Finished IRQ Pending.

3

R/W

0x0

0: No effect
1: Pending.

Setting 1 to this bit will clear it.
DVFS_VOLT_CHANGE_FIN_PEND.
DVFS Voltage Change Finished Pending.

2

R/W

0x0

0: No effect
1: Pending.

Setting 1 to this bit will clear it.
DVFS_SPD_DET_FIN_IRQ_PEND.
DVFS Speed Detect Finished IRQ Pending.

1

R/W

0x0

0: No effect
1: Pending.

Setting 1 to this bit will clear it.
0

R/W

0x0

GR8 User Manual(Version1.0)

DVFS_FIN_IRQ_PEND.
DVFS Finished IRQ Pending.

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System

0: No effect
1: Pending.

Setting 1 to this bit will clear it.

3.3.3.10. PMU Status Register (Default Value: 0x0000_0000)
Offset: 0x0048
Bit
Read/Write

Default/Hex

Register Name: PMU_STATUS_REG
Description

31:1

/

/

/

DVFS_BUSY.
DVFS Busy.
0

R/W

0x0
0: No effect
1: DVFS is busy.

3.3.3.11. PMU CPUVDD DCDC Control Register Address(Default Value: 0x0000_0023)
Offset: 0x004C
Bit
Read/Write

Default/Hex

Register Name: PMU_CPUVDD_CTRL_REG_ADDR
Description

31:8

/

/

/.

7:0

R/W

0x23

CPUVDD_CTRL_REG_ADDR.
PMU CPUVDD DCDC Control Register Address.

3.3.3.12. PMU TWI Address(Default Value: 0x0000_0068)
Offset: 0x0050
Bit
Read/Write
31:8
/

Default/Hex
/

7:0

0x68

R/W

Register Name: PMU_TWI_ADDR_REG
Description
/.
PMU_TWI_ADDR.
PMU TWI address set.

3.3.3.13. PMU CPUVDD Value(Default Value: 0x0000_0016)
Offset: 0x0054
Bit
Read/Write
31:8
/

Default/Hex
/

GR8 User Manual(Version1.0)

Register Name: PMU_CPUVDD_VALUE_REG
Description
/.

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 30

System
CPUVDD_DEFAULT.
PMU CPUVDD Default Value

0x00 : 0.70V
0x02 : 0.75V
0x04 : 0.80V
0x06 : 0.85V
0x08 : 0.90V
0x0A : 0.95V
0x0C : 1.00V
7:0

R/W

0x0E : 1.05V

0x16

0x10 : 1.10V
0x12 : 1.15V
0x14 : 1.20V
0x16 : 1.25V
0x18 : 1.30V
0x1A : 1.35V
0x1C : 1.40V
0x1E : 1.45V
0x20 : 1.50V
0x22 : 1.55V
0x24 : 1.60V

Note: This register can be modified by PMU DVFS.

3.3.3.14. PMU CPUVDD Voltage Ramp Control in DVM (Default Value: 0x0000_0000)
Offset: 0x0058
Bit
Read/Write
31:1
/

Default/Hex
/

Register Name: PMU_CPUVDD_RAMP_CTRL_REG
Description
/.
CPUVDD_VOLT_RAMP_CTRL.
CPUvdd voltage ramp control in DVM

0

R/W

0x0
0 : 15.625us
1 : 31.25us

Note: If the CPUVDD voltage ramp control in the external PMU is changed by the CPU, the CPU should also modify
this to be the same in the PMU.

GR8 User Manual(Version1.0)

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System

3.3.3.15. PMU 32KHz CPUVDD Minimum Value(Default Value: 0x0000_000C)
Offset: 0x005C
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: PMU_32K_CPUVDD_MIN_REG
Description
/.
CPUVDD_32K_MIN_VALUE.
PMU CPUVDD Default Value

0x00 : 0.70V
0x02 : 0.75V
0x04 : 0.80V
0x06 : 0.85V
0x08 : 0.90V
0x0A : 0.95V
0x0C : 1.00V
7:0

R/W

0x0E : 1.05V

0xc

0x10 : 1.10V
0x12 : 1.15V
0x14 : 1.20V
0x16 : 1.25V
0x18 : 1.30V
0x1A : 1.35V
0x1C : 1.40V
0x1E : 1.45V
0x20 : 1.50V
0x22 : 1.55V
0x24 : 1.60V

3.3.3.16. PMU VF Table Register 0
Offset: 0x0080
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG0
Description
/
CPU_MAX_FREQ_070.

10:0

R/W

UDF

CPU max frequency if cpuvdd=0.7V (unit: MHz)
This register can only be written if the DVFS function is disabled.

GR8 User Manual(Version1.0)

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System
3.3.3.17. PMU VF Table Register 1
Offset: 0x0084
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG1
Description
/
CPU_MAX_FREQ_075.

10:0

R/W

UDF

CPU max frequency if cpuvdd=0.75V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.18. PMU VF Table Register 2
Offset: 0x0088
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG2
Description
/
CPU_MAX_FREQ_080.

10:0

UDF

CPU max frequency if cpuvdd=0.8V (unit: MHz).

R/W

This register can only be written if the DVFS function is disabled.

3.3.3.19. PMU VF Table Register 3
Offset: 0x008C
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG3
Description
/
CPU_MAX_FREQ_085.

10:0

UDF

CPU max frequency if cpuvdd=0.85V (unit: MHz).

R/W

This register can only be written if the DVFS function is disabled.

3.3.3.20. PMU VF Table Register 4
Offset: 0x0090
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG4
Description
/
CPU_MAX_FREQ_090.

10:0

UDF

CPU max frequency if vddcpu=0.9V (unit: MHz).

R/W

This register can only be written if the DVFS function is disabled.

3.3.3.21. PMU VF Table Register 5
Offset: 0x0094
Bit
Read/Write
31:11
/

Default/Hex
/

GR8 User Manual(Version1.0)

Register Name: PMU_VF_TABLE_REG5
Description
/

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
CPU_MAX_FREQ_095.
10:0

R/W

CPU max frequency if cpuvdd=0.95V (unit: MHz).

UDF

This register can only be written if the DVFS function is disabled.

3.3.3.22. PMU VF Table Register 6
Offset: 0x0098
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG6
Description
/
CPU_MAX_FREQ_100.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.0V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.23. PMU VF Table Register 7
Offset: 0x009C
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG7
Description
/
CPU_MAX_FREQ_105.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.05V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.24. PMU VF Table Register 8
Offset: 0x00A0
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG8
Description
/
CPU_MAX_FREQ_110.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.1V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.25. PMU VF Table Register 9
Offset: 0x00A4
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG9
Description
/
CPU_MAX_FREQ_115.

10:0

UDF

CPU max frequency if cpuvdd=1.15V (unit: MHz).

R/W

This register can only be written if the DVFS function is disabled.

GR8 User Manual(Version1.0)

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System

3.3.3.26. PMU VF Table Register 10
Offset: 0x00A8
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG10
Description
/
CPU_MAX_FREQ_120.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.2V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.27. PMU VF Table Register 11
Offset: 0x00AC
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG11
Description
/
CPU_MAX_FREQ_125.

10:0

UDF

CPU max frequency if cpuvdd=1.25V (unit: MHz).

R/W

This register can only be written if the DVFS function is disabled.

3.3.3.28. PMU VF Table Register 12
Offset: 0x00B0
Bit
Read/Write

Default/Hex

31:11

/

/

Register Name: PMU_VF_TABLE_REG12
Description
/
CPU_MAX_FREQ_130.

10:0

R/W

CPU max frequency if cpuvdd=1.3V (unit: MHz).

UDF

This register can only be written if the DVFS function is disabled.

3.3.3.29. PMU VF Table Register 13
Offset: 0x00B4
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG13
Description
/.
CPU_MAX_FREQ_135.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.35V (unit: MHz).
This register can only be written if the DVFS function is disabled.

GR8 User Manual(Version1.0)

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System
3.3.3.30. PMU VF Table Register 14
Offset: 0x00B8
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG14
Description
/.
CPU_MAX_FREQ_140.

10:0

UDF

CPU max frequency if cpuvdd=1.4V (unit: MHz).

R/W

This register can only be written if the DVFS function is disabled.

3.3.3.31. PMU VF Table Register 15
Offset: 0x00BC
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG15
Description
/.
CPU_MAX_FREQ_145.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.45V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.32. PMU VF Table Register 16
Offset: 0x00C0
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG16
Description
/
CPU_MAX_FREQ_150.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.5V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.33. PMU VF Table Register 17
Offset: 0x00C4
Bit
Read/Write
31:11
/

Default/Hex
/

Register Name: PMU_VF_TABLE_REG17
Description
/
CPU_MAX_FREQ_155.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.55V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.34. PMU VF Table Register 18
Offset: 0x00C8
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: PMU_VF_TABLE_REG18
Description

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 36

System
31:11

/

/

/
CPU_MAX_FREQ_160.

10:0

R/W

UDF

CPU max frequency if cpuvdd=1.6V (unit: MHz).
This register can only be written if the DVFS function is disabled.

3.3.3.35. PMU VF Table Valid Register (Default Value: 0x0000_003C)
Offset: 0x00CC
Bit
Read/Write

Default/Hex

Register Name: PMU_VF_TABLE_VALID_REG
Description

31:6

/

/

/

VF_TABLE_18_VALID.
PMU V-F Table Register 18 Valid.
5

R/W

0x1
0: Valid
1: Invalid
VF_TABLE_17_VALID.
PMU V-F Table Register 17 Valid.

4

R/W

0x1
0: Valid
1: Invalid
VF_TABLE_16_VALID.
PMU V-F Table Register 16 Valid.

3

R/W

0x1
0: Valid
1: Invalid
VF_TABLE_15_VALID.
PMU V-F Table Register 15 Valid.

2

R/W

0x1
0: Valid
1: Invalid
VF_TABLE_14_VALID.
PMU V-F Table Register 14 Valid.

1

R/W

0x0
0: Valid
1: Invalid

0

R/W

0x0

GR8 User Manual(Version1.0)

VF_TABLE_13_VALID.

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System
PMU V-F Table Register 13 Valid.

0: Valid
1: Invalid

3.3.3.36. PMU VF Table Index Register (Default Value: 0x0000_0000)
Offset: 0x00D0
Bit
Read/Write
31:2
/

Default/Hex
/

1:0

0x0

R/W

Register Name: PMU_VF_TABLE_INDEX_REG
Description
/
VF_TABLE_IDX.
PMU V-F Table Index.

3.3.3.37. PMU VF Table Range Register (Default Value: 0x0000_0000)
Offset: 0x00D4
Bit
Read/Write
31:24
/

Default/Hex
/

23:16

R/W

0x0

15:8

R/W

0x0

7:0

R/W

0x0

Register Name: PMU_VF_TABLE_RANGE_REG
Description
/
VF_TABLE_RNG2.
PMU V-F Table Range 2.
VF_TABLE_RNG1.
PMU V-F Table Range 1.
VF_TABLE_RNG0.
PMU V-F Table Range 0.

3.3.3.38. PMU Speed Factor Register 0 (Default Value: 0x0000_0000)
Offset: 0x00E0
Bit
Read/Write

Default/Hex

Register Name: PMU_SPEED_FACTOR_REG0
Description
SPD_DET_EN
Speed Detect Enable

31

R/W

0x0
0: Disable
1: Enable
SPD_DET_MODE

30

R/W

0x0

Speed Detect Mode

0: Single mode
GR8 User Manual(Version1.0)

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System
1: Continuous mode
SPD_DET_SPDUP_FACTOR
Speed Detect Speed Up Factor
Setting these bits to non-zero value can speed up the scan operation.
29:28

R/W

0x0
00: lowest
…
11: fastest

27:17

/

/

/
SPD_DET_SCN_FIN
Speed Detect Scan Finished

16

R

0x0
0: No effect
1: Scan finished
SPD_DET_FACTOR1

15:8

R

Speed Detect Factor 1

0x0

This number indicates the delay length equivalent to input clock
period x2
SPD_DET_FACTOR0
7:0

R

Speed Detect Factor 0

0x0

This number indicates the delay length equivalent to input clock
period x1

3.3.3.39. PMU Speed Factor Register 1 (Default Value: 0x0000_0000)
Offset: 0x00E4
Bit
Read/Write

Default/Hex

Register Name: PMU_SPEED_FACTOR_REG1
Description
SPD_DET_EN
Speed Detect Enable

31

R/W

0x0
0: Disable
1: Enable
SPD_DET_MODE
Speed Detect Mode

30

R/W

0x0
0: Single mode
1: Continuous mode

GR8 User Manual(Version1.0)

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System
SPD_DET_SPDUP_FACTOR
Speed Detect Speed Up Factor
Setting these bits to non-zero value can speed up the scan operation
29:28

R/W

0x0
00: lowest
…
11: fastest

27:17

/

/

/
SPD_DET_SCN_FIN
Speed Detect Scan Finished

16

R

0x0
0: No effect
1: Scan finished
SPD_DET_FACTOR1

15:8

R

Speed Detect Factor 1

0x0

This number indicates the delay length equivalent to input clock
period x2
SPD_DET_FACTOR0
7:0

R

Speed Detect Factor 0

0x0

This number indicates the delay length equivalent to input clock
period x1

3.3.3.40. PMU Speed Factor Register 2 (Default Value: 0x0000_0000)
Offset: 0x00E8
Bit
Read/Write

Default/Hex

Register Name: PMU_SPEED_FACTOR_REG2
Description
SPD_DET_EN
Speed Detect Enable

31

R/W

0x0
0: Disable
1: Enable
SPD_DET_MODE
Speed Detect Mode

30

R/W

0x0
0: Single mode
1: Continuous mode

29:28

R/W

0x0

GR8 User Manual(Version1.0)

SPD_DET_SPDUP_FACTOR

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System
Speed Detect Speed Up Factor
Setting these bits to non-zero value can speed up the scan operation

00: lowest
…
11: fastest
27:17

/

/

/
SPD_DET_SCN_FIN
Speed Detect Scan Finished

16

R

0x0
0: No effect
1: Scan finished.
SPD_DET_FACTOR1

15:8

R

Speed Detect Factor 1

0x0

This number indicates the delay length equivalent to input clock
period x2
SPD_DET_FACTOR0
7:0

R

Speed Detect Factor 0

0x0

This number indicates the delay length equivalent to input clock
period x1

3.3.3.41. CPU Idle Counter Low Register (Default Value: 0x0000_0000)
Offset: 0x00F0
Bit
Read/Write

Default/Hex

Register Name: CPU_IDLE_CNT_LOW_REG
Description
CPU_IDLE_CNT_LO
CPU Idle Counter [31:0]

31:0

R/W

This counter clock source is 24 MHz. If CPU is in idle state, the
counter will count up in the clock of 24 MHz.

0x0

Any write to this register will clear this register and the CPU idle
counter high register.

3.3.3.42. CPU Idle Counter High Register (Default Value: 0x0000_0000)
Offset: 0x00F4
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

GR8 User Manual(Version1.0)

Register Name: CPU_IDLE_CNT_HIGH_REG
Description
CPU_IDLE_CNT_HI
CPU Idle Counter [63:32]

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System
Any write to this register will clear this register and the CPU idle
counter low register.

3.3.3.43. CPU Idle Control Register (Default Value: 0x0000_0000)
Offset: 0x00F8
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: CPU_IDLE_COUNTER_CTRL_REG
Description
/
CPU_IDLE_AUTO_SWTH_EN
CPU idle enter/exit, clk auto switch enable

0: Disable
7

R/W

0x0

1: Enable

If the CPU enter the idle mode and this bit is set, the CCU will auto
switch the CPU clock divide ratio to /8.
If the CPU exit the idle mode and this bit is set, the CCU will auto
switch the CPU clock divide ratio from /8 to /1 with 4 steps.
6:3

/

/

/
CPU_IDLE_CNT_EN
CPU idle counter enable

2

R/W

0x0
0: Disable
1: Enable.
CPU_IDLE_RL_EN
CPU idle counter read latch enable

1

R/W

0x0
0: No effect
1: To latch the idle Counter to the Low/Hi registers and it will change
to zero after the registers are latched.
CPU_IDLE_CNT_CLR_EN
CPU idle Counter Clear Enable

0

R/W

0x0
0: No effect
1: To clear the idle Counter Low/Hi registers and it will change to zero
after the registers are cleared.

GR8 User Manual(Version1.0)

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System
3.3.3.44. CPU Idle Status Register (Default Value: 0x0000_0000)
Offset: 0x00FC
Bit
Read/Write
31:1
/

Default/Hex
/

Register Name: CPU_IDLE_STATUS_REG
Description
/
CPU_IDLE_STA
CPU idle exit finished pending

0

R/W

0x0

0: No effect
1: Idle exit finished

Setting 1 to this bit will clear it.

GR8 User Manual(Version1.0)

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System

3.4. Clock Control Module (CCM)
3.4.1. Overview
The Clock Control Module (CCM) is made up of 7 PLLs, a main oscillator and an on-chip RC oscillator. The 24 MHz
crystal is mandatory to generate an input clock source for PLLs and main digital blocks.
In order to provide high performance, low-power consumption and user-friendly interfaces, the chip includes
several clock domains: CPU clock, AHB clock, APB clock and special clock. See details in the following table.
CLK Domain
OSC24M
RC_OSC
CPU32_clk
AHB_clk
APB_clk
SDRAM_clk
USB_clk

Module
Most Clock Generator
Timer,key
CPU32
AHB Devices
Peripheral
SDRAM
USB

Audio_clk

A/D,D/A

GR8 User Manual(Version1.0)

Speed Range
24 MHz
32 KHz
2 kHz~1200 MHz
8 kHz~276 MHz
0.5 kHz~138 MHz
0~400 MHz
480 MHz
24.576 MHz
/22.5792 MHz

Description
Root clock for most of the chip
Source for the timer
Divided from CPU32_clk or OSC24M
Divided from CPU32_clk
Divided from AHB_clk
Sourced from the PLL
Sourced from the PLL
Sourced from the PLL

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System

3.4.2. Clock Tree Diagram
PLL 1(240MHz-2GHz)
OUT =( 24MHz*N*K)/(M*P)
N:0-31
K:1-4
M:1-4
P:1/2/4/8

PLL 2

PLL1OUT

PLL2OUT

OUT = 22.5792MHz/24.576MHz

PLL 3(27MHz-381MHz)
OUT = 3MHz*M (Integer mode)
OUT = 270MHz/297MHz(Fractional)
M:9-127

PLL3OUT

PLL 4(240MHz-2GHz)

24MHz

X

OUT = (24MHz*N*K)/(M*P)
N:0-31
K:1-4
M:1-4
P:1/2/4/8

PLL4OUT

PLL 5(240MHz-2GHz)
OUT = ( 24MHz*N*K)/M
OUT = (24MHz*N*K)/P
N:0-31
K:1-4
M:1-4
P:1/2/4/8

PLL 6

PLL5OUT

PLL6OUT

Fixed To 1.2GHZ

PLL 7(27MHz-381MHz)
OUT = 3MHz*M (Integer mode)
OUT = 270MHz/297MHz(Fractional)
M:9-127

PLL7OUT

Figure 3-2. Clock Generation from PLL Outputs

GR8 User Manual(Version1.0)

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Page 45

System
Divider
00:/1
01:/2
10:/3
11:/4

32KHZ

OSC24M
CPU-CLK

AXI-CLK

Divider
00:/1
01:/2
10:/4
11:/8

AHB-CLK

Divider
00:/2
01:/2
10:/4
11:/8

APB0-CLK

PLL1
PLL6/6

OSC24M

PLL6

APB1-CLK
CLK_OUT= CLK_IN/(M*N)
M:1-32
N:1/2/4/8

APB1-CLK-OUT

TWI/UART//SCR

32KHZ

OSC24M

PLL6

PLL5

PLL2
8X

USB-PLL

NAND-CLK
SD0/1/2-CLK
CE-CLK
SPI0/1/2-CLK
IR-CLK
CLK_OUT= CLK_IN/(M*N)
M:1-16
N:1/2/4/8

NAND-CLK-OUT
SD0/1/2-CLK-OUT
CE-CLK-OUT

SPI0/1/2-CLK-OUT
IR-CLK-OUT

CLK_OUT= CLK_IN/*N
N:1/2/4/8

USB-CLK

USB-CLK-OUT

PLL3

PLL7

DE-BE/FE-CLK
CLK_OUT= CLK_IN/M
M:1-16

DE-BE/FE-CLK-OUT
BE-CLK-OUT

PLL5
IEP-CLK
PLL3x1

PLL7x1

LCD-CH0-CLK
CLK_OUT = CLK_IN

LCD-CH0-CLK-OUT

PLL3x2

PLL7x2

Figure 3-3. Bus Clock Generation Part 1

GR8 User Manual(Version1.0)

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System
PLL3x1

PLL7x1

LCD-CH1-CLK2
CLK_OUT= CLK_IN/M
M:1-16

LCD-CH1-CLK2

PLL3x2

LCD-CH1-CLK1
CLK_OUT = CLK_IN/M
M:1/2

PLL7x2

OSC24M

PLL3x1

CSI-CLK
CLK_OUT= CLK_IN/M
M:1-32

CSI-CLK-OUT

PLL7x1

PLL3x2

PLL7x2

VE-CLK-OUT
PLL4

VE-CLK

PLL2

AUDIOCODEC-CLK

OSC24M

AVS-CLK

AUDIOCODEC-CLK-OUT

AVS-CLK-OUT

OSC24M

PLL6

MBUS-CLK(Max 300MHz)
CLK_OUT= CLK_IN/(M*N)
M:1-16
N:1/2/4/8

MBUS-CLK-OUT

PLL5

Figure 3-4. Bus Clock Generation Part 2

3.4.3. CCM Register List
Module Name
CCM

GR8 User Manual(Version1.0)

Base Address
0x01C20000

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
Register Name

Offset

Description

PLL1_CFG_REG

0x0000

PLL1 Control

PLL1_TUN_REG

0x0004

PLL1 Tuning

PLL2_CFG_REG

0x0008

PLL2 Control

PLL2_TUN_REG

0x000C

PLL2 Tuning

PLL3_CFG_REG

0x0010

PLL3 Control

/

0x0014

/

PLL4_CFG_REG

0x0018

PLL4 Control

/

0x001C

/

PLL5_CFG_REG

0x0020

PLL5 Control

PLL5_TUN_REG

0x0024

PLL5 Tuning

PLL6_CFG_REG

0x0028

PLL6 Control

/

0x002C

PLL6 Tuning

PLL7_CFG_REG

0x0030

/

/

0x0034

/

PLL1_TUN2_REG

0x0038

PLL1 Tuning2

PLL5_TUN2_REG

0x003C

PLL5 Tuning2

/
OSC24M_CFG_REG
CPU_AHB_APB0_CFG_REG
APB1_CLK_DIV_REG
AXI_GATING_REG
AHB_GATING_REG0
AHB_GATING_REG1
APB0_GATING_REG
APB1_GATING_REG
NAND_SCLK_CFG_REG
/
SD0_SCLK_CFG_REG
SD1_SCLK_CFG_REG
SD2_SCLK_CFG_REG
/
/
CE_SCLK_CFG_REG
SPI 0_SCLK_CFG_REG
/
SPI 2_SCLK_CFG_REG
/
IR_SCLK_CFG_REG
/
I2S_SCLK_CFG_REG
/
OWA_SCLK_CFG_REG

0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
0x006C
0x0080
0x0084
0x0088
0x008C
0x0090
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8
0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0

/
OSC24M control
CPU, AHB And APB0 Divide Ratio
APB1 Clock Divider
AXI Module Clock Gating
AHB Module Clock Gating 0
AHB Module Clock Gating 1
APB0 Module Clock Gating
APB1 Module Clock Gating
NAND Flash Clock
/
SD0 Clock
SD1 Clock
SD2 Clock
/
/
Crypto Engine Clock
SPI0 Clock
/
SPI2 Clock
/
IR Clock
/
I2S Clock
/
OWA Clock

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 48

System
/
/
USBPHY_CFG_REG
/
/
DRAM_SCLK_CFG_REG
BE_CFG_REG
/
FE_CFG_REG
/
/
LCD_CH0_CFG_REG
/
/
/
/
LCD_CH1_CFG_REG
/
CSI_CFG_REG
/
VE_CFG_REG
AUDIO_CODEC_SCLK_CFG_REG
AVS_SCLK_CFG_REG
/
/
/
MALI_CLOCK_CFG_REG
/
MBUS_SCLK_CFG_REG
IEP_SCLK_CFG_REG

0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x0100
0x0104
0x0108
0x010C
0x0110
0x0114
0x0118
0x011C
0x0120
0x0124
0x0128
0x012C
0x0130
0x0134
0x0138
0x013C
0x0140
0x0144
0x0148
0x014C
0x0150
0x0154
0x0158
0x015C
0x0160

/
/
USBPHY Clock
/
/
DRAM Clock
Display Engine Backend Clock
Display Engine Front End Clock
/
/
LCD Channel0 Clock
/
/
/
/
LCD Channel1 Clock
/
CSI Clock
/
Video Engine Clock
Audio Codec Gating Special Clock
AVS Gating Special Clock
/
/
/
Mali400 Gating Special Clock
/
MBUS Gating Clock
IEP Gating Clock

3.4.4. CCM Register Description
3.4.4.1. PLL1-Core Register (Default Value: 0x2100_5000)
Offset: 0x0000
Bit
Read/Write

Default/Hex

31

0x0

R/W

Register Name: PLL1_CFG_REG
Description
PLL1_Enable.

0: Disable
1: Enable.

The PLL1 output= (24 MHz*N*K)/ (M*P).

GR8 User Manual(Version1.0)

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System
The PLL1 output is for the CORECLK.
Note: The output 24 MHz*N*K clock must be in the range of 240
MHz~2 GHz if the bypass is disabled.
Its default is 384 MHz.
30:18

/

/

/
PLL1_OUT_EXT_DIVP.

17:16

R/W

0x0

PLL1 Output external divider P.
The range is 1/2/4/8.

15:13

/

/

/.
PLL1_FACTOR_N
PLL1 Factor N.
Factor=0, N=0;

12:8

R/W

0x10

Factor=1, N=1;
Factor=2, N=2
……
Factor=31, N=31

7:6

/

/

/
PLL1_FACTOR_K.

5:4

R/W

0x0

PLL1 Factor K. (K=Factor + 1)
The range is from 1 to 4.

3

R/W

0x0

/

2

R/W

0x0

/
PLL1_FACTOR_M.

1:0

R/W

0x0

PLL1 Factor M. (M=Factor + 1)
The range is from 1 to 4.

3.4.4.2. PLL1-Tuning Register (Default Value: 0x0A10_1000)
Offset: 0x0004
Bit
Read/Write

Default/Hex

Register Name: PLL1_TUN_REG
Description

31:28

/

/

/

27

R/W

0x1

/

26

R/W

0x0

/

25:23

R/W

0x4

/

22:16

R/W

0x10

/

15

R/W

0x0

/

GR8 User Manual(Version1.0)

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System
14:8

R/W

0x10

/

7

R/W

0x0

/

6:0

R

0x0

/

3.4.4.3. PLL2-Audio Register (Default Value: 0x0810_0010)
Offset: 0x0008
Bit
Read/Write

Default/Hex

Register Name: PLL2_CFG_REG
Description
PLL2_Enable.

0: Disable
1: Enable.

31

R/W

0x0

The PLL2 is for Audio.
PLL2 Output = 24 MHz*N/PLL2_PRE_DIV/PLL2_POST_DIV.
1X = 48*N/PreDiv/PostDiv/2 (not 50% duty)
2X = 48*N/PreDiv/4 (8X/4 50% duty)
4X = 48*N/PreDiv/2 (8X/2 50% duty)
8X = 48*N/PreDiv (not 50% duty)

30

/

/

/
PLL2_POST_DIV.
PLL2 post-divider [3:0].

29:26

R/W

0x2

0000: 0x1
……
1111: 0x10

25:21

R/W

0x0

/

20:16

R/W

0x10

/

15

/

/

/
PLL2_Factor_N.
PLL2 Factor N.

14:8

R/W

0x0

Factor=0, N=1;
Factor=1, N=1;
……
Factor=0x7F, N=0x7F

7:5

/

/

GR8 User Manual(Version1.0)

/

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System
PLL2_PRE_DIV.
PLL2 pre-divider [4:0].
4:0

R/W

0x10

00000: 0x1
……
11111: 0x20

3.4.4.4. PLL2-Tuning Register (Default Value: 0x0000_0000)
Offset: 0x000C
Bit
Read/Write

Default/Hex

Register Name: PLL2_TUN_REG
Description

31

R/W

0x0

/

30:29

R/W

0x0

/

28:20

R/W

0x0

/

19

/

/

/

18:17

R/W

0x0

/

16:0

R/W

0x0

/

3.4.4.5. PLL3-Video Register (Default Value: 0x0010_D063)
Offset: 0x0010
Bit
Read/Write

Default/Hex

Register Name: PLL3_CFG_REG
Description
PLL3_Enable.

0: Disable
31

R/W

0x0

1: Enable.

In the integer mode, The PLL3 output=3 MHz*M.
In the fractional mode, the PLL3 output is selected by bit 14.
The PLL3 output range is 27 MHz~381 MHz.
30:27

/

/

/

26:24

R/W

0x0

/

23:21

/

/

/

20:16

R/W

0x10

/

15

R/W

0x1

GR8 User Manual(Version1.0)

PLL3_MODE_SEL.
PLL3 mode select.

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Page 52

System

0: Fractional mode
1: Integer mode.
PLL3_FUNC_SET.
PLL3 fractional setting.
14

R/W

0x1
0: 270 MHz
1: 297 MHz

13

/

/

/

12:8

R/W

0x10

/

7

/

/

/
PLL3_FACTOR_M.

6:0

R/W

0x63

PLL3 Factor M.
The range is from 9 to 127.

3.4.4.6. PLL4-VE Register (Default Value: 0x2108_1000)
Offset: 0x0018
Bit
Read/Write

Default/Hex

Register Name: PLL4_CFG_REG
Description
PLL4_Enable.

0: Disable
1: Enable.
31

R/W

0x0
The PLL4 output= (24 MHz*N*K)/ (M*P).
The PLL4 output is for the VE.
Note: The output 24 MHz*N*K clock must be in the range of
240 MHz~2 GHz if the bypass is disabled.
PLL4_OUT_BYPASS_EN.
PLL4 Output Bypass Enable.

30

R/W

0x0

0: Disable
1: Enable.

If the bypass is enabled, the PLL4 output is 24 MHz.
29:25

R/W

0x10

GR8 User Manual(Version1.0)

/

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Page 53

System
24:20

R/W

0x10

/

19

R/W

0x1

/

18

/

/

/
PLL4_OUT_EXT_DIV_P.

17:16

R/W

0x0

PLL4 Output external divider P.
The range is 1/2/4/8.

15:13

/

/

/
PLL4_FACTOR_N.
PLL4 Factor N.
Factor=0, N=0;

12:8

R/W

0x10

Factor=1, N=1;
Factor=2, N=2
……
Factor=31, N=31

7:6

/

/

/
PLL4_FACTOR_K.

5:4

R/W

0x0

PLL4 Factor K. (K=Factor + 1)
The range is from 1 to 4.

3:2

/

/

/
PLL4_FACTOR_M.

1:0

R/W

0x0

PLL4 Factor M. (M = Factor + 1)
The range is from 1 to 4.

3.4.4.7. PLL5-DDR Register (Default Value: 0x1104_9280)
Offset: 0x0020
Bit
Read/Write

Default/Hex

Register Name: PLL5_CFG_REG
Description
PLL5_Enable.

0: Disable
1: Enable.
31

R/W

0x0
The PLL5 output for DDR = (24 MHz*N*K)/M.
The PLL5 output for another module = (24 MHz*N*K)/P.
The PLL5 output is for the DDR.
Note: The output 24 MHz*N*K clock must be in the range of

GR8 User Manual(Version1.0)

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System
240 MHz~2 GHz if the bypass is disabled.
PLL5_OUT_BYPASS_EN.
PLL5 Output Bypass Enable.

30

R/W

0x0

0: Disable
1: Enable.

If the bypass is enabled, the PLL6 output is 24 MHz.
DDR_CLK_OUT_EN.

29

R/W

0x0

28:25

R/W

0x8

/

24:20

R/W

0x10

/

19

R/W

0x0

/

18

R/W

0x1

/

DDR clock output en.

PLL5_OUT_EXT_DIV_P.
17:16

R/W

0x0

PLL5 Output External Divider P.
The range is 1/2/4//8.

15:13

R/W

0x4

/
PLL5_FACTOR_N.
PLL5 Factor N.
Factor=0, N=0;

12:8

R/W

0x12

Factor=1, N=1;
Factor=2, N=2
……
Factor=31, N=31

7

R/W

0x1

6

/

/

LDO_EN.
LDO Enable.
/
PLL5_FACTOR_K.

5:4

R/W

0x0

PLL5 Factor K. (K=Factor + 1)
The range is from 1 to 4.

3:2

R/W

0x0

1:0

R/W

0x0

GR8 User Manual(Version1.0)

PLL5_FACTOR_M1.
PLL5 Factor M1.
PLL5_FACTOR_M.
PLL5 Factor M. (M = Factor + 1)

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System
The range is from 1 to 4.

3.4.4.8. PLL5-Tuning Register (Default Value: 0x1488_0000)
Offset: 0x0024
Bit
Read/Write
31:0
/

Default/Hex
/

Register Name: PLL5_TUN_REG
Description
/

3.4.4.9. PLL6 Register (Default Value: 0x2100_9931)
Offset: 0x0028
Bit
Read/Write

Default/Hex

Register Name: PLL6_CFG_REG
Description
PLL6_Enable.

0: Disable
1: Enable.
31

R/W

0x0
Output = (24 MHz*N*K)/M/2
Note: The output 24 MHz*N*K clock must be in the range of
240 MHz~3 GHz if the bypass is disabled.
Its default is 1200 MHz.
PLL6_BYPASS_EN.
PLL6 Output Bypass Enable.

30

R/W

0x0

0: Disable
1: Enable.

If the bypass is enabled, the PLL6 output is 24 MHz.
29:13

/

/

/
PLL6_FACTOR_N.
PLL6 Factor N.
Factor=0, N=0;

12:8

R/W

0x19

Factor=1, N=1;
Factor=2, N=2;
……
Factor=31, N=31

7:6

/

/

GR8 User Manual(Version1.0)

PLL6 damping factor control [1:0].

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 56

System
PLL6_FACTOR_K.
5:4

/

/

PLL6 Factor K. (K=Factor + 1)
The range is from 1 to 4.

3:2

/

/

/
PLL6_FACTOR_M.

1:0

R/W

0x1

PLL6 Factor M. (M = Factor + 1)
The range is from 1 to 4.

3.4.4.10. PLL7 Register (Default Value: 0x0010_D063)
Offset: 0x0030
Bit
Read/Write

Default/Hex

Register Name: PLL7_CFG_REG
Description
PLL7_Enable.

0: Disable
31

R/W

0x0

1: Enable.

In the integer mode, The PLL7 output=3 MHz*M.
In the fractional mode, the PLL7 output is selected by bit 14.
The PLL7 output range is 27 MHz~381 MHz.
30:16

/

/

/
PLL7_MODE_SEL.
PLL7 mode select.

15

R/W

0x1
0: Fractional mode
1: Integer mode.
PLL7_FRAC_SET.
PLL7 fractional setting.

14

R/W

0x1
0: 270 MHz
1: 297 MHz

13:7

/

/

/
PLL7_FACTOR_M.

6:0

R/W

0x63

PLL7 Factor M.
The range is from 9 to 127.

GR8 User Manual(Version1.0)

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System
3.4.4.11. PLL1-Tuning2 Register (Default Value: 0x0000_0000)
Offset: 0x0038
Bit
Read/Write

Default/Hex

31

0x0

R/W

Register Name: PLL1_TUN2_REG
Description
SIG_DELT_PAT_EN.
Sigma-delta pattern enable.
SPR_FREQ_MODE.
Spread Frequency Mode.

30:29

R/W

0x0

00: DC=0
01: DC=1
10: Triangular
11: awmode

28:20

R/W

0x0

19

/

/

WAVE_STEP.
Wave step.
/
FREQ.
Frequency.

18:17

R/W

0x0

00: 31.5 kHz
01: 32 kHz
10: 32.5 kHz
11: 33 kHz

16:0

R/W

WAVE_BOT.

0x0

Wave Bottom.

3.4.4.12. PLL5-Tuning2 Register (Default Value: 0x0000_0000)
Offset: 0x003C
Bit
Read/Write

Default/Hex

31

0x0

R/W

Register Name: PLL5_TUN2_REG
Description
SIG_DELT_PAT_EN.
Sigma-delta pattern enable.
SPR_FREQ_MODE.
Spread Frequency Mode.

30:29

R/W

0x0
00: DC=0
01: DC=1

GR8 User Manual(Version1.0)

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System
10: Triangular
11: awmode
28:20

R/W

0x0

19

/

/

WAVE_STEP.
Wave step.
/
FREQ.
Frequency.

18:17

R/W

0x0

00: 31.5 kHz
01: 32 kHz
10: 32.5 kHz
11: 33 kHz

16:0

R/W

WAVE_BOT.

0x0

Wave Bottom.

3.4.4.13. OSC24M Register (Default Value: 0x0013_8013)
Offset: 0x0050
Bit
Read/Write

Default/Hex

Register Name: OSC24M_CFG_REG
Description

31:24

R/W

0x0

/

23:18

/

/

/
PLL_IN_PWR_SEL.
PLL Input Power Select.

17

R/W

0x1
0: 2.5V
1: 3.3V
LDO_EN.
LDO Enable.

16

R/W

0x1
0: Disable
1: Enable.
PLL_BIAS_EN.
PLL Bias Enable.

15

R/W

0x1
0: Disable
1: Enable.

GR8 User Manual(Version1.0)

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Page 59

System
14:2

/

/

1

R/W

0x1

/
OSC24M_GSM.
OSC24M GSM.
OSC24M_EN.
OSC24M Enable.

0

R/W

0x1
0: Disable
1: Enable.

3.4.4.14. CPU/AHB/APB0 Clock Ratio Register (Default Value: 0x0001_0010)
Offset: 0x0054
Bit
Read/Write
31:18
/

Default/Hex
/

Register Name: CPU_AHB_APB0_CFG_REG
Description
/
CPU_CLK_SRC_SEL.
CPU Clock Source Select.

00: 32 KHz OSC( Internal )
17:16

R/W

0x1

01: OSC24M
10: PLL1
11: 200 MHz (source from the PLL6).

If the clock source is changed, at most to wait for 8 present running
clock cycles.
15:10

/

/

/
APB0_CLK_RATIO.
APB0 Clock divide ratio. APB0 clock source is AHB2 clock.

9:8

R/W

0x0

00: /2
01: /2
10: /4
11: /8
AHB_CLK_SRC_SEL.

7:6

R/W

0x0

00: AXI
01: CPUCLK

GR8 User Manual(Version1.0)

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System
10: PLL6/2
11:
AHB_CLK_DIV_RATIO.
AHB Clock divide ratio.
AHB clock source is AXI Clock.
5:4

R/W

0x1

00: /1
01: /2
10: /4
11: /8

3:2

/

/

/
AXI_CLK_DIV_RATIO.
AXI Clock divide ratio.
AXI Clock source is CPU clock.

1:0

R/W

0x0

00: /1
01: /2
10: /3
11: /4

3.4.4.15. APB1 Clock Divide Ratio Register (Default Value: 0x0000_0000)
Offset: 0x0058
Bit
Read/Write
31:26
/

Default/Hex
/

Register Name: APB1_CLK_DIV_REG
Description
/
APB1_CLK_SRC_SEL.
APB1 Clock Source Select

00: OSC24M
01: PLL6 (set to 1.2 GHz)
25:24

R/W

0x0

10: 32 KHz
11: /

This clock is used for some special module apbclk (TWI,UART).
Because these modules need special clock rate even if the apbclk
changes.
23:18

/

/

GR8 User Manual(Version1.0)

/

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Page 61

System
CLK_RAT_N
17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.

15:5

/

/

/
CLK_RAT_M.

4:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 32.

3.4.4.16. AXI Module Clock Gating Register (Default Value: 0x0000_0000)
Offset: 0x005C
Bit
Read/Write
31:1
/

Default/Hex
/

0

0x0

R/W

Register Name: AXI_GATING_REG
Description
/
DRAM_AXI_GATING.
Gating AXI Clock for SDRAM (0: mask, 1: pass).

3.4.4.17. AHB Module Clock Gating Register 0(Default Value: 0x0000_0000)
Offset: 0x0060
Bit
Read/Write
31:29
/

Default/Hex
/

28

R/W

0x0

27

/

/

/

26

R/W

0x0

/

25:23

/

/

/

22

R/W

0x0

21

R/W

0x0

20

R/W

0x0

19

/

/

/

18

R/W

0x0

/

17

R/W

0x0

/

16:15

/

/

/

14

R/W

0x0

GR8 User Manual(Version1.0)

Register Name: AHB_GATING_REG0
Description
/
STIMER_AHB_GATING.
Gating AHB Clock for Sync timer (0: mask, 1: pass).

SPI2_AHB_GATING.
Gating AHB Clock for SPI2 (0: mask, 1: pass).
/
SPI0_AHB_GATING.
Gating AHB Clock for SPI0 (0: mask, 1: pass).

SDRAM_AHB_GATING.
Gating AHB Clock for SDRAM (0: mask, 1: pass).
Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
NAND_AHB_GATING.

13

R/W

0x0

12

R/W

0x0

/

11

/

/

/

10

R/W

0x0

9

R/W

0x0

8

R/W

0x0

7

R/W

0x0

6

R/W

0x0

5

R/W

0x0

4:3

/

/

2

R/W

0x0

1

R/W

0x0

0

R/W

0x0

Gating AHB Clock for NAND (0: mask, 1: pass).

SD2_AHB_GATING.
Gating AHB Clock for SD/MMC2 (0: mask, 1: pass).
SD1_AHB_GATING.
Gating AHB Clock for SD/MMC1 (0: mask, 1: pass).
SD0_AHB_GATING.
Gating AHB Clock for SD/MMC0 (0: mask, 1: pass).
BIST_AHB_GATING.
Gating AHB Clock for BIST (0: mask, 1: pass).
DMA_AHB_GATING.
Gating AHB Clock for DMA (0: mask, 1: pass).
CE_AHB_GATING.
Gating AHB Clock for CE (0: mask, 1: pass).
/
OHCI_AHB_GATING.
Gating AHB Clock for USB OHCI (0: mask, 1: pass).
EHCI_AHB_GATING.
Gating AHB Clock for USB EHCI (0: mask, 1: pass).
USBOTG_AHB_GATING.
Gating AHB Clock for USB OTG (0: mask, 1: pass).

3.4.4.18. AHB Module Clock Gating Register 1(Default Value: 0x0000_0000)
Offset: 0x0064
Bit
Read/Write
31:21
/

Default/Hex
/

Register Name: AHB_GATING_REG1
Description
/

20

R/W

0x0

Gating AHB Clock for Mali-400(0: mask, 1: pass).

19

R/W

0x0

18:15

/

/

14

R/W

0x0

13

/

/

GR8 User Manual(Version1.0)

IEP_AHB_GATING.
Gating AHB Clock for IEP (0: mask, 1: pass).
/
FE_AHB_GATING.
Gating AHB Clock for DE-FE (0: mask, 1: pass).
/

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 63

System
BE_AHB_GATING.

12

R/W

0x0

11

R/W

0x0

/

10:9

/

/

/

8

R/W

0x0

7:5

/

/

4

R/W

0x0

3

/

/

/

2

R/W

0x0

/

1

/

/

/

0

R/W

0x0

Gating AHB Clock for DE-BE (0: mask, 1: pass).

CSI_AHB_GATING.
Gating AHB Clock for CSI (0: mask, 1: pass).
/
LCD_AHB_GATING.
Gating AHB Clock for LCD (0: mask, 1: pass).

VE_AHB_GATING.
Gating AHB Clock for VE (0: mask, 1: pass).

3.4.4.19. APB0 Module Clock Gating Register (Default Value: 0x0000_0000)
Offset: 0x0068
Bit
Read/Write

Default/Hex

Register Name: APB0_GATING_REG
Description

31:11

/

/

/

10

R/W

0x0

/

9:7

/

/

/

6

R/W

0x0

5

R/W

0x0

4

/

/

/

3

R/W

0x0

/

2

/

/

/

1

R/W

0x0

/

0

R/W

0x0

IR_APB_GATING.
Gating APB Clock for IR (0: mask, 1: pass).
PIO_APB_GATING.
Gating APB Clock for PIO (0: mask, 1: pass).

CODEC_APB_GATING.
Gating APB Clock for Audio CODEC (0: mask, 1: pass).

3.4.4.20. APB1 Module Clock Gating Register (Default Value: 0x0000_0000)
Offset: 0x006C
GR8 User Manual(Version1.0)

Register Name: APB1_GATING_REG
Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 64

System
Bit
31:24

Read/Write
/

Default/Hex
/

Description
/

23

/

/

/

22

/

/

/

21

/

/

/

20

/

/

/

19

R/W

0x0

18

R/W

0x0

17

R/W

0x0

16

R/W

0x0

15:8

/

/

/

7

/

/

/

6

/

/

/

5

/

/

/

4

/

/

/

3

/

/

/

2

R/W

0x0

1

R/W

0x0

0

R/W

0x0

UART3_APB_GATING.
Gating APB Clock for UART3 (0: mask, 1: pass).
UART2_APB_GATING.
Gating APB Clock for UART2 (0: mask, 1: pass).
UART1_APB_GATING.
Gating APB Clock for UART1 (0: mask, 1: pass).
UART0_APB_GATING.
Gating APB Clock for UART0 (0: mask, 1: pass).

TWI2_APB_GATING.
Gating APB Clock for TWI2 (0: mask, 1: pass).
TWI1_APB_GATING.
Gating APB Clock for TWI1 (0: mask, 1: pass).
TWI0_APB_GATING.
Gating APB Clock for TWI0 (0: mask, 1: pass).

3.4.4.21. NAND Clock Register (Default Value: 0x0000_0000)
Offset: 0x0080
Bit
Read/Write

Default/Hex

Register Name: NAND_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 200 MHz)

31

R/W

0x0
0: Clock is OFF
1: Clock is ON

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 65

System

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: /

23:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.

15:4

/

/

/
CLK_DIV_RATIO_M

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

Note: In application, the module clock frequency always switches off.

3.4.4.22. SD0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0088
Bit
Read/Write

Default/Hex

Register Name: SD0_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 200 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL.

25:24

R/W

0x0

Clock Source Select

00: OSC24M

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 66

System
01: PLL6
10: PLL5
11: /.
23:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.23. SD1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x008C
Bit
Read/Write

Default/Hex

Register Name: SD1_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 200 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: /

23:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.

15:4

/

/

GR8 User Manual(Version1.0)

/

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
CLK_DIV_RATIO_M.
3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.24. SD2 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0090
Bit
Read/Write

Default/Hex

Register Name: SD2_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 200 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: /.

23:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.25. CE Clock Register (Default Value: 0x0000_0000)
Offset: 0x009C
Bit
Read/Write
31
R/W

Default/Hex
0x0

GR8 User Manual(Version1.0)

Register Name: CE_SCLK_CFG_REG
Description
SCLK_GATING.

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 68

System
Gating Special Clock(Max Clock = 200 MHz)

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: /

23:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2n. The divider is 1/2/4/8.

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.26. SPI0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x00A0
Bit
Read/Write

Default/Hex

Register Name: SPI 0_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 200 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
Clock Source Select

00: OSC24M
01: PLL6
10: PLL5
11: /
23:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2n. The divider is 1/2/4/8.

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.27. SPI2 Clock Register (Default Value: 0x0000_0000)
Offset: 0x00A8
Bit
Read/Write

Default/Hex

Register Name: SPI2_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 200 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: /

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_M.

GR8 User Manual(Version1.0)

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System
Clock pre-divide ratio (n)
The select clock source is pre-divided by 2n. The divider is 1/2/4/8.
15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.28. IR Clock Register (Default Value: 0x0000_0000)
Offset: 0x00B0
Bit
Read/Write

Default/Hex

Register Name: IR_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 100 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:26

/

/

/
CLK_SRC_SEL
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: /

23:18

/

/

/
CLK_DIV_RATIO.

17:16

R/W

0x0

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2n. The divider is 1/2/4/8.

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

GR8 User Manual(Version1.0)

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System
3.4.4.29. I2S/PCM Clock Register (Default Value: 0x0000_0000)
Offset: 0x00B8
Bit
Read/Write

Default/Hex

Register Name: I2S/PCM_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 100 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N/Divider M.
30:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

Clock pre-divide ratio (n)

0x0

The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.
The clock source is PLL2 (8x).

15:0

/

/

/

3.4.4.30. I2S/PCM Clock Register (Default Value: 0x0001_0000)
Offset: 0x00C0
Bit
Read/Write

Default/Hex

Register Name: OWA_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 100MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider N.
30:18

/

/

/
CLK_DIV_RATIO_N.

17:16

R/W

0x1

Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.
The clock source is PLL2 (8x).

15:4

/

/

/

3:0

/

/

/

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 72

System
3.4.4.31. USB PHY Clock Register (Default Value: 0x0000_0000)
Offset: 0x00CC
Bit
Read/Write
31:10
/

Default/Hex
/

Register Name: USBPHY_CFG_REG
Description
/
USBPHY1_CLK_GATING.
Gating Special Clock for USB PHY1

9

R/W

0x0
0: Clock is OFF
1: Clock is ON
USBPHY0_CLK_GATING.
Gating Special Clock for USB PHY0

8

R/W

0x0
0: Clock is OFF
1: Clock is ON

7

/

/

/
OHCI_SCLK_GATING.
Gating Special Clock for OHCI

6

R/W

0x0
0: Clock is OFF
1: Clock is ON

5:2

/

/

/
USBPHY1_RST_CTRL.
USB PHY1 Reset Control

1

R/W

0x0
0: Reset valid
1: Reset invalid
USBPHY0_RST_CTRL.
USB PHY0 Reset Control

0

R/W

0x0
0: Reset valid
1: Reset invalid

3.4.4.32. DRAM Clock Register (Default Value: 0x0000_0000)
Offset: 0x0100
Bit
Read/Write
31
R/W

Default/Hex
0x0

GR8 User Manual(Version1.0)

Register Name: DRAM_SCLK_CFG_REG
Description
IEP_DCLK_GATING.

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 73

System
Gating DRAM Clock for IEP (0: mask, 1: pass).
30

/

/

/

29

R/W

0x0

28

/

/

/

27

/

/

/

26

R/W

0x0

25

R/W

0x0

24

/

/

/

23:16

/

/

/

15

/

/

/

14:7

/

/

/

6

/

/

/

5

R/W

0x0

/

4

/

/

/

3

R/W

0x0

/

2

/

/

/

1

R/W

0x0

0

R/W

0x0

ACE_DCLK_GATING.
Gating DRAM Clock for ACE (0: mask, 1: pass).

BE_DCLK_GATING.
Gating DRAM Clock for DE_BE (0: mask, 1: pass).
FE_DCLK_GATING.
Gating DRAM Clock for DE_FE (0: mask, 1: pass).

CSI_DCLK_GATING.
Gating DRAM Clock for CSI (0: mask, 1: pass).
VE_DCLK_GATING.
Gating DRAM Clock for VE (0: mask, 1: pass).

3.4.4.33. DE-BE Clock Register (Default Value: 0x0000_0000)
Offset: 0x0104
Bit
Read/Write

Default/Hex

Register Name: BE_CFG_REG
Description
SCLK_GATING.
Gating Special Clock

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider M.
30

R/W

0x0

GR8 User Manual(Version1.0)

BE_RST.

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 74

System
DE-BE Reset.

0: Reset valid
1: Reset invalid.
29:26

/

/

/
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: PLL3
01: PLL7
10: PLL5
11: /.

23:18

/

/

/

17:16

/

/

/

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.34. DE-FE Clock Register (Default Value: 0x0000_0000)
Offset: 0x010C
Bit
Read/Write

Default/Hex

Register Name: FE_CFG_REG
Description
SCLK_GATING.
Gating Special Clock

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider M.
FE_RST.
DE-FE Reset.
30

R/W

0x0
0: Reset valid
1: Reset invalid.

29:26

/

/

GR8 User Manual(Version1.0)

/

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 75

System
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: PLL3
01: PLL7
10: PLL5
11: /.

23:18

/

/

/

17:16

/

/

/

15:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.35. LCD CH0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0118
Bit
Read/Write

Default/Hex

Register Name: LCD_CH0_CFG_REG
Description
SCLK_GATING.
Gating Special Clock

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source
LCD_RST.
LCD Reset.
30

R/W

0x0
0: Reset valid
1: Reset invalid
TVE_RST.
TV Encoder Reset.

29

R/W

0x0
0: Reset valid
1: Reset invalid

28:26

/

/

GR8 User Manual(Version1.0)

/

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 76

System
CLK_SRC_SEL.
Clock Source Select

25:24

R/W

0x0

00: PLL3(1X)
01: PLL7(1X)
10: PLL3(2X)
11: PLL7(2X)

23:0

/

/

/

3.4.4.36. LCD CH1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x012C
Bit
Read/Write

Default/Hex

Register Name: LCD_CH1_CFG_REG
Description
SCLK2_GATING.
Gating Special Clock 2

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock 2= Special Clock 2 Source/Divider M.
30:26

/

/

/
SCLK2_SRC_SEL.
Special Clock 2 Source Select

25:24

R/W

0x0

00: PLL3(1X)
01: PLL7(1X)
10: PLL3(2X)
11: PLL7(2X)

23:18

/

/

/

17:16

R/W

0x0

/
SCLK1_GATING.
Gating Special Clock 1

15

/

/

0: Clock is OFF
1: Clock is ON

GR8 User Manual(Version1.0)

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Page 77

System
This special clock 1= Special Clock 1 Source.
14:12

/

/

/
SCLK1_SRC_SEL.
Special Clock 1 Source Select.

11

R/W

0x0
0: Special Clock 2
1: Special Clock 2 divide by 2

10:4

/

/

/
CLK_DIV_RATIO_M.

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.37. CSI Clock Register (Default Value: 0x0000_0000)
Offset: 0x0134
Bit
Read/Write

Default/Hex

Register Name: CSI_CFG_REG
Description
SCLK_GATING.
Gating Special Clock

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider M.
CSI_RST.
CSI Reset.
30

R/W

0x0
0: Reset valid
1: Reset invalid.

29:27

/

/

/
CLK_SRC_SEL.
Clock Source Select

26:24

R/W

0x0

000: OSC24M
001: PLL3(1X)
010: PLL7(1X)
011: /

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100: /
101: PLL3(2X)
110: PLL7(2X)
111: /
23:18

/

/

/

17:16

/

/

/

15:5

/

/

/
CLK_DIV_RATIO_M.

4:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 32.

3.4.4.38. VE Clock Register (Default Value: 0x0000_0000)
Offset: 0x013C
Bit
Read/Write

Default/Hex

Register Name: VE_CFG_REG
Description
SCLK_GATING.
Gating the Special clock for VE (0: mask, 1: pass).

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock is PLL4.
25:24

/

/

/

30:20

/

/

/

19:16

/

/

/

15:1

/

/

/
VE_RST.
VE Reset.

0

R/W

0x0
0: Reset valid
1: Reset invalid.

3.4.4.39. Audio Codec Clock Register (Default Value: 0x0000_0000)
Offset: 0x0140
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: AUDIO_CODEC_SCLK_CFG_REG
Description

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SCLK_GATING.
Gating Special Clock

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = PLL2 output.
30:0

/

/

/

3.4.4.40. AVS Clock Register (Default Value: 0x0000_0000)
Offset: 0x0144
Bit
Read/Write

Default/Hex

Register Name: AVS_SCLK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = OSC24M.
30:0

/

/

/

3.4.4.41. Mali-400 Clock Register(Default Value: 0x0000_0000)
Offset: 0x0154
Bit
Read/Write

Default/Hex

Register Name: MALI_CLOCK_CFG_REG
Description
SCLK_GATING.
Gating Special Clock(Max Clock = 381 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

This special clock = Clock Source/Divider M.
MALI400_RST.
30

R/W

0x0

Mali400 Reset.

0: Reset valid
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1: Reset invalid
29:27

/

/

/
CLK_SRC_SEL.
Clock Source Select

26:24

R/W

000: PLL3(1X)

0x0

001: PLL4
010: PLL5
011: PLL7 (1X).
100: PLL7(2X)

23:18

/

/

/

17:16

/

/

/

15:4

/

/

/.
CLK_DIV_RATIO_M

3:0

R/W

0x0

Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.4.4.42. MBUS Clock Control Register (Default Value: 0x0000_0000)
Offset: 0x015C
Bit
Read/Write

Default/Hex

Register Name: MBUS_SCLK_CFG_REG
Description
MBUS_SCLK_GATING.
Gating Clock for MBUS (Max Clock = 300 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

MBUS_CLOCK = Clock Source/Divider N/Divider M
30:26

/

/

/
MBUS_SCLK_SRC
Clock Source Select

25:24

R/W

0x0

00: OSC24M
01: PLL6
10: PLL5
11: Reserved

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23:18

/

/

/
MBUS_SCLK_RATIO_N

17:16

R/W

0x0

Clock Pre-divide Ratio (N)
The select clock source is pre-divided by 2^N. The divider is 1/2/4/8.

15:4

/

/

/
MBUS_SCLK_RATIO_M

3:0

R/W

0x0

Clock Divide Ratio (M)
The divided clock is divided by (M+1). The divider is from 1 to 16.

3.4.4.43. IEP Clock Control Register (Default Value: 0x0000_0000)
Offset: 0x0160
Bit
Read/Write

Default/Hex

Register Name: IEP_SCLK_CFG_REG
Description
IEP_SCLK_GATING.
Gating Clock for IEP (Max Clock = 300 MHz)

31

R/W

0x0

0: Clock is OFF
1: Clock is ON

IEP_CLOCK = BE Clock
IEP_RST.
IEP Reset.
30

R/W

0x0
0: Reset valid
1: Reset invalid.

29:0

/

/

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/

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3.5. System Control
3.5.1. Overview
The chip embeds a high-speed SRAM, which is split into five areas. Its memory mapping is detailed in the following
table:
Area
A1
A2
A3
A4
C1
C3
NAND
D( USB )
CPU I-Cache
CPU D-Cache
CPU L2 Cache

Address
0x00000000--0x00003FFF
0x00004000--0x00007FFF
0x00008000--0x0000B3FF
0x0000B400--0x0000BFFF
0x01D00000-0x01D7FFFF
0x01DC0000-0x01DCFFFF

Size(Bytes)
16K
16K
13K
3K
VE
ISP
2K
4K
32K
32K
128K

0x00010000—0x00010FFF

3.5.2. System Control Register List
Module Name
SRAM Controller

Base Address
0x01C00000

Register Name
SRAM_CFG_REG0
SRAM_CFG_REG1

Offset
0x0000
0x0004

Description
SRAM Configuration
SRAM Control

3.5.3. System Control Register Description
3.5.3.1. SRAM Configuration Register 0(Default Value: 0x7FFF_FFFF)
Offset: 0x0000
Bit
Read/Write
31
/

Default/Hex
/

Register Name: SRAM_CFG_REG0
Description
/
SRAM_C1_MAP.
SRAM Area C1 50K Bytes Configuration by AHB.

30:0

R/W

0x7fffffff
0: Map to CPU/DMA
1: Map to VE

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3.5.3.2. SRAM Configuration Register 1(Default Value: 0x0000_1000)
Offset: 0x0004
Bit
Read/Write

Default/Hex

Register Name: SRAM_CFG_REG1
Description

31

R/W

0x0

/

30:18

/

/

/

17

R/W

0x0

/

16

R/W

0x0

/

15:14

R/W

0x0

/

13

/

/

/
SRAM_C3_MAP.
SRAM C3 Map Config.

12

R/W

0x1
0: Map to CPU/BIST
1: Map to ISP

11:6

/

/

/
SRAM_A3_A4_MAP.
SRAM Area A3/A4 Configuration by AHB.

5:4

R/W

0x0

00: Map to CPU/DMA
01: /
10: /
11: /

3:1

/

/

/
SRAM_D_MAP.
SRAM D Area Config.

0

R/W

0x0
0: Map to CPU/DMA
1: Map to USB-OTG

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3.6. CPU Control
3.6.1. CPU Register List
Module Name
CPU CTL

Base Address
0x01C23400

Register Name
CPU_CTRL_REG

Offset
0x0020

Description
CPU Control Register

3.6.2. CPU Control Register Description
3.6.2.1. CPU Control Register(Default Value:0x0000_0002)
Offset: 0x0020
Bit
Read/Write
31:9
/

Default/Hex
/

Register Name: CPU_CTRL_REG
Description
/

8

R/W

0x0

7:2

/

/

/

1

R/W

0x1

/

CPU_ID.
CPU ID Option.

CP15_WRITE_DISABLE.
Disable write access to certain CP15 registers.
0

R/W

0x0
0: Enable
1: Disable

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3.7. PWM
3.7.1. Overview
The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable
registers. Each channel has a dedicated internal 16-bit up counter. If the counter reaches the value stored in the
channel period register, it resets. At the beginning of a count period cycle, the PWMOUT is set to activate state and
count from 0x0000.
The PWM divider divides the clock (24 MHz) by 1-4096 according to the pre-scalar bits in the PWM control register.
In PWM cycle mode, the output will be a square waveform; the frequency is set to the period register. In PWM
pulse mode, the output will be a positive pulse or a negative pulse.

3.7.2. PWM Register List
Module Name
PWM

Base Address
0x01C20C00

Register Name

Offset

Description

PWM_CTRL_REG
PWM_CH0_PERIOD_REG
PWM_CH1_PERIOD_REG

0x0200
0x0204
0x0208

PWM Control Register
PWM Channel 0 Period Register
PWM Channel 1 Period Register

3.7.3. PWM Register Description
3.7.3.1. PWM Control Register (Default Value: 0x0000_0000)
Offset: 0x0200
Bit
Read/Write
31:30
/

Default/Hex
/

Register Name: PWM_CTRL_REG
Description
/
PWM1_RDY.
PWM1 period register ready.

29

R/W

0x0
0: PWM1 period register is ready to write
1: PWM1 period register is busy
PWM0_RDY.
PWM0 period register ready.

28

R/W

0x0
0: PWM0 period register is ready to write
1: PWM0 period register is busy

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27:25

/

/

/
PWM1_BYPASS.
PWM CH1 bypass enable.

24

R/W

0x0

If the bit is set to 1, the output of PWM1 is OSC24M.

0: Disable
1: Enable.
PWM_CH1_PULSE_OUT_START.
PWM Channel 1 pulse output start.

0: No effect
23

R/W

0x0

1: Output 1 pulse.

The pulse width should be according to the period 1 register[15:0],
and the pulse state should be according to the active state.
After the pulse is finished, the bit will be cleared automatically.
PWM_CH1_MODE.
PWM Channel 1 mode.
22

R/W

0x0
0: Cycle mode
1: Pulse mode

21

R/W

0x0

PWM_CH1_CLK_GATING
Gating the Special Clock for PWM1(0: mask, 1: pass).
PWM_CH1_ACT_STATE.
PWM Channel 1 Active State.

20

R/W

0x0
0: Low Level
1: High Level
PWM_CH1_EN.
PWM Channel 1 Enable.

19

R/W

0x0
0: Disable
1: Enable

18:15

R/W

0x0

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PWM_CH1_PRESCAL.
PWM Channel 1 Prescaler.

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These bits should be setting before the PWM Channel 1 clock gate on.

0000: /120
0001: /180
0010: /240
0011: /360
0100: /480
0101: /
0110: /
0111: /
1000: /12k
1001: /24k
1010: /36k
1011: /48k
1100: /72k
1101: /
1110: /
1111: /1
14:10

/

/

/
PWM0_BYPASS.
PWM CH0 bypass enable.

9

R/W

0x0

If the bit is set to 1, the output of PWM0 is OSC24M.

0: Disable
1: Enable.
PWM_CH0_PUL_START.
PWM Channel 0 pulse output start.

0: No effect
8

R/W

0x0

1: Output 1 pulse.

The pulse width should be according to the period 0 register [15:0],
and the pulse state should be according to the active state.
After the pulse is finished, the bit will be cleared automatically.
7

R/W

0x0

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PWM_CHANNEL0_MODE.

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0: Cycle mode
1: Pulse mode.
6

R/W

0x0

SCLK_CH0_GATING.
Gating the Special Clock for PWM0 (0: mask, 1: pass).
PWM_CH0_ACT_STA.
PWM Channel 0 Active State.

5

R/W

0x0
0: Low Level
1: High Level.
PWM_CH0_EN.
PWM Channel 0 Enable.

4

R/W

0x0
0: Disable
1: Enable.
PWM_CH0_PRESCAL.
PWM Channel 0 Prescaler.
These bits should be setting before the PWM Channel 0 clock gate on.

0000: /120
0001: /180
0010: /240
0011: /360
0100: /480
3:0

R/W

0x0

0101: /
0110: /
0111: /
1000: /12k
1001: /24k
1010: /36k
1011: /48k
1100: /72k
1101: /
1110: /
1111: /1

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3.7.3.2. PWM Channel 0 Period Register
Offset: 0x0204
Bit
Read/Write

Default/Hex

Register Name: PWM_CH0_PERIOD_REG
Description
PWM_ENT_CYC.
Number of the entire cycles in the PWM clock.

31:16

R/W

UDF

0 : 1 cycle
1 : 2 cycles
……
N : N+1 cycles.
PWM_ACT_CYC.
Number of the active cycles in the PWM clock.

15:0

R/W

UDF

0 : 0 cycle
1 : 1 cycles
……
N : N cycles

Note: The active cycles should be no larger than the period cycles.

3.7.3.3. PWM Channel 1 Period Register
Offset: 0x0208
Bit
Read/Write

Default/Hex

Register Name: PWM_CH1_PERIOD_REG
Description
PWM_ENT_CYC.
Number of the entire cycles in the PWM clock.

31:16

R/W

UDF

0 : 1 cycle
1 : 2 cycles
……
N : N+1 cycles.
PWM_ACT_CYC.
Number of the active cycles in the PWM clock.

15:0

R/W

UDF

0 : 0 cycle
1 : 1 cycles
……

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N : N cycles

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3.8. Asynchronous Timer
3.8.1. Overview
The chip implements 6 async timers.
Timer 0/1/2 can take their inputs from the PLL6/6 or OSC24M. They provide the scheduler interrupt of the
operating system. It is designed to offer maximum accuracy and efficient management, even for systems with a
long or short response time. They provide 32-bit programmable overflow counter and work in auto-reload mode
or no-reload mode.
Timer 3 is used by the OS to generate a periodic interrupt.
The watchdog is used to resume controller operation by generating a general reset or an interrupt request when
it is disturbed by malfunctions such as noise and system errors. It features a down counter that allows a watchdog
period of up to 16 seconds.

3.8.2. ASYNC Timer Register List
Module Name
ASYNC Timer

Base Address
0x01C20C00

Register Name

Offset

Description

ASYNC_TMR_IRQ_EN_REG
ASYNC_TMR_IRQ_STAS_REG
ASYNC_TMR0_CTRL_REG
ASYNC_TMR0_INTV_VALUE_REG
ASYNC_TMR0_CURNT_VALUE_REG
ASYNC_TMR1_CTRL_REG
ASYNC_TMR1_INTV_VALUE_REG
ASYNC_TMR1_CURNT_VALUE_REG
ASYNC_TMR2_CTRL_REG
ASYNC_TMR2_INTV_VALUE_REG
ASYNC_TMR2_CURNT_VALUE_REG
ASYNC_TMR3_CTRL_REG
ASYNC_TMR3_INTV_VALUE_REG
ASYNC_TMR4_CTRL_REG
ASYNC_TMR4_INTV_VALUE_REG
ASYNC_TMR4_CURNT_VALUE_REG
ASYNC_TMR5_CTRL_REG
ASYNC_TMR5_INTV_VALUE_REG
ASYNC_TMR5_CURNT_VALUE_REG
AVS_CNT_CTL_REG
AVS_CNT0_REG

0x0000
0x0004
0x0010
0x0014
0x0018
0x0020
0x0024
0x0028
0x0030
0x0034
0x0038
0x0040
0x0044
0x0050
0x0054
0x0058
0x0060
0x0064
0x0068
0x0080
0x0084

Timer IRQ Enable Register
Timer Status Register
Timer 0 Control Register
Timer 0 Interval Value Register
Timer 0 Current Value Register
Timer 1 Control Register
Timer 1 Interval Value Register
Timer 1 Current Value Register
Timer 2 Control Register
Timer 2 Interval Value Register
Timer 2 Current Value Register
Timer 3 Control Register
Timer 3 Interval Value Register
Timer 4 Control Register
Timer 4 Interval Value Register
Timer 4 Current Value Register
Timer 5 Control Register
Timer 5 Interval Value Register
Timer 5 Current Value Register
AVS Control Register
AVS Counter 0 Register

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AVS_CNT1_REG
AVS_CNT_DIVISOR_REG
WDOG_CTRL_REG
WDOG_MODE_REG
COUNTER64_CTRL_REG
COUNTER64_LOW_REG
COUNTER64_HI_REG
CPU_CFG_REG

0x0088
0x008C
0x0090
0x0094
0x00A0
0x00A4
0x00A8
0x0140

AVS Counter 1 Register
AVS Divisor Register
Watchdog Control Register
Watchdog Mode Register
64-bit Counter Control Register
64-bit Counter Low Register
64-bit Counter High Register
CPU Configuration Register

3.8.3. ASYNC Timer Register Description
3.8.3.1. ASYNC Timer IRQ Enable Register (Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write
31:9
/

Default/Hex
/

Register Name: ASYNC_TMR_IRQ_EN_REG
Description
/
WDOG_INT_EN.
Watchdog Interrupt Enable.

8

R/W

0x0
0: No effect
1: Watchdog Interval Value reached interrupt enable.

7:6

/

/

/
TMR5_INT_EN.
Timer 5 Interrupt Enable.

5

R/W

0x0
0: No effect
1: Timer 5 Interval Value reached interrupt enable.
TMR4_INT_EN.
Timer 4 Interrupt Enable.

4

R/W

0x0
0: No effect
1: Timer 4 Interval Value reached interrupt enable.
TMR3_INT_EN.
Timer 3 Interrupt Enable.

3

R/W

0x0
0: No effect
1: Timer 3 Interval Value reached interrupt enable.

2

R/W

0x0

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TMR2_INT_EN.

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Timer 2 Interrupt Enable.

0: No effect
1: Timer 2 Interval Value reached interrupt enable.
TMR1_INT_EN.
Timer 1 Interrupt Enable.
1

R/W

0x0
0: No effect
1: Timer 1 Interval Value reached interrupt enable.
TMR0_INT_EN.
Timer 0 Interrupt Enable.

0

R/W

0x0
0: No effect
1: Timer 0 Interval Value reached interrupt enable.

3.8.3.2. ASYNC Timer IRQ Status Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write
31:9
/

Default/Hex
/

Register Name: ASYNC_TMR_IRQ_STAS_REG
Description
/
WDOG_IRQ_PEND.
Watchdog IRQ Pending. Setting 1 to the bit will clear it.

8

R/W

0x0
0: No effect
1: Pending, watchdog counter value is reached.

7:6

/

/

/
TMR5_IRQ_PEND.
Timer 5 IRQ Pending. Setting 1 to the bit will clear it.

5

R/W

0x0
0: No effect
1: Pending, timer 5 counter value is reached.
TMR4_IRQ_PEND.
Timer 4 IRQ Pending. Setting 1 to the bit will clear it.

4

R/W

0x0
0: No effect
1: Pending, timer 4 counter value is reached.

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TMR3_IRQ_PEND.
Timer 3 IRQ Pending. Setting 1 to the bit will clear it.
3

R/W

0x0
0: No effect
1: Pending, timer 3 counter value is reached.
TMR2_IRQ_PEND.
Timer 2 IRQ Pending. Setting 1 to the bit will clear it.

2

R/W

0x0
0: No effect
1: Pending, timer 2 counter value is reached.
TMR1_IRQ_PEND.
Timer 1 IRQ Pending. Setting 1 to the bit will clear it.

1

R/W

0x0
0: No effect
1: Pending, timer 1 interval value is reached.
TMR0_IRQ_PEND.
Timer 0 IRQ Pending. Setting 1 to the bit will clear it.

0

R/W

0x0
0: No effect
1: Pending, timer 0 interval value is reached.

3.8.3.3. ASYNC Timer 0 Control Register (Default Value: 0x0000_0004)
Offset: 0x0010
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: ASYNC_TMR0_CTRL_REG
Description
/
TMR0_MODE.
Timer0 mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.
TMR0_CLK_PRES

6:4

R/W

0x0

Select the pre-scale of timer 0 clock source.

000: /1

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001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
TMR0_CLK_SRC.
Timer 0 Clock Source.

3:2

R/W

0x1

00:/
01: OSC24M.
10: PLL6/6
11: /
TMR0_RELOAD.
Timer 0 Reload.

1

R/W

0x0

0: No effect
1: Reload timer 0 Interval value.

After the bit is set, it cannot be written again before it’s cleared
automatically.
TMR0_EN.
Timer 0 Enable.

0: Stop/Pause
1: Start.

0

R/W

0x0

If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcycles, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.

Note: Time between the timer disabled and enabled should be larger than 2*Tcycles (Tcycles= Timer clock
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source/pre-scale).

3.8.3.4. ASYNC Timer 0 Interval Value Register
Offset: 0x0014
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: ASYNC_TMR0_INTV_VALUE_REG
Description
TMR0_INTV_VALUE.
Timer 0 Interval Value.

Note: The value setting should consider the system clock and the timer clock source.

3.8.3.5. ASYNC Timer 0 Current Value Register (Default Value: 0x0000_0000)
Offset: 0x0018
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: ASYNC_TMR0_CURNT_VALUE_REG
Description
TMR0_CUR_VALUE.
Timer 0 Current Value.

Note: Timer 0 current value is a 32-bit down-counter (from interval value to 0). This register can be read correctly
if the PCLK is faster than 2*TimerFreq (TimerFreq = TimerClkSource/pre-scale).

3.8.3.6. ASYNC Timer 1 Control Register (Default Value: 0x0000_0004)
Offset: 0x0020
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: ASYNC_TMR1_CTRL_REG
Description
/
TMR1_MODE.
Timer1 Mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.
TMR1_CLK_PRES.
Select the pre-scale of timer 1 clock source.

6:4

R/W

0x0

000: /1
001: /2
010: /4
011: /8

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System
100: /16
101: /32
110: /64
111: /128
TMR1_CLK_SRC.
Timer 1 Clock Source.

3:2

R/W

0x1

00:/
01: OSC24M.
10: PLL6/6
11: /
TMR1_RELOAD.
Timer 1 Reload.

1

R/W

0x0

0: No effect
1: Reload timer 1 Interval value.

After the bit is set, it cannot be written again before it’s cleared
automatically.
TMR1_EN.
Timer 1 Enable.

0: Stop/Pause
1: Start.

0

R/W

0x0

If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.

Note: Time between the timer disabled and enabled should be larger than 2*Tcycles (Tcycles= Timer clock
source/pre-scale).

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System
3.8.3.7. ASYNC Timer 1 Interval Value Register
Offset: 0x0024
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: ASYNC_TMR1_INTV_VALUE_REG
Description
TMR1_INTV_VALUE.
Timer 1 Interval Value.

Note: The value setting should consider the system clock and the timer clock source.

3.8.3.8. ASYNC Timer 1 Current Value Register
Offset: 0x0028
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: ASYNC_TMR1_CURNT_VALUE_REG
Description
TMR1_CUR_VALUE.
Timer 1 Current Value.

Note: Timer 1 current value is a 32-bit down-counter (from interval value to 0). This register can be read correctly
if the PCLK is faster than 2*TimerFreq (TimerFreq = TimerClkSource/pre-scale).

3.8.3.9. ASYNC Timer 2 Control Register (Default Value: 0x0000_0004)
Offset: 0x0030
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: ASYNC_TMR2_CTRL_REG
Description
/
TMR2_EN.
Timer2 Mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.
TMR2_CLK_PRESCALE.
Select the pre-scale of timer 2 clock source.

000: /1
6:4

R/W

0x0

001: /2
010: /4
011: /8
100: /16
101: /32
110: /64

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System
111: /128
TMR2_CLK_SRC.
Timer 2 Clock Source.
3:2

R/W

0x1

00:/
01: OSC24M.
1x: /.
TMR2_RELOAD.
Timer 2 Reload.

1

R/W

0: No effect

0x0

1: Reload timer 2 Interval value.

After the bit is set, it cannot be written again before it’s cleared
automatically.
TMR2_EN.
Timer 2 Enable.

0: Stop/Pause
1: Start.

0

R/W

If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.

0x0

If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.
Note: Time between the timer disabled and enabled should be larger than 2*Tcycles (Tcycles= Timer clock
source/pre-scale).

3.8.3.10. ASYNC Timer 2 Interval Value Register
Offset: 0x0034
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

GR8 User Manual(Version1.0)

Register Name: ASYNC_TMR2_INTV_VALUE_REG
Description
TMR2_INTV_VALUE.
Timer 2 Interval Value.

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System
Note: The value setting should consider the system clock and the timer clock source.

3.8.3.11. ASYNC Timer 2 Current Value Register
Offset: 0x0038
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: ASYNC_TMR2_CURNT_VALUE_REG
Description
TMR2_CUR_VALUE.
Timer 2 Current Value.

Note: Timer current value is a 32-bit down-counter (from interval value to 0). This register can be read correctly if
the PCLK is faster than 2*TimerFreq (TimerFreq = TimerClkSource/pre-scale).

3.8.3.12. ASYNC Timer 3 Control Register (Default Value: 0x0000_0000)
Offset: 0x0040
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: ASYNC_TMR3_CTRL_REG
Description
/
TMR3_CLK_SRC.
Timer 3 Clock Source.

7

R/W

0x0
0: Internal 32k
1: OSC24M.

6:5

/

/

/
TMR3_MODE.
Timer 3 Mode.

4

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.
TMR3_CLK_PRESCALE.
Select the pre-scale of timer 3 clock source.

3:2

R/W

0x0

00: /16
01: /32
10: /64
11: /1

1

/

/

/

0

R/W

0x0

TMR3_EN.

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Timer 3 Enable.

0: Disable
1: Enable.
Note: The time between the timer disabled and enabled should be larger than 2*Tcycles (Tcycles= Timer clock
source/pre-scale).

3.8.3.13. ASYNC Timer 3 Interval Value
Offset: 0x0044
Read/Write
Bit
31:0

R/W

Default/Hex

Register Name: ASYNC_TMR3_INTV_VALUE_REG
Description
TMR3_INTV_VALUE.

UDF

Timer 3 Interval Value.

3.8.3.14. ASYNC Timer 4 Control Register (Default Value: 0x0000_0004)
Offset: 0x0050
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: ASYNC_TMR4_CTRL_REG
Description
/
TMR4_MODE.
Timer4 Mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.
TMR4_CLK_PRESCALE.
Select the pre-scale of timer 4 clock source.

000: /1
001: /2
6:4

R/W

0x0

010: /4
011: /8
100: /16
101: /32
110: /64
111: /128

3:2

R/W

0x1

GR8 User Manual(Version1.0)

TMR4_CLK_SRC.

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System
Timer 4 Clock Source.

00: /
01: OSC24M.
10: External CLKIN0
11: /.
TMR4_RELOAD.
Timer 4 Reload.

1

R/W

0: No effect

0x0

1: Reload timer 0 Interval value.

After the bit is set, it cannot be written again before it’s cleared
automatically.
TMR4_EN.
Timer 4 Enable.

0: Stop/Pause
1: Start.

0

R/W

If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.

0x0

If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.
Note:
If the clock source is External CLKIN, the interval value register is not used, the current value register is an up
counter that counts from 0.
The time between the timer disabled and enabled should be larger than 2*Tcycles (Tcycles= Timer clock
source/pre-scale).

3.8.3.15. ASYNC Timer 4 Interval Value Register
Offset: 0x0054
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: ASYNC_TMR4_INTV_VALUE_REG
Description

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Page 103

System

31:0

R/W

TMR4_INTV_VALUE.

UDF

Timer 4 Interval Value.

Note: The value setting should consider the system clock and the timer clock source.

3.8.3.16. ASYNC Timer 4 Current Value Register
Offset: 0x0058
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: ASYNC_TMR4_CURNT_VALUE_REG
Description
TMR4_CUR_VALUE.
Timer 4 Current Value.

Note:
Timer current value is a 32-bit down-counter (from interval value to 0). This register can be read correctly if the
PCLK is faster than 2*TimerFreq (TimerFreq = TimerClkSource/pre-scale).
Before the timer 4 is enabled, its current value register needs to be written with zero.

3.8.3.17. ASYNC Timer 5 Control Register (Default Value: 0x0000_0004)
Offset: 0x0060
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: ASYNC_TMR5_CTRL_REG
Description
/
TMR5_MODE.
Timer5 Mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.
TMR5_CLK_PRESCALE.
Select the pre-scale of timer 5 clock source.

000: /1
001: /2
6:4

R/W

0x0

010: /4
011: /8
100: /16
101: /32
110: /64
111: /128

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System
TMR5_CLK_SRC.
Timer 5 Clock Source.

3:2

R/W

0x1

00: /
01: OSC24M.
10: External CLKIN1
11: /.
TMR5_RELOAD.
Timer 5 Reload.

1

R/W

0x0

0: No effect
1: Reload timer 0 Interval value.

After the bit is set, it cannot be written again before it is cleared
automatically.
TMR5_EN.
Timer 5 Enable.

0: Stop/Pause
1: Start.

0

R/W

0x0

If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.

Note:
If the clock source is External CLKIN, the interval value register is not used, the current value register is an up
counter that counting from 0.
The time between the timer disabled and enabled should be larger than 2*Tcycles (Tcycles= Timer clock
source/pre-scale).

3.8.3.18. ASYNC Timer 5 Interval Value Register
Offset: 0x0064
GR8 User Manual(Version1.0)

Register Name: ASYNC_TMR5_INTV_VALUE_REG
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Page 105

System
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

Description
TMR5_INTV_VALUE.
Timer 5 Interval Value.

Note: The value setting should consider the system clock and the timer clock source.

3.8.3.19. ASYNC Timer 5 Current Value Register
Offset: 0x0068
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: ASYNC_TMR5_CURNT_VALUE_REG
Description
TMR5_CUR_VALUE.
Timer 5 Current Value.

Note:
Timer 1 current value is a 32-bit down-counter (from interval value to 0). This register can be read correctly if the
PCLK is faster than 2*TimerFreq (TimerFreq = TimerClkSource/pre-scale).
Before timer 5 is enabled, its current value register needs to be written with zero.

3.8.3.20. AVS Counter Control Register (Default Value: 0x0000_0000)
Offset: 0x0080
Bit
31:10

Read/Write
/

Register Name: AVS_CNT_CTL_REG
Default/Hex
/

Description
/
AVS_CNT1_PS
Audio/Video Sync Counter 1 Pause Control

9

R

0x0
0: Not pause
1: Pause Counter 1
AVS_CNT0_PS
Audio/Video Sync Counter 0 Pause Control

8

R/W

0x0
0: Not pause
1: Pause Counter 0

7:2

/

/

/
AVS_CNT1_EN

1

R/W

0x0

Audio/Video Sync Counter 1 Enable/ Disable. The counter source is
OSC24M.

0: Disable

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1: Enable
AVS_CNT0_EN
Audio/Video Sync Counter 1 Enable/ Disable. The counter source is
OSC24M.
0

R/W

0x0
0: Disable
1: Enable

3.8.3.21. AVS Counter 0 Register (Default Value: 0x0000_0000)
Offset: 0x0084
Bit

Read/Write

Register Name: AVS_CNT0_REG
Default/Hex

Description
AVS_CNT0
Counter 0 for Audio/ Video Sync Application

31:0

R/W

The high 32 bits of the internal 33-bit 90 kHz counter register. The
initial value of the internal 33-bit counter register can be set by
software. The LSB bit of the 33-bit counter register should be zero
when the initial value is updated. It will count from the initial value.
The initial value can be updated at any time. It can also be paused by
setting AVS_CNT0_PS to ‘1’. When it is paused, the counter won’t
increase.

0x0

3.8.3.22. AVS Counter 1 Register (Default Value: 0x0000_0000)
Offset: 0x0088
Bit
Read/Write

Default/Hex

Register Name: AVS_CNT1_REG
Description
AVS_CNT1
Counter 1 for Audio/ Video Sync Application

31:0

R/W

The high 32 bits of the internal 33-bit 90kHz counter register. The
initial value of the internal 33-bit counter register can be set by
software. The LSB bit of the 33-bit counter register should be zero
when the initial value is updated. It will count from the initial value.
The initial value can be updated at any time. It can also be paused by
setting AVS_CNT1_PS to ‘1’. When it is paused, the counter won’t
increase.

0x0

3.8.3.23. AVS Counter Divisor Register (Default Value: 0x05DB_05DB)
Offset: 0x008C
Bit
31:28

Read/Write
/

Register Name: AVS_CNT_DIVISOR_REG
Default/Hex
/

GR8 User Manual(Version1.0)

Description
/

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System
AVS_CNT1_D
Divisor N for AVS Counter1
The number N is from 1 to 0x7ff. The zero value is reserved.
27:16

R/W

The internal 33-bit counter engine will maintain another 12-bit
counter. The 12-bit counter is used for counting the cycle number of
one 24 MHz clock. When the 12-bit counter reaches (>= N) the divisor
value, the internal 33-bit counter register will increase 1 and the 12bit counter will reset to zero and restart again.

0x5DB

Note: It can be configured by software at any time.
15:12

/

/

/
AVS_CNT0_D
Divisor N for AVS Counter0
The number N is from 1 to 0x7ff. The zero value is reserved.

11:0

R/W

The internal 33-bit counter engine will maintain another 12-bit
counter. The 12-bit counter is used for counting the cycle number of
one 24MHz clock. When the 12-bit counter reaches (>= N) the divisor
value, the internal 33-bit counter register will increase 1 and the 12bit counter will reset to zero and restart again.

0x5DB

Note: It can be configured by software at any time.

3.8.3.24. Watchdog Control Register
Offset: 0x0090
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: WDOG_CTRL_REG
Description
/

12:1

0x333

KEY_FIELD.

R/W

WDOG_RESTART.
Watchdog Restart.
0

R/W

UDF
0: No effect
1: Restart the Watchdog.

3.8.3.25. Watchdog Mode Register (Default Value: 0x0000_0000)
Offset: 0x0094
Bit
Read/Write

Default/Hex

31

0x0

R/W

Register Name: WDOG_MODE_REG
Description
WDOG_TEST_MODE.

0: Normal mode

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System
1: Test mode.
30:7

/

/

/
WDOG_INTV_VALUE.
Watchdog Interval Value
Watchdog clock source is OSC24M. If the OSC24M is turned off, the
watchdog will not work.

0000: 0.5sec
0001: 1sec
0010: 2sec
0011: 3sec
0100: 4sec
6:3

R/W

0x0

0101: 5sec
0110: 6sec
0111: 8sec
1000: 10sec
1001: 12sec
1010: 14sec
1011: 16sec
1100: /
1101: /
1110: /
1111: /

2

/

/

/
WDOG_RST_EN.
Watchdog Reset Enable.

1

R/W

0x0
0: No effect on the resets,
1: Enables the Watchdog to activate the system reset.
WDOG_EN.
Watchdog Enable.

0

R/W

0x0
0: No effect
1: Enable the Watchdog.

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System
3.8.3.26. 64-bit Counter Low Register (Default Value: 0x0000_0000)
Offset: 0x00A4
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: COUNTER64_LOW_REG
Description
CONT64_LO.
64-bit Counter [31:0].

3.8.3.27. 64-bit Counter High Register (Default Value: 0x0000_0000)
Offset: 0x00A8
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: COUNTER64_HI_REG
Description
CONT64_HI.
64-bit Counter [63:32].

3.8.3.28. 64-bit Counter Control Register (Default Value: 0x0000_0000)
Offset: 0x00A0
Bit
Read/Write
31:3
/

Default/Hex
/

Register Name: COUNTER64_CTRL_REG
Description
/
CONT64_CLK_SRC_SEL.
64-bit Counter Clock Source Select.

2

R/W

0x0
0: OSC24M
1: PLL6/6
CONT64_RLATCH_EN.
64-bit Counter Read Latch Enable.

1

R/W

0x0
0: No effect
1: To latch the 64-bit Counter to the Low/Hi registers and it will change
to zero after the registers are latched.
CONT64_CLR_EN.
64-bit Counter Clear Enable.

0

R/W

0x0
0: No effect
1: To clear the 64-bit Counter Low/Hi registers and it will change to
zero after the registers are cleared.

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System
3.8.3.29. CPU Config Register (Default Value: 0x0000_0000)
Offset: 0x013C
Bit
Read/Write
31:2
/

Default/Hex
/

Register Name: CPU_CFG_REG
Description
/
L1_INVALID_RST_EN.
Enable L1 data cache invalidation at reset.

1

R/W

0x0

For L1 data cache, the cycles are up to 512 CPU clock cycles

0: Enable
1: Disable
L2_INVALID_RST_EN.
Enable L2 data cache invalidation at reset.
0

R/W

0x0

For L1 data cache, the cycles are up to 1024 CPU clock cycles

0: Enable
1: Disable
Note: The bit [1:0] can be set to 0 by software.

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System

3.9. Synchronic Timer
3.9.1. Overview
The chip implements 2 sync timers providing a high-speed counter.

3.9.2. Sync Timer Register List
Module Name
Sync Timer

Base Address
0x01C60000

Register Name

Offset

Description

SYNC_TMR_IRQ_EN_REG
SYNC_TMR_IRQ_STAS_REG
SYNC_TMR0_CTRL_REG
SYNC_TMR0_INTV_LO_REG
SYNC_TMR0_INTV_HI_REG
SYNC_TMR0_CURNT_LO_REG
SYNC_TMR0_CURNT_HI_REG
SYNC_TMR1_CTRL_REG
SYNC_TMR1_INTV_LO_REG
SYNC_TMR1_INTV_HI_REG
SYNC_TMR1_CURNT_LO_REG
SYNC_TMR1_CURNT_HI_REG

0x0000
0x0004
0x0010
0x0014
0x0018
0x001C
0x0020
0x0030
0x0034
0x0038
0x003C
0x0040

Timer IRQ Enable Register
Timer Status Register
Timer 0 Control Register
Timer 0 Interval Value Low Register
Timer 0 Interval Value High Register
Timer 0 Current Value Low Register
Timer 0 Current Value High Register
Timer 1 Control Register
Timer 1 Interval Value Low Register
Timer 1 Interval Value High Register
Timer 1 Current Value Low Register
Timer 1 Current Value High Register

3.9.3. Sync Timer Register Description
3.9.3.1. Sync Timer IRQ Enable Register (Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write
31:2
/

Default/Hex
/

Register Name: SYNC_TMR_IRQ_EN_REG
Description
/
STMR1_INT_EN.
Sync Timer 1 Interrupt Enable.

1

R/W

0x0
0: No effect
1: Timer 1 Interval Value reached interrupt enable.
STMR0_INT_EN.

0

R/W

0x0

GR8 User Manual(Version1.0)

Sync Timer 0 Interrupt Enable.

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System
0: No effect
1: Timer 0 Interval Value reached interrupt enable.

3.9.3.2. Sync Timer IRQ Status Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write
31:2
/

Default/Hex
/

Register Name: SYNC_TMR_IRQ_STAS_REG
Description
/
STMR1_IRQ_PEND.
Sync Timer 1 IRQ Pending. Setting 1 to the bit will clear it.

1

R/W

0x0
0: No effect
1: Pending, timer 1 interval value is reached.
STMR0_IRQ_PEND.
Sync Timer 0 IRQ Pending. Setting 1 to the bit will clear it.

0

R/W

0x0
0: No effect
1: Pending, timer 0 interval value is reached.

3.9.3.3. Sync Timer 0 Control Register (Default Value: 0x0000_0004)
Offset: 0x0010
Bit
Read/Write

31

R/W

Default/Hex

0x0

Register Name: SYNC_TMR0_CTRL_REG
Description
SYNC_TMR0_TEST.
Sync timer0 test mode. In test mode, the low register should be set
to 0x1, the high register will down count. The counter needs to be
reloaded.

0: Normal mode
1: Test mode.
30:8

/

/

/
STMR0_MODE.
Sync Timer0 mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.

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System
The clock source of Timer 0 is fixed to AHBCLK.
STMR0_CLK_
Select the pre-scale of the sync timer 0 clock source.

000: /1
001: /2
6:4

R/W

0x0

010: /4
011: /8
100: /16
101: /
110: /
111: /

3:2

/

/

/
STMR0_RELOAD.
Sync Timer 0 Reload.

1

R/W

0x0
0: No effect
1: Reload timer 0 Interval value.
STMR0_EN.
Sync Timer 0 Enable.

0: Stop/Pause
1: Start.

0

R/W

If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.

0x0

If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.

3.9.3.4. Sync Timer 0 Interval Value Low Register
Offset: 0x0014
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: SYNC_TMR0_INTV_LO_REG
Description

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STMR0_INTV_VALUE_LO.
31:0

R/W

UDF

Sync Timer 0 Interval Value [31:0].

3.9.3.5. Sync Timer 0 Interval Value High Register
Offset: 0x0018
Bit
Read/Write
31:24
/

Default/Hex
/

23:0

UDF

R/W

Register Name: SYNC_TMR0_INTV_HI_REG
Description
/
STMR0_INTV_VALUE_HI.
Sync Timer 0 Interval Value [55:32].

Note: The interval value register is a 56-bit register. When read or write the interval value, the Low register should
be read or written first. And the High register should be written after the Low register.

3.9.3.6. Sync Timer 0 Current Value Lo Register
Offset: 0x001C
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: SYNC_TMR0_CURNT_LOW_REG
Description
STMR0_CUR_VALUE_LOW.
Sync Timer 0 Current Value [31:0].

3.9.3.7. Sync Timer 0 Current Value Hi Register
Offset: 0x0020
Bit
Read/Write
31:24
/

Default/Hex
/

23:0

UDF

R/W

Register Name: SYNC_TMR0_CURNT_HI_REG
Description
/
STMR0_CUR_VALUE_HI.
Sync Timer 0 Current Value [55:32].

Note:
Timer 0 current value is a 56-bit down-counter (from interval value to 0).
The current value register is a 56-bit register. When read or write the current value, the Low register should be
read or written firstly.

3.9.3.8. Sync Timer 1 Control Register (Default Value: 0x0000_0004)
Offset: 0x0030
Bit
Read/Write

Default/Hex

Register Name: SYNC_TMR1_CTRL_REG
Description
SYNC_TMR1_TEST.

31

0x0

Sync Timer1 Test Mode.

R/W

In test mode, the low register should be set to 0x1, the high register

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will down count. The counter needs to be reloaded.

0: Normal mode
1: Test mode.
30:8

/

/

/
STMR1_MODE.
Sync Timer1 Mode.

7

R/W

0x0

0: Continuous mode. When reaches the internal value, the timer will
not be disabled automatically.
1: Single mode. When reaches the internal value, the timer will be
disabled automatically.

Sync Timer 1 Clock Source is fixed to AHBCLK.
STMR1_CLK_SRC.
Select the pre-scale of the sync timer 1 clock source.

000: /1
001: /2
6:4

R/W

0x0

010: /4
011: /8
100: /16
101: /
110: /
111: /

3:2

/

/

/
STMR1_RELOAD.
Sync Timer 1 Reload.

1

R/W

0x0
0: No effect
1: Reload timer 1 Interval value.
STMR1_EN.
Sync Timer 1 Enable.

0

R/W

0x0
0: Stop/Pause
1: Start.

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If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit
is set to “0”; the current value counter will pause. At least wait for 2
Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If
the timer is started again, and the Software hope the current value
register to down-count from the new interval value, the reload bit
and the enable bit should be set to 1 at the same time.

3.9.3.9. Sync Timer 1 Interval Value Low Register
Offset: 0x0034
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: SYNC_TMR1_INTV_LOW_REG
Description
STMR1_INTV_VALUE_LOW.
Sync Timer 1 Interval Value [31:0].

3.9.3.10. Sync Timer 1 Interval Value High Register
Offset: 0x0038
Bit
Read/Write
31:24
/

Default/Hex
/

23:0

UDF

R/W

Register Name: SYNC_TMR1_INTV_HI_REG
Description
/
STMR1_INTV_VALUE_HI.
Sync Timer 1 Interval Value [55:32].

Note: The interval value register is a 56-bit register. When read or write the interval value, the Low register should
be read or written firstly. And the High register should be written after the Low register.

3.9.3.11. Sync Timer 1 Current Value Low Register
Offset: 0x003C
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: SYNC_TMR1_CURNT_LOW_REG
Description
STMR1_CUR_VALUE_LOW.
Sync Timer 1 Current Value [31:0].

3.9.3.12. Sync Timer 1 Current Value High Register
Offset: 0x0040
Bit
Read/Write
31:24
/
23:0

R/W

Default/Hex
/
UDF

GR8 User Manual(Version1.0)

Register Name: SYNC_TMR1_CURNT_HI_REG
Description
/
STMR1_CUR_VALUE_HI.

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Sync Timer 1 Current Value [55:32].
Note: Timer 0 current value is a 56-bit down-counter (from interval value to 0). The current value register is a 56bit register. When read or write the current value, the Low register should be read or written firstly.

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3.10. Interrupt Controller
3.10.1. Overview
The interrupt controller features:
●

Controls the nIRQ and FIQ of a RISC Processor

●

Supports 96 interrupt sources

●

4-Level priority controller

●

External sources of Edge-sensitive or Level-sensitive

The 4-level Priority Controller allows users to define the priority of each interrupt source, so higher priority
interrupts can be serviced even if a lower priority interrupt is being treated.

3.10.2. Interrupt Source
The interrupt source 0 is always located at FIQ. The interrupt sources 1 to 83 are located at System Interrupt and
user peripheral.
Interrupt Source

SRC

Vector

FIQ

Description

External NMI

0

0x0000

YES

External Non-Mask Interrupt.

UART 0

1

0x0004

UART 0 interrupt

UART 1

2

0x0008

UART 1 interrupt

UART 2

3

0x000C

UART 2 interrupt

UART 3

4

0x0010

UART 3 interrupt

IR

5

0x0014

IR 0 interrupt

/

6

0x0018

/

TWI 0

7

0x001C

TWI 0 interrupt

TWI 1

8

0x0020

TWI 1 interrupt

TWI 2

9

0x0024

TWI 2 interrupt

SPI 0

10

0x0028

SPI 0 interrupt

/

11

0x002C

/

SPI 2

12

0x0030

SPI 2 interrupt

/

13

0x0034

/

/

14

0x0038

/

/

15

0x003C

/

/

16

0x0040

/

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Interrupt Source

SRC

Vector

/

17

0x0044

/

/

18

0x0048

/

/

19

0x004C

/

/

20

0x0050

/

/

21

0x0054

/

Timer 0

22

0x0058

Timer 0 interrupt

Timer 1

23

0x005C

Timer 1 interrupt

Timer 2/Alarm/WD

24

0x0060

Timer 2, Alarm, Watchdog

Timer 3

25

0x0064

Timer 3 interrupt

/

26

0x0068

/

DMA

27

0x006C

DMA channel interrupt

PIO

28

0x0070

PIO interrupt

Touch Panel

29

0x0074

Touch Panel interrupt.

Audio Codec

30

0x0078

Analog Audio Codec interrupt

LRADC

31

0x007C

LRADC interrupt

SD/MMC 0

32

0x0080

SD/MMC Host Controller 0 interrupt

SD/MMC 1

33

0x0084

SD/MMC Host Controller 1 interrupt

SD/MMC 2

34

0x0088

SD/MMC Host Controller 2 interrupt

/

35

0x008C

/

/

36

0x0090

/

NAND

37

0x0094

NAND Flash Controller (NFC) interrupt

USB-OTG

38

0x0098

USB OTG wakeup, connect, disconnect interrupt

USB-EHCI

39

0x009C

USB EHCI wakeup, connect, disconnect interrupt

USB-OHCI

40

0x00A0

USB OHCI wakeup, connect, disconnect interrupt

/

41

0x00A4

/

CSI

42

0x00A8

CSI interrupt

/

43

0x00AC

/

LCD Controller

44

0x00B0

LCD Controller interrupt

/

45

0x00B4

/

/

46

0x00B8

/

DE-FE/DE-BE

47

0x00BC

DE-FE/DE-BE interrupt

/

48

0x00C0

/

PMU

49

0x00C4

PMU interrupt

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FIQ

Description

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Interrupt Source

SRC

Vector

FIQ

Description

/

50

0x00C8

/

/

51

0x00CC

/

/

52

0x00D0

/

VE

53

0x00D4

VE interrupt

CE

54

0x00D8

Crypto Engine interrupt

/

55

0x00DC

/

/

56

0x00E0

/

/

57

0x00E4

/

/

58

0x00E8

/

/

59

0x00EC

/

/

60

0x00F0

/

/

61

0x00F4

/

/

62

0x00F8

/

/

63

0x00FC

/

/

64

0x100

/

/

65

0x104

/
PLE on non-secure transfers interrupt

PLE/PERFMU

66

0x108

PLE on secure transfer interrupt
PLE error interrupt
Performance monitor interrupt

Timer 4

67

0x010C

Timer 4 interrupt

Timer 5

68

0x0110

Timer 5 interrupt

GPU-GP

69

0x0114

GPU-GPMMU

70

0x0118

GPU-PP0

71

0x011C

GPU-PPMMU0

72

0x0120

GPU-PMU

73

0x0124

GPU-RSV0

74

0x0128

GPU-RSV1

75

0x012C

GPU-RSV2

76

0x0130

GPU-RSV3

77

0x0134

GPU-RSV4

78

0x0138

GPU-RSV5

79

0x013C

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Interrupt Source

SRC

Vector

GPU-RSV6

80

0x0140

/

81

0x0144

Sync timer 0

82

0x0148

Sync timer 1

83

0x014C

FIQ

Description

3.10.3. Interrupt Register List
Module Name
INTC

Base Address
0x01C20400

Register Name

Offset

Description

INTC_VECTOR_REG
INTC_BASE_ADDR_REG
INC_PROTEC_REG
INTC_NMIl_CTRL_REG
INTC_IRQ_PEND_REG0
INTC_IRQ_PEND_REG1
INTC_IRQ_PEND_REG2
/
INTC_FIQ_PEND_REG0
INTC_FIQ_PEND_REG1
INTC_FIQ_PEND_REG2
/
INTC_SEL_REG0
INTC_SEL_REG1
INTC_SEL_REG2
/
INTC_EN_REG0
INTC_EN_REG1
INTC_EN_REG2
/
INTC_MASK_REG0
INTC_MASK_REG1
INTC_MASK_REG2
/
INTC_RESP_REG0
INTC_RESP_REG1
INTC_RESP_REG2
/
INTC_FORCE_REG0

0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
0x006C
0x0070

Interrupt Vector
Interrupt Base Address
Interrupt Protection
Interrupt Control
Interrupt IRQ Pending 0 Status
Interrupt IRQ Pending 1 Status
Interrupt IRQ Pending 2 Status
/
Interrupt FIQ Pending 0 Status
Interrupt FIQ Pending 1 Status
Interrupt FIQ Pending 2 Status
/
Interrupt Select 0
Interrupt Select 1
Interrupt Select 2
/
Interrupt Enable 0
Interrupt Enable 1
Interrupt Enable 2
/
Interrupt Mask 0
Interrupt Mask 1
Interrupt Mask 2
/
Interrupt Response 0
Interrupt Response 1
Interrupt Response 2
/
Interrupt Fast Forcing 0

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INTC_FORCE_REG1
INTC_FORCE_REG2
/
INTC_SRC_PRIO_REG0
INTC_SRC_PRIO_REG1
INTC_SRC_PRIO_REG2
INTC_SRC_PRIO_REG3
INTC_SRC_PRIO_REG4
INTC_SRC_PRIO_REG5

0x0074
0x0078
0x007C
0x0080
0x0084
0x0088
0x008C
0x0090
0x0094

Interrupt Fast Forcing 1
Interrupt Fast Forcing 2
/
Interrupt Source Priority 0
Interrupt Source Priority 1
Interrupt Source Priority 2
Interrupt Source Priority 3
Interrupt Source Priority 4
Interrupt Source Priority 5

3.10.4. Interrupt Register Description
3.10.4.1. Interrupt Vector Register (Default Value: 0x0000_0000)
Offset:0x0000
Bit
Read/Write

Default/Hex

31:2

R

0x0

1:0

R

0x0

Register Name: INTC_VECTOR_REG
Description
VECTOR_ADDR.
This register presents the vector address for the interrupt currently
active on the CPU IRQ input.
ZERO.
Always return zero to this field.

3.10.4.2. Interrupt Base Address Register (Default Value: 0x0000_0000)
Offset:0x0004
Bit
Read/Write

Default/Hex

31:2

R/W

0x0

1:0

R

0x0

Register Name: INTC_BASE_ADDR_REG
Description
BASE_ADDR.
This bit-field holds the upper 30 bits of the base address of the vector
table.
ZERO.
Always return zero to this field.

3.10.4.3. Interrupt Protection Register (Default Value: 0x0000_0000)
Offset:0x0008
Bit
Read/Write

Default/Hex

Register Name: INC_PROTEC_REG
Description

31:1

/

/

/

PROTECT_EN.
0

R/W

0x0

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Enables or disables protected register access

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0: Disable protection mode
1: Enable protection mode

If enabled, only privileged mode access can access the interrupt
controller registers.
If disabled, both user mode and privileged mode can access the
registers.
This register can only be accessed in privileged mode.

3.10.4.4. NMI Interrupt Control Register (Default Value: 0x0000_0000)
Offset:0x000C
Bit
Read/Write
31:2
/

Default/Hex
/

Register Name: INTC_NMIl_CTRL_REG
Description
/
NMI_SRC_TYPE.
External NMI Interrupt Source Type.

1:0

R/W

0x0

00 : Low level sensitive
01 : Negative edge trigged
10 : High level sensitive
11 : Positive edge sensitive

3.10.4.5. Interrupt IRQ Pending Register 0(Default Value: 0x0000_0000)
Offset:0x0010
Bit
Read/Write

Default/Hex

Register Name: INTC_IRQ_PEND_REG0
Description
INT_IRQ_SRC_PEND0.
Interrupt IRQ Source [31:0] Pending/Clear Bit.

31:0

R

0x0
0: Corresponding interrupt is not pending.
1: Corresponding interrupt is pending

3.10.4.6. Interrupt IRQ Pending Register 1(Default Value: 0x0000_0000)
Offset:0x0014
Bit
Read/Write

Default/Hex

31:0

0x0

R

GR8 User Manual(Version1.0)

Register Name: INTC_PEND_REG1
Description
INT_IRQ_SRC_PEND1.
Interrupt IRQ Source [63:32] Pending/Clear Bit.

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0: Corresponding interrupt is not pending.
1: Corresponding interrupt is pending

3.10.4.7. Interrupt IRQ Pending Register 2(Default Value: 0x0000_0000)
Offset:0x0018
Bit
Read/Write

Default/Hex

Register Name: INTC_PEND_REG2
Description
INT_IRQ_SRC_PEND2.
Interrupt IRQ Source [95:64] Pending/Clear Bit.

31:0

R

0x0
0: Corresponding interrupt is not pending.
1: Corresponding interrupt is pending

3.10.4.8. Interrupt FIQ Pending/Clear Register 0 (Default Value: 0x0000_0000)
Offset:0x0020
Bit
Read/Write

Default/Hex

Register Name: INTC_FIQ_PEND_REG0
Description
INT_FIQ_SRC_PEND0.
Interrupt FIQ Source [31:0] Pending/Clear Bit.

31:0

R

0x0
0: Corresponding interrupt is not pending.
1: Corresponding interrupt is pending

3.10.4.9. Interrupt FIQ Pending/Clear Register 1(Default Value: 0x0000_0000)
Offset:0x0024
Bit
Read/Write

Default/Hex

Register Name: INTC_FIQ_PEND_REG1
Description
INT_FIQ_SRC_PEND1.
Interrupt Source [63:32] Pending/Clear Bit.

31:0

R

0x0
0: Corresponding interrupt is not pending.
1: Corresponding interrupt is pending

3.10.4.10. Interrupt FIQ Pending/Clear Register 2(Default Value: 0x0000_0000)
Offset:0x0028
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: INTC_FIQ_PEND_REG2
Description

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INT_FIQ_SRC_PEND2.
Interrupt Source [95:64] Pending/Clear Bit.
31:0

R

0x0
0: Corresponding interrupt is not pending.
1: Corresponding interrupt is pending

3.10.4.11. Interrupt Select Register 0(Default Value: 0x0000_0000)
Offset:0x0030
Bit
Read/Write

Default/Hex

Register Name: INTC_SEL_REG0
Description
INT_SRC_TYPE0
Interrupt Source [31:0] IRQ Type Select.

31:0

R/W

0x0
0: IRQ.
1: FIQ

3.10.4.12. Interrupt Select Register 1(Default Value: 0x0000_0000)
Offset:0x0034
Bit
Read/Write

Default/Hex

Register Name: INTC_SEL_REG1
Description
INT_SRC_TYPE1.
Interrupt Source [63:32] IRQ Type Select.

31:0

R/W

0x0
0: IRQ.
1: FIQ

3.10.4.13. Interrupt Select Register 2(Default Value: 0x0000_0000)
Offset:0x0038
Bit
Read/Write

Default/Hex

Register Name: INTC_SEL_REG2
Description
INT_SRC_TYPE2.
Interrupt Source [95:64] IRQ Type Select.

31:0

R/W

0x0
0: IRQ.
1: FIQ

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3.10.4.14. Interrupt Enable Register 0(Default Value: 0x0000_0000)
Offset:0x0040
Bit
Read/Write

Default/Hex

Register Name: INTC_EN_REG0
Description
INT_SRC_EN0.
Interrupt Source [31:0] Enable Bits.

31:0

R/W

0x0
0: Corresponding interrupt is disabled.
1: Corresponding interrupt is enabled.

3.10.4.15. Interrupt Enable Register 1(Default Value: 0x0000_0000)
Offset:0x0044
Bit
Read/Write

Default/Hex

Register Name: INTC_EN_REG1
Description
INT_SRC_EN1.
Interrupt Source [63:32] Enable Bits.

31:0

R/W

0x0
0: Corresponding interrupt is disabled.
1: Corresponding interrupt is enabled.

3.10.4.16. Interrupt Enable Register 2(Default Value: 0x0000_0000)
Offset:0x0048
Bit
Read/Write

Default/Hex

Register Name: INTC_EN_REG2
Description
INT_SRC_EN2.
Interrupt Source [95:64] Enable Bits.

31:0

R/W

0x0
0: Corresponding interrupt is disabled.
1: Corresponding interrupt is enabled.

3.10.4.17. Interrupt Mask Register 0(Default Value: 0x0000_0000)
Offset:0x0050
Bit
Read/Write

Default/Hex

Register Name: INTC_MASK_REG0
Description
INT_MASK0.
Interrupt Source [31:0] Mask Bits.

31:0

R/W

0x0
0: No effect.
1: interrupt is masked.

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If interrupt is enabled and the interrupt occurred, the interrupt
pending bit will be set whether the corresponding interrupt mask bit
is set.

3.10.4.18. Interrupt Mask Register 1(Default Value: 0x0000_0000)
Offset:0x0054
Bit
Read/Write

Default/Hex

Register Name: INTC_MASK_REG1
Description
INT_MASK1.
Interrupt Source [63:32] Mask Bits.

0: No effect.
31:0

R/W

0x0

1: interrupt is masked.

If interrupt is enabled and the interrupt occurred, the interrupt
pending bit will be set whether the corresponding interrupt mask bit
is set.

3.10.4.19. Interrupt Mask Register 2(Default Value: 0x0000_0000)
Offset:0x0058
Bit
Read/Write

Default/Hex

Register Name: INTC_MASK_REG2
Description
INT_MASK2.
Interrupt Source [95:64] Mask Bits.

0: No effect.
31:0

R/W

0x0

1: interrupt is masked.

If interrupt is enabled and the interrupt occurred, the interrupt
pending bit will be set whether the corresponding interrupt mask bit
is set.

3.10.4.20. Interrupt Response Register 0(Default Value: 0x0000_0000)
Offset:0x0060
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

GR8 User Manual(Version1.0)

Register Name: INTC_RESP_REG0
Description
INT_RESP0.
Interrupt Source [31:0] Response Bit.

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System
If the corresponding bit is set, the interrupt with the lower or the same
priority level is masked.

3.10.4.21. Interrupt Response Register 1(Default Value: 0x0000_0000)
Offset:0x0064
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: INTC_RESP_REG1
Description
INT_RESP1.
Interrupt Source [63:32] Response Bit.
If the corresponding bit is set, the interrupt with the lower or the same
priority level is masked.

3.10.4.22. Interrupt Response Register 2(Default Value: 0x0000_0000)
Offset:0x0068
Bit
Read/Write

Default/Hex

Register Name: INTC_RESP_REG2
Description
INT_RESP2.

31:0

R/W

Interrupt Source [95:64] Response Bit.

0x0

If the corresponding bit is set, the interrupt with the lower or the same
priority level is masked.

3.10.4.23. Interrupt Fast Forcing Register 0(Default Value: 0x0000_0000)
Offset:0x0070
Bit
Read/Write

Default/Hex

Register Name: INTC_FORCE_REG0
Description
INT_FF0
Enables the fast forcing feature on the corresponding interrupt source
[31:0].

31:0

W

0x0

0: No effect.
1: Forcing the corresponding interrupt.

Setting this bit can be valid only when the corresponding interrupt
enable bit is set.

3.10.4.24. Interrupt Fast Forcing Register 1(Default Value: 0x0000_0000)
Offset:0x0074
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: INTC_FORCE_REG1
Description

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System
INT_FF1.
Enables the fast forcing feature on the corresponding interrupt source
[63:32].

31:0

W

0x0

0: No effect.
1: Forcing the corresponding interrupt.

Setting this bit can be valid only when the corresponding interrupt
enable bit is set.

3.10.4.25. Interrupt Fast Forcing Register 2(Default Value: 0x0000_0000)
Offset:0x0078
Bit
Read/Write

Default/Hex

Register Name: INTC_FORCE_REG2
Description
INT_FF2.
Enables the fast forcing feature on the corresponding interrupt source
[95:64].

31:0

W

0x0

0: No effect.
1: Forcing the corresponding interrupt.

Setting this bit can be valid only when the corresponding interrupt
enable bit is set.

3.10.4.26. Interrupt Source Priority 0 Register (Default Value: 0x0000_0000)
Offset:0x0080
Bit
Read/Write

Default/Hex

Register Name: INTC_SRC_PRIO_REG0
Description
IRQ15_PRIO.
IRQ 15 Priority.
Set priority level for IRQ bit 15

31:30

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

29:28

R/W

0x0

GR8 User Manual(Version1.0)

IRQ14_PRIO.
IRQ 14 Priority.

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Offset:0x0080

Register Name: INTC_SRC_PRIO_REG0
Set priority level for IRQ bit 14

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ13_PRIO.
IRQ 13 Priority.
Set priority level for IRQ bit 13
27:26

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ12_PRIO.
IRQ 12 Priority.
Set priority level for IRQ bit 12

25:24

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ11_PRIO.
IRQ 11 Priority.
Set priority level for IRQ bit 11

23:22

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ10_PRIO.
IRQ 10 Priority.

21:20

R/W

0x0

Set priority level for IRQ bit 10

Level0 = 0x0 level 0, lowest priority
GR8 User Manual(Version1.0)

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System
Offset:0x0080

Register Name: INTC_SRC_PRIO_REG0
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ9_PRIO.
IRQ 9 Priority.
Set priority level for IRQ bit 9

19:18

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ8_PRIO.
IRQ 8 Priority.
Set priority level for IRQ bit 8

17:16

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ7_PRIO.
IRQ 7 Priority.
Set priority level for IRQ bit 7

15:14

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ6_PRIO.
IRQ 6 Priority.
Set priority level for IRQ bit 6

13:12

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

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System
Offset:0x0080

Register Name: INTC_SRC_PRIO_REG0
IRQ5_PRIO.
IRQ 5 Priority.
Set priority level for IRQ bit 5

11:10

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ4_PRIO.
IRQ 4 Priority.
Set priority level for IRQ 4

9:8

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ3_PRIO.
IRQ 3 Priority.
Set priority level for IRQ bit 3

7:6

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ2_PRIO.
IRQ 2 Priority.
Set priority level for IRQ bit 2

5:4

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ1_PRIO.

3:2

R/W

0x0

IRQ 1 Priority.
Set priority level for IRQ bit 1

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System
Offset:0x0080

Register Name: INTC_SRC_PRIO_REG0
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

1:0

/

/

/

Note: Programs the priority level for all sources except FIQ source (source 0). The priority level ranges from
0(lowest) to 3(highest).

3.10.4.27. Interrupt Source Priority 1 Register (Default Value: 0x0000_0000)
Offset:0x0084
Bit
Read/Write

Default/Hex

Register Name: INTC_SRC_PRIO_REG1
Description
IRQ31_PRIO.
IRQ 31 Priority.
Set priority level for IRQ bit 31

31:30

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ30_PRIO.
IRQ 30 Priority.
Set priority level for IRQ bit 30

29:28

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ29_PRIO.
IRQ 29 Priority.
Set priority level for IRQ bit 29

27:26

R/W

0x0
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2

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System
Offset:0x0084

Register Name: INTC_SRC_PRIO_REG1
Level3 = 0x3 level 3, highest priority
IRQ28_PRIO.
IRQ 28 Priority.
Set priority level for IRQ bit 28

25:24

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ27_PRIO.
IRQ 27 Priority.
Set priority level for IRQ bit 27

23:22

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ26_PRIO.
IRQ 26 Priority.
Set priority level for IRQ bit 26

21:20

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ25_PRIO.
IRQ 25 Priority.
Set priority level for IRQ bit 25

19:18

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

17:16

R/W

0x0

GR8 User Manual(Version1.0)

IRQ24_PRIO.
IRQ 24 Priority.
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System
Offset:0x0084

Register Name: INTC_SRC_PRIO_REG1
Set priority level for IRQ bit 24

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ23_PRIO.
IRQ 23 Priority.
Set priority level for IRQ bit 23
15:14

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ22_PRIO.
IRQ 22 Priority.
Set priority level for IRQ bit 22

13:12

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ21_PRIO.
IRQ 21 Priority.
Set priority level for IRQ bit 21

11:10

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ20_PRIO.
IRQ 20 Priority.

9:8

R/W

0x0

Set priority level for IRQ bit 20

Level0 = 0x0 level 0, lowest priority
GR8 User Manual(Version1.0)

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System
Offset:0x0084

Register Name: INTC_SRC_PRIO_REG1
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ19_PRIO.
IRQ 19 Priority.
Set priority level for IRQ bit 19

7:6

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ18_PRIO.
IRQ 18 Priority.
Set priority level for IRQ bit 18

5:4

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ17_PRIO.
IRQ 17 Priority.
Set priority level for IRQ bit 17

3:2

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ16_PRIO.
IRQ 16 Priority.
Set priority level for IRQ bit 16

1:0

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

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System

3.10.4.28. Interrupt Source Priority 2 Register (Default Value: 0x0000_0000)
Offset:0x0088
Bit
Read/Write

Default/Hex

Register Name: INTC_SRC_PRIO_REG2
Description
IRQ47_PRIO.
IRQ 47 Priority.
Set priority level for IRQ bit 47

31:30

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ46_PRIO.
IRQ 46 Priority.
Set priority level for IRQ bit 46

29:28

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ45_PRIO.
IRQ 45 Priority.
Set priority level for IRQ bit 45

27:26

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ44_PRIO.
IRQ 44 Priority.
Set priority level for IRQ bit 44

25:24

R/W

0x0
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2

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Page 138

System
Offset:0x0088

Register Name: INTC_SRC_PRIO_REG2
Level3 = 0x3 level 3, highest priority
IRQ43_PRIO.
IRQ 43 Priority.
Set priority level for IRQ bit 43

23:22

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ42_PRIO.
IRQ 42 Priority.
Set priority level for IRQ bit 42

21:20

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ41_PRIO.
IRQ 41 Priority.
Set priority level for IRQ bit 41

19:18

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ40_PRIO.
IRQ 40 Priority.
Set priority level for IRQ bit 40

17:16

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

15:14

R/W

0x0

GR8 User Manual(Version1.0)

IRQ39_PRIO.
IRQ 39 Priority.
Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 139

System
Offset:0x0088

Register Name: INTC_SRC_PRIO_REG2
Set priority level for IRQ bit 39

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ38_PRIO.
IRQ 38 Priority.
Set priority level for IRQ bit 38
13:12

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ37_PRIO.
IRQ 37 Priority.
Set priority level for IRQ bit 37

11:10

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ36_PRIO.
IRQ 36 Priority.
Set priority level for IRQ bit 36

9:8

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ35_PRIO.
IRQ 35 Priority.

7:6

R/W

0x0

Set priority level for IRQ bit 35

Level0 = 0x0 level 0, lowest priority
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System
Offset:0x0088

Register Name: INTC_SRC_PRIO_REG2
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ34_PRIO.
IRQ 34 Priority.
Set priority level for IRQ bit 34

5:4

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ33_PRIO.
IRQ 33 Priority.
Set priority level for IRQ bit 33

3:2

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ32_PRIO.
IRQ 32 Priority.
Set priority level for IRQ bit 32

1:0

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

3.10.4.29. Interrupt Source Priority 3 Register (Default Value: 0x0000_0000)
Offset:0x008C
Bit
Read/Write

Default/Hex

Register Name: INTC_SRC_PRIO_REG3
Description
IRQ63_PRIO.

31:30

0x0

IRQ 63 Priority.

R/W

Set priority level for IRQ bit 63

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System
Offset:0x008C

Register Name: INTC_SRC_PRIO_REG3
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ62_PRIO.
IRQ 62 Priority.
Set priority level for IRQ bit 62

29:28

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ61_PRIO.
IRQ 61 Priority.
Set priority level for IRQ bit 61

27:26

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ60_PRIO.
IRQ 60 Priority.
Set priority level for IRQ bit 60

25:24

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ59_PRIO.
IRQ 59 Priority.

23:22

R/W

0x0

Set priority level for IRQ bit 59

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
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System
Offset:0x008C

Register Name: INTC_SRC_PRIO_REG3
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ58_PRIO.
IRQ 58 Priority.
Set priority level for IRQ bit 58

21:20

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ57_PRIO.
IRQ 57 Priority.
Set priority level for IRQ bit 57

19:18

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ56_PRIO.
IRQ 56 Priority.
Set priority level for IRQ bit 56

17:16

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ55_PRIO.
IRQ 55 Priority.
Set priority level for IRQ bit 55

15:14

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

13:12

R/W

0x0

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IRQ54_PRIO.
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Page 143

System
Offset:0x008C

Register Name: INTC_SRC_PRIO_REG3
IRQ 54 Priority.
Set priority level for IRQ bit 54

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ53_PRIO.
IRQ 53 Priority.
Set priority level for IRQ bit 53
11:10

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ52_PRIO.
IRQ 52 Priority.
Set priority level for IRQ bit 52

9:8

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ51_PRIO.
IRQ 51 Priority.
Set priority level for IRQ bit 51

7:6

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ50_PRIO.

5:4

R/W

0x0

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IRQ 50 Priority.
Set priority level for IRQ bit 50

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System
Offset:0x008C

Register Name: INTC_SRC_PRIO_REG3
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ49_PRIO.
IRQ 49 Priority.
Set priority level for IRQ bit 49

3:2

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ48_PRIO.
IRQ 48 Priority.
Set priority level for IRQ bit 48

1:0

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

3.10.4.30. Interrupt Source Priority 4 Register (Default Value: 0x0000_0000)
Offset:0x0090
Bit
Read/Write

Default/Hex

Register Name: INTC_SRC_PRIO_REG4
Description
IRQ79_PRIO.
IRQ 79 Priority.
Set priority level for IRQ bit 79

31:30

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

29:28

R/W

0x0

GR8 User Manual(Version1.0)

IRQ78_PRIO.
IRQ 78 Priority.

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Page 145

System
Offset:0x0090

Register Name: INTC_SRC_PRIO_REG4
Set priority level for IRQ bit 78

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ77_PRIO.
IRQ 77 Priority.
Set priority level for IRQ bit 77
27:26

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ76_PRIO.
IRQ 76 Priority.
Set priority level for IRQ bit 76

25:24

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ75_PRIO.
IRQ 75 Priority.
Set priority level for IRQ bit 75

23:22

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ74_PRIO.
IRQ 74 Priority.

21:20

R/W

0x0

Set priority level for IRQ bit 74

Level0 = 0x0 level 0, lowest priority
GR8 User Manual(Version1.0)

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Page 146

System
Offset:0x0090

Register Name: INTC_SRC_PRIO_REG4
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ73_PRIO.
IRQ 73 Priority.
Set priority level for IRQ bit 73

19:18

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ72_PRIO.
IRQ 72 Priority.
Set priority level for IRQ bit 72

17:16

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ71_PRIO.
IRQ 71 Priority.
Set priority level for IRQ bit 71

15:14

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ70_PRIO.
IRQ 70 Priority.
Set priority level for IRQ bit 70

13:12

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

GR8 User Manual(Version1.0)

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Page 147

System
Offset:0x0090

Register Name: INTC_SRC_PRIO_REG4
IRQ69_PRIO.
IRQ 69 Priority.
Set priority level for IRQ bit 69

11:10

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ68_PRIO.
IRQ 68 Priority.
Set priority level for IRQ bit 68

9:8

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ67_PRIO.
IRQ 67 Priority.
Set priority level for IRQ bit 67

7:6

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ66_PRIO.
IRQ 66 Priority.
Set priority level for IRQ bit 66

5:4

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ65_PRIO.

3:2

R/W

0x0

IRQ 65 Priority.
Set priority level for IRQ bit 65

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System
Offset:0x0090

Register Name: INTC_SRC_PRIO_REG4
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ64_PRIO.
IRQ 64 Priority.
Set priority level for IRQ bit 64

1:0

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

3.10.4.31. Interrupt Source Priority 5 Register (Default Value: 0x0000_0000)
Offset:0x0094
Bit
Read/Write

Default/Hex

Register Name: INTC_SRC_PRIO_REG5
Description
IRQ95_PRIO.
IRQ 95 Priority.
Set priority level for IRQ bit 95

31:30

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ94_PRIO.
IRQ 94 Priority.
Set priority level for IRQ bit 94

29:28

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

27:26

R/W

0x0

GR8 User Manual(Version1.0)

IRQ93_PRIO.

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Page 149

System
Offset:0x0094

Register Name: INTC_SRC_PRIO_REG5
IRQ 93 Priority.
Set priority level for IRQ bit 93

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ92_PRIO.
IRQ 92 Priority.
Set priority level for IRQ bit 92
25:24

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ91_PRIO.
IRQ 91 Priority.
Set priority level for IRQ bit 91

23:22

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ90_PRIO.
IRQ 90 Priority.
Set priority level for IRQ bit 90

21:20

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ89_PRIO.

19:18

R/W

0x0

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IRQ 89 Priority.
Set priority level for IRQ bit 89

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Offset:0x0094

Register Name: INTC_SRC_PRIO_REG5
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ88_PRIO.
IRQ 88 Priority.
Set priority level for IRQ bit 88

17:16

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ87_RPIO.
IRQ 87 Priority.
Set priority level for IRQ bit 87

15:14

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ86_RPIO.
IRQ 86 Priority.
Set priority level for IRQ bit 86

13:12

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ85_PRIO.
IRQ 85 Priority.
Set priority level for IRQ bit 85

11:10

R/W

0x0
Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2

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Offset:0x0094

Register Name: INTC_SRC_PRIO_REG5
Level3 = 0x3 level 3, highest priority
IRQ84_PRIO.
IRQ 84 Priority.
Set priority level for IRQ bit 84

9:8

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ83_PRIO.
IRQ 83 Priority.
Set priority level for IRQ bit 83

7:6

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ82_PRIO.
IRQ 82 Priority.
Set priority level for IRQ bit 82

5:4

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority
IRQ81_PRIO.
IRQ 81 Priority.
Set priority level for IRQ bit 81

3:2

R/W

0x0

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

1:0

R/W

0x0

GR8 User Manual(Version1.0)

IRQ80_PRIO.
IRQ 80 Priority.
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Offset:0x0094

Register Name: INTC_SRC_PRIO_REG5
Set priority level for IRQ bit 80

Level0 = 0x0 level 0, lowest priority
Level1 = 0x1 level 1
Level2 = 0x2 level 2
Level3 = 0x3 level 3, highest priority

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3.11. DMA
3.11.1. Overview
There are two kinds of DMA implemented within GR8. One is Normal DMA (NDMA) with 8 channels, and the other
is Dedicated DMA (DDMA) with 8 channels.
For NDMA, only one channel can be active and the sequence is in accordance with the priority level. For DDMA,
at most 8 channels can be active at the same time if their source or destination does not conflict.

3.11.2. DMA Description
DMA can support 8-bit/16-bit/32-bit data width. The data width of Source and Destination can be different, but
the address should be aligned.

3.11.3. DMA Register List
Module Name
DMA

Base Address
0x01C02000

Register Name

Offset

Description

DMA_IRQ_EN_REG
DMA_IRQ_PEND_STAS_REG

0x0000
0x0004

DMA IRQ Enable
DMA IRQ Pending Status
Normal DMA Configuration

NDMA_CTRL_REG

0x100+N*0x20

NDMA_SRC_ADDR_REG

0x100+0x04+N*0x20

Normal DMA Source Address

NDMA_DEST_ADDR_REG

0x100+0x08+N*0x20

Normal DMA Destination Address

NDMA_BC_REG

0x100+N*0x20

Normal DMA Byte Counter

DDMA_CFG_REG

0x300+N*0x20

DDMA_SRC_ADDR_REG

0x300+0x04+N*0x20

Dedicated DMA Source Start Address

DDMA_DEST_ADDR_REG

0x300+0x08+N*0x20

Dedicated DMA Destination Start Address

DDMA_BC_REG

0x300+0x0C +N*0x20

Dedicated DMA Byte Counter

DDMA_PARA_REG

0x300+0x18+N*0x20

Dedicated DMA Parameter

(N=0,1,2,3,4,5,6,7)

Dedicated DMA Configuration

GR8 User Manual(Version1.0)

(N=0,1,2,3,4,5,6,7)

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3.11.4. DMA Register Description
3.11.4.1. DMA IRQ Enable Register (Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write

Default/Hex

Register Name: DMA_IRQ_EN_REG
Description
DDMA7_END_IRQ_EN.
Dedicated DMA 7 End Transfer Interrupt Enable.

31

R/W

0x0
0: Disable
1: Enable.
DDMA7_HF_IRQ_EN.
Dedicated DMA 7 Half Transfer Interrupt Enable.

30

R/W

0x0
0: Disable
1: Enable.
DDMA6_END_IRQ_EN.
Dedicated DMA 6 End Transfer Interrupt Enable.

29

R/W

0x0
0: Disable
1: Enable.
DDMA6_HF_IRQ_EN.
Dedicated DMA 6 Half Transfer Interrupt Enable.

28

R/W

0x0
0: Disable
1: Enable.
DDMA5_END_IRQ_EN.
Dedicated DMA 5 End Transfer Interrupt Enable.

27

R/W

0x0
0: Disable
1: Enable.
DDMA5_HF_IRQ_EN.
Dedicated DMA 5 Half Transfer Interrupt Enable.

26

R/W

0x0
0: Disable
1: Enable.

25

R/W

0x0

GR8 User Manual(Version1.0)

DDMA4_END_IRQ_EN.

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Dedicated DMA 4 End Transfer Interrupt Enable.

0: Disable
1: Enable.
DDMA4_HF_IRQ_EN.
Dedicated DMA 4 Half Transfer Interrupt Enable.
24

R/W

0x0
0: Disable
1: Enable.
DDMA3_END_IRQ_EN.
Dedicated DMA 3 End Transfer Interrupt Enable.

23

R/W

0x0
0: Disable
1: Enable.
DDMA3_HF_IRQ_EN.
Dedicated DMA 3 Half Transfer Interrupt Enable.

22

R/W

0x0
0: Disable
1: Enable.
DDMA2_END_IRQ_EN.
Dedicated DMA 2 End Transfer Interrupt Enable.

21

R/W

0x0
0: Disable
1: Enable.
DDMA2_HF_IRQ_EN.
Dedicated DMA 2 Half Transfer Interrupt Enable.

20

R/W

0x0
0: Disable
1: Enable.
DDMA1_END_IRQ_EN.
Dedicated DMA 1 End Transfer Interrupt Enable.

19

R/W

0x0
0: Disable
1: Enable.

18

R/W

0x0

GR8 User Manual(Version1.0)

DDMA1_HF_IRQ_EN.

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Dedicated DMA 1 Half Transfer Interrupt Enable.

0: Disable
1: Enable.
DDMA0_END_IRQ_EN.
Dedicated DMA 0 End Transfer Interrupt Enable.
17

R/W

0x0
0: Disable
1: Enable.
DDMA0_HF_IRQ_EN.
Dedicated DMA 0 Half Transfer Interrupt Enable.

16

R/W

0x0
0: Disable
1: Enable.
NDMA7_END_IRQ_EN.
Normal DMA 7 End Transfer Interrupt Enable.

15

R/W

0x0
0: Disable
1: Enable.
NDMA7_HF_IRQ_EN.
Normal DMA 7 Half Transfer Interrupt Enable.

14

R/W

0x0
0: Disable
1: Enable.
NDMA6_END_IRQ_EN.
Normal DMA 6 End Transfer Interrupt Enable.

13

R/W

0x0
0: Disable
1: Enable.
NDMA6_HF_IRQ_EN.
Normal DMA 6 Half Transfer Interrupt Enable.

12

R/W

0x0
0: Disable
1: Enable.

11

R/W

0x0

GR8 User Manual(Version1.0)

NDMA5_END_IRQ_EN.

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Normal DMA 5 End Transfer Interrupt Enable.

0: Disable
1: Enable.
NDMA5_HF_IRQ_EN.
Normal DMA 5 Half Transfer Interrupt Enable.
10

R/W

0x0
0: Disable
1: Enable.
NDMA4_END_IRQ_EN.
Normal DMA 4 End Transfer Interrupt Enable.

9

R/W

0x0
0: Disable
1: Enable.
NDMA4_HF_IRQ_EN.
Normal DMA 4 Half Transfer Interrupt Enable.

8

R/W

0x0
0: Disable
1: Enable.
NDMA3_END_IRQ_EN.
Normal DMA 3 End Transfer Interrupt Enable.

7

R/W

0x0
0: Disable
1: Enable.
NDMA3_HF_IRQ_EN.
Normal DMA 3 Half Transfer Interrupt Enable.

6

R/W

0x0
0: Disable
1: Enable.
NDMA2_END_IRQ_EN.
Normal DMA 2 End Transfer Interrupt Enable.

5

R/W

0x0
0: Disable
1: Enable.

4

R/W

0x0

GR8 User Manual(Version1.0)

NDMA2_HF_IRQ_EN.

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Normal DMA 2 Half Transfer Interrupt Enable.

0: Disable
1: Enable.
NDMA1_END_IRQ_EN.
Normal DMA 1 End Transfer Interrupt Enable.
3

R/W

0x0
0: Disable
1: Enable.
NDMA1_HF_IRQ_EN.
Normal DMA 1 Half Transfer Interrupt Enable.

2

R/W

0x0
0: Disable
1: Enable.
NDMA0_END_IRQ_EN.
Normal DMA 0 End Transfer Interrupt Enable.

1

R/W

0x0
0: Disable
1: Enable.
NDMA0_HF_IRQ_EN.
Normal DMA 0 Half Transfer Interrupt Enable.

0

R/W

0x0
0: Disable
1: Enable.

3.11.4.2. DMA IRQ Pending Status Register (Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write

Default/Hex

Register Name: DMA_IRQ_PEND_STAS_REG
Description
DDMA7_END_IRQ_PEND.
Dedicated DMA 7 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

31

R/W

0x0
0: No effect
1: Pending.

30

R/W

0x0

DDMA7_HF_IRQ_PEND.
Dedicated DMA 7 Half Transfer Interrupt Pending. Setting 1 to the bit

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will clear it.

0: No effect
1: Pending.
DDMA6_END_IRQ_PEND.
Dedicated DMA 6 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.
29

R/W

0x0
0: No effect
1: Pending.
DDMA6_HF_IRQ_PEND.
Dedicated DMA 6 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

28

R/W

0x0
0: No effect
1: Pending.
DDMA5_END_IRQ_PEND.
Dedicated DMA 5 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

27

R/W

0x0
0: No effect
1: Pending.
DDMA5_HF_IRQ_PEND.
Dedicated DMA 5 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

26

R/W

0x0
0: No effect
1: Pending.
DDMA4_END_IRQ_PEND.
Dedicated DMA 4 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

25

R/W

0x0
0: No effect
1: Pending.
DDMA4_HF_IRQ_PEND.

24

R/W

0x0

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Dedicated DMA 4 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

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0: No effect
1: Pending.
DDMA3_END_IRQ_PEND.
Dedicated DMA 3 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.
23

R/W

0x0
0: No effect
1: Pending.
DDMA3_HF_IRQ_PEND.
Dedicated DMA 3 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

22

R/W

0x0
0: No effect
1: Pending.
DDMA2_END_IRQ_PEND.
Dedicated DMA 2 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

21

R/W

0x0
0: No effect
1: Pending.
DDMA2_HF_IRQ_PEND.
Dedicated DMA 2 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

20

R/W

0x0
0: No effect
1: Pending.
DDMA1_END_IRQ_PEND.
Dedicated DMA 1 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

19

R/W

0x0
0: No effect
1: Pending.
DDMA1_HF_IRQ_PEND.

18

R/W

0x0

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Dedicated DMA 1 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

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0: No effect
1: Pending.
DDMA0_END_IRQ_PEND.
Dedicated DMA 0 End Transfer Interrupt Pending. Setting 1 to the bit
will clear it.
17

R/W

0x0
0: No effect
1: Pending.
DDMA0_HF_IRQ_PEND.
Dedicated DMA 0 Half Transfer Interrupt Pending. Setting 1 to the bit
will clear it.

16

R/W

0x0
0: No effect
1: Pending.
NDMA7_END_IRQ_PEND.
Normal DMA 7 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

15

R/W

0x0
0: No effect
1: Pending.
NDMA7_HF_IRQ_PEND.
Normal DMA 7 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

14

R/W

0x0
0: No effect
1: Pending.
NDMA6_END_IRQ_PEND.
Normal DMA 6 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

13

R/W

0x0
0: No effect
1: Pending.
NDMA6_HF_IRQ_PEND.

12

R/W

0x0

Normal DMA 6 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

0: No effect

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1: Pending.
NDMA5_END_IRQ_PEND.
Normal DMA 5 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.
11

R/W

0x0
0: No effect
1: Pending.
NDMA5_HF_IRQ_PEND.
Normal DMA 5 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

10

R/W

0x0
0: No effect
1: Pending.
NDMA4_END_IRQ_PEND.
Normal DMA 4 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

9

R/W

0x0
0: No effect
1: Pending.
NDMA4_HF_IRQ_PEND.
Normal DMA 4 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

8

R/W

0x0
0: No effect
1: Pending.
NDMA3_END_IRQ_PEND.
Normal DMA 3 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

7

R/W

0x0
0: No effect
1: Pending.
NDMA3_HF_IRQ_PEND.
Normal DMA 3 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

6

R/W

0x0
0: No effect
1: Pending.

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NDMA2_END_IRQ_PEND.
Normal DMA 2 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.
5

R/W

0x0
0: No effect
1: Pending.
NDMA2_HF_IRQ_PEND.
Normal DMA 2 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

4

R/W

0x0
0: No effect
1: Pending.
NDMA1_END_IRQ_PEND.
Normal DMA 1 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

3

R/W

0x0
0: No effect
1: Pending.
NDMA1_HF_IRQ_PEND.
Normal DMA 1 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

2

R/W

0x0
0: No effect
1: Pending.
NDMA0_END_IRQ_PEND.
Normal DMA 0 End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

1

R/W

0x0
0: No effect
1: Pending.
NDMA0_HF_IRQ_PEND.
Normal DMA 0 Half Transfer Interrupt Pending. Setting 1 to the bit will
clear it.

0

R/W

0x0
0: No effect
1: Pending.

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3.11.4.3. Normal DMA Configuration Register (Default Value: 0x0000_0000)
Offset: 0x100+N*0x20

Register Name: NDMA_CTRL_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

Description
NDMA_LOAD.
DMA Loading.

31

R/W

0x0

If set to 1, DMA will start and load the DMA registers to the shadow
registers. The bit will hold on until the DMA finishes. It will be cleared
automatically.
Setting 0 to the bit will reset the corresponding DMA channel.
NDMA_CONTI_EN.
DMA Continuous Mode Enable.

30

R/W

0x0
0: Disable
1: Enable.
NDMA_WAIT_STATE.
DMA Wait State.

29:27

R/W

0x0

000: wait for 0 DMA clock to request
…
111: wait for 2(n+1) DMA clock to request.
NDMA_DST_DATA_WIDTH.
Normal DMA Destination Data Width.

26:25

R/W

0x0

00: 8-bit
01: 16-bit
10: 32-bit
11: /
NDMA_DST_BST_LEN.
DMA Destination Burst Length.

24:23

R/W

0x0

00: 1
01: 4
10: 8
11: /

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22

/

/

/
NDMA_DST_ADDR_TYPE.
Normal DMA Destination Address Type.

21

R/W

0x0
0: Increment
1: No Change.
NDMA_DST_DRQ_TYPE.
Normal DMA Destination DRQ Type.

00000 : IR-TX
00001 : /
00010 : OWA-TX
00011 : I2S/PCM-TX
00100 : /
00101 : /
00110 : /
00111 : /
01000 : UART0 TX
01001 : UART1 TX
01010 : UART2 TX
20:16

R/W

0x0

01011 : UART3 TX
01100 : /
01101 : /
01110 : /
01111 : /
10000 : /
10001 : /
10010 : /
10011 : Audio Codec D/A
10100 : /
10101 : SRAM
10110 : SDRAM
10111 : /
11000 : SPI0 TX
11001 : /

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11010 : SPI2 TX
11011 : USB EP1
11100 : USB EP2
11101 : USB EP3
11110 : USB EP4
11111 : USB EP5
BC_MODE_SEL.
BC Mode Select.
15

R/W

0x0

0: Normal mode (the value read back equals to the value that is
written)
1: Remain mode (the value read back equals to the remain counter to
be transferred).

14:10

/

/

/
NDMA_SRC_DATA_WIDTH.
Normal DMA Source Data Width.

10:9

R/W

0x0

00: 8-bit
01: 16-bit
10: 32-bit
11: /
NDMA_SRC_BST_LEN.
DMA Source Burst Length.

8:7

R/W

0x0

00: 1
01: 4
10: 8
11: /.

6

/

/

/
NDMA_SRC_ADDR_TYPE.
Normal DMA Source Address Type.

5

R/W

0x0
0: Increment
1: No Change

4:0

R/W

0x0

GR8 User Manual(Version1.0)

NDMA_SRC_DRQ_TYPE.
Normal DMA Source DRQ Type.

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00000 : IR-RX
00001 : /
00010 :
00011 : I2S/PCM-RX
00100 : /
00101 : /
00110 :
00111 : /
01000 : UART0 RX
01001 : UART1 RX
01010 : UART2 RX
01011 : UART3 RX
01100 : /
01101 : /
01110 : /
01111 : /
10000 : /
10001 : /
10010 : /
10011 : Audio Codec A/D
10100 : /
10101 : SRAM
10110 : SDRAM
10111 : TP A/D
11000 : SPI0 RX
11001 : /
11010 : SPI2 RX
11011 : USB EP1
11100 : USB EP2
11101 : USB EP3
11110 : USB EP4
11111 : USB EP5

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3.11.4.4. Normal DMA Source Address Register
Offset: 0x100+0x04+N*0x20

Register Name: NDMA_SRC_ADDR_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

Description
NDMA_SRC_ADDR.
Normal DMA Source Address.

3.11.4.5. Normal DMA Destination Address Register
Offset: 0x0100+0x08+N*0x20

Register Name: NDMA_DEST_ADDR_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

Description
NDMA_DST_ADDR.
Normal DMA Destination Address.

3.11.4.6. Normal DMA Byte Counter Register
Offset: 0x0100+N*0x20+0xC

Register Name: NDMA_BC_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

Description

31:24

/

/

/

23:0

R/W

UDF

NDMA_BC.
Normal DMA Byte Counter.

Note: If ByteCounter=0, DMA will transfer no byte. The maximum value is 128k.

3.11.4.7. Dedicated DMA Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0300+N*0x20

Register Name: DDMA_CFG_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

Description
DDMA_LOAD.
DMA Loading.

31

R/W

0x0

If setting to 1, DMA will start and load the DMA registers to the
shadow registers. The bit will hold on until the DMA finishes. It will be
cleared automatically.
Setting 0 to the bit will stop the corresponding DMA channel and reset

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its state machine.
DDMA_BSY_STA.
DMA Busy Status.
30

R

0x0
0: DMA idle
1: DMA busy.
DDMA_CONTI_MODE_EN.
DMA Continuous Mode Enable.

29

R/W

0x0
0: Disable
1: Enable.

28

/

/

/

27

/

/

/
DDMA_DST_DATA_WIDTH.
DMA Destination Data Width.

26:25

R/W

0x0

00: 8-bit
01: 16-bit
10: 32-bit
11: /
DDMA_DST_BST_LEN.
DMA Destination Burst Length.

24:23

R/W

0x0

00: 1
01: 4.
10: 8
11: /
DDMA_ADDR_MODE.
DMA Destination Address Mode
DMA Source Address Mode

22:21

R/W

0x0

00: Linear Mode
01: IO Mode
10: Horizontal Page Mode
11: Vertical Page Mode

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DDMA_DST_DRQ_SEL.
Dedicated DMA Destination DRQ Type

00000: SRAM memory
00001: SDRAM memory
00010: /
00011: NAND Flash Controller (NFC)
00100: USB0
00101: /
00110: /
00111: /
01000: /
01001: /
01010: Crypto Engine TX
01011: /
01100: /
01101: /
20:16

R/W

0x0

01110: TCON0
01111: /
10000: /
10001: /
10010: /
10011: /
10100: /
10101: /
10110: /
10111: /
11000: /
11001: /
11010: SPI0 TX
11011: /.
11100: SPI2 TX
11101: /
11110: /
11111: /

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BC_MODE_SEL.
BC Mode Select.
15

R/W

0x0

0: Normal mode (the value read back equals to the value that is
written)
1: Remain mode (the value read back equals to the remain counter to
be transferred).

14:11

/

/

/
DDMA_SRC_DATA_WIDTH.
DMA Source Data Width.

10:9

R/W

0x0

00: 8-bit
01: 16-bit
10: 32-bit
11: /
DDMA_SRC_BST_LEN.
DMA Source Burst Length.

8:7

R/W

0x0

00: 1
01: 4
10: 8
11: /
DDMA_SRC_ADDR_MODE.
DMA Source Address Mode

6:5

R/W

0x0

00: Linear Mode
01: IO Mode
10: Horizontal Page Mode
11: Vertical Page Mode
DDMA_SRC_DRQ_TYPE.
Dedicated DMA Source DRQ Type

4:0

R/W

0x0

00000: SRAM memory
00001: SDRAM memory
00010: /
00011: NAND Flash Controller (NFC)

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00100: USB0
00101: /
00110: /
00111: /
01000: /
01001: /
01010: /
01011: Crypto Engine RX
01100: /
01101: /
01110: /
01111: /
10000: /
10001: /
10010: /
10011: /
10100: /
10101: /
10110: /
10111: /
11000: /
11001: /
11010: /
11011: SPI0 RX.
11100: /
11101: SPI2 RX
11110: /
11111: /

3.11.4.8. Dedicated DMA Source Start Address Register
Offset: 0x0300+0x04+N*0x20

Register Name: DDMA_SRC_ADDR_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

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Description
DDMA_SRC_START_ADDR.
Dedicated DMA Source Start Address.

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3.11.4.9. Dedicated DMA Destination Start Address Register
Offset: 0x0300+0x08+N*0x20

Register Name: DDMA_DEST_ADDR_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

Description
DDMA_DST_START_ADDR.
Dedicated DMA Destination Start Address.

3.11.4.10. Dedicated DMA Byte Counter Register
Offset: 0x0300+0x0C +N*0x20

Register Name: DDMA_BC_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

Description

31:25

/

/

/

24:0

R/W

UDF

DDMA_BC.
Dedicated DMA Byte Counter.

Note: If ByteCounter=0, DMA will transfer no byte. The maximum value is 0x1000000.

3.11.4.11. Dedicated DMA Parameter Register
Offset: 0x300+0x18+N*0x20

Register Name: DDMA_PARA_REG

(N=0,1,2,3,4,5,6,7)
Bit

Read/Write

Default/Hex

31:24

R/W

0x0

23:16

R/W

0x0

15:8

R/W

0x0

7:0

R/W

UDF

Description
DEST_DATA_BLK_SIZE.
Destination Data Block Size n.
DEST_WAIT_CLK_CYC.
Destination Wait Clock Cycles n
SRC_DATA_BLK_SIZE.
Source Data Block Size n.
SRC_WAIT_CLK_CYC.
Source Wait Clock Cycles n.

Note: If the counter is N, the value is N+1.

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3.12. LRADC
3.12.1. Overview
LRADC is a 6-bit resolution ADC for a 6-key application.
Features:
●

Supports APB 32-bit bus width

●

Supports interrupt

●

Supports general key, hold key and already hold key

●

Supports normal, single and continue work mode

●

6-bit resolution

●

Voltage input range between 0 to 0.667*AVCC

●

Sample rate up to 250Hz

3.12.2. Block Diagram
The block diagram of LRADC is shown in Figure 3-5.
IRQ
32K

APB

Clock Div

Analog Control

LRADC1

m
u
x

Register

LRADC0

Digital Logic
Process
ADC

Vrf

Figure 3-5. LRADC Block Diagram

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3.12.3. LRADC Control Logic
Level A
KEY_DOWN_IRQ

ADC_IN
Level B

Control HOLD_KEY_IRQ
Logic
ALREADY_HOLD_IRQ

Figure 3-6. LRADC Control Logic Diagram

Level A: 0.667*AVCC
Level B: Configurable by LEVELB_VOL
When the ADC_IN signal is less than Level A and Level B, the key down interrupt will be generated. When ADC_IN
signal is only less than Level A, the hold key interrupt will generate. When the ADC_IN signal is only less than Level
B, the already hold key interrupt will be generated.
If the ADC_IN signal is less than Level A, and in a certain time range (configurable by LEVELA_B_CNT) ADC_IN signal
is not less than Level B, the hold key interrupt will be generated. If the ADC_IN signal is less than Level A , and in a
certain time range (configurable by LEVELA_B_CNT) ADC_IN signal is less than Level B, the key down interrupt will
be generated. If the ADC_IN signal is less than Level B, and ADC_IN signal is not less than Level A, the already hold
key interrupt will be generated.
The LRADC has three modes: Normal Mode, Single Mode and Continue Mode. Normal Mode means the LRADC
will report the converted result data all the time when the key is down. Single Mode is when the LRADC will only
report the first converted result data when the key is down. Continue Mode is when the LRADC will report the
converted result data every other 8*(N+1) sample when the key is down.
The LRADC supports four sample rates: 250 Hz, 125 Hz, 62.5 Hz, and 31.25 Hz. You can configure the value of
LRADC_SAMPLE_RATE to select the desired sample rate.

3.12.4. LRADC Register List
Module Name
LRADC

Base Address
0x01C22800

Register Name
LRADC_CTRL
LRADC_INTC
LRADC_INTS
LRADC_DATA0
LRADC_DATA1

Offset
0x0000
0x0004
0x0008
0x000C
0x0010

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Description
LRADC Control Register
LRADC Interrupt Control Register
LRADC Interrupt Status Register
LRADC Data Register 0
LRADC Data Register 1

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3.12.5. LRADC Register Description
3.12.5.1. LRADC Control Register(Default Value: 0x0100_0168)
Offset: 0x0000
Bit
Read/Write

Default/Hex

31: 24

0x1

R/W

Register Name: LRADC_CTRL
Description
FIRST_CONCERT_DLY.
ADC First Convert Delay setting, ADC conversion is delayed by n
samples
ADC_CHAN_SELECT.
ADC Channel Select

23:22

R/W

0x0

00: ADC0 channel
01: ADC1 channel
1x: ADC0&ADC1 channel

21:20

/

/

/
CONTINUE_TIME_SELECT.

19:16

R/W

0x0

Continue Mode time select, one of 8*(N+1) sample as a valuable
sample data

15:14

/

/

/
LRADC_MODE_SELECT.
LRADC Mode Select

13:12

R/W

0x0

00: Normal Mode
01: Single Mode
10: Continue Mode
LEVELA_B_CNT.

11:8

R/W

0x1

Level A to Level B time threshold select, judge ADC convert value in
level A to level B in n+1 samples

7

/

/

/
LRADC_HOLD_EN.
LRADC Sample Hold Enable

6

R/W

0x1
0: Disable
1: Enable

5:4

R/W

0x2

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Level B Corresponding Data Value Setting

00: 0x3C
01: 0x39
10: 0x36
11: 0x33

Note: Voltage value = Data value/63 *(0.667*AVCC)
If data value is 0x3C, voltage value is about 1.9V.
LRADC_SAMPLE_RATE.
LRADC Sample Rate

3: 2

R/W

0x2

00: 250 Hz
01: 125 Hz
10: 62.5 Hz
11: 31.25 Hz

1

/

/

/
LRADC_EN.
LRADC Enable

0

R/W

0x0
0: Disable
1: Enable

3.12.5.2. LRADC Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write
31:16
/

Default/Hex
/

Register Name: LRADC_INTC
Description
/
ADC1_KEYUP_IRQ_EN.
ADC 1 Key Up IRQ Enable

12

R/W

0x0
0: Disable
1: Enable
ADC1_ALRDY_HOLD_IRQ_EN.

11

R/W

0x0

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0: Disable
1: Enable
ADC1_HOLD_IRQ_EN.
ADC 1 Hold Key IRQ Enable
10

R/W

0x0
0: Disable
1: Enable
ADC1_KEYIRQ_EN.
ADC 1 Key IRQ Enable

9

R/W

0x0
0: Disable
1: Enable
ADC1_DATA_IRQ_EN.
ADC 1 DATA IRQ Enable

8

R/W

0x0
0: Disable
1: Enable

7:5

/

/

/
ADC0_KEYUP_IRQ_EN.
ADC 0 Key Up IRQ Enable

4

R/W

0x0
0: Disable
1: Enable
ADC0_ALRDY_HOLD_IRQ_EN.
ADC 0 Already Hold IRQ Enable

3

R/W

0x0
0: Disable
1: Enable
ADC0_HOLD_IRQ_EN.
ADC 0 Hold Key IRQ Enable

2

R/W

0x0
0: Disable
1: Enable

1

R/W

0x0

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ADC0_KEYDOWN_EN
ADC 0 Key Down Enable

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0: Disable
1: Enable
ADC0_DATA_IRQ_EN.
ADC 0 Data IRQ Enable
0

R/W

0x0
0: Disable
1: Enable

3.12.5.3. LRADC Interrupt Status Register(Default Value: 0x0000_0000)
Offset: 0x0008
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: LRADC_INT
Description
/
ADC1_KEYUP_PENDING.
ADC 1 Key up Pending Bit
When General key pull up, it the corresponding interrupt is enabled.

12

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled
ADC1_ALRDY_HOLD_PENDING.
ADC 1 Already Hold Pending Bit
When Hold key pull down and pull the General key down, if the
corresponding interrupt is enabled.
11

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled
ADC1_HOLDKEY_PENDING.
10

R/W

0x0

ADC 1 Hold Key Pending Bit
When Hold, key pull down, the status bit is set and the interrupt line
is set if the corresponding interrupt is enabled.

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0: NO IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
ADC1_KEYDOWN_IRQ_PENDING.
ADC 1 Key Down IRQ Pending Bit
When General key pull down, the status bit is set and the interrupt line
is set if the corresponding interrupt is enabled.
9

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
ADC1_DATA_IRQ_PENDING.
ADC 1 Data IRQ Pending Bit

8

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled
7:5

/

/

/
ADC0_KEYUP_PENDING.
ADC 0 Key up Pending Bit
When general key pull up, it the corresponding interrupt is enabled.

4

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
ADC0_ALRDY_HOLD_PENDING.
3

R/W

0x0

ADC 0 Already Hold Pending Bit
When Hold key pull down and pull the General key down, if the

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corresponding interrupt is enabled.

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
ADC0_HOLDKEY_PENDING.
ADC 0 Hold Key Pending Bit
When Hold key pull down, the status bit is set and the interrupt line is
set if the corresponding interrupt is enabled.
2

R/W

0x0

0: NO IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
ADC0_KEYDOWN_PENDING.
ADC 0 Key Down IRQ Pending Bit
When General key pull down, the status bit is set and the interrupt line
is set if the corresponding interrupt is enabled.
1

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
ADC0_DATA_PENDING.
ADC 0 Data IRQ Pending Bit

0

R/W

0x0

0: No IRQ
1: IRQ Pending

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.

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3.12.5.4. LRADC Data 0 Register(Default Value: 0x0000_0000)
Offset: 0x000C
Bit
Read/Write
31:6
/

Default/Hex
/

5:0

0x0

R

Register Name: LRADC_DATA0
Description
/
LRADC0_DATA.
LRADC 0 Data

3.12.5.5. LRADC Data 1 Register(Default Value: 0x0000_0000)
Offset: 0x0010
Bit
Read/Write
31:6
/

Default/Hex
/

5:0

0x0

R

GR8 User Manual(Version1.0)

Register Name: LRADC_DATA1
Description
/
LRADC1_DATA.
LRADC 1 Data

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3.13. Touch Panel
3.13.1. Overview
The controller is a 4-wire resistive touch screen controller, it includes a 12-bit resolution A/D converter. The
controller, through the implementation of the two A/D conversion, can identify the location of a single touch and
detect an increase in pressure on the touch screen.
Features:
●

12-bit SAR type A/D converter

●

4-wire I/F

●

Touch-pressure measurement

●

Maximum sampling frequency: 2 MHz

●

Single-ended conversion of touch screen inputs and ratiometric conversion of touch screen inputs

●

TACQ up to 262ms

●

Median and averaging filter to reduce noise

●

Pen down detection, with programmable sensitivity

●

Supports X, Y change

3.13.2. Typical Application Circuit

Y+

X+

X-

Y-

Figure 3-7. TP Typical Application Circuit

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3.13.3. Clock Tree and ADC Time
3.13.3.1. Clock Tree
PRESCALER
00:/2
01:/3
10:/6
11:/1

HOSC24M

CLK_IN

AUDIO PLL

Figure 3-8. TP Clock Tree

3.13.3.2. A/D Conversion Time
When the clock source is 24 MHz and the prescaler value is 6, total 12-bit conversion time is:
CLK_IN = 24MHz/6 = 4MHz
Conversion Time = 1/(4MHz/13Cycles) = 3.25us
Touch acquire time divider is 16
TACQ = 16*16*1/4us = 64us
FS_TIME is based on TACQ and Touch Mode:
FS_TIME >= M*(TACQ + Conversion Time)
Conversion Time
X1-DATA

Y1-DATA

Z1-DATA

Z2-DATA

TACQ

FS_TIME

Figure 3-9. Single Touch and Pressure Measurement

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Conversion Time
X1-DATA

Y1-DATA

TACQ

FS_TIME

Figure 3-10. Single Touch No Pressure Measurement Mode

Conversion Time
ADC-DATA
TACQ

FS_TIME

Figure 3-11. General ADC Mode

3.13.4. Principle of Operation
3.13.4.1. The Basic Principle
The controller is a typical type of successive approximation ADC (SAR ADC), it contains a sample/hold, analog-todigital conversion, and serial data output functions. The analog inputs (X+, X-, Y+, Y-) via control register enter the
ADC, ADC can be configured as single-ended or differential mode. Selecting Aux ADC or temperature should be
configured for single-ended mode; as a touch screen application, it should be configured as a differential mode,
which can effectively eliminate the parasitic resistance of the driver switch and external interference caused by
measurement error and impact conversion accuracy.

3.13.4.2. Single-ended Mode
When the Bit12(ADC Mode Select) of TP Control Register 0 is high, the controller is in the measurement mode of
AUX, Temp, the internal ADC reference voltage source is the single-ended mode, using the AVCC reference source
as the ADC reference voltage, application of the principle of single-ended mode is shown in Figure 3-12.

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AVCC/REF

+IN

+REF
Converter

-IN
-REF

Figure 3-12. Simplified Diagram of Single-Ended Reference

3.13.4.3. Differential Mode
When the Bit12(ADC Mode Select) of TP Control Register 0 is low, the controller is in the measurement mode of
X,Y,Z, the internal ADC reference voltage source is the differential mode, is shown in Figure 3-13. The advantage of
differential mode: +REF and –REF input directly to the Y+, Y-, which can eliminate measurement error because of
the switch on-resistance. The disadvantage is that: both the ample or conversion process, the driver needs to be
on, relative to single-ended mode, the power consumption increases.
AVCC/REF

+IN

+REF
Converter

-IN
-REF

Figure 3-13. Simplified Diagram of Differential Reference

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3.13.4.4. Single Touch Detection
The principle of operation is illustrated below, For an X co-ordinate measurement, the X+ pin is internally switched
to AVCC and X- to GND. The X plate becomes a potential divider, and the voltage at the point of contact is
proportional to its X co-ordinate. This voltage is measured on the Y+, which carry no current (hence there is no
voltage drop in RY+ or RY-). Due to the ratiometric measurement method, the supply voltage does not affect
measurement accuracy. The voltage references VREF+ and VREF- are taken from after the matrix switches, so that
any voltage drop in these switches has no effect on the ADC measurement. Y co-ordinate measurements are similar
to X co-ordinate measurements, with the X and Y plates interchanged. In Single Touch mode, only need to test X+,
Y+ signal.
MEASURE
X-POSITION
X+

TOUCH
X-POSITION

X-

Figure 3-14. Single Touch X-Position Measurement

3.13.4.5. Touch-Pressure Measurement
The pressure applied to the touch screen by a pen or finger to filter unavailable can also be measurement with the
controller using some simple calculations. The contact resistance between the X and Y plates is measured,
providing a good indication of the size of the depressed area and, therefore, the applied pressure. The area of the
spot that is touched is proportional to the size of the object touching it. The size of this resistance (R touch) can be
calculated using two different methods.

First Method:
The first method requires the user to know the total resistance of the X-plate tablet (RX). Three touch screen
conversions are required: measurement of the X position, XPOSITION (Y+ input); measurement of the X+ input
with the excitation voltage applied to Y+ and X− (Z1 measurement); and measurement of the Y− input with the
excitation voltage applied to Y+ and X− (Z2 measurement). These three measurements are illustrated in Figure 315. The controller has two special ADC channel settings that configure the X and Y switches for the Z1 and Z2
measurements and store the results in the Z1 and Z2 result registers. The touch resistance (RTOUCH) can then be
calculated using the following equation:
RTOUCH = (RXPLATE) × (XPOSITION /4096) × [(Z2/Z1) − 1]

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MEASURE
X-POSITION

MEASURE
Z1-POSITION

Y+
X+

X+

Y+

Y+

X+

TOUCH
TOUCH
Z1-POSITION

X-POSITION

Y-

X-

X-

Z2-POSITION

Y-

X-

YMEASURE
Z2-POSITION

Figure 3-15. Pressure Measurement Block Diagram

Second Method:
The second method requires the user to know the resistance of the X-plate and Y-plate tablets. Three touch screen
conversions are required: a measurement of the X position (XPOSITION), the Y position (YPOSITION), and the Z1 position.
The following equation also calculates the touch resistance (RTOUCH):
RTOUCH = RXPLATE × (XPOSITION/4096) × [(4096/Z1) − 1] − RYPLATE × [1 − (YPOSITION/4096)] (2)

3.13.4.6. Pen Down Detection
Pen down detection is used as an interrupt to the host. RIRQ is an internal pull-up resistor with a programmable
value of 6~96 kΩ (default 48kΩ). The PENIRQ output is pulled high by an internal pull-up. the Y– driver is on and
connected to GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input
is pulled to ground through the touch screen, and the PENIRQ output goes low because of the current path through
the panel to GND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-position,
the X+ input is disconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage
current from flowing through the touch screen, thus causing no errors.
AVCC

RIRQ

Y+

Control
Logic

X+

ON

Y-

High when X+ or Y+ driver
is on

High when X+ or Y+ driver
is on

Figure 3-16. Example of Pen Touch Interrupt via Pen Down IRQ

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3.13.4.7. Median and Averaging Filter
As explained in the Touch Screen Principles section, touch screens are composed of two resistive layers, normally
placed over an LCD screen. Because these layers are in close proximity to the LCD screen, noise can be coupled
from the screen onto these resistive layers, causing errors in the touch screen positional measurements. The
controller contains a filtering block to process the data and discard the spurious noise before sending the
information to the host. The purpose of this block is not only the suppression of noise; the on-chip filtering also
greatly reduces the host processing loading. The processing function consists of two filters that are applied to the
converted results: the median filter and the averaging filter. The median filter suppresses the isolated out-of-range
noise and sets the number of measurements to be taken. These measurements are arranged in a temporary array,
where the first value is the smallest measurement and the last value is the largest measurement. The bit1 and bit0
(MED1 and MED0) in Median Filter Control Register set the window of the median filter and the number of
measurements taken.
Table 3-1. Median Filter Size
MED1
0
0
1
1

MED0
0
1
0
1

Median Filter Size
4
5
8
16

In this example, MED1=1, MED0=1, the median filter has a window size of 16. This means that 16 measurements
are taken and arranged in descending order in a temporary array. The averaging window size in this example is 8.
The output is the average of the middle eight values of the 16 measurements taken with the median filter.
12-BIT
SAR ADC

MEDIAN
FILTER

AVERAGING
FILTER

Converted Results

16 Measurements
Arranged

2

1

1

3

2

2

5

3

3

1

4

4

6

5

5

7

6

6

9

7

7

FIFO

Average Of Middle
8 Values

8

8

10

9

12

10

10

11

11

11

15

12

12

13

13

13

4

14

14

16

15

15

14

16

16

M=16

8
9

A=8

Figure 3-17. Median and Averaging Filter Example

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3.13.5. TP Register List
Module Name
TP

Base Address
0x01C25000

Register Name

Offset

Description

TP_CTRL0

0x0000

TP Control Register0

TP_CTRL1
TP_CTRL2
TP_MFCR
TP_INT_FIFOC
TP_INT_FIFOS
TP_CDAT
TP_DATA
TP_IO_CONFIG
TP_PORT_DATA

0x0004
0x0008
0x000C
0x0010
0x0014
0x001C
0x0024
0x0028
0x002C

TP Control Register1
TP Pressure Measurement and Touch Sensitive Control Register
Median Filter Controller Register
TP Interrupt FIFO Control Register
TP Interrupt FIFO Status Register
TP Common Data Register
TP Data Register
TP PORT IO Configure Register
TP Port Data Register

3.13.6. TP Register Description
3.13.6.1. TP Control Register 0(Default Value: 0x0F80_0000)
Offset: 0x0000
Bit
Read/Write

Default /Hex

Register Name: TP_CTRL0
Description
ADC_FIRST_DLY.

31:24

R/W

0xF

ADC First Convert Delay Setting
Based on ADC First Convert Delay Mode select
ADC_FIRST_DLY_MODE.
ADC First Convert Delay Mode Select

23

R/W

0x1
0: CLK_IN/16
1: CLK_IN/16*256
ADC_CLK_SELECT.
ADC Clock Source Select

22

R/W

0x0
0: HOSC(24 MHz)
1: Audio PLL

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ADC_CLK_DIVIDER.
ADC Clock Divider(CLK_IN)

00: CLK/2
21:20

R/W

0x0

01: CLK/3
10: CLK/6
11: CLK/1

In TP mode, these two bits must set 1x
FS_DIV.
ADC Sample Frequency Divider

19:16

R/W

0000: CLK_IN/2(20-n)

0x0

0001: CLK_IN/2(20-n)
0010: CLK_IN/2(20-n)
….
1111: CLK_IN/32
T_ACQ.

15:0

R/W

0x0

Touch Panel ADC Acquire Time
CLK_IN/(16*N)

3.13.6.2. TP Control Register 1(Default Value: 0x0000_0008)
Offset: 0x0004

Register Name: TP_CTRL1

Bit

Read/Write

Default /Hex

Description

31:20

/

/

/
STYLUS_UP_DEBOUNCE.
Stylus Up De-bounce Time Setting

19:12

R/W

0x0

0x00: 0
….
0xff: 2N*(CLK_IN/16*256)

11:10

/

/

9

R/W

0x0

GR8 User Manual(Version1.0)

/
STYLUS_UP_DEBOUCE_EN.
Stylus Up Debounce Function Select

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 192

System

0: Disable
1: Enable
8:7

/

/

/
TOUCH_PAN_CALI_EN.

6

R/W

0x0

Touch Panel Calibration
1: start Calibration, it is cleared to 0 after calibration
TP_DUAL_EN.
Touch Panel Double Point Enable

5

R/W

0x0
0: Disable
1: Enable
TP_MODE_EN.
TP Mode Function Enable

4

R/W

0x0
0: Disable
1: Enable
TP_ADC_SELECT.
Touch Panel and ADC Select

3

R/W

0x1
0: TP
1: ADC
ADC_CHAN_SELECT.
Analog Input Channel Select in Normal mode

000: X1 channel
001: X2 Channel
2:0

R/W

0x0

010: Y1 Channel
011: Y2 Channel
1xx : 4-channel robin-round

FIFO Access Mode, based on this setting. Selecting one channel, FIFO
will access that channel data; Selecting four channels FIFO will access
each channel data in successive turn, first is X1 data.

GR8 User Manual(Version1.0)

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System
3.13.6.3. TP Control Register 2(Default Value: 0x8000_0FFF)
Offset: 0x0008
Bit

Read/Write

Register Name: TP_CTRL2
Default/Hex

Description
TP_SENSITIVE_ADJUST.
Internal Pull-up Resistor Control

0000: least sensitive
31:28

R/W

0x8

0011
……
1111: most sensitive

Note: Used to adjust sensitivity of pen down detection
TP_MODE_SELECT.
TP Mode Select

27:26

R/W

0x0

00: FIFO store X,Y data with Z-filter
01: FIFO store X,Y, △X, △Y data with Z-filter
10: FIFO store X,Y, X2,Y2 data with Z-filter
11: Debug Mode, FIFO store X1,Y1, X2,Y2,Z1,Z2 data

25

/

/

/
PRE_MEA_EN.
TP Pressure Measurement Enable Control

24

R/W

0x0
0: Disable
1: Enable
PRE_MEA_THRE_CNT.
TP Pressure Measurement threshold Control

23:0

R/W

0xFFF

0x000000: least sensitive
0xFFFFFF: most sensitive

Note: Used to adjust sensitivity of touch

3.13.6.4. Median Filter Control Register(Default Value: 0x0000_0001)
Offset: 0x000C
GR8 User Manual(Version1.0)

Register Name: TP_MFCR
Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
Bit
31:3

Read/Write
/

Default/Hex
/

Description
/
FILTER_EN.
Filter Enable

2

R/W

0x0
0: Disable
1: Enable
FILTER_TYPE.
Filter Type

1:0

R/W

0x1

00: 4/2
01: 5/3
10: 8/4
11: 16/8

3.13.6.5. TP Interrupt& FIFO Control Register(Default Value: 0x0000_0F00)
Offset: 0x0010
Bit
Read/Write
31:19
/

Default/Hex
/

18

0x0

R/W

Register Name: TP_INT
Description
/
TP_OVERRUN_IRQ_EN.
TP FIFO Over Run IRQ Enable

17

R/W

0x0
0: Disable
1: Enable
TP_DATA_IRQ_EN.
TP FIFO Data Available IRQ Enable

16

R/W

0x0
0: Disable
1: Enable

15:14

/

/

/
TP_DATA_XY_CHANGE.

13

R/W

0x0

TP FIFO X,Y Data interchange Function Select

0: Disable

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System
1: Enable
TP_FIFO_TRIG_LEVEL.
12:8

R/W

TP FIFO Data Available Trigger Level

0xF

Interrupt and DMA request trigger level for TP or Auxiliary ADC
Trigger Level = TXTL + 1
TP_DATA_DRQ_EN.
TP FIFO Data Available DRQ Enable

7

R/W

0x0
0: Disable
1: Enable

6:5

/

/

/
TP_FIFO_FLUSH.

4

R/W

0x0

TP FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’

3:2

/

/

/
TP_UP_IRQ_EN.
Touch Panel Last Touch (Stylus Up) IRQ Enable

1

R/W

0x0
0: Disable
1: Enable
TP_DOWN_IRQ_EN.
Touch Panel First Touch (Stylus Down) IRQ Enable

0

R/W

0x0
0: Disable
1: Enable

3.13.6.6. TP Interrupt& FIFO Status Register(Default Value: 0x0000_0000)
Offset: 0x0014
Bit
Read/Write
31:19
/

Default/Hex
/

Register Name: TP_FIFOCS
Description
/

18

0x0

/

R/W

FIFO_OVERRUN_PENDING.
17

R/W

0x0

TP FIFO Over Run IRQ Pending

0: No Pending IRQ

GR8 User Manual(Version1.0)

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System
1: FIFO Overrun Pending IRQ

Write ‘1’ to clear this interrupt or automatically clear if interrupt
condition fails.
FIFO_DATA_PENDING.
TP FIFO Data Available Pending Bit

16

R/W

0x0

0: NO Pending IRQ
1: FIFO Available Pending IRQ

Write ‘1’ to clear this interrupt or automatically clear if interrupt
condition fails.
15:13

/

/

12:8

R

0x0

7:3

/

/

/
RXA_CNT.
TP FIFO Available Sample Word Counter
/
TP_IDLE_FLG.
Touch Panel Idle Flag

2

R

0x0
0: Idle
1: Not idle
TP_UP_PENDING.
Touch Panel Last Touch (Stylus Up) IRQ Pending bit

1

R/W

0x0

0: No IRQ
1: IRQ

Note: Writing 1 to the bit will clear it and its corresponding interrupt
if the interrupt is enabled.
TP_DOWN_PENDING.
Touch Panel First Touch (Stylus Down) IRQ Pending bit
0

R/W

0x0

0: No IRQ
1: IRQ

Note: Writing 1 to the bit will clear it and its corresponding interrupt

GR8 User Manual(Version1.0)

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System
if the interrupt is enabled.

3.13.6.7. Common Data Register(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
Read/Write

Default/Hex

Register Name: TP_CDAT
Description

31:12

/

/

/

11:0

R/W

0x0

TP_CDAT.
TP Common Data

3.13.6.8. TP Data Register(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
Read/Write
31:12
/

Default/Hex
/

11:0

0x0

R

Register Name: TP_DATA
Description
/
TP_DATA
Touch Panel X,Y data or Auxiliary analog input data

3.13.6.9. TP Port IO Configure Register(Default Value: 0x0000_2222)
Offset: 0x0028
Bit
Read/Write
31:15
/

Default/Hex
/

Register Name: TP_IO_CONFIG
Description
/
TY_N_SELECT
TY_N Port Function Select

14:12

11

R/W

/

0x2

/

000:Input

001:Output

010: TP_YN

011:/

100: /

101:/

110: /

111:/

/
TY_P_SELECT
TY_P Port Function Select

10:8

R/W

0x2

GR8 User Manual(Version1.0)

000:Input

001:Output

010: TP_YP

011:/

100: /

101:/

110: /

111:/

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System
7

/

/

/
TX_N_SELECT
TX_P Port Function Select

6:4

3

R/W

/

0x2

/

000:Input

001:Output

010: TP_XP

011:/

100: /

101:/

110: /

111:/

/
TX_P_SELECT
TX_P Port Function Select

2:0

R/W

0x2

000:Input

001:Output

010: TP_XP

011:/

100: /

101:/

110: /

111:/

3.13.6.10. TP Port Data Register(Default Value: 0x0000_0000)
Offset: 0x002C
Bit
Read/Write
31:12
/

Default/Hex
/

3:0

0x0

R/W

GR8 User Manual(Version1.0)

Register Name: TP_PORT_DATA
Description
/
TP_PORT_DATA
TP Port Data Value,TP_XP,TP_XN,TP_YP,TP_YN

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System

3.14. Crypto Engine
3.14.1. Overview
The Crypto Engine is one encrypt/ decrypt function accelerator suitable for a variety of applications. It supports
both encryption and decryption and several modes. Besides, both CPU mode and DMA method are supported for
different applications.
Features:
●

Supports AES, DES, 3DES, SHA-1, MD5

●

Supports ECB, CBC modes for AES/DES/3DES

●

128-bit, 192-bit and 256-bit key size for AES

●

160-bit hardware PRNG with 175-bit seed

●

Supports 32 words RX FIFO and 32 words TX FIFO for high speed application

●

Supports CPU mode and DMA mode

3.14.2. Crypto Engine Block Diagram

32-words
RX FIFO

AHB
Bus
SHA-1/
MD5/
PRNG

DES/
3DES

AES

Register
File

32-words
TX FIFO

Interrupt &
DMA

RX FIFO
DRQ

TX FIFO
DRQ

D-DMA

Figure 3-18. Crypto Engine Block Diagram

3.14.3. Crypto Engine Register List
Module Name
Crypto Engine

Base Address
0x01C15000

Register Name

Offset

GR8 User Manual(Version1.0)

Description

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 200

System
CE_CTL
CE_KEY0
CE_KEY1
…
CE_KEY7
CE_IV0
CE_IV1
…
CE_IV7
CE_FCSR
CE_ICSR
CE_MD0
CE_MD1
CE_MD2
CE_MD3
CE_MD4
CE_RXFIFO
CE_TXFIFO

0x0000
0x0004
0x0008
…
0x0020
0x0024
0x0028
…
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0200
0x0204

Control Register
Input Key 0/ PRNG Seed 0
Input Key 1/ PRNG Seed 1
…
Input Key 7
Initialization Vector 0
Initialization Vector 1
…
Initialization Vector 7
FIFO Control/ Status Register
Interrupt Control/ Status Register
SHA1/MD5 Message Digest 0/PRNG Data0
SHA1/MD5 Message Digest 1/PRNG Data1
SHA1/MD5 Message Digest 2/PRNG Data2
SHA1/MD5 Message Digest 3/PRNG Data3
SHA1/MD5 Message Digest 4/PRNG Data4
RX FIFO input port
TX FIFO output port

3.14.4. Crypto Engine Register Description
3.14.4.1. Crypto Engine Control Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
31:28

Read/Write
/

Register Name: CE_CTL
Default/Hex
/

Description
/
AES/DES/3DES key select

0000: Select input CE_KEYx (Normal Mode)
27:24

R/W

0x0

0001: Select SID_RKEYx from Security ID
0011: Reserved
0011~1010: Select internal Key n (n from 0 to 7)
Others: Reserved

18:16

R

UDF

Reserved
PRNG generator mode

15

R/W

0x0

0: One-shot mode
1: Continue mode
IV Steady of SHA-1/MD5 constants

14

R/W

0x0
0: Constants

GR8 User Manual(Version1.0)

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System
1: Arbitrary IV

Note: It is only used for SHA-1/MD5 engine. If the number of IV word is
beyond of 4, Counter 0 register is used for IV4.
CE Operation Mode

13:12

R/W

0x0

00: Electronic Code Book (ECB) mode
01: Cipher Block Chaining (CBC) mode
Others: Reserved

11:10

/

/

/
Key Size for AES

9:8

R/W

0x0

00: 128-bit
01: 192-bit
10: 256-bit
11: Reserved
CE Operation Direction

7

R/W

0x0

0: Encryption
1: Decryption
CE Method

000: AES
001: DES
6:4

R/W

0x0

010: Triple DES (3DES)
011: SHA-1
100: MD5
101: PRNG
Others: Reserved

3

/

/

/
SHA-1/MD5 Data End bit

2

R/W

0x0

Write ‘1’ to tell SHA-1/MD5 engine that the text data ends. If there is some
data in FIFO, the engine will fetch these data and process them. After
finishing message digest, this bit is cleared to ‘0’ by hardware and message
digest can be read out from digest registers.
Note: It is only used for SHA-1/MD5 engine.

GR8 User Manual(Version1.0)

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System
PRNG start bit
1

R/W

0x0

In PRNG one-shot mode, write ‘1’ to start PRNG. After generating one
group random data (5 words), this bit is cleared to ‘0’ by hardware.
CE Enable
A disable on this bit overrides any other block and flushes all FIFOs.

0

R/W

0x0
0: Disable
1: Enable

3.14.4.2. Crypto Engine Key [n] Register(Default Value: 0x0000_0000)
Offset: 0x0004 +N*0x04

Register Name: CE_KEY[n]

Bit

Read/Write

Default/Hex

Description

31:0

R/W

0x0

Key[n] Input Value (n= 0~7)/PRNG Seed[n] (n= 0~5)

3.14.4.3. Crypto Engine IV[n] Register(Default Value: 0x0000_0000)
Offset: 0x0024 +N*0x08

Register Name: CE_IV[n]

Bit

Read/Write

Default/Hex

Description

31:0

R/W

0x0

Initialization Vector (IV[n]) Input Value (n= 0~7)

3.14.4.4. Crypto Engine FIFO Control/ Status Register(Default Value: 0x6000_0F0F)
Offset: 0x0044
Bit
Read/Write

Default/Hex

Register Name: CE_FCSR
Description

31

/

/

/

RX FIFO Empty
30

R

0x1

0: No room for new word in RX FIFO
1: More than one room for new word in RX FIFO (>= 1 word)

29:24

R

0x20

RX FIFO Empty Space Word Counter

23

/

/

/
TX FIFO Data Available Flag

22

R

0x0

0: No available data in TX FIFO
1: More than one data in TX FIFO (>= 1 word)

21:16

R

0x0

GR8 User Manual(Version1.0)

TX FIFO Available Word Counter

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Page 203

System
15:13

/

/

/
RX FIFO Empty Trigger Level

12:8

R/W

Interrupt and DMA request trigger level for RXFIFO normal condition

0xF

Trigger Level = RXTL + 1
Note: RX FIFO is used for input the data.

7:5

/

/

/
TX FIFO Trigger Level

4:0

R/W

Interrupt and DMA request trigger level for TXFIFO normal condition

0xF

Trigger Level = TXTL + 1
Note: TX FIFO is used to output the result data.

3.14.4.5. Crypto Engine Interrupt Control/Status Register(Default Value: 0x0000_0000)
Offset: 0x0048
Bit
31:11

Read/Write
/

Register Name: CE_ICSR
Default/Hex
/

Description
/
RX FIFO Empty Pending bit

10

R/W

0x0

0: No pending
1: RX FIFO Empty pending

Note: Write ‘1’ to clear or automatically clear if interrupt condition fails.
9

/

/

/
TX FIFO Data Available Pending bit

8

R/W

0x0

0: No TX FIFO pending
1: TX FIFO pending

Note: Write ‘1’ to clear or automatically clear if interrupt condition fails.
7:5

/

/

/
DRQ Enable

4

R/W

0x0

0: Disable DRQ (CPU polling mode)
1: Enable DRQ (DMA mode)

3

/

/

/

2

R/W

0x0

RX FIFO Empty Interrupt Enable

GR8 User Manual(Version1.0)

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System

0: Disable
1: Enable

Note: If it is set to ‘1’, when the number of empty room is no smaller than
(>=) the preset threshold, the interrupt is triggered and the correspond flag
is set.
1

/

/

/
TX FIFO Data Available Interrupt Enable

0: Disable
0

R/W

1: Enable

0x0

Note: If it is set to ‘1’, when available data number is no smaller than (>=)
the preset threshold, the interrupt is triggered and the correspond flag is
set.

3.14.4.6. Crypto Engine Message Digest[n] Register(Default Value: 0x0000_0000)
Offset: 0x004C +N*0x04

Register Name: CE_MD[N]

Bit

Read/Write

Default/Hex

Description

31:0

R

0x0

SHA1/MD5 message digest MD[N] for SHA1/MD5 (N= 0~4)

3.14.4.7. Crypto Engine RX FIFO Register(Default Value: 0x0000_0000)
Offset: 0x0200

Register Name: CE_RX

Bit

Read/Write

Default/Hex

Description

31:0

W

0x0

32-bit RX FIFO for Input

3.14.4.8. Crypto Engine TX FIFO Register(Default Value: 0x0000_0000)
Offset: 0x0204

Register Name: CE_TX

Bit

Read/Write

Default/Hex

Description

31:0

R

0x0

32-bit TX FIFO for Output

3.14.5. Crypto Engine Clock Requirement
Clock Name
ahb_clk

GR8 User Manual(Version1.0)

Description
AHB bus clock

Requirement
>=24 MHz

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System
ce_clk

GR8 User Manual(Version1.0)

CE serial clock

<= 150 MHz

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 206

System

3.15. Security ID
3.15.1. Overview
GR8 supports an 128-bit EFUSE security key which can also be used as root key or for other purposes.
Features:
●

128-bit electrical fuses for root key

GR8 User Manual(Version1.0)

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System

3.16. Port Controller
3.16.1. Overview
GR8 has 6 ports for multi-functional input/out pins. They are:
●

Port B(PB): 19 input/output port

●

Port C(PC): 17 input/output port

●

Port D(PD): 22 input/output port

●

Port E(PE): 12 input/output port

●

Port F(PF): 6 input/output port

●

Port G(PG): 14 input/output port

These ports can be easily configured by software for various system configurations.

3.16.2. Port Configuration Table
PIO
Name
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PC0
PC1
PC2
PC3
PC4
PC5
PC6

M0
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input

M1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output

GR8 User Manual(Version1.0)

M2
TWI0-SCK
TWI0-SDA
PWM0

Multiplex Function Select
M3
M4

M5

IR-RX
I2S-MCLK
I2S-BCLK
I2S-LRCK
I2S-DO
I2S-DI
SPI2-CS0
SPI2-CLK
SPI2-MOSI
SPI2-MISO
TWI1-SCK
TWI1-SDA
TWI2-SCK
TWI2-SDA
NWE
NALE
NCLE
NCE1
NCE0
NRE
NRB0

OWA-DO
JTAG-MS0
JTAG-CK0
JTAG-DO0
JTAG-DI0

M6

EINT16
EINT17
EINT18
EINT19
EINT20
EINT21
EINT22
EINT23
EINT24
EINT25
EINT26
EINT27
EINT28

SPI0-MOSI
SPI0-MISO
SPI0-CLK
SPI0-CS0

SDC2-CMD

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System
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC19
PD2
PD3
PD4
PD5
PD6
PD7
PD10
PD11
PD12
PD13
PD14
PD15
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PF0
PF1
PF2
PF3
PF4
PF5

Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input

Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output

Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output

GR8 User Manual(Version1.0)

NRB1
NDQ0
NDQ1
NDQ2
NDQ3
NDQ4
NDQ5
NDQ6
NDQ7
NDQS
LCD-D2
LCD-D3
LCD-D4
LCD-D5
LCD-D6
LCD-D7
LCD-D10
LCD-D11
LCD-D12
LCD-D13
LCD-D14
LCD-D15
LCD-D18
LCD-D19
LCD-D20
LCD-D21
LCD-D22
LCD-D23
LCD-CLK
LCD-DE
LCD-HSYNC
LCD-VSYNC

SDC2-CLK
SDC2-D0
SDC2-D1
SDC2-D2
SDC2-D3
SDC2-D4
SDC2-D5
SDC2-D6
SDC2-D7
UART2-TX
UART2-RX
UART2-CTS
UART2-RTS

CSI-PCLK
CSI-MCLK
CSI-HSYNC
CSI-VSYNC
CSI-D0
CSI-D1
CSI-D2
CSI-D3
CSI-D4
CSI-D5
CSI-D6
CSI-D7
SDC0-D1
SDC0-D0
SDC0-CLK
SDC0-CMD
SDC0-D3
SDC0-D2

SPI2-CS0
SPI2-CLK
SPI2-MOSI
SPI2-MISO
SDC2-D0
SDC2-D1
SDC2-D2
SDC2-D3
SDC2-CMD
SDC2-CLK
UART1-TX
UART1-RX
JTAG-MS1
JTAG-DI1
UART0-TX
JTAG-DO1
UART0-RX
JTAG-CK1

Copyright © 2017 Next Thing Co. All Rights Reserved.

EINT14
EINT15

Page 209

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PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13

Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input

Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output

SDC1-CMD
SDC1-CLK
SDC1-D0
SDC1-D1
SDC1-D2
SDC1-D3

UART1-TX
UART1-RX
UART1-CTS
UART1-RTS

UART3-TX
UART3-RX
UART3-CTS
UART3-RTS
PWM1

EINT0
EINT1
EINT2
EINT3
EINT4
EINT5
EINT6
EINT7
EINT8
EINT9
EINT10
EINT11
EINT12
EINT13

3.16.3. Port Register List
Module Name
PIO

Base Address
0x01C20800

Register Name
Pn_CFG0
Pn_CFG1
Pn_CFG2
Pn_CFG3
Pn_DAT
Pn_DRV0
Pn_DRV1
Pn_PUL0
Pn_PUL1
PIO_INT_CFG0
PIO_INT_CFG1
PIO_INT_CFG2
PIO_INT_CFG3
PIO_INT_CTL
PIO_INT_STA
PIO_INT_DEB

Offset
0x0000+n*0x24
0x0004+n*0x24
0x0008+n*0x24
0x000C+n*0x24
0x0010+n*0x24
0x0014+n*0x24
0x0018+n*0x24
0x001C+n*0x24
0x0020+n*0x24
0x0200
0x0204
0x0208
0x020C
0x0210
0x0214
0x0218

Description
Port n Configure Register 0 (n from 1 to 6)
Port n Configure Register 1 (n from 1 to 6)
Port n Configure Register 2 (n from 1 to 6)
Port n Configure Register 3 (n from 1 to 6)
Port n Data Register (n from 1 to 6)
Port n Multi-Driving Register 0 (n from 1 to 6)
Port n Multi-Driving Register 1 (n from 1 to 6)
Port n Pull Register 0 (n from 1 to 6)
Port n Pull Register 1 (n from 1 to 6)
PIO Interrupt Configure Register 0
PIO Interrupt Configure Register 1
PIO Interrupt Configure Register 2
PIO Interrupt Configure Register 3
PIO Interrupt Control Register
PIO Interrupt Status Register
PIO Interrupt Debounce Register

3.16.4. Port Register Description
3.16.4.1. PB Configure Register 0(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: PB_CFG0
Description

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System
31

/

/

/
PB7 Select

30:28

27

R/W

/

0x0

/

000: Input

001: Output

010: I2S-LRCK

011: /

100: /

101: /

110: EINT21

111: /

/
PB6 Select

26:24

23

R/W

/

0x0

/

000: Input

001: Output

010: I2S-BCLK

011: /

100: /

101: /

110: EINT20

111: /

/
PB5 Select

22:20

19

R/W

/

0x0

/

000: Input

001: Output

010: I2S-MCLK

011: /

100: /

101: /

110: EINT19

111: /

/
PB4 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: IR-RX

011: /

100: /

101: /

110: EINT18

111: /

/
PB3 Select

14:12

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: /

011: /

100: /

101: /

110: EINT17

111: /

Copyright © 2017 Next Thing Co. All Rights Reserved.

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11

/

/

/
PB2 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: PWM0

011: /

100: /

101: /

110: EINT16

111: /

/
PB1 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Output

010: TWI0-SDA

011: /

100: /

101: /

110: /

111: /

/
PB0 Select

2:0

R/W

0x0

000: Input

001: Output

010: TWI0-SCK

011: /

100: /

101: /

110: /

111: /

3.16.4.2. PB Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x0028
Bit
31

Read/Write
/

Register Name: PB_CFG1
Default/Hex
/

Description
/
PB15 Select

30:28

R/W

0x0

27

/

/

26:24

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: TWI1-SCK

011: /

100: /

101: /

110: /

111: /

/
PB14 Select

Copyright © 2017 Next Thing Co. All Rights Reserved.

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23

/

/

000: Input

001: Output

010: SPI2-MISO

011: JTAG-DI0

100: /

101: /

110: EINT28

111: /

/
PB13 Select

22:20

19

R/W

/

0x0

/

000: Input

001: Output

010: SPI2-MOSI

011: JTAG-DO0

100: /

101: /

110: EINT27

111: /

/
PB12 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: SPI2-CLK

011: JTAG-CK0

100: /

101: /

110: EINT26

111: /

/
PB11 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: SPI2-CS0

011: JTAG-MS0

100: /

101: /

110: EINT25

111: /

/
PB10 Select

10:8

R/W

0x0

7

/

/

6:4

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: /

011: OWA-DO

100: /

101: /

110: EINT24

111: /

/
PB9 Select

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3

/

/

000: Input

001: Output

010: I2S-DI

011: /

100: /

101: /

110: EINT23

111: /

/
PB8 Select

2:0

R/W

0x0

000: Input

001: Output

010: I2S-DO

011: /

100: /

101: /

110: EINT22

111: /

3.16.4.3. PB Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x002C
Bit
31:11

Read/Write
/

Register Name: PB_CFG2
Default/Hex
/

Description
/
PB18 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: TWI2-SDA

011: /

100: /

101: /

110: /

111: /

/
PB17 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Output

010: TWI2-SCK

011: /

100: /

101: /

110: /

111: /

/
PB16 Select

2:0

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: TWI1-SDA

011: /

100: /

101: /

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110: /

111: /

3.16.4.4. PB Configure Register 3(Default Value: 0x0000_0000)
Offset: 0x0030

Register Name: PB_CFG3

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.5. PB Data Register(Default Value: 0x00000000)
Offset: 0x34

Register Name: PB_DAT

Bit
31:19

Read/Write
/

Default/Hex
/

18:0

R/W

0x0

Description
/
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.

3.16.4.6. PB Multi-Driving Register 0(Default Value: 0x5555_5555)
Offset: 0x0038
Bit
[2i+1:2i]
(i=0~15)

Register Name: PB_DRV0

Read/Write

Default/Hex

R/W

0x1

Description
PB[n] Multi-Driving Select (n = 0~15)

00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.7. PB Multi-Driving Register 1(Default Value: 0x0000_0155)
Offset: 0x003C
Bit
Read/Write

Default/Hex

Register Name: PB_DRV1
Description

31:10

/

/

/

9:8

R/W

0x1

Reserved

7:6

R/W

0x1

Reserved
PB[n] Multi-Driving Select (n = 16~18)

[2i+1:2i]
(i=0~2)

R/W

0x1

GR8 User Manual(Version1.0)

00: Level 0

01: Level 1

10: Level 2

11: Level 3

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3.16.4.8. PB Pull Register 0(Default Value: 0x0000_0000)
Offset: 0x0040
Read/Write

Bit

Register Name: PB_PULL0
Default/Hex

Description
PB[n] Pull-up/down Select (n = 0~15)

[2i+1:2i]

R/W

(i=0~15)

0x0

00: Pull-up/down disable

01: Pull-up

10: Pull-down

11: Reserved

3.16.4.9. PB Pull Register 1(Default Value: 0x0000_0000)
Offset: 0x0044
Bit
31:6

Read/Write
/

Register Name: PB_PULL1
Default/Hex
/

Description
/
PB[n] Pull-up/down Select (n = 16~18)

[2i+1:2i]

R/W

(i=0~2)

0x0

00: Pull-up/down disable

01: Pull-up enable

10: Pull-down

11: Reserved

3.16.4.10. PC Configure Register 0(Default Value: 0x0000_0000)
Offset: 0x0048
Bit
Read/Write

Default/Hex

Register Name: PC_CFG0
Description

31

/

/

/

PC7 Select

30:28

27

R/W

/

0x0

/

000: Input

001: Output

010: NRB1

011: SDC2-CLK

100: /

101: /

110: /

111: /

/
PC6 Select

26:24

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: NRB0

011: SDC2-CMD

100: /

101: /

110: /

111: /

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23

/

/

/
PC5 Select

22:20

19

R/W

/

0x0

/

000: Input

001: Output

010: NRE

011: /

100: /

101: /

110: /

111: /

/
PC4 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: NCE0

011: /

100: /

101: /

110: /

111: /

/
PC3 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: NCE1

011: SPI0-CS0

100: /

101: /

110: /

111: /

/
PC2 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: NCLE

011: SPI0-CLK

100: /

101: /

110: /

111: /

/
PC1 Select

6:4

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: NALE

011: SPI0-MISO

100: /

101: /

110: /

111: /

Copyright © 2017 Next Thing Co. All Rights Reserved.

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3

/

/

/
PC0 Select

2:0

R/W

0x0

000: Input

001: Output

010: NWE

011: SPI0-MOSI

100: /

101: /

110: /

111: /

3.16.4.11. PC Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x004C
Bit
Read/Write

Default/Hex

Register Name: PC_CFG1
Description

31

/

/

/

PC15 Select

30:28

27

R/W

/

0x0

/

000: Input

001: Output

010: NDQ7

011: SDC2-D7

100: /

101: /

110: /

111: /

/
PC14 Select

26:24

23

R/W

/

0x0

/

000: Input

001: Output

010: NDQ6

011: SDC2-D6

100: /

101: /

110: /

111: /

/
PC13 Select

22:20

R/W

0x0

000: Input

001: Output

010: NDQ5

011: SDC2-D5

100: /

101: /

110: /

111: /

19

/

/

/

18:16

R/W

0x0

PC12 Select

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System

15

/

/

000: Input

001: Output

010: NDQ4

011: SDC2-D4

100: /

101: /

110: /

111: /

/
PC11 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: NDQ3

011: SDC2-D3

100: /

101: /

110: /

111: /

/
PC10 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: NDQ2

011: SDC2-D2

100: /

101: /

110: /

111: /

/
PC9 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Output

010: NDQ1

011: SDC2-D1

100: /

101: /

110: /

111: /

/
PC8 Select

2:0

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: NDQ0

011: SDC2-D0

100: /

101: /

110: /

111: /

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3.16.4.12. PC Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x0050

Register Name: PC_CFG2

Bit
31:16

Read/Write
/

Default/Hex
/

Description
/

15

/

/

/
PC19 Select

14:12

11:0

R/W

/

0x0

/

000: Input

001: Output

010: NDQS

011: /

100: /

101: /

110: /

111: /

/

3.16.4.13. PC Configure Register 3(Default Value: 0x0000_0000)
Offset: 0x0054

Register Name: PC_CFG3

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.14. PC Data Register(Default Value: 0x0000_0000)
Offset: 0x0058

Register Name: PC_DAT

Bit
31:20

Read/Write
/

Default/Hex
/

19:0

R/W

0x0

Description
/
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.

3.16.4.15. PC Multi-Driving Register 0(Default Value: 0x5555_5555)
Offset: 0x005C
Bit
Read/Write

Default/Hex

Register Name: PC_DRV0
Description
PC[n] Multi-Driving Select (n = 0~15)

[2i+1:2i]
(i=0~15)

R/W

0x1

GR8 User Manual(Version1.0)

00: Level 0

01: Level 1

10: Level 2

11: Level 3

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System
3.16.4.16. PC Multi-Driving Register 1(Default Value: 0x0000_0055)
Offset: 0x0060
Bit
Read/Write

Default/Hex

Register Name: PC_DRV1
Description

31:8

/

/

/

PC[n] Multi-Driving Select (n = 16~19)
[2i+1:2i]
(i=0~3)

R/W

0x1

00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.17. PC Pull Register 0(Default Value: 0x0000_5140)
Offset: 0x0064
Bit

Read/Write

Register Name: PC_PULL0
Default/Hex

Description
PC[n] Pull-up/down Select (n = 0~15)

[2i+1:2i]
(i=0~15)

R/W

0x5140

00: Pull-up/down disable

01: Pull-up

10: Pull-down

11: Reserved

3.16.4.18. PC Pull Register 1(Default Value: 0x0000_0016)
Register Name: PC_PULL1

Offset: 0x0068
Bit
Read/Write

Default/Hex

Description

31:8

/

/

/

PC[n] Pull-up/down Select (n = 16~19)
[2i+1:2i]
(i=0~3)

R/W

0x16

00: Pull-up/down disable

01: Pull-up

10: Pull-down

11: Reserved

3.16.4.19. PD Configure Register 0(Default Value: 0x0000_0000)
Offset: 0x006C
Bit
31

Read/Write
/

Register Name: PD_CFG0
Default/Hex
/

Description
/
PD7 Select

30:28

R/W

0x0
000: Input

GR8 User Manual(Version1.0)

001: Output

Copyright © 2017 Next Thing Co. All Rights Reserved.

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27

/

/

010: LCD_D7

011: /

100: /

101: /

110: /

111: /

/
PD6 Select

26:24

23

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D6

011: /

100: /

101: /

110: /

111: /

/
PD5 Select

22:20

19

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D5

011: UART2-RTS

100: /

101: /

110: /

111: /

/
PD4 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D4

011: UART2-CTS

100: /

101: /

110: /

111: /

/
PD3 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D3

011: UART2-RX

100: /

101: /

110: /

111: /

/
PD2 Select

10:8

R/W

0x0
000: Input

GR8 User Manual(Version1.0)

001: Output

Copyright © 2017 Next Thing Co. All Rights Reserved.

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010: LCD-D2

011: UART2-TX

100: /

101: /

110: /

111: /

7

/

/

/

6:4

R/W

0x0

/

3

/

/

/

2:0

R/W

0x0

/

3.16.4.20. PD Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x0070
Bit
31

Read/Write
/

Register Name: PD_CFG1
Default/Hex
/

Description
/
PD15 Select

30:28

27

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D15

011: /

100: /

101: /

110: /

111: /

/
PD14 Select

26:24

23

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D14

011: /

100: /

101: /

110: /

111: /

/
PD13 Select

22:20

R/W

0x0

19

/

/

18:16

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: LCD-D13

011: /

100: /

101: /

110: /

111: /

/
PD12 Select

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15

/

/

000: Input

001: Output

010: LCD-D12

011: /

100: /

101: /

110: /

111: /

/
PD11 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D11

011: /

100: /

101: /

110: /

111: /

/
PD10 Select

10:8

R/W

0x0

000: Input

001: Output

010: LCD-D10

011: /

100: /

101: /

110: /

111: /

7

/

/

/

6:4

R/W

0x0

Reserved

3

/

/

/

2:0

R/W

0x0

Reserved

3.16.4.21. PD Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x0074
Bit
31

Read/Write
/

Register Name: PD_CFG2
Default/Hex
/

Description
/
PD23 Select

30:28

R/W

0x0

000: Input

001: Output

010: LCD-D23

011: /

100: /

101: /

110: /

111: /

27

/

/

/

26:24

R/W

0x0

PD22 Select

GR8 User Manual(Version1.0)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 224

System

23

/

/

000: Input

001: Output

010: LCD-D22

011: /

100: /

101: /

110: /

111: /

/
PD21 Select

22:20

19

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D21

011: /

100: /

101: /

110: /

111: /

/
PD20 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D20

011: /

100: /

101: /

110: /

111: /

/
PD19 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: LCD-D19

011: /

100: /

101: /

110: /

111: /

/
PD18 Select

10:8

R/W

0x0

000: Input

001: Output

010: LCD-D18

011: /

100: /

101: /

110: /

111: /

7

/

/

/

6:4

R/W

0x0

Reserved

GR8 User Manual(Version1.0)

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3

/

/

/

2:0

R/W

0x0

Reserved

3.16.4.22. PD Configure Register 3(Default Value: 0x00000000)
Offset: 0x0078

Register Name: PD_CFG3

Bit
31:16

Read/Write
/

Default/Hex
/

Description
/

15

/

/

/
PD27 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: LCD_VSYNC

011: /

100: /

101: /

110: /

111: /

/
PD26 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: LCD_HSYNC

011: /

100: /

101: /

110: /

111: /

/
PD25 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Output

010: LCD_DE

011: /

100: /

101: /

110: /

111: /

/
PD24 Select

2:0

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: LCD_CLK

011: /

100: /

101: /

110: /

111: /

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System

3.16.4.23. PD Data Register(Default Value: 0x0000_0000)
Offset: 0x007C

Register Name: PD_DAT

Bit
31:28

Read/Write
/

Default/Hex
/

27:0

R/W

0x0

Description
/
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.

3.16.4.24. PD Multi-Driving Register 0(Default Value: 0x5555_5555)
Offset: 0x0080
Bit
Read/Write

Default/Hex

Register Name: PD_DRV0
Description
PD[n] Multi-Driving Select (n = 0~15)

[2i+1:2i]
(i=0~15)

R/W

0x1

00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.25. PD Multi-Driving Register 1(Default Value: 0x0055_5555)
Offset: 0x0084
Bit
31:24

Read/Write
/

Register Name: PD_DRV1
Default/Hex
/

Description
/
PD[n] Multi-Driving Select (n = 16~27)

[2i+1:2i]
(i=0~11)

R/W

0x1

00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.26. PD Pull Register 0(Default Value: 0x0000_0000)
Offset: 0x0088
Bit
Read/Write

Default/Hex

Register Name: PD_PULL0
Description
PD[n] Pull-up/down Select (n = 0~15)

[2i+1:2i]
(i=0~15)

R/W

0x0

GR8 User Manual(Version1.0)

00: Pull-up/down disable

01: Pull-up

10: Pull-down

11: Reserved

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System
3.16.4.27. PD Pull Register 1(Default Value: 0x0000_0000)
Offset: 0x008C
Bit
31:24

Read/Write
/

Register Name: PD_PULL1
Default/Hex
/

Description
/
PD[n] Pull-up/down Select (n = 16~27)

[2i+1:2i]

R/W

(i=0~11)

0x0

00: Pull-up/down disable

01: Pull-up enable

10: Pull-down

11: Reserved

3.16.4.28. PE Configure Register 0(Default Value: 0x0000_0000)
Offset: 0x0090
Bit
31

Read/Write
/

Register Name: PE_CFG0
Default/Hex
/

Description
/
PE7 Select

30:28

27

R/W

/

0x0

/

000: Input

001: Output

010: /

011: CSI-D3

100: SDC2-D3

101: /

110: /

111: /

/
PE6 Select

26:24

23

R/W

/

0x0

/

000: Input

001: Output

010: /

011: CSI-D2

100: SDC2-D2

101: /

110: /

111: /

/
PE5 Select

22:20

R/W

0x0

000: Input

001: Output

010: /

011: CSI-D1

100: SDC2-D1

101: /

110: /

111: /

19

/

/

/

18:16

R/W

0x0

PE4 Select

GR8 User Manual(Version1.0)

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System

15

/

/

000: Input

001: Output

010: /

011: CSI-D0

100: SDC2-D0

101: /

110: /

111: /

/
PE3 Select

14:12

11

R/W

/

0x0

/

000: Input

001:Output

010: /

011: CSI-VSYNC

100: SPI2-MISO

101: /

110: /

111: /

/
PE2 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Reserved

010: /

011:CSI-HSYNC

100: SPI2-MOSI

101: /

110: /

111: /

/
PE1 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Reserved

010: /

011: CSI-MCLK

100: SPI2-CLK

101: /

110: EINT15

111: /

/
PE0 Select

2:0

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Reserved

010: /

011: CSI-PCLK

100: SPI2-CS0

101: /

110: EINT14

111: /

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System
3.16.4.29. PE Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x0094

Register Name: PE_CFG1

Bit
31:16

Read/Write
/

Default/Hex
/

Description
/

15

/

/

/
PE11 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: /

011: CSI-D7

100: UART1-RX

101: /

110: /

111: /

/
PE10 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: /

011: CSI-D6

100: UART1-TX

101: /

110: /

111: /

/
PE9 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Output

010: /

011: CSI-D5

100: SDC2-CLK

101: /

110: /

111: /

/
PE8 Select

2:0

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: /

011: CSI-D4

100: SDC2-CMD

101: /

110: /

111: /

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System
3.16.4.30. PE Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x0098

Register Name: PE_CFG2

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.31. PE Configure Register 3(Default Value: 0x0000_0000)
Offset: 0x009C

Register Name: PE_CFG3

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.32. PE Data Register(Default Value: 0x0000_0000)
Offset: 0x00A0

Register Name: PE_DAT

Bit
31:12

Read/Write
/

Default/Hex
/

11:0

R/W

0x0

Description
/
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.

3.16.4.33. PE Multi-Driving Register 0(Default Value: 0x0055_5555)
Offset: 0x00A4
Bit
31:24

Read/Write
/

Register Name: PE_DRV0
Default/Hex
/

Description
/
PE[n] Multi-Driving Select (n = 0~11)

[2i+1:2i]
(i=0~11)

R/W

0x1

00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.34. PE Multi-Driving Register 1(Default Value: 0x0000_0000)
Offset: 0x00A8
Bit
31:0

Read/Write
/

Register Name: PE_DRV1
Default
/

Description
/

3.16.4.35. PE Pull Register 0(Default Value: 0x0000_0000)
Offset: 0x00AC
GR8 User Manual(Version1.0)

Register Name: PE_PULL0
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System
Bit
31:24

Read/Write
/

Default/Hex
/

Description
/
PE[n] Pull-up/down Select (n = 0~11)

[2i+1:2i]

R/W

(i=0~11)

0x0

00: Pull-up/down disable

01: Pull-up

10: Pull-down

11: Reserved

3.16.4.36. PE Pull Register 1(Default Value: 0x0000_0000)
Offset: 0x00B0
Bit
31:0

Read/Write
/

Register Name: PE_PULL1
Default/Hex
/

Description
/

3.16.4.37. PF Configure Register 0(Default Value: 0x0040_4044)
Offset: 0x00B4

Register Name: PF_CFG0

Bit
31:24

Read/Write
/

Default/Hex
/

Description
/

23

/

/

/
PF5 Select

22:20

19

R/W

/

0x4

/

000: Input

001: Output

010: SDC0-D2

011: /

100: JTAG-CK1

101: /

110: /

111: /

/
PF4 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: SDC0-D3

011: /

100: UART0-RX

101: /

110: /

111: /

/
PF3 Select

14:12

R/W

0x4

GR8 User Manual(Version1.0)

000: Input

001: Output

010: SDC0-CMD

011: /

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System

11

/

/

100: JTAG-DO1

101: /

110: /

111: /

/
PF2 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: SDC0-CLK

011: /

100: UART0-TX

101: /

110: /

111: /

/
PF1 Select

6:4

3

R/W

/

0x4

/

000: Input

001: Output

010: SDC0-D0

011: /

100: JTAG-DI1

101: /

110: /

111: /

/
PF0 Select

2:0

R/W

0x4

000: Input

001: Output

010: SDC0-D1

011: /

100: JTAG-MS1

101: /

110: /

111: /

3.16.4.38. PF Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x00B8
Bit
31:0

Read/Write
/

Register Name: PF_CFG1
Default/Hex
/

Description
/

3.16.4.39. PF Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x00BC

Register Name: PF_CFG2

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

GR8 User Manual(Version1.0)

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System
3.16.4.40. PF Configure Register 3(Default Value: 0x0000_0000)
Offset: 0x00C0

Register Name: PF_CFG3

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.41. PF Data Register(Default Value: 0x0000_0000)
Offset: 0x00C4

Register Name: PF_DAT

Bit
31:6

Read/Write
/

Default/Hex
/

5:0

R/W

0x0

Description
/
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.

3.16.4.42. PF Multi-Driving Register 0(Default Value: 0x0000_0555)
Offset: 0x00C8
Bit
31:12

Read/Write
/

Register Name: PF_DRV0
Default/Hex
/

Description
/
PF[n] Multi-Driving Select (n = 0~5)

[2i+1:2i]
(i=0~5)

R/W

0x1

00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.43. PF Multi-Driving Register 1(Default Value: 0x0000_0000)
Offset: 0x00CC
Bit
31:0

Read/Write
/

Register Name: PF_DRV1
Default/Hex
/

Description
/

3.16.4.44. PF Pull Register 0(Default Value: 0x0000_0000)
Offset: 0x00D0
Bit
Read/Write

Default/Hex

Register Name: PF_PULL0
Description

31:12

/

/

[2i+1:2i]
(i=0~5)

/

PF[n] Pull-up/down Select (n = 0~5)
R/W

0x0

GR8 User Manual(Version1.0)

00: Pull-up/down disable

01: Pull-up

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System
10: Pull-down

11: Reserved

3.16.4.45. PF Pull Register 1(Default Value: 0x0000_0000)
Offset: 0x00D4
Bit
31:0

Read/Write
/

Register Name: PF_PULL1
Default/Hex
/

Description
/

3.16.4.46. PG Configure Register 0(Default Value: 0x0000_0000)
Offset: 0x00D8
Bit
31

Read/Write
/

Register Name: PG_CFG0
Default/Hex
/

Description
/
PG7 Select

30:28

27

R/W

/

0x0

/

000: Input

001: Output

010: SDC1-D2

011: /

100: /

101: /

110: EINT7

111: /

/
PG6 Select

26:24

23

R/W

/

0x0

/

000: Input

001: Output

010: SDC1-D1

011: /

100: UART1-RTS

101: /

110: EINT6

111: /

/
PG5 Select

22:20

R/W

0x0

19

/

/

18:16

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: SDC1-D0

011: /

100: UART1-CTS

101: /

110: EINT5

111: /

/
PG4 Select

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 235

System

15

/

/

000: Input

001: Output

010: SDC1-CLK

011: /

100: UART1-RX

101: /

110: EINT4

111: /

/
PG3 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: SDC1-CMD

011: /

100: UART1-TX

101: /

110: EINT3

111: /

/
PG2 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Reserved

010: /

011: /

100: /

101: /

110: EINT2

111: /

/
PG1 Select

6:4

3

R/W

/

0x0

/

000: Input

001: Reserved

010: /

011: /

100: /

101: /

110: EINT1

111: /

/
PG0 Select

2:0

R/W

0x0

000: Input

001: Reserved

010: /

011: /

100: /

101: /

110: EINT0

111: /

3.16.4.47. PG Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x00DC
GR8 User Manual(Version1.0)

Register Name: PG_CFG1
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Page 236

System
Bit
31:24

Read/Write
/

Default/Hex
/

Description
/

23

/

/

/
PG13 Select

22:20

19

R/W

/

0x0

/

000: Input

001: Output

010: /

011: PWM1

100: /

101: /

110: EINT13

111: /

/
PG12 Select

18:16

15

R/W

/

0x0

/

000: Input

001: Output

010: /

011: UART3-RTS

100: /

101: /

110: EINT12

111: /

/
PG11 Select

14:12

11

R/W

/

0x0

/

000: Input

001: Output

010: /

011: UART3-CTS

100: /

101: /

110: EINT11

111: /

/
PG10 Select

10:8

7

R/W

/

0x0

/

000: Input

001: Output

010: /

011: UART3-RX

100: /

101: /

110: EINT10

111: /

/
PG9 Select

6:4

R/W

0x0

GR8 User Manual(Version1.0)

000: Input

001: Output

010: /

011: UART3-TX

Copyright © 2017 Next Thing Co. All Rights Reserved.

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System

3

/

/

100: /

101: /

110: EINT9

111: /

/
PG8 Select

2:0

R/W

0x0

000: Input

001: Output

010: SDC1-D3

011: /

100: /

101: /

110: EINT8

111: /

3.16.4.48. PG Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x00E0

Register Name: PG_CFG2

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.49. PG Configure Register 3(Default Value: 0x0000_0000)
Offset: 0x00E4

Register Name: PG_CFG3

Bit

Read/Write

Default/Hex

Description

31:0

/

/

/

3.16.4.50. PG Data Register(Default Value: 0x0000_0000)
Offset: 0x00E8

Register Name: PG_DAT

Bit
31:14

Read/Write
/

Default/Hex
/

13:0

R/W

0x0

Description
/
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.

3.16.4.51. PG Multi-Driving Register 0(Default Value: 0x0555_5555)
Offset: 0x00EC
Bit
Read/Write

Default/Hex

Register Name: PG_DRV0
Description

31:28

/

/

/

R/W

0x1

[2i+1:2i]
(i=0~13)

GR8 User Manual(Version1.0)

PG[n] Multi-Driving Select (n = 0~13)

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 238

System
00: Level 0

01: Level 1

10: Level 2

11: Level 3

3.16.4.52. PG Multi-Driving Register 1(Default Value: 0x0000_0000)
Offset: 0x00F0
Bit
31:0

Read/Write
/

Register Name: PG_DRV1
Default/Hex
/

Description
/

3.16.4.53. PG Pull Register 0(Default Value: 0x0000_0000)
Offset: 0x00F4
Bit
31:28

Read/Write
/

Register Name: PG_PULL0
Default/Hex
/

Description
/
PG[n] Pull-up/down Select (n = 0~13)

[2i+1:2i]
(i=0~13)

R/W

0x0

00: Pull-up/down disable

01: Pull-up

10: Pull-down

11: Reserved

3.16.4.54. PG Pull Register 1(Default Value: 0x0000_0000)
Offset: 0x00F8
Bit
31:0

Read/Write
/

Register Name: PG_PULL1
Default/Hex
/

Description
/

3.16.4.55. PIO Interrupt Configure Register 0(Default Value: 0x0000_0000)
Offset: 0x0200
Bit

Read/Write

Register Name: PIO_INT_CFG0
Default/Hex

Description
External INTn Mode (n = 0~7)

0000: Positive Edge
[4i+3:4i]
(i=0~7)

R/W

0x0

0001: Negative Edge
0010: High Level
0011: Low Level
0100: Double Edge (Positive/ Negative)
Others: Reserved

GR8 User Manual(Version1.0)

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Page 239

System
3.16.4.56. PIO Interrupt Configure Register 1(Default Value: 0x0000_0000)
Offset: 0x0204
Bit

Read/Write

Register Name: PIO_INT_CFG1
Default/Hex

Description
External INTn Mode (n = 8~15)

0000: Positive Edge
[4i+3:4i]
(i=0~7)

R/W

0001: Negative Edge

0x0

0010: High Level
0011: Low Level
0100: Double Edge (Positive/ Negative)
Others: Reserved

3.16.4.57. PIO Interrupt Configure Register 2(Default Value: 0x0000_0000)
Offset: 0x0208
Bit

Read/Write

Register Name: PIO_INT_CFG2
Default/Hex

Description
External INTn Mode (n = 16~23)

0000: Positive Edge
[4i+3:4i]
(i=0~7)

R/W

0001: Negative Edge

0x0

0010: High Level
0011: Low Level
0100: Double Edge (Positive/ Negative)
Others: Reserved

3.16.4.58. PIO Interrupt Configure Register 3(Default Value: 0x0000_0000)
Offset: 0x020C
Bit

[4i+3:4i]
(i=0~7)

Read/Write

Register Name: PIO_INT_CFG3
Default/Hex

Description
External INTn Mode (n = 24~31)

0000: Positive Edge
R/W

0x0

0001: Negative Edge
0010: High Level
0011: Low Level
0100: Double Edge (Positive/ Negative)

GR8 User Manual(Version1.0)

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Page 240

System
Others: Reserved

3.16.4.59. PIO Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x0210
Bit
Read/Write

Default/Hex

Register Name: PIO_INT_CTL
Description
External INTn Enable (n = 0~31)

[n]
(n=0~31)

R/W

0x0

0: Disable
1: Enable

3.16.4.60. PIO Interrupt Status Register(Default Value: 0x0000_0000)
Offset: 0x0214
Bit

[n]
(n=0~31)

Register Name: PIO_INT_STATUS

Read/Write

Default/Hex

R/W

0x0

Description
External INTn Pending Bit (n = 0~31)

0: No IRQ pending
1: IRQ pending

Write ‘1’ to clear it.

3.16.4.61. PIO Interrupt Debounce Register(Default Value: 0x0000_0000)
Offset: 0x0218

Register Name: PIO_INT_DEB

Bit
31:7

Read/Write
/

Default/Hex
/

6:4

R/W

0x0

3:1

/

/

Description
/
Debounce Clock Pre-scale n
The selected clock source is pre-scaled by 2n.
/
PIO Interrupt Clock Select

0

R/W

0x0

0: 32 KHz
1: 24 MHz

GR8 User Manual(Version1.0)

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Page 241

Chapter 4. Memory
This section describes the GR8 memory from three aspects:
 SDRAM Controller
 NAND Flash
 SD/MMC Controller

GR8 User Manual(Version1.0)

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Page 242

Memory

4.1. SDRAM Controller
4.1.1. Overview
256MB of Nanya DDR3 SDRAM memory is embedded in the GR8 processor. The GR8 has no external ports to
connect an additional SDRAM device.

GR8 User Manual(Version1.0)

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Memory

4.2. NAND Flash
4.2.1. Overview
The NAND Flash(NFC) supports all SLC/MLC NAND flash memory available in the market and new types can be
supported by software re-configuration as well. It can support 2 NAND flash. There are 2 separate chip select lines
(CE#) to connect up to 2 flash chips with 2 R/B signals.
The On-the-fly error correction code (ECC) is built in NFC to enhance reliability. BCH is implemented to detect and
correct up to 64 bits error per 512 or 1024 bytes data. The on chip ECC and parity checking circuitry of NFC frees
CPU for other tasks. The ECC function can be disabled by software.
The data can be transferred by DMA or by a CPU memory-mapped IO method. The NFC provides automatic timing
control to read or writeto the external Flash. The NFC maintains the proper relativity for the CLE, CE# and ALE
control signal lines. Three modes are supported for serial read access: Mode 0 is the conventional serial access,
Mode 1 for EDO type, and Mode 2 is for the extension EDO type. In addition, NFC can monitor the status of the
R/B# signal line.
Block management and wear leveling management are implemented in software.
Features:
●

Supports SLC/MLC flash and EF-NAND memory

●

Software configure seed to randomize engine

●

Software configure method for adaptability to a variety of system and memory types

●

Supports 8-bit data bus width

●

Supports 1024, 2048, 4096, 8192, 16384 bytes size per page

●

Up to 2 flash chips which are controlled by NFC_CEx#

●

Supports Conventional and EDO serial access method for serial reading Flash

●

On-the-fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes

●

Corrected Error bits number information report

●

ECC automatic disable function for all 0xff data

●

NFC status information is reported by its registers

●

Supports interrupt

●

One Command FIFO

●

Supports external DMA for data transfer

●

Two 256x32-bit RAM for Pipeline Procession

●

Supports SDR, DDR and Toggle 1.0 NAND

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Memory

4.2.2. Block Diagram

Figure 4-1. NFC Block Diagram

4.2.3. NFC Timing Diagram
Typically, there are two kinds of the serial access method. One is the conventional method that fetches data on
the rising edge of an NFC_RE# signal line, and the other is the EDO type that fetches data at the next falling edge
of an NFC_RE# signal line.

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Memory

NFC_CLE
t3

t4

NFC_CE#
NFC_WE#

t12

t14
sample 0

sample n-1

NFC_RE#
t13
NFC_ALE
t10
NFC_RB#
NFC_IOx

Data(0)

Data(n-1)

Figure 4-2. Conventional Serial Access Cycle Diagram (SAM0)

NFC_CLE
t3

t4

NFC_CE#
NFC_WE#
t14
t12

sample 0

NFC_RE#
t13
NFC_ALE
t10
NFC_RB#
NFC_IOx

Data(0)

Data(n-1)

Figure 4-3. EDO Type Serial Access after Read Cycle (SAM1)

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Memory

NFC_CLE
t3
NFC_CE#
NFC_WE#
sample
t14
t12
NFC_RE#
t13
NFC_ALE
t10
NFC_RB#
NFC_IOx

Data(0)

Data(n-1)

Figure 4-4. Extending EDO Type Serial Access Mode (SAM2)

t1

t2

t3

t4

NFC_CLE

NFC_CE#
t5
NFC_WE#
NFC_RE#
t7

t11

NFC_ALE
t8
NFC_IOx

t9
COMMAND

Figure 4-5. Command Latch Cycle

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Memory

t1
NFC_CLE
t3

t4

NFC_CE#
t15
t5

t6

NFC_WE#
NFC_RE#
t7

t11

NFC_ALE
t8
NFC_IOx

t9
Addr(0)

Addr(n-1)

Figure 4-6. Address Latch Cycle

t1

t2

t3

t4

NFC_CLE

NFC_CE#
t15
t5

t6

NFC_WE#
NFC_RE#
t7
NFC_ALE
t8
NFC_IOx

t9
Data(0)

Data(n-1)

Figure 4-7. Write Data to Flash Cycle

NFC_CLE
NFC_CE#
NFC_WE#
t13
t12
t14
NFC_RE#
NFC_ALE
t16
NFC_RB#
NFC_IOx

cmd

GR8 User Manual(Version1.0)

d(0)

d(1)

d(n-1)

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Memory
Figure 4-8. Waiting R/B# Ready Diagram

NFC_CLE
NFC_CE#
NFC_WE#
t17
NFC_RE#
NFC_ALE
NFC_RB#
NFC_IOx

cmd

d(0)

d(1)

d(n-1)

Figure 4-9. WE # High to RE# Low Timing Diagram

NFC_CLE
NFC_CE#
NFC_WE#
t18
NFC_RE#
NFC_ALE
NFC_RB#
NFC_IOx

d(0)

d(1)

d(n-1)

05h

col1

col2

E0h

Figure 4-10. RE # High to WE# Low Timing Diagram

NFC_CLE
NFC_CE#
T19
NFC_WE#
NFC_RE#
NFC_ALE
NFC_RB#
NFC_IOx

addr2

addr3

d(0)

d(1)

d(2)

d(n-1)

Figure 4-11. Address to Data Loading Timing Diagram
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Memory

Timing Cycle List:
ID
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16

Parameter
Timing Notes
NFC_CLE setup time
T
NFC_CLE hold time
T
NFC_CE setup time
T
NFC_CE hold time
T
NFC_WE# pulse width
T
NFC_WE# hold time
T
NFC_ALE setup time
T
Data setup time
T
Data hold time
T
Ready to NFC_RE# low
3T
NFC_ALE hold time
T
NFC_RE# pulse width
T
NFC_RE# hold time
T
Read cycle time
2T
Write cycle time
2T
NFC_WE# high to R/B#
tWB
Specified by timing configure register(NFC_TIMING_CFG)
busy
T17
NFC_WE# high to
tWHR
Specified by timing configure register(NFC_TIMING_CFG)
NFC_RE# low
T18
NFC_RE# high to
tRHW
Specified by timing configure register(NFC_TIMING_CFG)
NFC_WE# low
T19
Address to Data Loading tADL
Specified by timing configure register(NFC_TIMING_CFG)
time
Note: T is the clock period duration of NFC_CLK (x2).

4.2.4. NFC Read and Write Diagram

Figure 4-12. Page Read Command Diagram

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Memory

Figure 4-13. Page Program Diagram

Figure 4-14. EF-NAND Page Read Diagram

Figure 4-15. Interleave Page Read Diagram
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Memory

4.3. SD/MMC Controller
4.3.1. Overview
The SD/MMC Host Controller(SMHC) provides three controllers including SD card, MMC and SDIO device. SMHC
controls the read/write operations on the secure digital(SD) card, multimedia card(MMC), and supports extended
Wi-Fi devices based on the secure digital input/output(SDIO) protocol.
Features:
●

Supports Secure Digital memory protocol commands (up to SD2.0)

●

Supports Secure Digital I/O protocol commands(up to SDIO2.0)

●

Supports Multimedia Card protocol commands (up to MMC4.4)

●

1-bit,4-bit,8-bit data bus width

●

Supports block size of 1 to 65535 bytes

●

Supports hardware CRC generation and error detection

●

Supports descriptor-based internal DMA controller

●

Internal 16x32-bit (64 bytes total) FIFO for data transfer

4.3.2. SD/MMC Timing Diagram
Please refer to relative specifications listed below:
●

Physical Layer Specification Ver2.00 Final

●

SDIO Specification Ver2.00

●

Multimedia Cards (MMC – version 4.2)

●

JEDEC Standard – JESD84-44, Embedded Multimedia Card (eMMC) Card Product Standard

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Chapter 5. Image
This section describes the image input GR8 supports:
 CSI

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Image

5.1. CSI
5.1.1. Overview
The CMOS Sensor Interface (CSI) is an image or video input control module which can receive image or video data
by a digital camera interface and high speed serial interface.
●

Supports 8-bit digital camera interface

●

Supports BT656 interface

●

Maximum still capture resolution for parallel interface to 5M

●

Maximum video capture resolution for parallel interface to 1080p@30fps

●

Maximum pixel clock to 150MHz

System BUS

5.1.2. CSI Block Diagram

FIFO 2
DMA

FIFO 1

PCLK
MCLK
HS
VS

CSI
Control
Module

Data[7:0]

Figure 5-1. CSI Block Diagram

5.1.3. CCIR656 Format
5.1.3.1. Header Data Bit Definition
Data Bit
CS D[7] (MSB)
CS D[6]
CS D[5]
CS D[4]
CS D[3]
CS D[2]
CS D[1]
CS D[0]

First Word
1
1
1
1
1
1
1
1

GR8 User Manual(Version1.0)

Second Word
0
0
0
0
0
0
0
0

Third Word
0
0
0
0
0
0
0
0

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Fourth Word
1
F
V
H
P3
P2
P1
P0

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Image
5.1.3.2. CCIR656 Header Decode
Decode
Field 1 start of active video (SAV)
Field 1 end of active video (EAV)
Field 1 SAV (digital blanking)
Field 1 EAV (digital blanking)
Field 2 SAV
Field 2 EAV
Field 2 SAV (digital blanking)
Field 2 EAV (digital blanking)

F
0
0
0
0
1
1
1
1

V
0
0
1
1
0
0
1
1

H
0
1
0
1
0
1
0
1

P3
0
1
1
0
0
1
1
0

P2
0
1
0
1
1
0
1
0

P1
0
0
1
1
1
1
0
0

P0
0
1
1
0
1
0
0
1

5.1.4. CSI Timing Diagram

Figure 5-2. Vref= Positive; Href= Positive

Figure 5-3. Vertical Size Setting

Figure 5-4. Horizontal Size Setting and Pixel Clock Timing (Href= positive)

5.1.5. CSI Register List
Module Name
GR8 User Manual(Version1.0)

Base Address
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Image
CSI

0x01C09000

Register Name

Offset

Description

CSI_EN_REG
CSI_CFG_REG
CSI_CPT_CTRL_REG
CSI_FIFO0_BUF_A_ADDR_REG
CSI_FIFO0_ BUF_B_ADDR_REG
CSI_FIFO1_ BUF_A_ADDR_REG
CSI_FIFO1_ BUF_B_ADDR_REG
CSI_BUF_CTRL_REG
CSI_STA_REG
CSI_INT_EN_REG
CSI_INT_STA_REG
CSI_WIN_CTRL_W_REG
CSI_WIN_CTRL_H_REG
CSI_BUF_LEN_REG

0x0000
0x0004
0x0008
0x0010
0x0014
0x0018
0x001C
0x0028
0x002C
0x0030
0x0034
0x0040
0x0044
0x0048

CSI Enable Register
CSI Configuration Register
CSI Capture Control Register
CSI FIFO0 Buffer A Register
CSI FIFO0 Buffer B Register
CSI FIFO1 Buffer A Register
CSI FIFO1 Buffer B Register
CSI Buffer Control Register
CSI Status Register
CSI Interrupt Enable Register
CSI Interrupt Status Register
CSI Window Width Control Register
CSI Window Height Control Register
CSI Buffer Length Register

5.1.6. CSI Register Description
5.1.6.1. CSI Enable Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write
31:1
/

Default/Hex
/

Name: CSI_EN_REG
Description
Reserved
EN
CSI Enable

0

R/W

0x0
0: Reset and disable
1: Enable

5.1.6.2. CSI Configuration Register(Default Value: 0x0000_0200)
Offset: 0x0004
Bit
Read/Write
31:23
/

Default/Hex
/

Register Name: CSI_CFG_REG
Description
Reserved
IN_FMT

22:20

R/W

0x0

Input data format

000: RAW stream

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Image
010: CCIR656
011: YUV422
others: reserved
OUT_FMT
Output data format
When the input format is set RAW stream
0000: pass-through

When the input format is set CCIR656 interface
0000: field planar YCbCr 422
0001: field planar YCbCr 420
0010: frame planar YCbCr 420
0011: frame planar YCbCr 422
0100: field planar YCbCr 422 UV combined
0101: field planar YCbCr 420 UV combined
0110: frame planar YCbCr 420 UV combined
0111: frame planar YCbCr 422 UV combined
19:16

R/W

0x0

1111: interlaced interleaved YCbCr422. In this mode, capturing
interlaced input and output the interlaced fields from individual ports.
Field 1 data will be written to FIFO0 output buffer and field 2 data will
be written to FIFO1 output buffer.
1000: field MB YCbCr 422
1001: field MB YCbCr 420
1010: frame MB YCbCr 420
1011: frame MB YCbCr 422

When the input format is set YUV422
0000: planar YUV 422
0001: planar YUV 420
0100: planar YUV 422 UV combined
0101: planar YUV 420 UV combined
1000: MB YUV 422
1001: MB YUV 420
15:12

/

/

11:10

R/W

0x0

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Reserved
FIELD_SEL
Field selection. Applies to CCIR656 interface only.

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Image

00: start capturing with field odd.
01: start capturing with field even.
10: start capturing with either field.
11: reserved
DATA_SEQ
Input data sequence, only valid for YUV422 mode.

9:8

R/W

0x2

00: YUYV
01: YVYU
10: UYVY
11: VYUY

7:3

/

/

Reserved
VSYNC_POL
Vref polarity

2

R/W

0

0: negative
1: positive

This register is not applied to CCIR656 interface.
HSYNC_POL
Href polarity

1

R/W

0

0: negative
1: positive

This register is not applied to CCIR656 interface.
PCLK_POL
Data clock type
0

R/W

0
0: active in falling edge
1: active in rising edge

5.1.6.3. CSI Capture Control Register(Default Value: 0x0000_0000)
Offset: 0x0008
GR8 User Manual(Version1.0)

Register Name: CSI_CPT_CTRL_REG
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Image
Bit
31:2

Read/Write
/

Default/Hex
/

Description
/
VIDEO_CAP_CTRL
Video capture control: Capture the video image data stream.

0: Disable video capture
1

R/W

If video capture is in progress, the CSI stops capturing image data at
the end of the current frame, and all of the current frame data is
written to output FIFO.

0x0

1: Enable video capture

The CSI starts capturing image data at the start of the next frame.
STILL_CAP_CTRL
Still capture control: Capture a single still image frame.

0: Disable still capture.
0

W

0x0

1: Enable still capture

The CSI module starts capturing image data at the start of the next
frame. The CSI module captures only one frame of image data. This bit
is self cleared and always reads as a 0.

5.1.6.4. CSI FIFO0 Buffer A Register(Default Value: 0x0000_0000)
Offset: 0x0010
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: CSI_FIFO0_BUF_A_ADDR_REG
Description
FIFO0_BUF_A
FIFO0 output buffer-A address

5.1.6.5. CSI FIFO0 Buffer B Register(Default Value: 0x0000_0000)
Offset: 0x0014
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: CSI_FIFO0_BUF_B_ADDR_REG
Description
FIFO0_BUF_B
FIFO0 output buffer-B address

5.1.6.6. CSI FIFO1 Buffer A Register(Default Value: 0x0000_0000)
Offset: 0x0018
GR8 User Manual(Version1.0)

Register Name: CSI_FIFO1_BUF_A_ADDR_REG
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Image
Bit

Read/Write

Default/Hex

31:0

R/W

0x0

Description
FIFO1_BUF_A
FIFO1 output buffer-A address

5.1.6.7. CSI FIFO1 Buffer B Register(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
Read/Write

Default/Hex

31:00

0x0

R/W

Register Name: CSI_FIFO1_BUF_B_ADDR_REG
Description
FIFO1_BUF_B
FIFO1 output buffer-B address

5.1.6.8. CSI Buffer Control Register(Default Value: 0x0000_0000)
Offset: 0x0028
Bit
Read/Write
31:2
/

Default/Hex
/

Register Name: CSI_BUF_CTRL_REG
Description
/
DBS
output buffer selected status

1

R

0x0
0: Selected output buffer-A
1: Selected output buffer-B
DBE
Double buffer mode enable

0

R/W

0: disable

0x0

1: enable

If the double buffer mode is disabled, the buffer-A will be always
selected by CSI module.

5.1.6.9. CSI Status Register(Default Value: 0x0000_0000)
Offset: 0x002C
Bit
Read/Write

Default/Hex

Register Name: CSI_STA_REG
Description
LUM_STAT_VALUE
luminance statistical value

31:8

R

0x0

When frame done interrupt flag come, value is ready and will last until
next frame done.
For raw data, value = (G>>1+R+G)>>8

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Image
For yuv422, value = Y>>8
7:2

/

/

Reserved
VIDEO_CAP_ON
Video capture in progress

1

R

Indicates the CSI is capturing video image data (multiple frames). The
bit is set at the start of the first frame after enabling video capture.
When software disables video capture, it clears itself after the last
pixel of the current frame is captured.

0x0

STILL_CPT_ON
Still capture in progress
0

R

Indicates the CSI is capturing still image data (single frame). The bit is
set at the start of the first frame after enabling still frame capture. It
is self-cleared after the last pixel of the first frame is captured.

0x0

For CCIR656 interface, if the output format is frame planar YCbCr 420
mode, the frame end means the field2 end, and the other frame end
means filed end.

5.1.6.10. CSI Interrupt Enable Register(Default Value: 0x0000_0000)
Offset: 0x0030
Bit
Read/Write
31:8
/

Default/Hex
/

Register Name: CSI_INT_EN_REG
Description
/
VSYNC_FLAG
vsync flag

7

R/W

0x0

The bit is set when vsync comes. Now load the buffer address for the
coming frame. So, after this irq comes, changes to the buffer address
can only affect next frame.
HB_OF

6

R/W

0x0

Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.
PRT_ERR

5

R/W

0x0

Protection error
Indicates a protection error has been detected. Applies only when the
656 protocol is selected.

4

/

/

Reserved
FIFO0_OF

3

R/W

0x0

FIFO1 overflow
The bit is set when the FIFO 1 overflows.

2

R/W

0x0

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FIFO0 overflow

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Image
The bit is set when the FIFO 0 overflows.
FRM_DONE
Frame done
1

R/W

0x0

Indicates the CSI finishes capturing an image frame. Applied to video
capture mode. The bit is set after each completed frame capturing
data is written to buffer as long as video capture remains enabled.
CPT_DONE
Capture done
Indicates the CSI has completed capturing the image data.

0

R/W

For still capture, the bit is set when one frame data has been written
to buffer.

0x0

For video capture, the bit is set when the last frame has been written
to buffer after video capture is disabled.
For CCIR656 interface, if the output format is frame planar YCbCr 420
mode, the frame end means the field2 end, and the other frame end
means field end.

5.1.6.11. CSI Interrupt Status Register(Default Value: 0x0000_0000)
Offset: 0x0034
Bit
Read/Write
31:8
/

Default/Hex
/

7

R/W

0x0

6

R/W

0x0

5

R/W

0x0

4

/

/

3

R/W

0x0

2

R/W

0x0

1

R/W

0x0

0

R/W

0x0

GR8 User Manual(Version1.0)

Register Name: CSI_INT_STA_REG
Description
/
VSYNC_FLAG
vsync flag
HB_OF
Hblank FIFO overflow
PRT_ERR
Protection error
/
FIFO1 OF
FIFO1 overflow
FIFO0_OF
FIFO0 overflow
FRM_DONE
Frame done
CPT_DONE
Capture done

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Image
5.1.6.12. CSI Window Width Control Register(Default Value: 0x0500_0000)
Offset: 0x0040
Bit
Read/Write

Default/Hex

Register Name: CSI_WIN_CTRL_W_REG
Description

31:29

/

/

/

28:16

R/W

0x500

15:13

/

/

12:0

R/W

0x0

ACTIVE_LEN
Horizontal pixel clock length. Valid pixel clocks of a line.
/
ACTIVE_START
Horizontal pixel clock start. Pixel data is valid from this clock.

5.1.6.13. CSI Window Height Control Register(Default Value: 0x01E0_0000)
Offset: 0x0044
Bit
Read/Write

Default/Hex

Register Name: CSI_WIN_CTRL_H_REG
Description

31:29

/

/

/

28:16

R/W

0x1E0

15:13

/

/

12:0

R/W

0x0

ACTIVE_LEN
Vertical line length. Valid line number of a frame.
Reserved
ACTIVE_START
Vertical line start. Data is valid from this line.

5.1.6.14. CSI Buffer Length Register(Default Value: 0x0000_0280)
Offset: 0x0048
Bit
Read/Write

Default/Hex

Register Name: CSI_BUF_LEN_REG
Description

31:13

/

/

/

BUFF_LEN
12:0

R/W

0x280

Buffer Length
Buffer length of a line. The unit is byte.

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Chapter 6. Display
This chapter describes GR8’s display system from the following perspectives:
 Display Engine Front End (DEFE)
 Display Engine Back End (DEBE)
 TCON
 IEP

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Display

6.1. Display Engine Front End (DEFE)
6.1.1. Overview
The Display Engine Front End (DEFE) performs image capture/driver, video/graphic scale, format conversion and
color space conversion. It is composed of a DMA controller, input controller, scaler, color space converter and
output controller.
Features:
●

Output scan type: interlace/progressive

●

Input format: YUV444/YUV422/YUV420/YUV411/RGB

●

Direct display output format: RGB

●

Write back output format: RGB/YUV444/YUV420/YUV422/YUV411

●

3 channel scaling pipelines for scaling up/down

●

Programmable source image size from 8x4 to 2048x2048 resolution

●

Programmable destination image size from 8x4 to 2048x2048 resolution

●

4 tap scale filter in horizontal and vertical direction

●

32 Programmable coefficients for each tap

●

Color space conversion between YUV and RGB

●

Supports direct display and write back to memory

6.1.2. DEFE Block Diagram
Ahb bus

Register file

Mbus
scaler

CSC

Output
control

display

DMAC

Figure 6-1. DEFE Block Diagram

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Display

6.1.3. DEFE Register List
Module Name
DEFE0

Base Address
0x01E00000

Register Name

Offset

Description

DEFE_EN_REG
DEFE_FRM_CTRL_REG
DEFE_BYPASS_REG
DEFE_AGTH_SEL_REG
DEFE_LINT_CTRL_REG
DEFE_BUF_ADDR0_REG
DEFE_BUF_ADDR1_REG
DEFE_BUF_ADDR1_REG
DEFE_FIELD_CTRL_REG
DEFE_TB_OFF0_REG
DEFE_TB_OFF1_REG
DEFE_TB_OFF2_REG
DEFE_LINESTRD0_REG
DEFE_LINESTRD1_REG
DEFE_LINESTRD2_REG
DEFE_INPUT_FMT_REG
DEFE_WB_ADDR0_REG
DEFE_OUTPUT_FMT_REG
DEFE_INT_EN_REG
DEFE_INT_STATUS_REG
DEFE_STATUS_REG
DEFE_CSC_COEF00_REG
DEFE_CSC_COEF01_REG
DEFE_CSC_COEF02_REG
DEFE_CSC_COEF03_REG
DEFE_CSC_COEF10_REG
DEFE_CSC_COEF11_REG
DEFE_CSC_COEF12_REG
DEFE_CSC_COEF13_REG
DEFE_CSC_COEF20_REG
DEFE_CSC_COEF21_REG
DEFE_CSC_COEF22_REG
DEFE_CSC_COEF23_REG
DEFE_WB_LINESTRD_EN_REG
DEFE_WB_LINESTRD0_REG
DEFE_CH0_INSIZE_REG
DEFE_CH0_OUTSIZE_REG
DEFE_CH0_HORZFACT_REG

0x0000
0x0004
0x0008
0x000C
0x0010
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x0040
0x0044
0x0048
0x004C
0x0050
0x005C
0x0060
0x0064
0x0068
0x0070
0x0074
0x0078
0x007C
0x0080
0x0084
0x0088
0x008C
0x0090
0x0094
0x0098
0x009C
0x00D0
0x00D4
0x0100
0x0104
0x0108

DEFE Module Enable Register
DEFE Frame Process Control Register
DEFE CSC By-Pass Register
DEFE Algorithm Selection Register
DEFE Line Interrupt Control Register
DEFE Input Channel 0 Buffer Address Register
DEFE Input Channel 1 Buffer Address Register
DEFE Input Channel 2 Buffer Address Register
DEFE Field Sequence Register
DEFE Channel 0 Tile-Based Offset Register
DEFE Channel 1 Tile-Based Offset Register
DEFE Channel 2 Tile-Based Offset Register
DEFE Channel 0 Line Stride Register
DEFE Channel 1 Line Stride Register
DEFE Channel 2 Line Stride Register
DEFE Input Format Register
DEFE Channel 3 Write Back Address Register
DEFE Output Format Register
DEFE Interrupt Enable Register
DEFE Interrupt Status Register
DEFE Status Register
DEFE CSC Coefficient 00 Register
DEFE CSC Coefficient 01 Register
DEFE CSC Coefficient 02 Register
DEFE CSC Coefficient 03 Register
DEFE CSC Coefficient 10 Register
DEFE CSC Coefficient 11 Register
DEFE CSC Coefficient 12 Register
DEFE CSC Coefficient 13 Register
DEFE CSC Coefficient 20 Register
DEFE CSC Coefficient 21 Register
DEFE CSC Coefficient 22 Register
DEFE CSC Coefficient 23 Register
DEFE Write Back Line Stride Enable Register
DEFE Write Back Channel Line Stride Register
DEFE Channel 0 Input Size Register
DEFE Channel 0 Output Size Register
DEFE Channel 0 Horizontal Factor Register

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Display
DEFE_CH0_VERTFACT_REG
DEFE_CH0_HORZPHASE_REG
DEFE_CH0_VERTPHASE0_REG
DEFE_CH0_VERTPHASE1_REG
DEFE_CH1_INSIZE_REG
DEFE_CH1_OUTSIZE_REG
DEFE_CH1_HORZFACT_REG
DEFE_CH1_VERTFACT_REG
DEFE_CH1_HORZPHASE_REG
DEFE_CH1_VERTPHASE0_REG
DEFE_CH1_VERTPHASE1_REG
DEFE_CH0_HORZCOEF_REGN

DEFE_CH0_VERTCOEF_REGN

DEFE_CH1_HORZCOEF_REGN

DEFE_CH1_VERTCOEF_REGN

0x010C
0x0110
0x0114
0x0118
0x0200
0x0204
0x0208
0x020C
0x0210
0x0214
0x0218
0x0400+N*0x04
(N=0:31)

DEFE Channel 0 Vertical factor Register
DEFE Channel 0 Horizontal Initial Phase Register
DEFE Channel 0 Vertical Initial Phase 0 Register
DEFE Channel 0 Vertical Initial Phase 1 Register
DEFE Channel 1 Input Size Register
DEFE Channel 1 Output Size Register
DEFE Channel 1 Horizontal Factor Register
DEFE Channel 1 Vertical factor Register
DEFE Channel 1 Horizontal Initial Phase Register
DEFE Channel 1 Vertical Initial Phase 0 Register
DEFE Channel 1 Vertical Initial Phase 1 Register
DEFE Channel 0 Horizontal Filter Coefficient Register

0x0500+N*0x04
(N=0:31)

DEFE Channel 0 Vertical Filter Coefficient Register

0x0600+N*0x04
(N=0:31)

DEFE Channel 1 Horizontal Filter Coefficient Register

0x0700+N*0x04
(N=0:31)

DEFE Channel 1 Vertical Filter Coefficient Register

Note: Registers 0x0008~0x0218 except status registers are double buffered. when a new frame process starts and
the buffered register configuration ready bit in frame process control register is set, the value of corresponding
internal configuration register will be refreshed by this register, and programmers always cannot read the value
of corresponding internal register.

6.1.4. DEFE Register Description
6.1.4.1. DEFE Module Enable Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write
31:1
/

Default/Hex
/

Register Name: DEFE_EN_REG
Description
/
EN
DEFE enable

0: Disable
0

R/W

0x0

1: Enable

When DEFE enable bit is disabled, the clock of DEFE module will be
disabled.
If this bit transits is from 0 to 1, the frame process control register and
the interrupt enable register will be initialized to default value, and the
GR8 User Manual(Version1.0)

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Display
state machine of the module is reset.

6.1.4.2. DEFE Frame Process Control Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write
31:24
/

Default/Hex
/

Register Name: DEFE_FRM_CTRL_REG
Description
/
COEF_ACCESS_CTRL
Fir coef ram access control

23

R/W

0x0

0: CPU does not access fir coef ram
1: CPU will access fir coef ram

This bit will be set to 1 before CPU accesses fir coef ram
22:17

/

/

/
FRM_START
Frame start & reset control

0: reset
16

R/W

0x0

1: start

If the bit is written to zero, the whole state machine and data paths of
DEFE module will be reset.
When the bit is written to 1, DEFE will start a new frame process.
15:12

/

/

/
OUT_CTRL
DEFE output control

11

R/W

0x0

0: enable DEFE output to DEBE
1: disable DEFE output to DEBE

If DEFE write back function is enabled, DEFE output to DEBE is not
recommended.
10:3

/

/

/
WB_EN

2

R/W

0x0

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Write back enable

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Display
0: Disable
1: Enable

If output to DEBE is enabled, the writing back process will start when
write back enable bit is set and a new frame processing begins. The bit
will be self-cleared when writing-back frame process starts.
1

/

/

/
REG_RDY_EN
Register ready enable

0: not ready
1: registers configuration ready
0

R/W

0x0
Just as filter coefficients configuration, in order to ensure the display
to be correct, the correlative display configuration registers are
buffered too, and programmers also can change the value of
correlative registers in any time. When the registers setting is finished,
the programmer should set the bit if the new configuration is needed
in next scaling frame.
When the new frame starts, the bit will also be self-cleared.

6.1.4.3. DEFE CSC By-Pass Register(Default Value: 0x0000_0000)
Offset: 0x0008
Bit
Read/Write
31:2
/

Default/Hex
/

Register Name: DEFE_BYPASS_REG
Description
/
CSC_BYPASS_EN
CSC by-pass enable

0: CSC enable
1

R/W

0x0

1: CSC will be by-passed

Actually, in order to ensure the module working to be correct, this bit
only can be set when input data format is the same as output data
format (both YUV or both RGB)
0

/

/

/

6.1.4.4. DEFE Algorithm Selection Register(Default Value: 0x0000_0000)
Offset: 0x000C
GR8 User Manual(Version1.0)

Register Name: DEFE_AGTH_SEL_REG
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Display
Bit

Read/Write

Default/Hex

Description

31:9

/

/

/
LINEBUF_AGTH
DEFE line buffer algorithm select

8

R/W

0x0
0: horizontal filtered result
1: original data

7:0

/

/

/

6.1.4.5. DEFE Line Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x0010
Bit
Read/Write

Default/Hex

Register Name: DEFE_LINT_CTRL_REG
Description

31:28

/

/

/

27:16

R

0x0

CURRENT_LINE
FIELD_SEL
Field select

15

R/W

0x0
0: each field
1: end field(field counter in reg0x2c)

14:13

/

/

12:0

R/W

0x0

/
TRIG_LINE
Trigger line number of line interrupt

6.1.4.6. DEFE Input Channel 0 Buffer Address Register(Default Value: 0x0000_0000)
Offset: 0x0020
Bit
Read/Write

Default/Hex

Register Name: DEFE_BUF_ADDR0_REG
Description
BUF_ADDR
DEFE frame buffer address
In tile-based type:

31:0

R/W

0x0

The address is the start address of the line in the first tile used to
generate output frame.
In non-tile-based type:
The address is the start address of the first line.

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Display
6.1.4.7. DEFE Input Channel 1 Buffer Address Register(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
Read/Write

Default/Hex

Register Name: DEFE_BUF_ADDR1_REG
Description
BUF_ADDR
DEFE frame buffer address
In tile-based type:

31:0

R/W

0x0

The address is the start address of the line in the first tile used to
generate output frame.
In non-tile-based type:
The address is the start address of the first line.

6.1.4.8. DEFE Input Channel 2 Buffer Address Register(Default Value: 0x0000_0000)
Offset: 0x0028
Bit
Read/Write

Default/Hex

Register Name: DEFE_BUF_ADDR2_REG
Description
BUF_ADDR
DEFE frame buffer address
In tile-based type:

31:0

R/W

0x0

The address is the start address of the line in the first tile used to
generate output frame.
In non-tile-based type:
The address is the start address of the first line.

6.1.4.9. DEFE Field Sequence Register(Default Value: 0x0000_0000)
Offset: 0x002C
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: DEFE_FIELD_CTRL_REG
Description
/
FIELD_LOOP_MOD
Field loop mode

12

R/W

0x0
0: the last field
1: the full frame

11

/

/

/
VALID_FIELD_CNT

10:8

R/W

0x0

Valid field counter bit
the valid value = this value + 1

7:0

R/W

0x0

GR8 User Manual(Version1.0)

FIELD_CNT

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Display
Field counter
each bit specifies a field to display

0: top field
1: bottom field

6.1.4.10. DEFE Channel 0 Tile-Based Offset Register(Default Value: 0x0000_0000)
Offset: 0x0030
Bit
Read/Write
31:21
/

Default/Hex
/

20:16

R/W

0x0

15:13

/

/

12:8

R/W

0x0

7:5

/

/

4:0

R/W

0x0

Register Name: DEFE_TB_OFF0_REG
Description
/
X_OFFSET1
The x offset of the bottom-right point in the end tile
/
Y_OFFSET0
The y offset of the top-left point in the first tile
/
X_OFFSET0
The x offset of the top-left point in the first tile

6.1.4.11. DEFE Channel 1 Tile-Based Offset Register(Default Value: 0x0000_0000)
Offset: 0x0034
Bit
Read/Write

Default/Hex

Register Name: DEFE_TB_OFF1_REG
Description

31:21

/

/

/

20:16

R/W

0x0

15:13

/

/

12:8

R/W

0x0

7:5

/

/

4:0

R/W

0x0

X_OFFSET1
The x offset of the bottom-right point in the end tile
/
Y_OFFSET0
The y offset of the top-left point in the first tile
/
X_OFFSET0
The x offset of the top-left point in the first tile

6.1.4.12. DEFE Channel 2 Tile-Based Offset Register(Default Value: 0x0000_0000)
Offset: 0x0038
GR8 User Manual(Version1.0)

Register Name: DEFE_TB_OFF2_REG
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Display
Bit

Read/Write

Default/Hex

Description

31:21

/

/

/

20:16

R/W

0x0

15:13

/

/

12:8

R/W

0x0

7:5

/

/

4:0

R/W

0x0

X_OFFSET1
The x offset of the bottom-right point in the end tile
/
Y_OFFSET0
The y offset of the top-left point in the first tile
/
X_OFFSET0
The x offset of the top-left point in the first tile

6.1.4.13. DEFE Channel 0 Line Stride Register(Default Value: 0x0000_0000)
Offset: 0x0040
Bit
Read/Write

31:0

R/W

Default/Hex

Register Name: DEFE_LINESTRD0_REG
Description
LINE_STRIDE
In tile-based type, the stride length is the distance from the start of
the end line in one tile to the start of the first line in next tile (here
next tile is in vertical direction).

0x0

In non-tile-based type, the stride length is the distance from the start
of one line to the start of the next line.

6.1.4.14. DEFE Channel 1 Line Stride Register(Default Value: 0x0000_0000)
Offset: 0x0044
Bit
Read/Write

Default/Hex

Register Name: DEFE_LINESTRD1_REG
Description
LINE_STRIDE

31:0

R/W

In tile-based type, the stride length is the distance from the start of
the end line in one tile to the start of the first line in next tile (here
next tile is in vertical direction).

0x0

In non- tile-based type, the stride length is the distance from the start
of one line to the start of the next line.

6.1.4.15. DEFE Channel 2 Line Stride Register(Default Value: 0x0000_0000)
Offset: 0x0048
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: DEFE_LINESTRD2_REG
Description

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Display
LINE_STRIDE

31:0

R/W

In tile-based type, the stride length is the distance from the start of
the end line in one tile to the start of the first line in next tile (here
next tile is in vertical direction).

0x0

In non- tile-based type, the stride length is the distance from the
start of one line to the start of the next line.

6.1.4.16. DEFE Input Format Register(Default Value: 0x0000_0000)
Offset: 0x004C
Bit
Read/Write
31:17
/

Default/Hex
/

Register Name: DEFE_INPUT_FMT_REG
Description
/
BYTE_SEQ
Input data byte sequence selection

16

R/W

0x0
0: P3P2P1P0(word)
1: P0P1P2P3(word)

15:13

/

/

/
SCAN_MOD
Scanning Mode selection

12

R/W

0x0
0: non-interlace
1: interlace

11

/

/

/
DATA_MOD
Input data mode selection

000: non-tile-based planar data
10:8

R/W

0x0

001: interleaved data
010: non- tile-based UV combined data
100: tile-based planar data
110: tile-based UV combined data
other: reserved

7

/

/

6:4

R/W

0x0

GR8 User Manual(Version1.0)

/
DATA_FMT
Input component data format

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Display

In non-tile-based planar data mode:
000: YUV 4:4:4
001: YUV 4:2:2
010: YUV 4:2:0
011: YUV 4:1:1
100: CSI RGB data
101: RGB888
Other: Reserved

In interleaved data mode:
000: YUV 4:4:4
001: YUV 4:2:2
101: ARGB8888
Other: reserved

In non-tile-based UV combined data mode:
001: YUV 4:2:2
010: YUV 4:2:0
011: YUV 4:1:1
Other: reserved

In tile-based planar data mode:
001: YUV 4:2:2
010: YUV 4:2:0
011: YUV 4:1:1
Other: Reserved

In tile-based UV combined data mode:
001: YUV 4:2:2
010: YUV 4:2:0
011: YUV 4:1:1
Other: reserved
3:2

/

/

/

1:0

R/W

0x0

DATA_PS

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Display
Pixel sequence

In interleaved YUV422 data mode:
00: Y1V0Y0U0
01: V0Y1U0Y0
10: Y1U0Y0V0
11: U0Y1V0Y0

In interleaved YUV444 data mode:
00: VUYA
01: AYUV
Other: reserved

In UV combined data mode: (UV component)
00: V1U1V0U0
01: U1V1U0V0
Other: reserved

In interleaved ARGB8888 data mode:
00: BGRA
01: ARGB
Other: reserved

6.1.4.17. DEFE Channel 3 Write Back Address Register(Default Value: 0x0000_0000)
Offset: 0x0050
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: DEFE_WB_ADDR0_REG
Description
WB_ADDR
Write-back address setting for scaled data.

6.1.4.18. DEFE Output Format Register(Default Value: 0x0000_0000)
Offset: 0x5C
Bit
Read/Write

Default/Hex

Register Name: DEFE_OUTPUT_FMT_REG
Description

31:18

/

/

/

17:16

R/W

0x0

GR8 User Manual(Version1.0)

WB_Ch_Sel
Write back channel select(chsel)
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Display

00~01: Ch3
10: Ch4
11: Ch5
15:9

/

/

/
BYTE_SEQ
Output data byte sequence selection

8

R/W

0x0

0: P3P2P1P0(word)
1: P0P1P2P3(word)

For ARGB, when this bit is 0, the byte sequence is BGRA, and when
this bit is 1, the byte sequence is ARGB;
7:5

/

/

/
SCAN_MOD
Output interlace enable

4

R/W

0x0

0: disable
1: enable

When output interlace enable, scaler selects YUV initial phase
according to LCD field signal
3

/

/

/
DATA_FMT
Data format

000: planar RGB888 conversion data format
001: interleaved BGRA8888 conversion data format(A component
always be pad 0xff)
2:0

R/W

0x0

010: interleaved ARGB8888 conversion data format(A component
always be pad 0xff)
100: planar YUV 444
101: planar YUV 420(only support YUV input and not interleaved
mode)
110: planar YUV 422(only support YUV input)
111: planar YUV 411(only support YUV input)
Other: reserved

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Display

6.1.4.19. DEFE Interrupt Enable Register(Default Value: 0x0000_0000)
Offset: 0x0060
Bit
Read/Write

Default/Hex

Register Name: DEFE_INT_EN_REG
Description

31:11

/

/

/

10

R/W

0x0

9

R/W

0x0

8

/

/

REG_LOAD_EN
Register ready load interrupt enable
LINE_EN
Line interrupt enable
/
WB_EN
Write-back end interrupt enable

7

R/W

0x0
0: Disable
1: Enable

6:0

/

/

/

6.1.4.20. DEFE Interrupt Status Register(Default Value: 0x0000_0000)
Offset: 0x0064
Bit
Read/Write

Default/Hex

Register Name: DEFE_INT_STATUS_REG
Description

31:11

/

/

/

10

R/W

0x0

9

R/W

0x0

8

/

/

7

R/W

0x0

6:0

/

/

REG_LOAD_STATUS
Register ready load interrupt status
LINE_STATUS
Line interrupt status
/
WB_STATUS
Write-back end interrupt status
/

6.1.4.21. DEFE Status Register(Default Value: 0x0000_0000)
Offset: 0x0068
Bit
Read/Write

Default/Hex

Register Name: DEFE_STATUS_REG
Description

31:29

/

/

/

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Display

28:16

R

0x0

15

R/W

0x0

14

R/W

0x0

13

/

/

LINE_ON_SYNC
Line number(when sync reached)
WB_ERR_SYNC
Sync reach flag when capture in process
WB_ERR_LOSEDATA
Lose data flag when capture in process
/
WB_ERR_STATUS
write-back error status

12

R

0x0

0: valid write back
1: un-valid write back

This bit is cleared through writing 0 to reset/start bit in frame control
register
COEF_ACCESS_STATUS
FIR coef access status

11

R

0x0

0: scaler module can access FIR coef RAM
1: CPU can access FIR coef ram

This bit must be 1 before CPU accesses FIR coef RAM. When this bit
is 1, scaler module will fetch 0x00004000 from RAM.
10:6

/

/

/
LCD_FIELD
LCD field status

5

R

0x0
0: top field
1: bottom field
DRAM_STATUS
Access dram status

4

R

0x0

0: idle
1: busy

This flag indicates whether DEFE is accessing dram

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Display
3

/

/

/
CFG_PENDING
Register configuration pending

0: no pending
2

R

0x0

1: configuration pending

This bit indicates the registers for the next frame has been
configured. This bit will be set when configuration ready bit is set
and this bit will be cleared when a new frame process begins.
WB_STATUS
Write-back process status

0: write-back end or write-back disable
1

R

0x0

1: write-back in process

This flag indicates that a full frame has not been written back to
memory. The bit will be set when write-back enable bit is set, and be
cleared when write-back process ends.
FRM_BUSY
Frame busy.
0

R

0x0

This flag indicates that the frame is being processed.
The bit will be set when frame process reset & start is set, and be
cleared when frame process is reset or disabled.

6.1.4.22. DEFE CSC Coefficient 00 Register(Default Value: 0x0000_0000)
Offset: 0x0070
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: DEFE_CSC_COEF00_REG
Description
/
COEF

12:0

R/W

0x0

the Y/G coefficient
the value equals to coefficient*210

6.1.4.23. DEFE CSC Coefficient 01 Register(Default Value: 0x0000_0000)
Offset: 0x0074
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: DEFE_CSC_COEF01_REG
Description

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Page 280

Display
31:13

/

/

/
COEF

12:0

R/W

0x0

the Y/G coefficient
the value equals to coefficient*210

6.1.4.24. DEFE CSC Coefficient 02 Register(Default Value: 0x0000_0000)
Offset: 0x0078
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: DEFE_CSC_COEF02_REG
Description
/
COEF

12:0

R/W

0x0

the Y/G coefficient
the value equals to coefficient*210

6.1.4.25. DEFE CSC Coefficient 03 Register(Default Value: 0x0000_0000)
Offset: 0x007C
Bit
Read/Write
31:14
/

Default/Hex
/

Register Name: DEFE_CSC_COEF03_REG
Description
/
CONT

13:0

R/W

0x0

the Y/G constant
the value equals to coefficient*24

6.1.4.26. DEFE CSC Coefficient 10 Register(Default Value: 0x0000_0000)
Offset: 0x0080
Bit
Read/Write

Default/Hex

Register Name: DEFE_CSC_COEF10_REG
Description

31:13

/

/

/

COEF
12:0

R/W

0x0

the U/R coefficient
the value equals to coefficient*210

6.1.4.27. DEFE CSC Coefficient 11 Register(Default Value: 0x0000_0000)
Offset: 0x0084
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: DEFE_CSC_COEF11_REG
Description
/

12:0

0x0

COEF

R/W

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Display
the U/R coefficient
the value equals to coefficient*210

6.1.4.28. DEFE CSC Coefficient 12 Register(Default Value: 0x0000_0000)
Offset: 0x0088
Bit
Read/Write

Default/Hex

Register Name: DEFE_CSC_COEF12_REG
Description

31:13

/

/

/

COEF
12:0

R/W

0x0

the U/R coefficient
the value equals to coefficient*210

6.1.4.29. DEFE CSC Coefficient 13 Register(Default Value: 0x0000_0000)
Offset: 0x008C
Bit
Read/Write

Default/Hex

Register Name: DEFE_CSC_COEF13_REG
Description

31:14

/

/

/

CONT
13:0

R/W

0x0

the U/R constant
the value equals to coefficient*24

6.1.4.30. DEFE CSC Coefficient 20 Register(Default Value: 0x0000_0000)
Offset: 0x0090
Bit
Read/Write

Default/Hex

Register Name: DEFE_CSC_COEF20_REG
Description

31:13

/

/

/

COEF
12:0

R/W

0x0

the V/B coefficient
the value equals to coefficient*210

6.1.4.31. DEFE CSC Coefficient 21 Register(Default Value: 0x0000_0000)
Offset: 0x0094
Bit
Read/Write

Default/Hex

Register Name: DEFE_CSC_COEF21_REG
Description

31:13

/

/

/

12:0

R/W

0x0

GR8 User Manual(Version1.0)

COEF
the V/B coefficient

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 282

Display
the value equals to coefficient*210

6.1.4.32. DEFE CSC Coefficient 22 Register(Default Value: 0x0000_0000)
Offset: 0x0098
Bit
Read/Write
31:13
/

Default/Hex
/

Register Name: DEFE_CSC_COEF22_REG
Description
/
COEF

12:0

R/W

0x0

the V/B coefficient
the value equals to coefficient*210

6.1.4.33. DEFE CSC Coefficient 23 Register(Default Value: 0x0000_0000)
Offset: 0x009C
Bit
Read/Write

Default/Hex

Register Name: DEFE_CSC_COEF23_REG
Description

31:14

/

/

/

CONT
13:0

R/W

0x0

the V/B constant
the value equals to coefficient*24

6.1.4.34. DEFE Write Back Line Stride Enable Register(Default Value: 0x0000_0000)
Offset: 0x00D0
Bit
Read/Write
31:1
/

Default/Hex
/

Register Name: DEFE_WB_LINESTRD_EN_REG
Description
/
EN
Write back line-stride enable

0

R/W

0x0
0: disable
1: enable

6.1.4.35. DEFE Write Back Channel Line Stride Register(Default Value: 0x0000_0000)
Offset: 0x00D4
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

GR8 User Manual(Version1.0)

Register Name: DEFE_WB_LINESTRD0_REG
Description
LINE_STRD
Ch3 write back line-stride

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Display
6.1.4.36. DEFE Channel 0 Input Size Register(Default Value: 0x0000_0000)
Offset: 0x0100
Bit
Read/Write

Default/Hex

Register Name: DEFE_CH0_INSIZE_REG
Description

31:29

/

/

/

IN_HEIGHT
28:16

R/W

0x0

Input image Y/G component height
Input image height = The value of these bits add 1

15:13

/

/

/
IN_WIDTH
Input image Y/G component width

12:0

R/W

0x0

The image width = The value of these bits add 1
When line buffer result selection is original data, the maximum
width is 2048.

6.1.4.37. DEFE Channel 0 Output Size Register(Default Value: 0x0000_0000)
Offset: 0x0104
Bit
Read/Write

Default/Hex

Register Name: DEFE_CH0_OUTSIZE_REG
Description

31:29

/

/

/

OUT_HEIGHT
28:16

R/W

0x0

Output layer Y/G component height
The output layer height = The value of these bits add 1

15:13

/

/

/
OUT_WIDTH
Output layer Y/G component width

12:0

R/W

0x0

The output layer width = The value of these bits add 1
When line buffer result selection is horizontal filtered result, the
maximum width is 2048

6.1.4.38. DEFE Channel 0 Horizontal Factor Register(Default Value: 0x0000_0000)
Offset: 0x0108
Bit
Read/Write

Default/Hex

Register Name: DEFE_CH0_HORZFACT_REG
Description

31:24

/

/

/

FACTOR_INT
23:16

R/W

0x0

The integer part of the horizontal scaling ratio
The horizontal scaling ratio = input width/output width

GR8 User Manual(Version1.0)

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Display
FACTOR_FRAC
15:0

R/W

0x0

The fractional part of the horizontal scaling ratio
The horizontal scaling ratio = input width/output width

6.1.4.39. DEFE Channel 0 Vertical factor Register(Default Value: 0x0000_0000)
Offset: 0x010C
Bit
Read/Write
31:24
/

Default/Hex
/

Register Name: DEFE_CH0_VERTFACT_REG
Description
/
FACTOR_INT

23:16

R/W

0x0

The integer part of the vertical scaling ratio
The vertical scaling ratio = input height/output height
FACTOR_FRAC

15:0

R/W

0x0

The fractional part of the vertical scaling ratio
The vertical scaling ratio = input height /output height

6.1.4.40. DEFE Channel 0 Horizontal Initial Phase Register(Default Value: 0x0000_0000)
Offset: 0x0110
Bit
Read/Write

Default/Hex

Register Name: DEFE_CH0_HORZPHASE_REG
Description

31:20

/

/

/

PHASE
19:0

R/W

0x0

Y/G component initial phase in horizontal (complement)
This value equals to initial phase * 216

6.1.4.41. DEFE Channel 0 Vertical Initial Phase 0 Register(Default Value: 0x0000_0000)
Offset: 0x0114
Bit
Read/Write
31:20
/

Default/Hex
/

Register Name: DEFE_CH0_VERTPHASE0_REG
Description
/
PHASE

19:0

R/W

0x0

Y/G component initial phase in vertical for top field (complement)
This value equals to initial phase * 216

6.1.4.42. DEFE Channel 0 Vertical Initial Phase 1 Register(Default Value: 0x0000_0000)
Offset: 0x0118
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: DEFE_CH0_VERTPHASE1_REG
Description

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 285

Display
31:20

/

/

/
PHASE

19:0

R/W

Y/G component initial phase in vertical for bottom field
(complement)

0x0

This value equals to initial phase * 216

6.1.4.43. DEFE Channel 1 Input Size Register(Default Value: 0x0000_0000)
Offset: 0x0200
Bit
Read/Write
31:29
/

Default/Hex
/

Register Name: DEFE_CH1_INSIZE_REG
Description
/
IN_HEIGHT

28:16

R/W

0x0

Input image U/R component height
Input image height = The value of these bits add 1

15:13

/

/

/
IN_WIDTH
Input image U/R component width

12:0

R/W

0x0

The image width = The value of these bits add 1
When line buffer result selection is original data, the maximum
width is 2048

6.1.4.44. DEFE Channel 1 Output Size Register(Default Value: 0x0000_0000)
Offset: 0x0204
Bit
Read/Write
31:29
/

Default/Hex
/

Register Name: DEFE_CH1_OUTSIZE_REG
Description
/
OUT_HEIGHT

28:16

0x0

Output layer U/R component height

R/W

The output layer height = The value of these bits add 1
15:13

/

/

/
OUT_WIDTH
Output layer U/R component width

12:0

R/W

0x0

The output layer width = The value of these bits add 1
When line buffer result selection is horizontal filtered result, the
maximum width is 2048

6.1.4.45. DEFE Channel 1 Horizontal Factor Register(Default Value: 0x0000_0000)
Offset: 0x0208
GR8 User Manual(Version1.0)

Register Name: DEFE_CH1_HORZFACT_REG
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Display
Bit

Read/Write

Default/Hex

Description

31:24

/

/

/
FACTOR_INT

23:16

R/W

0x0

The integer part of the horizontal scaling ratio
The horizontal scaling ratio = input width/output width
FACTOR_FRAC

15:0

R/W

0x0

The fractional part of the horizontal scaling ratio
The horizontal scaling ratio = input width/output width

6.1.4.46. DEFE Channel 1 Vertical factor Register(Default Value: 0x0000_0000)
Offset: 0x020C
Bit
Read/Write

Default/Hex

Register Name: DEFE_CH1_VERTFACT_REG
Description

31:24

/

/

/

FACTOR_INT
23:16

R/W

0x0

The integer part of the vertical scaling ratio
The vertical scaling ratio = input height/output height
FACTOR_FRAC

15:0

R/W

0x0

The fractional part of the vertical scaling ratio
The vertical scaling ratio = input height /output height

6.1.4.47. DEFE Channel 1 Horizontal Initial Phase Register(Default Value: 0x0000_0000)
Offset: 0x0210
Bit
Read/Write

Default/Hex

Register Name: DEFE_CH1_HORZPHASE_REG
Description

31:20

/

/

/

PHASE
19:0

R/W

0x0

U/R component initial phase in horizontal (complement)
This value equals to initial phase * 216

6.1.4.48. DEFE Channel 1 Vertical Initial Phase 0 Register(Default Value: 0x0000_0000)
Offset: 0x0214
Bit
Read/Write
31:20
/

Default/Hex
/

19:0

0x0

R/W

GR8 User Manual(Version1.0)

Register Name: DEFE_CH1_VERTPHASE0_REG
Description
/
PHASE
U/R component initial phase in vertical for top field (complement)

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Display
This value equals to initial phase * 216

6.1.4.49. DEFE Channel 1 Vertical Initial Phase 1 Register(Default Value: 0x0000_0000)
Offset: 0x0218
Bit
Read/Write
31:20
/

Default/Hex
/

Register Name: DEFE_CH1_VERTPHASE1_REG
Description
/
PHASE

19:0

R/W

U/R component initial phase in vertical for bottom field
(complement)

0x0

This value equals to initial phase * 216

6.1.4.50. DEFE Channel 0 Horizontal Filter Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x0400+N*0x04(N=0~31)
Bit
Read/Write Default/Hex

Register Name: DEFE_CH0_HORZCOEF0_REGN
Description
TAP3

31:24

R/W

0x0

Horizontal tap3 coefficient
The value equals to coefficient*26
TAP2

23:16

R/W

0x0

Horizontal tap2 coefficient
The value equals to coefficient*26
TAP1

15:8

R/W

0x0

Horizontal tap1 coefficient
The value equals to coefficient*26
TAP0

7:0

R/W

0x0

Horizontal tap0 coefficient
The value equals to coefficient*26

6.1.4.51. DEFE Channel 0 Vertical Filter Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x0500+N*0x04(N=0~31)
Bit
Read/Write Default/Hex

Register Name: DEFE_CH0_VERTCOEF_REGN
Description
TAP3

31:24

R/W

0x0

Vertical tap3 coefficient
The value equals to coefficient*26

23:16

R/W

0x0

GR8 User Manual(Version1.0)

TAP2

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Page 288

Display
Vertical tap2 coefficient
The value equals to coefficient*26
TAP1
15:8

R/W

0x0

Vertical tap1 coefficient
The value equals to coefficient*26
TAP0

7:0

R/W

0x0

Vertical tap0 coefficient
The value equals to coefficient*26

6.1.4.52. DEFE Channel 1 Horizontal Filter Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x0600+N*0x04(N=0~31)
Bit
Read/Write Default/Hex

Register Name: DEFE_CH1_HORZCOEF0_REGN
Description
TAP3

31:24

R/W

0x0

Horizontal tap3 coefficient
The value equals to coefficient*26
TAP2

23:16

R/W

0x0

Horizontal tap2 coefficient
The value equals to coefficient*26
TAP1

15:8

R/W

0x0

Horizontal tap1 coefficient
The value equals to coefficient*26
TAP0

7:0

R/W

0x0

Horizontal tap0 coefficient
The value equals to coefficient*26

6.1.4.53. DEFE Channel 1 Vertical Filter Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x0700+N*0x04(N=0~31)
Bit
Read/Write Default/Hex

Register Name: DEFE_CH1_VERTCOEF_REGN
Description
TAP3

31:24

R/W

0x0

Vertical tap3 coefficient
The value equals to coefficient*26
TAP2

23:16

R/W

0x0

Vertical tap2 coefficient
The value equals to coefficient*26

GR8 User Manual(Version1.0)

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Display
TAP1
15:8

R/W

0x0

Vertical tap1 coefficient
The value equals to coefficient*26
TAP0

7:0

R/W

0x0

Vertical tap0 coefficient
The value equals to coefficient*26

GR8 User Manual(Version1.0)

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Page 290

Display

6.2. Display Engine Back End (DEBE)
6.2.1. Overview
The Display Engine Back End (DEBE) including the following features:
●

4 moveable & size-adjustable layers

●

Layer size up to 2048x2048 pixels

●

Supports Alpha blending

●

Supports color key

●

Supports write back function

●

Supports 1/2/4/8 bpp mono / palette

●

Supports 16/24/32 bpp color (external frame buffer)
–

5/6/5

–

1/5/5/5

–

0/8/8/8

–

8/8/8

–

8/8/8/8

–

4/4/4/4

●

Supports on-chip SRAM
–

256 entry 32-bpp palette

–

1/2/4/8 bpp internal frame buffer

–

Supports Gamma correction

●

Supports hardware cursor
–

32x32 @8-bpp

–

64x64 @2-bpp

–

64x32 @4-bpp

–

32x64 @4-bpp

●

Supports YUV input channel

●

Output color correction

6.2.2. DEBE Block Diagram

GR8 User Manual(Version1.0)

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Display
AHB BUS

Intelligent
Ext DMA
Controller

On Chip
Frame
SRAM

H W Cursor
pattern buffer

FE0

FE1
PIPE 1 FIFO
PIPE 0 FIFO

Alpha
Blender 1

Alpha
Blender 0

Color
Correction

LCD Controller
TV Encoder

Normal/YUV/Palette/Gamma/
Internal frame buffer Controller

Write back channel

DEFE

DEBE

Figure 6-2. Display Engine Block Diagram

6.2.3. DEBE Register list
Module name
DEBE

Base address
0x01E60000

Register name
DEBE_MODCTL_REG
DEBE_BACKCOLOR_REG
DEBE_DISSIZE_REG

Offset
0x0800
0x0804
0x0808
0x0810 –
0x081C
0x0820 –
0x082C
0x0840 –
0x084C
0x0850 –
0x085C
0x0860
0x0870
0x0880
0x0884
0x0888
0x0890 –
0x089C
0x08A0 –
0x08AC
0x08D8
0x08E0

DEBE_LAYSIZE_REG
DEBE_LAYCOOR_REG
DEBE_LAYLINEWIDTH_REG
DEBE_LAYFB_L32ADD_REG
DEBE_LAYFB_H4ADD_REG
DEBE_REGBUFFCTL_REG
DEBE_CKMAX_REG
DEBE_CKMIN_REG
DEBE_CKCFG_REG
DEBE_ATTCTL_REG0
DEBE_ATTCTL_REG1
DEBE_HWCCTL_REG
DEBE_HWCFBCTL_REG
GR8 User Manual(Version1.0)

Description
DEBE Mode Control Register
DE-back Color Control Register
DE-back Display Size Setting Register
DE-layer Size Register
DE-layer Coordinate Control Register
DE-layer Frame Buffer Line Width Register
DE-layer Frame Buffer Low 32 bit Address Register
DE-layer Frame Buffer High 4 bit Address Register
DE-Register Buffer Control Register
DE-color Key MAX Register
DE-color Key MIN Register
DE-color Key Configuration Register
DE-layer Attribute Control Register0
DE-layer Attribute Control Register1
DE-HWC Coordinate Control Register
DE-HWC Frame Buffer Format Register

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 292

Display
DEBE_WBCTL_REG
DEBE_WBADD_REG
DEBE_WBLINEWIDTH_REG
DEBE_IYUVCTL_REG
DEBE_IYUVADD_REG
DEBE_IYUVLINEWIDTH_REG
DEBE_YGCOEF_REG
DEBE_YGCONS_REG
DEBE_URCOEF_REG
DEBE_URCONS_REG
DEBE_VBCOEF_REG
DEBE_VBCONS_REG
DEBE_OCCTL_REG
DEBE_OCRCOEF_REG
DEBE_OCRCONS_REG
DEBE_OCGCOEF_REG
DEBE_OCGCONS_REG
DEBE_OCBCOEF_REG
DEBE_OCBCONS_REG
/
/

0x08F0
0x08F4
0x08F8
0x0920
0x0930 – 0x0938
0x0940 – 0x0948
0x0950 – 0x0958
0x095C
0x0960 – 0x0968
0x096C
0x0970 – 0x0978
0x097C
0x09C0
0x09D0-0x09D8
0x09DC
0x09E0-0x09E8
0x09EC
0x09F0-0x09F8
0x09FC
Memories
0x4400-0x47FF
0x4800-0x4BFF
0x4C00-0x4FFF
0x5000-0x53FF
0x5400-0x57FF

DEBE Write Back Control Register
DEBE Write Back Address Register
DEBE Write Back Buffer Line Width Register
DEBE Input YUV Channel Control Register
DEBE YUV Channel Frame Buffer Address Register
DEBE YUV Channel Buffer Line Width Register
DEBE Y/G Coefficient Register
DEBE Y/G Constant Register
DEBE U/R Coefficient Register
DEBE U/R Constant Register
DEBE V/B Coefficient Register
DEBE V/B Constant Register
DEBE Output Color Control Register
DEBE Output Color R Coefficient Register
DEBE Output Color R Constant Register
DEBE Output Color G Coefficient Register
DEBE Output Color G Constant Register
DEBE Output Color B Coefficient Register
DEBE Output Color B Constant Register
/
Gamma Table
DE-HWC Pattern Memory Block
DE-HWC Color Palette Table
Pipe0 Palette Table
Pipe1 Palette Table

6.2.4. DEBE Register Description
6.2.4.1. DEBE Mode Control Register (Default Value: 0x0000_0000)
Offset: 0x0800
Bit
Read/Write
31:30
/

Default/Hex
/

29

0x0

R/W

Register Name: DEBE_MODCTL_REG
Description
/
LINE_SEL
Start top/bottom line selection in interlace mode
ITLMOD_EN
Interlace mode enable

28

R/W

0x0
0:Disable
1:Enable

27:17

/

/

/
HWC_EN

16

R/W

0x0

GR8 User Manual(Version1.0)

Hardware cursor enabled/disabled control

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Page 293

Display
0: Disable
1: Enable

Hardware cursor has the highest priority, in the alpha blender0, the
alpha value of cursor will be selected
15:12

/

/

/
LAY3_EN
Layer3 Enable/Disable

11

R/W

0x0
0: Disable
1: Enable
LAY2_EN
Layer2 Enable/Disable

10

R/W

0x0
0: Disable
1: Enable
LAY1_EN
Layer1 Enable/Disable

9

R/W

0x0
0: Disable
1: Enable
LAY0_EN
Layer0 Enable/Disable

8

R/W

0x0
0: Disable
1: Enable

7:2

/

/

/
START_CTL
Normal output channel Start & Reset control

1

R/W

0x0
0: Reset
1: Start
DEBE_EN

0

R/W

0x0

GR8 User Manual(Version1.0)

DEBE Enable/Disable

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Page 294

Display
0: Disable
1: Enable

6.2.4.2. DE-Back Color Control Register
Offset: 0x0804
Bit
Read/Write

Default/Hex

Register Name: DEBE_BACKCOLOR_REG
Description

31:24

/

/

/

BK_RED
23:16

R/W

UDF

Red
Red screen background color value
BK_GREEN

15:8

R/W

UDF

Green
Green screen background color value
BK_BLUE

7:0

R/W

UDF

Blue
Blue screen background color value

6.2.4.3. DE-Back Display Size Setting Register
Offset: 0x0808
Bit
Read/Write

Default/Hex

Register Name: DEBE_DISSIZE_REG
Description
DIS_HEIGHT

31:16

R/W

UDF

Display height
The real display height = The value of these bits add 1
DIS_WIDTH

15:0

R/W

UDF

Display width
The real display width = The value of these bits add 1

6.2.4.4. DE-Layer Size Register
Offset:
Layer 0: 0x0810
Layer 1: 0x0814

Register Name: DEBE_LAYSIZE_REG

Layer 2: 0x0818
Layer 3: 0x081C

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Display
Bit

Read/Write

Default/Hex

Description

31:29

/

/

/
LAY_HEIGHT

28:16

R/W

UDF

Layer Height
The Layer Height = The value of these bits add 1

15:13

/

/

/
LAY_WIDTH

12:0

R/W

UDF

Layer Width
The Layer Width = The value of these bits add 1

6.2.4.5. DE-Layer Coordinate Control Register
Offset:
Layer 0: 0x0820
Layer 1: 0x0824

Register Name: DEBE_LAYCOOR_REG

Layer 2: 0x0828
Layer 3: 0x082C
Bit

Read/Write

Default/Hex

Description
LAY_YCOOR

31:16

R/W

UDF

Y coordinate
Y is the left-top y coordinate of layer on screen in pixels
The Y represents the two’s complement
LAY_XCOOR

15:0

R/W

UDF

X coordinate
X is left-top x coordinate of the layer on screen in pixels
The X represents the two’s complement

Note: Setting the layer0-layer3 the coordinate (left-top) on screen control information

6.2.4.6. DE-Layer Frame Buffer Line Width Register
Offset:
Layer 0: 0x0840
Layer 1: 0x0844

Register Name: DEBE_LAYLINEWIDTH_REG

Layer 2: 0x0848
Layer 3: 0x084C

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Display
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

Description
LAY_LINEWIDTH
Layer frame buffer line width in bits

Note: If the layer is selected by video channel or YUV channel, the setting of this register will be ignored.

6.2.4.7. DE-Layer Frame Buffer Low 32 Bit Address Register
Offset:
Layer 0: 0x0850
Layer 1: 0x0854

Register Name: DEBE_LAYFB_L32ADD_REG

Layer 2: 0x0858
Layer 3: 0x085C
Bit

Read/Write

Default/Hex

Description
LAYFB_L32ADD

31:0

R/W

UDF

Buffer start Address
Layer Frame start Buffer Address in bit

Note: If the layer is selected by video channel or YUV channel, the setting of this register will be ignored.

6.2.4.8. DE-Layer Frame Buffer High 4 Bit Address Register
Offset: 0x0860
Bit
Read/Write

Default/Hex

Register Name: DEBE_LAYFB_H4ADD_REG
Description

31:28

/

/

/

LAY3FB_H4ADD
27:24

R/W

UDF

Layer3
Layer Frame Buffer Address in bit

23:20

/

/

/
LAY2FB_H4ADD

19:16

R/W

UDF

Layer2
Layer Frame Buffer Address in bit

15:12

/

/

/
LAY1FB_H4ADD

11:8

R/W

UDF

Layer1
Layer Frame Buffer Address in bit

7:4

/

/

GR8 User Manual(Version1.0)

/

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Display
LAY0FB_H4ADD
3:0

R/W

UDF

Layer0
Layer Frame Buffer Address in bit

Note: If the layer is selected by video channel or YUV channel, the setting of this register will be ignored.

6.2.4.9. DE-Register Buffer Control Register (Default Value: 0x0000_0000)
Offset: 0x0870
Bit
Read/Write

Default/Hex

Register Name: DEBE_REGBUFFCTL_REG
Description

31:2

/

/

/

REGAUTOLOAD_DIS
Module registers loading auto mode disable control
1

R/W

0x0
0: registers auto loading mode
1: disable registers auto loading mode, the registers will be loaded by
writing 1 to bit0 of this register
REGLOADCTL
Register load control

0

R/W

0x0

When the Module registers loading auto mode disable control bit is set,
the registers will be loaded by writing 1 to the bit, and the bit will be
self cleared after the registers is loaded.

6.2.4.10. DE-Color Key MAX Register
Offset: 0x0880
Bit
Read/Write

Default/Hex

Register Name: DEBE_CKMAX_REG
Description

31:24

/

/

/

CKMAX_R
23:16

R/W

UDF

Red
Red color key max
CKMAX_G

15:8

R/W

UDF

Green
Green color key max
CKMAX_B

7:0

R/W

UDF

Blue
Blue color key max

GR8 User Manual(Version1.0)

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Page 298

Display
6.2.4.11. DE-Color Key MIN Register
Offset: 0x0884
Bit
Read/Write

Default/Hex

Register Name: DEBE_CKMIN_REG
Description

31:24

/

/

/

CKMIN_R
23:16

R/W

UDF

Red
Red color key min
CKMIN_G

15:8

R/W

UDF

Green
Green color key min
CKMIN_B

7:0

R/W

UDF

Blue
Blue color key min

6.2.4.12. DE-Color Key Configuration Register
Offset: 0x0888
Bit
Read/Write

Default/Hex

Register Name: DEBE_CKCFG_REG
Description

31:06

/

/

/

CKR_MATCH
Red Match Rule

5:4

R/W

UDF

00: always match
01: always match
10: match if (Color Min=Color Max or ColorColor Max or ColorColor Max or Color10>01>00

11:10

R/W

UDF

When more than 2 layers are enabled, the priority value of each layer
must be different, so designers must keep the condition.

If more than 1 layers select the same pipe, in the overlapping area, only
the pixel of highest priority layer can pass the pipe to blender1.

If both 2 pipes are selected by layers, in the overlapping area, the alpha
value will use the alpha value of higher priority layer in the blender1.
9:3

/

/

/
LAY_YUVEN
YUV channel selection

2

R/W

UDF

0: disable
1: enable

Setting 2 or more layers YUV channel mode is illegal, so programmers
should confirm it.
LAY_VDOEN
1

R/W

UDF

GR8 User Manual(Version1.0)

Layer video channel selection enable control

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Display
0: disable
1: enable

Normally, one layer cannot be set both video channel and YUV channel
mode. If both 2 mode are set, the layer will work in video channel mode,
and YUV channel mode will be ignored, so programmers should confirm
it.
Setting 2 or more layers video channel mode is illegal, and programmers
should confirm it.
LAY_GLBALPHAEN
0

R/W

Alpha Enable

UDF

0: Disable the alpha value of this register
1: Enable the alpha value of this register for the layer

6.2.4.14. DE-Layer Attribute Control Register1
Offset:
Layer0: 0x08A0
Layer1: 0x08A4

Register Name: DEBE_ATTCTL_REG1

Layer2: 0x08A8
Layer3: 0x08AC
Bit
31:16

Read/Write
/

Default/Hex
/

Description
/
LAY_HSCAFCT
Setting the internal frame buffer scaling factor, only valid in internal
frame buffer mode
SH
Height scale factor

15:14

R/W

UDF
00: no scaling
01: *2
10: *4
11: Reserved
LAY_WSCAFCT

13:12

R/W

UDF

Setting the internal frame buffer scaling factor, only valid in internal
frame buffer mode
SW

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Display
Width scale factor

00: no scaling
01: *2
10: *4
11: Reserved
LAY_FBFMT
Frame buffer format
Normal mode data format

0000: mono 1-bpp
0001: mono 2-bpp
0010: mono 4-bpp
0011: mono 8-bpp
0100: color 16-bpp (R:6/G:5/B:5)
0101: color 16-bpp (R:5/G:6/B:5)
0110: color 16-bpp (R:5/G:5/B:6)
0111: color 16-bpp (Alpha:1/R:5/G:5/B:5)
1000: color 16-bpp (R:5/G:5/B:5/Alpha:1)
1001: color 24-bpp (Padding:8/R:8/G:8/B:8)
11:8

R/W

UDF

1010: color 32-bpp (Alpha:8/R:8/G:8/B:8)
1011: color 24-bpp (R:8/G:8/B:8)
1100: color 16-bpp (Alpha:4/R:4/G:4/B:4)
1101: color 16-bpp (R:4/G:4/B:4/Alpha:4)
Other: Reserved

Palette Mode data format
In palette mode, the data of external frame buffer is regarded as
pattern.
0000: 1-bpp
0001: 2-bpp
0010: 4-bpp
0011: 8-bpp
other: Reserved

Internal Frame buffer mode data format

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Display
0000: 1-bpp
0001: 2-bpp
0010: 4-bpp
0011: 8-bpp
Other: Reserved
7:3

/

/

/
LAY_BRSWAPEN
B R channel swap

2

R/W

UDF
0: RGB. Follow the bit[11:8]----RGB
1: BGR. Swap the B R channel in the data format.
LAY_FBPS

1:0

R/W

PS

UDF

Pixels Sequence
See the follow table “Pixels Sequence”

6.2.4.15. Pixels Sequence Table
DE-layer attribute control register1 [11:08] = FBF (frame buffer format)
DE-layer attribute control register1 [01:00] = PS (pixels sequence)

Mono or Internal Frame Buffer 1-Bpp Or Palette 1-Bpp Mode

:

FBF = 0000

PS=00
Bit
31

30

P31 P30
P15 P14
15 14

29

28

27

26

P29 P28 P27
P13 P12 P11
13 12
11

P26
P10
10

29

28

27

26

P26

P27

P28

25

24

23

22

21

20

19

18

17

16

P25 P24 P23 P22 P21 P20 P19 P18 P17 P16
P09 P08 P07 P06 P05 P04 P03 P02 P01 P00
09 08
07 06
05 04 03
02 01 00

PS=01
Bit
31
P24

30
P25

GR8 User Manual(Version1.0)

P29

25
P30

24

23
P31

P16

22

21
P17

20
P18

19
P19

18
P20

Copyright © 2017 Next Thing Co. All Rights Reserved.

17
P21

16
P22

P23

Page 304

Display
P08 P09
15
14

P10 P11 P12 P13 P14 P15 P00 P01 P02 P03 P04 P05 P06 P07
13 12
11 10
09 08 07
06
05 04
03
02 01 00

PS=10
Bit
31

30

P07 P06
P23 P22
15
14

29
P05
P21
13

28

27

26

25

24

23

22

21

20

19

18

17

16

P04 P03 P02 P01 P00 P15 P14 P13 P12 P11 P10 P09 P08
P20 P19 P18 P17 P16 P31 P30 P29 P28 P27 P26 P25 P24
12 11 10
09
08 07
06 05
04 03
02 01 00

PS=11
Bit
31

30

P00 P01
P16 P17
15
14

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15
P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31
13 12
11
10 09 08
07
06
05 04
03 02 01 00

Mono or Internal Frame Buffer 2-Bpp Or Palette 2-Bpp Mode

:

FBF = 0001

PS=00
Bit
31

30

P15
P07
15 14

29

28

27

P14

26

25

P13

13

P06
12

29

28

11

24

23

P12
P05
10

21

P11
P04
08

09

22

19

P10
P03
06

07

20

05

18

17

P09

P02
04
03

16
P08

P01
02
01

P00
00

PS=01
Bit
31

30

P12
P04
15 14

27

P13
13

26

P14
P05
12

11

25

24
P15

P06
10

09

23

22

21

P08
P07
08

07

20

19

P09
P00
06

05

18

17

P10

P01
04
03

P02
02
01

16
P11
P03
00

PS=10
Bit
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Display
31

30

P03
P11
15 14

29

28

27

P02

26

25

P01

13

P10
12

29

28

24

23

P00

11

P09
10

27

26

22

21

P07

09

P08
08

25

24

20

19

P06

07

P15
06

23

22

18

17

P05

16
P04

05

P14
04
03

P13
02
01

P12
00

21

20

18

16

PS=11
Bit
31

30

P00
P08
15 14

P01
13

P02
P09
12

11

P03
P10
10

Mono 4-bpp or palette 4-bpp mode

P11
08

09

:

P04
07

19

P05
P12
06

05

17

P06

P07

P13
04

03

P14
02 01

P15
00

20

19

18

17

16

03

P00
02 01

00

19

18

17

16

P01
02 01

00

FBF = 0010

PS=00
Bit
31

30

P07
P03
15
14

29

28

27

26

25

24

P06
13

12

23

22

21

P05

11

P02
10

09

27

26

25

08

P04

07

P01
06

23

22

05

04

PS=01
Bit
31

30

P06
P02
15
14

29

28

24

P07

21

20

P04

13

12

11

P03
10

29

28

27

26

09

08

07

P05
P00
06

05

04

03

PS=10
Bit
31

30

P01
P05
15
14

25

24

P00
13

12

11

GR8 User Manual(Version1.0)

23

22

21

20

P03
P04
10

09

08

07

19

18

17

16

P02
P07
06

05

04

03

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P06
02 01

00

Page 306

Display
PS=11
Bit
31

30

P00
P04
15
14

29

28

27

26

25

24

23

P01
13

12

21

20

19

P02
P05
10

11

22

09

Mono 8-bpp mode or palette 8-bpp mode

08

:

07

18

17

16

P07
02 01

00

P03
P06
06

05

04

03

FBF = 0011

PS=00/11
Bit
31

30

P3
P1
15 14

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P0
06 05

04

03

02

01

00

P2
13

12

11

10

09

08

07

PS=01/10
Bit
31

30

P0
P2
15 14

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P1
13

12

Color 16-bpp mode

11

:

10

09

08

07

P3
06 05

04

03

02

01

00

FBF = 0100 or 0101 or 0110 or 0111 or 1000

PS=00
Bit
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P1
P0
15 14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

PS=01
Bit

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Display
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P0
P1
15 14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

PS=10/11
Invalid

Color 24-bpp or 32-bpp mode

:

FBF = 1001 or 1010

PS=00/01
Bit
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

P0
15

The bytes sequence is ARGB
PS=10/11
Bit
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

P0
15

The bytes sequence is BGRA
6.2.4.16. DE-HWC Coordinate Control Register
Offset: 0x08D8
Bit
Read/Write

Default/Hex

31:16

R/W

UDF

15:0

R/W

UDF

GR8 User Manual(Version1.0)

Register Name: DEBE_HWCCTL_REG
Description
HWC_YCOOR
Hardware cursor Y coordinate
HWC_XCOOR
Hardware cursor X coordinate

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Display
6.2.4.17. DE-HWC Frame Buffer Format Register
Offset: 0x08E0
Bit
Read/Write

Default/Hex

31:24

UDF

R/W

Register Name: DEBE_HWCFBCTL_REG
Description
HWC_YCOOROFF
Y coordinate offset
The hardware cursor is 32*32 2-bpp pattern, this value represents the
start position of the cursor in Y coordinate
HWC_XCOOROFF

23:16

R/W

X coordinate offset

UDF

The hardware cursor is 32*32 2-bpp pattern, this value represent the
start position of the cursor in X coordinate
15:6

/

/

/
HWC_YSIZE
Y size control

5:4

R/W

UDF

00: 32pixels per line
01: 64pixels per line
Other: reserved
HWC_XSIZE
X size control

3:2

R/W

UDF

00: 32pixels per row
01: 64pixels per row
Other: reserved
HWC_FBFMT
Pixels format control

1:0

R/W

UDF

00: 1bpp
01: 2bpp
10: 4bpp
11: 8bpp

6.2.4.18. DEBE Write Back Control Register
Offset: 0x08F0
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: DEBE_WBCTL_REG
Description

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Page 309

Display
31:13

/

/

/
WB_FMT
Write back data format setting

12

R/W

UDF
0:ARGB (little endian system)
1:BGRA (little endian system)

11:10

/

/

/
WB_EFLAG
Error flag

9

R/W

UDF
0:/
1: write back error
WB_STATUS
Write-back process status

0: write-back end or write-back disable
8

R/W

UDF

1: write-back in process

This flag indicates that a full frame has not been written back to
memory. The bit will be set when write-back enable bit is set, and be
cleared when write-back process ends.
7:2

/

/

/
WB_WOC
Write back only control

1

R/W

UDF

0: disable the write back only control, the normal channel data of back
end will transfer to LCD/TV controller too.
1: enable the write back only function, and the all output data will
bypass the LCD/TV controller.
WB_EN
Write back enable

0

R/W

UDF

0: Disable
1: Enable

If normal channel of back-end is selected by LCD/TV controller (write
back only function is disabled), the writing back process will start

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Display
when write back enable bit is set and a new frame processing begins.
The bit will be cleared when the new writing-back frame starts to
process.

6.2.4.19. DEBE Write Back Address Register
Offset: 0x08F4
Bit

Read/Write

Default/Hex

31:0

R/W

UDF

Register Name: DEBE_WBADD_REG
Description
WB_ADD
The start address of write back data in WORD

6.2.4.20. DEBE Write Back Buffer Line Width Register
Offset: 0x08F8
Bit
Read/Write

Default/Hex

31:0

UDF

R/W

Register Name: DEBE_WBLINEWIDTH_REG
Description
WB_LINEWIDTH
Write back image buffer line width in bits

6.2.4.21. DEBE Input YUV Channel Control Register
Offset: 0x0920
Bit
Read/Write

Default/Hex

Register Name: DEBE_IYUVCTL_REG
Description

31:15

/

/

/

IYUV_FBFMT
Input data format

000: planar YUV 411
14:12

R/W

UDF

001: planar YUV 422
010: planar YUV 444
011: interleaved YUV 422
100: interleaved YUV 444
Other: illegal

11:10

/

/

/
IYUV_FBPS

9:8

R/W

UDF

Pixel sequence

In planar data format mode:

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Display
00: Y3Y2Y1Y0
01: Y0Y1Y2Y3 (the other 2 components are same)
Other: illegal

In interleaved YUV 422 data format mode:
00: UYVY
01: YUYV
10: VYUY
11: YVYU

In interleaved YUV 444 data format mode:
00: AYUV
01: VUYA
Other: illegal
7:5

/

/

/
IYUV_LINNEREN

4

R/W

UDF

0: liner
1:

3:1

/

/

/
IYUV_EN
YUV channel enable control

0

R/W

UDF
0: disable
1: enable

Source Data Input Data Ports:

Input buffer channel

Planar YUV

Interleaved YUV

Channel0
Channel1
Channel2

Y
U
V

YUV
-

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Display
6.2.4.22. DEBE YUV Channel Frame Buffer Address Register
Offset:
Channel 0 : 0x0930

Register Name: DEBE_IYUVADD_REG

Channel 1 : 0x0934
Channel 2 : 0x0938
Bit

Read/Write

Default/Hex

Description
IYUV_ADD

31:0

R/W

UDF

Buffer Address
Frame buffer address in BYTE

6.2.4.23. DEBE YUV Channel Buffer Line Width Register
Offset:
Channel 0 : 0x0940

Register Name: DEBE_IYUVLINEWIDTH_REG

Channel 1 : 0x0944
Channel 2 : 0x0948
Bit

Read/Write

Default/Hex

Description
IYUV_LINEWIDTH
Line width

31:0

R/W

UDF

The width is the distance from the start of one line to the start of the
next line.
Description in bits

YUV to RGB conversion algorithm formula:
R=
(R Y component coefficient * Y) +
(R U component coefficient * U) +
(R V component coefficient * V) +
R constant

G=
(G Y component coefficient * Y) +
(G U component coefficient * U) +
(G V component coefficient * V) +

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G constant

B=
(B Y component coefficient * Y) +
(B U component coefficient * U) +
(B V component coefficient * V) +
B constant

6.2.4.24. DEBE Y/G Coefficient Register
Offset:
G/Y component: 0x0950

Register Name: DEBE_YGCOEF_REG

R/U component: 0x0954
B/V component: 0x0958
Bit

Read/Write

Default/Hex

Description

31:13

/

/

/
IYUV_YGCOEF

12:0

R/W

UDF

The Y/G coefficient
The value equals to coefficient*210

6.2.4.25. DEBE Y/G Constant Register
Offset: 0x095C
Bit
Read/Write
31:14
/

Default/Hex
/

Register Name: DEBE_YGCONS_REG
Description
/
IYUV_YGCONS

13:0

R/W

UDF

The Y/G constant
The value equals to coefficient*24

6.2.4.26. DEBE U/R Coefficient Register
Offset:
G/Y component: 0x0960

Register Name: DEBE_URCOEF_REG

R/U component: 0x0964
B/V component: 0x0968
Bit

Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Description

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Page 314

Display
31:13

/

/

/
IYUV_URCOEF

12:0

R/W

UDF

The U/R coefficient
The value equals to coefficient*210

6.2.4.27. DEBE U/R Constant Register
Offset: 0x096C
Bit
Read/Write

Default/Hex

Register Name: DEBE_URCONS_REG
Description

31:14

/

/

/

IYUV_URCONS
13:0

R/W

UDF

The U/R constant
The value equals to coefficient*24

6.2.4.28. DEBE V/B Coefficient Register
Offset:
G/Y component: 0x0970

Register Name: DEBE_VBCOEF_REG

R/U component: 0x0974
B/V component: 0x0978
Bit

Read/Write

Default/Hex

Description

31:13

/

/

/
IYUV_VBCOEF

12:0

R/W

UDF

The V/B coefficient
The value equals to coefficient*210

6.2.4.29. DEBE V/B Constant Register
Offset: 0x097C
Bit
Read/Write

Default/Hex

Register Name: DEBE_VBCONS_REG
Description

31:14

/

/

/

IYUV_VBCONS
13:0

R/W

UDF

The V/B constant
The value equals to coefficient*24

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Display
6.2.4.30. DEBE Output Color Control Register
Offset: 0x09C0
Bit
Read/Write

Default/Hex

Register Name: DEBE_OCCTL_REG
Description

31:1

/

/

/

OC_EN
Color control module enable control
0

R/W

UDF
0: disable
1: enable

Color correction conversion algorithm formula:
R=
(R R component coefficient * R) +
(R G component coefficient * G) +
(R B component coefficient * B) +
R constant

G=
(G R component coefficient * R) +
(G G component coefficient * G) +
(G B component coefficient * B) +
G constant

B=
(B R component coefficient * R) +
(B G component coefficient * G) +
(B B component coefficient * B) +
B constant

6.2.4.31. DEBE Output Color R Coefficient Register
Offset:
R component: 0x09D0

Register Name: DEBE_OCRCOEF_REG

G component: 0x09D4

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Display
B component: 0x09D8
Bit

Read/Write

Default/Hex

Description

31:14

/

/

/
OC_RCOEF

13:0

R/W

UDF

The R coefficient
The value equals to coefficient*210

6.2.4.32. DEBE Output Color R Constant Register
Offset: 0x09DC
Bit
Read/Write

Default/Hex

Register Name: DEBE_OCRCONS_REG
Description

31:15

/

/

/

OC_RCONS
14:0

R/W

UDF

The R constant
The value equals to coefficient*24

6.2.4.33. DEBE Output Color G Coefficient Register
Offset:
R component: 0x09E0

Register Name: DEBE_OCGCOEF_REG

G component: 0x09E4
B component: 0x09E8
Bit

Read/Write

Default/Hex

Description

31:14

/

/

/
OC_GCOEF

13:0

R/W

UDF

The G coefficient
The value equals to coefficient*210

6.2.4.34. DEBE Output Color G Constant Register
Offset: 0x09EC
Bit
Read/Write
31:15
/

Default/Hex
/

Register Name: DEBE_OCGCONS_REG
Description
/
OC_GCONS

14:0

R/W

UDF

The G constant
The value equals to coefficient*24

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Display

6.2.4.35. DEBE Output Color B Coefficient Register
Offset:
G/Y component: 0x09F0

Register Name: DEBE_OCBCOEF_REG

R/U component: 0x09F4
B/V component: 0x09F8
Bit

Read/Write

Default/Hex

Description

31:14

/

/

/
OC_BCOEF

13:0

R/W

UDF

The B coefficient
The value equals to coefficient*210

6.2.4.36. DEBE Output Color B Constant Register
Offset: 0x09FC
Bit
Read/Write

Default/Hex

Register Name: DEBE_OCBCONS_REG
Description

31:15

/

/

/

OC_BCONS
14:0

R/W

UDF

The B constant
The value equals to coefficient*24

6.2.4.37. DE-HWC Pattern Memory Block
Function:
1bpp:
Bit
31

30

P31 P30
P15 P14
15
14

29

28

P29 P28
P13 P12
13 12

27

26

P27 P26
P11 P10
11 10

25

24

23

22

21

P25
P09
09

P24
P08
08

P23
P07
07

P22 P21
P06 P05
06 05

20

19

18

P20 P19
P04 P03
04 03

17

P18 P17
P02 P01
02 01

16
P16
P00
00

2bpp:
Bit
31

30

29

28

27

GR8 User Manual(Version1.0)

26

25

24

23

22

21

20

19

18

Copyright © 2017 Next Thing Co. All Rights Reserved.

17

16
Page 318

Display
P15
P07
15 14

P14

P13

P12

13

P06
12

11

P05
10

29

28

27

26

09

P11

P04
08
07

P10

P03
06
05

P09

P08

P02
04

P01
03

02

P00
01

00

17

16

P00
02 01

00

4bpp:
Bit
31

30

P07
P03
15 14

25

24

23

P06
13

12

11

22

21

20

19

P05
P02
10

09

08

P04
P01
06

07

18

05

04

03

8bpp:
Bit
31

30

P3
P1
15 14

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P2
P0
13

12

11

10

09

Offset:

08

07

06

05

04

03

02

01

00

DE-HW cursor pattern memory block

0x4800-0x4BFF
Bit

Read/Write

Default/Hex

31:00

R/W

UDF

Description
Hardware cursor pixel pattern
Specify the color displayed for each of the hardware cursor pixels.

6.2.4.38. DE-HWC Palette Table
Offset:

DE-HW palette table

0x4C00-0x4FFF
Bit

Read/Write

Default/Hex

Description

31:24

R/W

UDF

Alpha value

23:16

R/W

UDF

Red value

15:08

R/W

UDF

Green value

07:00

R/W

UDF

Blue value

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Display
The following figure (only with 2bpp mode) shows the RAM array used for hardware cursor palette lookup and the
corresponding colors output.
Output color

HWC Index memory
array
2bpp mode
bit0

bit7

HWC palette table

3

Color0

0

R0

G0

B0

Color1

1

R1

G1

B1

Color254



254 R254 G254 B254

Color255



255 R255 G255 B255

2

0

2

2

R2

G2

B2

0

R0

G0

B0

2

R2

G2

B2

3

R3

G3

B3

2

R2

G2

B2

1

3

2

2

2

R2

G2

B2

3

3

0

1

3

R3

G3

B3

1

R1

G1

B1

1

R1

G1

B1

0

R0

G0

B0

3

R3

G3

B3

3

R3

G3

B3

Hardware cursor index memory
& palette

6.2.4.39. Palette Mode
Offset:
Pipe0:0x5000-0x53FF

Pipe palette color table SRAM block

Pipe1:0x5400-0x57FF
Bit

Read/Write

Default/Hex

Description

31:24

R/W

UDF

Alpha value

23:16

R/W

UDF

Red value

15:08

R/W

UDF

Green value

07:00

R/W

UDF

Blue value

In this mode, RAM array is used for palette lookup table; each pixel in the layer frame buffer is treated as an index
into the RAM array to select the actual color.
The following figure shows the RAM array used for palette lookup and the corresponding colors output.

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Display
On chip SRAM array
Inputting external
frame buffer data
(8bpp)

5

38

133

0
1

n

28

254
255

R0

G0

B0

R1

G1

B1

Rn

Gn

Output color

5
38
133
28

Bn

R5

G5

B5

R38

G38

B38

R133 G133 B133
R28

G28

B28

R254 G254 B254
R255 G255 B255

On chip SRAM for palette lookup

6.2.4.40. Internal Frame Buffer Mode
In internal frame buffer mode, the RAM array is used as an on-chip frame buffer; each pixel in the RAM array is
used to select one of the palette 32-bit colors.
1bpp:
Bit
31

30

29

28

27

26

25

P31 P30 P29
P15 P14 P13
15
14 13

P28
P12
12

P27
P11
11

P26 P25
P10 P09
10 09

28

27

26

12

P13
P05
11 10

24

23

22

21

20

P24 P23
P08 P07
08 07

P22
P06
06

P21
P05
05

P20
P04
04

24

22

19

18

P19 P18
P03 P02
03 02

17

16

P17
P01
01

P16
P00
00

17

16

2bpp:
Bit
31

30

29

P15
P07
15 14

P14
P06
13

25

P12
P04
09 08

23

21

20

P11
P03
07 06

P10
P02
05 04

23

21

19

18

P09
P01
03 02

01

P08
P00
00

4bpp:
Bit
31

30

P07
P03
15 14

29

13

28

27

26

12

P06
P02
11 10

25

09

24

08

22

P05
P01
07 06

05

20

19

18

17

16

04

P04
P00
03 02

01

00

8bpp:
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Display
Bit
31

30

P3
P1
15 14

29

28

27

26

24

23

22

21

20

19

18

17

16

06

05

04

03

02

01

00

P2
P0
13

12

11

10

09

Offset:

Read/Write

31:00

08

07

DE-on chip SRAM block

0x4000-0x57FF
Bit

25

Default/Hex

R/W

Description
Internal frame buffer pixel pattern

UDF

Specify the color displayed for each of the internal frame buffer pixels.

6.2.4.41. Internal Frame Buffer Mode Palette Table
Offset:
Pipe0:0x5000-0x53FF

Pipe palette table

Pipe1:0x5400-0x57FF
Bit

Read/Write

Default/Hex

Description

31:24

R/W

UDF

Alpha value

23:16

R/W

UDF

Red value

15:08

R/W

UDF

Green value

07:00

R/W

UDF

Blue value

The following figure shows the RAM array used for internal frame buffer mode and the corresponding colors output.

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Display
Output color
On chip SRAM array
2bpp mode
Internal frame buffer
Palette table

bit0

bit7
3

Color0

0

R0

G0

B0

Color1

1

R1

G1

B1

Color254



254 R254 G254 B254

Color255



255 R255 G255 B255

2

0

2

2

R2

G2

B2

0

R0

G0

B0

2

R2

G2

B2

3

R3

G3

B3

2

R2

G2

B2

1

3

2

2

2

R2

G2

B2

3

3

0

1

3

R3

G3

B3

1

R1

G1

B1

1

R1

G1

B1

0

R0

G0

B0

3

R3

G3

B3

3

R3

G3

B3

On chip SRAM for internal
frame buffer

6.2.4.42. Gamma Correction Mode
Offset:

DE-on chip SRAM block

0x4400-0x47FF
Bit

Read/Write

Default/Hex

Description

31:24

R/W

UDF

Alpha channel intensity

23:16

R/W

UDF

Red channel intensity

15:08

R/W

UDF

Green channel intensity

07:00

R/W

UDF

Blue channel intensity

In gamma correction mode, the RAM array is used for gamma correction; each pixel’s alpha, red, green, and blue
color component is treated as an index into the SRAM array. The corresponding
Alpha, red, green, or blue channel intensity value at that index is used in the actual color.
The following figure shows the RAM array used for gamma correction and the corresponding colors output.

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Display
On chip SRAM array
Inputting external
frame buffer data

0
1

R0

G0

B0

R1

G1

B1

Output color

5
5

38

133

28

n

254
255

Rn

Gn

R38

G133 B28

Bn

R254 G254 B254
R255 G255 B255

On chip SRAM for gamma correction

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Display

6.3. TCON
6.3.1. Block Diagram
MAX
700MHz

CONTROL LOGIC

OUT0

DMA

Async FIFO1

F
R
M

RGB
2
YUV
(444)

DATA
FORMATTER

LCDdata

HV TIMING
BASIC
TIMING
GENERATOR

OUT2
3
To
2
M
U
X

DE

OUT1

CEU

FIFO Flag
&
CLOCK
GEN

Gamma

CPU TIMING

TV TIMING GENERATOR

LCD

LCD ctlr

TV ctlr
TV

Async FIFO2

TV DATA

TV data

Figure 6-3. LCD/TV Timing Controller Block Diagram

6.3.2. TCON Register List
Module Name
TCON

Base Address
0x01C0C000

Register Name

Offset

Description

TCON_GCTL_REG
TCON_GINT0_REG
TCON_GINT1_REG
TCON0_FRM_CTL_REG
TCON0_FRM_SEED0_REG
TCON0_FRM_SEED1_REG
TCON0_FRM_SEED2_REG
TCON0_FRM_SEED3_REG
TCON0_FRM_SEED4_REG
TCON0_FRM_SEED5_REG
TCON0_FRM_TAB0_REG
TCON0_FRM_TAB1_REG
TCON0_FRM_TAB2_REG
TCON0_FRM_TAB3_REG
TCON0_CTL_REG
TCON0_DCLK_REG

0x0000
0x0004
0x0008
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x0040
0x0044

TCON Global Control Register
TCON Global Interrupt Register0
TCON Global Interrupt Register1
TCON FRM Control Register
TCON FRM Seed Register0
TCON FRM Seed Register1
TCON FRM Seed Register2
TCON FRM Seed Register3
TCON FRM Seed Register4
TCON FRM Seed Register5
TCON FRM Table Register0
TCON FRM Table Register1
TCON FRM Table Register2
TCON FRM Table Register3
TCON0 Control Register
TCON0 Data Clock Register

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Display
TCON0_BASIC0_REG
TCON0_BASIC1_REG
TCON0_BASIC2_REG
TCON0_BASIC3_REG
TCON0_HV_IF_REG
TCON0_CPU_IF_REG
TCON0_CPU_WR_REG
TCON0_CPU_RD0_REG
TCON0_CPU_RD1_REG
TCON0_IO_POL_REG
TCON0_IO_TRI_REG
TCON1_CTL_REG
TCON1_BASIC0_REG
TCON1_BASIC1_REG
TCON1_BASIC2_REG
TCON1_BASIC3_REG
TCON1_BASIC4_REG
TCON1_BASIC5_REG
TCON1_IO_POL_REG
TCON1_IO_TRI_REG
TCON_CEU_CTL_REG
TCON_CEU_COEF0_REG
TCON_CEU_COEF1_REG
TCON_CEU_COEF2_REG
TCON_CEU_COEF3_REG
TCON_CEU_COEF4_REG
TCON_CEU_COEF5_REG
TCON_CEU_COEF6_REG
TCON_CEU_COEF7_REG
TCON_CEU_COEF8_REG
TCON_CEU_COEF9_REG
TCON_CEU_COEF10_REG
TCON_CEU_COEF11_REG
TCON_CEU_COEF12_REG
TCON_CEU_COEF13_REG
TCON_CEU_COEF14_REG
TCON1_ FILL_CTL_REG
TCON1_ FILL_BEGIN0_REG
TCON1_ FILL_END0_REG
TCON1_ FILL_DATA0_REG
TCON1_ FILL_BEGIN1_REG
TCON1_ FILL_END1_REG
TCON1_ FILL_DATA1_REG
TCON1_ FILL_BEGIN2_REG
TCON1_ FILL_END2_REG

GR8 User Manual(Version1.0)

0x0048
0x004C
0x0050
0x0054
0x0058
0x0060
0x0064
0x0068
0x006C
0x0088
0x008C
0x0090
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8
0x00F0
0x00F4
0x0100
0x0110
0x0114
0x0118
0x011C
0x0120
0x0124
0x0128
0x012C
0x0130
0x0134
0x0138
0x013C
0x0140
0x0144
0x0148
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0318
0x031C
0x0320

TCON0 Basic Timing Register0
TCON0 Basic Timing Register1
TCON0 Basic Timing Register2
TCON0 Basic Timing Register3
TCON0 Hv Panel Interface Register
TCON0 CPU Panel Interface Register
TCON0 CPU Panel Write Data Register
TCON0 CPU Panel Read Data Register0
TCON0 CPU Panel Read Data Register1
TCON0 IO Polarity Register
TCON0 IO Control Register
TCON1 Control Register
TCON1 Basic Timing Register0
TCON1 Basic Timing Register1
TCON1 Basic Timing Register2
TCON1 Basic Timing Register3
TCON1 Basic Timing Register4
TCON1 Basic Timing Register5
TCON1 IO Polarity Register
TCON1 IO Control Register
TCON CEU Control Register
TCON CEU Coefficient Register0
TCON CEU Coefficient Register1
TCON CEU Coefficient Register2
TCON CEU Coefficient Register3
TCON CEU Coefficient Register4
TCON CEU Coefficient Register5
TCON CEU Coefficient Register6
TCON CEU Coefficient Register7
TCON CEU Coefficient Register8
TCON CEU Coefficient Register9
TCON CEU Coefficient Register10
TCON CEU Coefficient Register11
TCON CEU Coefficient Register12
TCON CEU Coefficient Register13
TCON CEU Coefficient Register14
TCON1 Fill Data Control Register
TCON1 Fill Data Begin Register0
TCON1 Fill Data End Register0
TCON1 Fill Data Value Register0
TCON1 Fill Data Begin Register1
TCON1 Fill Data End Register1
TCON1 Fill Data Value Register1
TCON1 Fill Data Begin Register2
TCON1 Fill Data End Register2

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Display
TCON1_ FILL_DATA2_REG
TCON1_GAMMA_TABLE_REG

0x0324
0x400-0x7FF

TCON1 Fill Data Value Register2
TCON1 Gama Table Register

6.3.3. TCON Register Description
6.3.3.1. TCON Global Control Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit

Read/Write

Register Name: TCON_GCTL_REG
Default/Hex

Description
TCON_EN

31

R/W

0: disable

0x0

1: enable

When it is disabled, the module will be reset to idle state.
TCON_GAMMA_EN
30

R/W

0x0

0: disable
1: enable

29:1

/

/

/
IO_MAP_SEL

0

R/W

0: TCON0

0x0

1: TCON1

Note: This bit determines which IO_INV/IO_TRI is valid

6.3.3.2. TCON Global Interrupt Register0(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write

Default/Hex

Register Name: TCON_GINT0_REG
Description
TCON0_VB_INT_EN

31

R/W

0x0

0: disable
1: enable

30

R/W

0x0

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TCON1_VB_INT_EN

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Display
0: disable
1: enable
TCON0_LINE_INT_EN
29

R/W

0x0

0: disable
1: enable
TCON1_LINE_INT_EN

28

R/W

0x0

0: disable
1: enable

27:16

/

/

/
TCON0_VB_INT_FLAG

15

R/W

0x0

Asserted during vertical no-display period every frame.
Write 0 to clear it.
TCON1_VB_INT_FLAG

14

R/W

0x0

Asserted during vertical no-display period every frame.
Write 0 to clear it.
TCON0_LINE_INT_FLAG

13

R/W

0x0

Trigger when SY0 matches the current TCON0 scan line
Write 0 to clear it.
TCON1_LINE_INT_FLAG

12

R/W

0x0

Trigger when SY1 matches the current TCON1 scan line
Write 0 to clear it.

11:0

/

/

/

6.3.3.3. TCON Global Interrupt Register1(Default Value: 0x0000_0000)
Offset: 0x0008
Bit
Read/Write
31:27
/

Default/Hex
/

Register Name: TCON_GINT1_REG
Description
/
TCON0_Line_Int_Num

26:16

R/W

0x0

scan line for TCON0 line trigger(including inactive lines)
Setting it for the specified line for trigger0.
Note: SY0 is writable only when LINE_TRG0 is disabled.

15:11

/

/

/

10:0

R/W

0x0

TCON1_Line_Int_Num

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Display
scan line for TCON1 line trigger(including inactive lines)
Setting it for the specified line for trigger 1.
Note: SY1 is writable only when LINE_TRG1 is disabled.

6.3.3.4. TCON FRM Control Register(Default Value: 0x0000_0000)
Offset: 0x0010
Bit
Read/Write

Default/Hex

Register Name: TCON0_FRM_CTL_REG
Description
TCON0_FRM_EN

31

R/W

0x0

0:disable
1:enable

30:12

/

/

/
TCON0_FRM_MODE_R

6

R/W

0x0

0: 6bit frm output
1: 5bit frm output
TCON0_FRM_MODE_G

5

R/W

0x0

0: 6bit frm output
1: 5bit frm output
TCON0_FRM_MODE_B

4

R/W

0x0

0: 6bit frm output
1: 5bit frm output
TCON0_FRM_TEST

1:0

R/W

00: FRM

0x0

01: half 5/6bit, half FRM
10: half 8bit, half FRM
11: half 8bit, half 5/6bit

6.3.3.5. TCON FRM Pixel Seed Register(Default Value: 0x0000_0000)
Offset: 0x0014-0x001C
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: TCON0_FRM_PIXEL_SEED_REG
Description

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Display
31:25

/

/

24:0

R/W

0x0

/
PIXEL_SEED_VALUE
Note: Avoid set it to 0

6.3.3.6. TCON FRM Line Seed Register(Default Value: 0x0000_0000)
Offset: 0x0020-0x0028

Register Name: TCON0_FRM_LINE_SEED_REG

Bit

Read/Write

Default/Hex

Description

31:25

/

/

/

12:0

R/W

0x0

LINE_SEED_VALUE
Note: Avoid set it to 0

6.3.3.7. TCON FRM Table Register(Default Value: 0x0000_0000)
Offset: 0x002C-0x0038
Bit
Read/Write
31:0
R/W

Default/Hex
0x0

Register Name: TCON0_FRM_TAB_REG
Description
FRM_TABLE_VALUE

6.3.3.8. TCON0 Control Register(Default Value: 0x0000_0000)
Offset: 0x0040
Bit
Read/Write

Default/Hex

Register Name: TCON0_CTL_REG
Description
TCON0_EN

0: Disable
31

R/W

0x0

1: Enable

Note: It executes at the beginning of the first blank line of TCON0
timing.
30:26

/

/

/
TCON0_IF

25:24

R/W

0x0

00: HV(Sync+DE)
01: 8080 I/F
10: TTL I/F
11: reserved

23

R/W

0x0

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Display
0: Default
1: Swap RED and BLUE data at FIFO1
TCON0_TEST_VALUE
22

R/W

0x0

0:All 0s
1:All 1s
TCON0_FIFO1_RST

21

R/W

0x0

Writing 1 and then 0 to this bit will reset FIFO 1

Note: 1 holding time must be more than 1 DCLK
TCON0_INTERLACE_EN

20

R/W

0x0

0:Disable
1:Enable

Note: This flag is valid only when TCON0_EN == 1
19:9

/

/

/
TCON0_STATE_DELAY

8:4

R/W

0x0

STA delay

Note: Valid only when TCON0_EN == 1
3:2

/

/

/
TCON0_SRC_SEL

00: DE CH1(FIFO1 enable)
01: DE CH2(FIFO1 enable)
10: DMA 565 input(FIFO1 enable)
11: Test intput(FIFO1 disable)
1:0

R/W

0x0
Note: These bits are sampled only at the beginning of the first blank
line of TCON0 timing. Generally, when input source changes, it will
change at the beginning of the first blank line of TCON0 timing.
When FIFO1 and FIFO2 select the same source and FIFO2 is enabled,
it executes at the beginning of the first blank line of TV timing. Also,
TCON0 timing generator will reset to the beginning of the first blank
line.

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Display
6.3.3.9. TCON0 Data Clock Register(Default Value: 0x0000_0000)
Offset: 0x0044
Bit
Read/Write

Default/Hex

Register Name: TCON0_DCLK REG
Description

31

R/W

0x0

TCON0_DCLK_EN

30:7

/

/

/
TCON0_DCLK_DIV
Tdclk = Tsclk * DCLKDIV

6:0

R/W

0x0

Note:
1.If dclk1&dclk2 used, DCLKDIV >=6
2.If dclk only, DCLKDIV >=4

6.3.3.10. TCON0 Basic Timing Register0(Default Value: 0x0000_0000)
Offset: 0x0048
Bit
Read/Write

Default/Hex

Register Name: TCON0_BASIC0_REG
Description

31:27

/

/

/

26:16

R/W

0x0

15:11

/

/

10:0

R/W

0x0

TCON0_X
Panel width is X+1
/
TCON0_Y
Panel height is Y+1

6.3.3.11. TCON0 Basic Timing Register1(Default Value: 0x0000_0000)
Offset: 0x004C
Bit
Read/Write

Default/Hex

Register Name: TCON0_BASIC1_REG
Description

31:28

/

/

/

HT
Thcycle = (HT+1) * Tdclk
27:16

R/W

0x0

Note:1) parallel :HT >= (HBP +1) + (X+1) +2
2) serial 1: HT >= (HBP +1) + (X+1) *3+2
3) serial 2: HT >= (HBP +1) + (X+1) *3/2+2

15:10

/

/

GR8 User Manual(Version1.0)

/

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Display
6.3.3.12. TCON0 Basic Timing Register2(Default Value: 0x0000_0000)
Offset: 0x0050
Bit
Read/Write

Default/Hex

Register Name: TCON0_BASIC2_REG
Description

31:21

/

/

/

VT
27:16

R/W

TVT = (VT)/2 * Thsync

0x0

Note: VT/2 >= (VBP+1 ) + (Y+1) +2
15:10

/

/

9:0

R/W

0x0

/
VBP
Tvbp = (VBP +1) * Thsync

6.3.3.13. TCON0 Basic Timing Register3(Default Value: 0x0000_0000)
Offset: 0x0054
Bit
Read/Write
31:22
/

Default/Hex
/

Register Name: TCON0_BASIC3_REG
Description
/
HSPW

25:16

R/W

Thspw = (HSPW+1) * Tdclk

0x0

Note: HT> (HSPW+1)
15:10

/

/

/
VSPW

9:0

R/W

Tvspw = (VSPW+1) * Thsync

0x0

Note: VT/2 > (VSPW+1)

6.3.3.14. TCON0 HV Panel Interface Register(Default Value: 0x0000_0000)
Offset: 0x0058
Bit
Read/Write

Default/Hex

Register Name: TCON0_HV_IF_REG
Description
HV_MODE

31

R/W

0x0

0: 24bit parallel mode
1: 8bit serial mode

30

R/W

0x0

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Display

0: 8bit/3cycle RGB serial mode(RGB888)
1: 8bit/2cycle YUV serial mode(CCIR656)
29:28

/

/

/
RGB888_SM0
Serial RGB888 mode Output sequence at odd lines of the panel (line
1, 3, 5, 7…)

27:26

R/W

0x0

00: R→G→B
01: B→R→G
10: G→B→R
11: R→G→B
RGB888_SM1
Serial RGB888 mode Output sequence at even lines of the panel (line
2, 4, 6, 8…)

25:24

R/W

0x0

00: R→G→B
01: B→R→G
10: G→B→R
11: R→G→B
YUV_SM
serial YUV mode Output sequence 2-pixel-pair of every scan line

23:22

R/W

0x0

00: YUYV
01: YVYU
10: UYVY
11: VYUY
YUV EAV/SAV F LINE DELAY

21:20

R/W

0x0

00:F toggle right after active video line
01:delay 2 line(CCIR NTSC)
10:delay 3 line(CCIR PAL)
11:reserved

19:0

/

/

GR8 User Manual(Version1.0)

/

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Display
6.3.3.15. TCON0 CPU Panel Interface Register(Default Value: 0x0000_0000)
Offset: 0x0060
Bit
Read/Write

Register Name: TCON0_CPU_IF_REG
Default/Hex

Description
CPU_MOD

000: 18bit/256K mode
001: 16bit mode0
31:29

010: 16bit mode1
R/W

0x0

011: 16bit mode2
100: 16bit mode3
101: 9bit mode
110: 8bit 256K mode
111: 8bit 65K mode
AUTO

28

Auto Transfer Mode:
R/W

0x0

If it’s 1, all valid data during this frame is written to panel.
Note: This bit is sampled by Vsync
FLUSH
direct transfer mode:

27

R/W

0x0

If it’s enabled, FIFO1 is irrelevant to the HV timing, and pixels data
keeps being transferred unless the input FIFO is empty.
Data output rate control by DCLK.
DA

26

R/W

0x0

25

R/W

0x0

pin A1 value in 8080 mode auto/flash states
CA
pin A1 value in 8080 mode WR/RD execute
VSYNC_CS_SEL

24

R/W

0x0

0:CS
1:VSYNC
WR_FLAG

23

R

0x0

0:write operation ends
1:write operation is pending

22

R

0x0

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RD_FLAG

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Display

0:read operation ends
1:read operation is pending
21:0

/

/

/

6.3.3.16. TCON0 CPU Panel Write Data Register(Default Value: 0x0000_0000)
Offset: 0x0064
Bit
Read/Write
31:0
/

Default/Hex
/

23:0

0x0

W

Register Name: TCON0_CPU_WR_REG
Description
/
DATA_WR
data write on 8080 bus, launch a write operation on 8080 bus

6.3.3.17. TCON0 CPU Panel Read Data Register0(Default Value: 0x0000_0000)
Offset: 0x0068
Bit
Read/Write
31:24
/

Default/Hex
/

23:0

/

R

Register Name: TCON0_CPU_RD0_REG
Description
/
DATA_RD0
data read on 8080 bus, launch a new read operation on 8080 bus

6.3.3.18. TCON0 CPU Panel Read Data Register1(Default Value: 0x0000_0000)
Offset: 0x006C
Bit
Read/Write
31:24

/

Default/Hex
/

23:0

R

/

Register Name: TCON0_CPU_RD1_REG
Description
/
DATA_RD1
data read on 8080 bus, without a new read operation on 8080 bus

6.3.3.19. TCON0 IO Polarity Register(Default Value: 0x0000_0000)
Offset: 0x0088
Bit
Read/Write

Default/Hex

Register Name: TCON0_IO_POL_REG
Description

31:30

/

/

/

DCLK_SEL
29:28

R/W

0x0

00: used DCLK0(normal phase offset)
01: used DCLK1(1/3 phase offset)

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Display
10: used DCLK2(2/3 phase offset)
11: reserved
IO3_INV
27

R/W

0x0

0: not invert
1: invert
IO2_INV

26

R/W

0x0

0: not invert
1: invert
IO1_INV

25

R/W

0x0

0: not invert
1: invert
IO0_INV

24

R/W

0x0

0: not invert
1: invert
DATA_INV
TCON0 output port D[23:0] polarity control, with independent bit
control:

23:0

R/W

0x0
0s: normal polarity
1s: invert the specify output

6.3.3.20. TCON0 IO Control Register(Default Value: 0x0FFF_FFFF)
Offset: 0x008C
Bit
Read/Write

Default/Hex

Register Name: TCON0_IO_TRI_REG
Description

31:28

/

/

/

IO3_OUTPUT_TRI_EN
27

R/W

0x1

1: disable
0: enable

26

R/W

0x1

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IO2_OUTPUT_TRI_EN

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Display
1: disable
0: enable
IO1_OUTPUT_TRI_EN
25

R/W

0x1

1: disable
0: enable
IO0_OUTPUT_TRI_EN

24

R/W

0x1

1: disable
0: enable
DATA_OUTPUT_TRI_EN
TCON0 output port D[23:0] output enable, with independent bit
control:

23:0

R/W

0xFFFFFF
1s: disable
0s: enable

6.3.3.21. TCON1 Control Register(Default Value: 0x0000_0000)
Offset: 0x0090
Bit
Read/Write

Default/Hex

31

0x0

R/W

Register Name: TCON1_CTL_REG
Description
TCON1_EN

0: disable
1: enable

30:21

/

/

/
INTERLACE_EN

20

R/W

0x0

0:disable
1:enable

19:9

/

/

8:4

R/W

0x0

3:0

/

/

GR8 User Manual(Version1.0)

/
Start_Delay
This is for DE1 and DE2
/

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Display
6.3.3.22. TCON1 Basic Timing Register0(Default Value: 0x0000_0000)
Offset: 0x0094
Bit
Read/Write

Default/Hex

Register Name: TCON1_BASIC0_REG
Description

31:27

/

/

/

27:16

R/W

0x0

15:12

/

/

11:0

R/W

0x0

TCON1_XI
source width is X+1
/
TCON1_YI
source height is Y+1

6.3.3.23. TCON1 Basic Timing Register1(Default Value: 0x0000_0000)
Offset: 0x0098
Bit
Read/Write
31:27
/

Default/Hex
/

27:16

R/W

0x0

15:12

/

/

Register Name: TCON1_BASIC1_REG
Description
/
LS_XO
width is LS_XO+1
/
LS_YO

11:0

R/W

0x0

width is LS_YO+1
Note: This version LS_YO = TCON1_YI

6.3.3.24. TCON1 Basic Timing Register2(Default Value: 0x0000_0000)
Offset: 0x009C
Bit
Read/Write

Default/Hex

Register Name: TCON1_BASIC2_REG
Description

31:27

/

/

/

27:16

R/W

0x0

15:12

/

/

11:0

R/W

0x0

TCON1_XO
width is TCON1_XO+1
/
TCON1_YO
height is TCON1_YO+1

6.3.3.25. TCON1 Basic Timing Register3(Default Value: 0x0000_0000)
Offset: 0x00A0
Bit
Read/Write

Default/Hex

GR8 User Manual(Version1.0)

Register Name: TCON1_BASIC3_REG
Description

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Display
31:28

/

/

/
HT

28:16

R/W

0x0

horizontal total time
Thcycle = (HT+1) * Thdclk

15:12

/

/

/
HBP

11:0

R/W

0x0

horizontal back porch
Thbp = (HBP +1) * Thdclk

6.3.3.26. TCON1 Basic Timing Register4(Default Value: 0x0000_0000)
Offset: 0x00A4
Bit
Read/Write
31:28
/

Default/Hex
/

Register Name: TCON1_BASIC4_REG
Description
/
VT

28:16

R/W

0x0

horizontal total time (in HD line)
Tvt = VT/2 * Th

15:12

/

/

/
VBP

11:0

R/W

0x0

horizontal back porch (in HD line)
Tvbp = (VBP +1) * Th

6.3.3.27. TCON1 Basic Timing Register5(Default Value: 0x0000_0000)
Offset: 0x00A8
Bit
Read/Write

Default/Hex

Register Name: TCON1_BASIC5_REG
Description

31:26

/

/

/

HSPW
25:16

R/W

0x0

horizontal Sync Pulse Width (in dclk)
Thspw = (HSPW+1) * Tdclk
Note: HT> (HSPW+1)

15:10

/

/

/
VSPW

9:0

R/W

0x0

vertical Sync Pulse Width (in lines)
Tvspw = (VSPW+1) * Th
Note: VT/2 > (VSPW+1)

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Display
6.3.3.28. TCON1 IO Polarity Register(Default Value: 0x0000_0000)
Offset: 0x00F0
Bit
Read/Write

Default/Hex

Register Name: TCON1_IO_POL_REG
Description

31:28

/

/

/

IO3_INV
27

R/W

0x0

0: not invert
1: invert
IO2_INV

26

R/W

0x0

0: not invert
1: invert
IO1_INV

25

R/W

0x0

0: not invert
1: invert
IO0_INV

24

R/W

0x0

0: not invert
1: invert
DATA_INV
TCON1 output port D[23:0] polarity control, with independent bit
control:

23:0

R/W

0x0
0s: normal polarity
1s: invert the specify output

6.3.3.29. TCON1 IO Control Register(Default Value: 0x0FFF_FFFF)
Offset: 0x00F4
Bit
Read/Write

Default/Hex

Register Name: TCON1_IO_TRI_REG
Description

31:28

/

/

/

IO3_OUTPUT_TRI_EN
27

R/W

0x1

1: disable
0: enable

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Display
IO2_OUTPUT_TRI_EN
26

R/W

0x1

1: disable
0: enable
IO1_OUTPUT_TRI_EN

25

R/W

0x1

1: disable
0: enable
IO0_OUTPUT_TRI_EN

24

R/W

0x1

1: disable
0: enable
DATA_OUTPUT_TRI_EN
TCON1 output port D[23:0] output enable, with independent bit
control:

27:0

R/W

0xFFFFFF
1s: disable
0s: enable

6.3.3.30. TCON CEU Control Register(Default Value: 0x0000_0000)
Offset: 0x0100
Bit
Read/Write

Default/Hex

Register Name: TCON_CEU_CTL_REG
Description
CEU_EN

31

R/W

0x0

0: bypass
1: enable

30:0

/

/

/

6.3.3.31. TCON CEU Multiplier Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x0110-0x0118,

Register Name: TCON_CEU_MUL_COEF_REG

0x0120-0x0128, 0x0130-0x0138
Bit

Read/Write

Default/Hex

Description

31:13

/

/

/

12:0

R/W

0x0

CEU_COEF_MUL_VALUE

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Display
signed 13bit value, range of (-16,16)

6.3.3.32. TCON CEU Add Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x011C,0x012C,0x013C
Bit
Read/Write Default/Hex

Register Name: TCON_CEU_ADD_COEF_REG
Description

31:19

/

/

/

18:0

R/W

0x0

CEU_COEF_ADD_VALUE
signed 19bit value, range of (-16384, 16384)

6.3.3.33. TCON CEU Range Coefficient Register(Default Value: 0x0000_0000)
Offset: 0x0140,0x0144,0x0148
Bit
Read/Write Default/Hex

Register Name: TCON_CEU_RANGE_COEF_REG
Description

31:24

/

/

/

23:16

R/W

0x0

15:8

/

/

7:0

R/W

0x0

CEU_COEF_RANGE_MIN
unsigned 8bit value, range of [0,255]
/
CEU COEF_RANGE_MAX
unsigned 8bit value, range of [0,255]

6.3.3.34. TCON1 Fill Data Control Register(Default Value: 0x0000_0000)
Offset: 0x0300
Bit
Read/Write

Default/Hex

Register Name: TCON1_FILL_CTL_REG
Description
TCON1_FILL_EN

31

R/W

0x0

0: bypass
1: enable

30:0

/

/

/

6.3.3.35. TCON1 Fill Data Begin Register(Default Value: 0x0000_0000)
Offset: 0x0304,0x0310,0x031C
Bit
Read/Write Default/Hex
31:24
/
/
23:0
R/W
0x0

GR8 User Manual(Version1.0)

Register Name: TCON1_FILL_BEGIN_REG
Description
/
FILL_BEGIN

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Display
6.3.3.36. TCON1 Fill Data End Register(Default Value: 0x0000_0000)
Offset: 0x0308,0x0314,0x0320
Bit
Read/Write Default/Hex
31:24
/
/
23:0
R/W
0x0

Register Name: TCON1_FILL_END_REG
Description
/
FILL_END

6.3.3.37. TCON1 Fill Data Value Register(Default Value: 0x0000_0000)
Offset: 0x030C,0x0318,0x0324
Bit
Read/Write Default/Hex
31:24
/
/
23:0
R/W
0x0

GR8 User Manual(Version1.0)

Register Name: TCON1_FILL_DATA_REG
Description
/
FILL_VALUE

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Display

6.4. IEP
6.4.1. Overview
The Image Enhancement Processor (IEP) is capable of adjusting the dynamic range of pictures according to
statistics.

6.4.2. IEP Register List
Module Name
IEP

Base Address
0x01E70000

Register Name

Offset

Description

IMGEHC_GNECTL_REG

0x0000

General Control Register

IMGEHC_DRCSIZE_REG

0x0004

DRC Size Setting Register

IMGEHC_DRCCTL_REG

0x0010

DRC Control Register

IMGEHC_DRCLGC_STAADD_REG

0x0014

DRC External LGC Start Address Register

IMGEHC_DRC_SET_REG

0x0018

DRC Setting Register

IMGEHC_DRC_WP_REG0

0x001C

DRC Window Position Register0

IMGEHC_DRC_WP_REG1

0x0020

DRC Window Position Register1

IMGEHC_WBCTL_REG

0x0024

DRC Write Back Control Register

IMGEHC_WBADD_REG

0x0028

DRC Write Back Address Register

IMGEHC_WBLINEWIDTH_REG

0x002C

DRC Write Back Buffer Line Width Register

IMGEHC_LHC_REG

0x0030

Luminance Histogram Control Register

IMGEHC_LHT_REG0

0x0034

Luminance Histogram Threshold Setting Register 0

IMGEHC_LHT_REG1

0x0038

Luminance Histogram Threshold Setting Register 1

IMGEHC_LHSLUM_REG

0x0040~0x005C
0x00C0,0x00C4,

Luminance Histogram Statistics Lum Recording Register

IMGEHC_CSCYGCOFF_REG
IMGEHC_CSCYGCON_REG

0x00C8
0x00CC

CSC Y/G Coefficient Register
CSC Y/G Constant Register

0x00D0,0x00D4,
IMGEHC_CSCURCOFF_REG
IMGEHC_CSCURCON_REG

0x00D8
0x00DC

CSC U/R Coefficient Register
CSC U/R Constant Register

0x00E0,0x00E4,
IMGEHC_CSCVBCOFF_REG

0x00E8

CSC V/B Coefficient Register

IMGEHC_CSCVBCON_REG

0x00EC

CSC V/B Constant Register

IMGEHC_DRCSPACOFF

0x00F0~0x00F8

DRC Spatial Coefficient Register

IMGEHC_DRCINTCOFF

0x0100~0x01FC

DRC Intensity Coefficient Register

IMGEHC_DRCLGCOFF

0x0200~0x03FC

DRC Luminance Gain Coefficient Register

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Display

6.4.3. IEP Register Description
6.4.3.1. General Control Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_GNECTL_REG
Description
BIST_EN
BIST enable

31

R/W

0x0
0: Disable
1: Enable

30:10

/

/

/
MOD
Work mode selection.
If bit 0 of the register is set ZERO, the following setting will be ignored.

9:8

R/W

0x0

00: Output FIFO mode
01: De-flicker mode
10: DRC mode
11: Reserved

7:1

/

/

/
EN

0

R/W

0x0

0: Disable the module, and the whole module will be bypassed
1: Enable

6.4.3.2. DRC Size Setting Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_DRCSIZE_REG
Description

31:28

/

/

/

DRC_HEIGHT
27:16

R/W

0x0

Display height
The real display height = The value of these bits + 1.

15:12

/

/

/

11:0

R/W

0x0

DRC_WIDTH

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Display
Display width
The real display width = The value of these bits + 1.

6.4.3.3. DRC Control Register(Default Value: 0x0000_0000)
Offset: 0x0010
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_DRCCTL_REG
Description

31:09

/

/

/

DRC_WIN_EN
Output window function enable
08

R/W

0x0
0: Disable
1: Enable

07:02

/

/

/
DRC_DBRDY_CTL
Only valid when DRC_DB_EN bit is set.

01

R/W

0x0

If the bit is set, when the SYNC signal is coming, the all double buffered
DRC registers will be loaded, and the loading is done, the bit will be
cleared automatically
DRC_DB_EN
DRC double buffer function enable control

00

R/W

0x0
0: Disable
1: Enable

(LGC = Luminance Gain Coefficient)

6.4.3.4. DRC External LGC Start Address Register(Default Value: 0x0000_0000)
Offset: 0x0014
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: IMGEHC_DRCLGC_STAADD_REG
Description
DRC_LGC_STAADD
Start address in byte

Note: Double buffered register of DRC, double buffer function is controlled by DRC_DB_EN and DRC_DBRDY_CTL
bits.

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Display
6.4.3.5. DRC Setting Register(Default Value: 0x0000_8000)
Offset: 0x0018
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_DRC_SET_REG
Description

31:25

/

/

/

DRC_GAIN_AUTOLOAD_DIS
Only valid when the module is enabled and MOD is DRC mode, or the
bit is ignored.

24

R/W

If the auto load function is enabled, the DRC luminance gain coefficient
will be auto loaded from the external appointed memory address when
the SYNC signal (LCD SYNC signal) is coming, otherwise ignore the auto
load function.

0x0

About the calculating way of the external appointed memory address,
refer to the DRC external LGC start address register.

0: Enable the auto load function
1: Disable the auto load function
23:16

/

/

15:8

R/W

0x80

7:2

/

/

/
DRC_LGC_ABSLUMPERVAL
Abs luminance percent value
/
DRC_ADJUST_EN

1

R/W

0x0

0: Disable
1: Enable
DRC_LGC_ABSLUMSHF
Abs luminance shift bits

0

R/W

0x0
0: Shift 8bits
1: Shift 9bits

Note: Double buffered register of DRC, double buffer function is controlled by DRC_DB_EN and DRC_DBRDY_CTL
bits.
6.4.3.6. DRC Window Position Register0(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_DRC_WP_REG0
Description

31:28

/

/

/

27:16

R/W

0x0

DRC_WIN_TOP

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Display
Window Top position
Top position is the left-top y coordinate of display window in pixels
15:12

/

/

/
DRC_WIN_LEFT

11:0

R/W

0x0

Window Left position
Left position is left-top x coordinate of display window in pixels

6.4.3.7. DRC Window Position Register1(Default Value: 0x0000_0000)
Offset: 0x0020
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_DRC_WP_REG1
Description

31:28

/

/

/

DRC_WIN_BOT
27:16

R/W

Window Bottom position

0x0

Bottom position is the right-bottom y coordinate of display window in
pixels
15:12

/

/

/
DRC_WIN_RIGHT

11:0

R/W

Window Right position

0x0

Right position is the right-bottom x coordinate of display window in
pixels

6.4.3.8. DRC Write Back Control Register(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_WBCTL_REG
Description
WB_STATUS
Write back process status

31

R/W

0x0
0: Write back end or write back disable
1: Write back in process

30:25

/

/

/
WB_FIELD
Write back field setting for de-flicker

24

R/W

0x0
0: Top field
1: Bottom field

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Display
23:17

/

/

/
WB_FMT
Write back data format setting

16

R/W

0x0
0: ARGB
1: BGRA

15:9

/

/

/
WB_WOC
Write back only control

8

R/W

0x0

0: Disable the write back only control, the data will transfer to LCD
controller too.
1: Enable the write back only control, the data will not transfer to LCD
controller.

7:1

/

/

/
WB_EN
Write back enable

0

R/W

0x0

0: Disable
1: Enable

The bit will be cleared when write back ends.

6.4.3.9. DRC Write Back Address Register(Default Value: 0x0000_0000)
Offset: 0x0028
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

Register Name: IMGEHC_WBADD_REG
Description
WB_ADD
The start address of write back data in BYTE

6.4.3.10. DRC Write Back Buffer Line Width Register(Default Value: 0x0000_0000)
Offset: 0x002C
Bit
Read/Write

Default/Hex

31:0

0x0

R/W

GR8 User Manual(Version1.0)

Register Name: IMGEHC_WBLINEWIDTH_REG
Description
WB_LINEWIDTH
Write back image buffer line width in BYTE

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Display
6.4.3.11. Luminance Histogram Control Register(Default Value: 0x0000_0000)
Offset: 0x0030
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_LHC_REG
Description

31:2

/

/

/

LH_MOD
1

R/W

0x0

0: Current frame case
1: Average case
LH_REC_CLR

0

R/W

If the bit is set, all of the luminance statistics recording registers will be
cleared, and the bit will self-clear when the recording registers is
cleared.

0x0

6.4.3.12. Luminance Histogram Threshold Setting Register 0(Default Value: 0x8060_4020)
Offset: 0x0034
Bit
Read/Write

Default/Hex

31:24

R/W

0x80

23:16

R/W

0x60

15:8

R/W

0x40

7:0

R/W

0x20

Register Name: IMGEHC_LHT_REG0
Description
LH_THRES_VAL4
Step4 threshold value
LH_THRES_VAL3
Step3 threshold value
LH_THRES_VAL2
Step2 threshold value
LH_THRES_VAL1
Step1 threshold value

6.4.3.13. Luminance Histogram Threshold Setting Register 1(Default Value: 0x00E0_C0A0)
Offset: 0x0038
Bit
Read/Write

Default/Hex

Register Name: IMGEHC_LHT_REG1
Description

31:24

/

/

/

23:16

R/W

0xe0

15:8

R/W

0xc0

7:0

R/W

0xa0

GR8 User Manual(Version1.0)

LH_THRES_VAL7
Step7 threshold value
LH_THRES_VAL6
Step6 threshold value
LH_THRES_VAL5

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Display
Step5 threshold value
Note:
When
set
IMGEHC_LHT_REG0
THRES_VAL1 TXTL

22:21

R/W

0x0
01: 4
10: 8
11: 16

20:15

/

/

/
TX FIFO Empty Trigger Level (TXTL[6:0])

14:8

R/W

0x10

Interrupt and DMA request trigger level for TX FIFO normal condition.
IRQ/DRQ Generated when WLEVEL ≤ TXTL
ADDA_LOOP_EN.
ADDA Loop Enable

7

R/W

0x0
0: Disable
1: Enable
DAC_MONO_EN.
DAC Mono Enable

6

R/W

0x0
0: Stereo, 64 levels FIFO
1: mono, 128 levels FIFO

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Audio

When enabled, L & R channel send same data
TX_SAMPLE_BITS.
Transmitting Audio Sample Resolution
5

R/W

0x0
0: 16 bits
1: 24 bits
DAC_DRQ_EN.
DAC FIFO Empty DRQ Enable

4

R/W

0x0
0: Disable
1: Enable
DAC_IRQ_EN.
DAC FIFO Empty IRQ Enable

3

R/W

0x0
0: Disable
1: Enable
FIFO_UNDERRUN_IRQ_EN.
DAC FIFO Underrun IRQ Enable

2

R/W

0x0
0: Disable
1: Enable
FIFO_OVERRUN_IRQ_EN.
DAC FIFO Overrun IRQ Enable

1

R/W

0x0
0: Disable
1: Enable
FIFO_FLUSH.

0

R/W

0x0

DAC FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’

7.1.4.3. DAC FIFO Status Register(Default Value: 0x0080_8008)
Offset: 0x0008
Bit
31:24

Read/Write
/

Register Name: AC_DAC_FIFOS
Default/Hex
/

GR8 User Manual(Version1.0)

Description
/

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Audio
TX_EMPTY.
TX FIFO Empty
23

R

0x1
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)

22:8

R

0x80

7:4

/

/

TXE_CNT.
TX FIFO Empty Space Word Counter
/
TXE_INT.
TX FIFO Empty Pending Interrupt

3

R/W

0: No Pending IRQ

0x1

1: FIFO Empty Pending Interrupt

Write ‘1’ to clear this interrupt or automatically clear if interrupt
condition fails.
TXU_INT.
TX FIFO Underrun Pending Interrupt

2

R/W

0x0

0: No Pending Interrupt
1: FIFO Under run Pending Interrupt

Write ‘1’ to clear this interrupt
TXO_INT.
TX FIFO Overrun Pending Interrupt

1

R/W

0x0

0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt

Write ‘1’ to clear this interrupt
0

/

/

/

7.1.4.4. DAC TX DATA Register(Default Value: 0x0000_0000)
Offset: 0x000C
Bit

Read/Write

Register Name: AC_DAC_TXDATA
Default/Hex

GR8 User Manual(Version1.0)

Description

Copyright © 2017 Next Thing Co. All Rights Reserved.

Page 362

Audio
TX_DATA.
31:0

W

Transmitting left, right channel sample data should be written this
register one by one. The left channel sample data is first and then the
right channel sample.

0x0

7.1.4.5. DAC Analog Control Register(Default Value: 0x05B0_0000)
Offset:0x0010
Bit
Read/Write

Default/Hex

Register Name: AC_DAC_ACTRL
Description
DACAREN.
Internal DAC Analog Right channel Enable

31

R/W

0x0
0:Disable
1:Enable
DACALEN.
Internal DAC Analog Left channel Enable

30

R/W

0x0
0:Disable
1:Enable
MIXEN.
Analog Output Mixer Enable

29

R/W

0x0
0:Disable
1:Enable

28:27

/

/

/
LNG.
Line-in gain stage to output mixer Gain Control

26

R/W

0x1
0: -1.5dB
1: 0dB

25:23

R/W

0x3

Reserved
MICG.

22:20

R/W

0x3

MIC1/2 gain stage to output mixer Gain Control
From -4.5dB to 6dB, 1.5dB/step, default is 0dB
LLNS.

19

R/W

0x0

GR8 User Manual(Version1.0)

Left LINEIN gain stage to left output mixer mute

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Audio
0: Mute
1: Not mute

When LNRDF is 0, left select LINEINL
When LNRDF is 1, left select LINEINL-LINEINR
RLNS.
Right LINEIN gain stage to right output mixer mute

18

R/W

0x0

0: Mute
1: Not mute

When LNRDF is 0, right select LINEINR
When LNRDF is 1, right select LINEINL-LINEINR
LFMS.
Left FM to left output mixer mute
17

R/W

0x0
0:Mute
1:Not mute
RFMS.
right FM to right output mixer mute

16

R/W

0x0
0:Mute
1:Not mute
LDACLMIXS.
Left DAC to left output mixer mute

15

R/W

0x0
0:Mute
1:Not mute
RDACRMIXS.
Right DAC to right output mixer mute

14

R/W

0x0
0:Mute
1:Not mute

13

R/W

0x0

GR8 User Manual(Version1.0)

LDACRMIXS.
Left DAC to right output mixer mute

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Audio

0:Mute
1:Not mute
MIC1 LS.
MIC1 to output mixer left channel mute
12

R/W

0x0
0: Mute
1: Not mute
MIC1 RS.
MIC1 to output mixer right channel mute

11

R/W

0x0
0: Mute
1: Not mute
MIC2 LS.
MIC2 to output mixer left channel mute

10

R/W

0x0
0: Mute
1: Not mute
MIC2 RS.
MIC2 to output mixer right channel mute

9

R/W

0x0
0: Mute
1: Not mute
DACPAS.
DAC to PA Mute

8

R/W

0x0
0: Mute
1: Not mute
MIXPAS.
Output Mixer to PA mute

7

R/W

0x0
0: Mute
1: Not mute

6

R/W

0x0

GR8 User Manual(Version1.0)

PAMUTE.
All input source to PA mute, including Output mixer and Internal DAC,

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Audio

0:Mute
1: Not mute
PAVOL.
5:0

R/W

0x0

PA Volume Control, (PAVOL): Total 64 level, from 0dB to -62dB,
1dB/step，mute when 000000

7.1.4.6. ADC FIFO Control Register(Default Value: 0x0000_0F00)
Offset: 0x001C
Bit

Read/Write

Register Name: AC_ADC_FIFOC
Default/Hex

Description
ADFS.
Sample Rate of ADC

000: 48 kHz
010: 24 kHz
31:29

R/W

0x0

100: 12 kHz
110: Reserved
001: 32 kHz
011: 16 kHz
101: 8 kHz
111: Reserved
EN_AD.
ADC Digital Part Enable

28

R/W

0x0
0: Disable
1: Enable

27:25

/

/

/
RX_FIFO_MODE.
RX FIFO Output Mode (Mode 0, 1)

24

R/W

0x0

0: Expanding ‘0’ at LSB of TX FIFO register
1: Expanding received sample sign bit at MSB of TX FIFO register

For 24-bits received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[23:0], 8’h0}

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Audio
Mode 1: Reserved

For 16-bits received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[23:8], 16’h0}
Mode 1: RXDATA[31:0] = {16{FIFO_O[23]}, FIFO_O[23:8]}
23:13

/

/

/
RX_FIFO_TRG_LEVEL.
RX FIFO Trigger Level (RXTL[4:0])

12:8

R/W

0xF

Interrupt and DMA request trigger level for TX FIFO normal condition
IRQ/DRQ Generated when WLEVEL ＞ RXTL[4:0]
Note:
WLEVEL represents the number of valid samples in the RX FIFO
ADC_MONO_EN.
ADC Mono Enable.

7

R/W

0x0

0: Stereo, 16 levels FIFO
1: mono, 32 levels FIFO

When set to ‘1’, Only left channel samples are recorded
RX_SAMPLE_BITS.
Receiving Audio Sample Resolution
6

R/W

0x0
0: 16 bits
1: 24 bits

5

/

/

/
ADC_DRQ_EN.
ADC FIFO Data Available DRQ Enable.

4

R/W

0x0
0: Disable
1: Enable
ADC_IRQ_EN.
ADC FIFO Data Available IRQ Enable.

3

R/W

0x0
0: Disable
1: Enable

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Audio
2

/

/

/
ADC_OVERRUN_IRQ_EN.
ADC FIFO Over Run IRQ Enable

1

R/W

0x0
0: Disable
1: Enable
ADC_FIFO_FLUSH.

0

R/W

0x0

ADC FIFO Flush.
Write ‘1’ to flush TX FIFO, self clear to ‘0’.

7.1.4.7. ADC FIFO Status Register(Default Value: 0x0000_0000)
Offset: 0x0020
Bit
31:24

Read/Write
/

Register Name: AC_ADC_FIFOS
Default/Hex
/

Description
/
RXA.
RX FIFO Available

23

R

0x0
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)

22:14

/

/

13:8

R

0x0

7:4

/

/

/
RXA_CNT.
RX FIFO Available Sample Word Counter
/
RXA_INT.
RX FIFO Data Available Pending Interrupt

3

R/W

0x0

0: No Pending IRQ
1: Data Available Pending IRQ

Write ‘1’ to clear this interrupt or automatically clear if interrupt
condition fails.
2

/

/

/
RXO_INT.

1

R/W

0x0

GR8 User Manual(Version1.0)

RX FIFO Overrun Pending Interrupt

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Audio
0: No Pending IRQ
1: FIFO Overrun Pending IRQ

Write ‘1’ to clear this interrupt
0

/

/

/

7.1.4.8. ADC RX DATA Register(Default Value: 0x0000_0000)
Offset: 0x0024

Register Name: AC_ADC_RXDATA

Bit

Read/Write

Default/Hex

31:0

R

0x0

Description
RX_DATA.
RX Sample
Host can get one sample by reading this register. The left channel
sample data is first and then the right channel sample.

7.1.4.9. ADC Analog Control Register(Default Value: 0x0534_814C)
Offset:0x0028
Bit
Read/Write

Default/Hex

Register Name: AC_PA_ADC_ACTRL
Description
ADCREN.
ADC Right Channel Enable

31

R/W

0x0
0: Disable
1: Enable
ADCLEN.
ADC Left Channel Enable

30

R/W

0x0
0: Disable
1: Enable
PREG1EN.
MIC1 Pre-amplifier Enable

29

R/W

0x0
0: Disable
1: Enable
PREG2EN.

28

R/W

0x0

GR8 User Manual(Version1.0)

MIC2 Pre-amplifier Enable

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Audio
0: Disable
1: Enable
VMICEN.
VMIC Pin Voltage Enable
27

R/W

0x0
0: Disable
1: Enable
PREG1.
MIC1 Pre-Amplifier Gain Control

26:25

R/W

0x2

00: 0dB
01: 35dB
10: 38dB
11: 41dB
PREG2.
MIC2 Pre-Amplifier Gain Control

24:23

R/W

0x2

00: 0dB
01: 35dB
10: 38dB
11: 41dB
ADCG.
ADC Input Gain Control

000: -4.5dB
001: -3dB
22:20

R/W

0x3

010: -1.5dB
011: 0dB
100: 1.5dB
101: 3dB
110: 4.5dB
111: 6dB
ADCIS.

19:17

R/W

0x2

ADC Input Source Select

000: left select LINEINL, right select LINEINR; or, both select LINEINLGR8 User Manual(Version1.0)

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Audio
LINEINR, depending on LNRDF (bit 16)
001: Reserved
010: left and right channel both select MIC1 gain stage output
011: left and right channel both select MIC2 gain stage output
100: left select MIC1 gain stage output & right select MIC2 gain stage
output
101: left and right both select MIC1 gain stage plus MIC2 gain stage
output
110: left select output mixer L & right select output Mixer right
111: left select LINEINL or LINEINL-LINEINR, depending on LNRDF (bit
16), right select MIC1 gain stage
LNRDF.
Line-in-r Function Define
16

R/W

0x0
0: Line-in right channel which is independent of line-in left channel
1: Negative input of line-in left channel for fully differential
application
LNPREG.

15:13

R/W

0x4

Line-in Pre-amplifier Gain Control
From -12dB to 9dB, 3dB/step, default is 0dB
MIC1NEN.
Mic1Outn Enable

12

R/W

0x0
0: Disable
1: Enable

11:9

/

/

/
DITHER.
ADC Dither On/Off Control

8

R/W

0x1
0: Dither off
1: Dither on

7:6

R/W

0x1

/

5

/

/

/
PA_EN.

4

R/W

0x0

GR8 User Manual(Version1.0)

PA Enable

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Audio
0: Disable
1: Enable
DDE.
Headphone Direct-Drive Enable (DDE)
3

R/W

0x1
0: Disable
1: Enable
COMPTEN.
HPCOM Output Protection Enable

2

R/W

0x1
0: Protection disable
1: Protection enable
PTDBS.
HPCOM Protect De-bounce Time Setting

1:0

R/W

0x0

00: 2-3ms
01: 4-6ms
10: 8-12ms
11: 16-24ms

7.1.4.10. DAC TX Counter Register(Default Value: 0x0000_0000)
Offset: 0x0030
Bit

Read/Write

Register Name: AC_DAC_CNT
Default/Hex

Description
TX_CNT.
TX Sample Counter

31:0

R/W

The audio sample number of sending into TXFIFO. When one sample
is put into TXFIFO by DMA or by host IO, the TX sample counter
register increases by one. The TX sample counter register can be set
to any initial valve at any time. After been updated by the initial value,
the counter register should count on base of this initial value.

0x0

Note: It is used for Audio/ Video Synchronization

7.1.4.11. ADC RX Counter Register(Default Value: 0x0000_0000)
Offset: 0x0034
Bit
31:0

Read/Write
R/W

Register Name: AC_ADC_CNT
Default/Hex
0x0

GR8 User Manual(Version1.0)

Description
RX_CNT.

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Audio
RX Sample Counter
The audio sample number of writing into RXFIFO. When one sample
is written by Digital Audio Engine, the RX sample counter register
increases by one. The RX sample counter register can be set to any
initial valve at any time. After been updated by the initial value, the
counter register should count on base of this initial value.
Note: It is used for Audio/Video Synchronization

GR8 User Manual(Version1.0)

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Audio

7.2. I2S/PCM
7.2.1. Overview
The I2S/PCM can be configured as an I2S interface or PCM interface through software. When configured as an I2S
interface, it can support the industry standard format for I2S, left-justified, or right-justified. PCM is a standard
method used to transmit digital audio over digital communication channels. It supports 13 or 16-bits linear, 8-bit
Mu-law or A-law companding sample formats at 8K samples/s and can receive and transmit on any of the first four
slots following PCM_SYNC.
Features:
●

I2S or PCM configured by software

●

Full-duplex synchronous serial interface

●

Master/slave mode operation configured by software

●

Audio data resolutions of 16, 20, 24

●

I2S Audio data sample rate from 8 kHz to 192 kHz

●

I2S data format for standard I2S, Left Justified and Right Justified

●

PCM supports linear sample (8-bit or 16-bit), 8-bit u-law and A-law companding sample

●

One 128x24 bits FIFO for data transmit, one 64x24-bits FIFO for data receive

●

Programmable FIFO thresholds

●

Interrupt and DMA Support

7.2.2. I2S/PCM Block Diagram
The I2S/PCM block diagram is shown below.

DA_INT

RX_DRQ

TX_DRQ

Audio_PLL

Clock
Divide

Register
APB

BCLK

MCLK
128x24bits
RX FIFO

64x24-bits
TX FIFO

GR8 User Manual(Version1.0)

I2S_SCLK/PCM_CLK

I2S
Engine
S
Y
N
C

I2S_LRC/PCM_SYNC
M
U
X

PCM
Codec

PCM
Engine

I2S_SDO/PCM_OUT
I2S_SDI/PCM_IN

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Audio
Figure 6-5. I2S/PCM Block Diagram

7.2.3. I2S/PCM Timing Diagram

I2S_LRC

Left Channel

Right Channel

I2S_SCLK
I2S_SDO/SDI

MSB

LSB

MSB

LSB

Standard I2S Timing Diagram

Figure 6-6. I2S Timing Diagram

I2S_LRC

Left Channel

Right Channel

I2S_SCLK
I2S_SDO/SDI

MSB

LSB

MSB

LSB

Left-justified I2S Timing Diagram

Figure 6-7. I2S Left-justified Timing Diagram

I2S_LRC

Left Channel

Right Channel

I2S_SCLK
I2S_SDO/SDI

MSB

LSB

MSB

LSB

Right-justified I2S Timing Diagram

Figure 6-8. I2S Right-justified Timing Diagram

GR8 User Manual(Version1.0)

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Audio

PCM_SYNC

2 Clocks

PCM_CLK
PCM_OUT
PCM_IN

1
Undefined
1

2

3

4

5

6

7

8

2

3

4

5

6

7

8

Undefined

PCM Long Frame SYNC Timing Diagram (8-bits Companded Sample Example)

Figure 6-9. PCM Long Frame SYNC Timing Diagram

PCM_SYNC
PCM_CLK
PCM_OUT

1

2

3

4

5

6

7

8

9

10 11 12 13

14 15 16

PCM_IN

Undefined 1

2

3

4

5

6

7

8

9

10 11 12 13

14 15 16 Undefined

PCM Short Frame SYNC Timing Diagram (16-bits sample example)

Figure 6-10. PCM Short Frame SYNC Timing Diagram

7.2.4. I2S/PCM Register List
Module Name
I2S/PCM

Base Address
0x01C22400

Register Name
I2S/PCM_CTL
I2S/PCM_FAT0
I2S/PCM_FAT1
I2S/PCM_TXFIFO
I2S/PCM_RXFIFO
I2S/PCM_FCTL
I2S/PCM_FSTA
I2S/PCM_INT
I2S/PCM_ISTA
I2S/PCM_CLKD
I2S/PCM_TXCNT
I2S/PCM_RXCNT
I2S/PCM_TXCHSEL

Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030

GR8 User Manual(Version1.0)

Description
I2S/PCM Control Register
I2S/PCM Format Register 0
I2S/PCM Format Register 1
I2S/PCM TX FIFO Register
I2S/PCM RX FIFO Register
I2S/PCM FIFO Control Register
I2S/PCM FIFO Status Register
I2S/PCM Interrupt Control Register
I2S/PCM Interrupt Status Register
I2S/PCM Clock Divide Register
I2S/PCM RX Sample Counter Register
I2S/PCM TX Sample Counter Register
I2S/PCM TX Channel Select register

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Audio
I2S/PCM_TXCHMAP

0x0034

I2S/PCM TX Channel Mapping Register

7.2.5. I2S/PCM Register Description
7.2.5.1. I2S/PCM Control Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
31:9

Read/Write
/

Register Name: I2S/PCM_CTL
Default/Hex
/

Description
/
SDO_EN

8

R/W

0x0

0: Disable
1: Enable

7

/

/

/
ASS
Audio sample select when TX FIFO under run

6

R/W

0x0
0: Sending zero
1: Sending last audio sample
MS
Master Slave Select

5

R/W

0x0
0: Master
1: Slave
PCM

4

R/W

0x0

0: I2S Interface
1: PCM Interface
LOOP
Loop Back Test

3

R/W

0x0

0: Normal mode
1: Loop back test

When set ‘1’, connecting the SDO with the SDI in Master mode.
2

R/W

0x0

GR8 User Manual(Version1.0)

TXEN

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Audio
Transmitter Block Enable

0: Disable
1: Enable
RXEN
Receiver Block Enable
1

R/W

0x0
0: Disable
1: Enable
GEN
Globe Enable

0

R/W

A disable on this bit overrides any other block or channel enables.

0x0

0: Disable
1: Enable
7.2.5.2. I2S/PCM Format Register0(Default Value: 0x0000_000C)
Offset: 0x0004
Bit
31:8

Read/Write
/

Register Name: I2S/PCM_FAT0
Default/Hex
/

Description
/
LRCP
Left/ Right Clock Parity

0: Normal
7

R/W

0x0

1: Inverted

In DSP/ PCM mode
0: MSB is available on 2nd BCLK rising edge after LRC rising edge
1: MSB is available on 1st BCLK rising edge after LRC rising edge
BCP
BCLK Parity
6

R/W

0x0
0: Normal
1: Inverted

5:4

R/W

0x0

GR8 User Manual(Version1.0)

SR
Sample Resolution
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Audio

00: 16-bit
01: 20-bit
10: 24-bit
11: Reserved
WSS
Word Select Size

3:2

R/W

0x3

00: 16 BCLK
01: 20 BCLK
10: 24 BCLK
11: 32 BCLK
FMT
Serial Data Format

1:0

R/W

0x0

00: Standard I2S Format
01: Left Justified Format
10: Right Justified Format
11: Reserved

7.2.5.3. I2S/PCM Format Register1(Default Value: 0x0000_4020)
Offset: 0x0008
Bit
31:15

Read/Write
/

Register Name: I2S/PCM_FAT1
Default/Hex
/

Description
/
PCM SYNC Period Clock Number

000: 16 BCLK period
14:12

R/W

0x4

001: 32 BCLK period
010: 64 BCLK period
011: 128 BCLK period
100: 256 BCLK period
Others : Reserved
PCM Sync Out

11

R/W

0x0
0: Enable PCM_SYNC output in Master mode

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Audio
1: Suppress PCM_SYNC whilst keeping PCM_CLK running. Some Codec
utilize this to enter a low power state.
10

R/W

0x0

PCM Out Mute
Write 1 force PCM_OUT to 0
MLS
MSB/LSB First Select

9

R/W

0x0
0: MSB First
1: LSB First
SEXT
Sign Extend (only for 16 bits slot)

0: Zeros or audio gain padding at LSB position
8

R/W

0x0

1: Sign extension at MSB position

When writing, the bit is 0, the unused bits are audio gain for 13-bit linear
sample and zeros padding for 8-bit companding sample.
When writing, the bit is 1, the unused bits are both sign extension.
SI
Slot Index

7:6

R/W

0x0

00: the 1st slot
01: the 2nd slot
10: the 3rd slot
11: the 4th slot
SW
Slot Width

5

R/W

0x1

0: 8 clocks width
1: 16 clocks width

Note: For A-law or u-law PCM sample, if this bit is set to 1, eight zero bits
are following with PCM sample.
SSYNC
4

R/W

0x0

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Short Sync Select

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Audio
0: Long Frame Sync
1: Short Frame Sync

It should be set ‘1’ for 8 clocks width slot.
RX PDM
PCM Data Mode

3:2

R/W

0x0

00: 16-bit Linear PCM
01: 8-bit Linear PCM
10: 8-bit u-law
11: 8-bit A-law
TX PDM
PCM Data Mode

1:0

R/W

0x0

00: 16-bit Linear PCM
01: 8-bit Linear PCM
10: 8-bit u-law
11: 8-bit A-law

7.2.5.4. I2S/PCM TX FIFO Register(Default Value: 0x0000_0000)
Offset: 0x000C

Register Name: I2S/PCM_TXFIFO

Bit

Read/Write

Default/Hex

Description
TX Sample

31:0

W

0x0

Transmitting left, right channel sample data should be written this
register one by one. The left channel sample data is first and then the
right channel sample.

7.2.5.5. I2S/PCM RX FIFO Register(Default Value: 0x0000_0000)
Offset: 0x0010

Register Name: I2S/PCM_RXFIFO

Bit

Read/Write

Default/Hex

Description
RX Sample

31:0

R

0x0

Host can get one sample by reading this register. The left channel sample
data is first and then the right channel sample.

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Audio
7.2.5.6. I2S/PCM FIFO Control Register(Default Value: 0x0004_00F0)
Offset: 0x0014
Bit

Read/Write

Register Name: I2S/PCM_FCTL
Default/Hex

Description
FIFOSRC
TX FIFO source select

31

R/W

0x0
0: APB bus
1: Analog Audio Codec

30:26

/

/

25

R/W

0x0

24

R/W

0x0

23:19

/

/

/
FTX
Write ‘1’ to flush TX FIFO, self clear to ‘0’.
FRX
Write ‘1’ to flush RX FIFO, self clear to ‘0’.
/
TXTL

18:12

R/W

0x40

TX FIFO Empty Trigger Level
Interrupt and DMA request trigger level for TXFIFO normal condition
Trigger Level = TXTL

11:10

/

/

/
RXTL

9:4

R/W

0xF

RX FIFO Trigger Level
Interrupt and DMA request trigger level for RXFIFO normal condition
Trigger Level = RXTL + 1

3

/

/

/
TXIM
TX FIFO Input Mode (Mode 0, 1)

0: Valid data at the MSB of TXFIFO register
2

R/W

0x0

1: Valid data at the LSB of TXFIFO register

Example for 20-bit transmitted audio sample:
Mode 0: FIFO_I[23:0] = {4’h0, TXFIFO[31:12]}
Mode 1: FIFO_I[23:0] = {4’h0, TXFIFO[19:0]}
1:0

R/W

0x0

GR8 User Manual(Version1.0)

RXOM
RX FIFO Output Mode (Mode 0, 1, 2, 3)

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Page 382

Audio

00: Expanding ‘0’ at LSB of DA_RXFIFO register.
01: Expanding received sample sign bit at MSB of DA_RXFIFO register.
10: Truncating received samples at high half-word of DA_RXFIFO register
and low half-word of DA_RXFIFO register is filled by ‘0’.
11: Truncating received samples at low half-word of DA_RXFIFO register
and high half-word of DA_RXFIFO register is expanded by its sign bit.

Example for 20-bit received audio sample:
Mode 0: RXFIFO[31:0] = {FIFO_O[19:0], 12’h0}
Mode 1: RXFIFO[31:0] = {12{FIFO_O[19]}, FIFO_O[19:0]}
Mode 2: RXFIFO[31:0] = {FIFO_O[19:4], 16’h0}
Mode 3: RXFIFO[31:0] = {16{FIFO_O[19], FIFO_O[19:4]}

7.2.5.7. I2S/PCM FIFO Status Register(Default Value: 0x1080_0000)
Offset: 0x0018
Bit
31:29

Read/Write
/

Register Name: I2S/PCM_FSTA
Default/Hex
/

Description
/
TXE
TX FIFO Empty

28

R

0x1
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)

27:24

/

/

23:16

R

0x80

15:9

/

/

/
TXE_CNT
TX FIFO Empty Space Word Counter
/
RXA
RX FIFO Available

8

R

0x0
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)

7

/

/

6:0

R

0x0

GR8 User Manual(Version1.0)

/
RXA_CNT
RX FIFO Available Sample Word Counter

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Audio
7.2.5.8. I2S/PCM DMA&Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
31:8

Read/Write
/

Register Name: I2S/PCM_INT
Default/Hex
/

Description
/
TX_DRQ
TX FIFO Empty DRQ Enable

7

R/W

0x0
0: Disable
1: Enable
TXUI_EN
TX FIFO Underrun Interrupt Enable

6

R/W

0x0
0: Disable
1: Enable
TXOI_EN
TX FIFO Overrun Interrupt Enable

5

R/W

0x0

0: Disable
1: Enable

When set to ‘1’, an interrupt happens when writing new audio data if TX
FIFO is full.
TXEI_EN
TX FIFO Empty Interrupt Enable
4

R/W

0x0
0: Disable
1: Enable
RX_DRQ
RX FIFO Data Available DRQ Enable

3

R/W

0x0

0: Disable
1: Enable

When set to ‘1’, RXFIFO DMA Request line is asserted if Data is available
in RX FIFO.
2

R/W

0x0

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RXUI_EN

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Audio
RX FIFO Underrun Interrupt Enable

0: Disable
1: Enable
RXOI_EN
RX FIFO Overrun Interrupt Enable
1

R/W

0x0
0: Disable
1: Enable
RXAI_EN
RX FIFO Data Available Interrupt Enable

0

R/W

0x0
0: Disable
1: Enable

7.2.5.9. I2S/PCM Interrupt Status Register(Default Value: 0x0000_0010)
Offset: 0x0020
Bit
31:7

Read/Write
/

Register Name: I2S/PCM_ISTA
Default/Hex
/

Description
/
TXU_INT
TX FIFO Underrun Pending Interrupt

6

R/W

0x0
0: No Pending Interrupt
1: FIFO Underrun Pending Interrupt
TXO_INT
TX FIFO Overrun Pending Interrupt

5

R/W

0x0

0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt

Write ‘1’ to clear this interrupt
TXE_INT
4

R/W

0x1

TX FIFO Empty Pending Interrupt

0: No Pending IRQ

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Audio
1: FIFO Empty Pending Interrupt

Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails.
3:2

/

/

/
RXO_INT
RX FIFO Overrun Pending Interrupt

1

R/W

0x0

0: No Pending IRQ
1: FIFO Overrun Pending IRQ

Write ‘1’ to clear this interrupt
RXA_INT
RX FIFO Data Available Pending Interrupt

0

R/W

0: No Pending IRQ

0x0

1: Data Available Pending IRQ

Write ‘1’ to clear this interrupt or automatically clear if interrupt
condition fails.

7.2.5.10. I2S/PCM Clock Divide Register(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
31:8

Read/Write
/

Register Name: I2S/PCM_CLKD
Default/Hex
/

Description
/
MCLKO_EN

0: Disable MCLK Output
7

R/W

0x0

1: Enable MCLK Output

Note: Whether in Slave or Master mode, when this bit is set to 1, MCLK
should be output.
BCLKDIV
6:4

R/W

0x0

BCLK Divide Ratio from MCLK

000: Divide by 2 (BCLK = MCLK/2)

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Audio
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 12
101: Divide by 16
110: Divide by 32
111: Divide by 64
MCLKDIV
MCLK Divide Ratio from Audio PLL Output

0000: Divide by 1
0001: Divide by 2
0010: Divide by 4
0011: Divide by 6
3:0

R/W

0x0

0100: Divide by 8
0101: Divide by 12
0110: Divide by 16
0111: Divide by 24
1000: Divide by 32
1001: Divide by 48
1010: Divide by 64
Others : Reserved

7.2.5.11. I2S/PCM TX Counter Register(Default Value: 0x0000_0000)
Offset: 0x0028

Register Name: I2S/PCM_TXCNT

Bit

Read/Write

Default/Hex

31:0

R/W

0x0

Description
TX Sample Counter
The audio sample number of sending into TXFIFO. When one sample is
put into TXFIFO by DMA or by host IO, the TX sample counter register
increases by one. The TX sample counter register can be set to any initial
valve at any time. After been updated by the initial value, the counter
register should count on base of this initial value.

7.2.5.12. I2S/PCM RX Counter Register(Default Value: 0x0000_0000)
Offset: 0x002C

GR8 User Manual(Version1.0)

Register Name: I2S/PCM_RXCNT

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Audio
Bit

Read/Write

Default/Hex

31:0

R/W

0x0

Description
RX Sample Counter
The audio sample number of writing into RXFIFO. When one sample is
written by Digital Audio Engine, the RX sample counter register increases
by one. The RX sample counter register can be set to any initial valve at
any time. After been updated by the initial value, the counter register
should count on base of this initial value.

7.2.5.13. I2S/PCM TX Channel Select Register(Default Value: 0x0000_0001)
Offset: 0x0030

Register Name: I2S/PCM_TXCHSEL

Bit

Read/Write

Default/Hex

Description

31:3

/

/

/
Channel_Select

2:0

R/W

0x1

0: 1-ch
1: 2-ch
Others: Reserved

7.2.5.14. I2S/PCM TX Channel Mapping Register(Default Value: 0x7654_3210)
Offset: 0x0034
Bit
31:7

Read/Write
/

Register Name: I2S/PCM_TXCHMAP
Default/Hex
/

Description
/
CH1_MAP

6:4

R/W

0x1

000: 1st sample
001: 2nd sample
Others: Reserved

3

/

/

/
CH0_MAP

2:0

R/W

0x0

000: 1st sample
001: 2nd sample
Others: Reserved

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Audio
7.2.5.15. I2S/PCM RX Channel Select Register(Default Value: 0x0000_0001)
Offset: 0x0038

Register Name: I2S/PCM_RXCHSEL

Bit

Read/Write

Default/Hex

Description

31:3

/

/

/
Channel_Select

000: 1-ch
2:0

R/W

0x1

001: 2-ch
010: 3-ch
011: 4-ch
Others: Reserved

7.2.5.16. I2S/PCM RX Channel Mapping Register(Default Value: 0x0000_3210)
Offset: 0x003C
Bit
31:15

Read/Write
/

Register Name: I2S/PCM_RXCHMAP
Default/Hex
/

Description
/
CH3_MAP
000: 1st sample

14:12

R/W

0x3

001: 2nd sample
010: 3rd sample
011: 4th sample
Others: Reserved

11

/

/

/
CH2_MAP
000: 1st sample

10:8

R/W

0x2

001: 2nd sample
010: 3rd sample
011: 4th sample
Others: Reserved

7

/

/

/
CH1_MAP

6:4

R/W

0x1
000: 1st sample

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Audio
001: 2nd sample
010: 3rd sample
011: 4th sample
Others: Reserved
3

/

/

/
CH0_MAP
000: 1st sample

2:0

R/W

001: 2nd sample

0x0

010: 3rd sample
011: 4th sample
Others: Reserved

7.3. OWA
7.3.1. Overview
The OWA (One Wire Audio) provides a serial bus interface between the system and the codec chip. This interface
is widely used for consumer audio connections.
Features:


IEC-60958 transmitter functionality



Complies with S/PDIF Interface



Supports channel status insertion for the transmitter



Hardware parity generation on the transmitter



One 32×24 bits TX FIFO for audio data transfer



Programmable FIFO thresholds



Interrupt and DMA support

7.3.2. OWA Block Diagram
Figure 7-8 shows a block diagram of the OWA.

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Audio

Registers

FSM & Control

Channel status
& user data
buffers

Transmitter

TX FIFO

Clock Divider

APB
I/F
OWA_OUT

DMA & INT

Figure 6-11. OWA Block Diagram

7.3.3. OWA Frame Format
0

7 8

3 4

Sync
preamble

Aux

L
S
B

27 28

31

M
S V U C P
B

Audio sample word

Validity flag
User data
Channel status
Parity bit

Figure 6-12. Sub-Frame Format

M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1
Sub-frame
Frame 191

Channel 2 M Channel 1 W Channel 2

Sub-frame
Frame 191

Frame 0
Block

Figure 6-13. Frame/Block Format

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Audio

Clock
128×FS

Data
1

0

1

1

0

0

1

0

1

1

0

1 0

1 1

0 1

0 1

0 0

0 0

0 1

0 1

1 0

1 0

1 1

BMC

Figure 6-14. Biphase-Mark Encoding

7.3.4. OWA Register List
Module Name
OWA

Base Address
0x01C21000

Register Name
OWA_GEN_CTL
OWA_TX_CFIG
OWA_ISTA
OWA_FCTL
OWA_FSTA
OWA_INT
OWA_ISTA
OWA_TX_CNT
OWA_TX_CHSTA0
OWA_TX_CHSTA1

Offset
0x0000
0x0004
0x000C
0x0014
0x0018
0x001C
0x0020
0x0024
0x002C
0x0030

Description
OWA General Control
OWA TX Configuration Register
OWA Interrupt Status Register
OWA FIFO Control Register
OWA FIFO Status Register
OWA Interrupt Control Register
OWA Interrupt Status Register
OWA TX Counter Register
OWA TX Channel Status Register0
OWA TX Channel Status Register1

7.3.5. OWA Register Description
7.3.5.1. OWA General Control Register(Default Value: 0x0000_0080)
Offset: 0x0000
Bit
31:10

Read/Write
/

Register Name: OWA_CTL
Default/Hex
/

Description
/
MCLK_DIV_RATIO

9:4

R/W

0x08

Mclk divide Ratio
Note: Only support 2n divide ratio (n=1~31)

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Audio
3

/

/

/
MCLK_OUT_EN
Mclk Output Enable

2

R/W

0x0
0: Disable
1: Enable
GEN
Globe Enable

1

R/W

A disable on this bit overrides any other block or channel enables and
flushes all FIFOs.

0x0

0: Disable
1: Enable
Reset

0

R/W

0x0

0: N 0: Normal
1: Reset

Self clear to 0

7.3.5.2. OWA TX Configure Register(Default Value: 0x0000_00F0)
Offset: 0x0004
Bit

Read/Write

Register Name: OWA_TX_CFG
Default/Hex

Description
TX_SINGLE_MODE
Tx Single Channel Mode

31

R/W

0x0
0: Disable
1: Enable

30:18

/

/

/
ASS
Audio sample select with TX FIFO under run when

17

R/W

0x0

0: Sending 0
1: Sending the last audio

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Audio
Note: This bit is only valid in PCM mode
TX_AUDIO
TX Data Type
16

R/W

0x0
0: Linear PCM (Valid bit of both sub-frame set to 0)
1: Non-audio(Valid bit of both sub-frame set to 1)

15:9

/

/

/
TX RATIO

8:4

R/W

0xF

TX Clock Divide Ratio
Note: clock divide ratio = TX TATIO +1
TX Sample Format

3:2

R/W

00: 16-bit

0x0

01: 20-bit
10: 24-bit
11: Reserved
CHSTMODE

1

R/W

0x0

0: Channel status A&B set to 0
1: Channel status A&B generated form TX_CHSTA
TXEN

0

R/W

0x0

0: Disable
1: Enable

7.3.5.3. OWA TX FIFO Register(Default Value: 0x0000_0000)
Offset: 0x000C

Register Name: OWA_TX_FIFO

Bit

Read/Write

Default/Hex

Description

31:0

W

0x0

Transmitting A, B channel data should be written this register one by one.
The A channel data is first and then the B channel data.

7.3.5.4. OWA FIFO Control Register(Default Value: 0x0000_1078)
Offset: 0x0014
Bit

Read/Write

Register Name: OWA_FCTL
Default/Hex

GR8 User Manual(Version1.0)

Description

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Page 394

Audio
FIFOSRC
TX FIFO source select
31

R/W

0x0
0: APB bus
1: Analog Audio CODEC

30:18

/

/

17

R/W

0x0

16:13

/

/

/
FTX
Write “1” to flush TX FIFO, self clear to “0”
/
TXTL

12:8

R/W

TX FIFO Empty Trigger Level

0x10

Interrupt and DMA request trigger level for TX FIFO normal condition
Trigger Level = TXTL

7:3

R/W

0xF

Reserved
TXIM
TX FIFO Input Mode(Mode0, 1)

0: Valid data at the MSB of SPDIF_TXFIFO register
2

R/W

0x0

1: Valid data at the LSB of SPDIF_TXFIFO register

Example for 20-bit transmitted audio sample:
Mode 0: FIFO_I[23:0] = {TXFIFO[31:12], 4’h0}
Mode 1: FIFO_I[23:0] = {TXFIFO[19:0], 4’h0}
1:0

R/W

0x0

Reserved

7.3.5.5. OWA FIFO Status Register(Default Value: 0x0000_6000)
Offset: 0x0018
Bit
31:15

Read/Write
/

Register Name: OWA_FSTA
Default/Hex
/

Description
/
TXE
TX FIFO Empty

14

R

0x1
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO ( >=1 word )

13:8

R

0x20

GR8 User Manual(Version1.0)

TXE_CNT

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Page 395

Audio
TX FIFO Empty Space Word counter
7:0

/

/

/

7.3.5.6. OWA Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
31:8

Read/Write
/

Register Name: OWA_INT
Default/Hex
/

Description
/
TX_DRQ
TX FIFO Empty DRQ Enable

7

R/W

0x0
0: Disable
1: Enable
TXUI_EN
TX FIFO Underrun Interrupt Enable

6

R/W

0x0
0: Disable
1: Enable
TXOI_EN
TX FIFO Overrun Interrupt Enable

5

R/W

0x0
0: Disable
1: Enable
TXEI_EN
TX FIFO Empty Interrupt Enable

4

R/W

0x0
0: Disable
1: Enable

3:0

/

/

/

7.3.5.7. OWA Interrupt Status Register(Default Value: 0x0000_0010)
Offset: 0x0020

Register Name: OWA_ISTA

Bit
31:7

Read/Write
/

Default/Hex
/

Description
/

6

R/W

0x0

TXU_INT

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Audio
TX FIFO Underrun Pending Interrupt

0: No pending IRQ
1: FIFO Under run Pending Interrupt

Write “1” to clear this interrupt
TXO_INT
TX FIFO Overrun Pending Interrupt

5

R/W

0x0

0: No Pending IRQ
1: FIFO Overrun Pending Interrupt

Write “1” to clear this interrupt
TXE_INT
TX FIFO Empty Pending Interrupt

4

R/W

0: No Pending IRQ

0x1

1: FIFO Empty Pending Interrupt

Write “1” to clear this interrupt or automatically clear if interrupt
condition fails.
3:0

/

/

/

7.3.5.8. OWA TX Counter Register(Default Value: 0x0000_0000)
Offset: 0x0024

Register Name: OWA_TX_CNT

Bit

Read/Write

Default/Hex

31:0

R/W

0x0

Description
TX Sample Counter

The audio sample number of writing into TX FIFO. When one sample is
written by DMA or by host IO, the TX sample counter register increases
by one. The TX Counter register can be set to any initial value at any time.
After been updated by the initial value, the counter register should count
on base of this value.

7.3.5.9. OWA TX Channel Status Register0(Default Value: 0x0000_0000)
Offset: 0x002C

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Register Name: OWA_TX_CHSTA0

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Audio
Bit
31: 30

Read/Write
/

Default/Hex
/

Description
/
Clock Accuracy

29:28

R/W

0x0

00: Level 2
01: Level 1
10: Level 3
11: not matched
Sampling Frequency

27:24

R/W

0x0

0000: 44.1kHz

1000: Reserved

0001: not indicated

1001: 768kHz

0010: 48kHz

1010: 96kHz

0011: 32kHz

1011: Reserved

0100: 22.05kHz

1100:176.4kHz

0101: Reserved

1101: Reserved

0110: 24kHz

1110: 192kHz

0111: Reserved

1111: Reserved

23:20

R/W

0x0

Channel Number

19:16

R/W

0x0

Source Number
Category Code

15:8

R/W

0x0

Indicates the kind of equipment that generates the digital audio interface
signal.
Mode

7:6

R/W

0x0

00: Default Mode
01~11: Reserved
Emphasis
Additional Format Information

For bit 1 = “0”, Linear PCM audio mode:
5:3

R/W

0x0

000: 2 audio channels without pre-emphasis
001: 2 audio channels with 50 μs / 15 μs pre-emphasis
010: Reserved (for 2 audio channels with pre-emphasis)
011: Reserved (for 2 audio channels with pre-emphasis)
100~111: Reserved

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For bit 1 = “1”, other than Linear PCM applications:
000: Default state
001~111: Reserved
CP
Copyright
2

R/W

0x0
0: Copyright is asserted
1: No copyright is asserted
Audio
Data Type

1

R/W

0x0
0: Linear PCM Samples
1: For none-linear PCM audio such as AC3, DTS, MPEG audio
PRO
Application Type

0

R/W

0x0

0: Consumer Application
1: Professional Application

Note: This bit must be fixed to “0”

7.3.5.10. OWA TX Channel Status Register1(Default Value: 0x0000_0000)
Offset: 0x0030
Bit
31:10

Read/Write
/

Register Name: OWA_TX_CHSTA1
Default/Hex
/

Description
/
CGMS-A

9:8

R/W

0x0

00: Copying is permitted without restriction
01: One generation of copies may be made
10: Condition not be used
11: No copying is permitted
Original Sampling Frequency

7:4

R/W

0x0
0000: not indicated

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Audio
0001: 192kHz
0010: 12kHz
0011: 176.4kHz
0100: Reserved
0101: 96kHz
0110: 8kHz
0111: 88.2kHz
1000: 16kHz
1001: 24kHz
1010: 11.025kHz
1011: 22.05kHz
1100: 32kHz
1101: 48kHz
1110: Reserved
1111: 44.1kHz
Sample Word Length
For bit 0 = “0”:
000: not indicated
001: 16 bits
010: 18 bits
100: 19 bits
101: 20 bits
110: 17 bits
3:1

R/W

0x0

111: Reserved

For bit 0 = “1”:
000: not indicated
001: 20 bits
010: 22 bits
100: 23 bits
101: 24 bits
110: 21 bits
111: Reserved
0

R/W

0

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Max Word Length

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Audio
0: Maximum audio sample word length is 20 bits
1: Maximum audio sample word length is 24 bits

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Chapter 8. Interfaces
This chapter describes GR8 interfaces, including:
 TWI
 SPI
 UART
 CIR
 USB OTG
 USB Host

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8.1. TWI
8.1.1. Overview
The Two Wire Interface (TWI) controller is designed to be used as an interface between the CPU host and the serial
2-wire bus. It can support all the standard 2-wire transfer, including slave and master. The communication of the
2-wire bus is carried out by a byte-wise mode based on interrupted or polled handshaking. This TWI controller can
be operated in standard mode (100 kbit/s) or fast-mode, supporting data rates up to 400 kbit/s. Multi-masters and
10-bit addressing mode are supported for this specified application. General call addressing is also supported in
slave mode.
Features:
●

Software-programmable for Slave or Master

●

Supports Repeated START signal

●

Supports 10-bit addressing with 2-Wire bus

●

Perform arbitration and clock synchronization

●

Own address and General Call address detection

●

Interrupt on address detection

●

Supports speed up to 400 kbit/s (‘fast mode’)

●

Supports operation from a wide range of input clock frequencies

8.1.2. TWI Timing Diagram
Data is always transferred:
1) In unit of byte (8-bit);
2) Each byte followed by an acknowledge bit;
3) Unlimited number of byte in each data transfer;
4) Data is transferred in serial, with MSB first;
5) The receiver will hold SCL low to force the transmitter to enter a wait state while it is waiting for responses
from the microprocessor after every byte transfer.

An acknowledge signal is indispensable in data transfer, and a related acknowledge clock pulse is generated by the
master. After sending a byte, the transmitter will release the SDA line, and one of the following two cases will occur:
The SDA is pulled down by the receiver and an acknowledge signal is sent back;
The SDA is left high, and a “not acknowledged” signal is sent back;
When the slave receiver does not acknowledge the slave address (because of resource deficiency), the SDA will be
left high for the master to generate a STOP condition to abort the transfer.

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When the slave receiver acknowledges the slave address, but not ready to receive more during a data transfer, the
SDA will be left high for the master to generate a STOP condition to abort the transfer.
The following diagram provides an illustration to the relation between SDA signal line and SCL signal line on the 2Wire serial bus.

SDA
IIC1

IIC3

IIC4

IIC5

IIC2

SCL

Figure 8-1. TWI Timing Diagram

8.1.3. TWI Controller Special Requirement
8.1.3.1. TWI Pin List
Port Name
TWI_SCL
TWI_SDA

Width
1
1

Direction
IN/OUT
IN/OUT

Description
TWI Clock line
TWI Serial Data line

8.1.3.2. TWI Controller Operation
There are four operation modes on the two-wire bus which dictate the communication method: Master Transmit,
Master Receive, Slave Transmit and Slave Receive. In general, the CPU host controls TWI by writing commands and
data to its registers. The TWI interrupts the CPU host for the attention each time a byte transfer is done or a
START/STOP condition is detected. The CPU host can also poll the status register for the current status if the
interrupt mechanism is not disabled by the CPU host.
When the CPU host wants to start a bus transfer, it initiates a bus START to enter the master mode by setting
IM_STA bit in the 2WIRE_CNTR register to high (before it must be low). The TWI will assert INT line and INT_FLAG
to indicate a completion for the START condition and each consequent byte transfer. At each interrupt, the microprocessor needs to check the 2WIRE_STAT register for the current status. A transfer has to be concluded with a
STOP condition by setting the M_STP bit high.
In Slave Mode, the TWI also constantly samples the bus and looks for its own slave address during addressing
cycles. Once a match is found, it is addressed and interrupts the CPU host with the corresponding status. Upon
request, the CPU host should read the status, read/write 2WIRE_DATA data register, and set the 2WIRE_CNTR
control register. After each byte transfer, a slave device always halts the operation of the remote master by holding
the next low pulse on the SCL line until the microprocessor responds to the status of the previous byte transfer or
START condition.

8.1.4. TWI Controller Register List
Module Name

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Base Address

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TWI0
TWI1
TWI2

0x01C2AC00
0x01C2B000
0x01C2B400

Register Name

Offset

Description

TWI_ADDR

0x0000

TWI Slave Address

TWI_XADDR

0x0004

TWI Extended Slave Address

TWI_DATA

0x0008

TWI Data Byte

TWI_CNTR

0x000C

TWI Control Register

TWI_STAT

0x0010

TWI Status Register

TWI_CCR

0x0014

TWI Clock Control Register

TWI_SRST

0x0018

TWI Software Reset

TWI_EFR

0x001C

TWI Enhance Feature Register

TWI_LCR

0x0020

TWI Line Control Register

8.1.5. TWI Controller Register Description
8.1.5.1. TWI Slave Address Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
31:8

Read/Write
/

Register Name: TWI_ADDR
Default/Hex
/

Description
/
SLA
Slave address
7-bit addressing

7:1

R/W

0x0

SLA6, SLA5, SLA4, SLA3, SLA2, SLA1, SLA0

10-bit addressing
1, 1, 1, 1, 0, SLAX[9:8]
GCE
General call address enable
0

R/W

0x0
0: Disable
1: Enable

Note:
For 7-bit addressing:
SLA6 – SLA0 is the 7-bit address of TWI in slave mode. When TWI receives this address after a START condition, it
will generate an interrupt and enter slave mode. (SLA6 corresponds to the first bit received from the two wire bus.)
If GCE is set to ‘1’, the TWI will also recognize the general call address (00h).
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For 10-bit addressing:
When the address received starts with 11110b, the TWI recognizes this as the first part of a 10-bit address and if
the next two bits match ADDR[2:1] (i.e. SLAX9 and SLAX8 of the device’s extended address), it sends an ACK. (The
device does not generate an interrupt at this point.) If the next byte of the address matches the XADDR register
(SLAX7 – SLAX0), the TWI generates an interrupt and goes into slave mode.

8.1.5.2. TWI Extend Address Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
31:8

Read/Write
/

Register Name: TWI_XADDR
Default/Hex
/

Description
/
SLAX

7:0

R/W

0x0

Extend Slave Address
SLAX[7:0]

8.1.5.3. TWI Data Register(Default Value: 0x0000_0000)
Offset: 0x0008
Bit
Read/Write

Default/Hex

Register Name: TWI_DATA
Description

31:8

/

/

/

7:0

R/W

0x0

Data byte for transmitting or receiving

8.1.5.4. TWI Control Register(Default Value: 0x0000_0000)
Offset: 0x000C
Bit
31:8

Read/Write
/

Register Name: TWI_CNTR
Default/Hex
/

Description
/
INT_EN
Interrupt Enable

7

R/W

0x0
0: The interrupt line always low
1: The interrupt line will go high when INT_FLAG is set.
BUS_EN
two-wire bus Enable

6

R/W

0x0
0: The two-wire bus inputs ISDA/ISCL are ignored and the 2-Wire
Controller will not respond to any address on the bus
1: The TWI will respond to calls to its slave address – and to the general

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call address if the GCE bit in the ADDR register is set.

Note: In master operation mode, this bit should be set to ‘1’
M_STA
Master Mode Start

5

R/W

0x0

When M_STA is set to ‘1’, TWI controller enters master mode and will
transmit a START condition on the bus when the bus is free. If the M_STA
bit is set to ‘1’ when the 2-Wire Controller is already in master mode and
one or more bytes have been transmitted, then a repeated START
condition will be sent. If the M_STA bit is set to ‘1’ when the TWI is being
accessed in slave mode, the TWI will complete the data transfer in slave
mode then enter master mode when the bus has been released.

The M_STA bit is cleared automatically after a START condition is sent:
writing a ‘0’ to this bit has no effect.
M_STP
Master Mode Stop

4

R/W

0x0

If M_STP is set to ‘1’ in master mode, a STOP condition is transmitted on
the two-wire bus. If the M_STP bit is set to ‘1’ in slave mode, the TWI will
behave as if a STOP condition has been received, but no STOP condition
will be transmitted on the two-wire bus. If both M_STA and M_STP bits
are set, the TWI will first transmit the STOP condition (if in master mode),
and then transmit the START condition.

The M_STP bit is cleared automatically: writing a ‘0’ to this bit has no
effect.
INT_FLAG
Interrupt Flag

3

R/W

0x0

INT_FLAG is automatically set to ‘1’ when any of 28 (out of the possible
29) states is entered (see ‘STAT Register’ below). The only state that does
not set INT_FLAG is state F8h. If the INT_EN bit is set, the interrupt line
goes high when IFLG is set to ‘1’. If the TWI is operating in slave mode,
data transfer is suspended when INT_FLAG is set and the low period of
the two-wire bus clock line (SCL) is stretched until ‘0’ is written to
INT_FLAG. The 2-wire clock line is then released and the interrupt line
goes low.
A_ACK
Assert Acknowledge

2

R/W

0x0

When A_ACK is set to ‘1’, an Acknowledge (low level on SDA) will be sent
during the acknowledge clock pulse on the two-wire bus if:
(1). Either the whole of a matching 7-bit slave address or the first or the
second byte of a matching 10-bit slave address has been received.

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Interfaces

(2). The general call address has been received and the GCE bit in the
ADDR register is set to ‘1’.

(3). A data byte has been received in master or slave mode.
When A_ACK is ‘0’, a Not Acknowledge (high level on SDA) will be sent
when a data byte is received in master or slave mode.

If A_ACK is cleared to ‘0’ in slave transmitter mode, the byte in the DATA
register is assumed to be the ‘last byte’. After this byte is transmitted,
the TWI will enter state C8h then return to the idle state (status code
F8h) when INT_FLAG is cleared.

The TWI will not respond as a slave unless A_ACK is set.
1:0

/

/

/

8.1.5.5. TWI Status Register(Default Value: 0x0000_00F8)
Offset: 0x0010
Bit
Read/Write

Default/Hex

Register Name: TWI_STAT
Description

31:8

/

/

/

Status Information Byte
Code Status

0x00: Bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
7:0

R

0xF8

0x28: Data byte transmitted in master mode, ACK received
0x30: Data byte transmitted in master mode, ACK not received
0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK transmitted
0x58: Data byte received in master mode, not ACK transmitted
0x60: Slave address + Write bit received, ACK transmitted
0x68: Arbitration lost in address as master, slave address + Write bit

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received, ACK transmitted
0x70: General Call address received, ACK transmitted
0x78: Arbitration lost in address as master, General Call address
received, ACK transmitted
0x80: Data byte received after slave address received, ACK transmitted
0x88: Data byte received after slave address received, not ACK
transmitted
0x90: Data byte received after General Call received, ACK transmitted
0x98: Data byte received after General Call received, not ACK
transmitted
0xA0: STOP or repeated START condition received in slave mode
0xA8: Slave address + Read bit received, ACK transmitted
0xB0: Arbitration lost in address as master, slave address + Read bit
received, ACK transmitted
0xB8: Data byte transmitted in slave mode, ACK received
0xC0: Data byte transmitted in slave mode, ACK not received
0xC8: Last byte transmitted in slave mode, ACK received
0xD0: Second Address byte + Write bit transmitted, ACK received
0xD8: Second Address byte + Write bit transmitted, ACK not received
0xF8: No relevant status information, INT_FLAG=0
Others: Reserved

8.1.5.6. TWI Clock Register(Default Value: 0x0000_0000)
Offset: 0x0014
Bit
Read/Write

Default/Hex

Register Name: TWI_CCR
Description

31:7

/

/

/

6:3

R/W

0x0

CLK_M
CLK_N
The two-wire bus is sampled by the TWI at the frequency defined by F0:
Fsamp = F0 = Fin / 2^CLK_N

2:0

R/W

0x0

The TWI OSCL output frequency, in master mode, is F1 / 10:
F1 = F0 / (CLK_M + 1)
Foscl = F1 / 10 = Fin / (2^CLK_N * (CLK_M + 1)*10)
For Example：
Fin = 48 MHz (APB clock input)

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For 400 kHz full speed 2Wire, CLK_N = 2, CLK_M=2
F0 = 48 MHz/2^2=12 MHz, F1= F0/(10*(2+1)) = 0.4 MHz

For 100 kHz standard speed 2 Wire, CLK_N=2, CLK_M=11
F0=48 MHz/2^2=12 MHz, F1=F0/(10*(11+1)) = 0.1 MHz

8.1.5.7. TWI Soft Reset Register(Default Value: 0x0000_0000)
Offset: 0x0018
Bit
31:1

Read/Write
/

Register Name: TWI_SRST
Default/Hex
/

Description
/
Soft Reset

0

R/W

0x0

Write ‘1’ to this bit to reset the TWI and clear to ‘0’ when complete Soft
Reset operation.

8.1.5.8. TWI Enhance Feature Register(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
Read/Write

Default/Hex

Register Name: TWI_EFR
Description

31:2

/

/

/

Data Byte follow Read Command Control
No Data Byte to be written after read command
0:1

R/W

0x0

Only 1 byte data to be written after read command
2 bytes data can be written after read command
3 bytes data can be written after read command

8.1.5.9. TWI Line Control Register(Default Value: 0x0000_003A)
Offset: 0x0020
Bit
31:6

Read/Write
/

Register Name: TWI_LCR
Default/Hex
/

Description
/
Current state of TWI_SCL

5

R

0x1

0: Low
1: High

4

R

0x1

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Current state of TWI_SDA

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0: Low
1: High
TWI_SCL line state control bit
When line control mode is enabled (bit[2] set), value of this bit decides
the output level of TWI_SCL
3

R/W

0x1
0: Output low level
1: Output high level
TWI_SCL line state control enable
When this bit is set, the state of TWI_SCL is controlled by the value of
bit[3].

2

R/W

0x0
0: Disable TWI_SCL line control mode
1: Enable TWI_SCL line control mode
TWI_SDA line state control bit
When line control mode is enabled (bit[0] set), value of this bit decides
the output level of TWI_SDA

1

R/W

0x1
0: Output low level
1: Output high level
TWI_SDA line state control enable
When this bit is set, the state of TWI_SDA is controlled by the value of
bit[1].

0

R/W

0x0
0: Disable TWI_SDA line control mode
1: Enable TWI_SDA line control mode

8.1.5.10. TWI DVFS Control Register(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
31:2

Read/Write
/

Register Name: TWI_DVFSCR
Default/Hex
/

Description
/
CPU and DVFS BUSY set priority select

0: CPU has higher priority
2

R/W

0x0

1: DVFS has higher priority

1

R/W

0x0

CPU Busy set

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0

R/W

0x0

DVFS Busy set

Note: This register is only implemented in TWI0.

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8.2. SPI
8.2.1. Overview
The Serial Peripheral Interface (SPI) allows rapid data communication with less software interrupts. The SPI
module contains one 8x64-bit receiver buffer (RXFIFO) and one 8x64-bit transmit buffer (TXFIFO). It can work in
two modes: Master mode and Slave mode.
Features:
●

Full-duplex synchronous serial interface

●

Configurable Master/Slave

●

8x64-bit FIFO for data transmit and 8x64-bit FIFO for data receive

●

Configurable polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK)

●

Supports Dedicated DMA

8.2.2. SPI Timing Diagram
The SPI master uses the SPI_SCLK signal to transfer data in and out of the shift register. Data is clocked using one
of four programmable clock phase and polarity combinations.
During Phase 0, Polarity 0 and Phase 1, Polarity 1 operations, output data changes on the falling clock edge and
input data is shifted in on the rising edge.
During Phase 1, Polarity 0 and Phase 0, Polarity 1 operations, output data changes on the rising edges of the
clock and is shifted in on the falling edges.
The POL defines the signal polarity when SPI_SCLK is in an idle state. The SPI_SCLK is high level when POL is ‘1’
and it is low level when POL is ‘0’. The PHA decides whether the leading edge of SPI_SCLK is used to setup or
sample data. The leading edge is used to setup data when PHA is ‘1’ and to sample data when PHA is ‘0’. The
four modes are listed below:
SPI Mode
0
1
2
3

POL
0
0
1
1

PHA
0
1
0
1

GR8 User Manual(Version1.0)

Leading Edge
Rising, Sample
Rising, Setup
Falling, Sample
Failing, Setup

Trailing Edge
Falling, Setup
Falling, Sample
Rising, Setup
Rising, Sample

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SPI_SCLK (Mode 0)
SPI_SCLK (Mode 2)
SPI_MOSI
SPI_MISO
SPI_SS
Sample MOSI/ MISO pin

Phase 0

Figure 8-2. SPI Phase 0 Timing Diagram

SPI_SCLK (Mode 1)
SPI_SCLK (Mode 3)
SPI_MOSI
SPI_MISO
SPI_SS
Sample MOSI/ MISO pin

Phase 1

Figure 8-3. SPI Phase 1 Timing Diagram

8.2.3. Functional Descriptions
8.2.3.1. SPI Pin List
The direction of the SPI pin is different in two work modes: Master Mode and Slave Mode.
Port Name
SPI-CLK
SPI-MOSI
SPI-MISO
SPI-CS

Width
1
1
1
1

Direction(M)
OUT
OUT
IN
OUT

GR8 User Manual(Version1.0)

Direction(S)
IN
IN
OUT
IN

Description
SPI Clock
SPI Master Output Slave Input Data Signal
SPI Master Input Slave Output Data Signal
SPI Chip Select Signal

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8.2.3.2. SPI Module Clock Source and Frequency
The SPI module uses two clock sources: AHB_CLK and SPI_CLK. The SPI_SCLK can in the range from 3 kHz to 100
MHz and AHB_CLK>= 2x SPI_SCLK.
Clock Name
AHB_CLK
SPI_CLK

Description
AHB Bus Clock, as the clock source of SPI module
SPI Serial Input Clock

Requirement
AHB_CLK >= 2xSPI_SCLK

8.2.4. SPI Register List
Module Name
SPI0
SPI2

Base Address
0x01C05000
0x01C17000

Register Name
SPI_RXDATA
SPI_TXDATA
SPI_CTL
SPI_INTCTL
SPI_ST
SPI_DMACTL
SPI_WAIT
SPI_CCTL
SPI_BC
SPI_TC
SPI_FIFO_STA

Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028

Description
SPI RX Data Register
SPI TX Data Register
SPI Control Register
SPI Interrupt Control Register
SPI Status Register
SPI DMA Control Register
SPI Wait Clock Counter Register
SPI Clock Rate Control Register
SPI Burst Counter Register
SPI Transmit Counter Register
SPI FIFO Status Register

8.2.5. SPI Register Description
8.2.5.1. SPI RX Data Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
Read/Write

Default/hex

Register Name: SPI_RXDATA
Description
Receive Data

31:0

R

0x0

In 8-bits SPI bus width, this register can be accessed in byte, half-word
or word unit by AHB. In byte accessing method, if there are words in
RXFIFO, the top word is returned and the RXFIFO depth is decreased by
1. In half-word accessing method, the two SPI bursts are returned and
the RXFIFO depth decreases by 2. In word accessing method, the four
SPI bursts are returned and the RXFIFO depth decreases by 4.

8.2.5.2. SPI TX Data Register(Default Value: 0x0000_0000)
Offset: 0x0004
GR8 User Manual(Version1.0)

Register Name: SPI_TXDAT
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Bit

Read/Write

Default/Hex

Description

31:0

W

0x0

Transmit Data

8.2.5.3. SPI Control Register(Default Value: 0x0002_001C)
Offset: 0x0008
Bit
31:20

19

Read/Write
/

R/W

Register Name: SPI_CTL
Default/Hex
/

0x0

Description
/
Master Sample Data Control
Set this bit to ‘1’ to make the internal read sample point with a delay of
half cycle of SPI_CLK. It is used in high speed read operation to reduce
the error caused by the time delay of SPI_CLK propagating between
master and slave.

1: Delay internal read sample point
0: Normal operation, do not delay internal read sample point
Transmit Pause Enable
In master mode, it is used to control transmit state machine to stop
smart burst sending when RX FIFO is full.
18

R/W

0x0
1: Stop transmit data when RXFIFO full
0: Normal operation, ignore RXFIFO status
SS_LEVEL
When control SS signal manually (SPI_CTRL_REG.SS_CTRL==1), set this
bit to ‘1’ or ‘0’ to control the level of SS signal.

17

R/W

0x1
1: Set SS to high
0: Set SS to low
SS_CTRL
SS Output Mode Select

16

R/W

0x0

Usually, the controller sends SS signal automatically with data together.
When this bit is set to 1, software must manually write
SPI_CTRL_REG.SS_LEVEL (bit [17]) to 1 or 0 to control the level of SS
signal.

1: Manual output SS
0: Automatic output SS
15

R/W

0x0

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DHB
Discard Hash Burst

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In master mode, it controls whether discarding unused SPI bursts.

0: Receiving all SPI bursts in BC period
1: Discard unused SPI bursts, only fetching the SPI bursts during dummy
burst period. The bursts number is specified by WTC.
DDB
Dummy Burst Type
14

R/W

0x0
0: The bit value of dummy SPI burst is zero
1: The bit value of dummy SPI burst is one
SS
SPI Chip Select
Select one of four external SPI Master/Slave Devices

13:12

R/W

0x0

00: SPI_SS0 will be asserted
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
RPSM
Rapids Mode Select

11

R/W

0x0

Select Rapids operation mode for high speed read.

0: Normal read mode
1: Rapids read mode
XCH
Exchange Burst
In master mode, it is used to start to SPI burst.
10

R/W

0x0
0: Idle
1: Initiates exchange. After finishing the SPI bursts transfer specified by
BC, this bit is cleared to zero by SPI Controller.
RXFIFO Reset

9

R/W

0x0

Write ‘1’ to reset the control portion of the receiver FIFO and treats the
FIFO as empty.
It is 'self-clearing'. It is not necessary to clear this bit.

8

R/W

0x0

TXFIFO Reset
Write ‘1’ to reset the control portion of the transmit FIFO and treats the

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FIFO as empty.
It is 'self-clearing'. It is not necessary to clear this bit.
SSCTL
In master mode, this bit selects the output wave form for the SPI_SSx
signal.
7

R/W

0x0
0: SPI_SSx remains asserted between SPI bursts
1: Negate SPI_SSx between SPI bursts
LMTF
LSB/ MSB Transfer First Select

6

R/W

0x0
0: MSB first
1: LSB first
DMAM
DMA Mode Control

5

R/W

0x0
0: Normal dma
1: Dedicate dma
SSPOL
SPI Chip Select Signal Polarity Control

4

R/W

0x1
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
POL
SPI Clock Polarity Control

3

R/W

0x1
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
PHA
SPI Clock/Data Phase Control

2

R/W

0x1
0: Phase 0 (Leading edge for sample data)
1: Phase 1 (Leading edge for setup data)
MODE

1

R/W

0x0

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0: Slave Mode
1: Master Mode
EN
SPI Module Enable Control
0

R/W

0x0
0: Disable
1: Enable

8.2.5.4. SPI Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x000C
Bit
Read/Write

Default/Hex

Register Name: SPI_INTCTL
Description

31:18

/

/

/

SSI Interrupt Enable
Chip Select Signal (SSx) from valid state to invalid state
17

R/W

0x0
0: Disable
1: Enable
Transfer Completed Interrupt Enable

16

R/W

0x0

0: Disable
1: Enable

15

/

/

/
TXFIFO underrun Interrupt Enable

14

R/W

0x0

0: Disable
1: Enable
TX FIFO Overflow Interrupt Enable

13

R/W

0x0

0: Disable
1: Enable
TX FIFO 3/4 Empty Interrupt Enable

12

R/W

0x0

0: Disable
1: Enable

11

R/W

0x0

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TX FIFO 1/4 Empty Interrupt Enable

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0: Disable
1: Enable
TX FIFO Full Interrupt Enable
10

R/W

0x0

0: Disable
1: Enable
TX FIFO Half Empty Interrupt Enable

9

R/W

0x0

0: Disable
1: Enable
TX FIFO Empty Interrupt Enable

8

R/W

0x0

0: Disable
1: Enable

7

/

/

/
RXFIFO underrun Interrupt Enable

6

R/W

0x0

0: Disable
1: Enable
RX FIFO Overflow Interrupt Enable

5

R/W

0x0

0: Disable
1: Enable
RXFIFO 3/4 Full Interrupt Enable

4

R/W

0x0

0: Disable
1: Enable
RX FIFO 1/4 Full Interrupt Enable

3

R/W

0x0

0: Disable
1: Enable
RX FIFO Full Interrupt Enable

2

R/W

0x0

0: Disable
1: Enable

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RX FIFO Half Full Interrupt Enable
1

R/W

0x0

0: Disable
1: Enable
RX FIFO Ready Interrupt Enable

0

R/W

0x0

0: Disable
1: Enable

8.2.5.5. SPI Interrupt Status Register(Default Value: 0x0000_1B00)
Offset: 0x0010

Register Name: SPI_INT_STA

Bit

Read/Write

Default/Hex

31

R

0x0

Description
Clear interrupt busy flag

0: clearing interrupt is done
1: clearing interrupt is busy

30:24

/

/

/

23:20

/

/

/

19:18

/

/

/
SSI

17

R/W

0x0

SS Invalid Interrupt
When SSI is 1, it indicates that SS has changed from valid state to invalid
state. Writing 1 to this bit clears it.
TC
Transfer Completed

16

R/W

0x0

In master mode, it indicates that all bursts specified by BC have been
exchanged. In other condition, when set, this bit indicates that all the
data in TXFIFO has been loaded in the Shift register, and the Shift
register has shifted out all the bits. Writing 1 to this bit clears it.

0: Busy
1: Transfer Completed
15

/

/

/
TU

14

R/W

0x0

TXFIFO underrun
This bit is set when if the TXFIFO is underrun. Writing 1 to this bit clears

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it.

0: TXFIFO is not underrun
1: TXFIFO is underrun
TO
TXFIFO Overflow
13

R/W

0x0

This bit is set when the TXFIFO overflows. Writing 1 to this bit clears it.

0: TXFIFO is not overflowed
1: TXFIFO is overflowed
TXFIFO 3/4 empty
12

R/W

0x1

This bit is set if the TXFIFO is more than 3/4 empty. Writing 1 to this bit
clears it.
TXFIFO 1/4 empty

11

R/W

0x1

This bit is set if the TXFIFO is more than 1/4 empty. Writing 1 to this bit
clears it.
TF
TXFIFO Full

10

R/W

0x0

This bit is set when the TXFIFO is full. Writing 1 to this bit clears it.

0: TXFIFO is not Full
1: TXFIFO is Full
THE
TXFIFO Half empty
9

R/W

0x1

This bit is set if the TXFIFO is more than half empty. Writing 1 to this bit
clears it.

0: TXFIFO holds more than half words
1: TXFIFO holds half or fewer words
TE
TXFIFO Empty
8

R/W

0x1

This bit is set if the TXFIFO is empty. Writing 1 to this bit clears it.

0: TXFIFO contains one or more words.
1: TXFIFO is empty
7

/

/

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RU
6

R/W

0x0

RXFIFO Underrun
When set, this bit indicates that RXFIFO has underrun. Writing 1 to this
bit clears it.
RO
RXFIFO Overflow

5

R/W

0x0

When set, this bit indicates that RXFIFO has overflowed. Writing 1 to
this bit clears it.

0: RXFIFO is available.
1: RXFIFO has overflowed.
RXFIFO 3/4 Full
This bit is set when the RXFIFO is 3/4 full. Writing 1 to this bit clears it.
4

R/W

0x0
0: Not 3/4 Full
1: 3/4 Full
RXFIFO 1/4 Full
This bit is set when the RXFIFO is 1/4 full. Writing 1 to this bit clears it.

3

R/W

0x0
0: Not 1/4 Full
1: 1/4 Full
RF
RXFIFO Full

2

R/W

0x0

This bit is set when the RXFIFO is full. Writing 1 to this bit clears it.

0: Not Full
1: Full
RHF
RXFIFO Half Full. This bit is set if the RXFIFO is half full (≥ 4 words in
RXFIFO) . Writing 1 to this bit clears it.
1

R/W

0x0
0: Less than 4 words are stored in RXFIFO.
1: Four or more words are available in RXFIFO.
RR

0

R/W

0x0

RXFIFO Ready
This bit is set any time there is one or more words stored in RXFIFO (≥

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1 words). Writing 1 to this bit clears it.

0: No valid data in RXFIFO
1: More than 1 word in RXFIFO

8.2.5.6. SPI DMA Control Register(Default Value: 0x0000_0000)
Offset: 0x0014
Bit
31:13

Read/Write
/

Register Name: SPI_DMACTL
Default/Hex
/

Description
/
TXFIFO3/4 Empty DMA Request Enable

12

R/W

0x0

0: Disable
1: Enable
TXFIFO 1/4 Empty DMA Request Enable

11

R/W

0x0

0: Disable
1: Enable
TXFIFO Not Full DMA Request Enable
When enabled, if more than one free room for burst, DMA request is
asserted, otherwise, it’s de-asserted.

10

R/W

0x0
0: Disable
1: Enable
TXFIFO Half Empty DMA Request Enable

9

R/W

0x0

0: Disable
1: Enable
TXFIFO Empty DMA Request Enable

8

R/W

0x0

0: Disable
1: Enable

7:5

/

/

/
RXFIFO 3/4 Full DMA Request Enable

4

R/W

0x0

GR8 User Manual(Version1.0)

This bit enables/disables the RXFIFO 3/4 Full DMA Request.

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0: Disable
1: Enable
RXFIFO 1/4 Full DMA Request Enable
This bit enables/disables the RXFIFO 1/4 Full DMA Request.
3

R/W

0x0
0: Disable
1: Enable
RXFIFO Full DMA Request Enable
This bit enables/disables the RXFIFO Half Full DMA Request.

2

R/W

0x0
0: Disable
1: Enable
RXFIFO Half Full DMA Request Enable
This bit enables/disables the RXFIFO Half Full DMA Request.

1

R/W

0x0
0: Disable
1: Enable
RXFIFO Ready Request Enable
This bit enables/disables the RXFIFO Ready DMA Request when one or
more than one words in RXFIFO.

0

R/W

0x0
0: Disable
1: Enable

8.2.5.7. SPI Wait Clock Register(Default Value: 0x0000_0000)
Offset: 0x0018
Bit
31:16

Read/Write
/

Register Name: SPI_WAIT
Default/Hex
/

Description
/
WCC
Wait Clock Counter (In Master mode)

15:0

R/W

0x0

These bits control the number of wait states to be inserted in data
transfers. The SPI module counts SPI_SCLK by WCC for delaying next
word data transfer.

0: No wait states inserted
N: N SPI_SCLK wait states inserted

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8.2.5.8. SPI Clock Control Register(Default Value: 0x0000_0002)
Offset: 0x001C
Bit
31:13

Read/Write
/

Register Name: SPI_CCTL
Default/Hex
/

Description
/
DRS

12

R/W

Divide Rate Select (Master Mode Only)

0x0

0: Select Clock Divide Rate 1
1: Select Clock Divide Rate 2
CDR1
Clock Divide Rate 1 (Master Mode Only)

11:8

R/W

This field selects the baud rate of the SPI_SCLK based on a division of
the AHB_CLK. These bits allow SPI to synchronize with different external
SPI devices. The max frequency is one quarter of AHB_CLK. The divide
ratio is determined according to the following table using the equation:
2^(n+1). The SPI_SCLK is determined according to the following
equation: SPI_CLK = AHB_CLK / 2^(n+1).

0x0

CDR2
7:0

R/W

Clock Divide Rate 2 (Master Mode Only)

0x2

The SPI_SCLK is determined according to the following equation:
SPI_CLK = AHB_CLK / (2*(n + 1)).

8.2.5.9. SPI Burst Counter Register(Default Value: 0x0000_0000)
Offset: 0x0020
Bit
31:24

Read/Write
/

Register Name: SPI_BC
Default/Hex
/

Description
/
BC
Burst Counter
In master mode, this field specifies the total burst number.

23:0

R/W

0x0

0: 0 burst
1: 1 burst
…
N: N bursts

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8.2.5.10. SPI Transmit Counter Register(Default Value: 0x0000_0000)
Offset: 0x0024
Bit
31:24

Read/Write
/

Register Name: SPI_TC
Default/Hex
/

Description
/
WTC
Write Transmit Counter

23:0

R/W

In master mode, this field specifies the burst number that should be
sent to TXFIFO before automatically sending dummy burst. For saving
bus bandwidth, the dummy burst (all zero bits or all one bits) is sent
by SPI Controller automatically.

0x0

0: 0 burst
1: 1 burst
…
N: N bursts

8.2.5.11. SPI FIFO Status Register(Default Value: 0x0000_0000)
Offset: 0x0028
Bit
31:25

Read/Write
/

Register Name: SPI_FIFO_STA
Default/Hex
/

Description
/
TXFIFO Counter
These bits indicate the number of words in TXFIFO

0: 0 byte in TXFIFO
22:16

R

0x0

1: 1 byte in TXFIFO
…
…
63: 63 bytes in TXFIFO
64: 64 bytes in TXFIFO

15:7

/

/

/
RXFIFO Counter
These bits indicate the number of words in RXFIFO

6:0

R

0x0

0: 0 byte in RXFIFO
1: 1 byte in RXFIFO
…

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…
63: 63 bytes in RXFIFO
64: 64 bytes in RXFIFO

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8.3. UART
8.3.1. Overview
The UART is used for serial communication with a peripheral, modem (data carrier equipment, DCE) or data set.
Data is written from a master (CPU) over the APB bus to the UART and it is converted to serial form and transmitted
to the destination device. Serial data is also received by the UART and stored for the master (CPU) to read back.
The UART contains registers to control the character length, baud rate, parity generation/checking, and interrupt
generation. Although there is only one interrupt output signal from the UART, there are several prioritized
interrupt types responsible for its assertion. Each of the interrupt types can be separately enabled/disabled with
the control registers.
The UART has 16450 and 16550 modes of operation, which are compatible with a range of standard software
drivers. In 16550 mode, transmit and receive operations are both buffered by FIFOs. In 16450 mode, these FIFOs
are disabled.
The UART supports word lengths from five to eight bits, an optional parity bit and 1, 1.5 or 2 stop bits, and is fully
programmable by an AMBA APB CPU interface. A 16-bit programmable baud rate generator and an 8-bit scratch
register are included, together with separate transmit and receive FIFOs. Eight modem control lines and a
diagnostic loop-back mode are provided.
Interrupts can be generated for a range of TX Buffer/FIFO, RX Buffer/FIFO, Modem Status and Line Status
conditions.
Features:
●

Compatible with industry-standard 16550 UARTs

●

64 bytes transmit and receive data FIFOs

●

DMA controller interface

●

Software/hardware flow control

●

Programmable transmit holding register empty interrupt

●

Interrupt support for FIFOs, Status Change

8.3.2. UART Timing Diagram
One Character
Bit Time
TX/RX

Serial Data

S

Data bits 5-8

P

S 1,1.5,2

Figure 8-4. UART Serial Data Format

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Data Bits
Bit Time
SIN/SOUT

S

Stop
3/16 Bit Time

3/16 Bit Time

SIR_OUT
3/16 Bit Time
SIR_IN

Figure 8-5. Serial IrDA Data Format

8.3.3. UART Special Requirement
When the UART is working in IrDA mode (MCR[6]=’1’), if HALT[4] is set to ‘1’, the signal is inverted before
transferring to SOUT, and if HALT[5] is set to ‘1’, the signal is inverted after receiving from pin SIN.

8.3.4. UART Register List
There are 3 UART controllers that can be configured as Serial IrDA.
Module Name
UART0
UART1
UART2
UART3

Base Address
0x01C28000
0x01C28400
0x01C28800
0x01C28C00

Register Name

Offset

Description

UART_RBR

0x0000

UART Receive Buffer Register

UART_THR

0x0000

UART Transmit Holding Register

UART_DLL

0x0000

UART Divisor Latch Low Register

UART_DLH

0x0004

UART Divisor Latch High Register

UART_IER

0x0004

UART Interrupt Enable Register

UART_IIR

0x0008

UART Interrupt Identity Register

UART_FCR

0x0008

UART FIFO Control Register

UART_LCR

0x000C

UART Line Control Register

UART_MCR

0x0010

UART Modem Control Register

UART_LSR

0x0014

UART Line Status Register

UART_MSR

0x0018

UART Modem Status Register

UART_SCH

0x001C

UART Scratch Register

UART_USR

0x007C

UART Status Register

UART_TFL

0x0080

UART Transmit FIFO Level

UART_RFL

0x0084

UART Receive FIFO Level

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UART_HALT

0x00A4

UART Halt TX Register

8.3.5. UART Register Description
8.3.5.1. UART Receiver Buffer Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
31:8

Read/Write
/

Register Name: UART_RBR
Default/Hex
/

Description
/
RBR
Receiver Buffer Register
Data byte received on the serial input port (sin) in UART mode, or the
serial infrared input (sir_in) in infrared mode. The data in this register is
valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set.

7:0

R

0x0
If in FIFO mode and FIFOs are enabled (FCR[0] set to one), this register
accesses the head of the receive FIFO. If the receive FIFO is full and this
register is not read before the next data character arrives, the data
already in the FIFO is preserved, but all incoming data are lost and an
overrun error occurs.

8.3.5.2. UART Transmit Holding Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
31:8

Read/Write
/

Register Name: UART_THR
Default/Hex
/

Description
/
THR
Transmit Holding Register

7:0

W

Data to be transmitted on the serial output port (sout) in UART mode or
the serial infrared output (sir_out_n) in infrared mode. Data should only
be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set.

0x0

If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, 16
number of characters of data may be written to the THR before the FIFO
is full. Any attempt to write data when the FIFO is full results the write
data lost.

8.3.5.3. UART Divisor Latch Low Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit

Read/Write

Register Name: UART_DLL
Default/Hex

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Description

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Interfaces
31:8

/

/

/
DLL
Divisor Latch Low
Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains
the baud rate divisor for the UART. This register may only be accessed
when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is
zero).

7:0

R/W

0x0

The output baud rate equals to the serial clock (sclk) frequency divided
by sixteen times the value of the baud rate divisor, as follows: baud rate
= (serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the
baud clock is disabled and no serial communications occur. Also, once the
DLL is set, at least 8 clock cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving data.

8.3.5.4. UART Divisor Latch High Register(Default Value: 0x0000_0000)
Offset: 0x0004
Bit
31:8

Read/Write
/

Register Name: UART_DLH
Default/Hex
/

Description
/
DLH
Divisor Latch High
Upper 8 bits of a 16-bit, read/write, Divisor Latch register that contains
the baud rate divisor for the UART. This register may only be accessed
when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is
zero).

7:0

R/W

0x0

The output baud rate equals to the serial clock (sclk) frequency divided
by sixteen times the value of the baud rate divisor, as follows: baud rate
= (serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the
baud clock is disabled and no serial communications occur. Also, once the
DLH is set, at least 8 clock cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving data.

8.3.5.5. UART Interrupt Enable Register(Default Value: 0x0000_0000)
Offset: 0x0004

Register Name: UART_IER

Bit
31:8

Read/Write
/

Default/Hex
/

7

R/W

0x0

GR8 User Manual(Version1.0)

Description
/
PTIME
Programmable THRE Interrupt Mode Enable

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Interfaces
This is used to enable/disable the generation of THRE Interrupt.

0: Disable
1: Enable
6:4

/

/

/
EDSSI
Enable Modem Status Interrupt

3

R/W

0x0

This is used to enable/disable the generation of Modem Status Interrupt.
This is the fourth highest priority interrupt.

0: Disable
1: Enable
ELSI
Enable Receiver Line Status Interrupt
2

R/W

0x0

This is used to enable/disable the generation of Receiver Line Status
Interrupt. This is the highest priority interrupt.

0: Disable
1: Enable
ETBEI
Enable Transmit Holding Register Empty Interrupt
1

R/W

0x0

This is used to enable/disable the generation of Transmitter Holding
Register Empty Interrupt. This is the third highest priority interrupt.

0: Disable
1: Enable
ERBFI
Enable Received Data Available Interrupt

0

R/W

0x0

This is used to enable/disable the generation of Received Data Available
Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs
enabled). These are the second highest priority interrupts.

0: Disable
1: Enable

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8.3.5.6. UART Interrupt Identity Register(Default Value: 0x0000_0000)
Offset: 0x0008
Bit
31:8

Read/Write
/

Register Name: UART_IIR
Default/Hex
/

Description
/
FEFLAG
FIFOs Enable Flag

7:6

R

This is used to indicate whether the FIFOs are enabled or disabled.

0x0

00: Disable
11: Enable
5:4

/

/

/
IID
Interrupt ID
This indicates the highest priority pending interrupt which can be one of
the following types

0000: modem status
0001: no interrupt pending
3:0

R

0x1

0010: THR empty
0100: received data available
0110: receiver line status
0111: busy detect
1100: character timeout

Bit 3 indicates an interrupt can only occur when the FIFOs are enabled
and used to distinguish a Character Timeout condition interrupt.

Interrupt
ID
0001
0110

Priority
Level
Highest

Interrupt Type

Interrupt Source

None
Receiver Line
Status

None
Overrun/parity/ framing errors
or break interrupt

0100

Second

Received Data
Available

Receiver data available (nonFIFO mode or FIFOs disabled) or
RCVR FIFO trigger level reached
(FIFO mode and FIFOs enabled)

1100

Second

Character
Timeout

No characters in or out of the
RCVR FIFO during the last 4

GR8 User Manual(Version1.0)

Interrupt Reset
Reading the line status register
Reading the receiver buffer
register (non-FIFO mode or
FIFOs disabled) or the FIFO
drops below the trigger level
(FIFO mode and FIFOs enabled)
Reading the receiver buffer
register

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Indication

0010

Third

0000

0111

character times and there is at
least 1character in it during this
time

Transmit Holding
Register Empty

Fourth

Modem Status

Fifth

Busy
Detect
Indication

Transmitter holding register
empty (Program THRE Mode
disabled) or XMIT FIFO at or
below threshold (Program THRE
Mode enabled)
Clear to send or data set ready
or ring indicator or data carrier
detect. Note that if auto flow
control mode is enabled, a
change in CTS (that is, DCTS set)
does not cause an interrupt.
UART_16550_COMPATIBLE =
NO and master has tried to
write to the Line Control
Register while the UART is busy
(USR[0] is set to one).

Reading the IIR register (if
source of interrupt); or, writing
into THR (FIFOs or THRE Mode
not selected or disabled) or
XMIT FIFO above threshold
(FIFOs and THRE Mode selected
and enabled).

Reading the Modem status
Register

Reading the UART status
register

8.3.5.7. UART FIFO Control Register(Default Value: 0x0000_0000)
Offset: 0x0008
Bit
31:8

Read/Write
/

Register Name: UART_FCR
Default/Hex
/

Description
/
RT
RCVR Trigger

7:6

W

0x0

This is used to select the trigger level in the receiver FIFO at which the
Received Data Available Interrupt is generated. In auto flow control
mode, it is used to determine when the rts_n signal is de-asserted. It also
determines when the dma_rx_req_n signal is asserted in certain modes
of operation.

00: 1 character in the FIFO
01: FIFO ¼ full
10: FIFO ½ full
11: FIFO-2 less than full
TFT
TX Empty Trigger
5:4

W

0x0

GR8 User Manual(Version1.0)

Writes have no effect when THRE_MODE_USER = Disabled. This is used
to select the empty threshold level at which the THRE Interrupts are
generated when the mode is active. It also determines when the
dma_tx_req_n signal is asserted when in certain modes of operation.

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00: FIFO empty
01: 2 characters in the FIFO
10: FIFO ¼ full
11: FIFO ½ full
DMAM
DMA Mode
3

W

0x0
0: Mode 0
1: Mode 1
XFIFOR
XMIT FIFO Reset

2

W

0x0

This resets the control portion of the transmit FIFO and treats the FIFO as
empty. This also de-asserts the DMA TX request.
It is 'self-clearing'. It is not necessary to clear this bit.
RFIFOR
RCVR FIFO Reset

1

W

0x0

This resets the control portion of the receive FIFO and treats the FIFO as
empty. This also de-asserts the DMA RX request.
It is 'self-clearing'. It is not necessary to clear this bit.
FIFOE
Enable FIFOs

0

W

0x0

This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs.
Whenever the value of this bit is changed both the XMIT and RCVR
controller portion of FIFOs is reset.

8.3.5.8. UART Line Control Register(Default Value: 0x0000_0000)
Offset: 0x000C
Bit
31:8

Read/Write
/

Register Name: UART_LCR
Default/Hex
/

Description
/
DLAB
Divisor Latch Access Bit

7

R/W

0x0

GR8 User Manual(Version1.0)

It is writeable only when UART is not busy (USR[0] is zero) and always
readable. This bit is used to enable reading and writing of the Divisor
Latch register (DLL and DLH) to set the baud rate of the UART. This bit
must be cleared after initial baud rate setup in order to access other
registers.

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0: Select RX Buffer Register (RBR) / TX Holding Register(THR) and
Interrupt Enable Register (IER)
1: Select Divisor Latch LS Register (DLL) and Divisor Latch MS Register
(DLM)
BC
Break Control Bit

6

R/W

0x0

5

/

/

This is used to cause a break condition to be transmitted to the receiving
device. If set to one, the serial output is forced to the spacing (logic 0)
state. When not in Loopback Mode, as determined by MCR[4], the sout
line is forced low until the Break bit is cleared. If SIR_MODE = Enabled
and active (MCR[6] set to one) the sir_out_n line is continuously pulsed.
When in Loopback Mode, the break condition is internally looped back to
the receiver and the sir_out_n line is forced low.
/
EPS
Even Parity Select

4

R/W

0x0

It is writeable only when UART is not busy (USR[0] is zero) and always
writable readable. This is used to select between even and odd parity,
when parity is enabled (PEN set to one).

0: Odd Parity
1: Even Parity
PEN
Parity Enable

3

R/W

0x0

It is writeable only when UART is not busy (USR[0] is zero) and always
readable. This bit is used to enable and disable parity generation and
detection in transmitted and received serial character respectively.

0: parity disabled
1: parity enabled
STOP
Number of stop bits

2

R/W

0x0

GR8 User Manual(Version1.0)

It is writeable only when UART is not busy (USR[0] is zero) and always
readable. This is used to select the number of stop bits per character that
the peripheral transmits and receives. If set to zero, one stop bit is
transmitted in the serial data. If set to one and the data bits are set to 5
(LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise,
two stop bits are transmitted. Note that regardless of the number of stop
bits selected, the receiver checks only the first stop bit.

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0: 1 stop bit
1: 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
DLS
Data Length Select

1:0

R/W

It is writeable only when UART is not busy (USR[0] is zero) and always
readable. This is used to select the number of data bits per character that
the peripheral transmits and receives. The number of bit that may be
selected areas follows.

0x0

00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits

8.3.5.9. UART Modem Control Register(Default Value: 0x0000_0000)
Offset: 0x0010
Bit
31:7

Read/Write
/

Register Name: UART_MCR
Default/Hex
/

Description
/
SIRE
SIR Mode Enable

6

R/W

0x0
0: IrDA SIR Mode disabled
1: IrDA SIR Mode enabled
AFCE
Auto Flow Control Enable

5

R/W

0x0

When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is
set, Auto Flow Control features are enabled.

0: Auto Flow Control Mode disabled
1: Auto Flow Control Mode enabled
LOOP
Loop Back Mode
4

R/W

0x0

0: Normal Mode
1: Loop Back Mode

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Interfaces
This is used to put the UART into a diagnostic mode for test purposes. If
operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set
to zero), data on the sout line is held high, while serial data output is
looped back to the sin line, internally. In this mode, all the interrupts are
fully functional. Also, in loopback mode, the modem control inputs
(dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control
outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs,
internally. If operating in infrared mode (SIR_MODE == Enabled AND
active, MCR[6] set to one), data on the sir_out_n line is held low, while
serial data output is inverted and looped back to the sir_in line.
3

/

/

/

2

/

/

/
RTS
Request to Send
This is used to directly control the Request to Send (rts_n) output. The
Request to Send (rts_n) output is used to inform the modem or data set
that the UART is ready to exchange data. When Auto RTS Flow Control is
not enabled (MCR[5] set to zero), the rts_n signal is set low by
programming MCR[1] (RTS) to high. In Auto Flow Control, AFCE_MODE
== Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set
to one), the rts_n output is controlled in the same

1

R/W

0x0

way, but is also gated with the receiver FIFO threshold trigger (rts_n is
inactive high when above the threshold). The rts_n signal is de-asserted
when MCR[1] is set low.

0: rts_n de-asserted (logic 1)
1: rts_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the rts_n output is held
inactive high while the value of this location is internally looped back to
an input.
DTR
Data Terminal Ready
This is used to directly control the Data Terminal Ready (dtr_n) output.
The value written to this location is inverted and driven out on dtr_n.
0

R/W

0x0

0: dtr_n de-asserted (logic 1)
1: dtr_n asserted (logic 0)

The Data Terminal Ready output is used to inform the modem or data set
that the UART is ready to establish communications.
Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held

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Interfaces
inactive high while the value of this location is internally looped back to
an input.

8.3.5.10. UART Line Status Register(Default Value: 0x0000_0060)
Offset: 0x0014
Bit
31:8

Read/Write
/

Register Name: UART_LSR
Default/Hex
/

Description
/
FIFOERR
RX Data Error in FIFO

7

R

0x0

When FIFOs are disabled, this bit is always 0. When FIFOs are enabled,
this bit is set to 1 when there is at least one PE, FE, or BI in the RX FIFO. It
is cleared by a read from the LSR register provided there are no
subsequent errors in the FIFO.
TEMT
Transmitter Empty

6

R

0x1

If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding
Register and the TX Shift Register are empty. If the FIFOs are enabled, this
bit is set whenever the TX FIFO and the TX Shift Register are empty. In
both cases, this bit is cleared when a byte is written to the TX data
channel.
THRE
TX Holding Register Empty

5

R

0x1

If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding
Register is empty and ready to accept new data and it is cleared when the
CPU writes to the TX Holding Register.
If the FIFOs are enabled, this bit is set to "1" whenever the TX FIFO is
empty and it is cleared when at least one byte is written to the TX FIFO.
BI
Break Interrupt
This is used to indicate the detection of a break sequence on the serial
input data.

4

R

0x0

If in UART mode (SIR_MODE == Disabled), it is set whenever the serial
input, sin, is held in a logic '0' state for longer than the sum of start time
+ data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial
input, sir_in, is continuously pulsed to logic '0' for longer than the sum of
start time + data bits + parity + stop bits. A break condition on serial input
causes one and only one character, consisting of all zeros, to be received
by the UART.
In the FIFO mode, the character associated with the break condition is
carried through the FIFO and is revealed when the character is at the top

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Interfaces
of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the
BI indication occurs immediately and persists until the LSR is read.
FE
Framing Error
This is used to indicate the occurrence of a framing error in the receiver.
A framing error occurs when the receiver does not detect a valid STOP bit
in the received data.

3

R

0x0

In the FIFO mode, since the framing error is associated with a character
received, it is revealed when the character with the framing error is at
the top of the FIFO. When a framing error occurs, the UART tries to
resynchronize. It does this by assuming the error occurs due to the start
bit of the next character and then continues receiving the other bit i.e.
data, and/or parity and stop. It should be noted that the Framing Error
(FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by
Break Interrupt (BI) bit (LSR[4]).

0: no framing error
1:framing error

Reading the LSR clears the FE bit.
PE
Parity Error

2

R

0x0

This is used to indicate the occurrence of a parity error in the receiver if
the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the
parity error is associated with a character received, it is revealed when
the character with the parity error arrives at the top of the FIFO. It should
be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt
has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).

0: no parity error
1: parity error

Reading the LSR clears the PE bit.
OE
Overrun Error

1

R

0x0

GR8 User Manual(Version1.0)

This occurs if a new data character is received before the previous data is
read. In the non-FIFO mode, the OE bit is set when a new character
arrives in the receiver before the previous character is read from the RBR.
When this happens, the data in the RBR is overwritten. In the FIFO mode,
an overrun error occurs when the FIFO is full and a new character arrives
at the receiver. The data in the FIFO is retained and the data in the receive
shift register is lost.

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0: no overrun error
1: overrun error

Reading the LSR clears the OE bit.
DR
Data Ready
This is used to indicate that the receiver contains at least one character
in the RBR or the receiver FIFO.
0

R

0x0

0: no data ready
1: data ready

This bit is cleared when the RBR is read in non-FIFO mode, or when the
receiver FIFO is empty in FIFO mode.

8.3.5.11. UART Modem Status Register(Default Value: 0x0000_0000)
Offset: 0x0018
Bit
31:8

Read/Write
/

Register Name: UART_MSR
Default/Hex
/

Description
/
DCD
Line State of Data Carrier Detect

7

R

0x0

This is used to indicate the current state of the modem control line
dcd_n. This bit is the complement of dcd_n. When the Data Carrier
Detect input (dcd_n) is asserted it is an indication that the carrier has
been detected by the modem or data set.

0: dcd_n input is de-asserted (logic 1)
1: dcd_n input is asserted (logic 0)
RI
Line State of Ring Indicator

6

R

0x0

This is used to indicate the current state of the modem control line ri_n.
This bit is the complement of ri_n. When the Ring Indicator input (ri_n)
is asserted it is an indication that a telephone ringing signal has been
received by the modem or data set.

0: ri_n input is de-asserted (logic 1)

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1: ri_n input is asserted (logic 0)
DSR
Line State of Data Set Ready

5

R

0x0

This is used to indicate the current state of the modem control line dsr_n.
This bit is the complement of dsr_n. When the Data Set Ready input
(dsr_n) is asserted it is an indication that the modem or data set is ready
to establish communications with UART.

0: dsr_n input is de-asserted (logic 1)
1: dsr_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR).
CTS
Line State of Clear to Send

4

R

0x0

This is used to indicate the current state of the modem control line cts_n.
This bit is the complement of cts_n. When the Clear to Send input (cts_n)
is asserted, it is an indication that the modem or data set is ready to
exchange data with UART.

0: cts_n input is de-asserted (logic 1)
1: cts_n input is asserted (logic 0)

In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS).
DDCD
Delta Data Carrier Detect
This is used to indicate that the modem control line dcd_n has changed
since the last time the MSR was read.

3

R

0x0

0: no change on dcd_n since last read of MSR
1: change on dcd_n since last read of MSR

Reading the MSR clears the DDCD bit.
Note: If the DDCD bit is not set and the dcd_n signal is asserted (low) and
a reset occurs (software or otherwise), then the DDCD bit is set when
the reset is removed if the dcd_n signal remains asserted.
TERI
2

R

0x0

Trailing Edge Ring Indicator
This is used to indicate that a change on the input ri_n (from an activelow to an inactive-high state) has occurred since the last time the MSR is

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read.

0: no change on ri_n since last read of MSR
1: change on ri_n since last read of MSR

Reading the MSR clears the TERI bit.
DDSR
Delta Data Set Ready
This is used to indicate that the modem control line dsr_n has changed
since the last time the MSR was read.

0: no change on dsr_n since last read of MSR
1

R

0x0

1: change on dsr_n since last read of MSR

Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1),
DDSR reflects changes on MCR[0] (DTR).
Note: If the DDSR bit is not set and the dsr_n signal is asserted (low) and
a reset occurs (software or otherwise), the DDSR bit is set when the reset
is removed if the dsr_n signal remains asserted.
DCTS
Delta Clear to Send
This is used to indicate that the modem control line cts_n has changed
since the last time the MSR was read.

0: no change on ctsdsr_n since last read of MSR
0

R

0x0

1: change on ctsdsr_n since last read of MSR

Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1),
DCTS reflects changes on MCR[1] (RTS).
Note: If the DCTS bit is not set and the cts_n signal is asserted (low) and
a reset occurs (software or otherwise), the DCTS bit is set when the reset
is removed if the cts_n signal remains asserted.

8.3.5.12. UART Scratch Register(Default Value: 0x0000_0000)
Offset: 0x001C
Bit
31:8

Read/Write
/

Register Name: UART_SCH
Default/Hex
/

GR8 User Manual(Version1.0)

Description
/

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Interfaces
Scratch Register
7:0

R/W

0x0

This register is used by programmers as a temporary storage space. It has
no defined purpose in the UART.

8.3.5.13. UART Status Register(Default Value: 0x0000_0006)
Offset: 0x007C
Bit
31:5

Read/Write
/

Register Name: UART_USR
Default/Hex
/

Description
/
RFF
Receive FIFO Full
This is used to indicate that the receive FIFO is completely full.

4

R

0x0

0: Receive FIFO not full
1: Receive FIFO Full

This bit is cleared when the RX FIFO is no longer full.
RFNE
Receive FIFO Not Empty
This is used to indicate that the receive FIFO contains one or more
entries.
3

R

0x0
0: Receive FIFO is empty
1: Receive FIFO is not empty

This bit is cleared when the RX FIFO is empty.
TFE
Transmit FIFO Empty
This is used to indicate that the transmit FIFO is completely empty.
2

R

0x1

0: Transmit FIFO is not empty
1: Transmit FIFO is empty

This bit is cleared when the TX FIFO is no longer empty.
1

R

0x1

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TFNF
Transmit FIFO Not Full

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This is used to indicate that the transmit FIFO is not full.

0: Transmit FIFO is full
1: Transmit FIFO is not full

This bit is cleared when the TX FIFO is full.
BUSY
UART Busy Bit
0

R

0x0
0: Idle or inactive
1: Busy

8.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x0000_0000)
Offset: 0x0080

Register Name: UART_TFL

Bit
31:7

Read/Write
/

Default/Hex
/

6:0

R

0x0

Description
/
Transmit FIFO Level
This indicates the number of data entries in the transmit FIFO.

8.3.5.15. UART Receive FIFO Level Register(Default Value: 0x0000_0000)
Offset: 0x0084
Bit
31:7

Read/Write
/

Register Name: UART_RFL
Default/Hex
/

Description
/
Receive FIFO Level

6:0

R

0x0

This indicates the number of data entries in the receive FIFO.

8.3.5.16. UART Halt TX Register(Default Value: 0x0000_0000)
Offset: 0x00A4
Bit
31:6

Read/Write
/

Register Name: UART_HALT
Default/Hex
/

Description
/
SIR Receiver Pulse Polarity Invert

5

R/W

0x0

0: Not invert receiver signal
1: Invert receiver signal

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SIR Transmit Pulse Polarity Invert
4

R/W

0x0

0: Not invert transmit pulse
1: Invert transmit pulse

3:1

/

/

/
Halt TX
This register is use to halt transmissions for testing, so that the transmit
FIFO can be filled by the master when FIFOs are implemented and
enabled.

0

R/W

0x0

0 : Halt TX disabled
1 : Halt TX enabled

Note: If FIFOs are not enabled, the setting of the halt TX register has no
effect on operation.

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Interfaces

8.4. CIR
8.4.1. Overview
The CIR (Consumer IR) interface is used for remote control through infra-red light.
The CIR receiver is implemented in hardware to save CPU resources. It samples the input signals on the
programmable frequency and records these samples into RX FIFO when one CIR signal is found on the air. The CIR
receiver uses Run-Length Code (RLC) to encode pulse width, and the encoded data is buffered in 64 levels and 8bit width RX FIFO: the MSB bit is used to record the polarity of the receiving CIR signal (The high level is represented
as 1 and the low level is represented as 0), and the rest of the 7 bits are used for the length of the RLC. The
maximum length is 128. If the duration of one level (high or low) is more than 128, another byte is used. Since
there are always some noises in the air, a threshold can be set to filter the noises to reduce system loading and
improve system stability.
Features:
●

Full physical layer implementation

●

Support CIR for remote control or wireless keyboard

●

64x8 bits FIFO for data transfer

●

Programmable FIFO thresholds

●

Supports Interrupt and DMA

8.4.2. CIR Register List
Module Name
CIR

Base Address
0x01C21800

Register Name
CIR_CTL
CIR_RXCTL
CIR_RXFIFO
CIR_RXINT
CIR_RXSTA
CIR_CONFIG

Offset
0x0000
0x0010
0x0020
0x002C
0x0030
0x0034

Description
CIR Control Register
CIR Receiver Configure Register
CIR Receiver FIFO Register
CIR Receiver Interrupt Control Register
CIR Receiver Status Register
CIR Configure Register

8.4.3. CIR Register Description
8.4.3.1. CIR Control Register(Default Value: 0x0000_0000)
Offset: 0x0000
Bit
31:9

Read/Write
/

Register Name: CIR_CTL
Default/Hex
/

GR8 User Manual(Version1.0)

Description
/

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Interfaces
CGPO
General Program Output (GPO) Control in CIR mode for TX Pin
8

R/W

0x0
0: Low level
1: High level

7:6

/

/

/
CIR ENABLE

5:4

R/W

0x0

00~10: /
11: CIR mode enable

3:2

/

/

/
RXEN
Receiver Block Enable

1

R/W

0x0
0: Disable
1: Enable
GEN
Global Enable

0

R/W

A disable on this bit overrides any other block or channel enables and
flushes all FIFOs.

0x0

0: Disable
1: Enable

8.4.3.2. CIR Receiver Configure Register(Default Value: 0x0000_0004)
Offset: 0x0010
Bit
31:3

Read/Write
/

Register Name: IR_RXCTL
Default/Hex
/

Description
/
RPPI
Receiver Pulse Polarity Invert

2

R/W

0x1
0: Not invert receiver signal
1: Invert receiver signal

1:0

/

/

GR8 User Manual(Version1.0)

/

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Interfaces
8.4.3.3. CIR Receiver FIFO Register(Default Value: 0x0000_0000)
Offset: 0x0020

Register Name: IR_RXFIFO

Bit
31:8

Read/Write
/

Default/Hex
/

Description
/

7:0

R

0x0

Receiver Byte FIFO

8.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x0000_0000)
Offset: 0x002C
Bit
Read/Write

Default/Hex

Register Name: IR_RXINT
Description

31:12

/

/

/

RAL
11:6

R/W

0x0

RX FIFO Available Received Byte Level for interrupt and DMA request
TRIGGER_LEVEL = RAL + 1
DRQ_EN
RX FIFO DMA Enable

5

R/W

0x0

0: Disable
1: Enable

When set to ‘1’, the Receiver FIFO DRQ is asserted if reaching RAL. The
DRQ is de-asserted when condition fails.
RAI_EN
RX FIFO Available Interrupt Enable

4

R/W

0x0

0: Disable
1: Enable

When set to ‘1’, the Receiver FIFO IRQ is asserted if reaching RAL. The IRQ
is de-asserted when condition fails.
3:2

/

/

/
RPEI_EN
Receiver Packet End Interrupt Enable

1

R/W

0x0
0: Disable
1: Enable

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ROI_EN
Receiver FIFO Overrun Interrupt Enable
0

R/W

0x0
0: Disable
1: Enable

8.4.3.5. CIR Receiver Status Register(Default Value: 0x0000_0000)
Offset: 0x0030
Bit
31:13

Read/Write
/

Register Name: IR_RXSTA
Default/Hex
/

Description
/
RAC
RX FIFO Available Counter

12:6

R

0x0

0000000: No available data in RX FIFO
0000001: 1 byte available data in RX FIFO
0000010: 2 byte available data in RX FIFO
…
1000000: 64 byte available data in RX FIFO

5

/

/

/
RA
RX FIFO Available

4

R/W

0x0

0: RX FIFO not available according its level
1: RX FIFO available according its level

This bit is cleared by writing a ‘1’.
3:2

/

/

/
RPE
Receiver Packet End Flag

1

R/W

0x0

0: STO was not detected. In CIR mode, one CIR symbol is receiving or not
detected.
1: STO field or packet abort symbol (7’b0000,000 and 8’b0000,0000 for
MIR and FIR) is detected. In CIR mode, one CIR symbol is received.

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This bit is cleared by writing a ‘1’.
ROI
Receiver FIFO Overrun

0

R/W

0x0

0: Receiver FIFO not overrun
1: Receiver FIFO overrun

This bit is cleared by writing a ‘1’.

8.4.3.6. CIR Configure Register(Default Value: 0x0000_1828)
Offset: 0x0034
Bit
31:16

Read/Write
/

Register Name: IR_CIR
Default/Hex
/

Description
/
ITHR
Idle Threshold for CIR

15:8

R/W

0x18

The Receiver uses it to decide whether the CIR command has been
received. If there is no CIR signal on the air, the receiver is staying in IDLE
status. One active pulse will bring the receiver from IDLE status to
Receiving status. After the CIR is end, the inputting signal will keep the
specified level (high or low level) for a long time. The receiver can use this
idle signal duration to decide that it has received the CIR command. The
corresponding flag is asserted. If the corresponding interrupt is enabled,
the interrupt line is asserted to CPU.
When the duration of signal keeps one status (high or low level) for the
specified duration ((ITHR + 1)*128 sample_clk), this means that the
previous CIR command has been finished.
NTHR
Noise Threshold for CIR
When the duration of signal pulse (high or low level) is less than NTHR,
the pulse is taken as noise and should be discarded by hardware.

0: all samples are recorded into RX FIFO
7:2

R/W

0xa

1: If the signal is only one sample duration, it is taken as noise and
discarded.
2: If the signal is less than (<=) two sample duration, it is taken as noise
and discarded.
…
61: if the signal is less than (<=) sixty-one sample duration, it is taken as
noise and discarded.

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SCS
Sample Clock Select for CIR

1:0

R/W

0

00: CIR sample_clk is ir_clk/64
01: CIR sample_clk is ir_clk/128
10: CIR sample_clk is ir_clk/256
11: CIR sample_clk is ir_clk/512

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8.5. USB OTG
8.5.1. Overview
The USB OTG controller supports host and device functions. It can also be configured as a Host-only or Device-only
controller, full compliant with the USB 2.0 Specification. The USB2.0 OTG can support high-speed (HS, 480 Mbit/s),
full-speed (FS, 12 Mbit/s), and low-speed (LS, 1.5 Mbit/s) transfers in Host mode and support high-speed (HS, 480
Mbit/s) and full-speed (FS, 12 Mbit/s) in Device mode.
Features:
●

64-byte Endpoint 0 for Control Transfer

●

Supports up to 10 User-Configurable Endpoints for Bulk, Isochronous, Control and Interrupt bi-directional
transfers

●

Supports High-Bandwidth Isochronous & Interrupt transfers

●

Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral mode

8.5.2. USB OTG Timing Diagram
Please refer to USB2.0 Specification.

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8.6. USB Host
8.6.1. Overview
The USB Host Controller is fully compliant with the following specifications: USB 2.0 Enhanced Host Controller
Interface (EHCI) 1.0, and the Open Host Controller Interface (OHCI) 1.0a release. The controller supports highspeed, 480 Mbit/s transfers (40 times faster than USB 1.1 full-speed mode) using an EHCI Host Controller, as well
as full and low speeds through one or more integrated OHCI Host Controllers.
Features:
●

An internal DMA controller for data transfer with memory.

●

Complies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0, and the Open Host
Controller Interface (OHCI) Specification, Version 1.0a.

●

Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s), and Low-Speed (LS, 1.5 Mbit/s) Device.

●

Supports only one USB Root Port shared between EHCI and OHCI

8.6.2. USB Host Block Diagram
The system-level block diagram of USB host controller is shown below.

USB HCI

Port Control

System AHB BUS

EHCI

AHB
Slave

UTMI/FS

USB
PHY

USB Port

AHB
Master

OHCI

DRAM
Memory
Figure 8-6. USB Host Block Diagram

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8.6.3. USB Host Timing Diagram
Please refer to USB2.0 Enhanced Host Controller Interface (EHCI) Specification 1.0, and the Open Host Controller
Interface (OHCI) Specification 1.0a.

8.6.4. USB Host Special Requirement
Name
HCLK
CLK60M
CLK48M

Description
System clock (provided by AHB bus clock). This clock needs to be >30 MHz.
Clock from PHY for HS SIE, is constant to be 60 MHz.
Clock from PLL for FS/LS SIE, is constant to be 48 MHz.

8.6.5. USB Host Register List
Module Name
USB_HCI

Base Address
0x01C14000

Register Name
Offset
Description
EHCI Capability Register
E_CAPLENGTH
0x000
EHCI Capability Register Length
E_HCIVERSION
0x002
EHCI Host Interface Version Number Register
E_HCSPARAMS
0x004
EHCI Host Control Structural Parameter Register
E_HCCPARAMS
0x008
EHCI Host Control Capability Parameter Register
E_HCSPPORTROUTE
0x00c
EHCI Companion Port Route Description
EHCI Operational Register
E_USBCMD
0x010
EHCI USB Command Register
E_USBSTS
0x014
EHCI USB Status Register
E_USBINTR
0x018
EHCI USB Interrupt Enable Register
E_FRINDEX
0x01C
EHCI USB Frame Index Register
E_CTRLDSSEGMENT
0x020
EHCI 4G Segment Selector Register
E_PERIODICLISTBASE
0x024
EHCI Frame List Base Address Register
E_ASYNCLISTADDR
0x028
EHCI Next Asynchronous List Address Register
E_CONFIGFLAG
0x050
EHCI Configured Flag Register
E_PORTSC
0x054
EHCI Port Status/Control Register
OHCI Control and Status Partition Register
O_HcRevision
0x400
OHCI Revision Register
O_HcControl
0x404
OHCI Control Register
O_HcCommandStatus
0x408
OHCI Command Status Register
O_HcInterruptStatus
0x40C
OHCI Interrupt Status Register
O_HcInterruptEnable
0x410
OHCI Interrupt Enable Register
O_HcInterruptDisable
0x414
OHCI Interrupt Disable Register
OHCI Memory Pointer Partition Register
O_HcHCCA
0x418
OHCI HCCA Base
O_HcPeriodCurrentED
0x41c
OHCI Period Current ED Base
O_HcControlHeadED
0x420
OHCI Control Head ED Base
O_HcControlCurrentED
0x424
OHCI Control Current ED Base
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O_HcBulkHeadED
0x428
O_HcBulkCurrentED
0x42C
O_HcDoneHead
0x430
OHCI Frame Counter Partition Register
O_HcFmInterval
0x434
O_HcFmRemaining
0x438
O_HcFmNumber
0x43C
O_HcPerioddicStart
0x440
O_HcLSThreshold
0x444
OHCI Root Hub Partition Register
O_HcRhDescriptorA
0x448
O_HcRhDesriptorB
0x44C
O_HcRhStatus
0x450
O_HcRhPortStatus
0x454

OHCI Bulk Head ED Base
OHCI Bulk Current ED Base
OHCI Done Head Base
OHCI Frame Interval Register
OHCI Frame Remaining Register
OHCI Frame Number Register
OHCI Periodic Start Register
OHCI LS Threshold Register
OHCI Root Hub Descriptor Register A
OHCI Root Hub Descriptor Register B
OHCI Root Hub Status Register
OHCI Root Hub Port Status Register

8.6.6. EHCI Register Description
8.6.6.1. EHCI Identification Register(Default Value: Implementation Dependent)
Offset:0x00

Register Name: CAPLENGTH

Bit

Read/Write

Default/Hex

Description
CAPLENGTH

7:0

R

0x10

The value in these bits indicates an offset to add to register base to find
the beginning of the Operational Register Space.

8.6.6.2. EHCI Host Interface Version Number Register(Default Value:0x0000_0100)
Offset: 0x02

Register Name: HCIVERSION

Bit

Read/Write

Default/Hex

15:0

R

0x0100

Description
HCIVERSION
This is a 16-bits register containing a BCD encoding of the EHCI revision
number supported by this host controller. The most significant byte of this
register represents a major revision and the least significant byte is the
minor revision.

8.6.6.3. EHCI Host Control Structural Parameter Register(Default Value: Implementation Dependent)
Offset: 0x04

Register Name: HCSPARAMS

Bit

Read/Write

Default/Hex

31:24

/

0x0

23:20

R

0x0

Description
Reserved.
These bits are reserved and should be set to zero.
Debug Port Number
This register identifies which of the host controller ports is the debug

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port. The value is the port number (one based) of the debug port.
This field will always be ‘0’.
19:16

/

Reserved.

0x0

These bits are reserved and should be set to zero.
Number of Companion Controller (N_CC)

15:12

R

This field indicates the number of companion controllers associated with
this USB2.0 host controller. A zero in this field indicates there are no
companion host controllers. And a value larger than zero in this field
indicates there are companion USB1.1 host controller(s).

0x0

This field will always be ‘0’.
Number of Port per Companion Controller(N_PCC)
11:8

R

This field indicates the number of ports supported per companion host
controller host controller. It is used to indicate the port routing
configuration to system software.

0x0

This field will always fix with ‘0’.
Port Routing Rules
This field indicates the method used by this implementation for how all
ports are mapped to companion controllers. The value of this field has
the following interpretation:

7

R

Value

Meaning

0

The first N_PCC ports are routed to the lowest numbered
function companion host controller, the next N_PCC port
are routed to the next lowest function companion
controller, and so on.

1

The port routing is explicitly enumerated by the first
N_PORTS elements of the HCSP-PORTTOUTE array.

0x0

This field will always be ‘0’.
6:4

/

Reserved.

0x0

These bits are reserved and should be set to zero.
N_PORTS

3:0

R

This field specifies the number of physical downstream ports
implemented on this host controller. The value of this field determines
how many port registers are addressable in the Operational Register
Space. Valid values are in the range of 0x1 to 0x0f.

0x1

This field is always 1.

8.6.6.4. EHCI Host Control Capability Parameter Register(Default Value: Implementation Dependent)
Offset: 0x08
Bit

Read/Write

Register Name: HCCPARAMS
Default/Hex

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31:16

/

0x0

Reserved
These bits are reserved and should be set to zero.
EHCI Extended Capabilities Pointer (EECP)

15:18

R

0x0

This optional field indicates the existence of a capabilities list. A value of
00b indicates no extended capabilities are implemented. A non-zero
value in this register indicates the offset in PCI configuration space of the
first EHCI extended capability. The pointer value must be 40h or greater if
implemented to maintain to consistency of the PCI header defined for this
class of device.
The value of this field is always ‘00b’.
Isochronous Scheduling Threshold
This field indicates, relative to the current position of the executing host
controller, where software can reliably update the isochronous schedule.

7:4

R

UDF

3

R

0x0

When bit[7] is zero, the value of the least significant 3 bits indicates the
number of micro-frames a host controller can hold a set of isochronous
data structures(one or more) before flushing the state. When bit[7] is a
one, then host software assumes the host controller may cache an
isochronous data structure for an entire frame.
Reserved
These bits are reserved and should be set to zero.
Asynchronous Schedule Park Capability

2

R

UDF

If this bit is set to a one, then the host controller supports the park feature
for high-speed queue heads in the Asynchronous Schedule. The feature
can be disabled or enabled and set to a specific level by using the
Asynchronous Schedule Park Mode Enable and Asynchronous Schedule
Park Mode Count fields in the USBCMD register.
Programmable Frame List Flag
If this bit is set to a zero, then system software must use a frame list length
of 1024 elements with this host controller. The USBCMD register

1

R

UDF

Frame List Size field is a read-only register and should be set to zero.
If set to 1, then system software can specify and use the frame list in the
USBCMD register Frame List Size field to configure the host controller.
The frame list must always align on a 4K page boundary. This requirement
ensures that the frame list is always physically contiguous.
Reserved

0

R

0x0

These bits are reserved for future use and should return a value of zero
when read.

8.6.6.5. EHCI Companion Port Route Description
Offset: 0x0C

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Bit

Read/Write

Default/Hex

Description
HCSP-PORTROUTE
This optional field is valid only if Port Routing Rules field in HCSPARAMS
register is set to a one.

31:0

R

This field is used to allow a host controller implementation to explicitly
describe to which companion host controller each implemented port is
mapped. This field is a 15-element nibble array (each 4 bit is one array
element). Each array location corresponds one-to-one with a physical
port provided by the host controller (e.g. PORTROUTE [0] corresponds to
the first PORTSC port, PORTROUTE [1] to the second PORTSC port, etc.).
The value of each element indicates to which of the companion host
controllers this port is routed. Only the first N_PORTS elements have valid
information. A value of zero indicates that the port is routed to the lowest
numbered function companion host controller. A value of one indicates
that the port is routed to the next lowest numbered function companion
host controller, and so on.

UDF

8.6.6.6. EHCI USB Command Register(Default Value: 0x0008_0000)
The default value is 0x00080B00 if Asynchronous Schedule Park Capability is a one.
Offset: 0x10

Register Name: USBCMD

Bit

Read/Write

Default/Hex

31:24

/

0x0

Description
Reserved
These bits are reserved and should be set to zero.
Interrupt Threshold Control
The value in this field is used by system software to select the maximum
rate at which the host controller will issue interrupts. The only valid values
are defined below:

23:16

R/W

0x08

Value

Minimum Interrupt Interval

0x00

Reserved

0x01

1 micro-frame

0x02

2 micro-frame

0x04

4 micro-frame

0x08

8 micro-frame(default, equates to 1 ms)

0x10

16 micro-frame(2ms)

0x20

32 micro-frame(4ms)

0x40

64 micro-frame(8ms)

Any other value in this register yields undefined results.
The default value in this field is 0x08.
Software modifications to this bit while HC Halted bit equals to zero

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results in undefined behavior.
15:12

/

0x0

Reserved
These bits are reserved and should be set to zero.
Asynchronous Schedule Park Mode Enable(OPTIONAL)

11

R/W or R

0x0

10

/

0x0

If the Asynchronous Park Capability bit in the HCCPARAMS register is a
one, then this bit defaults to a 1 and is R/W. Otherwise the bit must be a
zero and is Read Only. Software uses this bit to enable or disable Park
mode. When this bit is one, Park mode is enabled. When this bit is zero,
Park mode is disabled.
Reserved
These bits are reserved and should be set to zero.
Asynchronous Schedule Park Mode Count(OPTIONAL)
Asynchronous Park Capability bit in the HCCPARAMS register is a one,

9:8

R/W or R

0x0

Then this field defaults to 0x3 and is W/R. Otherwise it defaults to zero
and is R. It contains a count of the number of successive transactions the
host controller is allowed to execute from a high-speed queue head on
the Asynchronous schedule before continuing traversal of the
Asynchronous schedule.
Valid values are 0x1 to 0x3.Software must not write a zero to this bit when
Park Mode Enable is a one as it will result in undefined behavior.
Light Host Controller Reset(OPTIONAL)
This control bit is not required.

7

R/W

0x0

If implemented, it allows the driver to reset the EHCI controller without
affecting the state of the ports or relationship to the companion host
controllers. For example, the PORSTC registers should not be reset to their
default values and the CF bit setting should not go to zero (retaining port
ownership relationships).
A host software read of this bit as zero indicates the Light Host Controller
Reset has completed and it is safe for software to re-initialize the host
controller. A host software read of this bit as a one indicates the Light Host
Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host controller to issue
an interrupt the next time it advances asynchronous schedule. SoftWare must write a 1 to this bit to ring the doorbell.

6

R/W

0x0

When the host controller has evicted all appropriate cached schedule
state, it sets the Interrupt on Async Advance status bit in the USBSTS. if
the Interrupt on Async Advance Enable bit in the USBINTR register is a one
then the host controller will assert an interrupt at the next interrupt
threshold.
The host controller sets this bit to a zero after it has set the Interrupt on
Async Advance status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronous

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schedule is disabled. Doing so will yield undefined results.
Asynchronous Schedule Enable
This bit controls whether the host controller skips processing the
Asynchronous Schedule. Values mean:
5

R/W

0x0

Bit Value

Meaning

0

Do not process the Asynchronous Schedule.

1

Use the ASYNLISTADDR
Asynchronous Schedule.

register

to

access

the

The default value of this field is ‘0b’.
Periodic Schedule Enable
This bit controls whether the host controller skips processing the Periodic
Schedule. Values mean:
4

R/W

0x0

Bit Value

Meaning

0

Do not process the Periodic Schedule.

1

Use the PERIODICLISTBASE register to access the Periodic
Schedule.

The default value of this field is ‘0b’.
Frame List Size
This field is R/W only if Programmable Frame List Flag in the HCCPARAMS
registers is set to a one. This field specifies the size of the
Frame list. The size the frame list controls which bits in the Frame Index
Register should be used for the Frame List Current index. Values mean:
3:2

R/W or R

0x0

Bits

Meaning

00b

1024 elements(4096bytes)Default value

01b

512 elements(2048byts)

10b

256 elements(1024bytes)For resource-constrained condition

11b

Reserved

The default value is ‘00b’.
Host Controller Reset
This control bit is used by software to reset the host controller. The effects
of this on Root Hub registers are similar to a Chip Hardware Reset.

1

R/W

0x0

When software writes a one to this bit, the Host Controller resets its
internal pipelines, timers, counters, state machines, etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports.
All operational registers, including port registers and port state machines
are set to their initial values. Port ownership reverts to the companion
host controller(s). Software must reinitialize the host controller as
described in Section 4.1 of the CHEI Specification in order to return the

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host controller to an operational state.
This bit is set to zero by the Host Controller when the reset process is
complete. Software cannot terminate the reset process early by writing a
zero to this register.
Software should not set this bit to a one when the HC Halted bit in the
USBSTS register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
Run/Stop
When set to a 1, the Host Controller proceeds with execution of the
schedule. When set to 0, the Host Controller completes the current and
any actively pipelined transactions on the USB and then halts. The Host
Controller must halt within 16 micro-frames after software clears this bit.
0

R/W

0x0

The HC Halted bit indicates when the Host Controller has finished its
pending pipelined transactions and has entered the stopped state.
Software must not write a one to this field unless the Host Controller is in
the Halt State.
The default value is 0x0.

8.6.6.7. EHCI USB Status Register(Default Value: 0x0000_1000)
Offset: 0x14

Register Name: USBSTS

Bit

Read/Write

Default/Hex

31:16

/

0x0

Description
Reserved
These bits are reserved and should be set to zero.
Asynchronous Schedule Status

15

R

0x0

The bit reports the current real status of Asynchronous Schedule. If this
bit is a zero, then the status of the Asynchronous Schedule is disabled. If
this bit is a one, then the status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (1) or disabled (0).
Periodic Schedule Status

14

R

0x0

13

R

0x0

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The bit reports the current real status of the Periodic Schedule. If this bit
is a zero, then the status of the Periodic Schedule is disabled. If this bit is
a one, then the status of the Periodic Schedule is enabled. The Host
Controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit in
the USBCMD register. When this bit and the Periodic Schedule Enable bit
are the same value, the Periodic Schedule is either enabled (1) or disabled
(0).
Reclamation

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This is a read-only status bit, which is used to detect an empty
asynchronous schedule.
HC Halted

12

R

0x1

This bit is a zero whenever the Run/Stop bit is a one. The Host Controller
Sets this bit to one after it has stopped executing as a result of the
Run/Stop bit being set to 0, either by software or by the Host Controller
Hardware (e.g. internal error).
The default value is ‘1’.

11:6

/

0x0

Reserved
These bits are reserved and should be set to zero.
Interrupt on Async Advance

5

R/WC

0x0

System software can force the host controller to issue an interrupt the
next time the host controller advances the asynchronous schedule by
writing a one to the Interrupt on Async Advance Doorbell bit in the
USBCMD register. This status bit indicates the assertion of that interrupt
source.
Host System Error

4

R/WC

0x0

The Host Controller set this bit to 1 when a serious error occurs during a
host system access involving the Host Controller module. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command
register to prevent further execution of the scheduled TDs.
Frame List Rollover

3

R/WC

0x0

The Host Controller sets this bit to a one when the Frame List Index rolls
over from its maximum value to zero. The exact value at which the
rollover occurs depends on the frame list size. For example, if the frame
list size is 1024, the Frame Index Register rolls over every time FRINDEX
[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to
a one every time FRINDEX [12] toggles.
Port Change Detect

2

R/WC

0x0

The Host Controller sets this bit to a one when any port for which the Port
Owner bit is set to zero has a change bit transition from a zero to a one or
a Force Port Resume bit transition from a zero to a one as a result of a JK transition detected on a suspended port. This bit will also be set as a
result of the Connect Status Chang being set to a one after system
software has relinquished ownership of a connected port by writing a one
to a port’s Port Owner bit.
USB Error Interrupt(USBERRINT)

1

R/WC

0x0

The Host Controller sets this bit to 1 when completion of USB transaction
results in an error condition (e.g. error counter underflow). If the TD on
which the error interrupt occurred also had its IOC bit set, both.
This bit and USBINT bit are set.

0

R/WC

0x0

USB Interrupt(USBINT)
The Host Controller sets this bit to a one on the completion of a USB

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transaction, which results in the retirement of a Transfer Descriptor that
had its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is detected
(actual number of bytes received was less than the expected number of
bytes)

8.6.6.8. EHCI USB Interrupt Enable Register(Default Value: 0x0000_0000)
Offset: 0x18

Register Name: USBINTR

Bit

Read/Write

Default/Hex

31:6

/

0x0

Description
Reserved
These bits are reserved and should be zero.
Interrupt on Async Advance Enable

5

R/W

0x0

When this bit is 1, and the Interrupt on Async Advance bit in the USBSTS
register is 1, the host controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software clearing the
Interrupt on Async Advance bit.
Host System Error Enable

4

R/W

0x0

When this bit is 1, and the Host System Error Status bit in the USBSTS
register is 1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Host System Error bit.
Frame List Rollover Enable

3

R/W

0x0

When this bit is 1, and the Frame List Rollover bit in the USBSTS register
is 1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Frame List Rollover bit.
Port Change Interrupt Enable

2

R/W

0x0

When this bit is 1, and the Port Chang Detect bit in the USBSTS register is
1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Port Chang Detect bit.
USB Error Interrupt Enable

1

R/W

0x0

When this bit is 1, and the USBERRINT bit in the USBSTS register is 1, the
host controller will issue an interrupt at the next interrupt threshold.
The interrupt is acknowledged by software clearing the USBERRINT bit.
USB Interrupt Enable

0

R/W

0x0

When this bit is 1, and the USBINT bit in the USBSTS register is 1, the host
controller will issue an interrupt at the next interrupt threshold.
The interrupt is acknowledged by software clearing the USBINT bit

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8.6.6.9. EHCI Frame Index Register(Default Value: 0x0000_0000)
Offset: 0x1C

Register Name: FRINDEX

Bit

Read/Write

Default/Hex

31:14

/

0x0

Description
Reserved
These bits are reserved and should be zero.
Frame Index
The value in this register increment at the end of each time frame
(e.g. micro-frame).Bits[N:3] are used for the Frame List current index. It
Means that each location of the frame list is accessed 8 times (frames or
Micro-frames) before moving to the next index. The following illustrates

13:0

R/W

Values of N based on the value of the Frame List Size field in the USBCMD
register.

0x0

USBCMD[Frame List Size]

Number Elements

N

00b

1024

12

01b

512

11

10b

256

10

11b

Reserved

Note: This register must be written as a DWord. Byte writes produce undefined results.

8.6.6.10. EHCI Periodic Frame List Base Address Register
Offset: 0x24
Bit

Read/Write

Register Name: PERIODICLISTBASE
Default/Hex

Description
Base Address
These bits correspond to memory address signals [31:12], respectively.
This register contains the beginning address of the Periodic Frame List in
the system memory.

31:12

R/W

System software loads this register prior to starting the schedule
execution by the Host Controller. The memory structure referenced by
this physical memory pointer is assumed to be 4-K byte aligned. The
contents of this register are combined with the Frame Index Register
(FRINDEX) to enable the Host Controller to step through the Periodic
Frame List in sequence.

UDF

Reserved
11:0

/

UDF

Must be written as 0x0 during runtime, the values of these bits are
undefined.

Note: Writes must be Dword Writes.

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8.6.6.11. EHCI Current Asynchronous List Address Register
Offset: 0x28

Register Name: ASYNCLISTADDR

Bit

Read/Write

Default/Hex

31:5

R/W

UDF

Description
Link Pointer (LP)
This field contains the address of the next asynchronous queue head to
be executed.
These bits correspond to memory address signals [31:5], respectively.
Reserved

4:0

/

These bits are reserved and their value has no effect on operation.

/

Bits in this field cannot be modified by system software and will always
return a zero when read.

Note: Write must be DWord Writes.

8.6.6.12. EHCI Configure Flag Register(Default Value: 0x0000_0000)
Offset: 0x50

Register Name: CONFIGFLAG

Bit

Read/Write

Default/Hex

31:1

/

0x0

Description
Reserved
These bits are reserved and should be set to zero.
Configure Flag(CF)
Host software sets this bit as the last action in its process of configuring
the Host Controller. This bit controls the default port-routing control logic
as follow:

0

R/W

0x0

Value

Meaning

0

Port routing control logic default-routs each port to an
implementation dependent classic host controller.

1

Port routing control logic default-routs all ports to this host
controller.

The default value of this field is ‘0’.
Note: This register is not used in the normal implementation.

8.6.6.13. EHCI Port Status and Control Register(Default Value: 0x00002000(w/PPC set to one))
The default value is 0x00003000 when w/PPC set to zero.
Offset: 0x54

Register Name: PORTSC

Bit

Read/Write

Default/Hex

31:22

/

0x0

Description
Reserved
These bits are reserved for future use and should return a value of zero

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when read.
Wake on Disconnect Enable(WKDSCNNT_E)
21

R/W

0x0

Writing this bit to a one enables the port to be sensitive to device
disconnects as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Wake on Connect Enable(WKCNNT_E)

20

R/W

0x0

Writing this bit to a one enable the port to be sensitive to device connects
as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Port Test Control
The value in this field specifies the test mode of the port. The encoding
of the test mode bits are as follow:

19:16

R/W

0x0

Bits

Test Mode

0000b

The port is NOT operating in a test mode.

0001b

Test J_STATE

0010b

Test K_STATE

0011b

Test SE0_NAK

0100b

Test Packet

0101b

Test FORCE_ENABLE

0110b1111b

Reserved

The default value in this field is ‘0000b’.
Reserved
15:14

R/W

0x0

These bits are reserved for future use and should return a value of zero
when read.
Port Owner
This bit unconditionally goes to a 0b when the Configured bit in the
CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally
goes to 1b whenever the Configured bit is zero.

13

R/W

0x1

System software uses this field to release ownership of the port to
selected host controller (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the attached
device is not a high-speed device. A one in this bit means that a
companion host controller owns and controls the port.
Default Value = 1b.

12

/

0x0

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Reserved

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These bits are reserved for future use and should return a value of zero
when read.
Line Status
These bits reflect the current logical levels of the D+ (bit11) and D-(bit10)
signal lines. These bits are used for detection of low-speed USB devices
prior to port reset and enable sequence. This read-only field is valid only
when the port enable bit is zero and the current connect status bit is set
to a one.
The encoding of the bits are:

11:10

R

0x0

Bit[11:10]

USB State

Interpretation

00b

SE0

Not Low-speed device, perform EHCI
reset.

10b

J-state

Not Low-speed device, perform EHCI
reset.

01b

K-state

Low-speed device, release ownership of
port.

11b

Undefined

Not Low-speed device, perform EHCI
reset.

This value of this field is undefined if Port Power is zero.
Reserved
9

/

0x0

This bit is reserved for future use, and should return a value of zero when
read.
Port Reset
1=Port is in Reset. 0=Port is not in Reset. Default value = 0.
When software writes a one to this bit (from a zero), the bus reset
sequence as defined in the USB Specification Revision 2.0 is started.
Software writes a zero to this bit to terminate the bus reset sequence.
Software must keep this bit at a one long enough to ensure the reset
sequence, as specified in the USB Specification Revision 2.0, completes.
Notes: when software writes this bit to a one, it must also write a zero to
the Port Enable bit.

8

R/W

0x0

Note that when software writes a zero to this bit there may be a delay
before the bit status changes to a zero. The bit status will not read as a
zero until after the reset has completed. If the port is in high-speed mode
after reset is complete, the host controller will automatically enable this
port (e.g. set the Port Enable bit to a one). A host controller must
terminate the reset and stabilize the state of the port within 2
milliseconds of software transitioning this bit from a one to a zero. For
example: if the port detects that the attached device is high-speed during
reset, then the host controller must have the port in the enabled state
with 2ms of software writing this bit to a zero.
The HC Halted bit in the USBSTS register should be a zero before software
attempts to use this bit. The host controller may hold Port Reset asserted
to a one when the HC Halted bit is a one.

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This field is zero if Port Power is zero.
Suspend
Port Enabled Bit and Suspend bit of this register define the port states as
follows:
Bits[Port Enables, Suspend]

7

R/W

0x0

Port State

0x

Disable

10

Enable

11

Suspend

When in suspend state, downstream propagation of data is blocked on
this port, except for port reset. The blocking occurs at the end of the
current transaction, if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume
detection. Not that the bit status does not change until the port is
suspend and that there may be a delay in suspending a port if there is a
transaction currently in progress on the USB.
A write of zero to this bit is ignored by the host controller. The host
controller will unconditionally set this bit to a zero when:
① Software sets the Force Port Resume bit to a zero(from a one).
② Software sets the Port Reset bit to a one(from a zero).
If host software sets this bit to a one when the port is not enabled (i.e.
Port enabled bit is a zero), the results are undefined.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Force Port Resume
1 = Resume detected/driven on port. 0 = No resume (K-state) detected/
driven on port. Default value = 0.
This functionality defined for manipulating this bit depends on the value
of the Suspend bit. For example, if the port is not suspended and software
transitions this bit to a one, then the effects on the bus are undefined.

6

R/W

0x0

Software sets this bit to a 1 drive resume signaling. The Host Controller
sets this bit to a 1 if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register
is also set to a one. If software sets this bit to a one, the host controller
must not set the Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification
Revision 2.0. The resume signal (Full-speed ‘K’) is driven on the port as
long as this remains a one. Software must appropriately time the Resume
and set this bit to a zero when the appropriate amount of time has
elapsed. Writing a zero (from one) causes the port to return high-speed
mode (forcing the bus below the port into a high-speed idle). This bit will
remain a one until the port has switched to high-speed idle. The host

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controller must complete this transition within 2 milliseconds of software
setting this bit to a zero.
This field is zero if Port Power is zero.
Over-current Change
5

R/WC

0x0

Default = 0. This bit gets set to a one when there is a change to Overcurrent Active. Software clears this bit by writing a one to this bit position.
Over-current Active

4

R

0x0

0 = This port does not have an over-current condition. 1 = This port
currently has an over-current condition. This bit will automatically
transition from a one to a zero when the over current condition is
removed.
The default value of this bit is ‘0’.
Port Enable/Disable Change
Default = 0. 1 = Port enabled/disabled status has changed. 0 = No change.

3

R/WC

0x0

For the root hub, this bit gets set to a one only when a port is disabled
due to the appropriate conditions existing at the EOF2 point (See Chapter
11 of the USB Specification for the definition of a Port Error). Software
clears this bit by writing a 1 to it.
This field is zero if Port Power is zero.
Port Enabled/Disabled
1=Enable, 0=Disable. Ports can only be enabled by the host controller as
a part of the reset and enable. Software cannot enable a port by writing
a one to this field. The host controller will only set this bit to a one when
the reset sequence determines that the attached device is a high-speed
device.

2

R/W

0x0

Ports can be disabled by either a fault condition (disconnect event or
other fault condition) or by host software. Note that the bit status does
not change until the port state changes. There may be a delay in disabling
or enabling a port due to other host controller and bus events.
When the port is disabled, downstream propagation of data is blocked on
this port except for reset.
The default value of this field is ‘0’.
This field is zero if Port Power is zero.
Connect Status Change
1=Change in Current Connect Status, 0=No change, Default=0.

1

R/WC

0x0

Indicates a change has occurred in the port’s Current Connect Status. The
host controller sets this bit for all changes to the port device connect
status, even if system software has not cleared an existing connect status
change. For example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be
“setting” an already-set bit. Software sets this bit to 0 by writing a 1 to it.
This field is zero if Port Power is zero.

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Current Connect Status

0

R

Device is present on port when the value of this field is a one, and no
device is present on port when the value of this field is a zero. This value
reflects the current state of the port, and may not correspond directly to
the event that caused the Connect Status Change (Bit 1) to be set.

0x0

This field is zero if Port Power zero.
Note: This register is only reset by hardware or in response to a host controller reset.

8.6.7. OHCI Register Description
8.6.7.1. HcRevision Register(Default Value: 0x0000_0010)
Offset: 0x400
Read/Write
Bit
31:8

HCD
/

HC
/

Register Name: HcRevision
Default/Hex
0x00

Description
Reserved
Revision

7:0

R

R

This read-only field contains the BCD representation of the version of
the HCI specification that is implemented by this HC. For example, a
value of 0x11 corresponds to version 1.1. All of the HC implementations
that are compliant with this specification will have a value of 0x10.

0x10

8.6.7.2. HcControl Register(Default Value: 0x0000_0000)
Register Name: HcRevision

Offset: 0x404
Read/Write
Bit
31:11

HCD
/

HC
/

Description
Default/Hex
0x00

Reserved
RemoteWakeupEnable

10

R/W

R

0x0

This bit is used by HCD to enable or disable the remote wakeup feature
upon the detection of upstream resume signaling. When this bit is set
and the ResumeDetected bit in HcInterruptStatus is set, a remote
wakeup is signaled to the host system. Setting this bit has no impact on
the generation of hardware interrupt.
RemoteWakeupConnected

9

R/W

R/W

0x0

8

R/W

R

0x0

GR8 User Manual(Version1.0)

This bit indicates whether HC supports remote wakeup signaling. If
remote wakeup is supported and used by the system, it is the
responsibility of system firmware to set this bit during POST. HC clear
the bit upon a hardware reset but does not alter it upon a software
reset. Remote wakeup signaling of the host system is host-bus-specific
and is not described in this specification.
InterruptRouting

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This bit determines the routing of interrupts generated by events
registered in HcInterruptStatus. If clear, all interrupts are routed to the
normal host bus interrupt mechanism. If set interrupts are routed to
the System Management Interrupt. HCD clears this bit upon a hardware
reset, but it does not alter this bit upon a software reset. HCD uses this
bit as a tag to indicate the ownership of HC.
HostControllerFunctionalState for USB

7:6

R/W

R/W

0x0

00b

USBReset

01b

USBResume

10b

USBOperational

11b

USBSuspend

A transition to USBOperational from another state causes SOF
generation to begin 1 ms later. HCD may determine whether HC has
begun sending SOFs by reading the StartoFrame field of
HcInterruptStatus.
This field may be changed by HC only when in the USBSUSPEND state.
HC may move from the USBSUSPEND state to the USBRESUME state
after detecting the resume signaling from a downstream port.
HC enters USBSUSPEND after a software reset, whereas it enters
USBRESET after a hardware reset. The latter also resets the Root
Hub and asserts subsequent reset signaling to downstream ports.
BulkListEnable
This bit is set to enable the processing of the Bulk list in the next

5

R/W

R

0x0

Frame. If cleared by HCD, processing of the Bulk list does not occur after
the next SOF. HC checks this bit whenever it determines to process the
list. When disabled, HCD may modify the list. If HcBulkCurrentED is
pointing to an ED to be removed, HCD must advance the pointer by
updating HcBulkCurrentED before re-enabling processing of the list.
ControlListEnable

4

R/W

R

0x0

This bit is set to enable the processing of the Control list in the next
Frame. If cleared by HCD, processing of the Control list does not occur
after the next SOF. HC must check this bit whenever it determines to
process the list. When disabled, HCD may modify the list. If
HcControlCurrentED is pointing to an ED to be removed, HCD must
advance the pointer by updating HcControlCurrentED before reenabling processing of the list.
IsochronousEnable

3

R/W

R

0x0

GR8 User Manual(Version1.0)

This bit is used by HCD to enable/disable processing of isochronous
EDs. While processing the periodic list in a Frame, HC checks the status
of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC
continues processing the EDs. If cleared (disabled), HC halts processing
of the periodic list (which now contains only isochronous EDs) and
begins processing the Bulk/Control lists.

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Setting this bit is guaranteed to take effect in the next Frame (not the
current Frame).
PeriodicListEnable
2

R/W

R

This bit is set to enable the processing of periodic list in the next Frame.
If cleared by HCD, processing of the periodic list does not occur after
the next SOF. HC must check this bit before it starts processing the list.

0x0

ControlBulkServiceRatio

1:0

R/W

R

This specifies the service ratio between Control and Bulk EDs. Before
processing any of the non-periodic lists, HC must compare the ratio
specified with its internal count on how many nonempty Control EDs
have been processed, in determining whether to continue serving
another Control ED or switching to Bulk EDs. The internal count will be
retained when crossing the frame boundary. In case of reset, HCD is
responsible for restoring this value.

0x0

CBSR

No. of Control EDs Over Bulk EDs Served

0

1:1

1

2:1

2

3:1

3

4:1

The default value is 0x0.

8.6.7.3. HcCommandStatus Register(Default Value: 0x0000_0000)
Offset: 0x408
Read/Write
Bit
31:18

HCD
/

HC
/

Register Name: HcCommandStatus
Default/Hex
0x0

Description
Reserved
SchedulingOverrunCount

17:16

R

R/W

0x0

15:4

/

/

0x0

These bits are incremented on each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. This will be incremented
when a scheduling overrun is detected even if SchedulingOverrun in
HcInterruptStatus has already been set. This is used by HCD to monitor
any persistent scheduling problem.
Reserved
OwershipChangeRequest

3

R/W

R/W

0x0

2

R/W

R/W

0x0

This bit is set by an OS HCD to request a change of control of the HC.
When set, HC will set the OwnershipChange field in HcInterruptStatus.
After the changeover, this bit is cleared and remains so until the next
request from OS HCD.
BulklListFilled
This bit is used to indicate whether there are any TDs on the Bulk list.

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It is set by HCD whenever it adds a TD to an ED in the Bulk list.
When HC begins to process the head of the Bulk list, it checks BLF. If
BulkListFilled is 0, HC will not start processing the Bulk list. If
BulkListFilled is 1, HC will start processing the Bulk list and will set BF to
0. If HC finds a TD on the list, then HC will set BulkListFilled to 1 causing
the Bulk list processing to continue. If no TD is found on the Bulk list,
and if HCD does not set BulkListFilled, then BulkListFilled will still be 0
when HC completes processing the Bulk list and Bulk list processing will
stop.
ControlListFilled
This bit is used to indicate whether there are any TDs on the Control
list. It is set by HCD whenever it adds a TD to an ED in the Control list.

1

R/W

R/W

When HC begins to process the head of the Control list, it checks CLF. If
ControlListFilled is 0, HC will not start processing the Control list. If CF
is 1, HC will start processing the Control list and will set ControlListFilled
to 0. If HC finds a TD on the list, then HC will set ControlListFilled to 1
causing the Control list processing to continue. If no TD is found on the
Control list, and if the HCD does not set ControlListFilled, then
ControlListFilled will still be 0 when HC completes processing the
Control list and Control list processing will stop.

0x0

HostControllerReset

0

R/W

R/E

This bit is by HCD to initiate a software reset of HC. Regardless of the
functional state of HC, it moves to the USBSuspend state in which most
of the operational registers are reset except those stated otherwise;
e.g, the InterruptRouting field of HcControl, and no Host bus accesses
are allowed. This bit is cleared by HC upon the completion of the reset
operation. The reset operation must be completed within 10 ms. This
bit,

0x0

when set, should not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream ports.

8.6.7.4. HcInterruptStatus Register(Default Value: 0x0000_0000)
Offset: 0x40C
Read/Write
Bit
31:7

HCD
/

HC
/

Register Name: HcInterruptStatus
Default/Hex
0x0

Description
Reserved
RootHubStatusChange

6

R/W

R/W

0x0

This bit is set when the content of HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
FrameNumberOverflow

5

R/W

R/W

0x0

GR8 User Manual(Version1.0)

This bit is set when the MSb of HcFmNumber (bit 15) changes value,
from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been
updated.

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UnrecoverableError
4

R/W

R/W

This bit is set when HC detects a system error not related to USB. HC
should not proceed with any processing nor signaling before the system
error has been corrected. HCD clears this bit after HC has been reset.

0x0

ResumeDetected
3

R/W

R/W

This bit is set when HC detects that a device on the USB is asserting
resume signaling. It is the transition from no resume signaling to
resume signaling causing this bit to be set. This bit is not set when HCD
sets the USBRseume state.

0x0

StartofFrame
2

R/W

R/W

0x0

This bit is set by HC at each start of frame and after the update of
HccaFrameNumber. HC also generates a SOF token at the same time.
WritebackDoneHead
This bit is set immediately after HC has written HcDoneHead to

1

R/W

R/W

0x0

HccaDoneHead. Further updates of the HccaDoneHead will not occur
until this bit has been cleared. HCD should only clear this bit after it has
saved the content of HccaDoneHead.
SchedulingOverrun

0

R/W

R/W

This bit is set when the USB schedule for the current Frame overruns
and after the update of HccaFrameNumber. A scheduling overrun will
also cause the SchedulingOverrunCount of HcCommandStatus to be

0x0

Incremented.

8.6.7.5. HcInterruptEnable Register(Default Value: 0x0000_0000)
Offset: 0x410
Read/Write

Register Name: HcInterruptEnable Register

Bit

HCD

HC

Default/Hex

Description
MasterInterruptEnable

31

R/W

R

0x0

A ‘0’ written to this field is ignored by HC. A ‘1’ written to this field
enables interrupt generation due to events specified in the other bits
of this register. This is used by HCD as Master Interrupt Enable.

30:7

/

/

0x0

Reserved
RootHubStatusChange Interrupt Enable

6

R/W

R

0x0

0

Ignore;

1

Enable interrupt generation due to Root Hub Status Change;

FrameNumberOverflow Interrupt Enable
5

R/W

R

0x0

GR8 User Manual(Version1.0)

0

Ignore;

1

Enable interrupt generation due to Frame Number Over Flow;

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UnrecoverableError Interrupt Enable
4

R/W

R

0x0

0

Ignore;

1

Enable interrupt generation due to Unrecoverable Error;

ResumeDetected Interrupt Enable
3

R/W

R

0x0

0

Ignore;

1

Enable interrupt generation due to Resume Detected;

StartofFrame Interrupt Enable
2

R/W

R

0x0

0

Ignore;

1

Enable interrupt generation due to Start of Frame;

WritebackDoneHead Interrupt Enable
1

R/W

R

0x0

0

Ignore;

1

Enable interrupt generation due to Write-back Done Head;

SchedulingOverrun Interrupt Enable
0

R/W

R

0x0

0

Ignore;

1

Enable interrupt generation due to Scheduling Overrun;

8.6.7.6. HcInterruptDisable Register(Default Value: 0x0000_0000)
Offset: 0x414
Read/Write

Register Name: HcInterruptDisable Register

Bit

HCD

HC

Default/Hex

Description
MasterInterruptEnable

31

R/W

R

0x0

A written ‘0’ to this field is ignored by HC. A ‘1’ written to this field
disables interrupt generation due events specified in the other bits of
this register. This field is set after a hardware or software reset.

30:7

/

/

0x0

Reserved
RootHubStatusChange Interrupt Disable

6

R/W

R

0x0

0

Ignore;

1

Disable interrupt generation due to Root Hub Status Change;

FrameNumberOverflow Interrupt Disable
5

R/W

R

0x0

0

Ignore;

1

Disable interrupt generation due to Frame Number Over Flow;

UnrecoverableError Interrupt Disable
4

R/W

R

0x0

GR8 User Manual(Version1.0)

0

Ignore;

1

Disable interrupt generation due to Unrecoverable Error;

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ResumeDetected Interrupt Disable
3

R/W

R

0x0

0

Ignore;

1

Disable interrupt generation due to Resume Detected;

StartofFrame Interrupt Disable
2

R/W

R

0x0

0

Ignore;

1

Disable interrupt generation due to Start of Flame;

WritebackDoneHead Interrupt Disable
1

R/W

R

0x0

0

Ignore;

1

Disable interrupt generation due to Write-back Done Head;

SchedulingOverrun Interrupt Disable
0

R/w

R

0x0

0

Ignore;

1

Disable interrupt generation due to Scheduling Overrun;

8.6.7.7. HcHCCA Register(Default Value: 0x0000_0000)
Offset: 0x418
Read/Write

Register Name: HcHCCA

Bit

HCD

HC

Default/Hex

31:8

R/W

R

0x0

Description
HCCA[31:8]
This is the base address of the Host Controller Communication Area.
This area is used to hold the control structures and the Interrupt table
that are accessed by both the Host Controller and the Host Controller
Driver.
HCCA[7:0]

7:0

R

R

The alignment restriction in HcHCCA register is evaluated by examining
the number of zeros in the lower order bits. The minimum alignment is
256 bytes, therefore, bits 0 through 7 must always return 0 when read.

0x0

8.6.7.8. HcPeriodCurrentED Register(Default Value: 0x0000_0000)
Offset: 0x41C
Read/Write
Bit

31:4

HCD

R

HC

R/W

Register Name: HcPeriodCurrentED(PCED)
Default/Hex

0x0

GR8 User Manual(Version1.0)

Description
PCED[31:4]
This is used by HC to point to the head of one of the periodic list which
will be processed in the current Frame. The content of this register is
updated by HC after a periodic ED has been processed. HCD may read
the content in determining which ED is currently being processed at the
time of reading.

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PCED[3:0]
3:0

R

R

Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So, the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

0x0

8.6.7.9. HcControlHeadED Register(Default Value: 0x0000_0000)
Offset: 0x420
Read/Write

Register Name: HcControlHeadED[CHED]

Bit

HCD

HC

Default/Hex

31:4

R/W

R

0x0

Description
EHCD[31:4]
The HcControlHeadED register contains the physical address of the first
Endpoint Descriptor of the Control list. HC traverse the Control list
starting with the HcControlHeadED pointer. The content is loaded from
HCCA during the initialization of HC.
EHCD[3:0]

3:0

R

R

Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So, the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

0x0

8.6.7.10. HcControlCurrentED Register(Default Value: 0x0000_0000)
Offset: 0x424
Read/Write
Bit

31:4

HCD

R/W

HC

R/W

Register Name: HcControlCurrentED[CCED]
Default/Hex

0x0

Description
CCED[31:4]
The pointer is advanced to the next ED after serving the present one.
HC will continue processing the list from where it left off in the last
Frame. When it reaches the end of the Control list, HC checks the
ControlListFilled of in HcCommandStatus. If set, it copies the content of
HcControlHeadED to HcControlCurrentED and clears the bit. If not set,
it does nothing.
HCD is allowed to modify this register only when the ControlListEnable
of HcControl is cleared. When set, HCD only reads the instantaneous
value of this register. Initially, this is set to zero to indicate the end of
the Control list.
CCED[3:0]

3:0

R

R

0x0

GR8 User Manual(Version1.0)

Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So, the lower bits in the
PCED, bit 0 to bit 3, must be zero in this field.

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8.6.7.11. HcBulkHeadED Register(Default Value: 0x0000_0000)
Offset: 0x428
Read/Write

Register Name: HcBulkHeadED[BHED]

Bit

HCD

HC

Default/Hex

31:4

R/W

R

0x0

Description
BHED[31:4]
The HcBulkHeadED register contains the physical address of the first
Endpoint Descriptor of the Bulk list. HC traverses the Bulk list starting
with the HcBulkHeadED pointer. The content is loaded from HCCA
during the initialization of HC.
BHED[3:0]

3:0

R

R

Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So, the lower bits in the
PCED, bit 0 to bit 3, must be zero in this field.

0x0

8.6.7.12. HcBulkCurrentED Register(Default Value: 0x0000_0000)
Offset: 0x42C
Read/Write
Bit

31:4

HCD

R/W

HC

R/W

Register Name: HcBulkCurrentED [BCED]
Default/Hex

Description
BulkCurrentED[31:4]
This is advanced to the next ED after the HC has served the present
one. HC continues processing the list from where it left off in the last
Frame. When it reaches the end of the Bulk list, HC checks the
ControlListFilled of HcControl. If set, it copies the content of
HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it
does nothing. HCD is only allowed to modify this register when the
BulkListEnable of HcControl is cleared. When set, the HCD only reads
the instantaneous value of this register. This is initially set to zero to
indicate the end of the Bulk list.

0x0

BulkCurrentED [3:0]
3:0

R

R

Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So, the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

0x0

8.6.7.13. HcDoneHead Register(Default Value: 0x0000_0000)
Offset: 0x430
Read/Write

Register Name: HcDoneHead

Bit

HCD

HC

Default/Hex

31:4

R

R/W

0x0

GR8 User Manual(Version1.0)

Description
HcDoneHead[31:4]
When a TD is completed, HC writes the content of HcDoneHead to the
NextTD field of the TD. HC then overwrites the content of HcDoneHead

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Interfaces
with the address of this TD. This is set to zero whenever HC writes the
content of this register to HCCA. It also sets the WritebackDoneHead of
HcInterruptStatus.
HcDoneHead[3:0]
3:0

R

R

Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So, the lower bits in the
PCED, bit 0 to bit 3, must be zero in this field.

0x0

8.6.7.14. HcFmInterval Register(Default Value: 0x0000_2EDF)
Offset: 0x434
Read/Write

Register Name: HcFmInterval Register

Bit

HCD

HC

Default/Hex

31

R/W

R

0x0

Description
FrameIntervalToggler
HCD toggles this bit whenever it loads a new value to FrameInterval.
FSLargestDataPacket

30:16

R/W

R

0x0

15:14

/

/

0x0

This field specifies a value which is loaded into the Largest Data Packet
Counter at the beginning of each frame. The counter value represents
the largest amount of data in bits which can be sent or received by the
HC in a single transaction at any given time without causing scheduling
overrun. The field value is calculated by the HCD.
Reserved
FrameInterval

13:0

R/W

R

This specifies the interval between two consecutive SOFs in bit times.
The nominal value is set to be 11,999. HCD should store the current
value of this field before resetting HC. By setting the
HostControllerReset field of HcCommandStatus as this will cause the
HC to reset this field to its nominal value. HCD may choose to restore
the stored value upon the completion of the Reset sequence.

0x2edf

8.6.7.15. HcFmRemaining Register(Default Value: 0x0000_0000)
Offset: 0x438
Read/Write

Register Name: HcFmRemaining

Bit

HCD

HC

Default/Hex

Description
FrameRemaining Toggle

31

R

R/W

0x0

This bit is loaded from the FrameIntervalToggle field of HcFmInterval
whenever FrameRemaining reaches 0. This bit is used by HCD for the
synchronization between FrameInterval and FrameRemaining.

30:14

/

/

0x0

Reserved

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Interfaces
FramRemaining
13:0

R

RW

This counter is decremented at each bit time. When it reaches zero, it
is reset by loading the FrameInterval value specified in HcFmInterval at
the next bit time boundary. When entering the USBOPERATIONAL
state, HC re-loads the content with the FrameInterval of HcFmInterval
and uses the updated value from the next SOF.

0x0

8.6.7.16. HcFmNumber Register(Default Value: 0x0000_0000)
Offset: 0x43c
Read/Write
Bit
31:16

HCD
/

HC
/

Register Name: HcFmNumber
Default/Hex
/

Description
Reserved
FrameNumber

15:0

R

R/W

This is incremented when HcFmRemaining is re-loaded. It will be rolled
over to 0x0 after 0x0ffff. When entering the USBOPERATIONAL state,
this will be incremented automatically. The content will be written to
HCCA after HC has incremented the FrameNumber at each frame
boundary and sent a SOF but before HC reads the first ED in that Frame.
After writing to HCCA, HC will set the StartofFrame in
HcInterruptStatus.

0x0

8.6.7.17. HcPeriodicStart Register(Default Value: 0x0000_0000)
Offset: 0x440
Read/Write
Bit
31:14

HCD
/

HC
/

Register Name: HcPeriodicStatus
Default/Hex
/

Description
Reserved
PeriodicStart

13:0

R/W

R

After hardware reset, this field is cleared. This is then set by HCD during
the HC initialization. The value is calculated roughly as 10% off from
HcFmInterval. A typical value will be 0x2A3F. When HcFmRemaining
reaches the value specified, processing of the periodic lists will have
priority over Control/Bulk processing. HC will therefore start processing
the Interrupt list after completing the current Control or Bulk
transaction that is in progress.

0x0

8.6.7.18. HcLSThreshold Register(Default Value: 0x0000_0628)
Offset: 0x444
Read/Write
Bit

HCD

HC

Register Name: HcLSThreshold
Default/Hex

GR8 User Manual(Version1.0)

Description

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Interfaces
31:12

/

/

/

Reserved
LSThreshold

11:0

R/W

R

0x0628

This field contains a value which is compared to the FrameRemaining
field prior to initiating a Low Speed transaction. The transaction is
started only if FrameRemaining ³ this field. The value is calculated by
HCD with the consideration of transmission and setup overhead.

8.6.7.19. HcRhDescriptorA Register(Default Value: 0x0200_1201)
Offset: 0x448
Read/Write

Register Name: HcRhDescriptorA

Bit

HCD

HC

Default/Hex

Description
PowerOnToPowerGoodTime[POTPGT]

31:24

R/W

R

0x2

This byte specifies the duration HCD must wait before accessing a
powered-on port of the Root Hub. It is implementation-specific. The
unit of time is 2 ms. The duration is calculated as POTPGT * 2ms.

23:13

Reserved
NoOverCurrentProtection

12

R/W

R

0x1

This bit describes how the overcurrent status for the Root Hub ports
are reported. When this bit is cleared, the OverCurrentProtectionMode
field specifies global or per-port reporting.
0

Over-current status is reported collectively for all downstream
ports.

1

No overcurrent protection supported.

OverCurrentProtectionMode

11

R/W

R

0x0

This bit describes how the overcurrent status for the Root Hub ports
are reported. At reset, these fields should reflect the same mode as
PowerSwitchingMode. This field is valid only if the
NoOverCurrentProtection field is cleared.
0

Over-current status is reported collectively for all downstream
ports.

1

Over-current status is reported on per-port basis.

Device Type
10

R

R

0x0

This bit specifies that the Root Hub is not a compound device. The Root
Hub is not permitted to be a compound device. This field should always
read/write 0.
PowerSwitchingMode

9

R/W

R

0x1

GR8 User Manual(Version1.0)

This bit is used to specify how the power switching of the Root Hub
ports is controlled. It is implementation-specific. This field is only valid
when the NoPowerSwitching field is cleared.

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Interfaces
0

All ports are powered at the same time.

1

Each port is powered individually. This mode allows port power
to be controlled by either the global switch or per-port
switch. If the PortPowerControlMask bit is set, the port
responds only to port power commands (Set/ClearPortPower).
If the port mask is cleared, then the port is controlled only by
the global power switch (Set/ClearGlobalPower).

NoPowerSwitching

8

R/W

R

These bits are used to specify whether power switching is supported or
ports are always powered. It is implementation-specific. When this bit
is cleared, the PowerSwitchingMode specifies global or per-port
switching.

0x0

0

Ports are power switched.

1

Ports are always powered on when the HC is powered on.

NumberDownstreamPorts
7:0

R

R

These bits specify the number of downstream ports supported by the
Root Hub. It is implementation-specific. The minimum number of ports
is 1.

0x1

8.6.7.20. HcRhDescriptorB Register(Default Value: 0x0000_0000)
Offset: 0x44C
Read/Write
Bit

31:16

HCD

R/W

HC

R

Register Name: HcRhDescriptorB Register
Default/Hex

0x0

Description
PortPowerControlMask
Each bit indicates if a port is affected by a global power control
command when PowerSwitchingMode is set. When set, the port's
power state is only affected by per-port power control
(Set/ClearPortPower). When cleared, the port is controlled by the
global power switch (Set/ClearGlobalPower). If the device is configured
to global switching mode (PowerSwitchingMode = 0), this field is not
valid.
Bit0

Reserved

Bit1

Ganged-power mask on Port #1.

Bit2

Ganged-power mask on Port #2.

…
Bit15

Ganged-power mask on Port #15.

DeviceRemovable
15:0

R/W

R

0x0

GR8 User Manual(Version1.0)

Each bit is dedicated to a port of the Root Hub. When cleared, the
attached device is removable. When set, the attached device is not
removable.

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Bit0

Reserved

Bit1

Device attached to Port #1.

Bit2

Device attached to Port #2.

…
Bit15

Device attached to Port #15.

8.6.7.21. HcRhStatus Register(Default Value: 0x0000_0000)
Offset: 0x450
Read/Write

Register Name: HcRhStatus Register

Bit

HCD

HC

Default/Hex

Description
(write)ClearRemoteWakeupEnable

31

W

R

0x0

Write a ‘1’ clears DeviceRemoteWakeupEnable. Writing a ‘0’ has no
effect.

30:18

/

/

0x0

Reserved
OverCurrentIndicatorChange

17

R/W

R

0x0

This bit is set by hardware when a change has occurred to the
OverCurrentIndicator field of this register. The HCD clears this bit by
writing a ‘1’. Writing a ‘0’ has no effect.
(read)LocalPowerStatusChange
The Root Hub does not support the local power status features, thus,
this bit is always read as ‘0’.

16

R/W

R

0x0

(write)SetGlobalPower
In global power mode (PowerSwitchingMode=0), this bit is written to
‘1’ to turn on power to all ports (clear PortPowerStatus). In per-port
power mode, it sets PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.
(read)DeviceRemoteWakeupEnable
This bit enables a ConnectStatusChange bit as a resume event, causing
a USBSUSPEND to USBRESUME state transition and setting the
ResumeDetected interrupt.

15

R/W

R

0x0

0

ConnectStatusChange is not a remote wakeup event.

1

ConnectStatusChange is a remote wakeup event.

(write)SetRemoteWakeupEnable
Writing a ‘1’ sets DeviceRemoveWakeupEnable. Writing a ‘0’ has no
effect.
14:2

/

/

0x0

Reserved

1

R

R/W

0x0

OverCurrentIndicator

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Interfaces
This bit reports overcurrent conditions when the global reporting is
implemented. When set, an overcurrent condition exists. When
cleared, all power operations are normal.
If per-port overcurrent protection is implemented this bit is always ‘0’
(Read)LocalPowerStatus
When read, this bit returns the LocalPowerStatus of the Root Hub. The
Root Hub does not support the local power status feature; thus, this bit
is always read as ‘0’.
0

R/W

R

(Write)ClearGlobalPower

0x0

When write, this bit is operated as the ClearGlobalPower. In global
power mode (PowerSwitchingMode=0), This bit is written to ‘1’ to turn
off power to all ports (clear PortPowerStatus). In per-port power mode,
it clears PortPowerStatus only on ports whose PortPowerControlMask
bit is not set. Writing a ‘0’ has no effect.

8.6.7.22. HcRhPortStatus Register(Default Value: 0x0000_0100)
Offset: 0x454
Read/Write
Bit
31:21

HCD
/

HC
/

Register Name: HcRhPortStatus
Default/Hex
0x0

Description
Reserved
PortResetStatusChange

20

R/W

R/W

0x0

This bit is set at the end of the 10-ms port reset signal. The HCD writes
a ‘1’ to clear this bit. Writing a ‘0’ has no effect.
0

port reset is not complete

1

port reset is complete

PortOverCurrentIndicatorChange
This bit is valid only if overcurrent conditions are reported on a per-port
basis. This bit is set when Root Hub changes the
19

R/W

R/W

0x0

PortOverCurrentIndicator bit. The HCD writes a ‘1’ to clear this bit.
Writing a ‘0’ has no effect.
0

no change in PortOverCurrentIndicator

1

PortOverCurrentIndicator has changed

PortSuspendStatusChange
This bit is set when the full resume sequence has been completed. This
sequence includes the 20-s resume pulse, LS EOP, and 3-ms
18

R/W

R/W

0x0

GR8 User Manual(Version1.0)

resynchronization delay. The HCD writes a ‘1’ to clear this bit. Writing a
‘0’ has no effect. This bit is also cleared when ResetStatusChange is set.
0

resume is not completed

1

resume completed

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PortEnableStatusChange

17

R/W

R/W

0x0

This bit is set when hardware events cause the PortEnableStatus bit to
be cleared. Changes from HCD writes do not set this bit. The HCD writes
a ‘1’ to clear this bit. Writing a ‘0’ has no effect.
0

no change in PortEnableStatus

1

change in PortEnableStatus

ConnectStatusChange
This bit is set whenever a connect or disconnect event occurs. The HCD
writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. If

16

R/W

R/W

0x0

CurrentConnectStatus is cleared when a SetPortReset, SetPortEnable,
or SetPortSuspend write occurs, this bit is set to force the driver to reevaluate the connection status since these writes should not occur if
the port is disconnected.
0

no change in PortEnableStatus

1

change in PortEnableStatus

Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a
Root Hub reset to inform the system that the device is attached.
15:10

/

/

0x0

Reserved
(read)LowSpeedDeviceAttached
This bit indicates the speed of the device attached to this port. When
set, a Low Speed device is attached to this port. When cleared, a Full
Speed device is attached to this port. This field is valid only when the
CurrentConnectStatus is set.

9

R/W

R/W

-

0

full speed device attached

1

low speed device attached

(write)ClearPortPower
The HCD clears the PortPowerStatus bit by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect.
(read)PortPowerStatus

8

R/W

R/W

0x1

This bit reflects the port’s power status, irrelevant of the type of power
switching implemented. This bit is cleared if an overcurrent condition
is detected. HCD sets this bit by writing SetPortPower or
SetGlobalPower. HCD clears this bit by writing ClearPortPower or
ClearGlobalPower. Which power control switches are enabled is
determined
by
PowerSwitchingMode
and
PortPortControlMask[NumberDownstreamPort]. In global switching
mode(PowerSwitchingMode=0), only Set/ClearGlobalPower controls
this bit. In per-port power switching (PowerSwitchingMode=1), if the
PortPowerControlMask[NDP] bit for the port is set, only

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Interfaces
Set/ClearPortPower commands are enabled. If the mask is not set, only
Set/ClearGlobalPower commands are enabled. When port power is
disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus,
and PortResetStatus should be reset.
0

port power is off

1

port power is on

(write)SetPortPower
The HCD writes a ‘1’ to set the PortPowerStatus bit. Writing a ‘0’ has no
effect.
Note: This bit is always read as ‘1b’ if power switching is not supported.
7:5

/

/

0x0

Reserved
(read)PortResetStatus
When this bit is set by writing to SetPortReset, port reset signaling is
asserted. When reset is completed, this bit is cleared when
PortResetStatusChange is set. This bit cannot be set if
CurrentConnectStatus is cleared.

4

R/W

R/W

0x0

0

port reset signal is not active

1

port reset signal is active

(write)SetPortReset
The HCD sets the port reset signaling by writing a ‘1’ to this bit. Writing
a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does
not set PortResetStatus, but instead sets ConnectStatusChange. This
informs the driver that it attempted to reset a disconnected port.
(read)PortOverCurrentIndicator
This bit is only valid when the Root Hub is configured in such a way that
overcurrent conditions are reported on a per-port basis. If per-port
overcurrent reporting is not supported, this bit is set to 0. If cleared, all
power operations are normal for this port. If set, an overcurrent
condition exists on this port. This bit always reflects the overcurrent
input signal.
3

R/W

R/W

0x0

0

no overcurrent condition.

1

overcurrent condition detected.

(write)ClearSuspendStatus
The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’ has no effect. A
resume is initiated only if PortSuspendStatus is set.
2

R/W

R/W

0x0

(read)PortSuspendStatus
This bit indicates the port is suspended or in the resume sequence. It is

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Interfaces
set by a SetSuspendState write and cleared when
PortSuspendStatusChange is set at the end of the resume interval. This
bit cannot be set if CurrentConnectStatus is cleared. This bit is also
cleared when PortResetStatusChange is set at the end of the port reset
or when the HC is placed in the USBRESUME state. If an upstream
resume is in progress, it should propagate to the HC.
0

port is not suspended

1

port is suspended

(write)SetPortSuspend
The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write
does not set PortSuspendStatus; instead it sets ConnectStatusChange.
This informs the driver that it attempted to suspend a disconnected
port.
(read)PortEnableStatus

1

R/W

R/W

0x0

This bit indicates whether the port is enabled or disabled. The Root Hub
may clear this bit when an overcurrent condition, disconnect event,
switched-off power, or operational bus error such as babble is
detected. This change also causes PortEnabledStatusChange to be set.
HCD sets this bit by writing SetPortEnable and clears it by writing
ClearPortEnable. This bit cannot be set when CurrentConnectStatus is
cleared. This bit is also set, if not already, at the completion of a port
reset when ResetStatusChange is set or port suspend when
SuspendStatusChange is set.
0

port is disabled

1

port is enabled

(write)SetPortEnable
The HCD sets PortEnableStatus by writing a ‘1’. Writing a ‘0’ has no
effect. If CurrentConnectStatus is cleared, this write does not set
PortEnableStatus, and sets ConnectStatusChange instead. This informs
the driver that it attempts to enable a disconnected Port.
(read)CurrentConnectStatus
This bit reflects the current state of the downstream port.

0

R/W

R/W

0x0

0

No device connected

1

Device connected

(write)ClearPortEnable
The HCD writes a ‘1’ to clear the PortEnableStatus bit. Writing ‘0’ has
no effect. The CurrentConnectStatus is not affected by any write.
Note: This bit is always read as ‘1’ when the attached device is nonremovable(DeviceRemoveable[NumberDownstreamPort]).

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Interfaces

GR8 User Manual(Version1.0)

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Chapter 9. Reference Design
This chapter shows C.H.I.P. Pro, a reference design using the GR8.SiP.
 CHIP Pro board
 Pinout Diagram
 Block Diagram
 Schematic

GR8 User Manual(Version1.0)

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Reference Design

9.1. C.H.I.P. Pro Board
The following image is of the CHIP Pro single board computer.

Figure 9-1: C.H.I.P. Pro

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Reference Design

9.2. Pinout Diagram
The Following pin map demonstrates some of the common alternate pin mux configurations, overlaid on C.HIP Pro.

Figure 9-2: Pinout Diagram

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Reference Design

9.3. Schematic
The most-current version of C.H.I.P. Pro’ Schematics and other technical documents are made available at:
https://github.com/NextThingCo/CHIP_Pro-Hardware.

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Join the discussion @ http://bbs.nextthing.co

Contact Us
Sales:
Sales@NextThing.co

Technical Questions:
Hardware@NextThing.co

www.getchip.com

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