W90N745 Data Sheet_0808 Nuvoton Sheet
User Manual: Nuvoton W90N745 - W90N745 data sheet
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W90N745CD/W90N745CDG
32-BIT ARM7TDMI-BASED MCU
W90N745CD/W90N745CDG
16/32-bit ARM microcontroller
Product Data Sheet
W90N745CD/W90N745CDG
Revision History
REVISION
DATE
COMMENTS
A
2006/06/23
Draft
A1
2006/07/26
Add Electrical specification
-I-
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................... 1
2.
FEATURES ................................................................................................................................. 2
3.
PIN DIAGRAM ............................................................................................................................ 7
4.
PIN ASSIGNMENT ..................................................................................................................... 8
5.
PIN DESCRIPTION................................................................................................................... 13
6.
BLOCK DIAGRAM .................................................................................................................... 24
7.
FUNCTIONAL DESCRIPTION ................................................................................................. 25
7.1
ARM7TDMI CPU CORE ............................................................................................... 25
7.2
System Manager........................................................................................................... 26
7.3
7.4
7.5
7.6
7.7
7.2.1
Overview ........................................................................................................................26
7.2.2
System Memory Map......................................................................................................26
7.2.3
Address Bus Generation ................................................................................................29
7.2.4
Data Bus Connection with External Memory ..................................................................29
7.2.5
Bus Arbitration................................................................................................................38
7.2.6
Power Management .......................................................................................................39
7.2.7
Power-On Setting ...........................................................................................................42
7.2.8
System Manager Control Registers Map ........................................................................43
External Bus Interface .................................................................................................. 58
7.3.1
EBI Overview..................................................................................................................58
7.3.2
SDRAM Controller ..........................................................................................................58
7.3.3
EBI Control Registers Map .............................................................................................62
Cache Controller........................................................................................................... 81
7.4.1
On-Chip RAM .................................................................................................................81
7.4.2
Non-Cacheable Area ......................................................................................................81
7.4.3
Instruction Cache............................................................................................................82
7.4.4
Data Cache ....................................................................................................................84
7.4.5
Write Buffer ....................................................................................................................86
7.4.6
Cache Control Registers Map.........................................................................................86
Ethernet MAC Controller............................................................................................... 94
7.5.1
EMC Functional Description ...........................................................................................95
7.5.2
EMC Register Mapping ................................................................................................105
GDMA Controller ........................................................................................................ 160
7.6.1
GDMA Functional Description ......................................................................................160
7.6.2
GDMA Register Map ....................................................................................................161
USB Host Controller ................................................................................................... 170
7.7.1
USB Host Functional Description .................................................................................170
7.7.2
USB Host Controller Registers Map .............................................................................171
- II -
W90N745CD/W90N745CDG
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
USB Device Controller................................................................................................ 195
7.8.1
USB Endpoints .............................................................................................................195
7.8.2
Standard Device Request.............................................................................................195
7.8.3
USB Device Register Description .................................................................................195
Audio Controller .......................................................................................................... 236
7.9.1
I²S Interface..................................................................................................................236
7.9.2
AC97 Interface .............................................................................................................237
7.9.3
Audio Controller Register Map......................................................................................240
Universal Asynchronous Receiver/Transmitter Controller ......................................... 259
7.10.1
UART0........................................................................................................................261
7.10.2
UART1........................................................................................................................261
7.10.3
UART2........................................................................................................................263
7.10.4
UART3........................................................................................................................265
7.10.5
General UART Controller ...........................................................................................266
7.10.6
High speed UART Controller ......................................................................................280
Timer/Watchdog Controller......................................................................................... 294
7.11.1
General Timer Controller ............................................................................................294
7.11.2
Watchdog Timer .........................................................................................................294
7.11.3
Timer Control Registers Map......................................................................................294
Advanced Interrupt Controller..................................................................................... 303
7.12.1
Interrupt Sources ........................................................................................................304
7.12.2
AIC Registers Map .....................................................................................................307
General-Purpose Input/Output ................................................................................... 321
7.13.1
GPIO Register Description .........................................................................................323
7.13.2
GPIO Register Description .........................................................................................324
2
I C Interface ................................................................................................................ 345
7.14.1
I2C Protocol ................................................................................................................346
7.14.2
I C Serial Interface Control Registers Map .................................................................349
2
Universal Serial Interface............................................................................................ 356
7.15.1
USI Timing Diagram ...................................................................................................357
7.15.2
USI Registers Map .....................................................................................................358
PWM ........................................................................................................................... 365
7.16.1
PWM Double Buffering and Reload Automatically......................................................366
7.16.2
Modulate Duty Ratio ...................................................................................................366
7.16.3
Dead Zone Generator.................................................................................................367
7.16.4
PWM Timer Start Procedure ......................................................................................367
7.16.5
PWM Timer Stop Procedure.......................................................................................367
7.16.6
PWM Register Map ....................................................................................................368
Keypad Interface......................................................................................................... 378
- III -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.18
8.
7.17.1
Keypad Interface Register Map ..................................................................................379
7.17.2
Register Description ...................................................................................................380
PS2 Host Interface Controller ..................................................................................... 387
7.18.1
PS2 Host Controller Interface Register Map...............................................................388
7.18.2
Register Description ...................................................................................................389
ELECTRICAL SPECIFICATIONS........................................................................................... 393
8.1
Absolute Maximum Ratings ........................................................................................ 393
8.2
DC Specifications ....................................................................................................... 393
8.3
8.2.1
Digital DC Characteristics.............................................................................................393
8.2.2
USB Transceiver DC Characteristics............................................................................396
AC Specifications........................................................................................................ 397
8.3.1
EBI/SDRAM Interface AC Characteristics ....................................................................397
8.3.2
EBI/(ROM/SRAM/External I/O) AC Characteristics ......................................................398
8.3.3
USB Transceiver AC Characteristics............................................................................399
8.3.4
EMC RMII AC Characteristics ......................................................................................399
8.3.5
AC97/I2S Interface AC Characteristics.........................................................................401
8.3.6
I2C Interface AC Characteristics ...................................................................................403
8.3.7
USI Interface AC Characteristics ..................................................................................404
8.3.8
PS2 Interface AC Characteristics .................................................................................405
9.
PACKAGE SPECIFICATIONS................................................................................................ 407
10.
ORDERING INFORMATION .................................................................................................. 408
11.
APPENDIX A: W90N745 REGISTERS MAPPING TABLE .................................................... 409
- IV -
W90N745CD/W90N745CDG
1. GENERAL DESCRIPTION
The W90N745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which
designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static
design is particularly suitable for cost sensitive and power sensitive applications.
One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost.
The W90N745 also provides one USB 1.1 host controller, one USB 1.1 device controller, one
AC97/I²S controller, one 2-channel GDMA, four independent UARTs, one watchdog timer, two 24-bit
timers with 8-bit pre-scale, up to 31 programmable I/O ports, PS2 keyboard controller and an
advanced interrupt controller. The external bus interface (EBI) controller provides for SDRAM,
ROM/SRAM, flash memory and I/O devices. The system manager includes an internal 32-bit system
bus arbiter and a PLL clock controller.
With a wide range of serial communication and Ethernet interfaces, the W90N745 is suitable for
communication gateways as well as many other general purpose applications.
-1-
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
2. FEATURES
Architecture
•
Fully 16/32-bit RISC architecture
•
Little/Big-Endian mode supported
•
Efficient and powerful ARM7TDMI core
•
Cost-effective JTAG-based debug solution
External Bus Interface
•
8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
•
Support for SDRAM
•
Programmable access cycle (0-7 wait cycle)
•
Four-word depth write buffer for SDRAM write data
•
Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
•
Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache
•
Support for LRU (Least Recently Used) protocol
•
Cache can be configured as internal SRAM
•
Support cache lock function
Ethernet MAC Controller
•
DMA engine with burst mode
•
MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
•
Data alignment logic
•
Endian translation
•
100/10 Mbit per second operation
•
Full compliance with IEEE standard 802.3
•
RMII interface only
•
Station Management Signaling
•
On-chip CAM (up to 16 destination addresses)
•
Full-duplex mode with PAUSE feature
•
Long/short packet modes
•
PAD generation
-2-
W90N745CD/W90N745CDG
DMA Controller
•
2-channel general DMA for memory-to-memory data transfers without CPU intervention
•
Initialed by a software or external DMA request
•
Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers
•
4-data burst mode
UART
•
Four UART (serial I/O) blocks with interrupt-based operation
•
Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive
•
Programmable baud rates
•
1, ½ or 2 stop bits
•
Odd or even parity
•
Break generation and detection
•
Parity, overrun and framing error detection
•
X16 clock mode
•
UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR
Timers
•
Two programmable 24-bit timers with 8-bit pre-scaler
•
One programmable 20 bit with selectable additional 8-bit prescaler watchdog timer
•
One-shot mode, periodical mode or toggle mode operation
Programmable I/Os
•
31 programmable I/O ports
•
Pins individually configurable to input, output or I/O mode for dedicated signals
•
I/O ports are configurable for multiple functions
Advanced Interrupt Controller
•
24 interrupt sources, including 4 external interrupt sources
•
Programmable normal or fast interrupt mode (IRQ, FIQ)
•
Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources
•
Programmable as either low-active or high-active for 4 external interrupt sources
•
Priority methodology is encoded to allow for interrupt daisy-chaining
•
Automatically mask out the lower priority interrupt during interrupt nesting
-3-
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Host Controller
•
USB 1.1 compliant
•
Compatible with Open HCI 1.0 specification
•
Supports low-speed and full speed devices
•
Build-in DMA for real time data transfer
•
Two on-chip USB transceivers with one optionally shared with USB device controller
USB Device Controller
•
USB 1.1 compliant
•
Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich
USB functions
Two PLLs
•
The external clock can be multiplied by on-chip PLL to provide high frequency system clock
•
The input frequency range is 3-30MHz; 15MHz is preferred.
•
One PLL for both CPU and USB host/device controller
•
One PLL for audio I²S 12.288/16.934MHz clock source
•
Programmable clock frequency
4-Channel PWM
•
Four 16-bit timers with PWM
•
Two 8-bit pre-scalers & Two 4-bit dividers
•
Programmable duty control of output waveform (PWM)
•
Auto reload mode or one-shot pulse mode
•
Dead-zone generator
I2C Master
•
2-channel I2C
•
Compatible with Philips I2C standard, support master mode only
•
Support multi master operation
•
Clock stretching and wait state generation
•
Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
•
Software programmable acknowledge bit
•
Arbitration lost interrupt, with automatic transfer cancellation
•
Start/Stop/Repeated Start/Acknowledge generation
•
Start/Stop/Repeated Start detection
•
Bus busy detection
-4-
W90N745CD/W90N745CDG
•
Supports 7 bit addressing mode
•
Software mode I2C
Universal Serial Interface (USI)
•
1-channel USI
•
Support USI (Microwire/SPI) master mode
•
Full duplex synchronous serial data transfer
•
Variable length of transfer word up to 32 bits
•
Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
•
MSB or LSB first data transfer
•
Rx and Tx on both rising or falling edge of serial clock independently
•
Two slave/device select lines
•
Fully static synchronous design with one clock domain
2-Channel AC97/I²S Audio Codec Host Interface
•
AHB master port and an AHB slave port are offered in audio controller.
•
Always 8-beat incrementing burst
•
Always bus lock when 8-beat incrementing burst
•
When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
KeyPad Scan Interface
•
Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4x8 array without auxiliary
component
•
Programmable debounce time
•
One or two keys scan with interrupt and three keys reset function.
•
Wakeup CPU from IDEL/Power Down mode
PS2 Host Interface
•
APB slave consisted of PS2 protocol.
•
Connect IBM keyboard or bar-code reader through PS2 interface.
•
Provide hardware scan code to ASCII translation
-5-
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Power management
•
Programmable clock enables for individual peripheral
•
IDLE mode to halt ARM core and keep peripheral working
•
Power-Down mode to stop all clocks included external crystal oscillator.
•
Exit IDLE by all interrupts
Exit Power-Down by keypad,USB device and external interrupts
Operation Voltage Range
•
3.0 ~ 3.6 V for IO buffer
•
1.62 ~ 1.98 V for core logic
Operation Temperature Range
•
TBD
Operating Frequency
•
Up to 80 MHz
Package Type
•
128-pin LQFP
-6-
W90N745CD/W90N745CDG
3. PIN DIAGRAM
Fig 3.1 Pin Diagram
-7-
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
4. PIN ASSIGNMENT
Table 4.1 W90N745 Pins Assignment
PIN NAME
128-PIN LQFP
Clock & Reset
( 3 pins )
EXTAL (15M)
XTAL (15M)
nRESET
40
41
25
JTAG Interface
( 5 pins )
TMS
TDI
TDO
TCK
nTRST
33
34
35
36
37
External Bus Interface
( 53 pins )
A [20:0]
D [15:0]
nWBE [1;0] /
SDQM [1:0]
nSCS [1:0]
nSRAS
nSCAS
MCKE
nSWE
MCLK
nWAIT /
GPIO [30] /
nIRQ [3]
nBTCS
nECS [3:0]
nOE
89-86,84-82,80-77,75-71,69-65
110-111,113-116,118-122,124-128
108,107
100,99
101
102
98
106
104
96
97
90,92-94
95
-8-
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, Continued
PIN NAME
128-PIN LQFP
Ethernet Interface
( 10 pins )
PHY_MDC /
GPIO [29] /
KPROW [1]
PHY_MDIO /
GPIO [28] /
KPROW [0]
PHY_TXD [1:0] /
GPIO [27:26] /
KPCOL [7:6]
PHY_TXEN /
GPIO [25] /
KPCOL [5]
PHY_REFCLK /
GPIO [24] /
KPCOL [4]
PHY_RXD [1:0] /
GPIO [23:22] /
KPCOL [3:2]
PHY_CRSDV /
GPIO [21] /
KPCOL [1]
PHY_RXERR /
GPIO [20] /
KPCOL [0]
64
63
62,60
59
58
57,55
54
53
( 5 pins )
AC97/I²S/PWM/UART3
AC97_nRESET /
I²S_MCLK /
GPIO [0] /
nIRQ [2] /
USB_PWREN
44
-9-
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, Continued
PIN NAME
128-PIN LQFP
( 5 pins )
AC97/I²S/PWM/UART3
AC97_DATAI /
I²S_DATAI /
PWM [0] /
DTR3 /
GPIO [1]
AC97_DATAO /
I²S_DATAO /
PWM [1] /
DSR3 /
GPIO [2]
AC97_SYNC /
I²S_LRCLK /
PWM [2] /
TXD3 /
GPIO [3]
AC97_BITCLK /
I²S_BITCLK /
PWM [3] /
RXD3
GPIO [4]
45
46
47
48
USB Interface
( 4 pins )
DP0
DN 0
DP1
DN1
7
6
2
3
Miscellaneous
( 7 pins )
nIRQ [1] /
GPIO [17] /
USB_OVRCUR
nIRQ [0] /
GPIO [16]
nWDOG /
GPIO [15] /
USB_PWREN
TEST
32
31
38
26
- 10 -
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, Continued
PIN NAME
128-PIN LQFP
2
( 4 pins )
I C/USI(SPI/MW)
SCL0 /
SFRM /
TIMER0 /
GPIO [11]
SDA0 /
SSPTXD /
TIMER1 /
GPIO [12]
SCL1 /
SCLK /
GPIO [13] /
KPROW [3]
SDA1 /
SSPRXD /
GPIO [14] /
KPROW [2]
17
18
19
20
UART0/UART1/UART2/PS2
( 6 pins )
TXD0 /
GPIO [5]
RXD0 /
GPIO [6]
TXD1 /
GPIO [7]
RXD1 /
GPIO [8]
CTS1 /
TXD2(IrDA) /
PS2_CLK /
GPIO [9]
RTS1 /
RXD2(IrDA) /
PS2_DATA /
GPIO [10]
10
11
12
13
14
15
- 11 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, Continued
PIN NAME
128-PIN LQFP
XDMA
nXDREQ /
GPIO [19] /
nXDACK /
GPIO [18] /
( 2 pins )
51
52
Power/Ground
( 36 pins )
VDD18
VSS18
VDD33
VSS33
USBVDD
USBVSS
PLLVDD18
PLLVSS18
21,43,49,85,112
22,50,81,109
9,23,42,61,76,103,117
16,24,39,56,70,91,105,123
1,8
4,5
27,30
28,29
- 12 -
W90N745CD/W90N745CDG
5. PIN DESCRIPTION
Table 5.1 W90N745 Pins Description
PIN NAME
IO TYPE
DESCRIPTION
Clock & Reset
EXTAL (15M)
XTAL (15M)
nRESET
I
O
IS
15MHz External Clock / Crystal Input
15MHz Crystal Output
System Reset, active-low
JTAG Interface
TMS
TDI
TDO
TCK
nTRST
IUS
IUS
O
IDS
IUS
JTAG Test Mode Select, internal pull-up with 70K ohm
JTAG Test Data in, internal pull-up with 70K ohm
JTAG Test Data out
JTAG Test Clock, internal pull-down with 58K ohm
JTAG Reset, active-low, internal pull-up with 70K ohm
O
IOS
IOS
Address Bus (MSB) of external memory and IO devices.
Address Bus of external memory and IO devices.
Data Bus (LSB) of external memory and IO device.
Write Byte Enable for specific device (nECS [1:0]).
Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.
SDRAM chip select for two external banks, active-low.
Row Address Strobe for SDRAM, active-low.
Column Address Strobe for SDRAM, active-low.
SDRAM Clock Enable, active-high
SDRAM Write Enable, active-low
System Master Clock Out, SDRAM clock, output with slew-rate control
External Bus Interface
A [20:18]
A [17:0]
D [15:0]
nWBE [1:0] /
SDQM [1:0]
nSCS [1:0]
nSRAS
nSCAS
MCKE
nSWE
MCLK
nWAIT /
GPIO[30] /
nIRQ3
nBTCS
nECS [3:0]
nOE
IOS
O
O
O
O
O
O
IUS
O
IO
O
External Wait, active-low. This pin indicates that the external devices need
more active cycle during access operation.
General Programmable In/Out Port GPIO[30]. If memory and IO devices in EBI
do not need wait request, it can be configured as GPIO[30] or nIRQ3.
ROM/Flash Chip Select, active-low.
External I/O Chip Select, active-low.
ROM/Flash, External Memory Output Enable, active-low.
- 13 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, Continued
PIN NAME
IO TYPE
DESCRIPTION
IOU
RMII Management Data Clock for Ethernet. It is the reference clock of MDIO.
Each MDIO data will be latched at the rising edge of MDC clock.
General Programmable In/Out Port [29]
Keypad ROW[1] scan output.
IO
RMII Management Data I/O for Ethernet. It is used to transfer RMII control and
status information between PHY and MAC.
General Programmable In/Out Port [28]
Keypad ROW[0] scan output.
Ethernet Interface
PHY_MDC /
GPIO [29] /
KPROW [1]
PHY_MDIO /
GPIO [28] /
KPROW [0]
PHY_TXD [1:0] /
GPIO [27:26] /
KPCOL [7:6]
PHY_TXEN /
IOU
2-bit Transmit Data bus for Ethernet.
General programmable In/Out Port [27:26]
Keypad column input [7:6], active low
IOU
PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble
and shall remain asserted while all di-bits to be transmitted are presented. Of
course, it is synchronized with PHY_REFCLK.
General Programmable In/Out Port [25]
Keypad column input [5], active low
IOS
Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35%
duty cycle at high or low state.
General Programmable In/Out port [24]
Keypad column input [4], active low
IOS
2-bit Receive Data bus for Ethernet.
General Programmable In/Out Port [23:22]
Keypad column input [3:2], active low
IOS
Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be
asserted by PHY when the receive medium is non-idle. Loss of carrier shall
result in the de-assertion of PHY_CRSDV synchronous to the cycle of
PHY_REFCLK, and only on 2-bit receive data boundaries.
General Programmable In/Out port [21]
Keypad column input [1], active low
IOS
Receive Data Error for Ethernet. It indicates a data error detected by PHY.The
assertion should be lasted for longer than a period of PHY_REFCLK. When
PHY_RXERR is asserted, the MAC will report a CRC error.
General programmable In/Out port [20]
Keypad column input [0], active low
GPIO [25] /
KPCOL [5]
PHY_REFCLK /
GPIO [24] /
KPCOL [4]
PHY_RXD [1:0] /
GPIO [23:22] /
KPCOL [3:2]
PHY_CRSDV /
GPIO [21] /
KPCOL [1]
PHY_RXERR /
GPIO [20] /
KPCOL [0]
- 14 -
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, Continued
PIN NAME
IO TYPE
AC97/I²S/PWM/UART3
AC97_nRESET /
I²S_MCLK /
IOU
GPIO [0] /
nIRQ [2] /
USB_PWREN
AC97_DATAI /
I²S_DATAI /
IOU
PWM [0] /
DTR3 /
GPIO [1]
AC97_DATAO /
I²S_DATAO /
PWM [1] /
DSR3 /
GPIO [2]
IOU
AC97_SYNC /
I²S_LRCLK /
PWM [2] /
TXD3 /
GPIO [3]
IOU
AC97_BITCLK /
I²S_BITCLK /
PWM [3] /
RXD3 /
GPIO [4]
IOS
USB Interface
DP0
DN0
DP1
DN1
Miscellaneous
IO
IO
IO
IO
nIRQ [1:0] /
GPIO [17:16] /
AC97 CODEC Host Interface RESET Output.
I²S CODEC Host Interface System Clock Output.
General Purpose In/Out port [0]
External interrupt request.
USB host power enable output
AC97 CODEC Host Interface Data Input.
I²S CODEC Host Interface Data Input.
PWM Channel 0 output.
Data Terminal Ready for UART3.
General Purpose In /Out port [1]
AC97 CODEC Host Interface Data Output.
I²S CODEC Host Interface Data Output.
PWM Channel 1 output.
Data Set Ready for UART3.
General Purpose In/Out port [2]
AC97 CODEC Host Interface Synchronous Pulse Output.
I²S CODEC Host Interface Left/Right Channel Select Clock.
PWM Channel 2 output.
Transmit Data for UART3.
General Purpose In/Out port [3]
AC97 CODEC Host Interface Bit Clock Input.
I²S CODEC Host Interface Bit Clock.
PWM Channel 3 output.
Receive Data for UART3.
General Purpose In/Out port [4].
Differential Positive USB IO signal
Differential Negative USB IO signal
Differential Positive USB IO signal
Differential Negative USB IO signal
External Interrupt Request
IOU
USB_OVRCUR
nWDOG /
GPIO [15] /
USB_PWREN
TEST
DESCRIPTION
General Purpose I/O
nIRQ1 is used as USB host over-current detection input
IOU
IDS
Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low
General Purpose In/output
USB host power switch enable output
This test pin must be short to ground or left unconnected
- 15 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, Continued
PIN NAME
IO TYPE
DESCRIPTION
2
I C/USI
SCL0 /
SFRM /
TIMER0 /
GPIO [11]
SDA0 /
SSPTXD /
TIMER1 /
GPIO [12]
SCL1 /
SCLK /
GPIO [13] /
KPROW [3]
SDA1 /
SSPRXD /
GPIO [14] /
KPROW [2]
2
IOU
I C Serial Clock Line 0.
USI Serial Frame.
Timer0 time out output.
General Purpose In/Out port [11].
IOU
I C Serial Data Line 0
USI Serial Transmit Data
Timer1 time out output
General Purpose In/Out port [12]
IOU
I C Serial Clock Line 1
USI Serial Clock
General Purpose In/Out port [13]
Keypad row scan output [3]
IDU
I C Serial Data Line 1
USI Serial Receive Data
General Purpose In/Out port [14]
Keypad scan output [2]
2
2
2
UART0/UART1/UART2
TXD0 /
IOU
GPIO [5]
RXD0 /
IOU
GPIO [6]
TXD1 /
IOU
GPIO [7]
RXD1 /
IOU
GPIO [8]
CTS1/
TXD2(IrDA) /
IOU
PS2_CLK /
GPIO [9]
RTS1/
RXD2(IrDA) /
IOU
PS2_DATA /
GPIO [10]
XDMA
nXDREQ /
IO
GPIO [19] /
nXDACK /
IO
GPIO [18] /
UART0 Transmit Data.
General Purpose In/Out [5]
UART0 Receive Data.
General Purpose In/Out [6]
UART1 Transmit Data.
General Purpose In/Out [7]
UART1 Receive Data.
General Purpose In/Out [8]
UART1 Clear To Send for Bluetooth application
UART2 Transmit Data supporting SIR IrDA.
PS2 Interface Clock Input/Output
General Purpose In/Out [9]
UART1 Request To Send for Bluetooth application
UART2 Receive Data supporting SIR IrDA.
PS2 Interface Bi-Directional Data Line.
General Purpose In/Out [10]
External DMA Request.
General Purpose In/Out [19]
External DMA Acknowledgement.
General Purpose In/Out [18]
- 16 -
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, Continued
PIN NAME
IO TYPE
DESCRIPTION
Power/Ground
VDD18
P
Core Logic power (1.8V)
VSS18
G
Core Logic ground (0V)
VDD33
P
IO Buffer power (3.3V)
VSS33
G
IO Buffer ground (0V)
USBVDD
P
USB power (3.3V)
USBVSS
G
USB ground (0V)
DVDD18
P
PLL Digital power (1.8V)
DVSS18
G
PLL Digital ground (0V)
AVDD18
P
PLL Analog power (1.8V)
AVSS18
G
PLL Analog ground (0V)
- 17 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List
PIN NO.
DEFAULT
FUNCTION0
FUNCTION1
FUNCTION2
FUNCTION3
USB1.1 Host/Device Interface
1
USBVDD
USBVDD
-
-
-
2
DP1
DP1
-
-
-
3
DN1
DN1
-
-
-
4
USBVSS
USBVSS
-
-
-
5
USBVSS
USBVSS
-
-
-
6
DN0
DN0
-
-
-
7
DP0
DP0
-
-
-
8
USBVDD
USBVDD
-
-
-
9
VDD33
VDD33
-
-
-
UART[2:0]/PS2 Interface
10
GPIO[5]
GPIO[5]
UART_TXD0
-
-
11
GPIO[6]
GPIO[6]
UART_RXD0
-
-
12
GPIO[7]
GPIO[7]
UART_TXD1
-
-
13
GPIO[8]
GPIO[8]
UART_RXD1
-
-
14
GPIO[9]
GPIO[9]
UART_TXD2
UART_CTS1
PS2_CLK
15
GPIO[10]
GPIO[10]
UART_RXD2
UART_RTS1
PS2_DATA
16
VSS33
VSS33
-
-
-
I C_SCL0
SSP_FRAM
TIMER0
SSP_TXD
TIMER1
SSP_SCLK
KPI_ROW[3]
2
I C/USI Interface
17
18
19
GPIO[11]
GPIO[12]
GPIO[13]
2
GPIO[11]
2
I C_SDA0
GPIO[12]
2
I C_SCL1
GPIO[13]
2
20
GPIO[14]
GPIO[14]
I C_SDA1
SSP_RXD
KPI_ROW[2]
21
VDD18
VDD18
-
-
-
22
VSS18
VSS18
-
-
-
23
VDD33
VDD33
-
-
-
24
VSS33
VSS33
-
-
-
System Reset & TEST
25
nRESET
nRESET
-
-
-
26
TEST
TEST
-
-
-
- 18 -
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List , Continued
PLL Power/Ground
27
PLL_VDD18
PLL_VDD18
-
-
-
28
PLL_VSS18
PLL_VSS18
-
-
-
29
PLL_VSS18
PLL_VSS18
-
-
-
30
PLL_VDD18
PLL_VDD18
-
-
-
External IRQ[1:0]/USB Over Current
31
GPIO[16]
GPIO[16]
nIRQ [0]
-
-
32
GPIO[17]
GPIO[17]
nIRQ [1]
USB_OVRCUR
-
JTAG Interface
33
TMS
TMS
-
-
-
34
TDI
TDI
-
-
-
35
TDO
TDO
-
-
-
36
TCK
TCK
-
-
-
37
nTRST
nTRST
-
-
-
WatchDog/USB Power Enable
38
GPIO[15]
GPIO[15]
nWDOG
USB_PWREN
-
39
VSS33
VSS33
-
-
-
System Clock
40
EXTAL(15M)
EXTAL(15M)
-
-
-
41
XTAL(15M)
XTAL(15M)
-
-
-
42
VDD33
VDD33
-
-
-
43
VDD18
VDD18
-
-
-
- 19 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List , Continued
PIN NO.
DEFAULT
FUNCTION0
FUNCTION1
FUNCTION2
FUNCTION3
nIRQ [2]
USB_PWREN
PWM0
UART_DTR3
PWM1
UART_DSR3
PWM2
UART_TXD3
PWM3
UART_RXD3
-
-
-
-
-
-
AC97/I²S/PWM/UART3 Interface
AC97_nRESET
44
GPIO[0]
GPIO[0]
or
I²SMCLK
AC97_DATAI
45
GPIO[1]
GPIO[1]
or
I²SDATAI
AC97_DATAO
46
GPIO[2]
GPIO[2]
or
I²SDATAO
AC97_SYNC
47
GPIO[3]
GPIO[3]
or
I²SLRCLK
AC97_BITCLK
48
GPIO[4]
GPIO[4]
or
I²SBITCLK
49
VDD18
VDD18
50
VSS18
VSS18
XDMAREQ
51
GPIO[19]
GPIO[19]
nXDREQ
-
-
52
GPIO[18]
GPIO[18]
nXDACK
-
-
Ethernet RMII/KeyPad Interface
53
GPIO[20]
GPIO[20]
PHY_RXERR
KPI_COL[0]
-
54
GPIO[21]
GPIO[21]
PHY_CRSDV
KPI_COL[1]
-
55
GPIO[22]
GPIO[22]
PHY_RXD[0]
KPI_COL[2]
-
56
VSS33
VSS33
-
-
-
57
GPIO[23]
GPIO[23]
PHY_RXD[1]
KPI_COL[3]
-
58
GPIO[24]
GPIO[24]
PHY_REFCLK
KPI_COL[4]
-
59
GPIO[25]
GPIO[25]
PHY_TXEN
KPI_COL[5]
-
60
GPIO[26]
GPIO[26]
PHY_TXD[0]
KPI_COL[6]
-
61
VDD33
VDD33
-
-
-
62
GPIO[27]
GPIO[27]
PHY_TXD[1]
KPI_COL[7]
-
63
GPIO[28]
GPIO[28]
PHY_MDIO
KPI_ROW[0]
64
GPIO[29]
GPIO[29]
PHY_MDC
KPI_ROW[1]
- 20 -
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List, Continued
PIN
NO.
DEFAULT
FUNCTION0
FUNCTION1
FUNCTION2
FUNCTION3
Memory Address/Data/Control
65
A[0]
A[0]
-
-
-
66
A[1]
A[1]
-
-
-
67
A[2]
A[2]
-
-
-
68
A[3]
A[3]
-
-
-
69
A[4]
A[4]
-
-
-
70
VSS33
VSS33
-
-
-
71
A[5]
A[5]
-
-
-
72
A[6]
A[6]
-
-
-
73
A[7]
A[7]
-
-
-
74
A[8]
A[8]
-
-
-
75
A[9]
A[9]
-
-
-
76
VDD33
VDD33
-
-
-
77
A[10]
A[10]
-
-
-
78
A[11]
A[11]
-
-
-
79
A[12]
A[12]
-
-
-
80
A[13]
A[13]
-
-
-
81
VSS18
VSS18
-
-
-
82
A[14]
A[14]
-
-
-
83
A[15]
A[15]
-
-
-
84
A[16]
A[16]
-
-
-
85
VDD18
VDD18
-
-
-
86
A[17]
A[17]
-
-
-
87
A[18]
A[18]
-
-
-
88
A[19]
A[19]
-
-
-
89
A[20]
A[20]
-
-
-
90
nECS[3]
nECS[3]
-
-
-
91
VSS33
VSS33
-
-
-
- 21 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List, Continued
PIN
NO.
DEFAULT
FUNCTION0
FUNCTION1
FUNCTION2
FUNCTION3
Memory Address/Data/Control
92
nECS[2]
nECS[2]
-
-
-
93
nECS[1]
nECS[1]
-
-
-
94
nECS[0]
nECS[0]
-
-
-
95
nOE
nOE
-
-
-
96
nWAIT
GPIO[30]
nWAIT
nIRQ [3]
-
97
nBTCS
nBTCS
-
-
-
98
MCKE
MCKE
-
-
-
99
nSCS[0]
nSCS[0]
-
-
-
100
nSCS[1]
nSCS[1]
-
-
-
101
nSRAS
nSRAS
-
-
-
102
nSCAS
nSCAS
-
-
-
103
VDD33
VDD33
-
-
-
104
MCLK
MCLK
-
-
-
105
VSS33
VSS33
-
-
-
106
nSWE
nSWE
-
-
-
107
nWBE/SDQM[0]
nWBE or SDQM[0]
108
nWBE/SDQM[1]
nWBE or SDQM[1]
109
VSS18
VSS18
-
-
-
110
D[15]
D[15]
-
-
-
111
D[14]
D[14]
-
-
-
112
VDD18
VDD18
-
-
-
113
D[13]
D[13]
-
-
-
114
D[12]
D[12]
-
-
-
115
D[11]
D[11]
-
-
-
116
D[10]
D[10]
-
-
-
117
VDD33
VDD33
-
-
-
118
D[9]
D[9]
-
-
-
119
D[8]
D[8]
-
-
-
120
D[7]
D[7]
-
-
-
- 22 -
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List, Continued
PIN NO.
DEFAULT
FUNCTION0
FUNCTION1
FUNCTION2
FUNCTION3
Memory Address/Data/Control
121
D[6]
D[6]
-
-
-
122
D[5]
D[5]
-
-
-
123
VSS33
VSS33
-
-
-
124
D[4]
D[4]
-
-
-
125
D[3]
D[3]
-
-
-
126
D[2]
D[2]
-
-
-
127
D[1]
D[1]
-
-
-
128
D[0]
D[0]
-
-
-
- 23 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
6. BLOCK DIAGRAM
Cache
Controller
TDMI Bus
JTAG
ICE
ARM7TDMI
Wrapper
Clock
Synthesizer
PLL
Clock
Synthesizer
* 15MHz
RMII Bus
PHY
Ethernet MAC
Controller
PHY
USB 1.1 Host
Controller
PHY
USB 1.1 Device
Controller
Power
Management
Unit
AHB Bus
External Bus
Interface
2 Timers
4KB
D-Cache
APB Bus
PLL
4KB
I-Cache
AHB
Arbiter
AHB
Decoder
Watch-Dog
Timer
I2C(x2)/USI
UART (x4) with
IrDA/Bluetooth/
Micro-printer
4-Channels
PWM
APB
Bridge
* Host/Device
Advanced
Interrupt
Controller
31 GPIOs
2-Channel GDMA
Keypad
Controller
2-channel AC97/I2S
W90N745
Block Diagram
Fig 6.1 W90N745 Functional Block Diagram
- 24 -
PS/2 Keyboard
Host Interface
W90N745CD/W90N745CDG
7. FUNCTIONAL DESCRIPTION
7.1
ARM7TDMI CPU CORE
The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set
Computers. Pipelining is employed so that all parts of the processing and memory systems can operate
continuously. The high instruction throughput and impressive real-time interrupt response are the major
benefits.
The ARM7TDMI CPU core has two instruction sets:
(1) The standard 32-bit ARM set
(2) A 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core
while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit
registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent
interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding
32-bit ARM instruction with the same effect on the processor model.
ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers
are used to speed up exception processing. All the register specified in ARM instructions can address
any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt,
memory aborts, attempted execution of an undefined instruction and software interrupts.
A[31:0]
Address Register
Incrementer Bus
PC Bus
Address
Incrementer
Scan Control
Instruction Decoder
Control Logic
Register Bank
(31 x 32-bit registers)
(6 status registers)
B Bus
32 x8 Multiplier
A Bus
ALU Bus
Instruction Pipeline
Read Data Register
Thumb Instruction Decoder
Barrel Shifter
Writer Data
Register
32-bit ALU
D[31:0]
Fig 7.1 ARM7TDMI CPU Core Block Diagram
- 25 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.2
7.2.1
System Manager
Overview
The W90N745 system manager has the following functions.
System memory map
Data bus connection with external memory
Product identifier register
Bus arbitration
PLL module
Clock select and power saving control register
Power-On setting
7.2.2
System Memory Map
W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the OnChip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space:0x0000_0000~0x7FDF_FFFF
if
Cache
ON;
non-cacheable
space:
0x8000_0000~0xFFDF_FFFF).
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. Please note that when setting the bank control registers, the address
boundaries of consecutive banks must not overlap.
Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access requested to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 4M bytes (by word
format), and 64M bytes on each SDRAM bank.
- 26 -
W90N745CD/W90N745CDG
0x7FFF_FFFF
512KB
(Fixed)
0x7FF8.0000
RESERVED
512KB
(Fixed)
0x7FF0_0000
RESERVED
8KB
RESERVED
0x7FE0_0000
RESERVED
0xFFFF_FFFF
512KB
(Fixed)
0xFFF8_0000
512KB
(Fixed)
0xFFF0_0000
On-Chip AHB
Peripherals
RESERVED
On-Chip RAM
8KB
0xFFE0_0000
4KB,4KB
External I/O Bank 3
External I/O Bank 3
External I/O Bank 2
External I/O Bank 2
External I/O Bank 1
External I/O Bank 1
256 KB - 4MB
256 KB - 4MB
256 KB - 4MB
256 KB - 4MB
256 KB - 4MB
256 KB - 4MB
EBI Space
EBI Space
External I/O Bank 0
External I/O Bank 0
SDRAM Bank 1
SDRAM Bank 1
2MB - 64MB
2MB - 64MB
SDRAM Bank 0
SDRAM Bank 0
2MB - 64MB
2MB - 64MB
ROM/FLASH
ROM/FLASH
256 KB - 4MB
0x0000 _0000
On-Chip APB
Peripherals
256 KB - 4MB
256 KB - 4MB
0x8000 _0000
256 KB - 4MB
Fig7.2.1 System Memory Map
- 27 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 7.2.1 On-Chip Peripherals Memory Map
BASE ADDRESS
DESCRIPTION
AHB Peripherals
0xFFF0_0000
Product Identifier Register (PDID)
0xFFF0_0004
Arbitration Control Register (ARBCON)
0xFFF0_0008
PLL Control Register 0(PLLCON0)
0xFFF0_000C
Clock Select Register (CLKSEL)
0xFFF0_0010
PLL Control Register 1 (PLLCON1)
0xFFF0_0014
Audio I²S Clock Control Register (I²SCKCON)
0xFFF0_0020
IRQ Wakeup Control Register (IRQWAKEUPCON)
0xFFF0_0024
IRQ Wakeup Flag Register (IRQWAKEFLAG)
0xFFF0_0028
Power Manager Control Register (PMCON)
0xFFF0_0030
USB Transceiver Control Register (USBTXRCON)
0xFFF0_1000
EBI Control Register (EBICON) Control Registers
0xFFF0_1004
ROM/FLASH (ROMCON) Control Registers
0xFFF0_1008
SDRAM bank 0 – 1 Control Registers
0xFFF0_1018
External I/O 0 – 3 Control Registers
0xFFF0_2000
Cache Controller Control Registers
0xFFF0_3000
Ethernet MAC Controller Control Registers
0xFFF0_4000
GDMA 0 – 1 Control Registers
0xFFF0_5000
USB Host Controller Control Registers
0xFFF0_6000
USB Device Controller Control Registers
0xFFF0_9000
AC97/I²S Controller Control Registers
APB Peripherals
0xFFF8_0000
UART 0 (Tx, RX for console)
0xFFF8_0100
UART 1 (Tx, Rx, for bluetooth)
0xFFF8_0200
UART 2 (bluetooth CTS, RTS/ IrDA Tx, Rx)
0xFFF8_0300
UART 3 (micro-print DTR, DTS, Tx, Rx)
0xFFF8_1000
Timer 0 – 1, WDOG Timer
0xFFF8_2000
Interrupt Controller
0xFFF8_3000
GPIO
0xFFF8_6000
I2C-0 Control Registers
0xFFF8_6100
I2C-1 Control Registers
0xFFF8_6200
USI Control Registers
0xFFF8_7000
Pulse Width Modulation (PWM) Control Registers
0xFFF8_8000
KeyPad Interface Control Register (KPI)
0xFFF8_9000
PS2 Control Registers
- 28 -
W90N745CD/W90N745CDG
7.2.3
Address Bus Generation
The W90N745 address bus generation is depended on the required data bus width of each memory
bank. The data bus width is determined by DBWD bits in each bank’s control register.
The maximum accessible memory size of each external IO bank is 4M bytes.
Table 7.2.2 Address Bus Generation Guidelines
DATA BUS
EXTERNAL ADDRESS PINS
WIDTH
A [20:0]
A20 – A0
(Internal)
A21 – A1
(Internal)
8-bit
16-bit
7.2.4
MAXIMUM ACCESSIBLE MEMORY SIZE
2M bytes
2M half-words
Data Bus Connection with External Memory
7.2.4.1. Memory formats
The W90N745 can be configured as big endian or little endian mode by pull up or down the external data
bus D14 pin. If D14 is pull up, then it is a little endian mode, otherwise, it is a big endian mode.
Little endian
In little endian format, the lowest addressed byte in a word is considered the least significant byte of the
word and the highest addressed byte is the most significant. So the byte at address 0 of the memory
system connects to data lines 7 through 0.
For a word aligned address A, Fig7.2.2 shows how the half-word at addresses A and A+2, and the bytes
at addresses A, A+1, A+2, and A+3 map on to each other when D14 pin is High.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Half-word at address A
Half-word at address A+2
Byte at address A+1
Byte at address A
Byte at address A+3
Byte at address A+2
Fig7.2.2 Little endian addresses of bytes and half-words within half words
- 29 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Big endian
In Big endian format, the W90N745 stores the most significant byte of a word at the lowest numbered
byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory
system connects to data lines 31 through 24.
For a word aligned address A, Fig7.2.3 shows how the half-word at addresses A and A+2, and the bytes
at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Half-word at address A
Half-word at address A+2
Byte at address A
Byte at address A+1
Byte at address A+2
Byte at address A+3
Fig7.2.3 Big endian addresses of bytes and half-words within half words
7.2.4.2. Connection of External Memory with Various Data Width
The system diagram for W90N745 connecting with the external memory is shown in Fig7.2.4. Below
tables (Table7.2.3 through Table7.2.14) show the program/data path between CPU register and the
external memory using little / big endian and word/half-word/byte access.
Fig7.2.4 Address/Data bus connection with external memory
- 30 -
W90N745CD/W90N745CDG
Fig7.2.5 CPU registers Read/Write with external memory
Table 7.2.3 and Table 7.2.4
Using big-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C
X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table7.2.3 Word access write operation with Big Endian
ACCESS
OPERATION
XD WIDTH
Bit Number
CPU Reg
Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [1-0]
/
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem
Data
Timing
Sequence
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
HALF WORD
BYTE
31 0
ABCD
31 0
ABCD
WA
31
0
AB CD
WA
31
0
A B C D
7 0
7 0
B
C
WA+1
WA+2
15 0
AB
WA
15 0
CD
WA+2
7 0
A
WA
AA
AA
XA
XA
XA
XA
15 0
AB
15 0
CD
7 0
A
7 0
B
7 0
C
7 0
D
15 0
AB
15 0
CD
7 0
A
7 0
B
7 0
C
7 0
D
1st write
2nd write
1st write
2nd write
3rd write
4th write
- 31 -
7 0
D
WA+3
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table7.2.4 Word access read operation with Big Endian
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
ACCESS OPERATION
XD WIDTH
HALF WORD
BYTE
Bit Number
CPU Reg Data
31 0
CDAB
31 0
DCBA
SA
WA
WA
Bit Number
SD
Bit Number
ED
31
0
CD AB
31
0
31
0
CD XX
CD AB
31
0
D C B A
31
0
31
0
D C X X D C B X
WA
XA
31
0
D X X X
WA+2
WA
WA+1
WA+2
31
0
D C B A
WA+3
SDQM [1-0]
AA
AA
XA
XA
XA
XA
Bit Number
XD
Bit Number
Ext. Mem Data
15 0
CD
15 0
CD
15 0
AB
15 0
AB
7 0
D
7 0
D
7 0
C
7 0
C
7 0
B
7 0
B
7 0
A
7 0
A
Timing Sequence
1st read
2nd read
1st read
2nd read
3rd read
4th read
Table 7.2.5 and Table 7.2.6
Using big-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0,2,4,6,8,A,C,E
X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table7.2.5 Half-word access write operation with Big Endian
ACCESS OPERATION
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD WIDTH
HALF WORD
BYTE
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
HA
SA
HA
Bit Number
SD
Bit Number
ED
31 0
CD CD
31 0
CD CD
31 0
CD CD
7 0
C
31 0
CD CD
7 0
D
XA
HA
HA
HA+1
AA
XA
XA
15 0
CD
15 0
CD
7 0
C
7 0
C
7 0
D
7 0
D
1st write
2nd write
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
- 32 -
W90N745CD/W90N745CDG
Table7.2.6 Half-word access read operation with Big Endian
ACCESS OPERATION
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD WIDTH
HALF WORD
BYTE
Bit Number
CPU Reg Data
15 0
CD
15 0
DC
SA
HA
HA
Bit Number
SD
Bit Number
ED
15 0
CD
15 0
CD
15 0
DC
15 0
DX
15 0
DC
XA
HA
HA
HA+1
SDQM [1-0]
AA
XA
XA
Bit Number
XD
Bit Number
Ext. Mem Data
15 0
CD
15 0
CD
7 0
D
7 0
D
7 0
C
7 0
C
1st read
2nd read
Timing Sequence
Table 7.2.7 and Table 7.2.8
Using big-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E
BAU = Address whose LSB is 1,3,5,7,9,B,D,F
- 33 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table7.2.7 Byte access write operation with Big Endian
ACCESS OPERATION
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD WIDTH
HALF WORD
BYTE
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
SA
BAL
BAU
BA
Bit Number
SD
Bit Number
ED
31
0
D D D D
15 8
D
31
0
D D D D
7 0
D
31
0
D D D D
7 0
D
XA
BAL
BAL
BA
AU
UA
XA
15 0
DX
15 8
D
15 0
XD
7 0
D
7 0
D
7 0
D
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
Table7.2.8 Byte access read operation with Big Endian
ACCESS OPERATION
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD WIDTH
HALF WORD
BYTE
Bit Number
CPU Reg Data
7 0
C
7 0
D
7 0
D
SA
BAL
BAU
BA
Bit Number
SD
Bit Number
ED
7 0
C
7 0
C
7 0
D
15 8
D
7 0
D
7 0
D
XA
BAL
BAL
BA
SDQM [1-0]
AU
UA
XA
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
15 0
CD
15 0
CD
7 0
D
7 0
D
15 0
CD
- 34 -
W90N745CD/W90N745CDG
Table 7.2.9 and Table 7.2.10
Using little-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C
X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table7.2.9 Word access write operation with little Endian
ACCESS OPERATION
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD WIDTH
HALF WORD
BYTE
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
SA
WA
WA
Bit Number
SD
Bit Number
ED
31
0
AB CD
15 0
CD
15 0
AB
7 0
D
31
0
A B C D
7 0
7 0
C
B
XA
WA
WA+2
WA
WA+1
WA+2
WA+3
7 0
A
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
AA
AA
XA
XA
XA
XA
15 0
CD
15 0
CD
15 0
AB
15 0
AB
7 0
D
7 0
D
7 0
C
7 0
C
7 0
B
7 0
B
7 0
A
7 0
A
Timing Sequence
1st write
2nd write
1st write
2nd write
3rd write
4th write
Table7.2.10 Word access read operation with Little Endian
Read Operation (CPU Register Í External Memory)
Access Operation
XD Width
Half Word
Byte
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
SA
WA
WA
Bit Number
SD
Bit Number
ED
31
0
AB CD
31
0
31
0
XX CD
AB CD
31
0
A B C D
31
0
31
0
X X C D X B C D
31
0
X X X D
31
0
A B C D
XA
WA
WA+2
WA
WA+1
WA+2
WA+3
SDQM [1-0]
AA
AA
XA
XA
XA
XA
Bit Number
XD
Bit Number
Ext. Mem Data
15 0
CD
15 0
CD
15 0
AB
15 0
AB
7 0
D
7 0
D
7 0
C
7 0
C
7 0
B
7 0
B
7 0
A
7 0
A
Timing Sequence
1st write
2nd write
1st write
2nd write
3rd write
4th write
- 35 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 7.2.11 and Table 7.2.12
Using little-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0,2,4,6,8,A,C,E
X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table7.2.11 Half-word access write operation with little Endian
Access Operation
Write Operation (CPU Register Î External Memory)
XD Width
Half Word
Byte
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
SA
HA
Bit Number
SD
Bit Number
ED
31 0
CD CD
31 0
CD CD
31 0
CD CD
7 0
D
31 0
CD CD
7 0
C
XA
HA
HA
HA+1
AA
XA
XA
15 0
CD
15 0
CD
7 0
D
7 0
D
7 0
C
7 0
C
1st write
2nd write
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
HA
Timing Sequence
Table7.2.12 Half-word access read operation with Little Endian
Access Operation
Read Operation (CPU Register Í External Memory)
XD Width
Half Word
Byte
Bit Number
CPU Reg Data
15 0
CD
15 0
CD
SA
HA
HA
Bit Number
SD
Bit Number
ED
15 0
CD
15 0
CD
15 0
CD
15 0
XD
15 0
CD
XA
HA
HA
HA+1
SDQM [1-0]
AA
XA
XA
Bit Number
XD
Bit Number
Ext. Mem Data
15 0
CD
15 0
CD
7 0
D
7 0
D
7 0
C
7 0
C
1st read
2nd read
Timing Sequence
- 36 -
W90N745CD/W90N745CDG
Table 7.2.13 and Table 7.2.14
Using little-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F
Table7.2.13 Byte access write operation with little Endian
Access Operation
Write Operation (CPU Register Î External Memory)
XD Width
Half Word
Byte
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
SA
BAL
BAU
BA
Bit Number
SD
Bit Number
ED
31
0
D D D D
7 0
D
31
0
D D D D
15 8
D
31
0
D D D D
7 0
D
XA
BAL
BAL
BA
UA
AU
XA
15 0
XD
7 0
D
15 0
DX
15 8
D
7 0
D
7 0
D
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
Table7.2.14 Byte access read operation with Little Endian
Access Operation
Read Operation (CPU Register Í External Memory)
XD Width
Half Word
Byte
Bit Number
CPU Reg Data
7 0
D
7 0
C
7 0
D
SA
BAL
BAU
BA
Bit Number
SD
Bit Number
ED
7 0
D
7 0
D
7 0
C
7 0
C
7 0
D
7 0
D
XA
BAL
BAL
BA
SDQM [1-0]
UA
AU
XA
Bit Number
XD
Bit Number
Ext. Mem Data
15 0
CD
15 0
CD
7 0
D
7 0
D
15 0
CD
Timing Sequence
- 37 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.2.5
Bus Arbitration
The W90N745’s internal function blocks or external devices can request mastership of the system bus
and then hold the system bus in order to perform data transfers. Because the design of W90N745 bus
allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal
units or external devices simultaneously request bus mastership. When bus mastership is granted to an
internal function block or an external device, other pending requests are not acknowledged until the
previous bus master has released the bus.
W90N745 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode,
depends on the ARBCON register PRTMOD bit setting.
7.2.5.1. Fixed Priority Mode
In Fixed Priority Mode (PRTMOD=0, default value), to facilitate bus arbitration, priorities are assigned to
each internal W90N745 function block. The bus controller arbitration requests for the bus mastership
according to these fixed priorities. In the event of contention, mastership is granted to the function block
with the highest assigned priority. These priorities are listed in Table 7.2.15.
W90N745 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit 1
of the Arbitration Control Register (ARBCON), is set to “0”, the priority of ARM Core is fixed to lowest.
If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still lowest
and the IPACT=0, Bit 2 of the Arbitration Control Register (ARBCON) ； If there is an unmasked
interrupt request, then the ARM Core’s priority is raised to first and IPACT=1.
If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an
alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in
the interrupt handler. The IPACT bit can be read and written. Writing with “0”, the IPACT bit is cleared,
but it will be no effect as writing with “1”.
Table 7.2.15 Bus Priorities for Arbitration in Fixed Priority Mode
BUS
FUNCTION BLOCK
PRIORITY
1 (Highest)
IPACT = 0
IPEN = 1 AND IPACT = 1
Audio Controller (AC97 & I²S)
ARM Core
2
General DMA0
Audio Controller (AC97 & I²S)
3
General DMA1
General DMA0
4
EMC DMA
General DMA1
5
USB Host
EMC DMA
6
USB Device
USB Host
ARM Core
USB Device
7(Lowest)
7.2.5.2. Rotate Priority Mode
In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored).
W90N745 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain
the bus and that a retracted master does not lock up the bus.
- 38 -
W90N745CD/W90N745CDG
7.2.6
Power Management
W90N745 provide three power management scenarios to reduce power consumption. The
peripherals’ clocks can be enabled / disabled individually by controlling the co-responding bit in
CLKSEL control register. Software can turn-off the unused modules’ clocks to saving the unnecessary
power consumption. It also provides idle and power-down modes to reduce power consumption.
Fig. 7.2.6 W90N745 system clock generation diagram
- 39 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
IDLE MODE
If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source
will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock
to cache controller and ARM are stopped. W90N745 will exit idle state when nIRQ or nFIQ from any
peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also
be forced to enter idle state if both MIDLE and IDLE bits are set. Software must switch SDRAM into
self-refresh mode before forcing memory to enter idle mode.
IDLE Period
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
HCLK
(memc)
Case1. IDLE=1, PD=0, MIDLE=0
Fig. 7.2.7 Clock management for system idle mode
IDLE Period
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
HCLK
(memc)
Case2. IDLE=1, PD=0, MIDLE=1
Fig. 7.2.8 Clock management for system and memory idle mode
- 40 -
W90N745CD/W90N745CDG
Power Down Mode
This mode provides the minimum power consumption. When the W90N745 system is not working or
waiting an external event, software can write PD bit “1” to turn off all the clocks includes system crystal
oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode
since the clock source is stopped. W90N745 will exit power down state when nIRQ/nFIQ is detected.
W90N745 provides external interrupt nIRQ[1:0], keypad, and USB device interfaces to wakeup the
system clock.
65536 clocks
EXTAL
HCLK
idle _state
pd_state
wake up by pheripheral's
interrupts
HCLK
(cache)
Case3. IDLE=0, PD=1, MIDLE=0
Fig 7.2.9 Clock management for system power down mode and wake up
- 41 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.2.7
Power-On Setting
After power on reset, there are eight Power-On setting pins to configure W90N745 system configuration.
POWER-ON SETTING
PIN
Internal System Clock Select
Little/Big Endian Mode Select
Boot ROM/FLASH Data Bus Width
D15
D14
D [13:12]
Default: Pull-Down in Normal Operation
D9
Default: Pull-Up in Normal Operation
D8
D15 pin：Internal System Clock Select
If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock.
If pin D15 is pull-up, the PLL output clock is used as internal system clock.
D14 pin：Little/Big Endian Mode Select
If pin D14 is pull-down, the external memory format is Big Endian mode.
If pin D14 is pull-up, the external memory format is Little Endian mode.
D [13:12] ： Boot ROM/FLASH Data Bus Width
D [13:12]
Pull-down
Pull-down
Pull-up
Pull-up
BUS WIDTH
Pull-down
Pull-up
Pull-down
Pull-up
8-bit
16-bit
RESERVED
RESERVED
- 42 -
W90N745CD/W90N745CDG
7.2.8
System Manager Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
PDID
0xFFF0_0000
R
Product Identifier Register
0xX090_0745
ARBCON
0xFFF0_0004
R/W
Arbitration Control Register
0x0000_0000
PLLCON0
0xFFF0_0008
R/W
PLL Control Register 0
0x0000_2F01
CLKSEL
0xFFF0_000C
R/W
Clock Select Register
0x1FFF_3FX8
PLLCON1
0xFFF0_0010
R/W
PLL Control Register 1
0x0001_0000
I²SCKCON
0xFFF0_0014
R/W
Audio I²S Clock Control Register
0x0000_0000
IRQWAKECON 0xFFF0_0020
R/W
IRQ Wakeup Control register
0x0000_0000
IRQWAKEFLAG 0xFFFF_0024
R/W
IRQ wakeup Flag Register
0x0000_0000
PMCON
0xFFF0_0028
R/W
Power Manager Control Register
0x0000_0000
USBTxrCON
0xFFF0_0030
R/W
USB Transceiver Control Register
0x0000_0000
- 43 -
RESET VALUE
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Product Identifier Register （PDID）
This register is read only and lets software can use it to recognize certain characteristics of the chip ID
and the version number.
REGISTER
ADDRESS
R/W
PDID
0xFFF0_0000
R
31
30
29
DESCRIPTION
Product Identifier Register
28
27
PACKAGE
23
22
RESET VALUE
26
0xX090_0745
25
24
18
17
16
10
9
8
2
1
0
VERSION
21
20
19
CHPID
15
14
13
12
11
CHPID
7
6
5
4
3
CHPID
BITS
DESCRIPTION
Package Type Select
[31:30]
PACKAGE
[29:24]
VERSION
[23:0]
CHIPID
These two bits are power-on setting latched from pin D[9:8]
Package [31:30]
0
1
Package Type
128-pin Package
Version of chip
The chip identifier of W90N745 is 0x090.0745
- 44 -
W90N745CD/W90N745CDG
Arbitration Control Register (ARBCON)
REGISTER
ADDRESS
R/W
DESCRIPTION
ARBCON
0xFFF0_0004
R/W
Arbitration Control Register
31
30
29
28
23
22
21
20
27
RESET VALUE
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
IPACT
IPEN
PRTMOD
RESERVED
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
BITS
DESCRIPTION
[31:3]
RESERVED
[2]
IPACT
[1]
IPEN
[0]
PRTMOD
Interrupt priority active.
When IPEN=”1”, this bit will be set when the ARM core has an
unmasked interrupt request. This bit is available only when the
PRTMOD=0.
Interrupt priority enable bit
0 = the ARM core has the lowest priority.
1 = enable to raise the ARM core priority to second
This bit is available only when the PRTMOD=0.
Priority mode select
0 = Fixed Priority Mode (default)
1 = Rotate Priority Mode
- 45 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PLL Control Register0 （PLLCON0）
W90N745 provides two clock generation options – crystal and oscillator. The external clock via
EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the
PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock
for the internal system clock, D15 pin must be pull-up.
REGISTER
ADDRESS
R/W
PLLCON
0xFFF0_0008
R/W
31
30
29
DESCRIPTION
RESET VALUE
PLL Control Register
28
27
0x0000_2F01
26
25
24
18
17
16
RESERVED
23
22
21
20
19
RESERVED
15
14
13
PWDEN
12
11
10
9
8
3
2
1
0
FBDV
7
FBDV
6
5
4
OTDV
INDV
BITS
DESCRIPTION
[31:17]
RESERVED
[16]
PWDEN
[15:7]
FBDV
Power down mode enable
0 = PLL is in normal mode (default)
1 = PLL is in power down mode
PLL VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL.
PLL output clock divider
OTDV [6:5]
[6:5]
OTDV
[4:0]
INDV
0
0
1
1
0
1
0
1
DIVIDED BY
1
2
2
4
PLL input clock divider
Input divider divides the input reference clock into the PLL.
- 46 -
W90N745CD/W90N745CDG
EXTAL
USBCKS
FIN
INDV[4:0]
PFD
FBDV[8:0]
GP0
PLL
Input Divider
(NR)
Charge
Pump
VCO
48MHz
Gen
Output 480MHz
Divider
FOUT
(NO)
Feedback
Divider
(NF)
Clock
Divider
&
Selector
1
0
0
1
USB
Module
Internal
System
Clock
ECLKS
CLKS[2:0]
OTDV[1:0]
Fig 7.2.8.1 System PLL block diagram
The formula of output clock of PLL is:
FOUT = FIN ∗
NF 1
∗
NR NO
FOUT：Output clock of Output Divider
FIN：External clock into the Input Divider
NR：Input divider value (NR = INDV + 2)
NF：Feedback divider value (NF = FBDV + 2)
NO：Output divider value (NO = OTDV)
- 47 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Clock Select Register (CLKSEL)
REGISTER
ADDRESS
R/W
CLKSEL
0xFFF0_000C
R/W
31
30
DESCRIPTION
RESET VALUE
Clock Select Register
0x1FFF_7FX8
29
28
27
26
23
RESERVED
22
21
PS2
20
KPI
19
RESERVED
18
17
UART3
UART2
UART1
I2C1
I2C0
15
14
13
12
11
USBCKS
7
USBD
6
GDMA
5
USBH
TIMER
UART
BITS
[31:29]
RESERVE
D
10
RESERVED
4
3
ECLKS
EMC
2
CLKS
DESCRIPTION
RESERVED
PS2 controller clock enable bit
[28]
PS2
0 = Disable PS2 controller clock
1 = Enable PS2 controller clock
Keypad controller clock enable bit
[27]
KPI
0 = Disable keypad controller clock
1 = Enable keypad controller clock
[26]
RESERVED
-
[25]
RESERVED
USI controller clock enable bit
[24]
USI
0 = Disable USI controller clock
1 = Enable USI controller clock
UART3 controller clock enable bit
[23]
UART3
0 = Disable UART3 controller clock
1 = Enable UART3 controller clock
UART2 controller clock enable bit
[22]
UART2
0 = Disable UART2 controller clock
1 = Enable UART2 controller clock
UART1 controller clock enable bit
[21]
UART1
0 = Disable UART1 controller clock
1 = Enable UART1 controller clock
- 48 -
25
24
SSP
16
PWM
AC97
9
8
RESERVED
1
WDT
0
RESET
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
2
I C1 controller clock enable bit
[20]
2
I C1
0 = Disable I2C1 controller clock
1 = Enable I2C1 controller clock
I2C0 controller clock enable bit
[19]
I2C0
0 = Disable I2C0 controller clock
1 = Enable I2C0 controller clock
[18]
RESERVED
PWM controller clock enable bit
[17]
PWM
0 = Disable PWM controller clock
1 = Enable PWM controller clock
Audio Controller clock enable bit
[16]
AC97
0 = Disable AC97 controller clock
1 = Enable AC97 controller clock
USB host/device 48MHz clock source Select bit
[15]
USBCKS
0 = USB clock 48MHz input from internal PLL (480MHz/10)
1 = USB clock 48MHz input from external GPIO0 pin, this pin
direction must set to input.
USB device clock enable bit
[14]
USBD
0 = Disable USB device controller clock
1 = Enable USB device controller clock
GDMA controller clock enable bit
[13]
GDMA
0 = Disable GDMA clock
1 = Enable GDMA clock
[12]
RESERVED
-
[11]
RESERVED
EMC controller clock enable bit
[10]
EMC
0 = Disable EMC controller clock
1 = Enable EMC controller clock
[9]
RESERVED
WDT clock enable bit
[8]
WDT
0 = Disable WDT counting clock
1 = Enable WDT counting clock
- 49 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
USB host clock enable bit
[7]
USBH
0 = Disable USB host controller clock
1 = Enable USB host controller clock
Timer clock enable bit
[6]
TIMER
0 = Disable timer clock
1 = Enable timer clock
UART0 controller clock enable bit
[5]
UART0
0 = Disable UART0 controller clock
1 = Enable UART0 controller clock
External clock select
0 = External clock from EXTAL pin is used as system clock
[4]
ECLKS
1 = PLL output clock is used as system clock
After power on reset, the content of ECLKS is the Power-On
Setting value. You can program this bit to change the system clock
source.
PLL output clock select
CLKS [3:1]
[3:1]
CLKS
System clock
0
0
0
58.594 KHz*
0
0
1
24 MHz
0
1
0
48 MHz
0
1
1
60 MHz
1
0
0
80 MHz
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
RESERVED
Note:
1. This values are based on PLL output(FOUT) is 480MHz.
2. When 24Mhz ~ 80MHz is selected, the ECLKS bit must be set to
1.
3. About 58.594KHz setting, two steps are needed. First, clear
ECLKS bit, and then clear CLKS.
Software Reset bit
[0]
RESET
This is a software reset control bit. Set logic 1 to generate an
internal reset pulse. This bit is auto-clear to logic 0 at the end of
the reset pulse.
- 50 -
W90N745CD/W90N745CDG
PLL Control Register 1（PLLCON1）
W90N745 provides extra PLL to provide 12.288/16.934 MHz clock source to Audio Controller. It uses the
same 15MHz crystal clock input source with system PLL mentioned above.
REGISTER
ADDRESS
R/W
PLLCON1
0xFFF0_0010
R/W
31
30
29
DESCRIPTION
RESET VALUE
PLL Control Register 1
28
27
0x0001_0000
26
25
24
18
17
16
RESERVED
23
22
21
20
19
RESERVED
15
14
13
PWDEN1
12
11
10
9
8
3
2
1
0
FBDV1
7
FBDV1
6
5
4
OTDV1
INDV1
BITS
DESCRIPTION
[31:17]
RESERVED
[16]
PWDEN1
[15:7]
FBDV1
[6:5]
OTDV1
[4:0]
INDV1
PLL1 power down enable
0 = PLL1 is in normal mode
1 = PLL1 is in power down mode (default)
PLL1 VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL1.
PLL1 output clock divider
OTDV1 [6:5]
Divided by
0
0
1
0
1
2
1
0
2
1
1
4
PLL1 input clock divider
Input divider divides the input reference clock into the PLL1.
- 51 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
EXTAL
FIN
INDV1[4:0]
PFD
FBDV1[8:0]
PLL1
Input Divider
(NR)
Charge
Pump
VCO
Output
480MHz
Divider
FOUT
(NO)
Feedback
Divider
(NF)
OTDV1[1:0]
Fig 7.2.8.2 Audio PLL block diagram
The formula of output clock of PLL is:
FOUT = FIN ∗
NF 1
∗
NR NO
FOUT：Output clock of Output Divider
FIN：External clock into the Input Divider
NR：Input divider value (NR = INDV1 + 2)
NF：Feedback divider value (NF = FBDV1 + 2)
NO：Output divider value (NO = OTDV1)
- 52 -
to Audio Controller
W90N745CD/W90N745CDG
I²S Clock Control Register (I²SCKCON)
REGISTER
ADDRESS
R/W
I²SCKCON
0xFFF0_0014
R/W
31
30
29
23
22
21
15
14
13
7
6
5
RESET VALUE
I²S PLL clock Control Register
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
PRESCALE
BITS
[31:9]
DESCRIPTION
0x0000_0000
26
25
24
18
17
16
10
9
2
1
8
I²SPLLEN
0
DESCRIPTION
RESERVED
I²S PLL clock source enable
[8]
I²SPLLEN
Set this bit will enable PLL1 clock output to audio I²S clock input.
1 = Enable PLL1 clock source for audio I²S
0 = Disable PLL1 clock source for audio I²S
[7:0]
PRESCALE
The PLL1 is used by I²S, if in use, software can using this
prescaler to generate an appropriate clock nearly 12.288M or
16.934M. The clock is generated as below, and if PRESCALE =0,
the PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO =
PLL_FOUT/(PRESCALE +1)”
- 53 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
IRQ Wakeup Control Register (IRQWAKECON)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
IRQWAKECON
0xFFF0_0020
R/W
IRQ Wakeup Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RESERVED
23
22
21
20
RESERVED
15
14
13
12
RESERVED
7
6
RESERVED
5
RESERVED
IRQWAKEUPPOL
BITS
[31:6]
4
DESCRIPTION
RESERVED
nIRQ1 wake up polarity
[5]
IRQWAKEUPPOL[1]
1 = nIRQ1 is high level wake up
0 = nIRQ1 is low level wake up
nIRQ0 wake up polarity
[4]
IRQWAKEUPPOL[0]
1 = nIRQ0 is high level wake up
0 = nIRQ0 is low level wake up
[3:2]
RESERVED
nIRQ1 wake up enable bit
[1]
IRQWAKEUPEN[1]
1 = nIRQ1 wake up enable
0 = nIRQ1 wake up disable
nIRQ0 wake up enable bit
[0]
IRQWAKEUPEN[0]
1 = nIRQ0 wake up enable
0 = nIRQ0 wake up disable
- 54 -
IRQWAKEUPEN
W90N745CD/W90N745CDG
IRQ Wakeup Flag Register (IRQWAKEFLAG)
REGISTER
ADDRESS
IRQWAKEFLAG 0xFFF0_0024
31
30
29
R/W
DESCRIPTION
RESET VALUE
R/W
IRQ Wakeup Flag Register
0x0000_0000
28
27
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
IRQWAKEFLAG
This register is used to record the wakeup event, after clock recovery, software should check these flags
to identify which nIRQ is used to wakeup the system. And clear the flags in IRQ interrupt sevice routine.
BITS
[31:2]
DESCRIPTION
RESERVED
nIRQ1 wake up flag
[1]
IRQWAKEFLAG[1]
1 = chip is waked up by nIRQ1
0 = no active
nIRQ0 wake up flag
[0]
IRQWAKEFLAG[0]
1 = chip is waked up by nIRQ0
0 = no active
- 55 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Power Management Control Register (PMCON)
REGISTER
ADDRESS
R/W
PMCON
0xFFF0_0028
R/W
31
30
29
23
22
21
15
14
13
7
6
5
RESERVED
DESCRIPTION
Power Management Control Register
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
BITS
[31:3]
RESET VALUE
0x0000_0000
26
25
24
18
17
16
10
9
8
2
MIDLE
1
PD
0
IDLE
DESCRIPTION
RESERVED
Memory controller IDLE enable
Setting both MIDLE and IDLE bits HIGH will let memory controller
enter IDLE mode, the clock source of memory controller will be halted
while ARM CORE enter IDLE mode.
[2]
MIDLE
1=memory controller will be forced into IDLE mode, (clock of memory
controller will be halted), when IDLE bit is set.
0 = memory controller still active when IDLE bit is set.
NOTE: Software must let SDRAM enter self-refresh mode before
enable this function because SDRAM MCLK will be stopped.
Power down enable
[1]
PD
Setting this bit HIGH will let W90N745 enter power saving mode. The
clock source 15M crystal oscillator and PLLs are stopped to generate
clock. User can use nIRQ[3:0], keypad and external RESET to wakeup
W90N745.
1 = Enable power down
0 = Disable
IDLE mode enable
[0]
IDLE
Setting this bit HIGH will let ARM Core enter power saving mode. The
peripherals can still keep working if the clock enable bit in CLKSEL is
set. Any nIRQ or nFIQ to ARM Core will let ARM CORE to exit IDLE
state.
1 = IDLE mode
0 = Disable
- 56 -
W90N745CD/W90N745CDG
USB Transceiver Control Register (USBTXRCON)
REGISTER
ADDRESS
R/W
USBTXRCO
N
0xFFF0_0030
R/W
31
30
29
DESCRIPTION
RESET VALUE
USB Transceiver Control Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
BITS
[31:1]
USBHnD
DESCRIPTION
RESERVED
USBHnD[0]: USB transceiver control
[0]
USBHnD
There are two USB1.1 built-in transceivers for data transmission. One
is dedicated for USB host and the other is shared with USB device.
Software can program this bit to switch the transceiver path.
1 = HOST
0 = Device
- 57 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.3
7.3.1
External Bus Interface
EBI Overview
W90N745 supports External Bus Interface (EBI), which controls the access to the external memory
(ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one
ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 21 bits. It
supports 8-bit, 16-bit external data bus width for each bank.
The EBI has the following functions：
SDRAM controller
EBI control register
ROM/FLASH interface
External I/O interface
External bus mastership
7.3.2
SDRAM Controller
The SDRAM controller module within W90N745 contains configuration registers 、 timing control
registers、common control register and other logic to provide 8、16 bits SDRAM interface with a single
8、16 bits SDRAM device or two 8-bit devices wired to give a 16-bit data path. The maximum size of
each bank is 64M bytes, and maximum memory size can span up to 128MB.
The SDRAM controller has the following features：
Supports up to 2 external SDRAM banks
Maximum size of each bank is 64M bytes
8、16-bit data interface
Programmable CAS Latency： 1、2 and 3
Fixed Burst Length： 1
Sequential burst type
Auto Refresh Mode and Self Refresh Mode
Adjustable Refresh Rate
Power up sequence
- 58 -
W90N745CD/W90N745CDG
7.3.2.1. SDRAM Components Supported
Table 7.3.2.1 SDRAM supported by W90N745
SIZE
16M bits
64M bits
128M bits
256M bits
TYPE
BANKS
ROW ADDRESSING
COLUMN ADDRESSING
2Mx8
2
RA0~RA10
CA0~CA8
1Mx16
2
RA0~RA10
CA0~CA7
8Mx8
4
RA0~RA11
CA0~CA8
4Mx16
4
RA0~RA11
CA0~CA7
16Mx8
4
RA0~RA11
CA0~CA9
8Mx16
4
RA0~RA11
CA0~CA8
32Mx8
4
RA0~RA12
CA0~CA9
16Mx16
4
RA0~RA12
CA0~CA8
AHB Bus Address Mapping to SDRAM Bus
Note:
* indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used;
The HADDR prefixes have been omitted on the following tables.
A14 ~ A0 are the Address pins of the W90N745 EBI interface;
A14 and A13 are the Bank Select Signals of SDRAM.
- 59 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
SDRAM Data Bus Width: 16-bit
A14
Total
Type
RxC
R/C
16M
2Mx8
11x9
R
**
C
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
10
**
10*
21
20
19
18
17
16
15
14
13
12
11
**
10
**
10*
AP
24*
9
8
7
6
5
4
3
2
1
**
9
**
9*
10
20
19
18
17
16
15
14
13
12
11
(BS1) (BS0)
16M
1Mx16
11x8
R
C
**
9
**
9*
AP
24*
9*
8
7
6
5
4
3
2
1
64M
8Mx8
12x9
R
10
11
10*
22
21
20
19
18
17
16
15
14
13
12
23
C
10
11
10*
22*
AP
24*
9
8
7
6
5
4
3
2
1
R
10
9
10*
22
21
20
19
18
17
16
15
14
13
12
11
C
10
9
10*
22*
AP
24* 23*
8
7
6
5
4
3
2
1
10
11
10*
22
21
20
18
17
16
15
14
13
12
23
64M
4Mx16
12x8
128M
16Mx8 12x10
R
C
10
11
10*
22*
AP
24
9
8
7
6
5
4
3
2
1
128M
8Mx16
R
10
11
10*
22
21
20
19
18
17
16
15
14
13
12
23
C
10
11
10*
22*
AP
24*
9
8
7
6
5
4
3
2
1
256M* 32Mx8 13x10
R
10
11
23
22
21
20
19
18
17
16
15
14
13
12
24
C
10
11
23*
22*
AP
25*
9
8
7
6
5
4
3
2
1
256M 16Mx16 13x9
R
10
11
23
22
21
20
19
18
17
16
15
14
13
12
24
C
10
11
23*
22*
AP
25*
9
8
7
6
5
4
3
2
1
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12x9
19
SDRAM Data Bus Width: 8-bit
A14
A13
Total
Type
RxC
R/C
16M
2Mx8
11x9
R
**
9
**
9*
20
19
18
17
16
15
14
13
12
11
10
C
**
9
**
9*
AP
23*
8
7
6
5
4
3
2
1
0
R
9
10
9*
21
20
19
18
17
16
15
14
13
12
11
22
C
9
10
9*
21*
AP
23*
8
7
6
5
4
3
2
1
1
R
9
10
9*
21
20
19
18
17
16
15
14
13
12
11
22
C
9
10
9*
21*
AP
23
8
7
6
5
4
3
2
1
0
R
9
10
22
21
20
19
18
17
16
15
14
13
12
11
23
C
9
10
22*
21*
AP
24
8
7
6
5
4
3
2
1
0
64M
128M
256M
8Mx8
12x9
16Mx8 12x10
32Mx8 13x10
(BS1) (BS0)
- 60 -
W90N745CD/W90N745CDG
7.3.2.2. SDRAM Power Up Sequence
The SDRAM must be initialized predefined manner after power on.W90N745 SDRAM Controller
automatically executes the commands needed for initialion and set the mode register of each bank to
default value. The default value is：
— Burst Length = 1
— Burst Type
= Sequential (fixed)
— CAS Latency = 2
— Write Burst Length = Burst (fixed)
The value of mode register can be changed after power up sequence by setting the value of
corresponding bank’s configuration register “LENGTH” and “LATENCY” bits and set the MRSET bit
enable to execute the Mode Register Set command.
7.3.2.3. SDRAM Interface
A [ 1 0 :0 ]
A [ 2 0 :0 ]
A [ 1 0 :0 ]
A13
BS0
A14
BS1
D Q [ [ 1 5 :0 ]
D [ 1 5 :0 ]
M CLK
CLK
MCKE
CKE
nSCS0
n S C S [ 1 :0 ]
nCS
nSRAS
nRAS
nSCAS
nCAS
nSW E
nW E
n S D Q M [ 1 :0 ]
n S D Q M [ 1 :0 ]
D Q M [ 1 :0 ]
SDRAM
32M b 512Kx4x16
W 90N745
Fig 7.3.1 SDRAM Interface
- 61 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.3.3
EBI Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
EBICON
0xFFF0_1000
R/W EBI control register
0x0001_0000
ROMCON
0xFFF0_1004
R/W ROM/FLASH control register
0x0000_0XFC
SDCONF0
0xFFF0_1008
R/W SDRAM bank 0 configuration register
0x0000_0800
SDCONF1
0xFFF0_100C
R/W SDRAM bank 1 configuration register
0x0000_0800
SDTIME0
0xFFF0_1010
R/W SDRAM bank 0 timing control register
0x0000_0000
SDTIME1
0xFFF0_1014
R/W SDRAM bank 1 timing control register
0x0000_0000
EXT0CON
0xFFF0_1018
R/W External I/O 0 control register
0x0000_0000
EXT1CON
0xFFF0_101C
R/W External I/O 1 control register
0x0000_0000
EXT2CON
0xFFF0_1020
R/W External I/O 2 control register
0x0000_0000
EXT3CON
0xFFF0_1024
R/W External I/O 3 control register
0x0000_0000
CKSKEW
0xFFF0_1F00
R/W Clock skew control register (for testing)
0xXXXX_0038
- 62 -
RESET VALUE
W90N745CD/W90N745CDG
EBI Control Register (EBICON)
REGISTER
ADDRESS
EBICON
0xFFF0_1000
31
30
R/W
DESCRIPTION
R/W EBI control register
29
28
RESERVED
23
22
21
14
13
0x0001_0000
27
26
25
24
EXBE3
EXBE2
EXBE1
EXBE0
19
18
17
16
REFEN
REFMOD
CLKEN
11
10
9
8
3
2
1
0
20
RESERVED
15
RESET VALUE
12
REFRAT
7
6
5
4
REFRAT
BITS
[31:27]
WAITVT
LITTLE
DESCRIPTION
RESERVED
External IO bank 3 byte enable
[27]
EXBE3
This function is used for some devices that with high and low bytes
enable signals to control which byte will be write or mask data output
when read. For this kind device, software can set this bit HIGH to
implement this function. Detail pin interconnection is showed as Fig7.3.8.
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM.
0 = nWBE[1:0] pin is byte write strobe signal.
External IO bank 2 byte enable
The bit function description is the same as EXBE3 above.
[26]
EXBE2
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM.
0 = nWBE[1:0] pin is byte write strobe signal.
External IO bank 1 byte enable
The bit function description is the same as EXBE3 above.
[25]
EXBE1
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM
0 = nWBE[1:0] pin is byte write strobe signal
- 63 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
External IO bank 0 byte enable
This bit function description is the same as EXBE3 above.
[24]
EXBE0
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM
0 = nWBE[1:0] pin is byte write strobe signal
[23:19]
RESERVED
Enable SDRAM refresh cycle for SDRAM bank0 & bank1
[18]
REFEN
This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is
according to REFRAT bits.
1 = enable refresh function
0 = disable refresh function
Refresh mode of SDRAM for SDRAM bank
Defines the refresh mode type of external SDRAM bank
Software can write this bit “1” to force SDRAM enter self-refresh mode.
[17]
REFMOD
0 = Auto refresh mode
1 = Self refresh mode
NOTE: If any read/write to SDRAM occurs then this bit will be cleared to
“0” by hardware automatically and SDRAM will enters auto-refresh
mode.
Clock enable for SDRAM
[16]
CLKEN
Enables the SDRAM clock enable (CKE) control signal
0 = Disable (power down mode)
1 = Enable （Default）
Refresh count value for SDRAM
[15:3]
REFRAT
The SDRAM Controller automatically provides an auto refresh cycle for
every refresh period programmed into the REFRAT bits when the
REFEN bit of each bank is set
The refresh period is calculated as period =
- 64 -
value
fMCLK
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
Valid time of nWAIT signal
W90N745 recognizes the nWAIT signal at the next “nth” MCLK
rising edge after the nOE or nWBE active cycle. WAITVT bits
determine the n.
[2:1]
WAITVT
WAITVT [2:1]
0
0
1
1
0
1
0
1
nth MCLK
1
2
3
4
Little Endian mode
[0]
LITTLE
After power on reset, the content of LITTLE is the Power-On Setting
value from D14 pin. If pin D14 is pull-down, the external memory format
is Big Endian mode. If pin D14 is pull-up, the external memory format is
Little Endian mode. For more detail, refer to Power-On Setting of System
Manager.
NOTE: This bit is read only.
- 65 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
ROM/Flash Control Register （ROMCON）
REGISTER
ADDRESS
ROMCON
0xFFF0_1004
31
R/W
30
DESCRIPTION
RESET VALUE
R/W ROM/FLASH control register
0x0000_0XFC
29
28
27
26
25
24
18
17
16
BASADDR
23
22
21
20
19
BASADDR
15
14
SIZE
13
12
11
10
RESERVED
7
6
9
8
1
0
tPA
5
4
3
tACC
2
BTSIZE
BITS
PGMODE
DESCRIPTION
Base address pointer of ROM/Flash bank
[31:19]
BASADDR
The start address is calculated as ROM/Flash bank base pointer << 18.
The base address pointer together with the “SIZE” bits constitutes the
whole address range of each bank.
The size of ROM/FLASH memory
SIZE [10:8]
[18:16]
[15:12]
SIZE
RESERVED
Byte
0
0
0
256K
0
0
1
512K
0
1
0
1M
0
1
1
2M
1
0
0
4M
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
RESERVED
-
- 66 -
W90N745CD/W90N745CDG
Continued.
BITS
[11:8]
[7:4]
DESCRIPTION
tPA
Page mode access cycle time
tPA[11:8]
MCLK
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
1
1
1
1
1
1
1
tPA[11:8]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
tACC
Access cycle time
tACC[11:8]
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
tACC[11:8]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
MCLK
1
2
3
4
5
6
7
8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MCLK
10
12
14
16
18
20
22
24
MCLK
10
12
14
16
18
20
22
24
Boot ROM/FLASH data bus width
This ROM/Flash bank is designed for a boot ROM. BASADDR bits
determine its start address. The external data bus width is determined by
the data bus signals D [13:12] power-on setting.
[3:2]
[1:0]
BTSIZE
PGMODE
BTSIZE [3:2]
0
0
0
1
1
0
1
1
Bus Width
8-bit
16-bit
RESERVED
RESERVED
Page mode configuration
PGMODE [1:0]
0
0
0
1
1
0
1
1
- 67 -
D [13:12]
Bus Width
Pull-down Pull-down
8-bit
Pull-down Pull-up
16-bit
Pull-up Pull-down RESERVED
Pull-up
Pull-up
RESERVED
Mode
Normal ROM
4 word page
8 word page
16 word page
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Fig7.3.2 ROM/FLASH Read Operation Timing
Fig 7.3.3 ROM/FLASH Page Read Operation Timing
- 68 -
W90N745CD/W90N745CDG
Configuration Registers（SDCONF0/1）
The configuration registers enable software to set a number of operating parameters for the SDRAM
controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1
respectively. Each bank can have a different configuration.
REGISTER
ADDRESS
SDCONF0
SDCONF1
0xFFF0_1008
0xFFF0_100C
31
30
R/W
DESCRIPTION
RESET VALUE
R/W SDRAM bank 0 configuration register
R/W SDRAM bank 1 configuration register
29
28
0x0000_0800
0x0000_0800
27
26
25
24
19
18
17
16
BASADDR
23
22
21
20
BASADDR
15
14
13
MRSET
RESERVED
AUTOPR
7
6
5
COMPBK
DBWD
BITS
RESERVED
12
11
10
LATENCY
4
9
8
RESERVED
3
COLUMN
2
1
0
SIZE
DESCRIPTION
[31:19]
BASADDR
[18:16]
RESERVED
[15]
MRSET
[14]
RESERVED
[13]
AUTOPR
[12:11]
LATENCY
Base address pointer of SDRAM bank 0/1
The start address is calculated as SDRAM bank 0/1 base pointer
<< 18. The SDRAM base address pointer together with the “SIZE”
bits constitutes the whole address range of each SDRAM bank.
SDRAM Mode register set command for SDRAM bank 0/1
This bit set will issue a mode register set command to SDRAM.
Auto pre-charge mode of SDRAM for SDRAM bank 0/1
Enable the auto pre-charge function of external SDRAM bank 0/1
0 = Auto pre-charge
1 = No auto pre-charge
The CAS Latency of SDRAM bank 0/1
Defines the CAS latency of external SDRAM bank 0/1
LATENCY [12:11]
MCLK
0
0
1
0
1
2
1
0
3
1
1
REVERSED
- 69 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
[10:8]
RESERVED
[7]
COMPBK
[6:5]
DBWD
Number of component bank in SDRAM bank 0/1
Indicates the number of component bank (2 or 4 banks) in external
SDRAM bank 0/1.
0 = 2 banks
1 = 4 banks
Data bus width for SDRAM bank 0/1
Indicates the external data bus width connect with SDRAM bank 0/1
If DBWD = 00, the assigned SDRAM access signal is not generated
i.e. disable.
DBWD [6:5]
Bits
0
0
Bank disable
0
1
8-bit (byte)
1
0
16-bit (half-word)
1
1
REVERSED
Number of column address bits in SDRAM bank 0/1
Indicates the number of column address bits in external SDRAM
bank 0/1.
COLUMN [4:3]
[4:3]
COLUMN
Bits
0
0
8
0
1
9
1
0
10
1
1
REVERSED
Size of SDRAM bank 0/1
Indicates the memory size of external SDRAM bank 0/1
SIZE [2:0]
Size of SDRAM （Byte）
[2:0]
SIZE
0
0
0
Bank disable
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
2M
4M
8M
16M
32M
64M
REVERSED
- 70 -
W90N745CD/W90N745CDG
Timing Control Registers （SDTIME0/1）
W90N745 offers the flexible timing control registers to control the generation and processing of the
control signals and can achieve you use different speed of SDRAM
REGISTER
ADDRESS
SDTIME0
0xFFF0_1010
R/W SDRAM bank 0 timing control register
0x0000_0000
SDTIME1
0xFFF0_1014
R/W SDRAM bank 1 timing control register
0x0000_0000
31
30
R/W
29
DESCRIPTION
28
27
RESET VALUE
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
tRDL
[10:8]
[7:6]
3
2
tRP
BITS
[31:11]
tRCD
1
0
tRAS
DESCRIPTION
RESERVED
-
tRCD
SDRAM bank 0/1, /RAS to /CAS delay
tRCD [10:8]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
tRDL
SDRAM bank 0/1, Last data in to pre-charge command
tRDL [7:6]
MCLK
0
0
1
0
1
2
1
0
3
1
1
4
- 71 -
MCLK
1
2
3
4
5
6
7
8
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
[5:3]
[2:0]
DESCRIPTION
tRP
tRAS
SDRAM bank 0/1, Row pre-charge time
tRP [5:3]
MCLK
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
SDRAM bank 0/1, Row active time
tRAS [2:0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
- 72 -
MCLK
1
2
3
4
5
6
7
8
W90N745CD/W90N745CDG
Fig 7.3.4 Access timing 1 of SDRAM
Fig 7.3.5 Access timing 2 of SDRAM
- 73 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
External I/O Control Registers（EXT0CON – EXT3CON）
The W90N745 supports an external device control without glue logic. It is very cost effective because
address decoding and control signals timing logic are not needed. Using these control registers you can
configure special external I/O devices for providing the low cost external devices control solution.
REGISTER
ADDRESS
EXT0CON
0xFFF0_1018
R/W External I/O 0 control register
0x0000_0000
EXT1CON
0xFFF0_101C
R/W External I/O 1 control register
0x0000_0000
EXT2CON
0xFFF0_1020
R/W External I/O 2 control register
0x0000_0000
EXT3CON
0xFFF0_1024
R/W External I/O 3 control register
0x0000_0000
31
30
R/W
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
BASADDR
23
22
21
20
BASADDR
15
14
13
ADRS
SIZE
12
11
tACC
7
6
5
BITS
[18:16]
9
8
tCOH
4
3
tACS
[31:11]
10
2
1
tCOS
0
DBWD
DESCRIPTION
BASADDR
SIZE
Base address pointer of external I/O bank 0~3
The start address of each external I/O bank is calculated as “BASADDR”
base pointer << 18.
Each external I/O bank base address pointer together with the “SIZE” bits
constitutes the whole address range of each external I/O bank.
The size of the external I/O bank 0~3
SIZE [18:16]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
- 74 -
Byte
256K
512K
1M
2M
4M
8M
REVERSED
REVERSED
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
Address bus alignment for external I/O bank 0~3
[15]
ADRS
When ADRS is set, external address (A20~A0) bus is alignment to byte
address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is
AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting.
Access cycles of external I/O bank 0~3
This parameter means nWE, nWBE and nOE active time clock. Detail timing
diagram please refer to Fig. 7.3.6 and 7.3.7
tACC[14:11]
[14:11]
tACC
MCLK
tACC[14:11]
MCLK
0
0
0
0
Reversed
1
0
0
0
9
0
0
0
1
1
1
0
0
1
11
0
0
1
0
2
1
0
1
0
13
0
0
1
1
3
1
0
1
1
15
0
1
0
0
4
1
1
0
0
17
0
1
0
1
5
1
1
0
1
19
0
1
1
0
6
1
1
1
0
21
0
1
1
1
7
1
1
1
1
23
Chip selection hold time of external I/O bank 0~3
This parameters control nWBE and nOE hold time. Detail timing diagram
please refer to Fig. 7.3.6 and 7.3.7
[10:8]
tCOH
0
0
0
0
1
1
1
1
tCOH [10:8]
0
0
1
1
0
0
1
1
- 75 -
0
1
0
1
0
1
0
1
MCLK
0
1
2
3
4
5
6
7
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
Address set-up before nECS for external I/O bank 0~3
[7:5]
tACS
0
0
0
0
1
1
1
1
tACS [7:5]
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MCLK
0
1
2
3
4
5
6
7
Chip selection set-up time of external I/O bank 0~3
When ROM/Flash memory bank is configured, the access to its bank
stretches chip selection time before the nOE or new signal is activated.
[4:2]
tCOS
0
0
0
0
1
1
1
1
tCOS [4:2]
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MCLK
0
1
2
3
4
5
6
7
Programmable data bus width for external I/O bank 0~3
[1:0]
DBWD
DBWD [1:0]
0
0
0
1
1
0
1
1
- 76 -
Width of Data Bus
Disable bus
8-bit
16-bit
RESERVED
W90N745CD/W90N745CDG
Fig 7.3.6 External I/O write operation timing
Fig 7.3.7 External I/O read operation timing
- 77 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Fig. 7.3.8 External IO bank with 16-bit SRAM
Clock Skew Control Register （CKSKEW）
REGISTER
ADDRESS
R/W
CKSKEW
0xFFF0_1F00
R/W
31
30
29
DESCRIPTION
RESET VALUE
Clock skew control register
28
27
0xXXXX_0018
26
25
24
18
17
16
10
9
8
DLH_CLK_REF
23
22
21
20
19
DLH_CLK_REF
15
14
13
12
11
RESVERED
7
6
5
4
SWPON
3
DLH_CLK_SKEW
2
MCLK_O_D
- 78 -
1
0
W90N745CD/W90N745CDG
BITS
DESCRIPTION
Latch DLH_CLK clock tree by HCLK positive edge
[31:16]
DLH_CLK_REF
[15:9]
RESERVED
The SDRAM MCLK is generated by inserting a delay (XOR2) chain in
HCLK positive or negedge edge to adjust the MCLK skew. So software
can read these bits to expore MCLK and HCLK relationship. [31:24] is
used for positive edge and [23:16] is for negedge edge.
SDRAM Initialization by Software
[8]
SWPON
Set this bit “1” will issue a SDRAM power on default setting command
sequence like system power on, this bit will be auto-clear by hardware
while SDRAM initialization finish.
Data latch Clock Skew Adjustment
Due to PC board loading or too many devices connect to external
address and data bus, it may causes SDRAM can not work correctly at
high frequency (usually, > 80MHz) software can control
MCLK_O_D[3:0] to adjust address and data bus to adjust setup/hold
time.
DLH_CLK_SKEW[7:4]
[7:4]
DLH_CLK_SKEW
Gate
Delay
DLH_CLK_SKEW[7:4]
Gate
Delay
0
0
0
0
P-0
1
0
0
0
N-0
0
0
0
1
P-1
1
0
0
1
N-1
0
0
1
0
P-2
1
0
1
0
N-2
0
0
1
1
P-3
1
0
1
1
N-3
0
1
0
0
P-4
1
1
0
0
N-4
0
1
0
1
P-5
1
1
0
1
N-5
0
1
1
0
P-6
1
1
1
0
N-6
0
1
1
1
P-7
1
1
1
1
N-7
NOTE: P-x means Data latched Clock shift “X” gates delays by refer
MCLKO positive edge, N-x means Data latched Clock shift “X” gates
delays by refer MCLKO negative edge.
- 79 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
MCLK output delay adjustment
MCLK_O_D [3:0]
[3:0]
MCLK_O_D
Gate
Dela
y
MCLK_O_D [3:0]
Gate
Dela
y
0
0
0
0
P-0
1
0
0
0
N-0
0
0
0
1
P-1
1
0
0
1
N-1
0
0
1
0
P-2
1
0
1
0
N-2
0
0
1
1
P-3
1
0
1
1
N-3
0
1
0
0
P-4
1
1
0
0
N-4
0
1
0
1
P-5
1
1
0
1
N-5
0
1
1
0
P-6
1
1
1
0
N-6
0
1
1
1
P-7
1
1
1
1
N-7
NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK
positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK
negative edge. MCLK is the output pin of MCLKO, which is an internal
signal on chip.
- 80 -
W90N745CD/W90N745CDG
7.4
Cache Controller
The W90N745 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The ICache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these
two caches are configured two-way set associative addressing. Each cache has four words cache line
size. When a miss occurs, four words must be fetched consecutively from external memory. The
replacement algorithm is a LRU (Least Recently Used).
If disabling the I-Cache / D-Cache, these cache memories can be treated as On-Chip RAM. The
W90N745 also provides a write buffer to improve system performance. The write buffer can buffer up to
eight words of data.
7.4.1
On-Chip RAM
If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has
4KB On-Chip RAM, its start address is 0xFFE01000. If I-Cache is disabled, there has 4KB On-Chip RAM
and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has
8KB On-Chip RAM starting from 0xFFE00000.
The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in
Cache Control Register (CAHCON).
Table7.4.1 The size and start address of On-Chip RAM
ICAEN
7.4.2
ON-CHIP RAM
DCAEN
SIZE
START ADDRESS
0
0
8KB
0xFFE0_0000
0
1
4KB
0xFFE0_0000
1
0
4KB
0xFFE0.1000
1
1
Unavailable
Non-Cacheable Area
Although the cache affects the entire 2GB system memory, it is sometimes necessary to define noncacheable areas when the consistency of data stored in memory and the cache must be ensured. To
support this, the W90N745 provides a non-cacheable area control bit in the address field, A[31].
If A[31] in the ROM/FLASH, SDRAM, or external I/O bank’s access address is “0”, then the accessed
data is cacheable. If the A [31] value is “1”, the accessed data is non-cacheable.
- 81 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.4.3
Instruction Cache
The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is
128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache access cycle begins with an instruction request from the instruction unit in the core.
In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the
cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The
first word received from the bus is the requested instruction. The cache forwards this instruction to the
instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to
receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is
used to select a line when no empty lines are available. When I-Cache is disabled, the cache memory is
served as 4KB On-chip RAM. The I-Cache is always disabled on reset.
The following is a list of the instruction cache features：
4K bytes instruction cache
Two-way set associative
Four words in a cache line
LRU replacement policy
Lockable on a per-line basis
Critical word first, burst access
Instruction Cache Operation
On an instruction fetch, bits 10-4 of the instruction’s address point into the cache to retrieve the tags and
data of one set. The tags from both ways are then compared against bits 30-11 of the instruction’s
address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor
the matched tag is not valid, it is a cache miss.
Instruction Cache Hit
In case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line
whose tag matches. The instruction is immediately transferred to the instruction unit of the core.
Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4word burst transfer read request. A cache line is then selected to receive the data that will be coming
from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the
selected set is invalid, then the least recently used line is selected for replacement. Locked lines are
never replaced. The transfer begins with the word requested by the instruction unit (critical word first),
followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound).
Instruction Cache Flushing
The W90N745 does not support external memory snooping. Therefore, if self-modifying code is written,
the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one
operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with
the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is
automatically flushed during reset.
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Instruction Cache Load and Lock
The W90N745 supports a cache-locking feature that can be used to lock critical sections of code into ICache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line
command.
To load and lock instruction, the following sequence should be followed:
1.
Write the start address of the instructions to be locked into CAHADR register.
2.
Set LDLK and ICAH bits in the CAHCON register.
3.
Increased the address by 16 and written into CAHADR register.
4.
Set LDLK and ICAH bits in the CAHCON register.
5.
Repeat the steps 3 and 4, until the desired instructions are all locked.
When using I-Cache load and lock command, there are some notes should be cared.
The programs executing load and lock operation should be held in a non-cacheable area of memory.
The cache should be enabled and interrupts should be disabled.
Software must flush the cache before execute load and lock to ensure that the code to be locked
down is not already in the cache.
Instruction Cache Unlock
The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line
is cleared to “0”. W90N745 has two unlock command, unlock line and unlock all.
The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,
it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the
cache, no operation is done and the command terminates with no exception. To unlock one line the
following unlock line sequence should be followed:
1.
Write the address of the line to be unlocked into the CAHADR Register.
2.
Set the ULKS and ICAH bits in the CAHCON register.
The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache
lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a
line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA
and ICAH bits.
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7.4.4
Data Cache
The W90N745 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is
128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache is designed for buffer write-through mode of operation and a least recently used
(LRU) replacement algorithm is used to select a line when no empty lines are available.
When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM.
The D-Cache is always disabled on reset.
The following is a list of the data cache features：
4K bytes data cache
Two-way set associative
Four words in a cache line
LRU replacement policy
Lockable on a per-line basis
Critical word first, burst access
Buffer Write-through mode
8 words write buffer
Drain write buffer
Data Cache Operation
On a data fetch, bits 10-4 of the data’s address point into the cache to retrieve the tags and data of one
set. The tags from both ways are then compared against bits 30-11 of the data’s address. If a match is
found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is
not valid, it is a cache miss.
Data Cache Read
Read Hit：On a cache hit, the requested word is immediately transferred to the core.
Read Miss：A line in the cache is selected to hold the data, which will be fetched from memory. The
selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is
selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is
selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the
missed data (critical word first), followed by the remaining word in the line, then by the word at the
beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to
the core.
Data Cache Write
As buffer write-through mode, store operations always update memory. The buffer write-through mode is
used when external memory and internal cache images must always agree.
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Write Hit：Data is written into both the cache and write buffer. The processor then continues to access
the cache, while the cache controller simultaneously downloads the contents of the write buffer to main
memory. This reduces the effective write memory cycle time from the time required for a main memory
cycle to the cycle time of the high-speed cache.
Write Miss：Data is only written into write buffer, not to the cache (write no allocate).
Data Cache Flushing
The W90N745 allows flushing of the data cache under software control. The data cache may be
invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register.
Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the “V” bit
of the line is cleared to “0”. The D-cache is automatically flushed during reset.
Data Cache Load and Lock
The W90N745 supports a cache-locking feature that can be used to lock critical sections of data into DCache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. The locked lines are not replaced during misses and it is not affected by flush per line
command.
To load and lock data, the following sequence should be followed:
1.
Write the start address of the data to be locked into CAHADR register.
2.
Set LDLK and DCAH bits in the CAHCON register.
3.
Increased the address by 16 and written into CAHADR register.
4.
Set LDLK and DCAH bits in the CAHCON register.
5.
Repeat the steps 3 and 4, until the desired data are all locked.
When using D-Cache load and lock command, there are some notes should be cared.
The programs executing load and lock operation should be held in a non-cacheable area of memory.
The cache should be enabled and interrupts should be disabled.
Software must flush the cache before execute load and lock to ensure that the data to be locked down
is not already in the cache.
Data Cache Unlock
The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line
is cleared to “0”. W90N745 has two unlock command, unlock line and unlock all.
The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,
it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the
cache, no operation is done and the command terminates with no exception. To unlock one line the
following unlock line sequence should be followed:
1.
Write the address of the line to be unlocked into the CAHADR Register.
2.
Set the ULKS and DCAH bits in the CAHCON register.
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The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache
lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a
line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA
and DCAH bits.
7.4.5
Write Buffer
The W90N745 provides a write buffer to improve system performance. The write buffer can buffer up to
eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF
register, and the buffer is disabled and flushed on reset.
Drain write buffer
To force data, this is in write buffer, to be written to external main memory. This operation is useful in real
time applications where the processor needs to be sure that a write to a peripheral has completed before
program execution continues.
To perform this command, you can set the DRWB and DCAH bits in CAHCON register.
7.4.6
Cache Control Registers Map
REGISTER
ADDRESS
R/W
CAHCNF
0xFFF0_2000
R/W Cache configuration register
0x0000_0000
CAHCON
0xFFF0_2004
R/W Cache control register
0x0000_0000
CAHADR
0xFFF0_2008
R/W Cache address register
0x0000_0000
CTEST0
0xFFF6_0000
R/W Cache test register 0
0x0000_0000
CTEST1
0xFFF6_0004
R
DESCRIPTION
Cache test register 1
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RESET VALUE
0x0000_0000
W90N745CD/W90N745CDG
Configuration Register (CAHCNF)
Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write
buffer.
REGISTER
ADDRESS
CAHCNF
0xFFF0_2000
31
30
R/W
DESCRIPTION
RESET VALUE
R/W Cache configuration register
0x0000_0000
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
WRBEN
DCAEN
ICAEN
RESERVED
23
22
21
20
RESERVED
15
14
13
12
RESERVED
7
6
5
4
RESERVED
BITS
[31:3]
DESCRIPTION
RESERVED
Write buffer enable
[2]
WRBEN
Write buffer is disabled after reset.
1 = enable write buffer
0 = disable write buffer
D-Cache enable
[1]
DCAEN
D-Cache is disabled after reset.
1 = enable D-cache
0 = disable D-cache
I-Cache enable
[0]
ICAEN
I-Cache is disabled after reset.
1 = enable I-cache
0 = disable I-cache
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Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
Flush I-Cache and D-Cache
Load and lock I-Cache and D-Cache
Unlock I-Cache and D-Cache
Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
REGISTER
ADDRESS
CAHCON
0xFFF0_2004
31
30
R/W
DESCRIPTION
RESET VALUE
R/W Cache control register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
RESERVED
23
22
21
20
RESERVED
15
14
13
12
RESERVED
7
6
5
4
3
2
1
0
DRWB
ULKS
ULKA
LDLK
FLHS
FLHA
DCAH
ICAH
BITS
DESCRIPTION
[31:8]
RESERVED
[7]
DRWB
[6]
ULKS
[5]
ULKA
Drain write buffer
Forces write buffer data to be written to main memory.
Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in
CAHADR register must be specified.
Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared
to 0.
Load and Lock I-Cache/D-Cache
[4]
LDLK
Loads the instruction or data from external memory and locks into
cache. Both WAY and ADDR bits in CAHADR register must be
specified.
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Continued.
BITS
DESCRIPTION
Flush I-Cache/D-Cache single line
[3]
FLHS
Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR
bits in CAHADR register must be specified.
Flush I-Cache/D-Cache entirely
[2]
FLHA
[1]
DCAH
[0]
ICAH
To flush the entire I-Cache/D-Cache, also flushes any locked-down
code. If the I-Cache/D-Cache contains locked down code, the
programmer must flush lines individually
D-Cache selected
When set to “1”, the command set is executed with D-Cache.
I-Cache selected
When set to “1”, the command set is executed with I-Cache.
NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute
entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be
executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set
both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid
command and no operation is done and the command terminates with no exception.
The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB
and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no
operation is done and the command terminates with no exception.
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Address Register (CAHADR)
W90N745 Cache Controller supports one address register. This address register is used with the
command set in the control register (CAHCON) by specifying instruction/data address.
REGISTER
ADDRESS
CAHADR
0xFFF0_2008
31
30
R/W
DESCRIPTION
R/W Cache address register
29
28
27
WAY
23
RESET VALUE
0x0000_0000
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDR
22
21
20
ADDR
15
14
13
12
ADDR
7
6
5
4
ADDR
BITS
DESCRIPTION
Way selection
[31]
WAY
0 = Way0 is selected
1 = Way1 is selected
[30:0]
ADDR
The absolute address of instruction or data
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Cache Test Register 0 (CTEST0)
Cache test control register that configures the cache and tag ram testing enable or disable. In addition,
this register controls the built-in-self-test (BIST) function of SRAM.
REGISTER
ADDRESS
CTEST0
0xFFF6_0000
31
30
R/W
DESCRIPTION
RESET VALUE
R/W Cache test register 0
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
RESERVED
23
22
21
20
RESERVED
15
14
BISTEN
7
13
12
RESERVED
6
5
BST_GP3
4
3
BST_GP2 BST_GP1 BST_GP0
2
RESERVED
BITS
[31:16]
1
0
CATEST
DESCRIPTION
RESERVED
BIST mode enable
[15]
BISTEN
[14:12]
RESERVED
[11]
BIST_GP3
[10]
BIST_GP2
When set to “1”, BIST mode will be enabled, the selected memory
groups begins to be tested by BIST.
Memory group 3 is selected to test by BIST
When set to “1”, memory group 3, including data cache tag ram
way 0 and way 1, are selected to be tested by BIST.
Memory group 2 is selected to test by BIST
When set to “1”, memory group 2, including program cache tag
ram way 0 and way 1, are selected to be tested by BIST.
Memory group 1 is selected to test by BIST
[9]
BIST_GP1
When set to “1”, memory group 1, including data cache ram way 0
and way 1, are selected to be tested by BIST.
Memory group 0 is selected to test by BIST
[8]
BIST_GP0
[7:0]
RESERVED
When set to “1”, memory group 0, including program cache ram
way 0 and way 1, are selected to be tested by BIST.
-
** Note: The 4 memory groups can be selected and tested simultaneously by BIST.
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Cache Test Register 1 (CTEST1)
Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST
is finish and all of bank of SRAM are tested successfully will be presented in this register.
REGISTER
ADDRESS
R/W
CTEST1
0xFFF6_0004
R
31
30
29
DESCRIPTION
Cache test register 1
28
27
FINISH
23
RESET VALUE
0x0000_0000
26
25
24
19
18
17
16
11
10
9
8
RESERVED
22
21
20
RESERVED
15
14
13
12
RESERVED
7
6
5
4
3
2
1
0
BFAIL7
BFAIL6
BFAIL5
BFAIL4
BFAIL3
BFAIL2
BFAIL1
BFAIL0
BITS
DESCRIPTION
BIST completed
[31]
FINISH
[30:8]
RESERVED
[7]
BFAIL7
[6]
BFAIL6
This bit is “0” initially. When BIST mode enabled, this bit will be “1”
after BIST test completed. The values of BFAIL0-7 are valid only
after FINISH = 1.
BIST test fail for data cache tag ram way 1
If this bit equals to “1”, it indicates the data cache tag ram for way
1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache tag ram way 0
If this bit equals to “1”, it indicates the data cache tag ram for way
0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 1
[5]
BFAIL5
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 0
[4]
BFAIL4
[3]
BFAIL3
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache ram way 1
If this bit equals to “1”, it indicates the data cache ram for way 1 is
tested fail by BIST. “0” means the test is passed.
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Continued.
BITS
DESCRIPTION
BIST test fail for data cache ram way 0
[2]
BFAIL2
If this bit equals to “1”, it indicates the data cache ram for way 0 is
tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache ram way 1
[1]
BFAIL1
[0]
BFAIL0
If this bit equals to “1”, it indicates the instruction cache ram for
way 1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache ram way 0
If this bit equals to “1”, it indicates the instruction cache ram for
way 0 is tested fail by BIST. “0” means the test is passed.
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7.5
Ethernet MAC Controller
Overview
The W90N745 provides an Ethernet MAC Controller (EMC) for LAN application. This EMC has its
DMA controller, transmit FIFO, and receive FIFO.
The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM
function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine
controller and status controller. The EMC only supports RMII (Reduced MII) interface to connect with
PHY operating on 50MHz REF_CLK.
Features
Supports IEEE Std. 802.3 CSMA/CD protocol.
Supports both half and full duplex for 10M/100M bps operation.
Supports RMII interface.
Supports MII Management function.
Supports pause and remote pause function for flow control.
Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception.
Supports 16 entries CAM function for Ethernet MAC address recognition.
Supports internal loop back mode for diagnostic.
Supports 256 bytes embedded transmit and receive FIFO.
Supports DMA function.
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7.5.1
EMC Functional Description
MII Management State Machine
The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management
interface, software can access the control and status registers of the external PHY chip. Tow
programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII
Management Data Control and Address Register) are for MII management function. Set the bit BUSY
of MIIDA register will trigger the MII management state machine. After the MII management cycle is
finished, the BUSY bit will be cleared automatically.
Media Access Control (MAC)
The function of W90N745 MAC fully meets the requirements defined by the IEEE802.3u specification.
The following paragraphs will describe the frame structure and the operation of the transmission and
receive.
The transmission data frame sent from the transmit DMA will be encapsulated by the MAC before
transmitting onto the MII bus. The sent data will be assembled with the preamble, the start frame
delimiter (SFD), the frame check sequence and the padding for enforcing those less than 64 bytes to
meet the minimum size frame and CRC sequence. The out going frame format will be as following
110101010 --- 10101010 10101011 d0 d1 d2 -
dn Padding
CRC31 CRC30 ---
CRC0
As mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern
“10101010” and the SFD is a one byte 10101011 data. The padding data will be all 0 value if the sent
data frame is less than 64 bytes. The padding disable function specified in the bit P of the transmit
descriptor is used to control if the MAC needs to pad data at the end of frame data or not when the
transmitted data frame is less than 64 bytes. The padding data will not be appended if the padding
disable bit is set to be high. The bits CRC0 ... CRC31 are the 32 bits cyclic redundancy check (CRC)
sequence. The CRC encoding is defined by the following polynomial specified by the IEEE802.3. This
32 bits CRC appending function will be disabled if the Inhibit CRC of the transmission descriptor is set
to high.
The MAC also performs many other transmission functions specified by the IEEE802.3, including the
inter-frame spacing function, collision detection, collision enforcement, collision back off and
retransmission. The collision back-off timer is a function of the integer slot time, 512 bit times. The
number of slot times to delay between the current transmissions attempts to the next attempt is
determined by a uniformly distributed random integer algorithm specified by the IEEE802.3. The MAC
performs the receive functions specified by the IEEE 802.3 including the address recognition function,
the frame check sequence validation, the frame disassembly, framing and collision filtering.
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EMC Descriptors
A link-list data structure named as descriptor is used to keep the control, status and data
information of each frame. Through the descriptor, CPU and EMC exchange the information for frame
reception and transmission.
Two different descriptors are defined in W90N745. One named as Rx descriptor for frame
reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of
four words. There is much information kept in the descriptors and details are described as below.
7.5.1.1. Rx Buffer Descriptor
3 3 2
1 0 9
O
1 1
6 5
0
Rx Status
Receive Byte Count
Receive Buffer Starting Address
BO
Reserved
Next Rx Descriptor Starting Address
Rx Descriptor Word 0
31
30
29
28
27
Owner
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
RP
ALIE
RXGD
PTLE
Reserved
CRCE
RXINTR
15
14
13
12
11
10
9
8
3
2
1
0
RBC
7
6
5
4
RBC
Owner [31:30]: Ownership
The ownership field defines which one, the CPU or EMC, is the owner of each Rx descriptor. Only the
owner has right to modify the Rx descriptor and the others can read the Rx descriptor only.
00: The owner is CPU
01: Undefined
10: The owner is EMC
11: Undefined
If the O=2’b10 indicates the EMC RxDMA is the owner of Rx descriptor and the Rx descriptor is
available for frame reception. After the frame reception completed, if the frame needed NAT
translation, EMC RxDMA modify ownership field to 2’b11. Otherwise, the ownership field will be
modified to 2’b00.
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If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing
the frame, it modifies the ownership field to 2’b10 and releases the Rx descriptor to EMC RxDMA.
Rx Status [29:16]: Receive Status
This field keeps the status for frame reception. All status bits are updated by EMC. In the receive
status, bits 29 to 23 are undefined and reserved for the future.
RP [22]: Runt Packet
The RP indicates the frame stored in the data buffer pointed by Rx descriptor is a short frame (frame
length is less than 64 bytes).
1’b0: The frame is not a short frame.
1’b1: The frame is a short frame.
ALIE [21]: Alignment Error
The ALIE indicates the frame stored in the data buffer pointed by Rx descriptor is not a multiple of
byte.
1’b0: The frame is a multiple of byte.
1’b1: The frame is not a multiple of byte.
RXGD [20]: Frame Reception Complete
The RXGD indicates the frame reception has completed and stored in the data buffer pointed by Rx
descriptor.
1’b0: The frame reception not complete yet.
1’b1: The frame reception completed.
PTLE [19]: Packet Too Long
The PTLE indicates the frame stored in the data buffer pointed by Rx descriptor is a long frame (frame
length is greater than 1518 bytes).
1’b0: The frame is not a long frame.
1’b1: The frame is a long frame.
CRCE [17]: CRC Error
The CRCE indicates the frame stored in the data buffer pointed by Rx descriptor incurred CRC error.
1’b0: The frame doesn’t incur CRC error.
1’b1: The frame incurred CRC error.
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RXINTR [16]: Receive Interrupt
The RXINTR indicates the frame stored in the data buffer pointed by Rx descriptor caused an interrupt
condition.
1’b0: The frame doesn’t cause an interrupt.
1’b1: The frame caused an interrupt.
RBC [15:0]: Receive Byte Count
The RBC indicates the byte count of the frame stored in the data buffer pointed by Rx descriptor. The
four bytes CRC field is also included in the receive byte count. But if the SPCRC of register MCMDR
is enabled, the four bytes CRC field will be excluded from the receive byte count.
Rx Descriptor Word 1
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RXBSA
23
22
21
20
RXBSA
15
14
13
12
RXBSA
7
6
5
4
RXBSA
BO
RXBSA [31:2]: Receive Buffer Starting Address
The RXBSA indicates the starting address of the receive frame buffer. The RXBSA is used to be the
bit 31 to 2 of memory address. In other words, the starting address of the receive frame buffer always
located at word boundary.
BO [1:0]: Byte Offset
The BO indicates the byte offset from RXBSA where the received frame begins to store. If the BO is
2’b01, the starting address where the received frame begins to store is RXBSA+2’b01, and so on.
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W90N745CD/W90N745CDG
Rx Descriptor Word 2
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Reserved
The Rx descriptor word 2 keeps obsolete information for MAC translation. Therefore, these
information bits are undefined and should be ignored.
Rx Descriptor Word 3
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
NRXDSA
23
22
21
20
NRXDSA
15
14
13
12
NRXDSA
7
6
5
4
NRXDSA
NRXDSA [31:0]: Next Rx Descriptor Starting Address
The Rx descriptor is a link-list data structure. Consequently, NRXDSA is used to keep the starting
address of the next Rx descriptor. The bits [1:0] will be ignored by EMC. So, all Rx descriptor must
locate at word boundary memory address.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.5.1.2. Tx Buffer Descriptor
3 3
1 0
1 1
6 5
O
3 2 1 0
Reserved
I
C P
Transmit Buffer Starting Address
Tx Status
Transmit Byte Count
Next Tx Descriptor Starting Address
BO
Tx Descriptor Word 0
31
30
29
28
Owner
23
27
26
25
24
18
17
16
10
9
8
2
1
0
IntEn
CRCApp
PadEn
Reserved
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
4
3
Reserved
Owner [31]: Ownership
The ownership field defines which one, the CPU or EMC, is the owner of each Tx descriptor. Only the
owner has right to modify the Tx descriptor and the other can read the Tx descriptor only.
0: The owner is CPU
1: The owner is EMC
If the O=1’b1 indicates the EMC TxDMA is the owner of Tx descriptor and the Tx descriptor is
available for frame transmission. After the frame transmission completed, EMC TxDMA modify
ownership field to 1’b0 and return the ownership of Tx descriptor to CPU.
If the O=1’b0 indicates the CPU is the owner of Tx descriptor. After the CPU prepares new frame to
wait transmission, it modifies the ownership field to 1’b1 and releases the Tx descriptor to EMC
TxDMA.
IntEn [2]: Transmit Interrupt Enable
The IntEn controls the interrupt trigger circuit after the frame transmission completed. If the IntEn is
enabled, the EMC will trigger interrupt after frame transmission completed. Otherwise, the interrupt
doesn’t be triggered.
1’b0: Frame transmission interrupt is masked.
1’b1: Frame transmission interrupt is enabled.
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W90N745CD/W90N745CDG
CRCApp [1]: CRC Append
The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes
CRC checksum will be appended to frame at the end of frame transmission.
1’b0: 4-bytes CRC appending is disabled.
1’b1: 4-bytes CRC appending is enabled.
PadEN [0]: Padding Enable
The PadEN control the PAD bits appending while the length of transmission frame is less than 60
bytes. If PadEN is enabled, EMC does the padding automatically.
1’b0: PAD bits appending is disabled.
1’b1: PAD bits appending is enabled.
Tx Descriptor Word 1
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TXBSA
23
22
21
20
TXBSA
15
14
13
12
TXBSA
7
6
5
4
TXBSA
BO
TXBSA [31:2]: Transmit Buffer Starting Address
The TXBSA indicates the starting address of the transmit frame buffer. The TXBSA is used to be the
bit 31 to 2 of memory address. In other words, the starting address of the transmit frame buffer always
located at word boundary.
BO [1:0]: Byte Offset
The BO indicates the byte offset from TXBSA where the transmit frame begins to read. If the BO is
2’b01, the starting address where the transmit frame begins to read is TXBSA+2’b01, and so on.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Tx Descriptor Word 2
31
30
29
28
CCNT
27
26
25
24
Reserved
SQE
PAU
TXHA
23
22
21
20
19
18
17
16
LC
TXABT
NCS
EXDEF
TXCP
Reserved
DEF
TXINTR
15
14
13
12
11
10
9
8
3
2
1
0
TBC
7
6
5
4
TBC
CCNT [31:28]: Collision Count
The CCNT indicates the how many collision occurred consecutively during a packet transmission. If
the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4’h0 and bit
TXABT will be set to 1.
SQE [26]: SQE Error
The SQE indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.
The SQE error check will only be done while both bit EnSQE of MCMDR is enabled and EMC is
operating on 10Mbps half-duplex mode.
1’b0: No SQE error found at end of packet transmission.
1’b0: SQE error found at end of packet transmission.
PAU [25]: Transmission Paused
THE PAU INDICATES THE NEXT NORMAL PACKET transmission process will be paused temporally
because EMC received a PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to
transmit a PAUSE control frame out.
1’b0: Next normal packet transmission process will go on.
1’b1: Next normal packet transmission process will be paused.
TXHA [24]: Transmission Halted
The TXHA indicates the next normal packet transmission process will be halted because the bit TXON
of MCMDR is disabled be S/W.
1’b0: Next normal packet transmission process will go on.
1’b1: Next normal packet transmission process will be halted.
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W90N745CD/W90N745CDG
LC [23]: Late Collision
The LC indicates the collision occurred in the outside of 64 bytes collision window. This means after
the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision
check will only be done while EMC is operating on half-duplex mode.
1’b0: No collision occurred in the outside of 64 bytes collision window.
1’b1: Collision occurred in the outside of 64 bytes collision window.
TXABT [22]: Transmission Abort
The TXABT indicates the packet incurred 16 consecutive collisions during transmission, and then the
transmission process for this packet is aborted. The transmission abort is only available while EMC is
operating on half-duplex mode.
1’b0: Packet doesn’t incur 16 consecutive collisions during transmission.
1’b1: Packet incurred 16 consecutive collisions during transmission.
NCS [21]: No Carrier Sense
The NCS indicates the MII I/F signal CRS doesn’t active at the start of or during the packet
transmission. The NCS is only available while EMC is operating on half-duplex mode.
1’b0: CRS signal actives correctly.
1’b1: CRS signal doesn’t active at the start of or during the packet transmission.
EXDEF [20]: Defer Exceed
The EXDEF indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps
mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NDEF of
MCMDR is disabled, and EMC is operating on half-duplex mode.
1’b0: Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms
(10Mbps).
1’b1: Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
TXCP [19]: Transmission Complete
The TXCP indicates the packet transmission has completed correctly.
1’b0: The packet transmission doesn’t complete.
1’b1: The packet transmission has completed.
DEF [17]: Transmission Deferred
The DEF indicates the packet transmission has deferred once. The DEF is only available while EMC
is operating on half-duplex mode.
1’b0: Packet transmission doesn’t defer.
1’b1: Packet transmission has deferred once.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
TXINTR [16]: Transmit Interrupt
The TXINTR indicates the packet transmission caused an interrupt condition.
1’b0: The packet transmission doesn’t cause an interrupt.
1’b1: The packet transmission caused an interrupt.
TBC [15:0]: Transmit Byte Count
The TBC indicates the byte count of the frame stored in the data buffer pointed by Tx descriptor for
transmission.
Tx Descriptor Word 3
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
NTXDSA
23
22
21
20
NTXDSA
15
14
13
12
NTXDSA
7
6
5
4
NTXDSA
NTXDSA [31:0]: Next Tx Descriptor Starting Address
The Tx descriptor is a link-list data structure. Consequently, NTXDSA is used to keep the starting
address of the next Tx descriptor. The bits [1:0] will be ignored by EMC. So, all Tx descriptor must
locate at word boundary memory address.
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W90N745CD/W90N745CDG
7.5.2
EMC Register Mapping
The EMC implements many registers and the registers are separated into three types, the control
registers, the status registers and diagnostic registers. The control registers are used by S/W to pass
control information to EMC. The status registers are used to keep EMC operation status for S/W. And,
the diagnostic registers are used for debug only.
EMC Registers
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CONTROL REGISTERS (44)
CAMCMR
0xFFF0_3000
R/W
CAM Command Register
0x0000_0000
CAMEN
0xFFF0_3004
R/W
CAM Enable Register
0x0000_0000
CAM0M
0xFFF0_3008
R/W
CAM0 Most Significant Word Register
0x0000_0000
CAM0L
0xFFF0_300C
R/W
CAM0 Least Significant Word Register
0x0000_0000
CAM1M
0xFFF0_3010
R/W
CAM1 Most Significant Word Register
0x0000_0000
CAM1L
0xFFF0_3014
R/W
CAM1 Least Significant Word Register
0x0000_0000
CAM2M
0xFFF0_3018
R/W
CAM2 Most Significant Word Register
0x0000_0000
CAM2L
0xFFF0_301C
R/W
CAM2 Least Significant Word Register
0x0000_0000
CAM3M
0xFFF0_3020
R/W
CAM3 Most Significant Word Register
0x0000_0000
CAM3L
0xFFF0_3024
R/W
CAM3 Least Significant Word Register
0x0000_0000
CAM4M
0xFFF0_3028
R/W
CAM4 Most Significant Word Register
0x0000_0000
CAM4L
0xFFF0_302C
R/W
CAM4 Least Significant Word Register
0x0000_0000
CAM5M
0xFFF0_3030
R/W
CAM5 Most Significant Word Register
0x0000_0000
CAM5L
0xFFF0_3034
R/W
CAM5 Least Significant Word Register
0x0000_0000
CAM6M
0xFFF0_3038
R/W
CAM6 Most Significant Word Register
0x0000_0000
CAM6L
0xFFF0_303C
R/W
CAM6 Least Significant Word Register
0x0000_0000
CAM7M
0xFFF0_3040
R/W
CAM7 Most Significant Word Register
0x0000_0000
CAM7L
0xFFF0_3044
R/W
CAM7 Least Significant Word Register
0x0000_0000
CAM8M
0xFFF0_3048
R/W
CAM8 Most Significant Word Register
0x0000_0000
CAM8L
0xFFF0_304C
R/W
CAM8 Least Significant Word Register
0x0000_0000
CAM9M
0xFFF0_3050
R/W
CAM9 Most Significant Word Register
0x0000_0000
CAM9L
0xFFF0_3054
R/W
CAM9 Least Significant Word Register
0x0000_0000
CAM10M
0xFFF0_3058
R/W
CAM10 Most Significant Word Register
0x0000_0000
CAM10L
0xFFF0_305C
R/W
CAM10 Least Significant Word Register
0x0000_0000
CAM11M
0xFFF0_3060
R/W
CAM11 Most Significant Word Register
0x0000_0000
CAM11L
0xFFF0_3064
R/W
CAM11 Least Significant Word Register
0x0000_0000
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CONTROL REGISTERS (44)
CAM12M
0xFFF0_3068
R/W
CAM12 Most Significant Word Register
0x0000_0000
CAM12L
0xFFF0_306C
R/W
CAM12 Least Significant Word Register
0x0000_0000
CAM13M
0xFFF0_3070
R/W
CAM13 Most Significant Word Register
0x0000_0000
CAM13L
0xFFF0_3074
R/W
CAM13 Least Significant Word Register
0x0000_0000
CAM14M
0xFFF0_3078
R/W
CAM14 Most Significant Word Register
0x0000_0000
CAM14L
0xFFF0_307C
R/W
CAM14 Least Significant Word Register
0x0000_0000
CAM15M
0xFFF0_3080
R/W
CAM15 Most Significant Word Register
0x0000_0000
CAM15L
0xFFF0_3084
R/W
CAM15 Least Significant Word Register
0x0000_0000
TXDLSA
0xFFF0_3088
R/W
Transmit Descriptor Link List Start
Address Register
0xFFFF_FFFC
RXDLSA
0xFFF0_308C
R/W
Receive Descriptor Link List Start
Address Register
0xFFFF_FFFC
MCMDR
0xFFF0_3090
R/W
MAC Command Register
0x0000_0000
MIID
0xFFF0_3094
R/W
MII Management Data Register
0x0000_0000
MIIDA
0xFFF0_3098
R/W
MII Management Control and Address
Register
0x0090_0000
FFTCR
0xFFF0_309C
R/W
FIFO Threshold Control Register
0x0000_0101
TSDR
0xFFF0_30A0
W
Transmit Start Demand Register
Undefined
RSDR
0xFFF0_30A4
W
Receive Start Demand Register
Undefined
DMARFC
0xFFF0_30A8
R/W
Maximum Receive Frame Control
Register
0x0000_0800
MIEN
0xFFF0_30AC
R/W
MAC Interrupt Enable Register
0x0000_0000
Status Registers (11)
MISTA
0xFFF0_30B0
R/W
MAC Interrupt Status Register
0x0000_0000
MGSTA
0xFFF0_30B4
R/W
MAC General Status Register
0x0000_0000
MPCNT
0xFFF0_30B8
R/W
Missed Packet Count Register
0x0000_7FFF
MRPC
0xFFF0_30BC
R
MAC Receive Pause Count Register
0x0000_0000
MRPCC
0xFFF0_30C0
R
MAC Receive Pause Current Count
Register
0x0000_0000
MREPC
0xFFF0_30C4
R
MAC Remote Pause Count Register
0x0000_0000
DMARFS
0xFFF0_30C8
R/W
DMA Receive Frame Status Register
0x0000_0000
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W90N745CD/W90N745CDG
Continued.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
Status Registers (11)
CTXDSA
0xFFF0_30CC
R
Current Transmit Descriptor Start
Address Register
0x0000_0000
CTXBSA
0xFFF0_30D0
R
Current Transmit Buffer Start Address
Register
0x0000_0000
CRXDSA
0xFFF0_30D4
R
Current Receive Descriptor Start
Address Register
0x0000_0000
CRXBSA
0xFFF0_30D8
R
Current Receive Buffer Start Address
Register
0x0000_0000
Diagnostic Registers (7)
RXFSM
0xFFF0_3200
R
Receive Finite State Machine Register
0x0081_1101
TXFSM
0xFFF0_3204
R
Transmit Finite State Machine Register
0x0101_1101
FSM0
0xFFF0_3208
R
Finite State Machine Register 0
0x0001_0101
FSM1
0xFFF0_320C
R
Finite State Machine Register 1
0x1100_0100
DCR
0xFFF0_3210
R/W
Debug Configuration Register
0x0000_003F
DMMIR
0xFFF0_3214
R
Debug Mode MAC Information Register
0x0000_0000
BISTR
0xFFF0_3300
R/W
BIST Mode Register
0x0000_0000
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.5.2.1. Register Details
CAM Command Register (CAMCMR)
The EMC of W90N745 supports CAM function for destination MAC address recognition. The
CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet
reception.
REGISTER
ADDRESS
R/W
CAMCMR
0xFFF0_3000
R/W
31
30
29
DESCRIPTION
RESET VALUE
CAM Command Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
Reserved
BITS
[31:5]
[4]
[3]
4
3
2
1
0
ECMP
CCAM
ABP
AMP
AUP
DESCRIPTIONS
Reserved
-
ECMP
The ECMP(Enable CAM Compare) controls the enable of CAM
comparison function for destination MAC address recognition.
If S/W wants to receive a packet with specific destination MAC
address, configures the MAC address into anyone of 16 CAM entries,
then enables that CAM entry and set ECMP to 1.
1’b0: Disable CAM comparison function for destination MAC address
recognition.
1’b1: Enable CAM comparison function for destination MAC address
recognition.
CCAM
The CCAM(Complement CAM Compare) controls the complement of
the CAM comparison result. If the ECMP and CCAM are both enabled,
the incoming packet with specific destination MAC address configured
in CAM entry will be dropped. And the incoming packet with
destination MAC address doesn’t configured in any CAM entry will be
received.
1’b0: The CAM comparison result doesn’t be complemented.
1’b1: The CAM comparison result will be complemented.
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W90N745CD/W90N745CDG
Continued.
BITS
[2]
DESCRIPTIONS
ABP
The Accept Broadcast Packet controls the broadcast packet
reception. If ABP is enabled, EMC receives all incoming packet it’s
destination MAC address is a broadcast address.
1’b0: EMC receives packet depends on the CAM comparison result.
1’b1: EMC receives all broadcast packets.
[1]
AMP
The Accept Multicast Packet controls the multicast packet reception.
If AMP is enabled, EMC receives all incoming packet it’s destination
MAC address is a multicast address.
1’b0: EMC receives packet depends on the CAM comparison result.
1’b1: EMC receives all multicast packets.
[0]
AUP
The Accept Unicast Packet controls the unicast packet reception. If
AUP is enabled, EMC receives all incoming packet it’s destination
MAC address is a unicast address.
1’b0: EMC receives packet depends on the CAM comparison result.
1’b1: EMC receives all unicast packets.
CAMCMR SETTING AND COMPARISON RESULT
CAMCMR Setting and Comparison Result
The following table is the address recognition result in different CAMCMR configuration. The
column Result shows the incoming packet type that can pass the address recognition in specific
CAM configuration. The C, U, M and B represents the:
C: It indicates the destination MAC address of incoming packet has been configured in CAM entry.
U: It indicates the incoming packet is a unicast packet.
M: It indicates the incoming packet is a multicast packet.
B: It indicates the incoming packet is a broadcast packet.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
ECMP
CCAM
AUP
AMP
ABP
RESULT
0
0
0
0
0
No Packet
0
0
0
0
1
B
0
0
0
1
0
M
0
0
0
1
1
M
B
0
0
1
0
0
C
U
0
0
1
0
1
C
U
B
0
0
1
1
0
C
U
M
0
0
1
1
1
C
U
M
B
0
1
0
0
0
C
U
M
B
0
1
0
0
1
C
U
M
B
0
1
0
1
0
C
U
M
B
0
1
0
1
1
C
U
M
B
0
1
1
0
0
C
U
M
B
0
1
1
0
1
C
U
M
B
0
1
1
1
0
C
U
M
B
0
1
1
1
1
C
U
M
B
1
0
0
0
0
C
1
0
0
0
1
C
B
1
0
0
1
0
C
M
1
0
0
1
1
C
N
1
0
1
0
0
C
U
1
0
1
0
1
C
U
B
1
0
1
1
0
C
U
M
1
0
1
1
1
C
U
M
1
1
0
0
0
U
M
B
1
1
0
0
1
U
M
B
1
1
0
1
0
U
M
B
1
1
0
1
1
U
M
B
1
1
1
0
0
C
U
M
B
1
1
1
0
1
C
U
M
B
1
1
1
1
0
C
U
M
B
1
1
1
1
1
C
U
M
B
- 110 -
B
B
W90N745CD/W90N745CDG
CAM Enable Register (CAMEN)
The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before
it can participate in the destination MAC address recognition.
REGISTER
ADDRESS
R/W
CAMEN
0xFFF0_3004
R/W
31
30
DESCRIPTION
RESET VALUE
CAM Enable Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
CAM9EN
CAM8EN
Reserved
23
22
21
20
Reserved
15
14
13
12
CAM15EN CAM14EN CAM13EN CAM12EN CAM11EN CAM10EN
7
6
5
4
3
2
1
0
CAM7EN
CAM6EN
CAM5EN
CAM4EN
CAM3EN
CAM2EN
CAM1EN
CAM0EN
BITS
DESCRIPTIONS
[31:16]
Reserved
CAM15EN
[15:13]
CAM14EN
CAM13EN
The CAM entry 13, 14 and 15 are for PAUSE control frame
transmission. If S/W wants to transmit a PAUSE control frame out to
network, the enable bits of these three CAM entries all must be
enabled first.
CAM entry 12 is enabled
[12]
CAM12EN
1’b0: CAM entry 12 disabled.
1’b1: CAM entry 12 enabled.
CAM entry 11 is enabled
[11]
CAM11EN
1’b0: CAM entry 11 disabled.
1’b1: CAM entry 11 enabled.
CAM entry 10 is enabled
[10]
CAM10EN
1’b0: CAM entry 10 disabled.
1’b1: CAM entry 10 enabled.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
CAM entry 9 is enabled
[9]
CAM9EN
1’b0: CAM entry 9 disabled.
1’b1: CAM entry 9 enabled.
CAM entry 8 is enabled
[8]
CAM8EN
1’b0: CAM entry 8 disabled.
1’b1: CAM entry 8 enabled.
CAM entry 7 is enabled
[7]
CAM7EN
1’b0: CAM entry 7 disabled.
1’b1: CAM entry 7 enabled.
CAM entry 6 is enabled
[6]
CAM6EN
1’b0: CAM entry 6 disabled.
1’b1: CAM entry 6 enabled.
CAM entry 5 is enabled
[5]
CAM5EN
1’b0: CAM entry 5 disabled.
1’b1: CAM entry 5 enabled.
CAM entry 4 is enabled
[4]
CAM4EN
1’b0: CAM entry 4 disabled.
1’b1: CAM entry 4 enabled.
CAM entry 3 is enabled
[3]
CAM3EN
1’b0: CAM entry 3 disabled.
1’b1: CAM entry 3 enabled.
CAM entry 2 is enabled
[2]
CAM2EN
1’b0: CAM entry 2 disabled.
1’b1: CAM entry 2 enabled.
CAM entry 1 is enabled
[1]
CAM1EN
1’b0: CAM entry 1 disabled.
1’b1: CAM entry 1 enabled.
CAM entry 0 is enabled
[0]
CAM0EN
1’b0: CAM entry 0 disabled.
1’b1: CAM entry 0 enabled.
- 112 -
W90N745CD/W90N745CDG
CAM Entry Registers (CAMxx)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CAM0M
CAM0L
0xFFF0_3008
0xFFF0_300C
R/W
R/W
CAM0 Most Significant Word Register
CAM0 Least Significant Word Register
0x0000_0000
0x0000_0000
CAM1M
0xFFF0_3010
R/W
CAM1 Most Significant Word Register
0x0000_0000
CAM1L
0xFFF0_3014
R/W
CAM1 Least Significant Word Register
0x0000_0000
CAM2M
0xFFF0_3018
R/W
CAM2 Most Significant Word Register
0x0000_0000
CAM2L
0xFFF0_301C
R/W
CAM2 Least Significant Word Register
0x0000_0000
CAM3M
0xFFF0_3020
R/W
CAM3 Most Significant Word Register
0x0000_0000
CAM3L
0xFFF0_3024
R/W
CAM3 Least Significant Word Register
0x0000_0000
CAM4M
0xFFF0_3028
R/W
CAM4 Most Significant Word Register
0x0000_0000
CAM4L
0xFFF0_302C
R/W
CAM4 Least Significant Word Register
0x0000_0000
CAM5M
0xFFF0_3030
R/W
CAM5 Most Significant Word Register
0x0000_0000
CAM5L
0xFFF0_3034
R/W
CAM5 Least Significant Word Register
0x0000_0000
CAM6M
0xFFF0_3038
R/W
CAM6 Most Significant Word Register
0x0000_0000
CAM6L
0xFFF0_303C
R/W
CAM6 Least Significant Word Register
0x0000_0000
CAM7M
0xFFF0_3040
R/W
CAM7 Most Significant Word Register
0x0000_0000
CAM7L
0xFFF0_3044
R/W
CAM7 Least Significant Word Register
0x0000_0000
CAM8M
0xFFF0_3048
R/W
CAM8 Most Significant Word Register
0x0000_0000
CAM8L
0xFFF0_304C
R/W
CAM8 Least Significant Word Register
0x0000_0000
CAM9M
0xFFF0_3050
R/W
CAM9 Most Significant Word Register
0x0000_0000
CAM9L
0xFFF0_3054
R/W
CAM9 Least Significant Word Register
0x0000_0000
CAM10M
0xFFF0_3058
R/W
CAM10 Most Significant Word Register
0x0000_0000
CAM10L
0xFFF0_305C
R/W
CAM10 Least Significant Word Register
0x0000_0000
CAM11M
0xFFF0_3060
R/W
CAM11 Most Significant Word Register
0x0000_0000
CAM11L
0xFFF0_3064
R/W
CAM11 Least Significant Word Register
0x0000_0000
CAM12M
0xFFF0_3068
R/W
CAM12 Most Significant Word Register
0x0000_0000
CAM12L
0xFFF0_306C
R/W
CAM12 Least Significant Word Register
0x0000_0000
CAM13M
0xFFF0_3070
R/W
CAM13 Most Significant Word Register
0x0000_0000
CAM13L
0xFFF0_3074
R/W
CAM13 Least Significant Word Register
0x0000_0000
CAM14M
0xFFF0_3078
R/W
CAM14 Most Significant Word Register
0x0000_0000
CAM14L
0xFFF0_307C
R/W
CAM14 Least Significant Word Register
0x0000_0000
CAM15M
0xFFF0_3080
R/W
CAM15 Most Significant Word Register
0x0000_0000
CAM15L
0xFFF0_3084
R/W
CAM15 Least Significant Word Register
0x0000_0000
- 113 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
CAMxM
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
MAC Address Byte 5 (MSB)
23
22
21
20
19
MAC Address Byte 4
15
14
13
12
11
MAC Address Byte 3
7
6
5
4
3
MAC Address Byte 2
BITS
[31:0]
DESCRIPTIONS
CAMxM
The CAMxM(CAMx Most Significant Word) keeps the bit 47~16 of
MAC address. The x can be the 0~14. The register pair {CAMxM,
CAMxL} represents a CAM entry and can keep a MAC address. For
example, if the MAC address 00-50-BA-33-BA-44 is kept in CAM
entry 1, the register CAM1M is 32’h0050_BA33 and CAM1L is
32’hBA44_0000.
- 114 -
W90N745CD/W90N745CDG
CAMxL
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
MAC Address Byte 1
23
22
21
20
19
MAC Address Byte 0 (LSB)
15
14
13
12
11
Reserved
7
6
5
4
3
Reserved
BITS
DESCRIPTIONS
[31:16]
CAMxL
The CAMxL(CAMx Least Significant Word) keeps the bit 15~0 of
MAC address. The x can be the 0~14. The register pair {CAMxM,
CAMxL} represents a CAM entry and can keep a MAC address. For
example, if the MAC address 00-50-BA-33-BA-44 is kept in CAM
entry 1, the register CAM1M is 32’h0050_BA33 and CAM1L is
32’hBA44_0000.
[15:0]
Reserved
-
CAM15M
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Length/Type (MSB)
23
22
21
20
19
Length/Type
15
14
13
12
11
OP-Code (MSB)
7
6
5
4
3
OP-Code
- 115 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
Length/Type Field of PAUSE Control Frame
[31:0]
Length/Type
In the PAUSE control frame, a length/type field is
defined and will be 16’h8808.
OP Code Field of PAUSE Control Frame
[15:0]
OP-Code
In the PAUSE control frame, an op code field is defined
and will be 16’h0001.
CAM15L
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Operand (MSB)
23
22
21
20
19
Operand
15
14
13
12
11
Reserved
7
6
5
4
3
Reserved
BITS
[31:16]
[15:0]
DESCRIPTIONS
Operand
Pause Parameter, In the PAUSE control frame, an operand field is
defined and controls how much time the destination Ethernet MAC
Controller is paused. The unit of the operand is the slot time, the 512
bits time.
Reserved
- 116 -
W90N745CD/W90N745CDG
Transmit Descriptor Link List Start Address Register (TXDLSA)
The Tx descriptor defined in EMC is a link-list data structure. The TXDLSA keeps the starting address
of this link-list. In other words, the TXDLSA keeps the starting address of the 1st Tx descriptor. S/W
must configure TXDLSA before enable bit TXON of MCMDR register.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
TXDLSA
0xFFF0_3088
R/W
Transmit Descriptor Link List Start
Address Register
0xFFFF_FFFC
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
TXDLSA
23
22
21
20
19
TXDLSA
15
14
13
12
11
TXDLSA
7
6
5
4
3
TXDLSA
BITS
[31:0]
DESCRIPTIONS
TXDLSA
The TXDLSA(Transmit Descriptor Link-List Start Address) keeps
the start address of transmit descriptor link-list. If the S/W enables the
bit TXON of MCMDR register, the content of TXDLSA will be loaded
into the current transmit descriptor start address register (CTXDSA).
The TXDLSA doesn’t be updated by EMC. During the operation, EMC
will ignore the bits [1:0] of TXDLSA. This means that each Tx
descriptor always must locate at word boundary memory address.
Receive Descriptor Link List Start Address Register (RXDLSA)
The Rx descriptor defined in EMC is a link-list data structure. The RXDLSA keeps the starting address
of this link-list. In other words, the RXDLSA keeps the starting address of the 1st Rx descriptor. S/W
must configure RXDLSA before enable bit RXON of MCMDR register.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
RXDLSA
0xFFF0_308C
R/W
Receive Descriptor Link List Start
Address Register
0xFFFF_FFFC
- 117 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
RXDLSA
23
22
21
20
19
RXDLSA
15
14
13
12
11
RXDLSA
7
6
5
4
3
RXDLSA
BITS
[31:0]
DESCRIPTIONS
The RXDLSA(Receive Descriptor Link-List Start Address) keeps
the start address of receive descriptor link-list. If the S/W enables the
bit RXON of MCMDR register, the content of RXDLSA will be loaded
into the current receive descriptor start address register (CRXDSA).
The RXDLSA doesn’t be updated by EMC. During the operation,
EMC will ignore the bits [1:0] of RXDLSA. This means that each Rx
descriptor always must locate at word boundary memory address.
RXDLSA
MAC Command Register (MCMDR)
The MCMDR provides the control information for EMC. Some command settings affect both frame
transmission and reception, such as bit FDUP, the full/half duplex mode selection, or bit OPMOD, the
100/10M bps mode selection. Some command settings control frame transmission and reception
separately, likes bit TXON and RXON.
REGISTER
ADDRESS
R/W
MCMDR
0xFFF0_3090
R/W
31
30
DESCRIPTION
RESET VALUE
MAC Command Register
29
28
27
0x0000_0000
26
25
Reserved
23
22
Reserved
15
14
SWR
21
20
19
18
17
16
LBK
OPMOD
EnMDC
FDUP
EnSQE
SDPZ
13
12
11
10
9
8
NDEF
TXON
Reserved
7
Reserved
6
24
5
4
3
2
1
0
SPCRC
AEP
ACP
ARP
ALP
RXON
- 118 -
W90N745CD/W90N745CDG
BITS
[31:25]
[24]
DESCRIPTIONS
Reserved
SWR
The SWR (Software Reset) implements a reset function to make the
EMC return default state. The SWR is a self-clear bit. This means
after the software reset finished, the SWR will be cleared
automatically. Enable SWR can also reset all control and status
registers, except for OPMOD bit of MCMDR register.
The EMC re-initial is needed after the software reset completed.
1’b0: Software reset completed.
1’b1: Enable software reset.
[23:22]
[21]
Reserved
LBK
The LBK (Internal Loop Back Select) enables the EMC operating
on internal loop-back mode. If the LBK is enabled, the packet
transmitted out will be loop-backed to Rx. If the EMC is operating on
internal loop-back mode, it also means the EMC is operating on fullduplex mode and the value of FDUP of MCMDR register is ignored.
Beside, the LBK doesn’t be affected by SWR bit.
1’b0: The EMC operates in normal mode.
1’b1: The EMC operates in internal loop-back mode.
The Operation Mode Select defines the EMC is operating on 10M or
100M bps mode. The OPMOD doesn’t be affected by SWR bit.
[20]
OPMOD
1’b0: The EMC operates on 10Mbps mode.
1’b1: The EMC operates on 100Mbps mode.
[19]
EnMDC
The Enable MDC Clock Generation controls the MDC clock
generation for MII Management Interface. If the EnMDC is set to 1,
the MDC clock generation is enabled. Otherwise, the MDC clock
generation is disabled. Consequently, if S/W wants to access the
registers of external PHY through MII Management Interface, the
EnMDC must be set to high.
1’b0: Disable MDC clock generation.
1’b1: Enable MDC clock generation.
The Full Duplex Mode Select controls that EMC is operating on full
or half duplex mode.
[18]
FDUP
1’b0: The EMC operates on half duplex mode.
1’b1: The EMC operates on full duplex mode.
- 119 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
[17]
DESCRIPTIONS
EnSQE
The Enable SQE Checking controls the enable of SQE checking.
The SQE checking is only available while EMC is operating on 10M
bps and half duplex mode. In other words, the EnSQE cannot affect
EMC operation, if the EMC is operating on 100M bps or full duplex
mode.
1’b0: Disable SQE checking while EMC is operating on 10Mbps and
half duplex mode.
1’b1: Enable SQE checking while EMC is operating on 10Mbps and
half duplex mode.
The Send PAUSE Frame controls the PAUSE control frame
transmission.
If S/W wants to send a PAUSE control frame out, the CAM entry 13,
14 and 15 must be configured first and the corresponding CAM
enable bit of CAMEN register also must be set. Then, set SDPZ to 1
enables the PAUSE control frame transmission.
[16]
SDPZ
The SDPZ is a self-clear bit. This means after the PAUSE control
frame transmission has completed, the SDPZ will be cleared
automatically.
It is recommended that only enables SPDZ while EMC is operating
on full duplex mode.
1’b0: The PAUSE control frame transmission has completed.
1’b1: Enable EMC to transmit a PAUSE control frame out.
[15:10]
[9]
Reserved
NDEF
The No Defer controls the enable of deferral exceed counter. If
NDEF is set to high, the deferral exceed counter is disabled. The
NDEF is only useful while EMC is operating on half duplex mode.
1’b0: The deferral exceed counter is enabled.
1’b1: The deferral exceed counter is disabled.
- 120 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Frame Transmission ON controls the normal packet transmission
of EMC. If the TXON is set to high, the EMC starts the packet
transmission process, including the Tx descriptor fetching, packet
transmission and Tx descriptor modification.
[8]
TXON
It is must to finish EMC initial sequence before enable TXON.
Otherwise, the EMC operation is undefined.
If the TXON is disabled during EMC is transmitting a packet out, the
EMC stops the packet transmission process after the current packet
transmission finished.
1’b0: The EMC stops packet transmission process.
1’b1: The EMC starts packet transmission process.
[7:6]
Reserved
The Strip CRC Checksum controls if the length of incoming packet is
calculated with 4 bytes CRC checksum. If the SPCRC is set to high, 4
bytes CRC checksum is excluded from length calculation of incoming
packet.
[5]
SPCRC
1’b0: The 4 bytes CRC checksum is included in packet length
calculation.
1’b1: The 4 bytes CRC checksum is excluded in packet length
calculation.
[4]
AEP
The Accept CRC Error Packet controls the EMC accepts or drops the
CRC error packet. If the AEP is set to high, the incoming packet with
CRC error will be received by EMC as a good packet.
1’b0: The CRC error packet will be dropped by EMC.
1’b1: The CRC error packet will be accepted by EMC.
The Accept Control Packet controls the control frame reception. If the
ACP is set to high, the EMC will accept the control frame. Otherwise,
the control frame will be dropped.
[3]
ACP
It is recommended that S/W only enable AEP while EMC is operating
on full duplex mode.
1’b0: The control frame will be dropped by EMC.
1’b1: The control frame will be accepted by EMC.
- 121 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Accept Runt Packet controls the runt packet, which length is less
than 64 bytes, reception. If the ARP is set to high, the EMC will
accept the runt packet.
[2]
ARP
Otherwise, the runt packet will be dropped.
1’b0: The runt packet will be dropped by EMC.
1’b1: The runt packet will be accepted by EMC.
The Accept Long Packet controls the long packet, which packet
length is greater than 1518 bytes, reception. If the ALP is set to high,
the EMC will accept the long packet.
[1]
ALP
Otherwise, the long packet will be dropped.
1’b0: The long packet will be dropped by EMC.
1’b1: The long packet will be accepted by EMC.
The Frame Reception ON controls the normal packet reception of
EMC. If the RXON is set to high, the EMC starts the packet reception
process, including the Rx descriptor fetching, packet reception and
Rx descriptor modification.
[0]
RXON
It is must to finish EMC initial sequence before enable RXON.
Otherwise, the EMC operation is undefined.
If the RXON is disabled during EMC is receiving an incoming packet,
the EMC stops the packet reception process after the current packet
reception finished.
1’b0: The EMC stops packet reception process.
1’b1: The EMC starts packet reception process.
- 122 -
W90N745CD/W90N745CDG
MII Management Data Register (MIID)
The EMC provides MII management function to access the control and status registers of the external
PHY. The MIID register is used to store the data that will be written into the registers of external PHY
for write command or the data that is read from the registers of external PHY for read command.
REGISTER
ADDRESS
R/W
MIID
0xFFF0_3094
R/W
31
30
29
DESCRIPTION
RESET VALUE
MII Management Data Register
28
27
0x0000_0000
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
MIIData
7
6
5
4
MIIData
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
-
MIIData
The MII Management Data is the 16 bits data that will be written into
the registers of external PHY for MII Management write command or
the data from the registers of external PHY for MII Management
read command.
- 123 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
MII Management Control and Address Register (MIIDA)
The EMC provides MII management function to access the control and status registers of the external
PHY. The MIIDA register is used to keep the MII management command information, like the register
address, external PHY address, MDC clocking rate, read/write etc.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MIIDA
0xFFF0_3098
R/W
MII Management Control and Address
Register
0x0090_0000
31
30
29
28
27
26
25
24
19
18
17
16
MDCON
PreSP
BUSY
Write
11
10
9
8
1
0
Reserved
23
22
21
20
MDCCR
15
14
13
12
Reserved
7
6
PHYAD
5
4
3
Reserved
PHYRAD
BITS
[31:24]
2
DESCRIPTIONS
Reserved
The MDC Clock Rating controls the MDC clock rating for MII
Management I/F.
[23:20]
MDCCR
Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum
period for MDC shall be 400ns. In other words, the maximum
frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus
clock, the HCLK. Consequently, for different HCLKs the different
ratios are required to generate appropriate MDC clock.
The following table shows relationship between HCLK and MDC
clock in different MDCCR configurations. The THCLK indicates the
period of HCLK.
The MDC Clock ON Always controls the MDC clock generation. If the
MDCON is set to high, the MDC clock actives always. Otherwise, the
MDC will only active while S/W issues a MII management command.
[19]
MDC
1’b0: The MDC clock will only active while S/W issues a MII
management command.
1’b1: The MDC clock actives always.
- 124 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Preamble Suppress controls the preamble field generation of
MII management frame. If the PreSP is set to high, the preamble field
generation of MII management frame is skipped.
[18]
PreSP
1’b0: Preamble field generation of MII management frame is not
skipped.
1’b1: Preamble field generation of MII management frame is skipped.
The Busy Bit controls the enable of the MII management frame
generation. If S/W wants to access registers of external PHY, it set
BUSY to high and EMC generates the MII management frame to
external PHY through MII Management I/F.
[17]
BUSY
The BUSY is a self-clear bit. This means the BUSY will be cleared
automatically after the MII management command finished.
1’b0: The MII management has finished.
1’b1: Enable EMC to generate a MII management command to
external PHY.
The Write Command defines the MII management command is a
read or write.
[16]
Write
1’b0: The MII management command is a read command.
1’b1: The MII management command is a write command.
[15:13]
Reserved
The PHY Address keeps the address to differentiate which external
PHY is the target of the MII management command.
[12:8]
PHYAD
[7:5]
Reserved
-
[4:0]
PHYRAD
The PHY Register Address keeps the address to indicate which
register of external PHY is the target of the MII management
command.
- 125 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
MDCCR [23:20]
MDC CLOCK PERIOD
MDC CLOCK FREQUENCY
4’b0000
4 x THCLK
HCLK/4
4’b0001
6 x THCLK
HCLK/6
4’b0010
8 x THCLK
HCLK/8
4’b0011
12 x THCLK
HCLK/12
4’b0100
16 x THCLK
HCLK/16
4’b0101
20 x THCLK
HCLK/20
4’b0110
24 x THCLK
HCLK/24
4’b0111
28 x THCLK
HCLK/28
4’b1000
30 x THCLK
HCLK/30
4’b1001
32 x THCLK
HCLK/32
4’b1010
36 x THCLK
HCLK/36
4’b1011
40 x THCLK
HCLK/40
4’b1100
44 x THCLK
HCLK/44
4’b1101
48 x THCLK
HCLK/48
4’b1110
54 x THCLK
HCLK/54
4’b1111
60 x THCLK
HCLK/60
- 126 -
W90N745CD/W90N745CDG
MII Management Function Frame Format
In IEEE Std. 802.3 clause 22.2.4, the MII management function is defined. The MII management
function is used for the purpose of controlling the PHY and gathering status from the PHY. The MII
management frame format is shown as follow.
MANAGEMENT FRAME FIELDS
PRE
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
READ
1…1
01
10
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
WRITE
1…1
01
01
AAAAA
RRRRR
10
DDDDDDDDDDDDDDDD
Z
MII Management Function Configure Sequence
READ
WRITE
1.
Set appropriate MDCCR.
1.
Write data to MIID register
2.
Set PHYAD and PHYRAD.
2.
Set appropriate MDCCR.
3.
Set Write to 1’b0
3.
Set PHYAD and PHYRAD.
4.
Set bit BUSY to 1’b1 to send a MII
management frame out.
4.
Set Write to 1’b1
5.
5.
Wait BUSY to become 1’b0.
Set bit BUSY to 1’b1 to send a MII
management frame out.
6.
Read data from MIID register.
6.
Wait BUSY to become 1’b0.
7.
Finish the read command.
7.
Finish the write command.
- 127 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
FIFO Threshold Control Register (FFTCR)
The FFTCR defines the high and low threshold of internal FIFOs, including TxFIFO and RxFIFO. The
threshold of internal FIFOs is related to EMC request generation and when the frame transmission
starts. The FFTCR also defines the burst length of AHB bus cycle for system memory access.
REGISTER
ADDRESS
R/W
FFTCR
0xFFF0_309C
R/W
31
30
29
DESCRIPTION
RESET VALUE
0x0000_0101
FIFO Threshold Control Register
28
27
26
25
24
18
17
16
Reserved
23
22
21
Reserved
15
20
19
BLength
14
13
Reserved
12
11
10
9
Reserved
7
6
5
TxTHD
4
3
Reserved
BITS
[31:22]
8
2
1
0
RxTHD
DESCRIPTIONS
Reserved
[21:20]
Blength
[19:10]
Reserved
The DMA Burst Length defines the burst length of AHB bus cycle
while EMC accesses system memory.
2’b00: 4 words
2’b01: 8 words
2’b10: 16 words
2’b11: 16 words
-
- 128 -
W90N745CD/W90N745CDG
Continued.
BITS
[9:8]
DESCRIPTIONS
TxTHD
The TxFIFO Low Threshold controls when TxDMA requests internal
arbiter for data transfer between system memory and TxFIFO. The
TxTHD defines not only the low threshold of TxFIFO, but also the high
threshold. The high threshold is the twice of low threshold always.
During the packet transmission, if the TxFIFO reaches the high
threshold, the TxDMA stops generate request to transfer frame data
from system memory to TxFIFO. If the frame data in TxFIFO is less
than low threshold, TxDMA starts to transfer frame data from system
memory to TxFIFO.
The TxTHD also defines when the TxMAC starts to transmit frame out
to network. The TxMAC starts to transmit the frame out while the
TxFIFO first time reaches the high threshold during the transmission
of the frame. If the frame data length is less than TxFIFO high
threshold, the TxMAC starts to transmit the frame out after the frame
data are all inside the TxFIFO.
2’b00: Undefined.
2’b01: TxFIFO low threshold is 64B and high threshold is 128B.
2’b10: TxFIFO low threshold is 80B and high threshold is 160B.
2’b11: TxFIFO low threshold is 96B and high threshold is 192B.
[7:2]
Reserved
[1:0]
The RxFIFO High Threshold controls when RxDMA requests internal
arbiter for data transfer between RxFIFO and system memory. The
RxTHD defines not only the high threshold of RxFIFO, but also the low
threshold. The low threshold is the half of high threshold always.
During the packet reception, if the RxFIFO reaches the high threshold,
the RxDMA starts to transfer frame data from RxFIFO to system
memory. If the frame data in RxFIFO is less than low threshold,
RxDMA stops to transfer the frame data to system memory.
2’b00: Depend on the burst length setting. If the burst length is 8
words, high threshold is 8 words, too.
2’b01: RxFIFO high threshold is 64B and low threshold is 32B.
2’b10: RxFIFO high threshold is 128B and low threshold is 64B.
2’b11: RxFIFO high threshold is 192B and low threshold is 96B.
RxTHD
- 129 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Transmit Start Demand Register (TSDR)
If the Tx descriptor is not available for use of TxDMA after the TXON of MCMDR register is enabled,
the FSM (Finite State Machine) of TxDMA enters the Halt state and the frame transmission is halted.
After the S/W has prepared the new Tx descriptor for frame transmission, it must issue a write
command to TSDR register to make TxDMA leave Halt state and contiguous frame transmission. The
TSDR is a write only register and read from this register is undefined. The write to TSDR register has
took effect only while TxDMA stayed at Halt state.
REGISTER
ADDRESS
R/W
TSDR
0xFFF0_30A0
W
DESCRIPTION
Transmit Start Demand Register
BITS
[31:0]
RESET VALUE
Undefined
DESCRIPTIONS
Reserved
-
Receive Start Demand Register (RSDR)
If the Rx descriptor is not available for use of RxDMA after the RXON of MCMDR register is enabled,
the FSM (Finite State Machine) of RxDMA enters the Halt state and the frame reception is halted.
After the S/W has prepared the new Rx descriptor for frame reception, it must issue a write command
to RSDR register to make RxDMA leave Halt state and contiguous frame reception. The RSDR is a
write only register and read from this register is undefined. The write to RSDR register has took effect
only while RxDMA stayed at Halt state.
REGISTER
ADDRESS
R/W
RSDR
0xFFF0_30A4
W
BITS
[31:0]
DESCRIPTION
Receive Start Demand Register
DESCRIPTIONS
Reserved
--
- 130 -
RESET VALUE
Undefined
W90N745CD/W90N745CDG
Maximum Receive Frame Control Register (DMARFC)
The DMARFC defines the maximum frame length for a received frame that can be stored in the
system memory. It is recommend that only use this register while S/W wants to receive a frame which
length is greater than 1518 bytes.
REGISTER
ADDRESS
R/W
DMARFC
0xFFF0_30A8
R/W
31
30
DESCRIPTION
Maximum
Register
Receive
28
27
29
RESET VALUE
Frame
Control
0x0000_0800
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
RXMS
7
6
5
4
RXMS
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
-
RXMS
The Maximum Receive Frame Length defines the
maximum frame length for received frame. If the frame
length of received frame is greater than RXMS, and bit
EnDFO of MIEN register is also enabled, the bit DFOI of
MISTA register is set and the Rx interrupt is triggered.
It is recommended that only use RXMS to qualify the length
of received frame while S/W wants to receive a frame which
length is greater than 1518 bytes.
- 131 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
MAC Interrupt Enable Register (MIEN)
The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR
for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.
REGISTER
ADDRESS
R/W
MIEN
0xFFF0_30AC
R/W
31
30
29
DESCRIPTION
RESET VALUE
MAC Interrupt Enable Register
28
27
26
0x0000_0000
25
Reserved
24
EnTxBErr
23
22
21
20
19
18
17
16
EnTDU
EnLC
EnTXABT
EnNCS
EnEXDEF
EnTXCP
EnTXEMP
EnTXINTR
15
14
13
12
11
10
9
8
Reserved
EnCFR
EnRxBErr
EnRDU
EnDEN
EnDFO
7
6
5
4
3
2
1
0
EnMMP
EnRP
EnALIE
EnRXGD
EnPTLE
EnRXOV
EnCRCE
EnRXINTR
Reserved
BITS
[31:25]
[24]
DESCRIPTIONS
Reserved
-
EnTxBErr
The Enable Transmit Bus Error Interrupt controls the TxBErr
interrupt generation. If TxBErr of MISTA register is set, and both
EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TxBErr of MISTA register is set.
1’b0: TxBErr of MISTA register is masked from Tx interrupt generation.
1’b1: TxBErr of MISTA register can participate in Tx interrupt
generation.
[23]
EnTDU
The Enable Transmit Descriptor Unavailable Interrupt controls the
TDU interrupt generation. If TDU of MISTA register is set, and both
EnTDU and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is
generated to CPU even the TDU of MISTA register is set.
1’b0: TDU of MISTA register is masked from Tx interrupt generation.
1’b1: TDU of MISTA register can participate in Tx interrupt generation.
- 132 -
W90N745CD/W90N745CDG
[22]
EnLC
The Enable Late Collision Interrupt controls the LC interrupt
generation. If LC of MISTA register is set, and both EnLC and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnLC or EnTXINTR is disabled, no Tx interrupt is generated to CPU
even the LC of MISTA register is set.
1’b0: LC of MISTA register is masked from Tx interrupt generation.
1’b1: LC of MISTA register can participate in Tx interrupt generation.
[21]
EnTXABT
The Enable Transmit Abort Interrupt controls the TXABT interrupt
generation. If TXABT of MISTA register is set, and both EnTXABT and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnTXABT or EnTXINTR is disabled, no Tx interrupt is generated to
CPU even the TXABT of MISTA register is set.
1’b0: TXABT of MISTA register is masked from Tx interrupt generation.
1’b1: TXABT of MISTA register can participate in Tx interrupt
generation.
[20]
EnNCS
The Enable No Carrier Sense Interrupt controls the NCS interrupt
generation. If NCS of MISTA register is set, and both EnNCS and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnNCS or EnTXINTR is disabled, no Tx interrupt is generated to CPU
even the NCS of MISTA register is set.
1’b0: NCS of MISTA register is masked from Tx interrupt generation.
1’b1: NCS of MISTA register can participate in Tx interrupt generation.
[19]
EnEXDEF
The Enable Defer Exceed Interrupt controls the EXDEF interrupt
generation. If EXDEF of MISTA register is set, and both EnEXDEF and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnEXDEF or EnTXINTR is disabled, no Tx interrupt is generated to
CPU even the EXDEF of MISTA register is set.
1’b0: EXDEF of MISTA register is masked from Tx interrupt generation.
1’b1: EXDEF of MISTA register can participate in Tx interrupt
generation.
[18]
EnTXCP
The Enable Transmit Completion Interrupt controls the TXCP
interrupt generation. If TXCP of MISTA register is set, and both
EnTXCP and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTXCP or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TXCP of MISTA register is set.
1’b0: TXCP of MISTA register is masked from Tx interrupt generation.
1’b1: TXCP of MISTA register can participate in Tx interrupt
generation.
- 133 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
[17]
DESCRIPTIONS
EnTXEMP
The Enable Transmit FIFO Underflow Interrupt controls the TXEMP
interrupt generation. If TXEMP of MISTA register is set, and both
EnTXEMP and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTXEMP or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TXEMP of MISTA register is set.
1’b0: TXEMP of MISTA register is masked from Tx interrupt
generation.
1’b1: TXEMP of MISTA register can participate in Tx interrupt
generation.
The EnTXINTR controls the Tx interrupt generation.
[16]
EnTXINTR
If Enable Transmit Interrupt is enabled and TXINTR of MISTA
register is high, EMC generates the Tx interrupt to CPU. If EnTXINTR
is disabled, no Tx interrupt is generated to CPU even the status bits
17~24 of MISTA are set and the corresponding bits of MIEN are
enabled. In other words, if S/W wants to receive Tx interrupt from
EMC, this bit must be enabled. And, if S/W doesn’t want to receive any
Tx interrupt from EMC, disables this bit.
1’b0: TXINTR of MISTA register is masked and Tx interrupt generation
is disabled.
1’b1: TXINTR of MISTA register is unmasked and Tx interrupt
generation is enabled.
[15]
[14]
Reserved
EnCFR
-The Enable Control Frame Receive Interrupt controls the CFR
interrupt generation. If CFR of MISTA register is set, and both EnCFR
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnCFR or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the CFR of MISTA register is set.
1’b0: CFR of MISTA register is masked from Rx interrupt generation.
1’b1: CFR of MISTA register can participate in Rx interrupt generation.
[13:12]
[11]
Reserved
--
EnRxBErr
The Enable Receive Bus Error Interrupt controls the RxBerr interrupt
generation. If RxBErr of MISTA register is set, and both EnRxBErr and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnRxBErr or EnTXINTR is disabled, no Rx interrupt is generated to
CPU even the RxBErr of MISTA register is set.
1’b0: RxBErr of MISTA register is masked from Rx interrupt generation.
1’b1: RxBErr of MISTA register can participate in Rx interrupt
generation.
- 134 -
W90N745CD/W90N745CDG
Continued.
BITS
[10]
DESCRIPTIONS
EnRDU
The Enable Receive Descriptor Unavailable Interrupt controls the
RDU interrupt generation. If RDU of MISTA register is set, and both
EnRDU and EnTXINTR are enabled, the EMC generates the Rx
interrupt to CPU. If EnRDU or EnTXINTR is disabled, no Rx interrupt is
generated to CPU even the RDU of MISTA register is set.
1’b0: RDU of MISTA register is masked from Rx interrupt generation.
1’b1: RDU of MISTA register can participate in Rx interrupt generation.
[9]
EnDEN
The Enable DMA Early Notification Interrupt controls the DENI
interrupt generation. If DENI of MISTA register is set, and both EnDEN
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the DENI of MISTA register is set.
1’b0: DENI of MISTA register is masked from Rx interrupt generation.
1’b1: DENI of MISTA register can participate in Rx interrupt generation.
[8]
EnDFO
The Enable Maximum Frame Length Interrupt controls the DFOI
interrupt generation. If DFOI of MISTA register is set, and both EnDFO
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnDFO or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the DFOI of MISTA register is set.
1’b0: DFOI of MISTA register is masked from Rx interrupt generation.
1’b1: DFOI of MISTA register can participate in Rx interrupt generation.
[7]
EnMMP
The Enable More Missed Packet Interrupt controls the MMP interrupt
generation. If MMP of MISTA register is set, and both EnMMP and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnMMP or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the MMP of MISTA register is set.
1’b0: MMP of MISTA register is masked from Rx interrupt generation.
1’b1: MMP of MISTA register can participate in Rx interrupt generation.
[6]
EnRP
The Enable Runt Packet Interrupt controls the RP interrupt
generation. If RP of MISTA register is set, and both EnRP and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnRP or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the RP of MISTA register is set.
1’b0: RP of MISTA register is masked from Rx interrupt generation.
1’b1: RP of MISTA register can participate in Rx interrupt generation.
- 135 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
[5]
DESCRIPTIONS
EnALIE
The Enable Alignment Error Interrupt controls the ALIE interrupt
generation. If ALIE of MISTA register is set, and both EnALIE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnALIE or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the ALIE of MISTA register is set.
1’b0: ALIE of MISTA register is masked from Rx interrupt generation.
1’b1: ALIE of MISTA register can participate in Rx interrupt generation.
[4]
EnRXGD
The Enable Receive Good Interrupt controls the RXGD interrupt
generation. If RXGD of MISTA register is set, and both EnRXGD and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnRXGD or EnTXINTR is disabled, no Rx interrupt is generated to
CPU even the RXGD of MISTA register is set.
1’b0: RXGD of MISTA register is masked from Rx interrupt generation.
1’b1: RXGD of MISTA register can participate in Rx interrupt
generation.
[3]
EnPTLE
The Enable Packet Too Long Interrupt controls the PTLE interrupt
generation. If PTLE of MISTA register is set, and both EnPTLE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnPTLE or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the PTLE of MISTA register is set.
1’b0: PTLE of MISTA register is masked from Rx interrupt generation.
1’b1: PTLE of MISTA register can participate in Rx interrupt
generation.
[2]
EnRXOV
The Enable Receive FIFO Overflow Interrupt controls the RXOV
interrupt generation. If RXOV of MISTA register is set, and both
EnRXOV and EnTXINTR are enabled, the EMC generates the Rx
interrupt to CPU. If EnRXOV or EnTXINTR is disabled, no Rx interrupt
is generated to CPU even the RXOV of MISTA register is set.
1’b0: RXOV of MISTA register is masked from Rx interrupt generation.
1’b1: RXOV of MISTA register can participate in Rx interrupt
generation.
- 136 -
W90N745CD/W90N745CDG
Continued.
BITS
[1]
DESCRIPTIONS
EnCRCE
The Enable CRC Error Interrupt controls the CRCE interrupt
generation. If CRCE of MISTA register is set, and both EnCRCE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnCRCE or EnTXINTR is disabled, no Rx interrupt is generated to
CPU even the CRCE of MISTA register is set.
1’b0: CRCE of MISTA register is masked from Rx interrupt generation.
1’b1: CRCE of MISTA register can participate in Rx interrupt
generation.
The Enable Receive Interrupt controls the Rx interrupt generation.
[0]
EnRXINTR
If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC
generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx
interrupt is generated to CPU even the status bits 1~14 of MISTA are
set and the corresponding bits of MIEN are enabled. In other words, if
S/W wants to receive Rx interrupt from EMC, this bit must be enabled.
And, if S/W doesn’t want to receive any Rx interrupt from EMC,
disables this bit.
1’b0: RXINTR of MISTA register is masked and Rx interrupt generation
is disabled.
1’b1: RXINTR of MISTA register is unmasked and Rx interrupt
generation is enabled.
- 137 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
MAC Interrupt Status Register (MISTA)
The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO
status and also NATA processing status. The statuses kept in MISTA will trigger the reception or
transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the
status and also clears the interrupt.
REGISTER
ADDRESS
R/W
MISTA
0xFFF0_30B0
R/W
31
30
29
DESCRIPTION
RESET VALUE
MAC Interrupt Status Register
28
27
26
0x0000_0000
25
Reserved
24
TxBErr
23
22
21
20
19
18
17
16
TDU
LC
TXABT
NCS
EXDEF
TXCP
TXEMP
TXINTR
15
14
13
12
11
10
9
8
Reserved
CFR
RxBErr
RDU
DENI
DFOI
7
6
5
4
3
2
1
0
MMP
RP
ALIE
RXGD
PTLE
RXOV
CRCE
RXINTR
Reserved
BITS
[31:25]
DESCRIPTIONS
Reserved
The Transmit Bus Error Interrupt high indicates the memory
controller replies ERROR response while EMC access system
memory through TxDMA during packet transmission process. Reset
EMC is recommended while TxBErr status is high.
[24]
TxBErr
If the TxBErr is high and EnTxBErr of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TxBErr status.
1’b0: No ERROR response is received.
1’b1: ERROR response is received.
[23]
TDU
The Transmit Descriptor Unavailable Interrupt high indicates that
there is no available Tx descriptor for packet transmission and
TxDMA will stay at Halt state. Once, the TxDMA enters the Halt
state, S/W must issues a write command to TSDR register to make
TxDMA leave Halt state while new Tx descriptor is available.
If the TDU is high and EnTDU of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TDU status.
1’b0: Tx descriptor is available.
1’b1: Tx descriptor is unavailable.
- 138 -
W90N745CD/W90N745CDG
Continued.
BITS
[22]
DESCRIPTIONS
LC
The Late Collision Interrupt high indicates the collision occurred in the
outside of 64 bytes collision window. This means after the 64 bytes of a
frame has transmitted out to the network, the collision still occurred.
The late collision check will only be done while EMC is operating on
half-duplex mode.
If the LC is high and EnLC of MIEN register is enabled, the TxINTR will
be high. Write 1 to this bit clears the LC status.
1’b0: No collision occurred in the outside of 64 bytes collision window.
1’b1: Collision occurred in the outside of 64 bytes collision window.
The Transmit Abort Interrupt high indicates the packet incurred 16
consecutive collisions during transmission, and then the transmission
process for this packet is aborted. The transmission abort is only
available while EMC is operating on half-duplex mode.
[21]
TXABT
If the TXABT is high and EnTXABT of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TXABT status.
1’b0: Packet doesn’t incur 16 consecutive collisions during
transmission.
1’b1: Packet incurred 16 consecutive collisions during transmission.
The No Carrier Sense Interrupt high indicates the MII I/F signal CRS
doesn’t active at the start of or during the packet transmission. The
NCS is only available while EMC is operating on half-duplex mode.
[20]
NCS
If the NCS is high and EnNCS of MIEN register is enabled, the TxINTR
will be high. Write 1 to this bit clears the NCS status.
1’b0: CRS signal actives correctly.
1’b1: CRS signal doesn’t active at the start of or during the packet
transmission.
The Defer Exceed Interrupt high indicates the frame waiting for
transmission has deferred over 0.32768ms on 100Mbps mode, or
3.2768ms on 10Mbps mode. The deferral exceed check will only be
done while bit NDEF of MCMDR is disabled, and EMC is operating on
half-duplex mode.
[19]
EXDEF
If the EXDEF is high and EnEXDEF of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the EXDEF status.
1’b0: Frame waiting for transmission has not deferred over 0.32768ms
(100Mbps) or 3.2768ms (10Mbps).
1’b1: Frame waiting for transmission has deferred over 0.32768ms
(100Mbps) or 3.2768ms (10Mbps).
- 139 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Transmit Completion Interrupt indicates the packet
transmission has completed correctly.
[18]
TXCP
If the TXCP is high and EnTXCP of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TXCP status.
1’b0: The packet transmission doesn’t complete.
1’b1: The packet transmission has completed.
[17]
TXEMP
The Transmit FIFO Underflow Interrupt high indicates the
TxFIFO underflow occurred during packet transmission. While the
TxFIFO underflow occurred, the EMC will retransmit the packet
automatically without S/W intervention. If the TxFIFO underflow
occurred often, it is recommended that modify TxFIFO threshold
control, the TxTHD of FFTCR register, to higher level.
If the TXEMP is high and EnTXEMP of MIEN register is enabled,
the TxINTR will be high. Write 1 to this bit clears the TXEMP
status.
1’b0: No TxFIFO underflow occurred during packet transmission.
1’b0: TxFIFO underflow occurred during packet transmission.
The Transmit Interrupt indicates the Tx interrupt status.
If TXINTR high and its corresponding enable bit, EnTXINTR of
MISTA register, is also high indicates the EMC generates Tx
interrupt to CPU. If TXINTR is high but EnTXINTR of MISTA is
disabled, no Tx interrupt is generated.
[16]
TXINTR
The TXINTR is logic OR result of the bits 17~24 in MISTA register
do logic AND with the corresponding bits in MIEN register. In
other words, if one of the bits 17~24 in MISTA register is high and
its corresponding enable bit in MIEN register is also enabled, the
TXINTR will be high. Because the TXINTR is a logic OR result,
clears bits 17~24 of MISTA register makes TXINTR be cleared,
too.
1’b0: No status of bits 17~24 in MISTA is set or no enable of bits
17~24 in MIEN is turned on.
1’b1: At least one status of bits 17~24 in MISTA is set and its
corresponding enable bit is turned on.
[15]
Reserved
- 140 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Control Frame Receive Interrupt high indicates EMC
receives a flow control frame. The CFR only available while EMC
is operating on full duplex mode.
[14]
CFR
If the CFR is high and EnCFR of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the CFR status.
1’b0: The EMC doesn’t receive the flow control frame.
1’b1: The EMC receives a flow control frame.
[13:12]
Reserved
The Receive Bus Error Interrupt high indicates the memory
controller replies ERROR response while EMC access system
memory through RxDMA during packet reception process. Reset
EMC is recommended while RxBErr status is high.
[11]
RxBErr
If the RxBErr is high and EnRxBErr of MIEN register is enabled,
the RxINTR will be high. Write 1 to this bit clears the RxBErr
status.
1’b0: No ERROR response is received.
1’b1: ERROR response is received.
[10]
RDU
The Receive Descriptor Unavailable Interrupt high indicates that
there is no available Rx descriptor for packet reception and
RxDMA will stay at Halt state. Once, the RxDMA enters the Halt
state, S/W must issues a write command to RSDR register to
make RxDMA leave Halt state while new Rx descriptor is
available.
If the RDU is high and EnRDU of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the RDU status.
1’b0: Rx descriptor is available.
1’b1: Rx descriptor is unavailable.
The DMA Early Notification Interrupt high indicates the EMC has
received the Length/Type field of the incoming packet.
[9]
DENI
If the DENI is high and EnDENI of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the DENI status.
1’b0: The Length/Type field of incoming packet has not received
yet.
1’b1: The Length/Type field of incoming packet has received.
- 141 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
[8]
DESCRIPTIONS
DFOI
The Maximum Frame Length Interrupt high indicates the length
of the incoming packet has exceeded the length limitation
configured in DMARFC register and the incoming packet is
dropped. If the DFOI is high and EnDFO of MIEN register is
enabled, the RxINTR will be high. Write 1 to this bit clears the
DFOI status.
1’b0: The length of the incoming packet doesn’t exceed the length
limitation configured in DMARFC.
1’b1: The length of the incoming packet has exceeded the length
limitation configured in DMARFC.
[7]
MMP
The More Missed Packet Interrupt high indicates the MPCNT,
Missed Packet Count, has overflow. If the MMP is high and
EnMMP of MIEN register is enabled, the RxINTR will be high.
Write 1 to this bit clears the MMP status.
1’b0: The MPCNT has not rolled over yet.
1’b1: The MPCNT has rolled over yet.
Runt Packet Interrupt
The RP high indicates the length of the incoming packet is less
than 64 bytes and the packet is dropped. If the ARP of MCMDR
register is set, the short packet is regarded as a good packet and
RP will not be set.
[6]
RP
If the RP is high and EnRP of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the RP status.
1’b0: The incoming frame is not a short frame or S/W wants to
receive a short frame.
1’b1: The incoming frame is a short frame and dropped.
The Alignment Error Interrupt high indicates the length of the
incoming frame is not a multiple of byte.
[5]
ALIE
If the ALIE is high and EnALIE of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the ALIE status.
1’b0: The frame length is a multiple of byte.
1’b1: The frame length is not a multiple of byte.
- 142 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Receive Good Interrupt high indicates the frame reception
has completed.
[4]
RXGD
If the RXGD is high and EnRXGD of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the RXGD status.
1’b0: The frame reception has not complete yet.
1’b1: The frame reception has completed.
The Packet Too Long Interrupt high indicates the length of the
incoming packet is greater than 1518 bytes and the incoming
packet is dropped. If the ALP of MCMDR register is set, the long
packet will be regarded as a good packet and PTLE will not be
set.
[3]
PTLE
If the PTLE is high and EnPTLE of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the PTLE status.
1’b0: The incoming frame is not a long frame or S/W wants to
receive a long frame.
1’b1: The incoming frame is a long frame and dropped.
[2]
RXOV
The Receive FIFO Overflow Interrupt high indicates the RxFIFO
overflow occurred during packet reception. While the RxFIFO
overflow occurred, the EMC drops the current receiving packer. If
the RxFIFO overflow occurred often, it is recommended that
modify RxFIFO threshold control, the RxTHD of FFTCR register,
to higher level.
If the RXOV is high and EnRXOV of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the RXOV status.
1’b0: No RxFIFO overflow occurred during packet reception.
1’b0: RxFIFO overflow occurred during packet reception.
The CRC Error Interrupt high indicates the incoming packet
incurred the CRC error and the packet is dropped. If the AEP of
MCMDR register is set, the CRC error packet will be regarded as
a good packet and CRCE will not be set.
[1]
CRCE
If the CRCE is high and EnCRCE of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the CRCE status.
1’b0: The frame doesn’t incur CRC error.
1’b1: The frame incurred CRC error.
- 143 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Receive Interrupt indicates the Rx interrupt status.
If RXINTR high and its corresponding enable bit, EnRXINTR of
MISTA register, is also high indicates the EMC generates Rx
interrupt to CPU. If RXINTR is high but EnRXINTR of MISTA is
disabled, no Rx interrupt is generated.
[0]
The RXINTR is logic OR result of the bits 1~14 in MISTA register
do logic AND with the corresponding bits in MIEN register. In
other words, if one of the bits 1~14 in MISTA register is high and
its corresponding enable bit in MIEN register is also enabled, the
RXINTR will be high.
RXINTR
Because the RXINTR is a logic OR result, clears bits 1~14 of
MISTA register makes RXINTR be cleared, too.
1’b0: No status of bits 1~14 in MISTA is set or no enable of bits
1~14 in MIEN is turned on.
1’b1: At least one status of bits 1~14 in MISTA is set and its
corresponding enable bit is turned on.
MAC General Status Register (MGSTA)
The MGSTA also keeps the statuses of EMC. But the statuses in the MGSTA will not trigger any
interrupt. The MGSTA is a write clear register and write 1 to corresponding bit clears the status.
REGISTER
ADDRESS
R/W
MGSTA
0xFFF0_30B4
R/W
31
30
29
DESCRIPTION
RESET VALUE
MAC General Status Register
28
27
0x0000_0000
26
25
24
18
17
16
11
10
9
8
TXHA
SQE
PAU
DEF
3
2
1
0
Reserved
RFFull
RXHA
CFR
Reserved
23
22
21
20
19
Reserved
15
14
13
12
Reserved
7
6
5
CCNT
4
- 144 -
W90N745CD/W90N745CDG
BITS
[31:12]
DESCRIPTIONS
Reserved
-
TXHA
The Transmission Halted high indicates the next normal packet transmission
process will be halted because the bit TXON of MCMDR is disabled be S/W.
1’b0: Next normal packet transmission process will go on.
1’b1: Next normal packet transmission process will be halted.
SQE
The Signal Quality Error high indicates the SQE error found at end of packet
transmission on 10Mbps half-duplex mode. The SQE error check will only be
done while both bit EnSQE of MCMDR is enabled and EMC is operating on
10Mbps half-duplex mode.
1’b0: No SQE error found at end of packet transmission.
1’b0: SQE error found at end of packet transmission.
PAU
The Transmission Paused high indicates the next normal packet
transmission process will be paused temporally because EMC received a
PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to
transmit a PAUSE control frame out.
1’b0: Next normal packet transmission process will go on.
1’b1: Next normal packet transmission process will be paused.
[8]
DEF
The Deferred Transmission high indicates the packet transmission has
deferred once. The DEF is only available while EMC is operating on halfduplex mode.
1’b0: Packet transmission doesn’t defer.
1’b1: Packet transmission has deferred once.
[7:4]
CCNT
The Collision Count indicates the how many collision occurred consecutively
during a packet transmission. If the packet incurred 16 consecutive collisions
during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1.
[3]
Reserved
[11]
[10]
[9]
[2]
[1]
[0]
-
RFFull
The RxFIFO Full indicates the RxFIFO is full due to four 64-byte packets are
kept in RxFIFO and the following incoming packet will be dropped.
1’b0: The RxFIFO is not full.
1’b1: The RxFIFO is full and the following incoming packet will be dropped.
RXHA
The Receive Halted high indicates the next normal packet reception process
will be halted because the bit RXON of MCMDR is disabled be S/W.
1’b0: Next normal packet reception process will go on.
1’b1: Next normal packet reception process will be halted.
CFR
The Control Frame Received high indicates EMC receives a flow control
frame. The CFR only available while EMC is operating on full duplex mode.
1’b0: The EMC doesn’t receive the flow control frame.
1’b1: The EMC receives a flow control frame.
- 145 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Missed Packet Count Register (MPCNT)
The MPCNT keeps the number of packets that were dropped due to various types of receive errors.
The MPCNT is a read clear register. In addition, S/W also can write an initial value to MPCNT and the
missed packet counter will start counting from that initial value. If the missed packet counter is
overflow, the MMP of MISTA will be set.
REGISTER
ADDRESS
R/W
MPCNT
0xFFF0_30B8
R/W
31
30
29
DESCRIPTION
RESET VALUE
Missed Packet Count Register
28
27
0x0000_7FFF
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
MPC
7
6
5
4
MPC
BITS
[31:16]
DESCRIPTIONS
Reserved
The Miss Packet Count indicates the number of packets that were
dropped due to various types of receive errors. The following type of
receiving error makes missed packet counter increase:
[15:0]
MPC
Incoming packet is incurred RxFIFO overflow.
Incoming packet is dropped due to RXON is disabled.
Incoming packet is incurred CRC error.
- 146 -
W90N745CD/W90N745CDG
MAC Receive Pause Count Register (MRPC)
The EMC of W90N745 supports the PAUSE control frame reception and recognition. If EMC received
a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored in
the MRPC register. The MRPC register will keep the same while Tx of EMC is pausing due to the
PAUSE control frame is received. The MRPC is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
MRPC
0xFFF0_30BC
R
31
30
29
DESCRIPTION
RESET VALUE
MAC Receive Pause Count Register
28
27
0x0000_0000
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
MRPC
7
6
5
4
MRPC
BITS
DESCRIPTIONS
[31:16]
Reserved
[15:0]
MRPC
The MAC Receive Pause Count keeps the operand field of the
PAUSE control frame. It indicates how many slot time (512 bit time)
the Tx of EMC will be paused.
MAC Receive Pause Current Count Register (MRPCC)
The EMC of W90N745 supports the PAUSE control frame reception and recognition. If EMC received
a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored into
a down count timer. The MRPCC shows the current value of that down count timer for S/W to know
how long the Tx of EMC will be paused. The MRPCC is read only and write to this register has no
effect.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MRPCC
0xFFF0_30C0
R
MAC Receive Pause Current Count
Register
0x0000_0000
- 147 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
MRPCC
7
6
5
4
3
MRPCC
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
-
MRPCC
The MAC Receive Pause Current Count shows the current value of
that down count timer. If a new PAUSE control frame is received
before the timer count down to zero, the new operand of the PAUSE
control frame will be stored into the down count timer and the timer
starts count down from the new value.
MAC Remote Pause Count Register (MREPC)
The EMC of W90N745 supports the PAUSE control frame transmission. After the PAUSE control
frame is transmitted out completely, a timer starts to count down from the value of operand of the
transmitted PAUSE control frame. The MREPC shows the current value of this down count timer. The
MREPC is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
MREPC
0xFFF0_30C4
R
31
30
29
DESCRIPTION
RESET VALUE
MAC Remote Pause Count Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
MREPC
7
6
5
4
3
MREPC
- 148 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:16]
Reserved
[15:0]
MREPC
The MAC Remote Pause Count shows the current value of the
down count timer that starts to count down from the value of operand
of the transmitted PAUSE control frame.
DMA Receive Frame Status Register (DMARFS)
The DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. This register is
writing clear and writes 1 to corresponding bit clears the bit.
REGISTER
ADDRESS
R/W
DMARFS
0xFFF0_30C8
R/W
31
30
29
DESCRIPTION
RESET VALUE
DMA Receive Frame Status Register
28
27
0x0000_0000
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
RXFLT
7
6
5
4
RXFLT
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
RXFLT
The Receive Frame Length/Type keeps the Length/Type field of
each incoming Ethernet packet. If the bit EnDEN of MIEN is enabled
and the Length/Type field of incoming packet has received, the bit
DENI of MISTA will be set and trigger interrupt. And, the content of
Length/Type field will be stored in RXFLT.
- 149 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Current Transmit Descriptor Start Address Register (CTXDSA)
The CTXDSA keeps the start address of Tx descriptor that is used by TxDMA currently. The CTXDSA
is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
CTXDSA
0xFFF0_30CC
R
31
30
29
DESCRIPTION
Current
Transmit
Address Register
28
RESET VALUE
Descriptor
27
Start
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
CTXDSA
23
22
21
20
19
CTXDSA
15
14
13
12
11
CTXDSA
7
6
5
4
3
CTXDSA
BITS
[31:0]
DESCRIPTIONS
CTXDSA
Current Transmit Descriptor Start Address
Current Transmit Buffer Start Address Register (CTXBSA)
The CTXDSA keeps the start address of Tx frame buffer that is used by TxDMA currently. The
CTXBSA is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
CTXBSA
0xFFF0_30D0
R
31
30
29
DESCRIPTION
Current
Transmit
Address Register
28
27
Buffer
RESET VALUE
Start
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
CTXBSA
23
22
21
20
19
CTXBSA
15
14
13
12
11
CTXBSA
7
6
5
4
3
CTXBSA
- 150 -
W90N745CD/W90N745CDG
BITS
[31:0]
DESCRIPTIONS
CTXBSA
Current Transmit Buffer Start Address
Current Receive Descriptor Start Address Register (CRXDSA)
The CRXDSA keeps the start address of Rx descriptor that is used by RxDMA currently. The
CRXDSA is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
CRXDSA
0xFFF0_30D4
R
31
30
29
DESCRIPTION
Current Receive
Address Register
28
RESET VALUE
Descriptor
Start
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CRXDSA
23
22
21
20
CRXDSA
15
14
13
12
CRXDSA
7
6
5
4
CRXDSA
BITS
[31:0]
DESCRIPTIONS
CRXDSA
Current Receive Descriptor Start Address
Current Receive Buffer Start Address Register (CRXBSA)
The CRXBSA keeps the start address of Rx frame buffer that is used by RxDMA currently. The
CRXBSA is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CRXBSA
0xFFF0_30D8
R
Current Receive Buffer Start Address
Register
0x0000_0000
- 151 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
CRXBSA
23
22
21
20
19
CRXBSA
15
14
13
12
11
CRXBSA
7
6
5
4
3
CRXBSA
BITS
[31:0]
DESCRIPTIONS
CRXBSA
Current Receive Buffer Start Address
Receive Finite State Machine Register (RXFSM)
The RXFSM shows the current value of the FSM (Finite State Machine) of RxDMA and RxFIFO
controller. The RXFSM is read only and write to it has no effect. The RXFSM is used only for debug.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
RXFSM
0xFFF0_3200
R
Receive Finite State Machine Register
0x0081_1101
31
30
29
28
27
26
25
24
19
18
17
16
9
8
RX_FSM
23
22
RX_FSM
Reserved
15
14
21
20
RxBuf_FSM
13
12
11
RXFetch_FSM
7
6
10
RXClose_FSM
5
4
3
RFF_FSM
- 152 -
2
1
0
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:23]
RX_FSM
RxDMA FSM
[22]
Reserved
-
[21:16]
RXBuf_FSM
Receive Buffer FSM
[15:12]
RXFetch_FSM
Receive Descriptor Fetch FSM
[11:8]
RXClose_FSM
Receive Descriptor Close FSM
[7:0]
RFF_FSM
RxFIFO Controller FSM
Transmit Finite State Machine Register (TXFSM)
The TXFSM shows the current value of the FSM (Finite State Machine) of TxDMA and TxFIFO
controller. The TXFSM is read only and write to it has no effect. The TXFSM is used only for debug.
REGISTER
ADDRESS
R/W
TXFSM
0xFFF0_3204
R
31
30
29
DESCRIPTION
Transmit
Register
Finite
28
RESET VALUE
State
Machine
0x0101_1101
27
26
25
24
19
18
17
16
9
8
TX_FSM
23
22
21
20
Reserved
15
TxBuf_FSM
14
13
12
11
10
TXFetch_FSM
7
6
TXClose_FSM
5
4
3
Reserved
2
1
0
TFF_FSM
- 153 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:24]
TX_FSM
TxDMA FSM
[23:22]
Reserved
-
[21:16]
TXBuf_FSM
[15:12]
TXFetch_FSM
Transmit Descriptor Fetch FSM
[11:8]
TXClose_FSM
Transmit Descriptor Close FSM
[7:5]
Reserved
-
[4:0]
TFF_FSM
TxFIFO Controller FSM
Transmit Buffer FSM
Finite State Machine Register 0 (FSM0)
The FSM0 shows the current value of the FSM (Finite State Machine) of the function module in EMC.
The FSM0 is read only and write to it has no effect. The FSM0 is used only for debug.
REGISTER
ADDRESS
R/W
FSM0
0xFFF0_3208
R
31
30
29
DESCRIPTION
RESET VALUE
Finite State Machine Register 0
28
27
26
0x0001_0101
25
Reserved
23
22
21
24
TXMAC_FSM
20
19
18
17
16
10
9
8
1
0
TXMAC_FSM
15
14
13
12
11
Reserved
7
TXDefer_FSM
6
5
4
3
2
STA_FSM
BITS
DESCRIPTIONS
[31:26]
Reserved
-
[25:16]
TXMAC_FSM
TxMAC FSM
[15:14]
Reserved
-
[13:8]
TXDefer_FSM
Transmit Defer Process FSM
[7:0]
STA_FSM
MII Management I/F FSM
- 154 -
W90N745CD/W90N745CDG
Finite State Machine Register 1 (FSM1)
The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC.
The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug.
REGISTER
ADDRESS
R/W
FSM1
0xFFF0_320C
R
31
30
DESCRIPTION
Finite State Machine Register 1
29
28
27
26
ARB_FSM
Reserved
23
22
RESET VALUE
0x1100_0100
25
24
TxPause_FSM
21
20
19
18
17
16
11
10
9
8
1
0
Reserved
15
14
13
12
Reserved
7
AHB_FSM
6
5
4
3
2
Reserved
BITS
DESCRIPTIONS
[31]
Reserved
-
[30:28]
ARB_FSM
Internal Arbiter FSM
[27:24]
TxPause_FSM
Transmit PAUSE Control Frame FSM
[23:14]
Reserved
-
[13:8]
AHB_FSM
[13:8]: AHB Master FSM
[7:0]
RESERVED
-
Debug Configuration Register (DCR)
The DCR is for debug only to multiplex different signal group out. In FPGA emulation, the signals are
outputted to probe pins in emulation board. In real chip, the signals are outputted through the GPIO
pins.
REGISTER
ADDRESS
R/W
DCR
0xFFF0_3210
R/W
DESCRIPTION
Debug Configuration Register
- 155 -
RESET VALUE
0x0000_003f
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
19
Enable
15
Reserved
14
13
12
11
Reserved
7
6
5
4
3
Out
Config
BITS
[31:24]
DESCRIPTIONS
Reserved
The Function Enable outputs two function enable signals to
external stimulus circuit.
[23:22]
Enable
[21:8]
Reserved
[7:6]
Out
The Flag Out provides two output flags to trigger Logic Analyzer for
debug. These two bits can be written at any time.
[5:0]
Config
The Configuration controls which group of internal signals can be
multiplexed out for debug. Each group includes 16 signals.
CONFIG
At this stage, only the bit 22 is used for external random collision
generator. The random collision generator used only in FPGA
emulation.
-
SIGNALS
CONFIG
SIGNALS
OUT [6], TransDone, GrantLost,
6’h00
Trans_CTR [4:0], LAST,
TransCtrExpire,
6’h01
OUT [6], DMode_TxBuf_CS [6:0]
DMode_TXFSM_CS [7:0]
DMode_AHB_CS [5:0]
6’h02
6’h04
OUT [6], DMode_RXBuf_CS [5:0],
DMode_RXFSM_CS [8:0]
TxBuf_DRDY, TFF_WPTR [5:0],
TX_START,
OUT [6], TXFIFO_HT, TXFIFO_LT,
6’h03
DMode_TFF_CS [4:0],
DMode_RFF_CS [7:0]
6’h05
TXSTART, READ, TFF_RPTR [5:0]
- 156 -
WRITE, RFF_WPTR [5:0],
RXFIFO_HT,
RXFIFO_LT, RxBuf_ACK, RFF_RPTR
[5:0]
W90N745CD/W90N745CDG
Continued.
CONFIG
SIGNALS
6’h06
R0_PTLE, RxStart, SFD, WasSFD,
RxFrame, WrByte, Rx_OvFlow, 1’b0,
R0_RBC [7:0]
6’h07
6’h08
Reserved
6’h09
6’h0A
OUT [7:6], RegMISTA_Rx_W,
RXERR_sync, R0_CRCE,
R0_PTLE, R0_RP,
RegMISTA_Tx_W, T0_EXDEF,
T0_TXABT,
T0_CCNT [3:0], 2’b00
6’h0B
6’h0C
OUT [7:6], FrameWPtr [1:0],
FrameRPtr [1:0], RFF_One,
FrameWPtr_Inc, FrameRPtr_Inc,
Rounding, NexPktStartPtr [5:0]
6’h0D
6’h0E
R0_CRCE, Rx_OvFlow, R0_MRE,
CRCERR,
DAMATCH, RxFrame, SFD,
RxMIIErr,
SynStart, Hi_Lo_Syn,
New_DataValid,
L_RxFrame, RxStart, DataValid,
Hi_Lo,
RX_DV_In
6’h0F
OUT [6], WRITE, RFF_WPTR [5:0],
RxReuse, RxBuf_ACK, RFF_RPTR
[5:0]
6’h10
WRITE, RFF_CS [7:1], RFF_WPTR
[5:0],
RXERR_sync, RxReuse
6’h11
OUT [6], TX_CLK, TX_EN, TXD [3:0],
RX_CLK, RX_DV, RX_ER, RXD [3:0],
CRS,
COL
6’h13
OUT [6], DMode_TxBuf_CS[6:0],
DMode_TFF_CS[4:0], TXFIFO_UF,
TXFIFO_HT, TXOK_sync
6’h12
6’h14
OUT [6], TXSTART, TX_START,
DMode_TFF_CS [4:0],
TXSTART_Set,
TXSTART_Clr, TXSTART_Re_Set,
FrameWaiting, Deferring, COL,
TXCOL,
TXCOL_sync
OUT [6], READ, READ_sync,
READ_Mask,
ReadMask_sync, TFF_RPTR [5:0],
DMode_TFF_CS [4:0]
CONFIG
SIGNALS
R0_CRCE, RX_DV_In, SynStart,
R0_DB,
Rx_OvFlow, WRITECTR [2:0],
RxByte [7:0]
Reserved
OUT [7:6], MCMDR_SDPZ_Clr,
RegMCMDR_SDPZ_Clr,
DMode_Pause_CS [3:0], MacCtlFra,
PauseFra, PauseTx,
MacCtlFra_sync, PauseFra_sync,
PAUSE,
Pause_en, FDUP
OUT [7:6], ARB_REQ_Set,
ARB_REQ_Clr,
DMode_ARB_CS [2:0], TransDone,
GrantLost, TransCtrExpire,
Trans_CTR [4:0], BURST
6’h15
- 157 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Debug Mode MAC Information Register (DMMIR)
The DMMIR keeps the information of MAC module for debug.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
DMMIR
0xFFF0_3214
R
Debug Mode MAC Information Register
0x0000_0000
31
30
29
28
27
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
RBC
7
6
5
4
RBC
BITS
DESCRIPTIONS
[31:16]
Reserved
-
[15:0]
RBC
Receive Byte Count
BIST Mode Register (BISTR)
The BISTR controls the BIST (Built In Self Test) for embedded SRAM, 256B for RxFIFO and 256B for
TxFIFO.
REGISTER
ADDRESS
R/W
BISTR
0xFFF0_3300
R/W
31
30
29
DESCRIPTION
RESET VALUE
BIST Mode Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
Finish
0
BMEn
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
Reserved
4
3
BistFail
- 158 -
W90N745CD/W90N745CDG
BITS
[31:5]
[3:2]
DESCRIPTIONS
Reserved
BistFail
The BIST Fail indicates if the BIST test fails or succeeds. If the
BistFail is low at the end, the embedded SRAM pass the BIST test,
otherwise, it is faulty. The BistFail will be high once the BIST
detects the error and remains high during the BIST operation. If
BistFail[2] high indicates the embedded SRAM for TxFIFO BIST
test failed. If BistFail[3] high indicates the embedded SRAM for
RxFIFO BIST test failed.
The BistFail is a write clear field. Write 1 to this field clears the
content and write 0 has no effect.
[1]
Finish
The BIST Operation Finish indicates the end of the BIST
operation. When BIST controller finishes all operations, this bit will
be high.
The Finish is a write clear field. Write 1 to this field clears the
content and write 0 has no effect.
[0]
BMEn
The BIST Mode Enable is used to enable the BIST operation. If
high enables the BIST controller to do embedded SRAM test. This
bit is also used to do the reset for BIST circuit. It is necessary to
reset the BIST circuit one clock cycle at least in order to initialize
the BIST properly.
The BMEn can be disabled by write 0.
- 159 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.6
GDMA Controller
The W90N745 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA
performs the following data transfers without the CPU intervention:
Memory-to-memory (memory to/from memory)
Memory –to – IO
IO- to -memory
The on-chip GDMA can be started by the software or external DMA request nXDREQ. Software can also
be used to restart the GDMA operation after it has been stopped. The CPU can recognize the completion
of a GDMA operation by software polling or when it receives an internal GDMA interrupt. The W90N745
GDMA controller can increment source or destination address, decrement them as well, and conduct 8bit (byte), 16-bit (half-word), or 32-bit (word) data transfers.
The GDMA includes the following features
AMBA AHB compliant
Supports 4-data burst mode to boost performance
Provides support for external GDMA device
Demand mode speeds up external GDMA operations
7.6.1
GDMA Functional Description
The GDMA directly transfers data between source and destination. The GDMA starts to transfer data
after it receives service requests from nXDREQ signal or software. When the entire data have been
transferred completely, the GDMA becomes idle. Nevertheless, if another transfer is needed, then the
GDMA must be programmed again. There are three transfer modes:
Single Mode
Single mode requires a GDMA request for each data transfer. A GDMA request (nXDREQ or
software) causes one byte, one half-word, or one word to transfer if the 4-data burst mode is
disabled, or four times of transfer width is the 4-data burst mode is enabled.
Block Mode
The assertion of a single GDMA request causes all of the data to be transferred in a single
operation. The GDMA transfer is completed when the current transfer count register reaches zero.
Demand Mode
The GDMA continues transferring data until the GDMA request input nXDREQ becomes inactive.
- 160 -
W90N745CD/W90N745CDG
7.6.2
GDMA Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
Channel 0
GDMA_CTL0
0xFFF0_4000
R/W Channel 0 Control Register
0x0000_0000
GDMA_SRCB0
0xFFF0_4004
R/W Channel 0 Source Base Address Register
0x0000_0000
GDMA_DSTB0
0xFFF0_4008
R/W Channel 0 Destination Base Address Register
0x0000_0000
GDMA_TCNT0
0xFFF0_400C
R/W Channel 0 Transfer Count Register
0x0000_0000
GDMA_CSRC0
0xFFF0_4010
R
Channel 0 Current Source Address Register
0x0000_0000
0xFFF0_4014
R
Channel 0 Current Destination Address
Register
0x0000_0000
GDMA_CTCNT0 0xFFF0_4018
R
Channel 0 Current Transfer Count Register
0x0000_0000
GDMA_CDST0
Channel 1
GDMA_CTL1
0xFFF0_4020
R/W Channel 1 Control Register
0x0000_0000
GDMA_SRCB1
0xFFF0_4024
R/W Channel 1 Source Base Address Register
0x0000_0000
GDMA_DSTB1
0xFFF0_4028
R/W Channel 1 Destination Base Address Register
0x0000_0000
GDMA_TCNT1
0xFFF0_402C
R/W Channel 1 Transfer Count Register
0x0000_0000
GDMA_CSRC1
0xFFF0_4030
R
Channel 1 Current Source Address Register
0x0000_0000
0xFFF0_4034
R
Channel 1 Current Destination Address
Register
0x0000_0000
GDMA_CTCNT1 0xFFF0_4038
R
Channel 1 Current Transfer Count Register
0x0000_0000
GDMA_CDST1
Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1)
REGISTER
ADDRESS
R/W
DESCRIPTION
GDMA_CTL0
0xFFF0_4000
R/W
Channel 0 Control Register
0x0000_0000
GDMA_CTL1
0xFFF0_4020
R/W
Channel 1 Control Register
0x0000_0000
31
30
RESERVED
29
28
TC_WIDTH
23
22
RW_TC
SABNDERR
15
14
DM
RESERVED
21
20
27
26
REQ_SEL
19
18
DABNDERR GDMAERR AUTOIEN
13
12
TWS
7
6
5
4
SAFIX
DAFIX
SADIR
DADIR
- 161 -
TC
RESET VALUE
25
24
REQ_ATV
ACK_ATV
17
16
BLOCK
SOFTREQ
11
10
9
8
SBMS
RESERVED
BME
SIEN
3
2
GDMAMS
1
0
RESERVED
GDMAEN
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31]
RESERVED
-
[30:28]
TC_WIDTH
nRTC/nWTC active width selection, from 1 to 7 HCLK cycles.
REQ_SEL
External request pin selection, if GDMAMS [3:2]=00, REQ_SEL will
be don’t care.
If REQ_SEL [27:26]=00, external request don’t use.
If REQ_SEL [27:26]=01, use nXDREQ.
If REQ_SEL [27:26]=10, external request don’t use.
If REQ_SEL [27:26]=11, external request don’t use.
REQ_ATV
nXDREQ High/Low active selection
1’b0 = nXDREQ is LOW active.
1’b1 = nXDREQ is HIGH active.
[24]
ACK_ATV
nXDACK High/Low active selection
1’b0 = nXDACK is LOW active.
1’b1 = nXDACK is HIGH active.
[23]
RW_TC
[27:26]
[25]
[22]
[21]
[20]
Read/Write terminal count output selection.
1’b0 = output to nRTC.
1’b1 = output to nWTC.
SABNDERR
Source address Boundary alignment Error flag
If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00
If TWS [13:12]=01, GDMA_SRCB [0] should be 0
The address boundary alignment should be depended on TWS [13:12].
1’b0 = the GDMA_SRCB is on the boundary alignment.
1’b1 = the GDMA_SRCB not on the boundary alignment
The SABNDERR register bits just can be read only.
DABNDERR
Destination address Boundary alignment Error flag
If TWS [13:12]=10, GDMA_DSTB [1:0] should be 00
If TWS [13:12]=01, GDMA_DSTB [0] should be 0
The address boundary alignment should be depended on TWS [13:12].
1’b0 = the GDMA_DSTB is on the boundary alignment.
1’b1 = the GDMA_DSTB not on the boundary alignment
The DABNDERR register bits just can be read only.
GDMATERR
GDMA Transfer Error
1’b0 = No error occurs
1’b1 = Hardware sets this bit on a GDMA transfer failure
Transfer error will generate GDMA interrupt
- 162 -
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
AUTOIEN
Auto initialization Enable
1’b0 = Disables auto initialization
1’b1
=
Enables
auto
initialization,
the
GDMA_CSRC0/1,
GDMA_CDST0/1,and GDMA_CTCNT0/1 registers are updated by the
GDMA_SRC0/1,GDMA_DST0/1,and
GDMA_TCNT0/1
registers
automatically when transfer is complete.
[18]
TC
Terminal Count
1’b0 = Channel does not expire
1’b1 = Channel expires; this bit is set only by GDMA hardware, and clear
by software to write logic 0.
TC [18] is the GDMA interrupt flag. TC [18] or GDMATERR[20] will
generate interrupt
[17]
BLOCK
[19]
Bus Lock
1’b0 = Unlocks the bus during the period of transfer
1’b1 = Locks the bus during the period of transfer
SOFTREQ
Software Triggered GDMA Request
Software can request the GDMA transfer service by setting this bit to 1.
This bit is automatically cleared by hardware when the transfer is
completed. This bit is available only while GDMAMS [3:2] register bits are
set on software mode (memory to memory).
[15]
DM
Demand Mode
1’b0 = Normal external GDMA mode
1’b1 = When this bit is set to 1, the external GDMA operation is speeded
up. When external GDMA device is operating in the demand mode, the
GDMA transfers data as long as the external GDMA request signal
nXDREQ is active. The amount of data transferred depends on how long
the nXDREQ is active. When the nXDREQ is active and GDMA gets the
bus in Demand mode, DMA holds the system bus until the nXDREQ
signal becomes non-active. Therefore, the period of the active nXDREQ
signal should be carefully tuned such that the entire operation does not
exceed an acceptable interval (for example, in a DRAM refresh
operation).
[14]
Reserved
[16]
-
- 163 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
TWS
Transfer Width Select
00 = One byte (8 bits) is transferred for every GDMA operation
01 = One half-word (16 bits) is transferred for every GDMA operation
10 = One word (32 bits) is transferred for every GDMA operation
11 = Reserved
The GDMA_SCRB and GDMA_DSTB should be alignment under the
TWS selection
[11]
SBMS
Single/Block Mode Select
1’b0 = Selects single mode. It requires an external GDMA request for
every incurring GDMA operation.
1’b1 = Selects block mode. It requires a single external GDMA request
during the atomic GDMA operation. An atomic GDMA operation is defined
as the sequence of GDMA operations until the transfer count register
reaches zero.
[10]
Reserved
[13:12]
-
BME
Burst Mode Enable
1’b0 = Disables the 4-data burst mode
1’b1 = Enables the 4-data burst mode
FF there are 16 words to be transferred, and BME [9]=1, the
GDMA_TCNT should be 0x04;
However, if BME [9]=0, the GDMA_TCNT should be 0x10.
SIEN
Stop Interrupt Enable
1’b0 = Do not generate an interrupt when the GDMA operation is
stopped
1’b1 = Interrupt is generated when the GDMA operation is stopped
SAFIX
Source Address Fixed
1’b0 = Source address is changed during the GDMA operation
1’b1 = Do not change the destination address during the GDMA
operation. This feature can be used when data were transferred from a
single source to multiple destinations.
[6]
DAFIX
Destination Address Fixed
1’b0 = Destination address is changed during the GDMA operation
1’b1 = Do not change the destination address during the GDMA
operation. This feature can be used when data were transferred from
multiple sources to a single destination.
[5]
SADIR
Source Address Direction
1’b0 = Source address is incremented successively
1’b1 = Source address is decremented successively
[9]
[8]
[7]
- 164 -
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
[4]
Destination Address Direction
1’b0 = Destination address is incremented successively
1’b1 = Destination address is decremented successively
DADIR
[3:2]
GDMAMS
GDMA Mode Select
00 = Software mode (memory-to-memory)
01 = External nXDREQ mode for external device
10 = Reserved
11 = Reserved
[1]
Reserved
-
GDMAEN
GDMA Enable
1’b0 = Disables the GDMA operation
1’b1 = Enables the GDMA operation; this bit will be clear automatically
when the transfer is complete on AUTOIEN [19] register bit is on Disable
mode.
[0]
Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1)
The GDMA channel starts reading its data from the source address as defined in this source base
address register.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GDMA_SRCB0
0xFFF0_4004
R/W
Channel 0 Source Base Address Register
0x0000_0000
GDMA_SRCB1
0xFFF0_4024
R/W
Channel 1 Source Base Address Register
0x0000_0000
31
30
29
23
22
21
15
14
13
7
6
5
BITS
[31:0]
28
27
SRC_BASE_ADDR [31:24]
20
19
SRC_BASE_ADDR [23:16]
12
11
SRC_BASE_ADDR [15:8]
4
3
SRC_BASE_ADDR [7:0]
26
25
24
18
17
16
10
9
8
2
1
0
DESCRIPTIONS
SRC_BASE_ADDR
32-bit Source Base Address
- 165 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA_DSTB1)
Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1)
The GDMA channel starts writing its data to the destination address as defined in this destination base
address register. During a block transfer, the GDMA determines successive destination addresses by
adding to or subtracting from the destination base address.
REGISTER
ADDRESS
R/W
GDMA_DSTB0
0xFFF0_4008
R/W
GDMA_DSTB1
0xFFF0_4028
R/W
31
30
29
23
22
21
15
14
13
7
6
5
RESET VALUE
Channel 0 Destination Base Address
Register
Channel 1 Destination Base Address
Register
28
27
DST_BASE_ADDR [31:24]
20
19
DST_BASE_ADDR [23:16]
12
11
DST_BASE_ADDR [15:8]
4
3
DST_BASE_ADDR [7:0]
BITS
[31:0]
DESCRIPTION
0x0000_0000
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
DESCRIPTIONS
DST_BASE_ADDR
32-bit Destination Base Address
Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1)
REGISTER
ADDRESS
R/W
GDMA_TCNT0
0xFFF0_400C
R/W
Channel 0 Transfer Count Register
0x0000_0000
GDMA_TCNT1
0xFFF0_402C
R/W
Channel 1 Transfer Count Register
0x0000_0000
31
30
29
23
22
21
15
14
13
7
6
5
DESCRIPTION
28
27
Reserved
20
19
TFR_CNT [23:16]
12
11
TFR_CNT [15:8]
4
3
TFR_CNT [7:0]
- 166 -
RESET VALUE
26
25
24
18
17
16
10
9
8
2
1
0
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:24]
Reserved
-
[23:0]
TFR_CNT
The TFR_CNT represents the required number of GDMA
transfers. The maximum transfer count is 16M –1.
Channel 0/1 Current Source Register (GDMA_CSRC0, GDMA_CSRC1)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GDMA_CSRC0
0xFFF0_4010
R
Channel 0 Current Source Address
Register
0x0000_0000
GDMA_CSRC1
0xFFF0_4030
R
Channel 1 Current Source Address
Register
0x0000_0000
31
30
23
22
15
14
7
6
29
28
27
CURRENT_SRC_ADDR [31:24]
21
20
19
CURRENT_SRC_ADDR [23:16]
13
12
11
CURRENT_SRC_ADDR [15:8]
5
4
3
CURRENT_SRC_ADDR [7:0]
BITS
[31:0]
26
25
24
18
17
16
10
9
8
2
1
0
DESCRIPTIONS
CURRENT_SRC_ADDR
The 32-bit Current Source Address indicates the source
address where the GDMA transfer is just occurring.
During a block transfer, the GDMA determines the
successive source addresses by adding to or subtracting
from the source base address. Depending on the settings
you make to the control register, the current source
address will remain the same or will be incremented or
decremented.
- 167 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GDMA_CDST0
0xFFF0_4014
R
Channel 0 Current Destination Address
Register
0x0000_0000
GDMA_CDST1
0xFFF0_4034
R
Channel 1 Current Destination Address
Register
0x0000_0000
31
30
23
22
15
14
7
6
29
28
27
CURRENT_DST_ADDR [31:24]
21
20
19
CURRENT_DST_ADDR [23:16]
13
12
11
CURRENT_DST_ADDR [15:8]
5
4
3
CURRENT_DST_ADDR [7:0]
BITS
[31:0]
26
25
24
18
17
16
10
9
8
2
1
0
DESCRIPTIONS
CURRENT_DST_ADDR
The 32-bit Current Destination Address indicates the
destination address where the GDMA transfer is just
occurring. During a block transfer, the GDMA determines
the successive destination addresses by adding to or
subtracting from the destination base address. Depending
on the settings you make to the control register, the current
destination address will remain the same or will be
incremented or decremented.
Channel 0/1 Current Transfer Count Register (GDMA_CTCNT0,
GDMA_CTCNT1)
The Current transfer count register indicates the number of transfer being performed.
DESCRIPTION
RESET
VALUE
REGISTER
ADDRESS
R/W
GDMA_CTCNT0
0xFFF0_4018
R
Channel 0 Current Transfer Count Register
0x0000_0000
GDMA_CTCNT1
0xFFF0_4038
R
Channel 1 Current Transfer Count Register
0x0000_0000
- 168 -
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
15
14
7
6
21
20
19
CURENT_TFR_CNT [23:16]
13
12
11
CURRENT_TFR_CNT [15:8]
5
4
3
CURRENT_TFR_CNT [7:0]
BITS
DESCRIPTIONS
[31:24]
Reserved
[23:0]
CURRENT_TFR_CNT
Current Transfer Count register
The current transfer count register indicates the number of
transfer being performed
- 169 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.7
USB Host Controller
The Universal Serial Bus (USB) is a low-cost, low-to-mid-speed peripheral interface standard
intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a highbandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange
between a Host Controller and a network of peripheral devices. The attached peripherals share USB
bandwidth through a host-scheduled, token-based protocol. Peripherals may be attached, configured,
used, and detached, while the host and other peripherals continue operation (i.e. hot plug and unplug
is supported).
A major design goal of the USB standard was to allow flexible, plug-and-play networks of USB
devices. In any USB network, there will be only one host, but there can be many devices and hubs.
The USB Host Controller has the following features:
• Open Host Controller Interface (OHCI) Revision 1.1 compatible.
• USB Revision 1.1 compatible
• Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices.
• Handles all the USB protocol.
• Built-in DMA for real-time data transfer
• Multiple low power modes for efficient power management
7.7.1
USB Host Functional Description
7.7.1.1. AHB Interface
The OpenHCI Host Controller is connected to the system by the AHB bus. The design requires both
master and slave bus operations. As a master, the Host Controller is responsible for running cycles
on the AHB bus to access EDs and TDs as well as transferring data between memory and the local
data buffer. As a slave, the Host Controller monitors the cycles on the AHB bus and determines when
to respond to these cycles. Configuration and non-real-time control access to the Host Controller
operational registers are through the AHB bus slave interface.
7.7.1.2. Host Controller
List Processing
The List Processor manages the data structures from the Host Controller Driver and coordinates all
activity within the Host Controller.
Frame Management
Frame Management is responsible for managing the frame specific tasks required by the USB
specification and the OpenHCI specification. These tasks are:
1)
2)
3)
4)
Management of the OpenHCI frame specific Operational Registers
Operation of the Largest Data Packet Counter.
Performing frame qualifications on USB Transaction requests to the SIE.
Generate SOF token requests to the SIE.
- 170 -
W90N745CD/W90N745CDG
Interrupt Processing
Interrupts are the communication method for HC-initiated communication with the Host Controller
Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific
event sets a specific bit in the HcInterruptStatus register.
Host Controller Bus Master
The Host Controller Bus Master is the central block in the data path. The Host Controller Bus Master
coordinates all access to the AHB Interface. There are two sources of bus mastering within Host
Controller: the List Processor and the Data Buffer Engine.
Data Buffer
The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a combination
of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword AHB Holding
Register.
7.7.1.3. USB Interface
The USB interface includes the integrated Root Hub with two external ports, Port 1 and Port 2 as well
as the Serial Interface Engine (SIE) and USB clock generator. The interface combines responsibility
for executing bus transactions requested by the HC as well as the hub and port management
specified by USB.
7.7.2
USB Host Controller Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
HcRevision
0xFFF0_5000
R
HcControl
0xFFF0_5004 R/W Host Controller Control Register
0x0000_0000
HcCommandStatus
0xFFF0_5008 R/W Host Controller Command Status Register
0x0000_0000
HcInterruptStatus
0xFFF0_500C R/W Host Controller Interrupt Status Register
0x0000_0000
HcInterruptEnbale
0xFFF0_5010 R/W Host Controller Interrupt Enable Register
0x0000_0000
HcInterruptDisbale
0xFFF0_5014 R/W Host Controller Interrupt Disable Register
0x0000_0000
HcHCCA
0xFFF0_5018 R/W
Host Controller
Register
Communication
HcPeriodCurrentED
0xFFF0_501C R/W
Host Controller
Register
Period
HcControlHeadED
0xFFF0_5020 R/W Host Controller Control Head ED Register
HcControlCurrentED
0xFFF0_5024 R/W
HcBulkHeadEd
0xFFF0_5028 R/W Host Controller Bulk Head ED Register
0x0000_0000
HcBulkCurrentED
0xFFF0_502C R/W Host Controller Bulk Current ED Register
0x0000_0000
OpenHCI Registers
Host Controller Revision Register
Host Controller
Register
- 171 -
Control
0x0000_0010
Area
Current
Current
ED
ED
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
OpenHCI Registers
HcDoneHeadED
0xFFF0_5030 R/W Host Controller Done Head Register
HcFmInterval
0xFFF0_5034 R/W Host Controller Frame Interval Register 0x0000_2EDF
HcFrameRemaining
0xFFF0_5038 R
Host Controller
Register
HcFmNumber
0xFFF0_503C R
Host
Controller
Register
HcPeriodicStart
0xFFF0_5040 R/W Host Controller Periodic Start Register 0x0000_0000
HcLSThreshold
0xFFF0_5044 R/W
Host Controller Low Speed Threshold
0x0000_0628
Register
HcRhDescriptorA
0xFFF0_5048 R/W
Host Controller Root Hub Descriptor A
0x0100_0002
Register
HcRhDescriptorB
0xFFF0_504C R/W
Host Controller Root Hub Descriptor B
0x0000_0000
Register
HcRhStatus
0xFFF0_5050 R/W
Host Controller
Register
HcRhPortStatus [1]
0xFFF0_5054 R/W
Host Controller Root Hub Port Status
0x0000_0000
[1]
HcRhPortStatus [2]
0xFFF0_5058 R/W
Host Controller Root Hub Port Status
0x0000_0000
[2]
Frame
Remaining
Frame
Root
Number
Hub
Status
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
USB Configuration Registers
TestModeEnable
0xFFF0_5200 R/W USB Test Mode Enable Register
OperationalModeEnabl
USB
Operational
0xFFF0_5204 R/W
e
Register
- 172 -
Mode
Enable
0x0XXX_XXXX
0x0000_0000
W90N745CD/W90N745CDG
Host Controller Revision Register
REGISTER
OFFSET
ADDRESS
R/W
HcRevision
0xFFF0_5000
R
31
30
29
23
22
21
15
14
13
7
6
5
DESCRIPTION
RESET VALUE
Host Controller Revision Register
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
Revision
BITS
0x0000_0010
26
25
24
18
17
16
10
9
8
2
1
0
DESCRIPTION
[31:8]
Reserved
Reserved. Read/Write 0's
[7:0]
Revision
Indicates the Open HCI Specification revision number implemented
by the Hardware.
Host Controller supports 1.0 specification.
(X.Y = XYh)
Host Controller Control Register
REGISTER
ADDRESS
HcControl
0xFFF0_5004
31
30
23
22
15
14
7
6
HCFS
29
21
13
Reserved
5
BLE
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Control Register
28
27
Reserved
20
19
Reserved
12
11
4
CLE
3
ISE
- 173 -
0x0000_0000
26
25
24
18
17
16
10
RWCE
2
PLE
9
RWC
1
8
IR
0
CBR
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTION
[31:11]
Reserved
[10]
RWCE
Reserved. Read/Write 0's
RemoteWakeupConnectedEnable
If a remote wakeup signal is supported, this bit enables that operation.
Since there is no remote wakeup signal supported, this bit is ignored.
RemoteWakeupConnected
[9]
RWC
This bit indicated whether the HC supports a remote wakeup signal. This
implementation does not support any such signal. The bit is hard-coded to
‘0.’
InterruptRouting
[8]
INR
This bit is used for interrupt routing:
0: Interrupts routed to normal interrupt mechanism (INT).
1: Interrupts routed to SMI.
HostControllerFunctionalState
This field sets the Host Controller state. The Controller may force a state
change from USB SUSPEND to USB RESUME after detecting resume
signaling from a downstream port. States are:
[7:6]
HCFS
00: USB RESET
01: USBRESUME
10: USBOPERATIONAL
11: USBSUSPEND
[5]
[4]
BLE
BulkListEnable
When set this bit enables processing of the Bulk list.
CLE
Control Listenable
When set this bit enables processing of the Control list.
Isochronous Enable
[3]
ISE
When clear, this bit disables the Isochronous List when the Periodic List is
enabled (so Interrupt EDs may be serviced). While processing the
Periodic List, the Host Controller will check this bit when it finds an
isochronous ED.
Periodic Listenable
[2]
PLE
When set, this bit enables processing of the Periodic (interrupt and
isochronous) list. The Host Controller checks this bit prior to attempting
any periodic transfers in a frame.
ControlBulkServiceRatio
[1:0]
CBR
Specifies the number of Control Endpoints serviced for every Bulk
Endpoint. Encoding is N-1 where N is the number of Control Endpoints
(i.e. ‘00’ = 1 Control Endpoint; ‘11’ = 3 Control Endpoints)
- 174 -
W90N745CD/W90N745CDG
- 175 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Host Controller Command Status Register
REGISTER
ADDRESS
HcCommandStatus
0xFFF0_5008
R/W
RESET
VALUE
DESCRIPTION
R/W Host Controller Command Status Register
31
30
29
28
23
22
21
15
14
20
Reserved
13
12
7
6
5
4
Reserved
BITS
0x0000_0000
27
26
25
24
Reserved
19
18
17
16
10
9
8
2
BLF
1
CLF
0
HCR
11
Reserved
3
OCR
DESCRIPTION
[31:18]
Reserved
[17:16]
SOC
[15:4]
Reserved
[3]
OCR
Reserved
ScheduleOverrunCount
This field is increment every time the SchedulingOverrun bit in
HcInterruptStatus is set. The count wraps from ‘11’ to ‘00.’
Reserved. Read/Write 0's
OwnershipChangeRequest
When set by software, this bit sets the OwnershipChange field in
HcInterruptStatus. The bit is cleared by software.
BulkListFilled
[2]
BLF
Set to indicate there is an active ED on the Bulk List. The bit may be
set by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Bulk List.
ControlListFilled
[1]
CLF
Set to indicate there is an active ED on the Control List. It may be set
by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Control List.
HostControllerReset
[0]
HCR
This bit is set to initiate the software reset. This bit is cleared by the
Host Controller, upon completed of the reset operation.
- 176 -
W90N745CD/W90N745CDG
Host Controller Interrupt Status Register
All bits are set by hardware and cleared by software.
REGISTER
ADDRESS
HcInterruptStatus 0xFFF0_500C
R/W
DESCRIPTION
RESET VALUE
R/W
Host Controller Interrupt Status Register
0x0000_0000
31
30
29
28
Reserved
23
OCH
22
21
20
15
14
13
7
Reserved
6
RHSC
5
FNO
19
Reserved
12
11
Reserved
4
3
URE
RDT
BITS
[31]
27
26
25
24
Reserved
18
17
16
10
9
8
2
SOF
1
WDH
0
SCO
DESCRIPTION
Reserved
Reserved
OwnershipChange
[30]
OCH
[29:7]
This bit is set when the OwnershipChangeRequest bit of
HcCommandStatus is set.
Reserved
RootHubStatusChange
[6]
RHSC
[5]
FNO
[4]
URE
[3]
RDT
This bit is set when the content of HcRhStatus or the content of any
HcRhPortStatus register has changed.
FrameNumberOverflow
Set when bit 15 of FrameNumber changes value.
UnrecoverableError
This event is not implemented and is hard-coded to ‘0.’
ignored.
Writes are
ResumeDetected
Set when Host Controller detects resume signaling on a downstream
port.
StartOfFrame
[2]
SOF
Set when the Frame Management block signals a ‘Start of Frame’
event.
- 177 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
WritebackDoneHead
[1]
WDH
Set after the Host
HccaDoneHead.
Controller
has
written
HcDoneHead
to
SchedulingOverrun
[0]
SCHO
Set when the List Processor determines a Schedule Overrun has
occurred.
Host Controller Interrupt Enable Register
Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit
unchanged.
REGISTER
ADDRESS
HcInterruptEnable
0xFFF0_5010
31
30
29
MIE
23
OCE
22
21
15
14
13
7
Reserved
6
RHCE
5
FNOE
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Interrupt Enable Register
28
27
26
Reserved
19
18
Reserved
12
11
10
Reserved
4
3
2
UREE
RDTE
SOFE
BITS
20
0x0000_0000
25
24
17
16
9
8
1
WDHE
0
SCHOE
DESCRIPTION
MasterInterruptEnable
[31]
MIE
This bit is a global interrupt enable. A write of ‘1’ allows interrupts to
be enabled via the specific enable bits listed above.
OwnershipChangeEnable
[30]
OCE
0: Ignore
1: Enable interrupt generation due to Ownership Change.
[29:7]
Reserved
Reserved. Read/Write 0's
RootHubStatusChangeEnable
[6]
RHSCE
0: Ignore
1: Enable interrupt generation due to Root Hub Status Change.
- 178 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
FrameNumberOverflowEnable
[5]
FNOE
0: Ignore
1: Enable interrupt generation due to Frame Number Overflow.
[4]
UnrecoverableErrorEnable
UREE
This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable
[3]
RDTE
0: Ignore
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable
[2]
SOFE
0: Ignore
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable
[1]
WDHE
0: Ignore
1: Enable interrupt generation due to Write-back Done Head.
SchedulingOverrunEnable
[0]
SCHOE
0: Ignore
1: Enable interrupt generation due to Scheduling Overrun.
Host Controller Interrupt Disable Register
Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit
unchanged.
REGISTER
ADDRESS
HcInterruptEnable
0xFFF0_5014
31
30
MIE
OCE
23
22
29
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Interrupt Disable Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
SOFE
1
WDHE
0
SCHOE
Reserved
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
4
Reserved
RHSCE
FNOE
UREE
3
RDTE
- 179 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
[31]
DESCRIPTION
MIE
MasterInterruptEnable
Global interrupt disable. A write of ‘1’ disables all interrupts.
OwnershipChangeEnable
[30]
OCE
0: Ignore
1: Disable interrupt generation due to Ownership Change.
[29:7]
Reserved
Reserved. Read/Write 0's
RootHubStatusChangeEnable
[6]
RHSCE
0: Ignore
1: Disable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable
[5]
FNOE
0: Ignore
1: Disable interrupt generation due to Frame Number Overflow.
[4]
UREE
UnrecoverableErrorEnable
This event is not implemented. All writes to this bit will be ignored.
ResumeDetectedEnable
[3]
RDTE
0: Ignore
1: Disable interrupt generation due to Resume Detected.
StartOfFrameEnable
[2]
SOFE
0: Ignore
1: Disable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable
[1]
WDHE
0: Ignore
1: Disable interrupt generation due to Write-back Done Head.
SchedulingOverrunEnable
[0]
SCHOE
0: Ignore
1: Disable interrupt generation due to Scheduling Overrun.
- 180 -
W90N745CD/W90N745CDG
Host Controller Communication Area Register
REGISTER
ADDRESS
R/W
HcHCCA
0xFFF0_5018
R/W
31
30
DESCRIPTION
Host
Controller
Register
29
28
Communication
RESET VALUE
Area
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
Reserved
2
1
0
HCCA
23
22
21
20
15
14
13
12
7
6
5
4
HCCA
HCCA
BITS
DESCRIPTION
HCCA
[31:8]
[7:0]
HCCA
Pointer to HCCA base address.
Reserved
Reserved
Host Controller Period Current ED Register
REGISTER
ADDRESS
HcPeriodCurretED
31
0xFFF0_501C
30
29
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Period Current ED Register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PCED
23
22
21
20
PCED
15
14
13
12
PCED
7
6
5
4
PCED
BITS
DESCRIPTION
[31:4]
PCED
[3:0]
Reserved
PeriodCurrentED. Pointer to the current Periodic List ED.
Reserved. Read/Write 0's
- 181 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Host Controller Control Head ED Register
REGISTER
ADDRESS
HcControlHeadED
31
0xFFF0_5020
30
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Control Head ED Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CHED
23
22
21
20
CHED
15
14
13
12
7
6
5
4
CHED
CHED
Reserved
BITS
DESCRIPTION
ControlHeadED
[31:4]
CHED
[3:0]
Reserved
Pointer to the Control List Head ED.
Reserved
Host Controller Control Current ED Register
REGISTER
OFFSET
ADDRESS
HcControlCurrentED
0xFFF0_5024
31
30
29
R/W
RESET
VALUE
DESCRIPTION
R/W Host Controller Control Current ED Register 0x0000_0000
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CCED
23
22
21
20
CCED
15
14
13
12
CCED
7
6
5
4
CCED
BITS
Reserved
DESCRIPTION
[31:4]
CCED
[3:0]
Reserved
ControlCurrentED
Pointer to the current Control List ED.
Reserved. Read/Write 0's
- 182 -
W90N745CD/W90N745CDG
Host Controller Bulk Head ED Register
REGISTER
OFFSET ADDRESS
HcBulkHEADED
0xFFF0_5028
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Bulk Head ED Register
31
30
29
28
23
22
21
20
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
BHED
BHED
15
14
13
12
BHED
7
6
5
4
BHED
Reserved
BITS
DESCRIPTION
[31:4]
BHED
[3:0]
Reserved
BulkHeadED. Pointer to the Bulk List Head ED.
Reserved. Read/Write 0's
Host Controller Bulk Current ED Register
REGISTER
OFFSET ADDRESS R/W
HcBulkCurrentED
31
0xFFF0_502C
30
29
DESCRIPTION
RESET VALUE
R/W Host Controller Bulk Current ED Register 0x0000_0000
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
BCED
23
22
21
20
BCED
15
14
13
12
BCED
7
6
5
4
BCED
BITS
Reserved
DESCRIPTION
[31:4]
BCED
[3:0]
Reserved
BulkCurrentED. Pointer to the current Bulk List ED.
Reserved. Read/Write 0's
- 183 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Host Controller Done Head Register
REGISTER
ADDRESS
HcDoneHead
0xFFF0_5030
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Done Head Register
31
30
29
28
23
22
21
20
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
DOHD
DOHD
15
14
13
12
DOHD
7
6
5
4
DOHD
Reserved
BITS
DESCRIPTION
[31:4]
DOHD
[3:0]
Reserved
DoneHead. Pointer to the current Done List Head ED.
Reserved. Read/Write 0's
Host Controller Frame Interval Register
REGISTER
ADDRESS
HcFmInterval
0xFFF0_5034
31
30
29
R/W
DESCRIPTION
R/W Host Controller Frame Interval Register
28
FINTVT
23
RESET VALUE
27
0x0000_2EDF
26
25
24
18
17
16
10
9
8
2
1
0
FSLDP
22
21
20
19
FSLDP
15
14
13
12
11
Reserved
7
FINTV
6
5
4
3
FINTV
- 184 -
W90N745CD/W90N745CDG
BITS
DESCRIPTION
31
FrameIntervalToggle
FINTVT
This bit is toggled by HCD when it loads a new value into Frame Interval.
FSLargestDataPacket
[30:16]
FSLDP
[15:14]
Reserved
[13:0]
FINTV
This field specifies a value that is loaded into the Largest Data Packet
Counter at the beginning of each frame.
Reserved. Read/Write 0's
Frame Interval
This field specifies the length of a frame as (bit times - 1). For 12,000 bit
times in a frame, a value of 11,999 is stored here.
Host Controller Frame Remaining Register
REGISTER
ADDRESS
R/W
HcFmInterval
0xFFF0_5038
R
31
30
29
DESCRIPTION
RESET VALUE
Host Controller Frame Remaining Register 0x0000_0000
28
27
FRMT
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
FRM
6
5
4
3
FRM
BITS
DESCRIPTION
[31]
FRMT
[30:14]
Reserved
FrameRemainingToggle
Loaded with FrameIntervalToggle when Frame Remaining is loaded.
Reserved. Read/Write 0's
Frame Remaining
[13:0]
FRM
When the Host Controller is in the USBOPERATIONAL state, this 14-bit field
decrements each 12 MHz clock period. When the count reaches 0, (end of
frame) the counter reloads with Frame Interval. In addition, the counter
loads when the Host Controller transitions into USBOPERATIONAL.
- 185 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Host Controller Frame Number Register
REGISTER
ADDRESS
R/W
HcFmNumber
0xFFF0_503C
R
DESCRIPTION
RESET VALUE
Host Controller Frame Number Register
31
30
29
28
23
22
21
20
27
0x0000_0000
26
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
19
Reserved
15
14
13
12
FRMN
7
6
5
4
FRMN
BITS
DESCRIPTION
[31:16]
Reserved
[15:0]
FRMN
Reserved. Read/Write 0's
FrameNumber
This 16-bit incrementing counter field is incremented coincident with the
loading of FrameRemaining. The count rolls over from ‘000Fh’ to ‘0h.’
Host Controller Periodic Start Register
REGISTER
ADDRESS
HcPeriodicStart
0xFFF0_5040
31
30
29
R/W
DESCRIPTION
RESET VALUE
R/W Host Controller Periodic Start Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
PERST
7
6
5
4
3
PERST
- 186 -
W90N745CD/W90N745CDG
BITS
DESCRIPTION
[31:14]
Reserved
Reserved. Read/Write 0's
PeriodicStart
[13:0]
PERST
This field contains a value used by the List Processor to determine where in a
frame the Periodic List processing must begin.
Host Controller Low Speed Threshold Register
REGISTER
ADDRESS
R/W
HcLSThreshold
0xFFF0_5044
R/W
31
30
23
22
15
14
DESCRIPTION
Host Controller
Register
29
28
27
Reserved
20
19
Reserved
12
11
21
13
Reserved
6
5
7
Low
4
3
LsTreshold
BITS
Speed
RESET VALUE
Threshold
0x0000_0628
26
25
24
18
17
16
10
9
LsThreshold
2
1
8
0
DESCRIPTION
[31:12]
Reserved
Rsvd. Read/Write 0's
[11:0]
LsTreshold
LSThreshold
This field contains a value used by the Frame Management block to determine
whether or not a low speed transaction can be started in the current frame.
Host Controller Root Hub Descriptor A Register
This register is only reset by a power-on reset. It is written during system initialization to configure the
Root Hub. This bit should not be written during normal operation.
REGISTER
ADDRESS
R/W
HcRhDescriptorA
0xFFF0_5048
R/W
DESCRIPTION
RESET
VALUE
Host Controller Root Hub Descriptor A
0x0100.0002
Register
- 187 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
POTPGT
23
22
21
20
19
Reserved
15
14
13
Reserved
7
6
5
12
11
10
9
8
OCPM
OCPM
DEVT
NPSW
PSWM
3
2
1
0
4
NDSP
BITS
DESCRIPTION
PowerOnToPowerGoodTime
[31:24]
[23:13]
POTPGT
Reserved
This field value is represented as the number of 2 ms intervals, which ensuring
that the power switching is effective within 2 ms. Only bits [25:24] is implemented
as R/W. The remaining bits are read only as ‘0’. It is not expected that these bits
be written to anything other than 1h, but limited adjustment is provided. This field
should be written to support system implementation. This field should always be
written to a non-zero value.
Reserved. Read/Write 0's
NoOverCurrentProtection
[12]
NOCP
Global over-current reporting implemented in HYDRA-2. This bit should be written
to support the external system port over-current implementation.
0 = Over-current status is reported
1 = Over-current status is not reported
OverCurrentProtectionMode
[11]
OCPM
[10]
DEVT
Global over-current reporting implemented in HYDRA-2. This bit should be written
0 and is only valid when NoOverCurrentProtection is cleared.
0 = Global Over-Current
1 = Individual Over-Current
DeviceType
table of none-4is not a compound device.
NoPowerSwitching
[9]
NPSW
Global power switching implemented in HYDRA-2. This bit should be written to
support the external system port power switching implementation.
0 = Ports are power switched.
1 = Ports are always powered on.
PowerSwitchingMode
[8]
PSWM
[7:0]
NDSP
Global power switching mode implemented in HYDRA-2. This bit is only valid
when NoPowerSwitching is cleared. This bit should be written '0'.
0 = Global Switching
1 = Individual Switching
NumberDownstreamPorts
table of none-4 supports two downstream ports.
- 188 -
W90N745CD/W90N745CDG
Host Controller Root Hub Descriptor B Register
This register is only reset by a power-on reset. It is written during system initialization to configure the
Root Hub. These bits should not be written during normal operation.
REGISTER
ADDRESS
R/W
R/W Host Controller Root Hub Descriptor B Register 0x0000_0000
HcRhDescriptorB 0xFFF0_504C
31
30
RESET
VALUE
DESCRIPTION
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PPCM
23
22
21
20
PPCM
15
14
13
12
DEVRM
7
6
5
4
DEVRM
BITS
DESCRIPTION
PortPowerControlMask
[31:16]
PPCM
Global-power switching. This field is only valid if NoPowerSwitching is
cleared and PowerSwitchingMode is set (individual port switching). When
set, the port only responds to individual port power switching commands
(Set/ClearPortPower). When cleared, the port only responds to global power
switching commands (Set/ClearGlobalPower).
0 = Device not removable
1 = Global-power mask
Port Bit relationship - Unimplemented ports are reserved, read/write '0'.
0 : Reserved
1 : Port 1
2 : Port 2
...
15 : Port 15
DeviceRemoveable
table of none-4 ports default to removable devices.
0 = Device not removable
1 = Device removable
[15:0]
DEVRM
Port Bit relationship
0 : Reserved
1 : Port 1
2 : Port 2
...
15 : Port 15
Unimplemented ports are reserved, read/write '0'.
- 189 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Host Controller Root Hub Status Register
This register is reset by the USBRESET state.
REGISTER
OFFSET
ADDRESS
HcRhStstus
0xFFF0_5050
31
30
29
R/W
RESET
VALUE
DESCRIPTION
R/W Host Controller Root Hub Status Register
28
27
26
25
0x0000_0000
24
Reserved
23
22
21
20
19
18
Reserved
15
14
13
12
DRWE
7
11
10
17
16
OVIC
LPSC
9
8
Reserved
6
5
4
3
2
Reserved
BITS
1
0
OVRCI
LOPS
DESCRIPTION
(Write) ClearRemoteWakeupEnable
[31]
CRWE
[30:18]
Reserved
[17]
OVIC
Writing a '1' to this bit clears DeviceRemoteWakeupEnable. Writing
a '1' has no effect.
Reserved. Read/Write 0's
OverCurrentIndicatorChange
This bit is set when OverCurrentIndicator changes. Writing a '1'
clears this bit. Writing a '0' has no effect.
(Read) LocalPowerStatusChange
Not supported. Always read '0'.
[16]
LPSC
(Write) SetGlobalPower
Write a '1' issues a SetGlobalPower command to the ports. Writing a
'0' has no effect.
(Read) DeviceRemoteWakeupEnable
[15]
DRWE
This bit enables ports' ConnectStatusChange as a remote wakeup
event.
0 = disabled
1 = enabled
(Write) SetRemoteWakeupEnable
Writing a '1' sets DeviceRemoteWakeupEnable. Writing a '0' has no
effect.
[14:2]
Reserved
Reserved. Read/Write 0's
- 190 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
OverCurrentIndicator
[1]
This bit reflects the state of the OVRCUR pin. This field is only valid
if NoOverCurrentProtection and OverCurrentProtectionMode are
cleared.
0 = No over-current condition
1 = Over-current condition
OVRCI
(Read) LocalPowerStatus
Not Supported. Always read '0'.
[0]
LOPS
(Write) ClearGlobalPower
Writing a '1' issues a ClearGlobalPower command to the ports.
Writing a '0' has no effect.
Host Controller Root Hub Port Status [1][2]
This register is reset by the USBRESET state.
ADDRESS
HcRhPortStatus [1]
0xFFF0_5054
R/W Host Controller Root Hub Port Status [1]
0x0000_0000
HcRhPortStatus [2]
0xFFF0_5058
R/W Host Controller Root Hub Port Status [2]
0x0000_0000
31
23
15
30
22
Reserved
14
R/W
RESET
VALUE
REGISTER
DESCRIPTION
29
28
21
Reserved
20
19
13
27
26
6
Reserved
5
18
17
16
POCIC
PSSC
PESC
CSC
12
11
10
9
4
3
2
1
8
PPS
0
SPR
CPS
SPS
SPE
DRM
LSDA
BITS
[31:21]
24
PRSC
Reserved
7
25
DESCRIPTION
Reserved
Reserved. Read/Write 0's
PortResetStatusChange
[20]
PRSC
This bit indicates that the port reset signal has completed.
0 = Port reset is not complete.
1 = Port reset is complete.
- 191 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
PortOverCurrentIndicatorChange
[19]
POCIC
This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit.
Writing a '0' has no effect.
PortSuspendStatusChange
[18]
PSSC
This bit indicates the completion of the selective resume sequence for the port.
0 = Port is not resumed.
1 = Port resume is complete.
PortEnableStatusChange
[17]
PESC
This bit indicates that the port has been disabled due to a hardware event
(cleared PortEnableStatus).
0 = Port has not been disabled.
1 = PortEnableStatus has been cleared.
ConnectStatusChange
[16]
CSC
This bit indicates a connect or disconnect event has been detected. Writing a '1'
clears this bit. Writing a '0' has no effect.
0 = No connect/disconnect event.
1 = Hardware detection of connect/disconnect event.
Note: If DeviceRemoveable is set, this bit resets to '1'.
[15:10]
Reserved
Reserved. Read/Write 0's
(Read) LowSpeedDeviceAttached
[9]
LSDA
This bit defines the speed (and bud idle) of the attached device. It is only valid
when CurrentConnectStatus is set.
0 = Full Speed device
1 = Low Speed device
(Write) ClearPortPower
Writing a '1' clears PortPowerStatus. Writing a '0' has no effect
(Read) PortPowerStatus
[8]
PPS
This bit reflects the power state of the port regardless of the power switching
mode.
0 = Port power is off.
1 = Port power is on.
Note: If NoPowerSwitching is set, this bit is always read as '1'.
(Write) SetPortPower
Writing a '1' sets PortPowerStatus. Writing a '0' has no effect.
[7:5]
Reserved
Reserved. Read/Write 0's
- 192 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
(Read) PortResetStatus
[4]
SPR
0 = Port reset signal is not active.
1 = Port reset signal is active.
(Write) SetPortReset
Writing a '1' sets PortResetStatus. Writing a '0' has no effect.
(Read) PortOverCurrentIndicator
[3]
CPS
table of none-2 supports global over-current reporting. This bit reflects the state
of the OVRCUR pin dedicated to this port. This field is only valid if
NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.
0 = No over-current condition
1 = Over-current condition
(Write) ClearPortSuspend
Writing a '1' initiates the selective resume sequence for the port. Writing a '0'
has no effect.
(Read) PortSuspendStatus
[2]
SPS
0 = Port is not suspended
1 = Port is selectively suspended
(Write) SetPortSuspend
Writing a '1' sets PortSuspendStatus. Writing a '0' has no effect.
(Read) PortEnableStatus
[1]
SPE
0 = Port disabled.
1 = Port enabled.
(Write) SetPortEnable
Writing a '1' sets PortEnableStatus. Writing a '0' has no effect.
(Read) CurrentConnectStatus
0 = No device connected.
1 = Device connected.
[0]
DRM
NOTE: If DeviceRemoveable is set (not removable) this bit is always '1'.
(Write) ClearPortEnable
Writing '1' a clears PortEnableStatus. Writing a '0' has no effect.
- 193 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Operational Mode Enable Register
This register selects which operational mode is enabled. Bits defined as write-only are read as 0's.
REGISTER
ADDRESS
R/W
RESET
VALUE
DESCRIPTION
OperationalModeEnable 0xFFF0_5204 R/W USB Operational Mode Enable Register
31
30
29
28
27
0x0000_000
0
26
25
24
18
17
16
11
10
9
3
OVRCUR
2
1
8
SIEPD
0
Reserved
23
22
21
20
19
Reserved
15
14
13
7
6
5
12
Reserved
Reserved
4
BITS
[31:9]
Reserved
DBREG
BIT DESCRIPTION
Reserved
[8]
SIEPD
[7:4]
Reserved
Reserved. Read/write 0
SIE Pipeline Disable
When set, waits for all USB bus activity to complete prior to
returning completion status to the List Processor. This is a failsafe
mechanism to avoid potential problems with the clk_dr transition
between 1.5 MHz and 12 MHz.
Reserved. Read/write 0
OVRCURP (over current indicator polarity)
[3]
OVRCURP
[2:1]
Reserved
[0]
DBREG
When the OVRCURP bit is clear, the OVRCUR non-inverted to
input into USB host controller. In contrast, when the OVRCURP bit
is set, the OVRCUR inverted to input into USB host controller.
Reserved. Read/write 0
Data Buffer Region 16
When set, the size of the data buffer region is 16 bytes. Otherwise, the
size is 32 bytes.
- 194 -
W90N745CD/W90N745CDG
7.8
USB Device Controller
The USB controller interfaces the AHB bus and the USB bus. The USB controller contains both the
AHB master interface and AHB slave interface. CPU programs the USB controller through the AHB
slave interface. For IN or OUT transfer, the USB controller needs to write data to memory or read data
from memory through the AHB master interface. The USB controller also contains the USB
transceiver to interface the USB.
7.8.1
USB Endpoints
It consists of four endpoints, designated EP0, EPA, EPB and EPC. Each is intended for a particular
use as described below:
EP0: the default endpoint uses control transfer (In/Out) to handle configuration and control functions
required by the USB specification. Maximum packed size is 16 bytes.
EPA: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN
endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint.
EPB: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN
endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint.
EPC: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN
endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint.
7.8.2
Standard Device Request
The USB controller has built-in hard-wired state machine to automatically respond to USB standard
device request. It also supports to detect the class and vendor requests. For Get Descriptor request
and Class or Vendor command, the firmware will control these procedures.
7.8.3
USB Device Register Description
USB Control Register (USB_CTL)
REGISTER
USB_CTL
31
ADDRESS
0xFFF0_6000
30
29
R/W
R/W
DESCRIPTION
RESET VALUE
USB control register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
- 195 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
CCMD
VCMD
SIE_RCV
SUS_TST
RWU_EN
- 196 -
SUSP
USB_RST
USB_EN
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:8]
Reserved
[7]
CCMD
USB Class Command Decode Control Enable
0: Disable, the H/W circuit doesn’t need to decode USB class command.
It will return a stall status when it received a USB Class Command.
1: Enable, the H/W circuit decodes USB class command. It will assert
an interrupt event when it received a USB Class Command.
VCMD
USB Vendor Command Decode Enable
0: Disable, the H/W circuit doesn’t need to decode USB vendor
command. It will return a stall status when it received a USB Vendor
Command.
1: Enable, the H/W circuit decodes USB vendor command. It will assert
an interrupt event when it received a USB Vendor Command.
SIE_RCV
USB SIE Differential RCV Source
0: RCV generated by the SIE
1: RCV generated by the USB transceiver
SUS_TST
USB Suspend Accelerate Test
0: Normal Operation
1: USB Suspend Accelerate Test (Only for Test)
RWU_EN
USB Remote Wake-up Enable
0: Disable USB Remote Wake-Up Detect
1: Enable USB Remote Wake-Up Detect
SUSP
USB Suspend Detect Enable
0: Disable USB Suspend Detect
1: Enable USB Suspend Detect
USB_RST
USB Engine Reset
0: Normal operation
1: Reset USB Engine
USB_EN
USB Engine Enable
0: disable USB Engine
1: enable USB Engine
Note: set this bit to “0”, the device is absent from host. After set
this bit to “1”, the host will detect a device attached.
[6]
[5]
[4]
[3]
[2]
[1]
[0]
- 197 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Class or Vendor command Register (USB_CVCMD)
REGISTER
ADDRESS
USB_CVCMD
0xFFF0_600
4
31
30
R/W
R/W
29
DESCRIPTION
USB class
register
28
or
RESET VALUE
vendor
command
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Reserved
CVI_LG
BITS
DESCRIPTIONS
[31:5]
[4:0]
Reserved
CVI_LG
Byte Length for Class and Vendor Command and Get Descriptor Return
Data Packet
USB Interrupt Enable Register (USB_IE)
REGISTER
USB_IE
ADDRESS
R/W
0xFFF0_6008
R/W
DESCRIPTION
RESET VALUE
USB interrupt enable register
0x0000_0000
31
30
29
28
27
26
25
24
23
22
21
Reserved
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
RUM_CLKI
RST_ENDI
USB_CGI
USB_BTI
CVSI
CDII
CDOI
VENI
7
6
5
4
3
2
1
0
CLAI
GSTRI
GCFGI
GDEVI
ERRI
RUMI
SUSI
RSTI
- 198 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:16]
Reserved
RUM_CLKI
Interrupt enable for RESUME (for clock is stopped)
0: Disable
1: Enable
RST_ENDI
Interrupt enable for USB reset end
0: Disable
1: Enable
USB_CGI
Interrupt Enable for Device Configured
0: Disable
1: Enable
Note: the interrupt occurs when device configured or dis-configured.
[12]
USB_BTI
Interrupt Enable for USB Bus Transition
0: Disable
1: Enable
[11]
CVSI
Interrupt Enable Control for Status Phase of Class or Vendor Command
0: Disable
1: Enable
[10]
CDII
Interrupt Enable Control for Data-In of Class or Vendor Command
0: Disable
1: Enable
[9]
CDOI
Interrupt Enable Control for Data-Out of Class or Vendor Command
0: Disable
1: Enable
[8]
VENI
Interrupt Enable Control for USB Vendor Command
0: Disable
1: Enable
[7]
CLAI
Interrupt Enable Control for USB Class Command
0: Disable
1: Enable
[6]
GSTRI
Interrupt Enable Control for USB Get_String_Descriptor Command
0: Disable
1: Enable
[15]
[14]
[13]
- 199 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
[5]
GCFGI
Interrupt Enable Control for USB Get_Configuration_Descriptor Command
0: Disable
1: Enable
- 200 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
GDEVI
Interrupt Enable Control for USB Get_Device_Descriptor Command
0: Disable
1: Enable
ERRI
Interrupt Enable Control for USB Error Detect
0: Disable
1: Enable
[2]
RUMI
Interrupt Enable Control for USB Resume Detect
0: Disable
1: Enable
[1]
SUSI
Interrupt Enable Control for USB Suspend Detect
0: Disable
1: Enable
[0]
RSTI
Interrupt Enable Control for USB Reset Command Detect
0: Disable
1: Enable
[4]
[3]
USB Interrupt status Register (USB_IS)
REGISTER
USB_IS
31
ADDRESS
R/W
0xFFF6_000C
30
R
DESCRIPTION
RESET VALUE
USB interrupt status register
29
28
27
26
0x0000_0000
25
24
17
16
Reserved
23
22
21
20
19
18
Reserved
15
14
13
12
11
10
9
8
RUM_CLK
S
RSTENDS
USB_CGS
USB_BTS
CVSS
CDIS
CDOS
VENS
7
6
5
4
3
2
1
0
CLAS
GSTRS
GCFGS
GDEVS
ERRS
RUMS
SUSS
RSTS
- 201 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:16]
Reserved
Interrupt status for RESUME (for clock is stopped)
[15]
RUM_CLKS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt status for USB reset end
[14]
RSTENDS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Device Configured
[13]
USB_CGS
0: No Interrupt Generated
1: Interrupt Generated(configured and dis-configured)
Interrupt Status for USB Bus Transition
[12]
USB_BTS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for Status Phase of Class or Vendor Command
[11]
CVSS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for Data-In of Class or Vendor Command
[10]
CDIS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for Data-Out of Class or Vendor Command
[9]
CDOS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Vendor Command
[8]
VENS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Class Command
[7]
CLAS
0: No Interrupt Generated
1: Interrupt Generated
- 202 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
Interrupt Status for USB Get_String_Descriptor Command
[6]
GSTRS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Get_Configuration_Descriptor Command
[5]
GCFGS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Get_Device_Descriptor Command
[4]
GDEVS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Error Detect
[3]
ERRS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Resume Detect
[2]
RUMS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Suspend Detect
[1]
SUSS
0: No Interrupt Generated
1: Interrupt Generated
Interrupt Status for USB Reset Command Detect
[0]
RSTS
0: No Interrupt Generated
1: Interrupt Generated
USB Interrupt Status Clear (USB_IC)
REGISTER
USB_IC
ADDRESS
0xFFF6_0010
R/W
R/W
DESCRIPTION
USB interrupt status clear register
- 203 -
RESET VALUE
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
23
22
21
28
Reserved
20
27
26
25
24
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
RUM_CLK
C
RSTENDC
USB_CGC
USB_BTC
CVSC
CDIC
CDOC
VENC
7
6
5
4
3
2
1
0
CLAC
GSTRC
GCFGC
GDEVC
ERRC
RUMC
SUSC
RSTC
BITS
DESCRIPTIONS
[31:16]
Reserved
[15]
RUM_CLKC
Interrupt status clear for RESUME (for clock is stopped)
0: NO Operation
1: Clear Interrupt Status
RSTENDC
Interrupt status clear for USB reset end
0: NO Operation
1: Clear Interrupt Status
USB_CGC
Interrupt Status Clear for USB Device Configured
0: NO Operation
1: Clear Interrupt Status
[12]
USB_BTC
Interrupt Status Clear for USB Bus Transition
0: NO Operation
1: Clear Interrupt Status
[11]
CVSC
Interrupt Status Clear for Status Phase of Class or Vendor Command
0: NO Operation
1: Clear Interrupt Status
[10]
CDIC
Interrupt Status Clear for Data-In of Class or Vendor Command
0: NO Operation
1: Clear Interrupt Status
[9]
CDOC
Interrupt Status Clear for Data-Out of Class or Vendor Command
0: NO Operation
1: Clear Interrupt Status
[14]
[13]
- 204 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
VENC
Interrupt Status Clear for USB Vendor Command
0: NO Operation
1: Clear Interrupt Status
CLAC
Interrupt Status Clear for USB Class Command
0: NO Operation
1: Clear Interrupt Status
[6]
GSTRC
Interrupt Status Clear for USB Get_String_Descriptor Command
0: NO Operation
1: Clear Interrupt Status
[5]
GCFGC
Interrupt Status Clear for USB Get_Configuration_Descriptor Command
0: NO Operation
1: Clear Interrupt Status
[4]
GDEVC
Interrupt Status Clear for USB Get_Device_Descriptor Command
0: NO Operation
1: Clear Interrupt Status
[3]
ERRC
Interrupt Status Clear for USB Error Detect
0: NO Operation
1: Clear Interrupt Status
[2]
RUMC
Interrupt Status Clear for USB Resume Detect
0: NO Operation
1: Clear Interrupt Status
[1]
SUSC
Interrupt Status Clear for USB Suspend Detect
0: NO Operation
1: Clear Interrupt Status
RSTC
Interrupt Status Clear for USB Reset Command Detect
0: NO Operation
1: Clear Interrupt Status
[8]
[7]
[0]
USB Interface and String Register (USB_IFSTR)
REGISTER
ADDRESS
R/W
USB_IFSTR
0xFFF06014
R/W
DESCRIPTION
USB interface and string register
- 205 -
RESET VALUE
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
23
30
22
29
28
27
26
25
24
21
Reserved
20
19
18
17
16
10
9
8
STR6_EN
STR5_EN
Reserved
15
14
13
12
11
Reserved
7
6
5
4
3
2
1
0
STR4_EN
STR3_EN
STR2_EN
STR1_EN
INF4_EN
INF3_EN
INF2_EN
INF1_EN
BITS
DESCRIPTIONS
[31:10]
Reserved
USB String Descriptor-6 Control
[9]
STR6_EN
0: Disable
1: Enable
USB String Descriptor-5 Control
[8]
STR5_EN
0: Disable
1: Enable
USB String Descriptor-4 Control
[7]
STR4_EN
0: Disable
1: Enable
USB String Descriptor-3 Control
[6]
STR3_EN
0: Disable
1: Enable
USB String Descriptor-2 Control
[5]
STR2_EN
0: Disable
1: Enable
USB String Descriptor-1 Control
[4]
STR1_EN
0: Disable
1: Enable
- 206 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
USB Interface-4 Control
[3]
INF4_EN
0: Disable
1: Enable
USB Interface-3 Control
[2]
INF3_EN
0: Disable
1: Enable
USB Interface-2 Control
[1]
INF2_EN
0: Disable
1: Enable
USB Interface-1 Control
[0]
INF1_EN
0: Disable
1: Enable
USB Control transfer-out port 0 (USB_ODATA0)
REGISTER
ADDRESS
USB_ODATA0
0xFFF06018
31
30
R/W
29
R
DESCRIPTION
RESET VALUE
USB control transfer-out port 0 register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ODATA0
23
22
21
20
ODATA0
15
14
13
12
ODATA0
7
6
5
4
ODATA0
BITS
[31:0]
DESCRIPTIONS
ODATA0
Control Transfer-out data 0
- 207 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Control transfer-out port 1 (USB_ODATA1)
REGISTER
ADDRESS
USB_ODATA1
0xFFF0601C
31
30
R/W
R
DESCRIPTION
RESET VALUE
USB control transfer-out port 1 register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ODATA1
23
22
21
20
ODATA1
15
14
13
12
ODATA1
7
6
5
4
ODATA1
BITS
[31:0]
DESCRIPTIONS
ODATA1
Control Transfer-out data 1
USB Control transfer-out port 2 (USB_ODATA2)
REGISTER
ADDRESS
R/W
USB_ODATA2
0xFFF06020
R
31
30
29
DESCRIPTION
RESET VALUE
USB control transfer-out port 2
register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ODATA2
23
22
21
20
ODATA2
15
14
13
12
ODATA2
7
6
5
4
ODATA2
BITS
[31:0]
DESCRIPTIONS
ODATA2
Control Transfer-out data 2
USB Control transfer-out port 3 (USB_ODATA3)
- 208 -
W90N745CD/W90N745CDG
REGISTER
ADDRESS
USB_ODATA3
0xFFF06024
31
30
R/W
R
29
DESCRIPTION
RESET VALUE
USB control transfer-out port 3 register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ODATA3
23
22
21
20
ODATA3
15
14
13
12
ODATA3
7
6
5
4
ODATA3
BITS
[31:0]
DESCRIPTIONS
ODATA3
Control Transfer-out data 3
USB Control transfer-in data port0 Register (USB_IDATA0)
REGISTER
USB_IDATA0
31
ADDRESS
R/W
0xFFF06028
R/W
30
29
DESCRIPTION
RESET VALUE
USB transfer-in data port0 register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IDATA0
23
22
21
20
15
14
13
12
IDATA0
IDATA0
7
6
5
4
IDATA0
BITS
[31:6]
DESCRIPTIONS
IDATA0
Control transfer-in data0
USB Control transfer-in data port 1 Register (USB_IDATA1)
- 209 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
REGISTER
USB_IDATA1
31
ADDRESS
R/W
0xFFF0602C
30
R/W
29
DESCRIPTION
RESET VALUE
USB control transfer-in data port 1
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IDATA1
23
22
21
20
IDATA1
15
14
13
12
IDATA1
7
6
5
4
IDATA1
BITS
[31:6]
DESCRIPTIONS
IDATA1
Control transfer-in data1
USB Control transfer-in data port 2 Register (USB_IDATA2)
REGISTER
USB_IDATA2
31
ADDRESS
R/W
0xFFF06030
R/W
30
29
DESCRIPTION
RESET VALUE
USB control transfer-in data port 2
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IDATA2
23
22
21
20
IDATA2
15
14
13
12
IDATA2
7
6
5
4
IDATA2
BITS
[31:6]
DESCRIPTIONS
IDATA2
Control transfer-in data2
USB Control transfer-in data port 3 Register (USB_IDATA3)
- 210 -
W90N745CD/W90N745CDG
REGISTER
USB_IDATA3
31
ADDRESS
R/W
0xFFF06034
R/W
30
29
DESCRIPTION
RESET VALUE
USB control transfer-in data port 3
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IDATA3
23
22
21
20
IDATA3
15
14
13
12
IDATA3
7
6
5
4
IDATA3
BITS
[31:6]
DESCRIPTIONS
IDATA3
Control transfer-in data3
USB SIE Status Register (USB_SIE)
REGISTER
USB_SIE
31
ADDRESS
R/W
0xFFF06038
30
R
29
DESCRIPTION
RESET VALUE
USB SIE status Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
USB_DPS
USB_DMS
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
4
3
Reserved
- 211 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:2]
Reserved
[1]
USB_DPS
USB Bus D+ Signal Status
0: USB Bus D+ Signal is low
1: USB Bus D+ Signal is high
USB_DMS
USB Bus D- Signal Status
0: USB Bus D- Signal is low
1: USB Bus D- Signal is high
[0]
USB Engine Register (USB_ENG)
REGISTER
USB_ENG
ADDRESS
0xFFF0603C
R/W
DESCRIPTION
R/W
RESET VALUE
USB Engine Register
0x0000_0000
31
30
29
28
27
26
25
24
23
22
21
20
Reserved
19
18
17
16
10
9
8
3
2
1
0
SDO_RD
CV_LDA
CV_STL
CV_DAT
Reserved
15
14
13
12
11
Reserved
7
6
5
Reserved
BITS
4
DESCRIPTIONS
[31:4]
Reserved
[3]
SDO_RD
Setup or Bulk-Out Data Read Control
0: NO Operation
1: Read Setup or Bulk-Out Data from USB Host
NOTE: this bit will auto clear after 32 HCLK
CV_LDA
USB Class and Vendor Command Last Data Packet Control
0: NO Operation
1: Last Data Packet for Data Input of Class and Vendor Command
NOTE: this bit will auto clear after 32 HCLK
[2]
- 212 -
W90N745CD/W90N745CDG
Continued.
BITS
[1]
[0]
DESCRIPTIONS
CV_STL
USB Class and Vendor Command Stall Control
0: NO Operation
1: Return Stall for Class and Vendor Command
NOTE: this bit will auto clear after 32 HCLK
CV_DAT
USB Class and Vendor Command return data control
0: NO Operation
1: The Data Packet for Data Input of Class and Vendor Command or
Get Descriptor command is ready.
NOTE: this bit will auto clear after 32 HCLK
USB Control Register (USB_CTLS)
REGISTER
USB_CTLS
31
ADDRESS
R/W
0xFFF06040
30
R
29
DESCRIPTION
RESET VALUE
USB control transfer status register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
CONF
7
6
5
4
Reserved
CTLRPS
ITS
DESCRIPTIONS
[31:16]
[15:8]
Reserved
CONF
[7:5]
[4:0]
USB configured value
Reserved
CTLRPS
Control transfer received packet size
- 213 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Configured Value Register (USB_CONFD)
REGISTER
USB_CONFD
31
ADDRESS
R/W
0xFFF06044
R/W
30
29
DESCRIPTION
RESET VALUE
USB Configured Value register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
CONFD
BITS
DESCRIPTIONS
[31:8]
[7:0]
Reserved
CONFD
Software configured value
USB Endpoint A Information Register (EPA_INFO)
REGISTER
EPA_INFO
31
Reserved
23
ADDRESS
R/W
0xFFF06048
R/W
30
29
EPA_TYPE
22
21
DESCRIPTION
RESET VALUE
USB endpoint A information register
28
27
EPA_DIR
20
26
0x0000_0000
25
Reserved
24
EPA_MPS
19
18
17
16
11
10
9
8
1
0
EPA_MPS
15
14
13
12
EPA_ALT
7
6
EPA_INF
5
4
3
EPA_CFG
2
EPA_NUM
- 214 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31]
Reserved
[30:29]
EPA_TYPE
Endpoint A type
00: reserved
01: bulk
10: interrupt
11: isochronous
[28]
EPA_DIR
Endpoint A direction
0: OUT
1: IN
[27:26]
Reserved
[25:16]
EPA_MPS
Endpoint A max. packet size
[15:12]
EPA_ALT
Endpoint A alternative setting (READ ONLY)
[11:8]
EPA_INF
Endpoint A interface
[7:4]
EPA_CFG
Endpoint A configuration
[3:0]
EPA_NUM
Endpoint A number
USB Endpoint A Control Register (EPA_CTL)
REGISTER
EPA_CTL
31
ADDRESS
R/W
0xFFF0604C
30
R/W
29
DESCRIPTION
RESET VALUE
USB endpoint A control register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
Reserved
6
EPA_ZERO
5
EPA_STL_CLR
4
EPA_THRE EPA_STL
- 215 -
EPA_RDY
EPA_RST
EPA_EN
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:6]
Reserved
[6]
EPA_ZERO
Send zero length packet to HOST
[5]
EPA_STL_CLR
CLEAR the Endpoint A stall(WRITE ONLY)
Endpoint A threshold (only for ISO)
[4]
1: once available space in FIFO over 16 bytes, DMA accesses
memory
EPA_THRE
0: once available space in FIFO over 32 bytes, DMA accesses
memory
[3]
EPA_STL
Set the Endpoint A stall
[2]
EPA_RDY
The memory is ready for Endpoint A to access
[1]
EPA_RST
Endpoint A reset
[0]
EPA_EN
Endpoint A enable
USB Endpoint A interrupt enable Register (EPA_IE)
REGISTER
ADDRESS
R/W
EPA_IE
0xFFF06050
R/W
DESCRIPTION
USB endpoint
register
31
30
29
28
23
22
21
20
A
27
Interrupt
RESET VALUE
Enable
0x0000_0000
26
25
24
18
17
16
10
9
8
Reserved
19
Reserved
15
14
13
12
11
Reserved
7
6
Reserved
5
4
3
2
1
0
EPA_CF_IE
EPA_BUS_ERR_I
E
EPA_DMA_IE
EPA_ALT_IE
EPA_TK_IE
EPA_STL_IE
- 216 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPA_CF_IE
Endpoint A clear feature interrupt enable
[4]
EPA_BUS_ERR_IE
Endpoint A system bus error interrupt enable
[3]
EPA_DMA_IE
Endpoint A DMA transfer complete interrupt enable
[2]
EPA_ALT_IE
Endpoint A alternate setting interrupt enable
[1]
EPA_TK_IE
Endpoint A token input interrupt enable
[0]
EPA_STL_IE
Endpoint A stall interrupt enable
USB Endpoint A Interrupt Clear Register (EPA_IC)
REGISTER
EPA_IC
ADDRESS
0xFFF06054
31
30
R/W
W
29
DESCRIPTION
USB endpoint
register
28
A
interrupt
RESET VALUE
clear
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
Reserved
5
4
3
2
1
0
EPA_CF_IC
EPA_BUS_ERR_I
C
EPA_DMA_IC
EPA_ALT_IC
EPA_TK_IC
EPA_STL_IC
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPA_CF_INT_IC
Endpoint A clear feature interrupt clear
[4]
EPA_BUS_ERR_IC
Endpoint A system bus error interrupt clear
[3]
EPA_DMA_IC
Endpoint A DMA transfer complete interrupt clear
- 217 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
[2]
EPA_ALT_IC
Endpoint A alternate setting interrupt clear
[1]
EPA_TK_IC
Endpoint A token input interrupt clear
[0]
EPA_STL_IC
Endpoint A stall interrupt clear
USB Endpoint A Interrupt Status Register (EPA_IS)
REGISTER
ADDRESS
R/W
EPA_IS
0xFFF06058
R
31
30
29
DESCRIPTION
RESET VALUE
USB endpoint A interrupt status
register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
EPA_ALT_IS
EPA_TK_IS
EPA_STL_IS
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
Reserved
5
4
EPA_CF_IS
EPA_BUS_ERR_IS EPA_DMA_IS
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPA_CF_IS
Endpoint A clear feature interrupt status
[4]
EPA_BUS_ERR_IS
Endpoint A system bus error interrupt status
[3]
EPA_DMA_IS
Endpoint A DMA transfer complete interrupt status
[2]
EPA_ALT_IS
Endpoint A alternative setting interrupt status
[1]
EPA_TK_IS
Endpoint A token interrupt status
[0]
EPA_STL_IS
Endpoint A stall interrupt status
- 218 -
W90N745CD/W90N745CDG
USB Endpoint A Address Register (EPA_ADDR)
REGISTER
EPA_ADDR
ADDRESS
R/W
0xFFF0605C
R/W
DESCRIPTION
RESET VALUE
USB endpoint A address register
0x0000_0000
31
30
29
28
27
26
25
24
23
22
21
EPA_ADDR
20
19
18
17
16
10
9
8
2
1
0
EPA_ADDR
15
14
13
12
11
EPA_ADDR
7
6
5
4
3
EPA_ADDR
BITS
[31:0]
DESCRIPTIONS
EPA_ADDR
Endpoint A transfer address
USB Endpoint A transfer length Register (EPA_LENTH)
REGISTER
EPA_LENTH
31
ADDRESS
R/W
0xFFF06060
R/W
30
29
DESCRIPTION
USB endpoint
register
28
A
RESET VALUE
transfer
length
0x0000_0000
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
EPA_LENTH
13
12
11
10
9
8
2
1
0
EPA_LENTH
7
6
5
4
3
EPA_LENTH
- 219 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:20]
[19:0]
Reserved
EPA_LENTH
Endpoint A transfer length
USB Endpoint B Information Register (EPB_INFO)
REGISTER
EPB_INFO
31
Reserved
23
ADDRESS
R/W
0xFFF06064
R/W
30
DESCRIPTION
USB endpoint B information register
29
EPB_TYPE
22
RESET VALUE
28
27
EPB_DIR
21
20
26
0x0000_0000
25
Reserved
24
EPB_MPS
19
18
17
16
11
10
9
8
1
0
EPB_MPS
15
14
13
12
EPB_ALT
7
6
EPB_INF
5
4
3
EPB_CFG
BITS
EPB_NUM
DESCRIPTIONS
[31]
Reserved
Endpoint B type
00: reserved
[30:29]
EPB_TYPE
01: bulk
10: interrupt
11: isochronous
Endpoint B direction
[28]
EPB_DIR
0: OUT
1: IN
[27:26]
[25:16]
Reserved
EPB_MPS
2
Endpoint B max. packet size
- 220 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
[15:12]
EPB_ALT
Endpoint B alternative setting (READ ONLY)
[11:8]
EPB_INF
Endpoint B interface
[7:4]
EPB_CFG
Endpoint B configuration
[3:0]
EPB_NUM
Endpoint B number
USB Endpoint B Control Register (EPB_CTL)
REGISTER
EPB_CTL
ADDRESS
R/W
0xFFF06068
R/W
DESCRIPTION
RESET VALUE
USB endpoint B control register
31
30
29
28
23
22
21
20
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
Reserved
EPB_ZERO
EPB_STL_CLR
EPB_THRE
EPB_STL
EPB_RDY
EPB_RST
EPB_EN
BITS
DESCRIPTIONS
[31:7]
Reserved
[6]
EPB_ZERO
Send zero length packet back to HOST
[5]
EPB_STL_CLR
Clear the Endpoint B stall(WRITE ONLY)
Endpoint B threshold (only for ISO)
[4]
EPB_THRE
1: once available space in FIFO over 16 bytes, DMA
accesses memory
0: once available space in FIFO over 32 bytes, DMA
accesses memory
[3]
EPB_STL
Set the Endpoint B stall
- 221 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
[2]
EPB_RDY
The memory is ready for Endpoint B to access
[1]
EPB_RST
Endpoint B reset
[0]
EPB_EN
Endpoint B enable
USB Endpoint B interrupt enable Register (EPB_IE)
REGISTER
EPB_IE
31
30
ADDRESS
R/W
DESCRIPTION
0xFFF0606C
R/W
USB endpoint B Interrupt Enable register
29
28
27
RESET VALUE
0x0000_0000
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
Reserved
5
4
3
2
1
0
EPB_CF_IE
EPB_BUS_ERR_IE
EPB_DMA_IE
EPB_ALT_IE
EPB_TK_IE
EPB_STL_I
E
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPB_CF_IE
Endpoint B clear feature interrupt enable
[4]
EPB_BUS_ERR_IE
Endpoint B system bus error interrupt enable
[3]
EPB_DMA_IE
Endpoint B DMA transfer complete interrupt enable
[2]
EPB_ALT_IE
Endpoint B alternate setting interrupt enable
[1]
EPB_TK_IE
Endpoint B token input interrupt enable
[0]
EPB_STL_IE
Endpoint B stall interrupt enable
USB Endpoint B Interrupt Clear Register (EPB_IC)
- 222 -
W90N745CD/W90N745CDG
REGISTER
EPB_IC
31
ADDRESS
R/W
0xFFF06070
30
W
29
DESCRIPTION
USB endpoint
register
28
B
interrupt
27
RESET VALUE
clear
0x0000_0000
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
Reserved
5
4
3
2
1
0
EPB_CF_IC
EPB_BUS_ERR_IC
EPB_DMA_IC
EPB_ALT_IC
EPB_TK_IC
EPB_STL_IC
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPB_CF_IC
Endpoint B clear feature interrupt clear
[4]
EPB_BUS_ERR_IC
Endpoint B system bus error interrupt clear
[3]
EPB_DMA_IC
Endpoint B DMA transfer complete interrupt clear
[2]
EPB_ALT_IC
Endpoint B alternate setting interrupt clear
[1]
EPB_TK_IC
Endpoint B token input interrupt clear
[0]
EPB_STL_IC
Endpoint B stall interrupt clear
USB Endpoint B Interrupt Status Register (EPB_IS)
REGISTER
EPB_IS
ADDRESS
0xFFF06074
R/W
R
DESCRIPTION
USB endpoint
register
- 223 -
B
interrupt
RESET VALUE
status
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
Reserved
5
4
3
2
1
0
EPB_CF_IS
EPB_BUS_ERR_IS
EPB_DMA_IS
EPB_ALT_IS
EPB_TK_IS
EPB_STL_IS
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPB_CF_IS
Endpoint B clear feature interrupt status
[4]
EPB_DMA_IS
Endpoint B system bus error interrupt status
[3]
EPB_DMA_IS
Endpoint B DMA transfer complete interrupt status
[2]
EPB_ALT_IS
Endpoint B alternative setting interrupt status
[1]
EPB_TK_IS
Endpoint B token interrupt status
[0]
EPB_STL_IS
Endpoint B stall interrupt status
USB Endpoint B Address Register (EPB_ADDR)
REGISTER
ADDRESS
R/W
EPB_ADDR
0xFFF06078
R/W
31
30
29
DESCRIPTION
RESET VALUE
USB endpoint B address register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
EPB_ADDR
23
22
21
20
19
EPB_ADDR
15
14
13
12
11
EPB_ADDR
7
6
5
4
3
EPB_ADDR
- 224 -
W90N745CD/W90N745CDG
BITS
[31:0]
DESCRIPTIONS
EPB_ADDR
Endpoint B transfer address
USB Endpoint B transfer length Register (EPB_LENTH)
REGISTER
EPB_LENTH
31
ADDRESS
R/W
0xFFF0607C
30
R/W
29
DESCRIPTION
USB endpoint
register
28
B
RESET VALUE
transfer
length
0x0000_0000
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
EPB_LENTH
13
12
11
10
9
8
2
1
0
EPB_LENTH
7
6
5
4
3
EPB_LENTH
BITS
DESCRIPTIONS
[31:20]
[19:0]
Reserved
EPB_LENTH
Endpoint B transfer length
USB Endpoint C Information Register (EPC_INFO)
REGISTER
EPC_INFO
ADDRESS
R/W
DESCRIPTION
0xFFF06080
R/W
USB endpoint C information register
- 225 -
RESET VALUE
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
Reserved
23
30
29
EPC_TYPE
22
28
27
EPC_DIR
21
20
26
25
Reserved
24
EPC_MPS
19
18
17
16
11
10
9
8
1
0
EPC_MPS
15
14
13
12
EPC_ALT
7
6
EPC_INF
5
4
3
EPC_CFG
2
EPC_NUM
BITS
DESCRIPTIONS
[31]
Reserved
Endpoint C type
00: reserved
[30:29]
EPC_TYPE
01: bulk
10: interrupt
11: isochronous
Endpoint C direction
[28]
EPC_DIR
0: OUT
1: IN
[27:26]
Reserved
[25:16]
EPC_MPS
Endpoint C max. packet size
[15:12]
EPC_ALT
Endpoint C alternative setting (READ ONLY)
[11:8]
EPC_INF
Endpoint C interface
[7:4]
EPC_CFG
Endpoint C configuration
[3:0]
EPC_NUM
Endpoint C number
- 226 -
W90N745CD/W90N745CDG
USB Endpoint C Control Register (EPC_CTL)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EPC_CTL
0xFFF06084
R/W
USB endpoint C control register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
Reserved
EPC_ZERO
EPC_STL_CLR
EPC_THRE
EPC_STL
EPC_RDY
EPC_RST
EPC_EN
BITS
DESCRIPTIONS
[31:7]
Reserved
[6]
EPC_ZERO
Send zero length packet back to HOST
[5]
EPC_STL_CLR
Clear the Endpoint C stall(WRITE ONLY)
Endpoint C threshold (only for ISO)
[4]
EPC_THRE
1: once available space in FIFO over 16 bytes, DMA accesses
memory
0: once available space in FIFO over 32 bytes, DMA accesses
memory
[3]
EPC_STL
Set the Endpoint C stall
[2]
EPC_RDY
The memory is ready for Endpoint C to access
[1]
EPC_RST
Endpoint C reset
[0]
EPC_EN
Endpoint C enable
- 227 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Endpoint C interrupt enable Register (EPC_IE)
REGISTER
EPC_IE
31
30
ADDRESS
R/W
DESCRIPTION
0xFFF0608
8
R/W
USB endpoint C Interrupt Enable register
29
28
27
RESET VALUE
0x0000_0000
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
Reserved
5
4
3
2
1
0
EPC_CF_IE
EPC_BUS_ERR_IE
EPC_DMA_IE
EPC_ALT_IE
EPC_TK_IE
EPC_STL_IE
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPC_CF_IE
Endpoint C clear feature interrupt enable
[4]
EPC_DMA_IE
Endpoint C system bus error interrupt enable
[3]
EPC_DMA_IE
Endpoint C DMA transfer complete interrupt enable
[2]
EPC_ALT_IE
Endpoint C alternate setting interrupt enable
[1]
EPC_TK_IE
Endpoint C token input interrupt enable
[0]
EPC_STL_IE
Endpoint C stall interrupt enable
USB Endpoint C Interrupt Clear Register (EPC_IC)
REGISTER
EPC_IC
ADDRESS
0xFFF0608C
R/W
W
DESCRIPTION
USB endpoint C interrupt clear register
- 228 -
RESET VALUE
0x0000_0000
W90N745CD/W90N745CDG
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
EPC_ALT_IC
EPC_TK_IC
EPC_STL_IC
Reserved
Reserved
15
14
13
12
Reserved
7
6
5
Reserved
4
EPC_CF_IC
EPC_BUS_ERR
EPC_DMA_IC
_IC
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPC_CF_IC
Endpoint C clear feature interrupt clear
[4]
EPC_DMA_IC
Endpoint C system bus error interrupt clear
[3]
EPC_DMA_IC
Endpoint C DMA transfer complete interrupt clear
[2]
EPC_ALT_IC
Endpoint C alternate setting interrupt clear
[1]
EPC_TK_IC
Endpoint C token input interrupt clear
[0]
EPC_STL_IC
Endpoint C stall interrupt clear
USB Endpoint C Interrupt Status Register (EPC_IS)
REGISTER
EPC_IS
ADDRESS
0xFFF06090
R/W
R
DESCRIPTION
USB endpoint
register
- 229 -
C
interrupt
RESET VALUE
status
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
Reserved
4
EPC_CF_IS
3
EPC_BUS_ERR_IS EPC_DMA_IS
BITS
EPC_ALT_IS
EPC_TK_IS
EPC_STL_IS
DESCRIPTIONS
[31:6]
Reserved
[5]
EPC_CF_IS
Endpoint C clear feature interrupt status
[4]
EPC_BUS_ERR_IS
Endpoint A system bus error interrupt status
[3]
EPC_DMA_IS
Endpoint A DMA transfer complete interrupt status
[2]
EPC_ALT_IS
Endpoint A alternative setting interrupt status
[1]
EPC_TK_IS
Endpoint A token interrupt status
[0]
EPC_STL_IS
Endpoint A stall status
USB Endpoint C Address Register (EPC_ADDR)
REGISTER
EPC_ADDR
31
ADDRESS
R/W
0xFFF0_6094
30
R/W
29
DESCRIPTION
RESET VALUE
USB endpoint C address register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
EPC_ADDR
23
22
21
20
19
EPC_ADDR
15
14
13
12
11
EPC_ADDR
7
6
5
4
3
EPC_ADDR
- 230 -
W90N745CD/W90N745CDG
BITS
[31:0]
DESCRIPTIONS
EPC_ADDR
Endpoint C transfer address
USB Endpoint C transfer length Register (EPC_LENTH)
REGISTER
ADDRESS
EPC_LENTH
31
0xFFF0_6098
30
29
R/W
DESCRIPTION
R/W
USB endpoint C transfer length
register
28
RESET VALUE
0x0000_0000
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
EPC_LENTH
13
12
11
10
9
8
2
1
0
EPC_LENTH
7
6
5
4
3
EPC_LENTH
BITS
DESCRIPTIONS
[31:20]
[19:0]
Reserved
EPC_LENTH
Endpoint C transfer length
USB Endpoint A Remain transfer length Register (EPA_XFER)
REGISTER
EPA_XFER
ADDRESS
0xFFF0_609C
R/W
DESCRIPTION
R/W
USB endpoint A remain transfer length
register
- 231 -
RESET VALUE
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
EPA_XFER
13
12
11
10
9
8
2
1
0
EPA_XFER
7
6
5
4
3
EPA_XFER
BITS
DESCRIPTIONS
[31:20]
[19:0]
Reserved
EPA_XFER
Endpoint A remain transfer length
USB Endpoint A Remain packet length Register (EPA_PKT)
REGISTER
ADDRESS
EPA_PKT
0xFFF0_60A0
31
30
R/W
RESET
VALUE
DESCRIPTION
R/W USB endpoint A remain packet length register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
EPA_PKT
4
3
2
EPA_PKT
BITS
Descriptions
[31:10]
[9:0]
Reserved
EPA_PKT
Endpoint A remain packet length
- 232 -
1
0
W90N745CD/W90N745CDG
USB Endpoint B Remain transfer length Register (EPB_XFER)
REGISTER
EPB_XFER
31
ADDRESS
R/W
DESCRIPTION
0xFFF0_60A4
R/W
USB endpoint B remain transfer length
register
30
29
28
RESET VALUE
0x0000_0000
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
EPB_XFER
13
12
11
10
9
8
2
1
0
EPB_XFER
7
6
5
4
3
EPB_XFER
BITS
DESCRIPTIONS
[31:20]
[19:0]
Reserved
EPB_XFER
Endpoint B remain transfer length
USB Endpoint B Remain packet length Register (EPB_PKT)
REGISTER
EPB_PKT
31
ADDRESS
0xFFF0_60A8
30
R/W
DESCRIPTION
R/W
USB endpoint B remain packet length
register
29
28
RESET VALUE
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
EPB_PKT
4
3
2
1
0
EPB_PKT
- 233 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:10]
[9:0]
Reserved
EPB_PKT
Endpoint B remain packet length
USB Endpoint C Remain transfer length Register (EPC_XFER)
REGISTER
EPC_XFER
ADDRESS
0xFFF0_60AC
R/W
DESCRIPTION
R/W
USB endpoint C remain transfer
length register
31
30
29
28
23
22
21
20
RESET VALUE
0x0000_0000
27
26
25
24
19
18
17
16
Reserved
Reserved
15
14
EPC_XFER
13
12
11
10
9
8
2
1
0
EPC_XFER
7
6
5
4
3
EPC_XFER
BITS
DESCRIPTIONS
[31:20]
[19:0]
Reserved
EPC_XFER
Endpoint C remain transfer length
- 234 -
W90N745CD/W90N745CDG
USB Endpoint C Remain packet length Register (EPC_PKT)
REGISTER
EPC_PKT
31
ADDRESS
R/W
0xFFF0_60B0
R/W
30
29
DESCRIPTION
USB endpoint
length register
28
C
27
remain
RESET VALUE
packet
0x0000_0000
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
EPC_PKT
4
3
2
1
0
EPC_PKT
BITS
DESCRIPTIONS
[31:10]
[9:0]
Reserved
EPC_PKT
Endpoint C remain packet length
- 235 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.9
Audio Controller
The audio controller consists of I²S/AC-link protocol to interface with external audio CODEC.
One 8-level deep FIFO for read path and write path and each level has 32-bit width (16 bits for right
channel and 16 bits for left channel). One DMA controller handles the data movement between FIFO
and memory.
The following are the property of the DMA.
•
Always 8-beat incrementing burst
•
Always bus lock when 8-beat incrementing burst
•
When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
An AHB master port and an AHB slave port are offered in audio controller.
7.9.1
I²S Interface
The I²S interface signals are shown as figure 7.9.2.1
MCLK
BCLK
Audio
Controller
LRCLK
Audio
DOUT
Codec
DIN
Figure 7.9.2.1 The interface signal of I²S
The 16 bits I²S and MSB-justified format are support, the timing diagram is shown as Figure 7.9.2.2
- 236 -
W90N745CD/W90N745CDG
LRC LK
L e ft
1
2
R ig h t
3
1
2
BCK
DATA
B2
M SB
LSB
M SB
I2S b u s
LRC LK
L e ft
1
2
R ig h t
3
1
2
BCK
DATA
M SB B2
B3
LSB
M SB
B2
M S B – J u s tif ie d f o r m a t
Figure 7.9.2.2 The format of I²S
The sampling rate, bit shift clock frequency could be set by the control register ACTL_I²SCON.
7.9.2
AC97 Interface
The AC97 interface, called AC-link is supported. For input and output direction, each frame contains a
Tag slot and 12 data slots. However, in the 12 data slots, only 4 slots are used in W90N745, other 8
slots are not supported, and the control data and audio data are transferred in the 4 valid slots. Each
slot contains 20 bits data.
The interface signals are shown as Figure 7.9.2.1
SYNC
BCLK
Audio
DIN
Controller
Audio
Codec
DOUT
RESETB
Figure 7.9.2.1 The interface signal of AC-link
The signal format is shown as Figure 7.9.2.2
- 237 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Frame (48 KHz)
Data phase
Tag phase
SYN
12.288 MHz
BCL
.
.
.
.
.
.
DIN
.
.
.
.
.
.
.
DOU
B255 B0
MS
.
B1
B15 B16
Slot 0
.
Slot 1
LS
.
B35 B36
.
B55 B56
Slot 2
.
B75 B76
B95 B96
Slot 4
Slot 3
B255
Slot 5 –12
Figure 7.9.2.2 The signal format of AC-link
The structure of output frame is shown as below:
SLOT #
0
CONTENT
Tag
BITS
15-0
PHASE
Tag
phase
1
2
3
4
CMD
CMD
PCM
PCM
ADDR DATA
19-0
19-0
5
6
7
8
9
LEFT RIGHT
Unused
19-0
159 - 0
19-0
10
11
12
Data phase
The output frame data format is shown as following:
SLOT #
BIT
15
Tag
(slot 0)
CMD ADDR
(slot 1)
DESCRIPTION
Frame validity bit, 1 is valid, 0 is invalid.
14 - 3
Slot validity, but in W90N745, only bits 6-3 are used, bits 14-7 are
unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot
2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared
to 0.
2-0
This field should be cleared to 0.
19
Read/write control, 1 for read and 0 for write
18-12
Control register address
11 - 0
This field should be cleared to 0
- 238 -
W90N745CD/W90N745CDG
Continued.
SLOT #
CMD DATA
(slot 2)
PCM LEFT
(slot 3)
PCM RIGHT
(slot 4)
BIT
DESCRIPTION
19 - 4
Control register write data. It should be cleared to 0 if current
operation is read.
3-0
19 - 4
This field should be cleared to 0
PCM playback data for left channel
3-0
This field should be cleared to 0
19 - 4
PCM playback data for right channel
3-0
This field should be cleared to 0
The structure of input frame is shown as below:
Slot #
0
Content
Tag
Bits
0-15
1
2
3
4
5
6
7
8
9
status
status
PCM
PCM
ADDR
DATA
LEFT
RIGHT
Unused
19-0
19-0
19-0
19-0
159 - 0
10
11
12
The input frame data format is shown as following:
SLOT #
BIT
15
Tag
(slot 0)
Frame validity bit, 1 is valid, 0 is invalid.
14 - 3
Slot validity, but in W90N745, only bits 6-3 are used, bits 14-7 are
unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot
2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared
to 0.
2-0
This field should be cleared to 0.
19
18-12
Status ADDR
(slot 1)
DESCRIPTION
11
10
This bit should be cleared to 0
Control register address echo which previous frame requested
PCM data for left channel request, it should be always 0 when
VRA=0 (VRA: Variable Rate Audio mode).
PCM data for right channel request (Same as Bit 11).
9-0
This field should be cleared to 0
Status DATA
(slot 2)
19 - 4
Control register read data which previous frame requested. It should
be cleared to 0 if this slot is invalid.
3-0
This field should be cleared to 0
PCM LEFT
19 - 4
PCM record data for left channel
(slot 3)
3 -0
This field should be cleared to 0
PCM RIGHT
19 - 4
PCM record data for right channel
(slot 4)
3 -0
This field should be cleared to 0
- 239 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.9.3
Audio Controller Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
ACTL_CON
0xFFF0_9000 R/W Audio controller control register
0x0000_0000
ACTL_RESET
0xFFF0_9004 R/W Sub block reset control register
0x0000_0000
ACTL_RDSTB
0xFFF0_9008 R/W
DMA destination base address register
0x0000_0000
for record
DMA destination length register for
ACTL_RDST_LENGT
0xFFF0_900C R/W
0x0000_0000
record
H
R
DMA destination
register for record
current
address
ACTL_RDSTC
0xFFF0_9010
ACTL_RSR
0xFFF0_9014 R/W
Record status register
ACTL_PDSTB
0xFFF0_9018 R/W
DMA destination base address register
0x0000_0000
for play
ACTL_PDST_LENGTH 0xFFF0_901C R/W
DMA destination length register for
0x0000_0000
play
R
DMA destination
register for play
current
0x0000_0000
0x0000_0000
address
ACTL_PDSTC
0xFFF0_9020
ACTL_PSR
0xFFF0_9024 R/W
ACTL_I²SCON
0xFFF0_9028 R/W I²S control register
0x0000_0000
ACTL_ACCON
0xFFF0_902C R/W AC-link control register
0x0000_0000
ACTL_ACOS0
0xFFF0_9030 R/W AC-link out slot 0
0x0000_0000
ACTL_ACOS1
0xFFF0_9034 R/W AC-link out slot 1
0x0000_0080
ACTL_ACOS2
0xFFF0_9038 R/W AC-link out slot 2
0x0000_0000
ACTL_ACIS0
0xFFF0_903C
R
AC-link in slot 0
0x0000_0000
ACTL_ACIS1
0xFFF0_9040
R
AC-link in slot 1
0x0000_0000
ACTL_ACIS2
0xFFF0_9044
R
AC-link in slot 2
0x0000_0000
Play status register
0x0000_0000
0x0000_0004
Audio controller control registers (ACTL_CON)
REGISTER
ACTL_CON
ADDRESS
R/W
0xFFF0_9000 R/W
DESCRIPTION
RESET VALUE
Audio controller control register
0x0000_0000
The ACTL_CON register control the basic operation of audio controller.
- 240 -
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
R_DMA_IRQ
T_DMA_IRQ
7
6
5
4
3
FIFO_TH
Reserved
Reserved
BITS
Reserved
-
[14]
Reserved
-
[13]
Reserved
-
[11]
2
I²S_AC_PIN_SEL
1
BLOCK_EN[1:0]
0
Reserved
DESCRIPTIONS
[15]
[12]
Reserved
R_DMA_IRQ
When recording, when the DMA destination current address reach the DMA
destination end address or middle address, the R_DMA_IRQ bit will be set to
1 automatically, and this bit could be cleared to 0 by CPU. The bit is
hardwired to ARM as interrupt request signal with an inverter.
The R_DMA_IRQ bit is read/write (write 1 to clear)
T_DMA_IRQ
Transmit DMA interrupt request bit. When DMA current address reach the
middle address (((ACTL_DESE – ACTL_DESB)-1)/2 + ACTL_DESB) or
reach the end address ACTL_DESB, the bit T_DMA_IRQ will be set to 1, and
this bit could be clear to 0 by write “1” by CPU. And the bit is hardwired to
ARM as interrupt request signal with an inverter.
The T_DMA_IRQ bit is read/write (write 1 to clear).
I²S or AC-link pin selection
[8]
I²S_AC_PIN_SEL
[7]
FIFO_TH
[6]
Reserved
• If I²S_AC_PIN_SEL = 0, the pins select I²S
• If I²S_AC_PIN_SEL = 1, the pins select AC-link
The I²S_AC_PIN_SEL bis is read/write
FIFO threshold control bit
• If FIFO_TH=0, the FIFO threshold is 8 level
• If FIFO_TH=1, the FIFO threshold is 4 level
The FIFO_TH bit is read/write
Audio interface type selection
[2:1]
BLOCK_EN[1:0]
[0]
Reserved
• If BLOCK_EN[0]=0/1, I²S interface is disable/enable
• If BLOCK_EN[1]=0/1, AC-link interface is disable/enable
The BLOCK_EN[1:0] bits are read/write
- 241 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Sub-block reset control register (ACTL_RESET)
REGISTER
ACTL_RESET
ADDRESS
R/W
0xFFF0_9004 R/W
DESCRIPTION
RESET VALUE
Sub block reset control
0x0000_0000
The value in ACTL_RESET register control the reset operation in each sub block.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ACTL_RESET
15
14
13
RECORD_SINGLE[1:0]
12
PLAY_SINGLE[1:0]
7
6
5
AC_PLAY
I²S_RECORD
I²S_PLAY
[16]
[15:14]
10
9
3
Reserved
2
8
AC_RECOR
D
Reserved
4
BITS
[31:17]
11
1
0
AC_RESET
I²S_RESET
DESCRIPTIONS
Reserved
ACTL_RESET
RECORD_SINGLE
[1:0]
Audio controller reset control bit
1 = the whole audio controller is reset
0 = the audio controller is normal operation
The ACTL_RESET bit is read/write
record single/dual channel select bits
2’b11= the record is dual channel
2’b01= the record only select left channel
2’b10= the record only select right channel
2’b00 is reserved
Note that, when ADC is selected as record path, it only
support left channel record.
The PLAY_SINGLE[1:0] bits are read/write
- 242 -
W90N745CD/W90N745CDG
Continued.
BITS
[13:12]
[8]
[7]
[6]
[5]
[1]
[0]
DESCRIPTIONS
PLAY_SINGLE
[1:0]
AC_RECORD
AC_PLAY
I²S_RECORD
I²S_PLAY
Playback single/dual channel select bits
PLAY_SINGLE[1:0]=11, the playback is in stereo mode
PLAY_SINGLE[1:0]=10, the playback is in mono mode
PLAY_SINGLE[1:0]= 00 & 01 is reserved
The PLAY_SINGLE[1:0] bits are read/write
AC link record control bit
AC_RECORD=0, the record path of AC link is disable
AC_RECORD=1, the record path of AC link is enable
The AC_RECORD bit is read/write
AC link playback control bit
AC_PLAY=0, the playback path of AC link is disable
AC_PLAY=1, the playback path of AC link is enable
The AC_PLAY bit is read/write
I²S record control bit
I²S_RECORD=0, the record path of I²S is disable
I²S_RECORD=1, the record path of I²S is enable
The I²S_RECORD bit is read/write
I²S playback control bit
I²S_PLAY=0, the playback path of I²S is disable
I²S_PLAY=1, the playback path of I²S is enable
The I²S_PLAY bit is read/write
AC_RESET
AC link sub block RESET control bit
AC_RESET=0, release the AC link function block from reset
mode
AC_RESET=1, force the AC link function block to reset mode
The AC_RESET bit is read/write
I²S_RESET
I²S sub block RESET control bit
I²S_RESET=0, release the I²S function block from reset
mode
I²S_RESET=1, force the I²S function block to reset mode
The I²S_RESET bit is read/write
DMA record destination base address (ACTL_RDSTB)
REGISTER
ACTL_RDSTB
ADDRESS
R/W
0xFFF0_9008 R/W
DESCRIPTION
DMA record destination base address
- 243 -
RESET VALUE
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
The value in ACTL_RDSTB register is the record destination base address of DMA, and only could be
changed by CPU.
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
AUDIO_RDSTB[31:24]
23
22
21
20
19
AUDIO_RDSTB[23:16]
15
14
13
12
11
AUDIO_RDSTB[15:8]
7
6
5
4
3
AUDIO_RDSTB[7:0]
BITS
[31:0]
DESCRIPTIONS
AUDIO_RDSTB[31:0]
32-bit record destination base address
The AUDIO_RDSTB[31:0] bits is read/write.
DMA destination end address (ACTL_RDST_LENGTH)
REGISTER
ADDRESS
ACTL_RDST_LENGTH
R/W
DESCRIPTION
DMA record
0xFFF0_900
R/W
length
C
destination
RESET VALUE
address
0x0000_0000
The value in ACTL_RDST_LENGTH register is the record destination address length of DMA, and the
register could only be changed by CPU.
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
AUDIO_RDST_L[31:24]
23
22
21
20
19
AUDIO_RDST_L[23:16]
15
14
13
12
11
AUDIO_RDST_L[15:8]
7
6
5
4
3
AUDIO_RDST_L[7:0]
- 244 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
32-bit record destination address length
[31:0]
AUDIO_RDST_L[31:0]
The AUDIO_RDST_L[31:0] bits is read/write.
DMA destination current address (ACTL_RDSTC)
REGISTER
ACTL_RDSTC
ADDRESS
R/W
0xFFF0_9010 RO
DESCRIPTION
RESET VALUE
DMA record destination current address
0x0000_0000
The value in ACTL_RDSTC is the DMA record destination current address, this register could only be
read by CPU.
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
AUDIO_RDSTC[31:24]
23
22
21
20
19
AUDIO_RDSTC[23:16]
15
14
13
12
11
AUDIO_RDSTC[15:8]
7
6
5
4
3
AUDIO_RDSTC[7:0]
BITS
[31:0]
DESCRIPTIONS
AUDIO_RDSTC[31:0]
32-bit record destination current address
The AUDIO_RDSTC[31:0] bits is read only.
Audio controller record status register (ACTL_RSR)
REGISTER
ACTL_RSR
ADDRESS
R/W
0xFFF0_9014 R/W
DESCRIPTION
RESET VALUE
Audio controller FIFO and DMA status
register for record
0x0000_0000
- 245 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
17
16
9
8
1
0
Reserved
23
22
21
20
19
18
Reserved
15
14
13
12
11
10
Reserved
7
6
5
4
3
Reserved
2
R_FIFO_FULL
BITS
R_DMA_END_IRQ R_DMA_MIDDLE_IRQ
DESCRIPTIONS
[31:3]
Reserved
Record FIFO full indicator bit
[2]
R_FIFO_FULL
R_FIFO_FULL=0, the record FIFO not full
R_FIFO_FULL=1, the record FIFO is full
The R_FIFO_READY bit is read only
DMA end address interrupt request bit for record
[1]
R_DMA_END_IRQ
R_DMA_END_IRQ=0, means record DMA address does not
reach the end address
R_DMA_END_IRQ=1, means record DMA address reach the end
address
The R_DMA_END_IRQ bit is readable, and only can be clear by
write “1” to this bit
DMA address interrupt request bit for record
[0]
R_DMA_MIDDLE
_IRQ
R_DMA_MIDDLE_IRQ=0, means record DMA address does not
reach the middle address
R_DMA_MIDDLE_IRQ=1, means record DMA address reach the
middle address
The R_DMA_MIDDLE_IRQ bit is readable, and only can be clear
by write “1” to this bit
DMA play destination base address (ACTL_PDSTB)
REGISTER
ACTL_PDSTB
ADDRESS
R/W
0xFFF0_9018 R/W
DESCRIPTION
DMA play destination base address
RESET VALUE
0x0000_0000
The value in ACTL_PDSTB register is the play destination base address of DMA, and only could be
changed by CPU.
- 246 -
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
AUDIO_PDSTB[31:24]
23
22
21
20
19
AUDIO_PDSTB[23:16]
15
14
13
12
11
AUDIO_PDSTB[15:8]
7
6
5
4
3
AUDIO_PDSTB[7:0]
BITS
[31:0]
DESCRIPTIONS
AUDIO_PDSTB[31:0]
32-bit play destination base address
The AUDIO_PDSTB[31:0] bits is read/write.
DMA destination end address (ACTL_PDST_LENGTH)
REGISTER
ADDRESS
ACTL_PDST_LENGTH
R/W
DESCRIPTION
RESET VALUE
0xFFF0_901
R/W DMA play destination address length
C
0x0000_0000
The value in ACTL_PDST_LENGTH register is the play destination address length of DMA, and the
register could only be changed by CPU.
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
AUDIO_PDST_L[31:24]
23
22
21
20
19
AUDIO_PDST_L[23:16]
15
14
13
12
11
AUDIO_PDST_L[15:8]
7
6
5
4
3
AUDIO_PDST_L[7:0]
- 247 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
[31:0]
DESCRIPTIONS
32-bit play destination address length
AUDIO_PDST_L[31:0]
The AUDIO_PDST_L[31:0] bits is read/write.
DMA destination current address (ACTL_PDSTC)
REGISTER
ADDRESS
R/W
0xFFF0_9020 RO
ACTL_PDSTC
DESCRIPTION
RESET VALUE
DMA play destination current address
0x0000_0000
The value in ACTL_PDSTC is the DMA play destination current address, this register could only be
read by CPU.
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
AUDIO_PDSTC[31:24]
23
22
21
20
19
AUDIO_PDSTC[23:16]
15
14
13
12
11
AUDIO_PDSTC[15:8]
7
6
5
4
3
AUDIO_PDSTC[7:0]
BITS
[31:0]
DESCRIPTIONS
AUDIO_PDSTC[31:0]
32-bit play destination current address
The AUDIO_PDSTC[31:0] bits is read/write.
Audio controller playback status register (ACTL_PSR)
REGISTER
ACTL_PSR
ADDRESS
R/W
0xFFF0_9024 R/W
DESCRIPTION
RESET VALUE
Audio controller FIFO and DMA
status register for playback
0x0000_0004
- 248 -
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
17
16
9
8
2
1
0
P_FIFO_EMPTY
P_DMA_END_IRQ
P_DMA_MIDDL
E_IRQ
Reserved
23
22
21
20
19
18
Reserved
15
14
13
12
11
10
Reserved
7
6
5
4
3
Reserved
BITS
DESCRIPTIONS
[31:3]
Reserved
Playback FIFO empty indicator bit
[2]
P_FIFO_EMPTY
P_FIFO_EMPTY=0, the playback FIFO is not empty
P_FIFO_EMPTY=1, the playback FIFO is empty
The P_FIFO_EMPTY bit is read only
DMA end address interrupt request bit for playback
[1]
P_DMA_END_IRQ
P_DMA_END_IRQ=0, means playback DMA address does not
reach the end address
P_DMA_END_IRQ=1, means playback DMA address reach the
end address
The P_DMA_END_IRQ bit is readable, and only can be clear
by write “1” to this bit
DMA address interrupt request bit for playback
[0]
P_DMA_MIDDLE
_IRQ
P_DMA_MIDDLE_IRQ=0, means playback DMA address does
not reach the middle address
P_DMA_MIDDLE_IRQ=1, means playback DMA address reach
the middle address
The P_DMA_MIDDLE_IRQ bit is readable, and only can be
clear by write “1” to this bit
I²S control register (ACTL_I²SCON)
REGISTER
ACTL_I²SCON
ADDRESS
R/W
0xFFF0_9028 R/W
DESCRIPTION
I²S control register
RESET VALUE
0x0000_0000
The ACTL_I²SCON is the I²S basic operation control register.
- 249 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
PRS[3:0]
13
12
11
10
9
8
2
1
0
Reserved
7
6
BCLK_SEL[1:0]
5
4
3
FS_SEL
MCLK_SEL
FORMAT
BITS
[31:20]
Reserved
DESCRIPTIONS
Reserved
I²S frequency pre-scaler selection bits. (FPLL is the input PLL
frequency, MCLK is the output main clock)
PSR[3:0]=0000, MCLK=FPLL/1
PSR[3:0]=0001, MCLK=FPLL/2
PSR[3:0]=0010, MCLK=FPLL/3
PSR[3:0]=0011, MCLK=FPLL/4
PSR[3:0]=0100, MCLK=FPLL/5
PSR[3:0]=0101, MCLK=FPLL/6
PSR[3:0]=0110, MCLK=FPLL/7
PSR[3:0]=0111, MCLK=FPLL/8
[19:16]
PRS[3:0]
PSR[3:0]=1000, reserved
PSR[3:0]=1001, MCLK=FPLL/10
PSR[3:0]=1010, reserved
PSR[3:0]=1011, MCLK=FPLL/12
PSR[3:0]=1100, reserved
PSR[3:0]=1101, MCLK=FPLL/14
PSR[3:0]=1110, reserved
PSR[3:0]=1111, MCLK=FPLL/16
(when the division factor is 3/5/7, the duty cycle of MCLK is not
50%, the high duration is 0.5*FPLL)
The PSR[3:0] bits are read/write
- 250 -
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
I²S serial data clock frequency selection bit
[7:6]
BCLK_SEL
[1:0]
BCLK_SEL[1:0]=00, 32fs is selected (fs is sampling rate), when
FS_SEL=0, the frequency of bit clock is MCLK/8, when
FS_SEL=1, the frequency of bit clock is MCLK/12.
BCLK_SEL[1:0]=01, 48fs is selected (only when FS_SEL=1, this
term could be selection), when FS_SEL=1, the frequency of bit
clock is MCLK/8.
The BCLK_SEL[1:0] bits are read/write
I²S sampling frequency selection bit
[5]
FS_SEL
FS_SEL=0, FMCLK/256 is selected (FMCLK is the frequency of
signal MCLK)
FS_SEL=1, FMCLK/384 is selected
The FS_SEL bit is read/write
I²S MCLK output selection bit
[4]
MCLK_SEL
MCLK_SEL=0, I²S MCLK output will follow the PRS[3:0] setting.
MCLK_SEL=1, I²S MCLK output will be the same with FPLL.
The MCLK_SEL bit is read/write
I²S format selection bits
[3]
FORMAT
[2:0]
Reserved
FORMAT=0, I²S compatible format is selected
FORMAT=1, MSB-justified format is selected
The FORMAT bit is read/write
-
AC-link Control Register (ACTL_ACCON)
REGISTER
ACTL_ACCON
ADDRESS
R/W
0xFFF0_902
R/W
C
DESCRIPTION
AC-link control register
RESET VALUE
0x0000_0000
The ACTL_ACCON register is the AC-link basic operation control register.
- 251 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
Reserved
5
4
3
2
1
0
AC_BCLK_
PU_EN
AC_R_FINI
SH
AC_W_FINI
SH
AC_W_RE
S
AC_C_RES
Reserved
BITS
[6]
[5]
[4]
[3]
DESCRIPTIONS
Reserved
-
AC_BCLK_PU_EN
This bit controls the AC_BCLK pin pull-high resister.
AC_BCLK_PU_EN=0, the AC_BCLK pin pull-high resister will be
disabled
AC_BCLK_PU_EN=1, the AC_BCLK pin pull-high resister will be
enabled
The AC_BCLK_PU_EN bit is read/write.
AC_R_FINISH
AC-link read data ready bit. When read data indexed by previous
frame is shifted into ACTL_ACIS2, the AC_R_FINISH bit will be
set to 1 automatically. After CPU read out the read data,
AC_R_FINISH bit will be cleared to 0.
AC_R_FINISH=0, read data buffer has been read by CPU
AC_R_FINISH=1, read data buffer is ready for CPU read
The AC_R_FINISH bit is read only
AC_W_FINISH
AC-link write frame finish bit. When writing data to register
ACTL_ACOS0, the AC_W_FINISH bit will be set to 1
automatically. After AC-link interface shift out the register
ACTL_ACOS0, the AC_W_FINISH bit will be cleared to 0.
AC_W_FINISH=0, AC-link control data out buffer has been shifted
out to codec by CPU and data out buffer is empty.
AC_W_FINISH=1, AC-link control data out buffer is ready to be
shifted out(After users have wrote data into register
ACTL_ACOS0)
The AC_W_FINISH bit is read only
- 252 -
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
AC_W_RES
AC-link warm reset control bit, when this bit is set to 1, (AC-link
begin warn reset procedure, after warn reset procedure finished,
this bit will be cleared automatically) the interface signal
AC_SYNC is high, when this bit is set to 0, the interface signal
AC_SYNC is controlled by AC_BCLK input when this bit is set to
1. Note the AC-link spec. shows it need at least 10 us high
duration of AC_SYNC to warn reset AC97.
AC_W_RES=0, AC_SYNC pin is controlled by AC_BCLK input pin
AC_W_RES=1, AC_SYNC pin is forced to high
The AC_W_RES bit is read/write
[1]
AC_C_RES
AC-link cold reset control bit, when this bit is set to 1, the interface
signal AC_RESETB is low, when this bit is set to 0, the signal
AC_RESETB is high. Note the AC-link spec. shows it need at
least 10 us low duration of AC_RESETB to cold reset AC97.
AC_C_RES=0, AC_RESETB pin is set to 1
AC_C_RES=1, AC_RESETB pin is set to 0
The AC_C_RES bit is read/write
[0]
Reserved
[2]
-
AC-link output slot 0 (ACTL_ACOS0)
REGISTER
ACTL_ACOS0
ADDRESS
R/W
0xFFF0_9030 R/W
DESCRIPTION
RESET VALUE
0x0000_0000
AC-link out slot 0
The ACTL_ACOS0 register store the slot 0 value to be shift out by AC-link. Note that write data to
ACTL_ACOS0 register when AC_W_FINISH bit (ACTL_ACCON[3]) is set is invalid. Therefore, check
AC_W_FINISH bit status before write data into ACTL_ACOS0 register.
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
Reserved
5
4
VALID_
FRAME
SLOT_VALID[3:0]
- 253 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:5]
Reserved
Frame valid indicated bits
[4]
VALID_FRAME=1, any one of slot is valid
VALID_FRAME=0, no any slot is valid
The VALID_FRAME bits are read/write
VALID_FRAME
Slot valid indicated bits
[3:0]
SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid
SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid
SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid
SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid
The SLOT_VALID[3:0] bits are read/write
SLOT_VALID
[3:0]
The AC-link output slot 1 (ACTL_ACOS1)
REGISTER
ACTL_ACOS1
ADDRESS
R/W
0xFFF0_9034 R/W
DESCRIPTION
RESET VALUE
0x0000_0080
AC-link out slot 1
The ACTL_ACOS1 register store the slot 1 value to be shift out by AC-link.
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
R_WB
6
5
4
R_INDEX[6:0]
- 254 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:8]
Reserved
Read/Write select bit
[7]
R_WB
[6:0]
R_INDEX[6:0]
R_WB=1, a read specified by R_INDEX[6:0] will occur, and the
data will appear in next frame
R_WB=0, a write specified by R_INDEX[6:0] will occur, and the
write data is put at out slot 2
The R_WB bit is read/write
External AC97 CODEC control register index (address) bits
The R_INDEX[6:0] bits are read/write
AC-link output slot 2 (ACTL_ACOS2)
REGISTER
ACTL_ACOS2
ADDRESS
R/W
0xFFF0_9038 R/W
DESCRIPTION
RESET VALUE
AC-link out slot 2
0x0000_0000
The ACTL_ACOS2 register store the slot 2 value to be shift out by AC-link.
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
WD[15:8]
7
6
5
4
WD[7:0]
BITS
DESCRIPTIONS
[31:0]
Reserved
[15:0]
WD[15:0]
AC-link write data
The WD[15:0] bits are read/write
- 255 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
AC-link input slot 0 (ACTL_ACIS0)
REGISTER
ACTL_ACIS0
ADDRESS
R/W
0xFFF0_903
C
R
DESCRIPTION
RESET VALUE
AC-link in slot 0
0x0000_0000
The ACTL_ACIS0 store the shift in slot 0 data of AC-link.
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
CODEC_READ
Y
Reserved
BITS
[31:5]
SLOT_VALID[3:0]
DESCRIPTIONS
Reserved
External AC97 audio CODEC ready bit
[4]
CODEC_READY
CODEC_READY=0, indicate external AC97 audio CODEC is not
ready
CODEC_READY=1, indicate external AC97 audio CODEC is ready
The CODEC_READY bit is read only
Slot valid indicated bits
[3:0]
SLOT_VALID[3:0]
SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid
SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid
SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid
SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid
The SLOT_VALID[3:0] bits are read
- 256 -
W90N745CD/W90N745CDG
AC-link input slot 1 (ACTL_ACIS1)
REGISTER
ACTL_ACIS1
ADDRESS
R/W
0xFFF0_9040
R
DESCRIPTION
RESET VALUE
AC-link in slot 1
0x0000_0000
The ACTL_ACIS1 stores the shift in slot 1 data of AC-link.
31
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
4
R_INDEX[6]
3
2
R_INDEX[5:0]
BITS
[31:9]
[8:2]
1
0
SLOT_REQ[1:0]
DESCRIPTIONS
Reserved
R_INDEX[6:0]
Register index. The R_INDEX[6:0] echo the register index (address)
when a register read has been requested in the previous frame.
The R_INDEX[6:0] bits are read only
Slot request. The bits indicate if the external codec need new PCM
data that will transfer in next frame.
[1:0]
SLOT_REQ[1:0]
Any bit in SLOT_REQ[1:0] is set to 1, indicate external codec does
not need a new sample in the corresponding slot[3:4] of the next
frame
Any SLOT_REQ[1:0] is clear to 0, indicate external codec need a
new sample in the corresponding slot[3:4] of the next frame
The SLOT_REQ[1:0] bits are read only
- 257 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
AC-link input slot 2 (ACTL_ACIS2)
REGISTER
ACTL_ACIS2
ADDRESS
R/W
0xFFF0_9044
R
DESCRIPTION
RESET VALUE
AC-link in slot 2
0x0000_0000
The ACTL_ACIS2 stores the shift in slot 2 data of AC-link.
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
RD[15:8]
7
6
5
4
RD[7:0]
BITS
DESCRIPTIONS
[31:16]
Reserved
[15:0]
RD[15:0]
AC-link read data.
The RD[15:0] bits are read only
- 258 -
W90N745CD/W90N745CDG
7.10 Universal Asynchronous Receiver/Transmitter Controller
Asynchronous serial communication block include 4 UART blocks and accessory logic. They can be
described as follow:
•
UART0
It is merely a general purpose UART. It does not include any accessory function.
•
Clock Source
: 15MHz
UART Type
: general UART
FIFO Number
: 16-byte receiving FIFO and 16 byte transmitting FIFO
Modem Function
: N/A
Accessory Function
: N/A
UART1
It is designed for general purpose UART or Bluetooth transceiver. It includes a high speed
UART block with 64-byte receiving FIFO and 64-byte transmitting FIFO. It includes 5 clock
sources: 15M, 30M, 43.6M, 48M and 60M. Programmer can feel free to choose the clock
source and divisor number for suitable baud rate.
Clock Source
: 15MHz from external crystal
30M, 43.6M, 48M, 60M (optional function for Bluetooth HCI
transport layer)
•
UART Type
: high speed UART
FIFO Number
: 64-byte receiving FIFO and 64 byte transmitting FIFO
Modem Function
: CTS and RTS (optional for Bluetooth. If they were enabled, TX & RX
in UART2 will be cut off)
Accessory Function
: Bluetooth (optional)
Baud Rate (max)
: 1.875MHz
I/O pin
: TXD1, RXD1, RTS, CTS (optional)
UART2
It is designed for general purpose UART or IrDA SIR. The part of UART includes 16-byte
receiving FIFO and 16-byte transmitting FIFO. TXD2/RXD2 of UART2 occupy the same
pins with RTS and CTS of UART1. Once the Bluetooth function has been enabled, UART2
should be disabled.
Clock Source
: 15MHz
- 259 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
•
UART Type
: general UART
FIFO Number
: 16-byte receiving FIFO and 16 byte transmitting FIFO
Modem Function
: N/A
Accessory Function
: IrDA SIR (optional)
I/O Pin
: TXD2, RXD2.
I/O Pin Share with
: UART1 (Bluetooth function)
UART3
It is also merely a general purpose UART. It does not include any accessory function. It
share four I/O pins with AC97/I²S.
Clock Source
: 15MHz
UART Type
: general UART
FIFO Number
: 16-byte receiving FIFO and 16 byte transmitting FIFO
Modem Function
: DTR, DSR
Accessory Function
: N/A
I/O Pin
: TXD3, RXD3, DTR, DSR
I/O Pin Share with
: AC97_DATAO, AC97_DATAI, AC97_SYNC, AC97_BITCLK
Table 7.10.1 W90N745 UART features list
BLOCK
NUMBER
UART TYPE
CLOCK
SOURCE
0
General
UART
15M
1
High speed
UART
15M,
43.6M,
60M
2
General
UART
15M
3
General
UART
15M
30M,
48M,
MODEM
FUNCTION
SIGNALS
IO PINS
DESIGN TARGET
N/A
TxD0,
RXD0
General UART
CTS, RTS
TXD1,
RXD1,
CTS1,
RTS1
General
Bluetooth
N/A
TX2, RX2
General
SIR
DTR, DSR
TXD3,
RXD3,
DRT3,
DSR3
General UART
- 260 -
UART/
UART/IrDA
W90N745CD/W90N745CDG
7.10.1 UART0
UART0 is a general UART block. It is same as the UART in W90N740 but without Modem I/O signals.
More detail function description, please refer to section 7.10.5 General UARTcontroller description
Table 7.10.1.1 UART0 Register Map
ADDRESS
R/W
OTHER
CONDITION
RESET VALUE
UART0_RBR
0xFFF8_0000
R
DLAB=0
Undefined
UART0_THR
0xFFF8_0000
W
DLAB=0
Undefined
UART0_IER
0xFFF8_0004
R/W
DLAB=0
0x0000_0000
UART0_DLL
0xFFF8_0000
R/W
DLAB=1
0x0000_0000
UART0_DLM
0xFFF8_0004
R/W
DLAB=1
0x0000_0000
UART0_IIR
0xFFF8_0008
R
0x8181_8181
UART0_FCR
0xFFF8_0008
W
Undefined
UART0_LCR
0xFFF8_000c
R/W
0x0000_0000
Reserved
0xFFF8_0010
UART0_LSR
0xFFF8_0014
R
0x6060_6060
Reserved
0xFFF8_0018
UART0_TOR
0xFFF8_001c
R/W
0x0000_0000
REGISTER
7.10.2 UART1
The UART1 is designed for general purpose UART or Bluetooth HCI transport layer. It is a high speed
UART with 64-byte receive FIFO and 64-byte transmit FIFO. To perform 1.875MHz maximum baud
rate, UART1 has 5 clock sources, 15M, 30M, 43.6M, 48M, and 60M. The first one is from external
15M crystal clock and the other are divided from system PLL 480MHz output. More detail about high
speed UART, please refer to next section 7.10.6 High Speed UART controller function description.
The block UART1 offer 4 I/O signals, TX, RX, CTS, and RTS. CTS and RTS are used as flow control
for Bluetooth. CTS and RTS share the same I/O pins with TX and RX in block UART2.
- 261 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 7.10.2.1 UART1 Register Map
ADDRESS
R/W
OTHER
CONDITION
RESET VALUE
UART1_RBR
0xFFF8_0100
R
DLAB=0
Undefined
UART1_THR
0xFFF8_0100
W
DLAB=0
Undefined
UART1_IER
0xFFF8_0104
R/W
DLAB=0
0x0000_0000
UART1_DLL
0xFFF8_0100
R/W
DLAB=1
0x0000_0000
UART1_DLM
0xFFF8_0104
R/W
DLAB=1
0x0000_0000
UART1_IIR
0xFFF8_0108
R
0x8181_8181
UART1_FCR
0xFFF8_0108
W
Undefined
UART1_LCR
0xFFF8_010c
R/W
0x0000_0000
UART1_MCR
0xFFF8_0110
R/W
0x0000_0000
UART1_LSR
0xFFF8_0114
R
0x6060_6060
UART1_MSR
0xFFF8_0118
R
0x0000_0000
UART1_TOR
0xFFF8_011c
R/W
0x0000_0000
UART1_UBCR
0xFFF8_0120
R/W
0x0000_0000
REGISTER
UART1 Bluetooth Control Register (UART1_UBCR)
REGISTER
ADDRESS
R/W
UART1_UBCR 0xFFF8_0120
31
30
DESCRIPTION
RESET VALUE
R/W UART 1 Bluetooth Control Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Reserved
UBCR[2:0]
- 262 -
W90N745CD/W90N745CDG
BITS
[31:3]
DESCRIPTIONS
Reserved
UBCR is a 3 bits register which is used to select clock source to
generate suitable baud rate:
000: 15Mhz from external crystal
[2:0]
UBCR
100: 30Mhz divided from PLL 480Mhz
101: 43.6Mhz divided from PLL 480Mhz
110: 48Mhz divided from PLL 480Mhz
111: 60Mhz divided from PLL 480Mhz
7.10.3 UART2
UART2 contains 2 features: general UART and IrDA SIR decoder/encoder. UART is same as the
UART of W90N740 but without modem function. Please read the spec of section 7.10.5 General
UART controller function description. The IrDA SIR is described as follow:
Table 7.10.3.1 UART2 Register Map
REGISTER
ADDRESS
R/W
OTHER
CONDITION
RESET VALUE
UART2_RBR
0xFFF8_0200
R
DLAB=0
Undefined
UART2_THR
0xFFF8_0200
W
DLAB=0
Undefined
UART2_IER
0xFFF8_0204
R/W
DLAB=0
0x0000_0000
UART2_DLL
0xFFF8_0200
R/W
DLAB=1
0x0000_0000
UART2_DLM
0xFFF8_0204
R/W
DLAB=1
0x0000_0000
UART2_IIR
0xFFF8_0208
R
0x8181_8181
UART2_FCR
0xFFF8_0208
W
Undefined
UART2_LCR
0xFFF8_020c
R/W
0x0000_0000
Reserved
0xFFF8_0210
UART2_LSR
0xFFF8_0214
Reserved
0xFFF8_0218
UART2_TOR
0xFFF8_021c
R/W
0x0000_0000
UART2_IRCR
0xFFF8_0220
R/W
0x0000_0040
Undefined
R
0x6060_6060
Undefined
UART2 IrDA Control Register (UART2_IRCR)
REGISTER
ADDRESS
UART2_IRC
0xFFF8_0220
R/W
DESCRIPTION
R/W UART 2 IrDA Control Register
- 263 -
RESET VALUE
0x0000_0040
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
R
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
Reserved
INV_RX
INV_TX
Reserved
Reserved
LB
BITS
DESCRIPTIONS
[31:7]
Reserved
[6]
INV_RX
Reserved
1: Inverse RX input signal
0: No inversion
[5]
INV_TX
1: Inverse TX output signal
0: No inversion
[4:3]
Reserved
Reserved
IrDA loop back mode for self test.
[2]
LB
1: enable IrDA loop back mode
0: disable IrDA loop back mode
[1]
TX_SELECT
1: enable IrDA transmitter
0: enable IrDA receiver
[0]
IrDA_EN
1: enable IrDA block
0: disable IrDA block
- 264 -
TX_SELECT IrDA_EN
W90N745CD/W90N745CDG
7.10.4 UART3
UART3 is a general UART block. It is same as the UART in W90N740 but with some Modem I/O
signals.
More detail general UART function description, please refer to next section 7.10.5 General UART
controller.
Table 7.10.4.1 UART3 register map
REGISTER
ADDRESS
R/W
OTHER CONDITION
RESET VALUE
UART3_RBR
UART3_THR
UART3_IER
UART3_DLL
UART3_DLM
UART3_IIR
UART3_FCR
UART3_LCR
UART3_MCR
UART3_LSR
UART3_MSR
UART3_TOR
0xFFF8_0300
0xFFF8_0300
0xFFF8_0304
0xFFF8_0300
0xFFF8_0304
0xFFF8_0308
0xFFF8_0308
0xFFF8_030c
0xFFF8_0310
0xFFF8_0314
0xFFF8_0318
0xFFF8_031c
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R
R
R/W
DLAB=0
DLAB=0
DLAB=0
DLAB=1
DLAB=1
Undefined
Undefined
0x0000_0000
0x0000_0000
0x0000_0000
0x8181_8181
Undefined
0x0000_0000
0x0000_0000
0x6060_6060
0x0000_0000
0x0000_0000
UART3 Modem Control Register (UART3_MCR)
REGISTER
ADDRESS
R/W
UART3_MCR 0xFFF8_0310
31
30
DESCRIPTION
RESET VALUE
R/W UART 3 Modem Control Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
LBME
Reserved
Reserved
Reserved
DTR#
Note: UART3_MCR is subset of MCR in W90N745. Please refer to section 7.10.5 ‘General UART Controller’.
- 265 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
UART3 Modem Status Register (UART3_MSR)
REGISTER
ADDRESS
R/W
UART3_MSR 0xFFF8_0318
31
30
R
DESCRIPTION
RESET VALUE
UART 3 Modem Status Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
Reserved
Reserved
DSR#
Reserved
Reserved
Reserved
DDSR
Reserved
Note: UART3_MSR is subset of MSR in W90N745. Please refer to section 7.10.5 ‘General UART Controller’.
7.10.5 General UART Controller
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion
on data characters received from the peripheral such as MODEM, and a parallel-to-serial conversion on
data characters received from the CPU. There are five types of interrupts, i.e., line status interrupt,
transmitter FIFO empty interrupt, receiver threshold level reaching interrupt, time out interrupt,
and MODEM status interrupt. One 16-byte transmitter FIFO (TX_FIFO) and one 16-byte (plus 3-bit of
error data per byte) receiver FIFO (RX_FIFO) has been built in to reduce the number of interrupts
presented to the CPU. The CPU can completely read the status of the UART at any time during the
operation. The reported status information includes the type and condition of the transfer operations
being performed by the UART, as well as any error conditions (parity, overrun, framing, or break
interrupt) found. The UART includes a programmable baud rate generator that is capable of dividing
crystal clock input by divisors to produce the clock that transmitter and receiver needed. The equation is
BaudOut = crystal clock / 16 * [Divisor + 2].
The UART includes the following features:
Transmitter and receiver are buffered with a 16-byte FIFO each to reduce the number of interrupts
presented to the CPU.
Subset of MODEM control functions (DSR, DTR, by IP selection)
Fully programmable serial-interface characteristics:
--
5-, 6-, 7-, or 8-bit character
--
Even, odd, or no-parity bit generation and detection
--
1-, 1&1/2, or 2-stop bit generation
--
Baud rate generation
Line break generation and detection
- 266 -
W90N745CD/W90N745CDG
False start bit detection
Full prioritized interrupt system controls
Loop back mode for internal diagnostic testing
7.10.5.1.
UART Control Registers Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER
OFFSET
R/W
DESCRIPTION
UART_RBR
0x00
R
Receive Buffer Register (DLAB = 0)
Undefined
UART_THR
0x00
W
Transmit Holding Register (DLAB = 0)
Undefined
UART_IER
0x04
R/W
Interrupt Enable Register (DLAB = 0)
0x0000_0000
UART_DLL
0x00
R/W
UART_DLM
0x04
R/W
UART_IIR
0x08
R
Interrupt Identification Register
UART_FCR
0x08
W
FIFO Control Register
Undefined
UART_LCR
0x0C
R/W
Line Control Register
0x0000_0000
UART_MCR
0x10
R/W
Modem Control Register (Optional)
0x0000_0000
UART_LSR
0x14
R
Line Status Register
0x6060_6060
UART_MSR
0x18
R
MODEM Status Register (Optional)
0x0000_0000
UART_TOR
0x1C
R/W
Time Out Register
0x0000_0000
Divisor Latch Register (LS)
RESET VALUE
0x0000_0000
(DLAB = 1)
Divisor Latch Register (MS)
0x0000_0000
(DLAB = 1)
0x8181_8181
Note: Real register address = 0xFFF8_0000+ (UART number – 1) * (0x0100) + offset
Note: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times
before send to APB bus. For example, when ARM CPU read register UARTn_BRR, ARM CPU will get
UART0_RBR = {RBR[7:0], RBR[7:0], RBR[7:0], RBR[7:0]}.
UART Receive Buffer Register (UART_RBR)
REGISTER
OFFSET
R/W
UART_RBR
0x00
R
DESCRIPTION
Receive Buffer Register (DLAB = 0)
- 267 -
RESET VALUE
Undefined
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
8-bit Received Data
BITS
[7:0]
DESCRIPTIONS
By reading this register, the UART will return an 8-bit data
received from SIN pin (LSB first).
8-bit Received Data
UART Transmit Holding Register (UART_THR)
REGISTER
OFFSET
R/W
UART_TH
R
0x00
W
31
30
DESCRIPTION
RESET VALUE
Transmit Holding Register (DLAB = 0)
29
28
Undefined
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
8-bit Transmitted Data
BITS
[7:0]
DESCRIPTIONS
8-bit Transmitted Data
By writing to this register, the UART will send out an 8-bit data
through the SOUT pin (LSB first).
- 268 -
W90N745CD/W90N745CDG
UART Interrupt Enable Register (UART_IER)
REGISTER
OFFSET
R/W
UART_IER
0x04
R/W
31
30
DESCRIPTION
RESET VALUE
Interrupt Enable Register (DLAB = 0)
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
4
3
2
1
0
nDBGACK_E
N
MSIE
RLSIE
THREIE
RDAIE
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
RESERVED
BITS
[31:5]
DESCRIPTIONS
Reserved
ICE debug mode acknowledge enable
0 = When DBGACK is high, the UART receiver time-out clock will
be held
1 = No matter what DBGACK is high or not, the UART receiver
timer-out clock will not be held
[4]
nDBGACK_EN
[3]
MSIE
MODEM Status Interrupt (Irpt_MOS) Enable
0 = Mask off Irpt_MOS
1 = Enable Irpt_MOS
[2]
RLSIE
Receive Line Status Interrupt (Irpt_RLS) Enable
0 = Mask off Irpt_RLS
1 = Enable Irpt_RLS
[1]
[0]
THREIE
Transmit Holding Register Empty Interrupt (Irpt_THRE)
Enable
0 = Mask off Irpt_THRE
1 = Enable Irpt_THRE
RDAIE
Receive Data Available Interrupt (Irpt_RDA) Enable and
Time-out Interrupt (Irpt_TOUT) Enable
0 = Mask off Irpt_RDA and Irpt_TOUT
1 = Enable Irpt_RDA and Irpt_TOUT
- 269 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
UART Divider Latch (Low Byte) Register (UART_DLL)
REGISTER
OFFSET
R/W
UART_DL
L
0x00
R/W
31
30
DESCRIPTION
RESET VALUE
Divisor Latch Register (LS) (DLAB = 1)
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Baud Rate Divider (Low Byte)
BITS
[7:0]
DESCRIPTIONS
Baud Rate Divider (Low Byte)
The low byte of the baud rate divider
UART Divisor Latch (High Byte) Register (UART_DLM)
REGISTER
OFFSET
R/W
UART_DLM
0x04
R/W
31
30
29
DESCRIPTION
RESET VALUE
Divisor Latch Register (MS) (DLAB = 1)
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Baud Rate Divider (High Byte)
- 270 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
Baud Rate Divider (High Byte)
[7:0]
The high byte of the baud rate divider
This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows
Baud Rate = Crystal Clock / {16 * [Divisor + 2]}
Note: This definition is different from 16550
UART Interrupt Identification Register (UART_IIR)
REGISTER
OFFSET
R/W
UART_IIR
0x08
R
31
30
DESCRIPTION
RESET VALUE
Interrupt Identification Register
29
28
0x8181_8181
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
FMES
5
RFTLS
BITS
4
DMS
IID
NIP
DESCRIPTIONS
[7]
FMES
FIFO Mode Enable Status
This bit indicates whether the FIFO mode is enabled or not. Since the FIFO
mode is always enabling, this bit always shows the logical 1 when CPU is
reading this register.
[6:5]
RFTLS
RX FIFO Threshold Level Status
These bits show the current setting of receiver FIFO threshold level (RTHO).
The meaning of RTHO is defined in the following FCR description.
[4]
DMS
DMA Mode Select
The DMA function is not implemented in this version. When reading IIR, the
DMS is always returned 0.
[3:1]
IID
Interrupt Identification
The IID together with NIP indicates the current interrupt request from UART
[0]
NIP
No Interrupt Pending
There is no pending interrupt.
- 271 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
- 272 -
W90N745CD/W90N745CDG
Table 7.10.5.1 Interrupt Control Functions
IIR [3:0]
PRIORITY
INTERRUPT
TYPE
INTERRUPT SOURCE
INTERRUPT RESET
CONTROL
---1
--
None
None
--
0110
Highest
Receiver Line
Status (Irpt_RLS)
Overrun error, parity error,
framing error, or break
interrupt
Reading the LSR
0100
Second
Received Data
Available
(Irpt_RDA)
Receiver FIFO
level is reached
Receiver FIFO drops
below the threshold
level
Second
Receiver FIFO
Time-out
(Irpt_TOUT)
Receiver FIFO is non-empty
and no activities are
occurred in the receiver
FIFO during the TOR
defined time duration
Reading the RBR
Third
Transmitter
Holing Register
Empty
(Irpt_THRE)
Transmitter holding register
empty
Reading the IIR (if
source of interrupt is
Irpt_THRE) or writing
into the THR
Fourth
MODEM Status
(Irpt_MOS)
The CTS, DSR, or DCD bits
are changing state or the RI Reading the MSR
bit is changing from high to (optional)
low.
1100
0010
0000
threshold
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550
UART FIFO Control Register (UART_FCR)
REGISTER
OFFSET
R/W
UART_FCR
0x08
W
31
30
DESCRIPTION
RESET VALUE
FIFO Control Register
29
28
Undefined
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
DMS
TFR
RFR
FME
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
RFITL
5
4
RESERVED
- 273 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
RX FIFO Interrupt (Irpt_RDA) Trigger Level
[7:6]
RFITL [7:6]
Irpt_RDA Trigger Level (Bytes)
00
01
01
04
10
08
11
14
RFITL
[3]
[2]
[1]
[0]
DMS
DMA Mode Select
The DMA function is not implemented in this version.
TFR
TX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The
TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is
returned to 0 automatically after the reset pulse is generated.
RFR
RX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The
RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit
is returned to 0 automatically after the reset pulse is generated.
FME
FIFO Mode Enable
Because UART is always operating in the FIFO mode, writing this bit has no
effect while reading always gets logical one. This bit must be 1 when other
FCR bits are written to; otherwise, they will not be programmed.
UART Line Control Register (UART_LCR)
REGISTER
OFFSET
R/W
UART_LCR
0x0C
R/W
31
30
29
DESCRIPTION
RESET VALUE
Line Control Register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
DLAB
BCB
SPE
EPE
PBE
NSB
- 274 -
WLS
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
Divider Latch Access Bit
[7]
DLAB
0 = It is used to access RBR, THR or IER.
1 = It is used to access Divisor Latch Registers {DLL, DLM}
Break Control Bit
[6]
BCB
When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing
State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic.
Stick Parity Enable
0 = Disable stick parity
[5]
SPE
1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as
a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit
enable) is set.
Even Parity Enable
[4]
EPE
0 = Odd number of logic 1’s are transmitted or checked in the data word and
parity bits.
1 = Even number of logic 1’s are transmitted or checked in the data word and
parity bits.
This bit has effect only when bit 3 (parity bit enable) is set.
Parity Bit Enable
[3]
PBE
0 = Parity bit is not generated (transmit data) or checked (receive data) during
transfer.
1 = Parity bit is generated or checked between the "last data word bit" and "stop bit"
of the serial data.
Number of “STOP bit”
0= One “ STOP bit” is generated in the transmitted data
[2]
NSB
1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word
length is selected;
Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected.
Word Length Select
[1:0]
WLS
WLS[1:0]
Character length
00
5 bits
01
6 bits
10
7 bits
11
8 bits
- 275 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
UART Modem Control Register (UART_MCR)
REGISTER
OFFSET
R/W
UART_MCR
0x10
R/W
31
30
29
DESCRIPTION
RESET VALUE
0x0000_0000
Modem Control Register (Optional)
28
27
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
Reserved
BITS
[31:5]
4
3
2
1
0
LBME
Reserve
Reserve
Reserved
DTR#
DESCRIPTIONS
Reserved
-
Loop-back Mode Enable
0 = Disable
[4]
LBME
1 = When the loop-back mode is enabled, the following signals are connected
internally
SOUT connected to SIN and SOUT pin fixed at logic 1
DTR# connected to DSR# and DTR# pin fixed at logic 1
[3:1]
Reserved
Complement version of DTR# (Data-Terminal-Ready) signal
[0]
DTR
Writing 0x00 to MCR, the DTR# bit are set to logic 1’s;
Writing 0x0f to MCR, the DTR# bit are reset to logic 0’s.
UART Line Status Control Register (UART_LSR)
REGISTER
OFFSET
R/W
UART_LSR
0x14
R
DESCRIPTION
Line Status Register
- 276 -
RESET VALUE
0x6060_6060
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
ERR_RX
TE
THRE
BII
FEI
PEI
OEI
RFDR
BITS
[31:8]
DESCRIPTIONS
Reserved
-
RX FIFO Error
0 = RX FIFO works normally
[7]
ERR_RX
1 = There is at least one parity error (PE), framing error (FE), or break
indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and
if there are no subsequent errors in the RX FIFO.
Transmitter Empty
[6]
TE
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift
Register (TSR) are not empty.
1 = Both THR and TSR are empty.
Transmitter Holding Register Empty
0 = THR is not empty.
1 = THR is empty.
[5]
THRE
THRE is set when the last data word of TX FIFO is transferred to Transmitter
Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is
loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the
CPU when IER [1]=1.
Break Interrupt Indicator
[4]
BII
This bit is set to a logic 1 whenever the received data input is held in the
"spacing state" (logic 0) for longer than a full word transmission time (that is,
the total time of "start bit" + data bits + parity + stop bits) and is reset
whenever the CPU reads the contents of the LSR.
Framing Error Indicator
[3]
FEI
This bit is set to logic 1 whenever the received character does not have a
valid "stop bit" (that is, the stop bit following the last data bit or parity bit is
detected as a logic 0), and is reset whenever the CPU reads the contents of
the LSR.
- 277 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
Parity Error Indicator
[2]
This bit is set to logic 1 whenever the received character does not have a
valid "parity bit", and is reset whenever the CPU reads the contents of the
LSR.
PEI
Overrun Error Indicator
[1]
An overrun error will occur only after the RX FIFO is full and the next
character has been completely received in the shift register. The character
in the shift register is overwritten, but it is not transferred to the RX FIFO.
OE is indicated to the CPU as soon as it happens and is reset whenever
the CPU reads the contents of the LSR.
OEI
RX FIFO Data Ready
[0]
0 = RX FIFO is empty
RFDR
1 = RX FIFO contains at least 1 received data word.
LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not
suggested)
UART Modem Status Register (UART_MSR)
REGISTER
OFFSET
R/W
UART_MSR
0x18
R
31
30
DESCRIPTION
RESET VALUE
0x0000_0000
MODEM Status Register (Optional)
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
Reserved
Reserved
DSR#
Reserved
Reserved
Reserved
DDSR
Reserved
- 278 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:6]
Reserved
[5]
DSR#
[4:2]
Reserved
[1]
DDSR
[0]
Reserved
-
Complement version of data set ready (DSR#) input
(This bit is selected by IP)
DSR# State Change (This bit is selected by IP)
This bit is set whenever DSR# input has changed state, and it will be reset
if the CPU reads the MSR.
-
Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
UART Time Out Register (UART_TOR)
REGISTER
OFFSET
R/W
UART_TOR
0x1C
R/W
31
30
DESCRIPTION
RESET VALUE
Time Out Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
TOIE
TOIC
BITS
DESCRIPTIONS
[31:8]
Reserved
[7]
TOIE
Time Out Interrupt Enable
The feature of receiver time out interrupt is enabled when TOR [7] = IER[0] = 1.
TOIC
Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock = baud
rate) whenever the RX FIFO receives a new data word. Once the content of
time out counter (TOUT_CNT) is equal to that of time out interrupt
comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if
TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears
Irpt_TOUT.
[6:0]
-
- 279 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.10.6 High speed UART Controller
The High Speed Universal Asynchronous Receiver/Transmitter (HS_UART) performs a serial-toparallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion
on data characters received from the CPU. There are five types of interrupts, they are, transmitter
FIFO empty interrupt, receiver threshold level reaching interrupt, line status interrupt (overrun error or
parity error or framing error or break interrupt) ,time out interrupt, and Modem status interrupt . One
64-byte transmitter FIFO (TX_FIFO) and one 64-byte (plus 3-bit of error data per byte) receiver FIFO
(RX_FIFO) has been built in to reduce the number of interrupts presented to the CPU. The CPU can
completely read the status of the UART at any time during the operation. The reported status
information includes the type and condition of the transfer operations being performed by the UART,
as well as any error conditions (parity, overrun, framing, or break interrupt) found. The UART includes
a programmable baud rate generator that is capable of dividing crystal clock input by divisors to
produce the clock that transmitter and receiver needed. The equation is
Baud Out = crystal clock / 16 * [Divisor + 2].
The UART includes the following features:
Transmitter and receiver are buffered with a 64-byte FIFO each to reduce the number of interrupts
presented to the CPU.
Subset of MODEM control function(selected by IP)
Fully programmable serial-interface characteristics:
¾
5-, 6-, 7-, or 8-bit character
¾
Even, odd, or no-parity bit generation and detection
¾
1-, 1&1/2, or 2-stop bit generation
¾
Baud rate generation
False start bit detection
Full-prioritized interrupt system controls
Not support Loop back mode
7.10.6.1.
High Speed UART Control Registers Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER
OFFSET
R/W
DESCRIPTION
HSUART_RBR
0x00
R
Receive Buffer Register (DLAB = 0)
Undefined
HSUART_THR
0x00
W
Transmit Holding Register (DLAB = 0)
Undefined
HSUART_IER
0x04
R/W Interrupt Enable Register (DLAB = 0)
0x0000_0000
HSUART_DLL
0x00
R/W Divisor Latch Register (LS)(DLAB = 1)
0x0000_0000
HSUART_DLM
0x04
R/W Divisor Latch Register (MS)(DLAB = 1)
0x0000_0000
- 280 -
RESET VALUE
W90N745CD/W90N745CDG
Continued.
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_IIR
0x08
R
Interrupt Identification Register
0x8181_8181
HSUART_FCR
0x08
W
FIFO Control Register
HSUART_LCR
0x0C
R/W Line Control Register
0x0000_0000
HSUART_MCR
0x10
R/W Modem Control Register (Optional)
0x0000_0000
HSUART_LSR
0x14
R
Line Status Register
0x6060_6060
HSUART_MSR
0x18
R
MODEM Status Register (Optional)
0x0000_0000
HSUART_TOR
0x1C
Undefined
0x0000_0000
R/W Time Out Register
Note: Real register address = 0xFFF8_0000+ (UART number – 1) * (0x0100) + offset
NOTE: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times
before send to APB bus. For example, when ARM CPU read register UART1_BRR, ARM CPU will get
UART1_RBR = {RBR[7:0], _RBR[7:0], RBR[7:0], RBR[7:0]}.
HSUART Receive Buffer Register (HSUART_RBR)
REGISTER
OFFSET R/W
HSUART_RBR
0x00
31
30
R
29
DESCRIPTION
RESET VALUE
Receive Buffer Register (DLAB = 0)
Undefined
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
8-bit Received Data
BITS
[7:0]
DESCRIPTIONS
8-bit Received Data
By reading this register, the UART will return an 8-bit data
received from SIN pin (LSB first).
- 281 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
HSUART Transmit Holding Register (HSUART_THR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_THR
0x00
W
Transmit Holding Register (DLAB = 0)
Undefined
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
8-bit Transmitted Data
BITS
DESCRIPTIONS
[7:0]
By writing to this register, the UART will send out an
8-bit data through the SOUT pin (LSB first).
8-bit Transmitted Data
HSUART Interrupt Enable Register (HSUART_IER)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_IER
0x04
R/W
Interrupt Enable Register (DLAB = 0)
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
4
3
2
1
0
nDBGACK_EN
MSIE
RLSIE
THREIE
RDAIE
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
RESERVED
5
- 282 -
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:5]
Reserved
ICE debug mode acknowledge enable
0 = When DBGACK is high, the UART receiver time-out clock will be
held
1 = No matter what DBGACK is high or not, the UART receiver timerout clock will not be held
[4]
nDBGACK_EN
[3]
MSIE
MODEM Status Interrupt (Irpt_MOS) Enable
0 = Mask off Irpt_MOS
1 = Enable Irpt_MOS
[2]
RLSIE
Receive Line Status Interrupt (Irpt_RLS) Enable
0 = Mask off Irpt_RLS
1 = Enable Irpt_RLS
[1]
THREIE
Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable
0 = Mask off Irpt_THRE
1 = Enable Irpt_THRE
RDAIE
Receive Data Available Interrupt (Irpt_RDA) Enable and
Time-out Interrupt (Irpt_TOUT) Enable
0 = Mask off Irpt_RDA and Irpt_TOUT
1 = Enable Irpt_RDA and Irpt_TOUT
[0]
HSUART Divider Latch (Low Byte) Register (HSUART_DLL)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_DL
L
0x00
R/W
Divisor Latch Register (LS) (DLAB = 1)
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Baud Rate Divider (Low Byte)
- 283 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:8]
Reserved
-
[7:0]
Baud Rate Divisor
(Low Byte)
The low byte of the baud rate divider
HSUART Divisor Latch (High Byte) Register (HSUART_DLM)
REGISTER
OFFSET
HSUART_DLM
0x04
31
30
R/W
DESCRIPTION
RESET VALUE
R/W Divisor Latch Register (MS) (DLAB = 1)
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Baud Rate Divider (High Byte)
BITS
DESCRIPTIONS
[31:8]
Reserved
[7:0]
Baud Rate Divisor
(High Byte)
The high byte of the baud rate divider
This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows
Baud Rate = Crystal Clock / {16 * [Divisor + 2]}
HSUART Interrupt Identification Register (HSUART_IIR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_IIR
0x08
R
Interrupt Identification Register
0x8181_8181
- 284 -
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
FMES
5
RFTLS
4
DMS
BITS
[31:8]
IID
NIP
DESCRIPTIONS
Reserved
FIFO Mode Enable Status
[7]
FMES
This bit indicates whether the FIFO mode is enabled or not. Since the
FIFO mode is always enable, this bit always shows the logical 1 when
CPU is reading this register.
RX FIFO Threshold Level Status
[6:5]
RFTLS
These bits show the current setting of receiver FIFO threshold level
(RTHO). The meaning of RTHO is defined in the following FCR
description.
DMA Mode Select
[4]
DMS
[3:1]
IID
[0]
NIP
The DMA function is not implemented in this version. When reading IIR,
the DMS is always returned 0.
Interrupt Identification
The IID together with NIP indicates the current interrupt request from
UART.
No Interrupt Pending
There is no pending interrupt.
- 285 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Interrupt Control Functions
INTERRUPT RESET
CONTROL
IIR [3:0]
PRIORITY
INTERRUPT TYPE
INTERRUPT SOURCE
---1
--
None
0110
Highest
Receiver Line Status
(Irpt_RLS)
None
Overrun
error,
parity
error, framing error, or
break interrupt
0100
Second
Received Data
Available (Irpt_RDA)
Receiver FIFO threshold
level is reached
Receiver FIFO drops
below the threshold
level
Second
Receiver FIFO Timeout (Irpt_TOUT)
Receiver FIFO is nonempty and no activities
are occurred in the
receiver FIFO during the
TOR
defined
time
duration
Reading the RBR
0010
Third
Transmitter Holing
Register Empty
(Irpt_THRE)
Transmitter
register empty
Reading the IIR (if
source of interrupt is
Irpt_THRE)
or
writing into the THR
0000
Fourth
MODEM Status
(Irpt_MOS)
1100
holding
-Reading the LSR
The CTS bits are changing Reading the MSR
state .
(optional)
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550.
HSUART FIFO Control Register (HSUART_FCR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_FCR
0x08
W
FIFO Control Register
Undefined
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
DMS
TFR
RFR
FME
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
RFITL
- 286 -
W90N745CD/W90N745CDG
BITS
[31:8]
DESCRIPTIONS
Reserved
RX FIFO Interrupt (Irpt_RDA) Trigger Level
[7:4]
RFITL
RFITL
Irpt_RDA Trigger Level (Bytes)
0000
01
0001
04
0010
08
0011
14
0100
30
0101
46
0110
62
others
62
DMA Mode Select
[3]
DMS
The DMA function is not implemented in this version.
TX FIFO Reset
[2]
TFR
Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO.
The TX FIFO becomes empty (TX pointer is reset to 0) after such reset.
This bit is returned to 0 automatically after the reset pulse is generated.
RX FIFO Reset
[1]
RFR
Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO.
The RX FIFO becomes empty (RX pointer is reset to 0) after such reset.
This bit is returned to 0 automatically after the reset pulse is generated.
FIFO Mode Enable
[0]
FME
Because UART is always operating in the FIFO mode, writing this bit has
no effect while reading always gets logical one. This bit must be 1 when
other FCR bits are written to; otherwise, they will not be programmed.
- 287 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
HSUART Line Control Register (HSUART_LCR)
REGISTER
OFFSET
HSUART_LCR
0x0C
R/W
DESCRIPTION
RESET VALUE
R/W Line Control Register
BITS
0x0000_0000
DESCRIPTIONS
[31:8]
Reserved
[7]
DLAB
[6]
BCB
[5]
SPE
[4]
EPE
[3]
PBE
[2]
NSB
Divider Latch Access Bit
0 = It is used to access RBR, THR or IER.
1 = It is used to access Divisor Latch Registers {DLL, DLM}.
Break Control Bit
When this bit is set to logic 1, the serial data output (SOUT) is
forced to the Spacing State (logic 0). This bit acts only on
SOUT and has no effect on the transmitter logic.
Stick Parity Enable
0 = Disable stick parity
1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is
0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This
bit has effect only when bit 3 (parity bit enable) is set.
Even Parity Enable
0 = Odd number of logic 1’s are transmitted or checked in
the data word and parity bits.
1 = Even number of logic 1’s are transmitted or checked in
the data word and parity bits.
This bit has effect only when bit 3 (parity bit enable) is set.
Parity Bit Enable
0 = Parity bit is not generated (transmit data) or checked
(receive data) during transfer.
1 = Parity bit is generated or checked between the "last data
word bit" and "stop bit" of the serial data.
Number of “STOP bit”
0= One “ STOP bit” is generated in the transmitted data
1= One and a half “ STOP bit” is generated in the transmitted
data when 5-bit word length is selected;
Two “ STOP bit” is generated when 6-, 7- and 8-bit word length
is selected.
Word Length Select
WLS[1:0]
[1:0]
WLS
Character length
00
5 bits
01
10
6 bits
11
8 bits
- 288 -
7 bits
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
DLAB
BCB
SPE
EPE
PBE
NSB
WLS
HSUART Modem Control Register (HSUART_MCR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_MCR
0x10
R/W
Modem Control Register (Optional)
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RTS
Reserved
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
Reserved
LBME
BITS
[31:5]
4
Reserved
DESCRIPTIONS
Reserved
Loop-back Mode Enable
0 = Disable
[4]
LBME
1 = When the loop-back mode is enabled, the following signals are connected
internally:
SOUT connected to SIN and SOUT pin fixed at logic 1
RTS# connected to CTS# and RTS# pin fixed at logic 1
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Revision A1
W90N745CD/W90N745CDG
Continued.
BITS
[3:2]
DESCRIPTIONS
Reserved
Complement version of RTS# (Request-To-Send) signal
[1]
Writing 0x00 to MCR, RTS# bit are set to logic 1’s;
RTS#
Writing 0x0f to MCR, RTS# bit are reset to logic 0’s.
[0]
Reserved
-
HSUART Line Status Control Register (HSUART_LSR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_LSR
0x14
R
Line Status Register
0x6060_6060
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
3
2
1
0
ERR_RX
TE
THRE
BII
FEI
PEI
OEI
RFDR
BITS
[31:8]
DESCRIPTIONS
Reserved
RX FIFO Error
0 = RX FIFO works normally
[7]
ERR_RX
1 = There is at least one parity error (PE), framing error (FE), or break
indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the
LSR and if there are no subsequent errors in the RX FIFO.
Transmitter Empty
[6]
TE
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter
Shift Register (TSR) are not empty.
1 = Both THR and TSR are empty.
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W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
Transmitter Holding Register Empty
0 = THR is not empty.
[5]
THRE
1 = THR is empty.
THRE is set when the last data word of TX FIFO is transferred to
Transmitter Shift Register (TSR). The CPU resets this bit when the THR
(or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt
(Irpt_THRE) to the CPU when IER [1]=1.
Break Interrupt Indicator
[4]
BII
This bit is set to a logic 1 whenever the received data input is held in the
"spacing state" (logic 0) for longer than a full word transmission time (that
is, the total time of "start bit" + data bits + parity + stop bits) and is reset
whenever the CPU reads the contents of the LSR.
Framing Error Indicator
[3]
FEI
This bit is set to logic 1 whenever the received character does not have a
valid "stop bit" (that is, the stop bit following the last data bit or parity bit is
detected as a logic 0), and is reset whenever the CPU reads the contents
of the LSR.
Parity Error Indicator
[2]
PEI
This bit is set to logic 1 whenever the received character does not have a
valid "parity bit", and is reset whenever the CPU reads the contents of the
LSR.
Overrun Error Indicator
[1]
OEI
An overrun error will occur only after the RX FIFO is full and the next
character has been completely received in the shift register. The character
in the shift register is overwritten, but it is not transferred to the RX FIFO.
OE is indicated to the CPU as soon as it happens and is reset whenever
the CPU reads the contents of the LSR.
RX FIFO Data Ready
[0]
RFDR
0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not
suggested).
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Revision A1
W90N745CD/W90N745CDG
HSUART Modem Status Register (HSUART_MSR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_MSR
0x18
R
MODEM Status Register (Optional)
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
CTS#
Reserved
BITS
Reserved
DCTS
DESCRIPTIONS
[31:5]
Reserved
[4]
CTS#
[3:1]
Reserved
[0]
4
DCTS
Complement version of clear to send (CTS#) input
(This bit is selected by IP)
CTS# State Change
(This bit is selected by IP)
This bit is set whenever CTS# input has changed state, and it will be reset if
the CPU reads the MSR.
Whenever any of MSR [0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
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W90N745CD/W90N745CDG
HSUART Time Out Register (HSUART_TOR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
HSUART_TOR
0x1C
R/W
Time Out Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
TOIE
TOIC
BITS
DESCRIPTIONS
[31:8]
Reserved
[7]
TOIE
Time Out Interrupt Enable
The feature of receiver time out interrupt is enabled only when TOR [7] =
IER[0] = 1.
Time Out Interrupt Comparator
[6:0]
TOIC
The time out counter resets and starts counting (the counting clock = baud
rate) whenever the RX FIFO receives a new data word. Once the content
of time out counter (TOUT_CNT) is equal to that of time out interrupt
comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if
TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears
Irpt_TOUT.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.11 Timer/Watchdog Controller
7.11.1 General Timer Controller
The timer module includes two channels, TIMER0 and TIMER1, which allow you to easily implement a
counting scheme for use. The timer can perform functions like frequency measurement, event
counting, interval measurement, clock generation, delay timing, and so on. The timer possesses
features such as adjustable resolution, programmable counting period, and detailed information. The
timer can generate an interrupt signal upon timeout, or provide the current value of count during
operation.
The general TIMER Controller includes the following features
AMBA APB interface compatible
Two channels with a 8-bit presale counter/24-bit down counter and an interrupt request each
Independent clock source for each channel
Maximum uninterrupted time = (1 / 25 MHz) * (256) * (2^24), if TCLK = 25 MHz
7.11.2 Watchdog Timer
7.11.3 Timer Control Registers Map
R: read only, W: write only, R/W: both read and write
REGISTER
ADDRESS
R/W/C
DESCRIPTION
RESET VALUE
TCSR0
0xFFF8_1000
R/W
Timer Control and Status Register 0
0x0000_0005
TCSR1
0xFFF8_1004
R/W
Timer Control and Status Register 1
0x0000_0005
TICR0
0xFFF8_1008
R/W
Timer Initial Control Register 0
0x0000_0000
TICR1
0xFFF8_100C
R/W
Timer Initial Control Register 1
0x0000_0000
TDR0
0xFFF8_1010
R
Timer Data Register 0
0x0000_0000
TDR1
0xFFF8_1014
R
Timer Data Register 1
0x0000_0000
TISR
0xFFF8_1018
R/W
Timer Interrupt Status Register
0x0000_0000
WTCR
0xFFF8_101C
R/W
Watchdog Timer Control Register
0x0000_0400
Timer Control Register 0/1 (TCSR 0/1)
REGISTER
ADDRESS
R/W
DESCRIPTION
TCSR0
0xFFF8_1000
R/W
Timer Control and Status Register 0
0x0000_0005
TCSR1
0xFFF8_1004
R/W
Timer Control and Status Register 1
0x0000_0005
- 294 -
RESET VALUE
W90N745CD/W90N745CDG
31
30
29
nDBGACK_EN
CEN
IE
23
22
21
28
27
26
25
24
CRST
CACT
Reserved
19
18
17
16
11
10
9
8
3
2
1
0
MODE[1:0]
20
Reserved
15
14
13
12
Reserved
7
6
5
4
PRESCALE[7:0]
BITS
DESCRIPTIONS
ICE debug mode acknowledge enable
[31]
nDBGACK_EN
0 = When DBGACK is high, the TIMER counter will be held
1 = No matter DBGACK is high or not, the TIMER counter will not
be held
Counter Enable
[30]
CEN
0 = Stops/Suspends counting
1 = Starts counting
Interrupt Enable
0 = Disable TIMER Interrupt.
[29]
IE
1 = Enable TIMER Interrupt. If timer interrupt is enabled, the timer
asserts its interrupt signal when the associated counter
decrements to zero.
Timer Operating Mode
MODE
[28:27]
MODE
Timer Operating Mode
00
The timer is operating in the one-shot mode. The
associated interrupt signal is generated once (if IE is
enabled) and CEN is automatically cleared then.
01
The timer is operating in the periodic mode. The
associated interrupt signal is generated periodically
(if IE is enabled).
10
The timer is operating in the toggle mode. The
interrupt signal is generated periodically (if IE is
enabled). And the associated signal (tout) is
changing back and forth with 50% duty cycle.
11
Reserved.
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Revision A1
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
Counter Reset
Set this bit will reset the TIMER counter, and also force CEN to 0.
[26]
CRST
0 = No effect.
1 = Reset Timer’s prescale counter, internal 24-bit counter and
CEN.
Timer is in Active
[25]
CACT
This bit indicates the counter status of timer.
0 = Timer is not active.
1 = Timer is in active.
[24:8]
Reserved
Reserved
Prescale
[7:0]
PRESCALE
Clock input is divided by PRESCALE+1 before it is fed to the
counter. If PRESCALE=0, then there is no scaling.
Timer Initial Count Register 0/1 (TICR0/1)
REGISTER
ADDRESS
R/W
TICR0
0xFFF8_1008
R/W
Timer Initial Control Register 0
0x0000_0000
TICR1
0xFFF8_100C
R/W
Timer Initial Control Register 1
0x0000_0000
31
30
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
TIC [23:16]
15
14
13
12
TIC [15:8]
7
6
5
4
TIC [7:0]
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W90N745CD/W90N745CDG
BITS
[31:24]
[23:0]
DESCRIPTIONS
Reserved
TIC
Reserved
Timer Initial Count
This is a 24-bit value representing the initial count. Timer will reload
this value whenever the counter is decremented to zero.
NOTE1: Never write 0x0 in TIC, or the core will run into unknown
state.
NOTE2: No matter CEN is 0 or 1, whenever software write a new
value into this register, TIMER will restart counting using this new
value and abort previous count.
Timer Data Register 0/1 (TDR0/1)
REGISTER
ADDRESS
R/W
TDR0
0xFFF8_10010
R
Timer Data Register 0
0x0000_0000
TDR1
0xFFF8_10014
R
Timer Data Register 1
0x0000_0000
31
30
DESCRIPTION
29
28
RESET VALUE
27
26
25
24
19
18
17
16
10
9
8
2
1
0
Reserved
23
22
21
20
TDR [23:16]
15
14
13
12
11
TDR [15:8]
7
6
5
4
3
TDR [7:0]
BITS
[31:24]
[23:0]
DESCRIPTIONS
Reserved
TDR
Reserved
Timer Data Register
The current count is registered in this 24-bit value.
NOTE: Software can read a correct current value on this register only
when CEN = 0, or the value represents here could not be a correct
one.
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Revision A1
W90N745CD/W90N745CDG
- 298 -
W90N745CD/W90N745CDG
Timer Interrupt Status Register (TISR)
REGISTER
TISR
31
ADDRESS
R/W
0xFFF8_1018
R/W
30
DESCRIPTION
RESET VALUE
Timer Interrupt Status Register
29
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
TIF1
TIF0
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
5
4
3
Reserved
BITS
DESCRIPTIONS
Timer Interrupt Flag 1
This bit indicates the interrupt status of Timer channel 1.
[1]
TIF1
0 = It indicates that the Timer 1 dose not countdown to zero yet.
1 = It indicates that the counter of Timer 1 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Timer Interrupt Flag 0
This bit indicates the interrupt status of Timer channel 0.
[0]
TIF0
0 = It indicates that the Timer 0 dose not countdown to zero yet.
1 = It indicates that the counter of Timer 0 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Watchdog Timer Control Register (WTCR)
REGISTER
ADDRESS
R/W
WTCR
0xFFF8_101C
R/W
DESCRIPTION
Watchdog Timer Control Register
- 299 -
RESET VALUE
0x0000_0400
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
23
22
21
20
19
Reserved
15
14
13
12
11
Reserved
7
6
WTE
WTIE
5
4
WTIS
BITS
[31:11]
WTCLK nDBGACK_EN WTTME
3
2
1
0
WTIF
WTRF
WTRE
WTR
DESCRIPTIONS
Reserved
Reserved
Watchdog Timer Clock
This bit is used for deciding whether the Watchdog timer clock input is
divided by 256 or not. Clock source of Watchdog timer is Crystal
input.
[10]
WTCLK
0 = Using original clock input
1 = The clock input will be divided by 256
NOTE: When WTTME = 1, set this bit has no effect on WDT clock
(using original clock input).
ICE debug mode acknowledge enable
[9]
nDBGACK_EN
0 = When DBGACK is high, the Watchdog timer counter will be
held
1 = No matter DBGACK is high or not, the Watchdog timer counter
will not be held
Watchdog Timer Test Mode Enable
[8]
WTTME
For reasons of efficiency, the 26-bit counter within the Watchdog
timer is considered as two independent 13-bit counters in the test
mode. They are operated concurrently and separately during the test.
This approach can save a lot of time spent in the test. When the 13bit counter overflows, a Watchdog timer interrupt is generated.
0 = Put the Watchdog timer in normal operating mode
1 = Put the Watchdog timer in test mode
Watchdog Timer Enable
[7]
WTE
0 = Disable the Watchdog timer (This action will reset the internal
counter)
1 = Enable the Watchdog timer
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W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
Watchdog Timer Interrupt Enable
[6]
WTIE
0 = Disable the Watchdog timer interrupt
1 = Enable the Watchdog timer interrupt
Watchdog Timer Interval Select
These two bits select the interval for the Watchdog timer. No matter
which interval is chosen, the reset timeout is always occurred 512
WDT clock cycles later than the interrupt timeout.
[5:4]
WTIS
WTIS
Interrupt
Timeout
Reset Timeout
Real Time Interval
(CLK=15MHz/256)
00
214 clocks
214 + 1024
clocks
0.28 sec.
01
216 clocks
216 + 1024
clocks
1.12 sec.
10
218 clocks
218 + 1024
clocks
4.47 sec.
11
220 clocks
220 + 1024
clocks
17.9 sec.
Watchdog Timer Interrupt Flag
[3]
WTIF
If the Watchdog timer interrupt is enabled, then the hardware will set
this bit to indicate that the Watchdog timer interrupt has occurred. If
the Watchdog timer interrupt is not enabled, then this bit indicates that
a timeout period has elapsed.
0 = Watchdog timer interrupt does not occur
1 = Watchdog timer interrupt occurs
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Watchdog Timer Reset Flag
[2]
WTRF
When the Watchdog timer initiates a reset, the hardware will set this
bit. This flag can be read by software to determine the source of
reset. Software is responsible to clear it up manually. If WTRE is
disabled, then the Watchdog timer has no effect on this bit.
0 = Watchdog timer reset does not occur
1 = Watchdog timer reset occurs
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
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Revision A1
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
Watchdog Timer Reset Enable
[1]
WTRE
Setting this bit will enable the Watchdog timer reset function.
0 = Disable Watchdog timer reset function
1 = Enable Watchdog timer reset function
Watchdog Timer Reset
[0]
WTR
This bit brings the Watchdog timer into a known state. It helps reset
the Watchdog timer before a timeout situation occurring. Failing to set
WTR before timeout will initiates an interrupt if WTIE is set. If the
WTRE bit is set, Watchdog timer reset will be occurred 512 WDT
clock cycles after timeout. This bit is self-clearing.
0 = No operation
1 = Reset the contents of the Watchdog timer
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W90N745CD/W90N745CDG
7.12 Advanced Interrupt Controller
An interrupt temporarily changes the sequence of program execution to react to a particular event
such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC
Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt
(FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception
is occurred when the nIRQ input is asserted. Similarly, the FIQ exception is occurred when the nFIQ
input is asserted. The FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible
to ignore the FIQ and the IRQ by setting the F and I bits in the current program status register
(CPSR).
The W90N745 incorporates the advanced interrupt controller (AIC) that is capable of dealing with
the interrupt requests from a total of 32 different sources. Currently, 31 interrupt sources are defined.
Each interrupt source is uniquely assigned to an interrupt channel. For example, the watchdog timer
interrupt is assigned to channel 1. The AIC implements a proprietary eight-level priority scheme that
differentiates the available 31 interrupt sources into eight priority levels. Interrupt sources within the
priority level 0 have the highest priority and the priority level 7 has the lowest. To work this scheme
properly, you must specify a certain priority level to each interrupt source during power-on
initialization; otherwise, the system shall behave unexpectedly. Within each priority level, interrupt
source that is positioned in a lower channel has a higher priority. Interrupt source that is active,
enabled, and positioned in the lowest channel within the priority level 0 is promoted to the FIQ.
Interrupt sources within the priority levels other than 0 can petition for the IRQ. The IRQ can be
preempted by the occurrence of the FIQ. Interrupt nesting is performed automatically by the AIC.
Though interrupt sources originated from the W90N745 itself are intrinsically high-level sensitive, the
AIC can be configured as either low-level sensitive, high-level sensitive, negative-edge triggered, or
positive-edge triggered to each interrupt source. When the W90N745 is put in the test mode, all
interrupt sources must be configured as positive-edge triggered.
The advanced interrupt controller includes the following features:
AMBA APB bus interface
External interrupts can be programmed as either edge-triggered or level-sensitive
External interrupts can be programmed as either low-active or high-active
Has flags to reflect the status of each interrupt source
Individual mask for each interrupt source
Proprietary 8-level interrupt scheme to ease the burden from the interrupt
Priority methodology is adopted to allow for interrupt daisy-chaining
Automatically masking out the lower priority interrupt during interrupt nesting
Automatically clearing the interrupt flag when the external interrupt source is programmed to be edgetriggered
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.12.1 Interrupt Sources
Table 7.12.1 W90N745 Interrupt Sources
PRIORITY
1 (Highest)
NAME
MODE
SOURCE
WDT_INT
Positive Level
Watch Dog Timer Interrupt
2
nIRQ0
Programmable
External Interrupt 0
3
nIRQ1
Programmable
External Interrupt 1
4
Reserved
-
-
5
Reserved
-
-
6
AC97_INT
Positive Level
AC97 Interrupt
7
Reserved
-
-
8
Reserved
-
-
9
UART_INT0
Positive Level
UART Interrupt0
10
UART_INT1
Positive Level
UART Interrupt1
11
UART_INT2
Positive Level
UART Interrupt2
12
UART_INT3
Positive Level
UART Interrupt3
13
T_INT0
Positive Level
Timer Interrupt 0
14
T_INT1
Positive Level
Timer Interrupt 1
15
USBH_INT0
Positive Level
USB Host Interrupt 0
16
USBH_INT1
Positive Level
USB Host Interrupt 1
17
EMCTX_INT
Positive Level
EMC TX Interrupt
18
EMCRX_INT
Positive Level
EMC RX Interrupt
19
GDMA_INT0
Positive Level
GDMA Channel Interrupt 0
20
GDMA_INT1
Positive Level
GDMA Channel Interrupt 1
21
Reserved
-
-
22
USBD_INT
Positive Level
USB Device Interrupt
23
Reserved
-
-
24
Reserved
-
-
2
25
I C_INT0
Positive Level
I2C Interrupt0
26
I2C_INT1
Positive Level
I2C Interrupt1
27
SSP_INT
Positive Level
SSP Interrupt
28
PWM _INT
Positive Level
PWM Timer interrupt
29
KPI_INT
Positive Level
Keypad Interrupt
30
PS2_INT
Positive Level
PS2 Interrupt
31
nIRQ2/3_INT
Positive Level
GPIO0 & GPIO30 Interrupt
- 304 -
W90N745CD/W90N745CDG
AIC Functional Description
Hardware Interrupt Vectoring
The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used,
priority determination must be carried out by software. When the Interrupt Priority Encoding
Register (AIC_IPER) is read, it will return an integer representing the channel that is active and
having the highest priority. This integer is equivalent to multiplied by 4 (shifted left two bits to
word-align it) such that it may be used directly to index into a branch table to select the
appropriate interrupt service routine vector.
Priority Controller
An 8-level priority encoder controls the nIRQ line. Each interrupt source belongs to priority group
between of 0 to 7. Group 0 has the highest priority and group 7 the lowest. When more than one
unmasked interrupt channels are active at a time, the interrupt with the highest priority is serviced
first. If all active interrupts have equal priority, the interrupt with the lowest interrupt source number
is serviced first.
The current priority level is defined as the priority level of the interrupt with the highest priority at
the time the register AIC_IPER is read. In the case when a higher priority unmasked interrupt
occurs while an interrupt already exits, there are two possible outcomes depending on whether the
AIC_IPER has been read.
If the processor has already read the AIC_IPER and caused the nIRQ line to be deasserted, then the nIRQ line is reasserted. When the processor has enabled nested
interrupts and reads the AIC_IPER again, it reads the new, higher priority interrupt
vector. At the same time, the current priority level is updated to the higher priority.
If the AIC_IPER has not been read after the nIRQ line has been asserted, then the
processor will read the new higher priority interrupt vector in the AIC_IPER register
and the current priority level is updated.
When the End of Service Command Register (AIC_EOSCR) is written, the current interrupt
level is updated with the last stored interrupt level from the stack (if any). Therefore, at the end
of a higher priority interrupt, the AIC returns to the previous state corresponding to the
preceding lower priority interrupt which had been interrupted.
Interrupt Handling
When the IRQ line is asserted, the interrupt handler must read the AIC_IPER as soon as possible.
This can de-assert the nIRQ request to the processor and clears the interrupt if it is programmed
to be edge triggered. This allows the AIC to assert the nIRQ line again when a higher priority
unmasked interrupt occurs.
The AIC_EOSCR (End of Service Command Register) must be written at the end of the interrupt
service routine. This permits pending interrupts to be serviced.
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Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Interrupt Masking
Each interrupt source, including FIQ, can be enabled or disabled individually by using the
command registers AIC_MECR and AIC_MDCR. The status of interrupt mask can be read in the
read only register AIC_IMR. A disabled interrupt doesn’t affect the servicing of other interrupts.
Interrupt Clearing and Setting
All interrupt sources (including FIQ) can be individually set or clear by respectively writing to the
registers AIC_SSCR and AIC_SCCR when they are programmed to be edge triggered. This
feature of the AIC is useful in auto-testing or software debugging.
Fake Interrupt
When the AIC asserts the nIRQ line, the processor enters interrupt mode and the interrupt handler
reads the AIC_IPER, it may happen that AIC de-asserts the nIRQ line after the processor has
taken into account the nIRQ assertion and before the read of the AIC_IPER.
This behavior is called a fake interrupt.
The AIC is able to detect these fake interrupts and returns all zero when AIC_IPER is read. The
same mechanism of fake interrupt occurs if the processor reads the AIC_IPER (application
software or ICE) when there is no interrupt pending. The current priority level is not updated in this
situation. Hence, the AIC_EOSCR shouldn’t be written.
ICE/Debug Mode
This mode allows reading of the AIC_IPER without performing the associated automatic
operations. This is necessary when working with a debug system. When an ICE or debug monitor
reads the AIC user interface, the AIC_IPER can be read. This has the following consequences in
normal mode:
If there is no enabled pending interrupt, the fake vector will be returned.
If an enabled interrupt with a higher priority than the current one is pending, it will be
stacked.
In the second case, an End-of-Service command would be necessary to restore the state of the
AIC. This operation is generally not performed by the debug system. Therefore, the debug system
would become strongly intrusive, and could cause the application to enter an undesired state.
This can be avoided by using ICE/Debug Mode. When this mode is enabled. The AIC performs
interrupt stacking only when a write access is performed on the AIC_IPER. Hence, the interrupt
service routine must write to the AIC_IPER (any value) just after reading it. When AIC_IPER is
written, the new status of AIC, including the value of interrupt source number register (AIC_ISNR),
is updated with the value that is kept at previous reading of AIC_IPER The debug system must not
write to the AIC_IPER as this would cause undesirable effects.
The following table shows the main steps of an interrupt and the order in which they are performed
according to the mode:
- 306 -
W90N745CD/W90N745CDG
ACTION
NORMAL MODE
Calculate active interrupt
ICE/DEBUG MODE
Read AIC_IPER
Read AIC_IPER
Determine and return the vector of the active interrupt Read AIC_IPER
Read AIC_IPER
Push on internal stack the current priority level
Read AIC_IPER
Write AIC_IPER
Acknowledge the interrupt (Note 1)
Read AIC_IPER
Write AIC_IPER
No effect (Note 2)
Read AIC_IPER
Notes:
nIRQ de-assertion and automatic interrupt clearing if the source is programmed as
level sensitive.
Note that software which has been written and debugged using this mode will run
correctly in normal mode without modification. However, in normal mode writing to
AIC_IPER has no effect and can be removed to optimize the code
7.12.2 AIC Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
AIC_SCR1
0xFFF8_2004 R/W Source Control Register 1
0x0000_0047
AIC_SCR2
0xFFF8_2008 R/W Source Control Register 2
0x0000_0047
AIC_SCR3
0xFFF8_200C R/W Source Control Register 3
0x0000_0047
AIC_SCR4
0xFFF8_2010 R/W Source Control Register 4
0x0000_0047
AIC_SCR5
0xFFF8_2014 R/W Source Control Register 5
0x0000_0047
AIC_SCR6
0xFFF8_2018 R/W Source Control Register 6
0x0000_0047
AIC_SCR7
0xFFF8_201C R/W Source Control Register 7
0x0000_0047
AIC_SCR8
0xFFF8_2020 R/W Source Control Register 8
0x0000_0047
AIC_SCR9
0xFFF8_2024 R/W Source Control Register 9
0x0000_0047
AIC_SCR10
0xFFF8_2028 R/W Source Control Register 10
0x0000_0047
AIC_SCR11
0xFFF8_202C R/W Source Control Register 11
0x0000_0047
AIC_SCR12
0xFFF8_2030 R/W Source Control Register 12
0x0000_0047
AIC_SCR13
0xFFF8_2034 R/W Source Control Register 13
0x0000_0047
AIC_SCR14
0xFFF8_2038 R/W Source Control Register 14
0x0000_0047
AIC_SCR15
0xFFF8_203C R/W Source Control Register 15
0x0000_0047
- 307 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
AIC Registers Map, continued
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
AIC_SCR16
0xFFF8_2040 R/W Source Control Register 16
0x0000_0047
AIC_SCR17
0xFFF8_2044 R/W Source Control Register 17
0x0000_0047
AIC_SCR18
0xFFF8_2048 R/W Source Control Register 18
0x0000_0047
AIC_SCR19
0xFFF8_204C R/W Source Control Register 19
0x0000_0047
AIC_SCR20
0xFFF8_2050 R/W Source Control Register 20
0x0000_0047
AIC_SCR21
0xFFF8_2054 R/W Source Control Register 21
0x0000_0047
AIC_SCR22
0xFFF8_2058 R/W Source Control Register 22
0x0000_0047
AIC_SCR23
0xFFF8_205C R/W Source Control Register 23
0x0000_0047
AIC_SCR24
0xFFF8_2060 R/W Source Control Register 24
0x0000_0047
AIC_SCR25
0xFFF8_2064 R/W Source Control Register 25
0x0000_0047
AIC_SCR26
0xFFF8_2068 R/W Source Control Register 26
0x0000_0047
AIC_SCR27
0xFFF8_206C R/W Source Control Register 27
0x0000_0047
AIC_SCR28
0xFFF8_2070 R/W Source Control Register 28
0x0000_0047
AIC_SCR29
0xFFF8_2074 R/W Source Control Register 29
0x0000_0047
AIC_SCR30
0xFFF8_2078 R/W Source Control Register 30
0x0000_0047
AIC_SCR31
0xFFF8_207C R/W Source Control Register 31
0x0000_0047
AIC_IRSR
0xFFF8_2100
R
Interrupt Raw Status Register
0x0000_0000
AIC_IASR
0xFFF8_2104
R
Interrupt Active Status Register
0x0000_0000
AIC_ISR
0xFFF8_2108
R
Interrupt Status Register
0x0000_0000
AIC_IPER
0xFFF8_210C
R
Interrupt Priority Encoding Register
0x0000_0000
AIC_ISNR
0xFFF8_2110
R
Interrupt Source Number Register
0x0000_0000
AIC_IMR
0xFFF8_2114
R
Interrupt Mask Register
0x0000_0000
AIC_OISR
0xFFF8_2118
R
Output Interrupt Status Register
0x0000_0000
AIC_MECR
0xFFF8_2120
W
Mask Enable Command Register
Undefined
AIC_MDCR
0xFFF8_2124
W
Mask Disable Command Register
Undefined
AIC_SSCR
0xFFF8_2128
W
Source Set Command Register
Undefined
AIC_SCCR
0xFFF8_212C
W
Source Clear Command Register
Undefined
AIC_EOSCR 0xFFF8_2130
W
End of Service Command Register
Undefined
0xFFF8_2200
W
ICE/Debug mode Register
Undefined
AIC_TEST
- 308 -
W90N745CD/W90N745CDG
AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR31)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
AIC_SCR1
0xFFF8_2004 R/W Source Control Register 1
0x0000_0047
AIC_SCR2
0xFFF8_2008 R/W Source Control Register 2
0x0000_0047
yyy
yyy
yyy
yyy
yyy
AIC_SCR28
0xFFF8_2070 R/W Source Control Register 28
0x0000_0047
AIC_SCR29
0xFFF8_2074 R/W Source Control Register 29
0x0000_0047
AIC_SCR30
0xFFF8_2078 R/W Source Control Register 30
0x0000_0047
AIC_SCR31
0xFFF8_207C R/W Source Control Register 31
0x0000_0047
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
SRCTYPE
BITS
[31:8]
PRIORITY
DESCRIPTIONS
Reserved
Reserved
Interrupt Source Type
Whether an interrupt source is considered active or not by the AIC is
subject to the settings of this field. Interrupt sources other than nIRQ0,
nIRQ1 should be configured as level sensitive during normal operation
unless in the testing situation.
[7:6]
SRCTYPE
SRCTYPE [7:6]
Interrupt Source Type
0
0
Low-level Sensitive
0
1
High-level Sensitive
1
0
Negative-edge Triggered
1
1
Positive-edge Triggered
- 309 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued
BITS
[5:3]
DESCRIPTIONS
Reserved
Reserved
Priority Level
[2:0]
Every interrupt source must be assigned a priority level during
initiation. Among them, priority level 0 has the highest priority and
priority level 7 the lowest. Interrupt sources with priority level 0 are
promoted to FIQ. Interrupt sources with priority level other than 0
belong to IRQ. For interrupt sources of the same priority level that
located in the lower channel number has higher priority.
PRIORITY
AIC Interrupt Raw Status Register (AIC_IRSR)
REGISTER
ADDRESS
R/W
AIC_IRSR
0xFFF8_2100
R
DESCRIPTION
RESET VALUE
0x0000_0000
Interrupt Raw Status Register
31
30
29
28
27
26
25
24
IRS31
IRS30
IRS29
IRS28
IRS27
IRS26
IRS25
IRS24
23
22
21
20
19
18
17
16
IRS23
IRS22
IRS21
IRS20
IRS19
IRS18
IRS17
IRS16
15
14
13
12
11
10
9
8
IRS15
IRS14
IRS13
IRS12
IRS11
IRS10
IRS9
IRS8
7
6
5
4
3
2
1
0
IRS7
IRS6
IRS5
IRS4
IRS3
IRS2
IRS1
RESERVED
BITS
DESCRIPTIONS
This register records the intrinsic state within each interrupt channel.
[31:1]
IRSx
IRSx: Interrupt Status
Indicate the intrinsic status of the corresponding interrupt source
0 = Interrupt channel is in the voltage level 0
1 = Interrupt channel is in the voltage level 1
[0]
Reserved
Reserved
- 310 -
W90N745CD/W90N745CDG
AIC Interrupt Active Status Register (AIC_IASR)
REGISTER
ADDRESS
R/W
AIC_IASR
0xFFF8_2104
R
DESCRIPTION
RESET VALUE
0x0000_0000
Interrupt Active Status Register
31
30
29
28
27
26
25
24
IAS31
IAS30
IAS29
IAS28
IAS27
IAS26
IAS25
IAS24
23
22
21
20
19
18
17
16
IAS23
IAS22
IAS21
IAS20
IAS19
IAS18
IAS17
IAS16
15
14
13
12
11
10
9
8
IAS15
IAS14
IAS13
IAS12
IAS11
IAS10
IAS9
IAS8
7
6
5
4
3
2
1
0
IAS7
IAS6
IAS5
IAS4
IAS3
IAS2
IAS1
RESERVED
BITS
DESCRIPTIONS
This register indicates the status of each interrupt channel in
consideration of the interrupt source type as defined in the
corresponding Source Control Register, but regardless of its mask
setting.
[31:1]
IASx
IASx: Interrupt Active Status
Indicate the status of the corresponding interrupt source
0 = Corresponding interrupt channel is inactive
1 = Corresponding interrupt channel is active
[0]
Reserved
Reserved
AIC Interrupt Status Register (AIC_ISR)
REGISTER
ADDRESS
R/W
AIC_ISR
0xFFF8_2108
R
DESCRIPTION
Interrupt Status Register
- 311 -
RESET VALUE
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
IS31
IS30
IS29
IS28
IS27
IS26
IS25
IS24
23
22
21
20
19
18
17
16
IS23
IS22
IS21
IS20
IS19
IS18
IS17
IS16
15
14
13
12
11
10
9
8
IS15
IS14
IS13
IS12
IS11
IS10
IS9
IS8
7
6
5
4
3
2
1
0
IS7
IS6
IS5
IS4
IS3
IS2
IS1
RESERVED
BITS
DESCRIPTIONS
This register identifies those interrupt channels whose are both active and
enabled.
ISx: Interrupt Status
Indicates the status of corresponding interrupt channel
0 = Two possibilities:
(1) The corresponding interrupt channel is inactive no matter
whether it is enabled or disabled;
(2) It is active but not enabled
1 = Corresponding interrupt channel is both active and enabled (can assert an
interrupt)
[31:1]
ISx
[0]
Reserved
Reserved
AIC IRQ Priority Encoding Register (AIC_IPER)
REGISTER
ADDRESS
R/W
AIC_IPER
0xFFF8_210C
R
DESCRIPTION
RESET VALUE
0x0000_0000
Interrupt Priority Encoding Register
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
VECTOR
- 312 -
W90N745CD/W90N745CDG
BITS
[6:2]
DESCRIPTIONS
Vector
When the AIC generates the interrupt, VECTOR represents the
interrupt channel number that is active, enabled, and has the highest
priority. If the representing interrupt channel possesses a priority level
0, then the interrupt asserted is FIQ; otherwise, it is IRQ. The value of
VECTOR is copied to the register AIC_ISNR thereafter by the AIC.
This register was restored a value 0 after it was read by the interrupt
handler. This register can help indexing into a branch table to quickly
jump to the corresponding interrupt service routine.
VECTOR [6:2]: Interrupt Vector
0 = no interrupt occurs
1 ~ 31 = representing the interrupt channel that is active, enabled, and
having the highest priority
[0]
Reserved
Reserved
AIC Interrupt Source Number Register (AIC_ISNR)
REGISTER
ADDRESS
R/W
AIC_ISNR
0xFFF8_2110
R
DESCRIPTION
RESET VALUE
0x0000_0000
Interrupt Source Number Register
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
BITS
[31:5]
IRQID
DESCRIPTIONS
Reserved
Reserved
The purpose of this register is to record the interrupt channel number
that is active, enabled, and has the highest priority.
[4:0]
IRQID
IRQID [4:0]: IRQ Identification
Stands for the interrupt channel number
- 313 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
- 314 -
W90N745CD/W90N745CDG
AIC Interrupt Mask Register (AIC_IMR)
REGISTER
ADDRESS
R/W
AIC_IMR
0xFFF8_2114
R
DESCRIPTION
RESET VALUE
0x0000_0000
Interrupt Mask Register
31
30
29
28
27
26
25
24
IM31
IM30
IM29
IM28
IM27
IM26
IM25
IM24
23
22
21
20
19
18
17
16
IM23
IM22
IM21
IM20
IM19
IM18
IM17
IM16
15
14
13
12
11
10
9
8
IM15
IM14
IM13
IM12
IM11
IM10
IM9
IM8
7
6
5
4
3
2
1
0
IM7
IM6
IM5
IM4
IM3
IM2
IM1
RESERVED
BITS
DESCRIPTIONS
[31:1]
IM x
[0]
Reserved
IMx: Interrupt Mask
This bit determines whether the corresponding interrupt channel is
enabled or disabled. Every interrupt channel can be active no matter
whether it is enabled or disabled. If an interrupt channel is enabled, it
does not definitely mean it is active. Every interrupt channel can be
authorized by the AIC only when it is both active and enabled.
0 = Corresponding interrupt channel is disabled
1 = Corresponding interrupt channel is enabled
Reserved
AIC Output Interrupt Status Register (AIC_OISR)
REGISTER
ADDRESS
R/W
AIC_OISR
0xFFF8_2118
R
31
30
29
DESCRIPTION
RESET VALUE
0x0000_0000
Output Interrupt Status Register
28
27
26
25
24
18
17
16
10
9
8
2
1
0
IRQ
FIQ
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
- 315 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted
interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred.
BITS
[31:2]
DESCRIPTIONS
Reserved
Reserved
IRQ [1]: Interrupt Request
[1]
IRQ
0 = nIRQ line is inactive.
1 = nIRQ line is active.
FIQ [0]: Fast Interrupt Request
[0]
FIQ
0 = nFIQ line is inactive.
1 = nFIQ line is active
AIC Mask Enable Command Register (AIC_MECR)
REGISTER
ADDRESS
R/W
AIC_MECR
0xFFF8_2120
W
DESCRIPTION
RESET VALUE
Mask Enable Command Register
Undefined
31
30
29
28
27
26
25
24
MEC31
MEC30
MEC29
MEC28
MEC27
MEC26
MEC25
MEC24
23
22
21
20
19
18
17
16
MEC23
MEC22
MEC21
MEC20
MEC19
MEC18
MEC17
MEC16
15
14
13
12
11
10
9
8
MEC15
MEC14
MEC13
MEC12
MEC11
MEC10
MEC9
MEC8
7
6
5
4
3
2
1
0
MEC7
MEC6
MEC5
MEC4
MEC3
MEC2
MEC1
RESERVED
BITS
DESCRIPTIONS
MEC x: Mask Enable Command
[31:1]
MEC x
0 = No effect
1 = Enables the corresponding interrupt channel
[0]
Reserved
Reserved
- 316 -
W90N745CD/W90N745CDG
AIC Mask Disable Command Register (AIC_MDCR)
REGISTER
ADDRESS
R/W
AIC_MDCR
0xFFF8_2124
W
DESCRIPTION
RESET VALUE
Mask Disable Command Register
Undefined
31
30
29
28
27
26
25
24
MDC31
MDC30
MDC29
MDC28
MDC27
MDC26
MDC25
MDC24
23
22
21
20
19
18
17
16
MDC23
MDC22
MDC21
MDC20
MDC19
MDC18
MDC17
MDC16
15
14
13
12
11
10
9
8
MDC15
MDC14
MDC13
MDC12
MDC11
MDC10
MDC9
MDC8
7
6
5
4
3
2
1
0
MDC7
MDC6
MDC5
MDC4
MDC3
MDC2
MDC1
RESERVED
BITS
DESCRIPTIONS
MDC x: Mask Disable Command
[31:1]
MDCx
0 = No effect
1 = Disables the corresponding interrupt channel
[0]
Reserved
Reserved
AIC Source Set Command Register (AIC_SSCR)
REGISTER
ADDRESS
R/W
AIC_SSCR
0xFFF8_2128
W
DESCRIPTION
RESET VALUE
Source Set Command Register
Undefined
31
30
29
28
27
26
25
24
SSC31
SSC30
SSC29
SSC28
SSC27
SSC26
SSC25
SSC24
23
22
21
20
19
18
17
16
SSC23
SSC22
SSC21
SSC20
SSC19
SSC18
SSC17
SSC16
15
14
13
12
11
10
9
8
SSC15
SSC14
SSC13
SSC12
SSC11
SSC10
SSC9
SSC8
7
6
5
4
3
2
1
0
SSC7
SSC6
SSC5
SSC4
SSC3
SSC2
SSC1
RESERVED
- 317 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
[31:1]
DESCRIPTIONS
When the W90N745 is under debugging or verification, software can
activate any interrupt channel by setting the corresponding bit in this
register. This feature is useful in hardware verification or software
debugging.
SSCx
SSCx: Source Set Command
0 = No effect.
1 = Activates the corresponding interrupt channel
[0]
Reserved
Reserved
AIC Source Clear Command Register (AIC_SCCR)
REGISTER
ADDRESS
R/W
AIC_SCCR
0xFFF8_212C
W
DESCRIPTION
RESET VALUE
Source Clear Command Register
Undefined
31
30
29
28
27
26
25
24
SCC31
SCC30
SCC29
SCC28
SCC27
SCC26
SCC25
SCC24
23
22
21
20
19
18
17
16
SCC23
SCC22
SCC21
SCC20
SCC19
SCC18
SCC17
SCC16
15
14
13
12
11
10
9
8
SCC15
SCC14
SCC13
SCC12
SCC11
SCC10
SCC9
SCC8
7
6
5
4
3
2
1
0
SCC7
SCC6
SCC5
SCC4
SCC3
SCC2
SCC1
RESERVED
BITS
[31:1]
DESCRIPTIONS
SCCx
When the W90N745 is under debugging or verification, software can
deactivate any interrupt channel by setting the corresponding bit in this
register. This feature is useful in hardware verification or software
debugging.
SCCx: Source Clear Command
0 = No effect.
1 = Deactivates the corresponding interrupt channels
[0]
Reserved
Reserved
- 318 -
W90N745CD/W90N745CDG
AIC End of Service Command Register (AIC_EOSCR)
REGISTER
ADDRESS
R/W
W
AIC_EOSCR 0xFFF8_2130
DESCRIPTION
RESET VALUE
End of Service Command Register
Undefined
31
30
29
28
27
26
25
24
---
---
---
---
---
---
---
---
23
22
21
20
19
18
17
16
---
---
---
---
---
---
---
---
15
14
13
12
11
10
9
8
---
---
---
---
---
---
---
---
7
6
5
4
3
2
1
0
---
---
---
---
---
---
---
---
BITS
[31:0]
DESCRIPTIONS
EOSCR
This register is used by the interrupt service routine to indicate that it is
completely served. Thus, the interrupt handler can write any value to
this register to indicate the end of its interrupt service.
AIC ICE/Debug Register (AIC_TEST)
REGISTER
ADDRESS
R/W
AIC_TEST
0xFFF8_2200
W
31
30
29
DESCRIPTION
RESET VALUE
Undefined
ICE/Debug mode Register
28
27
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
- 319 -
TEST
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
[31:1]
[0]
DESCRIPTIONS
Reserved
TEST
Reserved
This register indicates whether AIC_IPER will be cleared or not after
been read. If bit0 of AIC_TEST has been set, ICE or debug monitor can
read AIC_IPER for verification and the AIC_IPER will not be cleared
automatically. Write access to the AIC_IPER will perform the interrupt
stacking in this mode.
TEST: ICE/Debug mode
0 = normal mode.
1 = ICE/Debug mode.
- 320 -
W90N745CD/W90N745CDG
7.13 General-Purpose Input/Output
The General-Purpose Input/Output (GPIO) module possesses 31 pins and serves multiple function
purposes. Each port can be configured by software to meet various system configurations and design
requirements. Software must configure each pin before starting the main program. If a pin is not used for
multiplexed functions, the pin can be configured as I/O port
Two extended interrupts nIRQ2 (GPIO0 pin) and nIRQ3 (nWAIT pin) are used the same interrupt request
(channel #31) of AIC. It can be programmed as low/high sensitive or positive/negative edge triggered.
When interrupt #31 assert in AIC, software can poll XISTATUS status register to identify which interrupt
occur.
These 31 IO pins are divided into 7 groups according to its peripheral interface definition.
Port0: 5-pin input/output port
Port1: 2-pin input/output port
Port2: 10-pin input/output port
Port3: Reserved
Port4: 1-pin input/output port
Port5: 13-pin input/output port
need updated
Port6: Reserved
Table 7.13.1 GPIO multiplexed functions table
PORT0
Configurable Pin Functions
0
GPIO0
AC97_nRESET
(I²S_MCLK)
nIRQ2
USBPWREN
1
GPIO1
AC97_DATAI (I²S_DATAI)
PWM0
DTR3
2
GPIO2
AC97_DATAO
(I²S_DATAO)
PWM1
DSR3
3
GPIO3
AC97_SYNC
(I²S_LRCLK)
PWM2
TXD3
4
GPIO4
AC97_BITCLK
(I²S_BITCLK)
PWM3
RXD3
PORT1
Configuration Pin Functions
0
GPIO18
-
nXDACK
-
1
GPIO19
-
nXDREQ
-
PORT2
Configuration Pin Functions
0
GPIO20
PHY_RXERR
KPCOL0
-
1
GPIO21
PHY_CRSDV
KPCOL1
-
2
GPIO22
PHY_RXD[0]
KPCOL2
-
3
GPIO23
PHY_RXD[1]
KPCOL3
-
- 321 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Table 7.13.1 GPIO multiplexed functions table, continued
4
GPIO24
PHY_REFCLK
KPCOL4
-
5
GPIO25
PHY_TXEN
KPCOL5
-
6
GPIO26
PHY_TXD[0]
KPCOL6
-
7
GPIO27
PHY_TXD[1]
KPCOL7
-
8
GPIO28
PHY_MDIO
KPROW0
-
9
GPIO29
PHY_MDC
KPROW1
-
PORT3
Configuration Pin Functions
RESERVED
PORT4
0
PORT5
0
1
2
3
4
5
6
7
8
9
10
11
12
PORT6
Configuration Pin Functions
GPIO30
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GP1O17
nWAIT
nIRQ3
Configuration Pin Functions
TXD0
RXD0
TXD1
RXD1
TXD2
CTS1
RXD2
RTS1
SCL0
SFRM
SDA0
SSPTXD
SCL1
SCLK
SDA1
SSPRXD
nWDOG
USBPWREN
nIRQ0
nIRQ1
USBOVRCUR
Configuration Pin Function
RESERVED
- 322 -
PS2CLK
PS2DATA
TIMER0
TIMER1
KPROW3
KPROW2
-
W90N745CD/W90N745CDG
7.13.1 GPIO Register Description
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GPIO_CFG0
0xFFF8_3000
R/W
GPIO Port0 Configuration
Register
0x0000_0000
GPIO_DIR0
0xFFF8_3004
R/W
GPIO Port0 Direction Control
Register
0x0000_0000
GPIO_DATAOUT0
0xFFF8_3008
R/W
GPIO Port0 Data Output
Register
0x0000_0000
GPIO_DATAIN0
0xFFF8_300C
R
GPIO Port0 Data Input
Register
0xXXXX_XXXX
GPIO_CFG1
0xFFF8_3010
R/W
GPIO port1 configuration
register
0x0000_0000
GPIO_DIR1
0xFFF8_3014
R/W
GPIO port1 direction control
register
0x0000_0000
GPIO_DATAOUT1
0xFFF8_3018
R/W
GPIO port1 data output
register
0x0000_0000
GPIO_DATAIN1
0xFFF8_301C
R
GPIO port1 data input
register
0xXXXX_XXXX
GPIO_CFG2
0xFFF8_3020
R/W
GPIO Port2 Configuration
Register
0x0000_0000
GPIO_DIR2
0xFFF8_3024
R/W
GPIO Port2 Direction Control
Register
0x0000_0000
GPIO_DATAOUT2
0xFFF8_3028
R/W
GPIO Port2 Data Output
Register
0x0000_0000
GPIO_DATAIN2
0xFFF8_302C
R
GPIO Port2 Data Input
Register
0xXXXX_XXXX
GPIO_CFG4
0xFFF8_3040
R/W
GPIO Port4 Configuration
Register
0x0015_5555
GPIO_DIR4
0xFFF8_3044
R/W
GPIO Port4 Direction Control
Register
0x0000_0000
GPIO_DATAOUT4
0xFFF8_3048
R/W
GPIO Port4 Data Output
Register
0x0000_0000
GPIO_DATAIN4
0xFFF8_304C
R
GPIO Port4 Data Input
Register
0xXXXX_XXXX
GPIO_CFG5
0xFFF8_3050
R/W
GPIO Port5 Configuration
Register
0x0000_0000
GPIO_DIR5
0xFFF8_3054
R/W
GPIO Port5 Direction Control
Register
0x0000_0000
GPIO_DATAOUT5
0xFFF8_3058
R/W
GPIO Port5 Data Output
Register
0x0000_0000
- 323 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Register Description, continued.
REGISTER
ADDRESS
R/W
GPIO_DATAIN5
0xFFF8_305C
R
GPIO_DBNCECON
0xFFF8_3070
R/W
GPIO_XICFG
0xFFF8_3074
R/W
GPIO_XISTATUS
0xFFF8_3078
R/W
DESCRIPTION
RESET VALUE
GPIO Port5 Data Input
Register
GPIO Input Debounce
Control Register
Extend Interrupt Configure
Register
Extend Interrupt Status
Register
0xXXXX_XXXX
0x0000_0000
0xXXXX_XXX0
0xXXXX_XXX0
7.13.2 GPIO Register Description
GPIO Port0 Configuration Register (GPIO_CFG0)
REGISTER
ADDRESS
GPIO_CFG0
0xFFF8_3000
31
30
R/W
DESCRIPTION
R/W
29
RESET VALUE
GPIO port0 configuration register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
PT0CFG3
PT0CFG4
4
3
PT0CFG2
11
PT0CFG0
NAME
2
PT0CFG1
10
TYPE
1
NAME
0
PT0CFG0
01
TYPE
NAME
00
TYPE
NAME
TYPE
O
GPIO0
I/O
AC97RESET
PORT0_0
USB_PWREN
O
nIRQ2
I
or
I²SMCLK
11
PT0CFG1
NAME
10
TYPE
NAME
01
TYPE
NAME
00
TYPE
NAME
TYPE
O
GPIO1
I/O
AC97DATAI
PORT0_1
DTR3
O
PWM0
O
or
I²SDATAI
- 324 -
W90N745CD/W90N745CDG
Continued
11
PT0CFG2
10
NAME
TYPE
NAME
01
TYPE
NAME
00
TYPE
NAME
TYPE
O
GPIO2
I/O
AC97DATAO
PORT0_2
DSR3
I
PWM1
O
or
I²SDATAO
11
PT0CFG3
10
NAME
TYPE
NAME
01
TYPE
NAME
00
TYPE
NAME
TYPE
O
GPIO3
I/O
AC97SYNC
PORT0_3
TXD3
O
PWM2
O
or
I²SLRCLK
11
PT0CFG4
10
NAME
PORT0_4
TYPE
RXD3
O
NAME
PWM3
01
TYPE
O
00
NAME
TYPE
AC97BITCLK
I
or
I²SBITCLK
NAME
TYPE
GPIO4
I/O
O
GPIO Port0 Direction Register (GPIO_DIR0)
REGISTER
ADDRESS
GPIO_DIR0
31
0xFFF8_3004
30
29
R/W
DESCRIPTION
RESET VALUE
GPIO port0 in/out direction control
and pull-up enable register
R/W
28
27
0x0000_0000
26
25
24
18
17
16
RESERVED
23
22
21
20
19
RESERVED
15
14
13
PUPEN0[3:0]
12
11
10
9
8
2
1
0
RESERVED
7
6
5
4
3
RESERVED
OMDEN0[4:0]
- 325 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
DESCRIPTION
[31:20]
RESERVED
[19:16]
PUPEN0
[15:5]
RESERVED
[4:0]
GPIO3 -GPIO0 port pin internal pull-up resister enable
There are 4 bits for this register, the corresponding bit is set to “1”
will enable pull-up resister on IO pin.
1 = enable
0 = disable
After power on the pull-up resisters are disabled.
NOTE: GPIO4 is used as AC97 BITCLK input, an IO pad with
Schmitt trigger input buffer PDB04SDGZ is implemented for this
pin. Due to TSMC IO library without pull-up register, an external
pull-up resister is necessary.
GPIO4 ~GPIO0 output mode enable
1 = output mode
0 = input mode
NOTE: Output mode enable bits are valid only when bit
PT0CFG4-0 is configured as general purpose I/O mode.
Each port pin can be enabled individually by setting the
corresponding control bit.
OMDEN0
GPIO Port0 Data Output Register (GPIO_DATAOUT0)
REGISTER
ADDRESS
R/W
GPIO_DATAOUT0
0xFFF8_3008
R/W
29
28
31
30
DESCRIPTION
RESET VALUE
GPIO port0 data output register
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
DATAOUT0
BITS
[31:5]
[4:0]
DESCRIPTION
RESERVED
-
DATAOUT0
PORT0 data output value
Writing data to this register will reflect the data value on the
corresponding port0 pin when it is configured as general purpose
output pin. And writing data to reserved bits is not effective.
- 326 -
W90N745CD/W90N745CDG
GPIO Port0 Data Input Register (GPIO_DATAIN0)
REGISTER
GPIO_DATAIN0
31
ADDRESS
R/W
0xFFF8_300C
R/W
30
29
DESCRIPTION
RESET VALUE
GPIO port0 data input register
28
27
0xXXXX_XXXX
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
DATAIN0
BITS
DESCRIPTION
[31:5]
RESERVED
[4:0]
DATAIN0
PORT0 data input value
The DATAIN0 indicates the status of each GPIO0~GPIO4 port pin
regardless of its operation mode. The reserved bits will be read as
“0”.
GPIO Port1 Configuration Register (GPIO_CFG1)
REGISTER
ADDRESS
GPIO_CFG1
31
0xFFF8_3010
30
29
R/W
DESCRIPTION
R/W
RESET VALUE
GPIO port1 configuration register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
PT1CFG1
- 327 -
PT1CFG0
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
*In the following pin definition, mark with shading is default function.
11
PT1CFG0
NAME
10
TYPE
PORT1_0
TYPE
NAME
TYPE
NAME
TYPE
-
-
nXDACK
O
GPIO18
I/O
11
NAME
PORT1_1
10
TYPE
00
NAME
-
PT1CFG1
01
01
00
NAME
TYPE
NAME
TYPE
NAME
TYPE
-
-
nXDREQ
I
GPIO19
I/O
-
GPIO Port1 Direction Register (GPIO_DIR1)
REGISTER
ADDRESS
GPIO_DIR1
31
R/W
0xFFF8_3014
30
DESCRIPTION
R/W
29
RESET VALUE
GPIO port0 in/out direction control
and pull-up enable register
28
27
0x0000_0000
26
25
24
18
17
16
RESERVED
23
22
21
20
19
RESERVED
15
14
13
PUPEN1[1:0]
12
11
10
9
8
2
1
0
RESERVED
7
6
5
4
3
RESERVED
BITS
[31:18]
OMDEN1[1:0]
DESCRIPTION
RESERVED
-
[17:16]
PUPEN1
GPIO19 ~ GPIO18 port pins internal pull-up resister enable
This is a 2-bit registers, set corresponding bit to “1” will enable pull
up resister in IO pin.
1 = enable
0 = disable
After power on the resisters are disabled.
[15:2]
RESERVED
-
- 328 -
W90N745CD/W90N745CDG
Continued.
[1:0]
GPIO19 ~ GPIO18 output mode enable
1 = enable
0 = disable
NOTE: Output mode enable bits are valid only when bit
PT1CFG1-0 is configured as general purpose I/O mode.
Each port pin can be enabled individually by setting the
corresponding control bit.
OMDEN1
GPIO Port1 Data Output Register (GPIO_DATAOUT1)
REGISTER
ADDRESS
R/W
GPIO_DATAOUT1
0xFFF8_3018
R/W
29
28
31
30
DESCRIPTION
RESET VALUE
GPIO port1 data output register
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
BITS
[31:2]
DATAOUT1[1:0]
DESCRIPTION
RESERVED
PORT1 data output value
[1:0]
DATAOUT1
Writing data to this register will reflect the data value on the
corresponding port1 pin when it is configured as general purpose
output pin. And writing data to reserved bits is not effective.
GPIO Port1 Data Input Register (GPIO_DATAIN1)
REGISTER
GPIO_DATAIN1
ADDRESS
R/W
0xFFF8_301C
R/W
DESCRIPTION
GPIO port1 data input register
- 329 -
RESET VALUE
0xXXXX_XXXX
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
DATAIN1[1:0]
BITS
DESCRIPTION
[31:2]
RESERVED
[1:0]
DATAIN1
Port1 input data register
The DATAIN1 indicates the status of each GPIO19~GPIO18 pin
regardless of its operation mode. The reserved bits are read as 0s.
GPIO Port2 Configuration Register (GPIO_CFG2)
REGISTER
ADDRESS
GPIO_CFG2
31
0xFFF8_3020
30
R/W
DESCRIPTION
R/W
29
RESET VALUE
GPIO port2 configuration register
28
27
0x0000_0000
26
25
24
18
17
16
RESERVED
23
22
21
20
19
RESERVED
15
14
PT2CFG9
13
PT2CFG7
7
12
11
PT2CFG6
6
5
PT2CFG3
PT2CFG8
10
9
PT2CFG5
4
3
PT2CFG2
8
PT2CFG4
2
1
PT2CFG1
0
PT2CFG0
*In the following pin definition, mark with shading is default function.
PT2CFG0
PORT2_0
PT2CFG1
11
Name
10
Type
RESERVED
11
01
00
Name
Type
Name
Type
Name
Type
KPCOL0
I
PHY_RXERR
I
GPIO20
I/O
10
- 330 -
01
00
W90N745CD/W90N745CDG
Name
PORT2_1
PT2CFG2
PORT2_2
PT2CFG3
PORT2_3
PT2CFG4
PORT2_4
PT2CFG5
PORT2_5
PT2CFG6
PORT2_6
PT2CFG7
PORT2_7
PT2CFG8
PORT2_8
PT2CFG9
PORT2_9
Type
RESERVED
11
Name
Type
11
Type
11
Type
11
Type
11
Type
11
Type
11
I
PHY_CRSDV
I
GPIO21
I/O
01
Type
11
Type
Name
Type
Name
Type
KPCOL2
I
PHY_RXD[0]
I
GPIO22
I/O
01
RESERVED
00
Name
Type
Name
Type
Name
Type
KPCOL3
I
PHY_RXD[1]
I
GPIO23
I/O
01
00
Name
Type
Name
Type
Name
Type
KPCOL4
I
PHY_REFCL
K
I
GPIO24
I/O
01
00
Name
Type
Name
Type
Name
Type
KPCOL5
I
PHY_TXEN
O
GPIO25
I/O
01
00
Name
Type
Name
Type
Name
Type
KPCOL6
I
PHY_TXD[0]
O
GPIO26
I/O
01
00
Name
Type
Name
Type
Name
Type
KPCOL7
I
PHY_TXD[1]
O
GPIO27
I/O
01
00
Name
Type
Name
Type
Name
Type
KPROW0
O
PHY_MDIO
I/O
GPIO28
I/O
10
Type
00
Name
10
RESERVED
Name
KPCOL1
10
RESERVED
Name
Type
10
RESERVED
Name
Name
10
RESERVED
Name
Type
10
RESERVED
Name
Name
10
RESERVED
Name
Type
10
RESERVED
Name
Name
01
00
Name
Type
Name
Type
Name
Type
KPROW1
O
PHY_MDC
O
GPIO29
I/O
- 331 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Port2 Direction Register (GPIO_DIR2)
REGISTER
ADDRESS
GPIO_DIR2
31
R/W
0xFFF8_3024
30
R/W
29
DESCRIPTION
GPIO port2 in/out direction control
and pull-up enable register
28
27
26
RESERVED
23
22
21
RESET VALUE
25
0x0000_0000
24
PUPEN2[9:8]
20
19
18
17
16
10
9
8
PUPEN2[7:0]
15
14
13
12
11
RESERVED
7
6
5
OMDEN2[9:8]
4
3
2
1
0
OMDEN2[7:0]
BITS
[31:26]
DESCRIPTION
RESERVED
-
[25:16]
PUPEN2
GPIO29 ~ GPIO20 port pin internal pull-up resister enable
There are 10 bits for this register, the corresponding bit is set to
“1” will enable pull-up resister on IO pin.
1 = enable
0 = disable
After power on, the registers are disabled.
[15:10]
RESERVED
-
OMDEN2
GPIO19 ~ GPIO20 output mode enable
1 = output mode
0 = input mode
NOTE: Output mode enable bits are valid only when bit
PT2CFG9-0 is configured as general purpose I/O mode.
Each port pin can be enabled individually by setting the
corresponding control bit.
[9:0]
- 332 -
W90N745CD/W90N745CDG
PGPIO Port2 Data Output Register (GPIO_DATAOUT2)
REGISTER
GPIO_DATAOUT2
31
ADDRESS
R/W
0xFFF8_3028
R/W
30
29
28
DESCRIPTION
RESET VALUE
GPIO port2 data output register
27
0x0000_0000
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
DATAOUT2[9:8]
4
3
2
1
0
DATAOUT2[7:0]
BITS
[31:10]
DESCRIPTION
RESERVED
PORT2 data output value
[9:0]
Writing data to this register will reflect the data value on the
corresponding port2 pin when it is configured as general purpose
output pin. And writing data to reserved bits is not effective.
DATAOUT2
GPIO Port2 Data Input Register (GPIO_DATAIN2)
REGISTER
GPIO_DATAIN2
31
30
ADDRESS
R/W
0xFFF8_302C
R/W
29
28
DESCRIPTION
RESET VALUE
GPIO port2 data input register
27
0xXXXX_XXXX
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
DATAIN2[9:8]
4
3
2
1
0
DATAIN2[7:0]
- 333 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
[31:10]
DESCRIPTION
RESERVED
Port2 input data register
[9:0]
The DATAIN2 indicates the status of each GPIO18~GPIO27 pin
regardless of its operation mode. The reserved bits will be read as
0s.
DATAIN2
GPIO Port4 Configuration Register (GPIO_CFG4)
REGISTER
ADDRESS
GPIO_CFG4
31
0xFFF8_3040
30
29
R/W
DESCRIPTION
R/W
RESET VALUE
GPIO port4 configuration register
28
27
0x0015_5555
26
25
24
18
17
16
RESERVED
23
22
21
RESERVED
15
20
19
PT4CFG10
14
13
RESERVED
12
11
10
9
8
2
1
0
RESERVED
7
6
5
4
3
RESERVED
*In the following pin definition, mark with shading is default function.
11
PT4CFG10
NAME
PORT4_10
10
TYPE
RESERVED
01
00
NAME
TYPE
NAME
TYPE
NAME
TYPE
nIRQ3
I
nWAIT
I
GPIO28
I/O
- 334 -
W90N745CD/W90N745CDG
GPIO Port4 Direction Register (GPIO_DIR4)
REGISTER
ADDRESS
GPIO_DIR4
31
R/W
0xFFF8_3044
30
DESCRIPTION
GPIO port4 in/out direction control
and pull-up enable register
R/W
29
28
27
RESERVED
23
22
21
RESET VALUE
26
PUPEN4[
10]
20
19
0x0000_0000
25
24
RESERVED
18
17
16
10
9
8
RESERVED
15
14
13
12
11
RESERVED
7
6
5
OMDEN4
[10]
4
3
2
RESERVED
1
0
RESERVED
BITS
[31:27]
DESCRIPTION
RESERVED
-
[26]
PUPEN4
GPIO28 pin internal pull-up resister enable
There is 1 bit for this register, the bit is set to “1” will enable pull-up
resister on IO pin.
1 = enable
0 = disable
After power on the pull-up resister is disabled
[25:11]
RESERVED
GPIO28 output mode enable
1 = enable
0 = disable
[10]
OMDEN4
NOTE: Output mode enable bits are valid only when bit
PT4CFG10 is configured as general purpose I/O mode.
Each port pin can be enabled individually by setting the
corresponding control bit.
[9:0]
RESERVED
-
- 335 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Port4 Data Output Register (GPIO_DATAOUT4)
REGISTER
GPIO_DATAOUT4
31
ADDRESS
R/W
0xFFF8_3048
R/W
30
29
28
DESCRIPTION
RESET VALUE
GPIO port4 data output register
27
0x0000_0000
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
DATAOUT4[10
]
5
4
3
2
RESERVED
1
0
RESERVED
BITS
[31:11]
DESCRIPTION
RESERVED
PORT4 data output value
[10]
DATAOUT4
Writing data to this register will reflect the data value on the
corresponding port4 pin when it is configured as general purpose
output pin. And writing data to reserved bits is not effective.
[9:0]
RESERVED
-
GPIO Port4 Data Input Register (GPIO_DATAIN4)
REGISTER
GPIO_DATAIN4
31
30
ADDRESS
R/W
0xFFF8_304C
R/W
29
28
DESCRIPTION
RESET VALUE
GPIO port4 data input register
27
0xXXXX_XXXX
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
DATAIN4[10]
4
3
RESERVED
- 336 -
2
RESERVED
1
0
W90N745CD/W90N745CDG
BITS
[31:11]
DESCRIPTION
RESERVED
Port4 input data register
[10:0]
DATAIN4
The DATAIN4 indicates the status of GPIO28 pin regardless of its
operation mode. The reserved bits will be read as 0s
[9:0]
RESERVED
-
GPIO Port5 Configuration Register (GPIO_CFG5)
REGISTER
ADDRESS
GPIO_CFG5
31
0xFFF8_3050
30
R/W
R/W
29
DESCRIPTION
RESET VALUE
GPIO port5 configuration register
28
27
26
0x0000_0000
25
RESERVED
23
22
21
PT5CFG11
15
20
13
PT5CFG7
7
PT5CFG12
19
PT5CFG10
14
12
5
PT5CFG3
18
17
PT5CFG9
11
PT5CFG6
6
24
PT5CFG8
10
9
PT5CFG5
4
3
PT5CFG2
16
8
PT5CFG4
2
1
PT5CFG1
0
PT5CFG0
*In the following pin definition, mark with shading is default function.
PT5CFG0
PORT5_0
PT5CFG1
PORT5_1
PT5CFG2
PORT5_2
11
Name
10
Type
Name
01
Type
RESERVED
RESERVED
11
10
Name
Type
Name
Type
RESERVED
11
10
Type
RESERVED
Name
Name
Type
Name
Type
TXD0
O
GPIO5
I/O
01
RESERVED
Name
00
00
Name
Type
Name
Type
RXD0
I
GPIO6
I/O
01
Type
RESERVED
- 337 -
00
Name
Type
Name
Type
TXD1
O
GPIO7
I/O
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PT5CFG3
PORT5_3
PT5CFG4
PORT5_4
11
Name
10
Type
Name
01
Type
RESERVED
RESERVED
11
10
00
Name
Type
Name
Type
RXD1
I
GPIO8
I/O
01
00
Name
Type
Name
Type
Name
Type
Name
Type
PS2CLK
O
CTS1
I
TXD2
IO
GPIO9
I/O
Continued
PT5CFG5
PORT5_5
PT5CFG6
PORT5_6
PT5CFG7
PORT5_7
PT5CFG8
PORT5_8
PT5CFG9
PORT5_9
PT5CFG10
PORT5_10
11
10
01
00
Name
Type
Name
Type
Name
Type
Name
Type
PS2DATA
I/O
RTS1
IO
RXD2
I
GPIO10
I/O
11
10
01
00
Name
Type
Name
Type
Name
Type
Name
Type
TIMER0
O
SFRM
O
SCL0
I/O
GPIO11
I/O
11
10
01
Name
Type
Name
Type
TIMER1
O
SSPTX
D
O
11
Name
SDA0
10
00
Type
Name
Type
I/O
GPIO12
I/O
01
00
Name
Type
Name
Type
Name
Type
Name
Type
KPROW2
O
SSPSCLK
O
SCL1
I/O
GPIO13
I/O
11
10
01
00
Name
Type
Name
Type
Name
Type
Name
Type
KPROW3
O
SSPRXD
I/O
SDA1
I/O
GPIO14
I/O
11
Name
10
Type
RESERVED
01
00
Name
Type
Name
Type
Name
Type
USBPWREN
O
nWDOG
O
GPIO15
I/O
- 338 -
W90N745CD/W90N745CDG
11
PT5CFG11
Name
PORT5_11
10
Type
Name
RESERVED
Name
PORT5_12
Type
RESERVED
11
PT5CFG12
01
Name
Type
Name
Type
nIRQ0
I
GPIO16
I/O
10
01
00
Name
Type
Name
Type
Name
Type
USBOVCUR
I
nIRQ1
I
GPIO17
I/O
Type
RESERVED
00
GPIO Port5 Direction Register (GPIO_DIR5)
REGISTER
GPIO_DIR5
31
ADDRESS
0xFFF8_3054
30
29
R/W
DESCRIPTION
GPIO port5 in/out direction control
and pull-up enable register
R/W
28
27
RESERVED
23
22
RESET VALUE
26
0x0000_0000
25
24
PUPEN5[12:8]
21
20
19
18
17
16
11
10
9
8
1
0
PUPEN5[7:0]
15
14
13
12
RESERVED
7
6
OMDEN5[12:8]
5
4
3
2
OMDEN5[7:0]
BITS
DESCRIPTION
[31:29]
RESERVED
[28:16]
PUPEN5
[15:13]
RESERVED
[12:0]
OUTEN5
GPIO17 ~ GPIO5 port pin internal pull-up resister enable
There are 13 bits for this register, the corresponding bit is set to
“1” will enable pull-up resister on IO pin.
1 = enable
0 = disable
After power on the pull-up resisters are disable.
GPIO17 ~ GPIO5 output mode enable
1 = output mode
0 = input mode
NOTE: Output mode enable bits are valid only when bit
PT5CFG12-0 is configured as general purpose I/O mode.
Each port pin can be enabled individually by setting the
corresponding control bit.
- 339 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Port5 Data Output Register (GPIO_DATAOUT5)
REGISTER
GPIO_DATAOUT5
31
ADDRESS
R/W
0xFFF8_3058
R/W
30
29
DESCRIPTION
RESET VALUE
GPIO port5 data output register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
1
0
RESERVED
23
22
21
20
RESERVED
15
14
13
12
RESERVED
7
6
DATAOUT5[12:8]
5
4
3
2
DATAOUT5[7:0]
BITS
[31:13]
DESCRIPTION
RESERVED
PORT5 data output value
[12:0]
Writing data to this register will reflect the data value on the
corresponding port5 pin when it is configured as general purpose
output pin. And writing data to reserved bits is not effective.
DATAOUT5
GPIO Port5 Data Input Register (GPIO_DATAIN5)
REGISTER
GPIO_DATAIN5
31
ADDRESS
R/W
0xFFF8_305C
R/W
30
29
DESCRIPTION
RESET VALUE
GPIO port5 data input register
28
0xXXXX_XXXX
27
26
25
24
19
18
17
16
11
10
9
8
1
0
RESERVED
23
22
21
20
RESERVED
15
14
13
12
RESERVED
7
6
DATAIN5[12:8]
5
4
3
DATAIN5[7:0]
- 340 -
2
W90N745CD/W90N745CDG
BITS
[31:13]
DESCRIPTION
RESERVED
Port5 input data register
[12:0]
The DATAIN5 indicates the status of each GPIO17~GPIO5 pin
regardless of its operation mode. The reserved bits will be read
as 0s.
DATAIN5
GPIO Debounce Control Register (GPIO_DBNCECON)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GPIO_DBNCECON
0xFFF8_3070
R/W
GPIO debounce control register
0xXXXX_XX00
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
DBEN1
DBEN0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
RESERVED
5
DBCLKSEL
BITS
[31:7]
4
3
RESERVED
DESCRIPTION
RESERVED
Debounce Clock Selection
[6:4]
DBCLKSEL
These 3 bits are used to select the clock rate for de-bouncer circuit. The
relationship between the system clock HCLK and the de-bounce clock
TCLK_BUN is as follows: TCLK_BUN = HCLK / 2DBCLKSEL
[3:2]
RESERVED
Debounce circuit enable for GPIO17 (nIRQ1)
[1]
DBEN1
1 = enable
0 = disable
Debounce circuit enable for GPIO16 (nIRQ0)
[0]
DBEN0
1 = enable
0 = disable
- 341 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Interrupt Configuration Register (GPIO_XICFG)
REGISTER
ADDRESS
GPIO_XICFG
31
0xFFF8_3074
30
R/W
R/W
29
DESCRIPTION
RESET VALUE
Extend interrupt configure register
0xXXXX_XX00
28
27
26
25
24
18
17
16
10
9
8
3
2
1
0
EnIRQ2
DBE2
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
EnIRQ3
DBE3
5
4
ISTYPE3
BITS
[31:8]
ISTYPE2
DESCRIPTION
RESERVED
Enable nIRQ3
Setting this bit 1 to enable nIRQ3.
1 = Enable nIRQ3
[7]
EnIRQ3
0 = Disable nIRQ3
The AIC interrupt channel 31 is reserved for nIRQ3 and nIRQ2 (wired-OR),
if this bit is set and nIRQ3 occur, then it will send an interrupt request
signal into AIC module.
Debounce circuit enable for nIRQ3
(alternative function of nWAIT pin)
[6]
DBE3
The nIRQ3 shares the same debounce circuit with nIRQ[3:0], software can
configure debounce sampling time in GPIO_DEBNCE control register.
DBE3 function is the same as DBE0 in GPIO_DBENCE register.
1 = Enable debounce
0 = Disable debounce
nIRQ3 source type
ISTYPE3
[5:4]
ISTYPE3
Interrupt Source Type
2’b00
LOW level sensitive
2’b01
HIGH level sensitive
2’b10
Negative edge triggered
2’b11
Positive edge triggered
- 342 -
W90N745CD/W90N745CDG
Continued
[3]
[2]
EnIRQ2
Enable nIRQ2
Setting this bit 1 to enable nIRQ2
1 = Enable nIRQ2
0 = Disable nIRQ2
The AIC interrupt channel 31 is reserved for nIRQ3 and nIRQ2 (wire-OR),
if this bit is set and nIRQ2 occur, then it will send an interrupt request
signal into AIC module.
DBE2
Debounce circuit enable for nIRQ2
(alternative function of GPIO0 pin)
1 = Enable debounce
0 = Disable debounce
The nIRQ2 shares the same debounce circuit with nIRQ[1:0], software can
configure debounce sampling time in GPIO_DEBNCE control register.
DBE2 function is the same as DBE0 in GPIO_DBENCE register.
nIRQ2 source type
[1:0]
ISTYPE2
ISTYPE2
2’b00
2’b01
2’b10
2’b11
- 343 -
Interrupt Source Type
LOW level sensitive
HIGH level sensitive
Negative edge triggered
Positive edge triggered
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Interrupt Status Register (GPIO_XISTATUS)
REGISTER
GPIO_XISTATUS
31
ADDRESS
R/W
0xFFF8_3078
R/W
30
29
DESCRIPTION
RESET VALUE
Extend interrupt status register
28
27
0xXXXX_XX00
26
25
24
18
17
16
10
9
8
2
1
0
nIRQ3
nIRQ2
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
BITS
[31:2]
DESCRIPTION
RESERVED
Interrupt 3 status
[1]
nIRQ3
When interrupt input is detected with ISTYPE3 triggered condition, this
flag will be set. It must be cleared by software.
1 = interrupt nIRQ3 is detected.
0 = No interrupt
Interrupt 2 status
[0]
nIRQ2
When interrupt input is detected with ISTYPE2 triggered condition, this
flag will be set. It must be cleared by software.
1 = interrupt nIRQ2 is detected.
0 = no interrupt
- 344 -
W90N745CD/W90N745CDG
7.14 I2C Interface
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up
to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and
400kbps modes are supported directly. For High-speed mode special IOs are needed. If these IOs are
available and used, then High-speed mode is also supported.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byteby-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the
MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled
during the high period of SCL; therefore, the SDA line may be changed only during the low period of
SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is
high is interpreted as a command (START or STOP).
The I2C Master Core includes the following features:
• AMBA APB interface compatible
• Compatible with Philips I2C standard, support master mode
• Multi Master Operation
• Clock stretching and wait state generation
• Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
• Software programmable acknowledge bit
• Arbitration lost interrupt, with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Supports 7 bit addressing mode
• Fully static synchronous design with one clock domain
• Software mode I2C
- 345 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.14.1 I2C Protocol
Normally, a standard communication consists of four parts:
1) START or Repeated START signal generation
2) Slave address transfer
3) Data transfer
4) STOP signal generation
SCL
1
2
SDA
A6
A5
7
8
9
1
2
3-7
8
9
A0
R/W
ACK
D7
D6
D5 - D1
D0
NACK
ACK
P
S
or
Sr
A4 - A1
MSB
LSB
MSB
P
or
Sr
LSB
Fig. 7.15.1.1 Data transfer on the I2C-bus
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
data transfer
(n bytes + acknowledge)
'0'(write)
from master to slave
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = START condition
P = STOP condition
from slave to master
A master-transmitter addressing a slave receiver with a 7-bit address
The transfer direction is not changed
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A
data transfer
(n bytes + acknowledge)
'1'(read)
A master reads a slave immediately after the first byte (address)
- 346 -
P
Sr
W90N745CD/W90N745CDG
START or Repeated START signal
When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines
are high), a master can initiate a transfer by sending a START signal. A START signal, usually
referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH.
The START signal denotes the beginning of a new data transfer.
A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses
this method to communicate with another slave or the same slave in a different transfer direction (e.g.
from writing to a device to reading from a device) without releasing the bus.
The I2C core generates a START signal when the START bit in the Command Register (CMDR) is set
and the READ or WRITE bits are also set. Depending on the current status of the SCL line, a START
or Repeated START is generated.
STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal, usually
referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.
SCL
SDA
START condition
STOP condition
START and STOP conditions
Slave Address Transfer
The first byte of data transferred by the master immediately after the START signal is the slave
address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data
transfer direction. No two slaves in the system can have the same address. Only the slave with an
address that matches the one transmitted by the master will respond by returning an acknowledge bit
by pulling the SDA low at the 9th SCL clock cycle.
The core treats a Slave Address Transfer as any other write action. Store the slave device’s address
in the Transmit Register (TxR) and set the WRITE bit. The core will then transfer the slave address on
the bus.
MSB
A6
LSB
A5
A4
A3
A2
A1
A0
R/W
slave address
The first byte after the START procedure
- 347 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Data Transfer
Once successful slave addressing has been achieved, the data transfer can proceed on a byte-bybyte basis in the direction specified by the RW bit sent by the master. Each transferred byte is
followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge
(NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated
START signal and start a new transfer cycle.
If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases
the SDA line for the master to generate a STOP or Repeated START signal.
To write data to a slave, store the data to be transmitted in the Transmit Register (TxR) and set the
WRITE bit. To read data from a slave, set the READ bit. During a transfer the core set the I2C_TIP
flag, indicating that a Transfer is In Progress. When the transfer is done the I2C_TIP flag is cleared,
the IF flag set if enabled, then an interrupt generated. The Receive Register (RxR) contains valid data
after the IF flag has been set. The software may issue a new write or read command when the
I2C_TIP flag is cleared.
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Bit transfer on the I2C-bus
clock pulse for
acknowledgement
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT BY
TRANSMITTER
not acknowledge
DATA OUTPUT BY
RECEIVER
S
acknowledge
START
condition
Acknowledge on the I2C-bus
- 348 -
W90N745CD/W90N745CDG
7.14.2 I2C Serial Interface Control Registers Map
R: read only, W: write only, R/W: both read and write
NOTE1: The reset value of I2C_WR0/1 is 0x3F only when SCR, SDR and SER are connected to pull
high resistor.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
2
I C Interface 0
2
I C_CSR0
0xFFF8_6000
2
R/W
2
0x0000_0000
2
I C0 Control and Status Register
I C_DIVIDER0
0xFFF8_6004
R/W
I C0 Clock Prescale Register
0x0000_0000
I2C_CMDR0
0xFFF8_6008
R/W
I2C0 Command Register
0x0000_0000
2
I C_SWR0
0xFFF8_600C
2
I C_RxR0
R/W
0xFFF8_6010
2
I C_TxR0
R
0xFFF8_6014
2
0x0000_003F
2
0x0000_0000
I C0 Software Mode Control Register
I C0 Data Receive Register
R/W
2
I C0 Data Transmit Register
0x0000_0000
I2C Interface 1
I2C_CSR1
0xFFF8_6100
2
I C_DIVIDER1
R/W
0xFFF8_6104
2
R/W
I2C1 Control and Status Register
0x0000_0000
2
I C1 Clock Prescale Register
0x0000_0000
2
I C_CMDR1
0xFFF8_6108
R/W
I C1 Command Register
0x0000_0000
I2C_SWR1
0xFFF8_610C
R/W
I2C1 Software Mode Control Register
0x0000_003F
I2C_RxR1
0xFFF8_6110
R
I2C1 Data Receive Register
0x0000_0000
2
I C_TxR1
0xFFF8_6114
R/W
2
I C1 Data Transmit Register
0x0000_0000
I2C Control and Status Register 0/1 (I2C_CSR0/1)
REGISTER
2
ADDRESS
R/W
DESCRIPTION
RESET VALUE
2
I C_CSR0
0xFFF8_6000 R/W I C Control and Status Register 0
0x0000_0000
I2C_CSR1
0xFFF8_6100 R/W I2C Control and Status Register 1
0x0000_0000
31
30
29
28
27
26
25
24
18
17
16
11
10
9
8
I2C_RxACK
I2C_BUSY
I2C_AL
I2C_TIP
3
2
1
0
Reserved
IF
IE
I2C_EN
Reserved
23
22
21
20
19
Reserved
15
14
13
12
Reserved
7
6
Reserved
5
Tx_NUM
4
- 349 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
BITS
[31:12]
DESCRIPTIONS
Reserved
2
[11]
[10]
I C_RxAC
K
2
I C_BUSY
Reserved
Received Acknowledge From Slave (Read only)
This flag represents acknowledge from the addressed slave.
0 = Acknowledge received (ACK).
1 = Not acknowledge received (NACK).
I2C Bus Busy (Read only)
0 = After STOP signal detected.
1 = After START signal detected.
I C_AL
Arbitration Lost (Read only)
This bit is set when the I2C core lost arbitration. Arbitration is lost when:
A STOP signal is detected, but no requested.
The master drives SDA high, but SDA is low.
I2C_TIP
Transfer In Progress (Read only)
0 = Transfer complete.
1 = Transferring data.
NOTE: When a transfer is in progress, you will not allow writing to any
register of the I2C master core except SWR.
[5:4]
Tx_NUM
Transmit Byte Counts
These two bits represent how many bytes are remained to transmit. When a
byte has been transmitted, the Tx_NUM will decrease 1 until all bytes are
transmitted (Tx_NUM = 0x0) or NACK received from slave. Then the
interrupt signal will assert if IE was set.
0x0 = Only one byte is left for transmission.
0x1 = Two bytes are left to for transmission.
0x2 = Three bytes are left for transmission.
0x3 = Four bytes are left for transmission.
[3]
Reserved
Reserved
[9]
[8]
2
[2]
IF
Interrupt Flag
The Interrupt Flag is set when:
Transfer has been completed.
Transfer has not been completed, but slave responded NACK (in multi-byte
transmit mode).
Arbitration is lost.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
[1]
IE
Interrupt Enable
0 = Disable I2C Interrupt.
1 = Enable I2C Interrupt.
[0]
I2C_EN
I2C Core Enable
0 = Disable I2C core, serial bus outputs are controlled by SDW/SCW.
1 = Enable I2C core, serial bus outputs are controlled by I2C core.
I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1)
- 350 -
W90N745CD/W90N745CDG
REGISTER
ADDRESS
R/W
I2C_DIVIDER0
0xFFF8_6004
R/W
2
I C_DIVIDER1
31
0xFFF8_6104
30
29
DESCRIPTION
RESET VALUE
I2C Clock Prescale Register 0
0x0000_0000
2
R/W
I C Clock Prescale Register 1
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
DIVIDER[15:8]
7
6
5
4
3
DIVIDER[7:0]
BITS
DESCRIPTIONS
Clock Prescale Register
[15:0]
DIVIDER
It is used to prescale the SCL clock line. Due to the structure of the I2C
interface, the core uses a 5*SCL clock internally. The prescale register must
be programmed to this 5*SCL frequency (minus 1). Change the value of the
prescale register only when the “I2C_EN” bit is cleared.
Example: pclk = 32MHz, desired SCL = 100KHz
prescale
=
32 MHz
− 1 = 63 ( dec ) = 3 F ( hex )
5 ∗ 100 KHz
- 351 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
I2C Command Register 0/1 (I2C_CMDR 0/1)
REGISTER
ADDRESS
2
R/W
DESCRIPTION
RESET VALUE
2
I C_CMDR0
0xFFF8_6008 R/W I C Command Register 0
0x0000_0000
I2C_CMDR1
0xFFF8_6108 R/W I2C Command Register 1
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
4
3
2
1
0
START
STOP
READ
WRITE
ACK
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
Reserved
2
NOTE: Software can write this register only when I C_EN = 1.
BITS
DESCRIPTIONS
[31:5]
Reserved
[4]
START
[3]
STOP
Generate Stop Condition
Generate stop condition on I2C bus.
[2]
READ
Read Data From Slave
Retrieve data from slave.
[1]
WRITE
Write Data To Slave
Transmit data to slave.
[0]
ACK
Reserved
Generate Start Condition
Generate (repeated) start condition on I2C bus.
Send Acknowledge To Slave
When I2C behaves as a receiver, sent ACK (ACK = ‘0’) or NACK (ACK
= ‘1’) to slave.
NOTE: The START, STOP, READ and WRITE bits are cleared automatically while transfer finished. READ and WRITE cannot
be set concurrently.
- 352 -
W90N745CD/W90N745CDG
I2C Software Mode Register 0/1(I2C_SWR 0/1)
REGISTER
2
ADDRESS
R/W
DESCRIPTION
RESET VALUE
2
I C_SWR0
0xFFF8_600C
R/W I C Software Mode Control Register 0
0x0000_003F
I2C_SWR1
0xFFF8_610C
R/W I2C Software Mode Control Register 1
0x0000_003F
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
Reserved
5
4
3
2
1
0
Reserved
SDR
SCR
Reserved
SDW
SCW
2
2
Note: This register is used as software mode of I C. Software can read/write this register no matter I C_EN is 0 or 1. But SCL
2
and SDA are controlled by software only when I C_EN = 0.
BITS
DESCRIPTIONS
[31:6]
Reserved
Reserved
[5]
Reserved
Reserved
[4]
SDR
Serial Interface SDA Status (Read only)
0 = SDA is Low.
1 = SDA is High.
[3]
SCR
Serial Interface SCK Status (Read only)
0 = SCL is Low.
1 = SCL is High.
[2]
Reserved
[1]
SDW
Serial Interface SDA Output Control
0 = SDA pin is driven Low.
1 = SDA pin is tri-state.
SCW
Serial Interface SCK Output Control
0 = SCL pin is driven Low.
1 = SCL pin is tri-state.
[0]
Reserved
I2C Data Receive Register 0/1 (I2C_RxR 0/1)
- 353 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
REGISTER
OFFSET
R/W
I2C_RXR0
0xFFF8_6010
R
2
I C_RXR1
31
0xFFF8_6110
30
R
DESCRIPTION
RESET VALUE
I2C Data Receive Register 0
0x0000_0000
2
I C Data Receive Register 1
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Rx [7:0]
BITS
DESCRIPTIONS
[31:8]
Reserved
[7:0]
Rx
Reserved
Data Receive Register
The last byte received via I2C bus will put on this register. The I2C core
only used 8-bit receive buffer.
- 354 -
W90N745CD/W90N745CDG
I2C Data Transmit Register 0/1 (I2C_TxR 0/1)
REGISTER
2
ADDRESS
R/W
DESCRIPTION
RESET VALUE
2
I C_TXR0
0xFFF8_6014 R/W I C Data Transmit Register
0x0000_0000
I2C_TXR1
0xFFF8_6114 R/W I2C Data Transmit Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Tx [31:24]
23
22
21
20
Tx [23:16]
15
14
13
12
Tx [15:8]
7
6
5
4
Tx [7:0]
BITS
DESCRIPTIONS
Data Transmit Register
The I2C core used 32-bit transmit buffer and provide multi-byte
transmit function. Set CSR[Tx_NUM] to a value that you want to
transmit. I2C core will always issue a transfer from the highest byte
first. For example, if CSR[Tx_NUM] = 0x3, Tx[31:24] will be
transmitted first, then Tx[23:16], and so on.
[31:0]
Tx
In case of a data transfer, all bits will be treated as data.
In case of a slave address transfer, the first 7 bits will be treated as 7bit address and the LSB represent the R/W bit. In this case,
LSB = 1, reading from slave
LSB = 0, writing to slave
- 355 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.15 Universal Serial Interface
The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters
received from the peripheral, and a parallel-to-serial conversion on data characters received from
CPU. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1
to the interrupt flag. The active level of device/slave select signal can be chosen to low active or high
active, which depends on the peripheral it’s connected. Writing a divisor into DIVIDER register can
program the frequency of serial clock output. This master core contains four 32-bit transmit/receive
buffers, and can provide burst mode operation. The maximum bits can be transmitted/received is 32
bits, and can transmit/receive data up to four times successive.
The USI (Microwire/SPI) Master Core includes the following features:
• AMBA APB interface compatible
• Support USI (Microwire/SPI) master mode
• Full duplex synchronous serial data transfer
• Variable length of transfer word up to 32 bits
• Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
• MSB or LSB first data transfer
• Rx and Tx on both rising or falling edge of serial clock independently
• 1 slave/device select lines
• Fully static synchronous design with one clock domain
- 356 -
W90N745CD/W90N745CDG
7.15.1 USI Timing Diagram
The timing diagram of USI is shown as following.
mw_ss_o
mw_sclk_o
mw_so_o
MSB
(Tx[7])
Tx[6]
Tx[5]
Tx[4]
Tx[3]
Tx[2]
Tx[1]
LSB
(Tx[0])
mw_si_i
MSB
(Rx[7])
Rx[6]
Rx[5]
Rx[4]
Rx[3]
Rx[2]
Rx[1]
LSB
(Rx[0])
CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,
CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0
Fig. 7.16.1.1 USI Timing
mw_ss_o
mw_sclk_o
mw_so_o
LSB
(Tx[0])
Tx[1]
Tx[2]
Tx[3]
Tx[4]
Tx[5]
Tx[6]
MSB
(Tx[7])
mw_si_i
LSB
(Rx[0])
Rx[1]
Rx[2]
Rx[3]
Rx[4]
Rx[5]
Rx[6]
MSB
(Rx[7])
CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,
CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0
Fig. 7.16.1.2 Alternate Phase SCLK Clock Timing
- 357 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.15.2 USI Registers Map
R: read only, W: write only, R/W: both read and write
REGISTER
ADDRESS
R/W
DESCRIPTION
USI_CNTRL
0xFFF8_6200
R/W
Control and Status Register
0x0000_0004
USI_DIVIDER
0xFFF8_6204
R/W
Clock Divider Register
0x0000_0000
USI_SSR
0xFFF8_6208
R/W
Slave Select Register
0x0000_0000
Reserved
0xFFF8_620C
N/A
Reserved
USI_Rx0
0xFFF8_6210
R
Data Receive Register 0
0x0000_0000
USI_Rx1
0xFFF8_6214
R
Data Receive Register 1
0x0000_0000
USI_Rx2
0xFFF8_6218
R
Data Receive Register 2
0x0000_0000
USI_Rx3
0xFFF8_621C
R
Data Receive Register 3
0x0000_0000
USI_Tx0
0xFFF8_6210
W
Data Transmit Register 0
0x0000_0000
USI_Tx1
0xFFF8_6214
W
Data Transmit Register 1
0x0000_0000
USI_Tx2
0xFFF8_6218
W
Data Transmit Register 2
0x0000_0000
USI_Tx3
0xFFF8_621C
W
Data Transmit Register 3
0x0000_0000
NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last.
- 358 -
RESET VALUE
N/A
W90N745CD/W90N745CDG
USI_Control and Status Register (USI_CNTRL)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register
31
30
29
28
0x0000_0004
27
26
25
24
19
18
17
16
IE
IF
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
SLEEP
7
6
5
11
10
Reserved
LSB
3
2
1
0
Tx_NEG
Rx_NEG
GO_BUSY
4
Tx_BIT_LEN
BITS
Tx_NUM
DESCRIPTIONS
[31:18]
Reserved
[17]
IE
Interrupt Enable
0 = Disable USI Interrupt.
1 = Enable USI Interrupt.
IF
Interrupt Flag
0 = It indicates that the transfer dose not finish yet.
1 = It indicates that the transfer is done. The interrupt flag is set if it
was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
SLEEP
Suspend Interval
These four bits provide the configuration of suspend interval between
two successive transmit/receive in a transfer. The default value is 0x0.
When CNTRL [Tx_NUM] = 00, setting this field has no effect on
transfer. The desired interval is obtained according to the following
equation (from the last falling edge of current sclk to the first rising
edge of next sclk):
(CNTRL[SLEEP] + 2)*period of SCLK
SLEEP = 0x0 … 2 SCLK clock cycle
SLEEP = 0x1 … 3 SCLK clock cycle
……
SLEEP = 0xe … 16 SCLK clock cycle
SLEEP = 0xf … 17 SCLK clock cycle
[16]
[15:12]
Reserved
- 359 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued
BITS
[11]
DESCRIPTIONS
Reserved
Reserved
LSB
Send LSB First
0 = The MSB is transmitted/received first (which bit in TxX/RxX
register that is depends on the Tx_BIT_LEN field in the CNTRL
register).
1 = The LSB is sent first on the line (bit TxX[0]), and the first bit
received from the line will be put in the LSB position in the Rx register
(bit RxX[0]).
Tx_NUM
Transmit/Receive Numbers
This field specifies how many transmit/receive numbers should be
executed in one transfer.
00 = Only one transmit/receive will be executed in one transfer.
01 = Two successive transmit/receive will be executed in one transfer.
10 = Three successive transmit/receive will be executed in one
transfer.
11 = Four successive transmit/receive will be executed in one transfer.
Tx_BIT_LEN
Transmit Bit Length
This field specifies how many bits are transmitted in one
transmit/receive. Up to 32 bits can be transmitted.
Tx_BIT_LEN = 0x01 … 1 bit
Tx_BIT_LEN = 0x02 … 2 bits
……
Tx_BIT_LEN = 0x1f … 31 bits
Tx_BIT_LEN = 0x00 … 32 bits
[2]
Tx_NEG
Transmit On Negative Edge
0 = The mw_so_o signal is changed on the rising edge of mw_sclk_o.
1 = The mw_so_o signal is changed on the falling edge of
mw_sclk_o.
[1]
Rx_NEG
Receive On Negative Edge
0 = The mw_si_i signal is latched on the rising edge of mw_sclk_o.
1 = The mw_si_i signal is latched on the falling edge of mw_sclk_o.
[10]
[9:8]
[7:3]
[0]
GO_BUSY
Go and Busy Status
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit starts the transfer. This bit remains set during
the transfer and is automatically cleared after transfer finished.
NOTE: All registers should be set before writing 1 to the GO_BUSY bit
in the CNTRL register. When a transfer is in progress, writing to any
register of the USI(Microwire/SPI) master core has no effect.
- 360 -
W90N745CD/W90N745CDG
USI Divider Register (USI_DIVIDER)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register
31
30
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
DIVIDER[15:8]
7
6
5
4
3
DIVIDER[7:0]
BITS
DESCRIPTIONS
Clock Divider Register
The value in this field is the frequency divider of the system clock pclk
to generate the serial clock on the output mw_sclk_o. The desired
frequency is obtained according to the following equation:
[15:0]
DIVIDER
f sclk =
f pclk
(DIVIDER + 1)* 2
NOTE: Suggest DIVIDER should be at least 1.
- 361 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USI Slave Select Register (USI_SSR)
REGISTER
USI_SSR
31
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF8_6208 R/W USI Slave Select Register
30
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ASS
SS_LVL
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Reserved
BITS
[3]
[2]
SSR[1:0]
DESCRIPTIONS
ASS
SS_LVL
Automatic Slave Select
0 = If this bit is cleared, slave select signals are asserted and deasserted by setting and clearing related bits in SSR register.
1 = If this bit is set, mw_ss_o signals are generated automatically. It
means that device/slave select signal, which is set in SSR register is
asserted by the USI controller when transmit/receive is started by
setting CNTRL[GO_BUSY], and is de-asserted after every
transmit/receive is finished.
Slave Select Active Level
It defines the active level of device/slave select signal (mw_ss_o).
0 = The mw_ss_o slave select signal is active Low.
1 = The mw_ss_o slave select signal is active High.
Slave Select Register
[1:0]
SSR
If SSR[ASS] bit is cleared, writing 1 to any bit location of this field sets
the proper mw_ss_o line to an active state and writing 0 sets the line
back to inactive state.
If SSR[ASS] bit is set, writing 1 to any bit location of this field will select
appropriate mw_ss_o line to be automatically driven to active state for
the duration of the transmit/receive, and will be driven to inactive state
for the rest of the time. (The active level of mw_ss_o is specified in
SSR[SS_LVL]).
NOTE: This interface can only drive one device/slave at a given time.
Therefore, the slave select of the selected device must be set to its
active level before starting any read or write transfer.
- 362 -
W90N745CD/W90N745CDG
USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3)
REGISTER
ADDRESS
R/W
USI_RX0
0xFFF8_6210
R
USI Data Receive Register 0
0x0000_0000
USI_RX1
0xFFF8_6214
R
USI Data Receive Register 1
0x0000_0000
USI_RX2
0xFFF8_6218
R
USI Data Receive Register 2
0x0000_0000
USI_RX3
0xFFF8_621C
R
USI Data Receive Register 3
0x0000_0000
31
30
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Rx [31:24]
23
22
21
20
Rx [23:16]
15
14
13
12
Rx [15:8]
7
6
5
4
Rx [7:0]
BITS
DESCRIPTIONS
Data Receive Register
[31:0]
Rx
The Data Receive Registers hold the value of received data of the last
executed transfer. Valid bits depend on the transmit bit length field in the
CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and
CNTRL[Tx_NUM] is set to 0x0, bit Rx0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers. A Write to
these registers will actually modify the Data Transmit Registers because
those registers share the same FFs.
- 363 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Data Transmit Register 0/1/2/3 (Tx0/1/2/3)
REGISTER
ADDRESS
R/W
USI_TX0
0xFFF8_6210
W
USI Data Transmit Register 0
0x0000_0000
USI_TX1
0xFFF8_6214
W
USI Data Transmit Register 1
0x0000_0000
USI_TX2
0xFFF8_6218
W
USI Data Transmit Register 2
0x0000_0000
USI_TX3
0xFFF8_621C
W
USI Data Transmit Register 3
0x0000_0000
31
30
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Tx [31:24]
23
22
21
20
Tx [23:16]
15
14
13
12
Tx [15:8]
7
6
5
4
Tx [7:0]
BITS
DESCRIPTIONS
Data Transmit Register
[31:0]
Tx
The Data Transmit Registers hold the data to be transmitted in the next
transfer. Valid bits depend on the transmit bit length field in the CNTRL
register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and the
CNTRL[Tx_NUM] is set to 0x0, the bit Tx0[7:0] will be transmitted in next
transfer. If CNTRL[Tx_BIT_LEN] is set to 0x00 and CNTRL[Tx_NUM] is
set to 0x3, the core will perform four 32-bit transmit/receive successive
using the same setting (the order is Tx0[31:0], Tx1[31:0], Tx2[31:0],
Tx3[31:0]).
NOTE: The RxX and TxX registers share the same flip-flops, which
means that what is received from the input data line in one transfer will
be transmitted on the output data line in the next transfer if no write
access to the TxX register is executed between the transfers.
- 364 -
W90N745CD/W90N745CDG
7.16 PWM
The W90N745 have 4 channels PWM timers. They can be divided into two groups. Each group has 1
Prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 Dead-Zone
generator. They are all driven by PCLK (80 MHz). Each channel can be used as a timer and issue
interrupt independently.
Two channels PWM timers in one group share the same prescaler. Clock divider provides each
channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock signal from
clock divider which receives clock from 8-bit prescaler. The 16-bit counter in each channel receive
clock signal from clock selector and can be used to handle one PWM period. The 16-bit comparator
compares number in counter with threshold number in register loaded previously to generate PWM
duty cycle.
The clock signal from clock divider is called PWM clock. Dead-Zone generator utilize PWM clock as
clock source. Once Dead-Zone generator is enabled, output of two PWM timer in one group is
blocked. Two output pin are all used as Dead-Zone generator output signal to control off-chip power
device.
To prevent PWM driving output pin with unsteady waveform, 16-bit counter and 16-bit comparator are
implemented with double buffering feature. User can feel free to write data to counter buffer register
and comparator buffer register without generating glitch.
When 16-bit down counter reaches zero, the interrupt request is generated to inform CPU that time is
up. When counter reaches zero, if counter is set as toggle mode, it is reloaded automatically and start
to generate next cycle. User can set counter as one-shot mode instead of toggle mode. If counter is
set as one-shot mode, counter will stop and generate one interrupt request when it reaches zero.
The value of comparator is used for pulse width modulation. The counter control logic changes the
output level when down-counter value matches the value of compare register.
The PWM timer features are shown as below:
z
Two 8-bit prescalers and two clock dividers
z
Four clock selectors
z
Four 16-bit counters and four 16-bit comparators
z
Two Dead-Zone generator
- 365 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.16.1 PWM Double Buffering and Reload Automatically
W90N745 PWM Timers have a double buffering function, enabling the reload value changed for next
timer operation without stopping current timer operation. Although new timer value is set, current timer
operation still operate successfully.
The counter value can be written into PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 and
current counter value can be read from PWM_PDR0, PWM_PDR1, PWM_PDR2, PWM_PDR3.
The auto-reload operation copies from PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 to
down-counter when down-counter reaches zero. If PWM_CNR0~3 are set as zero, counter will be halt
when counter count to zero. If auto-reload bit is set as zero, counter will be stopped immediately.
7.16.2 Modulate Duty Ratio
The double buffering function allows CMR written at any point in current cycle. The loaded value will
take effect from next cycle.
- 366 -
W90N745CD/W90N745CDG
7.16.3 Dead Zone Generator
W90N745 PWM is implemented with Dead Zone generator. They are built for power device protection.
This function enables generation of a programmable time gap at the rising of PWM output waveform.
User can program PWM_PPR [31:24] and PWM_PPR [23:16] to determine the Dead Zone interval.
Dead zone generator operation
PWM_out1
PWM_out1_n
PWM_out1_DZ
PWM_out1_n_DZ
Dead zone interval
7.16.4 PWM Timer Start Procedure
1. Setup clock selector (PWM_CSR)
2. Setup prescaler & dead zone interval (PWM_PPR)
3. Setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and PWM timer
off. (PWM_PCR)
4. Setup comparator register (PWM_CMR)
5. Setup counter register (PWM_CNR)
6. Setup interrupt enable register (PWM_PIER)
7. Enable PWM timer (PWM_PCR)
7.16.5 PWM Timer Stop Procedure
Method 1 : Set 16-bit down counter(PWM_CNR) as 0, and monitor PWM_PDR. When PWM_PDR
reaches to 0, disable PWM timer (PWM_PCR). (Recommended)
Method 2 : Set 16-bit down counter(PWM_CNR) as 0. When interrupt request happen, disable PWM
timer (PWM_PCR). (Recommended)
Method 3 : Disable PWM timer directly (PWM_PCR). (Not recommended)
- 367 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.16.6 PWM Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
PWM_PPR
0xFFF8_7000
R/W
PWM Prescaler Register
0x0000_0000
PWM_CSR
0xFFF8_7004
R/W
PWM Clock Select Register
0x0000_0000
PWM_PCR
0xFFF8_7008
R/W
PWM Control Register
0x0000_0000
PWM_CNR0
0xFFF8_700C
R/W
PWM Counter Register 0
0x0000_0000
PWM_CMR0
0xFFF8_7010
R/W
PWM Comparator Register 0
0x0000_0000
PWM_PDR0
0xFFF8_7014
R
PWM Data Register 0
0x0000_0000
PWM_CNR1
0xFFF8_7018
R/W
PWM Counter Register 1
0x0000_0000
PWM_CMR1
0xFFF8_701C
R/W
PWM Comparator Register 1
0x0000_0000
PWM_PDR1
0xFFF8_7020
R
PWM Data Register 1
0x0000_0000
PWM_CNR2
0xFFF8_7024
R/W
PWM Counter Register 2
0x0000_0000
PWM_CMR2
0xFFF8_7028
R/W
PWM Comparator Register 2
0x0000_0000
PWM_PDR2
0xFFF8_702C
R
PWM Data Register 2
0x0000_0000
PWM_CNR3
0xFFF8_7030
R/W
PWM Counter Register 3
0x0000_0000
PWM_CMR3
0xFFF8_7034
R/W
PWM Comparator Register 3
0x0000_0000
PWM_PDR3
0xFFF8_7038
R
PWM Data Register 3
0x0000_0000
PWM_PIER
0xFFF8_703C
R/W
PWM Interrupt Enable Register
0x0000_0000
PWM_PIIR
0xFFF8_7040
R/C
PWM Interrupt Indication Register
0x0000_0000
- 368 -
RESET VALUE
W90N745CD/W90N745CDG
PWM Prescaler Register (PWM_PPR)
REGISTER
ADDRESS
PWM_PPR
0xFFF8_7000
31
30
R/W
DESCRIPTION
RESET VALUE
R/W PWM Prescaler Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
DZI1
23
22
21
20
DZI0
15
14
13
12
CP1
7
6
5
4
CP0
BITS
[31:24]
DESCRIPTIONS
DZI1
DZI1: Dead zone interval register 1, these 8-bit determine dead zone
length.
The 1 unit time of dead zone length is received from clock selector 2.
[23:16]
DZI0
DZI0: Dead zone interval register 0, these 8-bit determine dead zone
length.
The 1 unit time of dead zone length is received from clock selector 0.
CP1 : Clock prescaler 1 for PWM Timer channel 2 & 3
[15:8]
CP1
Clock input is divided by (CP1 + 1) before it is fed to the counter. 2 & 3
If CP1=0, then the prescaler 1 output clock will be stopped.
CP0 : Clock prescaler 0 for PWM Timer channel 0 & 1
[7:0]
CP0
Clock input is divided by (CP0 + 1) before it is fed to the counter. 0 & 1
If CP0=0, then the prescaler 0 output clock will be stopped.
- 369 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PWM Clock Select Register (PWM_CSR)
REGISTER
ADDRESS
PWM_CSR
0xFFF8_7004
31
30
R/W
DESCRIPTION
RESET VALUE
R/W PWM Clock Select Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
Reserved
13
12
CSR3
7
6
Reserved
5
CSR1
BITS
Reserved
4
CSR2
3
2
Reserved
CSR0
DESCRIPTIONS
[14:12]
CSR3
Select clock input for channel 3
[10:8]
CSR2
Select clock input for channel 2.
[6:4]
CSR1
Select clock input for channel 1
[2:0]
CSR0
Select clock input for channel 0
CSR3
INPUT CLOCK DIVIDED BY
000
2
001
4
010
8
011
16
100
1
- 370 -
1
0
W90N745CD/W90N745CDG
PWM Control Register (PWM_PCR)
REGISTER
ADDRESS
PWM_PCR
0xFFF8_7008
31
30
R/W
DESCRIPTION
RESET VALUE
R/W PWM Control Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
PCR19
PCR18
PCR17
PCR16
Reserved
23
22
21
20
Reserved
15
14
13
12
11
10
9
8
PCR15
PCR14
PCR13
PCR12
PCR11
PCR10
PCR09
PCR08
7
6
5
4
3
2
1
0
PCR07
PCR06
PCR05
PCR04
PCR03
PCR02
PCR01
PCR00
BITS
DESCRIPTIONS
Channel 3 toggle/one shot mode
[19]
PCR 19
1 = toggle mode
0 = one shot mode
Channel 3 Inverter on/off
[18]
PCR 18
1 = inverter on
0 = inverter off
[17]
PCR 17
Reserved
Channel 3 enable/disable
[16]
PCR 16
1 = enable
0 = disable
Channel 2 toggle/one shot mode
[15]
PCR 15
1 = toggle mode
0 = one shot mode
Channel 2 Inverter on/off
[14]
PCR 14
1 = inverter on
0 = inverter off
[13]
PCR 13
Reserved
- 371 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
Channel 2 enable/disable
[12]
PCR 12
1 = enable
0 = disable
Channel 1 toggle/one shot mode
[11]
PCR 11
1 = toggle mode
0 = one shot mode
Channel 1 Inverter on/off
[10]
PCR 10
1 = inverter on
0 = inverter off
[09]
PCR 09
Reserved
Channel 1 enable/disable
[08]
PCR 08
1 = enable
0 = disable
[07]
PCR 07
Reserved
[06]
PCR 06
Reserved
Dead-Zone generator 1 enable/disable
[05]
PCR 05
1 = enable dead-zone generator
0 = disable dead-zone generator
Dead-Zone generator 0 enable/disable
[04]
PCR 04
1 = enable dead-zone generator
0 = disable dead-zone generator
Channel 0 toggle/one shot mode
[03]
PCR 03
1 = toggle mode
0 = one shot mode
Channel 0 Inverter on/off
[02]
PCR 02
1 = inverter on
0 = inverter off
[01]
PCR 01
Reserved
Channel 0 enable/disable
[00]
PCR 00
1 = enable
0 = disable
- 372 -
W90N745CD/W90N745CDG
PWM Counter Register 0/1/2/3 (PWM_CNR0/1/2/3)
REGISTER
ADDRESS
PWM_CNR0
0xFFF8_700C
R/W PWM Counter Register 0
0x0000_0000
PWM_CNR1
0xFFF8_7018
R/W PWM Counter Register 1
0x0000_0000
PWM_CNR2
0xFFF8_7024
R/W PWM Counter Register 2
0x0000_0000
PWM_CNR3
0xFFF8_7030
R/W PWM Counter Register 3
0x0000_0000
31
30
R/W
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
11
10
9
8
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
CNRx[15:8]
7
6
5
4
3
CNRx[7:0]
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
CNRx
CNR: PWM counter/timer buffer. Inserted data range: 65535~0. Unit:
1 PWM clock cycle
Note 1: One PWM counter countdown interval = CNR + 1.If CNR is
loaded as
zero, PWM counter will be stopped.
Note 2: Programmer can feel free to write data to CNR at any time,
and it will be reloaded when PWM counter reaches zero.
- 373 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PWM Comparator Register 0/1/2/3 (PWM_CMR0/1/2/3)
REGISTER
ADDRESS
PWM_CMR0
0xFFF8_7010
R/W PWM Comparator Register 0
0x0000_0000
PWM_CMR1
0xFFF8_701C
R/W PWM Comparator Register 1
0x0000_0000
PWM_CMR2
0xFFF8_7028
R/W PWM Comparator Register 2
0x0000_0000
PWM_CMR3
0xFFF8_7034
R/W PWM Comparator Register 3
0x0000_0000
31
30
R/W
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
11
10
9
8
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
CMRx[15:8]
7
6
5
4
3
CMRx[7:0]
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
CMRx
CMR: PWM comparator register
Inserted data range: 65535~0. CMR is used to determine PWM output
duty ratio.
Note 1: PWM duty = CMR + 1.If CMR is loaded as zero, PWM duty =
1
Note 2: Programmer can feel free to write data to CMR at any time,
and it will be reloaded when PWM counter reaches zero.
- 374 -
W90N745CD/W90N745CDG
PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3)
REGISTER
ADDRESS
R/W
PWM_PDR0
0xFFF8_7014
R
PWM Data Register 0
0x0000_0000
PWM_PDR1
0xFFF8_7020
R
PWM Data Register 1
0x0000_0000
PWM_PDR2
0xFFF8_702C
R
PWM Data Register 2
0x0000_0000
PWM_PDR3
0xFFF8_7038
R
PWM Data Register 3
0x0000_0000
31
30
29
DESCRIPTION
28
RESET VALUE
27
26
25
24
19
18
17
16
11
10
9
8
2
1
0
Reserved
23
22
21
20
Reserved
15
14
13
12
PDRx[15:8]
7
6
5
4
3
PDRx[7:0]
BITS
DESCRIPTIONS
[31:16]
Reserved
[15:0]
PDRx
PDR: PWM Data register. User can monitor PDR to get current value
in 16-bit down counter.
- 375 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PWM Interrupt Enable Register (PWM_PIER)
REGISTER
ADDRESS
PWM_PIER
0xFFF8_703C
31
R/W
30
DESCRIPTION
RESET VALUE
R/W PWM Interrupt Enable Register
29
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PIER3
PIER2
PIER1
PIER0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
Reserved
BITS
4
DESCRIPTIONS
[31:4]
Reserved
-
[3]
PIER3
Enable/Disable PWM counter channel 3 interrupt request
1 = enable
0 = disable
[2]
PIER2
Enable/Disable PWM counter channel 2 interrupt request
1 = enable
0 = disable
[1]
PIER1
Enable/Disable PWM counter channel 1 interrupt request
1 = enable
0 = disable
[0]
PIER0
Enable/Disable PWM counter channel 0 interrupt request
1 = enable
0 = disable
- 376 -
W90N745CD/W90N745CDG
PWM Interrupt Indication Register (PWM_PIIR)
REGISTER
ADDRESS
R/W/C
PWM_PIIR
0xFFF8_7040
R/C
31
30
29
DESCRIPTION
RESET VALUE
PWM Interrupt Indication Register
28
0x0000_0000
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PIIR3
PIIR2
PIIR1
PIIR0
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
Reserved
BITS
4
DESCRIPTIONS
[3]
PIIR3
PWM counter channel 3 interrupt flag
[2]
PIIR2
PWM counter channel 2 interrupt flag
[1]
PIIR1
PWM counter channel 1 interrupt flag
[0]
PIIR0
PWM counter channel 0 interrupt flag
Note: User can clear each interrupt flag by writing a zero to corresponding bit in PIIR
- 377 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.17 Keypad Interface
W90N745 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input.
KPI scans an array up to 16x8 with an external 4 to 16 decoder. It can also be programmed to scan
8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the
scan signals are dived by W90N745 itself. For minimum pin counts application, an auxiliary priority
encoder (TTL 74148) can be used to encode 8 columns input to 3 binary code and one indicator flag.
Total 8 pins are required to implement 16x8 key scan.
Any 1 or 2 keys in the array that pressed are debounced and encoded. The keypad controller scan
key matrix from ROW0 COL 0 Æ 1 Æ 2 …. Æ 7, ROW1 COL 0 Æ 1 Æ 2 … Æ 7 till to ROW 16 (or
ROW 8 or ROW 4) COL 0 Æ 0 Æ 1 …. Æ 7. If more than 2 keys are pressed, only the keys or
apparent keys in the array with the lowest address will be decoded.
KPI also supports 2-keys scan interrupt and specified 3-keys interrupt or chip reset. If the 3 pressed
keys matches with the 3 keys defined in KPI3KCONF, it will generate an interrupt or chip reset to
nWDOG reset output depend on the ENRST setting. The interrupt is generated whenever the scanner
detects a key is pressed. The interrupt conditions are 1 key, 2 keys and 3keys.
W90N745 provides one keypad connecting interface. The interface is in Ethernet RMII PHY interface
and I2C interface 2 SDA1, SCL1 (GPIO18-27). Software should set KPSEL bit to “0” in KPICONF
register to select MAC PHY interface for connecting keypad matrix.
The keypad interface has the following features:
z
maximum 16x8 array
z
programmable debounce time
z
low-power wakeup mode
z
programmable three-key reset
- 378 -
W90N745CD/W90N745CDG
Fig. 7.18.1 W90N745 Keypad Interface
7.17.1 Keypad Interface Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
KPICONF
0xFFF8_8000
R/W
Keypad Controller
Register
KPI3KCONF
0xFFF8_8004
R/W
Keypad
Controller
Configuration Register
3-keys
KPILPCONF
0xFFF8_8008
R/W
Keypad Controller Low
Configuration Register
Power
KPISTATUS
0xFFF8_800C
R/O
Keypad Controller Status Register
- 379 -
RESET VALUE
Configuration
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.17.2 Register Description
Keypad Controller Configuration Register (KPI_CONF)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
KPICONF
0xFFF8_8000
R/O
key pad configuration register
0x0000_0000
31
30
29
28
27
26
25
24
17
16
RESERVED
23
22
RESERVED
15
21
20
19
18
ENCODE
ODEN
KPSEL
ENKP
13
12
11
10
9
8
3
2
1
0
14
KSIZE
DBTC
7
6
5
4
PRESCALE
BITS
[31:22]
DESCRIPTION
RESERVED
Enable Encode Function
[21]
ENCODE
If an auxiliary 8 to 3 encoder is used to minimize keypad interface
pin counts, user can connect encoder data to KPI_COL[2:0] and
indicator flag (low active) to KPI_COL[3].
1 = enable encoder function
0 = default. (8 column inputs)
Open Drain Enable
[20]
ODEN
If there are more than one key are pressed in the same column, then
“short-circuit” will appear between active scan and inactive scan row.
Software can set this bit HIGH to enable scan output KPI_ROW[3:0]
pins work as “open-drain” to avoid the “short-circuit”.
1 = Open drain
0 = push-pull driver
Key pad select
[19]
KPSEL
Software should set this bit to “0” to select MAC PHY interface for
connecting keypad matrix.
0 = pin #53~55, #57~60, #62~65 #19 and #20 are used as keypad
interface
- 380 -
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTION
Key pad scan enable
[18]
ENKP
Setting this bit high enable the key scan function.
1 = enable key pad scan
0 = disable key pad scan
Key array size
[17:16]
KSIZE
KSIZE
Key array size
2’b00
4x8, 3x8, 2x8, 1x8
2’b01
8x8, 7x8, 6x8, 5x8
2’b1x
16x8, 15x8, 14x8, 13x8, 12x8, 11x8, 10x8, 9x8
Debounce terminal count
[15:8]
DBTC
Debounce counter counts the number of consecutive scans that
decoded the same keys. When de-bounce counter counter is equal
to terminal count it will generate a key scan interrupt.
Row scan cycle pre-scale value
This value is used to prescale row scan cycle. The prescale counter
is clocked by 0.9375MHz clock.
Key array scan time = 1.067us x PRESCALE x16 ROWS
[7:0]
PRESCALE
The following example is the scan time for PRESCALE = 0xFA
Tscan_time = 1.067us x 250 x16 = 4.268ms
If debounce terminal count = 0x05, key detection interrupt is fired in
approximately 21.34ms. The array scan time can range from
17.07us to 1.118 sec.
- 381 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Fig. 7.18.1 Keypad Interface with row decoder and column encoder
Keypad Controller 3-keys Configuration Register (KPI3KCONF)
REGISTER
ADDRESS
R/W
KPI3KCONF
0xFFF8_8004
W/R
31
30
29
DESCRIPTION
three-key
register
28
27
configuration
26
RESERVED
23
22
21
RESERVED
15
RESERVED
19
18
K32R
14
13
RESERVED
7
20
12
5
0x0000_0000
25
24
EN3KY
ENRST
17
16
K32C
11
10
K31R
6
RESET VALUE
9
8
K31C
4
3
K30R
2
1
K30C
- 382 -
0
W90N745CD/W90N745CDG
BITS
DESCRIPTION
[31:26]
RESERVED
[25]
EN3KY
Enable three-keys detection
Setting this bit enables hardware to detect 3 keys specified by
software
Enable three-key reset
Setting this bit enable hardware reset when three-key is detected.
[24]
[23]
ENRST
RESERVED
EN3KY
ENRST
Function
0
X
three-key function is disable
1
0
generate three-key interrupt
1
1
hardware reset by three-key-reset
The #2 key row address
[22:19]
K32R
The #2 means the row address and the column address is the highest
of the specified 3-kyes.
[18:16]
K32C
The #2 key column address
[15]
RESERVED
The #1 key row address
[14:11]
K31R
The #1 means the row address and the column address is the 2nd of
the specified 3-kyes.
[10:8]
K31C
The #1 key column address
[7]
RESERVED
The #0 key row address
[6:3]
K30R
The #0 means the row address and the column address is the
lowest of the specified 3-kyes.
[2:0]
K30C
The #0 key column address
Application Note: Due to hardware scan from {row[0], col[0]}, {row[0], col[1]}, …, to {row[15], col[7]}
the {K30R,K30C} should be filled the lowest address of the three-keys. For example, if {2,0} {4,6},
{1,3} keys are defined as three-keys. Software should set {K30R, K30C} = {1, 3}, {K31R, K31C} = {2,
0} and {K32R, K32C} = {4, 6}.
- 383 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
KeyPad Interface Low Power Mode Configuration Register (KPILPCONF)
REGISTER
ADDRESS
R/W
KPILPCOF
0xFFF8_8008
W/R
31
30
29
DESCRIPTION
RESET VALUE
Low power configuration register
28
27
0x0000_0000
26
25
24
18
17
16
RESERVED
23
22
21
20
19
WAKE
15
14
13
12
11
10
9
8
3
2
1
0
LPWCEN
7
6
5
4
RESERVED
LPWR
BITS
[31:17]
DESCRIPTION
RESERVED
Lower power wakeup enable
[16]
WAKE
Setting this bit enables low power wakeup
1 = wakeup enable
0 = not enable
Low power wakeup column enable
[15:8]
LPWCEN
[7:4]
RESERVED
Specify columns for low power wakeup. For example, if user wants to
use keys in row N and column 0, 2, 5 to wake up W90N745, then the
LPWCEN should be fill 8’b00100101.
Low power wakeup row address
[3:0]
LPWR
Define the row address keys used to wakeup. For 16x8 or 8x8 (with
4:16 or 3:8 decoder) keypad key configuration, LPWR means “Hex”
code but for 4x8 (without decoder), LPWR means “binary” code. For
example, if user wants to use all keys on row 3 of 16x8 keypad to
wakeup W90N745, then 0x3 should be fill into this register but for 4x8
keypad it should be filled as 4’b1000.
- 384 -
W90N745CD/W90N745CDG
Key Pad Interface Status Register (KPISTATUS)
REGISTER
ADDRESS
R/W
KPISTATUS
0xFFF8_800C
R/O
31
30
29
DESCRIPTION
key pad status register
28
RESET VALUE
0x0000_0000
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
INT
3 K R S T
PDWAKE
3KEY
2KEY
1KEY
15
13
12
11
10
9
8
14
RESERVED
7
KEY1R
6
5
RESERVED
4
3
KEY0R
BITS
[31:22]
KEY1C
2
1
0
KEY0C
DESCRIPTION
RESERVED
Key interrupt
[21]
INT
This bit indicates the key scan interrupt is active and that one or two
keys have changed status. The interrupt also occur when the three
specified keys are detected if ENRST bit in KPI3KFCON is cleared.
It will be cleared by hardware automatically when software read
KPISTATUS register.
3-Keys reset flag
This bit is a record flag for software reference, it will be set after 3keys reset occur.
[20]
3KRST
1 = 3 keys reset
0 = not reset.
This bit is cleared while it is read.
Power Down Wakeup flag
[19]
PDWAKE
This flag indicates the chip is wakeup from power down by keypad
1 =wakeup up by keypad
0 = not wakeup
Specified three-key is detected.
[18]
3KEY
This flag indicates specified-three-keys was detected. Software can
read this bit to know the keypad interrupt is 3 key or not.
- 385 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTION
Double-key press
[17]
2KEY
This bit indicates that 2 keys have been detected. Software can read
{KEY1R, KEY1C} and {KEY0R, KEY0C} to know which two keys are
pressed.
Single-key press
[16]
1KEY
[15]
RESERVED
This bit indicates that 1 key has been detected. Software can read
{KEY0R, KEY0C} to know which key is pressed.
KEY1 row address
[14:11]
KEY1R
[10:8]
KEY1C
[7]
RESERVED
This value indicates key1 row address. The keypad controller scan
keypad matrix from row 0, column0 Æ1 Æ2 …. Æ 7 and then row1
column 0 Æ 1 Æ 2 Æ7 so the lowest key address will be stored in
{KEY0R, KEY0C}. This register stores the 2nd address, if more than one
key is pressed.
KEY1 column address
This value indicates key1 column address..
KEY1 row address
[6:3]
KEY0R
[2:0]
KEY0C
This value indicates key0 row address. This value indicates key0 row
address. This value indicates key1 row address. The keypad controller
scan keypad matrix from row 0, column0 Æ1 Æ2 …. Æ 7 and then
row1 col 0 Æ 1 Æ 2 Æ …Æ 7 still to row16 (or 8, or 4) column 0 Æ 1 Æ
2 ….. Æ 7 so the lowest key address will be stored in {KEY0R,
KEY0C}.
KEY1 column address
This value indicates key0 row address.
- 386 -
W90N745CD/W90N745CDG
7.18 PS2 Host Interface Controller
W90N745 PS2 host controller interface is an APB slave consisted of PS2 protocol. It is used to
connect to your IBM keyboard or other device through PS2 interface. For example, the IBM keyboard
will sends scan codes to the host controller, and the scan codes will tell your Keyboard Bios what
keys you have pressed or released. Besides Scan codes, commands can also be sent to the
keyboard from host. The most common commands would be the setting/resetting of the status
indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs).
The PS2 interface implements a bi-directional protocol. The keyboard can send data to the Host and
the Host can send data to the Keyboard using two PS2 Clock and PS2 Data lines. Both the PS2
Clock and Data lines are Open Collector bi-directional I/O lines. The Host has the ultimate priority
over direction. The keyboard is free to send data to the host when both the PS2 Data and PS2 Clock
lines are high (Idle). If the host takes the PS2 Clock line low, the keyboard will buffer any data until
the PS2 Clock is released, ie goes high. The transmission of data in the forward direction, ie
Keyboard to Host is done with a frame of 11 bits. The first bit is a Start Bit (Logic 0) followed by 8 data
bits (LSB First), one Parity Bit (Odd Parity) and a Stop Bit (Logic 1). Each bit should be read on the
falling edge of the clock. The Keyboard will generate the clock. The frequency of the clock signal
typically ranges from 20 to 30 KHz.
The Host to Keyboard Protocol is initiated by taking the PS2 data line low. It is common to take the
PS2 Clock line low for more than 60us and then the KBD data line is taken low, while the KBD clock
line is released. After that, the keyboard will start generating a clock signal on its PS2 clock line. After
the first falling edge has been detected, host will load the first data bit on the PS2 Data line. This bit
will be read into the keyboard on the next falling edge, after which host place the next bit of data. This
process is repeated for the 8 data bits. It will follow an Odd Parity Bit after the data byte.
- 387 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
7.18.1 PS2 Host Controller Interface Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
PS2CMD
0xFFF8_9000
R/W
PS2 Host Controller Command Register
0x0000_0000
PS2STS
0xFFF8_9004
R/W
PS2 Host Controller Status Register
0x0000_0000
PS2SCANCODE 0xFFF8_9008
RO
PS2 Host Controller RX Scan Code
0x0000_0000
Register
PS2ASCII
RO
PS2 Host Controller RX ASCII Code
0x0000_0000
Register
0xFFF8_900C
- 388 -
W90N745CD/W90N745CDG
7.18.2 Register Description
PS2 Host Controller Command Register (PS2_CMD)
REGISTER
PS2CMD
31
ADDRESS
R/W
0xFFF8_900
0
30
DESCRIPTION
R/W
29
RESET VALUE
Command register
28
0x0000_0000
27
26
25
24
18
17
16
10
9
8
TRAP_SHIFT
EnCMD
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
2
PS2CMD
BITS
[31:10]
DESCRIPTIONS
RESERVED
Trap Shift Key Output to Scan Code Register
[9]
TRAP_SHIFT
If the shift key scan code (0x12 0r 0x59) is received by host,
software can indicate host whether to update to scan code
register or not. No ASCII or SCAN codes will be reported for the
shift keys if this bit is set. In this condition, host will only report the
shift keys at the RX_shift_key bit of Status register and no
interrupt will occur for the shift keys. This is useful for those who
wish to use the ASCII data stream and don’t want to “manually”
filter out the shift key codes. This bit is clear by default.
Enable write PS2 Host Controller Commands
[8]
EnCMD
This bit enables the write function of Host controller comm
device. Set this bit will start the write process of PS2CMD cont
hardware will automatically clear this bit while write pro
finished.
PS2 Host Controller Commands
[7:0]
PS2CMD
This command filed is sent by the Host to the Keyboard. Th
common command would be the setting/resetting of the
Indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs).
- 389 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PS2 Host Controller Status Register (PS2_STS)
REGISTER
ADDRESS
PS2STS
31
0xFFF8_9004
30
R/W
DESCRIPTION
R/W
29
RESET VALUE
Status register
28
0x0000_0000
27
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
RESERVED
5
4
3
TX_err
TX_IRQ
BITS
[31:6]
RESERVED
RX_IRQ
DESCRIPTIONS
RESERVED
This Transmit Error Status bit indicates software that device
doesn’t response ACK after Host wrote a command to it.
[5]
[4]
TX_err
TX_IRQ
This bit is valid when TX_IRQ is asserted. It will automatically
reset after software starts next command writing process.
This bit is read only.
This Transmit Complete Interrupt bit indicates software that
the process of Host controller writing command to device is
finished. Software needs to write one to this bit to clear this
interrupt.
[3:1]
Reserved
[0]
This Receive Interrupt bit indicates software that Host
controller receives one byte data from device. This data is
stored at PS2_SCANCODE register. Software needs to write
one to this bit to clear this interrupt after reading receiving
data in RX_SCAN_CODE register. Note that the reception of
the Extend (0xE0) and Release (0xF0) scan code will not
cause an interrupt by host. The case of the shift key codes
will be determined by the TRAP_SHIFT bit of PS2_CMD
register.
RX_IRQ
- 390 -
W90N745CD/W90N745CDG
PS2 Host Controller RX Scan Code Register (PS2_SCANCODE)
REGISTER
ADDRESS
R/W
PS2SCANCODE
0xFFFF_900
8
R/W
31
30
29
DESCRIPTION
RESET VALUE
PS2 Host RX Scan Code Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RX_shift_key
RESERVED
7
6
5
4
3
2
RX_releaseRX_extend
1
0
RX_SCAN_CODE
BITS
DESCRIPTIONS
[31:11]
RESERVED
-
[10]
RX_shift_key
This Receive Shift Key bit indicates that left or right shift key on
the keyboard is hold. This bit is read only and will clear by host
when the release shift key codes are received.
RX_release
Receive Released Byte
When one key has been released, the keyboard will send F0
(hex) to inform Host controller. This bit indicates software that
Host controller receives release byte (F0). This bit is read only
and will update when host has received next data byte.
RX_extend
Receive Extend Byte
A handful of the keys on keyboard are extended keys and thus
require two more scan code. These keys are preceded by an
E0 (hex). This bit indicates software that Host controller
receives extended byte (E0). This bit is read only and will
update when host has received next data byte.
RX_SCAN_CODE
PS2 Host Controller Received Data Field
This field stores the original data content transmitted from
device. This filed is valid when RX_IRQ is asserted. Note that
host will not report “Extend” or “Release” scan code to this field
and not generate interrupt if they are received by host, i.e.
0xE0 and 0xF0. The case of the shift key codes will be
determined by the TRAP_SHIFT bit of PS2_CMD register.
[9]
[8]
[7:0]
- 391 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
PS2 Host Controller RX ASCII Code Register (PS2_ASCII)
REGISTER
ADDRESS
R/W
PS2ASCII
0xFFF8_900C
R/W
31
30
29
DESCRIPTION
RESET VALUE
PS2 Host RX ASCII Code Register
28
27
0x0000_0000
26
25
24
18
17
16
10
9
8
2
1
0
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RX_ASCII_CODE
BITS
[31:8]
DESCRIPTIONS
RESERVED
PS2 Host Controller Received Data Filed
[7:0]
RX_ASCII_CODE
This field stores the ASCII data content transmitted from device.
Therefore, this part translates the scan code into an ASCII
value. It will be read as 0x2E when there is no ASCII code
mapped to the scan code stored in RX_SCAN_CODE register.
This filed is valid when RX_IRQ is asserted.
- 392 -
W90N745CD/W90N745CDG
8. ELECTRICAL SPECIFICATIONS
8.1
Absolute Maximum Ratings
Ambient
temperature .................................…………….............................
-40 °C ~ +85°C
Storage
temperature ..................................................……....................
-40 °C ~ +125°C
Voltage on any
pin ...............................................................……..........
-0.5V ~ 6V
Power supply voltage (Core
logic) ..............................…...........………..…..
-0.5V ~ 1.92V
Power supply voltage (IO
Buffer) ...............................…...........………..…..
-0.5V ~ 3.6V
Injection current (latch-up
testing) ..............................................………..
100mA
Crystal
Frequency ...............................................…...........………..………
…
4MHz ~ 30MHz
8.2
DC Specifications
8.2.1
Digital DC Characteristics
(Normal test conditions: VDD33/USBVDD = 3.3V+/- 0.3V, VDD18/DVDD18/AVDD18 =
1.8V+/- 0.18V
TA = -40 °C ~ +85 °C
SYMBOL
unless otherwise specified)
MIN.
MAX.
UNIT
Power Supply
3.00
3.60
V
Power Supply
1.62
1.98
V
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
5.5
V
1.47
1.5
V
0.89
0.95
V
-
0.4
V
VDD33/
USBVDD
VDD18/
DVDD18/
AVDD18
VT+
VTVOL
PARAMETER
Schmitt
Trigger
threshold
Schmitt trigger
threshold
CONDITION
positive-going
negative-going
Depend
driving
Output Low Voltage
- 393 -
on
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
VOH
Depend
driving
Output High Voltage
- 394 -
on
2.4
-
V
W90N745CD/W90N745CDG
Continued.
SYMBOL
PARAMETER
CONDITION
MIN.
MAX.
UNIT
ICC1
1.8V Supply Current
FCPU = 80MHz
-
150
mA
ICC2
3.3V Supply Current
FCPU = 80MHz
-
60
mA
ICCRTC
RTC 1.8V Supply Current
FRTC
32.768KHZ
-
7
uA
IIH
Input High Current
VIN = 2.4 V
-1
1
μA
IIL
Input Low Current
VIN = 0.4 V
-1
1
μA
IIHP
Input High Current (pull-up)
VIN = 2.4 V
-15
-10
μA
IILP
Input Low Current (pull-up)
VIN = 0.4 V
-55
-25
μA
IIHD
Input High Current (pull-down)
VIN = 2.4 V
25
60
μA
IILD
Input Low Current (pull-down)
VIN = 0.4 V
5
10
μA
=
Table 8.2.1TSMC IO DC Characteristics
PARAMETER
MIN.
TYP.
MAX.
VIL
Input Low Voltage
-0.3V
0.8V
V IH
Input High Voltage
2V
5.5V
VT
Threshold point
1.46V
1.59V
1.75V
VT+
Schmitt trig low to high threshold point
1.47V
1.50V
1.50V
VT-
Schmitt trig, high to low threshold point
0.90V
0.94V
0.96V
II
Input leakage current @VI= 3.3V or 0V
+/- 10uA
Ioz
Tri-state output leakage current @Vo
=3.3V or 0V
+/- 10UA
RPU
Pull-up resister
44KΩ
66KΩ
110KΩ
RPD
Pull-down resister
25KΩ
50KΩ
110KΩ
VOL
Output low voltage @IOL(min)
VOH
Output high voltage @IOH (min)
0.4V
2.4V
- 395 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Continued.
PARAMETER
IOL
IOH
MIN.
TYP.
MAX.
Low level output current @VOL = 0.4V
4mA
4.9mA
7.4mA
9.8mA
Low level output current @VOL = 0.4V
8mA
9.7mA
14.9mA
19.5mA
Low level output current @VOL = 0.4V
12mA
14.6mA
22.3mA
29.3mA
High level output current @VOH = 2.4V
4mA
6.3mA
12.8mA
21.2mA
High level output current @VOH = 2.4V
8mA
12.7mA
25.6mA
42.4mA
High level output current @VOH = 2.4V
12mA
19.0mA
38.4mA
63.6mA
NOTE: The values in this table are copied from TSMC 1P5M IO library tpz937g_240b
silicon report. This table is just for reference. More precision DC vaule should refer to
Alpha-Test result.
8.2.2
USB Transceiver DC Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN.
VDI
Differential Input Sensitivity
⎜DP − DM⎥
VCM
Differential
Range
Includes
range
VSE
Single
Ended
Threshold
VOL
Static Output Low Voltage
RL of 1.5 KΩ to
3.6 V
VOH
Static Output High Voltage
RL of 15 KΩ to
VSS
VCRS
Output
Voltage
ZDRV
Driver Output Resistance
CIN
Pin Capacitance
Common
Signal
Mode
0.2
VDI
Receiver
Crossover
Steady
drive
- 396 -
MAX.
state
UNIT
V
0.8
2.5
V
0.8
2.0
V
0.3
V
2.8
3.6
V
1.3
2.0
V
28
43
Ω
20
pF
W90N745CD/W90N745CDG
8.3
AC Specifications
8.3.1
EBI/SDRAM Interface AC Characteristics
1.5V
MCLK
TDSU
D[31:0]
TDH
Iutput Valid
1.5V
SDRAM input to W90P710
MCLK
D[31:0]
1.5V
TDO
1.5V
Output Valid
W90P710 write to SDRAM
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
TDSU
D [31:0] Setup Time
2
ns
TDH
D [31:0] Hold Time
2
ns
TDO
D [31:0], A [24:0], nSCS [1:0], SDQM [3:0],
CKE, nSWE, nSRAS, nSCAS
2
- 397 -
7
ns
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
8.3.2
EBI/(ROM/SRAM/External I/O) AC Characteristics
MCLK
TNECSO
TNECSO
nECS[3:0]
TADDO
A[21:0]
nOE
Address Valid
TNOEO
TNOEO
TDSU
D[31:0]
nWAIT
nWBE[3:0]
TDH
R Data
TNWASU TNWAH
TNWBO
TNWBO
TDO
D[31:0]
SYMBOL
TADDO
Write Data Vaild
DESCRIPTION
Address Output Delay Time
MIN
MAX
UNIT
2
7
ns
ROM/SRAM/Flash or External I/O Chip Select
Delay Time
ROM/SRAM or External I/O Bank Output Enable
Delay
ROM/SRAM or External I/O Bank Write Byte
Enable Delay
2
7
ns
2
7
ns
2
7
ns
TDH
Read Data Hold Time
7
ns
TDSU
Read Data Setup Time
0
ns
TDO
Write Data Output Delay Time (SRAM or
External I/O)
2
TNWASU
External Wait Setup Time
3
ns
TNWAH
External Wait Hold Time
1
ns
TNCSO
TNOEO
TNWBO
- 398 -
7
ns
W90N745CD/W90N745CDG
8.3.3
USB Transceiver AC Characteristics
Rise Time
CL
Fall Time
90%
Differential
Data Lines
90%
10%
CL
10%
tR
Full Speed: 4 to 20ns at CL = 50pF
tF
Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF
Data Signal Rise and Fall Time
USB Transceiver AC Characteristics
SYMBOL
DESCRIPTION
CONDITIONS
MIN
MAX
UNIT
TR
Rise Time
CL = 50 pF
4
20
ns
TF
Fall Time
CL = 50 pF
4
20
ns
TRFM
Rise/Fall Time Matching
90
110
%
TDRATE
Full Speed Data Rate
11.97
12.0
3
Mbps
8.3.4
Average bit rate
(12 Mb/s ± 0.25%)
EMC RMII AC Characteristics
The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3.
TFREQ
PHY_REFCLK
TDUTY
TTXO
PHY_TXEN
PHY_TXD[1:0]
TTXH
valid data
TRXS
PHY_RXERR
PHY_RXD[1:0]
PHY_CRSDV
TRXH
valid data
- 399 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
SYMBOL
DESCRIPTION
MIN
TFREQ
RMII reference clock frequency
TDUTY
RMII clock duty
TTXO
TYP
MAX
50
UNIT
MHz
35%
50%
65%
ns
Transmit data output delay
5
-
15
ns
TTXH
Transmit data hold time
2
-
-
ns
TRXS
Receive data setup time
4
-
-
ns
TRXH
Receive data hold time
2
-
-
ns
PHY_MDC
TMDO
TMDH
PHY_MDIO
(Write)
valid data
TMDS
PHY_MDIO
(Read)
SYMBOL
TMDH
valid data
DESCRIPTION
MIN
MAX
UNIT
15
ns
TMDO
MDIO Output Delay Time
0
TMDSU
MDIO Setup Time
5
ns
TMDH
MDIO Hold Time
5
ns
- 400 -
W90N745CD/W90N745CDG
8.3.5
AC97/I2S Interface AC Characteristics
TCLK_PERIOD
AC97_BCLK
TOD
AC97_DATAO
AC97_SYNC
TISU
TIHD
TOH
AC97_DATAI
SYMBOLS
DESCRIPTION
MIN
TYP.
MAX
UNIT
TCLK_PERIOD
AC97 Bit Clock Frequency
--
12.28
8
--
MHz
TOD
AC97_DATAO and AC97_SYNC output
delay from AC97_BCLK rising edge
--
--
30
ns
TOH
AC97_DATAO and AC97_SYNC output
hold time from AC97_BCLK rising edge
5
--
--
ns
TISU
AC97_DATAI input setup
AC97_BCLK falling edge
10
--
--
ns
TIHD
AC97_DATAI input hold
AC97_BCLK falling edge
5
--
--
ns
time
time
- 401 -
to
from
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
TBCLK_PERIOD
I2S_BCLK
Tout_delay
I2S_DATAO
I2S_RLCLK
TDOH
TDIS
TDIH
I2S_DATAI
SYMBOLS
DESCRIPTION
MIN
MAX
Note:depend
on
codec
spec.
and
register
setting
UNIT
TBCLK_PERIOD
IIS Bit Clock Frequency
Tout_delay
IIS_DATAO and IIS_RLCLK output delay from
IIS_BCLK falling edge
--
30
ns
TDOH
IIS_DATAO and IIS_RLCLK data output hold
time from IIS_BCLK falling edge
0
--
ns
TDIS
IIS_DATAI input setup time to IIS_BCLK
rising edge
10
--
ns
TDIH
IIS_DATAI input hold time from IIS_BCLK
rising edge
100
--
ns
- 402 -
MHz
W90N745CD/W90N745CDG
8.3.6
I2C Interface AC Characteristics
THIGH
SCL
TSU:STO
TLOW
Thd:STA
TSU:DAT2
TSU:DAT
SDA
Thd:DAT
SCL
TSU:SAT
SDA
SYMBOL
THIGH
TLOW
Thd:STA
TSU:DAT
THD:DAT
TSU:DAT2
TSU:STO
TSU:STA
DESCRIPTION
2
I C Clock high time
I2C clock low time
Start condition hold time
Receive data setup time
Transmit data output delay
Receive data hold time
Transmit data hold time
SDA setup time (before STOP condition)
Stop condition setup time
Restart condition setup time
- 403 -
MIN
MAX
UNIT
1
1
1
0.1
1
0
0.5
1
1.5
0.5
0.9
-
us
us
us
us
us
us
us
us
us
us
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
8.3.7
USI Interface AC Characteristics
Tlag
FUSI
SFRM
Tlead
SCLK
TCLKH
TCLKL
SSPTXD
(TX_NEG =1)
TOD
TOD
SSPTXD
(TX_NEG =0)
Tlag
FUSI
SFRM
Tlead
SCLK
TIH
TCLKH TCLKL
SSPRXD
(RX_NEG =1)
TISU
TIH
SSPRXD
(RX_NEG =0)
TISU
- 404 -
W90N745CD/W90N745CDG
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
FUSI
USI clock frequency
-
20
MHz
TCLKH
USI clock high time
12.5
-
ns
TCLKL
USI clock low time
-
-
ns
TISU
Data input setup time
-
14
ns
TIH
Data input hold time
0
-
ns
Tlead
USI enable lead time
12.5
-
ns
Tlag
USI enable lag time
12.5
-
ns
TOD
USI output data valid time
-
30
ns
8.3.8
PS2 Interface AC Characteristics
T4
T3
1st
CLK
PS2_CLK
2nd
CLK
10th
CLK
11th
CLK
T5
T1
PS2_DATA
T2
Start Bit
Bit 0
Parity Bit
Timing for data received from the auxiliary device
T7
PS2_CLK
T8
1st
CLK
2nd
CLK
9th
CLK
10th
CLK
11th
CLK
T9
PS2_DATA
Bit 0
Parity Bit STOP Bit
Timing for data send to the auxiliary device
- 405 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
T1
Time from DATA transition to falling edge of CLK
5
25
us
T2
Time form rising edge of CLK to DATA transition
5
T4-5
us
T3
Duration of CLK inactive
30
50
us
T4
Duration of clock active
30
50
us
T5
Time to auxiliary device inhibit after clock 11 to
ensure the auxiliary device does not start another
transmission
0
50
us
T7
Duration of CLK inactive
30
50
us
T8
Duration of CLK active
30
50
us
T9
Time to fom inactive to active CLK transition, used to
time when the auxiliary device samples DATA
30
50
us
- 406 -
W90N745CD/W90N745CDG
9. PACKAGE SPECIFICATIONS
128L LQFP (14X14X1.4 mm footprint 2.0mm)
- 407 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
10. ORDERING INFORMATION
PART NUMBER
NAME
PACKAGE DESCRIPTION
W90N745CD
LQFP128
128 Leads, body 14 x 14 x 1.4 mm
W90N745CDG
LQFP128
128 Leads, body 14 x 14 x 1.4 mm, Lead free package
- 408 -
W90N745CD/W90N745CDG
11. APPENDIX A: W90N745 REGISTERS MAPPING TABLE
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
System Manager Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
PDID
0xFFF0_0000
R
ARBCON
0xFFF0_0004 R/W Arbitration Control Register
0x0000_0000
PLLCON
0xFFF0_0008 R/W PLL Control Register
0x0000_2F01
CLKSEL
0xFFF0_000C R/W Clock Select Register
0x1FFF_3FX8
PLLCON1
0xFFF0_0010 R/W PLL Control Register 2
0x0001_0000
I²SCKCON
0xFFF0_0014 R/W Audio I²S Clock Control Register
0x0000_0000
Product Identifier Register
RESET VALUE
0xX090.0710
IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register
0x0000_0000
IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register
0x0000_0000
PMCON
0xFFF0_0028 R/W Power Manager Control Register
0x0000_0000
USBTxrCON
0xFFF0_0030 R/W USB Transceiver Control Register
0x0000_0000
External Bus Interface Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EBICON
0xFFF0_1000 R/W EBI control register
0x0001_0000
ROMCON
0xFFF0_1004 R/W ROM/FLASH control register
0x0000_0XFC
SDCONF0
0xFFF0_1008 R/W SDRAM bank 0 configuration register
0x0000_0800
SDCONF1
0xFFF0_100C R/W SDRAM bank 1 configuration register
0x0000_0800
SDTIME0
0xFFF0_1010 R/W SDRAM bank 0 timing control register
0x0000_0000
SDTIME1
0xFFF0_1014 R/W SDRAM bank 1 timing control register
0x0000_0000
EXT0CON
0xFFF0_1018 R/W External I/O 0 control register
0x0000_0000
EXT1CON
0xFFF0_101C R/W External I/O 1 control register
0x0000_0000
EXT2CON
0xFFF0_1020 R/W External I/O 2 control register
0x0000_0000
EXT3CON
0xFFF0_1024 R/W External I/O 3 control register
0x0000_0000
CKSKEW
0xFFF0_1F00 R/W Clock skew control register (for testing)
0xXXXX_0038
- 409 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
Cache Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CAHCNF
0xFFF0_2000
R/W
Cache configuration register
0x0000_0000
CAHCON
0xFFF0_2004
R/W
Cache control register
0x0000_0000
CAHADR
0xFFF0_2008
R/W
Cache address register
0x0000_0000
EMC Registers Map
REGISTER
ADDRESS
CAMCMR
0xFFF0_3000
CAMEN
R/W
DESCRIPTION
RESET VALUE
0x0000_0000
0xFFF0_3004
R/W CAM Command Register
R/W CAM Enable Register
CAM0M
0xFFF0_3008
R/W CAM0 Most Significant Word Register
0x0000_0000
CAM0L
0xFFF0_300C
R/W CAM0 Least Significant Word Register
0x0000_0000
CAM1M
0xFFF0_3010
R/W CAM1 Most Significant Word Register
0x0000_0000
CAM1L
0xFFF0_3014
R/W CAM1 Least Significant Word Register
0x0000_0000
CAM2M
0xFFF0_3018
R/W CAM2 Most Significant Word Register
0x0000_0000
CAM2L
0xFFF0_301C
R/W CAM2 Least Significant Word Register
0x0000_0000
CAM3M
0xFFF0_3020
R/W CAM3 Most Significant Word Register
0x0000_0000
CAM3L
0xFFF0_3024
R/W CAM3 Least Significant Word Register
0x0000_0000
CAM4M
0xFFF0_3028
R/W CAM4 Most Significant Word Register
0x0000_0000
CAM4L
0xFFF0_302C
R/W CAM4 Least Significant Word Register
0x0000_0000
CAM5M
0xFFF0_3030
R/W CAM5 Most Significant Word Register
0x0000_0000
CAM5L
0xFFF0_3034
R/W CAM5 Least Significant Word Register
0x0000_0000
CAM6M
0xFFF0_3038
R/W CAM6 Most Significant Word Register
0x0000_0000
CAM6L
0xFFF0_303C
R/W CAM6 Least Significant Word Register
0x0000_0000
CAM7M
0xFFF0_3040
R/W CAM7 Most Significant Word Register
0x0000_0000
CAM7L
0xFFF0_3044
R/W CAM7 Least Significant Word Register
0x0000_0000
CAM8M
0xFFF0_3048
R/W CAM8 Most Significant Word Register
0x0000_0000
CAM8L
0xFFF0_304C
R/W CAM8 Least Significant Word Register
0x0000_0000
CAM9M
0xFFF0_3050
R/W CAM9 Most Significant Word Register
0x0000_0000
CAM9L
0xFFF0_3054
R/W CAM9 Least Significant Word Register
0x0000_0000
CAM10M
0xFFF0_3058
R/W CAM10 Most Significant Word Register
0x0000_0000
CAM10L
0xFFF0_305C
R/W CAM10 Least Significant Word Register
0x0000_0000
CAM11M
0xFFF0_3060
R/W CAM11 Most Significant Word Register
0x0000_0000
CAM11L
0xFFF0_3064
R/W CAM11 Least Significant Word Register
0x0000_0000
- 410 -
0x0000_0000
W90N745CD/W90N745CDG
EMC Registers Map, continued
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CAM12M
0xFFF0_3068
R/W CAM12 Most Significant Word Register
0x0000_0000
CAM12L
0xFFF0_306C
R/W CAM12 Least Significant Word Register
0x0000_0000
CAM13M
0xFFF0_3070
R/W CAM13 Most Significant Word Register
0x0000_0000
CAM13L
0xFFF0_3074
R/W CAM13 Least Significant Word Register
0x0000_0000
CAM14M
0xFFF0_3078
R/W CAM14 Most Significant Word Register
0x0000_0000
CAM14L
0xFFF0_307C
R/W CAM14 Least Significant Word Register
0x0000_0000
CAM15M
0xFFF0_3080
R/W CAM15 Most Significant Word Register
0x0000_0000
CAM15L
0xFFF0_3084
R/W CAM15 Least Significant Word Register
0x0000_0000
TXDLSA
0xFFF0_3088
R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC
RXDLSA
0xFFF0_308C
MCMDR
0xFFF0_3090
R/W Receive Descriptor Link List Start Address 0xFFFF_FFFC
Register
0x0000_0000
R/W MAC Command Register
MIID
0xFFF0_3094
R/W MII Management Data Register
MIIDA
0xFFF0_3098
R/W MII Management Control and Address Register 0x0090_0000
FFTCR
0xFFF0_309C
R/W FIFO Threshold Control Register
TSDR
0xFFF0_30A0
W
Transmit Start Demand Register
Undefined
RSDR
0xFFF0_30A4
W
Receive Start Demand Register
Undefined
DMARFC
0xFFF0_30A8
R/W Maximum Receive Frame Control Register
0x0000_0800
MIEN
MISTA
0xFFF0_30AC
0xFFF0_30B0
0x0000_0000
0x0000_0000
MGSTA
0xFFF0_30B4
R/W MAC Interrupt Enable Register
R/W MAC Interrupt Status Register
R/W MAC General Status Register
MPCNT
0xFFF0_30B8
0x0000_7FFF
MRPC
0xFFF0_30BC
R/W Missed Packet Count Register
R MAC Receive Pause Count Register
MRPCC
0xFFF0_30C0
R
MAC Receive Pause Current Count Register
0x0000_0000
MREPC
0xFFF0_30C4
R
MAC Remote Pause Count Register
0x0000_0000
DMARFS
0xFFF0_30C8
CTXDSA
0xFFF0_30CC
CTXBSA
0xFFF0_30D0
R
Current Transmit Buffer Start Address Register 0x0000_0000
CRXDSA
0xFFF0_30D4
R
Current Receive Descriptor Start Address 0x0000_0000
Register
CRXBSA
0xFFF0_30D8
R
Current Receive Buffer Start Address Register
0x0000_0000
0x0000_0101
0x0000_0000
0x0000_0000
R/W DMA Receive Frame Status Register
0x0000_0000
R Current Transmit Descriptor Start Address 0x0000_0000
Register
- 411 -
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
EMC Registers Map, continued
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
RXFSM
0xFFF0_3200
R
Receive Finite State Machine Register
0x0081_1101
TXFSM
0xFFF0_3204
R
Transmit Finite State Machine Register
0x0101_1101
FSM0
0xFFF0_3208
R
Finite State Machine Register 0
0x0001_0101
FSM1
0xFFF0_320C
R
Finite State Machine Register 1
0x1100_0100
DCR
0xFFF0_3210
DMMIR
BISTR
0x0000_003F
0xFFF0_3214
R/W Debug Configuration Register
R Debug Mode MAC Information Register
0xFFF0_3300
R/W BIST Mode Register
0x0000_0000
0x0000_0000
GDMA Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
GDMA_CTL0
0xFFF0_4000
R/W
Channel 0 Control Register
0x0000_0000
GDMA_SRCB0
0xFFF0_4004
R/W
Channel 0 Source Base Address Register
0x0000_0000
GDMA_DSTB0
0xFFF0_4008
R/W
Channel 0 Destination Base Address Register
0x0000_0000
GDMA_TCNT0
0xFFF0_400C
R/W
Channel 0 Transfer Count Register
0x0000_0000
GDMA_CSRC0
0xFFF0_4010
R
Channel 0 Current Source Address Register
0x0000_0000
GDMA_CDST0
GDMA_CTCNT
0
GDMA_CTL1
0xFFF0_4014
R
Channel 0 Current Destination Address Register
0x0000_0000
0xFFF0_4018
R
Channel 0 Current Transfer Count Register
0x0000_0000
0xFFF0_4020
R/W
Channel 1 Control Register
0x0000_0000
GDMA_SRCB1
0xFFF0_4024
R/W
Channel 1 Source Base Address Register
0x0000_0000
GDMA_DSTB1
0xFFF0_4028
R/W
Channel 1 Destination Base Address Register
0x0000_0000
GDMA_TCNT1
0xFFF0_402C
R/W
Channel 1 Transfer Count Register
0x0000_0000
GDMA_CSRC1
0xFFF0_4030
R
Channel 1 Current Source Address Register
0x0000_0000
GDMA_CDST1
GDMA_CTCNT
1
0xFFF0_4034
R
Channel 1 Current Destination Address Register
0x0000_0000
0xFFF0_4038
R
Channel 1 Current Transfer Count Register
0x0000_0000
- 412 -
RESET VALUE
W90N745CD/W90N745CDG
USB Host Controller Registers Map
REGISTER
DESCRIPTION
RESET
VALUE
ADDRESS
R/W
HcRevision
0xFFF0_5000
R
HcControl
0xFFF0_5004
R/W Host Controller Control Register
0x0000_0000
HcCommandStatus
0xFFF0_5008
R/W Host Controller Command Status Register
0x0000_0000
HcInterruptStatus
0xFFF0_500C R/W Host Controller Interrupt Status Register
0x0000_0000
HcInterruptEnbale
0xFFF0_5010
R/W Host Controller Interrupt Enable Register
0x0000_0000
HcInterruptDisbale
0xFFF0_5014
R/W Host Controller Interrupt Disable Register
0x0000_0000
HcHCCA
0xFFF0_5018
R/W Host Controller Communication Area Register
0x0000_0000
HcPeriodCurrentED
0xFFF0_501C R/W Host Controller Period Current ED Register
0x0000_0000
HcControlHeadED
0xFFF0_5020
R/W Host Controller Control Head ED Register
0x0000_0000
HcControlCurrentED
0xFFF0_5024
R/W Host Controller Control Current ED Register
0x0000_0000
HcBulkHeadEd
0xFFF0_5028
R/W Host Controller Bulk Head ED Register
0x0000_0000
HcBulkCurrentED
0xFFF0_502C R/W Host Controller Bulk Current ED Register
0x0000_0000
HcDoneHeadED
0xFFF0_5030
R/W Host Controller Done Head Register
0x0000_0000
HcFmInterval
0xFFF0_5034
R/W Host Controller Frame Interval Register
0x0000_2EDF
HcFrameRemaining
0xFFF0_5038
R
Host Controller Frame Remaining Register
0x0000_0000
HcFmNumber
0xFFF0_503C
R
Host Controller Frame Number Register
0x0000_0000
HcPeriodicStart
0xFFF0_5040
R/W Host Controller Periodic Start Register
0x0000_0000
HcLSThreshold
0xFFF0_5044
R/W Host Controller Low Speed Threshold Register
0x0000_0628
HcRhDescriptorA
0xFFF0_5048
R/W Host Controller Root Hub Descriptor A Register
0x0100_0002
HcRhDescriptorB
0xFFF0_504C R/W Host Controller Root Hub Descriptor B Register
0x0000_0000
HcRhStatus
0xFFF0_5050
R/W Host Controller Root Hub Status Register
0x0000_0000
HcRhPortStatus [1]
0xFFF0_5054
R/W Host Controller Root Hub Port Status [1]
0x0000_0000
HcRhPortStatus [2]
0xFFF0_5058
R/W Host Controller Root Hub Port Status [2]
0x0000_0000
OpenHCI Registers
Host Controller Revision Register
0x0000_0010
USB Configuration Registers
TestModeEnable
0xFFF0_5200
OperationalModeEnable 0xFFF0_5204
R/W USB Test Mode Enable Register
R/W USB Operational Mode Enable Register
- 413 -
0x0XXX_XXXX
0x0000_0000
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Device Register Map
REGISTER
OFFSET
R/W
DESCRIPTION
RESET
VALUE
USB_CTL
0xFFF0_6000 R/W
USB control register
0x0000_000
0
VCMD
0xFFF0_6004 R/W
USB class or vendor command register
0x0000_000
0
USB_IE
0xFFF0_6008 R/W
USB interrupt enable register
0x0000_000
0
USB_IS
0xFFF0_600
C
USB interrupt status register
0x0000_000
0
USB_IC
0xFFF0_6010 R/W
USB interrupt status clear register
0x0000_000
0
USB_IFSTR
0xFFF0_6014 R/W
USB interface and string register
0x0000_000
0
USB_ODATA0
0xFFF0_6018
R
USB control transfer-out port 0 register
0x0000_000
0
USB_ODATA1
0xFFF0_601
C
R
USB control transfer-out port 1 register
0x0000_000
0
USB_ODATA2
0xFFF0_6020
R
USB control transfer-out port 2 register
0x0000_000
0
USB_ODATA3
0xFFF0_6024
R
USB control transfer-out port 3 register
0x0000_000
0
USB_IDATA0
0xFFF0_6028 R/W
USB transfer-in data port0 register
0x0000_000
0
USB_IDATA1
0xFFF0_602
C
R/W
USB control transfer-in data port 1
0x0000_000
0
USB_IDATA2
0xFFF0_6030 R/W
USB control transfer-in data port 2
0x0000_000
0
USB_IDATA3
0xFFF0_6034 R/W
USB control transfer-in data port 3
0x0000_000
0
USB_SIE
0xFFF0_6038
R
USB SIE status Register
0x0000_000
0
USB_ENG
0xFFF0_603
C
R/W
USB Engine Register
0x0000_000
0
USB_CTLS
0xFFF0_6040
R
USB control transfer status register
0x0000_000
0
USB_CONFD
0xFFF0_6044 R/W
USB Configured Value register
0x0000_000
0
EPA_INFO
0xFFF0_6048 R/W
USB endpoint A information register
0x0000_000
0
R
- 414 -
W90N745CD/W90N745CDG
USB endpoint A control register
0x0000_000
0
0xFFF0_6050 R/W
USB endpoint A Interrupt Enable register
0x0000_000
0
EPA_IC
0xFFF0_6054
W
USB endpoint A interrupt clear register
0x0000_000
0
EPA_IS
0xFFF0_6058
R
USB endpoint A interrupt status register
0x0000_000
0
EPA_ADDR
0xFFF0_605
C
R/W
USB endpoint A address register
0x0000_000
0
EPA_LENTH
0xFFF0_6060 R/W
USB endpoint A transfer length register
0x0000_000
0
EPB_INFO
0xFFF0_6064 R/W
USB endpoint B information register
0x0000_000
0
EPB_CTL
0xFFF0_6068 R/W
USB endpoint B control register
0x0000_000
0
EPB_IE
0xFFF0_606
C
R/W
USB endpoint B Interrupt Enable register
0x0000_000
0
EPB_IC
0xFFF0_6070
W
USB endpoint B interrupt clear register
0x0000_000
0
EPB_IS
0xFFF0_6074
R
USB endpoint B interrupt status register
0x0000_000
0
EPB_ADDR
0xFFF0_6078 R/W
USB endpoint B address register
0x0000_000
0
EPA_CTL
0xFFF0_604
C
EPA_IE
R/W
- 415 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
USB Device Register Map, continued
REGISTER
OFFSET
R/W
DESCRIPTION
RESET
VALUE
EPB_LENTH
0xFFF0_607C R/W USB endpoint B transfer length register
0x0000_0000
EPC_INFO
0xFFF0_6080
R/W USB endpoint C information register
0x0000_0000
EPC_CTL
0xFFF0_6084
R/W USB endpoint C control register
0x0000_0000
EPC_IE
0xFFF0_6 088 R/W USB endpoint C Interrupt Enable register 0x0000_0000
EPC_IC
0xFFF0_608C
W
USB endpoint C interrupt clear register
0x0000_0000
EPC_IS
0xFFF0_6090
R
USB endpoint C interrupt status register
0x0000_0000
EPC_ADDR
0xFFF0_6094
R/W USB endpoint C address register
0x0000_0000
EPC_LENTH
0xFFF0_6098
R/W USB endpoint C transfer length register
0x0000_0000
EPA_XFER
0xFFF0_609C R/W
USB endpoint A remain transfer length
0x0000_0000
register
EPA_PKT
0xFFF0_60A0
R/W
USB endpoint A remain packet length
0x0000_0000
register
EPB_XFER
0xFFF0_60A4
R/W
USB endpoint B remain transfer length
0x0000_0000
register
EPB_PKT
0xFFF0_60A8
R/W
USB endpoint B remain packet length
0x0000_0000
register
EPC_XFER
0xFFF0_60AC R/W
USB endpoint C remain transfer length
0x0000_0000
register
EPC_PKT
0xFFF0_60B0
USB endpoint C remain packet length
0x0000_0000
register
R/W
Audio Control Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
ACTL_CON
0xFFF0_9000
R/W Audio controller control register
0x0000_0000
ACTL_RESET
0xFFF0_9004
R/W Sub block reset control register
0x0000_0000
DMA destination base address
0x0000_0000
register for record
DMA destination length register for
0x0000_0000
ACTL_RDST_LENGTH 0xFFF0_900C R/W
record
DMA destination current address
0x0000_0000
ACTL_RDSTC
0xFFF0_9010
R
register for record
ACTL_RDSTB
0xFFF0_9008
R/W
ACTL_RSR
0xFFF0_9014
R/W
Record status register
0x0000_0000
DMA destination base address
0x0000_0000
ACTL_PDSTB
0xFFF0_9018 R/W
register for play
DMA destination length register for
ACTL_PDST_LENGTH 0xFFF0_901C R/W
0x0000_0000
play
- 416 -
W90N745CD/W90N745CDG
Audio Control Register Map, continued
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
ACTL_PDSTC
0xFFF0_9020
R
ACTL_PSR
0xFFF0_9024
R/W
ACTL_I²SCON
0xFFF0_9028
R/W I²S control register
ACTL_ACCON
0xFFF0_902C R/W AC-link control register
0x0000_0000
ACTL_ACOS0
0xFFF0_9030
R/W AC-link out slot 0
0x0000_0000
ACTL_ACOS1
0xFFF0_9034
R/W AC-link out slot 1
0x0000_0080
ACTL_ACOS2
0xFFF0_9038
R/W AC-link out slot 2
0x0000_0000
ACTL_ACIS0
0xFFF0_903C
R
AC-link in slot 0
0x0000_0000
ACTL_ACIS1
0xFFF0_9040
R
AC-link in slot 1
0x0000_0000
ACTL_ACIS2
0xFFF0_9044
R
AC-link in slot 2
0x0000_0000
DMA destination current address
register for play
0x0000_0000
Play status register
0x0000_0004
0x0000_0000
Cache Controller Test Registers Map
REGISTER
ADDRESS
R/W
CTEST0
0xFFF6_0000 R/W
CTEST1
0xFFF6_0004
R
DESCRIPTION
RESET VALUE
Cache test register 0
0x0000_0000
Cache test register 1
0x0000_0000
UART0 Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
UART0_RBR 0xFFF8_0000
R
Receive Buffer Register (DLAB = 0)
Undefined
UART0_THR 0xFFF8_0000
W
Transmit Holding Register (DLAB = 0)
Undefined
Interrupt Enable Register (DLAB = 0)
0x0000_0000
UART0_IER 0xFFF8_0004 R/W
UART0_DLL 0xFFF8_0000 R/W
UART0_DLM 0xFFF8_0004 R/W
UART0_IIR
Divisor Latch Register (LS)
(DLAB = 1)
Divisor Latch Register (MS)
(DLAB = 1)
0x0000_0000
0x0000_0000
0xFFF8_0008
R
Interrupt Identification Register
UART0_FCR 0xFFF8_0008
W
FIFO Control Register
Undefined
UART0_LCR 0xFFF8_000C R/W
Line Control Register
0x0000_0000
UART0_LSR 0xFFF8_0014
R
Line Status Register
0x6060_6060
UART0_TOR 0xFFF8_001C
R
Time Out Register
0x0000_0000
- 417 -
0x8181_8181
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
High Speed UART1 Control Registers Map
REGISTER
ADDRESS
R/W
UART1_RBR
0xFFF8_0100
R
Receive Buffer Register (DLAB = 0)
Undefined
UART1_THR
0xFFF8_0100
W
Transmit Holding Register (DLAB = 0)
Undefined
UART1_IER
0xFFF8_0104
R/W
Interrupt Enable Register (DLAB = 0)
0x0000_0000
UART1_DLL
0xFFF8_0100
R/W
UART1_DLM
0xFFF8_0104
R/W
UART1_IIR
0xFFF8_0108
R
Interrupt Identification Register
UART1_FCR
0xFFF8_0108
W
FIFO Control Register
Undefined
UART1_LCR
0xFFF8_010C
R/W
Line Control Register
0x0000_0000
UART1_MCR
0xFFF8_0110
R/W
Modem Control Register
0x0000_0000
UART1_LSR
0xFFF8_0114
R
Line Status Register
0x6060.6060
UART1_MSR
0xFFF8_0118
R
MODEM Status Register
0x0000_0000
UART1_TOR
0xFFF8_011C
R
Time Out Register
0x0000_0000
UART1 Bluetooth Control Register
0x0000_0000
UART1_UBCR 0xFFF8_0120
R/W
DESCRIPTION
Divisor Latch Register (LS)
(DLAB = 1)
Divisor Latch Register (MS)
(DLAB = 1)
RESET VALUE
0x0000_0000
0x0000_0000
0x8181_8181
UART2 Control Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
UART2_RBR 0xFFF8_0200
R
Receive Buffer Register (DLAB = 0)
Undefined
UART2_THR 0xFFF8_0200
W
Transmit Holding Register (DLAB = 0)
Undefined
Interrupt Enable Register (DLAB = 0)
0x0000_0000
UART2_IER
0xFFF8_0204 R/W
UART2_DLL 0xFFF8_0200 R/W
UART2_DLM 0xFFF8_0204 R/W
UART2_IIR
Divisor Latch Register (LS)
(DLAB = 1)
Divisor Latch Register (MS)
(DLAB = 1)
0x0000_0000
0x0000_0000
0xFFF8_0208
R
Interrupt Identification Register
UART2_FCR 0xFFF8_0208
W
FIFO Control Register
Undefined
UART2_LCR 0xFFF8_020C R/W
Line Control Register
0x0000_0000
UART2_MCR 0xFFF8_0210 R/W
Modem Control Register
0x0000_0000
UART2_LSR 0xFFF8_0214
R
Line Status Register
0x6060_6060
UART2_MSR 0xFFF8_0218
R
MODEM Status Register
0x0000_0000
UART2_TOR 0xFFF8_021C
R
Time Out Register
0x0000_0000
UART2_IRCR 0xFFF8_0220 R/W
IrDA Control Register
- 418 -
0x8181_8181
0x0000_0040
W90N745CD/W90N745CDG
UART3 Control Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
UART3_RBR 0xFFF8_0300
R
Receive Buffer Register (DLAB = 0)
Undefined
UART3_THR 0xFFF8_0300
W
Transmit Holding Register (DLAB = 0)
Undefined
Interrupt Enable Register (DLAB = 0)
0x0000_0000
UART3_IER
0xFFF8_0304 R/W
UART3_DLL 0xFFF8_0300 R/W
UART3_DLM 0xFFF8_0304 R/W
UART3_IIR
Divisor Latch Register (LS)
(DLAB = 1)
Divisor Latch Register (MS)
(DLAB = 1)
0x0000_0000
0x0000_0000
0xFFF8_0308
R
Interrupt Identification Register
0x8181_8181
UART3_FCR 0xFFF8_0308
W
FIFO Control Register
Undefined
UART3_LCR 0xFFF8_030C R/W
Line Control Register
0x0000_0000
UART3_MCR 0xFFF8_0310 R/W
Modem Control Register
0x0000_0000
UART3_LSR 0xFFF8_0314
R
Line Status Register
0x6060_6060
UART3_MSR 0xFFF8_0318
R
MODEM Status Register
0x0000_0000
UART3_TOR 0xFFF8_031C
R
Time Out Register
0x0000_0000
Timer Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
TCR0
0xFFF8_1000
R/W
Timer Control Register 0
0x0000_0005
TCR1
0xFFF8_1004
R/W
Timer Control Register 1
0x0000_0005
TICR0
0xFFF8_1008
R/W
Timer Initial Control Register 0
0x0000_00FF
TICR1
0xFFF8_100C R/W
Timer Initial Control Register 1
0x0000_00FF
TDR0
0xFFF8_1010
R
Timer Data Register 0
0x0000_0000
TDR1
0xFFF8_1014
R
Timer Data Register 1
0x0000_0000
TISR
0xFFF8_1018
R/C
Timer Interrupt Status Register
0x0000_0000
WTCR
0xFFF8_101C R/W
Watchdog Timer Control Register
0x0000_0000
- 419 -
RESET VALUE
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
AIC Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
AIC_SCR1
0xFFF8_2004
R/W
Source Control Register 1
0x0000_0047
AIC_SCR2
0xFFF8_2008
R/W
Source Control Register 2
0x0000_0047
AIC_SCR3
0xFFF8_200C R/W
Source Control Register 3
0x0000_0047
AIC_SCR4
0xFFF8_2010
R/W
Source Control Register 4
0x0000_0047
AIC_SCR5
0xFFF8_2014
R/W
Source Control Register 5
0x0000_0047
AIC_SCR6
0xFFF8_2018
R/W
Source Control Register 6
0x0000_0047
AIC_SCR7
0xFFF8_201C R/W
Source Control Register 7
0x0000_0047
AIC_SCR8
0xFFF8_2020
R/W
Source Control Register 8
0x0000_0047
AIC_SCR9
0xFFF8_2024
R/W
Source Control Register 9
0x0000_0047
AIC_SCR10
0xFFF8_2028
R/W
Source Control Register 10
0x0000_0047
AIC_SCR11
0xFFF8_202C R/W
Source Control Register 11
0x0000_0047
AIC_SCR12
0xFFF8_2030
R/W
Source Control Register 12
0x0000_0047
AIC_SCR13
0xFFF8_2034
R/W
Source Control Register 13
0x0000_0047
AIC_SCR14
0xFFF8_2038
R/W
Source Control Register 14
0x0000_0047
AIC_SCR15
0xFFF8_203C R/W
Source Control Register 15
0x0000_0047
AIC_SCR16 0xFFF8_2040 R/W
Source Control Register 16
0x0000_0000
AIC_SCR17 0xFFF8_2044 R/W
Source Control Register 17
0x0000_0000
AIC_SCR18 0xFFF8_2048 R/W
Source Control Register 18
0x0000_0000
AIC_SCR19 0xFFF8_204C R/W
Source Control Register 19
0x0000_0047
AIC_SCR20 0xFFF8_2050 R/W
Source Control Register 20
0x0000_0047
AIC_SCR21 0xFFF8_2054 R/W
Source Control Register 21
0x0000_0047
AIC_SCR22 0xFFF8_2058 R/W
Source Control Register 22
0x0000_0047
AIC_SCR23 0xFFF8_205C R/W
Source Control Register 23
0x0000_0047
AIC_SCR24 0xFFF8_2060 R/W
Source Control Register 24
0x0000_0047
AIC_SCR25 0xFFF8_2064 R/W
Source Control Register 25
0x0000_0047
AIC_SCR26 0xFFF8_2068 R/W
Source Control Register 26
0x0000_0047
AIC_SCR27 0xFFF8_206C R/W
Source Control Register 27
0x0000_0047
AIC_SCR28 0xFFF8_2070 R/W
Source Control Register 28
0x0000_0047
AIC_SCR29 0xFFF8_2074 R/W
Source Control Register 29
0x0000_0047
AIC_SCR30 0xFFF8_2078 R/W
Source Control Register 30
0x0000_0047
AIC_SCR31 0xFFF8_207C R/W
Source Control Register 31
0x0000_0047
- 420 -
W90N745CD/W90N745CDG
AIC Control Registers Map, continued
REGISTER
ADDRESS
R/W
DESCRIPTION
AIC_IRSR
0xFFF8_2100
R
Interrupt Raw Status Register
0x0000_0000
AIC_IASR
0xFFF8_2104
R
Interrupt Active Status Register
0x0000_0000
AIC_ISR
0xFFF8_2108
R
Interrupt Status Register
0x0000_0000
AIC_IPER
0xFFF8_210C
R
Interrupt Priority Encoding Register
0x0000_0000
AIC_ISNR
0xFFF8_2110
R
Interrupt Source Number Register
0x0000_0000
AIC_IMR
0xFFF8_2114
R
Interrupt Mask Register
0x0000_0000
AIC_OISR
0xFFF8_2118
R
Output Interrupt Status Register
0x0000_0000
AIC_MECR
0xFFF8_2120
W
Mask Enable Command Register
Undefined
AIC_MDCR
0xFFF8_2124
W
Mask Disable Command Register
Undefined
AIC_SSCR
0xFFF8_2128
W
Source Set Command Register
Undefined
AIC_SCCR
0xFFF8_212C
W
Source Clear Command Register
Undefined
AIC_EOSCR
0xFFF8_2130
W
End of Service Command Register
Undefined
AIC_TEST
0xFFF8_2200
W
ICE/Debug mode Register
RESET VALUE
Undefined
GPIO Control Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GPIO_CFG0
0xFFF8_3000 R/W
GPIO Port0 Configuration Register
0x0000_0000
GPIO_DIR0
0xFFF8_3004 R/W
GPIO Port0 Direction Control Register
0x0000_0000
GPIO_DATAOUT0 0xFFF8_3008 R/W
GPIO Port0 Data Output Register
0x0000_0000
GPIO_DATAIN0
0xFFF8_300C R
GPIO Port0 Data Input Register
0xXXXX_XXXX
GPIO_CFG1
0xFFF8_3010 R/W
GPIO port1 configuration register
0x0000_0000
GPIO_DIR1
0xFFF8_3014 R/W
GPIO port1 direction control register
0x0000_0000
GPIO_DATAOUT1 0xFFF8_3018 R/W
GPIO port1 data output register
0x0000_0000
GPIO_DATAIN1
0xFFF8_301C R
GPIO port1 data input register
0xXXXX_XXXX
GPIO_CFG2
0xFFF8_3020 R/W
GPIO Port2 Configuration Register
0x0000_0000
GPIO_DIR2
0xFFF8_3024 R/W
GPIO Port2 Direction Control Register
0x0000_0000
GPIO_DATAOUT2 0xFFF8_3028 R/W
GPIO Port2 Data Output Register
0x0000_0000
GPIO_DATAIN2
0xFFF8_302C R
GPIO Port2 Data Input Register
0xXXXX_XXXX
GPIO_CFG4
0xFFF8_3040 R/W
GPIO Port4 Configuration Register
0x0015_5555
GPIO_DIR4
0xFFF8_3044 R/W
GPIO Port4 Direction Control Register
0x0000_0000
GPIO_DATAOUT4 0xFFF8_3048 R/W
GPIO Port4 Data Output Register
0x0000_0000
GPIO_DATAIN4
GPIO Port4 Data Input Register
0xXXXX_XXXX
0xFFF8_304C R
- 421 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
GPIO Control Register Map, continued
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GPIO_CFG5
0xFFF8_3050 R/W
GPIO Port5 Configuration Register
0x0000_0000
GPIO_DIR5
0xFFF8_3054 R/W
GPIO Port5 Direction Control Register
0x0000_0000
GPIO_DATAOUT5 0xFFF8_3058 R/W
GPIO Port5 Data Output Register
0x0000_0000
GPIO_DATAIN5
GPIO Port5 Data Input Register
0xXXXX_XXXX
GPIO_DBNCECON 0xFFF8_3070 R/W
GPIO Input Debounce Control Register
0x0000_0000
GPIO_XICFG
0xFFF8_3074 R/W
Extend Interrupt Configure Register
0xXXXX_XXX0
GPIO_XISTATUS
0xFFF8_3078 R/W
Extend Interrupt Status Register
0xXXXX_XXX0
0xFFF8_305C R
I2C Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
2
I C Interface 0
2
2
I C_CSR0
0xFFF8_6000
R/W
I C0 Control and Status Register
0x0000_0000
I2C_DIVIDER0
0xFFF8_6004
R/W
I2C0 Clock Prescale Register
0x0000_0000
I2C_CMDR0
0xFFF8_6008
R/W
I2C0 Command Register
0x0000_0000
2
I C_SWR0
2
I C_RxR0
2
I C_TxR0
0xFFF8_600C
0xFFF8_6010
0xFFF8_6014
R/W
R
R/W
2
0x0000_003F
2
0x0000_0000
I C0 Software Mode Control Register
I C0 Data Receive Register
2
I C0 Data Transmit Register
0x0000_0000
2
I C Interface 1
I2C_CSR1
2
I C_DIVIDER1
2
I C_CMDR1
2
I C_SWR1
2
I C_RxR1
2
I C_TxR1
0xFFF8_6000
0xFFF8_6004
0xFFF8_6008
0xFFF8_600C
0xFFF8_6010
0xFFF8_6014
R/W
R/W
R/W
R/W
R
R/W
I2C1 Control and Status Register
0x0000_0000
2
0x0000_0000
2
0x0000_0000
2
0x0000_003F
2
0x0000_0000
2
0x0000_0000
I C1 Clock Prescale Register
I C1 Command Register
I C1 Software Mode Control Register
I C1 Data Receive Register
I C1 Data Transmit Register
- 422 -
W90N745CD/W90N745CDG
USI Register Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
USI_CNTRL
0xFFF8_6200 R/W
Control and Status Register
0x0000_0004
USI_DIVIDER
0xFFF8_6204 R/W
Clock Divider Register
0x0000_0000
USI_SSR
0xFFF8_6208 R/W
Slave Select Register
0x0000_0000
Reserved
0xFFF8_620C
N/A
Reserved
USI_Rx0
0xFFF8_6210
R
Data Receive Register 0
0x0000_0000
USI_Rx1
0xFFF8_6214
R
Data Receive Register 1
0x0000_0000
USI_Rx2
0xFFF8_6218
R
Data Receive Register 2
0x0000_0000
USI_Rx3
0xFFF8_621C
R
Data Receive Register 3
0x0000_0000
USI_Tx0
0xFFF8_6210
W
Data Transmit Register 0
0x0000_0000
USI_Tx1
0xFFF8_6214
W
Data Transmit Register 1
0x0000_0000
USI_Tx2
0xFFF8_6218
W
Data Transmit Register 2
0x0000_0000
USI_Tx3
0xFFF8_621C
W
Data Transmit Register 3
0x0000_0000
N/A
PWM Control Registers Map
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
PWM_PPR
0xFFF8_7000
R/W
PWM Prescaler Register
0x0000_0000
PWM_CSR
0xFFF8_7004
R/W
PWM Clock Select Register
0x0000_0000
PWM_PCR
0xFFF8_7008
R/W
PWM Control Register
0x0000_0000
PWM_CNR0
0xFFF8_700C
R/W
PWM Counter Register 0
0x0000_0000
PWM_CMR0
0xFFF8_7010
R/W
PWM_PDR0
0xFFF8_7014
R
PWM_CNR1
0xFFF8_7018
PWM_CMR1
PWM Comparator Register 0
0x0000_0000
PWM Data Register 0
0x0000_0000
R/W
PWM Counter Register 1
0x0000_0000
0xFFF8_701C
R/W
PWM Comparator Register 1
0x0000_0000
PWM_PDR1
0xFFF8_7020
R
PWM Data Register 1
0x0000_0000
PWM_CNR2
0xFFF8_7024
R/W
PWM Counter Register 2
0x0000_0000
PWM_CMR2
0xFFF8_7028
R/W
PWM_PDR2
0xFFF8_702C
R
PWM_CNR3
0xFFF8_7030
PWM_CMR3
PWM Comparator 2
0x0000_0000
PWM Data Register 2
0x0000_0000
R/W
PWM Counter Register 3
0x0000_0000
0xFFF8_7034
R/W
PWM Comparator Register 3
0x0000_0000
PWM_PDR3
0xFFF8_7038
R
PWM Data Register 3
0x0000_0000
PWM_PIER
0xFFF8_703C
R/W
PWM Interrupt Enable Register
0x0000_0000
PWM_PIIR
0xFFF8_7040
R/C
PWM Interrupt Indication Register
0x0000_0000
- 423 -
Publication Release Date: July 26, 2006
Revision A1
W90N745CD/W90N745CDG
KPI Control Register Map
REGISTER
KPICONF
ADDRESS
R/W
DESCRIPTION
0xFFF8_8000 R/W Keypad controller configuration Register
RESET VALUE
0x0000_0000
KPI3KCONF 0xFFF8_8004 R/W Keypad controller 3-keys configuration register 0x0000_0000
KPILPCONF 0xFFF8_8008 R/W Keypad controller low power configuration 0x0000_0000
register
KPISTATUS 0xFFF8_800C R/O
Keypad controller status register
0x0000_0000
PS2 Control Register Map
REGISTER
ADDRESS
R/W/C
DESCRIPTION
RESET VALUE
PS2CMD
0xFFF8_9000
R/W
PS2 Host Controller Command Register
0x0000_0000
PS2STS
0xFFF8_9004
R/W
PS2 Host Controller Status Register
0x0000_0000
PS2SCANCODE 0xFFF8_9008
RO
PS2 Host Controller RX Scan Code 0x0000_0000
Register
PS2ASCII
RO
PS2 Host Controller RX ASCII Code 0x0000_0000
Register
0xFFF8_900C
- 424 -
W90N745CD/W90N745CDG
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 425 -
Publication Release Date: July 26, 2006
Revision A1
Source Exif Data:
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