W90N745 Data Sheet_0808 Nuvoton Sheet

User Manual: Nuvoton W90N745 - W90N745 data sheet

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W90N745CD/W90N745CDG

32-BIT ARM7TDMI-BASED MCU

W90N745CD/W90N745CDG

16/32-bit ARM microcontroller

Product Data Sheet

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- I - Revision A1

Revision History

REVISION DATE COMMENTS

A 2006/06/23 Draft

A1 2006/07/26

Add Electrical specification

W90N745CD/W90N745CDG

- II -

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 1

2. FEATURES ................................................................................................................................. 2

3. PIN DIAGRAM ............................................................................................................................ 7

4. PIN ASSIGNMENT ..................................................................................................................... 8

5. PIN DESCRIPTION................................................................................................................... 13

6. BLOCK DIAGRAM .................................................................................................................... 24

7. FUNCTIONAL DESCRIPTION ................................................................................................. 25

7.1 ARM7TDMI CPU CORE............................................................................................... 25

7.2 System Manager........................................................................................................... 26

7.2.1 Overview ........................................................................................................................26

7.2.2 System Memory Map......................................................................................................26

7.2.3 Address Bus Generation ................................................................................................29

7.2.4 Data Bus Connection with External Memory ..................................................................29

7.2.5 Bus Arbitration................................................................................................................38

7.2.6 Power Management .......................................................................................................39

7.2.7 Power-On Setting ...........................................................................................................42

7.2.8 System Manager Control Registers Map........................................................................43

7.3 External Bus Interface .................................................................................................. 58

7.3.1 EBI Overview..................................................................................................................58

7.3.2 SDRAM Controller..........................................................................................................58

7.3.3 EBI Control Registers Map.............................................................................................62

7.4 Cache Controller........................................................................................................... 81

7.4.1 On-Chip RAM .................................................................................................................81

7.4.2 Non-Cacheable Area......................................................................................................81

7.4.3 Instruction Cache............................................................................................................82

7.4.4 Data Cache ....................................................................................................................84

7.4.5 Write Buffer ....................................................................................................................86

7.4.6 Cache Control Registers Map.........................................................................................86

7.5 Ethernet MAC Controller............................................................................................... 94

7.5.1 EMC Functional Description ...........................................................................................95

7.5.2 EMC Register Mapping ................................................................................................105

7.6 GDMA Controller ........................................................................................................ 160

7.6.1 GDMA Functional Description ......................................................................................160

7.6.2 GDMA Register Map ....................................................................................................161

7.7 USB Host Controller ................................................................................................... 170

7.7.1 USB Host Functional Description .................................................................................170

7.7.2 USB Host Controller Registers Map .............................................................................171

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- III - Revision A1

7.8 USB Device Controller................................................................................................ 195

7.8.1 USB Endpoints .............................................................................................................195

7.8.2 Standard Device Request.............................................................................................195

7.8.3 USB Device Register Description.................................................................................195

7.9 Audio Controller .......................................................................................................... 236

7.9.1 I²S Interface..................................................................................................................236

7.9.2 AC97 Interface .............................................................................................................237

7.9.3 Audio Controller Register Map......................................................................................240

7.10 Universal Asynchronous Receiver/Transmitter Controller ......................................... 259

7.10.1 UART0........................................................................................................................261

7.10.2 UART1........................................................................................................................261

7.10.3 UART2........................................................................................................................263

7.10.4 UART3........................................................................................................................265

7.10.5 General UART Controller ...........................................................................................266

7.10.6 High speed UART Controller ......................................................................................280

7.11 Timer/Watchdog Controller......................................................................................... 294

7.11.1 General Timer Controller............................................................................................294

7.11.2 Watchdog Timer .........................................................................................................294

7.11.3 Timer Control Registers Map......................................................................................294

7.12 Advanced Interrupt Controller..................................................................................... 303

7.12.1 Interrupt Sources........................................................................................................304

7.12.2 AIC Registers Map .....................................................................................................307

7.13 General-Purpose Input/Output ................................................................................... 321

7.13.1 GPIO Register Description .........................................................................................323

7.13.2 GPIO Register Description .........................................................................................324

7.14 I2C Interface................................................................................................................ 345

7.14.1 I2C Protocol ................................................................................................................346

7.14.2 I2C Serial Interface Control Registers Map.................................................................349

7.15 Universal Serial Interface............................................................................................ 356

7.15.1 USI Timing Diagram ...................................................................................................357

7.15.2 USI Registers Map .....................................................................................................358

7.16 PWM ........................................................................................................................... 365

7.16.1 PWM Double Buffering and Reload Automatically......................................................366

7.16.2 Modulate Duty Ratio...................................................................................................366

7.16.3 Dead Zone Generator.................................................................................................367

7.16.4 PWM Timer Start Procedure ......................................................................................367

7.16.5 PWM Timer Stop Procedure.......................................................................................367

7.16.6 PWM Register Map ....................................................................................................368

7.17 Keypad Interface......................................................................................................... 378

W90N745CD/W90N745CDG

- IV -

7.17.1 Keypad Interface Register Map ..................................................................................379

7.17.2 Register Description ...................................................................................................380

7.18 PS2 Host Interface Controller..................................................................................... 387

7.18.1 PS2 Host Controller Interface Register Map...............................................................388

7.18.2 Register Description ...................................................................................................389

8. ELECTRICAL SPECIFICATIONS........................................................................................... 393

8.1 Absolute Maximum Ratings........................................................................................ 393

8.2 DC Specifications ....................................................................................................... 393

8.2.1 Digital DC Characteristics.............................................................................................393

8.2.2 USB Transceiver DC Characteristics............................................................................396

8.3 AC Specifications........................................................................................................ 397

8.3.1 EBI/SDRAM Interface AC Characteristics ....................................................................397

8.3.2 EBI/(ROM/SRAM/External I/O) AC Characteristics ......................................................398

8.3.3 USB Transceiver AC Characteristics............................................................................399

8.3.4 EMC RMII AC Characteristics ......................................................................................399

8.3.5 AC97/I2S Interface AC Characteristics.........................................................................401

8.3.6 I2C Interface AC Characteristics...................................................................................403

8.3.7 USI Interface AC Characteristics..................................................................................404

8.3.8 PS2 Interface AC Characteristics .................................................................................405

9. PACKAGE SPECIFICATIONS................................................................................................ 407

10. ORDERING INFORMATION .................................................................................................. 408

11. APPENDIX A: W90N745 REGISTERS MAPPING TABLE .................................................... 409

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 1 - Revision A1

1. GENERAL DESCRIPTION

The W90N745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which

cache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static

design is particularly suitable for cost sensitive and power sensitive applications.

One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost.

The W90N745 also provides one USB 1.1 host controller, one USB 1.1 device controller, one

AC97/I²S controller, one 2-channel GDMA, four independent UARTs, one watchdog timer, two 24-bit

timers with 8-bit pre-scale, up to 31 programmable I/O ports, PS2 keyboard controller and an

advanced interrupt controller. The external bus interface (EBI) controller provides for SDRAM,

ROM/SRAM, flash memory and I/O devices. The system manager includes an internal 32-bit system

bus arbiter and a PLL clock controller.

With a wide range of serial communication and Ethernet interfaces, the W90N745 is suitable for

communication gateways as well as many other general purpose applications.

W90N745CD/W90N745CDG

- 2 -

2. FEATURES

Architecture

• Fully 16/32-bit RISC architecture

• Little/Big-Endian mode supported

• Efficient and powerful ARM7TDMI core

• Cost-effective JTAG-based debug solution

External Bus Interface

• 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os

• Support for SDRAM

• Programmable access cycle (0-7 wait cycle)

• Four-word depth write buffer for SDRAM write data

• Cost-effective memory-to-peripheral DMA interface

Instruction and Data Cache

• Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache

• Support for LRU (Least Recently Used) protocol

• Cache can be configured as internal SRAM

• Support cache lock function

Ethernet MAC Controller

• DMA engine with burst mode

• MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)

• Data alignment logic

• Endian translation

• 100/10 Mbit per second operation

• Full compliance with IEEE standard 802.3

• RMII interface only

• Station Management Signaling

• On-chip CAM (up to 16 destination addresses)

• Full-duplex mode with PAUSE feature

• Long/short packet modes

• PAD generation

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 3 - Revision A1

DMA Controller

• 2-channel general DMA for memory-to-memory data transfers without CPU intervention

• Initialed by a software or external DMA request

• Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers

• 4-data burst mode

UART

• Four UART (serial I/O) blocks with interrupt-based operation

• Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive

• Programmable baud rates

• 1, ½ or 2 stop bits

• Odd or even parity

• Break generation and detection

• Parity, overrun and framing error detection

• X16 clock mode

• UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR

Timers

• Two programmable 24-bit timers with 8-bit pre-scaler

• One programmable 20 bit with selectable additional 8-bit prescaler watchdog timer

• One-shot mode, periodical mode or toggle mode operation

Programmable I/Os

• 31 programmable I/O ports

• Pins individually configurable to input, output or I/O mode for dedicated signals

• I/O ports are configurable for multiple functions

Advanced Interrupt Controller

• 24 interrupt sources, including 4 external interrupt sources

• Programmable normal or fast interrupt mode (IRQ, FIQ)

• Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources

• Programmable as either low-active or high-active for 4 external interrupt sources

• Priority methodology is encoded to allow for interrupt daisy-chaining

• Automatically mask out the lower priority interrupt during interrupt nesting

W90N745CD/W90N745CDG

- 4 -

USB Host Controller

• USB 1.1 compliant

• Compatible with Open HCI 1.0 specification

• Supports low-speed and full speed devices

• Build-in DMA for real time data transfer

• Two on-chip USB transceivers with one optionally shared with USB device controller

USB Device Controller

• USB 1.1 compliant

• Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich

USB functions

Two PLLs

• The external clock can be multiplied by on-chip PLL to provide high frequency system clock

• The input frequency range is 3-30MHz; 15MHz is preferred.

• One PLL for both CPU and USB host/device controller

• One PLL for audio I²S 12.288/16.934MHz clock source

• Programmable clock frequency

4-Channel PWM

• Four 16-bit timers with PWM

• Two 8-bit pre-scalers & Two 4-bit dividers

• Programmable duty control of output waveform (PWM)

• Auto reload mode or one-shot pulse mode

• Dead-zone generator

I2C Master

• 2-channel I2C

• Compatible with Philips I2C standard, support master mode only

• Support multi master operation

• Clock stretching and wait state generation

• Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer

• Software programmable acknowledge bit

• Arbitration lost interrupt, with automatic transfer cancellation

• Start/Stop/Repeated Start/Acknowledge generation

• Start/Stop/Repeated Start detection

• Bus busy detection

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 5 - Revision A1

• Supports 7 bit addressing mode

• Software mode I2C

Universal Serial Interface (USI)

• 1-channel USI

• Support USI (Microwire/SPI) master mode

• Full duplex synchronous serial data transfer

• Variable length of transfer word up to 32 bits

• Provide burst mode operation, transmit/receive can be executed up to four times in one transfer

• MSB or LSB first data transfer

• Rx and Tx on both rising or falling edge of serial clock independently

• Two slave/device select lines

• Fully static synchronous design with one clock domain

2-Channel AC97/I²S Audio Codec Host Interface

• AHB master port and an AHB slave port are offered in audio controller.

• Always 8-beat incrementing burst

• Always bus lock when 8-beat incrementing burst

• When reach middle and end address of destination address, a DMA_IRQ is requested to CPU

automatically

KeyPad Scan Interface

• Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4x8 array without auxiliary

component

• Programmable debounce time

• One or two keys scan with interrupt and three keys reset function.

• Wakeup CPU from IDEL/Power Down mode

PS2 Host Interface

• APB slave consisted of PS2 protocol.

• Connect IBM keyboard or bar-code reader through PS2 interface.

• Provide hardware scan code to ASCII translation

W90N745CD/W90N745CDG

- 6 -

Power management

• Programmable clock enables for individual peripheral

• IDLE mode to halt ARM core and keep peripheral working

• Power-Down mode to stop all clocks included external crystal oscillator.

• Exit IDLE by all interrupts

Exit Power-Down by keypad,USB device and external interrupts

Operation Voltage Range

• 3.0 ~ 3.6 V for IO buffer

• 1.62 ~ 1.98 V for core logic

Operation Temperature Range

• TBD

Operating Frequency

• Up to 80 MHz

Package Type

• 128-pin LQFP

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 7 - Revision A1

3. PIN DIAGRAM

Fig 3.1 Pin Diagram

W90N745CD/W90N745CDG

- 8 -

4. PIN ASSIGNMENT

Table 4.1 W90N745 Pins Assignment

PIN NAME 128-PIN LQFP

Clock & Reset ( 3 pins )

EXTAL (15M) 40

XTAL (15M) 41

nRESET 25

JTAG Interface ( 5 pins )

TMS 33

TDI 34

TDO 35

TCK 36

nTRST 37

External Bus Interface ( 53 pins )

A [20:0] 89-86,84-82,80-77,75-71,69-65

D [15:0] 110-111,113-116,118-122,124-128

nWBE [1;0] /

SDQM [1:0] 108,107

nSCS [1:0] 100,99

nSRAS 101

nSCAS 102

MCKE 98

nSWE 106

MCLK 104

nWAIT /

GPIO [30] /

nIRQ [3]

nBTCS 97

nECS [3:0] 90,92-94

nOE 95

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 9 - Revision A1

Table 4.1 W90N745 Pins Assignment, Continued

PIN NAME 128-PIN LQFP

Ethernet Interface ( 10 pins )

PHY_MDC /

GPIO [29] /

KPROW [1]

PHY_MDIO /

GPIO [28] /

KPROW [0]

PHY_TXD [1:0] /

GPIO [27:26] /

KPCOL [7:6]

62,60

PHY_TXEN /

GPIO [25] /

KPCOL [5]

PHY_REFCLK /

GPIO [24] /

KPCOL [4]

PHY_RXD [1:0] /

GPIO [23:22] /

KPCOL [3:2]

57,55

PHY_CRSDV /

GPIO [21] /

KPCOL [1]

PHY_RXERR /

GPIO [20] /

KPCOL [0]

AC97/I²S/PWM/UART3 ( 5 pins )

AC97_nRESET /

I²S_MCLK /

GPIO [0] /

nIRQ [2] /

USB_PWREN

W90N745CD/W90N745CDG

- 10 -

Table 4.1 W90N745 Pins Assignment, Continued

PIN NAME 128-PIN LQFP

AC97/I²S/PWM/UART3 ( 5 pins )

AC97_DATAI /

I²S_DATAI /

PWM [0] /

DTR3 /

GPIO [1]

AC97_DATAO /

I²S_DATAO /

PWM [1] /

DSR3 /

GPIO [2]

AC97_SYNC /

I²S_LRCLK /

PWM [2] /

TXD3 /

GPIO [3]

AC97_BITCLK /

I²S_BITCLK /

PWM [3] /

RXD3

GPIO [4]

USB Interface ( 4 pins )

DP0 7

DN 0 6

DP1 2

DN1 3

Miscellaneous ( 7 pins )

nIRQ [1] /

GPIO [17] /

USB_OVRCUR

nIRQ [0] /

GPIO [16] 31

nWDOG /

GPIO [15] /

USB_PWREN

TEST 26

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 11 - Revision A1

Table 4.1 W90N745 Pins Assignment, Continued

PIN NAME 128-PIN LQFP

I2C/USI(SPI/MW) ( 4 pins )

SCL0 /

SFRM /

TIMER0 /

GPIO [11]

SDA0 /

SSPTXD /

TIMER1 /

GPIO [12]

SCL1 /

SCLK /

GPIO [13] /

KPROW [3]

SDA1 /

SSPRXD /

GPIO [14] /

KPROW [2]

UART0/UART1/UART2/PS2 ( 6 pins )

TXD0 /

GPIO [5] 10

RXD0 /

GPIO [6] 11

TXD1 /

GPIO [7] 12

RXD1 /

GPIO [8] 13

CTS1 /

TXD2(IrDA) /

PS2_CLK /

GPIO [9]

RTS1 /

RXD2(IrDA) /

PS2_DATA /

GPIO [10]

W90N745CD/W90N745CDG

- 12 -

Table 4.1 W90N745 Pins Assignment, Continued

PIN NAME 128-PIN LQFP

XDMA ( 2 pins )

nXDREQ /

GPIO [19] / 51

nXDACK /

GPIO [18] / 52

Power/Ground ( 36 pins )

VDD18 21,43,49,85,112

VSS18 22,50,81,109

VDD33 9,23,42,61,76,103,117

VSS33 16,24,39,56,70,91,105,123

USBVDD 1,8

USBVSS 4,5

PLLVDD18 27,30

PLLVSS18 28,29

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 13 - Revision A1

5. PIN DESCRIPTION

Table 5.1 W90N745 Pins Description

PIN NAME IO TYPE DESCRIPTION

Clock & Reset

EXTAL (15M) I 15MHz External Clock / Crystal Input

XTAL (15M) O 15MHz Crystal Output

nRESET IS System Reset, active-low

JTAG Interface

TMS IUS JTAG Test Mode Select, internal pull-up with 70K ohm

TDI IUS JTAG Test Data in, internal pull-up with 70K ohm

TDO O JTAG Test Data out

TCK IDS JTAG Test Clock, internal pull-down with 58K ohm

nTRST IUS JTAG Reset, active-low, internal pull-up with 70K ohm

External Bus Interface

A [20:18] O Address Bus (MSB) of external memory and IO devices.

A [17:0] IOS Address Bus of external memory and IO devices.

D [15:0] IOS Data Bus (LSB) of external memory and IO device.

nWBE [1:0] /

SDQM [1:0] IOS Write Byte Enable for specific device (nECS [1:0]).

Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.

nSCS [1:0] O SDRAM chip select for two external banks, active-low.

nSRAS O Row Address Strobe for SDRAM, active-low.

nSCAS O Column Address Strobe for SDRAM, active-low.

MCKE O SDRAM Clock Enable, active-high

nSWE O SDRAM Write Enable, active-low

MCLK O System Master Clock Out, SDRAM clock, output with slew-rate control

nWAIT /

GPIO[30] /

nIRQ3

IUS

External Wait, active-low. This pin indicates that the external devices need

more active cycle during access operation.

General Programmable In/Out Port GPIO[30]. If memory and IO devices in EBI

do not need wait request, it can be configured as GPIO[30] or nIRQ3.

nBTCS O ROM/Flash Chip Select, active-low.

nECS [3:0] IO External I/O Chip Select, active-low.

nOE O ROM/Flash, External Memory Output Enable, active-low.

W90N745CD/W90N745CDG

- 14 -

Table 5.1 W90N745 Pins Description, Continued

PIN NAME IO TYPE DESCRIPTION

Ethernet Interface

PHY_MDC /

GPIO [29] /

KPROW [1]

IOU

RMII Management Data Clock for Ethernet. It is the reference clock of MDIO.

Each MDIO data will be latched at the rising edge of MDC clock.

General Programmable In/Out Port [29]

Keypad ROW[1] scan output.

PHY_MDIO /

GPIO [28] /

KPROW [0]

RMII Management Data I/O for Ethernet. It is used to transfer RMII control and

status information between PHY and MAC.

General Programmable In/Out Port [28]

Keypad ROW[0] scan output.

PHY_TXD [1:0] /

GPIO [27:26] /

KPCOL [7:6]

IOU

2-bit Transmit Data bus for Ethernet.

General programmable In/Out Port [27:26]

Keypad column input [7:6], active low

PHY_TXEN /

GPIO [25] /

KPCOL [5]

IOU

PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble

and shall remain asserted while all di-bits to be transmitted are presented. Of

course, it is synchronized with PHY_REFCLK.

General Programmable In/Out Port [25]

Keypad column input [5], active low

PHY_REFCLK /

GPIO [24] /

KPCOL [4]

IOS

Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35%

duty cycle at high or low state.

General Programmable In/Out port [24]

Keypad column input [4], active low

PHY_RXD [1:0] /

GPIO [23:22] /

KPCOL [3:2]

IOS

2-bit Receive Data bus for Ethernet.

General Programmable In/Out Port [23:22]

Keypad column input [3:2], active low

PHY_CRSDV /

GPIO [21] /

KPCOL [1]

IOS

Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be

asserted by PHY when the receive medium is non-idle. Loss of carrier shall

result in the de-assertion of PHY_CRSDV synchronous to the cycle of

PHY_REFCLK, and only on 2-bit receive data boundaries.

General Programmable In/Out port [21]

Keypad column input [1], active low

PHY_RXERR /

GPIO [20] /

KPCOL [0]

IOS

Receive Data Error for Ethernet. It indicates a data error detected by PHY.The

assertion should be lasted for longer than a period of PHY_REFCLK. When

PHY_RXERR is asserted, the MAC will report a CRC error.

General programmable In/Out port [20]

Keypad column input [0], active low

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 15 - Revision A1

Table 5.1 W90N745 Pins Description, Continued

PIN NAME IO TYPE DESCRIPTION

AC97/I²S/PWM/UART3

AC97_nRESET /

I²S_MCLK /

GPIO [0] /

nIRQ [2] /

USB_PWREN

IOU

AC97 CODEC Host Interface RESET Output.

I²S CODEC Host Interface System Clock Output.

General Purpose In/Out port [0]

External interrupt request.

USB host power enable output

AC97_DATAI /

I²S_DATAI /

PWM [0] /

DTR3 /

GPIO [1]

IOU

AC97 CODEC Host Interface Data Input.

I²S CODEC Host Interface Data Input.

PWM Channel 0 output.

Data Terminal Ready for UART3.

General Purpose In /Out port [1]

AC97_DATAO /

I²S_DATAO /

PWM [1] /

DSR3 /

GPIO [2]

IOU

AC97 CODEC Host Interface Data Output.

I²S CODEC Host Interface Data Output.

PWM Channel 1 output.

Data Set Ready for UART3.

General Purpose In/Out port [2]

AC97_SYNC /

I²S_LRCLK /

PWM [2] /

TXD3 /

GPIO [3]

IOU

AC97 CODEC Host Interface Synchronous Pulse Output.

I²S CODEC Host Interface Left/Right Channel Select Clock.

PWM Channel 2 output.

Transmit Data for UART3.

General Purpose In/Out port [3]

AC97_BITCLK /

I²S_BITCLK /

PWM [3] /

RXD3 /

GPIO [4]

IOS

AC97 CODEC Host Interface Bit Clock Input.

I²S CODEC Host Interface Bit Clock.

PWM Channel 3 output.

Receive Data for UART3.

General Purpose In/Out port [4].

USB Interface

DP0 IO Differential Positive USB IO signal

DN0 IO Differential Negative USB IO signal

DP1 IO Differential Positive USB IO signal

DN1 IO Differential Negative USB IO signal

Miscellaneous

nIRQ [1:0] /

GPIO [17:16] /

USB_OVRCUR

IOU

External Interrupt Request

General Purpose I/O

nIRQ1 is used as USB host over-current detection input

nWDOG /

GPIO [15] /

USB_PWREN

IOU

Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low

General Purpose In/output

USB host power switch enable output

TEST IDS This test pin must be short to ground or left unconnected

W90N745CD/W90N745CDG

- 16 -

Table 5.1 W90N745 Pins Description, Continued

PIN NAME IO TYPE DESCRIPTION

I2C/USI

SCL0 /

SFRM /

TIMER0 /

GPIO [11]

IOU

I2C Serial Clock Line 0.

USI Serial Frame.

Timer0 time out output.

General Purpose In/Out port [11].

SDA0 /

SSPTXD /

TIMER1 /

GPIO [12]

IOU

I2C Serial Data Line 0

USI Serial Transmit Data

Timer1 time out output

General Purpose In/Out port [12]

SCL1 /

SCLK /

GPIO [13] /

KPROW [3]

IOU

I2C Serial Clock Line 1

USI Serial Clock

General Purpose In/Out port [13]

Keypad row scan output [3]

SDA1 /

SSPRXD /

GPIO [14] /

KPROW [2]

IDU

I2C Serial Data Line 1

USI Serial Receive Data

General Purpose In/Out port [14]

Keypad scan output [2]

UART0/UART1/UART2

TXD0 /

GPIO [5] IOU UART0 Transmit Data.

General Purpose In/Out [5]

RXD0 /

GPIO [6] IOU UART0 Receive Data.

General Purpose In/Out [6]

TXD1 /

GPIO [7] IOU UART1 Transmit Data.

General Purpose In/Out [7]

RXD1 /

GPIO [8] IOU UART1 Receive Data.

General Purpose In/Out [8]

CTS1/

TXD2(IrDA) /

PS2_CLK /

GPIO [9]

IOU

UART1 Clear To Send for Bluetooth application

UART2 Transmit Data supporting SIR IrDA.

PS2 Interface Clock Input/Output

General Purpose In/Out [9]

RTS1/

RXD2(IrDA) /

PS2_DATA /

GPIO [10]

IOU

UART1 Request To Send for Bluetooth application

UART2 Receive Data supporting SIR IrDA.

PS2 Interface Bi-Directional Data Line.

General Purpose In/Out [10]

XDMA

nXDREQ /

GPIO [19] / IO External DMA Request.

General Purpose In/Out [19]

nXDACK /

GPIO [18] / IO External DMA Acknowledgement.

General Purpose In/Out [18]

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 17 - Revision A1

Table 5.1 W90N745 Pins Description, Continued

PIN NAME IO TYPE DESCRIPTION

Power/Ground

VDD18 P Core Logic power (1.8V)

VSS18 G Core Logic ground (0V)

VDD33 P IO Buffer power (3.3V)

VSS33 G IO Buffer ground (0V)

USBVDD P USB power (3.3V)

USBVSS G USB ground (0V)

DVDD18 P PLL Digital power (1.8V)

DVSS18 G PLL Digital ground (0V)

AVDD18 P PLL Analog power (1.8V)

AVSS18 G PLL Analog ground (0V)

W90N745CD/W90N745CDG

- 18 -

Table 5.2 W90N745 128-pin LQFP Multi-function List

PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3

USB1.1 Host/Device Interface

1 USBVDD USBVDD - - -

2 DP1 DP1 - - -

3 DN1 DN1 - - -

4 USBVSS USBVSS - - -

5 USBVSS USBVSS - - -

6 DN0 DN0 - - -

7 DP0 DP0 - - -

8 USBVDD USBVDD - - -

9 VDD33 VDD33 - - -

UART[2:0]/PS2 Interface

10 GPIO[5] GPIO[5] UART_TXD0 - -

11 GPIO[6] GPIO[6] UART_RXD0 - -

12 GPIO[7] GPIO[7] UART_TXD1 - -

13 GPIO[8] GPIO[8] UART_RXD1 - -

14 GPIO[9] GPIO[9] UART_TXD2 UART_CTS1 PS2_CLK

15 GPIO[10] GPIO[10] UART_RXD2 UART_RTS1 PS2_DATA

16 VSS33 VSS33 - - -

I2C/USI Interface

17 GPIO[11] GPIO[11] I2C_SCL0 SSP_FRAM TIMER0

18 GPIO[12] GPIO[12] I2C_SDA0 SSP_TXD TIMER1

19 GPIO[13] GPIO[13] I2C_SCL1 SSP_SCLK KPI_ROW[3]

20 GPIO[14] GPIO[14] I2C_SDA1 SSP_RXD KPI_ROW[2]

21 VDD18 VDD18 - - -

22 VSS18 VSS18 - - -

23 VDD33 VDD33 - - -

24 VSS33 VSS33 - - -

System Reset & TEST

25 nRESET nRESET - - -

26 TEST TEST - - -

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 19 - Revision A1

Table 5.2 W90N745 128-pin LQFP Multi-function List , Continued

PLL Power/Ground

27 PLL_VDD18 PLL_VDD18 - - -

28 PLL_VSS18 PLL_VSS18 - - -

29 PLL_VSS18 PLL_VSS18 - - -

30 PLL_VDD18 PLL_VDD18 - - -

External IRQ[1:0]/USB Over Current

31 GPIO[16] GPIO[16] nIRQ [0] - -

32 GPIO[17] GPIO[17] nIRQ [1] USB_OVRCUR -

JTAG Interface

33 TMS TMS - - -

34 TDI TDI - - -

35 TDO TDO - - -

36 TCK TCK - - -

37 nTRST nTRST - - -

WatchDog/USB Power Enable

38 GPIO[15] GPIO[15] nWDOG USB_PWREN -

39 VSS33 VSS33 - - -

System Clock

40 EXTAL(15M) EXTAL(15M) - - -

41 XTAL(15M) XTAL(15M) - - -

42 VDD33 VDD33 - - -

43 VDD18 VDD18 - - -

W90N745CD/W90N745CDG

- 20 -

Table 5.2 W90N745 128-pin LQFP Multi-function List , Continued

PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3

AC97/I²S/PWM/UART3 Interface

44 GPIO[0] GPIO[0]

AC97_nRESET

I²SMCLK

nIRQ [2] USB_PWREN

45 GPIO[1] GPIO[1]

AC97_DATAI

I²SDATAI

PWM0 UART_DTR3

46 GPIO[2] GPIO[2]

AC97_DATAO

I²SDATAO

PWM1 UART_DSR3

47 GPIO[3] GPIO[3]

AC97_SYNC

I²SLRCLK

PWM2 UART_TXD3

48 GPIO[4] GPIO[4]

AC97_BITCLK

I²SBITCLK

PWM3 UART_RXD3

49 VDD18 VDD18 - - -

50 VSS18 VSS18 - - -

XDMAREQ

51 GPIO[19] GPIO[19] nXDREQ - -

52 GPIO[18] GPIO[18] nXDACK - -

Ethernet RMII/KeyPad Interface

53 GPIO[20] GPIO[20] PHY_RXERR KPI_COL[0] -

54 GPIO[21] GPIO[21] PHY_CRSDV KPI_COL[1] -

55 GPIO[22] GPIO[22] PHY_RXD[0] KPI_COL[2] -

56 VSS33 VSS33 - - -

57 GPIO[23] GPIO[23] PHY_RXD[1] KPI_COL[3] -

58 GPIO[24] GPIO[24] PHY_REFCLK KPI_COL[4] -

59 GPIO[25] GPIO[25] PHY_TXEN KPI_COL[5] -

60 GPIO[26] GPIO[26] PHY_TXD[0] KPI_COL[6] -

61 VDD33 VDD33 - - -

62 GPIO[27] GPIO[27] PHY_TXD[1] KPI_COL[7] -

63 GPIO[28] GPIO[28] PHY_MDIO KPI_ROW[0]

64 GPIO[29] GPIO[29] PHY_MDC KPI_ROW[1]

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 21 - Revision A1

Table 5.2 W90N745 128-pin LQFP Multi-function List, Continued

NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3

Memory Address/Data/Control

65 A[0] A[0] - - -

66 A[1] A[1] - - -

67 A[2] A[2] - - -

68 A[3] A[3] - - -

69 A[4] A[4] - - -

70 VSS33 VSS33 - - -

71 A[5] A[5] - - -

72 A[6] A[6] - - -

73 A[7] A[7] - - -

74 A[8] A[8] - - -

75 A[9] A[9] - - -

76 VDD33 VDD33 - - -

77 A[10] A[10] - - -

78 A[11] A[11] - - -

79 A[12] A[12] - - -

80 A[13] A[13] - - -

81 VSS18 VSS18 - - -

82 A[14] A[14] - - -

83 A[15] A[15] - - -

84 A[16] A[16] - - -

85 VDD18 VDD18 - - -

86 A[17] A[17] - - -

87 A[18] A[18] - - -

88 A[19] A[19] - - -

89 A[20] A[20] - - -

90 nECS[3] nECS[3] - - -

91 VSS33 VSS33 - - -

W90N745CD/W90N745CDG

- 22 -

Table 5.2 W90N745 128-pin LQFP Multi-function List, Continued

NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3

Memory Address/Data/Control

92 nECS[2] nECS[2] - - -

93 nECS[1] nECS[1] - - -

94 nECS[0] nECS[0] - - -

95 nOE nOE - - -

96 nWAIT GPIO[30] nWAIT nIRQ [3] -

97 nBTCS nBTCS - - -

98 MCKE MCKE - - -

99 nSCS[0] nSCS[0] - - -

100 nSCS[1] nSCS[1] - - -

101 nSRAS nSRAS - - -

102 nSCAS nSCAS - - -

103 VDD33 VDD33 - - -

104 MCLK MCLK - - -

105 VSS33 VSS33 - - -

106 nSWE nSWE - - -

107 nWBE/SDQM[0]

nWBE or SDQM[0]

108 nWBE/SDQM[1]

nWBE or SDQM[1]

109 VSS18 VSS18 - - -

110 D[15] D[15] - - -

111 D[14] D[14] - - -

112 VDD18 VDD18 - - -

113 D[13] D[13] - - -

114 D[12] D[12] - - -

115 D[11] D[11] - - -

116 D[10] D[10] - - -

117 VDD33 VDD33 - - -

118 D[9] D[9] - - -

119 D[8] D[8] - - -

120 D[7] D[7] - - -

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 23 - Revision A1

Table 5.2 W90N745 128-pin LQFP Multi-function List, Continued

PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3

Memory Address/Data/Control

121 D[6] D[6] - - -

122 D[5] D[5] - - -

123 VSS33 VSS33 - - -

124 D[4] D[4] - - -

125 D[3] D[3] - - -

126 D[2] D[2] - - -

127 D[1] D[1] - - -

128 D[0] D[0] - - -

W90N745CD/W90N745CDG

- 24 -

6. BLOCK DIAGRAM

ARM7TDMI

Clock

Synthesizer

Cache

Controller

4KB

I-Cache 4KB

D-Cache

Wrapper

Power

Management

Unit

External Bus

Interface

Ethernet MAC

Controller

USB 1.1 Host

Controller

USB 1.1 Device

Controller

Clock

Synthesizer

2-Channel GDMA

AHB

Arbiter

AHB

Decoder

APB

Bridge

2 Timers

Advanced

Interrupt

Controller

Watch-Dog

Timer

I2C(x2)/USI

UART (x4) with

IrDA/Bluetooth/

Micro-printer

2-channel AC97/I2S

4-Channels

PWM

31 GPIOs

PLL

PHY

PLL

W90N745

Block Diagram

JTAG

ICE

* 15MHz

* Host/Device

PHY RMII Bus

TDMI Bus

APB Bus

AHB Bus

PS/2 Keyboard

Host Interface

Keypad

Controller

Fig 6.1 W90N745 Functional Block Diagram

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 25 - Revision A1

7. FUNCTIONAL DESCRIPTION

7.1 ARM7TDMI CPU CORE

The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of general-

purpose 32-bit microprocessors, which offer high performance for very low power consumption. The

architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and

related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set

Computers. Pipelining is employed so that all parts of the processing and memory systems can operate

continuously. The high instruction throughput and impressive real-time interrupt response are the major

benefits.

The ARM7TDMI CPU core has two instruction sets:

(1) The standard 32-bit ARM set

(2) A 16-bit THUMB set

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core

while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit

registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent

interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding

32-bit ARM instruction with the same effect on the processor model.

ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers

are used to speed up exception processing. All the register specified in ARM instructions can address

any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt,

memory aborts, attempted execution of an undefined instruction and software interrupts.

Address Register

Address

Incrementer

Barrel Shifter

(31 x 32-bit registers)

(6 status registers)

32 x8 Multiplier

32-bit ALU

Writer Data

Instruction Pipeline

Read Data Register

Thumb Instruction Decoder

Instruction Decoder

Control Logic

Scan Control

B Bus

A Bus

ALU Bus

PC Bus

Incrementer Bus

A[31:0]

D[31:0]

Fig 7.1 ARM7TDMI CPU Core Block Diagram

W90N745CD/W90N745CDG

- 26 -

7.2 System Manager

7.2.1 Overview

The W90N745 system manager has the following functions.

System memory map

Data bus connection with external memory

Product identifier register

Bus arbitration

PLL module

Clock select and power saving control register

Power-On setting

7.2.2 System Memory Map

W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The

On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the On-

Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable

space:0x0000_0000~0x7FDF_FFFF if Cache ON; non-cacheable space:

0x8000_0000~0xFFDF_FFFF).

The size and location of each bank is determined by the register settings for “current bank base address

pointer” and “current bank size”. Please note that when setting the bank control registers, the address

boundaries of consecutive banks must not overlap.

Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You

can use bank control registers to assign a specific bank start address by setting the bank’s base pointer

(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<

18” and the bank’s size is “current bank size”.

In the event of an access requested to an address outside any programmed bank size, an abort signal is

generated. The maximum accessible memory size of each external IO bank is 4M bytes (by word

format), and 64M bytes on each SDRAM bank.

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 27 - Revision A1

ROM/FLASH

256KB - 4MB

SDRAM Bank 0

2MB - 64MB

SDRAM Bank 1

2MB - 64MB

External I/O Bank 0

256KB - 4MB

External I/O Bank 1

256KB - 4MB

External I/O Bank 2

256KB - 4MB

External I/O Bank 3

256KB - 4MB

RESERVED

8KB

512KB

(Fixed)

0x7FF8.0000

0x0000_0000

0x7FFF_FFFF

RESERVED

0x7FE0_0000

RESERVED

512KB

(Fixed)

0x7FF0_0000

EBI Space

ROM/FLASH

256KB - 4MB

SDRAM Bank 0

2MB - 64MB

SDRAM Bank 1

2MB - 64MB

External I/O Bank 0

256KB - 4MB

External I/O Bank 1

256KB - 4MB

External I/O Bank 2

256KB - 4MB

External I/O Bank 3

256KB - 4MB

On-Chip RAM

4KB,4KB

On-Chip APB

Peripherals

8KB

512KB

(Fixed)

0xFFF8_0000

0x8000_0000

0xFFFF_FFFF

RESERVED

0xFFE0_0000

On-Chip AHB

Peripherals

512KB

(Fixed)

0xFFF0_0000

EBI Space

Fig7.2.1 System Memory Map

W90N745CD/W90N745CDG

- 28 -

Table 7.2.1 On-Chip Peripherals Memory Map

BASE ADDRESS DESCRIPTION

AHB Peripherals

0xFFF0_0000 Product Identifier Register (PDID)

0xFFF0_0004 Arbitration Control Register (ARBCON)

0xFFF0_0008 PLL Control Register 0(PLLCON0)

0xFFF0_000C Clock Select Register (CLKSEL)

0xFFF0_0010 PLL Control Register 1 (PLLCON1)

0xFFF0_0014 Audio I²S Clock Control Register (I²SCKCON)

0xFFF0_0020 IRQ Wakeup Control Register (IRQWAKEUPCON)

0xFFF0_0024 IRQ Wakeup Flag Register (IRQWAKEFLAG)

0xFFF0_0028 Power Manager Control Register (PMCON)

0xFFF0_0030 USB Transceiver Control Register (USBTXRCON)

0xFFF0_1000 EBI Control Register (EBICON) Control Registers

0xFFF0_1004 ROM/FLASH (ROMCON) Control Registers

0xFFF0_1008 SDRAM bank 0 – 1 Control Registers

0xFFF0_1018 External I/O 0 – 3 Control Registers

0xFFF0_2000 Cache Controller Control Registers

0xFFF0_3000 Ethernet MAC Controller Control Registers

0xFFF0_4000 GDMA 0 – 1 Control Registers

0xFFF0_5000 USB Host Controller Control Registers

0xFFF0_6000 USB Device Controller Control Registers

0xFFF0_9000 AC97/I²S Controller Control Registers

APB Peripherals

0xFFF8_0000 UART 0 (Tx, RX for console)

0xFFF8_0100 UART 1 (Tx, Rx, for bluetooth)

0xFFF8_0200 UART 2 (bluetooth CTS, RTS/ IrDA Tx, Rx)

0xFFF8_0300 UART 3 (micro-print DTR, DTS, Tx, Rx)

0xFFF8_1000 Timer 0 – 1, WDOG Timer

0xFFF8_2000 Interrupt Controller

0xFFF8_3000 GPIO

0xFFF8_6000 I2C-0 Control Registers

0xFFF8_6100 I2C-1 Control Registers

0xFFF8_6200 USI Control Registers

0xFFF8_7000 Pulse Width Modulation (PWM) Control Registers

0xFFF8_8000 KeyPad Interface Control Register (KPI)

0xFFF8_9000 PS2 Control Registers

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 29 - Revision A1

7.2.3 Address Bus Generation

The W90N745 address bus generation is depended on the required data bus width of each memory

bank. The data bus width is determined by DBWD bits in each bank’s control register.

The maximum accessible memory size of each external IO bank is 4M bytes.

Table 7.2.2 Address Bus Generation Guidelines

DATA BUS EXTERNAL ADDRESS PINS

WIDTH A [20:0]

MAXIMUM ACCESSIBLE MEMORY SIZE

8-bit A20 – A0

(Internal) 2M bytes

16-bit A21 – A1

(Internal) 2M half-words

7.2.4 Data Bus Connection with External Memory

7.2.4.1. Memory formats

The W90N745 can be configured as big endian or little endian mode by pull up or down the external data

bus D14 pin. If D14 is pull up, then it is a little endian mode, otherwise, it is a big endian mode.

Little endian

In little endian format, the lowest addressed byte in a word is considered the least significant byte of the

word and the highest addressed byte is the most significant. So the byte at address 0 of the memory

system connects to data lines 7 through 0.

For a word aligned address A, Fig7.2.2 shows how the half-word at addresses A and A+2, and the bytes

at addresses A, A+1, A+2, and A+3 map on to each other when D14 pin is High.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Half-word at address A

Half-word at address A+2

Byte at address A+1 Byte at address A

Byte at address A+3 Byte at address A+2

Fig7.2.2 Little endian addresses of bytes and half-words within half words

W90N745CD/W90N745CDG

- 30 -

Big endian

In Big endian format, the W90N745 stores the most significant byte of a word at the lowest numbered

byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory

system connects to data lines 31 through 24.

For a word aligned address A, Fig7.2.3 shows how the half-word at addresses A and A+2, and the bytes

at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low.

15 14 13 12 1110987654321 0

Half-word at address A

Half-word at address A+2

Byte at address A Byte at address A+1

Byte at address A+2 Byte at address A+3

Fig7.2.3 Big endian addresses of bytes and half-words within half words

7.2.4.2. Connection of External Memory with Various Data Width

The system diagram for W90N745 connecting with the external memory is shown in Fig7.2.4. Below

tables (Table7.2.3 through Table7.2.14) show the program/data path between CPU register and the

external memory using little / big endian and word/half-word/byte access.

Fig7.2.4 Address/Data bus connection with external memory

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 31 - Revision A1

Fig7.2.5 CPU registers Read/Write with external memory

Table 7.2.3 and Table 7.2.4

Using big-endian and word access, Program/Data path between register and external memory

WA = Address whose LSB is 0,4,8,C X = Don’t care

nWBE [1-0] / SDQM [1-0] = A means active and U means inactive

Table7.2.3 Word access write operation with Big Endian

ACCESS

OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg

Data

31 0

ABCD 31 0

ABCD

SA WA WA

Bit Number

SD 31 0

AB CD 31 0

A B C D

Bit Number

ED 15 0

AB 15 0

CD 7 0

A 7 0

B 7 0

C 7 0

XA WA WA+2 WA WA+1 WA+2 WA+3

nWBE [1-0]

SDQM [1-0] AA AA XA XA XA XA

Bit Number

XD 15 0

AB 15 0

CD 7 0

A 7 0

B 7 0

C 7 0

Bit Number

Ext. Mem

Data

15 0

AB 15 0

CD 7 0

A 7 0

B 7 0

C 7 0

Timing

Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write

W90N745CD/W90N745CDG

- 32 -

Table7.2.4 Word access read operation with Big Endian

ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg Data 31 0

CDAB 31 0

DCBA

SA WA WA

Bit Number

SD 31 0

CD AB 31 0

D C B A

Bit Number

ED 31 0

CD XX 31 0

CD AB 31 0

D X X X 31 0

D C X X 31 0

D C B X 31 0

D C B A

XA WA WA+2 WA WA+1 WA+2 WA+3

SDQM [1-0] AA AA XA XA XA XA

Bit Number

XD 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

Bit Number

Ext. Mem Data 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

Timing Sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read

Table 7.2.5 and Table 7.2.6

Using big-endian and half-word access, Program/Data path between register and external memory.

HA = Address whose LSB is 0,2,4,6,8,A,C,E X = Don’t care

nWBE [1-0] / SDQM [1-0] = A means active and U means inactive

Table7.2.5 Half-word access write operation with Big Endian

ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg Data 31 0

ABCD 31 0

ABCD

SA HA HA

Bit Number

SD 31 0

CD CD 31 0

CD CD

Bit Number

ED 31 0

CD CD 7 0

C 7 0

XA HA HA HA+1

nWBE [1-0] /

SDQM [1-0] AA XA XA

Bit Number

XD 15 0

CD 7 0

C 7 0

Bit Number

Ext. Mem Data 15 0

CD 7 0

C 7 0

Timing Sequence 1st write 2nd write

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 33 - Revision A1

Table7.2.6 Half-word access read operation with Big Endian

ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg Data 15 0

CD 15 0

SA HA HA

Bit Number

SD 15 0

CD 15 0

Bit Number

ED 15 0

CD 15 0

DX 15 0

XA HA HA HA+1

SDQM [1-0] AA XA XA

Bit Number

XD 15 0

CD 7 0

D 7 0

Bit Number

Ext. Mem Data 15 0

CD 7 0

D 7 0

Timing Sequence 1st read 2nd read

Table 7.2.7 and Table 7.2.8

Using big-endian and byte access, Program/Data path between register and external memory.

BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F

W90N745CD/W90N745CDG

- 34 -

Table7.2.7 Byte access write operation with Big Endian

ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg Data 31 0

ABCD 31 0

ABCD

SA BAL BAU BA

Bit Number

SD 31 0

D D D D 31 0

D D D D

Bit Number

ED 15 8

D 7 0

XA BAL BAL BA

nWBE [1-0] /

SDQM [1-0] AU UA XA

Bit Number

XD 15 0

D X 15 0

X D 7 0

Bit Number

Ext. Mem Data 15 8

D 7 0

Timing Sequence

Table7.2.8 Byte access read operation with Big Endian

ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg Data 7 0

C 7 0

D 7 0

SA BAL BAU BA

Bit Number

SD 7 0

C 7 0

D 7 0

Bit Number

ED 7 0

C 15 8

D 7 0

XA BAL BAL BA

SDQM [1-0] AU UA XA

Bit Number

XD 15 0

CD 15 0

CD 7 0

Bit Number

Ext. Mem Data 15 0

CD 7 0

Timing Sequence

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 35 - Revision A1

Table 7.2.9 and Table 7.2.10

Using little-endian and word access, Program/Data path between register and external memory

WA = Address whose LSB is 0,4,8,C X = Don’t care

nWBE [1-0] / SDQM [1-0] = A means active and U means inactive

Table7.2.9 Word access write operation with little Endian

ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)

XD WIDTH HALF WORD BYTE

Bit Number

CPU Reg Data 31 0

ABCD 31 0

ABCD

SA WA WA

Bit Number

SD 31 0

AB CD 31 0

A B C D

Bit Number

ED 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

XA WA WA+2 WA WA+1 WA+2 WA+3

nWBE [1-0] /

SDQM [1-0] AA AA XA XA XA XA

Bit Number

XD 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

Bit Number

Ext. Mem Data 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write

Table7.2.10 Word access read operation with Little Endian

Access Operation Read Operation (CPU Register Í External Memory)

XD Width Half Word Byte

Bit Number

CPU Reg Data 31 0

ABCD 31 0

ABCD

SA WA WA

Bit Number

SD 31 0

AB CD 31 0

A B C D

Bit Number

ED 31 0

XX CD 31 0

AB CD 31 0

X X X D 31 0

X X C D 31 0

X B C D 31 0

A B C D

XA WA WA+2 WA WA+1 WA+2 WA+3

SDQM [1-0] AA AA XA XA XA XA

Bit Number

XD 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

Bit Number

Ext. Mem Data 15 0

CD 15 0

AB 7 0

D 7 0

C 7 0

B 7 0

Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write

W90N745CD/W90N745CDG

- 36 -

Table 7.2.11 and Table 7.2.12

Using little-endian and half-word access, Program/Data path between register and external memory.

HA = Address whose LSB is 0,2,4,6,8,A,C,E X = Don’t care

nWBE [1-0] / SDQM [1-0] = A means active and U means inactive

Table7.2.11 Half-word access write operation with little Endian

Access Operation Write Operation (CPU Register Î External Memory)

XD Width Half Word Byte

Bit Number

CPU Reg Data 31 0

ABCD 31 0

ABCD

SA HA HA

Bit Number

SD 31 0

CD CD 31 0

CD CD

Bit Number

ED 31 0

CD CD 7 0

D 7 0

XA HA HA HA+1

nWBE [1-0] /

SDQM [1-0] AA XA XA

Bit Number

XD 15 0

CD 7 0

D 7 0

Bit Number

Ext. Mem Data 15 0

CD 7 0

D 7 0

Timing Sequence 1st write 2nd write

Table7.2.12 Half-word access read operation with Little Endian

Access Operation Read Operation (CPU Register Í External Memory)

XD Width Half Word Byte

Bit Number

CPU Reg Data 15 0

CD 15 0

SA HA HA

Bit Number

SD 15 0

CD 15 0

Bit Number

ED 15 0

CD 15 0

XD 15 0

XA HA HA HA+1

SDQM [1-0] AA XA XA

Bit Number

XD 15 0

CD 7 0

D 7 0

Bit Number

Ext. Mem Data 15 0

CD 7 0

D 7 0

Timing Sequence 1st read 2nd read

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 37 - Revision A1

Table 7.2.13 and Table 7.2.14

Using little-endian and byte access, Program/Data path between register and external memory.

BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F

Table7.2.13 Byte access write operation with little Endian

Access Operation Write Operation (CPU Register Î External Memory)

XD Width Half Word Byte

Bit Number

CPU Reg Data 31 0

ABCD 31 0

ABCD

SA BAL BAU BA

Bit Number

SD 31 0

D D D D 31 0

D D D D

Bit Number

ED 7 0

D 15 8

D 7 0

XA BAL BAL BA

nWBE [1-0] /

SDQM [1-0] UA AU XA

Bit Number

XD 15 0

X D 15 0

D X 7 0

Bit Number

Ext. Mem Data 7 0

D 15 8

D 7 0

Timing Sequence

Table7.2.14 Byte access read operation with Little Endian

Access Operation Read Operation (CPU Register Í External Memory)

XD Width Half Word Byte

Bit Number

CPU Reg Data 7 0

D 7 0

C 7 0

SA BAL BAU BA

Bit Number

SD 7 0

D 7 0

C 7 0

Bit Number

ED 7 0

D 7 0

C 7 0

XA BAL BAL BA

SDQM [1-0] UA AU XA

Bit Number

XD 15 0

CD 15 0

CD 7 0

Bit Number

Ext. Mem Data 15 0

CD 7 0

Timing Sequence

W90N745CD/W90N745CDG

- 38 -

7.2.5 Bus Arbitration

The W90N745’s internal function blocks or external devices can request mastership of the system bus

and then hold the system bus in order to perform data transfers. Because the design of W90N745 bus

allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal

units or external devices simultaneously request bus mastership. When bus mastership is granted to an

internal function block or an external device, other pending requests are not acknowledged until the

previous bus master has released the bus.

W90N745 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode,

depends on the ARBCON register PRTMOD bit setting.

7.2.5.1. Fixed Priority Mode

In Fixed Priority Mode (PRTMOD=0, default value), to facilitate bus arbitration, priorities are assigned to

each internal W90N745 function block. The bus controller arbitration requests for the bus mastership

according to these fixed priorities. In the event of contention, mastership is granted to the function block

with the highest assigned priority. These priorities are listed in Table 7.2.15.

W90N745 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit 1

of the Arbitration Control Register (ARBCON), is set to “0”, the priority of ARM Core is fixed to lowest.

If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still lowest

and the IPACT=0, Bit 2 of the Arbitration Control Register (ARBCON) ； If there is an unmasked

interrupt request, then the ARM Core’s priority is raised to first and IPACT=1.

If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an

alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in

the interrupt handler. The IPACT bit can be read and written. Writing with “0”, the IPACT bit is cleared,

but it will be no effect as writing with “1”.

Table 7.2.15 Bus Priorities for Arbitration in Fixed Priority Mode

BUS FUNCTION BLOCK

PRIORITY IPACT = 0 IPEN = 1 AND IPACT = 1

1 (Highest) Audio Controller (AC97 & I²S) ARM Core

2 General DMA0 Audio Controller (AC97 & I²S)

3 General DMA1 General DMA0

4 EMC DMA General DMA1

5 USB Host EMC DMA

6 USB Device USB Host

7(Lowest) ARM Core USB Device

7.2.5.2. Rotate Priority Mode

In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored).

W90N745 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain

the bus and that a retracted master does not lock up the bus.

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 39 - Revision A1

7.2.6 Power Management

W90N745 provide three power management scenarios to reduce power consumption. The

peripherals’ clocks can be enabled / disabled individually by controlling the co-responding bit in

CLKSEL control register. Software can turn-off the unused modules’ clocks to saving the unnecessary

power consumption. It also provides idle and power-down modes to reduce power consumption.

Fig. 7.2.6 W90N745 system clock generation diagram

W90N745CD/W90N745CDG

- 40 -

IDLE MODE

If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source

will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock

to cache controller and ARM are stopped. W90N745 will exit idle state when nIRQ or nFIQ from any

peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also

be forced to enter idle state if both MIDLE and IDLE bits are set. Software must switch SDRAM into

self-refresh mode before forcing memory to enter idle mode.

FOUT

(PLL)

HCLK

idle_state

MCLK

(ARM)

HCLK

(cache)

IDLE Period

HCLK

(memc)

Case1. IDLE=1, PD=0, MIDLE=0

Fig. 7.2.7 Clock management for system idle mode

FOUT

(PLL)

HCLK

idle_state

MCLK

(ARM)

HCLK

(cache)

IDLE Period

HCLK

(memc)

Case2. IDLE=1, PD=0, MIDLE=1

Fig. 7.2.8 Clock management for system and memory idle mode

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 41 - Revision A1

Power Down Mode

This mode provides the minimum power consumption. When the W90N745 system is not working or

waiting an external event, software can write PD bit “1” to turn off all the clocks includes system crystal

oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode

since the clock source is stopped. W90N745 will exit power down state when nIRQ/nFIQ is detected.

W90N745 provides external interrupt nIRQ[1:0], keypad, and USB device interfaces to wakeup the

system clock.

HCLK

(cache)

Case3. IDLE=0, PD=1, MIDLE=0

EXTAL

idle _state

pd_state

65536 clocks

HCLK

wake up by pheripheral's

interrupts

Fig 7.2.9 Clock management for system power down mode and wake up

W90N745CD/W90N745CDG

- 42 -

7.2.7 Power-On Setting

After power on reset, there are eight Power-On setting pins to configure W90N745 system configuration.

POWER-ON SETTING PIN

Internal System Clock Select D15

Little/Big Endian Mode Select D14

Boot ROM/FLASH Data Bus Width D [13:12]

Default: Pull-Down in Normal Operation D9

Default: Pull-Up in Normal Operation D8

D15 pin：Internal System Clock Select

If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock.

If pin D15 is pull-up, the PLL output clock is used as internal system clock.

D14 pin：Little/Big Endian Mode Select

If pin D14 is pull-down, the external memory format is Big Endian mode.

If pin D14 is pull-up, the external memory format is Little Endian mode.

D [13:12] ： Boot ROM/FLASH Data Bus Width

D [13:12] BUS WIDTH

Pull-down Pull-down 8-bit

Pull-down Pull-up 16-bit

Pull-up Pull-down RESERVED

Pull-up Pull-up RESERVED

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 43 - Revision A1

7.2.8 System Manager Control Registers Map

PDID 0xFFF0_0000 R Product Identifier Register 0xX090_0745

ARBCON 0xFFF0_0004 R/W Arbitration Control Register 0x0000_0000

PLLCON0 0xFFF0_0008 R/W PLL Control Register 0 0x0000_2F01

CLKSEL 0xFFF0_000C R/W Clock Select Register 0x1FFF_3FX8

PLLCON1 0xFFF0_0010 R/W PLL Control Register 1 0x0001_0000

I²SCKCON 0xFFF0_0014 R/W Audio I²S Clock Control Register 0x0000_0000

IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register 0x0000_0000

IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register 0x0000_0000

PMCON 0xFFF0_0028 R/W Power Manager Control Register 0x0000_0000

USBTxrCON 0xFFF0_0030 R/W USB Transceiver Control Register 0x0000_0000

W90N745CD/W90N745CDG

- 44 -

Product Identifier Register （PDID）

This register is read only and lets software can use it to recognize certain characteristics of the chip ID

and the version number.

PDID 0xFFF0_0000 R Product Identifier Register 0xX090_0745

31 30 29 28 27 26 25 24

PACKAGE VERSION

23 22 21 20 19 18 17 16

CHPID

15 14 13 12 11 10 9 8

CHPID

7 6 5 4 3 2 1 0

CHPID

BITS DESCRIPTION

[31:30] PACKAGE

Package Type Select

These two bits are power-on setting latched from pin D[9:8]

Package [31:30] Package Type

0 1 128-pin Package

[29:24] VERSION

Version of chip

[23:0] CHIPID

The chip identifier of W90N745 is 0x090.0745

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 45 - Revision A1

Arbitration Control Register (ARBCON)

ARBCON 0xFFF0_0004 R/W

Arbitration Control Register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED IPACT IPEN PRTMOD

BITS DESCRIPTION

[31:3] RESERVED -

[2] IPACT

Interrupt priority active.

When IPEN=”1”, this bit will be set when the ARM core has an

unmasked interrupt request. This bit is available only when the

PRTMOD=0.

[1] IPEN

Interrupt priority enable bit

0 = the ARM core has the lowest priority.

1 = enable to raise the ARM core priority to second

This bit is available only when the PRTMOD=0.

[0] PRTMOD

Priority mode select

0 = Fixed Priority Mode (default)

1 = Rotate Priority Mode

W90N745CD/W90N745CDG

- 46 -

PLL Control Register0 （PLLCON0）

W90N745 provides two clock generation options – crystal and oscillator. The external clock via

EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the

PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock

for the internal system clock, D15 pin must be pull-up.

PLLCON 0xFFF0_0008 R/W

PLL Control Register 0x0000_2F01

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED PWDEN

15 14 13 12 11 10 9 8

FBDV

7 6 5 4 3 2 1 0

FBDV OTDV INDV

BITS DESCRIPTION

[31:17] RESERVED -

[16] PWDEN

Power down mode enable

0 = PLL is in normal mode (default)

1 = PLL is in power down mode

[15:7] FBDV

PLL VCO output clock feedback divider

Feedback Divider divides the output clock from VCO of PLL.

[6:5] OTDV

PLL output clock divider

OTDV [6:5] DIVIDED BY

0 0 1

0 1 2

1 0 2

1 1 4

[4:0] INDV

PLL input clock divider

Input divider divides the input reference clock into the PLL.

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 47 - Revision A1

Input Divider

(NR)

PFD

Feedback

Divider

(NF)

Charge

Pump VCO Output

Divider

(NO) Clock

Divider

Selector

EXTAL

ECLKS

OTDV[1:0] CLKS[2:0]

PLL

Internal

System

Clock

INDV[4:0]

FBDV[8:0]

48MHz

Gen

480MHz

USBCKS

USB

Module

FIN

FOUT

GP0

Fig 7.2.8.1 System PLL block diagram

The formula of output clock of PLL is:

FOUT = FIN N

NF 1

∗∗

FOUT：Output clock of Output Divider

FIN：External clock into the Input Divider

NR：Input divider value (NR = INDV + 2)

NF：Feedback divider value (NF = FBDV + 2)

NO：Output divider value (NO = OTDV)

W90N745CD/W90N745CDG

- 48 -

Clock Select Register (CLKSEL)

CLKSEL 0xFFF0_000C R/W

Clock Select Register 0x1FFF_7FX8

31 30 29 28 27 26 25 24

RESERVED PS2 KPI RESERVED SSP

23 22 21 20 19 18 17 16

UART3 UART2 UART1 I2C1 I2C0 RESERVE

D PWM AC97

15 14 13 12 11 10 9 8

USBCKS USBD GDMA RESERVED EMC RESERVED WDT

7 6 5 4 3 2 1 0

USBH TIMER UART ECLKS CLKS RESET

BITS DESCRIPTION

[31:29] RESERVED -

[28] PS2

PS2 controller clock enable bit

0 = Disable PS2 controller clock

1 = Enable PS2 controller clock

[27] KPI

Keypad controller clock enable bit

0 = Disable keypad controller clock

1 = Enable keypad controller clock

[26] RESERVED

[25] RESERVED

[24] USI

USI controller clock enable bit

0 = Disable USI controller clock

1 = Enable USI controller clock

[23] UART3

UART3 controller clock enable bit

0 = Disable UART3 controller clock

1 = Enable UART3 controller clock

[22] UART2

UART2 controller clock enable bit

0 = Disable UART2 controller clock

1 = Enable UART2 controller clock

[21] UART1

UART1 controller clock enable bit

0 = Disable UART1 controller clock

1 = Enable UART1 controller clock

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 49 - Revision A1

Continued.

BITS DESCRIPTION

[20] I2C1

I2C1 controller clock enable bit

0 = Disable I2C1 controller clock

1 = Enable I2C1 controller clock

[19] I2C0

I2C0 controller clock enable bit

0 = Disable I2C0 controller clock

1 = Enable I2C0 controller clock

[18] RESERVED

[17] PWM

PWM controller clock enable bit

0 = Disable PWM controller clock

1 = Enable PWM controller clock

[16] AC97

Audio Controller clock enable bit

0 = Disable AC97 controller clock

1 = Enable AC97 controller clock

[15] USBCKS

USB host/device 48MHz clock source Select bit

0 = USB clock 48MHz input from internal PLL (480MHz/10)

1 = USB clock 48MHz input from external GPIO0 pin, this pin

direction must set to input.

[14] USBD

USB device clock enable bit

0 = Disable USB device controller clock

1 = Enable USB device controller clock

[13] GDMA

GDMA controller clock enable bit

0 = Disable GDMA clock

1 = Enable GDMA clock

[12] RESERVED

[11] RESERVED

[10] EMC

EMC controller clock enable bit

0 = Disable EMC controller clock

1 = Enable EMC controller clock

[9] RESERVED

[8] WDT

WDT clock enable bit

0 = Disable WDT counting clock

1 = Enable WDT counting clock

W90N745CD/W90N745CDG

- 50 -

Continued.

BITS DESCRIPTION

[7] USBH

USB host clock enable bit

0 = Disable USB host controller clock

1 = Enable USB host controller clock

[6] TIMER

Timer clock enable bit

0 = Disable timer clock

1 = Enable timer clock

[5] UART0

UART0 controller clock enable bit

0 = Disable UART0 controller clock

1 = Enable UART0 controller clock

[4] ECLKS

External clock select

0 = External clock from EXTAL pin is used as system clock

1 = PLL output clock is used as system clock

After power on reset, the content of ECLKS is the Power-On

Setting value. You can program this bit to change the system clock

source.

[3:1] CLKS

PLL output clock select

CLKS [3:1] System clock

0 0 0 58.594 KHz*

0 0 1 24 MHz

0 1 0 48 MHz

0 1 1 60 MHz

1 0 0 80 MHz

1 0 1 RESERVED

1 1 0 RESERVED

1 1 1 RESERVED

Note:

1. This values are based on PLL output(FOUT) is 480MHz.

2. When 24Mhz ~ 80MHz is selected, the ECLKS bit must be set to

3. About 58.594KHz setting, two steps are needed. First, clear

ECLKS bit, and then clear CLKS.

[0] RESET

Software Reset bit

This is a software reset control bit. Set logic 1 to generate an

internal reset pulse. This bit is auto-clear to logic 0 at the end of

the reset pulse.

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 51 - Revision A1

PLL Control Register 1（PLLCON1）

W90N745 provides extra PLL to provide 12.288/16.934 MHz clock source to Audio Controller. It uses the

same 15MHz crystal clock input source with system PLL mentioned above.

PLLCON1 0xFFF0_0010 R/W

PLL Control Register 1 0x0001_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED PWDEN1

15 14 13 12 11 10 9 8

FBDV1

7 6 5 4 3 2 1 0

FBDV1 OTDV1 INDV1

BITS DESCRIPTION

[31:17] RESERVED -

[16] PWDEN1

PLL1 power down enable

0 = PLL1 is in normal mode

1 = PLL1 is in power down mode (default)

[15:7] FBDV1

PLL1 VCO output clock feedback divider

Feedback Divider divides the output clock from VCO of PLL1.

[6:5] OTDV1

PLL1 output clock divider

OTDV1 [6:5] Divided by

0 0 1

0 1 2

1 0 2

1 1 4

[4:0] INDV1 PLL1 input clock divider

Input divider divides the input reference clock into the PLL1.

W90N745CD/W90N745CDG

- 52 -

Input Divider

(NR)

PFD

Feedback

Divider

(NF)

Charge

Pump VCO Output

Divider

(NO)

EXTAL

OTDV1[1:0]

PLL1

INDV1[4:0]

FBDV1[8:0]

480MHz

FIN

FOUT to Audio Controller

Fig 7.2.8.2 Audio PLL block diagram

The formula of output clock of PLL is:

FOUT = FIN N

NF 1

∗∗

FOUT：Output clock of Output Divider

FIN：External clock into the Input Divider

NR：Input divider value (NR = INDV1 + 2)

NF：Feedback divider value (NF = FBDV1 + 2)

NO：Output divider value (NO = OTDV1)

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 53 - Revision A1

I²S Clock Control Register (I²SCKCON)

I²SCKCON 0xFFF0_0014 R/W

I²S PLL clock Control Register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED I²SPLLEN

7 6 5 4 3 2 1 0

PRESCALE

BITS DESCRIPTION

[31:9] RESERVED -

[8] I²SPLLEN

I²S PLL clock source enable

Set this bit will enable PLL1 clock output to audio I²S clock input.

1 = Enable PLL1 clock source for audio I²S

0 = Disable PLL1 clock source for audio I²S

[7:0] PRESCALE

The PLL1 is used by I²S, if in use, software can using this

prescaler to generate an appropriate clock nearly 12.288M or

16.934M. The clock is generated as below, and if PRESCALE =0,

the PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO =

PLL_FOUT/(PRESCALE +1)”

W90N745CD/W90N745CDG

- 54 -

IRQ Wakeup Control Register (IRQWAKECON)

IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control Register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED IRQWAKEUPPOL RESERVED IRQWAKEUPEN

BITS DESCRIPTION

[31:6] RESERVED

[5] IRQWAKEUPPOL[1]

nIRQ1 wake up polarity

1 = nIRQ1 is high level wake up

0 = nIRQ1 is low level wake up

[4] IRQWAKEUPPOL[0]

nIRQ0 wake up polarity

1 = nIRQ0 is high level wake up

0 = nIRQ0 is low level wake up

[3:2] RESERVED

[1] IRQWAKEUPEN[1]

nIRQ1 wake up enable bit

1 = nIRQ1 wake up enable

0 = nIRQ1 wake up disable

[0] IRQWAKEUPEN[0]

nIRQ0 wake up enable bit

1 = nIRQ0 wake up enable

0 = nIRQ0 wake up disable

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 55 - Revision A1

IRQ Wakeup Flag Register (IRQWAKEFLAG)

IRQWAKEFLAG 0xFFF0_0024 R/W IRQ Wakeup Flag Register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED IRQWAKEFLAG

This register is used to record the wakeup event, after clock recovery, software should check these flags

to identify which nIRQ is used to wakeup the system. And clear the flags in IRQ interrupt sevice routine.

BITS DESCRIPTION

[31:2] RESERVED -

[1] IRQWAKEFLAG[1]

nIRQ1 wake up flag

1 = chip is waked up by nIRQ1

0 = no active

[0] IRQWAKEFLAG[0]

nIRQ0 wake up flag

1 = chip is waked up by nIRQ0

0 = no active

W90N745CD/W90N745CDG

- 56 -

Power Management Control Register (PMCON)

PMCON 0xFFF0_0028 R/W

Power Management Control Register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED MIDLE PD IDLE

BITS DESCRIPTION

[31:3] RESERVED

[2] MIDLE

Memory controller IDLE enable

Setting both MIDLE and IDLE bits HIGH will let memory controller

enter IDLE mode, the clock source of memory controller will be halted

while ARM CORE enter IDLE mode.

1=memory controller will be forced into IDLE mode, (clock of memory

controller will be halted), when IDLE bit is set.

0 = memory controller still active when IDLE bit is set.

NOTE: Software must let SDRAM enter self-refresh mode before

enable this function because SDRAM MCLK will be stopped.

[1] PD

Power down enable

Setting this bit HIGH will let W90N745 enter power saving mode. Th

clock source 15M crystal oscillator and PLLs are stopped to generat

clock. User can use nIRQ[3:0], keypad and external RESET to wakeu

W90N745.

1 = Enable power down

0 = Disable

[0] IDLE

IDLE mode enable

Setting this bit HIGH will let ARM Core enter power saving mode. Th

peripherals can still keep working if the clock enable bit in CLKSEL i

set. Any nIRQ or nFIQ to ARM Core will let ARM CORE to exit IDL

state.

1 = IDLE mode

0 = Disable

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 57 - Revision A1

USB Transceiver Control Register (USBTXRCON)

USBTXRCO

N 0xFFF0_0030 R/W

USB Transceiver Control Register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED USBHnD

BITS DESCRIPTION

[31:1] RESERVED -

[0] USBHnD

USBHnD[0]: USB transceiver control

There are two USB1.1 built-in transceivers for data transmission. One

is dedicated for USB host and the other is shared with USB device.

Software can program this bit to switch the transceiver path.

1 = HOST

0 = Device

W90N745CD/W90N745CDG

- 58 -

7.3 External Bus Interface

7.3.1 EBI Overview

W90N745 supports External Bus Interface (EBI), which controls the access to the external memory

(ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one

ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 21 bits. It

supports 8-bit, 16-bit external data bus width for each bank.

The EBI has the following functions：

SDRAM controller

EBI control register

ROM/FLASH interface

External I/O interface

External bus mastership

7.3.2 SDRAM Controller

The SDRAM controller module within W90N745 contains configuration registers 、 timing control

registers、common control register and other logic to provide 8、16 bits SDRAM interface with a single

8、16 bits SDRAM device or two 8-bit devices wired to give a 16-bit data path. The maximum size of

each bank is 64M bytes, and maximum memory size can span up to 128MB.

The SDRAM controller has the following features：

Supports up to 2 external SDRAM banks

Maximum size of each bank is 64M bytes

8、16-bit data interface

Programmable CAS Latency： 1、2 and 3

Fixed Burst Length： 1

Sequential burst type

Auto Refresh Mode and Self Refresh Mode

Adjustable Refresh Rate

Power up sequence

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 59 - Revision A1

7.3.2.1. SDRAM Components Supported

Table 7.3.2.1 SDRAM supported by W90N745

SIZE TYPE BANKS ROW ADDRESSING COLUMN ADDRESSING

2Mx8 2 RA0~RA10 CA0~CA8

16M bits 1Mx16 2 RA0~RA10 CA0~CA7

8Mx8 4 RA0~RA11 CA0~CA8

64M bits 4Mx16 4 RA0~RA11 CA0~CA7

16Mx8 4 RA0~RA11 CA0~CA9

128M bits 8Mx16 4 RA0~RA11 CA0~CA8

32Mx8 4 RA0~RA12 CA0~CA9

256M bits 16Mx16 4 RA0~RA12 CA0~CA8

AHB Bus Address Mapping to SDRAM Bus

Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used;

The HADDR prefixes have been omitted on the following tables.

A14 ~ A0 are the Address pins of the W90N745 EBI interface;

A14 and A13 are the Bank Select Signals of SDRAM.

W90N745CD/W90N745CDG

- 60 -

SDRAM Data Bus Width: 16-bit

Total Type R x C R/C A14

(BS1)

A13

(BS0) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

16M 2Mx8 11x9 R ** 10 ** 10*21 20 19 18 17 16 15 14 13 12 11

** 10 ** 10*AP 24*98765 4 3 21

16M 1Mx16 11x8 R ** 9 ** 9* 10 20 19 18 17 16 15 14 13 12 11

** 9 ** 9* AP 24*9*8765 4 3 21

64M 8Mx8 12x9 R 10 11 10*22 21 20 19 18 17 16 15 14 13 12 23

C 10 11

10*22*AP 24*98765 4 3 21

64M 4Mx16 12x8 R 10 9 10*22 21 20 19 18 17 16 15 14 13 12 11

C 10 9

10*22*AP 24*23*8765 4 3 21

128M 16Mx8 12x10 R 10 11 10*22 21 20 19 18 17 16 15 14 13 12 23

C 10 11

10*22*AP 24 9 8 7 6 5 4 3 21

128M 8Mx16 12x9 R 10 11 10*22 21 20 19 18 17 16 15 14 13 12 23

C 10 11

10*22*AP 24*98765 4 3 21

256M* 32Mx8 13x10 R 10 11 23 22 21 20 19 18 17 16 15 14 13 12 24

C 10 11

23*22*AP 25*98765 4 3 21

256M 16Mx16 13x9 R 10 11 23 22 21 20 19 18 17 16 15 14 13 12 24

C 10 11

23*22*AP 25*98765 4 3 21

SDRAM Data Bus Width: 8-bit

Total Type R x C R/C A14

(BS1)

A13

(BS0) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

16M 2Mx8 11x9 R ** 9 ** 9* 20 19 18 17 16 15 14 13 12 11 10

** 9 ** 9* AP 23*87654 3 2 1 0

64M 8Mx8 12x9 R 9 10 9* 21 20 19 18 17 16 15 14 13 12 11 22

C 9 10

9* 21*AP 23*87654 3 2 1 1

128M 16Mx8 12x10 R 9 10 9* 21 20 19 18 17 16 15 14 13 12 11 22

C 9 10

9* 21*AP 2387654 3 2 1 0

256M 32Mx8 13x10 R 9 10 22 21 20 19 18 17 16 15 14 13 12 11 23

C 9 10

22*21*AP 24 87654 3 2 1 0

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 61 - Revision A1

7.3.2.2. SDRAM Power Up Sequence

The SDRAM must be initialized predefined manner after power on.W90N745 SDRAM Controller

automatically executes the commands needed for initialion and set the mode register of each bank to

default value. The default value is：

— Burst Length = 1

— Burst Type = Sequential (fixed)

— CAS Latency = 2

— Write Burst Length = Burst (fixed)

The value of mode register can be changed after power up sequence by setting the value of

corresponding bank’s configuration register “LENGTH” and “LATENCY” bits and set the MRSET bit

enable to execute the Mode Register Set command.

7.3.2.3. SDRAM Interface

MCLK

MCKE

nSCS[1:0]

nSRAS

nSCAS

nSWE

nSDQM[1:0]

A[20:0]

D[15:0]

A[10:0]

DQ[[15:0]

DQM[1:0]

nWE

nCAS

nRAS

nCS

BS0

BS1

CLK

CKE

W90N745

A13

A14

A[10:0]

nSCS0

SDRAM

32Mb 512Kx4x16

nSDQM[1:0]

Fig 7.3.1 SDRAM Interface

W90N745CD/W90N745CDG

- 62 -

7.3.3 EBI Control Registers Map

EBICON 0xFFF0_1000 R/W EBI control register 0x0001_0000

ROMCON 0xFFF0_1004 R/W ROM/FLASH control register 0x0000_0XFC

SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800

SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800

SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000

SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000

EXT0CON 0xFFF0_1018 R/W External I/O 0 control register 0x0000_0000

EXT1CON 0xFFF0_101C R/W External I/O 1 control register 0x0000_0000

EXT2CON 0xFFF0_1020 R/W External I/O 2 control register 0x0000_0000

EXT3CON 0xFFF0_1024 R/W External I/O 3 control register 0x0000_0000

CKSKEW 0xFFF0_1F00 R/W Clock skew control register (for testing) 0xXXXX_0038

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 63 - Revision A1

EBI Control Register (EBICON)

EBICON 0xFFF0_1000 R/W EBI control register 0x0001_0000

31 30 29 28 27 26 25 24

RESERVED EXBE3 EXBE2 EXBE1 EXBE0

23 22 21 20 19 18 17 16

RESERVED REFEN REFMOD CLKEN

15 14 13 12 11 10 9 8

REFRAT

7 6 5 4 3 2 1 0

REFRAT WAITVT LITTLE

BITS DESCRIPTION

[31:27] RESERVED

[27] EXBE3

External IO bank 3 byte enable

This function is used for some devices that with high and low bytes

enable signals to control which byte will be write or mask data output

when read. For this kind device, software can set this bit HIGH to

implement this function. Detail pin interconnection is showed as Fig7.3.8.

1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write

strobe signal to SRAM.

0 = nWBE[1:0] pin is byte write strobe signal.

[26] EXBE2

External IO bank 2 byte enable

The bit function description is the same as EXBE3 above.

1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write

strobe signal to SRAM.

0 = nWBE[1:0] pin is byte write strobe signal.

[25] EXBE1

External IO bank 1 byte enable

The bit function description is the same as EXBE3 above.

1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write

strobe signal to SRAM

0 = nWBE[1:0] pin is byte write strobe signal

W90N745CD/W90N745CDG

- 64 -

Continued.

BITS DESCRIPTION

[24] EXBE0

External IO bank 0 byte enable

This bit function description is the same as EXBE3 above.

1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write

strobe signal to SRAM

0 = nWBE[1:0] pin is byte write strobe signal

[23:19] RESERVED

[18] REFEN

Enable SDRAM refresh cycle for SDRAM bank0 & bank1

This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is

according to REFRAT bits.

1 = enable refresh function

0 = disable refresh function

[17] REFMOD

Refresh mode of SDRAM for SDRAM bank

Defines the refresh mode type of external SDRAM bank

Software can write this bit “1” to force SDRAM enter self-refresh mode.

0 = Auto refresh mode

1 = Self refresh mode

NOTE: If any read/write to SDRAM occurs then this bit will be cleared to

“0” by hardware automatically and SDRAM will enters auto-refresh

mode.

[16] CLKEN

Clock enable for SDRAM

Enables the SDRAM clock enable (CKE) control signal

0 = Disable (power down mode)

1 = Enable （Default）

[15:3] REFRAT

Refresh count value for SDRAM

The SDRAM Controller automatically provides an auto refresh cycle for

every refresh period programmed into the REFRAT bits when the

REFEN bit of each bank is set

The refresh period is calculated as fMCLK

value

period =

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 65 - Revision A1

Continued.

BITS DESCRIPTION

[2:1] WAITVT

Valid time of nWAIT signal

W90N745 recognizes the nWAIT signal at the next “nth” MCLK

rising edge after the nOE or nWBE active cycle. WAITVT bits

determine the n.

WAITVT [2:1] nth MCLK

0 0 1

0 1 2

1 0 3

1 1 4

[0] LITTLE

Little Endian mode

After power on reset, the content of LITTLE is the Power-On Setting

value from D14 pin. If pin D14 is pull-down, the external memory format

is Big Endian mode. If pin D14 is pull-up, the external memory format is

Little Endian mode. For more detail, refer to Power-On Setting of System

Manager.

NOTE: This bit is read only.

W90N745CD/W90N745CDG

- 66 -

ROM/Flash Control Register （ROMCON）

ROMCON 0xFFF0_1004 R/W ROM/FLASH control register 0x0000_0XFC

31 30 29 28 27 26 25 24

BASADDR

23 22 21 20 19 18 17 16

BASADDR SIZE

15 14 13 12 11 10 9 8

RESERVED tPA

7 6 5 4 3 2 1 0

tACC BTSIZE PGMODE

BITS DESCRIPTION

[31:19] BASADDR

Base address pointer of ROM/Flash bank

The start address is calculated as ROM/Flash bank base pointer << 18.

The base address pointer together with the “SIZE” bits constitutes the

whole address range of each bank.

[18:16] SIZE

The size of ROM/FLASH memory

SIZE [10:8] Byte

0 0 0 256K

0 0 1 512K

0 1 0 1M

0 1 1 2M

1 0 0 4M

1 0 1 RESERVED

1 1 0 RESERVED

1 1 1 RESERVED

[15:12] RESERVED -

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 67 - Revision A1

Continued.

BITS DESCRIPTION

[11:8] tPA

Page mode access cycle time

tPA[11:8] MCLK tPA[11:8] MCLK

0 0 0 0 1 1 0 0 0 10

0 0 0 1 2 1 0 0 1 12

0 0 1 0 3 1 0 1 0 14

0 0 1 1 4 1 0 1 1 16

0 1 0 0 5 1 1 0 0 18

0 1 0 1 6 1 1 0 1 20

0 1 1 0 7 1 1 1 0 22

0 1 1 1 8 1 1 1 1 24

[7:4] tACC

Access cycle time

tACC[11:8] MCLK tACC[11:8] MCLK

0 0 0 0 1 1 0 0 0 10

0 0 0 1 2 1 0 0 1 12

0 0 1 0 3 1 0 1 0 14

0 0 1 1 4 1 0 1 1 16

0 1 0 0 5 1 1 0 0 18

0 1 0 1 6 1 1 0 1 20

0 1 1 0 7 1 1 1 0 22

0 1 1 1 8 1 1 1 1 24

[3:2] BTSIZE

Boot ROM/FLASH data bus width

This ROM/Flash bank is designed for a boot ROM. BASADDR bits

determine its start address. The external data bus width is determined by

the data bus signals D [13:12] power-on setting.

BTSIZE [3:2] Bus Width D [13:12] Bus Width

0 0 8-bit Pull-down Pull-down 8-bit

0 1 16-bit Pull-down Pull-up 16-bit

1 0 RESERVED Pull-up Pull-down RESERVED

1 1 RESERVED Pull-up Pull-up RESERVED

[1:0] PGMODE

Page mode configuration

PGMODE [1:0] Mode

0 0 Normal ROM

0 1 4 word page

1 0 8 word page

1 1 16 word page

W90N745CD/W90N745CDG

- 68 -

Fig7.3.2 ROM/FLASH Read Operation Timing

Fig 7.3.3 ROM/FLASH Page Read Operation Timing

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 69 - Revision A1

Configuration Registers（SDCONF0/1）

The configuration registers enable software to set a number of operating parameters for the SDRAM

controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1

respectively. Each bank can have a different configuration.

SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800

SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800

31 30 29 28 27 26 25 24

BASADDR

23 22 21 20 19 18 17 16

BASADDR RESERVED

15 14 13 12 11 10 9 8

MRSET RESERVED AUTOPR LATENCY RESERVED

7 6 5 4 3 2 1 0

COMPBK DBWD COLUMN SIZE

BITS DESCRIPTION

[31:19] BASADDR

Base address pointer of SDRAM bank 0/1

The start address is calculated as SDRAM bank 0/1 base pointer

<< 18. The SDRAM base address pointer together with the “SIZE”

bits constitutes the whole address range of each SDRAM bank.

[18:16] RESERVED

[15] MRSET

SDRAM Mode register set command for SDRAM bank 0/1

This bit set will issue a mode register set command to SDRAM.

[14] RESERVED

[13] AUTOPR

Auto pre-charge mode of SDRAM for SDRAM bank 0/1

Enable the auto pre-charge function of external SDRAM bank 0/1

0 = Auto pre-charge

1 = No auto pre-charge

[12:11] LATENCY

The CAS Latency of SDRAM bank 0/1

Defines the CAS latency of external SDRAM bank 0/1

LATENCY [12:11] MCLK

0 0 1

0 1 2

1 0 3

1 1 REVERSED

W90N745CD/W90N745CDG

- 70 -

Continued.

BITS DESCRIPTION

[10:8] RESERVED

[7] COMPBK

Number of component bank in SDRAM bank 0/1

Indicates the number of component bank (2 or 4 banks) in external

SDRAM bank 0/1.

0 = 2 banks

1 = 4 banks

[6:5] DBWD

Data bus width for SDRAM bank 0/1

Indicates the external data bus width connect with SDRAM bank 0/1

If DBWD = 00, the assigned SDRAM access signal is not generated

i.e. disable.

DBWD [6:5] Bits

0 0 Bank disable

0 1 8-bit (byte)

1 0 16-bit (half-word)

1 1 REVERSED

[4:3] COLUMN

Number of column address bits in SDRAM bank 0/1

Indicates the number of column address bits in external SDRAM

bank 0/1.

COLUMN [4:3] Bits

0 0 8

0 1 9

1 0 10

1 1 REVERSED

[2:0] SIZE

Size of SDRAM bank 0/1

Indicates the memory size of external SDRAM bank 0/1

SIZE [2:0] Size of SDRAM （Byte）

0 0 0 Bank disable

0 0 1 2M

0 1 0 4M

0 1 1 8M

1 0 0 16M

1 0 1 32M

1 1 0 64M

1 1 1 REVERSED

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 71 - Revision A1

Timing Control Registers （SDTIME0/1）

W90N745 offers the flexible timing control registers to control the generation and processing of the

control signals and can achieve you use different speed of SDRAM

SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000

SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED tRCD

7 6 5 4 3 2 1 0

tRDL tRP tRAS

BITS DESCRIPTION

[31:11] RESERVED -

[10:8] tRCD

SDRAM bank 0/1, /RAS to /CAS delay

tRCD [10:8] MCLK

0 0 0 1

0 0 1 2

0 1 0 3

0 1 1 4

1 0 0 5

1 0 1 6

1 1 0 7

1 1 1 8

[7:6] tRDL

SDRAM bank 0/1, Last data in to pre-charge command

tRDL [7:6] MCLK

0 0 1

0 1 2

1 0 3

1 1 4

W90N745CD/W90N745CDG

- 72 -

Continued.

BITS DESCRIPTION

[5:3] tRP

SDRAM bank 0/1, Row pre-charge time

tRP [5:3] MCLK

0 0 0 1

0 0 1 2

0 1 0 3

0 1 1 4

1 0 0 5

1 0 1 6

1 1 0 7

1 1 1 8

[2:0] tRAS

SDRAM bank 0/1, Row active time

tRAS [2:0] MCLK

0 0 0 1

0 0 1 2

0 1 0 3

0 1 1 4

1 0 0 5

1 0 1 6

1 1 0 7

1 1 1 8

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 73 - Revision A1

Fig 7.3.4 Access timing 1 of SDRAM

Fig 7.3.5 Access timing 2 of SDRAM

W90N745CD/W90N745CDG

- 74 -

External I/O Control Registers（EXT0CON – EXT3CON）

The W90N745 supports an external device control without glue logic. It is very cost effective because

address decoding and control signals timing logic are not needed. Using these control registers you can

configure special external I/O devices for providing the low cost external devices control solution.

EXT0CON 0xFFF0_1018 R/W External I/O 0 control register 0x0000_0000

EXT1CON 0xFFF0_101C R/W External I/O 1 control register 0x0000_0000

EXT2CON 0xFFF0_1020 R/W External I/O 2 control register 0x0000_0000

EXT3CON 0xFFF0_1024 R/W External I/O 3 control register 0x0000_0000

31 30 29 28 27 26 25 24

BASADDR

23 22 21 20 19 18 17 16

BASADDR SIZE

15 14 13 12 11 10 9 8

ADRS tACC tCOH

7 6 5 4 3 2 1 0

tACS tCOS DBWD

BITS DESCRIPTION

[31:11] BASADDR

Base address pointer of external I/O bank 0~3

The start address of each external I/O bank is calculated as “BASADDR”

base pointer << 18.

Each external I/O bank base address pointer together with the “SIZE” bits

constitutes the whole address range of each external I/O bank.

[18:16] SIZE

The size of the external I/O bank 0~3

SIZE [18:16] Byte

0 0 0 256K

0 0 1 512K

0 1 0 1M

0 1 1 2M

1 0 0 4M

1 0 1 8M

1 1 0 REVERSED

1 1 1 REVERSED

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 75 - Revision A1

Continued.

BITS DESCRIPTION

[15] ADRS

Address bus alignment for external I/O bank 0~3

When ADRS is set, external address (A20~A0) bus is alignment to byte

address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is

AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting.

[14:11] tACC

Access cycles of external I/O bank 0~3

This parameter means nWE, nWBE and nOE active time clock. Detail timing

diagram please refer to Fig. 7.3.6 and 7.3.7

tACC[14:11] MCLK tACC[14:11] MCLK

0 0 0 0 Reversed 1 0 0 0 9

0 0 0 1 1 1 0 0 1 11

0 0 1 0 2 1 0 1 0 13

0 0 1 1 3 1 0 1 1 15

0 1 0 0 4 1 1 0 0 17

0 1 0 1 5 1 1 0 1 19

0 1 1 0 6 1 1 1 0 21

0 1 1 1 7 1 1 1 1 23

[10:8] tCOH

Chip selection hold time of external I/O bank 0~3

This parameters control nWBE and nOE hold time. Detail timing diagram

please refer to Fig. 7.3.6 and 7.3.7

tCOH [10:8] MCLK

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

W90N745CD/W90N745CDG

- 76 -

Continued.

BITS DESCRIPTION

[7:5] tACS

Address set-up before nECS for external I/O bank 0~3

tACS [7:5] MCLK

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

[4:2] tCOS

Chip selection set-up time of external I/O bank 0~3

When ROM/Flash memory bank is configured, the access to its bank

stretches chip selection time before the nOE or new signal is activated.

tCOS [4:2] MCLK

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

[1:0] DBWD

Programmable data bus width for external I/O bank 0~3

DBWD [1:0] Width of Data Bus

0 0 Disable bus

0 1 8-bit

1 0 16-bit

1 1 RESERVED

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 77 - Revision A1

Fig 7.3.6 External I/O write operation timing

Fig 7.3.7 External I/O read operation timing

W90N745CD/W90N745CDG

- 78 -

Fig. 7.3.8 External IO bank with 16-bit SRAM

Clock Skew Control Register （CKSKEW）

CKSKEW 0xFFF0_1F00 R/W Clock skew control register 0xXXXX_0018

31 30 29 28 27 26 25 24

DLH_CLK_REF

23 22 21 20 19 18 17 16

DLH_CLK_REF

15 14 13 12 11 10 9 8

RESVERED SWPON

7 6 5 4 3 2 1 0

DLH_CLK_SKEW MCLK_O_D

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 79 - Revision A1

BITS DESCRIPTION

[31:16] DLH_CLK_REF

Latch DLH_CLK clock tree by HCLK positive edge

The SDRAM MCLK is generated by inserting a delay (XOR2) chain in

HCLK positive or negedge edge to adjust the MCLK skew. So software

can read these bits to expore MCLK and HCLK relationship. [31:24] is

used for positive edge and [23:16] is for negedge edge.

[15:9] RESERVED -

[8] SWPON

SDRAM Initialization by Software

Set this bit “1” will issue a SDRAM power on default setting command

sequence like system power on, this bit will be auto-clear by hardware

while SDRAM initialization finish.

[7:4] DLH_CLK_SKEW

Data latch Clock Skew Adjustment

Due to PC board loading or too many devices connect to external

address and data bus, it may causes SDRAM can not work correctly at

high frequency (usually, > 80MHz) software can control

MCLK_O_D[3:0] to adjust address and data bus to adjust setup/hold

time.

DLH_CLK_SKEW[7:4] Gate

Delay DLH_CLK_SKEW[7:4] Gate

Delay

0 0 0 0 P-0 1 0 0 0 N-0

0 0 0 1 P-1 1 0 0 1 N-1

0 0 1 0 P-2 1 0 1 0 N-2

0 0 1 1 P-3 1 0 1 1 N-3

0 1 0 0 P-4 1 1 0 0 N-4

0 1 0 1 P-5 1 1 0 1 N-5

0 1 1 0 P-6 1 1 1 0 N-6

0 1 1 1 P-7 1 1 1 1 N-7

NOTE: P-x means Data latched Clock shift “X” gates delays by refer

MCLKO positive edge, N-x means Data latched Clock shift “X” gates

delays by refer MCLKO negative edge.

W90N745CD/W90N745CDG

- 80 -

Continued.

BITS DESCRIPTION

[3:0] MCLK_O_D

MCLK output delay adjustment

MCLK_O_D [3:0] Gate

Dela

MCLK_O_D [3:0] Gate

Dela

0 0 0 0 P-0 1 0 0 0 N-0

0 0 0 1 P-1 1 0 0 1 N-1

0 0 1 0 P-2 1 0 1 0 N-2

0 0 1 1 P-3 1 0 1 1 N-3

0 1 0 0 P-4 1 1 0 0 N-4

0 1 0 1 P-5 1 1 0 1 N-5

0 1 1 0 P-6 1 1 1 0 N-6

0 1 1 1 P-7 1 1 1 1 N-7

NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK

positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK

negative edge. MCLK is the output pin of MCLKO, which is an internal

signal on chip.

W90N745CD/W90N745CDG

Publication Release Date: July 26, 2006

- 81 - Revision A1

7.4 Cache Controller

The W90N745 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The I-

Cache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these

two caches are configured two-way set associative addressing. Each cache has four words cache line

size. When a miss occurs, four words must be fetched consecutively from external memory. The

replacement algorithm is a LRU (Least Recently Used).

If disabling the I-Cache / D-Cache, these cache memories can be treated as On-Chip RAM. The

W90N745 also provides a write buffer to improve system performance. The write buffer can buffer up to

eight words of data.

7.4.1 On-Chip RAM

If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has

4KB On-Chip RAM, its start address is 0xFFE01000. If I-Cache is disabled, there has 4KB On-Chip RAM

and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has

8KB On-Chip RAM starting from 0xFFE00000.

The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in

Cache Control Register (CAHCON).

Table7.4.1 The size and start address of On-Chip RAM

ON-CHIP RAM

ICAEN DCAEN SIZE START ADDRESS

0 0 8KB 0xFFE0_0000

0 1 4KB 0xFFE0_0000

1 0 4KB 0xFFE0.1000

1 1 Unavailable

7.4.2 Non-Cacheable Area

Although the cache affects the entire 2GB system memory, it is sometimes necessary to define non-

cacheable areas when the consistency of data stored in memory and the cache must be ensured. To

support this, the W90N745 provides a non-cacheable area control bit in the address field, A[31].

If A[31] in the ROM/FLASH, SDRAM, or external I/O bank’s access address is “0”, then the accessed

data is cacheable. If the A [31] value is “1”, the accessed data is non-cacheable.

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7.4.3 Instruction Cache

The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is

128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in

memory. The cache access cycle begins with an instruction request from the instruction unit in the core.

In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the

cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The

first word received from the bus is the requested instruction. The cache forwards this instruction to the

instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to

receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is

used to select a line when no empty lines are available. When I-Cache is disabled, the cache memory is

served as 4KB On-chip RAM. The I-Cache is always disabled on reset.

The following is a list of the instruction cache features：

4K bytes instruction cache

Two-way set associative

Four words in a cache line

LRU replacement policy

Lockable on a per-line basis

Critical word first, burst access

Instruction Cache Operation

On an instruction fetch, bits 10-4 of the instruction’s address point into the cache to retrieve the tags and

data of one set. The tags from both ways are then compared against bits 30-11 of the instruction’s

address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor

the matched tag is not valid, it is a cache miss.

Instruction Cache Hit

In case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line

whose tag matches. The instruction is immediately transferred to the instruction unit of the core.

Instruction Cache Miss

On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4-

word burst transfer read request. A cache line is then selected to receive the data that will be coming

from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the

selected set is invalid, then the least recently used line is selected for replacement. Locked lines are

never replaced. The transfer begins with the word requested by the instruction unit (critical word first),

followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound).

Instruction Cache Flushing

The W90N745 does not support external memory snooping. Therefore, if self-modifying code is written,

the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one

operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with

the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is

automatically flushed during reset.

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Instruction Cache Load and Lock

The W90N745 supports a cache-locking feature that can be used to lock critical sections of code into I-

Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The

smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular

instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line

command.

To load and lock instruction, the following sequence should be followed:

1. Write the start address of the instructions to be locked into CAHADR register.

2. Set LDLK and ICAH bits in the CAHCON register.

3. Increased the address by 16 and written into CAHADR register.

4. Set LDLK and ICAH bits in the CAHCON register.

5. Repeat the steps 3 and 4, until the desired instructions are all locked.

When using I-Cache load and lock command, there are some notes should be cared.

The programs executing load and lock operation should be held in a non-cacheable area of memory.

The cache should be enabled and interrupts should be disabled.

Software must flush the cache before execute load and lock to ensure that the code to be locked

down is not already in the cache.

Instruction Cache Unlock

The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line

is cleared to “0”. W90N745 has two unlock command, unlock line and unlock all.

The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,

it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the

cache, no operation is done and the command terminates with no exception. To unlock one line the

following unlock line sequence should be followed:

1. Write the address of the line to be unlocked into the CAHADR Register.

2. Set the ULKS and ICAH bits in the CAHCON register.

The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache

lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a

line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA

and ICAH bits.

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7.4.4 Data Cache

The W90N745 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is

128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in

memory. The cache is designed for buffer write-through mode of operation and a least recently used

(LRU) replacement algorithm is used to select a line when no empty lines are available.

When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM.

The D-Cache is always disabled on reset.

The following is a list of the data cache features：

4K bytes data cache

Two-way set associative

Four words in a cache line

LRU replacement policy

Lockable on a per-line basis

Critical word first, burst access

Buffer Write-through mode

8 words write buffer

Drain write buffer

Data Cache Operation

On a data fetch, bits 10-4 of the data’s address point into the cache to retrieve the tags and data of one

set. The tags from both ways are then compared against bits 30-11 of the data’s address. If a match is

found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is

not valid, it is a cache miss.

Data Cache Read

Read Hit：On a cache hit, the requested word is immediately transferred to the core.

Read Miss：A line in the cache is selected to hold the data, which will be fetched from memory. The

selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is

selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is

selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the

missed data (critical word first), followed by the remaining word in the line, then by the word at the

beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to

the core.

Data Cache Write

As buffer write-through mode, store operations always update memory. The buffer write-through mode is

used when external memory and internal cache images must always agree.

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Write Hit：Data is written into both the cache and write buffer. The processor then continues to access

the cache, while the cache controller simultaneously downloads the contents of the write buffer to main

memory. This reduces the effective write memory cycle time from the time required for a main memory

cycle to the cycle time of the high-speed cache.

Write Miss：Data is only written into write buffer, not to the cache (write no allocate).

Data Cache Flushing

The W90N745 allows flushing of the data cache under software control. The data cache may be

invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register.

Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the “V” bit

of the line is cleared to “0”. The D-cache is automatically flushed during reset.

Data Cache Load and Lock

The W90N745 supports a cache-locking feature that can be used to lock critical sections of data into D-

Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The

smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular

instruction SRAM. The locked lines are not replaced during misses and it is not affected by flush per line

command.

To load and lock data, the following sequence should be followed:

1. Write the start address of the data to be locked into CAHADR register.

2. Set LDLK and DCAH bits in the CAHCON register.

3. Increased the address by 16 and written into CAHADR register.

4. Set LDLK and DCAH bits in the CAHCON register.

5. Repeat the steps 3 and 4, until the desired data are all locked.

When using D-Cache load and lock command, there are some notes should be cared.

The programs executing load and lock operation should be held in a non-cacheable area of memory.

The cache should be enabled and interrupts should be disabled.

Software must flush the cache before execute load and lock to ensure that the data to be locked down

is not already in the cache.

Data Cache Unlock

The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line

is cleared to “0”. W90N745 has two unlock command, unlock line and unlock all.

The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,

it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the

cache, no operation is done and the command terminates with no exception. To unlock one line the

following unlock line sequence should be followed:

1. Write the address of the line to be unlocked into the CAHADR Register.

2. Set the ULKS and DCAH bits in the CAHCON register.

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The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache

lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a

line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA

and DCAH bits.

7.4.5 Write Buffer

The W90N745 provides a write buffer to improve system performance. The write buffer can buffer up to

eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF

Drain write buffer

To force data, this is in write buffer, to be written to external main memory. This operation is useful in real

time applications where the processor needs to be sure that a write to a peripheral has completed before

program execution continues.

To perform this command, you can set the DRWB and DCAH bits in CAHCON register.

7.4.6 Cache Control Registers Map

CAHCNF 0xFFF0_2000 R/W Cache configuration register 0x0000_0000

CAHCON 0xFFF0_2004 R/W Cache control register 0x0000_0000

CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000

CTEST0 0xFFF6_0000 R/W Cache test register 0 0x0000_0000

CTEST1 0xFFF6_0004 R Cache test register 1 0x0000_0000

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Configuration Register (CAHCNF)

Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write

buffer.

CAHCNF 0xFFF0_2000 R/W Cache configuration register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED WRBEN DCAEN ICAEN

BITS DESCRIPTION

[31:3] RESERVED

[2] WRBEN

Write buffer enable

Write buffer is disabled after reset.

1 = enable write buffer

0 = disable write buffer

[1] DCAEN

D-Cache enable

D-Cache is disabled after reset.

1 = enable D-cache

0 = disable D-cache

[0] ICAEN

I-Cache enable

I-Cache is disabled after reset.

1 = enable I-cache

0 = disable I-cache

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Control Register (CAHCON)

Cache controller supports one Control register used to control the following operations.

Flush I-Cache and D-Cache

Load and lock I-Cache and D-Cache

Unlock I-Cache and D-Cache

Drain write buffer

These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command

set bit will be cleared to “0” automatically.

CAHCON 0xFFF0_2004 R/W Cache control register 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH

BITS DESCRIPTION

[31:8] RESERVED

[7] DRWB

Drain write buffer

Forces write buffer data to be written to main memory.

[6] ULKS

Unlock I-Cache/D-Cache single line

Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in

CAHADR register must be specified.

[5] ULKA

Unlock I-Cache/D-Cache entirely

Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared

to 0.

[4] LDLK

Load and Lock I-Cache/D-Cache

Loads the instruction or data from external memory and locks into

cache. Both WAY and ADDR bits in CAHADR register must be

specified.

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Continued.

BITS DESCRIPTION

[3] FLHS

Flush I-Cache/D-Cache single line

Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR

bits in CAHADR register must be specified.

[2] FLHA

Flush I-Cache/D-Cache entirely

To flush the entire I-Cache/D-Cache, also flushes any locked-down

code. If the I-Cache/D-Cache contains locked down code, the

programmer must flush lines individually

[1] DCAH

D-Cache selected

When set to “1”, the command set is executed with D-Cache.

[0] ICAH

I-Cache selected

When set to “1”, the command set is executed with I-Cache.

NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute

entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be

executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set

both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid

command and no operation is done and the command terminates with no exception.

The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB

and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no

operation is done and the command terminates with no exception.

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Address Register (CAHADR)

W90N745 Cache Controller supports one address register. This address register is used with the

command set in the control register (CAHCON) by specifying instruction/data address.

CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000

31 30 29 28 27 26 25 24

WAY ADDR

23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8

ADDR

7 6 5 4 3 2 1 0

ADDR

BITS DESCRIPTION

[31] WAY

Way selection

0 = Way0 is selected

1 = Way1 is selected

[30:0] ADDR The absolute address of instruction or data

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Cache Test Register 0 (CTEST0)

Cache test control register that configures the cache and tag ram testing enable or disable. In addition,

this register controls the built-in-self-test (BIST) function of SRAM.

CTEST0 0xFFF6_0000 R/W Cache test register 0 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

BISTEN RESERVED BST_GP3 BST_GP2 BST_GP1 BST_GP0

7 6 5 4 3 2 1 0

RESERVED CATEST

BITS DESCRIPTION

[31:16] RESERVED

[15] BISTEN

BIST mode enable

When set to “1”, BIST mode will be enabled, the selected memory

groups begins to be tested by BIST.

[14:12] RESERVED

[11] BIST_GP3

Memory group 3 is selected to test by BIST

When set to “1”, memory group 3, including data cache tag ram

way 0 and way 1, are selected to be tested by BIST.

[10] BIST_GP2

Memory group 2 is selected to test by BIST

When set to “1”, memory group 2, including program cache tag

ram way 0 and way 1, are selected to be tested by BIST.

[9] BIST_GP1

Memory group 1 is selected to test by BIST

When set to “1”, memory group 1, including data cache ram way 0

and way 1, are selected to be tested by BIST.

[8] BIST_GP0

Memory group 0 is selected to test by BIST

When set to “1”, memory group 0, including program cache ram

way 0 and way 1, are selected to be tested by BIST.

[7:0] RESERVED

** Note: The 4 memory groups can be selected and tested simultaneously by BIST.

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Cache Test Register 1 (CTEST1)

Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST

is finish and all of bank of SRAM are tested successfully will be presented in this register.

CTEST1 0xFFF6_0004 R Cache test register 1 0x0000_0000

31 30 29 28 27 26 25 24

FINISH RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

BFAIL7 BFAIL6 BFAIL5 BFAIL4 BFAIL3 BFAIL2 BFAIL1 BFAIL0

BITS DESCRIPTION

[31] FINISH

BIST completed

This bit is “0” initially. When BIST mode enabled, this bit will be “1”

after BIST test completed. The values of BFAIL0-7 are valid only

after FINISH = 1.

[30:8] RESERVED

[7] BFAIL7

BIST test fail for data cache tag ram way 1

If this bit equals to “1”, it indicates the data cache tag ram for way

1 is tested fail by BIST. “0” means the test is passed.

[6] BFAIL6

BIST test fail for data cache tag ram way 0

If this bit equals to “1”, it indicates the data cache tag ram for way

0 is tested fail by BIST. “0” means the test is passed.

[5] BFAIL5

BIST test fail for instruction cache tag ram way 1

If this bit equals to “1”, it indicates the instruction cache tag ram for

way 1 is tested fail by BIST. “0” means the test is passed.

[4] BFAIL4

BIST test fail for instruction cache tag ram way 0

If this bit equals to “1”, it indicates the instruction cache tag ram for

way 0 is tested fail by BIST. “0” means the test is passed.

[3] BFAIL3

BIST test fail for data cache ram way 1

If this bit equals to “1”, it indicates the data cache ram for way 1 is

tested fail by BIST. “0” means the test is passed.

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Continued.

BITS DESCRIPTION

[2] BFAIL2

BIST test fail for data cache ram way 0

If this bit equals to “1”, it indicates the data cache ram for way 0 is

tested fail by BIST. “0” means the test is passed.

[1] BFAIL1

BIST test fail for instruction cache ram way 1

If this bit equals to “1”, it indicates the instruction cache ram for

way 1 is tested fail by BIST. “0” means the test is passed.

[0] BFAIL0

BIST test fail for instruction cache ram way 0

If this bit equals to “1”, it indicates the instruction cache ram for

way 0 is tested fail by BIST. “0” means the test is passed.

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7.5 Ethernet MAC Controller

Overview

The W90N745 provides an Ethernet MAC Controller (EMC) for LAN application. This EMC has its

DMA controller, transmit FIFO, and receive FIFO.

The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM

function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine

controller and status controller. The EMC only supports RMII (Reduced MII) interface to connect with

PHY operating on 50MHz REF_CLK.

Features

Supports IEEE Std. 802.3 CSMA/CD protocol.

Supports both half and full duplex for 10M/100M bps operation.

Supports RMII interface.

Supports MII Management function.

Supports pause and remote pause function for flow control.

Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception.

Supports 16 entries CAM function for Ethernet MAC address recognition.

Supports internal loop back mode for diagnostic.

Supports 256 bytes embedded transmit and receive FIFO.

Supports DMA function.

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7.5.1 EMC Functional Description

MII Management State Machine

The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management

interface, software can access the control and status registers of the external PHY chip. Tow

programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII

Management Data Control and Address Register) are for MII management function. Set the bit BUSY

of MIIDA register will trigger the MII management state machine. After the MII management cycle is

finished, the BUSY bit will be cleared automatically.

Media Access Control (MAC)

The function of W90N745 MAC fully meets the requirements defined by the IEEE802.3u specification.

The following paragraphs will describe the frame structure and the operation of the transmission and

receive.

The transmission data frame sent from the transmit DMA will be encapsulated by the MAC before

transmitting onto the MII bus. The sent data will be assembled with the preamble, the start frame

delimiter (SFD), the frame check sequence and the padding for enforcing those less than 64 bytes to

meet the minimum size frame and CRC sequence. The out going frame format will be as following

10101010 --- 10101010 10101011 d0 d1 d2

dn Padding CRC31 CRC30 --- CRC0

As mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern

“10101010” and the SFD is a one byte 10101011 data. The padding data will be all 0 value if the sent

data frame is less than 64 bytes. The padding disable function specified in the bit P of the transmit

descriptor is used to control if the MAC needs to pad data at the end of frame data or not when the

transmitted data frame is less than 64 bytes. The padding data will not be appended if the padding

disable bit is set to be high. The bits CRC0 ... CRC31 are the 32 bits cyclic redundancy check (CRC)

sequence. The CRC encoding is defined by the following polynomial specified by the IEEE802.3. This

32 bits CRC appending function will be disabled if the Inhibit CRC of the transmission descriptor is set

to high.

The MAC also performs many other transmission functions specified by the IEEE802.3, including the

inter-frame spacing function, collision detection, collision enforcement, collision back off and

retransmission. The collision back-off timer is a function of the integer slot time, 512 bit times. The

number of slot times to delay between the current transmissions attempts to the next attempt is

determined by a uniformly distributed random integer algorithm specified by the IEEE802.3. The MAC

performs the receive functions specified by the IEEE 802.3 including the address recognition function,

the frame check sequence validation, the frame disassembly, framing and collision filtering.

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EMC Descriptors

A link-list data structure named as descriptor is used to keep the control, status and data

information of each frame. Through the descriptor, CPU and EMC exchange the information for frame

reception and transmission.

Two different descriptors are defined in W90N745. One named as Rx descriptor for frame

reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of

four words. There is much information kept in the descriptors and details are described as below.

7.5.1.1. Rx Buffer Descriptor

1 3

0 2

9 1

5 0

O Rx Status Receive Byte Count

Receive Buffer Starting Address BO

Reserved

Next Rx Descriptor Starting Address

Rx Descriptor Word 0

31 30 29 28 27 26 25 24

Owner Reserved

23 22 21 20 19 18 17 16

Reserved RP ALIE RXGD PTLE Reserved CRCE RXINTR

15 14 13 12 11 10 9 8

RBC

7 6 5 4 3 2 1 0

RBC

Owner [31:30]: Ownership

The ownership field defines which one, the CPU or EMC, is the owner of each Rx descriptor. Only the

owner has right to modify the Rx descriptor and the others can read the Rx descriptor only.

00: The owner is CPU

01: Undefined

10: The owner is EMC

11: Undefined

If the O=2’b10 indicates the EMC RxDMA is the owner of Rx descriptor and the Rx descriptor is

available for frame reception. After the frame reception completed, if the frame needed NAT

translation, EMC RxDMA modify ownership field to 2’b11. Otherwise, the ownership field will be

modified to 2’b00.

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If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing

the frame, it modifies the ownership field to 2’b10 and releases the Rx descriptor to EMC RxDMA.

Rx Status [29:16]: Receive Status

This field keeps the status for frame reception. All status bits are updated by EMC. In the receive

status, bits 29 to 23 are undefined and reserved for the future.

RP [22]: Runt Packet

The RP indicates the frame stored in the data buffer pointed by Rx descriptor is a short frame (frame

length is less than 64 bytes).

1’b0: The frame is not a short frame.

1’b1: The frame is a short frame.

ALIE [21]: Alignment Error

The ALIE indicates the frame stored in the data buffer pointed by Rx descriptor is not a multiple of

byte.

1’b0: The frame is a multiple of byte.

1’b1: The frame is not a multiple of byte.

RXGD [20]: Frame Reception Complete

The RXGD indicates the frame reception has completed and stored in the data buffer pointed by Rx

descriptor.

1’b0: The frame reception not complete yet.

1’b1: The frame reception completed.

PTLE [19]: Packet Too Long

The PTLE indicates the frame stored in the data buffer pointed by Rx descriptor is a long frame (frame

length is greater than 1518 bytes).

1’b0: The frame is not a long frame.

1’b1: The frame is a long frame.

CRCE [17]: CRC Error

The CRCE indicates the frame stored in the data buffer pointed by Rx descriptor incurred CRC error.

1’b0: The frame doesn’t incur CRC error.

1’b1: The frame incurred CRC error.

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RXINTR [16]: Receive Interrupt

The RXINTR indicates the frame stored in the data buffer pointed by Rx descriptor caused an interrupt

condition.

1’b0: The frame doesn’t cause an interrupt.

1’b1: The frame caused an interrupt.

RBC [15:0]: Receive Byte Count

The RBC indicates the byte count of the frame stored in the data buffer pointed by Rx descriptor. The

four bytes CRC field is also included in the receive byte count. But if the SPCRC of register MCMDR

is enabled, the four bytes CRC field will be excluded from the receive byte count.

Rx Descriptor Word 1

31 30 29 28 27 26 25 24

RXBSA

23 22 21 20 19 18 17 16

RXBSA

15 14 13 12 11 10 9 8

RXBSA

7 6 5 4 3 2 1 0

RXBSA BO

RXBSA [31:2]: Receive Buffer Starting Address

The RXBSA indicates the starting address of the receive frame buffer. The RXBSA is used to be the

bit 31 to 2 of memory address. In other words, the starting address of the receive frame buffer always

located at word boundary.

BO [1:0]: Byte Offset

The BO indicates the byte offset from RXBSA where the received frame begins to store. If the BO is

2’b01, the starting address where the received frame begins to store is RXBSA+2’b01, and so on.

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Rx Descriptor Word 2

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved

The Rx descriptor word 2 keeps obsolete information for MAC translation. Therefore, these

information bits are undefined and should be ignored.

Rx Descriptor Word 3

31 30 29 28 27 26 25 24

NRXDSA

23 22 21 20 19 18 17 16

NRXDSA

15 14 13 12 11 10 9 8

NRXDSA

7 6 5 4 3 2 1 0

NRXDSA

NRXDSA [31:0]: Next Rx Descriptor Starting Address

The Rx descriptor is a link-list data structure. Consequently, NRXDSA is used to keep the starting

address of the next Rx descriptor. The bits [1:0] will be ignored by EMC. So, all Rx descriptor must

locate at word boundary memory address.

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7.5.1.2. Tx Buffer Descriptor

1 3

0 1

3 2 1 0

O Reserved I C P

Transmit Buffer Starting Address BO

Tx Status Transmit Byte Count

Next Tx Descriptor Starting Address

Tx Descriptor Word 0

31 30 29 28 27 26 25 24

Owner Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved IntEn CRCApp PadEn

Owner [31]: Ownership

The ownership field defines which one, the CPU or EMC, is the owner of each Tx descriptor. Only the

owner has right to modify the Tx descriptor and the other can read the Tx descriptor only.

0: The owner is CPU

1: The owner is EMC

If the O=1’b1 indicates the EMC TxDMA is the owner of Tx descriptor and the Tx descriptor is

available for frame transmission. After the frame transmission completed, EMC TxDMA modify

ownership field to 1’b0 and return the ownership of Tx descriptor to CPU.

If the O=1’b0 indicates the CPU is the owner of Tx descriptor. After the CPU prepares new frame to

wait transmission, it modifies the ownership field to 1’b1 and releases the Tx descriptor to EMC

TxDMA.

IntEn [2]: Transmit Interrupt Enable

The IntEn controls the interrupt trigger circuit after the frame transmission completed. If the IntEn is

enabled, the EMC will trigger interrupt after frame transmission completed. Otherwise, the interrupt

doesn’t be triggered.

1’b0: Frame transmission interrupt is masked.

1’b1: Frame transmission interrupt is enabled.

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CRCApp [1]: CRC Append

The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes

CRC checksum will be appended to frame at the end of frame transmission.

1’b0: 4-bytes CRC appending is disabled.

1’b1: 4-bytes CRC appending is enabled.

PadEN [0]: Padding Enable

The PadEN control the PAD bits appending while the length of transmission frame is less than 60

bytes. If PadEN is enabled, EMC does the padding automatically.

1’b0: PAD bits appending is disabled.

1’b1: PAD bits appending is enabled.

Tx Descriptor Word 1

31 30 29 28 27 26 25 24

TXBSA

23 22 21 20 19 18 17 16

TXBSA

15 14 13 12 11 10 9 8

TXBSA

7 6 5 4 3 2 1 0

TXBSA BO

TXBSA [31:2]: Transmit Buffer Starting Address

The TXBSA indicates the starting address of the transmit frame buffer. The TXBSA is used to be the

bit 31 to 2 of memory address. In other words, the starting address of the transmit frame buffer always

located at word boundary.

BO [1:0]: Byte Offset

The BO indicates the byte offset from TXBSA where the transmit frame begins to read. If the BO is

2’b01, the starting address where the transmit frame begins to read is TXBSA+2’b01, and so on.

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Tx Descriptor Word 2

31 30 29 28 27 26 25 24

CCNT Reserved SQE PAU TXHA

23 22 21 20 19 18 17 16

LC TXABT NCS EXDEF TXCP

Reserved DEF TXINTR

15 14 13 12 11 10 9 8

TBC

7 6 5 4 3 2 1 0

TBC

CCNT [31:28]: Collision Count

The CCNT indicates the how many collision occurred consecutively during a packet transmission. If

the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4’h0 and bit

TXABT will be set to 1.

SQE [26]: SQE Error

The SQE indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.

The SQE error check will only be done while both bit EnSQE of MCMDR is enabled and EMC is

operating on 10Mbps half-duplex mode.

1’b0: No SQE error found at end of packet transmission.

1’b0: SQE error found at end of packet transmission.

PAU [25]: Transmission Paused

THE PAU INDICATES THE NEXT NORMAL PACKET transmission process will be paused temporally

because EMC received a PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to

transmit a PAUSE control frame out.

1’b0: Next normal packet transmission process will go on.

1’b1: Next normal packet transmission process will be paused.

TXHA [24]: Transmission Halted

The TXHA indicates the next normal packet transmission process will be halted because the bit TXON

of MCMDR is disabled be S/W.

1’b0: Next normal packet transmission process will go on.

1’b1: Next normal packet transmission process will be halted.

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LC [23]: Late Collision

The LC indicates the collision occurred in the outside of 64 bytes collision window. This means after

the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision

check will only be done while EMC is operating on half-duplex mode.

1’b0: No collision occurred in the outside of 64 bytes collision window.

1’b1: Collision occurred in the outside of 64 bytes collision window.

TXABT [22]: Transmission Abort

The TXABT indicates the packet incurred 16 consecutive collisions during transmission, and then the

transmission process for this packet is aborted. The transmission abort is only available while EMC is

operating on half-duplex mode.

1’b0: Packet doesn’t incur 16 consecutive collisions during transmission.

1’b1: Packet incurred 16 consecutive collisions during transmission.

NCS [21]: No Carrier Sense

The NCS indicates the MII I/F signal CRS doesn’t active at the start of or during the packet

transmission. The NCS is only available while EMC is operating on half-duplex mode.

1’b0: CRS signal actives correctly.

1’b1: CRS signal doesn’t active at the start of or during the packet transmission.

EXDEF [20]: Defer Exceed

The EXDEF indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps

mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NDEF of

MCMDR is disabled, and EMC is operating on half-duplex mode.

1’b0: Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms

(10Mbps).

1’b1: Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).

TXCP [19]: Transmission Complete

The TXCP indicates the packet transmission has completed correctly.

1’b0: The packet transmission doesn’t complete.

1’b1: The packet transmission has completed.

DEF [17]: Transmission Deferred

The DEF indicates the packet transmission has deferred once. The DEF is only available while EMC

is operating on half-duplex mode.

1’b0: Packet transmission doesn’t defer.

1’b1: Packet transmission has deferred once.

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TXINTR [16]: Transmit Interrupt

The TXINTR indicates the packet transmission caused an interrupt condition.

1’b0: The packet transmission doesn’t cause an interrupt.

1’b1: The packet transmission caused an interrupt.

TBC [15:0]: Transmit Byte Count

The TBC indicates the byte count of the frame stored in the data buffer pointed by Tx descriptor for

transmission.

Tx Descriptor Word 3

31 30 29 28 27 26 25 24

NTXDSA

23 22 21 20 19 18 17 16

NTXDSA

15 14 13 12 11 10 9 8

NTXDSA

7 6 5 4 3 2 1 0

NTXDSA

NTXDSA [31:0]: Next Tx Descriptor Starting Address

The Tx descriptor is a link-list data structure. Consequently, NTXDSA is used to keep the starting

address of the next Tx descriptor. The bits [1:0] will be ignored by EMC. So, all Tx descriptor must

locate at word boundary memory address.

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7.5.2 EMC Register Mapping

The EMC implements many registers and the registers are separated into three types, the control

registers, the status registers and diagnostic registers. The control registers are used by S/W to pass

control information to EMC. The status registers are used to keep EMC operation status for S/W. And,

the diagnostic registers are used for debug only.

EMC Registers

CONTROL REGISTERS (44)

CAMCMR 0xFFF0_3000 R/W CAM Command Register 0x0000_0000

CAMEN 0xFFF0_3004 R/W CAM Enable Register 0x0000_0000

CAM0M 0xFFF0_3008 R/W CAM0 Most Significant Word Register 0x0000_0000

CAM0L 0xFFF0_300C R/W CAM0 Least Significant Word Register 0x0000_0000

CAM1M 0xFFF0_3010 R/W CAM1 Most Significant Word Register 0x0000_0000

CAM1L 0xFFF0_3014 R/W CAM1 Least Significant Word Register 0x0000_0000

CAM2M 0xFFF0_3018 R/W CAM2 Most Significant Word Register 0x0000_0000

CAM2L 0xFFF0_301C R/W CAM2 Least Significant Word Register 0x0000_0000

CAM3M 0xFFF0_3020 R/W CAM3 Most Significant Word Register 0x0000_0000

CAM3L 0xFFF0_3024 R/W CAM3 Least Significant Word Register 0x0000_0000

CAM4M 0xFFF0_3028 R/W CAM4 Most Significant Word Register 0x0000_0000

CAM4L 0xFFF0_302C R/W CAM4 Least Significant Word Register 0x0000_0000

CAM5M 0xFFF0_3030 R/W CAM5 Most Significant Word Register 0x0000_0000

CAM5L 0xFFF0_3034 R/W CAM5 Least Significant Word Register 0x0000_0000

CAM6M 0xFFF0_3038 R/W CAM6 Most Significant Word Register 0x0000_0000

CAM6L 0xFFF0_303C R/W CAM6 Least Significant Word Register 0x0000_0000

CAM7M 0xFFF0_3040 R/W CAM7 Most Significant Word Register 0x0000_0000

CAM7L 0xFFF0_3044 R/W CAM7 Least Significant Word Register 0x0000_0000

CAM8M 0xFFF0_3048 R/W CAM8 Most Significant Word Register 0x0000_0000

CAM8L 0xFFF0_304C R/W CAM8 Least Significant Word Register 0x0000_0000

CAM9M 0xFFF0_3050 R/W CAM9 Most Significant Word Register 0x0000_0000

CAM9L 0xFFF0_3054 R/W CAM9 Least Significant Word Register 0x0000_0000

CAM10M 0xFFF0_3058 R/W CAM10 Most Significant Word Register 0x0000_0000

CAM10L 0xFFF0_305C R/W CAM10 Least Significant Word Register 0x0000_0000

CAM11M 0xFFF0_3060 R/W CAM11 Most Significant Word Register 0x0000_0000

CAM11L 0xFFF0_3064 R/W CAM11 Least Significant Word Register 0x0000_0000

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Continued.

CONTROL REGISTERS (44)

CAM12M 0xFFF0_3068 R/W CAM12 Most Significant Word Register 0x0000_0000

CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register 0x0000_0000

CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register 0x0000_0000

CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register 0x0000_0000

CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register 0x0000_0000

CAM14L 0xFFF0_307C R/W CAM14 Least Significant Word Register 0x0000_0000

CAM15M 0xFFF0_3080 R/W CAM15 Most Significant Word Register 0x0000_0000

CAM15L 0xFFF0_3084 R/W CAM15 Least Significant Word Register 0x0000_0000

TXDLSA 0xFFF0_3088 R/W Transmit Descriptor Link List Start

Address Register 0xFFFF_FFFC

RXDLSA 0xFFF0_308C R/W Receive Descriptor Link List Start

Address Register 0xFFFF_FFFC

MCMDR 0xFFF0_3090 R/W MAC Command Register 0x0000_0000

MIID 0xFFF0_3094 R/W MII Management Data Register 0x0000_0000

MIIDA 0xFFF0_3098 R/W MII Management Control and Address

FFTCR 0xFFF0_309C R/W FIFO Threshold Control Register 0x0000_0101

TSDR 0xFFF0_30A0 W Transmit Start Demand Register Undefined

RSDR 0xFFF0_30A4 W Receive Start Demand Register Undefined

DMARFC 0xFFF0_30A8 R/W Maximum Receive Frame Control

MIEN 0xFFF0_30AC R/W MAC Interrupt Enable Register 0x0000_0000

Status Registers (11)

MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register 0x0000_0000

MGSTA 0xFFF0_30B4 R/W MAC General Status Register 0x0000_0000

MPCNT 0xFFF0_30B8 R/W Missed Packet Count Register 0x0000_7FFF

MRPC 0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000

MRPCC 0xFFF0_30C0 R MAC Receive Pause Current Count

MREPC 0xFFF0_30C4 R MAC Remote Pause Count Register 0x0000_0000

DMARFS 0xFFF0_30C8 R/W DMA Receive Frame Status Register 0x0000_0000

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Continued.

Status Registers (11)

CTXDSA 0xFFF0_30CC R Current Transmit Descriptor Start

Address Register 0x0000_0000

CTXBSA 0xFFF0_30D0 R Current Transmit Buffer Start Address

CRXDSA 0xFFF0_30D4 R Current Receive Descriptor Start

Address Register 0x0000_0000

CRXBSA 0xFFF0_30D8 R Current Receive Buffer Start Address

Diagnostic Registers (7)

RXFSM 0xFFF0_3200 R Receive Finite State Machine Register 0x0081_1101

TXFSM 0xFFF0_3204 R Transmit Finite State Machine Register 0x0101_1101

FSM0 0xFFF0_3208 R Finite State Machine Register 0 0x0001_0101

FSM1 0xFFF0_320C R Finite State Machine Register 1 0x1100_0100

DCR 0xFFF0_3210 R/W Debug Configuration Register 0x0000_003F

DMMIR 0xFFF0_3214 R Debug Mode MAC Information Register 0x0000_0000

BISTR 0xFFF0_3300 R/W BIST Mode Register 0x0000_0000

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7.5.2.1. Register Details

CAM Command Register (CAMCMR)

The EMC of W90N745 supports CAM function for destination MAC address recognition. The

CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet

reception.

CAMCMR 0xFFF0_3000 R/W CAM Command Register 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved ECMP CCAM ABP AMP AUP

BITS DESCRIPTIONS

[31:5] Reserved -

[4] ECMP

The ECMP(Enable CAM Compare) controls the enable of CAM

comparison function for destination MAC address recognition.

If S/W wants to receive a packet with specific destination MAC

address, configures the MAC address into anyone of 16 CAM entries,

then enables that CAM entry and set ECMP to 1.

1’b0: Disable CAM comparison function for destination MAC address

recognition.

1’b1: Enable CAM comparison function for destination MAC address

recognition.

[3] CCAM

The CCAM(Complement CAM Compare) controls the complement of

the CAM comparison result. If the ECMP and CCAM are both enabled,

the incoming packet with specific destination MAC address configured

in CAM entry will be dropped. And the incoming packet with

destination MAC address doesn’t configured in any CAM entry will be

received.

1’b0: The CAM comparison result doesn’t be complemented.

1’b1: The CAM comparison result will be complemented.

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Continued.

BITS DESCRIPTIONS

[2] ABP

The Accept Broadcast Packet controls the broadcast packet

reception. If ABP is enabled, EMC receives all incoming packet it’s

destination MAC address is a broadcast address.

1’b0: EMC receives packet depends on the CAM comparison result.

1’b1: EMC receives all broadcast packets.

[1] AMP

The Accept Multicast Packet controls the multicast packet reception.

If AMP is enabled, EMC receives all incoming packet it’s destination

MAC address is a multicast address.

1’b0: EMC receives packet depends on the CAM comparison result.

1’b1: EMC receives all multicast packets.

[0] AUP

The Accept Unicast Packet controls the unicast packet reception. If

AUP is enabled, EMC receives all incoming packet it’s destination

MAC address is a unicast address.

1’b0: EMC receives packet depends on the CAM comparison result.

1’b1: EMC receives all unicast packets.

CAMCMR SETTING AND COMPARISON RESULT

CAMCMR Setting and Comparison Result

The following table is the address recognition result in different CAMCMR configuration. The

column Result shows the incoming packet type that can pass the address recognition in specific

CAM configuration. The C, U, M and B represents the:

C: It indicates the destination MAC address of incoming packet has been configured in CAM entry.

U: It indicates the incoming packet is a unicast packet.

M: It indicates the incoming packet is a multicast packet.

B: It indicates the incoming packet is a broadcast packet.

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ECMP CCAM AUP AMP ABP RESULT

0 0 0 0 0 No Packet

0 0 0 0 1 B

0 0 0 1 0 M

0 0 0 1 1 M B

0 0 1 0 0 C U

0 0 1 0 1 C U B

0 0 1 1 0 C U M

0 0 1 1 1 C U M B

0 1 0 0 0 C U M B

0 1 0 0 1 C U M B

0 1 0 1 0 C U M B

0 1 0 1 1 C U M B

0 1 1 0 0 C U M B

0 1 1 0 1 C U M B

0 1 1 1 0 C U M B

0 1 1 1 1 C U M B

1 0 0 0 0 C

1 0 0 0 1 C B

1 0 0 1 0 C M

1 0 0 1 1 C N B

1 0 1 0 0 C U

1 0 1 0 1 C U B

1 0 1 1 0 C U M

1 0 1 1 1 C U M B

1 1 0 0 0 U M B

1 1 0 0 1 U M B

1 1 0 1 0 U M B

1 1 0 1 1 U M B

1 1 1 0 0 C U M B

1 1 1 0 1 C U M B

1 1 1 1 0 C U M B

1 1 1 1 1 C U M B

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CAM Enable Register (CAMEN)

The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before

it can participate in the destination MAC address recognition.

CAMEN 0xFFF0_3004 R/W CAM Enable Register 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

CAM15EN CAM14EN CAM13EN CAM12EN CAM11EN CAM10EN CAM9EN CAM8EN

7 6 5 4 3 2 1 0

CAM7EN CAM6EN CAM5EN CAM4EN CAM3EN CAM2EN CAM1EN CAM0EN

BITS DESCRIPTIONS

[31:16] Reserved

[15:13]

CAM15EN

CAM14EN

CAM13EN

The CAM entry 13, 14 and 15 are for PAUSE control frame

transmission. If S/W wants to transmit a PAUSE control frame out to

network, the enable bits of these three CAM entries all must be

enabled first.

[12] CAM12EN

CAM entry 12 is enabled

1’b0: CAM entry 12 disabled.

1’b1: CAM entry 12 enabled.

[11] CAM11EN

CAM entry 11 is enabled

1’b0: CAM entry 11 disabled.

1’b1: CAM entry 11 enabled.

[10] CAM10EN

CAM entry 10 is enabled

1’b0: CAM entry 10 disabled.

1’b1: CAM entry 10 enabled.

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Continued.

BITS DESCRIPTIONS

[9] CAM9EN

CAM entry 9 is enabled

1’b0: CAM entry 9 disabled.

1’b1: CAM entry 9 enabled.

[8] CAM8EN

CAM entry 8 is enabled

1’b0: CAM entry 8 disabled.

1’b1: CAM entry 8 enabled.

[7] CAM7EN

CAM entry 7 is enabled

1’b0: CAM entry 7 disabled.

1’b1: CAM entry 7 enabled.

[6] CAM6EN

CAM entry 6 is enabled

1’b0: CAM entry 6 disabled.

1’b1: CAM entry 6 enabled.

[5] CAM5EN

CAM entry 5 is enabled

1’b0: CAM entry 5 disabled.

1’b1: CAM entry 5 enabled.

[4] CAM4EN

CAM entry 4 is enabled

1’b0: CAM entry 4 disabled.

1’b1: CAM entry 4 enabled.

[3] CAM3EN

CAM entry 3 is enabled

1’b0: CAM entry 3 disabled.

1’b1: CAM entry 3 enabled.

[2] CAM2EN

CAM entry 2 is enabled

1’b0: CAM entry 2 disabled.

1’b1: CAM entry 2 enabled.

[1] CAM1EN

CAM entry 1 is enabled

1’b0: CAM entry 1 disabled.

1’b1: CAM entry 1 enabled.

[0] CAM0EN

CAM entry 0 is enabled

1’b0: CAM entry 0 disabled.

1’b1: CAM entry 0 enabled.

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Publication Release Date: July 26, 2006

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CAM Entry Registers (CAMxx)