PIC32MX FRM Section 31. DMA Controller PIC32 Family Reference Manual, Sect. 31
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- Section 31. DMA Controller
- 31.1 Introduction
- 31.2 Status and Control Registers
- Table 31-1: DMA Register Summary (Continued)
- Register 31-1: DMACON: DMA Controller Control Register(1,2,3) (Continued)
- Register 31-2: DMASTAT: DMA Status Register(1)
- Register 31-3: DMAADDR: DMA Address Register(1)
- Register 31-4: DCRCCON: DMA CRC Control Register(1,2,3) (Continued)
- Register 31-5: DCRCDATA: DMA CRC Data Register(1,2,3)
- Register 31-6: DCRCXOR: DMA CRCXOR Enable Register(1,2,3)
- Register 31-7: DCHxCON: DMA Channel x Control Register(1,2,3) (Continued)
- Register 31-8: DCHxECON: DMA Channel x Event Control Register(1,2,3) (Continued)
- Register 31-9: DCHxINT: DMA Channel x Interrupt Control Register(1,2,3) (Continued)
- Register 31-10: DCHxSSA: DMA Channel x Source Start Address Register(1,2,3)
- Register 31-11: DCHxDSA: DMA Channel x Destination Start Address Register
- Register 31-12: DCHxSSIZ: DMA Channel x Source Size Register(1,2,3)
- Register 31-13: DCHxDSIZ: DMA Channel x Destination Size Register(1,2,3)
- Register 31-14: DCHxSPTR: DMA Channel x Source Pointer Register(1)
- Register 31-15: DCHxDPTR: DMA Channel x Destination Pointer Register
- Register 31-16: DCHxCSIZ: DMA Channel x Cell-Size Register(1,2,3)
- Register 31-17: DCHxCPTR: DMA Channel x Cell Pointer Register(1)
- Register 31-18: DCHxDAT: DMA Channel x Pattern Data Register(1,2,3)
- 31.3 Modes of Operation
- 31.3.1 Basic Transfer Mode
- 31.3.2 Pattern Match Termination Mode
- 31.3.3 Channel Chaining Mode
- 31.3.4 Channel Auto-Enable Mode
- 31.3.5 Special Function Module (SFM) Mode
- Figure 31-4: Special Function Module (SFM)
- Example 31-4: DMA LFSR CRC Calculation in Background Mode Code Example
- Example 31-5: CRC Calculation in Append Mode Code Example
- Figure 31-5: Byte Order for BYTO Values
- Example 31-6: 16-bit CRC Polynomial
- Example 31-7: 32-bit CRC Polynomial
- Table 31-2: Example CRC Setup
- 31.3.6 Suspending Transfers
- 31.3.7 Resetting the Channel
- 31.3.8 Channel Priority and Selection
- 31.3.9 Byte Alignment
- 31.3.10 Channel Transfer Behavior
- 31.3.11 Channel Enable
- 31.3.12 Channel IRQ Detection
- 31.3.13 Channel Event Transfer Initiation
- 31.3.14 Channel Event Transfer Termination
- 31.3.15 Channel Abort Interrupt
- 31.3.16 Channel Abort
- 31.3.17 Address Error
- 31.3.18 DMA Suspend
- 31.4 Interrupts
- 31.5 Operation in Power-Saving and Debug Modes
- 31.6 Effects of Various Resets
- 31.7 Related Application Notes
- 31.8 Revision History
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