PIC32MZ Embedded Connectivity With Floating Point Unit (EF) Family Data Sheet EF Manual 60001320B

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TABLE 1: PIC32MZ EF Family Features
TABLE 2: Pin Names for 64-pin Devices
TABLE 3: Pin Names for 100-pin Devices
TABLE 4: Pin Names for 124-pin Devices
TABLE 5: Pin Names for 144-pin Devices
1.0 Device Overview
- FIGURE 1-1: PIC32MZ EF Family Block Diagram
- TABLE 1-1: ADC Pinout I/O Descriptions
- Table 1-2: Oscillator Pinout I/O Descriptions
- Table 1-3: IC1 through IC9 Pinout I/O Descriptions
- Table 1-4: OC1 Through OC9 Pinout I/O Descriptions
- Table 1-5: External Interrupts Pinout I/O Descriptions
- Table 1-6: PORTA through PORTK Pinout I/O Descriptions
- Table 1-7: Timer1 through Timer9 and RTCC Pinout I/O Descriptions
- Table 1-8: UART1 through UART6 Pinout I/O Descriptions
- Table 1-9: SPI1 through SPI 6 Pinout I/O Descriptions
- Table 1-10: I2C1 through I2C5 Pinout I/O Descriptions
- Table 1-11: Comparator 1, Comparator 2 and CVref Pinout I/O Descriptions
- Table 1-12: PMP Pinout I/O Descriptions
- Table 1-13: EBI Pinout I/O Descriptions
- Table 1-14: USB Pinout I/O Descriptions
- Table 1-15: CAN1 and CAN2 Pinout I/O Descriptions
- Table 1-16: Ethernet MII I/O Descriptions
- Table 1-17: Ethernet RMII Pinout I/O Descriptions
- Table 1-18: Alternate Ethernet MII Pinout I/O Descriptions
- Table 1-19: Alternate Ethernet RMII Pinout I/O Descriptions
- Table 1-20: SQI1 Pinout I/O Descriptions
- TABLE 1-21: Power, Ground, and Voltage Reference Pinout I/O Descriptions
- Table 1-22: JTAG, Trace, and Programming/Debugging Pinout I/O Descriptions
2.0 Guidelines for Getting Started with 32-bit Microcontrollers
- 2.1 Basic Connection Requirements
- 2.2 Decoupling Capacitors
  - FIGURE 2-1: Recommended Minimum Connection
- 2.3 Master Clear (MCLR) Pin
  - FIGURE 2-2: Example of MCLR Pin Connections
- 2.4 ICSP Pins
- 2.5 JTAG
- 2.6 Trace
- 2.7 External Oscillator Pins
  - FIGURE 2-3: Suggested Oscillator Circuit Placement
- 2.8 Unused I/Os
- 2.9 Designing for High-Speed Peripherals
- 2.10 Typical Application Connection Examples
  - FIGURE 2-6: Audio Playback Application
  - FIGURE 2-7: Low-cost Controllerless (LCC) Graphics Application With Projected Capacitive Touch
3.0 CPU
- FIGURE 3-1: PIC32MZ EF Family Microprocessor Core Block Diagram
- 3.1 Architecture Overview
- 3.2 Power Management
- 3.3 L1 Instruction and Data Caches
- 3.4 EJTAG Debug Support
- 3.5 MIPS DSP ASE Extension
- 3.6 microMIPS ISA
- 3.7 M-Class Core Configuration
4.0 Memory Organization
- 4.1 Memory Layout
- 4.2 System Bus Arbitration
  - Table 4-4: Initiators to Targets Access Association
  - Table 4-5: Initiator ID and QOS
- 4.3 Permission Access and System Bus Registers
5.0 Flash Program Memory
- 5.1 Flash Control Registers
6.0 Resets
- FIGURE 6-1: System Reset Block Diagram
- 6.1 Reset Control Registers
7.0 CPU Exceptions and Interrupt Controller
- FIGURE 7-1: CPU Exceptions and Interrupt Controller Module Block Diagram
- 7.1 CPU Exceptions
  - Table 7-1: MIPS32® M-Class Microprocessor Core Exception Types
- 7.2 Interrupts
  - Table 7-2: Interrupt IRQ, Vector, and Bit Location
- 7.3 Interrupt Control Registers
8.0 Oscillator Configuration
- FIGURE 8-1: PIC32MZ EF Family Oscillator Diagram
- Table 8-1: System and Peripheral clock Distribution
- 8.1 Fail-Safe Clock Monitor (FSCM)
- 8.2 Oscillator Control Registers
9.0 Prefetch Module
- FIGURE 9-1: Prefetch Module Block Diagram
- 9.1 Prefetch Control Registers
10.0 Direct Memory Access (DMA) Controller
- FIGURE 10-1: DMA Block Diagram
- 10.1 DMA Control Registers
11.0 Hi-Speed USB with On- The-Go (OTG)
- FIGURE 11-1: PIC32MZ EF Family USB Interface Diagram
- 11.1 USB OTG Control Registers
12.0 I/O Ports
- FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure
- 12.1 Parallel I/O (PIO) Ports
- 12.2 Registers for Slew Rate Control
  - Table 12-1: Slew Rate Control Bit Settings
- 12.3 CLR, SET, and INV Registers
- 12.4 Peripheral Pin Select (PPS)
- 12.5 I/O Ports Control Registers
13.0 Timer1
- 13.1 Additional Supported Features
  - FIGURE 13-1: Timer1 Block Diagram
- 13.2 Timer1 Control Register
  - TABLE 13-1: Timer1 Register Map
  - Register 13-1: T1CON: Type A Timer Control Register
14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9
- 14.1 Additional Supported Features
  - FIGURE 14-1: Timer2 through Timer9 Block Diagram (16-bit)
  - FIGURE 14-2: Timer2/3, Timer4/5, Timer6/7, and Timer8/9 Block Diagram (32-bit)
- 14.2 Timer2-Timer9 Control Registers
  - TABLE 14-1: Timer2 THROUGH Timer9 Register Map
  - Register 14-1: TxCON: Type B Timer Control Register (‘x’ = 2-9)
15.0 Deadman Timer (DMT)
- FIGURE 15-1: Deadman Timer Block diagram
- 15.1 Deadman Timer Control Registers
16.0 Watchdog Timer (WDT)
- Figure 16-1: Watchdog Timer Block Diagram
- 16.1 Watchdog Timer Control Registers
  - TABLE 16-1: Watchdog Timer Register Map
  - Register 16-1: WDTCON: Watchdog Timer Control Register
17.0 Input Capture
- FIGURE 17-1: Input Capture Block Diagram
- Table 17-1: Timer Source Configurations
- 17.1 Input Capture Control Registers
  - TABLE 17-2: Input Capture 1 THROUGH Input Capture 9 Register Map
  - Register 17-1: ICxCON: Input Capture x Control Register
18.0 Output Compare
- FIGURE 18-1: Output Compare Module Block Diagram
- Table 18-1: Timer Source Configurations
- 18.1 Output Compare Control Registers
  - TABLE 18-2: Output Compare 1 THROUGH Output Compare 9 Register Map
  - Register 18-1: OCxCON: Output Compare ‘x’ Control Register
19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)
- FIGURE 19-1: SPI/I2S Module Block Diagram
- 19.1 SPI Control Registers
20.0 Serial Quad Interface (SQI)
- FIGURE 20-1: SQI Module Block Diagram
- 20.1 SQI Control Registers
21.0 Inter-Integrated Circuit™ (I2C™)
- FIGURE 21-1: I2C™ Block Diagram
- 21.1 I2C Control Registers
22.0 Universal Asynchronous Receiver Transmitter (UART)
- FIGURE 22-1: UART Simplified Block Diagram
- 22.1 UART Control Registers
23.0 Parallel Master Port (PMP)
- FIGURE 23-1: PMP Module Pinout and Connections to External Devices
- 23.1 PMP Control Registers
24.0 External Bus Interface (EBI)
- Table 24-1: EBI Module FEATURES
- FIGURE 24-1: EBI System Block Diagram
- 24.1 EBI Control Registers
25.0 Real-Time Clock and Calendar (RTCC)
- FIGURE 25-1: RTCC Block Diagram
- 25.1 RTCC Control Registers
26.0 Crypto Engine
- Table 26-1: Crypto Engine Performance
- FIGURE 26-1: Crypto Engine Block Diagram
- 26.1 Crypto Engine Control Registers
- 26.2 Crypto Engine Buffer Descriptors
- 26.3 Security Association Structure
  - Table 26-4: Crypto Engine Security Association Structure
  - FIGURE 26-10: Format of SA_CTRL
27.0 Random Number Generator (RNG)
- Table 27-1: Random Number Generator Block Diagram
- 27.1 RNG Control Registers
28.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to- Digital Converter (ADC)
- FIGURE 28-1: ADC Block Diagram
- FIGURE 28-2: S&H Block Diagram
- FIGURE 28-3: FIFO Block Diagram
- 28.1 ADC Control Registers
29.0 Controller Area Network (CAN)
- FIGURE 29-1: PIC32 CAN Module Block Diagram
- 29.1 CAN Control Registers
30.0 Ethernet Controller
- FIGURE 30-1: Ethernet Controller Block Diagram
- TABLE 30-1: MII Mode Default Interface Signals (FMIIEN = 1, FETHIO = 1)
- TABLE 30-2: RMII Mode Default Interface Signals (FMIIEN = 0, FETHIO = 1)
- TABLE 30-3: MII Mode Alternate Interface Signals (FMIIEN = 1, FETHIO = 0)
- TABLE 30-4: RMII Mode Alternate Interface Signals (FMIIEN = 0, FETHIO = 0)
- 30.1 Ethernet Control Registers
31.0 Comparator
- FIGURE 31-1: Comparator Block Diagram
- 31.1 Comparator Control Registers
32.0 Comparator Voltage Reference (CVref)
- FIGURE 32-1: Comparator Voltage Reference Block Diagram
- 32.1 Comparator Voltage Reference Control Registers
  - TABLE 32-1: Comparator Voltage Reference Register Map
  - Register 32-1: CVRCON: Comparator Voltage Reference Control Register
33.0 Power-Saving Features
- 33.1 Power Saving with CPU Running
- 33.2 Power-Saving with CPU Halted
- 33.3 Peripheral Module Disable
  - Table 33-1: Peripheral Module Disable Bits and Locations(1)
  - TABLE 33-2: Peripheral Module Disable Register Summary
34.0 Special Features
- 34.1 Configuration Bits
- 34.2 Registers
- 34.3 On-Chip Voltage Regulator
- 34.4 On-chip Temperature Sensor
- 34.5 Programming and Diagnostics
  - Figure 34-1: Block Diagram of Programming, Debugging and Trace Ports
35.0 Instruction Set
36.0 Development Support
- 36.1 MPLAB X Integrated Development Environment Software
- 36.2 MPLAB XC Compilers
- 36.3 MPASM Assembler
- 36.4 MPLINK Object Linker/ MPLIB Object Librarian
- 36.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 36.6 MPLAB X SIM Software Simulator
- 36.7 MPLAB REAL ICE In-Circuit Emulator System
- 36.8 MPLAB ICD 3 In-Circuit Debugger System
- 36.9 PICkit 3 In-Circuit Debugger/ Programmer
- 36.10 MPLAB PM3 Device Programmer
- 36.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 36.12 Third-Party Development Tools
37.0 Electrical Characteristics
- 37.1 DC Characteristics
- 37.2 AC Characteristics and Timing Parameters
38.0 AC and DC Characteristics Graphs
- FIGURE 38-1: Voh – 4x Driver Pins
- FIGURE 38-2: Vol – 4x Driver Pins
- FIGURE 38-3: Voh – 8x Driver Pins
- FIGURE 38-4: Vol – 8x Driver Pins
- FIGURE 38-5: Voh – 12x Driver Pins
- FIGURE 38-6: Vol – 12x Driver Pins
- FIGURE 38-7: Typical Temperature Sensor Voltage
39.0 Packaging Information
- 39.1 Package Marking Information
- 39.1 Package Marking Information (Continued)
- 39.2 Package Details
Appendix A: Migrating from PIC32MX5XX/6XX/7XX to PIC32MZ EF
- TABLE A-1: Oscillator Configuration differences
- TABLE A-2: Code Differences for Maximum Speed using an External 24 MHz Crystal
- TABLE A-3: ADC Differences
- TABLE A-4: CPU Differences
- TABLE A-5: Reset Differences
- TABLE A-6: USB Differences
- TABLE A-7: DMA Differences
- TABLE A-8: Interrupt Differences
- TABLE A-9: Flash Programming Differences
- TABLE A-10: Peripheral Differences
- TABLE A-11: Package Differences
Appendix B: Migrating from PIC32MZ EC to PIC32MZ EF
- TABLE B-1: Oscillator Differences
- TABLE B-2: ADC Differences
- TABLE B-3: System Bus Differences
- TABLE B-4: Flash Controller Differences
- TABLE B-5: Resets Differences
- TABLE B-6: Watchdog Timer Differences
- TABLE B-7: Crypto Differences
- TABLE B-8: Device Configuration and Control Differences
Appendix C: Revision History
- TABLE C-1: Major Section Updates
INDEX
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