PIC32MZ Embedded Connectivity With Floating Point Unit (EF) Family Data Sheet EF Manual 60001320B
User Manual:
Open the PDF directly: View PDF
Page Count: 718 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- TABLE 1: PIC32MZ EF Family Features
- TABLE 2: Pin Names for 64-pin Devices
- TABLE 3: Pin Names for 100-pin Devices
- TABLE 4: Pin Names for 124-pin Devices
- TABLE 5: Pin Names for 144-pin Devices
- 1.0 Device Overview
- FIGURE 1-1: PIC32MZ EF Family Block Diagram
- TABLE 1-1: ADC Pinout I/O Descriptions
- Table 1-2: Oscillator Pinout I/O Descriptions
- Table 1-3: IC1 through IC9 Pinout I/O Descriptions
- Table 1-4: OC1 Through OC9 Pinout I/O Descriptions
- Table 1-5: External Interrupts Pinout I/O Descriptions
- Table 1-6: PORTA through PORTK Pinout I/O Descriptions
- Table 1-7: Timer1 through Timer9 and RTCC Pinout I/O Descriptions
- Table 1-8: UART1 through UART6 Pinout I/O Descriptions
- Table 1-9: SPI1 through SPI 6 Pinout I/O Descriptions
- Table 1-10: I2C1 through I2C5 Pinout I/O Descriptions
- Table 1-11: Comparator 1, Comparator 2 and CVref Pinout I/O Descriptions
- Table 1-12: PMP Pinout I/O Descriptions
- Table 1-13: EBI Pinout I/O Descriptions
- Table 1-14: USB Pinout I/O Descriptions
- Table 1-15: CAN1 and CAN2 Pinout I/O Descriptions
- Table 1-16: Ethernet MII I/O Descriptions
- Table 1-17: Ethernet RMII Pinout I/O Descriptions
- Table 1-18: Alternate Ethernet MII Pinout I/O Descriptions
- Table 1-19: Alternate Ethernet RMII Pinout I/O Descriptions
- Table 1-20: SQI1 Pinout I/O Descriptions
- TABLE 1-21: Power, Ground, and Voltage Reference Pinout I/O Descriptions
- Table 1-22: JTAG, Trace, and Programming/Debugging Pinout I/O Descriptions
- 2.0 Guidelines for Getting Started with 32-bit Microcontrollers
- 3.0 CPU
- FIGURE 3-1: PIC32MZ EF Family Microprocessor Core Block Diagram
- 3.1 Architecture Overview
- 3.2 Power Management
- 3.3 L1 Instruction and Data Caches
- 3.4 EJTAG Debug Support
- 3.5 MIPS DSP ASE Extension
- 3.6 microMIPS ISA
- 3.7 M-Class Core Configuration
- Register 3-1: Config: Configuration Register; CP0 Register 16, Select 0
- Register 3-2: Config1: Configuration Register 1; CP0 Register 16, Select 1
- Register 3-3: Config3: Configuration Register 3; CP0 Register 16, Select 3
- Register 3-4: Config5: Configuration Register 5; CP0 Register 16, Select 5
- Register 3-5: Config7: Configuration Register 7; CP0 Register 16, Select 7
- Register 3-6: FIR: Floating Point Implementation Register; CP1 Register 0
- Register 3-7: FCCR: Floating Point Condition Codes Register; CP1 Register 25
- Register 3-8: FEXR: Floating Point Exceptions Status Register; CP1 Register 26
- Register 3-9: FENR: Floating Point Exceptions and Modes Enable Register; CP1 Register 28
- Register 3-10: FCSR: Floating Point Control and Status Register; CP1 Register 31
- 4.0 Memory Organization
- 4.1 Memory Layout
- FIGURE 4-1: Memory Map for Devices With 512 KB of Program Memory(1,2)
- FIGURE 4-2: Memory Map for Devices With 1024 KB of Program Memory and 256 KB of Ram(1,2)
- FIGURE 4-3: Memory Map for Devices With 1024 KB of Program Memory and 512 KB of Ram(1,2)
- FIGURE 4-4: Memory Map for Devices With 2048 KB of Program Memory(1,2)
- FIGURE 4-5: Boot and Alias Memory Map
- Table 4-1: SFR Memory Map
- TABLE 4-2: Boot Flash 1 Sequence and Configuration Words Summary
- TABLE 4-3: Boot Flash 2 Sequence and Configuration Words Summary
- Register 4-1: BFxSEQ0/ABFxSEQ0: Boot Flash ‘x’ Sequence Word 0 Register (‘x’ = 1 and 2)
- 4.2 System Bus Arbitration
- 4.3 Permission Access and System Bus Registers
- Table 4-6: System Bus Targets and Associated Protection Registers
- TABLE 4-7: System Bus Register Map
- TABLE 4-8: System Bus Target 0 Register Map
- TABLE 4-9: System Bus Target 1 Register Map
- TABLE 4-10: System Bus Target 2 Register Map
- TABLE 4-11: System Bus Target 3 Register Map
- TABLE 4-12: System Bus Target 4 Register Map
- TABLE 4-13: System Bus Target 5 Register Map
- TABLE 4-14: System Bus Target 6 Register Map
- TABLE 4-15: System Bus Target 7 Register Map
- TABLE 4-16: System Bus Target 8 Register Map
- TABLE 4-17: System Bus Target 9 Register Map
- TABLE 4-18: System Bus Target 10 Register Map
- TABLE 4-19: System Bus Target 11 Register Map
- TABLE 4-20: System Bus Target 12 Register Map
- TABLE 4-21: System Bus Target 13 Register Map
- Register 4-2: SBFLAG: System Bus Status Flag Register
- Register 4-3: SBTxELOG1: System Bus Target ‘x’ Error Log Register 1 (‘x’ = 0-13)
- Register 4-4: SBTxELOG2: System Bus Target ‘x’ Error Log Register 2 (‘x’ = 0-13)
- Register 4-5: SBTxECON: System Bus Target ‘x’ Error Control Register (‘x’ = 0-13)
- Register 4-6: SBTxECLRS: System Bus Target ‘x’ Single Error Clear Register (‘x’ = 0-13)
- Register 4-7: SBTxECLRM: System Bus Target ‘x’ Multiple Error Clear Register (‘x’ = 0-13)
- Register 4-8: SBTxREGy: System Bus Target ‘x’ Region ‘y’ Register (‘x’ = 0-13; ‘y’ = 0-8)
- Register 4-9: SBTxRDy: System Bus Target ‘x’ Region ‘y’ Read Permissions Register (‘x’ = 0-13; ‘y’ = 0-8)
- Register 4-10: SBTxWRy: System Bus Target ‘x’ Region ‘y’ Write Permissions Register (‘x’ = 0-13; ‘y’ = 0-8)
- 4.1 Memory Layout
- 5.0 Flash Program Memory
- 5.1 Flash Control Registers
- TABLE 5-1: Flash Controller Register Map
- Register 5-1: NVMCON: Flash Programming Control Register
- Register 5-2: NVMCON2: Flash Programming Control Register 2
- Register 5-3: NVMKEY: Programming Unlock Register
- Register 5-4: NVMADDR: Flash Address Register
- Register 5-5: NVMDATAx: Flash Data Register (x = 0-3)
- Register 5-6: NVMSRCADDR: Source Data Address Register
- Register 5-7: NVMPWP: Program Flash Write-Protect Register
- Register 5-8: NVMBWP: Flash Boot (Page) Write-Protect Register
- 5.1 Flash Control Registers
- 6.0 Resets
- 7.0 CPU Exceptions and Interrupt Controller
- FIGURE 7-1: CPU Exceptions and Interrupt Controller Module Block Diagram
- 7.1 CPU Exceptions
- 7.2 Interrupts
- 7.3 Interrupt Control Registers
- Table 7-3: Interrupt Register Map
- Register 7-1: INTCON: Interrupt Control Register
- Register 7-2: PRISS: Priority Shadow Select Register
- Register 7-3: INTSTAT: Interrupt Status Register
- Register 7-4: IPTMR: Interrupt Proximity Timer Register
- Register 7-5: IFSx: Interrupt Flag Status Register
- Register 7-6: IECx: Interrupt Enable Control Register
- Register 7-7: IPCx: Interrupt Priority Control Register
- Register 7-8: OFFx: Interrupt Vector Address Offset Register (x = 0-190)
- 8.0 Oscillator Configuration
- FIGURE 8-1: PIC32MZ EF Family Oscillator Diagram
- Table 8-1: System and Peripheral clock Distribution
- 8.1 Fail-Safe Clock Monitor (FSCM)
- 8.2 Oscillator Control Registers
- TABLE 8-2: Oscillator Configuration Register Map
- Register 8-1: OSCCON: Oscillator Control Register
- Register 8-2: OSCTUN: FRC Tuning Register
- Register 8-3: SPLLCON: System PLL Control Register
- Register 8-4: REFOxCON: Reference Oscillator Control Register (‘x’ = 1-4)
- Register 8-5: REFOxTRIM: Reference Oscillator Trim Register (‘x’ = 1-4)
- Register 8-6: PBxDIV: Peripheral Bus ‘x’ Clock Divisor Control Register (‘x’ = 1-7)
- Register 8-7: SLEWCON: Oscillator Slew Control Register
- Register 8-8: CLKSTAT: Oscillator Clock Status Register
- 9.0 Prefetch Module
- 10.0 Direct Memory Access (DMA) Controller
- FIGURE 10-1: DMA Block Diagram
- 10.1 DMA Control Registers
- TABLE 10-1: DMA Global Register Map
- TABLE 10-2: DMA CRC Register Map
- TABLE 10-3: DMA Channel 0 THROUGH Channel 7 Register Map
- Register 10-1: DMACON: DMA Controller Control Register
- Register 10-2: DMASTAT: DMA Status Register
- Register 10-3: DMAADDR: DMA Address Register
- Register 10-4: DCRCCON: DMA CRC Control Register
- Register 10-5: DCRCDATA: DMA CRC Data Register
- Register 10-6: DCRCXOR: DMA CRCXOR Enable Register
- Register 10-7: DCHxCON: DMA Channel x Control Register
- Register 10-8: DCHxECON: DMA Channel x Event Control Register
- Register 10-9: DCHxINT: DMA Channel x Interrupt Control Register
- Register 10-10: DCHxSSA: DMA Channel x Source Start Address Register
- Register 10-11: DCHxDSA: DMA Channel x Destination Start Address Register
- Register 10-12: DCHxSSIZ: DMA Channel x Source Size Register
- Register 10-13: DCHxDSIZ: DMA Channel x Destination Size Register
- Register 10-14: DCHxSPTR: DMA Channel x Source Pointer Register
- Register 10-15: DCHxDPTR: DMA Channel x Destination Pointer Register
- Register 10-16: DCHxCSIZ: DMA Channel x Cell-Size Register
- Register 10-17: DCHxCPTR: DMA Channel x Cell Pointer Register
- Register 10-18: DCHxDAT: DMA Channel x Pattern Data Register
- 11.0 Hi-Speed USB with On- The-Go (OTG)
- FIGURE 11-1: PIC32MZ EF Family USB Interface Diagram
- 11.1 USB OTG Control Registers
- TABLE 11-1: USB Register Map 1
- TABLE 11-2: USB Register Map 2
- Register 11-1: USBCSR0: USB Control Status Register 0
- Register 11-2: USBCSR1: USB Control Status Register 1
- Register 11-3: USBCSR2: USB Control Status Register 2
- Register 11-4: USBCSR3: USB Control Status Register 3
- Register 11-5: USBIE0CSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 0)
- Register 11-6: USBIE0CSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 0)
- Register 11-7: USBIE0CSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 0)
- Register 11-8: USBIENCSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7)
- Register 11-9: USBIENCSR1: USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7)
- Register 11-10: USBIENCSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 1-7)
- Register 11-11: USBIENCSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 1-7)
- Register 11-12: USBFIFOx: USB FIFO Data Register ‘x’ (‘x’ = 0-7)
- Register 11-13: USBOTG: USB OTG Control/Status Register
- Register 11-14: USBFIFOA: USB FIFO Address Register
- Register 11-15: USBHWVER: USB Hardware Version Register
- Register 11-16: USBINFO: USB Information Register
- Register 11-17: USBEOFRST: USB End-of-Frame/Soft Reset Control Register
- Register 11-18: USBEXTXA: USB Endpoint ‘x’ Transmit Address Register
- Register 11-19: USBExRXA: USB Endpoint ‘x’ Receive Address Register
- Register 11-20: USBDMAINT: USB DMA Interrupt Register
- Register 11-21: USBDMAxC: USB DMA Channel ‘x’ Control Register (‘x’ = 1-8)
- Register 11-22: USBDMAxA: USB DMA Channel ‘x’ Memory Address Register (‘x’ = 1-8)
- Register 11-23: USBDMAxN: USB DMA Channel ‘x’ Count Register (‘x’ = 1-8)
- Register 11-24: USBEXRPC: USB Endpoint ‘x’ Request Packet Count Register (Host Mode Only) (‘x’ = 1-7)
- Register 11-25: USBDPBFD: USB Double Packet Buffer Disable Register
- Register 11-26: USBTMCON1: USB Timing Control Register 1
- Register 11-27: USBTMCON2: USB Timing Control Register 2
- Register 11-28: USBLPMR1: USB Link Power Management Control Register 1
- Register 11-29: USBLPMR2: USB Link Power Management Control Register 2
- Register 11-30: USBCRCon: USB Clock/Reset Control Register
- 12.0 I/O Ports
- FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure
- 12.1 Parallel I/O (PIO) Ports
- 12.2 Registers for Slew Rate Control
- 12.3 CLR, SET, and INV Registers
- 12.4 Peripheral Pin Select (PPS)
- 12.5 I/O Ports Control Registers
- TABLE 12-4: PORTA Register Map for 100-pin, 124-pin, and 144-pin devices Only
- TABLE 12-5: PORTB Register Map
- TABLE 12-6: PORTC Register Map for 100-pin, 124-pin, and 144-pin Devices Only
- TABLE 12-7: PORTC Register Map for 64-pin Devices Only
- TABLE 12-8: PORTD Register Map for 124-pin and 144-pin Devices Only
- TABLE 12-9: PORTD Register Map for 100-pin Devices Only
- TABLE 12-10: PORTD Register Map for 64-pin Devices Only
- TABLE 12-11: PORTE Register Map for 100-pin, 124-pin, and 144-pin Devices Only
- TABLE 12-12: PORTE Register Map for 64-pin Devices Only
- TABLE 12-13: PORTF Register Map for 100-pin, 124-pin, and 144-pin Devices Only
- TABLE 12-14: PORTF Register Map for 64-pin Devices Only
- TABLE 12-15: PORTG Register Map for 100-pin, 124-pin, and 144-pin Devices Only
- TABLE 12-16: PORTG Register Map for 64-pin Devices Only
- TABLE 12-17: PORTH Register Map for 124-pin Devices Only
- TABLE 12-18: PORTH Register Map for 144-pin Devices Only
- TABLE 12-19: PORTJ Register Map for 124-pin Devices Only
- TABLE 12-20: PORTJ Register Map for 144-pin Devices Only
- TABLE 12-21: PORTK Register Map for 144-pin Devices Only
- Table 12-22: Peripheral Pin Select Input Register Map
- Table 12-23: Peripheral Pin Select Output Register Map
- Register 12-1: [pin name]R: Peripheral Pin Select Input Register
- Register 12-2: RPnR: Peripheral Pin Select Output Register
- Register 12-3: CNCONx: Change Notice control for PORTx Register (x = A – K)
- 13.0 Timer1
- 14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9
- 15.0 Deadman Timer (DMT)
- FIGURE 15-1: Deadman Timer Block diagram
- 15.1 Deadman Timer Control Registers
- TABLE 15-1: Deadman Timer Register Map
- Register 15-1: DMTCON: Deadman Timer Control Register
- Register 15-2: DMTPRECLR: Deadman Timer Preclear Register
- Register 15-3: DMTCLR: Deadman Timer Clear Register
- Register 15-4: DMTSTAT: Deadman Timer Status Register
- Register 15-5: DMTCNT: Deadman Timer Count Register
- Register 15-6: DMTPSCNT: Post Status Configure DMT Count Status Register
- Register 15-7: DMTPSINTV: Post Status Configure DMT Interval Status Register
- 16.0 Watchdog Timer (WDT)
- 17.0 Input Capture
- 18.0 Output Compare
- 19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)
- 20.0 Serial Quad Interface (SQI)
- FIGURE 20-1: SQI Module Block Diagram
- 20.1 SQI Control Registers
- Table 20-1: Serial Quadrature Interface (SQI) Register Map
- Register 20-1: SQI1XCON1: SQI XIP Control Register 1
- Register 20-2: SQI1XCON2: SQI XIP Control Register 2
- Register 20-3: SQI1CFG: SQI Configuration Register
- Register 20-4: SQI1CON: SQI Control Register
- Register 20-5: SQI1CLKCON: SQI Clock Control Register
- Register 20-6: SQI1CMDTHR: SQI Command Threshold Register
- Register 20-7: SQI1INTTHR: SQI Interrupt Threshold Register
- Register 20-8: SQI1INTEN: SQI Interrupt Enable Register
- Register 20-9: SQI1INTSTAT: SQI Interrupt Status Register
- Register 20-10: SQI1TXDATA: SQI Transmit Data Buffer Register
- Register 20-11: SQI1RXDATA: SQI Receive Data Buffer Register
- Register 20-12: SQI1STAT1: SQI Status Register 1
- Register 20-13: SQI1STAT2: SQI Status Register 2
- Register 20-14: SQI1BDCON: SQI Buffer Descriptor Control Register
- Register 20-15: SQI1BDCurADD: SQI Buffer Descriptor Current Address Register
- Register 20-16: SQI1BDBASEADD: SQI Buffer Descriptor Base Address Register
- Register 20-17: SQI1BDSTAT: SQI Buffer Descriptor Status Register
- Register 20-18: SQI1BDPOLLCON: SQI Buffer Descriptor Poll Control Register
- Register 20-19: SQI1BDTXDSTAT: SQI Buffer Descriptor DMA Transmit Status Register
- Register 20-20: SQI1BDRXDSTAT: SQI Buffer Descriptor DMA Receive Status Register
- Register 20-21: SQI1THR: SQI Threshold Control Register
- Register 20-22: SQI1INTSIGEN: SQI Interrupt Signal Enable Register
- Register 20-23: SQI1TAPCON: SQI TAP Control Register
- Register 20-24: SQI1MEMSTAT: SQI Memory Status Register
- Register 20-25: SQI1XCON3: SQI XIP Control Register 3
- Register 20-26: SQI1XCON4: SQI XIP Control Register 4
- 21.0 Inter-Integrated Circuit™ (I2C™)
- 22.0 Universal Asynchronous Receiver Transmitter (UART)
- 23.0 Parallel Master Port (PMP)
- FIGURE 23-1: PMP Module Pinout and Connections to External Devices
- 23.1 PMP Control Registers
- TABLE 23-1: Parallel Master Port Register Map
- Register 23-1: PMCON: Parallel Port Control Register
- Register 23-2: PMMODE: Parallel Port Mode Register
- Register 23-3: PMADDR: Parallel Port Address Register
- Register 23-4: PMDOUT: Parallel Port Output Data Register
- Register 23-5: PMDIN: Parallel Port Input Data Register
- Register 23-6: PMAEN: Parallel Port Pin Enable Register
- Register 23-7: PMSTAT: Parallel Port Status Register (Slave modes only)
- Register 23-8: PMWADDR: Parallel Port Write Address Register
- Register 23-9: PMRADDR: Parallel Port Read Address Register
- Register 23-10: PMRDIN: Parallel Port Read Input Data Register
- 24.0 External Bus Interface (EBI)
- Table 24-1: EBI Module FEATURES
- FIGURE 24-1: EBI System Block Diagram
- 24.1 EBI Control Registers
- TABLE 24-2: EBI Register Map
- Register 24-1: EBICSX: External Bus Interface Chip Select Register (‘x’ = 0-3)
- Register 24-2: EBIMSKx: External Bus Interface Address Mask Register (‘x’ = 0-3)
- Register 24-3: EBISMTx: External Bus Interface Static Memory Timing Register (‘x’ = 0-2)
- Register 24-4: EBIFTRPD: External Bus Interface Flash Timing Register
- Register 24-5: EBISMCON: External Bus Interface Static Memory Control Register
- 25.0 Real-Time Clock and Calendar (RTCC)
- FIGURE 25-1: RTCC Block Diagram
- 25.1 RTCC Control Registers
- TABLE 25-1: RTCC Register Map
- Register 25-1: RTCCON: Real-Time Clock and Calendar Control Register
- Register 25-2: RTCALRM: Real-Time Clock ALARM Control Register
- Register 25-3: RTCTIME: Real-Time Clock Time Value Register
- Register 25-4: RTCDATE: Real-Time Clock Date Value Register
- Register 25-5: ALRMTIME: Alarm Time Value Register
- Register 25-6: ALRMDATE: Alarm Date Value Register
- 26.0 Crypto Engine
- Table 26-1: Crypto Engine Performance
- FIGURE 26-1: Crypto Engine Block Diagram
- 26.1 Crypto Engine Control Registers
- Table 26-2: Crypto Engine Register Map
- Register 26-1: CEVER: Crypto Engine Revision, Version, and ID Register
- Register 26-2: CECON: Crypto Engine Control Register
- Register 26-3: CEBDADDR: Crypto Engine Buffer Descriptor Register
- Register 26-4: CEBDPADDR: Crypto Engine Buffer Descriptor Processor Register
- Register 26-5: CESTAT: Crypto Engine Status Register
- Register 26-6: CEINTSRC: Crypto Engine Interrupt Source Register
- Register 26-7: CEINTEN: Crypto Engine Interrupt Enable Register
- Register 26-8: CEPOLLCON: Crypto Engine Poll Control Register
- Register 26-9: CEHDLEN: Crypto Engine Header Length Register
- Register 26-10: CETRLLEN: Crypto Engine Trailer Length Register
- 26.2 Crypto Engine Buffer Descriptors
- Table 26-3: Crypto Engine Buffer Descriptors
- FIGURE 26-2: Format of BD_CTRL
- FIGURE 26-3: Format of BD_SADDR
- FIGURE 26-4: Format of BD_SRCADDR
- FIGURE 26-5: Format of BD_DSTADDR
- FIGURE 26-6: Format of BD_NXTADDR
- FIGURE 26-7: Format of BD_UPDPTR
- FIGURE 26-8: Format of BD_MSG_LEN
- FIGURE 26-9: Format of BD_ENC_OFF
- 26.3 Security Association Structure
- 27.0 Random Number Generator (RNG)
- Table 27-1: Random Number Generator Block Diagram
- 27.1 RNG Control Registers
- Table 27-2: Random Number Generator (RNG) Register Map
- Register 27-1: RNGVER: Random Number Generator Version Register
- Register 27-2: RNGCON: Random Number Generator Control Register
- Register 27-3: RNGPOLYx: Random nUMBER Generator Polynomial Register ‘x’ (‘x’ = 1 or 2)
- Register 27-4: RNGNUMGENx: Random nUMBER Generator Register ‘x’ (‘x’ = 1 or 2)
- Register 27-5: RNGSEEDx: True Random Number Generator Seed Register ‘x’ (‘x’ = 1 or 2)
- Register 27-6: RNGCNT: True Random Number Generator Count Register
- 28.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to- Digital Converter (ADC)
- FIGURE 28-1: ADC Block Diagram
- FIGURE 28-2: S&H Block Diagram
- FIGURE 28-3: FIFO Block Diagram
- 28.1 ADC Control Registers
- Table 28-1: ADC Register Map
- Register 28-1: ADCCON1: ADC Control Register 1
- Register 28-2: ADCCON2: ADC Control Register 2
- Register 28-3: ADCCON3: ADC Control Register 3
- Register 28-4: ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register
- Register 28-5: ADCIMCON1: ADC Input Mode Control Register 1
- Register 28-6: ADCIMCON2: ADC Input Mode Control Register 2
- Register 28-7: ADCIMCON3: ADC Input Mode Control Register 3
- Register 28-8: ADCGIRQEN1: ADC Global Interrupt Enable Register 1
- Register 28-9: ADCGIRQEN2: ADC Global Interrupt Enable Register 2
- Register 28-10: ADCCSS1: ADC Common Scan Select Register 1
- Register 28-11: ADCCSS2: ADC Common Scan Select Register 2
- Register 28-12: ADCDSTAT1: ADC Data Ready Status Register 1
- Register 28-13: ADCDSTAT2: ADC Data Ready Status Register 2
- Register 28-14: ADCCMPENx: ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6)
- Register 28-15: ADCCMPx: ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6)
- Register 28-16: ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ = 1 through 6)
- Register 28-17: ADCTRG1: ADC Trigger Source 1 Register
- Register 28-18: ADCTRG2: ADC Trigger Source 2 Register
- Register 28-19: ADCTRG3: ADC Trigger Source 3 Register
- Register 28-20: ADCCMPCON1: ADC Digital Comparator 1 Control Register
- Register 28-21: ADCCMPCONx: ADC Digital Comparator ‘x’ Control Register (‘x’ = 2 through 6)
- Register 28-22: ADCFSTAT: ADC FIFO Status Register
- Register 28-23: ADCFIFO: ADC FIFO Data Register
- Register 28-24: ADCBASE: ADC Base Register
- Register 28-25: ADCDATAx: ADC Output Data Register (‘x’ = 0 through 44)
- Register 28-26: ADCTRGSNS: ADC Trigger Level/Edge Sensitivity Register
- Register 28-27: ADCxTIME: Dedicated ADCx Timing Register ‘x’ (‘x’ = 0 through 4)
- Register 28-28: ADCEIEN1: ADC Early Interrupt Enable Register 1
- Register 28-29: ADCEIEN2: ADC Early Interrupt Enable Register 2
- Register 28-30: ADCEISTAT1: ADC Early Interrupt Status Register 1
- Register 28-31: ADCEISTAT2: ADC Early Interrupt Status Register 2
- Register 28-32: ADCANCON: ADC Analog Warm-up Control Register
- Register 28-33: ADCxCFG: ADCx Configuration Register ‘x’ (‘x’ = 1 through 4 and 7)
- Register 28-34: ADCSYSCFG1: ADC System Configuration Register 1
- Register 28-35: ADCSYSCFG2: ADC System Configuration Register 2
- 29.0 Controller Area Network (CAN)
- FIGURE 29-1: PIC32 CAN Module Block Diagram
- 29.1 CAN Control Registers
- TABLE 29-1: CAN1 Register Summary for PIC32MZXXXXECF and PIC32MZXXXXECH Devices
- TABLE 29-2: CAN2 Register Summary for PIC32MZXXXXECF and PIC32MZXXXXECH Devices
- Register 29-1: CiCON: CAN Module Control Register
- Register 29-2: CiCFG: CAN Baud Rate Configuration Register
- Register 29-3: CiINT: CAN Interrupt Register
- Register 29-4: CiVEC: CAN Interrupt Code Register
- Register 29-5: CiTREC: CAN Transmit/Receive Error Count Register
- Register 29-6: CiFSTAT: CAN FIFO Status Register
- Register 29-7: CiRXOVF: CAN Receive FIFO Overflow Status Register
- Register 29-8: CiTMR: CAN Timer Register
- Register 29-9: CiRXMn: CAN Acceptance Filter Mask ‘n’ Register (‘n’ = 0-3)
- Register 29-10: CiFLTCON0: CAN Filter Control Register 0
- Register 29-11: CiFLTCON1: CAN Filter Control Register 1
- Register 29-12: CiFLTCON2: CAN Filter Control Register 2
- Register 29-13: CiFLTCON3: CAN Filter Control Register 3
- Register 29-14: CiFLTCON4: CAN Filter Control Register 4
- Register 29-15: CiFLTCON5: CAN Filter Control Register 5
- Register 29-16: CiFLTCON6: CAN Filter Control Register 6
- Register 29-17: CiFLTCON7: CAN Filter Control Register 7
- Register 29-18: CiRXFn: CAN Acceptance Filter ‘n’ Register 7 (‘n’ = 0-31)
- Register 29-19: CiFIFOBA: CAN Message Buffer Base Address Register
- Register 29-20: CiFIFOCONn: CAN FIFO Control Register ‘n’ (‘n’ = 0-31)
- Register 29-21: CiFIFOINTn: CAN FIFO Interrupt Register ‘n’ (‘n’ = 0-31)
- Register 29-22: CiFIFOUAn: CAN FIFO User Address Register ‘n’ (‘n’ = 0-31)
- Register 29-23: CiFIFOCIn: CAN Module Message Index Register ‘n’ (‘n’ = 0-31)
- 30.0 Ethernet Controller
- FIGURE 30-1: Ethernet Controller Block Diagram
- TABLE 30-1: MII Mode Default Interface Signals (FMIIEN = 1, FETHIO = 1)
- TABLE 30-2: RMII Mode Default Interface Signals (FMIIEN = 0, FETHIO = 1)
- TABLE 30-3: MII Mode Alternate Interface Signals (FMIIEN = 1, FETHIO = 0)
- TABLE 30-4: RMII Mode Alternate Interface Signals (FMIIEN = 0, FETHIO = 0)
- 30.1 Ethernet Control Registers
- TABLE 30-5: Ethernet Controller Register Summary
- Register 30-1: ETHCON1: Ethernet Controller Control Register 1
- Register 30-2: ETHCON2: Ethernet Controller Control Register 2
- Register 30-3: ETHTXST: Ethernet Controller TX Packet Descriptor Start Address Register
- Register 30-4: ETHRXST: Ethernet Controller RX Packet Descriptor Start Address Register
- Register 30-5: ETHHT0: Ethernet Controller Hash Table 0 Register
- Register 30-6: ETHHT1: Ethernet Controller Hash Table 1 Register
- Register 30-7: ETHPMM0: Ethernet Controller Pattern Match Mask 0 Register
- Register 30-8: ETHPMM1: Ethernet Controller Pattern Match Mask 1 Register
- Register 30-9: ETHPMCS: Ethernet Controller Pattern Match Checksum Register
- Register 30-10: ETHPMO: Ethernet Controller Pattern Match Offset Register
- Register 30-11: ETHRXFC: Ethernet Controller Receive Filter Configuration Register
- Register 30-12: ETHRXWM: Ethernet Controller Receive Watermarks Register
- Register 30-13: ETHIEN: Ethernet Controller Interrupt Enable Register
- Register 30-14: ETHIRQ: Ethernet Controller Interrupt Request Register
- Register 30-15: ETHSTAT: Ethernet Controller Status Register
- Register 30-16: ETHRXOVFLOW: Ethernet Controller Receive Overflow Statistics Register
- Register 30-17: ETHFRMTXOK: Ethernet Controller Frames Transmitted OK Statistics Register
- Register 30-18: ETHSCOLFRM: Ethernet Controller Single Collision Frames Statistics Register
- Register 30-19: ETHMCOLFRM: Ethernet Controller Multiple Collision Frames Statistics Register
- Register 30-20: ETHFRMRXOK: Ethernet Controller Frames Received OK Statistics Register
- Register 30-21: ETHFCSERR: Ethernet Controller Frame Check Sequence Error Statistics Register
- Register 30-22: ETHALGNERR: Ethernet Controller Alignment Errors Statistics Register
- Register 30-23: EMAC1CFG1: Ethernet Controller MAC Configuration 1 Register
- Register 30-24: EMAC1CFG2: Ethernet Controller MAC Configuration 2 Register
- TABLE 30-6: Pad Operation
- Register 30-25: EMAC1IPGT: Ethernet Controller MAC Back-to-Back Interpacket Gap Register
- Register 30-26: EMAC1IPGR: Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register
- Register 30-27: EMAC1CLRT: Ethernet Controller MAC Collision Window/Retry Limit Register
- Register 30-28: EMAC1MAXF: Ethernet Controller MAC Maximum Frame Length Register
- Register 30-29: EMAC1SUPP: Ethernet Controller MAC PHY Support Register
- Register 30-30: EMAC1TEST: Ethernet Controller MAC Test Register
- Register 30-31: EMAC1MCFG: Ethernet Controller MAC MII Management Configuration Register
- TABLE 30-7: MIIM Clock Selection
- Register 30-32: EMAC1MCMD: Ethernet Controller MAC MII Management Command Register
- Register 30-33: EMAC1MADR: Ethernet Controller MAC MII Management Address Register
- Register 30-34: EMAC1MWTD: Ethernet Controller MAC MII Management Write Data Register
- Register 30-35: EMAC1MRDD: Ethernet Controller MAC MII Management Read Data Register
- Register 30-36: EMAC1MIND: Ethernet Controller MAC MII Management Indicators Register
- Register 30-37: EMAC1SA0: Ethernet Controller MAC Station Address 0 Register
- Register 30-38: EMAC1SA1: Ethernet Controller MAC Station Address 1 Register
- Register 30-39: EMAC1SA2: Ethernet Controller MAC Station Address 2 Register
- 31.0 Comparator
- 32.0 Comparator Voltage Reference (CVref)
- 33.0 Power-Saving Features
- 34.0 Special Features
- 34.1 Configuration Bits
- 34.2 Registers
- TABLE 34-1: DEVCFG: Device Configuration Word Summary
- TABLE 34-2: aDEVCFG: Alternate Device Configuration Word Summary
- TABLE 34-3: Device ID, Revision, and Configuration Summary
- TABLE 34-4: Device Serial Number Summary
- Register 34-1: DEVSIGN0/ADEVSIGN0: Device Signature Word 0 Register
- Register 34-2: DEVCP0/ADEVCP0: Device Code-Protect 0 Register
- Register 34-3: DEVCFG0/ADEVCFG0: Device Configuration Word 0
- Register 34-4: DEVCFG1/ADEVCFG1: Device Configuration Word 1
- Register 34-5: DEVCFG2/ADEVCFG2: Device Configuration Word 2
- Register 34-6: DEVCFG3/ADEVCFG3: Device Configuration Word 3
- Register 34-7: CFGCON: Configuration Control Register
- Register 34-8: CFGEBIA: External Bus Interface Address Pin Configuration Register
- Register 34-9: CFGEBIC: External Bus Interface Control Pin Configuration Register
- Register 34-10: CFGPG: Permission Group Configuration Register
- Register 34-11: DEVID: Device and Revision ID Register
- Register 34-12: DEVSNx: Device Serial Number Register ‘x’ (‘x’ = 0, 1)
- 34.3 On-Chip Voltage Regulator
- 34.4 On-chip Temperature Sensor
- 34.5 Programming and Diagnostics
- 35.0 Instruction Set
- 36.0 Development Support
- 36.1 MPLAB X Integrated Development Environment Software
- 36.2 MPLAB XC Compilers
- 36.3 MPASM Assembler
- 36.4 MPLINK Object Linker/ MPLIB Object Librarian
- 36.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 36.6 MPLAB X SIM Software Simulator
- 36.7 MPLAB REAL ICE In-Circuit Emulator System
- 36.8 MPLAB ICD 3 In-Circuit Debugger System
- 36.9 PICkit 3 In-Circuit Debugger/ Programmer
- 36.10 MPLAB PM3 Device Programmer
- 36.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 36.12 Third-Party Development Tools
- 37.0 Electrical Characteristics
- 37.1 DC Characteristics
- Table 37-1: Operating MIPS vs. Voltage
- Table 37-2: Thermal Operating Conditions
- Table 37-3: Thermal Packaging Characteristics
- Table 37-4: DC Temperature and Voltage Specifications
- Table 37-5: Electrical Characteristics: BOR
- Table 37-6: DC Characteristics: Operating Current (Idd)
- Table 37-7: DC Characteristics: Idle Current (Iidle)
- Table 37-8: DC Characteristics: Power-Down Current (Ipd)
- Table 37-9: DC Characteristics: I/O Pin Input Specifications
- Table 37-10: DC Characteristics: I/O Pin Input Injection current Specifications
- Table 37-11: DC Characteristics: I/O Pin Output Specifications
- Table 37-12: DC Characteristics: Program Memory(3)
- Table 37-13: DC Characteristics: Program Flash Memory Wait States
- Table 37-14: Comparator Specifications
- Table 37-15: Comparator Voltage Reference Specifications
- 37.2 AC Characteristics and Timing Parameters
- Figure 37-1: Load Conditions for Device Timing Specifications
- Table 37-16: Capacitive Loading Requirements on Output Pins
- Figure 37-2: External Clock Timing
- Table 37-17: External Clock Timing Requirements
- Table 37-18: System Timing Requirements
- Table 37-19: PLL Clock Timing Specifications
- Table 37-20: Internal FRC Accuracy
- Table 37-21: Internal LPRC Accuracy
- Table 37-22: Internal Backup FRC (BFRC) Accuracy
- Figure 37-3: I/O Timing Characteristics
- Table 37-23: I/O Timing Requirements
- Figure 37-4: Power-On Reset Timing Characteristics
- Figure 37-5: External Reset Timing Characteristics
- Table 37-24: Resets Timing
- Figure 37-6: Timer1-Timer9 External Clock Timing Characteristics
- Table 37-25: Timer1 External Clock Timing Requirements(1)
- Table 37-26: Timer2-Timer9 External Clock Timing Requirements
- Figure 37-7: Input Capture (CAPx) Timing Characteristics
- Table 37-27: Input Capture Module Timing Requirements
- Figure 37-8: Output Compare Module (OCx) Timing Characteristics
- Table 37-28: Output Compare Module Timing Requirements
- Figure 37-9: OCx/PWM Module Timing Characteristics
- Table 37-29: Simple OCx/PWM Mode Timing Requirements
- Figure 37-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics
- Table 37-30: SPIx Master Mode (CKE = 0) Timing Requirements
- Figure 37-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics
- Table 37-31: SPIx Module Master Mode (CKE = 1) Timing Requirements
- Figure 37-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics
- Table 37-32: SPIx Module Slave Mode (CKE = 0) Timing Requirements
- Figure 37-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics
- Table 37-33: SPIx Module Slave Mode (CKE = 1) Timing Requirements
- Figure 37-14: SQI Serial Input Timing Characteristics
- Figure 37-15: SQI Serial Output Timing Characteristics
- Table 37-34: SQI Timing Requirements
- Figure 37-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)
- Figure 37-17: I2Cx Bus Data Timing Characteristics (Master Mode)
- Table 37-35: I2Cx Bus Data Timing Requirements (Master Mode)
- Figure 37-18: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)
- Figure 37-19: I2Cx Bus Data Timing Characteristics (Slave Mode)
- Table 37-36: I2Cx Bus Data Timing Requirements (Slave Mode)
- Figure 37-20: CANx Module I/O Timing Characteristics
- Table 37-37: CANx Module I/O Timing Requirements
- Table 37-38: ADC Module Specifications
- Table 37-39: Analog-to-Digital Conversion Timing Requirements
- Table 37-40: ADC Sample Times with CVD Enabled
- Table 37-41: Temperature Sensor Specifications
- Figure 37-21: Parallel Slave Port Timing
- Table 37-42: Parallel Slave Port Requirements
- Figure 37-22: Parallel Master Port Read Timing Diagram
- Table 37-43: Parallel Master Port Read Timing Requirements
- Figure 37-23: Parallel Master Port Write Timing Diagram
- Table 37-44: Parallel Master Port Write Timing Requirements
- Table 37-45: USB OTG Electrical Specifications
- Table 37-46: Ethernet Module Specifications
- Figure 37-24: MDIO Sourced by the PIC32 Device
- Figure 37-25: MDIO Sourced by the PHY
- Figure 37-26: Transmit Signal Timing Relationships at the MII
- Figure 37-27: Receive Signal Timing Relationships at the MII
- Figure 37-28: EBI Page Read Timing
- Figure 37-29: EBI Write Timing
- Table 37-47: EBI Timing Requirements
- Table 37-48: EBI Throughput Requirements
- Figure 37-30: EJTAG Timing Characteristics
- Table 37-49: EJTAG Timing Requirements
- 37.1 DC Characteristics
- 38.0 AC and DC Characteristics Graphs
- 39.0 Packaging Information
- Appendix A: Migrating from PIC32MX5XX/6XX/7XX to PIC32MZ EF
- TABLE A-1: Oscillator Configuration differences
- TABLE A-2: Code Differences for Maximum Speed using an External 24 MHz Crystal
- TABLE A-3: ADC Differences
- TABLE A-4: CPU Differences
- TABLE A-5: Reset Differences
- TABLE A-6: USB Differences
- TABLE A-7: DMA Differences
- TABLE A-8: Interrupt Differences
- TABLE A-9: Flash Programming Differences
- TABLE A-10: Peripheral Differences
- TABLE A-11: Package Differences
- Appendix B: Migrating from PIC32MZ EC to PIC32MZ EF
- Appendix C: Revision History
- INDEX
- Corporate Office
- Atlanta
- Austin, TX
- Boston
- Chicago
- Cleveland
- Dallas
- Detroit
- Houston, TX
- Indianapolis
- Los Angeles
- New York, NY
- San Jose, CA
- Canada - Toronto
- Asia Pacific Office
- Hong Kong
- Australia - Sydney
- China - Beijing
- China - Chengdu
- China - Chongqing
- China - Dongguan
- China - Hangzhou
- China - Hong Kong SAR
- China - Nanjing
- China - Qingdao
- China - Shanghai
- China - Shenyang
- China - Shenzhen
- China - Wuhan
- China - Xian
- China - Xiamen
- China - Zhuhai
- India - Bangalore
- India - New Delhi
- India - Pune
- Japan - Osaka
- Japan - Tokyo
- Korea - Daegu
- Korea - Seoul
- Malaysia - Kuala Lumpur
- Malaysia - Penang
- Philippines - Manila
- Singapore
- Taiwan - Hsin Chu
- Taiwan - Kaohsiung
- Taiwan - Taipei
- Thailand - Bangkok
- Austria - Wels
- Denmark - Copenhagen
- France - Paris
- Germany - Dusseldorf
- Germany - Karlsruhe
- Germany - Munich
- Italy - Milan
- Italy - Venice
- Netherlands - Drunen
- Poland - Warsaw
- Spain - Madrid
- Sweden - Stockholm
- UK - Wokingham
- Worldwide Sales and Service