STM32F205/215, STM32F207/217 Flash Programming Manual PM0059 STM32F205 215 STM32F207 217

• 1 Glossary
• 2 Flash memory interface
  • 2.1 Introduction
  • 2.2 Main features
    • Figure 1. Flash memory interface connection inside system architecture
  • 2.3 Flash memory
    • Table 2. Flash module organization
  • 2.4 Read interface
    • 2.4.1 Relation between CPU clock frequency and Flash memory read time
      • Table 3. Number of wait states according to CPU clock (HCLK) frequency
    • 2.4.2 Adaptive real-time memory accelerator (ART Accelerator™)
      • Figure 2. Sequential 32-bit instruction execution
  • 2.5 Erase and program operations
    • 2.5.1 Unlocking the Flash control register
    • 2.5.2 Program/erase parallelism
      • Table 4. Program/erase parallelism
    • 2.5.3 Erase
    • 2.5.4 Programming
    • 2.5.5 Interrupts
      • Table 5. Flash interrupt requests
  • 2.6 Option bytes
    • 2.6.1 Description of user option bytes
      • Table 6. Option byte organization
      • Table 7. Description of the option bytes
    • 2.6.2 Programming user option bytes
    • 2.6.3 Read protection (RDP)
      • Table 8. Access versus read protection level
      • Figure 3. RDP levels
    • 2.6.4 Write protections
  • 2.7 One-time programmable bytes
    • Table 9. OTP part organization
  • 2.8 Flash interface registers
    • 2.8.1 Flash access control register (FLASH_ACR)
    • 2.8.2 Flash key register (FLASH_KEYR)
    • 2.8.3 Flash option key register (FLASH_OPTKEYR)
    • 2.8.4 Flash status register (FLASH_SR)
    • 2.8.5 Flash control register (FLASH_CR)
    • 2.8.6 Flash option control register (FLASH_OPTCR)
    • 2.8.7 Flash interface register map
      • Table 10. Flash register map and reset values
• 3 Revision history
  • Table 11. Document revision history (continued)