STM32F205/215, STM32F207/217 Flash Programming Manual PM0059 STM32F205 215 STM32F207 217
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PM0059
Programming manual
STM32F205/215, STM32F207/217 Flash programming manual
Introduction
This programming manual describes how to program the Flash memory of STM32F205/215
and STM32F207/217 microcontrollers. For convenience, these will be referred to as
STM32F20x and STM32F21x in the rest of this document unless otherwise specified.
The STM32F20x and STM32F21xembedded Flash memory can be programmed using incircuit programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI,
etc.) to download programming data into memory. With IAP, the Flash memory can be reprogrammed while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out Flash memory operations (program/erase).
Program/erase operations can be performed over the whole product voltage range.
Read/write protections and option bytes are also implemented.
June 2013
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Contents
PM0059
Contents
1
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
2.6
3
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2.4.1
Relation between CPU clock frequency and Flash memory read time . . 8
2.4.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 9
Erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.5.1
Unlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.2
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.3
Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.4
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.1
Description of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.2
Programming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6.3
Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.4
Write protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7
One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8
Flash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8.1
Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 20
2.8.2
Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8.3
Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 21
2.8.4
Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8.5
Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.8.6
Flash option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . . . . 24
2.8.7
Flash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID15687 Rev 5
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . . 8
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Access versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OTP part organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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3
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
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Flash memory interface connection inside system architecture . . . . . . . . . . . . . . . . . . . . . . 6
Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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1
Glossary
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
The CPU core integrates two debug ports:
–
JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
–
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, please refer to the Cortex M3 Technical
Reference Manual
•
Word: data/instruction of 32-bit length.
•
Half word: data/instruction of 16-bit length.
•
Byte: data of 8-bit length.
•
Double word: data of 64-bit length.
•
IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a
microcontroller while the user program is running.
•
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
•
I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction
interface. Prefetch is performed on this bus.
•
D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU
to the Flash data interface.
•
Option bytes: product configuration bits stored in the Flash memory.
•
OBL: option byte loader.
•
AHB: advanced high-performance bus.
•
CPU: refers to the Cortex-M3 core.
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Flash memory interface
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2
Flash memory interface
2.1
Introduction
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the
1 Mbyte (64 Kbit × 128 bits) Flash memory. It implements the erase and program Flash
memory operations and the read and write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
2.2
Main features
•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
Prefetch on I-Code
•
64 cache lines of 128 bits on I-Code
•
8 cache lines of 128 bits on D-Code
Figure 1 shows the Flash memory interface connection inside the system architecture.
Figure 1. Flash memory interface connection inside system architecture
) #ODE BUS
) #ODE
!("
BIT
INSTRUCTION
BUS
&LASH INTERFACE
$ #ODE
#ORTEX
CORE
3 BUS
$ CODE BUS
!("
BIT
DATABUS
&LASH MEMORY
BUS
BITS
&LASH
MEMORY
&,)4& REGISTERS
#ORTEX -
PERIPH
!("
BIT
SYSTEM
BUS
$-!
$-!
32!-S
&3-#
!("
PERIPH
53" (3
%THERNET
!CCESS TO INSTRUCTIONS IN &LASH MEMORY
!CCESS TO DATA LITERAL POOL IN &LASH MEMORY
&,)4& REGISTER ACCESS
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2.3
Flash memory interface
Flash memory
The Flash memory has the following main features:
•
Capacity up to 1 Mbyte
•
128 bits wide data read
•
Byte, half-word, word and double word write
•
Sector and mass erase
•
Memory organization
The Flash memory is organized as follows:
–
Main memory block containing 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes, and
7 sectors of 128 Kbytes
–
System memory used to boot the device in System memory boot mode.
This area is reserved for STMicroelectronics and contains the bootloader which is
used to reprogram the Flash memory through one of the following interfaces:
USART1, USART3, CAN2, USB OTG FS in Device mode (DFU: device firmware
upgrade). The bootloader is programmed by ST when the device is manufactured,
and protected against spurious write/erase operations.
–
512 OTP (one-time programmable) bytes for user data
The OTP area contains 16 additional bytes used to lock the corresponding OTP
data block.
–
•
Option bytes: read and write protections, BOR level, watchdog software/hardware
and reset when the device is in Standby or Stop mode.
Low power modes (for details refer to the Power control (PWR) section of the reference
manual)
Table 2. Flash module organization
Block
Name
Block base addresses
Size
Sector 0
0x0800 0000 - 0x0800 3FFF
16 Kbyte
Sector 1
0x0800 4000 - 0x0800 7FFF
16 Kbyte
Sector 2
0x0800 8000 - 0x0800 BFFF
16 Kbyte
Sector 3
0x0800 C000 - 0x0800 FFFF
16 Kbyte
Sector 4
0x0801 0000 - 0x0801 FFFF
64 Kbyte
Sector 5
0x0802 0000 - 0x0803 FFFF
128 Kbyte
Sector 6
0x0804 0000 - 0x0805 FFFF
128 Kbyte
.
.
.
.
.
.
.
.
.
Sector 11
0x080E 0000 - 0x080F FFFF
128 Kbyte
System memory
0x1FFF 0000 - 0x1FFF 77FF
30 Kbyte
OTP area
0x1FFF 7800 - 0x1FFF 7A0F
528 bytes
Option bytes
0x1FFF C000 - 0x1FFF C00F
16 bytes
Main memory
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2.4
Read interface
2.4.1
Relation between CPU clock frequency and Flash memory read time
To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device. Table 3 shows the
correspondence between wait states and CPU clock frequency.
The prefetch must be disabled when the supply voltage is below 2.1 V.
Table 3. Number of wait states according to CPU clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
Voltage range
Voltage range
Voltage range
Voltage range
2.7 V - 3.6 V
2.4 V - 2.7 V
2.1 V - 2.4 V
1.8 V - 2.1 V(1)
0 WS (1 CPU cycle)
0 1, 1->2, 0->2) there is no mass erase.
•
Level 2: Disable debug/chip read protection
When the read protection Level 2 is set by writing 0xCC to the RDP option byte:
–
All protections provided by Level 1 are active.
–
Booting from system memory is not allowed anymore.
–
JTAG, SWV (single-wire viewer) are disabled.
–
User option bytes can no longer be changed.
–
When booting from Flash memory, accesses (read, erase and program) to Flash
memory and backup SRAM from user code are allowed.
Memory read protection Level 2 is an irreversible operation. When Level 2 is activated,
the level of protection cannot be decreased to Level 0 or Level 1.
Note:
The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a
consequence, boundary scan cannot be performed. STMicroelectronics is not able to
perform analysis on defective parts on which the Level 2 protection has been set.
Figure 3 shows how to go from one RDP level to another, and Table 8 summarizes the
memory accesses versus the protection level.
Table 8. Access versus read protection level
Memory area
Protection
Level
Debug features, Boot from RAM or
from System memory bootloader
Read
Main Flash Memory
and Backup SRAM
Option Bytes
OTP
Level 1
Write
Erase
Booting from Flash memory
Read
Write
NO(1)
NO
Erase
YES
Level 2
NO
YES
Level 1
YES
YES
Level 2
NO
NO
Level 1
NO
NA
YES
NA
Level 2
NO
NA
YES
NA
1. The main Flash memory and backup SRAM are only erased when the RDP changes from level 1 to 0. The OTP area
remains unchanged.
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Figure 3. RDP levels
2$0 !!H ##H
/THERS OPTIONS MODIFIED
,EVEL
2$0 !!H
2$0 ##H
DEFAULT
7RITE OPTIONS
INCLUDING
2$0 ##H
7RITE OPTIONSINCLUDING
2$0 ##H !!H
, EV E L
2$0 ##H
7RITE OPTIONS
INCLUDING
2$0 !!H
, EV E L
7RITE OPTIONS
INCLUDING
2$0 ##H
/PTIONS WRITE 2$0 LEVEL INCREASE INCLUDES
/PTIONS ERASE
.EW OPTIONS PROGRAM
/PTIONS WRITE 2$0 LEVEL DECREASE INCLUDES
-ASS ERASE
/PTIONS ERASE
.EW OPTIONS PROGRAM
2$0 !! H
2$0 !!H
/THERS OPTIONS MODIFIED
/PTIONS WRITE 2$0 LEVEL IDENTICAL INCLUDES
/PTIONS ERASE
.EW OPTIONS PROGRAM
AI
2.6.4
Write protections
The user sectors (0 to 11) in Flash memory can be protected against unwanted write
operations due to loss of program counter contexts. When the not write protection bit in
sector i (nWRPi, 0 ≤ i ≤ 11) is low, the corresponding sector cannot be erased or
programmed. Consequently, a mass erase cannot be performed if one of the sectors is
write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted
(sector protected by write protection bit, OTP part locked or part of the Flash memory that
can never be written like the ICP), the write protection error flag (WRPERR) is set in the
FLASH_SR register.
Note:
18/29
When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
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Flash memory interface
Write protection error flag
If an erase/program operation to a write protected area of the Flash memory is performed,
the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
If an erase operation is requested, the WRPERR bit is set when:
•
Mass or sector erase are configured (MER or MER/MER1 and SER = 1)
•
A sector erase is requested and the Sector Number SNB field is not valid
•
A mass erase is requested while at least one of the user sector is write protected by
option bit (MER or MER/MER1 = 1 and nWRPi = 0 with 0 ≤ i ≤ 11 bits in the
FLASH_OPTCRx register
•
The Flash memory is readout protected and an intrusion is detected.
If a program operation is requested, the WRPERR bit is set when:
2.7
•
A write operation is performed on system memory or on the reserved part of the user
specific sector.
•
A write operation is performed to the user configuration sector
•
A write operation is performed on a sector write protected by option bit.
•
A write operation is requested on an OTP area which is already locked
•
The Flash memory is read protected and an intrusion is detected.
One-time programmable bytes
Table 9 shows the organization of the one-time programmable (OTP) part of the OTP area.
Table 9. OTP part organization
Block
0
1
[128:96]
[95:64]
[63:32]
[31:0]
Address byte 0
OTP0
OTP0
OTP0
OTP0
0x1FFF 7800
OTP0
OTP0
OTP0
OTP0
0x1FFF 7810
OTP1
OTP1
OTP1
OTP1
0x1FFF 7820
OTP1
OTP1
OTP1
OTP1
0x1FFF 7830
.
.
.
15
Lock block
.
.
.
.
.
.
OTP15
OTP15
OTP15
OTP15
0x1FFF 79E0
OTP15
OTP15
OTP15
OTP15
0x1FFF 79F0
LOCKB15 ...
LOCKB12
LOCKB11 ...
LOCKB8
LOCKB7 ...
LOCKB4
LOCKB3 ...
LOCKB0
0x1FFF 7A00
The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16
bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes
LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP
data block can be programmed until the value 0x00 is programmed in the corresponding
OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP
bytes might not be taken into account correctly.
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2.8
Flash interface registers
2.8.1
Flash access control register (FLASH_ACR)
The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
6
5
4
3
2
17
16
1
0
Reserved
15
14
13
Reserved
12
11
DCRST ICRST
rw
w
10
9
8
DCEN
ICEN
PRFTEN
rw
rw
rw
7
Reserved
LATENCY
rw
rw
rw
Bits 31:11 Reserved, must be kept cleared.
Bit 12 DCRST: Data cache reset
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the D cache is disabled.
Bit 11 ICRST: Instruction cache reset
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the I cache is disabled.
Bit 10 DCEN: Data cache enable
0: Data cache is disabled
1: Data cache is enabled
Bit 9 ICEN: Instruction cache enable
0: Instruction cache is disabled
1: Instruction cache is enabled
Bit 8 PRFTEN: Prefetch enable
0: Prefetch is disabled
1: Prefetch is enabled
Bits 7:3 Reserved, must be kept cleared.
Bits 2:0 LATENCY: Latency
These bits represent the ratio of the CPU clock period to the Flash memory access time.
000: Zero wait state
001: One wait state
010: Two wait states
011: Three wait states
100: Four wait states
101: Five wait states
110: Six wait states
111: Seven wait states
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Flash memory interface
2.8.2
Flash key register (FLASH_KEYR)
The Flash key register is used to allow access to the Flash control register and so, to allow
program and erase operations.
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 FKEYR: FPEC key
The following values must be programmed consecutively to unlock the FLASH_CR register
and allow programming/erasing it:
a) KEY1 = 0x45670123
b) KEY2 = 0xCDEF89AB
2.8.3
Flash option key register (FLASH_OPTKEYR)
The Flash option key register is used to allow program and erase operations in the user
configuration sector.
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OPTKEYR[31:16
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
OPTKEYR[15:0]
w
w
Bits 31:0 OPTKEYR: Option byte key
The following values must be programmed consecutively to unlock the FLASH_OPTCR
register and allow programming it:
a) OPTKEY1 = 0x08192A3B
b) OPTKEY2 = 0x4C5D6E7F
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Flash memory interface
2.8.4
PM0059
Flash status register (FLASH_SR)
The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Reserved
15
14
13
12
11
Reserved
10
9
8
7
r
6
5
4
PGSERR PGPERR PGAERR WRPERR
rc_w1
16
BSY
rc_w1
rc_w1
rc_w1
3
2
Reserved
1
0
OPERR
EOP
rc_w1
rc_w1
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
Flash memory operation and cleared when the operation finishes or an error occurs.
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Bits 15:8 Reserved, must be kept cleared.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the code while
the control register has not been correctly configured.
Cleared by writing 1.
Bit 6 PGPERR: Programming parallelism error
Set by hardware when the size of the access (byte, half-word, word, double word) during the
program sequence does not correspond to the parallelism configuration PSIZE (x8, x16,
x32, x64).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same 128-bit Flash
memory row.
Cleared by writing 1.
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-protected
part of the Flash memory.
Cleared by writing 1.
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Flash memory interface
Bits 3:2 Reserved, must be kept cleared.
Bit 1 OPERR: Operation error
Set by hardware when a flash operation (programming / erase) request is detected and can
not be run because of parallelism, alignment, sequence or write protection error. This bit is
set only if error interrupts are enabled (ERRIE = 1).
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operations (program/erase) has/have
completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =
1).
Cleared by writing a 1.
2.8.5
Flash control register (FLASH_CR)
The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
LOCK
27
26
Reserved
rs
15
28
14
13
12
Reserved
11
10
25
24
ERRIE
EOPIE
rw
rw
9
8
PSIZE[1:0]
rw
rw
23
22
21
20
19
18
17
Reserved
7
6
5
Reserv
ed
rw
rw
4
rs
3
SNB[3:0]
rw
16
STRT
rw
2
1
0
MER
SER
PG
rw
rw
rw
Bit 31 LOCK: Lock
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 31:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is
set to 1.
0: Error interrupt generation disabled
1: Error interrupt generation enabled
Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes
to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bits 15:10 Reserved, must be kept cleared.
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PM0059
Bits 9:8 PSIZE: Program size
These bits select the program parallelism.
00 program x8
01 program x16
10 program x32
11 program x64
Bit 7 Reserved, must be kept cleared.
Bits 6:3 SNB: Sector number
These bits select the sector to erase.
0000 sector 0
0001 sector 1
...
1011 sector 11
Others not allowed
Bit 2 MER: Mass Erase
Erase activated for all user sectors.
Bit 1 SER: Sector Erase
Sector Erase activated.
Bit 0 PG: Programming
Flash programming activated.
2.8.6
Flash option control register (FLASH_OPTCR)
The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at
reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
28
14
13
26
25
24
12
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rw
rw
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
nRST_ nRST_
STDBY STOP
RDP[7:0]
rw
23
nWRP[11:0]
Reserved
15
27
rw
rw
rw
rw
rw
rw
rw
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WDG_
SW
rw
Reserv
ed
BOR_LEV
rw
rw
OPTST OPTLO
RT
CK
rs
rs
PM0059
Flash memory interface
Bits 31:28 Reserved, must be kept cleared.
Bits 27:16 nWRP: Not write protect
These bits contain the value of the write-protection option bytes after reset. They can be
written to program a new write protect value into Flash memory.
0: Write protection active
1: Write protection not active
Bits 15:8 RDP: Read protect
These bits contain the value of the read-protection option level after reset. They can be
written to program a new read protection value into Flash memory.
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, read protection of memories active
Bits 7:5 USER: User option bytes
These bits contain the value of the user option byte after reset. They can be written to
program a new user option byte value into Flash memory.
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: WDG_SW
Note: When changing the WDG mode from hardware to software or from software to
hardware, a system reset is required to make the change effective.
Bit 4 Reserved, must be kept cleared.
Bits 3:2 BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (VDD)
drops below the selected BOR level, a device reset is generated.
00: BOR Level 3 (VBOR3), reset threshold level 3
01: BOR Level 2 (VBOR2), reset threshold level 2
10: BOR Level 1 (VBOR1), reset threshold level 1
11: BOR off (VBOR0), POR/PDR reset threshold level is applied.
Note: For full details about BOR characteristics, refer to the “Electrical characteristics” section
in the device datasheet.
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.
This bit is cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
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2.8.7
PM0059
Flash interface register map
0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
STRT
1
EOPIE
LOCK
Reset value
Reserved
0
1
1
1
1
PSIZ
E[1:0
]
Reserved
0
nWRP[11:0]
Reserved
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Rese
rved
OPTKEYR[15:0]
Reserved
Reserved
0
1
0
0
1
0
RDP[7:0]
1
1
1
1
DocID15687 Rev 5
1
0
1
0
1
0
0
0
0
0
0
0
SNB[3:0]
0
0
1
1
1
0
0
1
1
EOP
0
0
OPERR
0
0
0
0
PG
0
FLASH_CR
Reset value
0
OPTKEYR[31:16]
Reset value
FLASH_OPT
CR
0
SER
0
0
0
OPTLOCK
0
MER
0
0
OPTSTRT
0
0
BOR_LEV
0
PGAERR
0
WRPERR
0
Reserved
0
PGPERR
0
0
KEY[15:0]
WDG_SW
0
FLASH_SR
0x14
0
PGSERR
0
0x0C
0x10
0
KEY[31:16]
FLASH_OPT
KEYR
Reset value
0
Reserved
0x08
0
nRST_STOP
Reset value
0
LATENC
Y
Reserved
nRST_STDBY
FLASH_KEY
R
BSY
0x04
ICEN
Reset value
PRFTEN
Reserved
DCEN
FLASH_ACR
0x00
ICRST
Register
DCRST
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 10. Flash register map and reset values
0
1
PM0059
3
Revision history
Revision history
Table 11. Document revision history
Date
24-Jun-2010
09-Dec-2010
30-Mar-2011
Revision
Changes
1
Updated memory organization in Section 2.3: Flash memory, and
replace user-specific block by OTP area.
Updated addresses in Table 6: Option byte organization.
Definition of BOR_LEV[3:2] bits updated in Table 7: Description of
the option bytes and Section 2.8.6: Flash option control register
(FLASH_OPTCR). Modified FLASH_OPTCR reset value in
Section 2.8.6: Flash option control register (FLASH_OPTCR) and
Table 10: Flash register map and reset values. Updated
OPTLOCK
definition.
Updated definition of ERRIE bit in Section 2.8.5: Flash control
register (FLASH_CR).
2
Updated size of OTP area, and option byte base address and size
in
Table 2: Flash module organization.
Changed 1.62 to 2.1 V range to 1.8 to 2.1 V, added Note 1 as well
as
wait states 4 to 7 in TTable 3: Number of wait states according to
CPU clock (HCLK) frequency.
Updated Table 4: Program/erase parallelism.
Updated BOR_LEVEL description in Table 7: Description of the
option bytes.
Renamed FLASH_FOCR, FLASH_OPTCR in Section 2.6.2:
Programming user option bytes.
Updated Level 1 and Level 2 descriptions in Section 2.6.3: Read
protection (RDP).
Updated LATENCY bits in Section 2.8.1: Flash access control
register (FLASH_ACR) to support up to 7 wait states.
Changed access type to bits 0 to 7 to rc-1, and OPERR
description
in Section 2.8.4: Flash status register (FLASH_SR).
Changed access type to bits 16 and 31 to rs in Section 2.8.5:
Flash control register (FLASH_CR).
Changed access type to bits 0 and 1 to rs, and added note related
to
bit 7 to 5 in Section 2.8.6: Flash option control register
(FLASH_OPTCR).
3
Updated OTP area in Section 2.3: Flash memory.
Updated Section 2.5: Erase and program operations to mention
the
fact that read operations cannot be performed during write/erase
operations.
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Revision history
PM0059
Table 11. Document revision history (continued)
Date
Revision
10-May-2011
4
Modified Note 1 in Table 3: Number of wait states according to
CPU clock (HCLK) frequency and Note 1 in Table 3: Number of
wait states according to CPU clock (HCLK) frequency.
5
Updated Section 2.4.1: Relation between CPU clock frequency
and Flash memory read time to add prefetch disabling when the
supply voltage is below 2.1 V.
Added note in Section : Standard programming
Updated Section 2.5.2: Program/erase parallelism.
Added Table 5: Flash interrupt requests.
Updated Section 2.6.3: Read protection (RDP).
Updated Section 2.6.4: Write protections.
Modified BOR_LEV bits definition in Section 2.8.6: Flash option
control register (FLASH_OPTCR).
Document converted to new template and disclaimer updated.
07-Jun-2013
28/29
Changes
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