SPI Data Sheets Pm25LV512A, Pm25LV010A, Pm25LV020, Pm25LV040 Pm25LV512 PM25LV020

User Manual: Pm25LV512

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Pm25LV512A / 010A / 020 / 040
512 Kbit /1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only,
Serial Flash Memory With 100 MHz SPI Bus Interface
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V

• Sector, Block or Chip Erase Operation
- Typical 60 ms sector, block or chip erase

• Memory Organization
- Pm25LV512A: 64K x 8 (512 Kbit)
- Pm25LV010A: 128K x 8 (1 Mbit)
- Pm25LV020: 256K x 8 (2 Mbit)
- Pm25LV040: 512K x 8 (4 Mbit)

• Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow partial
or entire memory to be configured as read-only

• Hardware Write Protection
- Protect and unprotect the device from write operation
by Write Protect (WP#) Pin

• Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4Kbyte sectors / Two uniform
32Kbyte blocks
- 1Mb : Uniform 4Kbyte sectors / Four uniform
32Kbyte blocks
- 2Mb : Uniform 4Kbyte sectors / Four uniform
64Kbyte blocks
- 4Mb : Uniform 4Kbyte sectors / Eight uniform
64Kbyte blocks
- Bottom sector is configurable as one 4Kbyte sector
or four 1Kbyte sectors (except Pm25LV512A)

• Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
• High Product Endurance
- Guarantee 200,000 program/erase cycles per single
sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LV040
- 8-pin 300mil PDIP for Pm25LV040
- 8-contact WSON
- 8-pin TSSOP for Pm25LV512A

• Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program

GENERAL DESCRIPTION
The Pm25LV512A/010A/020/040 are 512Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI)
Flash memories. The devices are designed to support 33 MHz fastest clock rate in the industry in normal read
mode, 100 MHz in fast read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features(except
Pm25LV512A). The devices use a single low voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform
read, erase and program operations. The devices can be programmed in standard EPROM programmers as well.
The Pm25LV512A/010A is backward compatible to their predecessors Pm25LV512/010.
The Pm25LV512A/010A/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, 1 to 256 bytes data can be programmed into the memory in one program operation. The memory of
Pm25LV512A/010A is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of
eight adjacent sectors) for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte
sectors or uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an
innovative feature to configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional
serial EEPROM needed for storing data. This is a further cost reduction for overall system.
The Pm25LV512A/010A/020/040 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices
are offered in 8-pin SOIC, 8-contact WSON and 8-pin PDIP (Pm25LV040) packages with operation frequency up to
100 MHz in fast read and 33 MHz in normal read mode.
Chingis Technology Corporation

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Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
CONNECTION DIAGRAMS

CE#

1

8

Vcc

CE#

1

8

Vcc

SO

2

7

HOLD#

SO

2

7

HOLD#

WP#

3

6

SCK

WP#

3

6

SCK

GND

4

5

SI

GND

4

5

SI

8-Pin SOIC

8-Contact WSON

CE#

1

8

Vcc

SO

2

7

HOLD#

WP#

3

6

SCK

GND

4

5

SI

CE#
SO
WP#
GND

1
2
3
4

8
7
6
5

Vcc
HOLD#
SCK
SI

8-Pin TSSOP

8-Pin PDIP

PIN DESCRIPTIONS
SYMBOL

TYPE

DESCRIPTION

CE#

INPUT

Chip Enable: CE# goes low activates the devices internal circuitries for
device operation. CE# goes high deselects the devices and switches into
standby mode to reduce the power consumption. When the devices are not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.

SCK

INPUT

Serial Data Clock

SI

INPUT

Serial Data Input

SO

OUTPUT

Serial Data Output

GND

Ground

Vcc

Device Power Supply

WP#

INPUT

Write Protect: A hardware program/erase protection for all or partial of
memory array. When the WP# pin is pulled to low, whole or partial of
memory array is write protected depends on the setting of BP2, BP1 and
BP0 bits in the Status Register. When the WP# is pulled high, the devices
are not write protected.

HOLD#

INPUT

Hold: Pause serial communication with the master device without resetting
the serial sequence.

Chingis Technology Corporation

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Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PRODUCT ORDERING INFORMATION
Pm25LVxxxA -100 S

C

E

R
Packing Type
R = Tape & Reel
Blank = Tube
Environmental Attribute
E = Lead-free/RoHS compliance package
Blank = Standard package
Temperature Range
C = Commercial (-40°C to +105°C)
Package Type
S = 8-pin SOIC 150 mil (8S)
B = 8-pin SOIC 208 mil (8B)
K = 8-contact WSON (8K)
P = 8-pin PDIP 300 mil (8P)
D = TSSOP (8D)
Operating Frequency
-100 : 33MHz normal read, 100MHz fast read
Device Number
Pm25LV512A/010A/020/040

Part Number

Operating Frequency (MHz)

Package

100

8S 150mil SOIC

Temperature Range

Pm25LV512A-100SCE
Pm25LV010A-100SCE
Pm25LV020-100SCE
Pm25LV040-100SCE
Pm25LV512A-100KCE
Pm25LV010A-100KCE

100

8Q WSON

Pm25LV040-100BCE

100

8B 208mil SOIC

Pm25LV040-100PCE

100

8P 300mil PDIP

Pm25LV512A-100DCE

100

8D TSSOP

Pm25LV512A-100WC

100

Pm25LV010A-100WC

100

Pm25LV020-100WC

100

Pm25LV020-100KCE

Commercial
(-40oC to +105oC)

Pm25LV040-100KCE

Chingis Technology Corporation

KGD

3

Commercial
(-40oC to 105oC)

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
BLOCK DIAGRAM

Control Logic

High Voltage Generator

I/O Buffers and
Data Latches

Status
Register

WP#
SI
SO
HOLD#

Address Latch
& Counter

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Y-DECODER

X-DECODER

SCK

Serial Peripheral Interface

CE#

256 Bytes
Page Buffer

Memory Array

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Pm25LV512A/010A/020/040
SPI MODES DESCRIPTION
Multiple Pm25LV512A/010A/020/040 devices can be serially connected onto the SPI serial bus controlled by a
SPI Master i.e. microcontroller as shown in Figure 1.
The devices support either of the two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)

The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and the
clock remains at “1” (SCK = 1) for Mode 1. Please refer
to Figure 2. For both modes, the input data is latched on
the rising edge of Serial Clock (SCK), and the output
data is available from the falling edge of SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SDO
SPI Interface with
(0, 0) or (1, 1)

SDI
SCK
SCK

SPI Master
(i.e. Microcontroller)

CS3

SO

SI

SCK SO

SPI Memory
Device

SI

SCK

SPI Memory
Device

SO

SI

SPI Memory
Device

CS2 CS1
CE#

WP# HOLD# CE#

WP# HOLD# CE#

WP# HOLD#

Note: 1. The Write Protect (WP#) and Hold (HOLD#) si gnals should be driven, High or Low as appropriate.

Figure 2. SPI Modes Supported

Mode 0 (0, 0) SCK

Mode 3 (1, 1) SCK

SI

MSB

MSB

SO

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Pm25LV512A/010A/020/040
REGISTERS
The Pm25LV512A/010A/020/040 are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of Motorola MC68HCxx series of
microcontrollers or all the SPI interface equipped system controllers.

2. The Pm25LV010A/020/040 have an option to configure the 4 Kbyte bottom sector (Sector 0) into four 1
Kbyte smaller sectors (Sector 0_0, Sector 0_1, Sector 0_2 and Sector 0_3). The finer granularity sector
size architecture allows user to update data more
efficiently. This feature allows user to eliminate the
need of addtional serial EEPROM.

The devices have two superset features can be enabled
through the specific software instructions and Configuration Register:

Refer to Table 1 for Configuration Register and Table 2
for Configuration Register Bit Definition.

1. Configurable sector size: The memory array of
Pm25LV512A/010A are divided into uniform 4 Kbyte
sectors or uniform 32 Kbyte blocks (sector group consists of eight adjacent sectors). The memory array of Pm25LV020/040 are divided into uniform 4
Kbyte sectors or uniform 64 Kbyte blocks (sector
group - consists of sixteen adjacent sectors).

Table 1. Configuration Register Format - Pm25LV010A/020/040
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

X

X

SP0_3

SP0_2

SP0_1

SP0_0

SCFG

Table 2. Configuration Register Bit Definition
Bit

Name

Definition

Read/Write

Bit 0

SCFG

Sector Configuration:
"0" indicates the bottom sector is one 4 Kbyte sector (default)
"1" indicates the bottom sector is broken down to four 1 Kbyte sectors
This feature can be implemented only when BP0,BP1&BP2 of status
register were enabled to "1" which is in protection mode.

R/W

Bit 1

SP0_0

1 Kbyte Sector 0_0 Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled

R/W

Bit 2

SP0_1

1 Kbyte Sector 0_1Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled

R/W

Bit 3

SP0_2

1 Kbyte Sector 0_2 Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled

R/W

Bit 4

SP0_3

1 Kbyte Sector 0_3 Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled

R/W

Bit 5 - 6

RES

Reserved for future (don't care)

N/A

Bit 7

RES

Reserved for future (don't use)

N/A

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Pm25LV512A/010A/020/040
REGISTERS (CONTINUED)

CONFIGURATION REGISTER (Pm25LV010A/020/ 040)
The Configuration Register is built by latchs need to be
set each time after power-up before enabling the 1 Kbyte
smaller sector size and 1 Kbyte sector write protection.
The Bit 0 - Bit 7 of Configuration Register are set as “0”s
after power-up reset. Therefore, the devices will be always set as normal mode - the bottom sector set as 4
Kbyte by default after power-up to maintain the backward-compatibility.

The BP0, BP1, BP2, and SRWD are non-volatile memory
cells that can be written by Write Status Register (WRSR)
instruction. The default value of BP0, BP1, BP2, and
SRWD bits were set as “0” at factory. Once those bits
are written as “0” or “1”, it will not be changed by devices
power-up or power-down until next WRSR instruction alters its value. The Status Register can be read by Read
Status Register (RDSR) instruction for its value and status. Refer to Table 8 for Instruction Set.

The function of Configuration Register is described as
following:

The function of Status Register is described as following:
WIP bit: The Write In Progress (WIP) bit can be used to
detact the progress or completion of program or erase
operation. When WIP bit is “0”, the devices are ready for
write status register, program or erase operation. When
WIP bit is “1”, the devices are busy.

SCFG bit: The 1 Kbyte smaller sector mode is enabled
by writing “1” to SCFG bit, then Sector 0 is configured
as Sector 0_0, Sector 0_1, Sector 0_2 and Sector 0_3.
A Sector Erase (SECTOR_ER) instruction can be used
to erase any one of those four 1 Kbyte sectors. The
SCFG bit will be reset “0” state automatically at power
on stage. Thus, the 1 Kbyte smaller sector mode is
disabled at power on till SCFG bit was set.

WEL bit: The Write Enable Latch (WEL) bit indicates
the status of internal write enable latch. When WEL bit
is “0”, the write enable latch is disabled, all write operations include write status register, write configuration register, page program, sector erase, block and chip erase
operations are inhibited. When WEL bit is “1”, the write
enable latch is enabled. Then write operations are allowed.
The WEL bit is enabled by Write Enable (WREN) instruction. All write register, program and erase instructions
must be preceded by a WREN instruction every time.
The WEL bit can be disabled by Write Disable (WRDI)
instruction or automatically return to reset state after the
completion of a write instruction.

The SCFG bit only can be enabled to “1” when BP0,
BP1&BP2 of status register were “1” state which in protection mode. On the other word, SCFG bit will be cleared
to “0” state when BPx were “0” to disable the protection
mode.
SP0_x bits: The write protection to those four 1 Kbyte
sectors can be activated by writing “1”s to the SP0_0,
SP0_1, SP0_2 and SP0_3 bits. The 1 Kbyte sector write
protection function can only be enabled when the SCFG
is also enabled.

BP2, BP1, BP0 bits: The Block Protection (BP2
(Pm25LV040 only), BP1, BP0) bits are used to define
the portion of memory area to be protected. Refer to Table
5 and Table 6 Block Write Protection Bits Setting for
Pm25LV512A/010A/020 and Pm25LV040. When one of
the combination of BP2, BP1 and BP0 bits were set as
“1”, the relevant memory area is protected. Any program
or erase operation to that area will be prohibited.
Especially, the Chip Erase (CHIP_ER) instruction is executed only if all the Block Protection Bits are set as
“0”s.

The Write Configuration Register (WRCR) instruction can
be used to write “0”s or “1”s into Configuration Register.
And the Read Configuration Register (RDCR) instruction can be used to read the setting of Configuration
Register. Refer to Table 8 for Instruction Set.
STATUS REGISTER
The Status Register contains WIP and WEL status bits
to indicate the status of the devices, the Block Protection Bits (BP0, BP1 and BP2 (Pm25LV040 only)) to
define the portion of memory blocks to be write protected,

If SCFG bit was enabled to support 1KB x4 sectores on
Sector 0, Sector 0’s protection status will respect SP0_x
in Configuration Register and ignore BPx bits status
whatever protection status.

and SRWD control bits to be set for status register write
protection. Refer to Table 3 and Table 4 for Status Register Format and Status Register Bit Definition.

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Pm25LV512A/010A/020/040
REGISTERS (CONTINUED)
SRWD bit: The Status Register Write Disable (SRWD)
bit is operated in conjuction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode.
When the SRWD is set to “0”, the Status Register is not
write protected. When the SRWD is set to “1” and the

WP# is pulled low (VIL), the non-volatile bits of Status
Register (SRWD, BP2, BP1, BP0) become read-only
and the WRSR instruction will be prohibited. If the SRWD
is set to “1” but WP# is pulled high (VIH), the Status
Register is still changeable by WRSR instruction.

Table 3. Status Register Format
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRWD

0

0

BP2

BP1

BP0

WEL

WIP

Table 4. Status Register Bit Definition
Bit

Name

Definition

Read/Write

Non-Volatile
bit

Bit 0

WIP

Write In Progress Bit:
"0" indicates the device is ready
"1" indicates the write cycle is in progress and the device is busy

R

No

Bit 1

WEL

Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled

R/W

No

Bit 2

BP0

Bit 3

BP1

R/W

Yes

Bit 4

BP2

Block Protection Bit: (See Table 5 and Table 6 for details)
"0" indicates the specific blocks are not write protected (default)
"1" indicates the specific blocks are write protected

Bits 5 - 6

N/A

Reserved: Always "0"s

N/A

Bit 7

SRWD

Status Register Write Disable: (See Table 7 for details)
"0" indicates the Status Register is not write protected (default)
"1" indicates the Status Register is write protected

R/W

Yes

Table 5. Block Write Protect Bits for Pm25LV512A/010A/020
Status Register Bits

Protected Memory Area

BP1

BP0

Pm25LV512A

Pm25LV010A

Pm25LV020

0

0

None

None

None

0

1

None

1

0

None

1

1

All Blocks
000000h - 00FFFFh

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Upper quarter (Block 3) Upper quarter (Block 3)
018000h - 01FFFFh
030000h - 03FFFFh
Upper half (Block 2 & 3) Upper half (Block 2 & 3)
010000h - 01FFFFh
020000h - 03FFFFh
All Blocks
All Blocks
000000h - 01FFFFh
000000h - 03FFFFh

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Pm25LV512A/010A/020/040
REGISTERS (CONTINUED)
Table 6. Block Write Protect Bits for Pm25LV040
Status Register Bits

Protected Memory Area

BP2

BP1

BP0

Pm25LV040

0

0

0

None

0

0

1

Upper eighth (Block 7): 070000h - 07FFFFh

0

1

0

Upper quarter (Block 6 and 7): 060000h - 07FFFFh

0

1

1

Upper half (Block 4 and 7): 040000h - 07FFFFh

1

0

0

1

0

1

1

1

0

1

1

1

All Blocks (Block 0 to 7):
000000h - 03FFFFh

PROTECTION MODE
The Pm25LV512A/010A/020/040 have two protection
modes: hardware write protection and software write protection to prevent any irrelevant operation under a possible noisy environment and protect the data integrity.

SOFTWARE WRITE PROTECTION
The Pm25LV512A/010A/020/040 also provide two software write protection features:
a. Before the execution of any program, erase or write
status register instruction, the Write Enable Latch
(WEL) bit must be enabled by execution of the Write
Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part
or whole memory area to be write protected.

HARDWARE WRITE PROTECTION
The devices provide two hardware write protection
features:
a. When input program instruction, the input clock pulses
must be 32 clock pulses for command and address,
and a multiple of eight for 1 to 256 of data before
execution of programming. Other write instrucstion
must fit in with the number of clock pulse what the
instruction requirement before the execution. Any
incomplete instruction command sequence will be
ignored.
b. Write inhibit is 2.1V, all write sequence will be ignored when Vcc drop to 2.1V and lower.
c. The devices feature a Write Protection (WP#) pin to
provide a hardware write protection method for BP2,
BP1,BP0 abd SRWD in the Status Register.
(1)When the WP# is pulled low (VIL), the Status
Register is write protected if the SRWD bit is enabled
(Refer to Table 7 for Hardware Write Protection on
Status Register). Hence part or whole memory area
can be write protected depends on the setting of BP2,
BP1 and BP0 bits.
(2) When the WP# is pulled high (VIH), the Status
Register is not protected, BP2,BP1,BP0 and SRWD
can be changed.
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Table 7. Hardware Write Protection on Status
Register

9

SRWD

WP#

Status Register

0

Low

Writable

1

Low

Protected

0

High

Writable

1

High

Writable

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Pm25LV512A/010A/020/040
DEVICE OPERATION
The Pm25LV512A/010A/020/040 utilize an 8-bit instruction register. Refer to Table 8 Instruction Set for the detail Instructions and Instruction Codes. All instructions,
addresses, and data are shifted in with the most significant bit (MSB) first on Serial Data Input (SI). The input
data on SI is latched on the rising edge of Serial Clock
(SCK) after the Chip Enable (CE#) is driven low (VIL).

Every instruction sequence starts with a one-byte instruction code and might be followed by address bytes,
data bytes, or address bytes and data bytes depends
on the type of instruction. The CE# must be driven high
(VIH) after the last bit of the instruction sequence has
been shifted in.

Table 8. Instruction Set
Instruction Name

Instruction Format

Hex Code

Operation

WREN

0000 0110

06h

Write Enable

WRDI

0000 0100

04h

Write Disable

RDSR

0000 0101

05h

Read Status Register

WRSR

0000 0001

01h

Write Status Register

READ

0000 0011

03h

Read Data Bytes from Memory at Normal Read Mode

FAST_READ

0000 1011

0Bh

Read Data Bytes from Memory at Fast Read Mode

RDID

1010 1011

ABh

Read Manufacturer and Product ID

JEDEC ID READ*1

1001 1111

9Fh

Read Manufacturer and Prduct ID by JEDEC ID Command

PAGE_ PROG

0000 0010

02h

Page Program Data Bytes Into Memory

RDCR

1010 0001

A1h

Read Configuration Register

WRCR

1111 0001

F1h

Write Configuration Register

SECTOR_ER

1101 0111

D7h

Sector Erase

BLOCK_ER

1101 1000

D8h

Block Erase

CHIP_ER

1100 0111

C7h

Chip Erase

HOLD OPERATION
The HOLD# is used in conjunction with the CE# to select the Pm25LV512A/010A/020/040. When the devices
are selected and a serial sequence is underway, HOLD#
can be used to pause the serial communication

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with the master device without resetting the serial
sequence. To pause, the HOLD# must be brought low
while the SCK signal is low. To resume serial communication, the HOLD# is brought high while the SCK signal
is low (SCK may still toggle during HOLD). Inputs to the
Sl will be ignored while the SO is in the high impedance
state.

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Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
Table 9. Product Identification

READ PRODUCT IDENTIFICATION OPERATION
The Read Product Identification (RDID) instruction allows the user to read the manufacturer and product ID of
the devices. Refer to Table 9 Product Identification for
pFLASH™ manufacturer ID and device ID. The RDID instruction code is followed by three dummy bytes, each
bit being latched-in on SI during the rising edge of SCK.
Then the first manufacturer ID (9Dh) is shifted out on SO
with the MSB first, followed by the device ID and the
second manufacturer ID (7Fh), each bit been shifted out
during the falling edge of SCK. If the CE# stays low after
the last bit of second manufacturer ID is shifted out, the
manufacturer ID and device ID will be looping until the
pulled high of CE# signal.

Product Identification

Data

First Byte

9Dh

Second Byte

7Fh

Manufacturer ID
Device ID:
Pm25LV512A

7Bh

Pm25LV010A

7Ch

Pm25LV020

7Dh

Pm25LV040

7Eh

Figure 3. Read Product Identification Sequence

CE#

0

1

7

8

9

38

31

46

39

47

54

SCK

INSTRUCTION

SI

SO

3 Dummy Bytes

1010 1011b

HIGH IMPEDANCE

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Manufacture ID1

11

Device ID

Manufacture ID2

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Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ PRODUCT IDENTIFICATION BY JEDEC ID
COMMAND
The JEDEC ID READ instruction allows the user to read
the manufacturer and product ID of the devices. Refer to
Table 9 Product Identification for pFLASH™ manufacturer ID and device ID. The second manufacturer ID (7Fh)
is shifted out on SO with the MSB first after JEDEC ID
READ command input, followed by the first manufacturer ID (9Dh) and the device ID, each bit been shifted
out during the falling edge of SCK.

If the CE# stays low after the last bit of device ID is
shifted out, the manufacturer ID and device ID will be looping until the pulled high of CE# signal.
Pm25LV512A do not support this JEDEC ID READ
instruction.

Figure 4. Read Product Identification by JEDEC ID READ Sequence

CE#
0

15 16

7 8

23 24

31

SCK

INSTRUCTION

SI

SO

1001 1111b

HIGH IMPEDANCE

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Manufacture ID2

12

Manufacture ID1

Device ID

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Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the
Write Enable Latch (WEL) bit. The WEL bit of the
Pm25LV512A/010A/020/040 are set as write disable state
after power-up. The WEL bit must be write enabled before any write operation includes sector, block and

chip erase, page program, write status register, and write
configuration register operations. The WEL bit will be
reset back to write disable state automatically after the
completion of a write operation. The WREN instruction
is required before any above instruction is executed.

Figure 5. Write Enable Sequence

CE#

SCK

SI

INSTRUCTION = 0000 0110b
HI-Z

SO

WRITE DISABLE OPERATION
To protect the device against inadvertent writes, the Write
Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction is not

required after the execution of a write instruction. The
WEL will be automatically reset.

Figure 6. Write Disable Sequence

CE#

SCK

SI

INSTRUCTION = 0000 0100b
HI-Z

SO

Chingis Technology Corporation

13

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ STATUS REGISTER OPERATION
instructions will be ignored except the RDSR instruction
can be used for detecting the progress or completion of
the operations by reading the WIP bit of status register.

The Read Status Register (RDSR) instruction provides
access to the status register. During the execution of a
program, erase or write status register operation, all other
Figure 7. Read Status Register Sequence

CE#

1

0

2

3

5

4

7

6

8

9

10

11

12

13

14

15

1

0

SCK

SI

INSTRUCTION = 0000 0101b

DATA OUT
SO

HIGH IMPEDANCE

7

6

5

4

3

2

MSB

WRITE STATUS REGISTER OPERATION
The Write Status Register (WRSR) instruction allows
the user to enable or disable the block protection and
status register write protection features by writting “0”s

or “1”s into those non-volatile BP2, BP1, BP0 and SRWD
bits. The erase operation for those non-volatile bits are
not required.

Figure 8. Write Status Register Sequence
CE#

SCK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

2

1

0

DATA IN

SI
INSTRUCTION = 0000 0001b

7

6

5

4

3

HIGH IMPEDANCE
SO

Chingis Technology Corporation

14

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ CONFIGURATION REGISTER OPERATION
bottom Sector 0 and the write protection setting for each
individual 1 Kbyte sector (Sector 0_0 ~ Sector 0_3) within
the Sector 0.

The Read Configuration Register (RDCR) instruction provides access to the Configuration Register. This instruction can be used to verify the configuration setting of
Figure 9. Read Configuration Register Sequence

CE#

1

0

2

3

5

4

7

6

9

8

10

11

12

13

14

15

2

1

0

SCK

SI

INSTRUCTION = 1010 0001b

DATA OUT
SO

HIGH IMPEDANCE

7

6

5

4

3

MSB

WRITE CONFIGURATION REGISTER OPERATION
Do not require WREN command before this WRCR
operation. Because Configuration Register is a data latch
architecture.

The Write Configuration Register (WRCR) instruction allows user to enable or disable four smaller 1K byte
sectors and protection for each 1K byte sector by writing “0”s or “1”s into SCFG and SP0_3 ~SP0_1 in the
congiguration register. please refer table 2 for details.
Figure 10. Write Configuration Register Sequence
CE#

SCK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

2

1

0

DATA IN

SI
7

INSTRUCTION = 1111 0001b

6

5

4

3

HIGH IMPEDANCE
SO

Chingis Technology Corporation

15

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ DATA OPERATION
The Read Data (READ) instruction is used to read memory
data of Pm25LV512A/010A/020/040 under normal mode
running up to 33 MHz.

The first byte data D7 - D0 addressed (can be at any
location) is then shifted out onto the SO line. A single
byte data or up to whole memory array can be read out
in one READ instruction. The address is automatically
increamented to the next higher address after each byte
of data is shifted out. The read operation can be terminated any time by driving the CE# high (VIH) after the
data comes out. When the highest address of the devices is reached, the address counter will roll over to the
000000h address allowing the entire memory to be read
in one continuous READ instruction.

The READ instruction is activated by pulling the CE#
line of the selected device to low (VIL), and the READ
instruction code is transmitted via the Sl line followed by
three bytes address (A23 - A0) to be read. There are
total 24 address bits will be shifted in, only the AMS (mostsignificant address) - A0 will be decoded and the rest of
A23 - AMS can be don’t cared. Refer to Table 10 for the
related Address Key. Upon completion, any data on the
Sl will be ignored.

Table 10. Address Key

Address

Pm25LV512A

Pm25LV010A

Pm25LV020

Pm25LV040

AN

A15 - A0

A16 - A0

A17 - A0

A18 - A0

Don't Care Bits

A23 - A16

A23 - A17

A23 - A18

A23 - A19

Figure 11. Read Data Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10 11

28 29 30 31 32 33 34

35 36 37 38 39

SCK

3-BYTE ADDRESS
SI

SO

INSTRUCTION = 0000 0011b

23 22 21

...

HIGH IMPEDANCE

Chingis Technology Corporation

3

2

1

0

7

16

6

5

4

3

2

1

0

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
FAST READ DATA OPERATION
addressed is shifted out on SO line, each bit being shifted
out at a maximum frequency fCT, during the falling edge
of SCK.

The Pm25LV512A/010A/020/040 also feature a Fast
Read (FAST_READ) instruction. This FAST_READ instruction is used to read memory data in 100 MHz clock
rate where the FAST_READ instruction proceeding.

The first byte addressed can be at any location. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached, the address counter will roll
over to the 000000h address allowing the entire memory
to be read with a single FAST_READ instruction. The
FAST_READ instruction is terminated by driving CE#
high (VIH).

The devices are first selected by driving CE# low (VIL).
The FAST_READ instruction code followed by three bytes
address (A23 - A0) and a dummy byte (8 clocks) is
trasmitted via the SI line, each bit being latched-in during the rising edge of SCK. Then the first data byte

Figure 12. Fast Read Data Sequence
CE#

0

1

2

3

4

5

6

7

8

9

10 11

28 29

30

31

1

0

SCK

3-BYTE ADDRESS
SI

SO

23 22 21

INSTRUCTION = 0000 1011b

...

3

2

HIGH IMPEDANCE

CE#
32

33

34 35 36 37 38

39 40

41 42 43

44 45 46 47 48

SCK

DUMMY BYTE
SI

7

6

5

4

3

2

1

0

DATA OUT 1
SO

HIGH IMPEDANCE

Chingis Technology Corporation

7

6

5

4

17

3

DATA OUT 2
2

1

0

7

6

5

4

3

2

1

0

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
PAGE PROGRAM OPERATION
operation, all instructions will be ignored except the
RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP
bit in Status Register through a RDSR instruction. If WIP
bit = “1”, the program operation is still in progress. If WIP
bit = “0”, the program operation has completed.

The Page Program (PAGE_PROG) instruction allow up
to 256 bytes data to be programmed into memory in one
program operation page by page. The destination of the
memory to be programmed must be outside the protected memory area set by the Block Protection (BP2,
BP1, BP0) bits. A PAGE_PROG instruction attemps to
program into a page which is write protected will be
ignored. Before the execution of PAGE_PROG
instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.

A single PAGE_PROG instruction programs 1 to 256
consecutive bytes within a page if it is not write protected.
If more than 256 bytes data are sent to the devices, the
address counter will roll over on the same page and the
previously latched data are discarded and the last 256
bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the same page.
When the end of the page is reached, the address will
wrap around to the beginning of the same page. If the
data to be programmed are less than a full page, the
data of all other bytes on the same page will remain
unchanged.

The PAGE_PROG instruction is activated, after the CE#
is pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
PAGE_PROG instruction code, three address bytes and
program data (1 to 256 bytes) to be programmed via the
Sl line. Program operation will start immediately after
the CE# is driven high. Chip Select (CE#) must be driven
high after the eighth bit of last data byte has been latch
in, otherwise the PAGE_PROG instruction will not be
executed.

A program operation can alter “1”s into “0”s, but an erase
operation is required to change “0”s back to “1”s. The
same byte cannot be reprogrammed without erasing the
whole sector or block first.

The internal control logic automatically handles the programming voltages and timing. During a program

Figure 13. Page Program Sequence

4

5

6

7

8

9

10 11 28 29 30 31 32 33 34

2079

3

2078

2

2077

1

2076

0

2075

CE#

SCK

256th BYTE DATA-IN

1st BYTE DATA-IN
3-BYTE ADDRESS
SI

INSTRUCTION = 0000 0010b

23 22 21

3

2

1

0

7

6

5

4

3

2

1

0

HIGH IMPEDANCE
SO

Chingis Technology Corporation

18

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
ERASE OPERATION

BLOCK ERASE OPERATION

The memory array of Pm25LV512A/010A is organized
into uniform 4 Kbyte sectors or 32 Kbyte uniform blocks
(sector group - consists of eight adjacent sectors). The
memory array of Pm25LV020/040 are organized into
uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (sector group - consists of sixteen adjacent sectors). The
Pm25LV010A/020/040 of bottom sector (Sector 0) of the
devices can be configured into four 1 Kbyte smaller
sectors.

A Block Erase (BLOCK_ER) instruction erases a 32
Kbyte block for the Pm25LV512A/010A or a 64 Kbyte
block for the Pm25LV020/040. Before the execution of
BLOCK_ER instruction, the Write Enable Latch (WEL)
must be enabled through a Write Enable (WREN) instruction. The WEL will be reset automatically after the
completion of block erase operation.

Before a byte can be reprogrammed, the sector or block
which contains this byte must be erased first. In order to
erase the devices, there are three erase instructions include Sector Erase (SECTOR_ER), Block Erase
(BLOCK_ER) and Chip Erase (CHIP_ER) instructions
can be used. A sector erase operation allows to erase
any individual sector without affecting the data in others.
A block erase operation allows to erase any individual
block. And a chip erase operation allows to erase the
whole memory array of the devices. Pre-programs the
devices are not required prior to a sector erase, block
erase or chip erase operation.
SECTOR ERASE OPERATION
A SECTOR_ER instruction erases a 4 Kbyte sector or a
1 Kbyte smaller sector (Sector 0_3, Sector 0_2, Sector
0_1, Sector 0_0) if the bottom Sector 0 has been configured as four smaller sectors. Before the execution of
SECTOR_ER instruction, the Write Enable Latch (WEL)
must be enabled through a Write Enable (WREN) instruction. The WEL will be reset automatically after the
completion of sector erase operation.
The SECTOR_ER instruction is entered, after the CE#
is pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
SECTOR_ER instruction code and three address bytes
via the SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the SECTOR_ER instruction will not be executed. The internal control logic
automatically handles the erase voltage and timing. Refer to Figure 13 for Sector Erase Sequence.

The BLOCK_ER instruction is entered, after the CE# is
pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
BLOCK_ER instruction code and three address bytes
via the SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BLOCK_ER instruction will not be executed. The internal control logic
automatically handles the erase voltage and timing. Refer to Figure 14 for Block Erase Sequence.
CHIP ERASE OPERATION
A Chip Erase (CHIP_ER) instruction erases the whole
memory array of Pm25LV512A/010A/020/040. Before the
execution of CHIP_ER instruction, the Write Enable Latch
(WEL) must be enabled through a Write Enable (WREN)
instruction. The WEL will be reset automatically after
the completion of chip erase operation.
The CHIP_ER instruction is entered, after the CE# is
pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
CHIP_ER instruction code via the SI. Erase operation
will start immediately after the CE# is pulled high, otherwise the CHIP_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 15 for Chip Erase
Sequence.

During a erase operation, all instruction will be ignored
except the Read Status Register (RDSR) instruction.
The progress or completion of the erase opertion can be
determined by reading the WIP bit in Status Register
through a RDSR instruction. If WIP bit = “1”, the erase
operation is still in progress. If WIP bit = “0”, the erase
operation has been completed.
Chingis Technology Corporation

19

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
Figure 14. Sector Erase Sequence
CE#

0

1

2

3

4

5

6

7

8

9

10

11

28

29

30

31

SCK
3-BYTE ADDRESS
SI

SO

INSTRUCTION = 1101 0111b

23

22

8

9

21

...

3

2

1

0

28

29

30

31

1

0

HIGH IMPEDANCE

Figure 15. Block Erase Sequence
CE#

0

1

2

3

4

5

6

7

10

11

SCK
3-BYTE ADDRESS
SI

SO

INSTRUCTION = 1101 1000b

23

22

21

5

6

7

...

3

2

HIGH IMPEDANCE

Figure 16. Chip Erase Sequence
CE#

0

1

2

3

4

SCK

SI

SO

Chingis Technology Corporation

INSTRUCTION = 1100 0111b

HIGH IMPEDANCE

20

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
BLOCK/SECTOR ADDRESS
Table 11. Block/Sector Addresses of Pm25LV512A/010A

Memory Density

Block No.

Block Size
Sector Size
Sector No.
(Kbytes)
(Kbytes)
(1)

4

000000h - 000FFFh

Sector 1

4

001000h - 001FFFh

:

:

:

Sector 7

4

007000h - 007FFFh

Sector 8

4

008000h - 008FFFh

Sector 9

4

009000h - 009FFFh

:

:

000000h - 006FFFh

Sector 15

4

00F000h - 00FFFFh

Sector 0
Block 0

32

512 Kbit
1 Mbit
Block 1

32

Address Range

Block 2

32

"

"

010000h - 017FFFh

Block 3

32

"

"

018000h - 01FFFFh

Note: 1. Pm25LV010A support 1KByte small sector - Sector 0 can be configured into four smaller 1 Kbyte
sectors (Sector 0_0: 000000h - 0003FFh, Sector 0_1: 000400h - 0007FFh, Sector 0_2: 000800h 000BFFh, and Sector 0_3: 000C00h - 000FFFh).

Chingis Technology Corporation

21

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
BLOCK/SECTOR ADDRESS (CONTINUED)
Table 12. Block/Sector Addresses of Pm25LV020/040

Memory Density

Block No.

Block Size
(Kbytes)

Sector Size
(Kbytes)

Address Range

4

000000h - 000FFFh

Sector 1

4

001000h - 001FFFh

:

:

:

Sector 15

4

00F000h - 00FFFFh

Sector 16

4

010000h - 010FFFh

Sector 17

4

011000h - 011FFFh

:

:

:

Sector 31

4

01F000h - 01FFFFh

Sector No.
Sector 0

Block 0

(1)

64

2 Mbit
Block 1

64

4 Mbit

Block 2

64

"

"

020000h - 02FFFFh

Block 3

64

"

"

030000h - 03FFFFh

Block 4

64

"

"

040000h - 04FFFFh

Block 5

64

"

"

050000h - 05FFFFh

Block 6

64

"

"

060000h - 06FFFFh

Block 7

64

"

"

070000h - 07FFFFh

Note: 1. Sector 0 can be configured into four smaller 1 Kbyte sectors (Sector 0_0: 000000h - 0003FFh, Sector
0_1: 000400h - 0007FFh, Sector 0_2: 000800h - 000BFFh, and Sector 0_3: 000C00h - 000FFFh).

Chingis Technology Corporation

22

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias

-65oC to +125oC

Storage Temperature

-65oC to +125oC
Standard Package

240oC 3 Seconds

Lead-free Package

260oC 3 Seconds

Surface Mount Lead Soldering Temperature
Input Voltage with Respect to Ground on All Pins

(2)

-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V

All Output Voltage with Respect to Ground
V CC

(2)

-0.5 V to +6.0 V

Notes:
1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only. The functional operation of the device or any other
conditions under those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condition for extended periods may affected
device reliability.
2. Maximum DC voltage on input or I/O pins are VCC + 0.5 V. During voltage transitioning
period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns.
Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period,
input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns.

DC AND AC OPERATING RANGE
Part Number

Pm25LV512A/010A/020/040
-40oC to +105oC

Operating Temperature
Vcc Power Supply

Chingis Technology Corporation

2.7 V - 3.6 V

23

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
DC CHARACTERISTICS
Applicable over recommended operating range from:
TAC = -40°C to +105°C, VCC = 2.7 V to 3.6 V (unless otherwise noted).
Symbol

Parameter

Min

Condition

Typ

Max

Units

ICC1

Vcc Active Read Current

VCC = 3.6V at 33 MHz, SO = Open

10

15

mA

ICC2

Vcc Program/Erase Current

VCC = 3.6V at 33 MHz, SO = Open

15

30

mA

ISB1

Vcc Standby Current CMOS VCC = 3.6V, CE# = VCC

10

20

uA

ISB2

Vcc Standby Current TTL

VCC = 3.6V, CE# = VIH to VCC

3

mA

ILI

Input Leakage Current

VIN = 0V to VCC

1

uA

1

uA

o

o

VIN = 0V to VCC, TAC = 0 C to 105 C

ILO

Output Leakage Current

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input HIgh Voltage

0.7VCC

VCC + 0.3

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

Chingis Technology Corporation

2.7V < VCC < 3.6V

IOL = 2.1 mA
IOH = -100 uA

24

VCC - 0.2

V

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
AC CHARACTERISTICS
Applicable over recommended operating range from TA = -40°C to +105°C, VCC = 2.7 V to 3.6 V
CL = 1TTL Gate and 10 pF (unless otherwise noted).
Symbol

Parameter

fCT

Clock Frequency for fast read mode

fC

Clock Frequency for read mode

tRI

Max

Units

0

100

MHz

0

33

MHz

Input Rise Time

8

ns

tFI

Input Fall Time

8

ns

tCKH

SCK High Time

4

ns

tCKL

SCK Low Time

4

ns

tCEH

CE# High Time

25

ns

tCS

CE# Setup Time

10

ns

tCH

CE# Hold Time

5

ns

tDS

Data In Setup Time

2

ns

tDH

Data in Hold Time

2

ns

tHS

Hold Setup Time

15

ns

tHD

Hold Time

15

ns

tV

Output Valid

tOH

Output Hold Time Normal Mode

tLZ

Hold to Output Low Z

200

ns

tHZ

Hold to Output High Z

200

ns

tDIS

Output Disable Time

100

ns

tEC

Secter/Block/Chip Erase Time

60

100

ms

tPP

Page Program Time

2

5

ms

tW

Write Status Register Time

60

100

ms

tVCS

VCC Set-up Time

Chingis Technology Corporation

Min

Typ

8
0

50

25

ns
ns

µs

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING(1)

CE#

tCEH

VIH
VIL

tCS
SCK

SI

tCH

VIH

tCKH

VIL

tDS

VIH

tCKL

tDH
VALID IN

VIL

tV
VOH

SO

tOH

tDIS
HI-Z

HI-Z

VOL

Note: 1. For SPI Mode 0 (0,0)

Chingis Technology Corporation

26

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
AC CHARACTERISTICS (CONTINUED)
HOLD TIMING

CE#
tH D

tH D
SCK
tH S
tH S

HOLD#
tH Z
SO

tL Z

PIN CAPACITANCE ( f = 1 MHz, T = 25°C )
Typ

Max

Units

Conditions

C IN

4

6

pF

VIN = 0 V

C OUT

8

12

pF

VOUT = 0 V

Note: These parameters are characterized but not 100% tested.
OUTPUT TEST LOAD

INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL

Vcc

0.8Vcc
Input
1.8 K

0.5 Vcc

AC
Measurement
Level

0.2Vcc
OUTPUT PIN

1.3 K

Chingis Technology Corporation

10 pF

Note: 1. Input Pulse Voltage : 0.2Vcc to 0.8Vcc.
2. Input Timing Reference Voltages :
0.3Vcc to 0.7Vcc.
3. Output Timing Reference Voltage : Vcc/2.

27

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (CE# must follow the voltage applied on Vcc)
until Vcc reaches the correct value:
- Vcc(min) at Power-up, and then for a further delay of
tVCE
- Vss at Power-down
Usually a simple pull-up resistor on CE# can be used to
insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is
included. The logic inside the device is held reset while
Vcc is less than the POR threshold value (Vwi) during
power up, the device does not respond to any instruction
until a time delay of tPUW has elapsed after the moment
that Vcc rised above the VWI threshold. However, the
correct operation of the device is not guaranteed if, by
this time, Vcc is still below Vcc(min). No Write Status

Register, Program or Erase instructions should be sent
until the later of:
- tPUW after Vcc passed the VWI threshold
- tVCE after Vcc passed the Vcc(min) level
At Power-up, the device is in the following state:
- The device is in the Standby mode
- The Write Enable Latch (WEL) bit is reset
At Power-down, when Vcc drops from the operating
voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write
instruction.

Power-up Timing
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed

Vcc(min)
Reset State
tVCE

V (write inhibit)

Read Access Allowed

Device fully accessible

tPUW

Time

Symbol
Parameter
*1
tVCE
Vcc(min) to CE# Low
tPUW

*1

Power-Up time delay to W rite instruction

*1

VW I
W rite Inhibit Voltage
Note : *1. These parameters are characterized only.

Chingis Technology Corporation

28

Min.
10

Max.

Unit
us

1

10

ms

2.1

2.3

V

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PROGRAM/ERASE PERFORMANCE
Parameter

Unit

Typ

Max

Remarks

Sector Erase Time

ms

60

100

From writing erase command to erase completion

Block Erase Time

ms

60

100

From writing erase command to erase completion

Chip Erase Time

ms

60

100

From writing erase command to erase completion

Page Programming Time

ms

2

5

From writing program command to program
completion

Note: These parameters are characterized and are not 100% tested.

RELIABILITY CHARACTERISTICS
Parameter
Endurance
Data Retention
ESD - Human Body Model
ESD - Machine Model
ESD - Charged Device Model
Latch-Up

Min

Typ

Unit

Test Method

200,000

Cycles

JEDEC Standard A117

20

Years

JEDEC Standard A103

2,000

Volts

JEDEC Standard A114

200

Volts

JEDEC Standard A115

1,000

Volts

JEDEC Standard C101-A

100 + ICC1

mA

JEDEC Standard 78

Note: These parameters are characterized and are not 100% tested.

Chingis Technology Corporation

29

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION
8S
8-Pin JEDEC 150mil Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
Top View

Side View

0.595
0.495

0.51
0.33
5.00
4.80
1.27 BSC

4.00
3.80

0.25
0.10

6.20
5.80

1.75
1.35

End View
45º

0.25
0.19

1.27
0.40

0o
8o

`

Chingis Technology Corporation

30

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION
8B
8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
Top View

Side View

0.48
0.35
5.38
5.18
1.27 BSC

0.25
0.05

5.38
5.18
8.10
7.70

2.16
1.75

End View
5.33
5.13

0.25
0.19
5.38
5.18

0.80
0.50

`

Chingis Technology Corporation

31

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION (CONTINUED)
8K
8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)

Top View

Side View

5.00
BSC

6.00
BSC

Bottom View

0.25
0.19
Pin 1

0.80
0.70

1.27
BSC
3.40

4.00

0.48
0.35
0.75
0.50

Chingis Technology Corporation

32

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION (CONTINUED)
8P
8-pin 300mil wide body, Plastic Dual In-Line Package PDIP (measure in millimeters)

9.53
9.12

0o
15o

8.26
7.62

6.60
6.20

3.45
3.25

9.40
8.38

4.20
3.60

0.38(min)

3.18(min)

0.56
0.36
2.54
(typ)
1.65
1.40

Chingis Technology Corporation

33

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION (CONTINUED)
8D
8-pin TSSOP Package (measure in millimeters)

4.3
4.5
6.2
6.6

0.127

Pin1

Detail A

2.9
3.1

1.00
1.05
1.05
1.20

Detail A

0.25
0.30

GAGE PLANE

0.05
0.15

0.25

0.65

0.5
0.7

00
80

Unit : millimeters

Chingis Technology Corporation

34

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
REVISION HISTORY
D a te

R e v is io n N o .

J a nua ry, 2 0 0 4

0 .3

A d va nce d P ro d uc t S p e c ific a tio n

A ll

M a rc h, 2 0 0 4

0 .4

E xte nd The R a ng e o f O p e ra tio n Te m p e ra ture

A ll

A ug ust, 2 0 0 4

0 .5

C o rre ct p a rt no fo r W S O N p a c ka g e
R e g is te r sta tus s e tting

O c to b e r, 2 0 0 4

0 .6

C o rre ct p a rt no
R e g is te r se tting fo r s m a ll s e cto r fe a thure

J a nua ry, 2 0 0 5

0 .7

P re lim ina ry ve rs io n re le a s e

J a nua ry, 2 0 0 5

0 .8

1 . S up p o rt 2 0 8 m il S O IC p a c ka g e
2 . C o rre ct re a d tim ing fo r D 0 la tch b y H O S T
3 . R e m o ve Turb o m o d e

F e b rua ry, 2 0 0 5

0 .9

S up p o rt 3 3 M H z
R e m o ve d b a sk s id e m e ta l o f W S O N
S ta nd b y c urre nt

M a y, 2 0 0 5

1 .0

J E D E C ID R E A D ins truc tio n
C o rre ct the s m a lle r se c to r (1 K B ) fe a ture

6 ,7 ,1 0 ,1 2

J une , 2 0 0 5

1 .1

D e s c rip tio n up d a te fo r the o p e ra tio n o f C o nfig ura tio n
R e g is te r

8 ,9 ,1 5 ,1 6

J uly, 2 0 0 5

2 .0

S up p o rt 7 5 M H z fo r F a st R e a d M o d e

2 .1

1 . U p d a te fa st re a d s p e e d to 1 0 0 M H z.
2 . S e c to re /B lo ck a rc he ticture d e s crip tio n.
3 . O rd e ring info rm a tio n - re m o ve no n-p b fre e p a rts .
4 . H ig hlig h no re q uire W R E N b e fo re W R C R co m m a nd .
5 . A C m e a s ure m e nt co nd itio ns .

1 ,3 ,1 6 ,2 8

N o ve m b e r, 2 0 0 5

2 .3

1 . C ha ng e A C p a ra m a te rs fo r 1 0 0 M H z s p e c .
Tv 8 ns w ith 1 0 p F L o a d ing , D a ta In H o ld /S e tup tiim e
2 ns (m in), C lo ck hig h/lo w tim e 4 ns(m in)
TR I, TF I, 8 ns (m a x), TD IS 1 0 ns (m a x)
2 . S up p o rt C o m m e rcia l G ra d e to -4 0 ~+8 5 d e g re e C
3 . P a rtno cha g e fo r P m 2 5 LV 0 1 0 to P m 2 5 LV 0 1 0 A .

3 , 2 4 ,2 5

F e b rua ry, 2 0 0 6

2 .4

1 . U p d a te e nd ura nce to 2 0 0 K cycle .
2 . U p d a te w rite inhib it s p e c . to 2 .1 V .
3 . U p d a te E S D C D M sp e c 1 0 0 0 V.

M a rc h, 2 0 0 6

2 .5

1 .C ha ng e L o g o a nd co m p a ny na m e
2 .M o d ifie d te st c o nd itio n fo r D C

M a rc h, 2 0 0 6

2 .6

E xte nd the o p e ra te d te m p e ra ture to +1 0 5 d e g re e C

A p ril, 2 0 0 6

2 .7

1 . U p d a te P m 2 5 LV 5 1 2 A in the d a ta she e t
2 . C o rre ct tC H d e finitio n
3 . P o w e r-up tim ing d ifinitio n

M a y, 2 0 0 6

2 .8

C o rre ct the s ta te m e nt o f ha rd w a re w rite p ro te c tio n

J une , 2 0 0 6

2 .9

S up p o rt 8 -p in P D IP p a c k a g e fo r 4 M b S P I

1 ,2 ,3 ,3 3

M a y, 2 0 0 7

3 .0

S up p o rt s e cto r lo c k/unlo ck fe a ture s
U p d a te e ra s e a nd W R S R tim e

1 ,1 0 ,11
1 ,2 6 ,3 0

J a n. 2 0 0 8

3 .1

S up p o rt TS S O P p a ck a g e fo r P m 2 5 LV 5 1 2 A .
S up p o rt S e c to r L o c k/U nlo ck fo r P m 2 5 LV 0 2 0 .

1 , 3 ,3 5
1 0 ,11

Feb. 2008

3 .2

S up p o rt W S O N w ith b a ck s id e m e ta l

J uly, 2 0 0 5

Chingis Technology Corporation

D e s c rip tio n o f C h a n g e s

35

Page N o.

3
6 ,7 ,8
A ll
page 7

A ll

1 ,3 ,1 5 ,2 3 ,2 4 ,
30

A ll

1 ,9 ,2 8
A ll
24
3 ,2 3 ,2 4 ,2 5
A ll
2 5 ,2 6
28
9

3, 34

Issue Date: Feb., 2009, Rev: 3.5

Pm25LV512A/010A/020/040
D a te

R e vision N o .

J un , 2 00 8

3 .3

A d d t h e T S S O P p a r t n u m b er

J u l y ,2 0 0 8

3 .4

R em ov e 8Q p ackag e

F eb, 20 09

3 .5

M o d if y D C

Chingis Technology Corporation

D e s c r i p ti on o f C h a n g e s

Pag e N o .
3
3

C H Z ta bl e

24

36

Issue Date: Feb., 2009, Rev: 3.5



---

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Title                           : SPI Data Sheets - Pm25LV512A, Pm25LV010A, Pm25LV020, Pm25LV040
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