PSM512_Single_Card_512K_8_Bit_Multibus_Memory_Feb81 PSM512 Single Card 512K 8 Bit Multibus Memory Feb81

PSM512_Single_Card_512K_8_Bit_Multibus_Memory_Feb81 PSM512_Single_Card_512K_8_Bit_Multibus_Memory_Feb81

User Manual: PSM512_Single_Card_512K_8_Bit_Multibus_Memory_Feb81

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PSM512 HANDBOOK
SINGLE CARD 512K
8 BIT MEMORY

CD

MICROSYSTEMS

.

8

P'~ssey

PSM512 HANDBOOK
SINGLE CARD 512K
8 BIT MEMORY

,

.

e

Microsystems

.~

l,se

t

The ?IessI¥ Canoany l.;mIllId

T'his ~ ana :Me rnTonTIatiQn e:rnaJneCI II.,,," may MOt ee e:lCIed.

I

used or dsc:csecr In wnae or :n can CC3Ct 'MU\ me oner ·...rmen
cerrTUSSIOIT at iIIe ~ ~ wmrtlld Ct. If :l'IIS =ctIment ;'I3S

::... ~ unaar a =rmac:: .....1n ~;::any. a UI:lI'4!SI1y
IUl:lanMC uncer mat e::mrac:. It is smied'Mlna.lt !iacnJry tor
~ OIl

ClmlGlCI1S.

,.....,. Mlc:osysttlf'tS l.irntt.e
Water '..an •• 1"CYICaS':I!t'. ~ ~IN'<: 7';:-1
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421jHBjlO225

PSM512 HANDBOOK - SINGLE CARD 512K 8 BIT
MEMORY
iSSl;e

1

r ~C;Et

(; )

8

8

Plessey Microsystems

DOCUMENT AUTHORlSAT10N

Prepared

By:

Approved

A. WAIGHTS

Department:

ENGINEERING

Division:

MICROSYSTEMS

By

engineering:
- ./

Marketing:

J k~ "

/

L

T?'\..;'/ -

First Issue:
OOCUMENT ISSUE. STATE

Issue

1

Date

2.11.81

c.'iange No.
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421 iHB!1 0225

PSM512 HANDBOOK - SINGLE CARD 512K 8 BIT
r~EMORY
iSS1.ie

1

;:lage

I

I

I

~

I

~

421/HB/10225

CONTENTS

PAGE

1.

SCOPE

4

2.

RELATED DOCUMENTS

4

3.

GENERAL DESCRIPTION
3.1 System Configuration
3.2 Circuit Description
3.3 Mechanical Construction

6

8

4.

SPECIFICATION SUMMARY

9

5.

ELECTRICAL CHARACTERISTICS
5.1 Functional Description
5.2 Interface Characteristics
5.3 Error Detection and Correction
5.4 Power Requirements
5.5 Memory Capacities

21
21
21

6.

ENVIRONMENTAL SPECIFICATION
6.1 Operating
6.2 Storage

27
27
27

7.

QUALITY AND RELIABILITY
28
7.1 Quality Programme for Design, Manufacture and Test 28
7.2 Reliability
28
29
7.3 Mean Time Between Failures

8.

MAINTENANCE

30

9.

BOARD SET UP
9.1 Interrupt
9.2 Memory Mapping
9.3 Refresh
9.4 Data Retention
9.5 Mi s ce 11 aneous

31
31
33

6

6

10
10
11

43
43
43

Page 2 Issue 1

421jHBjl0225

PAGE

CONTENTS
10.

SYSTEM DESCRIPTION
10.1 Memory Array
10.2 Address Multipying, Memory Selection and RAS
Decode
10.3 Refresh Logic
10.4 Data Control
10.5 Timi.ng Control
10.6 Error Detection and Correction

44
44
46

11.

FAULT FINDING

52

12.

INSTALLATION AND OPERATION
12.1 Receiving Inspection
12.2 Installation
12.3 Power Requirement

54

APPENDIX 1

47
49
50
51

54
54
54

55 - 57

Page 3 Issue 1

421/HB/10225

1.

SCOPE
This document defines the functional. e1ec~rical and mechanical
characteristics of the Plessey Semiconductors Memory PSM 512.
designed and manufactured by Plessey Microsystems Limited.
The PSM 512 is part of the Plessey series of module memory
systems designed for modular storage requirements.

2.'

RELATED DOCUMENTS
PLESSEY MICROSYSTEMS QUALITY MANUAL
PLESSEY MICROSYSiEMS ENGINEERING INSiRUCiION MANUAL
APPLICATION NOTES PSM 512.

Page 4 Issue 1

..

REAll/
WRITE
8UFnns

MS" 1

---TfA5"

1---. -- -. -.. - ..7. .

ADDRESS 8US
20 BITS

I
-

--

,ms

ADDRESS

~

BLOCK

----.-

8YTE ()

J

.-..i(1\S tl

----~---.

DATA 0-1 "

---- II-

- ....ADORES
--- .--.----

Mf.MORV
AOI_

i-

AIU{A V
(2S6K 16)

n[FHESII

RAS

ERROR
DETECTION

&COftRECTION
lOGIC

SWAP
OUFF£nS

-

i~nDC

,O\'S"

lW

EUoR

f'NIo-7

TIfff

PfUU

EXT ftE F

..

1\-~K

READ/

WRITE

lACK
"Q

DUfFER

lU

nEAD

I»

10
ID
Ul

nnrn

.

."..

0-'
II)
II)

c

III

NPIID

II-

... -

--r
BYTE 1

---- --_.-

__ __

WRI
-. TE.

._ _ _ _ _ _ _ _._ _ A _ __

llVH/WORO

---------

........

512K
8 OIT ----f1LMOHV
----.------BLOCK
-_.- - ...SUllMIH
- - - -I-C

"
j

DA rA

.~
. \ ....
~ f'o.l
.....
j:

U- 15"

421/HB/10225

3.

GENERAL DESCRIPTION

3.1

SYSTEM CONFIGURATION
The PSM 512 memory is designed to use with 8 bit and 16 bit
microprocessors. The memory has a maximum capacity of 524,288
words 8 bits and operates at a maximum cycle time of 500 nanoseconds, with an access time not greater than 300 nano-seconds.
The memory may be operated with an 8 bit or 16 bit word length.
The memory has an address capability of 16,048,576 words, thus 32
memory cards may be operated together to give a maximum capacity
of 8,048,576 words 16 bits.
The memory is fitted with single bit error detection and correction
and double error detection circuitry.
The communication between the Data Processing Equipment and the
memory takes place by means of three main buses. These are:Bi-directiona1 Data Bus
Control Bus
Address Bus

3.2

CIRCUIT DESCRIPTION
The memory uses the industry standard 16 pin dua1-in-1ine 65,536
MOS dynamic RAMS.
Texas 75136 Transceivers are connected to the Data bus. Address and
control input lines to the memory are loaded with one LS gate with
the exception of addresses ~, ~, ~, ~ and ~'which
have a maximum load of three LS gates.
The memory card can be depopulated to give different memory capacities.
On cardcompari tors enables the memory.starting and finishing addresses
to be selected by means of a dual-in-1ine switch. The address
boundary for the starting and finishing addresses are restricted to
64K when working in a 1 megabyte field. When working in a 16 megabyte
field the address is switchable into 5l2K blocks which cannot straddle
1 megabyte boundaries.
The internal timing signals for the memory are generated by means of
dual-in-line delay lines and TTL gates.
The block diagram of the memory system ;s shown on Page 5.
Page'6 Issue 1

0.25 x 4~

(2 PLACES)

~.------

-

.

.. ..

.,-------_.- .. --_ .. -_ .. -._._..

-,

.

'"

.'-

.....

..

12.000
REF
.. _... ----_._.
----

.

.... -

~

-

....

I

I

-

~-

0.250 REF
--. r-

--f

-

I

.to

til
til

.

0

COMPONnH S I DE

0\

1+

N
0

.
0

.
0

r

-n

0
0

til

86 WAY
.....

I/)

III

C
111

0.06R
(12 PLACES)

lL-------:~::~OC~05 ____-·-_-_·-=1

--W

I·

.60 WAY
0.100" cc
3.080
4.570

.

-~~ I-' -

f

[).5~

...J

lQ..30

-0.390

42i/HB!10225

3.3

MECHANICAL CONSTRUCTION
The memory is constructed on a sing1e printed card.
Details of the card size are s-hown on Page 7.
Connection to the card is via two edge connectors, one
designated P1 is 86 way, (43 + 43) on 0.156" centres.
The other designated P2 is 60 way (30 + 30)- on 0.1" centres.
Maximum component height of £r.4---enables cards to
be spaced on (0.6")" ce.ntres.

Pag~

8 Issue 1

42i/HB/l0225

4.

SPECIFICATION SUMMARY
Word Length:

8 bits or 16 bits

Number of Words:

524~288

Re 1i ab i 1i ty:

Better than 200,000 hours MTBF

Cycle Time:

500 nS Read or Write

Access Time:

300 nS Variant 1**
350 nS Variant 0**
Read

Modes or Operation:

max.

Write
Rerresh
~lec~rical

Interface:

Power:

?hysical Configuration:

ill

Operational SV

3.5 amps Max.

Standby

3 . 0 amps Max.

5V

SSC compatible
320 mm x 15' rom x

~3

mm

(12 in. x 6.75 in. x 0.5 in.)
Interface:

One 0.156 in. pitch edge connector
43 x 43 way.

One 0.1 in. pitch

_edge connector 30 + 30 way
Temperature range:
Humidity:

o-

Wei ght:

1 Kg (2.2 lb.)

95% without condensation

Page 9 Issue 1

421/HB/10225

5.

ELECTRICAL CHARACTERISirCS

5.1

FUNCTIONAL DESCRIPTION
The memory operates in the following modes:Read Cycle
Write Cycle
Refresh Cycle

5.1.1

READ CYCLE
On command from the processor, the memory places the contents of
of the address location onto the Data bus.
The read data is retained in the memory.

5.1.2 WRITE CYCLE
presented on the Data bus by the processor is written into
the addressed location.
Da~a

5.1.3

R£FRESH CYCLE
At ieast once every 2 mi11i-seconds the con~ents of the memory require
to be refreshed.
The memory uses distributed refresh and refresnes
the contents of one row address approximately every 15 microseconds.
Refresh ~cles occur asynchronously and in the event of simultaneous
.
requests from the processor and the refresh circuitry, a priority
staticiser determines which cycle the memory accepts.
If the memory
cycle carried out first is the refresh cycle, then the processor request
is staticised and actioned on completion of the refresh cycle. When
priority is given to the processor cycle. the next memory cycle wil' be
a refresh cycl e.
The on card refresh circuitry can be disabled at the interface and
refresh cycles can be initiated by the processor.

Page 10 Issue 1

421/HB/10225

5.2

INTERFACE CHARACTERISTICS

5.2.1 LOGIC LEVEL
Input and Output logic level shall be as follows:MIN.

Logic
Logic
Logic
Logic

high input voltage V!H
low input voltage VIL
high output voltage VOH
low output voltage VOL

2.2
-0.5
2.2
-0.5

MAX.

5.25V
O.6V
S.2SY
O.6V

Timings shall be measured at the O.BY ievel for low going signals anc
a: the 2.0Y level for high going signals.

?age lj

Issue 1

421;fiB /10225

5.2.2 INTERFACE SIGNALS
Input signals are all single sided, the complement is not
required.
The Data bus is connected to the memory via Texas 75136
transceivers.
The control and address inputs are loaded with one LS gate
except addresses Amrn', mnrrrr, A'OlITT, ~ and Arn 15 ~ seconds the on board refresh
re-asserts itself enabling the RAMS to be refreshed under idle or
DMA transfer conditions.
Internal Refresh
This ;s achieved by connecting LK23, and under these conditions
the board initiates its own refresh cycles every 15 ~ seconds.

Page 15 Issue 1

421/HB/10225

5.2.2.7 ADVANCE ACKNOWLEDGE (AACR)
signal from the memory to the processor indicating that the
memory has received the command signal. This line goes from
the logic high level to logic low level not later than
100 n seconds after the leading edge of the command signal and
will remain at logic low level until the command signal has been
removed.
A

5.2.2.8 TRANSFER ACKNOWLEDGE (XACK)
Signal from the memory going from a logic high level to a logic
low level indicating to the processor that the Data, in a write
cycle,has been accepted by the memory and that the data lines may
now be changed.
In a read cycle,
on the Data Bus.

~

indicates that the read data has been placed

5.2.2.9 MEMORY INHIBIT (iNH 1)
This line taken from the high to low state 10 nano-seconds before
the command signal going low prevents memory access, on both ~
and ~ remain high.
If the inhibit line is taken low 50 nS after
the command then an AACR may appear but XACK will remain high. This
permits PROM or memory mapped I/O to be allocated space within the
memory address field.

Page 16 Issue 1

42l/HB/l0225

5.2.2.10 MEMORY PROTECT

(~)

This line, via the auxiliary connector P2 on going low indicates
that the input signals to the memory are no longe!" val id due
to power failure.
This line used in conjunction with an
auxiliary power supply connected via the P2 connector permits
the memory to preserve data in the event pf main power failure.

5.2.2.11 BYTE HIGH ENABLE (]RtN)
This signal from the processor ;s used in conjunction with address
~ to provide Byte operation of the memory.
The memory is provided with data buffers which enable the memory's
most significant data bits to be connected to Data Bus ~ - ~
In this configuration the memory operates as an 8 bit memory.
0-

When

~

is jew, the memory ;s configured as a 16 bit memory. When
~ ;s high, the Data Bus ]A7rr - ~ is connected to the least
significant byte or the most significant by:e of the memory depending
upon the level of address AD'R'O. The truth tab 1e iss hown be low.

Page 17 Issue 1

421/ HB/10225

MEMORY
11.5

IMS

BUS

I

BY~I..

ByTE!

I mirn AtJRO I TRANSF'ER DATA PATrl

~ATO-15AT

-0D

H

- -

H

S BIT DATO-DAT7 LSB

DATS-DATF
,I

ILS BY,]

i

I

DAIC-DAI;

H

L

--

i8 BIT DATO-DAT7 ~SB

I
I
I
I,.,s

BY

,
I

!

OATB-DATF

r-

"

~

ILS

BYr5;~

.1

it

LJ
j-;
'I -:

D~T"O-DAi7

I

I,
!

,

i

L

i

H

! j 5 8 IT DATO-DATF 'rtORO

!

W

r.s

SYI~'

-

tLJ
:

I

I

DATS-DATF

DATA TRANSFE'R 8116 B.IT OPERATION

Page 1 8 Issue 1

421;HB 110225

5.2.2.12 SINGLE BIT ERROR INDICATION (S.B.E.)
This indicates the occurance of a corrected single bit
error in the word or chec~ bits being read.
This signal is optional and may be linked into INTO - 7,
power fail interrupt, or a LED, but there are conditions for
its use.
1)

On initial power up all memory locations which are
going to be used should be written to.

2)

No S.B.E. will be indicated after power up until the
first read command.

3)

The output signal is staticised and is reset by
(a)

The next write command

(b)

The Initialise signal

(c)

Power switch off-on

5.2.2.13 DOUBLE BIT ERROR INDICATION
This indicates the occur:.ence of two or more errors in the
data word read and leave the word uncorrected.
The output options to the interrupt and their re-setting are
as per the single bit error indication.

Page 19 Issue 1

421 IHB 11 0225

5.2.4

PIN ASS I GNt-1ENT

iwo edge connectors carry the interface signals to and from
the 'memory card. These edge connectors are designated Pl and
P2.
Pl is the Bus connector and P2 is the auxiliary connector used
when memory is operated in the data retention mode.
The pin assignment is tabulated below.

Page 20 Issue 1

421 jHB!10225

PIN ASSIGNMENT (PSM 512) CONNECTOR P1
NON COMPONENT SIDE

COMPONENT SIDE
PIN
1

3
5
7
9
11

13
15
17
19
21
23
25
27
29

SIGNAL

Ov

+5V
+5V

Ov
~

XAO':
Am

~

31

33
35
37
39
41
43

45
47
49
51

53
55

57
59
61
63
55
67
69
71
73
75

TNT 5
1Ni4

1Ni2
INT 0

ADR E
'AU1< C
~A

A1W 8
m6
Am{ 4
~2
~o

81
83
85

2

4.
5
8
10
12

14
15
18
20
22
24
26
2:
30
32
34
36
38
40
42
4A

46
48

~

INH 1
Am< 10
Am< 11
~

12
AOR 13
1'Ri7

w5

To 3
INT 1

~F

AUK D
~S

Am< 3
AOK 1

54

1ID'2

70
72

66
68

ma

74
75
78
80
82

Ov

Ov
TfW

56

"OAr 8
m6
'OAi 4

+5V
+5V

Ov

+5V
+5V

ATIk 9
AIm 7

Ni:i C
mA

Ov

SIGNAL

50
52

58
60
62
64

mE

77

79

PIN

84
86

~5

mF

]1ij 0
]AI 8
]Ai 9

1iAi 7

]7ij 5
]7ij 3
]Ail

Ov
+5V
+5V

Ov

Page 21 Issue 1

421,118/10225

PIN ASSIGNMENT (PSM 512) CONNECTOR P2

NON COMPONENT SIDE

COMPONENT SIDE

-PIN
1
3

PIN
Ov
+5V Aux

5

4
6

8
10

7
9
11

12
14

13
15

16·
18

17

19
21

Ov

23
25

20

22
24
26

27

28

29

30

31
33
35

32

37
39

38

40

~3

44

45
47
49

48

36

42

46

50

51

5i

59

MEMORY PROTECT
Ov

34

41

53
55

Ov
+5V Aux

2

AOiIT6

ADR14

52
54

56
58

60

ADm

ADR1S

Page 22 Issue 1

(~)

421 "HB /1 0225

5.3

ERROR DETECTION AND CORRECTION
The memory card is fitted with single bit error detection
and correction circuitry and double error detection circuitry.
Single bit error correction is automatic but "an error flag
may be connected to any of the bus interrupt lines by means of
Qn board links or to an on board LED.
Double or multiple error detection flag may be connected to
any of the bus interrupt lines by means of jumper links fitted
on the card.

5.4

POWER REQUIREMENTS
The memory operates from a single +5V rail.
current requirements are:-·
OP~TTNG

+5V

+

5%

3.0
3.5

A

The voltage and

CURRENT

STANDBY CURRENT

typi ca 1

2.5

max

3.0

typ;~al

A

max

When used in the da~a protect mode, a secure +sy supply
(i.e. battery supported PSU) shoul, be connected to the memory via
the auxiliary connector P2. This supply must meet the requests
for voltage and current stated above.
In the event of main poweY'" supply failure, the r:TI'mJ should
brought low to protect memory data.

5.5

be

MEMORY CAPACITIES
The memory may be depopulated to give the following capacities:64K 16 bits (128K bytes) and 128K 16 bits (256K bytes)
It should be noted that depopulated memories are continuous and
the starting and finish address should be set accordingly.

Page 23 -!-$sue

421/ HB/10225

TIMING REQUIREMENTS
READ OR WRITE CYCLE
MIN
TCY
TAS
TAH
TCP
TAC
TAACK
TDZ
TXACK
, TACKH
TDS
TDH

Note 1.

MAX

UNITS

Cycle Time
Address to Memory Start Set up
Address Hold Time Referenced to

500
50

nS

~

250

II

350

II

Command Pulse Width Referenced
to 'AAtR
Access Time
Conmand to 'AACK Delay
Command going positive to Read Data
High Impedance
Conmand to XACK Delay
AACK and XACK going pcsitive
reference command going positive
Write Data Set up Time
Write Data Hold Time Referenced
to AACK

..

350
100
0

0

400

.

100

II

II

Notes 1 &2
Note 1
Notes 1 & 3

..

350

II

100
390

II

Notes

,
I

&3

II

II

Note 1

The above timings assume there is no refresh cycle in operation when
command is sent.
In refresh cycle inhibit, t'he mR and "X'ArR
signals until the refresh cycle is complete. The Command, Address
and Data signals must be maintained until the memory responds with
~ and ~ and the timrngs referenced to AAtK observed .

.
'

Note 2.

When ~ is not used, the ~ Signal should be used to control the
Command. Address and Data signals.

Note 3.

The AArK and XACK signals are adjustable in 25 nS steps by means of
delay line taps so that their negative transition can be adjusted to
suit system requirements. Unless otherwise specified by the
customer the timing of 1Vi!1( and ~ wil 1 be within the 1imits
spec~fied above when the memory is despatched from the factory.

Note 4.

The board is also available using the 64K-2 part (150n$ access) the
access time can be reduced to 300nS and the cycle time to 470nS.

Page 24 Issue 1

421iHS/l022S

MJmC,

»m

VIH
VIL

r

VOL
VOH

VOl-!
VOL

~ iDZ

I

!

~

_ _ _ _--,I'---

-----------====

I

!

-I

Page 25 Issue 1

421 .lliB:/1 0225

TIMING WAVEFORMS

READ OR WRITE CYCLE

MEM BUSY
INTERNAL SIGNAL

\

\

f

DATA BUS

READ

'.

DATA BUS

~y:x

\

\

\

WRITE

I

\

I

f VALID

I

~

\
~

or

~

1

:Ii

VALID
I

and XACK delayed if

HIGH Z

!

XACK

~

I\)'1

HIGH :

i

'y

whi1e Refresh Cycle is in progress.

TYPICAL HANDSHAKE

OPERATIO~

Page (6 Issue 1

42l/HB/10225

6.

ENVIRONMENTAL SPECIFICATION

6. 1

OPERATING
The memory system will operate under the following condttions.
Temperature Range
Cooling Requirement

Airflow'of 100 metres per minute
parallel to the edge connectors

Damage may occur to the memory if run without cooling for a period
in excess of 30 minutes at maximum temperature.
Relative Humidity

Up to 95% without condensation

Thermal Shock

6.2

Altitude

- 300 to + 3000 M

Vibration

5 - 100Hz

Mechanical Shock

109 for 6 mill-seconds (half sine)
when mounted in a suitable racking
system

with 0.59 acceleration

STORAGE
The memory system may be stored or transported without damage
provided the environment is within the limitation shown bel~w:Temperature Range
Relative Humidity
Thenna1 Shock
Altitude
Vibration
Mechanical Shock

- 5SoC - + 85°C
o - 95% without condensation
! lOoe per minute
- 300m to + 16 ,ooOm

o - 500Hz, 29 acceleration
20g for 6 mill i-seconds (half sine)

Page 2J Issue 1

421/HB/10225

7.

QUALITY AND RELIABILITY

7.1

QUALITY PROGRAMME FOR DESIGN, MANUFACTURE AND TEST
All systems are manufac~ured directly in accordance with a
Quality Plan. The Qual;~ Plan monitors the systematic
evolution of system design and evaluation and production
activity.
By this means it is possible to ensure that all
systems despatched to the customer conform in all respects
to the requirements set out in this product specification.

7.2

RELIABILITY
In order to maximise system reliability, all areas of activity
are carefully controlled and monitored.
Design - All design activity is carried out to preaetermined
rules, which includes component derating, stress, reliability and
maintainability analysis.
Qualification - Each design is rigorously tested to ensure
conformance with the specified performance and environmental
requirements.
Pr.ocurement - Components are carefully selected and obtained only
from approved suppliers.
Manufacturing - Performed against planned work instructions and
firm workmanship standards.
Test - All testing is performed against defined test specifications
and the. results recorded and retained.
Thorough screening tests (burn-in) are applied to all production,
thereby ensuring that all manufacturing defects are detected and
corrected at the earliest opportunity.

Page 28 Issue 1

421/ Hatl 0225

7.3

MEAN TIME BETWEEN FAILURES
The calculated mean time between failure (MTBF) for the memory
is greater than 200.000 hoursA The component failure rates
used in this calculation have been derived from MIL STO 217B.
British Post Office publications, manufacturers published data
and in-house sources.

Page 29 Issue 1

421/HB/10225

8.

MAINTENANCE
No routine maintenance is necessary on the PSM 512 Memory Card.
However it is advisable to maintain a preventable maintenance
programme to give a maximum operating efficiency, this includes:(a)

Periodic checking of the Memory EDC·line should be
carried out while reading from the whole memory to
check that no memory device has failed and is being
continually corrected as this will reduce reliability.

(b)

A check that the operating volt~ge is within the limits
of the specification, ie. 5V ~ 5%.

(c)

Also check airflow is adequate, clean and replace air
filters as necessary.

Page 30 Issue 1

421/HB/10225

9.

BOARD SET UP

9.. 1

Interrupt
The memory provides an interrupt when either an un-correctable
error (double bit or multi-bit) is detected or when a Single
bit corrected error has occurred.
The un-correctable error interrupt may be'connected to either
the power fail line ~ to one of eight interrupt lines.
The correctable error interrupt may be connected to one of eight
interrupt lines.
Either of the interrupts may also be connected to the LED fitted
to the front of the card.
Figure 1 illustrates the different possibilities.
Interrupt is cleared on the next memory "'rite cycl e.
On power up due to the random data held in the RAMS, errors and
consequently interrupts will occur if attempts are made to read
data from the menory. The user must therefore write data to all
address locations after power up, before reading data from the
memory. Writing may be in 8 bit bytes or ~6 bit words as the
interrupt circuitry is enabled by the first read command to the
memory after power-up. If the memory is used in Data Retention
option this condition does not apply (see Section ~.~)

Page 31 Issue 1

421/HB/10225
TRISTATE

FOR 421 /MB/l 0226/ ALL VARIANTS ISSUE 3 ONWARDS
,..----,0

SINGLE

~_ _---i~RIVER~

ERROR--~--'

CONNECTOR P2

PF tNT

o
elKl 0

elK~

OlK3 0

-E~::u'"---'
lKl

MULTI ERROR

u-____

~

__- -__

~-

.b

«(

OlK4

._·...,:1--:..1........ elKS
IeSl

[K3~

TO LED
CONNECTOR Pl

?lK3P-,-

a

0-- INT 1

j

b-

t:~::

/9.

6/

lK6 '0

LK3

INTERRUPT LINKS
P.C.B. COMPONENT SIDE

J

lK3

INT 4

'b-

00 5
I LK2~ !Nt 6

~LK2e,:_
INTERRUPT CIRCUIT
Links LK2 and LKS fitted on shipment •
• Link LKl fitted'connects Multi-error to LED Indicator.
Link LK2 fitted connects Single-error to LED Indicator.
It is not permissible to fit both LKl and LK2.
Link LKJ fitted connects

~~lti-error

to Power Fail Interrupt

L~ne.

Link LK4 fitted connects Single-error to Power Fail Interrupt Line.
If neither LK3 o~.L~4 are fitted fit LK7 to hold PF iNT high.
Orily fit one of the following LKJ, 4, 7.
Link 5 fitted

INT

e

connec~Multi-error

to Interrupt Bus.

Link 6 fitted connects Single-error to Interrupt Bus.
Do not fit both LKS and LK6.

FIGURE 1:

INTERRUPT FACILITIES
Page

32 Issue 1

INT 7

42l/HB/10225

9.2

Memory Mapping
The user has two memory map options dependent upon the address
range used.

9.2.1·· Address Range 1 Megabyte (Multibus addresses ADRO - ADR13)
Two four bit comparators are used to set the start and finish
address of the memory. Multibus addresses ADR10, ADRll, ADR12
and ADR13 are fed to one set of the comparator inputs, the other
set being controlled by dual-in-line switch SW1 . . The start and
finish addresses are thus set in 64K qyte steps. The circuitry
is shown below.

~ ~

>

ADR10
ADRll
ADR12
ADR13

1

SWl
f~, aN
I
I

I

j

I

&.:'....

A>8

I

I

II

!

FInISH ADDRESS

> ~

I

i~
I

-I

I

:2:1

'-I

I

i

A<:'S

OV

SV

!__..,DI---e.e.- MEMORY SELECT

SWl

~.~

START ADDRESS

OV

Thefintsh address is determined by switch positions 2, 3, 6 and
8.
The start address is detennined by switch positions 1, 4, 5 and 7.
Table 1 shows the switch settings for the start address, and
Table 2 the switch settings for the finish address. Table 3 shows
the switch settings for a 5l2K by~e memory with a 1 megabyte field.
In the tables a nc" indicates the switch ;s closed, non indicates·
open.
Page 33 Issue 1

421/HB/~J225

START ADDRESS HEX ADDRESS
SYTES

SWITCH 1 POSITIONS

MUL TISUS ADDRESS
~ ~

A1lRT2 PJmT3

7

5

4

1

960K

FOOOO

L

L

L

L

C

C

C

C

896K

EOOOO

H

L

L

L

a

C

C

832K

00000

L

H

L

L

C

768K

COOOO

H

H

L

L

a

c
a
a

c
c

704K

BooOO

L

L

H

L

C

C

640K

AOOOO.

H

L

H

·L

a

c

576K

90000

L

H

H

L

C

0

c
c
a
a
a

512K

80000

H

H

H

L

0

0

0

C

448K

70000

L

L

L

H

C

C

C

384K

60000

H

L

L

H

0

C

C

a
a

320K

50000

L

H

L

H

C

0

C

0

253K

40000

H

H

L

H

a

a

c

a

192K

30000

L

L

H

H

C

C

0

0

128K

20000

H

L

H

H

0

C

a

64K

10000

L

H

H

H

C

0

OK

00000

H

H

H

H

a

0

a
a
a

C

c
c

0

0

TABLE 1: START ADDRESS

Page 34 Issue 1

I

421/HB/10225

MUL TISUS ADDRESS
SWITCH 1 POSITIONS
ADDRESS HEX ADDRESS
BYTES
Arnrnl Amm ~ ADm 8
6
3
2

~INISH

lO24K

FFFFF

L

L

L

L

C

C

C

C

960K

EFFFF

H

L

L

L'

0

C

C

C

896K

DFFFF

L

H

L

L

C

a

c

C

832K

CFFFF

H

H

L

L

0

0

c

C

768K

BFFFF

L

L

H

L

C

C

a

c

704K

AFFFF

H

L

H

L

0

C

0

C

640K

9FFFF

L

H

H

L

C

0

0

C

576K

8FFFF

H

H

H

L

0

0

0

C

C

C

0

I

512K

7FFFF

L

L

L

H

, C

448K

6FFFF

H

L

L

H

0

C

C

0

384K

SFFFF

L

H

L

H

C

0

,.
'"

0

320K

4FFFF

H

H

L

H

0

0

c

0

256K

3FFFF

L

L

H

H

C

C

0

0

192K

2FFFF

H

L

H

H

0

C

0

0

128K

lFFFF

L

H

H

H

C

0

0

0

64K

OFFFF

H

H

H

H

0

0

0

0

•

TABLE 2: FINISH ADDRESS

Page

35 Issue 1

I

421/HB/10225

MEMORY MAP
BYTES

o-

SWITCH 1 POSITION

HEX ADDRESS
7

5

4

1

8

6

3

2

512K

00OOO-7FFFF

0

0

0

0

C

C

C

0

64K - 576K

10000-SFFFF

C

0

0

0

0

0

0

C

12SK - 640K

20000-9FFFF

0

C

0

a

c

0

C

192K - 704K

C

0

0

0

0

c

2S6K - 768K

30000-AFFFF . C
40000-BFFFF
0

a
c

0

C

0

C

C

0

C

320K - 832K

50000-CFFFF

C

0

C

0

0

0

C

C

384K - 896K

60000-DFFFF

0

C

C

0

C

0

C

C

448K - 960K

70000-EFFFF

C

C

C

0

0

C

C

512K -1024K

80000-FFFFF

0

c

C

c
c

c

C

,

"~

0
0
START ADDRESS

TABLE 3:

FINISH ADDRESS

TYPICAL MEMORY MAPPING

FFFFF
FOOOO
EOOOO
00000
COOOO
BOOOO

~FINISH

ADDRESS

AOOOO

90000
80000
70000
60000
50000
40000
30000

<:

START ADDRESS

20000
10000

00000
TYPICAL MEMORY to1AP
Page 36. Issue 1

421/HB/10225

It should be noted that the start, finish address technique used
on the PSM512 memory allows areas at the top and bottom of the
memory range to be inhibited by using Tables 1 and 2.
In the
example shown above, if the area addressed by HEX 30000-3FFFF was
required for PROM, then the starting address would be altered to
4060. Th.;s feature is particularly useful when two PSM5l2
memories are occupying the whole address range of the processor.
Similarly depopulated memories can be mapped as desired.

Page 37 Issue 1

421/HB/10225

9.2.2 . Address Range , 6 Megabytes .
Recently the Intel Mu1tibus address range was extended to
16 megabytes with the additional four addresses ~ - ~
connected to the auxi1 iary connector P2 Pins 55, 56,.57 and 58.
To operate in this configuration it is necessary to cut and
strap as shawn in Figure 2.
This modification reconfigures the comparator circuitry as
shown below

.

~

I

I

ADR14----ADR15-ADR16-ADR17--

t f
!

SV

? ,
,

I

5
I

i

I

11.

I

J

•

A=

SWI

OV

7 ~

~
=D-

MEMORY SELECT

r • • • SV

ii
1---+-!----w"'O:.~
~t

ADRl
ADRll
ADR12
ADRl

SWl

OV

This allows the melOOry to be al located to 1 megabyte of the
address field and to occupy the top or bottom addresses of the
1 megabyte.

Page 3S-Is5ue 1

421/HB/l0225

Table 4 shows the settings of switch SWl to map the memory
to a 1 megabyte block and Table 5 shows the allocation of the
memory to the top or bottom of the 1 megabyte block. Note
that in this configuration the memory ~ reside in the top
or bottom 5l2K bytes, it cannot straddle the 5l2K boundary.
,

When allocated to the bottom of the 1 megabyte block, the top
address limit is governed by the A < B output of the comparator so
that the upper' address 1imi t can be changed by SWl enab 1i ng PROM to
be allocated address space at the top of the memories range or the
use of depopulated memory. When allocated to the top of the
1 megabyte block, the starting address is governed by the A > B
output so that the PROM could be allocated address space at the
bottom of the memories range.

Page 39 Issue 1

421/HB/10225

MEMORY ADDRES~
BYTES

SWITCH 1 POSITION

MULTIBUS ADDRESS

HEX ADDRESS

1'JlR14 AlmlS Alm16 ADR17

7

5

4

1

-

1M joOOOOO-OFFFFF

H

H

H

H

0

0

0

0

-

2M 100000-1FFFFF

L

H

H

H

C

0

0

0

3M 200000-2FFFFF

H

L

H

H

a

C

0

0

~OOOOO-3FFFFF

L

L

H

H

C

C

0

·0

5M 400000-4FFFFF

H

H

L

H

0

0

C

0

6M 500000-SFFFFF

L

H

L

H

C

0

C

0

7M 600000-6FFFFF

H

L

L

H

0

C

C

0

7M

-

SH 700000-7FFFFF

L

L

L

H

C

C

C

0

SM

-

9M \SOOOOO-SFFFFF

H

H

H

L

0

0

0

C

9M

- 10M ~00000-9FFFFF

L

H

H

L

C

0

0

C

10M - 11M jAOOOOO-AFFFFF

H

L

H

L

0

C

0

C

11 M - 12M BOOOOO-BFFFFF .

L

L

H

L

C

C

0

C

12M - 13M COOOOO-CFFFFF

H

H

L

L

0

0

c

C

13M - 14M DOOOOO-DFFFFF

L

H

L

L

C

0

C

C

14M - 15M EOOOOO-EFFFFF

H

L

L

L

0

C

C

C

15M - 16M FOOOOO-FFFFFF

L

L

L

L

C

C

C

C

0

1M
2M

3M
4M
SM

6M

4M

TABLE 4:

16 MEGABYTE MEMORY MAP

Page

40

Issue

1

II

421/HB/10225

MEMORY ADDRESS
BYTES

HEX ADDRESS

SWITCH 1 POSITION
8

6

3

,2

XOOOOO - X7FFFF

C

C

C

0

XOOOOO - X6FFFF

O.

C

C

0

384K

XOOOOO - X5FFFF

C

0

C

0

- 320K

XOOOOO - X4FFFF

0

0

C

0

256K

XOOOOO - X3FFFF

C

C

0

0

192K

XOOOOO - X2FFFF

0

C

0

0

128K

XOOOOO - X1FFFF

C

0

0

0

64K

XOOOOO - XOFFFF

0

X80000 - XFFFFF

0

a
a

0

512K - 1024K

a
a

c

576K - 1024K

X90000 - XFFFF

C

0

0

C

640K - 1024K

XAOOOO - XFFFF

a

c

0

C

704K - 1024K

XBOOOO - XFFFF

C

C

0

C

768K - 1024K

XCOOOO - XFFFF

0

0

c

C

832K - 1024K

XDOOO - XFFFF

C

0

C

C

896K - 1024K

XEOOOO - XFFFF

0

C

C

C

960K - lO24K

XFOOOO - XFFFF

C

C

C

C

0
0
0
0
0
0
0
0

- 512K
- 448K
-

-

TABLE 5: MEMORY WITHIN 1 MEGABYTE FIELD

Page 41 I.ssue 1

42l/HB/10225

FOR 42l/MB/10226jALL VARIANTS ISSUE 3 ONWARDS
FIGURE 2

16 MEGABYTE MEMORY MAPPING

Remove Links LK13, 16, 17, 18, 19 and 21.
Place Links in LK20, LK22.
Connect. Wires as follows:-

Connect wire from pin shown below on LK13 to AA on connector P2 Pin 57.
"

"

"

..

.

..

(I

II

II

II

II

11

"

"

" LK16 to Y "

"

P2 Pin 58 .

..

..

II

LK17 to Z ..

"

P2 Pin 55.

"

..

"

P2 Pin 56.

" LK18 to

X

"

To configure 512K to the lower half of the 1 megabyte leave in Link LK15.
To configure 512K to the top half of the 1 megabyte remove LK15 and put
in LK14.

Page 42 Issue 1

42l/HB/10225

FOR 421/MB/10226/ALL VARIANTS ISSUE 3 ONWARDS
9.3

Refresh
Jumper link LK23, LK38, LK39 control refresh circuitry.
For on board refresh only LK23, LK38 are in and LK39 removed.
For external refresh control only LK39, is in aftdLK23, LK38 removed.
For external refresh control unless the line is held low for more
than 15 pS whereupon the on board refresh circuitry takes over, this
is achieved by LK23, LK39 being in with LK38 removed.

9.4

Data Retention
If it is intended to use the anxiliary power supply for data
retention purposes, the following action is necessary:Remove wire links LK24, LK25 and wire link LK40.

9.5

Miscellaneous

9.5.1

~

Option

Jumper link LK27 connects ~ to Multibus Pl connector Pin 23 if
this facility is not required, remove jumper link LK12.

9.5.2

Bus Priority
Although the memory cannot act as a Bus Master, the facility exists
on the memory card to short BPRO to BPRIN by inserting link LK26.
This enables the memory card, when plugged into a system with serial
priority, to be positioned anywhere with the chassis.

Page 43 Issue 1

421/HB/10225

10.

SYSTEM DESCRIPTION
The Plessey PSM 512 Memory Card is a random access semiconductor
memory using 64K dynamic RAMS with single bit error correction
and double bit detection.
The Memory may be split up into six main $ections.
10.1
10.2
10.3
10.4
10.5
10.6

10.1

Memory Array
Address Manipulation
Refresh Logi c
Data Control
Timing Control
Error Detection and Correction

MEr40RY ARRAY
The memory array consists of 4 rows of 22 dynamic RAMS (as shown
in logic drawing sheet 2).
Each ROW containing 16 data RAMS and 6 EDC ,RAMS. These are all
driven with the same command signals of RAS, CAS, WE and address
and each column (containing 4 RAMS) has command Data In and Data
Out signals to complete the array.

Page 44 Issue 1

421/HB/10225

10.1.1

THE DYNAMIC RAM
The memory is fitted with 64K x 1 dynamic RAMS.
The storage cells within the RAM are matrixed in rows and
colu~with a cell being selected by the row and column
address being multiplied onto the device by means of the
falling edge of Row Address Strobe (RAS) or Column Address
Strobe (CAS) respectively. Data on the device Data In line
may be written into the selected cell by bringing the Write
Enable line (it) low when RAS and CAS are both low. Data Read
from the selected cell is presented on the Data Out line at
access time and remains valid until ~ returns to the high
state at which time the Data Out lines revert to high impedance
state.
The PSM 512 board permanently runs on a Read - Modify - Write
Cycle.
In this cycle the row and column addresses are strobed in and
the selected cel1·s data is latched onto the Data Out line at
access, this remains there until ~ goes high (as in a normal
read cycle) but also during the same cycle new data on the Data
. In line is written in by allowing it to go low while ~ and
~ are still low.
Thus enabling a Read and a Write to be
achieved on one cell location in one cycle.
The only other cycle used is a Refresh cycle which is carried
out by means of a ~ only cycle which is required to do 128
cycles every two milliseconds.

Page 45 Issue 1

421/HB/10225

10.2

ADDRESS MULTIPLYING, MEMORY SELECT

AND RAS DECODE

Address AO is used in conjunction with Byte Enable (BHEN) to
determine whether the memory is operating in 16 bit word of
256K or an a bit byte of 512K. This is done by using ]RtN
and AO to control the data being driven onto the RAM or
controlling the data read out of the RAM to the output bus.
The next 16 addresses (Ai - A10) form the multiplexed row and
column addresses which are driven onto the RAM where they are.
latched to form a cell selection. The timing of the
multiplexer is contrcl1ed by a signa1.called MUX unless the
memory is doing a refresh cycle whereupon the refresh address
is driven onto the RAM address lines.
Address All and A12 are fed into a two to four line decoder to
form a row select which determines which row of RAMS receives
a ~.
Addresses A10 - A13 are used in two hour bit magnitude comparators
to determine the area in which the memory is mapped and therefore
selected. One comparator is set with A > B and the other with
A < B where the A input is the address with the B input switchable
high or low via switches. Therefore the memory is only selected
when A > B on Comparator I (Iella) and A < B on Comparator II
(ICl19); for further"information see the memory mapping section.

Page 46 Issue 1

421/HB/10225

10.3

REFRESH LOGIC
Dynamic RAMS require all th~re rows to be addressed every 2 mS
and as there are 128 rows this means for a distributed refresh
lone row is to be refreshed every 15 ~ Sec. if data is not to be
lost.
This can be achieved in one of three ways.
(1)

Leave control of refresh to the on board timer and refresh
arbitration Logic with External Refresh signal (EXT.REF)
on Pl/77 disconnected.
This will result in a distributed refresh cycle every 15 ~S
controlled by the LS123 which makes up the timer, this then
clocks a D type latch which sends out a Refresh Request
(REF REO) and goes into a latch the other side of which is
Memory Request (M REO)}, so dependent on whether REF RFO or
MREO arrives first depends on whether a refresh cycle is
completed before the memory cycle or after it. At the end of
the RAS only refresh cycle a counter is clocked which increments
the refresh address before releasing Memory Busy to allow
another cycle.

(2)

This gives the driver of the board control of refresh as long
as the board gets a refresh at least once every 15 ~S otherwise
the board initiates a refresh cycle.
This is achieved by connecting EXT. REF. into Pin 1 of It 109
of LS123 and Pin 13 of- r~~_!~~:.the LS32 to clock REF REO; under
these conditions EXT REF is held normally low, going high to
initiate a refresh but if the EXT.REF has been low for 15 ~Sec.,
then the board will initiate its own.

Page 47 Issue 1

42l/HB/i0225

(3)

This totally hands over refresh control of the board to
the EXT.REF. signal with I~·'.~f Pin 1 held high and disables
the timing circuit.
Then by connecting EXT.REF. into Iel11 Pin 13 means that on
each rising edge of EXT.REF. initiates a refresh cycle and
counts up the refresh addresses so long as there are 128
cycles per 2 mS no data loss will occur.

Page 48 Issue 1

421/HB/10225

10.4 DATA CONTROL
When the memory receives a command signal such as MRDC or MWTC it
always initiates the same Read Modify Write cycle, the only difference
is in the data control, fo~ instance in a 16 bit read cycle the data
from the RAMS (EDC and data) passes through the Error Detection and
correction (EDC) device where it is corrected and is passed out onto
the bus, it is also turned round and written back into the memory
(16 bit), ie. on a read cycle corrected data is written back into the
read 1ocati on •
During a write cycle data is still read -out of the RAMS but is not
allowed out on the bus and the new write data passes into the EDC
device which is in the write mode and therefore generates new EDC
data and passes all the data through to the RAMS to be written into
on the write part of the cycle.
On an (8 bit) or byte read which is controlled by AO and ]H!N where
BHEN is high then AO controls which 8 bits of the memory is read or
written to.
For example in a byte read the whole word is read as a 16 bit read
but this time only 8 bits are allowed out either straight out for
Data 0 - 7 or byte swapped from 8 - 15 into Data 0 - 7 output.
However for a- byte write the memory reads the 16 bit word with EDC
check bits and corrects it, then one EDC device is put into the read
mode and the other with 'the new 8 bits of write data on its input
into the write mode. Then the new word consisting of 8 bits of read
corrected data and 8 bits of new write data generate the 6 EDC
check but data 'and the whole word is written into the memory thus
completing the cycle.

Page 49 Issue 1

421/HB/10225

10.5 TIMING CONTROL
The on board timing is controlled via delay lines, this is used to
generate the command signal for the RAMls such as RAS, CAS, WE and

MDX.
It is also used to generate the output signals such as ~, ~
and is used to strobe the multi error and single error line to
determine whether a single or multibit error has occurred. The·
delay lines are either driven by'a command signal, Readior Write or
by a Refresh cycle with the Busy timer and refresh arbitration logic
making sure that only one signal passes,down the line at a time.

Page 50 Issue 1

421/HB/1022S

10.6 ERROR DETECTION AND CORRECTION
This is controlled by two Fujitsu MB14l2A, each of which control
8 bits of data but are interconnected to form a 6 bit check bit
output for the 16 bit word.
Each device has separate Read (RDO-7) and Write (WDO-7) data in as
well as corrected data (00-7) out and this is controlled by means
of a single line 5TB. If 5TB is a logic low the chip is in the
read function and data and check bit (5l0-1S) are read in and
corrected data and syndrone (50-S) outputed as well as indication
whether a single bit error has occurred,]!T or an error has occurred
in the check bit]Ve. (The decode of the syndrone is shown in
Appendix 1).
If the 5TB is a logic high the chip is in the write mode and the
data on the write input (WDO-7) is outputed onto the data out
(00-7) along with the check bit output (CO 0-5). The devices
together correct any single bit error in data or EDC bits giving
indication that a single bit error has occurred (by means of a small.
amount of external logic).
It is also able to detect any double
bit error but does not attempt to correct them.
(An indication of
which memory device is failing is given in the syndrone data,for
information on how to decode this see fault finding).

Page 51 Issue 1

421/HB/10225

11.

FAULT FINDING
The Plessey P5M512 memory is designed as a plug in item and
faulty modules should be returned to P1essey for repair.
However in order to aid the turn round of repaired modules an
indication of the fault symptom is invaluable, especially when
the fault is intermittent or marginal.
In order to aid diagnosis, logic diagrams are provided in the
handbook together with a description of the memory system, and the
following syndrone decoding chart will help in detecting any
single bit errors.
The syndrone outputs appear on ICll2 as listed below and this is
only valid on the read half of a cycle and not on a refresh cycle,
a useful strobe when the syndrone is valid is on ICll1 Pin 8.

so is on ICl12/2
51
52
53
54
55

is
is
is
is
is

on
on
on
on
on

IC112/l
IC112/13
ICl12/3
ICll2/5
ICl12/4

P:age 52 Issue 1

421/ HB/ 10225

DATA
BIT

SO

Sl

S2

S3

S4

S5

ERROR

1

1
0
0

1
0

1

1
1
1

a

a

1

0

0

0

0

1

0

1

4

1

1

0

0

0

1
0
1
1
1
1

NONE
0
1

2
3

1
1
0
1

5

0

1

0

0

1

1

5

6
7
8

1

0

0

0

1

1

0

0

0

0

0

1

1

1

0

0

1

0

6
7
8

9

0

1

0

1

0

9

10

1
0

0

0

1

0

10

a

1

1
1
1

1

0

11

1
1
0

0

1

0

0

12

1

1

0

0

13

1
1

0

0

0

1
0

0

0

14
15

0

1

11
12
13
14
15

1
0
1
0

1

2
3
4

~

DATA BITS

SYNDROME

BIT

0

0

1

1

1

1

1

16

1
2
3
4

1

0

1

1

1

0

1

1
1

0

1
1

1
1
1

17

1
1

1
1

18
19

1

0

5

1

1

1

1

1
0

20
21

1

1
1

EDC BITS

The error column gives the RAM ROW numbered from right to left
looking. from :the connector, and any' other €OO1b·ination indicates a
multiple error.

Page 53 Issue 1

421jHBjl0225

12.

INSTALLATION AND OPERATION
This sections unpacking, installation and operating instructions
for the Plessey PSM512 memory.

12.1

RECEIVING INSPECTION
The PSMS12 memory is fully assembled and tested prior to shipment
from the factbry. The units are individually packed in accordance
with standard practices for electronic equipment. Every
precaution is taken to ensure that each,system leaving the factory
is complete and ready for installation. However it is recommended
that units be inspected upon receipt for shipping damage.

12.2 INSTALLATION
The memory is designed for mounting in a card cage and to plug into
printed circuit board connectors. The interface connector pin
assignment is shown on Pages 21·and 22~ The PSM5l2 has a number of
user options available, for details see Section 9 of this document.
Prior to installation in the card cage check that the appropriate
options have been set up.

12.3 POWER REQUIREMENT
The memory only has one power rail of +SV, this should be ~ 5% and
a check should be made that the board pin assignment coincides with
the backplane.

Page 54 Issue 1

421/HB/l0225

APPENDIX 1

APPLIES TO 421/MB/10226/ALL VARIANTS

ISSUE 2 ONLY

Page 55 Issue 1

421/HB/10225
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---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:09:24 09:55:47-08:00
Modify Date                     : 2013:09:24 10:18:11-07:00
Metadata Date                   : 2013:09:24 10:18:11-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:29df5272-e602-c54b-801d-06ab7e67a10b
Instance ID                     : uuid:de5e7968-134a-ac4d-954f-22fb613ca6af
Page Layout                     : SinglePage
Page Mode                       : UseOutlines
Page Count                      : 62

EXIF Metadata provided by EXIF.tools