Xilinx PlanAhead User Guide Plan Ahead
User Manual:
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- Software Manuals
- PlanAhead User Guide
- About This Guide
- Table of Contents
- Chapter 1 Introduction
- About PlanAhead Software
- Using PlanAhead
- Project Creation and Management
- RTL and IP Design
- Synthesis and Implementation
- Design Analysis and Constraints Definition
- Pin Planning
- Floorplanning
- Programming and Debugging Designs and ChipScope Integration
- Hierarchical Design, Design Preservation, and Partial Configuration
- Tcl Commands and Batch Scripting
- Using PlanAhead with the ISE Project Navigator Environment
- PlanAhead Menu and Command Overview
- Input and Output Files
- PlanAhead Terminology
- Accessing Updates
- Configuring Multiple Linux Hosts
- Chapter 2 Understanding the PlanAhead Design Flow
- Chapter 3 Working with Projects
- Understanding PlanAhead Project Types
- Creating a New Project
- Using the Create New Project Wizard
- Opening an Existing Project
- Opening Multiple Projects
- Saving a Project
- Closing a Project
- Managing Project Sources
- Adding and Managing Constraints
- Configuring Project Settings
- Understanding the Project Summary
- Determining Project Status
- Chapter 4 Using the Viewing Environment
- Understanding the Viewing Environment
- Using the Main Viewing Area
- Using the Flow Navigator
- Using the Compilation Message Area
- Using Common PlanAhead Views
- Using the Sources View
- Using the RTL Editor
- Using the Device View
- Using the Package View
- Using the Schematic View
- Schematic View Toolbar Buttons
- Using the Properties View
- Using the Netlist View
- Using the Hierarchy View
- Using the I/O Ports View
- Using the Package Pins View
- Using the Design Runs View
- Working with Views
- Selecting Objects
- Using the Select Main Menu Commands
- Selecting Multiple Objects
- Using the Select Area Command
- Selecting Primitive Parent Modules
- Using the Selection View
- Fitting the Display to Show Selected Objects
- Setting Selection Rules
- Setting Object Selections in the Workspace Views
- Highlighting Selected Objects
- Marking Selected Objects
- Configuring the Viewing Environment
- Customizing PlanAhead Display Options
- Setting General View Display Options
- Setting Device View Display Options
- Setting Package View Display Options
- Setting the Device View Bundle Nets Display Options
- Configuring Schematic Slack and Fanout Display Options
- Adjusting Display using Toolbar Commands
- Saving Custom Display Settings
- Selecting a Theme
- Moving Views
- Creating Custom View Layouts
- Restoring a View Layout
- Customizing PlanAhead Display Options
- Configuring PlanAhead Behavior
- Chapter 5 RTL and IP Design
- Introduction
- Managing the Design Source Files
- Editing RTL Source Files
- Configuring IP using the CORE Generator
- Elaborating and Analyzing the RTL Design
- RTL Rules: Power and Performance
- Chapter 6 Synthesizing the Design
- Chapter 7 Netlist Analysis and Constraint Definition
- Overview
- Using the Netlist Design
- Viewing and Reporting Resource Statistics
- Exploring the Logic
- Inserting ChipScope Debug Cores
- Defining Timing Constraints
- Running Timing Analysis
- Using Slack Histograms
- Defining Physical Constraints
- Running the Design Rule Checker (DRC)
- Chapter 8 I/O Pin Planning
- I/O Planning Overview
- Using the I/O Planner
- Viewing Device Resources
- Defining Alternate Compatible Parts
- Setting Device Configuration Modes
- Defining and Configuring I/O Ports
- Disabling or Enabling Interactive Design Rule Checking
- Placing I/O Ports
- Validating I/O and Clock Logic Placement
- Removing I/O Placement Constraints
- Exporting I/O Pin and Package Data
- Chapter 9 Implementing the Design
- Chapter 10 Analyzing Implementation Results
- Chapter 11 Floorplanning the Design
- Floorplanning Strategy Overview
- Working with Pblocks
- Configuring Pblocks
- Setting Pblock Logic Type Ranges
- Assigning Logic to Pblocks
- Moving and Resizing Pblocks
- Using Resource Utilization Statistics to Shape Pblocks
- Placing Pblocks Based on Connectivity
- Displaying Bundle Net Properties
- Using Non-Rectangular Pblocks
- Removing a Pblock Rectangle
- Setting Attributes for Pblocks
- Renaming a Pblock
- Deleting a Pblock
- Running the Automatic Pblock Placer
- Working with Placement LOC Constraints
- Understanding Fixed and Unfixed Placement Constraints
- Understanding Site and BEL Level Constraints
- Assigning Site Location Placement Constraints (LOCs)
- Assigning BEL Placement Constraints (BELs)
- Adjusting the Visibility of Placement Constraints
- Moving Placement Constraints
- Deleting Selected Placement Constraints
- Selectively Clearing Placement Constraints
- Moving Pblocks with Placement Constraints Assigned
- Locking Placement During ISE Implementation
- Setting Placement Prohibit Constraints
- Chapter 12 Programming and Debugging the Design
- Generating Bitstream Files
- Debugging the Design with ChipScope
- Overview of ChipScope Integration in PlanAhead
- Requirements and Limitations When Using Core Insertion Flow
- Using the Core Insertion Flow
- Selecting Nets for Debug
- Using the ChipScope Wizard for Debug Core Insertion
- Using the ChipScope Window to Add and Customize Debug Cores
- Implementing the Design with the Debug Cores
- Launching ChipScope Pro Analyzer
- Launching FPGA Editor
- Launching iMPACT
- Chapter 13 Using Hierarchical Design Techniques
- Chapter 14 Tcl and Batch Scripting
- Chapter 15 Using PlanAhead With Project Navigator
- Appendix A: Menu and Toolbar Commands
- Appendix B: PlanAhead Input and Output Files
- Inputs to PlanAhead
- Outputs for Reports
- I/O Pin Assignment (CSV)
- I/O Pin Assignment (RTL - Verilog or VHDL)
- Log File (planAhead.log)
- Journal File (planAhead.jou)
- Error Log Files (planAhead_pidxxxx.debug & hs_err_pidxxxx.log)
- DRC Results (results_x_drc.txt)
- Timing Analysis Results (Excel file)
- Netlist Module, Pblock, and Clock Region Statistics Reports
- SSN Analysis Report
- WASSO Analysis Reports
- Outputs for Environment Defaults
- Outputs for Project Data
- Project Directory (<projectname>)
- Project File (<projectname>.ppr)
- Project Data Directory (<projectname>.data)
- Project Data - Netlist Subdirectory (netlist)
- Project Data - Constraint Set Subdirectories and Files (<constraint_set_name>)
- Project RTL Directory (<projectname>.srcs)
- Outputs for ISE Implementation
- ChipScope Core Netlists (.ngc)
- Constraint Files (.ucf)
- ISE Launch Scripts (jobx.bat/sh & runme.bat/sh & .<ISE_command>.rst)
- Appendix C: PlanAhead Terminology
- Appendix D: Installing Releases with XilinxNotify
- Appendix E: Configuring SSH Without Password Prompting