QM_CycloneV_5CEFA2F23_User_Manual(CoreBoard) V01 QM Cyclone V 5CEFA2F23 User Manual(Core Board)
User Manual:
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Page Count: 12
- 1. Introduction
- 2. Getting Started
- 2.2 QM_CycloneV_5CEFA2 Hardware Design
- 2.2.1 QM_CycloneV_5CEFA2 Power Supply
- 2.2.2 QM_CycloneV_5CEFA2 SDRAM Memory
- 2.2.3 QM_CycloneV_5CEFA2 SPI Boot
- 2.2.4 QM_CycloneV_5CEFA2 System Clock
- 2.2.1 QM_CycloneV_5CEFA2 JTAG Port
- 2.2.2 QM_CycloneV_5CEFA2 Power Supply
- 2.2.3 QM_CycloneV_5CEFA2 Extension IO
- 2.2.4 QM_CycloneV_5CEFA2 User LED
- 2.2.5 QM_CycloneV_5CEFA2 User Key
- 2.2 QM_CycloneV_5CEFA2 Hardware Design
- 3. Reference
- 4. Revision
QM_CycloneV_5CEFA2 Core Board-User Manual(Hardware)
CYCLONEV_5CEFA2 CORE BOARD
USER MANUAL
Preface
The QMTech® Cyclone V SDRAM Development Kit uses Altera(Intel) 5CEFA2F23 device to
demonstrate the industry's lowest system cost and power, along with performance levels that
make the device family ideal for differentiating your high-volume applications. You'll get up to
40% lower total power compared with the previous generation, efficient logic integration
capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM®-based
hard processor system (HPS).
QM_CycloneV_5CEFA2 Core Board User Manual-V01
Table of Contents
1. INTRODUCTION .................................................................................. 3
1.1 DOCUMENT SCOPE ..................................................................... 3
1.2 KIT OVERVIEW ........................................................................... 3
1.3 KIT TOP VIEW ........................................................................... 3
2. GETTING STARTED .............................................................................. 4
2.2 QM_CYCLONEV_5CEFA2 HARDWARE DESIGN ............................... 5
2.2.1 QM_CycloneV_5CEFA2 Power Supply ........................ 5
2.2.2 QM_CycloneV_5CEFA2 SDRAM Memory .................... 6
2.2.3 QM_CycloneV_5CEFA2 SPI Boot ................................. 6
2.2.4 QM_CycloneV_5CEFA2 System Clock ......................... 7
2.2.1 QM_CycloneV_5CEFA2 JTAG Port .............................. 7
2.2.2 QM_CycloneV_5CEFA2 Power Supply ........................ 8
2.2.3 QM_CycloneV_5CEFA2 Extension IO .......................... 9
2.2.4 QM_CycloneV_5CEFA2 User LED .............................. 10
2.2.5 QM_CycloneV_5CEFA2 User Key .............................. 10
3. REFERENCE........................................................................................ 11
4. REVISION .......................................................................................... 12
QM_CycloneV_5CEFA2 Core Board User Manual-V01
1. Introduction
1.1 Document Scope
This demo user manual introduces the QM_CycloneV_5CEFA2 core board and describes how to setup
the core board running with application software Altera Quartus II 15.1. Users may employee the on
board rich logic resource FPGA 5CEFA2F23I7N and large SDRAM memory MT48LC16M16 to implement
various applications. The core board also has 108 non-multiplexed FPGA IOs for extending customized
modules, such as UART module, CMOS/CCD camera module, LCD/HDMI/VGA display module etc.
1.2 Kit Overview
Below section lists the parameters of the QM_CycloneV_5CEFA2:
On-Board FPGA: 5CEFA2F23I7N;
On-Board FPGA external crystal frequency: 50MHz;
5CEFA2F23I7N has rich block RAM resource up to 1760Kb;
5CEFA2F23I7N has 25K Logic elements;
On-Board N25Q064 SPI Flash, 8M bytes for user configuration code;
On-Board 32MB Micron SDRAM, MT48LC16M16A2;
On-Board 3.3V power supply for FPGA by using MP2315 wide input range DC/DC;
QM_CycloneV_5CEFA2 core board has two 64p, 2.54mm pitch headers for extending user IOs. All
IOs are precisely designed with length matching;
QM_CycloneV_5CEFA2 core board has 3 user switches;
QM_CycloneV_5CEFA2 core board has 2 user LEDs;
QM_CycloneV_5CEFA2 core board has JTAG interface, by using 10p, 2.54mm pitch header;
QM_CycloneV_5CEFA2 core board PCB size is: 6.7cm x 8.4cm;
Default power source for core board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm;
1.3 Kit Top View
Figure 1-1. QM_CycloneV_5CEFA2 Top View
QM_CycloneV_5CEFA2 Core Board User Manual-V01
2. Getting Started
Below image shows the dimension of the QM_CycloneV_5CEFA2 core board: 67.1mm x 84.1mm. The
unit in below image is millimeter(mm).
Figure 2-1. QM_CycloneV_5CEFA2 Dimension
The QM_CycloneV_5CEFA2 core board tool chain consists of Altera Quartus II 15.1, Altera USB Blaster
cable, 5CEFA2F23 core board and 5V DC power supply. Below image shows the Altera Quartus II 15.1
development environment which could be downloaded from Altera(Intel) office website:
QM_CycloneV_5CEFA2 Core Board User Manual-V01
2.2 QM_CycloneV_5CEFA2 Hardware Design
2.2.1 QM_CycloneV_5CEFA2 Power Supply
The core board needs 5V DC input as power supply which could be directly injected from power header
or the 64P header U7/U8. Users may refer to the hardware schematic for the detailed design. The on
board LED D4 indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In
default status, all the FPGA banks IO power level is 3.3V because bank power supply is 3.3V.
Note: FPGA core supply 1.1V is regulated by On-Semi DC/DC chip NCP1529 which could output
maximum 1A current.
Figure 2-2. Power Supply for the FPGA
5CEFA2F23
U12J
,GND1,,,,,,
P2
,GND2,,,,,,
AB19
,GND3,,,,,,
AB14
,GND4,,,,,,
AB9
,GND5,,,,,,
AB2
,GND6,,,,,,
AB1
,GND7,,,,,,
AA11
,GND8,,,,,,
AA6
,GND9,,,,,,
AA4
,GND10,,,,,,
AA3
,GND11,,,,,,
Y18
,GND12,,,,,,
Y5
,GND13,,,,,,
Y2
,GND14,,,,,,
Y1
,GND15,,,,,,
W4
,GND16,,,,,,
W3
,GND17,,,,,,
V22
,GND18,,,,,,
V17
,GND19,,,,,,
V12
,GND20,,,,,,
V7
,GND21,,,,,,
V4
,GND22,,,,,,
V2
,GND23,,,,,,
V1
,GND24,,,,,,
U9
,GND25,,,,,,
U5
,GND26,,,,,,
U4
,GND27,,,,,,
U3
,GND28,,,,,,
T21
,GND29,,,,,,
T16
,GND30,,,,,,
T2
,GND31,,,,,,
T1
,GND32,,,,,,
R13
,GND33,,,,,,
R3
,GND34,,,,,,
P10
,GND35,,,,,,
P4
,GND36,,,,,,
P1
,GND37,,,,,,
N22
,GND38,,,,,,
N17
,GND39,,,,,,
N15
,GND40,,,,,,
N13
,GND41,,,,,,
N11
,GND42,,,,,,
N7
,GND43,,,,,,
N5
,GND44,,,,,,
N3
,GND45,,,,,,
M14
,GND46,,,,,,
M12
,GND47,,,,,,
M10
,GND48,,,,,,
M4
,GND49,,,,,,
M2
,GND50,,,,,,
M1
5CEFA2F23
U12K
,GND,1,,,,,
L21
,GND,2,,,,,
L15
,GND,3,,,,,
L13
,GND,4,,,,,
L11
,GND,5,,,,,
L5
,GND,6,,,,,
L3
,GND,7,,,,,
K14
,GND,8,,,,,
K12
,GND,9,,,,,
K10
,GND,10,,,,,
K8
,GND,11,,,,,
K4
,GND,12,,,,,
K2
,GND,13,,,,,
K1
,GND,14,,,,,
J20
,GND,15,,,,,
J15
,GND,16,,,,,
J5
,GND,17,,,,,
J3
,GND,18,,,,,
H22
,GND,19,,,,,
H12
,GND,20,,,,,
H7
,GND,21,,,,,
H4
,GND,22,,,,,
H3
,GND,23,,,,,
H2
,GND,24,,,,,
H1
,GND,25,,,,,
G19
,GND,26,,,,,
G9
,GND,27,,,,,
G4
,GND,28,,,,,
G3
,GND,29,,,,,
F16
,GND,30,,,,,
F6
,GND,31,,,,,
F5
,GND,32,,,,,
F2
,GND,33,,,,,
F1
,GND,34,,,,,
E13
,GND,35,,,,,
E4
,GND,36,,,,,
E3
,GND,37,,,,,
D20
,GND,38,,,,,
D10
,GND,39,,,,,
D5
,GND,40,,,,,
D2
,GND,41,,,,,
D1
,GND,42,,,,,
C17
,GND,43,,,,,
C4
,GND,44,,,,,
C3
,GND,45,,,,,
B14
,GND,46,,,,,
B9
,GND,47,,,,,
B2
,GND,48,,,,,
B1
,GND,49,,,,,
A21
,GND,50,,,,,
A11
5CEFA2F23
U12L
,VCC1,,,,,,
N4
,VCC2,,,,,,
P15
,VCC3,,,,,,
P13
,VCC4,,,,,,
P11
,VCC5,,,,,,
P3
,VCC6,,,,,,
N14
,VCC7,,,,,,
N12
,VCC8,,,,,,
N10
,VCC9,,,,,,
M15
,VCC10,,,,,,
M13
,VCC11,,,,,,
M11
,VCC12,,,,,,
L16
,VCC13,,,,,,
L14
,VCC14,,,,,,
L12
,VCC15,,,,,,
L10
,VCC16,,,,,,
L4
,VCC17,,,,,,
K15
,VCC18,,,,,,
K13
,VCC19,,,,,,
K11
,VCC20,,,,,,
K5
,VCC21,,,,,,
K3
,VCC22,,,,,,
J16
,VCC23,,,,,,
J14
,VCC24,,,,,,
J12
,VCC25,,,,,,
J10
,VCC26,,,,,,
J4
5CEFA2F23
U12M
,DNU1,,,,,,
B3
,DNU2,,,,,,
B4
,DNU3,,,,,,
E17
,DNU4,,,,,,
L9
5CEFA2F23
U12N
,VCCPGM1,,,,,,
V8
,VCCPGM2,,,,,,
R19
,VCCPGM3,,,,,,
F8
,VCCBAT,,,,,,
A3
5CEFA2F23
U12O
,VCCIO2A1,,,,,,
D4
,VCCIO2A2,,,,,,
Y4
,VCCIO2A3,,,,,,
R1
,VCCIO2A4,,,,,,
J1
,VCCIO3A1,,,,,,
T6
,VCCIO3A2,,,,,,
Y8
,VCCIO3B1,,,,,,
T11
,VCCIO3B2,,,,,,
Y13
,VCCIO3B3,,,,,,
W10
,VCCIO3B4,,,,,,
R8
,VCCIO4A1,,,,,,
U19
,VCCIO4A2,,,,,,
AA21
,VCCIO4A3,,,,,,
AA16
,VCCIO4A4,,,,,,
W20
,VCCIO4A5,,,,,,
W15
,VCCIO4A6,,,,,,
U14
,VCCIO5A1,,,,,,
P20
,VCCIO5A2,,,,,,
R18
,VCCIO5B1,,,,,,
M19
,VCCIO5B2,,,,,,
K18
,VCCIO7A1,,,,,,
A16
,VCCIO7A2,,,,,,
H17
,VCCIO7A3,,,,,,
G14
,VCCIO7A4,,,,,,
F21
,VCCIO7A5,,,,,,
F11
,VCCIO7A6,,,,,,
E18
,VCCIO7A7,,,,,,
D15
,VCCIO7A8,,,,,,
C22
,VCCIO7A9,,,,,,
C12
,VCCIO7A10,,,,,,
B19
,VCCIO8A1,,,,,,
A6
,VCCIO8A2,,,,,,
G7
,VCCIO8A3,,,,,,
E8
,VCCIO8A4,,,,,,
C7
5CEFA2F23
U12P
,VCCPD1A2A1,,,,,,
E1
,VCCPD1A2A2,,,,,,
R2
,VCCPD1A2A3,,,,,,
J2
,VCCPD3A,,,,,,
W6
,VCCPD3B4A1,,,,,,
W17
,VCCPD3B4A2,,,,,,
W14
,VCCPD3B4A3,,,,,,
W12
,VCCPD3B4A4,,,,,,
W11
,VCCPD5A,,,,,,
P21
,VCCPD5B1,,,,,,
N18
,VCCPD5B2,,,,,,
M17
,VCCPD7A8A1,,,,,,
D16
,VCCPD7A8A2,,,,,,
E11
,VCCPD7A8A3,,,,,,
D14
,VCCPD7A8A4,,,,,,
D8
,VCCPD7A8A5,,,,,,
C10
5CEFA2F23
U12R
,RREF_TL,,,,,,
A1
5CEFA2F23
U12Q
,NC1,,,,,,
Y6
,NC2,,,,,,
V11
,NC3,,,,,,
J22
,NC4,,,,,,
J21
,NC5,,,,,,
H21
,NC6,,,,,,
H20
,NC7,,,,,,
G22
,NC8,,,,,,
G21
,NC9,,,,,,
G20
,NC10,,,,,,
F22
,NC11,,,,,,
F20
,NC12,,,,,,
F19
,NC13,,,,,,
F18
,NC14,,,,,,
E22
,NC15,,,,,,
E21
,NC16,,,,,,
E20
,NC17,,,,,,
E19
,NC18,,,,,,
D22
,NC19,,,,,,
D21
,NC20,,,,,,
D19
,NC21,,,,,,
C21
,NC22,,,,,,
C20
,NC23,,,,,,
C19
,NC24,,,,,,
C18
,NC25,,,,,,
B22
,NC26,,,,,,
B21
,NC27,,,,,,
B20
,NC28,,,,,,
B18
,NC29,,,,,,
B17
,NC30,,,,,,
A22
,NC31,,,,,,
A20
,NC32,,,,,,
A19
,NC33,,,,,,
A18
,NC34,,,,,,
A17
5CEFA2F23
U12S
,VCCA_FPLL1,,,,,,
M3
,VCCA_FPLL2,,,,,,
T3
,VCCA_FPLL3,,,,,,
T5
,VCCA_FPLL4,,,,,,
F4
,VCCA_FPLL5,,,,,,
U18
,VCCA_FPLL6,,,,,,
H19
5CEFA2F23
U12T
,VCC_AUX1,,,,,,
E6
,VCC_AUX2,,,,,,
D11
,VCC_AUX3,,,,,,
D18
,VCC_AUX4,,,,,,
W18
,VCC_AUX5,,,,,,
W13
,VCC_AUX6,,,,,,
W7
R240 2.0K
2V5
2V5
2V5
3V3
1V1
3V3
3V3
QM_CycloneV_5CEFA2 Core Board User Manual-V01
2.2.2 QM_CycloneV_5CEFA2 SDRAM Memory
QM_CycloneV_5CEFA2 has on board 16bit width data bus, 32MB memory size MT48LC16M16 SDRAM
provided by Micron. Below image shows the detailed hardware design:
Figure 2-3. SDRAM
2.2.3 QM_CycloneV_5CEFA2 SPI Boot
QM_CycloneV_5CEFA2 boots from external SPI Flash, detailed hardware design is shown in below
figure. The SPI flash is using N25Q064 manufactured by Micron, with 64Mbit memory storage.
Note: The SPI Flash is designed with x1 mode.
Figure 2-4. SPI Flash
A[14..0] D[15..0]
C4
100NF C6
100NF
C87
100NF
C88
100NF
C9
100NF
MT48LC16M16A2
MN1
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15
DQMH
39
CAS
17
RAS
18
WE
16
CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
C3
100NF
3V3
256 M bit s
DQML
A8
A9
A14
CAS
SD_NCS0
A13
A6
A11
A12
DQMH
SDCLK0
A1
A4
SDWE
A3
A7
RAS
SDCKE0
D2
D4
A5
A2
A0
A10 D9
D14
D5
D12
D10
D7
D6
D0
D3
D15
D11
D13
D1
D8
SDCLK0
SDCKE0
DQMH
DQML
RAS
CAS
SDWE
SD_NCS0
U6
N25Q064A13ESE40F
nCE
1
HOLD 7
SO
2
VSS
4SI 5
SCK 6
WP
3
VDD 8
3V3
R248 1K
R249 1K
FPGA_NCSO
FPGA_ADSO
FPGA_DCLK
FPGA_DATA1
QM_CycloneV_5CEFA2 Core Board User Manual-V01
Below image shows the hardware configuration of MSEL[4:0]: 10011, in which way will make the FPGA boot
from Active Serial (x1 or x4) Standard Mode:
Figure 2-5. MSEL Settings
2.2.4 QM_CycloneV_5CEFA2 System Clock
The QM_CycloneV_5CEFA2 has system clock frequency 50MHz which is directly provided by external
crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/°c.
Below image shows the detailed hardware design:
Figure 2-6. 50MHz System Clock
2.2.1 QM_CycloneV_5CEFA2 JTAG Port
The on board JTAG port uses 10P 2.54mm pitch header which could be easily connected to Altera USB
blaster cable. Below image shows the hardware design of the JTAG port:
Figure 2-7. JTAG Port
J2
CONA_10P
1 2
3 4
5 6
7 8
910
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TCK
3V3
QM_CycloneV_5CEFA2 Core Board User Manual-V01
2.2.2 QM_CycloneV_5CEFA2 Power Supply
The core board’s 3.3V power supply is using high efficiency DC/DC chip MP2315 provided by MPS Inc.
The MP2315 supports wide voltage input range from 4.5V to 24V. In normal use case, 5V DC power
supply is suggested to be applied on the board. Below image shows the MP2315 hardware design:
Figure 2-8. MP2315 Hardware Design
The core board’s 2.5V and 1.1V FPGA core voltage power supply is using high efficiency DC/DC chip
NCP1529 provided by On-Semi Inc.
Figure 2-9. NCP1529 Hardware Design
+C58
47uF
+C81
47uF
REGULATED
5V O NLY
L6
4.7uH
C68
100nF
JP5
Power_Header_SMT
1
2
3
4
C82
100nF
VIN
R235 100K
R236
33K
C7 22pF
3V3
R237 75K
U11
MP2315
AAM 1
IN 2
SW
3
GND
4
BST
5
EN/SYNC 6
VCC 7
FB
8
C80 100nF
C5
100nF R238
20R
R239 33K
R10 100K
L3 4.7uH
1V1
C47
4.7uF
3V3
U5
NCP1529
GND
2
FB 5
EN
1
VIN
4SW 3C46
22pF
R21
100K
R26
120K
C71
4.7uF
2V5
L7 4.7uH
3V3
C72
4.7uF
U10
NCP1529
GND
2
FB 5
EN
1
VIN
4SW 3R226
75K C73
22pF
R227
23.7K
M
2V5
C56
4.7uF
M
1V1
QM_CycloneV_5CEFA2 Core Board User Manual-V01
2.2.3 QM_CycloneV_5CEFA2 Extension IO
The core board has two 64P 2.54mm pitch female headers which are used for extending user modules,
such as ADC/DAC module, audio/video module, ethernet module, etc.
Figure 2-10. Extension IO
U8
HDR_32X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
3V3 3V3
VIN VIN
VIN
3V3
VIN
3V3
U7
HDR_32X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
BANK_5B_M22
BANK_5B_L18
BANK_5B_M18
BANK_5B_M21
BANK_5B_N20
BANK_4A_AA18
BANK_4A_Y17
BANK_4A_AB18
BANK_5B_K22
BANK_5B_L17
BANK_4A_AA22
BANK_4A_AB21
BANK_4A_Y20
BANK_4A_AA20
BANK_4A_AA15
BANK_4A_Y15
BANK_4A_U21
BANK_4A_V20
BANK_4A_U22
BANK_4A_Y21
BANK_4A_W22
BANK_4A_AA14
BANK_5A_P16
BANK_5A_T20
BANK_5A_P22
BANK_5A_R22
BANK_5B_M20
BANK_5B_N21
BANK_4A_AB15
BANK_5B_K21
BANK_5B_K17
BANK_5B_L22
BANK_5B_L19
BANK_5B_N19
BANK_4A_Y14
BANK_4A_AA19
BANK_4A_AA17
BANK_4A_Y16
BANK_4A_AB17
BANK_4A_W21
BANK_4A_Y22
BANK_4A_AB22
BANK_4A_AB20
BANK_4A_Y19
BANK_5A_T19
BANK_5A_R21
BANK_5A_T22
BANK_4A_U20
BANK_4A_W19
BANK_4A_V21
BANK_4A_AA13
BANK_5A_P17
BANK_5B_M16 BANK_5B_N16
BANK_2A_Y3
BANK_2A_AA2
BANK_2A_N1
BANK_2A_U1
BANK_2A_C1
BANK_2A_E2
BANK_2A_G1
BANK_2A_L1
BANK_2A_AA1
BANK_2A_C2
BANK_2A_D3
BANK_2A_G2
BANK_2A_L2
BANK_2A_N2
BANK_2A_U2
BANK_2A_W2
BANK_8A_A9
BANK_8A_A7
BANK_8A_B6
BANK_8A_B5
BANK_8A_D6
BANK_7A_E12
BANK_7A_B12
BANK_7A_C11
BANK_8A_G10
BANK_8A_E9
BANK_8A_B10
BANK_7A_C16
BANK_7A_B15
BANK_7A_A15
BANK_7A_B13
BANK_7A_D13
BANK_8A_A8
BANK_8A_D9
BANK_8A_B7
BANK_8A_A5
BANK_8A_C6
BANK_7A_D12
BANK_7A_A12
BANK_7A_B11
BANK_8A_F10
BANK_8A_C9
BANK_8A_A10
BANK_7A_B16
BANK_7A_C15
BANK_7A_A14
BANK_7A_A13
BANK_7A_C13
BANK_8A_G8 BANK_8A_H8
BANK_8A_E7BANK_8A_F7
BANK_8A_H6BANK_8A_G6
Connected to VIN
power header.
Connected to VIN
power header.
QM_CycloneV_5CEFA2 Core Board User Manual-V01
2.2.4 QM_CycloneV_5CEFA2 User LED
Below image shows one user LED and 3.3V power supply indicator:
Figure 2-11. User LEDs
2.2.5 QM_CycloneV_5CEFA2 User Key
Below image shows the nCONFIG key and two user keys:
Figure 2-12. User Keys
R131
1K
D4
1 2
3V3
D5
1 2
R255
1K
3V3
LED_D5
KEY0 RESET_N nCONFIG
SW3
1
2
SW1
1
2
KEY0
SW2
1
2
RESET_N
R221
4.7K
3V3
3V3
R228
4.7k
QM_CycloneV_5CEFA2 Core Board User Manual-V01
3. Reference
[1] 5cefa2-sdram_20171202_V01.pdf
[2] cv_5v2_Cyclone V Device Handbook.pdf
[3] an662_Arria V and Cyclone V Design Guidelines.pdf
[4] cv_51001_Cyclone V Device Overview.pdf
[5] cv_51002_Cyclone V Device Datasheet.pdf
[6] pcg-01014_Cyclone® V Device Family Pin Connection Guidelines.pdf
QM_CycloneV_5CEFA2 Core Board User Manual-V01
4. Revision
Doc. Rev.
Date
Comments
0.1
1/1/2018
Initial Version.
1.0
7/1/2018
V1.0 Formal Release.
