S32K1XXRM, S32K1xx Series Reference Manual S32K
S32K_ReferenceManual
User Manual:
Open the PDF directly: View PDF
Page Count: 2013 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- S32K1xx Reference Manual (Supports S32K116, S32K118, S32K142, S32K144, S32K146, and S32K148)
- Contents
- Chapter 1: About This Manual
- Chapter 2: Introduction
- Chapter 3: Memory Map
- Chapter 4: Signal Multiplexing and Pin Assignment
- Chapter 5: Security Overview
- Chapter 6: Safety Overview
- Chapters 7-24 Core and System Modules
- Chapter 7: CM4 Overview
- Chapter 8: CM0+ Overview
- Chapter 9: Micro Trace Buffer (MTB)
- Chapter 10: Miscellaneous Control Module (MCM)
- Chapter 11: System Integration Module (SIM)
- Chip-specific SIM information
- Introduction
- Memory map and register definition
- SIM register descriptions
- SIM Memory map
- Chip Control register (CHIPCTL)
- FTM Option Register 0 (FTMOPT0)
- LPO Clock Select Register (LPOCLKS)
- ADC Options Register (ADCOPT)
- FTM Option Register 1 (FTMOPT1)
- Miscellaneous control register 0 (MISCTRL0)
- System Device Identification Register (SDID)
- Platform Clock Gating Control Register (PLATCGC)
- Flash Configuration Register 1 (FCFG1)
- Unique Identification Register High (UIDH)
- Unique Identification Register Mid-High (UIDMH)
- Unique Identification Register Mid Low (UIDML)
- Unique Identification Register Low (UIDL)
- System Clock Divider Register 4 (CLKDIV4)
- Miscellaneous Control register 1 (MISCTRL1)
- SIM register descriptions
- Chapter 12: Port Control and Interrupts (PORT)
- Chapter 13: General-Purpose Input/Output (GPIO)
- Chapter 14: Crossbar Switch Lite (AXBS-Lite)
- Chapter 15: Memory Protection Unit (MPU)
- Chip-specific MPU information
- Introduction
- Overview
- MPU register descriptions
- MPU Memory map
- Control/Error Status Register (CESR)
- Error Address Register, slave port n (EAR0 - EAR4)
- Error Detail Register, slave port n (EDR0 - EDR4)
- Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)
- Region Descriptor 0, Word 1 (RGD0_WORD1)
- Region Descriptor 0, Word 2 (RGD0_WORD2)
- Region Descriptor 0, Word 3 (RGD0_WORD3)
- Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)
- Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)
- Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)
- Region Descriptor Alternate Access Control 0 (RGDAAC0)
- Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)
- Functional description
- Initialization information
- Application information
- Chapter 16: Peripheral Bridge (AIPS-Lite)
- Chip-specific AIPS information
- Introduction
- Memory map/register definition
- AIPS register descriptions
- AIPS Memory map
- Master Privilege Register A (MPRA)
- Peripheral Access Control Register (PACRA)
- Peripheral Access Control Register (PACRB)
- Peripheral Access Control Register (PACRD)
- Off-Platform Peripheral Access Control Register (OPACRA)
- Off-Platform Peripheral Access Control Register (OPACRB)
- Off-Platform Peripheral Access Control Register (OPACRC)
- Off-Platform Peripheral Access Control Register (OPACRD)
- Off-Platform Peripheral Access Control Register (OPACRE)
- Off-Platform Peripheral Access Control Register (OPACRF)
- Off-Platform Peripheral Access Control Register (OPACRG)
- Off-Platform Peripheral Access Control Register (OPACRH)
- Off-Platform Peripheral Access Control Register (OPACRI)
- Off-Platform Peripheral Access Control Register (OPACRJ)
- Off-Platform Peripheral Access Control Register (OPACRK)
- Off-Platform Peripheral Access Control Register (OPACRL)
- AIPS register descriptions
- Functional description
- Chapter 17: Direct Memory Access Multiplexer (DMAMUX)
- Chapter 18: Enhanced Direct Memory Access (eDMA)
- Chip-specific eDMA information
- Introduction
- Modes of operation
- Memory map/register definition
- TCD memory
- TCD initialization
- TCD structure
- Reserved memory and bit fields
- DMA register descriptions
- DMA Memory map
- Control Register (CR)
- Error Status Register (ES)
- Enable Request Register (ERQ)
- Enable Error Interrupt Register (EEI)
- Clear Enable Error Interrupt Register (CEEI)
- Set Enable Error Interrupt Register (SEEI)
- Clear Enable Request Register (CERQ)
- Set Enable Request Register (SERQ)
- Clear DONE Status Bit Register (CDNE)
- Set START Bit Register (SSRT)
- Clear Error Register (CERR)
- Clear Interrupt Request Register (CINT)
- Interrupt Request Register (INT)
- Error Register (ERR)
- Hardware Request Status Register (HRS)
- Enable Asynchronous Request in Stop Register (EARS)
- Channel Priority Register (DCHPRI0 - DCHPRI15)
- TCD Source Address (TCD0_SADDR - TCD15_SADDR)
- TCD Signed Source Address Offset (TCD0_SOFF - TCD15_SOFF)
- TCD Transfer Attributes (TCD0_ATTR - TCD15_ATTR)
- TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO - TCD15_NBYTES_MLNO)
- TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD15_NBYTES_MLOFFNO)
- TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0_NBYTES_MLOFFYES - TCD15_NBYTES_MLOFFYES)
- TCD Last Source Address Adjustment (TCD0_SLAST - TCD15_SLAST)
- TCD Destination Address (TCD0_DADDR - TCD15_DADDR)
- TCD Signed Destination Address Offset (TCD0_DOFF - TCD15_DOFF)
- TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_CITER_ELINKNO - TCD15_CITER_ELINKNO)
- TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD15_CITER_ELINKYES)
- TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA - TCD15_DLASTSGA)
- TCD Control and Status (TCD0_CSR - TCD15_CSR)
- TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_BITER_ELINKNO - TCD15_BITER_ELINKNO)
- TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_BITER_ELINKYES - TCD15_BITER_ELINKYES)
- Functional description
- Initialization/application information
- Chapter 19: Trigger MUX Control (TRGMUX)
- Chip-specific TRGMUX information
- Introduction
- Features
- Memory map and register definition
- TRGMUX register descriptions
- TRGMUX Memory map
- TRGMUX DMAMUX0 Register (DMAMUX0)
- TRGMUX EXTOUT0 Register (EXTOUT0)
- TRGMUX EXTOUT1 Register (EXTOUT1)
- TRGMUX ADC0 Register (ADC0)
- TRGMUX ADC1 Register (ADC1)
- TRGMUX CMP0 Register (CMP0)
- TRGMUX FTM0 Register (FTM0)
- TRGMUX FTM1 Register (FTM1)
- TRGMUX FTM2 Register (FTM2)
- TRGMUX FTM3 Register (FTM3)
- TRGMUX PDB0 Register (PDB0)
- TRGMUX PDB1 Register (PDB1)
- TRGMUX FLEXIO Register (FLEXIO)
- TRGMUX LPIT0 Register (LPIT0)
- TRGMUX LPUART0 Register (LPUART0)
- TRGMUX LPUART1 Register (LPUART1)
- TRGMUX LPI2C0 Register (LPI2C0)
- TRGMUX LPSPI0 Register (LPSPI0)
- TRGMUX LPSPI1 Register (LPSPI1)
- TRGMUX LPTMR0 Register (LPTMR0)
- TRGMUX LPI2C1 Register (LPI2C1)
- TRGMUX FTM4 Register (FTM4)
- TRGMUX FTM5 Register (FTM5)
- TRGMUX FTM6 Register (FTM6)
- TRGMUX FTM7 Register (FTM7)
- TRGMUX register descriptions
- Chapter 20: External Watchdog Monitor (EWM)
- Chapter 21: Error Injection Module (EIM)
- Chapter 22: Error Reporting Module (ERM)
- Chapter 23: Watchdog timer (WDOG)
- Chapter 24: Cyclic Redundancy Check (CRC)
- Chapters 25-26 Reset and Boot
- Chapters 27-30 Clocking
- Chapter 27: Clock Distribution
- Chapter 28: System Clock Generator (SCG)
- Chapter 29: Peripheral Clock Controller (PCC)
- Chip-specific PCC information
- Introduction
- Features
- Functional description
- Memory map and register definition
- PCC register descriptions
- PCC Memory map
- PCC FTFC Register (PCC_FTFC)
- PCC DMAMUX Register (PCC_DMAMUX)
- PCC FlexCAN0 Register (PCC_FlexCAN0)
- PCC FlexCAN1 Register (PCC_FlexCAN1)
- PCC FTM3 Register (PCC_FTM3)
- PCC ADC1 Register (PCC_ADC1)
- PCC FlexCAN2 Register (PCC_FlexCAN2)
- PCC LPSPI0 Register (PCC_LPSPI0)
- PCC LPSPI1 Register (PCC_LPSPI1)
- PCC LPSPI2 Register (PCC_LPSPI2)
- PCC PDB1 Register (PCC_PDB1)
- PCC CRC Register (PCC_CRC)
- PCC PDB0 Register (PCC_PDB0)
- PCC LPIT Register (PCC_LPIT)
- PCC FTM0 Register (PCC_FTM0)
- PCC FTM1 Register (PCC_FTM1)
- PCC FTM2 Register (PCC_FTM2)
- PCC ADC0 Register (PCC_ADC0)
- PCC RTC Register (PCC_RTC)
- PCC LPTMR0 Register (PCC_LPTMR0)
- PCC PORTA Register (PCC_PORTA)
- PCC PORTB Register (PCC_PORTB)
- PCC PORTC Register (PCC_PORTC)
- PCC PORTD Register (PCC_PORTD)
- PCC PORTE Register (PCC_PORTE)
- PCC SAI0 Register (PCC_SAI0)
- PCC SAI1 Register (PCC_SAI1)
- PCC FlexIO Register (PCC_FlexIO)
- PCC EWM Register (PCC_EWM)
- PCC LPI2C0 Register (PCC_LPI2C0)
- PCC LPI2C1 Register (PCC_LPI2C1)
- PCC LPUART0 Register (PCC_LPUART0)
- PCC LPUART1 Register (PCC_LPUART1)
- PCC LPUART2 Register (PCC_LPUART2)
- PCC FTM4 Register (PCC_FTM4)
- PCC FTM5 Register (PCC_FTM5)
- PCC FTM6 Register (PCC_FTM6)
- PCC FTM7 Register (PCC_FTM7)
- PCC CMP0 Register (PCC_CMP0)
- PCC QSPI Register (PCC_QSPI)
- PCC ENET Register (PCC_ENET)
- Chapter 30: Clock Monitoring Unit (CMU)
- Chapters 31-37 Memories and Memory Interfaces
- Chapter 31: Memories and Memory Interfaces
- Chapter 32: PRAM Controller (PRAMC)
- Chapter 33: Local Memory Controller (LMEM)
- Chapter 34: Miscellaneous System Control Module (MSCM)
- Chip-specific MSCM information
- Overview
- Chip Configuration and Boot
- MSCM Memory Map/Register Definition
- CPU Configuration Memory Map and Registers
- MSCM register descriptions
- MSCM Memory map
- Processor X Type Register (CPxTYPE)
- Processor X Number Register (CPxNUM)
- Processor X Master Register (CPxMASTER)
- Processor X Count Register (CPxCOUNT)
- Processor X Configuration Register 0 (CPxCFG0)
- Processor X Configuration Register 1 (CPxCFG1)
- Processor X Configuration Register 2 (CPxCFG2)
- Processor X Configuration Register 3 (CPxCFG3)
- Processor 0 Type Register (CP0TYPE)
- Processor 0 Number Register (CP0NUM)
- Processor 0 Master Register (CP0MASTER)
- Processor 0 Count Register (CP0COUNT)
- Processor 0 Configuration Register 0 (CP0CFG0)
- Processor 0 Configuration Register 1 (CP0CFG1)
- Processor 0 Configuration Register 2 (CP0CFG2)
- Processor 0 Configuration Register 3 (CP0CFG3)
- On-Chip Memory Descriptor Register (OCMDR0)
- On-Chip Memory Descriptor Register (OCMDR1)
- On-Chip Memory Descriptor Register (OCMDR2)
- Chapter 35: Flash Memory Controller (FMC)
- Chapter 36: Flash Memory Module (FTFC)
- Chip-specific FTFC information
- Flash memory types
- Flash memory sizes
- 128 KB program flash / 32 KB FlexNVM / 2 KB FlexRAM module
- 256 KB program flash / 32 KB FlexNVM / 2 KB FlexRAM module
- 256 KB program flash / 64 KB FlexNVM / 4 KB FlexRAM module
- 512 KB program flash / 64 KB FlexNVM / 4 KB FlexRAM module
- 1 MB program flash / 256 KB FlexNVM / 4 KB FlexRAM module
- 2 MB program flash / 256 KB FlexNVM / 4 KB FlexRAM module
- Flash memory map
- Flash memory security
- Power mode restrictions on flash memory programming
- Flash memory modes
- Erase all contents of flash memory
- Customize MCU operations via FTFC_FOPT register
- Simultaneous operations on PFLASH read partitions
- Introduction
- External signal description
- Memory map and registers
- Flash configuration field description
- Program flash 0 IFR map
- Data flash 0 IFR map
- Register descriptions
- FTFC register descriptions
- FTFC Memory map
- Flash Status Register (FSTAT)
- Flash Configuration Register (FCNFG)
- Flash Security Register (FSEC)
- Flash Option Register (FOPT)
- Flash Common Command Object Registers (FCCOB0 - FCCOBB)
- Program Flash Protection Registers (FPROT0 - FPROT3)
- EEPROM Protection Register (FEPROT)
- Data Flash Protection Register (FDPROT)
- Flash CSEc Status Register (FCSESTAT)
- Flash Error Status Register (FERSTAT)
- Flash Error Configuration Register (FERCNFG)
- FTFC register descriptions
- Functional description
- Flash protection
- FlexNVM description
- Interrupts
- Flash operation in low-power modes
- Functional modes of operation
- Flash memory reads and ignored writes
- Read while write (RWW)
- Flash program and erase
- FTFC command operations
- Margin read commands
- Flash command descriptions
- Read 1s Block command
- Read 1s Section command
- Program Check command
- Program Phrase command
- Erase Flash Block command
- Erase Flash Sector command
- Program Section command
- Read 1s All Blocks command
- Read Once command
- Program Once command
- Erase All Blocks command
- Verify Backdoor Access Key command
- Erase All Blocks Unsecure command
- Program Partition command
- Set FlexRAM Function command
- Security
- Cryptographic Services Engine (CSEc)
- Key/seed/random number generation
- Secure boot mode
- User CSEc command interface and command set
- Generic PRAM interface description
- CMD_ENC_ECB
- CMD_ENC_CBC
- CMD_DEC_ECB
- CMD_DEC_CBC
- CMD_GENERATE_MAC
- CSEc format for CMD_GENERATE_MAC (pointer method)
- CMD_VERIFY_MAC
- CMD_VERIFY_MAC - CSEc format (pointer method)
- CMD_LOAD_KEY
- CMD_LOAD_PLAIN_KEY
- CMD_EXPORT_RAM_KEY
- CMD_INIT_RNG
- CMD_EXTEND_SEED
- CMD_RND
- CMD_SECURE_BOOT
- CMD_BOOT_FAILURE
- CMD_BOOT_OK
- CMD_GET_STATUS
- CMD_GET_ID
- CMD_CANCEL
- CMD_BOOT_DEFINE
- CMD_DBG_CHAL
- CMD_DBG_AUTH
- CMD_MP_COMPRESS
- Reset sequence
- Chip-specific FTFC information
- Chapter 37: Quad Serial Peripheral Interface (QuadSPI)
- Chip-specific QuadSPI information
- Introduction
- External Signal Description
- Memory Map and Register Definition
- Register Write Access
- Peripheral Bus Register Descriptions
- QuadSPI
- QuadSPI_MCR
- QuadSPI_IPCR
- QuadSPI_FLSHCR
- QuadSPI_BUF0CR
- QuadSPI_BUF1CR
- QuadSPI_BUF2CR
- QuadSPI_BUF3CR
- QuadSPI_BFGENCR
- QuadSPI_SOCCR
- QuadSPI_BUF0IND
- QuadSPI_BUF1IND
- QuadSPI_BUF2IND
- QuadSPI_SFAR
- QuadSPI_SFACR
- QuadSPI_SMPR
- QuadSPI_RBSR
- QuadSPI_RBCT
- QuadSPI_TBSR
- QuadSPI_TBDR
- QuadSPI_TBCT
- QuadSPI_SR
- QuadSPI_FR
- QuadSPI_RSER
- QuadSPI_SPNDST
- QuadSPI_SPTRCLR
- QuadSPI_SFA1AD
- QuadSPI_SFA2AD
- QuadSPI_SFB1AD
- QuadSPI_SFB2AD
- QuadSPI_RBDRn
- QuadSPI_LUTKEY
- QuadSPI_LCKCR
- QuadSPI_LUTn
- QuadSPI
- Serial Flash Address Assignment
- Flash memory mapped AMBA bus
- Interrupt Signals
- Functional Description
- Initialization/Application Information
- Byte Ordering - Endianness
- Driving Flash Control Signals in Single and Dual Mode
- Serial Flash Devices
- Example Sequences
- Read Command (Spansion Hyperflash/HyperRAM)
- Read Status Register(Spansion Hyperflash/HyperRAM)
- Word Program (Spansion Hyperflash/HyperRAM)
- Fast Read Sequence (Macronix/Numonyx/Spansion/Winbond)
- Fast Dual I/O DT Read Sequence (Macronix)
- Fast Read Quad Output (Winbond)
- 4 x I/O Read Enhance Performance Mode (XIP) (Macronix)
- Dual Command Page Program (Numonyx)
- Sector Erase (Macronix/Spansion/Numonyx)
- Read Status Register (Macronix/Spansion/Numonyx/Winbond)
- Example Sequences
- Sampling of Serial Flash Input Data
- Data Input Hold Requirement of Flash
- Chapters 38-40 Power Management
- Chapter 38: Power Management
- Chapter 39: System Mode Controller (SMC)
- Chapter 40: Power Management Controller (PMC)
- Chapters 41-43 Analog Modules
- Chapter 41: ADC Configuration
- Instantiation information
- Register implementation
- DMA Support on ADC
- ADC Hardware Interleaved Channels
- ADC internal supply monitoring
- ADC Reference Options
- ADC Trigger Sources
- Trigger Selection
- Trigger Latching and Arbitration
- ADC triggering configurations
- ADC low-power modes
- ADC Trigger Concept – Use Case
- ADC calibration scheme
- Chapter 42: Analog-to-Digital Converter (ADC)
- Chip-specific ADC information
- Introduction
- ADC signal descriptions
- ADC register descriptions
- ADC Memory map
- ADC Status and Control Register 1 (SC1A - aSC1P)
- ADC Configuration Register 1 (CFG1)
- ADC Configuration Register 2 (CFG2)
- ADC Data Result Registers (RA - aRP)
- Compare Value Registers (CV1 - CV2)
- Status and Control Register 2 (SC2)
- Status and Control Register 3 (SC3)
- BASE Offset Register (BASE_OFS)
- ADC Offset Correction Register (OFS)
- USER Offset Correction Register (USR_OFS)
- ADC X Offset Correction Register (XOFS)
- ADC Y Offset Correction Register (YOFS)
- ADC Gain Register (G)
- ADC User Gain Register (UG)
- ADC General Calibration Value Register S (CLPS)
- ADC Plus-Side General Calibration Value Register 3 (CLP3)
- ADC Plus-Side General Calibration Value Register 2 (CLP2)
- ADC Plus-Side General Calibration Value Register 1 (CLP1)
- ADC Plus-Side General Calibration Value Register 0 (CLP0)
- ADC Plus-Side General Calibration Value Register X (CLPX)
- ADC Plus-Side General Calibration Value Register 9 (CLP9)
- ADC General Calibration Offset Value Register S (CLPS_OFS)
- ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)
- ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)
- ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)
- ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)
- ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)
- ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)
- ADC Status and Control Register 1 (SC1AA - SC1Z)
- ADC Data Result Registers (RAA - RZ)
- Functional description
- Chapter 43: Comparator (CMP)
- Chapter 41: ADC Configuration
- Chapters 44-48 Timer Modules
- Chapter 44: Programmable delay block (PDB)
- Chapter 45: FlexTimer Module (FTM)
- Chip-specific FTM information
- Introduction
- FTM signal descriptions
- Memory map and register definition
- Memory map
- Register descriptions
- FTM register descriptions
- FTM Memory map
- Status And Control (SC)
- Counter (CNT)
- Modulo (MOD)
- Channel (n) Status And Control (C0SC - C7SC)
- Channel (n) Value (C0V - C7V)
- Counter Initial Value (CNTIN)
- Capture And Compare Status (STATUS)
- Features Mode Selection (MODE)
- Synchronization (SYNC)
- Initial State For Channels Output (OUTINIT)
- Output Mask (OUTMASK)
- Function For Linked Channels (COMBINE)
- Deadtime Configuration (DEADTIME)
- FTM External Trigger (EXTTRIG)
- Channels Polarity (POL)
- Fault Mode Status (FMS)
- Input Capture Filter Control (FILTER)
- Fault Control (FLTCTRL)
- Quadrature Decoder Control And Status (QDCTRL)
- Configuration (CONF)
- FTM Fault Input Polarity (FLTPOL)
- Synchronization Configuration (SYNCONF)
- FTM Inverting Control (INVCTRL)
- FTM Software Output Control (SWOCTRL)
- FTM PWM Load (PWMLOAD)
- Half Cycle Register (HCR)
- Pair 0 Deadtime Configuration (PAIR0DEADTIME)
- Pair 1 Deadtime Configuration (PAIR1DEADTIME)
- Pair 2 Deadtime Configuration (PAIR2DEADTIME)
- Pair 3 Deadtime Configuration (PAIR3DEADTIME)
- Mirror of Modulo Value (MOD_MIRROR)
- Mirror of Channel (n) Match Value (C0V_MIRROR - C7V_MIRROR)
- Functional Description
- Clock source
- Prescaler
- Counter
- Channel Modes
- Input Capture Mode
- Output Compare mode
- Edge-Aligned PWM (EPWM) mode
- Center-Aligned PWM (CPWM) mode
- Combine mode
- Modified Combine PWM Mode
- Complementary Mode
- Registers updated from write buffers
- PWM synchronization
- Inverting
- Software Output Control Mode
- Deadtime insertion
- Output mask
- Fault Control
- Polarity Control
- Initialization
- Features Priority
- External Trigger
- Initialization Trigger
- Capture Test Mode
- DMA
- Dual Edge Capture Mode
- Quadrature Decoder Mode
- Debug mode
- Reload Points
- Global Load
- Global time base (GTB)
- Channel trigger output
- External Control of Channels Output
- Dithering
- Reset Overview
- FTM Interrupts
- Initialization Procedure
- Chapter 46: Low Power Interrupt Timer (LPIT)
- Chip-specific LPIT information
- Introduction
- Modes of operation
- Memory Map and Registers
- LPIT register descriptions
- LPIT Memory map
- Version ID Register (VERID)
- Parameter Register (PARAM)
- Module Control Register (MCR)
- Module Status Register (MSR)
- Module Interrupt Enable Register (MIER)
- Set Timer Enable Register (SETTEN)
- Clear Timer Enable Register (CLRTEN)
- Timer Value Register (TVAL0 - TVAL3)
- Current Timer Value (CVAL0 - CVAL3)
- Timer Control Register (TCTRL0 - TCTRL3)
- LPIT register descriptions
- Functional description
- Chapter 47: Low Power Timer (LPTMR)
- Chapter 48: Real Time Clock (RTC)
- Chapters 49-55 Communication Modules
- Chapter 49: Low Power Serial Peripheral Interface (LPSPI)
- Chip-specific LPSPI information
- Introduction
- Memory Map and Registers
- LPSPI register descriptions
- LPSPI Memory map
- Version ID Register (VERID)
- Parameter Register (PARAM)
- Control Register (CR)
- Status Register (SR)
- Interrupt Enable Register (IER)
- DMA Enable Register (DER)
- Configuration Register 0 (CFGR0)
- Configuration Register 1 (CFGR1)
- Data Match Register 0 (DMR0)
- Data Match Register 1 (DMR1)
- Clock Configuration Register (CCR)
- FIFO Control Register (FCR)
- FIFO Status Register (FSR)
- Transmit Command Register (TCR)
- Transmit Data Register (TDR)
- Receive Status Register (RSR)
- Receive Data Register (RDR)
- LPSPI register descriptions
- Functional description
- Chapter 50: Low Power Inter-Integrated Circuit (LPI2C)
- Chip-specific LPI2C information
- Introduction
- Memory Map and Registers
- LPI2C register descriptions
- LPI2C Memory map
- Version ID Register (VERID)
- Parameter Register (PARAM)
- Master Control Register (MCR)
- Master Status Register (MSR)
- Master Interrupt Enable Register (MIER)
- Master DMA Enable Register (MDER)
- Master Configuration Register 0 (MCFGR0)
- Master Configuration Register 1 (MCFGR1)
- Master Configuration Register 2 (MCFGR2)
- Master Configuration Register 3 (MCFGR3)
- Master Data Match Register (MDMR)
- Master Clock Configuration Register 0 (MCCR0)
- Master Clock Configuration Register 1 (MCCR1)
- Master FIFO Control Register (MFCR)
- Master FIFO Status Register (MFSR)
- Master Transmit Data Register (MTDR)
- Master Receive Data Register (MRDR)
- Slave Control Register (SCR)
- Slave Status Register (SSR)
- Slave Interrupt Enable Register (SIER)
- Slave DMA Enable Register (SDER)
- Slave Configuration Register 1 (SCFGR1)
- Slave Configuration Register 2 (SCFGR2)
- Slave Address Match Register (SAMR)
- Slave Address Status Register (SASR)
- Slave Transmit ACK Register (STAR)
- Slave Transmit Data Register (STDR)
- Slave Receive Data Register (SRDR)
- LPI2C register descriptions
- Functional description
- Chapter 51: Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
- Chip-specific LPUART information
- Introduction
- Register definition
- LPUART register descriptions
- LPUART Memory map
- Version ID Register (VERID)
- Parameter Register (PARAM)
- LPUART Global Register (GLOBAL)
- LPUART Pin Configuration Register (PINCFG)
- LPUART Baud Rate Register (BAUD)
- LPUART Status Register (STAT)
- LPUART Control Register (CTRL)
- LPUART Data Register (DATA)
- LPUART Match Address Register (MATCH)
- LPUART Modem IrDA Register (MODIR)
- LPUART FIFO Register (FIFO)
- LPUART Watermark Register (WATER)
- LPUART register descriptions
- Functional description
- Chapter 52: Flexible I/O (FlexIO)
- Chip-specific FlexIO information
- Introduction
- Memory Map and Registers
- FLEXIO register descriptions
- FLEXIO Memory map
- Version ID Register (VERID)
- Parameter Register (PARAM)
- FlexIO Control Register (CTRL)
- Pin State Register (PIN)
- Shifter Status Register (SHIFTSTAT)
- Shifter Error Register (SHIFTERR)
- Timer Status Register (TIMSTAT)
- Shifter Status Interrupt Enable (SHIFTSIEN)
- Shifter Error Interrupt Enable (SHIFTEIEN)
- Timer Interrupt Enable Register (TIMIEN)
- Shifter Status DMA Enable (SHIFTSDEN)
- Shifter Control N Register (SHIFTCTL0 - SHIFTCTL3)
- Shifter Configuration N Register (SHIFTCFG0 - SHIFTCFG3)
- Shifter Buffer N Register (SHIFTBUF0 - SHIFTBUF3)
- Shifter Buffer N Bit Swapped Register (SHIFTBUFBIS0 - SHIFTBUFBIS3)
- Shifter Buffer N Byte Swapped Register (SHIFTBUFBYS0 - SHIFTBUFBYS3)
- Shifter Buffer N Bit Byte Swapped Register (SHIFTBUFBBS0 - SHIFTBUFBBS3)
- Timer Control N Register (TIMCTL0 - TIMCTL3)
- Timer Configuration N Register (TIMCFG0 - TIMCFG3)
- Timer Compare N Register (TIMCMP0 - TIMCMP3)
- FLEXIO register descriptions
- Functional description
- Application Information
- Chapter 53: FlexCAN
- Chip-specific FlexCAN information
- Introduction
- FlexCAN signal descriptions
- Memory map/register definition
- FlexCAN memory mapping
- CAN register descriptions
- CAN Memory map
- Module Configuration Register (MCR)
- Control 1 register (CTRL1)
- Free Running Timer (TIMER)
- Rx Mailboxes Global Mask Register (RXMGMASK)
- Rx 14 Mask register (RX14MASK)
- Rx 15 Mask register (RX15MASK)
- Error Counter (ECR)
- Error and Status 1 register (ESR1)
- Interrupt Masks 1 register (IMASK1)
- Interrupt Flags 1 register (IFLAG1)
- Control 2 register (CTRL2)
- Error and Status 2 register (ESR2)
- CRC Register (CRCR)
- Rx FIFO Global Mask register (RXFGMASK)
- Rx FIFO Information Register (RXFIR)
- CAN Bit Timing Register (CBT)
- Rx Individual Mask Registers (RXIMR0 - RXIMR31)
- Pretended Networking Control 1 Register (CTRL1_PN)
- Pretended Networking Control 2 Register (CTRL2_PN)
- Pretended Networking Wake Up Match Register (WU_MTC)
- Pretended Networking ID Filter 1 Register (FLT_ID1)
- Pretended Networking DLC Filter Register (FLT_DLC)
- Pretended Networking Payload Low Filter 1 Register (PL1_LO)
- Pretended Networking Payload High Filter 1 Register (PL1_HI)
- Pretended Networking ID Filter 2 Register / ID Mask Register (FLT_ID2_IDMASK)
- Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register (PL2_PLMASK_LO)
- Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register (PL2_PLMASK_HI)
- Wake Up Message Buffer Register for C/S (WMB0_CS - WMB3_CS)
- Wake Up Message Buffer Register for ID (WMB0_ID - WMB3_ID)
- Wake Up Message Buffer Register for Data 0-3 (WMB0_D03 - WMB3_D03)
- Wake Up Message Buffer Register Data 4-7 (WMB0_D47 - WMB3_D47)
- CAN FD Control Register (FDCTRL)
- CAN FD Bit Timing Register (FDCBT)
- CAN FD CRC Register (FDCRC)
- Message buffer structure
- FlexCAN Memory Partition for CAN FD
- FlexCAN message buffer memory map
- Rx FIFO structure
- Functional description
- Initialization/application information
- Chapter 54: Synchronous Audio Interface (SAI)
- Chip-specific SAI information
- Introduction
- External signals
- Memory map and register definition
- I2S register descriptions
- I2S Memory map
- Version ID Register (VERID)
- Parameter Register (PARAM)
- SAI Transmit Control Register (TCSR)
- SAI Transmit Configuration 1 Register (TCR1)
- SAI Transmit Configuration 2 Register (TCR2)
- SAI Transmit Configuration 3 Register (TCR3)
- SAI Transmit Configuration 4 Register (TCR4)
- SAI Transmit Configuration 5 Register (TCR5)
- SAI Transmit Data Register (TDR0 - TDR3)
- SAI Transmit FIFO Register (TFR0 - TFR3)
- SAI Transmit Mask Register (TMR)
- SAI Receive Control Register (RCSR)
- SAI Receive Configuration 1 Register (RCR1)
- SAI Receive Configuration 2 Register (RCR2)
- SAI Receive Configuration 3 Register (RCR3)
- SAI Receive Configuration 4 Register (RCR4)
- SAI Receive Configuration 5 Register (RCR5)
- SAI Receive Data Register (RDR0 - RDR3)
- SAI Receive FIFO Register (RFR0 - RFR3)
- SAI Receive Mask Register (RMR)
- I2S register descriptions
- Functional description
- Chapter 55: Ethernet MAC (ENET)
- Chip-specific ENET information
- Introduction
- Overview
- External signal description
- Memory map/register definition
- ENET
- ENET_EIR
- ENET_EIMR
- ENET_RDAR
- ENET_TDAR
- ENET_ECR
- ENET_MMFR
- ENET_MSCR
- ENET_MIBC
- ENET_RCR
- ENET_TCR
- ENET_PALR
- ENET_PAUR
- ENET_OPD
- ENET_IAUR
- ENET_IALR
- ENET_GAUR
- ENET_GALR
- ENET_TFWR
- ENET_RDSR
- ENET_TDSR
- ENET_MRBR
- ENET_RSFL
- ENET_RSEM
- ENET_RAEM
- ENET_RAFL
- ENET_TSEM
- ENET_TAEM
- ENET_TAFL
- ENET_TIPG
- ENET_FTRL
- ENET_TACC
- ENET_RACC
- ENET_RMON_T_DROP
- ENET_RMON_T_PACKETS
- ENET_RMON_T_BC_PKT
- ENET_RMON_T_MC_PKT
- ENET_RMON_T_CRC_ALIGN
- ENET_RMON_T_UNDERSIZE
- ENET_RMON_T_OVERSIZE
- ENET_RMON_T_FRAG
- ENET_RMON_T_JAB
- ENET_RMON_T_COL
- ENET_RMON_T_P64
- ENET_RMON_T_P65TO127
- ENET_RMON_T_P128TO255
- ENET_RMON_T_P256TO511
- ENET_RMON_T_P512TO1023
- ENET_RMON_T_P1024TO2047
- ENET_RMON_T_P_GTE2048
- ENET_RMON_T_OCTETS
- ENET_IEEE_T_DROP
- ENET_IEEE_T_FRAME_OK
- ENET_IEEE_T_1COL
- ENET_IEEE_T_MCOL
- ENET_IEEE_T_DEF
- ENET_IEEE_T_LCOL
- ENET_IEEE_T_EXCOL
- ENET_IEEE_T_MACERR
- ENET_IEEE_T_CSERR
- ENET_IEEE_T_SQE
- ENET_IEEE_T_FDXFC
- ENET_IEEE_T_OCTETS_OK
- ENET_RMON_R_PACKETS
- ENET_RMON_R_BC_PKT
- ENET_RMON_R_MC_PKT
- ENET_RMON_R_CRC_ALIGN
- ENET_RMON_R_UNDERSIZE
- ENET_RMON_R_OVERSIZE
- ENET_RMON_R_FRAG
- ENET_RMON_R_JAB
- ENET_RMON_R_RESVD_0
- ENET_RMON_R_P64
- ENET_RMON_R_P65TO127
- ENET_RMON_R_P128TO255
- ENET_RMON_R_P256TO511
- ENET_RMON_R_P512TO1023
- ENET_RMON_R_P1024TO2047
- ENET_RMON_R_P_GTE2048
- ENET_RMON_R_OCTETS
- ENET_IEEE_R_DROP
- ENET_IEEE_R_FRAME_OK
- ENET_IEEE_R_CRC
- ENET_IEEE_R_ALIGN
- ENET_IEEE_R_MACERR
- ENET_IEEE_R_FDXFC
- ENET_IEEE_R_OCTETS_OK
- ENET_ATCR
- ENET_ATVR
- ENET_ATOFF
- ENET_ATPER
- ENET_ATCOR
- ENET_ATINC
- ENET_ATSTMP
- ENET_TGSR
- ENET_TCSRn
- ENET_TCCRn
- ENET
- Functional description
- Ethernet MAC frame formats
- IP and higher layers frame format
- IEEE 1588 message formats
- MAC receive
- MAC transmit
- Full-duplex flow control operation
- Magic packet detection
- IP accelerator functions
- Resets and stop controls
- IEEE 1588 functions
- FIFO thresholds
- Loopback options
- Legacy buffer descriptors
- Enhanced buffer descriptors
- Client FIFO application interface
- FIFO protection
- Reference clock
- PHY management interface
- Ethernet interfaces
- Chapter 49: Low Power Serial Peripheral Interface (LPSPI)
- Chapters 56-57 Debug Modules
- Chapter 56: Debug
- Chapter 57: JTAG Controller (JTAGC)
- Appendix A: Release Notes for Revision 7
- General changes
- About This Manual changes
- Introduction changes
- Memory map changes
- Signal multiplexing changes
- Security Overview changes
- Safety Overview changes
- CM0+ Overview changes
- CM4 Overview changes
- MTB changes
- MCM changes
- SIM changes
- PORT changes
- GPIO changes
- AXBS-Lite changes
- MPU changes
- AIPS-Lite changes
- DMAMUX changes
- eDMA changes
- TRGMUX changes
- EWM changes
- EIM changes
- ERM changes
- WDOG changes
- CRC module changes
- Reset and Boot changes
- RCM changes
- Clock Distribution changes
- SCG changes
- PCC changes
- CMU changes
- Memories and memory interfaces changes
- PRAMC changes
- LMEM changes
- MSCM changes
- FMC changes
- FTFC changes
- QSPI changes
- Power Management changes
- SMC changes
- PMC changes
- ADC Configuration changes
- ADC changes
- CMP changes
- PDB changes
- FTM changes
- LPIT changes
- LPTMR changes
- RTC changes
- LPSPI changes
- LPI2C changes
- LPUART changes
- FlexIO changes
- FlexCAN changes
- SAI changes
- ENETchanges
- Debug changes
- JTAGC changes
- Contents