S32K1XXRM, S32K1xx Series Reference Manual S32K

S32K_ReferenceManual

User Manual:

Open the PDF directly: View PDF PDF.
Page Count: 2013 [warning: Documents this large are best viewed by clicking the View PDF Link!]

S32K1xx Series Reference Manual
Supports S32K116, S32K118, S32K142, S32K144, S32K146, and
S32K148
Document Number: S32K1XXRM
Rev. 7, 04/2018
S32K1xx Series Reference Manual, Rev. 7, 04/2018
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 49
1.2 Organization..................................................................................................................................................................49
1.3 Module descriptions......................................................................................................................................................49
1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 50
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 51
1.4 Register descriptions.....................................................................................................................................................52
1.5 Conventions.................................................................................................................................................................. 53
1.5.1 Notes, Cautions, and Warnings......................................................................................................................53
1.5.2 Numbering systems........................................................................................................................................53
1.5.3 Typographic notation..................................................................................................................................... 54
1.5.4 Special terms..................................................................................................................................................54
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................57
2.2 S32K1xx Series introduction........................................................................................................................................57
2.2.1 S32K14x.........................................................................................................................................................57
2.2.2 S32K11x ........................................................................................................................................................59
2.3 Feature summary...........................................................................................................................................................60
2.4 Block diagram...............................................................................................................................................................63
2.5 Feature comparison.......................................................................................................................................................64
2.6 Applications..................................................................................................................................................................66
2.7 Module functional categories........................................................................................................................................67
2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................68
2.7.2 Arm Cortex-M0+ Core Modules....................................................................................................................69
2.7.3 System modules............................................................................................................................................. 69
2.7.4 Memories and memory interfaces..................................................................................................................70
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 3
Section number Title Page
2.7.5 Power Management........................................................................................................................................71
2.7.6 Clocking.........................................................................................................................................................71
2.7.7 Analog modules............................................................................................................................................. 72
2.7.8 Timer modules............................................................................................................................................... 72
2.7.9 Communication interfaces............................................................................................................................. 73
2.7.10 Debug modules.............................................................................................................................................. 73
Chapter 3
Memory Map
3.1 Introduction...................................................................................................................................................................75
3.2 SRAM memory map.....................................................................................................................................................75
3.2.1 S32K14x: SRAM memory map ....................................................................................................................75
3.2.2 S32K11x: SRAM memory map ....................................................................................................................75
3.3 Flash memory map........................................................................................................................................................76
3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................76
3.4.1 Read-after-write sequence and required serialization of memory operations................................................77
3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................78
3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 79
Chapter 4
Signal Multiplexing and Pin Assignment
4.1 Introduction...................................................................................................................................................................81
4.2 Functional description...................................................................................................................................................81
4.3 Pad description..............................................................................................................................................................82
4.4 Default pad state........................................................................................................................................................... 83
4.5 Signal Multiplexing sheet............................................................................................................................................. 84
4.5.1 IO Signal Table ............................................................................................................................................. 84
4.5.2 Input muxing table......................................................................................................................................... 86
4.6 Pinout diagrams............................................................................................................................................................ 87
Chapter 5
Security Overview
5.1 Introduction...................................................................................................................................................................89
S32K1xx Series Reference Manual, Rev. 7, 04/2018
4 NXP Semiconductors
Section number Title Page
5.2 Device security..............................................................................................................................................................89
5.2.1 Flash memory security...................................................................................................................................89
5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................90
5.2.3 Device Boot modes........................................................................................................................................ 91
5.3 Security use case examples...........................................................................................................................................91
5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 91
5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 92
5.3.3 Secure communication...................................................................................................................................93
5.3.4 Component protection....................................................................................................................................94
5.3.5 Message-authentication example................................................................................................................... 95
5.4 Steps required before failure analysis...........................................................................................................................96
5.5 Security programming flow example (Secure Boot).................................................................................................... 97
Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................99
6.2 S32K1xx safety concept............................................................................................................................................... 100
6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................101
6.2.2 ECC on RAM and flash memory...................................................................................................................102
6.2.3 Power supply monitoring...............................................................................................................................102
6.2.4 Clock monitoring........................................................................................................................................... 103
6.2.5 Temporal protection.......................................................................................................................................103
6.2.6 Operational interference protection............................................................................................................... 103
6.2.7 CRC................................................................................................................................................................105
6.2.8 Diversity of system resources........................................................................................................................ 105
Chapter 7
CM4 Overview
7.1 Arm Cortex-M4F core configuration............................................................................................................................107
7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 108
7.1.2 System Tick Timer.........................................................................................................................................108
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 5
Section number Title Page
7.1.3 Debug facilities.............................................................................................................................................. 108
7.1.4 Caches............................................................................................................................................................ 109
7.1.5 Core privilege levels...................................................................................................................................... 109
7.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 110
7.2.1 Interrupt priority levels.................................................................................................................................. 110
7.2.2 Non-maskable interrupt..................................................................................................................................111
7.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 111
7.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................112
7.3.1 Wake-up sources............................................................................................................................................112
7.4 FPU configuration.........................................................................................................................................................113
7.5 JTAG controller configuration......................................................................................................................................114
Chapter 8
CM0+ Overview
8.1 Arm Cortex-M0+ core introduction..............................................................................................................................115
8.1.1 Buses, interconnects, and interfaces.............................................................................................................. 116
8.1.2 System tick timer........................................................................................................................................... 116
8.1.3 Debug facilities.............................................................................................................................................. 116
8.1.4 Core privilege levels...................................................................................................................................... 116
8.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................117
8.2.1 Interrupt priority levels.................................................................................................................................. 117
8.2.2 Non-maskable interrupt..................................................................................................................................117
8.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 117
8.3 AWIC introduction....................................................................................................................................................... 118
8.3.1 Wake-up sources............................................................................................................................................118
Chapter 9
Micro Trace Buffer (MTB)
9.1 Introduction...................................................................................................................................................................121
9.1.1 Overview........................................................................................................................................................121
9.1.2 Features.......................................................................................................................................................... 123
S32K1xx Series Reference Manual, Rev. 7, 04/2018
6 NXP Semiconductors
Section number Title Page
9.1.3 Modes of operation........................................................................................................................................ 124
9.2 Memory map and register definition.............................................................................................................................124
9.2.1 MTB_DWT Memory Map.............................................................................................................................125
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Chip-specific MCM information.................................................................................................................................. 135
10.2 Introduction...................................................................................................................................................................136
10.2.1 Features.......................................................................................................................................................... 136
10.3 Memory map/register descriptions............................................................................................................................... 136
10.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................137
10.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 138
10.3.3 Core Platform Control Register (MCM_CPCR)............................................................................................139
10.3.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 142
10.3.5 Process ID Register (MCM_PID)..................................................................................................................145
10.3.6 Compute Operation Control Register (MCM_CPO)..................................................................................... 146
10.3.7 Local Memory Descriptor Register (MCM_LMDRn)...................................................................................147
10.3.8 Local Memory Descriptor Register2 (MCM_LMDR2).................................................................................150
10.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR).......................................................................154
10.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)...................................................................... 155
10.3.11 LMEM Fault Address Register (MCM_LMFAR).........................................................................................156
10.3.12 LMEM Fault Attribute Register (MCM_LMFATR).....................................................................................157
10.3.13 LMEM Fault Data High Register (MCM_LMFDHR).................................................................................. 158
10.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)....................................................................................158
10.4 Functional description...................................................................................................................................................159
10.4.1 Interrupts........................................................................................................................................................ 159
Chapter 11
System Integration Module (SIM)
11.1 Chip-specific SIM information.....................................................................................................................................161
11.1.1 SIM register bitfield implementation.............................................................................................................161
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 7
Section number Title Page
11.2 Introduction...................................................................................................................................................................161
11.2.1 Features.......................................................................................................................................................... 161
11.3 Memory map and register definition.............................................................................................................................162
11.3.1 SIM register descriptions............................................................................................................................... 162
Chapter 12
Port Control and Interrupts (PORT)
12.1 Chip-specific PORT information..................................................................................................................................189
12.1.1 Number of PCRs............................................................................................................................................ 189
12.1.2 I/O configuration sequence ........................................................................................................................... 190
12.1.3 Digital input filter configuration sequence ................................................................................................... 190
12.2 Introduction...................................................................................................................................................................191
12.3 Overview.......................................................................................................................................................................191
12.3.1 Features.......................................................................................................................................................... 192
12.3.2 Modes of operation........................................................................................................................................ 192
12.4 External signal description............................................................................................................................................193
12.5 Detailed signal description............................................................................................................................................193
12.6 Memory map and register definition.............................................................................................................................194
12.6.1 Pin Control Register n (PORT_PCRn).......................................................................................................... 196
12.6.2 Global Pin Control Low Register (PORT_GPCLR)......................................................................................199
12.6.3 Global Pin Control High Register (PORT_GPCHR).....................................................................................199
12.6.4 Global Interrupt Control Low Register (PORT_GICLR)..............................................................................200
12.6.5 Global Interrupt Control High Register (PORT_GICHR).............................................................................200
12.6.6 Interrupt Status Flag Register (PORT_ISFR)................................................................................................ 201
12.6.7 Digital Filter Enable Register (PORT_DFER).............................................................................................. 202
12.6.8 Digital Filter Clock Register (PORT_DFCR)................................................................................................202
12.6.9 Digital Filter Width Register (PORT_DFWR).............................................................................................. 203
12.7 Functional description...................................................................................................................................................203
12.7.1 Pin control......................................................................................................................................................203
12.7.2 Global pin control.......................................................................................................................................... 204
S32K1xx Series Reference Manual, Rev. 7, 04/2018
8 NXP Semiconductors
Section number Title Page
12.7.3 Global interrupt control..................................................................................................................................205
12.7.4 External interrupts..........................................................................................................................................205
12.7.5 Digital filter....................................................................................................................................................206
Chapter 13
General-Purpose Input/Output (GPIO)
13.1 Chip-specific GPIO information...................................................................................................................................207
13.1.1 Instantiation information................................................................................................................................207
13.1.2 GPIO ports memory map............................................................................................................................... 207
13.1.3 GPIO register reset values .............................................................................................................................208
13.2 Introduction...................................................................................................................................................................208
13.2.1 Features.......................................................................................................................................................... 209
13.2.2 Modes of operation........................................................................................................................................ 209
13.2.3 GPIO signal descriptions............................................................................................................................... 209
13.3 Memory map and register definition.............................................................................................................................210
13.3.1 GPIO register descriptions.............................................................................................................................211
13.4 Functional description...................................................................................................................................................218
13.4.1 General-purpose input....................................................................................................................................218
13.4.2 General-purpose output..................................................................................................................................218
Chapter 14
Crossbar Switch Lite (AXBS-Lite)
14.1 Chip-specific AXBS-Lite information..........................................................................................................................221
14.1.1 Crossbar Switch master assignments............................................................................................................. 221
14.1.2 Crossbar Switch slave assignments................................................................................................................221
14.2 Introduction...................................................................................................................................................................222
14.2.1 Features.......................................................................................................................................................... 222
14.3 Functional Description..................................................................................................................................................223
14.3.1 General operation...........................................................................................................................................223
14.3.2 Arbitration......................................................................................................................................................223
14.4 Initialization/application information........................................................................................................................... 225
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 9
Section number Title Page
Chapter 15
Memory Protection Unit (MPU)
15.1 Chip-specific MPU information................................................................................................................................... 227
15.1.1 MPU Slave Port Assignments........................................................................................................................227
15.1.2 MPU Logical Bus Master Assignments.........................................................................................................228
15.1.3 Current PID....................................................................................................................................................228
15.1.4 Region descriptors and slave port configuration............................................................................................228
15.2 Introduction...................................................................................................................................................................229
15.3 Overview.......................................................................................................................................................................229
15.3.1 Block diagram................................................................................................................................................229
15.3.2 Features.......................................................................................................................................................... 230
15.4 MPU register descriptions.............................................................................................................................................231
15.4.1 MPU Memory map........................................................................................................................................ 231
15.4.2 Control/Error Status Register (CESR)........................................................................................................... 234
15.4.3 Error Address Register, slave port n (EAR0 - EAR4)................................................................................... 236
15.4.4 Error Detail Register, slave port n (EDR0 - EDR4)...................................................................................... 237
15.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)...........................................................239
15.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)...........................................................................................240
15.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)...........................................................................................241
15.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...........................................................................................244
15.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)...........................................................245
15.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)...........................................................246
15.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)...........................................................249
15.4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)....................................................................... 251
15.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)...............................................254
15.5 Functional description...................................................................................................................................................257
15.5.1 Access evaluation macro................................................................................................................................257
15.5.2 Putting it all together and error terminations................................................................................................. 259
15.5.3 Power management........................................................................................................................................259
S32K1xx Series Reference Manual, Rev. 7, 04/2018
10 NXP Semiconductors
Section number Title Page
15.6 Initialization information.............................................................................................................................................. 260
15.7 Application information................................................................................................................................................260
Chapter 16
Peripheral Bridge (AIPS-Lite)
16.1 Chip-specific AIPS information................................................................................................................................... 263
16.1.1 Instantiation information................................................................................................................................263
16.1.2 Memory maps................................................................................................................................................ 263
16.2 Introduction...................................................................................................................................................................264
16.2.1 Features.......................................................................................................................................................... 265
16.2.2 General operation...........................................................................................................................................265
16.3 Memory map/register definition................................................................................................................................... 265
16.3.1 AIPS register descriptions..............................................................................................................................265
16.4 Functional description...................................................................................................................................................309
16.4.1 Access support............................................................................................................................................... 309
Chapter 17
Direct Memory Access Multiplexer (DMAMUX)
17.1 Chip-specific DMAMUX information......................................................................................................................... 311
17.1.1 Number of channels ...................................................................................................................................... 311
17.1.2 DMA transfers via TRGMUX trigger............................................................................................................311
17.2 Introduction...................................................................................................................................................................312
17.2.1 Overview........................................................................................................................................................312
17.2.2 Features.......................................................................................................................................................... 312
17.2.3 Modes of operation........................................................................................................................................ 313
17.3 Memory map/register definition................................................................................................................................... 313
17.3.1 DMAMUX register descriptions....................................................................................................................313
17.4 Functional description...................................................................................................................................................315
17.4.1 DMA channels with periodic triggering capability........................................................................................315
17.4.2 DMA channels with no triggering capability.................................................................................................318
17.4.3 Always-enabled DMA sources...................................................................................................................... 318
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 11
Section number Title Page
17.5 Initialization/application information........................................................................................................................... 319
17.5.1 Reset...............................................................................................................................................................319
17.5.2 Enabling and configuring sources..................................................................................................................319
Chapter 18
Enhanced Direct Memory Access (eDMA)
18.1 Chip-specific eDMA information ................................................................................................................................323
18.1.1 Number of channels ...................................................................................................................................... 323
18.2 Introduction...................................................................................................................................................................324
18.2.1 eDMA system block diagram........................................................................................................................ 324
18.2.2 Block parts..................................................................................................................................................... 325
18.2.3 Features.......................................................................................................................................................... 326
18.3 Modes of operation....................................................................................................................................................... 327
18.4 Memory map/register definition................................................................................................................................... 327
18.4.1 TCD memory................................................................................................................................................. 327
18.4.2 TCD initialization.......................................................................................................................................... 328
18.4.3 TCD structure.................................................................................................................................................328
18.4.4 Reserved memory and bit fields.....................................................................................................................328
18.4.5 DMA register descriptions.............................................................................................................................329
18.5 Functional description...................................................................................................................................................378
18.5.1 eDMA basic data flow................................................................................................................................... 378
18.5.2 Fault reporting and handling..........................................................................................................................380
18.5.3 Channel preemption....................................................................................................................................... 383
18.6 Initialization/application information........................................................................................................................... 384
18.6.1 eDMA initialization....................................................................................................................................... 384
18.6.2 Programming errors....................................................................................................................................... 386
18.6.3 Arbitration mode considerations....................................................................................................................386
18.6.4 Performing DMA transfers............................................................................................................................ 387
18.6.5 Monitoring transfer descriptor status............................................................................................................. 391
18.6.6 Channel Linking.............................................................................................................................................393
S32K1xx Series Reference Manual, Rev. 7, 04/2018
12 NXP Semiconductors
Section number Title Page
18.6.7 Dynamic programming.................................................................................................................................. 394
18.6.8 Suspend/resume a DMA channel with active hardware service requests......................................................397
Chapter 19
Trigger MUX Control (TRGMUX)
19.1 Chip-specific TRGMUX information...........................................................................................................................399
19.1.1 Module interconnectivity............................................................................................................................... 399
19.1.2 TRGMUX register information..................................................................................................................... 403
19.2 Introduction...................................................................................................................................................................403
19.3 Features.........................................................................................................................................................................403
19.4 Memory map and register definition.............................................................................................................................404
19.4.1 TRGMUX register descriptions.....................................................................................................................404
Chapter 20
External Watchdog Monitor (EWM)
20.1 Chip-specific EWM information ................................................................................................................................. 443
20.1.1 EWM_OUT signal configuration...................................................................................................................443
20.1.2 EWM Memory Map access............................................................................................................................443
20.1.3 EWM low-power modes................................................................................................................................ 443
20.2 Introduction...................................................................................................................................................................443
20.2.1 Features.......................................................................................................................................................... 444
20.2.2 Modes of Operation....................................................................................................................................... 444
20.2.3 Block Diagram............................................................................................................................................... 445
20.3 EWM Signal Descriptions............................................................................................................................................ 446
20.4 Memory Map/Register Definition.................................................................................................................................447
20.4.1 EWM register descriptions.............................................................................................................................447
20.5 Functional Description..................................................................................................................................................452
20.5.1 The EWM_OUT_b Signal............................................................................................................................. 452
20.5.2 EWM_OUT_b pin state in low power modes................................................................................................453
20.5.3 The EWM_in Signal...................................................................................................................................... 453
20.5.4 EWM Counter................................................................................................................................................454
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 13
Section number Title Page
20.5.5 EWM Compare Registers.............................................................................................................................. 454
20.5.6 EWM Refresh Mechanism.............................................................................................................................454
20.5.7 EWM Interrupt...............................................................................................................................................455
20.5.8 Counter clock prescaler..................................................................................................................................455
Chapter 21
Error Injection Module (EIM)
21.1 Chip-specific EIM information.....................................................................................................................................457
21.1.1 EIM channel assignments.............................................................................................................................. 457
21.2 Introduction...................................................................................................................................................................457
21.2.1 Overview........................................................................................................................................................457
21.2.2 Features.......................................................................................................................................................... 459
21.3 EIM register descriptions..............................................................................................................................................459
21.3.1 EIM Memory map..........................................................................................................................................460
21.3.2 Error Injection Module Configuration Register (EIMCR)............................................................................ 460
21.3.3 Error Injection Channel Enable register (EICHEN)...................................................................................... 461
21.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)............................464
21.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)............................466
21.4 Functional description...................................................................................................................................................467
21.4.1 Error injection scenarios................................................................................................................................ 467
Chapter 22
Error Reporting Module (ERM)
22.1 Chip-specific ERM information................................................................................................................................... 469
22.1.1 Sources of memory error events.................................................................................................................... 469
22.2 Introduction...................................................................................................................................................................469
22.2.1 Overview........................................................................................................................................................469
22.2.2 Features.......................................................................................................................................................... 470
22.3 ERM register descriptions.............................................................................................................................................470
22.3.1 ERM Memory map........................................................................................................................................ 470
22.3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 471
S32K1xx Series Reference Manual, Rev. 7, 04/2018
14 NXP Semiconductors
Section number Title Page
22.3.3 ERM Status Register 0 (SR0)........................................................................................................................ 473
22.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 475
22.4 Functional description...................................................................................................................................................476
22.4.1 Single-bit correction events........................................................................................................................... 476
22.4.2 Non-correctable error events..........................................................................................................................477
22.5 Initialization..................................................................................................................................................................478
Chapter 23
Watchdog timer (WDOG)
23.1 Chip-specific WDOG information................................................................................................................................479
23.1.1 WDOG clocks................................................................................................................................................479
23.1.2 WDOG low-power modes............................................................................................................................. 479
23.1.3 Default watchdog timeout .............................................................................................................................480
23.2 Introduction...................................................................................................................................................................480
23.2.1 Features.......................................................................................................................................................... 480
23.2.2 Block diagram................................................................................................................................................481
23.3 Memory map and register definition.............................................................................................................................482
23.3.1 WDOG register descriptions..........................................................................................................................482
23.4 Functional description...................................................................................................................................................488
23.4.1 Clock source...................................................................................................................................................488
23.4.2 Watchdog refresh mechanism........................................................................................................................489
23.4.3 Configuring the Watchdog.............................................................................................................................491
23.4.4 Using interrupts to delay resets......................................................................................................................492
23.4.5 Backup reset...................................................................................................................................................492
23.4.6 Functionality in debug and low-power modes...............................................................................................493
23.4.7 Fast testing of the watchdog...........................................................................................................................493
23.5 Application Information................................................................................................................................................495
23.5.1 Disable Watchdog..........................................................................................................................................495
23.5.2 Disable Watchdog after Reset........................................................................................................................495
23.5.3 Configure Watchdog......................................................................................................................................496
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 15
Section number Title Page
23.5.4 Refreshing the Watchdog...............................................................................................................................496
Chapter 24
Cyclic Redundancy Check (CRC)
24.1 Chip-specific CRC information....................................................................................................................................497
24.2 Introduction...................................................................................................................................................................497
24.2.1 Features.......................................................................................................................................................... 497
24.2.2 Block diagram................................................................................................................................................498
24.2.3 Modes of operation........................................................................................................................................ 498
24.3 Memory map and register descriptions.........................................................................................................................498
24.3.1 CRC register descriptions.............................................................................................................................. 498
24.4 Functional description...................................................................................................................................................503
24.4.1 CRC initialization/reinitialization..................................................................................................................503
24.4.2 CRC calculations............................................................................................................................................503
24.4.3 Transpose feature........................................................................................................................................... 504
24.4.4 CRC result complement.................................................................................................................................506
Chapter 25
Reset and Boot
25.1 Introduction...................................................................................................................................................................507
25.2 Reset..............................................................................................................................................................................507
25.2.1 Power-on reset (POR).................................................................................................................................... 508
25.2.2 System reset sources...................................................................................................................................... 508
25.2.3 MCU Resets................................................................................................................................................... 511
25.2.4 Reset pin ........................................................................................................................................................512
25.2.5 Debug resets...................................................................................................................................................513
25.3 Boot...............................................................................................................................................................................514
25.3.1 Boot sources...................................................................................................................................................514
25.3.2 FOPT boot options.........................................................................................................................................514
25.3.3 Boot sequence................................................................................................................................................ 515
Chapter 26
Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
16 NXP Semiconductors
Section number Title Page
26.1 Chip-specific RCM information................................................................................................................................... 517
26.1.1 RCM register information .............................................................................................................................517
26.2 Reset pin filter operation in STOP1/2 modes .............................................................................................................. 517
26.3 Introduction...................................................................................................................................................................518
26.4 Reset memory map and register descriptions............................................................................................................... 518
26.4.1 Version ID Register (RCM_VERID).............................................................................................................518
26.4.2 Parameter Register (RCM_PARAM)............................................................................................................ 520
26.4.3 System Reset Status Register (RCM_SRS)................................................................................................... 522
26.4.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 525
26.4.5 Sticky System Reset Status Register (RCM_SSRS)......................................................................................527
26.4.6 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 529
Chapter 27
Clock Distribution
27.1 Introduction...................................................................................................................................................................533
27.2 High level clocking diagram.........................................................................................................................................533
27.3 Clock definitions...........................................................................................................................................................534
27.4 Internal clocking requirements..................................................................................................................................... 536
27.4.1 Clock divider values after reset......................................................................................................................539
27.4.2 HSRUN mode clocking................................................................................................................................. 540
27.4.3 VLPR mode clocking.....................................................................................................................................540
27.4.4 VLPR/VLPS mode entry............................................................................................................................... 540
27.5 Clock Gating.................................................................................................................................................................541
27.6 Module clocks...............................................................................................................................................................541
Chapter 28
System Clock Generator (SCG)
28.1 Chip-specific SCG information.................................................................................................................................... 553
28.1.1 Supported frequency ranges...........................................................................................................................553
28.1.2 Oscillator and SPLL guidelines..................................................................................................................... 554
28.1.3 System clock switching .................................................................................................................................554
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 17
Section number Title Page
28.1.4 System clock and clock monitor requirement ...............................................................................................555
28.2 Introduction...................................................................................................................................................................555
28.2.1 Features.......................................................................................................................................................... 555
28.3 Memory Map/Register Definition.................................................................................................................................556
28.3.1 Version ID Register (SCG_VERID)..............................................................................................................558
28.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 558
28.3.3 Clock Status Register (SCG_CSR)................................................................................................................559
28.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................561
28.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................564
28.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................566
28.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................568
28.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................569
28.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 571
28.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 572
28.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................574
28.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 575
28.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................576
28.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 577
28.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................579
28.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 580
28.3.17 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 581
28.3.18 System PLL Divide Register (SCG_SPLLDIV)............................................................................................583
28.3.19 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 584
28.4 Functional description...................................................................................................................................................586
28.4.1 SCG Clock Mode Transitions........................................................................................................................586
Chapter 29
Peripheral Clock Controller (PCC)
29.1 Chip-specific PCC information.....................................................................................................................................589
29.1.1 PCC register information............................................................................................................................... 589
S32K1xx Series Reference Manual, Rev. 7, 04/2018
18 NXP Semiconductors
Section number Title Page
29.2 Introduction...................................................................................................................................................................592
29.3 Features.........................................................................................................................................................................592
29.4 Functional description...................................................................................................................................................593
29.5 Memory map and register definition.............................................................................................................................594
29.6 PCC register descriptions..............................................................................................................................................594
29.6.1 PCC Memory map......................................................................................................................................... 594
29.6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 595
29.6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 597
29.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 598
29.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 600
29.6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 601
29.6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................603
29.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 604
29.6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................606
29.6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................607
29.6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................609
29.6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................610
29.6.13 PCC CRC Register (PCC_CRC)....................................................................................................................612
29.6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................613
29.6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................615
29.6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 616
29.6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 618
29.6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 619
29.6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................621
29.6.20 PCC RTC Register (PCC_RTC)....................................................................................................................623
29.6.21 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................624
29.6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 626
29.6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................628
29.6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................629
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 19
Section number Title Page
29.6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 631
29.6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 632
29.6.27 PCC SAI0 Register (PCC_SAI0)...................................................................................................................634
29.6.28 PCC SAI1 Register (PCC_SAI1)...................................................................................................................635
29.6.29 PCC FlexIO Register (PCC_FlexIO).............................................................................................................637
29.6.30 PCC EWM Register (PCC_EWM)................................................................................................................638
29.6.31 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 640
29.6.32 PCC LPI2C1 Register (PCC_LPI2C1).......................................................................................................... 641
29.6.33 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 643
29.6.34 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 644
29.6.35 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 646
29.6.36 PCC FTM4 Register (PCC_FTM4)............................................................................................................... 648
29.6.37 PCC FTM5 Register (PCC_FTM5)............................................................................................................... 649
29.6.38 PCC FTM6 Register (PCC_FTM6)............................................................................................................... 651
29.6.39 PCC FTM7 Register (PCC_FTM7)............................................................................................................... 653
29.6.40 PCC CMP0 Register (PCC_CMP0)...............................................................................................................654
29.6.41 PCC QSPI Register (PCC_QSPI).................................................................................................................. 656
29.6.42 PCC ENET Register (PCC_ENET)............................................................................................................... 657
Chapter 30
Clock Monitoring Unit (CMU)
30.1 CMU chip-specific information....................................................................................................................................661
30.2 Introduction...................................................................................................................................................................663
30.2.1 Basic operation...............................................................................................................................................663
30.2.2 Features.......................................................................................................................................................... 664
30.3 CMU_FC register descriptions..................................................................................................................................... 665
30.3.1 CMU_FC Memory map.................................................................................................................................665
30.3.2 Global Configuration Register (GCR)........................................................................................................... 665
30.3.3 Reference Count Configuration Register (RCCR).........................................................................................666
30.3.4 High Threshold Configuration Register (HTCR).......................................................................................... 667
S32K1xx Series Reference Manual, Rev. 7, 04/2018
20 NXP Semiconductors
Section number Title Page
30.3.5 Low Threshold Configuration Register (LTCR)........................................................................................... 668
30.3.6 Status Register (SR).......................................................................................................................................669
30.3.7 Interrupt Enable Register (IER)..................................................................................................................... 671
30.4 Functional description...................................................................................................................................................673
30.4.1 Monitored clock lost...................................................................................................................................... 673
30.5 Programming guidelines...............................................................................................................................................674
30.5.1 Programming HFREF and LFREF................................................................................................................ 674
30.5.2 Programming RCCR[REF_CNT]..................................................................................................................674
30.5.3 CMU_FC programming sequence................................................................................................................. 675
Chapter 31
Memories and Memory Interfaces
31.1 Introduction...................................................................................................................................................................677
31.2 Flash Memory Controller and flash memory modules................................................................................................. 677
31.3 SRAM configuration.....................................................................................................................................................677
31.3.1 SRAM sizes....................................................................................................................................................678
31.3.2 SRAM accessibility........................................................................................................................................679
31.3.3 SRAM arbitration and priority control...........................................................................................................680
31.3.4 SRAM retention: power modes and resets.....................................................................................................680
Chapter 32
PRAM Controller (PRAMC)
32.1 PRAMC chip-specific information ..............................................................................................................................683
32.2 Introduction...................................................................................................................................................................683
32.3 Memory map and register definition.............................................................................................................................684
32.4 Functional description...................................................................................................................................................684
32.4.1 Error Correcting Code (ECC)........................................................................................................................ 684
32.4.2 Read/Write introduction.................................................................................................................................685
32.4.3 Reads..............................................................................................................................................................685
32.4.4 Writes.............................................................................................................................................................686
32.4.5 Late write hits.................................................................................................................................................687
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 21
Section number Title Page
32.5 Initialization / application information......................................................................................................................... 688
Chapter 33
Local Memory Controller (LMEM)
33.1 Chip-specific LMEM information ............................................................................................................................... 689
33.1.1 LMEM region description..............................................................................................................................689
33.1.2 LMEM SRAM sizes.......................................................................................................................................689
33.2 Introduction...................................................................................................................................................................689
33.2.1 Block Diagram............................................................................................................................................... 690
33.2.2 Cache features................................................................................................................................................691
33.3 Memory Map/Register Definition.................................................................................................................................693
33.3.1 LMEM register descriptions.......................................................................................................................... 693
33.4 Functional Description..................................................................................................................................................702
33.4.1 LMEM Function............................................................................................................................................ 702
33.4.2 SRAM Function............................................................................................................................................. 703
33.4.3 Cache Function.............................................................................................................................................. 705
33.4.4 Cache Control................................................................................................................................................ 706
Chapter 34
Miscellaneous System Control Module (MSCM)
34.1 Chip-specific MSCM information................................................................................................................................711
34.1.1 Chip-specific TMLSZ/TMUSZ information................................................................................................. 711
34.1.2 Chip-specific register information................................................................................................................. 711
34.2 Overview.......................................................................................................................................................................712
34.3 Chip Configuration and Boot........................................................................................................................................712
34.4 MSCM Memory Map/Register Definition....................................................................................................................712
34.4.1 CPU Configuration Memory Map and Registers...........................................................................................712
34.4.2 MSCM register descriptions.......................................................................................................................... 713
Chapter 35
Flash Memory Controller (FMC)
35.1 Chip-specific FMC information....................................................................................................................................745
35.1.1 FMC masters..................................................................................................................................................745
S32K1xx Series Reference Manual, Rev. 7, 04/2018
22 NXP Semiconductors
Section number Title Page
35.1.2 Program flash and Data flash port width....................................................................................................... 746
35.2 Introduction...................................................................................................................................................................746
35.2.1 Overview........................................................................................................................................................746
35.2.2 Features.......................................................................................................................................................... 746
35.3 Modes of operation....................................................................................................................................................... 747
35.4 External signal description............................................................................................................................................747
35.5 Functional description...................................................................................................................................................747
35.5.1 Default configuration..................................................................................................................................... 747
35.5.2 Speculative reads............................................................................................................................................748
35.6 Initialization and application information.....................................................................................................................749
Chapter 36
Flash Memory Module (FTFC)
36.1 Chip-specific FTFC information...................................................................................................................................751
36.1.1 Flash memory types....................................................................................................................................... 751
36.1.2 Flash memory sizes........................................................................................................................................752
36.1.3 Flash memory map.........................................................................................................................................771
36.1.4 Flash memory security...................................................................................................................................771
36.1.5 Power mode restrictions on flash memory programming..............................................................................772
36.1.6 Flash memory modes..................................................................................................................................... 772
36.1.7 Erase all contents of flash memory................................................................................................................772
36.1.8 Customize MCU operations via FTFC_FOPT register..................................................................................772
36.1.9 Simultaneous operations on PFLASH read partitions .................................................................................. 772
36.2 Introduction...................................................................................................................................................................773
36.2.1 Features.......................................................................................................................................................... 774
36.2.2 Block diagram................................................................................................................................................776
36.2.3 Glossary......................................................................................................................................................... 776
36.3 External signal description............................................................................................................................................779
36.4 Memory map and registers............................................................................................................................................779
36.4.1 Flash configuration field description............................................................................................................. 779
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 23
Section number Title Page
36.4.2 Program flash 0 IFR map...............................................................................................................................779
36.4.3 Data flash 0 IFR map..................................................................................................................................... 780
36.4.4 Register descriptions......................................................................................................................................781
36.5 Functional description...................................................................................................................................................799
36.5.1 Flash protection..............................................................................................................................................799
36.5.2 FlexNVM description.................................................................................................................................... 801
36.5.3 Interrupts........................................................................................................................................................ 804
36.5.4 Flash operation in low-power modes.............................................................................................................805
36.5.5 Functional modes of operation.......................................................................................................................805
36.5.6 Flash memory reads and ignored writes........................................................................................................ 805
36.5.7 Read while write (RWW).............................................................................................................................. 806
36.5.8 Flash program and erase................................................................................................................................ 806
36.5.9 FTFC command operations............................................................................................................................806
36.5.10 Margin read commands..................................................................................................................................813
36.5.11 Flash command descriptions..........................................................................................................................814
36.5.12 Security.......................................................................................................................................................... 840
36.5.13 Cryptographic Services Engine (CSEc).........................................................................................................842
36.5.14 Reset sequence............................................................................................................................................... 880
Chapter 37
Quad Serial Peripheral Interface (QuadSPI)
37.1 Chip-specific QuadSPI information..............................................................................................................................881
37.1.1 Overview........................................................................................................................................................881
37.1.2 Memory size requirement ............................................................................................................................. 881
37.1.3 QuadSPI register reset values........................................................................................................................ 881
37.1.4 Use case..........................................................................................................................................................882
37.1.5 Supported read modes....................................................................................................................................882
37.1.6 External memory options...............................................................................................................................883
37.1.7 Recommended software configuration.......................................................................................................... 883
37.1.8 Recommended programming sequence......................................................................................................... 884
S32K1xx Series Reference Manual, Rev. 7, 04/2018
24 NXP Semiconductors
Section number Title Page
37.1.9 Clock ratio between QuadSPI clocks ............................................................................................................884
37.1.10 QuadSPI_MCR[SCLKCFG] implementation ...............................................................................................884
37.1.11 QuadSPI_SOCCR[SOCCFG] implementation .............................................................................................885
37.2 Introduction...................................................................................................................................................................887
37.2.1 Features.......................................................................................................................................................... 887
37.2.2 Block Diagram............................................................................................................................................... 888
37.2.3 QuadSPI Modes of Operation........................................................................................................................889
37.2.4 Acronyms and Abbreviations.........................................................................................................................890
37.2.5 Glossary for QuadSPI module....................................................................................................................... 890
37.3 External Signal Description.......................................................................................................................................... 892
37.3.1 Driving External Signals................................................................................................................................893
37.4 Memory Map and Register Definition..........................................................................................................................895
37.4.1 Register Write Access....................................................................................................................................895
37.4.2 Peripheral Bus Register Descriptions............................................................................................................ 896
37.4.3 Serial Flash Address Assignment.................................................................................................................. 939
37.5 Flash memory mapped AMBA bus.............................................................................................................................. 940
37.5.1 AHB Bus Access Considerations...................................................................................................................941
37.5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A.....................................................941
37.5.3 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B..................................................... 942
37.5.4 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31).......................................................................... 943
37.6 Interrupt Signals............................................................................................................................................................945
37.7 Functional Description..................................................................................................................................................946
37.7.1 Serial Flash Access Schemes......................................................................................................................... 946
37.7.2 Normal Mode................................................................................................................................................. 946
37.7.3 HyperRAM Support.......................................................................................................................................965
37.8 Initialization/Application Information..........................................................................................................................966
37.8.1 Power Up and Reset.......................................................................................................................................966
37.8.2 Available Status/Flag Information.................................................................................................................966
37.8.3 Exclusive Access to Serial Flash for AHB Commands................................................................................. 969
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 25
Section number Title Page
37.8.4 Command Arbitration ................................................................................................................................... 970
37.8.5 Flash Device Selection...................................................................................................................................971
37.8.6 DMA Usage................................................................................................................................................... 971
37.9 Byte Ordering - Endianness..........................................................................................................................................975
37.9.1 Programming Flash Data............................................................................................................................... 976
37.9.2 Reading Flash Data into the RX Buffer.........................................................................................................977
37.9.3 Reading Flash Data into the AHB Buffer...................................................................................................... 978
37.10 Driving Flash Control Signals in Single and Dual Mode............................................................................................. 978
37.11 Serial Flash Devices......................................................................................................................................................979
37.11.1 Example Sequences........................................................................................................................................979
37.12 Sampling of Serial Flash Input Data.............................................................................................................................985
37.12.1 Basic Description........................................................................................................................................... 985
37.12.2 Supported read modes....................................................................................................................................986
37.12.3 Data Strobe (DQS) sampling method............................................................................................................ 988
37.13 Data Input Hold Requirement of Flash.........................................................................................................................992
Chapter 38
Power Management
38.1 Introduction...................................................................................................................................................................993
38.2 Power modes description.............................................................................................................................................. 993
38.3 Entering and exiting power modes............................................................................................................................... 995
38.4 Clocking modes............................................................................................................................................................ 995
38.4.1 Clock gating................................................................................................................................................... 995
38.4.2 Stop mode options..........................................................................................................................................995
38.4.3 DMA wake-up................................................................................................................................................996
38.4.4 Compute Operation (CPO).............................................................................................................................997
38.4.5 Peripheral Doze..............................................................................................................................................998
38.5 Power mode transitions.................................................................................................................................................999
38.6 Shutdown sequencing for power modes....................................................................................................................... 1000
38.7 Power mode restrictions on flash memory programming.............................................................................................1000
S32K1xx Series Reference Manual, Rev. 7, 04/2018
26 NXP Semiconductors
Section number Title Page
38.8 Module operation in available low power modes.........................................................................................................1001
38.9 QuadSPI, Ethernet, and SAI operation ........................................................................................................................ 1005
Chapter 39
System Mode Controller (SMC)
39.1 Introduction...................................................................................................................................................................1007
39.2 Modes of operation....................................................................................................................................................... 1007
39.3 Memory map and register descriptions.........................................................................................................................1009
39.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................1010
39.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 1011
39.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................1012
39.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................1013
39.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................1015
39.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 1017
39.4 Functional description...................................................................................................................................................1017
39.4.1 Power mode transitions..................................................................................................................................1018
39.4.2 Power mode entry/exit sequencing................................................................................................................ 1019
39.4.3 Run modes......................................................................................................................................................1021
39.4.4 Stop modes.....................................................................................................................................................1024
39.4.5 Debug in low power modes........................................................................................................................... 1025
Chapter 40
Power Management Controller (PMC)
40.1 Chip-specific PMC information....................................................................................................................................1027
40.1.1 Modes supported............................................................................................................................................1027
40.2 Introduction...................................................................................................................................................................1027
40.3 Features.........................................................................................................................................................................1027
40.4 Modes of Operation...................................................................................................................................................... 1027
40.4.1 Full Performance Mode (FPM)......................................................................................................................1027
40.4.2 Low Power Mode (LPM)...............................................................................................................................1028
40.5 Low Voltage Detect (LVD) System............................................................................................................................. 1028
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 27
Section number Title Page
40.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 1028
40.5.2 LVD Interrupt Operation............................................................................................................................... 1029
40.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 1029
40.6 Memory Map and Register Definition..........................................................................................................................1029
40.6.1 PMC register descriptions..............................................................................................................................1029
Chapter 41
ADC Configuration
41.1 Instantiation information...............................................................................................................................................1037
41.1.1 Number of ADC channels..............................................................................................................................1037
41.1.2 ADC Connections/Channel Assignment........................................................................................................1038
41.2 Register implementation...............................................................................................................................................1039
41.3 DMA Support on ADC.................................................................................................................................................1039
41.4 ADC Hardware Interleaved Channels.......................................................................................................................... 1040
41.5 ADC internal supply monitoring.................................................................................................................................. 1041
41.6 ADC Reference Options............................................................................................................................................... 1041
41.7 ADC Trigger Sources................................................................................................................................................... 1041
41.7.1 PDB triggering scheme.................................................................................................................................. 1043
41.7.2 TRGMUX trigger scheme..............................................................................................................................1044
41.8 Trigger Selection...........................................................................................................................................................1045
41.9 Trigger Latching and Arbitration..................................................................................................................................1046
41.10 ADC triggering configurations .................................................................................................................................... 1048
41.11 ADC low-power modes................................................................................................................................................ 1055
41.12 ADC Trigger Concept – Use Case................................................................................................................................1055
41.13 ADC calibration scheme...............................................................................................................................................1057
Chapter 42
Analog-to-Digital Converter (ADC)
42.1 Chip-specific ADC information....................................................................................................................................1059
42.2 Introduction...................................................................................................................................................................1059
42.2.1 Features.......................................................................................................................................................... 1059
S32K1xx Series Reference Manual, Rev. 7, 04/2018
28 NXP Semiconductors
Section number Title Page
42.2.2 Block diagram................................................................................................................................................1060
42.3 ADC signal descriptions............................................................................................................................................... 1061
42.3.1 Analog Power (VDDA)................................................................................................................................. 1061
42.3.2 Analog Ground (VSSA).................................................................................................................................1061
42.3.3 Voltage Reference Select...............................................................................................................................1061
42.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 1062
42.4 ADC register descriptions.............................................................................................................................................1062
42.4.1 ADC Memory map.........................................................................................................................................1062
42.4.2 ADC Status and Control Register 1 (SC1A - aSC1P)................................................................................... 1064
42.4.3 ADC Configuration Register 1 (CFG1).........................................................................................................1068
42.4.4 ADC Configuration Register 2 (CFG2).........................................................................................................1069
42.4.5 ADC Data Result Registers (RA - aRP)........................................................................................................ 1070
42.4.6 Compare Value Registers (CV1 - CV2)........................................................................................................ 1072
42.4.7 Status and Control Register 2 (SC2)..............................................................................................................1073
42.4.8 Status and Control Register 3 (SC3)..............................................................................................................1076
42.4.9 BASE Offset Register (BASE_OFS).............................................................................................................1077
42.4.10 ADC Offset Correction Register (OFS).........................................................................................................1078
42.4.11 USER Offset Correction Register (USR_OFS)............................................................................................. 1079
42.4.12 ADC X Offset Correction Register (XOFS)..................................................................................................1080
42.4.13 ADC Y Offset Correction Register (YOFS)..................................................................................................1081
42.4.14 ADC Gain Register (G)..................................................................................................................................1082
42.4.15 ADC User Gain Register (UG)...................................................................................................................... 1084
42.4.16 ADC General Calibration Value Register S (CLPS)..................................................................................... 1085
42.4.17 ADC Plus-Side General Calibration Value Register 3 (CLP3)..................................................................... 1086
42.4.18 ADC Plus-Side General Calibration Value Register 2 (CLP2)..................................................................... 1087
42.4.19 ADC Plus-Side General Calibration Value Register 1 (CLP1)..................................................................... 1087
42.4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..................................................................... 1088
42.4.21 ADC Plus-Side General Calibration Value Register X (CLPX)....................................................................1089
42.4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..................................................................... 1090
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 29
Section number Title Page
42.4.23 ADC General Calibration Offset Value Register S (CLPS_OFS).................................................................1091
42.4.24 ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS).................................................1092
42.4.25 ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS).................................................1093
42.4.26 ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS).................................................1094
42.4.27 ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS).................................................1095
42.4.28 ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)............................................... 1096
42.4.29 ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS).................................................1097
42.4.30 ADC Status and Control Register 1 (SC1AA - SC1Z).................................................................................. 1098
42.4.31 ADC Data Result Registers (RAA - RZ).......................................................................................................1101
42.5 Functional description...................................................................................................................................................1102
42.5.1 Clock select and divide control......................................................................................................................1102
42.5.2 Voltage reference selection............................................................................................................................1103
42.5.3 Hardware trigger and channel selects............................................................................................................ 1103
42.5.4 Conversion control.........................................................................................................................................1104
42.5.5 Automatic compare function..........................................................................................................................1108
42.5.6 Calibration function....................................................................................................................................... 1109
42.5.7 User-defined offset function.......................................................................................................................... 1110
42.5.8 MCU Normal Stop mode operation...............................................................................................................1111
Chapter 43
Comparator (CMP)
43.1 Chip-specific CMP information....................................................................................................................................1113
43.1.1 Instantiation information................................................................................................................................1113
43.1.2 CMP input connections..................................................................................................................................1113
43.1.3 CMP external references................................................................................................................................1114
43.1.4 External window/sample input.......................................................................................................................1114
43.1.5 CMP trigger mode..........................................................................................................................................1114
43.1.6 Programming recommendation......................................................................................................................1115
43.2 Introduction...................................................................................................................................................................1115
43.3 Features.........................................................................................................................................................................1116
S32K1xx Series Reference Manual, Rev. 7, 04/2018
30 NXP Semiconductors
Section number Title Page
43.3.1 CMP features..................................................................................................................................................1116
43.3.2 8-bit DAC key features.................................................................................................................................. 1117
43.3.3 ANMUX key features.................................................................................................................................... 1117
43.4 CMP, DAC, and ANMUX diagram..............................................................................................................................1117
43.5 CMP block diagram......................................................................................................................................................1118
43.6 CMP pin descriptions....................................................................................................................................................1120
43.6.1 External pins.................................................................................................................................................. 1120
43.7 CMP functional modes................................................................................................................................................. 1121
43.7.1 Disabled mode (# 1).......................................................................................................................................1122
43.7.2 Continuous mode (#s 2A & 2B).................................................................................................................... 1122
43.7.3 Sampled, Non-Filtered mode (#s 3A & 3B).................................................................................................. 1123
43.7.4 Sampled, Filtered mode (#s 4A & 4B).......................................................................................................... 1125
43.7.5 Windowed mode (#s 5A & 5B)..................................................................................................................... 1127
43.7.6 Windowed/Resampled mode (# 6).................................................................................................................1129
43.7.7 Windowed/Filtered mode (#7).......................................................................................................................1130
43.8 Memory map/register definitions..................................................................................................................................1131
43.8.1 CMP Control Register 0 (CMP_C0)..............................................................................................................1131
43.8.2 CMP Control Register 1 (CMP_C1)..............................................................................................................1135
43.8.3 CMP Control Register 2 (CMP_C2)..............................................................................................................1138
43.9 CMP functional description..........................................................................................................................................1140
43.9.1 Initialization................................................................................................................................................... 1140
43.9.2 Low-pass filter............................................................................................................................................... 1141
43.10 Interrupts.......................................................................................................................................................................1143
43.11 DMA support................................................................................................................................................................ 1143
43.12 DAC functional description.......................................................................................................................................... 1144
43.12.1 Digital-to-analog converter block diagram....................................................................................................1144
43.12.2 DAC resets..................................................................................................................................................... 1144
43.12.3 DAC clocks....................................................................................................................................................1145
43.12.4 DAC interrupts...............................................................................................................................................1145
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 31
Section number Title Page
43.13 Trigger mode.................................................................................................................................................................1145
Chapter 44
Programmable delay block (PDB)
44.1 Chip-specific PDB information.................................................................................................................................... 1149
44.1.1 Instantiation Information................................................................................................................................1149
44.1.2 PDB trigger interconnections with ADC and TRGMUX.............................................................................. 1150
44.1.3 Back-to-back acknowledgement connections................................................................................................1150
44.1.4 Pulse-Out Enable Register Implementation...................................................................................................1157
44.2 Introduction...................................................................................................................................................................1157
44.2.1 Features.......................................................................................................................................................... 1157
44.2.2 Implementation.............................................................................................................................................. 1158
44.2.3 Back-to-back acknowledgment connections..................................................................................................1158
44.2.4 Block diagram................................................................................................................................................1159
44.2.5 Modes of operation........................................................................................................................................ 1160
44.3 Memory map and register definition.............................................................................................................................1160
44.3.1 Status and Control register (PDB_SC)...........................................................................................................1162
44.3.2 Modulus register (PDB_MOD)......................................................................................................................1165
44.3.3 Counter register (PDB_CNT)........................................................................................................................ 1166
44.3.4 Interrupt Delay register (PDB_IDLY)........................................................................................................... 1166
44.3.5 Channel n Control register 1 (PDB_CHnC1)................................................................................................ 1167
44.3.6 Channel n Status register (PDB_CHnS)........................................................................................................ 1168
44.3.7 Channel n Delay 0 register (PDB_CHnDLY0)..............................................................................................1168
44.3.8 Channel n Delay 1 register (PDB_CHnDLY1)..............................................................................................1169
44.3.9 Channel n Delay 2 register (PDB_CHnDLY2)..............................................................................................1170
44.3.10 Channel n Delay 3 register (PDB_CHnDLY3)..............................................................................................1170
44.3.11 Channel n Delay 4 register (PDB_CHnDLY4)..............................................................................................1171
44.3.12 Channel n Delay 5 register (PDB_CHnDLY5)..............................................................................................1172
44.3.13 Channel n Delay 6 register (PDB_CHnDLY6)..............................................................................................1172
44.3.14 Channel n Delay 7 register (PDB_CHnDLY7)..............................................................................................1173
S32K1xx Series Reference Manual, Rev. 7, 04/2018
32 NXP Semiconductors
Section number Title Page
44.3.15 Pulse-Out n Enable register (PDB_POEN)....................................................................................................1173
44.3.16 Pulse-Out n Delay register (PDB_POnDLY)................................................................................................ 1174
44.4 Functional description...................................................................................................................................................1174
44.4.1 PDB pre-trigger and trigger outputs...............................................................................................................1174
44.4.2 PDB trigger input source selection................................................................................................................ 1177
44.4.3 Pulse-Out's..................................................................................................................................................... 1177
44.4.4 Updating the delay registers...........................................................................................................................1178
44.4.5 Interrupts........................................................................................................................................................ 1180
44.4.6 DMA.............................................................................................................................................................. 1180
44.5 Application information................................................................................................................................................1180
44.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................... 1180
Chapter 45
FlexTimer Module (FTM)
45.1 Chip-specific FTM information....................................................................................................................................1183
45.1.1 Instantiation Information................................................................................................................................1183
45.1.2 FTM Interrupts...............................................................................................................................................1184
45.1.3 FTM Fault Detection Inputs...........................................................................................................................1184
45.1.4 FTM Hardware Triggers and Synchronization.............................................................................................. 1186
45.1.5 FTM Input Capture Options...........................................................................................................................1188
45.1.6 FTM Hall sensor support............................................................................................................................... 1189
45.1.7 FTM Modulation Implementation................................................................................................................. 1189
45.1.8 FTM Global Time Base................................................................................................................................. 1190
45.1.9 FTM BDM and debug halt mode...................................................................................................................1191
45.2 Introduction...................................................................................................................................................................1191
45.2.1 FlexTimer philosophy....................................................................................................................................1191
45.2.2 Features.......................................................................................................................................................... 1192
45.2.3 Modes of operation........................................................................................................................................ 1194
45.2.4 Block Diagram............................................................................................................................................... 1194
45.3 FTM signal descriptions............................................................................................................................................... 1197
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 33
Section number Title Page
45.4 Memory map and register definition.............................................................................................................................1197
45.4.1 Memory map..................................................................................................................................................1197
45.4.2 Register descriptions......................................................................................................................................1198
45.4.3 FTM register descriptions.............................................................................................................................. 1198
45.5 Functional Description..................................................................................................................................................1255
45.5.1 Clock source...................................................................................................................................................1255
45.5.2 Prescaler.........................................................................................................................................................1256
45.5.3 Counter...........................................................................................................................................................1256
45.5.4 Channel Modes.............................................................................................................................................. 1262
45.5.5 Input Capture Mode....................................................................................................................................... 1264
45.5.6 Output Compare mode...................................................................................................................................1269
45.5.7 Edge-Aligned PWM (EPWM) mode............................................................................................................. 1270
45.5.8 Center-Aligned PWM (CPWM) mode.......................................................................................................... 1272
45.5.9 Combine mode............................................................................................................................................... 1274
45.5.10 Modified Combine PWM Mode.................................................................................................................... 1282
45.5.11 Complementary Mode....................................................................................................................................1285
45.5.12 Registers updated from write buffers.............................................................................................................1286
45.5.13 PWM synchronization....................................................................................................................................1288
45.5.14 Inverting.........................................................................................................................................................1304
45.5.15 Software Output Control Mode......................................................................................................................1305
45.5.16 Deadtime insertion......................................................................................................................................... 1307
45.5.17 Output mask................................................................................................................................................... 1311
45.5.18 Fault Control.................................................................................................................................................. 1312
45.5.19 Polarity Control..............................................................................................................................................1316
45.5.20 Initialization................................................................................................................................................... 1317
45.5.21 Features Priority.............................................................................................................................................1317
45.5.22 External Trigger............................................................................................................................................. 1318
45.5.23 Initialization Trigger...................................................................................................................................... 1319
45.5.24 Capture Test Mode.........................................................................................................................................1321
S32K1xx Series Reference Manual, Rev. 7, 04/2018
34 NXP Semiconductors
Section number Title Page
45.5.25 DMA.............................................................................................................................................................. 1322
45.5.26 Dual Edge Capture Mode...............................................................................................................................1323
45.5.27 Quadrature Decoder Mode.............................................................................................................................1331
45.5.28 Debug mode................................................................................................................................................... 1337
45.5.29 Reload Points................................................................................................................................................. 1338
45.5.30 Global Load....................................................................................................................................................1341
45.5.31 Global time base (GTB).................................................................................................................................1342
45.5.32 Channel trigger output................................................................................................................................... 1343
45.5.33 External Control of Channels Output.............................................................................................................1344
45.5.34 Dithering........................................................................................................................................................ 1344
45.6 Reset Overview.............................................................................................................................................................1355
45.7 FTM Interrupts..............................................................................................................................................................1357
45.7.1 Timer Overflow Interrupt...............................................................................................................................1357
45.7.2 Reload Point Interrupt....................................................................................................................................1357
45.7.3 Channel (n) Interrupt......................................................................................................................................1357
45.7.4 Fault Interrupt................................................................................................................................................ 1357
45.8 Initialization Procedure.................................................................................................................................................1358
Chapter 46
Low Power Interrupt Timer (LPIT)
46.1 Chip-specific LPIT information....................................................................................................................................1361
46.1.1 Instantiation Information................................................................................................................................1361
46.1.2 LPIT/DMA Periodic Trigger Assignments ...................................................................................................1361
46.1.3 LPIT input triggers ........................................................................................................................................1362
46.1.4 LPIT/ADC Trigger.........................................................................................................................................1362
46.2 Introduction...................................................................................................................................................................1363
46.2.1 Overview........................................................................................................................................................1363
46.2.2 Block Diagram............................................................................................................................................... 1365
46.3 Modes of operation....................................................................................................................................................... 1366
46.4 Memory Map and Registers..........................................................................................................................................1367
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 35
Section number Title Page
46.4.1 LPIT register descriptions..............................................................................................................................1367
46.5 Functional description...................................................................................................................................................1383
46.5.1 LPIT programming model............................................................................................................................. 1383
46.5.2 Initialization................................................................................................................................................... 1384
46.5.3 Timer Modes..................................................................................................................................................1385
46.5.4 Trigger Control for Timers............................................................................................................................ 1386
46.5.5 Channel Chaining...........................................................................................................................................1387
46.5.6 Detailed timing...............................................................................................................................................1387
Chapter 47
Low Power Timer (LPTMR)
47.1 Chip-specific LPTMR information...............................................................................................................................1401
47.1.1 Instantiation Information................................................................................................................................1401
47.1.2 LPTMR pulse counter input options..............................................................................................................1401
47.2 Introduction...................................................................................................................................................................1402
47.2.1 Features.......................................................................................................................................................... 1402
47.2.2 Modes of operation........................................................................................................................................ 1402
47.3 LPTMR signal descriptions.......................................................................................................................................... 1403
47.3.1 Detailed signal descriptions........................................................................................................................... 1403
47.4 Memory map and register definition.............................................................................................................................1403
47.4.1 LPTMR register descriptions.........................................................................................................................1404
47.5 Functional description...................................................................................................................................................1409
47.5.1 LPTMR power and reset................................................................................................................................1409
47.5.2 LPTMR clocking............................................................................................................................................1409
47.5.3 LPTMR prescaler/glitch filter........................................................................................................................1410
47.5.4 LPTMR compare............................................................................................................................................1411
47.5.5 LPTMR counter............................................................................................................................................. 1411
47.5.6 LPTMR hardware trigger...............................................................................................................................1412
47.5.7 LPTMR interrupt............................................................................................................................................1412
Chapter 48
S32K1xx Series Reference Manual, Rev. 7, 04/2018
36 NXP Semiconductors
Section number Title Page
Real Time Clock (RTC)
48.1 Chip-specific RTC information.................................................................................................................................... 1415
48.1.1 RTC instantiation........................................................................................................................................... 1415
48.1.2 RTC interrupts ...............................................................................................................................................1415
48.1.3 Software recommendation............................................................................................................................. 1415
48.2 Introduction...................................................................................................................................................................1415
48.2.1 Features.......................................................................................................................................................... 1416
48.2.2 Modes of operation........................................................................................................................................ 1416
48.2.3 RTC signal descriptions.................................................................................................................................1416
48.3 Register definition.........................................................................................................................................................1417
48.3.1 RTC register descriptions...............................................................................................................................1417
48.4 Functional description...................................................................................................................................................1427
48.4.1 Power, clocking, and reset............................................................................................................................. 1427
48.4.2 Time counter.................................................................................................................................................. 1428
48.4.3 Compensation.................................................................................................................................................1429
48.4.4 Time alarm..................................................................................................................................................... 1430
48.4.5 Update mode.................................................................................................................................................. 1430
48.4.6 Register lock.................................................................................................................................................. 1430
48.4.7 Interrupt..........................................................................................................................................................1430
Chapter 49
Low Power Serial Peripheral Interface (LPSPI)
49.1 Chip-specific LPSPI information..................................................................................................................................1433
49.1.1 Instantiation Information................................................................................................................................1433
49.2 Introduction...................................................................................................................................................................1434
49.2.1 Features.......................................................................................................................................................... 1436
49.2.2 Block Diagram............................................................................................................................................... 1436
49.2.3 Modes of operation........................................................................................................................................ 1437
49.2.4 Signal Descriptions........................................................................................................................................ 1437
49.2.5 Wiring options................................................................................................................................................1438
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 37
Section number Title Page
49.3 Memory Map and Registers..........................................................................................................................................1440
49.3.1 LPSPI register descriptions............................................................................................................................1440
49.4 Functional description...................................................................................................................................................1463
49.4.1 Clocking and resets........................................................................................................................................ 1463
49.4.2 Master Mode.................................................................................................................................................. 1464
49.4.3 Slave Mode.................................................................................................................................................... 1470
49.4.4 Interrupts and DMA Requests........................................................................................................................1472
49.4.5 Peripheral Triggers.........................................................................................................................................1473
Chapter 50
Low Power Inter-Integrated Circuit (LPI2C)
50.1 Chip-specific LPI2C information................................................................................................................................. 1475
50.1.1 Instantiation information................................................................................................................................1475
50.2 Introduction...................................................................................................................................................................1476
50.2.1 Features.......................................................................................................................................................... 1477
50.2.2 Block Diagram............................................................................................................................................... 1479
50.2.3 Modes of operation........................................................................................................................................ 1479
50.2.4 Signal Descriptions........................................................................................................................................ 1480
50.2.5 Wiring options................................................................................................................................................1480
50.3 Memory Map and Registers..........................................................................................................................................1482
50.3.1 LPI2C register descriptions............................................................................................................................1483
50.4 Functional description...................................................................................................................................................1521
50.4.1 Clocking and Resets.......................................................................................................................................1521
50.4.2 Master Mode.................................................................................................................................................. 1522
50.4.3 Slave Mode.................................................................................................................................................... 1528
50.4.4 Interrupts and DMA Requests........................................................................................................................1530
50.4.5 Peripheral Triggers.........................................................................................................................................1532
Chapter 51
Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
51.1 Chip-specific LPUART information.............................................................................................................................1535
S32K1xx Series Reference Manual, Rev. 7, 04/2018
38 NXP Semiconductors
Section number Title Page
51.1.1 Instantiation Information................................................................................................................................1535
51.2 Introduction...................................................................................................................................................................1536
51.2.1 Features.......................................................................................................................................................... 1536
51.2.2 Modes of operation........................................................................................................................................ 1537
51.2.3 Signal Descriptions........................................................................................................................................ 1537
51.2.4 Block diagram................................................................................................................................................1537
51.3 Register definition.........................................................................................................................................................1539
51.3.1 LPUART register descriptions.......................................................................................................................1539
51.4 Functional description...................................................................................................................................................1565
51.4.1 Baud rate generation...................................................................................................................................... 1565
51.4.2 Transmitter functional description.................................................................................................................1566
51.4.3 Receiver functional description..................................................................................................................... 1569
51.4.4 Additional LPUART functions...................................................................................................................... 1576
51.4.5 Infrared interface............................................................................................................................................1578
51.4.6 Interrupts and status flags.............................................................................................................................. 1579
51.4.7 Peripheral Triggers.........................................................................................................................................1580
Chapter 52
Flexible I/O (FlexIO)
52.1 Chip-specific FlexIO information.................................................................................................................................1581
52.1.1 FlexIO Configuration.....................................................................................................................................1581
52.2 Introduction...................................................................................................................................................................1581
52.2.1 Overview........................................................................................................................................................1581
52.2.2 Features.......................................................................................................................................................... 1582
52.2.3 Block Diagram............................................................................................................................................... 1582
52.2.4 Modes of operation........................................................................................................................................ 1583
52.2.5 FlexIO Signal Descriptions............................................................................................................................1583
52.3 Memory Map and Registers..........................................................................................................................................1584
52.3.1 FLEXIO register descriptions........................................................................................................................ 1584
52.4 Functional description...................................................................................................................................................1608
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 39
Section number Title Page
52.4.1 Clocking and Resets.......................................................................................................................................1608
52.4.2 Shifter operation.............................................................................................................................................1609
52.4.3 Timer Operation.............................................................................................................................................1611
52.4.4 Pin operation.................................................................................................................................................. 1614
52.4.5 Interrupts and DMA Requests........................................................................................................................1615
52.4.6 Peripheral Triggers.........................................................................................................................................1616
52.5 Application Information................................................................................................................................................1616
52.5.1 UART Transmit............................................................................................................................................. 1616
52.5.2 UART Receive...............................................................................................................................................1617
52.5.3 SPI Master......................................................................................................................................................1619
52.5.4 SPI Slave........................................................................................................................................................1621
52.5.5 I2C Master......................................................................................................................................................1623
52.5.6 I2S Master......................................................................................................................................................1625
52.5.7 I2S Slave........................................................................................................................................................ 1626
Chapter 53
FlexCAN
53.1 Chip-specific FlexCAN information.............................................................................................................................1629
53.1.1 Instantiation information................................................................................................................................1629
53.1.2 Reset value of MDIS bit.................................................................................................................................1630
53.1.3 FlexCAN external time tick .......................................................................................................................... 1630
53.1.4 FlexCAN Interrupts........................................................................................................................................1630
53.1.5 FlexCAN Operation in Low Power Modes....................................................................................................1631
53.1.6 FlexCAN oscillator clock...............................................................................................................................1631
53.1.7 Supported baud rate ...................................................................................................................................... 1631
53.1.8 Requirements for entering FlexCAN modes: Freeze, Disable, Stop............................................................. 1631
53.2 Introduction...................................................................................................................................................................1633
53.2.1 Overview........................................................................................................................................................1634
53.2.2 FlexCAN module features............................................................................................................................. 1635
53.2.3 Modes of operation........................................................................................................................................ 1637
S32K1xx Series Reference Manual, Rev. 7, 04/2018
40 NXP Semiconductors
Section number Title Page
53.3 FlexCAN signal descriptions........................................................................................................................................1639
53.3.1 CAN Rx .........................................................................................................................................................1639
53.3.2 CAN Tx .........................................................................................................................................................1639
53.4 Memory map/register definition................................................................................................................................... 1639
53.4.1 FlexCAN memory mapping...........................................................................................................................1639
53.4.2 CAN register descriptions..............................................................................................................................1641
53.4.3 Message buffer structure................................................................................................................................1712
53.4.4 FlexCAN Memory Partition for CAN FD..................................................................................................... 1718
53.4.5 FlexCAN message buffer memory map.........................................................................................................1719
53.4.6 Rx FIFO structure.......................................................................................................................................... 1722
53.5 Functional description...................................................................................................................................................1724
53.5.1 Transmit process............................................................................................................................................ 1725
53.5.2 Arbitration process.........................................................................................................................................1726
53.5.3 Receive process..............................................................................................................................................1730
53.5.4 Matching process........................................................................................................................................... 1732
53.5.5 Receive Process under Pretended Networking Mode....................................................................................1737
53.5.6 Move process................................................................................................................................................. 1741
53.5.7 Data coherence...............................................................................................................................................1743
53.5.8 Rx FIFO......................................................................................................................................................... 1746
53.5.9 CAN protocol related features....................................................................................................................... 1749
53.5.10 Clock domains and restrictions......................................................................................................................1770
53.5.11 Modes of operation details.............................................................................................................................1774
53.5.12 Interrupts........................................................................................................................................................ 1778
53.5.13 Bus interface.................................................................................................................................................. 1779
53.6 Initialization/application information........................................................................................................................... 1780
53.6.1 FlexCAN initialization sequence................................................................................................................... 1780
Chapter 54
Synchronous Audio Interface (SAI)
54.1 Chip-specific SAI information .....................................................................................................................................1783
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 41
Section number Title Page
54.1.1 SAI configuration...........................................................................................................................................1783
54.1.2 Chip-specific register information................................................................................................................. 1784
54.2 Introduction...................................................................................................................................................................1785
54.2.1 Features.......................................................................................................................................................... 1785
54.2.2 Block diagram................................................................................................................................................1785
54.2.3 Modes of operation........................................................................................................................................ 1786
54.3 External signals.............................................................................................................................................................1786
54.4 Memory map and register definition.............................................................................................................................1787
54.4.1 I2S register descriptions.................................................................................................................................1787
54.5 Functional description...................................................................................................................................................1817
54.5.1 SAI clocking.................................................................................................................................................. 1817
54.5.2 SAI resets....................................................................................................................................................... 1818
54.5.3 Synchronous modes....................................................................................................................................... 1819
54.5.4 Frame sync configuration...............................................................................................................................1820
54.5.5 Data FIFO...................................................................................................................................................... 1820
54.5.6 Word mask register........................................................................................................................................ 1824
54.5.7 Interrupts and DMA requests.........................................................................................................................1825
Chapter 55
Ethernet MAC (ENET)
55.1 Chip-specific ENET information..................................................................................................................................1829
55.1.1 Software guideline during ENET operation...................................................................................................1829
55.2 Introduction...................................................................................................................................................................1829
55.3 Overview.......................................................................................................................................................................1830
55.3.1 Features.......................................................................................................................................................... 1830
55.3.2 Block diagram................................................................................................................................................1833
55.4 External signal description............................................................................................................................................1833
55.5 Memory map/register definition................................................................................................................................... 1835
55.5.1 Interrupt Event Register (ENET_EIR)...........................................................................................................1840
55.5.2 Interrupt Mask Register (ENET_EIMR)........................................................................................................1843
S32K1xx Series Reference Manual, Rev. 7, 04/2018
42 NXP Semiconductors
Section number Title Page
55.5.3 Receive Descriptor Active Register (ENET_RDAR)....................................................................................1846
55.5.4 Transmit Descriptor Active Register (ENET_TDAR)...................................................................................1847
55.5.5 Ethernet Control Register (ENET_ECR).......................................................................................................1848
55.5.6 MII Management Frame Register (ENET_MMFR)...................................................................................... 1850
55.5.7 MII Speed Control Register (ENET_MSCR)................................................................................................ 1850
55.5.8 MIB Control Register (ENET_MIBC).......................................................................................................... 1853
55.5.9 Receive Control Register (ENET_RCR)....................................................................................................... 1854
55.5.10 Transmit Control Register (ENET_TCR)......................................................................................................1857
55.5.11 Physical Address Lower Register (ENET_PALR)........................................................................................ 1859
55.5.12 Physical Address Upper Register (ENET_PAUR)........................................................................................ 1859
55.5.13 Opcode/Pause Duration Register (ENET_OPD)........................................................................................... 1860
55.5.14 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................... 1860
55.5.15 Descriptor Individual Lower Address Register (ENET_IALR).................................................................... 1861
55.5.16 Descriptor Group Upper Address Register (ENET_GAUR).........................................................................1861
55.5.17 Descriptor Group Lower Address Register (ENET_GALR).........................................................................1862
55.5.18 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................... 1862
55.5.19 Receive Descriptor Ring Start Register (ENET_RDSR)...............................................................................1863
55.5.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR).................................................................. 1864
55.5.21 Maximum Receive Buffer Size Register (ENET_MRBR)............................................................................1865
55.5.22 Receive FIFO Section Full Threshold (ENET_RSFL)..................................................................................1866
55.5.23 Receive FIFO Section Empty Threshold (ENET_RSEM)............................................................................ 1866
55.5.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)............................................................................1867
55.5.25 Receive FIFO Almost Full Threshold (ENET_RAFL)..................................................................................1867
55.5.26 Transmit FIFO Section Empty Threshold (ENET_TSEM)........................................................................... 1868
55.5.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM)...........................................................................1868
55.5.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)................................................................................ 1869
55.5.29 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................... 1869
55.5.30 Frame Truncation Length (ENET_FTRL).....................................................................................................1870
55.5.31 Transmit Accelerator Function Configuration (ENET_TACC).................................................................... 1870
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 43
Section number Title Page
55.5.32 Receive Accelerator Function Configuration (ENET_RACC)......................................................................1871
55.5.33 Reserved Statistic Register (ENET_RMON_T_DROP)................................................................................1872
55.5.34 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS)............................................................ 1873
55.5.35 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)........................................................1873
55.5.36 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)........................................................1874
55.5.37 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN)............................ 1874
55.5.38 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)............1874
55.5.39 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)..........1875
55.5.40 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG).....................1875
55.5.41 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)........ 1876
55.5.42 Tx Collision Count Statistic Register (ENET_RMON_T_COL).................................................................. 1876
55.5.43 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................... 1876
55.5.44 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)............................................ 1877
55.5.45 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)........................................ 1877
55.5.46 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)........................................ 1878
55.5.47 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................... 1878
55.5.48 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047)................................ 1879
55.5.49 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048).......................... 1879
55.5.50 Tx Octets Statistic Register (ENET_RMON_T_OCTETS).......................................................................... 1879
55.5.51 Reserved Statistic Register (ENET_IEEE_T_DROP)...................................................................................1880
55.5.52 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK)................................................1880
55.5.53 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................... 1881
55.5.54 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).........................1881
55.5.55 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)....................................1881
55.5.56 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL)..................................1882
55.5.57 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL).....................1882
55.5.58 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)....................1883
55.5.59 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)....................... 1883
55.5.60 Reserved Statistic Register (ENET_IEEE_T_SQE)......................................................................................1883
S32K1xx Series Reference Manual, Rev. 7, 04/2018
44 NXP Semiconductors
Section number Title Page
55.5.61 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC)...............................1884
55.5.62 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK)...........1884
55.5.63 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS)............................................................1885
55.5.64 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)....................................................... 1885
55.5.65 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)....................................................... 1885
55.5.66 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)............................1886
55.5.67 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE)................................................................................................................1886
55.5.68 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE)...1887
55.5.69 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................... 1887
55.5.70 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)....... 1887
55.5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0).........................................................................1888
55.5.72 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)...................................................................1888
55.5.73 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)........................................... 1889
55.5.74 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)....................................... 1889
55.5.75 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)....................................... 1889
55.5.76 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................... 1890
55.5.77 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................... 1890
55.5.78 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)...........................1891
55.5.79 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)..........................................................................1891
55.5.80 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP).................................................1891
55.5.81 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................... 1892
55.5.82 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC)..............................................1892
55.5.83 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN)................................ 1893
55.5.84 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)..........................................1893
55.5.85 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC)...................................1893
55.5.86 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).........1894
55.5.87 Adjustable Timer Control Register (ENET_ATCR)..................................................................................... 1894
55.5.88 Timer Value Register (ENET_ATVR).......................................................................................................... 1896
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 45
Section number Title Page
55.5.89 Timer Offset Register (ENET_ATOFF)........................................................................................................1897
55.5.90 Timer Period Register (ENET_ATPER)........................................................................................................1897
55.5.91 Timer Correction Register (ENET_ATCOR)................................................................................................1898
55.5.92 Time-Stamping Clock Period Register (ENET_ATINC).............................................................................. 1898
55.5.93 Timestamp of Last Transmitted Frame (ENET_ATSTMP).......................................................................... 1899
55.5.94 Timer Global Status Register (ENET_TGSR)...............................................................................................1899
55.5.95 Timer Control Status Register (ENET_TCSRn)............................................................................................1900
55.5.96 Timer Compare Capture Register (ENET_TCCRn)......................................................................................1901
55.6 Functional description...................................................................................................................................................1902
55.6.1 Ethernet MAC frame formats........................................................................................................................ 1902
55.6.2 IP and higher layers frame format..................................................................................................................1905
55.6.3 IEEE 1588 message formats.......................................................................................................................... 1909
55.6.4 MAC receive..................................................................................................................................................1913
55.6.5 MAC transmit................................................................................................................................................ 1919
55.6.6 Full-duplex flow control operation................................................................................................................ 1923
55.6.7 Magic packet detection.................................................................................................................................. 1925
55.6.8 IP accelerator functions..................................................................................................................................1926
55.6.9 Resets and stop controls.................................................................................................................................1930
55.6.10 IEEE 1588 functions...................................................................................................................................... 1933
55.6.11 FIFO thresholds..............................................................................................................................................1937
55.6.12 Loopback options...........................................................................................................................................1940
55.6.13 Legacy buffer descriptors...............................................................................................................................1941
55.6.14 Enhanced buffer descriptors...........................................................................................................................1942
55.6.15 Client FIFO application interface.................................................................................................................. 1948
55.6.16 FIFO protection..............................................................................................................................................1951
55.6.17 Reference clock..............................................................................................................................................1953
55.6.18 PHY management interface........................................................................................................................... 1954
55.6.19 Ethernet interfaces..........................................................................................................................................1957
Chapter 56
S32K1xx Series Reference Manual, Rev. 7, 04/2018
46 NXP Semiconductors
Section number Title Page
Debug
56.1 Introduction...................................................................................................................................................................1963
56.2 CM4 and CM0+ ROM table......................................................................................................................................... 1966
56.3 Debug port.................................................................................................................................................................... 1967
56.3.1 JTAG-to-SWD change sequence................................................................................................................... 1968
56.4 Debug port pin descriptions..........................................................................................................................................1969
56.5 System TAP connection................................................................................................................................................1969
56.5.1 IR codes..........................................................................................................................................................1969
56.6 MDM-AP status and control registers.......................................................................................................................... 1970
56.6.1 MDM-AP Control Register............................................................................................................................1971
56.6.2 MDM-AP Status Register.............................................................................................................................. 1972
56.7 Debug resets..................................................................................................................................................................1973
56.8 AHB-AP........................................................................................................................................................................1974
56.9 ITM............................................................................................................................................................................... 1974
56.10 Core trace connectivity................................................................................................................................................. 1975
56.11 TPIU..............................................................................................................................................................................1975
56.12 DWT............................................................................................................................................................................. 1976
56.13 MTB .............................................................................................................................................................................1976
56.14 Debug in low-power modes..........................................................................................................................................1977
56.14.1 Debug module state in low-power modes......................................................................................................1977
56.15 Debug and security....................................................................................................................................................... 1978
Chapter 57
JTAG Controller (JTAGC)
57.1 Chip-specific JTAGC information................................................................................................................................1979
57.2 Introduction...................................................................................................................................................................1979
57.2.1 Block diagram................................................................................................................................................1979
57.2.2 Features.......................................................................................................................................................... 1980
57.2.3 Modes of operation........................................................................................................................................ 1980
57.3 External signal description............................................................................................................................................1982
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 47
Section number Title Page
57.3.1 Test clock input (TCK).................................................................................................................................. 1982
57.3.2 Test data input (TDI)......................................................................................................................................1982
57.3.3 Test data output (TDO)..................................................................................................................................1982
57.3.4 Test mode select (TMS).................................................................................................................................1983
57.4 Register description...................................................................................................................................................... 1983
57.4.1 Instruction register......................................................................................................................................... 1983
57.4.2 Bypass register............................................................................................................................................... 1983
57.4.3 Device identification register.........................................................................................................................1984
57.4.4 Boundary scan register...................................................................................................................................1984
57.5 Functional description...................................................................................................................................................1985
57.5.1 JTAGC reset configuration............................................................................................................................ 1985
57.5.2 IEEE 1149.1-2001 (JTAG) TAP....................................................................................................................1985
57.5.3 TAP controller state machine.........................................................................................................................1985
57.5.4 JTAGC block instructions..............................................................................................................................1988
57.5.5 Boundary scan................................................................................................................................................1991
57.6 Initialization/application information........................................................................................................................... 1991
S32K1xx Series Reference Manual, Rev. 7, 04/2018
48 NXP Semiconductors
Chapter 1
About This Manual
1.1 Audience
This reference manual is intended for system software and hardware developers and
applications programmers who want to develop products with this device. It assumes that
the reader understands operating systems, microprocessor system design, and basic
principles of software and hardware. The manual describes the functionality of the
superset device of the S32K1xx series. For the available features, register implementation
of a specific S32K1xx derivative (derivative device), please refer to the respective Chip-
specific module information.
NOTE
S32K116 and S32K118 specific information is preliminary
until these devices are qualified.
1.2 Organization
This manual has two main sets of chapters.
1. Chapters in the first set contain information that applies to all components on the
chip.
2. Chapters in the second set are organized into functional groupings that detail
particular areas of functionality.
• Examples of these groupings are clocking, timers, and communication interfaces.
• Each grouping includes chapters that provide a technical description of
individual modules.
1.3 Module descriptions
Each module chapter has two main parts:
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 49
•The first section, Chip-specific [module name] information, provides details such as
the number of module instances on the chip and connections between the module and
other modules. Read this section first because its content is crucial to understanding
the information in other sections of the chapter.
• The subsequent sections provide general information about the module, including its
signals, registers, and functional description.
Chapter 49
Enhanced Serial Communication Interface (eSCI)
49.1 Chip-specific eSCI information
This chip has six instances of the eSCI module. Some feature details vary between the
instances.
The following table summarizes the feature differences. The table does not list feature
details that the instances share.
Table 49-1. eSCI instance feature differences
Instance DMA support
eSCI_A and eSCI_B Yes
eSCI_C, eSCI_D, eSCI_E, and eSCI_F No: descriptions of eSCI DMA functionality do not apply to
these instances
NOTE
For eSCI_D, the single wire feature does not apply for TX/RX
via PCSA3 because this pad works only as an output.
49.2 Introduction
The eSCI block is an enhanced SCI block with a LIN master interface layer and DMA
support. The LIN master layer complies with the specifications LIN 1.3, LIN 2.0, LIN
2.1, and SAE J2602/1.
49.2.1 Bibliography
• LIN Specification Package Revision 1.3; December 12, 2002
• LIN Specification Package Revision 2.0; September 23, 2003
Sample Reference Manual
EXAMPLE
Chip-specific information
that should be read first
Beginning of general
module information
Figure 1-1. Example: chapter chip-specific information and general module information
1.3.1 Example: chip-specific information that clarifies content in
the same chapter
The example below shows chip-specific information that clarifies general module
information presented later in the chapter. In this case, the chip-specific register reset
values supercede the reset values that appear in the register diagram.
Module descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
50 NXP Semiconductors
Chapter 34
Software Watchdog Timer (SWT)
34.1 Chip-specific SWT information
This chip has two instances of the SWT module: SWT_A and SWT_B.
34.1.1 SWT register reset values
The following table identifies chip-specific reset values of SWT registers.
Table 34-1. Chip-specific SWT register reset values
Register SWT_A SWT_B
CR FF00_010Bh FF00_010Ah
TO 0005_FCD0h 0005_FCD0h
34.2 Introduction
Sample Reference Manual
This section provides an overview, list of features, and modes of operation for the SWT.
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system
lockup in situations such as software getting trapped in a loop or if a bus transaction fails
to terminate. When enabled, the SWT requires periodic execution of a watchdog
servicing operation. The servicing operation resets the timer to a specified time-out
period. If this servicing action does not occur before the timer expires the SWT generates
an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt
on an initial time-out. A reset is always generated on a second consecutive time-out.
34.2.1 Overview
accesses by masters without permission. If the RIA bit in the SWT_CR is set then the
SWT generates a system reset on an invalid access otherwise a bus error is generated. If
either the HLK or SLK bits in the SWT_CR are set, then the SWT_CR, SWT_TO,
SWT_WN, and SWT_SK registers are read-only.
The SWT memory map is shown in the following table.
SWT memory map
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
0 SWT Control Register (SWT_CR) 32 R/W See section 34.4.1/1331
4 SWT Interrupt Register (SWT_IR) 32 R/W 0000_0000h 34.4.2/1334
8 SWT Time-out Register (SWT_TO) 32 R/W See section 34.4.3/1334
C SWT Window Register (SWT_WN) 32 R/W 0000_0000h 34.4.4/1335
10 SWT Service Register (SWT_SR) 32 W 0000_0000h 34.4.5/1335
14 SWT Counter Output Register (SWT_CO) 32 R 0000_0000h 34.4.6/1336
18 SWT Service Key Register (SWT_SK) 32 R/W 0000_0000h 34.4.7/1336
34.4.1 SWT Control Register (SWT_CR)
NOTE
The reset value for the SWT_CR is implementation specific.
See the configuration information.
The SWT_CR contains fields for configuring and controlling the SWT.
This register is read-only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
Address: 0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MAP0
MAP1
MAP2
MAP3
MAP4
MAP5
MAP6
MAP7
0
W
Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
SMD RIA WND ITR HLK SLK CSL STP FRZ WEN
W
Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
The reset value for the SWT_CR is implementation specific. See the configuration information.•
Chapter 34 Software Watchdog Timer (SWT)
Sample Reference Manual
EXAMPLE
Figure 1-2. Example: chip-specific information that clarifies content in the same chapter
1.3.2 Example: chip-specific information that refers to a different
chapter
The chip-specific information below refers to another chapter's chip-specific information.
In this case, read both sets of chip-specific information before reading further in the
chapter.
Chapter 1 About This Manual
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 51
Chapter 10
Crossbar Integrity Checker (XBIC)
10.1 Chip-specific XBIC information
This chip has one instance of the XBIC module.
10.1.1 XBIC master and slave assignments
The XBIC identifies each XBAR master and slave in terms of the master or slave's
physical port number. See the "Physical master port" assignments in Table 9-1 and the
"Slave port" assignments in Table 9-2.
10.1.2 Unimplemented MCR and ESR fields
10.2 Overview
Sample Reference Manual
Chapter 9
Crossbar Switch (XBAR)
9.1 Chip-specific XBAR information
This chip has one instance of the XBAR module.
9.1.1 XBAR master and slave assignments
The following table lists the XBAR physical port numbers and logical IDs for all master
ports on this SoC.
• Each port number matches the default priority assigned to the corresponding physical
master port. This default priority equals the reset value of the priority field for each
master port in the PRSnregisters.
• A priority value of 0 is the highest priority. There is no "disabled" value for the
priority.
• A Nexus_3 module and core data bus share the same physical master port for each
core.
The logical master ID corresponds to the logical address provided by the master module
and is unique for each module. The logical master IDs are used by the bus masters
connected to the XBAR. The Nexus master is identified by setting the MSB in the 4-bit
field that supplies the master ID number.
Table 9-1. XBAR master ports and logical master IDs
Module Physical master port Logical master ID Comment
Core0 instruction 0 0
Core0 data 10
Nexus_3_0 8 Nexus_3_0 arbitrates with Core0 data for XBAR port 1
Core1 instruction 2 1
Core1 data 31
Nexus_3_1 9 Nexus_3_1 arbitrates with Core1 data for XBAR port 3
Table continues on the next page...
Sample Reference Manual
The Crossbar Integrity Checker (XBIC) verifies the integrity of the crossbar transfers.
For forward signals (master to slave), it is done by verifying the integrity of the attribute
information using an 8-bit Error Detection Code (EDC). The EDC detects any single- or
double-bit errors in the attribute information and signals the Fault Collection and Control
Unit (FCCU) when an error is detected. For feedback signals (slave to master), it is done
by comparing the consistency of the signals during the AHB dataphase.There are three
signals from slave to master, hready, hresp0, and hresp2. If any of the master signals is
different from the slave signals during dataphase, the error will be reported in the Error
Status Register.
On this chip, the MCR[SE5] and ESR[DPSE5] fields are not implemented. In XBIC
Module Control Register (XBIC_MCR) and XBIC Error Status Register (XBIC_ESR),
these fields are reserved.
EXAMPLE
Figure 1-3. Example: chip-specific information that refers to a different chapter
1.4 Register descriptions
Module chapters present register information in:
• Memory maps containing:
• An offset from the module's base address
• The name and acronym/abbreviation of each register
• The width of each register (in bits)
• Each register's reset value
• The page number on which each register is described
• Register figures
• Field-description tables
• Associated text
The register figures show the field structure using the conventions in the following figure.
Register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
52 NXP Semiconductors
R
WReserved
Reserved,
unimplemented
R
W1
Write-only one
0
R
W
Write-only zero
R
W
1
Read-only one
0
R
W
Read-only zero
R
W
Mnemonic
0
Read-only
writes zero
R
W
Mnemonic
1
Read-only
writes one
R
W
Mnemonic
Read-only
writes undefined
R
WMnemonic
Write-only
reads undefined
R
W
Mnemonic
w1c
Write one to clear
R
WMnemonic
Read/write
R
W
Mnemonic
Read-only
R
WMnemonic
Write-only
R
WMnemonic
0
Write-only
reads zero
R
WMnemonic
1
Write-only
reads one
Figure 1-4. Register figure conventions
Conventions
1.5.1 Notes, Cautions, and Warnings
Note, Caution, and Warning notices appear throughout this manual. Each notice type
alerts readers to a specific kind of information.
NOTE
Notes convey information that may be tangential to a topic or
that may not apply to all readers.
CAUTION
Caution notices call out information that readers should know
before taking further action. Cautions frequently point to
trouble spots that may damage the chip or board.
WARNING
Warning notices inform readers about actions that could result
in unwanted consequences, especially those that may cause
bodily injury.
1.5.2 Numbering systems
The following suffixes identify different numbering systems:
1.5
Chapter 1 About This Manual
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 53
This suffix Identifies a
b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases,
binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion
exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In
some cases, hexadecimal numbers are shown with the prefix 0x.
1.5.3 Typographic notation
The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.5.4 Special terms
The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
Table continues on the next page...
Conventions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
54 NXP Semiconductors
Term Meaning
reserved Refers to a memory space, register, field, or programming setting. Device operation is not
guaranteed when reserved locations are written to any value.
• Do not modify the default value of a reserved programming setting, such as the reset value of
a reserved register field.
• Consider undefined locations in memory to be reserved.
w1c Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared."
Chapter 1 About This Manual
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 55
Conventions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
56 NXP Semiconductors
Chapter 2
Introduction
2.1 Overview
The S32K1xx product series further extends the highly scalable portfolio of Arm®
Cortex®-M0+/M4F MCUs in the automotive industry. It builds on the legacy of the KEA
series, while introducing higher memory options alongside a richer peripheral set
extending capability into a variety of automotive applications. With a 2.70–5.5 V supply
and focus on automotive environment robustness, the S32K product series devices are
well suited to a wide range of applications in electrically harsh environments, and are
optimized for cost-sensitive applications offering low pin-count options. The S32K
product series offers a broad range of memory, peripherals, and package options. It shares
common peripherals and pin counts, allowing developers to migrate easily within an
MCU family or among the MCU families to take advantage of more memory or feature
integration. This scalability allows developers to use the S32K product series as the
standard for their end product platforms, maximizing hardware and software reuse and
reducing time to market.
S32K1xx Series introduction
2.2.1 S32K14x
S32K14x series of devices are 32-bit general purpose automotive microcontrollers based
on the Arm Cortex-M4F core. They offer superior performance, large memories and the
most scalable peripherals in this class. This product series provides up to 112 MHz CPU
performance with DSP and FPU support, with up to 2 MB Flash and up to 256 KB
SRAM. Overview of device features:
• 32-bit Arm Cortex-M4F core with FPU, up to 112 MHz (HSRUN) and 80 MHz
(Normal RUN)
2.2
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 57
• Up to 2 MB code flash memory and 64 KB FlexMem (supports up to 4 KB emulated
EEPROM 1 with 4 KB FlexRAM)
• Up to 256 KB SRAM supporting both CPU private access and crossbar access to
provide parallel access of instruction and data
• Modified Harvard connections with Local Memory controller (LMEM) to support
tightly coupled RAM and 4 KB Code Cache2
• Integrated clocking architecture with on-chip fast IRC 48-60 MHz, slow IRC 8
MHz / 2 MHz, 128 KHz LPO and a PLL unit
• Analog modules providing precision mixed-signal capabilities, including 12-bit up to
two 1 Msps SAR ADC, high-speed comparator
• Power Management Controller (PMC) with internal regulators capable of supporting
multiple power modes including:
• HSRUN 2, , 3
• RUN
• STOP
• VLPR
• VLPS
• I/O supporting 2.7 V to 5.5 V supply
• Wide operating voltage ranges (2.7–5.5 V) with fully functional flash memory
program/erase/read operations
• 64 LQFP, 100 LQFP, 144 LQFP, 176 LQFP and 100 MAPBGA packages with up to
156 GPIO pins
• Ambient operating temperature ranges from –40 °C to 125 °C 3
The S32K14x MCU portfolio is supported by a highly comprehensive set of development
tools and software. The enablement package includes: NXP Arduino compatible
evaluation boards, S32K Software Development Kit (SDK) including graphical
configurability and S32 Design Studio software, as well as broad support from IAR
Systems, Arm, Software, Green Hills, and other partners.
1. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case
is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 Mhz) to execute CSEc
(Security) or EEPROM writes/erase.
2. This refers to region addressable by Arm CM4 Code bus and is used to cache code as well as data in this region.
See S32K1xx_memory_map.xlsx for more details on cacheability of different regions.
3. HSRUN mode (112 MHz) operation is not valid at 125 °C.
S32K1xx Series introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
58 NXP Semiconductors
2.2.2 S32K11x
S32K11x series of devices are 32-bit general purpose automotive microcontrollers based
on the Arm Cortex-M0+ core. They offer superior performance, large memories and the
most scalable peripherals in this class. This product series provides 48 MHz CPU
performance, with up to 256 KB Flash and up to 25 KB SRAM. Overview of device
features:
• 32-bit Arm Cortex-M0+ core with 48 MHz CPU
• Up to 256 KB code flash memory and 32 KB FlexMem (supports up to 2 KB
emulated EEPROM with 2 KB FlexRAM)
• Up to 25 KB SRAM
• Integrated clocking architecture with on-chip fast IRC 48 MHz, slow IRC 8MHz, and
128 KHz LPO
• Analog modules providing precision mixed-signal capabilities, including 12-bit 1
Msps SAR ADC, high-speed comparator
• Power Management Controller (PMC) with internal regulators capable of supporting
multiple power modes including:
• RUN
• STOP
• VLPR
• VLPS
• I/O supporting 2.7 V to 5.5 V supply
• Wide operating voltage ranges (2.7–5.5 V) with fully functional flash memory
program/erase/read operations
• 32-pin QFN, 48-pinLQFP, 64-pinLQFP with up to 58 GPIO pins
• Ambient operating temperature ranges from –40 °C to 125 °C
The S32K11x MCU portfolio is supported by a highly comprehensive set of development
tools and software. The enablement package includes: NXP Arduino compatible
evaluation boards, S32K Software Development Kit (SDK) including graphical
configurability and S32 Design Studio software, as well as broad support from IAR
Systems, Cosmic Software, Green Hills, and other partners.
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 59
2.3 Feature summary
The following table lists the features integrated on S32K1xx product series.
Table 2-1. Device feature summary
Feature S32K14x product series S32K11x product series
Hardware Characteristics
Package 64-pin LQFP, 10*10 mm, 0.5 mm pitch
100-pin LQFP, 14*14 mm, 0.5 mm pitch
144-pin LQFP, 20*20 mm, 0.5 mm pitch
176-pin LQFP, 24*24 mm, 0.5 mm pitch
100-pin MAPBGA, 11*11 mm, 1 mm ball
pitch
32-pin QFN , 5*5 mm, 0.5 mm pitch
48-pin LQFP, 7*7 mm, 0.5 mm pitch
64-pin LQFP, 10*10 mm, 0.5 mm pitch
Voltage range 2.7 V to 5.5 V
Temperature range (TA) -40 °C to 125 °C12
Temperature range (TJ) -40 °C to 135 °C
System
Central processing unit (CPU) Arm Cortex-M4F Arm Cortex-M0+
Maximum CPU frequency 112 MHz 1, 248 MHz
Digital signal processor (DSP) Yes No
Floating point unit (FPU) Yes No
System memory protection unit
(MPU)3Yes
Code Cache size 4 KB Not available
Nested vectored Interrupt
controller (NVIC)
up to 240 vectored interrupts
16 programmable interrupt priority levels
up to 48 interrupts
4 programmable interrupt priority levels
Wake-up interrupt controller (WIC) Yes
Direct memory access (DMA) 16 channels 4 channels
Direct memory access multiplexer
(DMAMUX)
Yes
Non-maskable interrupt (NMI) Yes
Software watchdog Yes
Hardware watchdog Yes, with external monitor pin. Not available
Debug 2-pin serial wire debug (SWD)
IEEE 1149.1 Joint Test Access Group
(JTAG)
Available only for BSR
Trace Trace Port Interface Unit (TPIU) MTB
Boundary scan Yes
Unique Identification (ID) Number 128-bit wide
Memory
Program flash memory up to 2MB up to 256 KB
Table continues on the next page...
Feature summary
S32K1xx Series Reference Manual, Rev. 7, 04/2018
60 NXP Semiconductors
Table 2-1. Device feature summary (continued)
Feature S32K14x product series S32K11x product series
FlexMemory 64 KB
Data flash (D-flash)/emulated EEPROM 2
backup (E-Flash) memory: 4 KB additional
FlexRAM supporting high-endurance, non-
volatile emulated EEPROM
32 KB
Data flash (D-flash)/emulated EEPROM
backup (E-Flash) memory: 2 KB additional
FlexRAM supporting high-endurance, non-
volatile emulated EEPROM
Flash memory controller cache Yes (single speculative prefetch buffer only)
Flash memory access control
(FAC)
No
Random-access memory (RAM) Up to 256 KB. 4 KB is part of the EEERAM
solution
Up to 25 KB. 2 KB is part of the EEERAM
solution
Low-leakage standby memory RAM retained in all modes
QuadSPI Supports SDR and HyperRAM modes upto
4 and 8 bidirectional data lines respectively
Not avaiable
Cyclic redundancy check (CRC) 16- or 32-bit CRC with programmable generator polynomial
Clocks
System clock generator (SCG) OSC, FIRC, SIRC, PLL OSC, FIRC, SIRC
External crystal oscillator or
resonator
OSC: 4 - 40 MHz with low power or full-swing
External square wave input clock DC to 50 MHz
Internal clock references (IRC) 48 MHz internal IRC (FIRC) with 1% max deviation across full temperature
8 MHz internal IRC (SIRC) with 3% maximum deviation across full temperature
Phase-locked loop (PLL) Up to 320 MHz VCO Not available
Human-Machine Interface (HMI)
General-purpose input/output
(GPIO)
Up to 156 GPIOs Up to 58 GPIOs
Pin interrupt / DMA request capability
Configurable digital glitch filter
Hysteresis, pull up and pull down control on all input pins
Passive input filter on NMI_b and RESET_B input pins
High drive capability on up to 32 pins
Analog
Power management controller
(PMC)
Low voltage warning
Internal regulators offering various power modes
128 kHz LPO clock
12-bit analog-to-digital converter 1 Msps with 12-bit mode
1.2 Msps with 10-bit mode
Up to 64 single-ended external channels Up to 32 single-ended external channels
Up to 64 control and result registers Up to 32 control and result registers
Support result compare
High-speed comparator (CMP) Comparator with own 8-bit DAC
Timers
Programmable delay block (PDB) PDB0 with up to 4 ADC channels with 8 pre-triggers for each channel for ADC0
Table continues on the next page...
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 61
Table 2-1. Device feature summary (continued)
Feature S32K14x product series S32K11x product series
1 pulse-out channel
PDB1 with up 2 ADC channel with 8 pre-
triggers for each channel for ADC1
1 pulse-out channel
Not available
Flexible timer (FTM) 16-bit, 64 channels 16-bit, 16 channels
GTB and Global Load
Up to 2 with Quadrature Decoder
Deadtime by Pair
Up to 2 with Dither enable
32-bit Low-power programmable
interrupt timer (LPIT)
4 independent channels
Real-time clock (RTC) Yes
Low-power timer (LPTMR) LPTMR
1-channel, 16-bit pulse counter or Periodic interrupt
Communication Interfaces
Ethernet controller Dual-speed 10/100-Mbit/s Ethernet MAC
compliant with the IEEE802.3-2002
standard.
Compatible with half- or fullduplex 10/100-
Mbit/s Ethernet LANs
Not available
Control Area Network (CAN) With optional ISO CAN-FD support With optional ISO CAN-FD support
FlexIO Capable of supporting a wide range of protocols (UART, I2C, SPI, I2S) and PWM/
waveform generation
Low Power Serial peripheral
interface (LPSPI)
DMA support, 4 word FIFO support on all LPSPIs
Low Power Inter-Integrated Circuit
(LPI2C)
Standard SMBUS compatible I2C
4 word FIFO support on LPI2C0
DMA support
1 Mbps ability (even with maximum I2C bus loading of 400 pF)
Only high-drive pins are able to support 1 Mbps
Low Power UART (LPUART) Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602
Standard features
Configurable from 4x to 32x oversampling
LIN slave operation support
32-bit data width
All LPUARTs support DMA and 4-word FIFO
SAI Supports full duplex serial interfaces with
frame synchronization such as I2S, AC97,
TDM, and codec/DSP interfaces.
Not available
1. HSRUN mode is limited to a maximum ambient temperature of 105°C TA
Feature summary
S32K1xx Series Reference Manual, Rev. 7, 04/2018
62 NXP Semiconductors
2. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not
allowed to execute simultaneously. The device need to switch to RUN mode (80 Mhz) to execute CSEc (Security) or
EEPROM writes/erase.
3. On this device, NXP's system MPU implements the safety mechanisms to prevent masters from accessing restricted
memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each Crossbar master
(Core, DMA, Ethernet) can be assigned different access rights to each protected memory region. The Arm M4 core version
in this family does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2.4 Block diagram
The following figure shows block diagram of the S32K14x product series.
Mux
Trace
port
Crossbar switch (AXBS-Lite)
eDMA
DMA
MUX
Core
Peripheral bus controller
CRC
WDOG
S1
M0 M1
DSP
NVIC
ITM
FPB
DWT
AWIC
SWJ-DP
TPIU
JTAG &
Serial Wire
Arm Cortex M4F
ICODE
DCODE
AHB-AP
PPB
System
M2
S2
GPIO
Mux
FPU Clock
SPLL
LPO
128 kHz
Async
512B
TCD
LPIT
LPI2C FlexIO
Flash memory
controller
Code flash
S0
Data flash
Low Power
Timer
12-bit ADC
TRGMUX
LPUART
LPSPI
FlexCAN FlexTimer
PDB
generation
LPIT
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
Key:
Device architectural IP
on all S32K devices
S3
FIRC
48 MHz
M3
ENET
SAI
SOSC
8-40 MHz
(see the "Feature Comparison"
memory memory
4-40 MHz
QuadSPI
RTC
CMP
8-bit DAC
SIRC
8 MHz
FlexRAM/
SRAM
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned
different access rights to each protected memory region. The Arm M4 core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
section)
ERM
EWM
MCM
Lower region
Upper region
Main SRAM2
Code Cache
System MPU1
EIM
LMEM
controller
LMEM
QSPI
CSEc3
System MPU1System MPU1System MPU1
3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this
use case is not allowed to execute simultaneously. The device need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
Figure 2-1. S32K14x product series block diagram
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 63
The following figure shows block diagram of the S32K11x product series.
Crossbar switch (AXBS-Lite)
eDMA
DMA
MUX
SW-DP
Unified Bus
Serial Wire
AHBLite
AHBLite
AWIC
S0 S1
Clock
LPO
128 kHz
generation
FIRC
48 MHz
SOSC
4-40 MHz
SIRC
8 MHz
Peripheral bus controller
CRC
WDOG
LPIT
LPI2C FlexIO Low Power
Timer
12-bit ADC
TRGMUX
LPUART
LPSPI
FlexCAN FlexTimer
PDB
LPIT
RTC
CMP
8-bit DAC
ERM
CMU GPIO
M0 M2
Flash memory
controller
Data flash
memory
FlexRAM/
SRAM2
Code flash
memory
EIM
SRAM2
IO PORT
NVIC
PPB
MTB+DWT
BPU
AHB-AP
Arm Cortex M0+
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
Key:
Device architectural IP
on all S32K devices
(see the "Feature Comparison"
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The Arm M0+ core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
section)
S2
IO PORT
CSEc
System MPU1System MPU1
Figure 2-2. S32K11x product series block diagram
2.5 Feature comparison
The following figure summarizes the memory, peripherals and packaging options for the
S32K1xx devices. All devices which share a common package are pin-to-pin compatible.
Feature comparison
S32K1xx Series Reference Manual, Rev. 7, 04/2018
64 NXP Semiconductors
2 KB (up to 32 KB D-Flash)
EEPROM emulated by FlexRAM1
2 KB
FlexRAM (also available as system RAM)
Cache
25 KB
System RAM (including FlexRAM and MTB) 17 KB
Flash 128 KB 256 KB
2.7 - 5.5 V
Single supply voltage
HSRUN mode1
Watchdog 1x
Number of I/Os up to 43 up to 58
Memory Protection Unit (MPU)
K116 K118
Parameter
Peripheral speed
CRC module
IEEE-754 FPU
Arm® Cortex™-M0+
Core
1x
External Watchdog Monitor (EWM)
DMA
Crossbar
capable up to ASIL-B
ISO 26262
Cryptographic Services Engine (CSEc)1
48 MHz
Frequency
up to 48 MHz
Error Correcting Code (ECC)
1x
Low Power Timer (LPTMR)
1x
Low Power Interrupt Timer (LPIT)
LEGEND:
Not implemented
Available on the device
1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when
device is running at HSRUN mode (112MHz) or VLPR mode.
2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.
3 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB
of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.
4 Only for Boundary Scan Register
5 See Dimensions section for package drawings
Trigger mux (TRGMUX)
1x
Real Time Counter (RTC)
FlexTimer (16-bit counter) 8 channels 2x (16)
External memory interface
1x (16)
2x
1x
10/100 Mbps IEEE-1588 Ethernet MAC
12-bit SAR ADC (1 Msps each)
1x
FlexIO (8 pins configurable as UART, SPI, I2C, I2S)
Low Power I2C (LPI2C)
Low Power UART/LIN (LPUART)
(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602)
SWD, MTB (1 KB), JTAG4
Debug & trace
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
48-pin LQFP
64-pin LQFP
Packages5
Ecosystem
(IDE, compiler, debugger)
32-pin QFN
48-pin LQFP
FlexCAN
(CAN-FD ISO/CD 11898-1) 1x
(1x with FD)
1x 2x
Low Power SPI (LPSPI)
Serial Audio Interface (AC97, TDM, I2S)
Comparator with 8-bit DAC 1x
Programmable Delay Block (PDB) 1x
S32K11x S32K14x
K142 K144 K146 K148
1x
SWD, JTAG (ITM, SWV, SWO)
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
64-pin LQFP
100-pin LQFP
64-pin LQFP
100-pin LQFP
100-pin MAPBGA
64-pin LQFP
100-pin MAPBGA
100-pin LQFP
144-pin LQFP
100-pin MAPBGA
144-pin LQFP
176-pin LQFP
SWD, JTAG
(ITM, SWV,
SWO), ETM
1x (64)
2x (16) 2x (24) 2x (32)
1x
2x 3x
1x 2x
2x
(1x with FD) 3x
(2x with FD) 3x
(3x with FD)
3x
(1x with FD)
2x 3x
2x
1x
1x (73) 1x (81)
80 MHz (RUN mode) or 112 MHz (HSRUN mode)1
1x
Arm® Cortex™-M4F
1x
capable up to ASIL-B
up to 112 MHz (HSRUN)
4 KB (up to 64 KB D-Flash)
4 KB
4 KB
32 KB 48/64 KB 96/128 KB 192/256 KB
-40oC to +85oC / +105oC / +125oC
256 KB 512 KB 1 MB 2 MB2
2.7 - 5.5 V
up to 89 up to 128 up to 156
1x
1x
1x
4x (32) 6x (48) 8x (64)
QuadSPI incl.
HyperBus™
2x
See footnote 3
MemoryAnalog Timer
Communication
IDEs
Other System
-40oC to +85oC / +105oC / +125oC
Ambient Operation Temperature (Ta)
1x (43) 1x (45)
1x (13)
FIRC CMU
Low power modes
Figure 2-3. S32K1xx product series comparison
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 65
2.6 Applications
The S32K1xx product series are the ideal choices for general purpose automotive
applications, which include but not limited to:
• Exterior and interior lighting
• HVAC
• Door/Window/Wiper/Seat controller
• BLDC/PMSM motor control
• Park assistant
• E-shifter
• TPMS
• Real time control in infotainment system
• Battery management system
• Human machine interface such as touch sense control
• Secured vehicle data transfer
• Safety controller
• Over the air update 4
Moreover, the 100 Mbit IEEE-1588 Ethernet MAC and Serial audio interface (AC97,
TDM, and I2S) on S32K148 make it fit perfectly for Ethernet connected edge nodes in
vehicle, and the audio streaming application.
In addition to automotive applications, the S32K1xx product series can also be used in
challenging environments found in industrial, automation, communications,
transportation, medical and A & D applications which need high level quality, reliability
and safety.
NOTE
• For safety aware and critical application, the user must
refer to S32K1xx Safety Manual and Using the S32K1xx
EEPROM Functionality application note available on
nxp.com for correct part operation requirements.
• See S32K1xx Safety Manual and Production Flash
Programming Best Practices for S32K1xx MCUs
application note available on nxp.com for correct part
operation and memory handling during programming of the
internal flash memory.
4. See S32K Architecture and Capabilities to Enable Over the Air Updates
Applications
S32K1xx Series Reference Manual, Rev. 7, 04/2018
66 NXP Semiconductors
2.7 Module functional categories
The modules on this device are grouped into functional categories. The following
sections describe the modules assigned to each category in more detail.
Table 2-2. Module functional categories
Module category Description
Arm® Cortex®-M4F core • 32-bit MCU core from Arm's Cortex-M class adding DSP instructions and
single-precision floating point unit based on Armv7 architecture
Arm® Cortex®-M0+ core • 32-bit MCU core from Arm’s Cortex-M class, implements the Armv6-M
architecture profile.
System • Miscellaneous control module (MCM)
• System integration module (SIM)
• Port Control and Interrupts (PORT)
• General purpose input/output controller (GPIO)
• Crossbar switch (AXBS-Lite)
• Peripheral bridge (AIPS-Lite)
• Trigger Mux Control (TRGMUX)
• Watchdog timer (WDOG)
• Cyclic Redundancy Check (CRC)
Clocking • Multiple clock generation options available from internally- and externally-
generated clocks
• System oscillator to provide clock source for the MCU
Memories • Internal memories include:
• Program flash memory
• FlexMemory
• FlexNVM
• FlexRAM
• SRAM
• Direct memory access (DMA) controller with multiplexer to increase available
DMA requests. DMA can now handle transfers in VLPS mode
Power Management Power management and mode controllers (PMC)
• Multiple power modes available based on high speed run, run, stop
Security • Error-correcting code (ECC) on Flash and SRAM memories
• 128-bit unique identification (ID) number
• System Memory Protection Unit (MPU) module
Safety Clock monitoring unit (CMU), for monitoring FIRC clock
Power Management Power management and mode controllers (PMC)
• Multiple power modes available based on high speed run, run, stop
Analog • High speed analog-to-digital converter (ADC)
• Comparator (CMP), containing 8 bit reference DAC
• Bandgap voltage reference (1V reference voltage)
Timers • Programmable delay block (PDB)
• FlexTimers
• Low-power periodic interrupt timer (LPIT)
• Low power timer (LPTMR)
• Independent real time clock (RTC)
Communications • Ethernet MAC with IEEE802.3-2002 standard.
• Low-power Serial peripheral interface (LPSPI)
Table continues on the next page...
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 67
Table 2-2. Module functional categories (continued)
Module category Description
• Low-power Inter-integrated circuit (LPI2C)
• Low-power UART (LPUART)
• Synchronous Audio Interface (SAI)/Integrated interchip sound (I2S)
• FlexIO
• FlexCAN
Debug • JTAG Controller (JTAGC)
2.7.1 Arm® Cortex®-M4F Core Modules
The following core modules are available on this device.
Table 2-3. Core modules
Module Description
Arm Cortex-M4F The Arm® Cortex®-M4F is the newest member of the Cortex M Series of
processors targeting microcontroller cores focused on very cost sensitive,
deterministic, interrupt driven environments. The Cortex M4F processor is based
on the Armv7 Architecture and Thumb®-2 ISA and is upward compatible with the
Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4F improvements
include an Armv7 Thumb-2 DSP (ported from the Armv7-A/R profile architectures)
providing 32-bit instructions with SIMD (single instruction multiple data) DSP style
multiply-accumulates and saturating arithmetic.
Floating point unit (FPU) A single-precision floating point unit (FPU) that is compliant to the IEEE Standard
for Floating-Point Arithmetic (IEEE 754).
NVIC The Armv7-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to Arm internal
sources, with the others mapping to MCU-defined interrupts.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and then signal to clock
control logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Debug interfaces Most of the debug capability on this device is based on the Arm CoreSight™
architecture. Following debug interfaces are supported:
• Serial wire IEEE 1149.1 JTAG debug Port (SWJ-DP), with 2 pin serial wire
debug (SWD) for external debugger
• Debug Watchpoint and Trace (DWT), with four configurable comparators as
hardware watchpoints
• Serial wire output (SWO)-synchronous trace data support
• Instrumentation Trace Macrocell (ITM) with software and hardware trace,
plus time stamping
• Flash Patch and Breakpoints (FPB) with ability to patch code and data from
code space to system space
Module functional categories
S32K1xx Series Reference Manual, Rev. 7, 04/2018
68 NXP Semiconductors
Table 2-3. Core modules
Module Description
• Serial Wire Viewer (SWV): A trace capability providing displays of reads,
writes, exceptions, PC Samples and printf.
• Supports 4 pin trace interface
2.7.2 Arm Cortex-M0+ Core Modules
The following core modules are available on this device.
Table 2-4. Core modules
Module Description
Arm Cortex-M0+ The Arm® Cortex™-M0+processor is a configurable, multistage, 32-bit RISC
processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It
also has optional hardware debug, single-cycle I/O interfacing, and memory-
protection functionality. The processor can execute Thumb code and is compatible
with other Cortex-M profile processors.
NVIC NVIC features up to 32 external interrupt inputs, each with four levels of priority. It
implements optional relocation of the vector table.
It features dedicated Non-Maskable Interrupt (NMI) input, supprts optional Wake-
up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port.
Debug interfaces Most of this device's debug is based on the Arm CoreSight™ architecture. One
debug interfaces are supported:
• Serial Wire Debug (SWD)
• Micro Trace Buffer (MTB)
2.7.3 System modules
The following system modules are available on this device.
Table 2-5. System modules
Module Description
Miscellaneous control module (MCM) The MCM includes miscellaneous control logic for Core and System modules.
System integration module (SIM) The SIM includes miscellaneous device configuration and status registers.
Table continues on the next page...
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 69
Table 2-5. System modules (continued)
Module Description
PORT The Port Control and Interrupt (PORT) module provides support for port control,
digital filtering, and external interrupt functions.
GPIO The general-purpose input and output (GPIO) module communicates to the
processor core via a zero wait state interface for maximum pin performance. The
GPIO registers support 8-bit, 16-bit or 32-bit accesses.
Crossbar switch (AXBS-Lite) The AXBS-Lite connects bus masters and bus slaves, allowing all bus masters to
access different bus slaves simultaneously and providing arbitration among the bus
masters when they access the same slave.
System Memory protection unit (MPU) The system MPU provides memory protection and task isolation. It concurrently
monitors all bus master transactions for the slave connections.
Peripheral bridge (AIPS-Lite) The AIPS-Lite converts the crossbar switch interface to an interface that allows
access to a majority of peripherals on the device.
Direct memory access multiplexer
(DMAMUX)
The DMAMUX selects from many DMA requests down to a smaller number for the
DMA controller.
enhanced Direct Memory Access
controller (eDMA)
The eDMA provides programmable channels with transfer control descriptors for
data movement via dual-address transfers for 8-bit, 16-bit, 32-bit, 16-byte and 32-
byte data values.
TRGMUX The trigger multiplexer (TRGMUX) module allows software to configure the trigger
sources for various peripherals.
External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that
monitors both internal and external system operation for fail conditions.
Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 128 kHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
CRC Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all
single, double, odd, and most multi-bit errors, programmable initial seed value, and
optional feature to transpose input data and CRC result via transpose register.
2.7.4 Memories and memory interfaces
The following memories and memory interfaces are available on this device.
Table 2-6. Memories and memory interfaces
Module Description
Local memory controller(LMEM) Manages simultaneous accesses to system RAM by multiple master peripherals
and core. Also provide cache control, which improves system performance by
providing single-cycle access to the instruction and data pipelines.
Miscellaneous System Control Module
(MSCM)
The Miscellaneous System Control Module (MSCM) contains CPU configuration
registers and on-chip memory controller registers.
Flash memory • Program flash memory — non-volatile flash memory that can execute
program code
• FlexMemory — encompasses the following memory types:
Table continues on the next page...
Module functional categories
S32K1xx Series Reference Manual, Rev. 7, 04/2018
70 NXP Semiconductors
Table 2-6. Memories and memory interfaces (continued)
Module Description
• FlexNVM — Non-volatile flash memory that can execute program
code, store data, or backup emulated EEPROM data
• FlexRAM — RAM memory that can be used as traditional SRAM or as
high-endurance emulated EEPROM storage, and also accelerates
flash programming
QuadSPI The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to
external serial flash device. It supports SDR and HyperRAM modes up to 4 and 8
bidirectional data lines respectively.
Flash memory controller Manages the interface between the device and the on-chip flash memory.
SRAM Internal system RAM.
2.7.5 Power Management
The following modules are available on this device for power management and system
power modes control:
Table 2-7. Power Management modules
Module Description
PMC The PMC contains the internal voltage regulator, power on reset (POR) and the
low voltage detect (LVD) system.
SMC The System Mode Controller (SMC) is responsible for sequencing the system into
and out of all low-power Stop and Run modes.
2.7.6 Clocking
The following clock modules are available on this device.
Table 2-8. Clock modules
Module Description
System clock generator (SCG) The SCG provides several clock sources for the MCU that include:
• Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO)
• Fast internal reference clock (FIRC) — An internally-generated 48 MHz
clock, which can be used as a clock source for other on-chip peripherals
• Slow internal reference clock (SIRC) — An internally-generated 8 MHz clock,
which can be used as a clock source for other on-chip peripherals
• System oscillator (OSC) — The system oscillator, in conjunction with an
external crystal or resonator, generates a reference clock for the MCU
Low Power Oscillator (LPO) An internally-generated low power clock with typical frequency of 128 kHz, which
can be used as clock source for modules operational in low power modes.
Peripheral Clock Control (PCC) Controls the clock selection for most modules.
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 71
2.7.7 Analog modules
The following analog modules are available on this device:
Table 2-9. Analog modules
Module Description
12-bit analog-to-digital converters (ADC) 12-bit successive-approximation ADC
Analog comparators (CMP) Compares two analog input voltages across the full range of the supply voltage.
8-bit digital-to-analog converters (DAC)
within CMP
256-tap resistor ladder network which provides a selectable voltage reference for
applications where a voltage reference is needed.
2.7.8 Timer modules
The following timer modules are available on this device:
Table 2-10. Timer modules
Module Description
Programmable delay block (PDB) • 16-bit resolution
• 3-bit prescaler
• Positive transition of trigger event signal initiates the counter
• Supports multiple triggered delay output signals, each with an independently-
controlled delay from the trigger event
• Continuous-pulse output or single-shot mode supported, each output is
independently enabled, with possible trigger events
• Supports bypass mode
• Supports DMA
Flexible timer module (FTM) • Selectable FTM source clock, programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up
or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM
modes
• Operation of FTM channels as pairs with equal outputs, pairs with
complementary outputs, or independent channels with independent outputs
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed
counter, or detected fault condition and reload opportunity.
• Quadrature decoder with input filters, relative position counting, and interrupt
on position count or capture of position count on external event
• DMA support for FTM events
Low-power periodic interrupt timer
(LPIT)
• Four general purpose interrupt timers
• Interrupt timers for triggering ADC conversions
Table continues on the next page...
Module functional categories
S32K1xx Series Reference Manual, Rev. 7, 04/2018
72 NXP Semiconductors
Table 2-10. Timer modules (continued)
Module Description
• 32-bit counter resolution
• The counter is clocked by an asynchronous clock that can remain enabled in
low power modes.
• DMA support
• Supports chaining of Timer channels
Low power timer (LPTMR) • Selectable clock for prescaler/glitch filter of 128 kHz (internal LPO), or
internal reference clock
• Configurable glitch filter or prescaler with 16-bit counter
• 16-bit time or pulse counter with compare
• Interrupt generated on Timer Compare
• Hardware trigger generated on Timer Compare
Real-time clock (RTC) • 32-bit seconds counter with 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm
and 3906 ppm
2.7.9 Communication interfaces
The following communication interfaces are available on this device:
Table 2-11. Communication modules
Module Description
Low-power Serial peripheral interface
(LPSPI)
Synchronous serial bus for communication to an external device. LPSPI optionally
remains functional in low power modes.
Low-power Inter-integrated circuit
(LPI2C)
Allows communication between a number of devices. Also supports the System
Management Bus (SMBus) Specification, version 2. LPI2C optionally remains
functional in low power modes.
Low-power Universal asynchronous
receiver/transmitters (LPUART)
Asynchronous serial bus communication interface, supporting LIN master and
slave operation. LPUART optionally remains functional in low power modes.
SAI/I2S The I2S (or I2S) module provides a synchronous audio interface (SAI) that
supports fullduplex serial interfaces with frame synchronization such as I2S, AC97,
TDM, and codec/DSP interfaces.
ENET The core implements a dual-speed 10/100-Mbit/s Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with half- or
fullduplex 10/100-Mbit/s Ethernet LANs.
FlexCAN The FlexCAN module is a communication controller implementing the CAN
protocol according to the ISO 11898-1 standard and CAN 2.0 B protocol
specifications.
2.7.10 Debug modules
The following Debug modules are available on this device:
Chapter 2 Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 73
Table 2-12. Debug modules
Module Description
JTAGC The JTAGC block provides the means to test chip functionality and connectivity
while remaining transparent to system logic when not in test mode. Testing is
performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in
serial format.
Module functional categories
S32K1xx Series Reference Manual, Rev. 7, 04/2018
74 NXP Semiconductors
Chapter 3
Memory Map
3.1 Introduction
This chip contains various memories and memory-mapped peripherals that are located in
one 32-bit contiguous memory space. This chapter describes the memory and peripheral
locations within that memory space.
Details about the memory map appear in the spreadsheet that is attached to this
document: S32K1xx_memory_map.xlsx. To access this spreadsheet, view the document's
list of attachments.
3.2 SRAM memory map
3.2.1 S32K14x: SRAM memory map
The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in
the memory map. See S32K1xx_memory_map.xlsx attached to this document for details.
Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on
the chip causes the bus cycle to be terminated with an error followed by the appropriate
response in the requesting bus master.
3.2.2 S32K11x: SRAM memory map
In S32K11x on-chip RAM can be used in following applications:
• Safety critical applications: SRAM_U can be used, which starts from 2000_0000
• Non-safety critical applications: SRAM_U along with 1 KB MTB can be used
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 75
NOTE
CM0+ architecture implements single RAM controller, hence
SRAM_U and MTB are referred as single contiguous memory
regions. MTB in S32K11x is present at the same location as
SRAM_L in S32K14x.
See S32K1xx_memory_map.xlsx attached to this document for details. Accesses to the
memory ranges outside the amount of RAM on the chip causes the bus cycle to be
terminated with an error followed by the appropriate response in the requesting bus
master.
3.3 Flash memory map
The various flash memories and the flash memory registers are located at different base
addresses as shown in the following figure. The base address for each is specified in the
S32K1xx_memory_map.xlsx file attached to this document.
Figure 3-1. Flash memory map
3.4 Peripheral bridge (AIPS-Lite) memory map
The peripheral memory map is accessible via a crossbar slave port.
There are three regions associated with peripheral space, as shown in the following table.
Flash memory map
S32K1xx Series Reference Manual, Rev. 7, 04/2018
76 NXP Semiconductors
Table 3-1. Regions associated with peripheral space
Address space Region description
0x4000_0000–0x4001_FFFF A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on-
platform peripheral devices. AIPS-Lite generates unique module enables for all 32
spaces.
0x4002_0000–0x4007_FFFF A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off-
platform modules. AIPS-Lite generates unique module enables for all 96 spaces.
0x400F_F000 A 4 KB region for accessing the GPIO module. This block is connected to the
AMBA bus via the port splitter and provides direct master access without incurring
wait states associated with accesses via the AIPS-Lite modules. The GPIO is
implemented only in the upper space of this region (4 KB beginning at
0x400F_F000).
Modules that are disabled via their clock gate control bits in the PCC/SIM registers
disable the associated AIPS-Lite slots. Access to any address within an unimplemented or
disabled peripheral bridge slot results in a transfer error termination.
NOTE
While trying to access memory map region of unavailable
feature (See SIM_SDID[FEATURES]) with corresponding
module clock enabled through PCC CGC bit, there will not be
any transfer error termination.
3.4.1 Read-after-write sequence and required serialization of
memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations, as shown in the following
table.
Table 3-2. Read-after-write sequence to guarantee required serialization of memory
operations
Step Action
1 Write the peripheral register.
2 Read the written peripheral register to verify the write.
3 Continue with subsequent operations.
Chapter 3 Memory Map
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 77
NOTE
In S32K14x series of devices, one factor contributing to these
situations is processor write buffering. The processor
architecture has a programmable configuration field to disable
write buffering: ACTLR[DISDEFWBUF]. (For details see
Arm® Cortex® M4 Processor Technical Reference Manual,
Revision r0p1, at http://arm.com ). However, disabling buffered
writes is likely to degrade system performance much more than
simply performing the required memory serialization for the
situations that truly require it.
3.5 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined Arm bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 3-3. PPB memory map for CM4
System 32-bit address range Resource
0xE000_0000–0xE000_0FFF Instrumentation Trace Macrocell (ITM)
0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB)
0xE000_3000–0xE000_DFFF Reserved
0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC and FPU
0xE000_F000–0xE003_FFFF Reserved
0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU)
0xE004_1000–0xE004_1FFF Reserved
0xE004_2000–0xE004_2FFF Reserved
0xE004_3000–0xE004_3FFF Reserved
0xE004_4000–0xE007_FFFF Reserved
0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM)
0xE008_1000–0xE008_1FFF Reserved
0xE008_2000–0xE008_2FFF Cache Controller (LMEM)
0xE008_3000–0xE00F_EFFF Reserved
0xE00F_F000–0xE00F_FFFF Arm Core ROM Table1 - allows auto-detection of debug components
1. The Arm Core ROM table is optionally required by Arm CoreSight debug infrastructure to discover the components on the
chip. This ROM table has no any relationship with the MCU Boot ROM.
Private Peripheral Bus (PPB) memory map
S32K1xx Series Reference Manual, Rev. 7, 04/2018
78 NXP Semiconductors
Table 3-4. PPB memory map for CM0+
System 32-bit address range Resource
0xE000_0000–0xE000_0FFF Reserved 1
0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF Arm Core ROM Table
0xE000_3000–0xE000_DFFF Reserved1
0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC)
0xE000_F000–0xE003_FFFF Reserved1
0xE004_0000–0xE004_0FFF Reserved1
0xE004_1000–0xE004_1FFF Reserved1
0xE004_2000–0xE004_2FFF Reserved1
0xE004_3000–0xE004_3FFF Reserved1
0xE004_4000–0xE007_FFFF Reserved1
0xE008_0000–0xE008_0FFF Reserved1
0xE008_1000–0xE008_1FFF Reserved1
0xE008_2000–0xE008_2FFF Reserved1
0xE008_3000–0xE00F_EFFF Reserved1
0xE00F_F000–0xE00F_FFFF Reserved1
0xE010_0000-0xEFFF_FFFF Reserved1
1. Reserved area return transfer error. Reserved is Unknown/Should be 0. Software must not rely on reading as all 0s, and it
must treat the value as if it is unknown.
3.6 Aliased bit-band regions for CM4 core
The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources
reside in the Cortex-M4F processor bit-band regions.
The processor also includes two 32 MB aliased bit-band regions associated with the two
1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit
in the bit-band region. A 32-bit write in the alias region has the same effect as a read-
modify-write operation on the targeted bit in the bit-band region.
Bit 0 of the value written to the alias region determines what value is written to the target
bit:
• Writing a value with bit 0 set writes a 1 to the target bit.
• Writing a value with bit 0 clear writes a 0 to the target bit.
A 32-bit read in the alias region returns either:
• a value of 0x0000_0000 to indicate the target bit is clear
• a value of 0x0000_0001 to indicate the target bit is set
Chapter 3 Memory Map
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 79
31 0 0
31
Bit-band region Alias bit-band region
1 MB
32 MB
Figure 3-2. Alias bit-band mapping
NOTE
Each bit in a bit-band region has an equivalent bit that can be
manipulated through bit 0 in a corresponding long word in the
alias bit-band region.
NOTE
Do not use bit banding for w1c status bits.
CAUTION
The S32K product series and the software drivers support bit-
banding, but Arm no longer promotes its usage. Therefore, we
recommend that bit-banding should not be used.
Aliased bit-band regions for CM4 core
S32K1xx Series Reference Manual, Rev. 7, 04/2018
80 NXP Semiconductors
Chapter 4
Signal Multiplexing and Pin Assignment
4.1 Introduction
The signal multiplexing enables the sharing of single pad for multiple functions.
The signal multiplexing unit comprises of control signals from GPIO, PORT and pad
interface logic. The signal multiplexing unit consists of several individual sub-units, each
handling the signal multiplexing of one pad.
The Port Control block controls the module specific pad settings (pull up etc) and the
signal present on the external pin. See PORT_PCR for the description of control signals.
For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached
to the Reference Manual.
4.2 Functional description
The signal multiplexing architectural implementation is as shown in the following figure.
ibe
GPIO
ind
Functional
Modules/
Peripherals
obe
Pad controls
do
ind
ibe
obe
do
ind
Padring Signal
Multiplexing
Unit
Figure 4-1. Signal Multiplexing
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 81
4.3 Pad description
Following figure shows the basic representation of a GPIO Pad.
obe
do
pue
pus
ibe
ind
Pull logic
Input
Receiver
Output
Driver
Pad
Figure 4-2. GPIO pad representation
Table 4-1. Pad Signal description
Signal name Direction Descriprtion
pad I/O I/O to external world
do I Data coming from the core into the pad
obe I Enable output driver
pue I 0: Disable internal pullup or pulldown resistor 1: Enable internal pullup or
pulldown resistor
pus I 0: Enable internal pulldown resistor if pue is set 1: Enable internal pullup
resistor if pue is set
ibe I Enable input receiver
ind O Data coming out of the pad into the core
Pad description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
82 NXP Semiconductors
Table 4-2. Truth table
obe do pad Description
0 X Z Output buffer disabled, pad hi-Z (If not configured as input)
1 0/1 0/1 Output buffer enable, pad = do
pue pus pad Description
0 X - Weak pull disabled. Pad retains previous state
1 0 0 Weak pull down enabled
1 1 1 Weak pull up enabled
ibe pad ind Description
0 X 0 Input buffer disabled, ind gets low
1 0/1 0/1 Input buffer enabled, ind = pad
NOTE
The device does not support open drain on all the pins. Only
pins that are configured for a protocol that requires open-drain
(e.g;, LPI2C, LPUART single-wire) will work in open-drain
mode.
4.4 Default pad state
The default pad configurations out of reset are as follows. For PTA4, PTA5, PTC4 and
PTC5, the default configurations are as per protocol specifications/requirements.
Table 4-3. Default pad configurations
Pin Default
function
Default pad
state1ibe obe pue pus
PTA4 JTAG_TMS Weak pull-up
enabled
1011
PTA5 2RESET_b Weak pull-up
enabled
1011
PTC4 JTAG_TCK Weak pull-down
enabled
1010
PTC5 JTAG_TDI Weak pull-up
enabled
1011
Others Disabled High impedance 0 0 0 0
Chapter 4 Signal Multiplexing and Pin Assignment
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 83
1. The IO pad states are undefined until VDD rises sufficiently to enable the POR circuits. The level at which this occurs will
vary from device to device, but for reference it is approximately 700 mV. After POR circuits are enabled, the IO pad states
are high impedance with weak pull devices disabled until POR release.
2. While in reset, the pin behavior is same apart from reset pin. Chip drives pad low via obe=1, pue=0, till reset sequence is
complete to indicate reset to off-chip connected devices.
4.5 Signal Multiplexing sheet
IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual
contains information on pins/balls of this device.
The 'IO Signal Table' and 'Input Muxing' tabs in the sheet correspond to the signal
multiplexing information. The 'IO Signal Table' consists of all the pin muxing details and
the 'Input Muxing' specifies the priority for the input muxing where an input path is
driven by more than one pad.
S32K1xx variant specific IO Signal Description Input Multiplexing sheets attached to the
Reference Manual contains information about the pins/balls of the particular variant.
Module functionality is dependent on the availability of functional pins in a particular
package. For example LPI2C HREQ pin is not available in 48-LQFP and 32-QFN
package.
4.5.1 IO Signal Table
Following is an example snippet of IO Signal Table. For selecting any functionality, the
pad PCR register (refer to PORT_PCRn) needs to be configured accordingly.
Figure 4-3. IO signal table snippet
The columns of the above figure are described below:
• Port: This field in IO Signal Table specifies the PAD names of the device.
• CR(Control Register): This field specifies the name of PCR corresponding to the Port
field. On this device there are five PORT instances, namely, PTA, PTB, PTC, PTD
and PTE. Each pad has a corresponding Control Register, referred to as PCR_PTXn
Signal Multiplexing sheet
S32K1xx Series Reference Manual, Rev. 7, 04/2018
84 NXP Semiconductors
in the IO Signal Table, where X refers to PORT instance and n refers to
corresponding pin of that PORT instance. Refer PORT_PCR for description of PCR
fields.
• SSS: This field specifies the ALT mode of operation as per PCR[Mux_mode]. Not
all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved.
The corresponding pin is configured in the following pin muxing slot as follows:
• 000: Alternative 0 (Signal path disabled)
• 001: Alternative 1 (GPIO)
• 010: Alternative 2 (chip-specific)
• 011: Alternative 3 (chip-specific)
• 100: Alternative 4 (chip-specific)
• 101: Alternative 5 (chip-specific)
• 110: Alternative 6 (chip-specific)
• 111: Alternative 7 (chip-specific)
The analog functionalities are specified with '-' in this field. Here ADC_SE0 and
CMP_IN0 represent analog functions.
By default, ALT0 mode (configured by PTXn_PCR[SSS] as 3’b000)
corresponds to disabled functionality and pad represents disabled (high-
impedance) state. In case if the pad consists of analog functions, the ALT0 mode
corresponds to analog functionality once the analog module is configured to
enable corresponding channel/input.
For example, PTA0 supports ADC0 channel 0 and CMP channel 0. By default
the pad is disabled. After ADC0 is configured to enable channel0 using
ADC0_SC1n[ADCH], the pad functions as ADC input channel. Alternatively if
CMP is configured to enable channel 0 using CMP_C1[PSEL] or
CMP_C1[MSEL], the pad functions as CMP input channel. The software must
ensure to enable only one function at a time.
• Function: This field specifies the functionality of the pad as per the corresponding
ALT mode specified by SSS field.
• Module: The Module field contains the module which is governing the pad for the
ALT mode.
• Description: This field mentions a short description of pad functionality.
• Direction: This field specifies the direction (Input, Output or Inout) of the pad for the
concerned functionality.
• The next columns specify the pin number in the supported packages for the device.
• PCR: This field specifies the default PCR value for corresponding pad. Refer
PORT_PCR for description of PCR fields.
Chapter 4 Signal Multiplexing and Pin Assignment
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 85
• The next two columns specify the reset value and the configurable bit fields of PCR
corresponding to pad.
• Pad Type: This field mentions the pad type of the corresponding pad.
• GPIO: General Purpose IO Pad (Standard)
• GPIO-HD: General Purpose IO Pad that support high drive functionality
(Strong)
• GPIO-FAST: General Purpose IO Pad that support High Speed (applicable for
S32K148 only)
NOTE
If oscillator is enabled then enabling the GPIO or LPI2C
function for EXTAL/XTAL pins can lead to device damage.
This must be avoided by software.
4.5.2 Input muxing table
As the same function can be multiplexed to several pads by configuring their respective
PCRs, there is priority input muxing. In case of same input being driven from multiple
pads, the one with highest priority (1 being the highest) will drive the input. Following is
a snippet of Input Muxing Table.
Figure 4-4. Input muxing table snippet
The columns of the figure are briefly described below:
• Destination Instance: This field contains the instance name of the input path to where
the signal will propagate from padring.
• Destination Function: This field mentions the function name of the input path.
• Priority: This field specifies the priority of the path. Priority level 1 is highest and it
decreases onwards.
• SSS: This field specifies the PCR[Mux_mode] value corresponding to the pad
specified in source signal column. A blank is mentioned for the default source when
none pad is driving the input path.
• Source Instance: This field specifies the source pad type. A blank is mentioned for
the default source when none pad is driving the input path.
• Source Signal: This field mentions the pad name. A ‘disable low’/’disable high’
specifies the signal behavior when none of the pads are driving the input path.
Signal Multiplexing sheet
S32K1xx Series Reference Manual, Rev. 7, 04/2018
86 NXP Semiconductors
4.6 Pinout diagrams
See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual
for pinout diagrams corresponding to available packages.
Chapter 4 Signal Multiplexing and Pin Assignment
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 87
Pinout diagrams
S32K1xx Series Reference Manual, Rev. 7, 04/2018
88 NXP Semiconductors
Chapter 5
Security Overview
5.1 Introduction
All chips of this S32K1xx product series have a comprehensive set of customer-
configurable security features designed to protect code and data from unauthorized
access.
5.2 Device security
Flash memory security is available to both CSEc and non-CSEc parts. SIM_SDID[7]
indicates whether CSEc is available on your device.
Both CSEc and non CSEc users need to run PGMPART command to configure the Key
Size for the device. For more information, see Program Partition command. This process
involves configuring a number of user keys. For non CSEc users, Key Size will be 00.
• The total size of EEERAM is reduced by the space required to store the user keys.
(See Introduction chapter for available EEERAM.)
• The user key space effectively becomes un-addressable space in the EEERAM.
• For non-CSEc parts and CSEc parts with key size=00, CSEc_PRAM access is not
guaranteed.
5.2.1 Flash memory security
The flash memory module provides security information to the MCU based on the state
held by the FSEC[SEC] field. The MCU, in turn, confirms the security request and limits
access to flash memory resources. During reset, the flash memory module initializes the
FSEC register using data read from the security byte of the flash memory configuration
field.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 89
NOTE
The security features apply only to external accesses via debug.
CPU accesses to the flash memory are not affected by the status
of FSEC.
In the unsecured state, all flash memory commands are available to the programming
interfaces (SWD (Serial Wire Debug) and JTAG (Joint Test Access Group)), as are user
code execution of Flash Memory Controller commands. When the flash memory is
secured (FSEC[SEC] = 00b, 01b, or 11b), programmer interfaces are allowed to launch
only mass erase operations and have no access to memory locations.
Further information regarding the flash memory security options and enabling/disabling
flash security is available in the Flash Memory Module.
5.2.1.1 Flash memory security interactions with debug
When flash memory security is active, the JTAG port cannot access the memory
resources of the MCU. Boundary scan chain operations work, but debugging capabilities
are disabled so that the debug port cannot read flash memory contents.
When flash memory security is active, the SWD port cannot access the memory resources
of the MCU.
Although most debug functions are disabled, the debugger can write to the Flash Mass
Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All
Blocks) command provided that MEEN (mass erase) is enabled. Running the mass erase
de -asserts the FSEC and after that JTAG port can access the memory resources. A mass
erase via the debugger is allowed even when some memory locations are protected.
When mass erase is disabled, mass erase via the debugger is blocked. Hence, you will not
be able to connect the debugger in a secure device (MEEN disabled). An alternative in
that case would be to run verify backdoor key access through any communication
interface.
The FTFC_FCSESTAT[EDB] bit clear status is as follows:
• If the debugger has switched to SWD mode, the FTFC_FCSESTAT[EDB] bit can be
reset only through POR.
• If the debugger remains in JTAG mode, the FTFC_FCSESTAT[EDB] bit is reset on
pin_reset if correct debugger disconnection takes place or on POR.
Device security
S32K1xx Series Reference Manual, Rev. 7, 04/2018
90 NXP Semiconductors
5.2.2 Cryptographic Services Engine (CSEc) security features
The FTFC module's Cryptographic Services Engine (CSEc) implements a comprehensive
set of cryptographic functions as described in the SHE Functional Specification,
including:
• >10 general purpose keys
• AES-128, CBC, ECB, CMAC
• Sequential, Parallel, and Strict Boot mode
• AES-128 CMAC calculation and authentication
• Pseudo random number generation (PRNG) and true random number generation
(TRNG)
5.2.3 Device Boot modes
In parallel secure boot mode, secure boot and application boot shall happen in parallel.
Also even if the secure boot fails, the application shall boot. But Keys having
BOOT_PROT attribute set to one, would be disabled. Application can make use of rest of
the keys and encryption/decryption/SHE functions. However, application code should
poll the Busy Flag FCSESTAT[BSY] , before attempting to actuate any SHE command.
Additionally, during parallel secure boot, any mode transition initiated by Core will be
aborted and secure boot will proceed.
During parallel boot operation FLASH_CLK must be the default FIRC_CLK and should
not be changed until boot operation is complete. Once the boot operation is complete it
can be changed to any value including its maximum value of 26.6 MHz in RUN mode
and 28 MHz in HSRUN mode.
In Sequential Secure boot, Application shall boot only after successful completion of
Secure boot. And, Application can actuate any command without bothering for
FCSESTAT[BSY] flag. However, in Strict boot mode, the chip will not boot at all and
will remain stuck in reset, if secure boot fails.
Security use case examples
5.3.1 Secure boot: check bootloader for integrity and
authenticity
The following diagram illustrates a use case for detecting and preventing bootloader
modification.
5.3
Chapter 5 Security Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 91
Figure 5-1. Bootloader integrity and authencity
The MAC protects against modification of the bootloader and depends on the (secret)
boot key.
Only if the calculated MAC value matches the stored boot MAC value: a successful
secure boot occurs, and keys become unlocked for further use.
5.3.2 Chain of trust: check flash memory for integrity and
authenticity
In this use case:
• The bootloader is protected by the secure boot process.
• MACs stored in the bootloader provide integrity and authenticity of the related parts
in flash memory.
• Part-by-part checking of flash memory ensures each part's integrity and authenticity
before executing it. Critical parts of flash memory (for example, MCU
configuration/IRQ table) are checked and then executed as soon as possible.
Security use case examples
S32K1xx Series Reference Manual, Rev. 7, 04/2018
92 NXP Semiconductors
Figure 5-2. Flash memory integrity and authenticity
5.3.3 Secure communication
This use case demonstrates how to prevent illegal messages sent by ECUs.
• Random number generation and checking protect against replay attacks.
• Encryption protects against eavesdropping.
• Random number generation/checking and encryption ensure data integrity and
authenticity.
Chapter 5 Security Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 93
Figure 5-3. Secure communication
5.3.4 Component protection
The replacement or modification of ECU <n> will change its unique ID and/or keys. This
use case shows how both changes are detected.
Figure 5-4. Component protection
Security use case examples
S32K1xx Series Reference Manual, Rev. 7, 04/2018
94 NXP Semiconductors
5.3.5 Message-authentication example
This use case consists of an Rx-CAN message authentication scenario:
1. CAN data stored in local buffer
2. FlexCAN triggers interrupt to core/DMA
3. Transfer data to CSEc memory (maximum 12 CAN messages of 8 bytes + 16-byte
CMAC)
4. Trigger CSEc CMAC calculation/verification
5. CSEc triggers interrupt to core
6. Core reads processed message data
Chapter 5 Security Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 95
Parameter RAM
n
n-1
n-2
n-3
n-4
9
8
7
6
5
4
3
2
1
16 Bytes Blocks
6
5
4
3
2
1
Parameter RAM
CMD Word
2
1
7
13
12
10
14
17
16
15
19
18
13
12
11
10
9
8
14
20
19
18
17
16
15
21
n-3
n-2
n-1
n
Input Output
CSEc
System Memory
function
processing
time
function
processing
time
function
processing
time
function
processing
time
KeyID0x06 0x00 0x00
CMD Word
MAC
7
MAC Len MSG Len
Length
KeyID0x06 0x00 0x01
CMD Word
MAC Len MSG Len
Length
KeyID0x06 0x00 0x01
CMD Word
MAC Len MSG Len
Length
KeyID0x06 0x00 0x01
CMD Word
MAC Len MSG Len
Length
3
4
5
6
Length
CMD Word Length
CMD Word Length
CMD Word Length
13
12
11
10
9
8
14
20
19
18
17
16
15
21
n-3
n-2 n-1
n
MACMAC
Ver Status
Figure 5-5. Message authentication
5.4 Steps required before failure analysis
Before returning a device to NXP for failure analysis, the user must run the
CMD_DBG_CHAL and CMD_DBG_AUTH commands and ensure that all user keys are
deleted. This is a mandatory step to enable failure analysis at NXP.
Steps required before failure analysis
S32K1xx Series Reference Manual, Rev. 7, 04/2018
96 NXP Semiconductors
NOTE
If WRITE_PROTECTION flag is set for any key then the user
will be unable to delete that key with DEBUG_CHAL and
DEBUG_AUTH commands and failure analysis would not be
possible.
5.5 Security programming flow example (Secure Boot)
1. Run PGMPART to configure desired number of keys and other parameters
2. Program code section in Pflash to be checked in secure boot
3. LOAD_KEY(BOOT_MAC_KEY)
4. CMD_BOOT_DEFINE to select the flavor of boot and size of data to validate in
Pflash
Then optionally reset the part to "auto calculate" and program the BOOT_MAC or
the user loads the BOOT_MAC by external calculation.
Chapter 5 Security Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 97
Security programming flow example (Secure Boot)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
98 NXP Semiconductors
Chapter 6
Safety Overview
6.1 Introduction
The S32K1xx series is developed according to ISO 26262 and has an integrated safety
concept targeting an ISO26262 ASIL-B integrity level. The following documentation
supports the integration of an S32K1xx chip into safety-related systems:
• Reference Manual (S32K1XXRM): describes the programming model and
functionality of S32K1xx chips
• Data Sheet (S32K1XX): describes S32K1xx operating conditions as well as timing
and electrical characteristics
• Safety Manual (S32K1XXSM): describes the S32K1xx safety concept and possible
safety mechanisms (integrated in S32K1xx, system-level hardware, or system-level
software) as well as measures to reduce dependent failures
• Dynamic FMEDA: inductive analysis enabling customization of system-level safety
mechanisms, including the resulting safety metrics for ISO 26262 (SPFM, LFM &
PMHF) and IEC 61508 (SFF & Beta IC Factor)
• FMEDA Report: describes the FMEDA methodology and safety mechanisms
supported in the FMEDA, including source of failure rates, failure modes, and
assumptions during the analysis
The S32K1xx series is a SafeAssure™ solution. For more information regarding
functional safety at NXP, visit http://www.nxp.com/safeassure.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 99
Figure 6-1. Functional safety overview
6.2 S32K1xx safety concept
The S32K1xx series has an integrated safety concept targeting safety-related systems that
require an ASIL-B safety integrity level. In general, safety integrity is achieved by using
and applying S32K1xx safety features as described in the Safety Manual.
The following diagram provides an overview of integrated S32K1xx architecture and
safety features.
S32K1xx safety concept
S32K1xx Series Reference Manual, Rev. 7, 04/2018
100 NXP Semiconductors
ENET
1: On this device, NXP’s system MPU implements the safety mechanisms to
prevent masters from accessing restricted memory regions. This system MPU
provides memory protection at the level of the Crossbar Switch. Each Crossbar
master (Core, DMA, Ethernet) can be assigned different access rights to each
protected memory region. The Arm M4 core version in this family does not
integrate the Arm Core MPU, which would concurrently monitor only core-initiated
memory accesses. In this document, the term MPU refers to NXP’s system MPU.
Device architectural IP on all
S32K devices.
Peripherals present on all
S32K devices.
Peripherals present on selected
S32K devices. See section
Feature Comparison.
Key:
DMA
mux
JTAG &
serial
wire
Async
trace
port
System MPU1
S0
Crossbar switch (AXBS-Lite)
M2
S3
M1
S2
M0
System MPU1
Mux
GPIO
iahb_gasket
QuadSPI
TCD
512B
Code Cache
Mux
System MPU1
SWJ-DP
TPIU
AHB-AP
PPB
Arm Cortex
M0+ / M4F Core
DSP
FPU
DWT
FPB
ITM
NVIC AWIC
S1
eDMA
Clock Generation
Power
supply
monitoring
Clock
monitoring
System
memory
protection
unit
ECC on
flash
memory
Core
self test
ECC on
SRAM
Peripheral
protection
Internal SW
watchdog
External SW
watchdog
CRC
Register
protection Diversity of digital
analog signal paths Diversity of
communication channels
Main
SRAM2
Lower
Region
Upper
Region
System
DCODE
ICODE
SPLL
4-40 MHz 8-40 MHz
SIRC
8 MHz FIRC
48 MHz
LPO
128 kHz SOSC
System MPU1
M3
WDOG 12-bit ADC LPI2C
EWM LPUART
CRC TRGMUX
FlexIO
FlexCAN
Low power
timer
FlexTimer
PDB
SAI
LPIT
Peripheral bus controller
CSEc
LPSPI
Code flash
memory Data flash
memory
Flash memory
controller
RTC
CMP
8-bit DAC
QuadSPI
2: See Memories and Memory Interfaces chapter: On-chip SRAM sizes table for Device specific sizes
FlexRAM/
SRAM
Figure 6-2. S32K1xx safety block diagram
Chapter 6 Safety Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 101
6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST)
Cortex-M4/M0+ Structural Core Self Test (SCST) is a software product from NXP. It
was developed for detecting hardware permanent faults in a core by executing machine
opcodes with a fixed set of operands and comparing their execution results. This library
is considered a Safety Element out of context and was developed according to ASIL-B.
The SCST delivery contains the SCST library, a quality package, and a safety package.
• The quality package contains code coverage analysis, a MISRA report, a software
requirements specification, and a Test Specification.
• The safety package consists of the SCST fault coverage estimation, the Safety
Analysis and Concept, and the SCST Safety Manual.
The Safety Manual for Structural Core Self Test Library contains a list of
recommendations and assumptions that should be fulfilled and verified by a user for the
proper use of the SCST library for a Cortex-M4/M0+ core.
6.2.2 ECC on RAM and flash memory
Error correcting codes are used to protect transfers from a CPU core to flash memory and
from a CPU core to system memory. Error Correcting Code (ECC) is implemented with
Single-Error Correction, Double-Error Detection (SECDED).
References:
• Functional description: in this Reference Manual, see MCM, EIM, ERM, LMEM,
and FTFC
• ECC on RAM and flash memory in safety concept: see Safety Manual
6.2.3 Power supply monitoring
S32K1xx includes a system for managing low-voltage conditions to protect memory
contents and control MCU system states during supply voltage variations.
• Power-on reset (POR)
• Low-voltage detection (LVD)
References:
• Functional description: in this Reference Manual, see Power Management
• Power supply monitoring in safety concept: see Safety Manual chapter
S32K1xx safety concept
S32K1xx Series Reference Manual, Rev. 7, 04/2018
102 NXP Semiconductors
6.2.4 Clock monitoring
Clocks in the S32K1xx are supervised by clock monitor units.
• System PLL clock monitor1 : monitors the loss of PLL clock
• System Oscillator (SOSC) clock monitor 2 : monitors the loss of oscillator clock
• CMU monitor3 FIRC clock for:
• Loss of clock
• Out of high and low range
References:
• Functional description: in this Reference Manual, see Clock Distribution
• Clock monitoring in safety concept: see Safety Manual chapter
6.2.5 Temporal protection
In a safety concept, watchdog timers provide temporal protection and monitor the
operation of the system by expecting periodic communication from the software.
S32K1xx offers two watchdog timers:
• Watchdog timer (WDOG) 4 : An independent timer that is available for system use. It
provides a safety feature to ensure that software is executing as planned and that the
CPU is not stuck in an infinite loop.
• External Watchdog Monitor (EWM) 5 : A redundant watchdog system for safety. The
EWM provides an independent output signal. It does not reset the MCU and
peripherals.
References:
• Functional description: in this Reference Manual, see WDOG and EWM
• Temporal protection in safety concept: see Safety Manual chapter
6.2.6 Operational interference protection
S32K1xx provides safety mechanisms to:
1. Available in S32K14x variants only
2. Available in all S32K1xx variants
3. Available in S32K11x only
4. Available in all S32K1xx variants
5. Available in S32K14x variants only
Chapter 6 Safety Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 103
• prevent non-safety masters from interfering with the operation of the Safety Core
• manage the concurrent execution of software with different (lower) ASIL
A hierarchical memory protection scheme, which includes the following, protects against
interference:
• System Memory Protection Unit (MPU)
• Peripheral Bridge (AIPS-Lite)
• Register protection
6.2.6.1 System Memory Protection Unit (MPU)
For ASIL-B applications, the system Memory Protection Unit (MPU) is used for
execution control. It assigns access rights and ensures that only authorized software tasks
can configure modules and access their allocated resources.
• The system MPU6 provides memory protection at the Crossbar Switch. It splits the
physical memory into 16 different regions.
• Each XBAR master (core, DMA, Ethernet) can be assigned different access rights to
each region.
• The system MPU can be used to prevent non-safety masters (including DMA or
Ethernet Controller) from accessing restricted memory regions.
References:
• Functional description: in this Reference Manual, see MPU
• MPU in safety concept: see Safety Manual chapter
6.2.6.2 Peripheral protection
Peripheral protection is based on the Peripheral Bridge (AIPS-Lite) module. It provides
memory protection functionality by defining bus masters' access rights to various
peripherals on the chip.
References:
• Functional description: in this Reference Manual, see AIPS-Lite
• Peripheral protection in safety concept: see Safety Manual chapter
6. On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from accessing
restricted memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each
Crossbar master (Core, DMA, Ethernet) can be assigned different access rights to each protected memory region.
The Arm M4 core version in this family does not integrate the Arm Core MPU, which would concurrently monitor
only core-initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU.
S32K1xx safety concept
S32K1xx Series Reference Manual, Rev. 7, 04/2018
104 NXP Semiconductors
6.2.6.3 Register protection
S32K1xx offers register protection for safety-critical registers. This protection is based on
CPU program execution mode—User vs. Supervisor (privileged) mode—as well as
another type of access restriction based on a lock feature implemented for certain
registers. The lock-based access restriction inhibits a register update until the next system
reset or requires a special key to unlock access.
References:
• Functional description: in this Reference Manual, see notes about register protection
features for a specific register or a group of registers in the register-description
sections for SIM, SCG, ERM, RCM, MSCM, and others
• Register protection in safety concept: see Safety Manual
6.2.7 CRC
The CRC unit supports the detection of accidental alteration of data in memory or
configuration registers by calculating its CRC signature and comparing it to a previously
calculated CRC. The CRC module can also detect erroneous corruption of data during
transmission or storage.
References:
• Functional description: in this Reference Manual, see CRC
• CRC in safety concept: see Safety Manual chapter
6.2.8 Diversity of system resources
Features that are relevant to functional safety usually have redundant support in the
system. S32K1xx offers a diversity of system resources to provide this support.
• Digital inputs can be replicated to acquire safety-critical inputs redundantly
• Safety-critical digital outputs can always be written redundantly or in combination
with a read-back operation
• Analog inputs can operate in oversampling mode to detect transient faults affecting
the ADC channel, and two ADC units can acquire and digitize redundant copies of
an analog signal connected to a safety-relevant signal
• For cases of communication-channel redundancy for safety reasons, S32K1xx offers
redundant instances of communication peripherals:
• Synchronous Serial Communication Controller (LPSPI) modules
Chapter 6 Safety Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 105
• FlexIO module: capable of supporting a wide range of protocols (UART, I2C,
SPI, I2S) and PWM/waveform generation
• UART modules: support UART and LIN communication
References:
• Functional description: in this Reference Manual, see SIM, LPSPI, LPI2C, FlexIO,
and LPUART
• Diversity of system resources in safety concept: see Safety Manual
S32K1xx safety concept
S32K1xx Series Reference Manual, Rev. 7, 04/2018
106 NXP Semiconductors
Chapter 7
CM4 Overview
7.1 Arm Cortex-M4F core configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by Arm and can be found at arm.com.
PPB
modules
PPB
Arm Cortex-M4
core
Debug
Interrupts
Crossbar
switch
Figure 7-1. Core configuration
Table 7-1. Reference links to related information
Topic Related module Reference
Full description Arm Cortex-M4F core Arm Cortex-M4F Technical Reference Manual
— ARM Cortex-M4
Devices Generic User
Guide
ARM Cortex-M4 Devices Generic User Guide
System memory map — See the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
Debug IEEE 1149.1 JTAG
Serial Wire Debug
(SWD)
Arm Real-Time Trace
Interface
Debug
Table continues on the next page...
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 107
Table 7-1. Reference links to related information (continued)
Topic Related module Reference
Interrupts Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Private Peripheral Bus
(PPB) module
Miscellaneous Control
Module (MCM)
MCM
Private Peripheral Bus
(PPB) module
Single-precision floating
point unit (FPU)
FPU
7.1.1 Buses, interconnects, and interfaces
The Arm Cortex-M4 core has four buses as described in the following table.
Table 7-2. Arm core buses
Bus name Description
Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is
connected to the crossbar switch via a single master port.
Data code (DCODE) bus
System bus The system bus is connected to a separate master port on the crossbar.
Private peripheral (PPB) bus The PPB provides access to these modules:
• Arm modules such as the NVIC, ITM, DWT, FBP, and ROM table
• NXP Miscellaneous Control Module (MCM)
7.1.2 System Tick Timer
The System Tick Timer's clock source is always the core clock, CORE_CLK. This results
in the following:
• The CLKSOURCE bit in SysTick Control and Status register is always set to select
the core clock.
• Because the timing reference (CORE_CLK) is a variable frequency, the TENMS bit
in the SysTick Calibration Value Register is always zero.
• The NOREF bit in SysTick Calibration Value Register is always set, implying that
CORE_CLK is the only available source of reference timing.
Arm Cortex-M4F core configuration
S32K1xx Series Reference Manual, Rev. 7, 04/2018
108 NXP Semiconductors
7.1.3 Debug facilities
This chip has extensive debug capabilities including run control and tracing capabilities.
This is a standard Arm debug port that supports JTAG and SWD interfaces.
7.1.4 Caches
This device includes one 4 KB code cache to minimize the performance impact of
memory access latencies. The code cache exists on the I/D bus, and there is no cache on
the system bus.
Features of the cache are:
• 2-way set associative
• 4 word lines
• Lines can be individually flushed
• Entire cache can be flushed at once
7.1.4.1 Control
For control purposes, the cache can be in one of these states:
1. Write Back / Write Allocate (WBWA)
2. Write Through
3. No cache
For each defined region there will be 2 bits allocated on the control register (see
PCCRMR that determines the cache state for the memory region associated with this
section. The user can only "lower" the cache attribute, given the fixed relationship of
WBWA > WT > NC - so, you can demote a WBWA region to either WT or NC, you can
demote a WT space to NC. In order to change the state upwards a system reset is
required.
NOTE
See LMEM for the cache reset states.
7.1.5 Core privilege levels
The Arm documentation uses different terms than this document to distinguish between
privilege levels.
Chapter 7 CM4 Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 109
Table 7-3. Terms used
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User
7.2 Nested Vectored Interrupt Controller (NVIC)
Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by Arm and can be found at arm.com.
Nested Vectored
Interrupt Controller
(NVIC)
Arm
Cortex-M4
core
Interrupts Module
Module
Module
PPB
Figure 7-2. NVIC configuration
Table 7-4. Reference links to related information
Topic Related module Reference
Full description Nested Vectored
Interrupt Controller
(NVIC)
Arm Cortex-M4F Technical Reference Manual - Nested Vectored Interrupt
Controller
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
Private Peripheral Bus
(PPB)
Arm Cortex-M4 core Arm Cortex-M4F Technical Reference Manual - Private Peripheral Bus
(PPB)
7.2.1 Interrupt priority levels
This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source
in the IPR registers contains 4 bits. For example, the IPR0 diagram is shown below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIRQ3 0000 IRQ2 0000 IRQ1 0 0 0 0 IRQ0 0 0 0 0
W
Nested Vectored Interrupt Controller (NVIC) Configuration
S32K1xx Series Reference Manual, Rev. 7, 04/2018
110 NXP Semiconductors
7.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin on which the NMI signal is multiplexed must be configured for the NMI function
in order to generate the non-maskable interrupt request.
See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual
for details on NMI pad.
7.2.3 Determining the bitfield and register location for
configuring a particular interrupt
Suppose you need to configure the low-power timer (LPTMR) interrupt. The following
table is an excerpt of the LPTMR row from the file
'S32K1xx_DMA_INT_mapping.xlsm' attached to this Reference Manual.
Table 7-6. LPTMR interrupt vector assignment
Address Vector IRQ1NVIC non-IPR
register number2NVIC IPR register
number3Source module
0x0000_0128 74 58 1 14 Low Power Timer
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this
value is: IRQ div 32
3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
The NVIC registers you would use to configure the interrupt are:
• NVICISER1
• NVICICER1
• NVICISPR1
• NVICICPR1
• NVICIABR1
• NVICIPR14
To determine the particular IRQ's bitfield location within these particular registers:
• NVICISER1, NVICICER1, NVICISPR1, NVICICPR1, NVICIABR1 bit location =
IRQ mod 32 = 26
• NVICIPR14 bitfield starting location = 8 × (IRQ mod 4) + 4 = 20
Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14
bitfield range is 20-23
Chapter 7 CM4 Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 111
Therefore, the following bitfield locations are used to configure the LPTMR interrupts:
• NVICISER1[26]
• NVICICER1[26]
• NVICISPR1[26]
• NVICICPR1[26]
• NVICIABR1[26]
• NVICIPR14[23:20]
7.3 Asynchronous Wake-up Interrupt Controller (AWIC)
Configuration
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Figure 7-3. Asynchronous Wake-up Interrupt Controller configuration
Table 7-7. Reference links to related information
Topic Related module Reference
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to Reference Manual
for details.
Clocking — Clock distribution
Power management — Power management
Nested Vectored
Interrupt Controller
(NVIC)
—NVIC
Wake-up requests — AWIC wake-up sources
7.3.1 Wake-up sources
Table 7-8. AWIC stop and VLPS wake-up sources
Wake-up source Description
Available system resets RESET pin, WDOG, JTAG
Table continues on the next page...
Asynchronous Wake-up Interrupt Controller (AWIC) Configuration
S32K1xx Series Reference Manual, Rev. 7, 04/2018
112 NXP Semiconductors
Table 7-8. AWIC stop and VLPS wake-up sources (continued)
Wake-up source Description
Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
CMP (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
LPI2C0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPUART (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3)Functional in VLPS mode with
SIRC as clock source
LPSPI (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPTMR0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
RTC (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) RTC running in VLPS from
either LPO or RTC_CLKIN. Wakeup from alarm interrupt
CAN PNET is supported in STOP1/2 modes and will cause wake up. Only CAN0 supports PNET
feature.
NMI Non-maskable interrupt
WDOG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
FlexIO (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
LPIT (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source.
EWM Module off in STOP1 and VLPS. Can cause wakeup through sync Interrupt in STOP2.
CRC Module off in STOP1 and VLPS. Can cause wakeup through sync Interrupt in STOP2.
SCG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
7.4 FPU configuration
This section summarizes how the module has been configured in the chip.
FPU
transfers
Arm Cortex M4
core
PPB
Figure 7-4. FPU configuration
Table 7-9. Reference links to related information
Topic Related module Reference
Full description FPU Arm Cortex-M4 Technical Reference Manual - Floating-Point Unit
Table continues on the next page...
Chapter 7 CM4 Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 113
Table 7-9. Reference links to related information (continued)
Topic Related module Reference
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock Distribution
Power Management — Power Management
Transfers
Private Peripheral Bus
(PPB)
Arm Cortex M4 core Arm Cortex-M4 Technical Reference Manual - Private Peripheral Bus
7.5 JTAG controller configuration
This section summarizes how the module has been configured in the chip.
Signal
multiplexing
JTAG controller
Figure 7-5. JTAG controller configuration
Table 7-10. Reference links to related information
Topic Related module Reference
Full description JTAGC JTAGC
Signal multiplexing Port control See IO Signal Description Input Multiplexing sheet(s) attached to the
Reference Manual attached to this document for details.
JTAG controller configuration
S32K1xx Series Reference Manual, Rev. 7, 04/2018
114 NXP Semiconductors
Chapter 8
CM0+ Overview
8.1 Arm Cortex-M0+ core introduction
The enhanced Arm Cortex M0+ is the member of the Cortex-M Series of processors
targeting microcontroller cores focused on very cost sensitive, low power applications. It
has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also
has hardware debug functionality including support for simple program trace capability.
The processor supports the Armv6-M instruction set (Thumb) architecture including all
but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward
compatible with other Cortex-M profile processors.
Table 8-1. Reference links to related information
Topic Related module Reference
Full description Arm Cortex-M0+ core Arm Cortex-M0+ Technical Reference Manual
— ARM Cortex-M0
Devices Generic User
Guide
ARM Cortex-M0 Devices Generic User Guide
System memory map — See the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
Debug IEEE 1149.1 JTAG
Serial Wire Debug
(SWD)
MTB
Arm Real-Time Trace
Interface
Debug
Interrupts Nested Vectored
Interrupt Controller
(NVIC)
NVIC
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 115
8.1.1 Buses, interconnects, and interfaces
The Arm Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
• Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores
8.1.2 System tick timer
The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.
8.1.3 Debug facilities
This device supports standard Arm 2-pin SWD debug port.
8.1.4 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
Arm documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User
Arm Cortex-M0+ core introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
116 NXP Semiconductors
Nested vectored interrupt controller (NVIC)
8.2.1 Interrupt priority levels
This device supports four priority levels for interrupts. Therefore, in the NVIC, each
source in the IPR registers contains two bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIRQ3 000000IRQ2 000000IRQ1 0 0 0 0 0 0 IRQ0 0 0 0 0 0 0
W
8.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request. See IO Signal Description Input
Multiplexing sheet(s) attached to the Reference Manual for details on NMI pad.
8.2.3 Determining the bitfield and register location for
configuring a particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the
FlexCAN row from the file 'S32K1xx_DMA_INT_mapping.xlsm' attached to this
Reference Manual.
Table 8-3. Interrupt vector assignments
Address Vector IRQ1NVIC IPR
register
number2
Source
module
0x0000_006C 27 11 2 FlexCAN
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.
• The NVIC registers you would use to configure the interrupt are:
• NVICIPR2
• To determine the particular IRQ's field location within these particular registers:
• NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22
8.2
Chapter 8 CM0+ Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 117
Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field
range is 22–23.
Therefore, the following field locations are used to configure the FlexCAN interrupts:
• NVICIPR2[23:22]
8.3 AWIC introduction
The primary function of the AWIC block is to detect asynchronous wake-up events in
stop modes and signal to clock control logic to resume system clocking. After clock
restart, the NVIC observes the pending interrupt and performs the normal interrupt or
event processing.
Table 8-4. Reference links to related information
Topic Related module Reference
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to Reference Manual
for details.
Clocking — Clock distribution
Power management — Power management
Nested Vectored
Interrupt Controller
(NVIC)
—NVIC
Wake-up requests — AWIC wake-up sources
8.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 8-5. AWIC stop and VLPS wake-up sources
Wake-up source Description
Available system resets RESET pin, WDOG, JTAG
Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
CMP (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
LPI2C0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPUART (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
Table continues on the next page...
AWIC introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
118 NXP Semiconductors
Table 8-5. AWIC stop and VLPS wake-up sources (continued)
Wake-up source Description
LPSPI (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPTMR0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
RTC (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3 )RTC running in VLPS from
either LPO or RTC_CLKIN. Wakeup from alarm interrupt
CAN PNET is supported in STOP1/2 modes and will cause wake up. Only CAN0 supports PNET
feature.
NMI Non-maskable interrupt
WDOG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
FlexIO (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
LPIT (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
CRC Module off in STOP1 and VLPS. Can cause wakeup through sync Interrupt in STOP2.
SCG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
Chapter 8 CM0+ Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 119
AWIC introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
120 NXP Semiconductors
Chapter 9
Micro Trace Buffer (MTB)
9.1 Introduction
Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight
Micro Trace Buffer to provide program trace capabilities.
The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-
M0+ Processor; in this document, it is simply abbreviated as the MTB.
The simple program trace function creates instruction address change-of-flow data
packets in a user-defined region of the system RAM. Accordingly, the system RAM
controller manages requests from two sources:
• AMBA-AHB reads and writes from the system bus
• program trace packet writes from the processor
As part of the MTB functionality, there is a MTB_DWT (Data Watchpoint and Trace)
module that allows the user to define watchpoint addresses, or optionally, an address and
data value, that when triggered, can be used to start or stop the program trace recording.
9.1.1 Overview
As shown in the main block diagram, the platform RAM (PRAM) controller connects to
two input buses:
• the crossbar slave port for system bus accesses
• a "private execution MTB port" from the core
The logical paths from the crossbar master input ports to the PRAM controller are
highlighted along with the private execution trace port from the processor core. The
private MTB port signals the instruction address information needed for the 64-bit
program trace packets written into the system RAM. The PRAM controller output
interfaces to the attached RAM array. In this document, the PRAM controller is the
MTB_RAM controller.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 121
The following information is taken from the ARM CoreSight Micro Trace Buffer
documentation.
"The execution trace packet consists of a pair of 32-bit words that the MTB generates
when it detects the processor PC value changes non-sequentially. A non-sequential PC
change can occur during branch instructions or during exception entry.
The processor can cause a trace packet to be generated for any instruction.
The following figure shows how the execution trace information is stored in memory as a
sequence of packets.
Incrementing
SRAM memory
address
Nth destination address
Nth source address
S
A
31 0
1
2nd destination address
2nd source address
S
A
31 0
1
1st destination address
1st source address
S
A
Atom bit
Start bit
Odd word address
Even word address
Odd word address
Even word address
Figure 9-1. MTB execution trace storage format
The first, lower addressed, word contains the source of the branch, the address it
branched from. The value stored only records bits[31:1] of the source address, because
Thumb instructions are at least halfword aligned. The least significant bit of the value is
the A-bit. The A-bit indicates the atomic state of the processor at the time of the branch,
and can differentiate whether the branch originated from an instruction in a program, an
exception, or a PC update in Debug state. When it is zero the branch originated from an
instruction, when it is one the branch originated from an exception or PC update in
Debug state. This word is always stored at an even word location.
The second, higher addressed word contains the destination of the branch, the address it
branched to. The value stored only records bits[31:1] of the branch address. The least
significant bit of the value is the S-bit. The S-bit indicates where the trace started. An S-
bit value of 1 indicates where the first packet after the trace started and a value of 0 is
used for other packets. Because it is possible to start and stop tracing multiple times in a
trace session, the memory might contain several packets with the S-bit set to 1. This word
is always stored in the next higher word in memory, an odd word address.
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
122 NXP Semiconductors
When the A-bit is set to 1, the source address field contains the architecturally-preferred
return address for the exception. For example, if an exception was caused by an SVC
instruction, then the source address field contains the address of the following instruction.
This is different from the case where the A-bit is set to 0. In this case, the source address
contains the address of the branch instruction.
For an exception return operation, two packets are generated:
• The first packet has the:
• Source address field set to the address of the instruction that causes the exception
return, BX or POP.
• Destination address field set to bits[31:1] of the EXC_RETURN value. See the
ARM v6-M Architecture Reference Manual.
• The A-bit set to 0.
• The second packet has the:
• Source address field set to bits[31:1] of the EXC_RETURN value.
• Destination address field set to the address of the instruction where execution
commences.
• A-bit set to 1."
Given the recorded change-of-flow trace packets in system RAM and the memory image
of the application, a debugger can read out the data and create an instruction-by-
instruction program trace. In keeping with the low area and power implementation cost
design targets, the MTB trace format is less efficient than other CoreSight trace modules,
for example, the ETM (Embedded Trace Macrocell). Since each branch packet is 8 bytes
in size, a 1 KB block of system RAM can contain 128 branches. Using the Dhrystone 2.1
benchmark's dynamic runtime as an example, this corresponds to about 875 instructions
per KB of trace RAM, or with a zero wait state memory, this corresponds to
approximately 1600 processor cycles per KB. This metric is obviously very sensitive to
the runtime characteristics of the user code.
The MTB_DWT function (not shown in the core platform block diagram) monitors the
processor address and data buses so that configurable watchpoints can be detected to
trigger the appropriate response in the MTB recording.
9.1.2 Features
The key features of the MTB_RAM and MTB_DWT include:
• Memory controller for system RAM and Micro Trace Buffer for program trace
packets
• Read/write capabilities for system RAM accesses, write-only for program trace
packets
Chapter 9 Micro Trace Buffer (MTB)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 123
• Supports zero wait state response to system bus accesses when no trace data is being
written
• Can buffer two AHB address phases and one data write for system RAM accesses
• Supports 64-bit program trace packets including source and destination instruction
addresses
• Program trace information in RAM available to MCU's application code or external
debugger
• Program trace watchpoint configuration accessible by MCU's application code or
debugger
• Location and size of RAM trace buffer is configured by software
• Two DWT comparators (addresses or address + data) provide programmable start/
stop recording
• CoreSight compliant debug functionality
9.1.3 Modes of operation
The MTB_RAM and MTB_DWT functions do not support any special modes of
operation. The MTB_RAM controller, as a memory-mapped device located on the
platform's slave AHB system bus, responds strictly on the basis of memory addresses for
accesses to its attached RAM array. The MTB private execution bus provides program
trace packet write information to the RAM controller. Both the MTB_RAM and
MTB_DWT modules are memory-mapped, so their programming models can be
accessed.
All functionality associated with the MTB_RAM and MTB_DWT modules resides in the
core platform's clock domain; this includes its connections with the RAM array.
9.2 Memory map and register definition
The MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KB
address space for their programming models. For each address space, there are a variety
of control and configurable registers near the base address, followed by a large unused
address space and finally a set of CoreSight registers to support dynamic determination of
the debug configuration for the device.
Accesses to the programming model follow standard ARM conventions. Taken from the
ARM CoreSight Micro Trace Buffer documentation, these are:
• Do not attempt to access reserved or unused address locations. Attempting to access
these locations can result in UNPREDICTABLE behavior.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
124 NXP Semiconductors
• The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN
reset values are not programmed prior to enabling trace.
• Unless otherwise stated in the accompanying text:
• Do not modify reserved register bits
• Ignore reserved register bits on reads
• All register bits are reset to a logic 0 by a system or power-on reset
• Use only word size, 32-bit, transactions to access all registers
9.2.1 MTB_DWT Memory Map
The MTB_DWT programming model supports a very simplified subset of the v7M debug
architecture and follows the standard ARM DWT definition.
MTB_DWT memory map
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
0 MTB DWT Control Register (MTB_DWT_CTRL) 32 R 2F00_0000h 9.2.1.1/126
20 MTB_DWT Comparator Register (MTB_DWT_COMP0) 32 R/W 0000_0000h 9.2.1.2/127
24 MTB_DWT Comparator Mask Register
(MTB_DWT_MASK0) 32 R/W 0000_0000h 9.2.1.3/127
28 MTB_DWT Comparator Function Register 0
(MTB_DWT_FCT0) 32 R/W 0000_0000h 9.2.1.4/128
30 MTB_DWT Comparator Register (MTB_DWT_COMP1) 32 R/W 0000_0000h 9.2.1.2/127
34 MTB_DWT Comparator Mask Register
(MTB_DWT_MASK1) 32 R/W 0000_0000h 9.2.1.3/127
38 MTB_DWT Comparator Function Register 1
(MTB_DWT_FCT1) 32 R/W 0000_0000h 9.2.1.5/130
200 MTB_DWT Trace Buffer Control Register
(MTB_DWT_TBCTRL) 32 R/W 2000_0000h 9.2.1.6/131
FC8 Device Configuration Register (MTB_DWT_DEVICECFG) 32 R 0000_0000h 9.2.1.7/133
FCC Device Type Identifier Register (MTB_DWT_DEVICETYPID) 32 R 0000_0004h 9.2.1.8/133
FD0 Peripheral ID Register (MTB_DWT_PERIPHID4) 32 R See section 9.2.1.9/134
FD4 Peripheral ID Register (MTB_DWT_PERIPHID5) 32 R See section 9.2.1.9/134
FD8 Peripheral ID Register (MTB_DWT_PERIPHID6) 32 R See section 9.2.1.9/134
FDC Peripheral ID Register (MTB_DWT_PERIPHID7) 32 R See section 9.2.1.9/134
FE0 Peripheral ID Register (MTB_DWT_PERIPHID0) 32 R See section 9.2.1.9/134
FE4 Peripheral ID Register (MTB_DWT_PERIPHID1) 32 R See section 9.2.1.9/134
FE8 Peripheral ID Register (MTB_DWT_PERIPHID2) 32 R See section 9.2.1.9/134
FEC Peripheral ID Register (MTB_DWT_PERIPHID3) 32 R See section 9.2.1.9/134
FF0 Component ID Register (MTB_DWT_COMPID0) 32 R See section 9.2.1.10/
134
FF4 Component ID Register (MTB_DWT_COMPID1) 32 R See section 9.2.1.10/
134
Table continues on the next page...
Chapter 9 Micro Trace Buffer (MTB)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 125
MTB_DWT memory map (continued)
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
FF8 Component ID Register (MTB_DWT_COMPID2) 32 R See section 9.2.1.10/
134
FFC Component ID Register (MTB_DWT_COMPID3) 32 R See section 9.2.1.10/
134
9.2.1.1 MTB DWT Control Register (MTB_DWT_CTRL)
The MTBDWT_CTRL register provides read-only information on the watchpoint
configuration for the MTB_DWT.
Address: 0h base + 0h offset = 0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNUMCMP DWTCFGCTRL
W
Reset 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTB_DWT_CTRL field descriptions
Field Description
31–28
NUMCMP
Number of comparators
The MTB_DWT implements two comparators.
DWTCFGCTRL DWT configuration controls
This field is hardwired to 0xF00_0000, disabling all the remaining DWT functionality. The specific fields
and their state are:
MTBDWT_CTRL[27] = NOTRCPKT = 1, trace sample and exception trace is not supported
MTBDWT_CTRL[26] = NOEXTTRIG = 1, external match signals are not supported
MTBDWT_CTRL[25] = NOCYCCNT = 1, cycle counter is not supported
MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling counters are not supported
MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT underflow packets generated
MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction counter overflow events
MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow events
MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events
MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events
MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events
MTBDWT_CTRL[16] = EXCTRCENA = 0, generation of exception trace disabled
MTBDWT_CTRL[12] = PCSAMPLENA = 0, no periodic PC sample packets generated
MTBDWT_CTRL[11:10] = SYNCTAP = 0, no synchronization packets
MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not supported
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
126 NXP Semiconductors
MTB_DWT_CTRL field descriptions (continued)
Field Description
MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported
MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported
MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported
9.2.1.2 MTB_DWT Comparator Register (MTB_DWT_COMPn)
The MTBDWT_COMPn registers provide the reference value for comparator n.
Address: 0h base + 20h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCOMP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTB_DWT_COMPn field descriptions
Field Description
COMP Reference value for comparison
If MTBDWT_COMP0 is used for a data value comparator and the access size is byte or halfword, the data
value must be replicated across all appropriate byte lanes of this register. For example, if the data is a
byte-sized "x" value, then COMP[31:24] = COMP[23:16] = COMP[15:8] = COMP[7:0] = "x". Likewise, if the
data is a halfword-size "y" value, then COMP[31:16] = COMP[15:0] = "y".
9.2.1.3 MTB_DWT Comparator Mask Register (MTB_DWT_MASKn)
The MTBDWT_MASKn registers define the size of the ignore mask applied to the
reference address for address range matching by comparator n. Note the format of this
mask field is different than the MTB_MASTER[MASK].
Address: 0h base + 24h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTB_DWT_MASKn field descriptions
Field Description
31–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
MASK MASK
Table continues on the next page...
Chapter 9 Micro Trace Buffer (MTB)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 127
MTB_DWT_MASKn field descriptions (continued)
Field Description
The value of the ignore mask, 0-31 bits, is applied to address range matching. MASK = 0 is used to
include all bits of the address in the comparison, except if MASK = 0 and the comparator is configured to
watch instruction fetch addresses, address bit [0] is ignored by the hardware since all fetches must be at
least halfword aligned. For MASK != 0 and regardless of watch type, address bits [x-1:0] are ignored in the
address comparison.
Using a mask means the comparator matches on a range of addresses, defined by the unmasked most
significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a 16 Mbyte mask.
An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24.
If MTBDWT_COMP0 is used as a data value comparator, then MTBDWT_MASK0 should be programmed
to zero.
9.2.1.4 MTB_DWT Comparator Function Register 0 (MTB_DWT_FCT0)
The MTBDWT_FCTn registers control the operation of comparator n.
Address: 0h base + 28h offset = 28h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
MATCHED
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATAVADDR0 DATAVSIZE
0
DATAVMATCH
0
FUNCTION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
128 NXP Semiconductors
MTB_DWT_FCT0 field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24
MATCHED
Comparator match
If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since
the last read of the register. Reading the register clears this bit.
0 No match.
1 Match occurred.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–12
DATAVADDR0
Data Value Address 0
Since the MTB_DWT implements two comparators, the DATAVADDR0 field is restricted to values {0,1}.
When the DATAVMATCH bit is asserted, this field defines the comparator number to use for linked
address comparison.
If MTBDWT_COMP0 is used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint,
DATAVADDR0 must be set.
11–10
DATAVSIZE
Data Value Size
For data value matching, this field defines the size of the required data comparison.
00 Byte.
01 Halfword.
10 Word.
11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DATAVMATCH
Data Value Match
When this field is 1, it enables data value comparison. For this implementation, MTBDWT_COMP0
supports address or data value comparisons; MTBDWT_COMP1 only supports address comparisons.
0 Perform address comparison.
1 Perform data value comparison.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FUNCTION Function
Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and
MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this
configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on
a range of addresses.
0000 Disabled.
0100 Instruction fetch.
0101 Data operand read.
0110 Data operand write.
0111 Data operand (read + write).
others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
Chapter 9 Micro Trace Buffer (MTB)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 129
MTB_DWT_FCT0 field descriptions (continued)
Field Description
9.2.1.5 MTB_DWT Comparator Function Register 1 (MTB_DWT_FCT1)
The MTBDWT_FCTn registers control the operation of comparator n. Since the
MTB_DWT only supports data value comparisons on comparator 0, there are several
fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8).
Address: 0h base + 38h offset = 38h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
MATCHED
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
FUNCTION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTB_DWT_FCT1 field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
130 NXP Semiconductors
MTB_DWT_FCT1 field descriptions (continued)
Field Description
24
MATCHED
Comparator match
If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since
the last read of the register. Reading the register clears this bit.
0 No match.
1 Match occurred.
23–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FUNCTION Function
Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and
MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this
configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on
a range of addresses.
0000 Disabled.
0100 Instruction fetch.
0101 Data operand read.
0110 Data operand write.
0111 Data operand (read + write).
others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
9.2.1.6 MTB_DWT Trace Buffer Control Register
(MTB_DWT_TBCTRL)
The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the
actual trace buffer operation.
Recall the MTB supports starting and stopping the program trace based on the watchpoint
comparisons signaled via TSTART and TSTOP. The watchpoint comparison signals are
enabled in the MTB's control logic by setting the appropriate enable bits,
MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of
both TSTART and TSTOP, TSTART takes priority. There are two signals formed by the
MTB_DWT module and driven to the MTB_RAM controller: TSTART (trace start) and
TSTOP (trace stop). These signals can be configured using the trace watchpoints to
define programmable addresses and data values to affect the program trace recording
state.
Chapter 9 Micro Trace Buffer (MTB)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 131
Address: 0h base + 200h offset = 200h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNUMCOMP 0
W
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
ACOMP1
ACOMP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTB_DWT_TBCTRL field descriptions
Field Description
31–28
NUMCOMP
Number of Comparators
This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes
two registers.
27–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
ACOMP1
Action based on Comparator 1 match
When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has
triggered and the trace buffer's recording state is changed.
0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
0
ACOMP0
Action based on Comparator 0 match
When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address compare has
triggered and the trace buffer's recording state is changed. The assertion of MTBDWT_FCT0[MATCHED]
is caused by the following conditions:
• Address match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0
• Data match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0}
• Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when
MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1}
0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
132 NXP Semiconductors
9.2.1.7 Device Configuration Register (MTB_DWT_DEVICECFG)
This register indicates the device configuration. It is hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: 0h base + FC8h offset = FC8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDEVICECFG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTB_DWT_DEVICECFG field descriptions
Field Description
DEVICECFG DEVICECFG
Hardwired to 0x0000_0000.
9.2.1.8 Device Type Identifier Register (MTB_DWT_DEVICETYPID)
This register indicates the device type ID. It is hardwired to specific values used during
the auto-discovery process by an external debug agent.
Address: 0h base + FCCh offset = FCCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDEVICETYPID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
MTB_DWT_DEVICETYPID field descriptions
Field Description
DEVICETYPID DEVICETYPID
Hardwired to 0x0000_0004.
Chapter 9 Micro Trace Buffer (MTB)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 133
9.2.1.9 Peripheral ID Register (MTB_DWT_PERIPHIDn)
These registers indicate the peripheral IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: 0h base + FD0h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPERIPHID
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
MTB_DWT_PERIPHIDn field descriptions
Field Description
PERIPHID PERIPHID
Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.
9.2.1.10 Component ID Register (MTB_DWT_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: 0h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCOMPID
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
MTB_DWT_COMPIDn field descriptions
Field Description
COMPID Component ID
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
134 NXP Semiconductors
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Chip-specific MCM information
The following table summarizes the chip-specific register reset values of this module for
each chip in the product series.
Table 10-1. MCM register reset values
Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
MCM_LMDR0 8104_0000 8104_0000 8504_0003 8604_0003 8704_0003 8804_0003
MCM_LMDR1 8504_2003 9604_2003 8504_2003 8604_2003 8704_2003 8804_2003
MCM_LMDR2 NA NA 8424_40A0 8424_40A0 8424_40A0 8424_40A0
MCM_PLASC 0007 0007 0007 0007 0007 000F
MCM_PLAMC 0005 0005 0007 0007 0007 000F
NOTE
For S32K11x , LMDR information can be inferred for SRAM
size as below:
• S32K116: LMDR1[LMSZH]=0, LMDR1[LMSZH]=0x5 ,
so SRAM_U size 1*(16) KB = 16 KB. Actual size is 16
KB – 2 KB = 14 KB
• S32K118: LMDR1[LMSZH]=1, LMDR1[LMSZH]=0x6 ,
so SRAM_U size 0.75*(32) KB = 24 KB. Actual size is 24
KB – 2 KB = 22 KB
Address offset of LMPEIR register varies between S32K14x and S32K11x as given
below.
Table 10-2. MCM register offset
Register S32K14x offset S32K11x offset
MCM_LMPEIR 0x488 0x484
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 135
10.2 Introduction
The Miscellaneous Control Module (MCM) provides miscellaneous control functions.
NOTE
• Cache write buffer is not supported on S32K1xx.
• ECC on SRAML/MTB, FPU, and Cache is not supported
on S32K11x.
10.2.1 Features
The MCM includes the following feature:
• Program-visible information on the platform configuration and revision
10.3 Memory map/register descriptions
The memory map and register descriptions below describe the Miscellaneous Control
Module registers.
NOTE
• All registers are accessible only in Supervisor mode. User
mode accesses will generate an error.
• Writing to read-only MCM_PLASC and MCM_PLAMC
registers, would generate a bus error.
MCM memory map
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
8Crossbar Switch (AXBS) Slave Configuration
(MCM_PLASC) 16 R 0007h 10.3.1/137
ACrossbar Switch (AXBS) Master Configuration
(MCM_PLAMC) 16 R 0007h 10.3.2/138
C Core Platform Control Register (MCM_CPCR) 32 R/W See section 10.3.3/139
10 Interrupt Status and Control Register (MCM_ISCR) 32 R 0002_0000h 10.3.4/142
30 Process ID Register (MCM_PID) 32 R/W 0000_0000h 10.3.5/145
40 Compute Operation Control Register (MCM_CPO) 32 R/W 0000_0000h 10.3.6/146
400 Local Memory Descriptor Register (MCM_LMDR0) 32 R/W See section 10.3.7/147
404 Local Memory Descriptor Register (MCM_LMDR1) 32 R/W See section 10.3.7/147
Table continues on the next page...
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
136 NXP Semiconductors
MCM memory map (continued)
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
408 Local Memory Descriptor Register2 (MCM_LMDR2) 32 R/W 8424_40A0h 10.3.8/150
480 LMEM Parity and ECC Control Register (MCM_LMPECR) 32 R/W 0000_0000h 10.3.9/154
488 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR) 32 R/W 0000_0000h 10.3.10/155
490 LMEM Fault Address Register (MCM_LMFAR) 32 R 0000_0000h 10.3.11/156
494 LMEM Fault Attribute Register (MCM_LMFATR) 32 R 0000_0000h 10.3.12/157
4A0 LMEM Fault Data High Register (MCM_LMFDHR) 32 R 0000_0000h 10.3.13/158
4A4 LMEM Fault Data Low Register (MCM_LMFDLR) 32 R 0000_0000h 10.3.14/158
10.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
PLASC is a 16-bit read-only register identifying the presence/absence of bus slave
connections to the device’s crossbar switch.
Address: 0h base + 8h offset = 8h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 ASC
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
MCM_PLASC field descriptions
Field Description
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's
slave input port.
0 A bus slave connection to AXBS input port n is absent
1 A bus slave connection to AXBS input port n is present
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 137
10.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master
connections to the device's crossbar switch.
Address: 0h base + Ah offset = Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 AMC
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
MCM_PLAMC field descriptions
Field Description
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
138 NXP Semiconductors
10.3.3 Core Platform Control Register (MCM_CPCR)
CPCR defines the arbitration and protection schemes for the two system RAM arrays.
Address: 0h base + Ch offset = Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
SRAMLWP
SRAMLAP
0
SRAMUWP
SRAMUAP Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 139
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved CBR
RReserved
PBRIDGE_IDLE
Reserved
FMC_PF_IDLE
AXBS_HLTD
AXBS_HLT_REQ
HLT_FSM_
ST
W
Reset 0 0 0 0 0 0 0 0 0 x* 0 x* 0 0 0 0
* Notes:
x = Undefined at reset.•
MCM_CPCR field descriptions
Field Description
31
Reserved
This field is reserved.
30
SRAMLWP
SRAM_L Write Protect
When this field is set, writes to SRAM_L array generate a bus error.
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
29–28
SRAMLAP
SRAM_L Arbitration Priority
Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the
SRAM_L array.
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
00 Round robin
01 Special round robin (favors SRAM backdoor accesses over the processor)
10 Fixed priority. Processor has highest, backdoor has lowest
11 Fixed priority. Backdoor has highest, processor has lowest
Table continues on the next page...
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
140 NXP Semiconductors
MCM_CPCR field descriptions (continued)
Field Description
27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
SRAMUWP
SRAM_U Write Protect
When this field is set, writes to SRAM_U array generate a bus error.
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
25–24
SRAMUAP
SRAM_U Arbitration Priority
Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the
SRAM_U array.
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
00 Round robin
01 Special round robin (favors SRAM backdoor accesses over the processor)
10 Fixed priority. Processor has highest, backdoor has lowest
11 Fixed priority. Backdoor has highest, processor has lowest
23–10
Reserved
This field is reserved.
9
CBRR
Crossbar Round-robin Arbitration Enable
Configures the crossbar slave ports to fixed-priority or round-robin arbitration.
0 Fixed-priority arbitration
1 Round-robin arbitration
8–7
Reserved
This field is reserved.
6
PBRIDGE_IDLE
Peripheral Bridge Idle
This field indicates if the Peripheral Bridge is idle.
0 PBRIDGE is not idle
1 PBRIDGE is currently idle
5
Reserved
This field is reserved.
4
FMC_PF_IDLE
Flash Memory Controller Program Flash Idle
This field indicates if the program portion of the flash memory is idle.
0 FMC program flash is not idle
1 FMC program flash is currently idle
3
AXBS_HLTD
AXBS Halted
This field indicates if AXBS is in a halted state.
0 AXBS is not currently halted
1 AXBS is currently halted
2
AXBS_HLT_REQ
AXBS Halt Request
This field indicates if AXBS has received a halt request.
Table continues on the next page...
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 141
MCM_CPCR field descriptions (continued)
Field Description
0 AXBS is not receiving halt request
1 AXBS is receiving halt request
HLT_FSM_ST AXBS Halt State Machine Status
This field indicates the state of an AXBS halt.
00 Waiting for request
01 Waiting for platform idle
11 Platform stalled
10 Unused state
10.3.4 Interrupt Status and Control Register (MCM_ISCR)
ISCR defines the configuration and reports status for a number of core-related interrupt
exception conditions. It includes the enable and status fields associated with the core’s
floating-point exceptions and the bus errors associated with the core’s cache write buffer.
The individual event indicators are first qualified with their exception enables and then
logically summed to form an interrupt request sent to the core’s NVIC.
Bits 15-8 are read-only indicator flags based on the processor’s FPSCR. Attempted writes
to these fields are ignored. After the flags are set, they remain asserted until software
clears the corresponding FPSCR field.
NOTE
This register is Reserved for S32K11x variants.
Address: 0h base + 10h offset = 10h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FIDCE
0
FIXCE
FUFCE
FOFCE
FDZCE
FIOCE
0
Reserved
0 1 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
142 NXP Semiconductors
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FIDC
0
FIXC
FUFC
FOFC
FDZC
FIOC
0
Reserved
0
Ww1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_ISCR field descriptions
Field Description
31
FIDCE
FPU Input Denormal Interrupt Enable
0 Disable interrupt
1 Enable interrupt
30–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
FIXCE
FPU Inexact Interrupt Enable
0 Disable interrupt
1 Enable interrupt
27
FUFCE
FPU Underflow Interrupt Enable
0 Disable interrupt
1 Enable interrupt
26
FOFCE
FPU Overflow Interrupt Enable
0 Disable interrupt
1 Enable interrupt
25
FDZCE
FPU Divide-by-Zero Interrupt Enable
0 Disable interrupt
1 Enable interrupt
24
FIOCE
FPU Invalid Operation Interrupt Enable
0 Disable interrupt
1 Enable interrupt
23–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
Reserved
This field is reserved.
19–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 143
MCM_ISCR field descriptions (continued)
Field Description
17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
FIDC
FPU Input Denormal Interrupt Status
This field is a copy of the core’s FPSCR[IDC] field and signals input denormalized number has been
detected in the processor’s FPU. After the field is set, it remains set until software clears FPSCR[IDC].
0 No interrupt
1 Interrupt occurred
14–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
FIXC
FPU Inexact Interrupt Status
This field is a copy of the core’s FPSCR[IXC] field and signals an inexact number has been detected in the
processor’s FPU. Once set, this field remains set until software clears FPSCR[IXC].
0 No interrupt
1 Interrupt occurred
11
FUFC
FPU Underflow Interrupt Status
This field is a copy of the core’s FPSCR[UFC] field and signals an underflow has been detected in the
processor’s FPU. After this field is set, it remains set until software clears FPSCR[UFC].
0 No interrupt
1 Interrupt occurred
10
FOFC
FPU Overflow Interrupt Status
This field is a copy of the core’s FPSCR[OFC] field and signals an overflow has been detected in the
processor’s FPU. After this field is set, it remains set until software clears FPSCR[OFC].
0 No interrupt
1 Interrupt occurred
9
FDZC
FPU Divide-by-Zero Interrupt Status
This field is a copy of the core’s FPSCR[DZC] field and signals a divide by zero has been detected in the
processor’s FPU. After this field is set, it remains set until software clears FPSCR[DZC].
0 No interrupt
1 Interrupt occurred
8
FIOC
FPU Invalid Operation Interrupt Status
This field is a copy of the core’s FPSCR[IOC] field and signals an illegal operation has been detected in
the processor’s FPU. After this field is set, it remains set until software clears FPSCR[IOC].
0 No interrupt
1 Interrupt occurred
7–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
144 NXP Semiconductors
MCM_ISCR field descriptions (continued)
Field Description
4
Reserved
This field is reserved.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
10.3.5 Process ID Register (MCM_PID)
This register drives the M0_PID and M1_PID values in the Memory Protection Unit
(MPU). System software loads this register before passing control to a given user mode
process. If the PID of the process does not match the value in this register, a bus error
occurs. See the MPU chapter for more details.
Address: 0h base + 30h offset = 30h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0PID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_PID field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
PID M0_PID and M1_PID for MPU
Drives the M0_PID and M1_PID values in the MPU.
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 145
10.3.6 Compute Operation Control Register (MCM_CPO)
This register controls the compute operation.
Address: 0h base + 40h offset = 40h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
CPOWOI
CPOACK
CPOREQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_CPO field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
CPOWOI
Compute Operation Wakeup On Interrupt
0 No effect.
1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
1
CPOACK
Compute Operation Acknowledge
0 Compute operation entry has not completed or compute operation exit has completed.
1 Compute operation entry has completed or compute operation exit has not completed.
0
CPOREQ
Compute Operation Request
This field is auto-cleared by vector fetching if CPOWOI = 1.
Table continues on the next page...
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
146 NXP Semiconductors
MCM_CPO field descriptions (continued)
Field Description
0 Request is cleared.
1 Request Compute Operation.
10.3.7 Local Memory Descriptor Register (MCM_LMDRn)
The LMDRn registers mapping to the LMEMs is as follows:
• LMDR0: SRAM_L
• LMDR1: SRAM_U
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information on the attached memories as well as
configurable controls (where appropriate).
Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information. Reads from any other bus master return all zeroes. Privileged
writes from a processor core or the debugger to writeable registers update the appropriate
fields. Privileged writes from other bus masters are ignored. Attempted user mode
accesses or any access with a size other than 32 bits are terminated with an error.
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 147
Address: 0h base + 400h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RV
Reserved
Reserved
LMSZH
LMSZ WY DPW
LOCK
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMT
Reserved
Reserved Reserved CF0
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
148 NXP Semiconductors
The reset values are different for the individual LMDR registers. LMDR0: 0x8804_0003; LMDR1: 0x8804_2003. x =
Undefined at reset.
•
MCM_LMDRn field descriptions
Field Description
31
V
Local Memory Valid
This field defines the validity (presence) of the local memory.
0 LMEMn is not present.
1 LMEMn is present.
30
Reserved
This field is reserved.
29
Reserved
This field is reserved.
28
LMSZH
LMEM Size Hole
For local memories that are not fully populated, that is, include a memory hole in the upper 25% of the
address range, this field is used.
0 LMEMn is a power-of-2 capacity.
1 LMEMn is not a power-of-2, with a capacity is 0.75 × LMSZ.
27–24
LMSZ
LMEM Size
This field provides an encoded value of the local memory size. The capacity of the memory is expressed
as Size [bytes] = 2(9+LMSZ) where LMSZ is non-zero; a LMSZ = 0 indicates the memory is not present.
0000 no LMEMn (0 KB)
0001 1 KB LMEMn
0010 2 KB LMEMn
0011 4 KB LMEMn
0100 8 KB LMEMn
0101 16 KB LMEMn
0110 32 KB LMEMn
0111 64 KB LMEMn
1000 128 KB LMEMn
1001 256 KB LMEMn
1010 512 KB LMEMn
1011 1024 KB LMEMn
1100 2048 KB LMEMn
1101 4096 KB LMEMn
1110 8192 KB LMEMn
1111 16384 KB LMEMn
23–20
WY
Level 1 Cache Ways
0000 No Cache
0010 2-Way Set Associative
0100 4-Way Set Associative
19–17
DPW
LMEM Data Path Width. This field defines the width of the local memory.
000-001 Reserved
Table continues on the next page...
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 149
MCM_LMDRn field descriptions (continued)
Field Description
010 LMEMn 32-bits wide
011 LMEMn 64-bits wide
100-111 Reserved
16
LOCK
LOCK
Lock bit.
This field provides a mechanism to lock the configuration state defined by LMDRn[7:0]. Once asserted,
attempted writes to the LMDRn[7:0] register are ignored until the next reset clears the flag. Along with
LMDRn[7:0], this bit locks itself. Once locked, only reset can clear this bit.
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
0 Writes to the LMDRn[7:0] are allowed.
1 Writes to the LMDRn[7:0] are ignored.
15–13
MT
Memory Type
This field defines the type of the local memory.
000 SRAM_L
001 SRAM_U
12
Reserved
This field is reserved.
11–8
Reserved
This field is reserved.
7–4
Reserved
This field is reserved.
CF0 Control Field 0
NOTE
LMDR0[CF0] bit field is Reserved and Read-Only 0 for S32K11x
variants.
This field is used for TCM ECC control functions.
• CF0[3] - Reserved
• CF0[2] - Reserved
• CF0[1] - EERC = ECC Enable Read Check
• CF0[0] - EEWG = ECC Enable Write Generation
10.3.8 Local Memory Descriptor Register2 (MCM_LMDR2)
The LMDR2 registers mapping to the LMEMs representing PC CACHE.
NOTE
This value represents the maximum available cache within the
entire family. See Figure 2-3 to view the specific amount of
cache for a particular device.
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
150 NXP Semiconductors
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information on the attached memories as well as
configurable controls (where appropriate).
Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information. Reads from any other bus master return all zeroes. Privileged
writes from a processor core or the debugger to writeable registers update the appropriate
fields. Privileged writes from other bus masters are ignored. Attempted user mode
accesses or any access with a size other than 32 bits are terminated with an error.
Address: 0h base + 408h offset = 408h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RV
Reserved
Reserved
LMSZH
LMSZ WY DPW
LOCK
W
Reset 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 151
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMT
Reserved
Reserved CF1 Reserved
W
Reset 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0
MCM_LMDR2 field descriptions
Field Description
31
V
Local Memory Valid
This field defines the validity (presence) of the local memory.
0 LMEMn is not present.
1 LMEMn is present.
30
Reserved
This field is reserved.
29
Reserved
This field is reserved.
28
LMSZH
LMEM Size Hole
For local memories that are not fully populated, that is, include a memory hole in the upper 25% of the
address range, this field is used.
0 LMEMn is a power-of-2 capacity.
1 LMEMn is not a power-of-2, with a capacity is 0.75 × LMSZ.
27–24
LMSZ
LMEM Size
This field provides an encoded value of the local memory size; a LMSZ = 0 indicates the memory is not
present.
0100 4 KB LMEMn
23–20
WY
Level 1 Cache Ways
0000 No Cache
0010 2-Way Set Associative
0100 4-Way Set Associative
Table continues on the next page...
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
152 NXP Semiconductors
MCM_LMDR2 field descriptions (continued)
Field Description
19–17
DPW
LMEM Data Path Width. This field defines the width of the local memory.
000-001 Reserved
010 LMEMn 32-bits wide
011 LMEMn 64-bits wide
100-111 Reserved
16
LOCK
LOCK
Lock bit
This field provides a mechanism to lock the configuration state defined by LMDRn[7:0]. Once asserted,
attempted writes to the LMDRn[7:0] register are ignored until the next reset clears the flag. Along with
LMDRn[7:0], this bit locks itself. Once locked, only reset can clear this bit.
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
0 Writes to the LMDRn[7:0] are allowed.
1 Writes to the LMDRn[7:0] are ignored.
15–13
MT
Memory Type
This field defines the type of the local memory.
010 PC Cache
12
Reserved
This field is reserved.
11–8
Reserved
This field is reserved.
7–4
CF1
Control Field 1
This field is used for cache parity control functions.
• CF1[3]-PCPFE = PC Parity Fault Enable
• CF1[2]-Reserved
• CF1[1]-PCPME = PC Parity Miss Enable
• CF1[0]-Reserved
Reserved This field is reserved.
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 153
10.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR)
Address: 0h base + 480h offset = 480h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
ECPR
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
ER1BR
0
ERNCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_LMPECR field descriptions
Field Description
31–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
ECPR
Enable Cache Parity Reporting
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
0 Reporting disabled
1 Reporting enabled
19–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
ER1BR
Enable RAM ECC 1 Bit Reporting
0 Reporting disabled
1 Reporting enabled
7–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
ERNCR
Enable RAM ECC Noncorrectable Reporting
0 Reporting disabled
1 Reporting enabled
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
154 NXP Semiconductors
10.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)
NOTE
Writes of 1 to the error bit in LMPEIR[23:0] can clear the
interrupt flag. For S32K11x variants, MCM interrupt for ECC
is not supported and this register only captures the event.
Address: 0h base + 488h offset = 488h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RV 0 PEELOC PE
Ww1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE1B ENC
Ww1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_LMPEIR field descriptions
Field Description
31
V
Valid Bit
30–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–24
PEELOC
Parity or ECC Error Location
00 Non-correctable ECC event from SRAM_L
01 Non-correctable ECC event from SRAM_U
08 1-bit correctable ECC event from SRAM_L
09 1-bit correctable ECC event from SRAM_U
14 PC tag parity error
15 PC data parity error
23–16
PE
Cache Parity Error
• [21] - PC Data Parity Error
• [20] - PC Tag Parity Error
• [19] - Reserved
• [18] - Reserved
NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
15–8
E1B
E1Bn = ECC 1-bit Error n
• PEIR[15:10] - Reserved
Table continues on the next page...
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 155
MCM_LMPEIR field descriptions (continued)
Field Description
• PEIR[9] - 1-bit Error detected on SRAM_U
• PEIR[8] - 1-bit Error detected on SRAM_L. (This is Reserved for S32K11x variants.)
ENC ENCn = ECC Noncorrectable Error n
• PEIR[7:2] - Reserved
• PEIR[1] - Noncorrectable Error detected on SRAM_U
• PEIR[0] - Noncorrectable Error detected on SRAM_L (This is Reserved for S32K11x variants.)
10.3.11 LMEM Fault Address Register (MCM_LMFAR)
Address: 0h base + 490h offset = 490h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFADD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_LMFAR field descriptions
Field Description
EFADD ECC Fault Address
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
156 NXP Semiconductors
10.3.12 LMEM Fault Attribute Register (MCM_LMFATR)
Address: 0h base + 494h offset = 494h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
OVR
0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPEFMST
PEFW
PEFSIZE PEFPRT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_LMFATR field descriptions
Field Description
31
OVR
Overrun
30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
PEFMST
Parity/ECC Fault Master Number
7
PEFW
Parity/ECC Fault Write
Table continues on the next page...
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 157
MCM_LMFATR field descriptions (continued)
Field Description
6–4
PEFSIZE
Parity/ECC Fault Master Size
000 8-bit access
001 16-bit access
010 32-bit access
011 64-bit access
1xx Reserved
PEFPRT Parity/ECC Fault Protection
• FATR[3] - Cacheable: 0=Non-cacheable, 1=Cacheable
• FATR[2] - Bufferable: 0=Non-bufferable, 1=Bufferable
• FATR[1] - Mode: 0=User mode, 1=Supervisor mode
• FATR[0] - Type: 0=I-Fetch, 1=Data
10.3.13 LMEM Fault Data High Register (MCM_LMFDHR)
Address: 0h base + 4A0h offset = 4A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPEFDH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_LMFDHR field descriptions
Field Description
PEFDH Parity or ECC Fault Data High
10.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)
Address: 0h base + 4A4h offset = 4A4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPEFDL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map/register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
158 NXP Semiconductors
MCM_LMFDLR field descriptions
Field Description
PEFDL Parity or ECC Fault Data Low
10.4 Functional description
This section describes the functional description of MCM module.
10.4.1 Interrupts
The MCM interrupt is generated if any of the following is true:
• FPU input denormal interrupt is enabled (FIDCE) and an input is denormalized
(FIDC)
• FPU inexact interrupt is enabled (FIXCE) and a number is inexact (FIXC)
• FPU underflow interrupt is enabled (FUFCE) and an underflow occurs (FUFC)
• FPU overflow interrupt is enabled (FOFCE) and an overflow occurs (FOFC)
• FPU divide-by-zero interrupt is enabled (FDZCE) and a divide-by-zero occurs
(FDZC)
• FPU invalid operation interrupt is enabled (FIOCE) and an invalid occurs (FIOC)
• SRAM_L correctable (1-bit) ECC error
• SRAM_L uncorrectable ECC error
• SRAM_U correctable (1-bit) ECC error
• SRAM_U uncorrectable ECC error
• PC data parity error
• PC tag parity error
• Cache write buffer error
NOTE
The above interrupt is not applicable for S32K11x variants.
10.4.1.1 Determining source of the interrupt
These steps can be used to determine the exact source of the interrupt:
1. Logical AND the interrupt status flags with the corresponding interrupt enable bits:
ISCR[31:16] and ISCR[15:0].
2. Search the result for asserted bits which indicate the exact interrupt sources.
Chapter 10 Miscellaneous Control Module (MCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 159
NOTE
ECC and Parity interrupts are determined by LMPECR
(interrupt enable) and LMPEIR (interrupt source).
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
160 NXP Semiconductors
Chapter 11
System Integration Module (SIM)
11.1 Chip-specific SIM information
Some aspects of the SIM vary across the products in the S32K1xx series.
11.1.1 SIM register bitfield implementation
Not all register bitfields shown in the SIM memory map are implemented in every
S32K1xx variant. Register/ register bit field availability vary accordingly to the
availability of a module/the number of module instances present in a variant. See Figure
2-3 for details on module and instance information.
NOTE
PLATCGC register has CGCGPIO bit field at position 5 for
GPIO Clock Gating Control. This bit is available in S32K11x
variants only.
11.2 Introduction
The System Integration Module (SIM) provides system control and chip configuration
registers.
11.2.1 Features
Features of the SIM include:
• System clocking configuration
• Flash memory and system RAM size configuration
• FlexTimer clock channel and configuration
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 161
• ADC trigger selection
• LPO clock source selection
• ENET clock control
• Flash memory configuration
• System device identification (ID)
11.3 Memory map and register definition
The SIM contains many fields for selecting the clock source and dividers for various
module clocks. See section: Clock Distribution chapter for more information, including
block diagrams and clock definitions.
NOTE
The SIM registers can only be written in supervisor mode. In
user mode, write accesses are blocked and will result in a bus
error.
NOTE
Writing to Read-Only registers may /may not generate Transfer
error.
11.3.1 SIM register descriptions
11.3.1.1 SIM Memory map
SIM base address: 4004_8000h
Offset Register Width
(In bits)
Access Reset value
4h Chip Control register (CHIPCTL) 32 RW 0030_0000h
Ch FTM Option Register 0 (FTMOPT0) 32 RW 0000_0000h
10h LPO Clock Select Register (LPOCLKS) 32 RW 0000_0003h
18h ADC Options Register (ADCOPT) 32 RW 0000_0000h
1Ch FTM Option Register 1 (FTMOPT1) 32 RW 0000_0000h
20h Miscellaneous control register 0 (MISCTRL0) 32 RW 0000_0000h
24h System Device Identification Register (SDID) 32 RO See
description.
40h Platform Clock Gating Control Register (PLATCGC) 32 RW 0000_001Fh
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
162 NXP Semiconductors
Offset Register Width
(In bits)
Access Reset value
4Ch Flash Configuration Register 1 (FCFG1) 32 RW See
description.
54h Unique Identification Register High (UIDH) 32 RO See
description.
58h Unique Identification Register Mid-High (UIDMH) 32 RO See
description.
5Ch Unique Identification Register Mid Low (UIDML) 32 RO See
description.
60h Unique Identification Register Low (UIDL) 32 RO See
description.
68h System Clock Divider Register 4 (CLKDIV4) 32 RW 1000_0000h
6Ch Miscellaneous Control register 1 (MISCTRL1) 32 RW 0000_0000h
11.3.1.2 Chip Control register (CHIPCTL)
11.3.1.2.1 Offset
Register Offset
CHIPCTL 4h
11.3.1.2.2 Function
SIM_CHIPCTL contains the controls for selecting ADC COCO trigger, trace clock,
clock out source, PDB back-to-back mode, and ADC interleave channel.
NOTE
Bits 31:16 are reset on POR.
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 163
11.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
Reserved
SRAML_RETE
N
SRAMU_RETE
N
ADC_SUPPLYEN
ADC_SUPPLY
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PDB_BB_SE
L
TRACECLK_SE
L
CLKOUTEN
CLKOUTDIV
CLKOUTSEL
ADC_INTERLEAVE_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.2.4 Fields
Field Function
31-24
—
Reserved
23-22
—
Reserved
21
SRAML_RETEN
SRAML_RETEN
SRAML retention
NOTE: For S32K11x devices, SRAML refers to MTB RAM.
0b - SRAML contents are retained across resets
1b - No SRAML retention
20
SRAMU_RETE
N
SRAMU_RETEN
SRAMU retention
0b - SRAMU contents are retained across resets
1b - No SRAMU retention
19
ADC_SUPPLYE
N
ADC_SUPPLYEN
Enable for internal supply monitoring on ADC0 internal channel 0 (configured by selecting
ADC0_SC1n[ADCH] as 010101b).
0b - Disable internal supply monitoring
1b - Enable internal supply monitoring
18-16
ADC_SUPPLY
ADC_SUPPLY
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
164 NXP Semiconductors
Field Function
Internal supplies monitored on ADC0 internal channel 0 (configured by selecting ADC0_SC1n[ADCH] as
010101b)
000b - 5 V input VDD supply (VDD)
001b - 5 V input analog supply (VDDA)
010b - ADC Reference Supply (VREFH)
011b - 3.3 V Oscillator Regulator Output (VDD_3V)
100b - 3.3 V flash regulator output (VDD_flash_3V)
101b - 1.2 V core regulator output (VDD_LV)
110b - Reserved
111b - Reserved
15-14
—
Reserved
13
PDB_BB_SEL
PDB back-to-back select
Selects ADC COCO source as pdb back-to-back mode, see section Back-to-back acknowledgement
connections for details.
NOTE: This bit field is Reserved and Read-Only Zero for S32K11x variants.
0b - PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-
back operation with ADC1 COCO[7:0]
1b - Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1.
12
TRACECLK_SE
L
Debug trace clock select
Selects core clock or platform clock as the trace clock source.
NOTE: This bit field is Reserved and Read-Only Zero for S32K11x variants.
0b - Core clock
1b - Reserved
11
CLKOUTEN
CLKOUT enable
NOTE: The below sequence should be followed while CLKOUT configuration:
1. Configure SIM_CHIPCTL[CLKOUTSEL]
2. Configure SIM_CHIPCTL[CLKOUTDIV]
3. Enable SIM_CHIPCTL[CLKOUTEN]
(While switching, CLKOUTEN should be first cleared and then the above sequence should be
followed)
0b - Clockout disable
1b - Clockout enable
10-8
CLKOUTDIV
CLKOUT Divide Ratio
NOTE: The below sequence should be followed while CLKOUT configuration:
1. Configure SIM_CHIPCTL[CLKOUTSEL]
2. Configure SIM_CHIPCTL[CLKOUTDIV]
3. Enable SIM_CHIPCTL[CLKOUTEN]
(While switching, CLKOUTEN should be first cleared and then the above sequence should be
followed)
000b - Divide by 1
001b - Divide by 2
010b - Divide by 3
011b - Divide by 4
100b - Divide by 5
101b - Divide by 6
110b - Divide by 7
111b - Divide by 8
7-4 CLKOUT Select
Table continues on the next page...
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 165
Field Function
CLKOUTSEL NOTE: The below sequence should be followed while CLKOUT configuration:
1. Configure SIM_CHIPCTL[CLKOUTSEL]
2. Configure SIM_CHIPCTL[CLKOUTDIV]
3. Enable SIM_CHIPCTL[CLKOUTEN]
(While switching, CLKOUTEN should be first cleared and then the above sequence should be
followed)
NOTE: For QuadSPI clocks, see QuadSPI clocking diagram in table 'Peripheral module clocking'
Selects the clock to output on the CLKOUT pin.
0000b - SCG CLKOUT
0001b - Reserved
0010b - SOSC DIV2 CLK
0011b - Reserved
0100b - SIRC DIV2 CLK
0101b - For S32K148: QSPI_SFIF_CLK_HYP_PREMUX: Divide by 2 clock (configured through
SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved
0110b - FIRC DIV2 CLK
0111b - HCLK
1000b - For S32K14x: SPLL DIV2 CLK For S32K11x: Reserved
1001b - BUS_CLK
1010b - LPO128K_CLK
1011b - For S32K148: QSPI_Module clock; For others: Reserved
1100b - LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]
1101b - For S32K148: QSPI_SFIF_CLK; For others: Reserved
1110b - RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]
1111b - For S32K148: QSPI_2xSFIF_CLK; For others: Reserved
3-0
ADC_INTERLE
AVE_EN
ADC interleave channel enable
Select ADC interleave pins. See section ADC Hardware Interleaved Channels for more information.
NOTE: This bit field is Reserved and Read-Only Zero for S32K11x variants.
0000b - Interleaving disabled. No channel pair interleaved. Interleaved channels are individually
connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is
connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4.
PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to
ADC1_SE9.
1xxxb - PTB14 to ADC1_SE9 and ADC0_SE9
x1xxb - PTB13 to ADC1_SE8 and ADC0_SE8
xx1xb - PTB1 to ADC0_SE5 and ADC1_SE15
xxx1b - PTB0 to ADC0_SE4 and ADC1_SE14
11.3.1.3 FTM Option Register 0 (FTMOPT0)
11.3.1.3.1 Offset
Register Offset
FTMOPT0 Ch
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
166 NXP Semiconductors
11.3.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FTM3CLKSEL
FTM2CLKSEL
FTM1CLKSEL
FTM0CLKSEL
FTM7CLKSEL
FTM6CLKSEL
FTM5CLKSEL
FTM4CLKSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FTM3FLTxSEL
0
FTM2FLTxSEL
0
FTM1FLTxSEL
0
FTM0FLTxSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.3.3 Fields
Field Function
31-30
FTM3CLKSEL
FTM3 External Clock Pin Select
Selects the external pin used to drive the FTM3 module clock.
NOTE: The selected pin must also be configured for the FTM3 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM3 external clock driven by TCLK0 pin.
01b - FTM3 external clock driven by TCLK1 pin.
10b - FTM3 external clock driven by TCLK2 pin.
11b - No clock input
29-28
FTM2CLKSEL
FTM2 External Clock Pin Select
Selects the external pin used to drive the FTM2 module clock.
NOTE: The selected pin must also be configured for the FTM2 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM2 external clock driven by TCLK0 pin.
01b - FTM2 external clock driven by TCLK1 pin.
10b - FTM2 external clock driven by TCLK2 pin.
11b - No clock input
27-26
FTM1CLKSEL
FTM1 External Clock Pin Select
Selects the external pin used to drive the FTM1 module clock.
NOTE: The selected pin must also be configured for the FTM1 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM1 external clock driven by TCLK0 pin.
01b - FTM1 external clock driven by TCLK1 pin.
10b - FTM1 external clock driven by TCLK2 pin.
11b - No clock input
25-24 FTM0 External Clock Pin Select
Table continues on the next page...
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 167
Field Function
FTM0CLKSEL Selects the external pin used to drive the FTM0 module clock.
NOTE: The selected pin must also be configured for the FTM0 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM0 external clock driven by TCLK0 pin.
01b - FTM0 external clock driven by TCLK1 pin.
10b - FTM0 external clock driven by TCLK2 pin.
11b - No clock input
23-22
FTM7CLKSEL
FTM7 External Clock Pin Select
Selects the external pin used to drive the FTM7 module clock.
NOTE: The selected pin must also be configured for the FTM7 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM7 external clock driven by TCLK0 pin.
01b - FTM7 external clock driven by TCLK1 pin.
10b - FTM7 external clock driven by TCLK2 pin.
11b - No clock input
21-20
FTM6CLKSEL
FTM6 External Clock Pin Select
Selects the external pin used to drive the FTM6 module clock.
NOTE: The selected pin must also be configured for the FTM6 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM6 external clock driven by TCLK0 pin.
01b - FTM6 external clock driven by TCLK1 pin.
10b - FTM6 external clock driven by TCLK2 pin.
11b - No clock input
19-18
FTM5CLKSEL
FTM5 External Clock Pin Select
Selects the external pin used to drive the FTM5 module clock.
NOTE: The selected pin must also be configured for the FTM5 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM5 external clock driven by TCLK0 pin.
01b - FTM5 external clock driven by TCLK1 pin.
10b - FTM5 external clock driven by TCLK2 pin.
11b - No clock input
17-16
FTM4CLKSEL
FTM4 External Clock Pin Select
Selects the external pin used to drive the FTM4 module clock.
NOTE: The selected pin must also be configured for the FTM4 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM4 external clock driven by TCLK0 pin.
01b - FTM4 external clock driven by TCLK1 pin.
10b - FTM4 external clock driven by TCLK2 pin.
11b - No clock input
15
—
Reserved
14-12
FTM3FLTxSEL
FTM3 Fault X Select
Selects the source of the FTM3 fault. Every bit means one fault input, respectively.
NOTE: The pin source of the fault must be configured for FTM3 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM3 SELx
corresponds to the FTM3 Fault x input.
000b - FTM3_FLTx pin
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
168 NXP Semiconductors
Field Function
001b - TRGMUX_FTM3 out
11
—
Reserved
10-8
FTM2FLTxSEL
FTM2 Fault X Select
Selects the source of the FTM2 fault. Every bit means one fault input, respectively.
NOTE: The pin source of the fault must be configured for FTM2 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM2 SELx
corresponds to the FTM2 Fault x input.
000b - FTM2_FLTx pin
001b - TRGMUX_FTM2 out
7
—
Reserved
6-4
FTM1FLTxSEL
FTM1 Fault X Select
Selects the source of the FTM1 fault. Every bit means one fault input, respectively.
NOTE: The pin source of the fault must be configured for FTM1 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM1 SELx
corresponds to the FTM1 Fault x input.
000b - FTM1_FLTx pin
001b - TRGMUX_FTM1 out
3
—
Reserved
2-0
FTM0FLTxSEL
FTM0 Fault X Select
Selects the source of the FTM0 fault. Every bit means one fault input, respectively.
NOTE: The pin source of the fault must be configured for FTM0 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM0 SELx
corresponds to the FTM0 Fault x input.
000b - FTM0_FLTx pin
001b - TRGMUX_FTM0 out
11.3.1.4 LPO Clock Select Register (LPOCLKS)
11.3.1.4.1 Offset
Register Offset
LPOCLKS 10h
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 169
11.3.1.4.2 Function
NOTE
The LPOCLKS register is a write-once register, and is reset
only on POR or LVD.
11.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RTCCLKSE
L
LPOCLKSEL
LPO32KCLKEN
LPO1KCLKEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
11.3.1.4.4 Fields
Field Function
31-6
—
Reserved
5-4
RTCCLKSEL
32 kHz clock source select
Selects 32 kHz clock source for peripherals
00b - SOSCDIV1_CLK
01b - 32 kHz LPO_CLK
10b - RTC_CLKIN clock
11b - FIRCDIV1_CLK
3-2
LPOCLKSEL
LPO clock source select
Selects LPO clock source for peripherals
00b - 128 kHz LPO_CLK
01b - No clock
10b - 32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK
11b - 1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK
1
LPO32KCLKEN
32 kHz LPO_CLK enable
0b - Disable 32 kHz LPO_CLK output
1b - Enable 32 kHz LPO_CLK output
0
LPO1KCLKEN
1 kHz LPO_CLK enable
0b - Disable 1 kHz LPO_CLK output
1b - Enable 1 kHz LPO_CLK output
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
170 NXP Semiconductors
11.3.1.5 ADC Options Register (ADCOPT)
11.3.1.5.1 Offset
Register Offset
ADCOPT 18h
11.3.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADC1PRETRGSE
L
ADC1SWPRETRG
ADC1TRGSEL
0
ADC0PRETRGSE
L
ADC0SWPRETRG
ADC0TRGSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.5.3 Fields
Field Function
31-16
—
Reserved
15-14
—
Reserved
13-12
ADC1PRETRG
SEL
ADC1 pretrigger source select
Selects pretrigger source for ADC1.
00b - PDB pretrigger (default)
01b - TRGMUX pretrigger
10b - Software pretrigger
11b - Reserved
11-9
ADC1SWPRET
RG
ADC1 software pretrigger sources
000b - Software pretrigger disabled
001b - Reserved (do not use)
010b - Reserved (do not use)
Table continues on the next page...
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 171
Field Function
011b - Reserved (do not use)
100b - Software pretrigger 0
101b - Software pretrigger 1
110b - Software pretrigger 2
111b - Software pretrigger 3
8
ADC1TRGSEL
ADC1 trigger source select
Selects trigger source for ADC1.
NOTE: Each PDB supports two ADC channels, and each channel has 8 pretriggers. If needed, the
trigger of two ADC channels are OR'ed together to support up to 16 pretriggers.
0b - PDB output
1b - TRGMUX output
7-6
—
Reserved
5-4
ADC0PRETRG
SEL
ADC0 pretrigger source select
Selects pretrigger source for ADC0.
00b - PDB pretrigger (default)
01b - TRGMUX pretrigger
10b - Software pretrigger
11b - Reserved
3-1
ADC0SWPRET
RG
ADC0 software pretrigger sources
000b - Software pretrigger disabled
001b - Reserved (do not use)
010b - Reserved (do not use)
011b - Reserved (do not use)
100b - Software pretrigger 0
101b - Software pretrigger 1
110b - Software pretrigger 2
111b - Software pretrigger 3
0
ADC0TRGSEL
ADC0 trigger source select
Selects trigger source for ADC0.
NOTE: Each PDB supports two ADC channels, and each channel has 8 pretriggers. If needed, the
trigger of two ADC channels are OR'ed together to support up to 16 pretriggers.
0b - PDB output
1b - TRGMUX output
11.3.1.6 FTM Option Register 1 (FTMOPT1)
11.3.1.6.1 Offset
Register Offset
FTMOPT1 1Ch
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
172 NXP Semiconductors
11.3.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFTM3_OUTSEL FTM0_OUTSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FTMGLDOK
FTM7SYNCBIT
FTM6SYNCBIT
FTM5SYNCBIT
FTM4SYNCBIT
0
FTM2CH1SEL
FTM2CH0SEL
FTM1CH0SEL
FTM3SYNCBIT
FTM2SYNCBIT
FTM1SYNCBIT
FTM0SYNCBIT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.6.3 Fields
Field Function
31-24
FTM3_OUTSEL
FTM3 channel modulation select with FTM2_CH1
Bits 7 to 0 of this field are for channel 7 to 0, respectively.
00000000b - No modulation with FTM2_CH1
00000001b - Modulation with FTM2_CH1
23-16
FTM0_OUTSEL
FTM0 channel modulation select with FTM1_CH1
Bits 7 to 0 of this field are for channel 7 to 0, respectively.
00000000b - No modulation with FTM1_CH1
00000001b - Modulation with FTM1_CH1
15
FTMGLDOK
FTM global load enable
This bit is not self-clearing. For subsequent reload operations, it should be cleared and then set.
0b - FTM Global load mechanism disabled.
1b - FTM Global load mechanism enabled
14
FTM7SYNCBIT
FTM7 Sync Bit
This is used as trigger source for FTM7. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
13
FTM6SYNCBIT
FTM6 Sync Bit
This is used as trigger source for FTM6. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
12
FTM5SYNCBIT
FTM5 Sync Bit
This is used as trigger source for FTM5. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
11
FTM4SYNCBIT
FTM4 Sync Bit
This is used as trigger source for FTM4. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
10-9
—
Reserved
Table continues on the next page...
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 173
Field Function
8
FTM2CH1SEL
FTM2 CH1 Select
Selects FTM2 CH1 input
0b - FTM2_CH1 input
1b - exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1
7-6
FTM2CH0SEL
FTM2 CH0 Select
Selects FTM2 CH0 input
00b - FTM2_CH0 input
01b - CMP0 output
10b - Reserved
11b - Reserved
5-4
FTM1CH0SEL
FTM1 CH0 Select
Selects FTM1 CH0 input
00b - FTM1_CH0 input
01b - CMP0 output
10b - Reserved
11b - Reserved
3
FTM3SYNCBIT
FTM3 Sync Bit
This is used as trigger source for FTM3. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
2
FTM2SYNCBIT
FTM2 Sync Bit
This is used as trigger source for FTM2. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
1
FTM1SYNCBIT
FTM1 Sync Bit
This is used as trigger source for FTM1. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
0
FTM0SYNCBIT
FTM0 Sync Bit
This is used as trigger source for FTM0. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
11.3.1.7 Miscellaneous control register 0 (MISCTRL0)
11.3.1.7.1 Offset
Register Offset
MISCTRL0 20h
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
174 NXP Semiconductors
11.3.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
QSPI_CLK_SE
L
RMII_CLK_SEL
RMII_CLK_OBE
FTM7_OBE_CTRL
FTM6_OBE_CTRL
FTM5_OBE_CTRL
FTM4_OBE_CTRL
FTM3_OBE_CTRL
FTM2_OBE_CTRL
FTM1_OBE_CTRL
FTM0_OBE_CTRL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
FTM_GTB_SPLIT_EN
Reserved
STOP2_MONITOR
STOP1_MONITOR
Reserved
W
W1C
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.7.3 Fields
Field Function
31-27
—
Reserved
26
QSPI_CLK_SEL
QSPI CLK Select bit
QSPI asynchronous clock gating enable
0b - QuadSPI internal reference clock is gated.
1b - QuadSPI internal reference clock is enabled.
25
RMII_CLK_SEL
RMII CLK Select bit
Set this bit to enable SOSCDIV1_CLK as ENET RMII clock in Internal loopback mode.
24
RMII_CLK_OBE
RMII CLK OBE bit
Output Buffer Enable for ENET RMII clock in internal loopback mode
23
FTM7_OBE_CT
RL
FTM7 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
22 FTM6 OBE CTRL bit
Table continues on the next page...
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 175
Field Function
FTM6_OBE_CT
RL
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
21
FTM5_OBE_CT
RL
FTM5 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
20
FTM4_OBE_CT
RL
FTM4 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
19
FTM3_OBE_CT
RL
FTM3 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
18
FTM2_OBE_CT
RL
FTM2 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
17
FTM1_OBE_CT
RL
FTM1 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
16
FTM0_OBE_CT
RL
FTM0 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
176 NXP Semiconductors
Field Function
15
—
Reserved
14
FTM_GTB_SPLI
T_EN
FTM GTB split enable/disable bit
Split time base enable/disable.
0b - All the FTMs have a single global time-base
1b - FTM0-3 have a common time-base and others have a different common time-base. Please
refer 'FTM global time base' in FTM chapter for implementation details.
13-11
—
Reserved
10
STOP2_MONIT
OR
STOP2 monitor bit
This status bit monitors system clock status on STOP2 mode entry and can be used for monitoring
whether STOP2 entry was successful or aborted (In STOP2, system clock is disabled and bus clock is
enabled). This bit needs to be W1C after wakeup from STOP2 mode.
NOTE: This bit is reset on POR.
0b - System clock enabled or STOP2 entry aborted
1b - STOP2 entry successful
9
STOP1_MONIT
OR
STOP1 monitor bit
This status bit monitors bus clock status on STOP1 mode entry and can be used for monitoring whether
STOP1 entry was successful or aborted (In STOP1, both system and bus clocks are disabled). This bit
needs to be W1C after wakeup from STOP1 mode.
NOTE: This bit is reset on POR.
0b - Bus clock enabled or STOP1 entry aborted
1b - STOP1 entry successful
8-0
—
Reserved
11.3.1.8 System Device Identification Register (SDID)
11.3.1.8.1 Offset
Register Offset
SDID 24h
11.3.1.8.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 177
11.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGENERATION SUBSERIES DERIVATE RAMSIZE
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RREVID PACKAGE FEATURES
W
Reset uuuuuuuuuuuuuuuu
11.3.1.8.4 Fields
Field Function
31-28
GENERATION
S32K product series generation
Specifies the generation of the S32K product series of chips. Generation for this chip is 1.
27-24
SUBSERIES
Subseries
Specifies the sub-series of the chip. The value is 4 (S32K14x chip) or 1 (S32K11x chip).
23-20
DERIVATE
Derivate
Specifies the derivate of the chip. The value is 8 (S32K148), 6 (S32K146), 4 (S32K144), 2 (S32K142), 8
(S32118), or 6 (S32K116).
19-16
RAMSIZE
RAM size
This field specifies the total amount of system RAM available on the chip, including FlexRAM.
0000b - Reserved
0001b - Reserved
0010b - Reserved
0011b - Reserved
0100b - Reserved
0101b - Reserved
0110b - Reserved
0111b - Reserved
1000b - Reserved
1001b - Reserved
1010b - Reserved
1011b - 192 KB (S32K148), 96 KB (S32K146), Reserved (others)
1100b - Reserved
1101b - 48 KB (S32K144), Reserved (others)
1110b - Reserved
1111b - 256 KB (S32K148), 128 KB (S32K146), 64 KB (S32K144), 32 KB (S32K142), 25 KB
(S32K118), 17 KB (S32K116)
15-12
REVID
Device revision number
Specifies the silicon implementation number for the chip. REV ID for this chip is 0.
11-8
PACKAGE
Package
Specifies the available package options for the chip.
0000b - Reserved
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
178 NXP Semiconductors
Field Function
0001b - Reserved
0010b - 48 LQFP
0011b - 64 LQFP
0100b - 100 LQFP
0101b - Reserved
0110b - 144 LQFP
0111b - 176 LQFP
1000b - 100 MAP BGA
1001b - Reserved
1010b - Reserved
1011b - Reserved
1100b - Reserved
1101b - Reserved
1110b - Reserved
1111b - Reserved
7-0
FEATURES
Features
Specifies the supported features of the chip.
NOTE: • While trying to access memory map region of un-available feature with corresponding
module clock enabled through PCC CGC bit, there will not be any transfer error
termination.
• This bit field overrides the PCC.PR status for the chip.
1 Feature is present
0 Feature is not present
Each bit in this field represents the following:
• Bit 7: Security
• Bit 6: ISO CAN-FD
• Bit 5: FlexIO
• Bit 4: QuadSPI
• Bit 3: ENET
• Bit 2: Reserved
• Bit 1: SAI
• Bit 0: Reserved
11.3.1.9 Platform Clock Gating Control Register (PLATCGC)
11.3.1.9.1 Offset
Register Offset
PLATCGC 40h
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 179
11.3.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
CGCEIM
CGCERM
CGCDMA
CGCMPU
CGCMSCM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
11.3.1.9.3 Fields
Field Function
31-6
—
Reserved
5
—
Reserved
4
CGCEIM
EIM Clock Gating Control
Controls the clock gating to the EIM.
0b - Clock disabled
1b - Clock enabled
3
CGCERM
ERM Clock Gating Control
Controls the clock gating to the ERM.
0b - Clock disabled
1b - Clock enabled
2
CGCDMA
DMA Clock Gating Control
Controls the clock gating to the DMA module.
0b - Clock disabled
1b - Clock enabled
1
CGCMPU
MPU Clock Gating Control
Controls the clock gating to the MPU module.
0b - Clock disabled
1b - Clock enabled
0
CGCMSCM
MSCM Clock Gating Control
Controls the clock gating to the MSCM.
0b - Clock disabled
1b - Clock enabled
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
180 NXP Semiconductors
11.3.1.10 Flash Configuration Register 1 (FCFG1)
11.3.1.10.1 Offset
Register Offset
FCFG1 4Ch
11.3.1.10.2 Function
NOTE
The reset value of DEPART field of this register is loaded
during system reset from flash memory IFR.
NOTE
Attempted writes to this register may result in unpredictable
behavior.
11.3.1.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RReserved Reserved 0EEERAMSIZE
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DEPART
0
Reserved
Reserved
W
Reset uuuuuuuuuuuuuuuu
11.3.1.10.4 Fields
Field Function
31-28
—
Reserved
27-24
—
Reserved
23-20 Reserved
Table continues on the next page...
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 181
Field Function
—
19-16
EEERAMSIZE
EEE SRAM SIZE
EEE SRAM data size.
0000b - Reserved
0001b - Reserved
0010b - 4 KB
0011b - 2 KB
0100b - 1 KB
0101b - 512 Bytes
0110b - 256 Bytes
0111b - 128 Bytes
1000b - 64 Bytes
1001b - 32 Bytes
1111b - 0 Bytes
15-12
DEPART
FlexNVM partition
Data flash memory / emulated EEPROM backup split. See DEPART field description in FTFC chapter.
11-2
—
Reserved
1
—
Reserved
0
—
Reserved
11.3.1.11 Unique Identification Register High (UIDH)
11.3.1.11.1 Offset
Register Offset
UIDH 54h
11.3.1.11.2 Function
NOTE
• UID127_96, UID95_64, UID63_32, and UID31_0 together
represents 128-bit unique identification number for this
device.
• This register's reset value is loaded during system reset
from flash memory IFR.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
182 NXP Semiconductors
11.3.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RUID127_96
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUID127_96
W
Reset uuuuuuuuuuuuuuuu
11.3.1.11.4 Fields
Field Function
31-0
UID127_96
Unique Identification
Unique identification for the chip.
11.3.1.12 Unique Identification Register Mid-High (UIDMH)
11.3.1.12.1 Offset
Register Offset
UIDMH 58h
11.3.1.12.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 183
11.3.1.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RUID95_64
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUID95_64
W
Reset uuuuuuuuuuuuuuuu
11.3.1.12.4 Fields
Field Function
31-0
UID95_64
Unique Identification
Unique identification for the chip.
11.3.1.13 Unique Identification Register Mid Low (UIDML)
11.3.1.13.1 Offset
Register Offset
UIDML 5Ch
11.3.1.13.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
184 NXP Semiconductors
11.3.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RUID63_32
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUID63_32
W
Reset uuuuuuuuuuuuuuuu
11.3.1.13.4 Fields
Field Function
31-0
UID63_32
Unique Identification
Unique identification for the chip.
11.3.1.14 Unique Identification Register Low (UIDL)
11.3.1.14.1 Offset
Register Offset
UIDL 60h
11.3.1.14.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 185
11.3.1.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RUID31_0
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUID31_0
W
Reset uuuuuuuuuuuuuuuu
11.3.1.14.4 Fields
Field Function
31-0
UID31_0
Unique Identification
Unique identification for the chip.
11.3.1.15 System Clock Divider Register 4 (CLKDIV4)
11.3.1.15.1 Offset
Register Offset
CLKDIV4 68h
11.3.1.15.2 Function
NOTE
This register is Reserved for S32K11x variants.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
186 NXP Semiconductors
11.3.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRACEDIVEN
0
W
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRACEDIV
TRACEFRAC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.15.4 Fields
Field Function
31-29
—
Reserved
28
TRACEDIVEN
Debug Trace Divider control
This field controls the Debug Trace Divider.
0b - Debug trace divider disabled
1b - Debug trace divider enabled
27-4
—
Reserved
3-1
TRACEDIV
Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it
after setting TRACEDIV.
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider
input clock * [(TRACEFRAC+1)/(TRACEDIV+1)].
NOTE: TRACEFRAC should be ≤ TRACEDIV
0
TRACEFRAC
Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear
TRACEDIVEN to disable the trace clock divide function.
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider
input clock * [(TRACEFRAC+1)/(TRACEDIV+1)].
NOTE: TRACEFRAC should be ≤ TRACEDIV
Chapter 11 System Integration Module (SIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 187
11.3.1.16 Miscellaneous Control register 1 (MISCTRL1)
11.3.1.16.1 Offset
Register Offset
MISCTRL1 6Ch
11.3.1.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SW_TR
G
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.16.3 Fields
Field Function
31-1
—
Reserved
0
SW_TRG
Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through
TRGMUX (Refer to Figure: Trigger interconnectivity).
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
188 NXP Semiconductors
Chapter 12
Port Control and Interrupts (PORT)
12.1 Chip-specific PORT information
Not all pin control settings mentioned in PORT_PCRn register are configurable for all
pins. Refer 'Bits Configurable' field in 'IO Signal Table' tab of IO Signal Description
Input Multiplexing sheet(s) attached to the Reference Manual. The bits apart from 'Bit
Configurable' fields are reserved and should not be varied from the reset values.
PCR bits corresponding to reset pad are non-sticky bits and on a functional reset, reset
functionality on this pin will be resumed. Prior to entering any ALT functionality, PCR of
corresponding pad should be properly configured.
Before entering Analog mode (ALT0 corresponding to PORT_PCRn[MUX]=3'b000 for
corresponding pads for which Analog functionality is available), PUE and PUS should be
configured as 0 in corresponding PCR register.
PORT_PCRn[PFE] is configurable for only PTA5 and PTD3. See IO Signal Description
Input Multiplexing sheet(s) attached to the Reference Manual. PFE for these should be
configured in ALT7 mode only. For other modes, PFE should be kept 0.
The corresponding PAD should be configured for disabled mode(ALT0) prior to
configuring PORT_DFER register.
Any pad configuration done in RUN/VLPR mode is retained in low power
modes(STOP1,STOP2/VLPS).
Wait mode is not supported on this device.
See Module operation in available low power modes for details on available power
modes.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 189
12.1.1 Number of PCRs
The number of PCRs for each PORT varies across the products in the S32K1xx series.
The following table shows the number of PCRs for each PORT on each product. Memory
map and register definition documents the superset number of implemented ports. PCR
registers corresponding to ports which are not present in a particular device are read only
0. See the RM attachments IO Signal Description Input Multiplexing sheet(s) for details
on the count of PCRs on each product.
Table 12-1. PCRs on each product
PORT Number of PCRs1
S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
PORT A 11 12 18 18 25 32
PORT B 9 10 18 18 27 32
PORT C 12 14 18 18 25 32
PORT D 7 10 18 18 27 32
PORT E 4 12 17 17 24 28
1. See the attachments IO Signal Description Input Multiplexing sheet(s) for details.
12.1.2 I/O configuration sequence
1. Ensure pins for the peripheral are in tristate sate (default out of reset).
2. Initialize peripheral clock in the Peripheral Clock Controller register(PCC) and
peripheral specific clocking configurations.
3. Configure the peripheral
4. Initialize port clock for the peripheral pins in the Peripheral Clock Controller register
(PCC_PORTx).
5. Configure the peripheral pins mux and features in the Port Control and Interrupts
register (PORTx_PCRn).
6. Start communication
12.1.3 Digital input filter configuration sequence
1. Configure digital pin filtering controls for the corresponding pin using
PORTx_DFCR and PORTx_DFWR
2. Enable PORTx_DFER[DFE]
3. Configure PORTx_PCRn[MUX] for GPIO mode
4. Wait for delay equivalent to PORTx_DFWR for filter enabling glitches to propagate
5. Enable the corresponding function of the pin by configuring PORTx_PCRn[MUX]
Chip-specific PORT information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
190 NXP Semiconductors
12.1.3.1 Digital input filter configuration sequence while using GPIO
interrupt
1. Configure digital pin filtering controls for the corresponding pin using
PORTx_DFCR and PORTx_DFWR
2. Enable PORTx_DFER[DFE]
3. Configure PORTx_PCRn[MUX] for GPIO mode
4. Wait for delay equivalent to PORTx_DFWR for filter enabling glitches to propagate
5. Enable the interrupt on the corresponding pin by configuring PORTx_PCRn[IRQC]
12.1.3.2 Digital input filter configuration sequence while using NMI
1. Configure digital pin filtering controls for NMI pin using PORTD_DFCR and
PORTD_DFWR
2. Enable PORTD_DFER[3]
3. Configure PORTD_PCR3[MUX] for GPIO mode
4. Wait for delay equivalent to PORTD_DFWR for filter enabling glitches to propagate
5. Configure the pin for NMI mode using PORTD_PCR3[MUX]
Before entering STOP/VLPS modes, filter clock should be configured as
LPO128K_CLK and reconfigured on wakeup, if required.
If filtering is not required in STOP/VLPS modes, filtering should be disabled using
PORTx_DFER and reconfigured on wakeup, if required. If filtering is not required in
STOP/VLPS modes and is required wakeup onwards without reconfiguring
PORTx_DFER (with bus clock as filter clock), it should be ensured that:
cycles_tISR >> (PORTx_DFWR+3)*(SCG_xCCR[DIVBUS]+1)
where cycles_tISR: Core clock cycles in Interrupt Service Routine (ISR) from system
entering RUN mode till PORTx_PCRn[ISF] clearing for corresponding pin.
(Sufficient delay should be added in ISR, if required, to achieve the above)
12.2 Introduction
12.3 Overview
The Port Control and Interrupt (PORT) module provides support for port control, digital
filtering, and external interrupt functions.
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 191
Most functions can be configured independently for each pin in the 32-bit port and affect
the pin regardless of its pin muxing state.
There is one instance of the PORT module for each port. Not all pins within each port are
implemented on a specific device.
12.3.1 Features
The PORT module has the following features:
• Pin interrupt
• Interrupt flag and enable registers for each pin
• Support for edge sensitive (rising, falling, both) or level sensitive (low, high)
configured per pin
• Support for interrupt or DMA request configured per pin
• Asynchronous wake-up in low-power modes
• Pin interrupt is functional in all digital pin muxing modes
• Digital input filter
• Digital input filter for each pin, usable by any digital peripheral muxed onto the
pin
• Individual enable or bypass control field per pin
• Selectable clock source for digital input filter with a five bit resolution on filter
size
• Functional in all digital pin multiplexing modes
• Port control
• Individual pull control fields with pullup, pulldown, and pull-disable support
• Individual drive strength field supporting high and low drive strength
• Individual input passive filter field supporting enable and disable of the
individual input passive filter
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
six chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
12.3.2 Modes of operation
12.3.2.1 Run mode
In Run mode, the PORT operates normally.
Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
192 NXP Semiconductors
12.3.2.2 Wait mode
In Wait mode, PORT continues to operate normally and may be configured to exit the
Low-Power mode if an enabled interrupt is detected. DMA requests are still generated
during the Wait mode, but do not cause an exit from the Low-Power mode.
12.3.2.3 Stop mode
In Stop mode, the PORT can be configured to exit the Low-Power mode via an
asynchronous wake-up signal if an enabled interrupt is detected.
In Stop mode, the digital input filters are bypassed unless they are configured to run from
the LPO clock source.
12.3.2.4 Debug mode
In Debug mode, PORT operates normally.
12.4 External signal description
The table found here describes the PORT external signal.
Table 12-2. Signal properties
Name Function I/O Reset Pull
PORTx[31:0] External interrupt I/O 0 -
NOTE
Not all pins within each port are implemented on each device.
12.5 Detailed signal description
The table found here contains the detailed signal description for the PORT interface.
Table 12-3. PORT interface—detailed signal description
Signal I/O Description
PORTx[31:0] I/O External interrupt.
State meaning Asserted—pin is logic 1.
Negated—pin is logic 0.
Table continues on the next page...
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 193
Table 12-3. PORT interface—detailed signal description (continued)
Signal I/O Description
Timing Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.
12.6 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
0 Pin Control Register n (PORT_PCR0) 32 R/W See section 12.6.1/196
4 Pin Control Register n (PORT_PCR1) 32 R/W See section 12.6.1/196
8 Pin Control Register n (PORT_PCR2) 32 R/W See section 12.6.1/196
C Pin Control Register n (PORT_PCR3) 32 R/W See section 12.6.1/196
10 Pin Control Register n (PORT_PCR4) 32 R/W See section 12.6.1/196
14 Pin Control Register n (PORT_PCR5) 32 R/W See section 12.6.1/196
18 Pin Control Register n (PORT_PCR6) 32 R/W See section 12.6.1/196
1C Pin Control Register n (PORT_PCR7) 32 R/W See section 12.6.1/196
20 Pin Control Register n (PORT_PCR8) 32 R/W See section 12.6.1/196
24 Pin Control Register n (PORT_PCR9) 32 R/W See section 12.6.1/196
28 Pin Control Register n (PORT_PCR10) 32 R/W See section 12.6.1/196
2C Pin Control Register n (PORT_PCR11) 32 R/W See section 12.6.1/196
30 Pin Control Register n (PORT_PCR12) 32 R/W See section 12.6.1/196
34 Pin Control Register n (PORT_PCR13) 32 R/W See section 12.6.1/196
38 Pin Control Register n (PORT_PCR14) 32 R/W See section 12.6.1/196
3C Pin Control Register n (PORT_PCR15) 32 R/W See section 12.6.1/196
40 Pin Control Register n (PORT_PCR16) 32 R/W See section 12.6.1/196
44 Pin Control Register n (PORT_PCR17) 32 R/W See section 12.6.1/196
48 Pin Control Register n (PORT_PCR18) 32 R/W See section 12.6.1/196
4C Pin Control Register n (PORT_PCR19) 32 R/W See section 12.6.1/196
50 Pin Control Register n (PORT_PCR20) 32 R/W See section 12.6.1/196
54 Pin Control Register n (PORT_PCR21) 32 R/W See section 12.6.1/196
58 Pin Control Register n (PORT_PCR22) 32 R/W See section 12.6.1/196
5C Pin Control Register n (PORT_PCR23) 32 R/W See section 12.6.1/196
60 Pin Control Register n (PORT_PCR24) 32 R/W See section 12.6.1/196
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
194 NXP Semiconductors
PORT memory map (continued)
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
64 Pin Control Register n (PORT_PCR25) 32 R/W See section 12.6.1/196
68 Pin Control Register n (PORT_PCR26) 32 R/W See section 12.6.1/196
6C Pin Control Register n (PORT_PCR27) 32 R/W See section 12.6.1/196
70 Pin Control Register n (PORT_PCR28) 32 R/W See section 12.6.1/196
74 Pin Control Register n (PORT_PCR29) 32 R/W See section 12.6.1/196
78 Pin Control Register n (PORT_PCR30) 32 R/W See section 12.6.1/196
7C Pin Control Register n (PORT_PCR31) 32 R/W See section 12.6.1/196
80 Global Pin Control Low Register (PORT_GPCLR) 32
W
(always
reads 0)
0000_0000h 12.6.2/199
84 Global Pin Control High Register (PORT_GPCHR) 32
W
(always
reads 0)
0000_0000h 12.6.3/199
88 Global Interrupt Control Low Register (PORT_GICLR) 32
W
(always
reads 0)
0000_0000h 12.6.4/200
8C Global Interrupt Control High Register (PORT_GICHR) 32
W
(always
reads 0)
0000_0000h 12.6.5/200
A0 Interrupt Status Flag Register (PORT_ISFR) 32 w1c 0000_0000h 12.6.6/201
C0 Digital Filter Enable Register (PORT_DFER) 32 R/W 0000_0000h 12.6.7/202
C4 Digital Filter Clock Register (PORT_DFCR) 32 R/W 0000_0000h 12.6.8/202
C8 Digital Filter Width Register (PORT_DFWR) 32 R/W 0000_0000h 12.6.9/203
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 195
12.6.1 Pin Control Register n (PORT_PCRn)
NOTE
See the Signal Multiplexing and Pin Assignment chapter for the
reset value of this device.
See the GPIO Configuration section for details on the available
functions for each pin.
Do not modify pin configuration registers associated with pins
that are not available in a reduced-pin package offering.
Unbonded pins not available in a package are disabled by
default to prevent them from consuming power.
Address: 0h base + 0h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0 ISF 0
IRQC
Ww1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LK
0
MUX
0
DSE
Reserved
PFE
0
Reserved
PE PS
W
Reset 0 0 0 0 0 * * * 0 * 0 * 0 0 * *
* Notes:
MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
196 NXP Semiconductors
PORT_PCRn field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24
ISF
Interrupt Status Flag
The pin interrupt configuration is valid in all digital pin muxing modes.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
IRQC
Interrupt Configuration
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt/DMA request as follows:
0000 Interrupt Status Flag (ISF) is disabled.
0001 ISF flag and DMA request on rising edge.
0010 ISF flag and DMA request on falling edge.
0011 ISF flag and DMA request on either edge.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 ISF flag and Interrupt when logic 0.
1001 ISF flag and Interrupt on rising-edge.
1010 ISF flag and Interrupt on falling-edge.
1011 ISF flag and Interrupt on either edge.
1100 ISF flag and Interrupt when logic 1.
1101 Reserved.
1110 Reserved.
1111 Reserved.
15
LK
Lock Register
0 Pin Control Register fields [15:0] are not locked.
1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
14–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
MUX
Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
000 Pin disabled (Alternative 0) (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
Table continues on the next page...
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 197
PORT_PCRn field descriptions (continued)
Field Description
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
DSE
Drive Strength Enable
Drive strength configuration is valid in all digital pin muxing modes.
0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
5
Reserved
This field is reserved.
4
PFE
Passive Filter Enable
Passive filter configuration is valid in all digital pin muxing modes.
0 Passive input filter is disabled on the corresponding pin.
1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer
to the device data sheet for filter characteristics.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
Reserved
This field is reserved.
1
PE
Pull Enable
Pull configuration is valid in all digital pin muxing modes.
0 Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a
digital input.
0
PS
Pull Select
Pull configuration is valid in all digital pin muxing modes.
0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
198 NXP Semiconductors
12.6.2 Global Pin Control Low Register (PORT_GPCLR)
Only 32-bit writes are supported to this register.
Address: 0h base + 80h offset = 80h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
WGPWE GPWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_GPCLR field descriptions
Field Description
31–16
GPWE
Global Pin Write Enable
Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a
selected Pin Control Register is locked then the write to that register is ignored.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
12.6.3 Global Pin Control High Register (PORT_GPCHR)
Only 32-bit writes are supported to this register.
Address: 0h base + 84h offset = 84h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
WGPWE GPWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_GPCHR field descriptions
Field Description
31–16
GPWE
Global Pin Write Enable
Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a
selected Pin Control Register is locked then the write to that register is ignored.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data
Table continues on the next page...
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 199
PORT_GPCHR field descriptions (continued)
Field Description
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
12.6.4 Global Interrupt Control Low Register (PORT_GICLR)
Only 32-bit writes are supported to this register.
Address: 0h base + 88h offset = 88h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
WGIWD GIWE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_GICLR field descriptions
Field Description
31–16
GIWD
Global Interrupt Write Data
Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE.
GIWE Global Interrupt Write Enable
Selects which Pin Control Registers (15 through 0) bits [31:16] update with the value in GIWD.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
12.6.5 Global Interrupt Control High Register (PORT_GICHR)
Only 32-bit writes are supported to this register.
Address: 0h base + 8Ch offset = 8Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
WGIWD GIWE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_GICHR field descriptions
Field Description
31–16
GIWD
Global Interrupt Write Data
Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
200 NXP Semiconductors
PORT_GICHR field descriptions (continued)
Field Description
GIWE Global Interrupt Write Enable
Selects which Pin Control Registers (31 through 16) bits [31:16] update with the value in GIWD.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
12.6.6 Interrupt Status Flag Register (PORT_ISFR)
The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt
Status Flag for each pin is also visible in the corresponding Pin Control Register, and
each flag can be cleared in either location.
Address: 0h base + A0h offset = A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISF
Ww1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_ISFR field descriptions
Field Description
ISF Interrupt Status Flag
Each bit in the field indicates the detection of the configured interrupt of the same number as the field.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 201
12.6.7 Digital Filter Enable Register (PORT_DFER)
The digital filter configuration is valid in all digital pin muxing modes.
Address: 0h base + C0h offset = C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDFE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_DFER field descriptions
Field Description
DFE Digital Filter Enable
The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is
reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the
digital filter of the same number as the field.
0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
12.6.8 Digital Filter Clock Register (PORT_DFCR)
The digital filter configuration is valid in all digital pin muxing modes.
Address: 0h base + C4h offset = C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0CS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_DFCR field descriptions
Field Description
31–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
CS
Clock Source
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
202 NXP Semiconductors
PORT_DFCR field descriptions (continued)
Field Description
The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the
digital input filters. Changing the filter clock source must be done only when all digital filters are disabled.
0 Digital filters are clocked by the bus clock.
1 Digital filters are clocked by the LPO clock.
12.6.9 Digital Filter Width Register (PORT_DFWR)
The digital filter configuration is valid in all digital pin muxing modes.
Address: 0h base + C8h offset = C8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0FILT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORT_DFWR field descriptions
Field Description
31–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FILT Filter Length
The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the
glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters. Glitches that are longer
than this register setting will pass through the digital filter, and glitches that are equal to or less than this
register setting are filtered. Changing the filter length must be done only after all filters are disabled.
12.7 Functional description
12.7.1 Pin control
Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it.
The upper half of the Pin Control register configures the pin's capability to either
interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as
well as a logic level occurring on the port pin. It also includes a flag to indicate that an
interrupt has occurred.
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 203
The lower half of the Pin Control register configures the following functions for each pin
within the 32-bit port.
• Pullup or pulldown enable
• Drive strength
• Passive input filter enable
• Pin Muxing mode
The functions apply across all digital pin muxing modes and individual peripherals do not
override the configuration in the Pin Control register. For example, if an I2C function is
enabled on a pin, that does not override the pullup configuration for that pin.
When the Pin Muxing mode is configured for analog or is disabled, all the digital
functions on that pin are disabled. This includes the pullup and pulldown enables, output
buffer enable, input buffer enable, and passive filter enable.
The LK bit (bit 15 of Pin Control Register PCRn) allows the configuration for each pin to
be locked until the next system reset. When locked, writes to the lower half of that pin
control register are ignored, although a bus error is not generated on an attempted write to
a locked register.
The configuration of each Pin Control register is retained when the PORT module is
disabled.
Whenever a pin is configured in any digital pin muxing mode, the input buffer for that
pin is enabled allowing the pin state to be read via the corresponding GPIO Port Data
Input Register (GPIO_PDIR) or allowing a pin interrupt or DMA request to be generated.
If a pin is ever floating when its input buffer is enabled, then this can cause an increase in
power consumption and must be avoided. A pin can be floating due to an input pin that is
not connected or an output pin that has tri-stated (output buffer is disabled).
Enabling the internal pull resistor (or implementing an external pull resistor) will ensure a
pin does not float when its input buffer is enabled; note that the internal pull resistor is
automatically disabled whenever the output buffer is enabled allowing the Pull Enable bit
to remain set. Configuring the Pin Muxing mode to disabled or analog will disable the
pin’s input buffer and results in the lowest power consumption.
12.7.2 Global pin control
The two global pin control registers allow a single register write to update the lower half
of the pin control register on up to 16 pins, all with the same value. Registers that are
locked cannot be written using the global pin control registers.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
204 NXP Semiconductors
The global pin control registers are designed to enable software to quickly configure
multiple pins within the one port for the same peripheral function. However, the interrupt
functions cannot be configured using the global pin control registers.
The global pin control registers are write-only registers, that always read as 0.
12.7.3 Global interrupt control
The two global interrupt control registers allow a single register write to update the upper
half of the pin control register on up to 16 pins, all with the same value.
The global interrupt control registers are designed to enable software to quickly configure
multiple pins within the one port for the same interrupt configuration. However, the pin
control functions cannot be configured using the global interrupt control registers.
The global interrupt control registers are write-only registers and always read as 0.
12.7.4 External interrupts
The external interrupt capability of the PORT module is available in all digital pin
muxing modes provided the PORT module is enabled.
Each pin can be individually configured for any of the following external interrupt
modes:
• Interrupt disabled, default out of reset
• Active high level sensitive interrupt
• Active low level sensitive interrupt
• Rising edge sensitive interrupt
• Falling edge sensitive interrupt
• Rising and falling edge sensitive interrupt
• Rising edge sensitive DMA request
• Falling edge sensitive DMA request
• Rising and falling edge sensitive DMA request
The interrupt status flag is set when the configured edge or level is detected on the pin or
at the output of the digital input filter, if the digital input digital filter is enabled. When
not in Stop mode, the input is first synchronized to the bus clock to detect the configured
level or edge transition.
Chapter 12 Port Control and Interrupts (PORT)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 205
The PORT module generates a single interrupt that asserts when the interrupt status flag
is set for any enabled interrupt for that port. The interrupt negates after the interrupt status
flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in
either the PORT_ISFR or PORT_PCRn registers.
The PORT module generates a single DMA request that asserts when the interrupt status
flag is set for any enabled DMA request in that port. The DMA request negates after the
DMA transfer is completed, because that clears the interrupt status flags for all enabled
DMA requests.
During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously
set if the required level or edge is detected. This also generates an asynchronous wake-up
signal to exit the Low-Power mode.
12.7.5 Digital filter
The digital filter capabilities of the PORT module are available in all digital Pin Muxing
modes if the PORT module is enabled.
The clock used for all digital filters within one port can be configured between the bus
clock or the LPO clock. This selection must be changed only when all digital filters for
that port are disabled. If the digital filters for a port are configured to use the bus clock,
then the digital filters are bypassed for the duration of Stop mode. While the digital filters
are bypassed, the output of each digital filter always equals the input pin, but the internal
state of the digital filters remains static and does not update due to any change on the
input pin.
The filter width in clock size is the same for all enabled digital filters within one port and
must be changed only when all digital filters for that port are disabled.
The output of each digital filter is logic zero after system reset and whenever a digital
filter is disabled. After a digital filter is enabled, the input is synchronized to the filter
clock, either the bus clock or the LPO clock. If the synchronized input and the output of
the digital filter remain different for a number of filter clock cycles equal to the filter
width register configuration, then the output of the digital filter updates to equal the
synchronized filter input.
The maximum latency through a digital filter equals three filter clock cycles plus the
filter width configuration register.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
206 NXP Semiconductors
Chapter 13
General-Purpose Input/Output (GPIO)
Chip-specific GPIO information
13.1.1 Instantiation information
Port control and interrupt module features are supported, each 32-pin port will support a
single interrupt. Not all pins are available on each package supported. See IO Signal
Description Input Multiplexing sheet(s) attached to the Reference Manual for the details
on which pins are supported in different packages. See Port Control and Interrupts
(PORT) for details of how to control the ports.
See Module operation in available low power modes for details on available power
modes.
13.1.2 GPIO ports memory map
This chip implements five instances of GPIOs GPIOA to GPIOE. The GPIO register
descriptions in this chapter are generic. Refer to the table below to see how addresses are
allocated to every instance of GPIO in the device memory map.
Table 13-1. GPIO ports memory map
Start address Port
Base + 0h Port A
Base + 40h Port B
Base + 80h Port C
Base + C0h Port D
Base + 100h Port E
13.1
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 207
NOTE
• In S32K14x, GPIO can only be accessed by the core
through the cross bar interface at 0x400F_F000.
• In S32K11x, GPIO is multi-ported and can be accessed
directly by the core with zero wait states at base address
[0xF800_0000 + 0x40*n (n: 0 to 4)]. It can also be
accessed by the core through the cross bar/AIPS interface
at [0x400F_F000 + 0x40*n (n: 0 to 4)] and at an aliased
slot (15) at address [0x4000_F000 + 0x40*n (n: 0 to 4)].
• In S32K11x, when in GPIO mode (PORT_PCRn[MUX]
programmed to 0x1), the register PIDR cannot be written to
0x1. This programming helps to disable the input mode and
this is not possible to achieve in S32K11x. The implication
of this is that when the GPIO is configured in output mode
(PDDR[n] programmed to 1), the data written on PDOR
register would be reflected on PDIR after some delay if the
output does not toggle to often. If the pad needs to be tri-
stated, the PORT_PCRn[MUX] needs to be 00.
GPIO at 0x400FF000 GPIO at 0x4000F000 GPIO at 0xF8000000
S32K14x Accessible in CPO mode NA NA
S32K11x Not accessible in CPO mode Not accessible in CPO mode Accessible in CPO mode
13.1.3 GPIO register reset values
Following table defines the chip-specific register reset value.
Table 13-2. GPIO register reset values
Register Reset value
PDIR 0000_0020
13.2 Introduction
The general-purpose input and output (GPIO) module communicates to the processor
core via a zero wait state interface for maximum pin performance. The GPIO registers
support 8-bit, 16-bit or 32-bit accesses.
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
208 NXP Semiconductors
The GPIO data direction and output data registers control the direction and output data of
each pin when the pin is configured for the GPIO function. The GPIO input data register
displays the logic value on each pin when the pin is configured for any digital function,
provided the corresponding Port Control and Interrupt module for that pin is enabled.
Efficient bit manipulation of the general-purpose outputs is supported through the
addition of set, clear, and toggle write-only registers for each port output data register.
13.2.1 Features
Features of the GPIO module include:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
• Port Data Direction register
NOTE
The GPIO module is clocked by system clock.
13.2.2 Modes of operation
The following table depicts different modes of operation and the behavior of the GPIO
module in these modes.
Table 13-3. Modes of operation
Modes of operation Description
Run The GPIO module operates normally.
Stop The GPIO module is disabled.
Debug The GPIO module operates normally.
13.2.3 GPIO signal descriptions
Table 13-4. GPIO signal descriptions
GPIO signal descriptions Description I/O
PORTA31–PORTA0 General-purpose input/output I/O
PORTB31–PORTB0 General-purpose input/output I/O
PORTC31–PORTC0 General-purpose input/output I/O
PORTD31–PORTD0 General-purpose input/output I/O
PORTE31–PORTE0 General-purpose input/output I/O
Chapter 13 General-Purpose Input/Output (GPIO)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 209
NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.
13.2.3.1 Detailed signal description
Table 13-5. GPIO interface-detailed signal descriptions
Signal I/O Description
PORTA31–PORTA0
PORTB31–PORTB0
PORTC31–PORTC0
PORTD31–PORTD0
PORTE31–PORTE0
I/O General-purpose input/output
State meaning Asserted: The pin is logic 1.
Deasserted: The pin is logic 0.
Timing Assertion: When output, this
signal occurs on the rising-
edge of the system clock. For
input, it may occur at any time
and input may be asserted
asynchronously to the system
clock.
Deassertion: When output,
this signal occurs on the
rising-edge of the system
clock. For input, it may occur
at any time and input may be
asserted asynchronously to
the system clock.
NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.
13.3 Memory map and register definition
The registers for each GPIO port occupy 64-byte of the memory map. Any read or write
access to the GPIO slot outside this space results in a bus error.
NOTE
For simplicity, each GPIO port's registers appear with the same
width of 32 bits, corresponding to 32 pins. The actual number
of pins per port (and therefore the number of usable control bits
per port register) is chip-specific. Refer to the chip-specific
GPIO information to see the exact control bits for each port.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
210 NXP Semiconductors
13.3.1 GPIO register descriptions
13.3.1.1 GPIO Memory map
GPIOA base address: 400F_F000h
GPIOB base address: 400F_F040h
GPIOC base address: 400F_F080h
GPIOD base address: 400F_F0C0h
GPIOE base address: 400F_F100h
Offset Register Width
(In bits)
Access Reset value
0h Port Data Output Register (PDOR) 32 RW 0000_0000h
4h Port Set Output Register (PSOR) 32 WORZ 0000_0000h
8h Port Clear Output Register (PCOR) 32 WORZ 0000_0000h
Ch Port Toggle Output Register (PTOR) 32 WORZ 0000_0000h
10h Port Data Input Register (PDIR) 32 RO 0000_0000h
14h Port Data Direction Register (PDDR) 32 RW 0000_0000h
18h Port Input Disable Register (PIDR) 32 RW 0000_0000h
13.3.1.2 Port Data Output Register (PDOR)
13.3.1.2.1 Offset
Register Offset
PDOR 0h
13.3.1.2.2 Function
This register configures the logic levels that are driven on each general-purpose output
pin.
Chapter 13 General-Purpose Input/Output (GPIO)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 211
NOTE
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
13.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPDO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPDO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.2.4 Fields
Field Function
31-0
PDO
Port Data Output
Register bits for unbonded pins return an undefined value when read.
0b - Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1b - Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
13.3.1.3 Port Set Output Register (PSOR)
13.3.1.3.1 Offset
Register Offset
PSOR 4h
13.3.1.3.2 Function
This register configures whether to set the fields of the PDOR.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
212 NXP Semiconductors
13.3.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
WPTSO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
WPTSO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.3.4 Fields
Field Function
31-0
PTSO
Port Set Output
Writing to this register updates the contents of the corresponding bit in the PDOR as follows:
0b - Corresponding bit in PDORn does not change.
1b - Corresponding bit in PDORn is set to logic 1.
13.3.1.4 Port Clear Output Register (PCOR)
13.3.1.4.1 Offset
Register Offset
PCOR 8h
13.3.1.4.2 Function
This register configures whether to clear the fields of PDOR.
Chapter 13 General-Purpose Input/Output (GPIO)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 213
13.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
WPTCO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
WPTCO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.4.4 Fields
Field Function
31-0
PTCO
Port Clear Output
Writing to this register updates the contents of the corresponding bit in the Port Data Output Register
(PDOR) as follows:
0b - Corresponding bit in PDORn does not change.
1b - Corresponding bit in PDORn is cleared to logic 0.
13.3.1.5 Port Toggle Output Register (PTOR)
13.3.1.5.1 Offset
Register Offset
PTOR Ch
13.3.1.5.2 Function
This register toggles the logic levels that are driven on each general-purpose output pin.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
214 NXP Semiconductors
13.3.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
WPTTO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
WPTTO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.5.4 Fields
Field Function
31-0
PTTO
Port Toggle Output
Writing to this register updates the contents of the corresponding bit in the PDOR as follows:
0b - Corresponding bit in PDORn does not change.
1b - Corresponding bit in PDORn is set to the inverse of its existing logic state.
13.3.1.6 Port Data Input Register (PDIR)
13.3.1.6.1 Offset
Register Offset
PDIR 10h
13.3.1.6.2 Function
This register captures the logic levels that are driven into each general-purpose input pin.
NOTE
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
Chapter 13 General-Purpose Input/Output (GPIO)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 215
13.3.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPDI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPDI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.6.4 Fields
Field Function
31-0
PDI
Port Data Input
Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital
function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR
does not update.
0b - Pin logic level is logic 0, or is not configured for use by digital function.
1b - Pin logic level is logic 1.
13.3.1.7 Port Data Direction Register (PDDR)
13.3.1.7.1 Offset
Register Offset
PDDR 14h
13.3.1.7.2 Function
The PDDR configures the individual port pins for input or output.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
216 NXP Semiconductors
13.3.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPDD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPDD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.7.4 Fields
Field Function
31-0
PDD
Port Data Direction
Configures individual port pins for input or output.
0b - Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the
port input is disabled in GPIOx_PIDR register.
1b - Pin is configured as general-purpose output, for the GPIO function.
13.3.1.8 Port Input Disable Register (PIDR)
13.3.1.8.1 Offset
Register Offset
PIDR 18h
13.3.1.8.2 Function
This register disables each general-purpose pin from acting as an input.
Chapter 13 General-Purpose Input/Output (GPIO)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 217
13.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.3.1.8.4 Fields
Field Function
31-0
PID
Port Input Disable
0b - Pin is configured for General Purpose Input, provided the pin is configured for any digital
function.
1b - Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will
read zero.
13.4 Functional description
13.4.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the
corresponding bit in the port input enable register is set, the pin is configured for a digital
function and the corresponding Port Control and Interrupt module is enabled.
The input pin synchronizers are shared with the Port Control and Interrupt module, so
that if the corresponding Port Control and Interrupt module is disabled, then
synchronizers are also disabled. This reduces power consumption when a port is not
required for general-purpose input functionality.
13.4.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
218 NXP Semiconductors
If Then
A pin is configured for the GPIO function and the
corresponding port data direction register bit is clear.
The pin is configured as an input.
A pin is configured for the GPIO function and the
corresponding port data direction register bit is set.
The pin is configured as an output and the logic state of the
pin is equal to the corresponding port data output register.
To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin
data clear, and pin data toggle registers exist to allow one or more outputs within one port
to be set, cleared, or toggled from a single register write.
The corresponding Port Control and Interrupt module does not need to be enabled to
update the state of the port data direction registers and port data output registers including
the set/clear/toggle registers.
Chapter 13 General-Purpose Input/Output (GPIO)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 219
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
220 NXP Semiconductors
Chapter 14
Crossbar Switch Lite (AXBS-Lite)
Chip-specific AXBS-Lite information
14.1.1 Crossbar Switch master assignments
The following table identifies the masters connected to the Crossbar Switch and their
priority order in fixed-priority mode.
Table 14-1. Master port assignments and priority order for fixed-priority arbitration
Chips Master port number 0 Master port number 1 Master port number 2 Master port number 3
Priority 3 1Priority 21Priority 11Priority 41
S32K148 Arm core code bus Arm core system bus DMA ENET
S32K146 Arm core code bus Arm core system bus DMA -
S32K144 Arm core code bus Arm core system bus DMA
S32K142 Arm core code bus Arm core system bus DMA
S32K116 Arm core master bus - DMA
S32K118 Arm core master bus - DMA
1. Priority in fixed-priority mode. MCM controls mode selection for global slave port arbitration. For fixed priority, set
MCM_CPCR[CBRR] to 0. For round robin, set MCM_CPCR[CBRR] to 1. The arbitration setting applies to all slave ports.
14.1.2 Crossbar Switch slave assignments
The following table identifies the slaves connected to the Crossbar Switch and whether
the system MPU protects them.
Table 14-2. Slave port assignments and system MPU protection
Chips Slave port number 0 Slave port number 1 Slave port number 2 Slave port number 3
S32K148 Flash memory
controller1SRAM controllers 1Peripheral Bridge 0/
GPIO 2QuadSPI 1
Table continues on the next page...
14.1
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 221
Table 14-2. Slave port assignments and system MPU protection (continued)
Chips Slave port number 0 Slave port number 1 Slave port number 2 Slave port number 3
S32K146 Flash memory
controller1SRAM controllers 1Peripheral Bridge 0/
GPIO 2-
S32K144 Flash memory
controller 1SRAM controllers 1Peripheral Bridge 0/
GPIO 2
S32K142 Flash memory
controller 1SRAM controllers 1Peripheral Bridge 0/
GPIO 2
S32K116 Flash memory
controller 1SRAM controllers 1Peripheral Bridge 0/
GPIO 2
S32K118 Flash memory
controller 1SRAM controllers 1Peripheral Bridge 0/
GPIO2
1. Protected by system MPU
2. Not protected by system MPU: System MPU does not protect access to peripheral registers, including system MPU's own
registers. Protection is built into Peripheral Bridge (AIPS-Lite).
14.2 Introduction
The information found here provides information on the layout, configuration, and
programming of the crossbar switch.
The crossbar switch connects bus masters and bus slaves using a crossbar switch
structure. This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access the
same slave.
14.2.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• Up to single-clock 32-bit transfer
• Programmable configuration for fixed-priority or round-robin slave port arbitration
(see the chip-specific information).
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
222 NXP Semiconductors
14.3 Functional Description
Information about general operation and arbitration can be found here.
14.3.1 General operation
When a master accesses the crossbar switch, the access is immediately taken. If the
targeted slave port of the access is available, then the access is immediately presented on
the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.
If the targeted slave port of the access is busy or parked on a different master port, the
requesting master simply sees wait states inserted until the targeted slave port can service
the master's request. The latency in servicing the request depends on each master's
priority level and the responding slave's access time.
Because the crossbar switch appears to be just another slave to the master device, the
master device has no knowledge of whether it actually owns the slave port it is targeting.
While the master does not have control of the slave port it is targeting, it simply waits.
After the master has control of the slave port it is targeting, the master remains in control
of the slave port until it relinquishes the slave port by running an IDLE cycle or by
targeting a different slave port for its next access.
The master can also lose control of the slave port if another higher-priority master makes
a request to the slave port.
The crossbar terminates all master IDLE transfers, as opposed to allowing the termination
to come from one of the slave buses. Additionally, when no master is requesting access to
a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default
master may be granted access to the slave port.
When a slave bus is being idled by the crossbar, it remains parked with the last master to
use the slave port. This is done to save the initial clock of arbitration delay that otherwise
would be seen if the same master had to arbitrate to gain control of the slave port.
14.3.2 Arbitration
The crossbar switch supports two arbitration algorithms:
• Fixed priority
• Round-robin
Chapter 14 Crossbar Switch Lite (AXBS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 223
The selection of the global slave port arbitration algorithm is described in the crossbar
switch chip-specific information.
14.3.2.1 Arbitration during undefined length bursts
Undefined length bursts can be interrupted.
14.3.2.2 Fixed-priority operation
When operating in fixed-priority mode, each master is assigned a unique priority level
with the highest numbered master having the highest priority (for example, in a system
with 5 masters, master 1 has lower priority than master 3). If two masters request access
to the same slave port, the master with the highest priority gains control over the slave
port.
NOTE
In this arbitration mode, a higher-priority master can
monopolize a slave port, preventing accesses from any lower-
priority master to the port.
When a master makes a request to a slave port, the slave port checks whether the new
requesting master's priority level is higher than that of the master that currently has
control over the slave port, unless the slave port is in a parked state. The slave port
performs an arbitration check at every clock edge to ensure that the proper master, if any,
has control of the slave port.
The following table describes possible scenarios based on the requesting master port:
Table 14-3. How the Crossbar Switch grants control of a slave port to a master
When Then the Crossbar Switch grants control to the
requesting master
Both of the following are true:
• The current master is not running a transfer.
• The new requesting master's priority level is higher than
that of the current master.
At the next clock edge
Both of the following are true:
• The current master is running an undefined length burst
transfer.
• The requesting master's priority level is higher than that
of the current master.
At the next arbitration point for the undefined length burst
transfer
The requesting master's priority level is lower than the current
master.
At the conclusion of one of the following cycles:
• An IDLE cycle
• A non-IDLE cycle to a location other than the current
slave port
Functional Description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
224 NXP Semiconductors
14.3.2.3 Round-robin priority operation
When operating in round-robin mode, each master is assigned a relative priority based on
the master port number. This relative priority is compared to the master port number (ID)
of the last master to perform a transfer on the slave bus. The highest priority requesting
master becomes owner of the slave bus at the next transfer boundary. Priority is based on
how far ahead the ID of the requesting master is to the ID of the last master.
After granted access to a slave port, a master may perform as many transfers as desired to
that port until another master makes a request to the same slave port. The next master in
line is granted access to the slave port at the next transfer boundary, or possibly on the
next clock cycle if the current master has no pending access request.
As an example of arbitration in round-robin mode, assume the crossbar is implemented
with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and
master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5
then 0.
The round-robin arbitration mode generally provides a more fair allocation of the
available slave-port bandwidth (compared to fixed priority) as the fixed master priority
does not affect the master selection.
14.4 Initialization/application information
No initialization is required for the crossbar switch.
Chapter 14 Crossbar Switch Lite (AXBS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 225
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
226 NXP Semiconductors
Chapter 15
Memory Protection Unit (MPU)
15.1 Chip-specific MPU information
On this device, NXP's system MPU implements the safety mechanisms to prevent
masters from accessing restricted memory regions. This system MPU provides memory
protection at the level of the Crossbar Switch. Each Crossbar master (Core, DMA,
Ethernet) can be assigned different access rights to each protected memory region. The
Arm M4 and M0+ core version in this family does not integrate the Arm Core MPU,
which would concurrently monitor only core-initiated memory accesses. In this
document, the term MPU refers to NXP's system MPU.
15.1.1 MPU Slave Port Assignments
The memory-mapped resources protected by the MPU are:
Table 15-1. MPU Slave Port Assignments For S32K14x series
Source MPU Slave Port Assignment Destination
Crossbar slave port 0 MPU slave port 0 Flash Controller
Crossbar slave port 1 MPU slave port 1 SRAM backdoor
Code Bus MPU slave port 2 SRAM_L frontdoor
System Bus MPU slave port 3 SRAM_U frontdoor
Crossbar slave port 3 MPU Slave port 4 QuadSPI
Table 15-2. MPU Slave Port Assignments for S32K11x series
Source MPU Slave Port Assignment Destination
Crossbar slave port 0 MPU slave port 0 Flash Controller
Crossbar slave port 1 MPU slave port 1 SRAM controller/MTB_RAM/MCM
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 227
15.1.2 MPU Logical Bus Master Assignments
The logical bus master assignments for the MPU are:
Table 15-3. MPU Logical Bus Master Assignments
MPU
Logical
Bus
Master
ID
Bus
Master
Possible access types PID
avaialable
User Supervisor Data Instruction Read Write Execute
0 Core ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
1 Debugger ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
2 DMA - ✓ ✓ -✓ ✓ - -
3 ENET ✓-✓-✓ ✓ - -
4-7 Not implemented. The region descriptor register fields for these master IDs are Reserved.
15.1.3 Current PID
Current PID is configured at Miscellaneous Control Module Process ID register
(MCM_PID).
15.1.4 Region descriptors and slave port configuration
For each chip in the product series, the following table shows the numbers of region
descriptors and slave ports as well as the reset value of Control/Error Status Register
(CESR) that reflects those numbers.
Table 15-4. MPU configurations
Chips Region descriptors Slave ports CESR reset value
S32K116 8 2 0081_2001
S32K118 8 2 0081_2001
S32K142 8 4 0081_4001h
S32K144 8 4 0081_4001h
S32K146 8 4 0081_4001h
S32K148 16 5 0081_5201h
Chip-specific MPU information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
228 NXP Semiconductors
15.2 Introduction
The memory protection unit (MPU) provides hardware access control for all memory
references generated in the device.
15.3 Overview
The MPU concurrently monitors all system bus transactions and evaluates their
appropriateness using pre-programmed region descriptors that define memory spaces and
their access rights. Memory references that have sufficient access control rights are
allowed to complete, while references that are not mapped to any region descriptor or
have insufficient rights are terminated with a protection error response.
15.3.1 Block diagram
A simplified block diagram of the MPU module is shown in the following figure.
Slave Port n Internal
Region
Descriptor 0
Region
Descriptor 1
Region
Descriptor x
Access
Evaluation
Macro
Access
Evaluation
Macro
Access
Evaluation
Macro
Mux
Address Phase Signals Peripheral Bus
MPU_EARnMPU_EDRn
Figure 15-1. MPU block diagram
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 229
The hardware's two-dimensional connection matrix is clearly visible with the basic access
evaluation macro shown as the replicated submodule block. The crossbar switch slave
ports are shown on the left, the region descriptor registers in the middle, and the
peripheral bus interface on the right side. The evaluation macro contains two magnitude
comparators connected to the start and end address registers from each region descriptor
as well as the combinational logic blocks to determine the region hit and the access
protection error. For details of the access evaluation macro, see Access evaluation macro.
15.3.2 Features
The MPU implements a two-dimensional hardware array of memory region descriptors
and the crossbar slave ports to continuously monitor the legality of every memory
reference generated by each bus master in the system.
The feature set includes:
• 16 program-visible 128-bit region descriptors, accessible by four 32-bit words each
• Each region descriptor defines a modulo-32 byte space, aligned anywhere in
memory
• Region sizes can vary from 32 bytes to 4 Gbytes
• Two access control permissions defined in a single descriptor word
• Masters 0–3: read, write, and execute attributes for supervisor and user
accesses
• Masters 4–7: read and write attributes
• Hardware-assisted maintenance of the descriptor valid bit minimizes coherency
issues
• Alternate programming model view of the access control permissions word
• Priority given to granting permission over denying access for overlapping region
descriptors
• Detects access protection errors if a memory reference does not hit in any memory
region, or if the reference is illegal in all hit memory regions. If an access error
occurs, the reference is terminated with an error response, and the MPU inhibits the
bus cycle being sent to the targeted slave device.
Overview
S32K1xx Series Reference Manual, Rev. 7, 04/2018
230 NXP Semiconductors
• Error registers, per slave port, capture the last faulting address, attributes, and other
information
• Global MPU enable/disable control bit
15.4 MPU register descriptions
The programming model is partitioned into three groups:
• Control/status registers
• The data structure containing the region descriptors
• The alternate view of the region descriptor access control values
The programming model can be referenced using only 32-bit accesses. The programming
model can be accessed only in supervisor mode.
Attempted references of the following types generate an error termination:
• Non-32-bit references
• Accesses in user mode
• References to undefined—that is, reserved—addresses
• References with a non-supported access type, such as a write access to a read-only
register or a read access of a write-only register
15.4.1 MPU Memory map
MPU base address: 4000_D000h
Offset Register Width
(In bits)
Access Reset value
0h Control/Error Status Register (CESR) 32 RW 0081_5201h
10h Error Address Register, slave port 0 (EAR0) 32 RO 0000_0000h
14h Error Detail Register, slave port 0 (EDR0) 32 RO 0000_0000h
18h Error Address Register, slave port 1 (EAR1) 32 RO 0000_0000h
1Ch Error Detail Register, slave port 1 (EDR1) 32 RO 0000_0000h
20h Error Address Register, slave port 2 (EAR2) 32 RO 0000_0000h
24h Error Detail Register, slave port 2 (EDR2) 32 RO 0000_0000h
28h Error Address Register, slave port 3 (EAR3) 32 RO 0000_0000h
2Ch Error Detail Register, slave port 3 (EDR3) 32 RO 0000_0000h
Table continues on the next page...
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 231
Offset Register Width
(In bits)
Access Reset value
30h Error Address Register, slave port 4 (EAR4) 32 RO 0000_0000h
34h Error Detail Register, slave port 4 (EDR4) 32 RO 0000_0000h
400h Region Descriptor 0, Word 0 (RGD0_WORD0) 32 RW 0000_0000h
404h Region Descriptor 0, Word 1 (RGD0_WORD1) 32 RW FFFF_FFFFh
408h Region Descriptor 0, Word 2 (RGD0_WORD2) 32 RW 0061_F7DFh
40Ch Region Descriptor 0, Word 3 (RGD0_WORD3) 32 RW 0000_0001h
410h Region Descriptor 1, Word 0 (RGD1_WORD0) 32 RW 0000_0000h
414h Region Descriptor 1, Word 1 (RGD1_WORD1) 32 RW 0000_001Fh
418h Region Descriptor 1, Word 2 (RGD1_WORD2) 32 RW 0000_0000h
41Ch Region Descriptor 1, Word 3 (RGD1_WORD3) 32 RW 0000_0000h
420h Region Descriptor 2, Word 0 (RGD2_WORD0) 32 RW 0000_0000h
424h Region Descriptor 2, Word 1 (RGD2_WORD1) 32 RW 0000_001Fh
428h Region Descriptor 2, Word 2 (RGD2_WORD2) 32 RW 0000_0000h
42Ch Region Descriptor 2, Word 3 (RGD2_WORD3) 32 RW 0000_0000h
430h Region Descriptor 3, Word 0 (RGD3_WORD0) 32 RW 0000_0000h
434h Region Descriptor 3, Word 1 (RGD3_WORD1) 32 RW 0000_001Fh
438h Region Descriptor 3, Word 2 (RGD3_WORD2) 32 RW 0000_0000h
43Ch Region Descriptor 3, Word 3 (RGD3_WORD3) 32 RW 0000_0000h
440h Region Descriptor 4, Word 0 (RGD4_WORD0) 32 RW 0000_0000h
444h Region Descriptor 4, Word 1 (RGD4_WORD1) 32 RW 0000_001Fh
448h Region Descriptor 4, Word 2 (RGD4_WORD2) 32 RW 0000_0000h
44Ch Region Descriptor 4, Word 3 (RGD4_WORD3) 32 RW 0000_0000h
450h Region Descriptor 5, Word 0 (RGD5_WORD0) 32 RW 0000_0000h
454h Region Descriptor 5, Word 1 (RGD5_WORD1) 32 RW 0000_001Fh
458h Region Descriptor 5, Word 2 (RGD5_WORD2) 32 RW 0000_0000h
45Ch Region Descriptor 5, Word 3 (RGD5_WORD3) 32 RW 0000_0000h
460h Region Descriptor 6, Word 0 (RGD6_WORD0) 32 RW 0000_0000h
464h Region Descriptor 6, Word 1 (RGD6_WORD1) 32 RW 0000_001Fh
468h Region Descriptor 6, Word 2 (RGD6_WORD2) 32 RW 0000_0000h
46Ch Region Descriptor 6, Word 3 (RGD6_WORD3) 32 RW 0000_0000h
470h Region Descriptor 7, Word 0 (RGD7_WORD0) 32 RW 0000_0000h
474h Region Descriptor 7, Word 1 (RGD7_WORD1) 32 RW 0000_001Fh
478h Region Descriptor 7, Word 2 (RGD7_WORD2) 32 RW 0000_0000h
47Ch Region Descriptor 7, Word 3 (RGD7_WORD3) 32 RW 0000_0000h
480h Region Descriptor 8, Word 0 (RGD8_WORD0) 32 RW 0000_0000h
484h Region Descriptor 8, Word 1 (RGD8_WORD1) 32 RW 0000_001Fh
488h Region Descriptor 8, Word 2 (RGD8_WORD2) 32 RW 0000_0000h
48Ch Region Descriptor 8, Word 3 (RGD8_WORD3) 32 RW 0000_0000h
490h Region Descriptor 9, Word 0 (RGD9_WORD0) 32 RW 0000_0000h
494h Region Descriptor 9, Word 1 (RGD9_WORD1) 32 RW 0000_001Fh
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
232 NXP Semiconductors
Offset Register Width
(In bits)
Access Reset value
498h Region Descriptor 9, Word 2 (RGD9_WORD2) 32 RW 0000_0000h
49Ch Region Descriptor 9, Word 3 (RGD9_WORD3) 32 RW 0000_0000h
4A0h Region Descriptor 10, Word 0 (RGD10_WORD0) 32 RW 0000_0000h
4A4h Region Descriptor 10, Word 1 (RGD10_WORD1) 32 RW 0000_001Fh
4A8h Region Descriptor 10, Word 2 (RGD10_WORD2) 32 RW 0000_0000h
4ACh Region Descriptor 10, Word 3 (RGD10_WORD3) 32 RW 0000_0000h
4B0h Region Descriptor 11, Word 0 (RGD11_WORD0) 32 RW 0000_0000h
4B4h Region Descriptor 11, Word 1 (RGD11_WORD1) 32 RW 0000_001Fh
4B8h Region Descriptor 11, Word 2 (RGD11_WORD2) 32 RW 0000_0000h
4BCh Region Descriptor 11, Word 3 (RGD11_WORD3) 32 RW 0000_0000h
4C0h Region Descriptor 12, Word 0 (RGD12_WORD0) 32 RW 0000_0000h
4C4h Region Descriptor 12, Word 1 (RGD12_WORD1) 32 RW 0000_001Fh
4C8h Region Descriptor 12, Word 2 (RGD12_WORD2) 32 RW 0000_0000h
4CCh Region Descriptor 12, Word 3 (RGD12_WORD3) 32 RW 0000_0000h
4D0h Region Descriptor 13, Word 0 (RGD13_WORD0) 32 RW 0000_0000h
4D4h Region Descriptor 13, Word 1 (RGD13_WORD1) 32 RW 0000_001Fh
4D8h Region Descriptor 13, Word 2 (RGD13_WORD2) 32 RW 0000_0000h
4DCh Region Descriptor 13, Word 3 (RGD13_WORD3) 32 RW 0000_0000h
4E0h Region Descriptor 14, Word 0 (RGD14_WORD0) 32 RW 0000_0000h
4E4h Region Descriptor 14, Word 1 (RGD14_WORD1) 32 RW 0000_001Fh
4E8h Region Descriptor 14, Word 2 (RGD14_WORD2) 32 RW 0000_0000h
4ECh Region Descriptor 14, Word 3 (RGD14_WORD3) 32 RW 0000_0000h
4F0h Region Descriptor 15, Word 0 (RGD15_WORD0) 32 RW 0000_0000h
4F4h Region Descriptor 15, Word 1 (RGD15_WORD1) 32 RW 0000_001Fh
4F8h Region Descriptor 15, Word 2 (RGD15_WORD2) 32 RW 0000_0000h
4FCh Region Descriptor 15, Word 3 (RGD15_WORD3) 32 RW 0000_0000h
800h Region Descriptor Alternate Access Control 0 (RGDAAC0) 32 RW 0061_F7DFh
804h Region Descriptor Alternate Access Control 1 (RGDAAC1) 32 RW 0000_0000h
808h Region Descriptor Alternate Access Control 2 (RGDAAC2) 32 RW 0000_0000h
80Ch Region Descriptor Alternate Access Control 3 (RGDAAC3) 32 RW 0000_0000h
810h Region Descriptor Alternate Access Control 4 (RGDAAC4) 32 RW 0000_0000h
814h Region Descriptor Alternate Access Control 5 (RGDAAC5) 32 RW 0000_0000h
818h Region Descriptor Alternate Access Control 6 (RGDAAC6) 32 RW 0000_0000h
81Ch Region Descriptor Alternate Access Control 7 (RGDAAC7) 32 RW 0000_0000h
820h Region Descriptor Alternate Access Control 8 (RGDAAC8) 32 RW 0000_0000h
824h Region Descriptor Alternate Access Control 9 (RGDAAC9) 32 RW 0000_0000h
828h Region Descriptor Alternate Access Control 10 (RGDAAC10) 32 RW 0000_0000h
82Ch Region Descriptor Alternate Access Control 11 (RGDAAC11) 32 RW 0000_0000h
830h Region Descriptor Alternate Access Control 12 (RGDAAC12) 32 RW 0000_0000h
834h Region Descriptor Alternate Access Control 13 (RGDAAC13) 32 RW 0000_0000h
Table continues on the next page...
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 233
Offset Register Width
(In bits)
Access Reset value
838h Region Descriptor Alternate Access Control 14 (RGDAAC14) 32 RW 0000_0000h
83Ch Region Descriptor Alternate Access Control 15 (RGDAAC15) 32 RW 0000_0000h
15.4.2 Control/Error Status Register (CESR)
15.4.2.1 Offset
Register Offset
CESR 0h
15.4.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SPERR
0
SPERR
1
SPERR
2
SPERR
3
SPERR
4
0
0
0
1
0
HRL
W
W1C
W1C
W1C
W1C
W1C
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNSP NRGD 0VLD
W
Reset 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1
15.4.2.3 Fields
Field Function
31
SPERR0
Slave Port 0 Error
Indicates a captured error in EAR0 and EDR0. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 0.
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
234 NXP Semiconductors
Field Function
1b - An error has occurred for slave port 0.
30
SPERR1
Slave Port 1 Error
Indicates a captured error in EAR1 and EDR1. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 1.
1b - An error has occurred for slave port 1.
29
SPERR2
Slave Port 2 Error
Indicates a captured error in EAR2 and EDR2. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 2.
1b - An error has occurred for slave port 2.
28
SPERR3
Slave Port 3 Error
Indicates a captured error in EAR3 and EDR3. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 3.
1b - An error has occurred for slave port 3.
27
SPERR4
Slave Port 4 Error
Indicates a captured error in EAR4 and EDR4. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 4.
1b - An error has occurred for slave port 4.
26
—
Reserved
25
—
Reserved
24
—
Reserved
23
—
Reserved
22-20
—
Reserved
19-16
HRL
Hardware Revision Level
Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the
functional definition of the module.
15-12
NSP
Number Of Slave Ports
Specifies the number of slave ports connected to the MPU.
11-8 Number Of Region Descriptors
Table continues on the next page...
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 235
Field Function
NRGD Indicates the number of region descriptors implemented in the MPU.
0000b - 8 region descriptors
0001b - 12 region descriptors
0010b - 16 region descriptors
7-1
—
Reserved
0
VLD
Valid
Global enable/disable for the MPU.
0b - MPU is disabled. All accesses from all bus masters are allowed.
1b - MPU is enabled
15.4.3 Error Address Register, slave port n (EAR0 - EAR4)
15.4.3.1 Offset
Register Offset
EAR0 10h
EAR1 18h
EAR2 20h
EAR3 28h
EAR4 30h
15.4.3.2 Function
When the MPU detects an access error on slave port n, the 32-bit reference address is
captured in this read-only register and the corresponding bit in CESR[SPERRn] is set.
Additional information about the faulting access is captured in the corresponding EDRn
at the same time. This register and the corresponding EDRn contain the most recent
access error; there are no hardware interlocks with CESR[SPERRn], as the error registers
are always loaded upon the occurrence of each protection violation.
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
236 NXP Semiconductors
15.4.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.4.3.4 Fields
Field Function
31-0
EADDR
Error Address
Indicates the reference address from slave port n that generated the access error
15.4.4 Error Detail Register, slave port n (EDR0 - EDR4)
15.4.4.1 Offset
Register Offset
EDR0 14h
EDR1 1Ch
EDR2 24h
EDR3 2Ch
EDR4 34h
15.4.4.2 Function
When the MPU detects an access error on slave port n, 32 bits of error detail are captured
in this read-only register and the corresponding bit in CESR[SPERRn] is set. Information
on the faulting address is captured in the corresponding EARn register at the same time.
This register and the corresponding EARn register contain the most recent access error;
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 237
there are no hardware interlocks with CESR[SPERRn] as the error registers are always
loaded upon the occurrence of each protection violation.
15.4.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPID EMN EATTR ERW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.4.4.4 Fields
Field Function
31-16
EACD
Error Access Control Detail
Indicates the region descriptor with the access error.
• If EDRn contains a captured error and EACD is cleared, an access did not hit in any region
descriptor.
• If only a single EACD bit is set, the protection error was caused by a single non-overlapping region
descriptor.
• If two or more EACD bits are set, the protection error was caused by an overlapping set of region
descriptors.
15-8
EPID
Error Process Identification
Records the process identifier of the faulting reference. The process identifier is typically driven only by
processor cores; for other bus masters, this field is cleared.
7-4
EMN
Error Master Number
Indicates the bus master that generated the access error.
3-1
EATTR
Error Attributes
Indicates attribute information about the faulting reference.
NOTE: All other encodings are reserved.
000b - User mode, instruction access
001b - User mode, data access
010b - Supervisor mode, instruction access
011b - Supervisor mode, data access
0
ERW
Error Read/Write
Indicates the access type of the faulting reference.
0b - Read
1b - Write
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
238 NXP Semiconductors
15.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WO
RD0)
15.4.5.1 Offset
For n = 0 to 15:
Register Offset
RGDn_WORD0 400h + (n × 10h)
15.4.5.2 Function
The first word of the region descriptor defines the 0-modulo-32 byte start address of the
memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
15.4.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRTADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRTADDR 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.4.5.4 Fields
Field Function
31-5
SRTADDR
Start Address
Defines the most significant bits of the 0-modulo-32 byte start address of the memory region.
4-0
—
Reserved
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 239
15.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)
15.4.6.1 Offset
Register Offset
RGD0_WORD1 404h
15.4.6.2 Function
The second word of the region descriptor defines the 31-modulo-32 byte end address of
the memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
15.4.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RENDADDR
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RENDADDR Reserved
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15.4.6.4 Fields
Field Function
31-5
ENDADDR
End Address
Defines the most significant bits of the 31-modulo-32 byte end address of the memory region.
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.
4-0
—
Reserved
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
240 NXP Semiconductors
15.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)
15.4.7.1 Offset
Register Offset
RGD0_WORD2 408h
15.4.7.2 Function
The third word of the region descriptor defines the access control rights of the memory
region. The access control privileges depend on two broad classifications of bus masters:
• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and
supervisor mode accesses. Each of these bus masters optionally includes a process
identification field (if implemented for the master) within the definition.
• Bus masters 4–7 are limited to separate read and write permissions.
For the privilege rights of bus masters 0–3, there are three flags associated with this
function:
• Read (r) refers to accessing the referenced memory address using an operand (data)
fetch
• Write (w) refers to updating the referenced memory address using a store (data)
instruction
• Execute (x) refers to reading the referenced memory address using an instruction
fetch
Writes to RGDn_WORD2 clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn
instead because stores to these locations do not affect the descriptor’s valid bit.
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 241
15.4.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
M7RE
M7WE
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
Reserved
M3SM
M3UM
Reserved
M2SM
W
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
M2SM
M2UM
M1PE
M1SM
M1UM
M0PE
M0SM
M0UM
W
Reset 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
15.4.7.4 Fields
Field Function
31
M7RE
Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
1b - Bus master 7 reads allowed
30
M7WE
Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
1b - Bus master 7 writes allowed
29
M6RE
Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
1b - Bus master 6 reads allowed
28
M6WE
Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
1b - Bus master 6 writes allowed
27
M5RE
Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
1b - Bus master 5 reads allowed
26
M5WE
Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
1b - Bus master 5 writes allowed
25
M4RE
Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
1b - Bus master 4 reads allowed
24
M4WE
Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
1b - Bus master 4 writes allowed
23
—
Reserved
This bit must be written with a zero.
22-21 Bus Master 3 Supervisor Mode Access Control
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
242 NXP Semiconductors
Field Function
M3SM Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18
M3UM
Bus Master 3 User Mode Access Control
Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17
—
Reserved
This bit must be written with a zero.
16-15
M2SM
Bus Master 2 Supervisor Mode Access Control
Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12
M2UM
Bus Master 2 User Mode Access control
Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11
M1PE
Bus Master 1 Process Identifier enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9
M1SM
Bus Master 1 Supervisor Mode Access Control
Defines the access controls for bus master 1 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6
M1UM
Bus Master 1 User Mode Access Control
Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
5
M0PE
Bus Master 0 Process Identifier enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3 Bus Master 0 Supervisor Mode Access Control
Table continues on the next page...
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 243
Field Function
M0SM Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0
M0UM
Bus Master 0 User Mode Access Control
Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
15.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)
15.4.8.1 Offset
Register Offset
RGD0_WORD3 40Ch
15.4.8.2 Function
The fourth word of the region descriptor contains the optional process identifier and
mask, plus the region descriptor’s valid bit.
15.4.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPID PIDMASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 VLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
244 NXP Semiconductors
15.4.8.4 Fields
Field Function
31-24
PID
Process Identifier
Specifies the process identifier that is included in the region hit determination if RGDn_WORD2[MxPE] is
set. PIDMASK can mask individual bits in this field.
23-16
PIDMASK
Process Identifier Mask
Provides a masking capability so that multiple process identifiers can be included as part of the region hit
determination. If a bit in PIDMASK is set, then the corresponding PID bit is ignored in the comparison.
This field and PID are included in the region hit determination if RGDn_WORD2[MxPE] is set. For more
information on the handling of the PID and PIDMASK, see “Access Evaluation - Hit Determination.”
15-1
—
Reserved
0
VLD
Valid
Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit.
0b - Region descriptor is invalid
1b - Region descriptor is valid
15.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WO
RD1)
15.4.9.1 Offset
For n = 1 to 15:
Register Offset
RGDn_WORD1 404h + (n × 10h)
15.4.9.2 Function
The second word of the region descriptor defines the 31-modulo-32 byte end address of
the memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 245
15.4.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RENDADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RENDADDR Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
15.4.9.4 Fields
Field Function
31-5
ENDADDR
End Address
Defines the most significant bits of the 31-modulo-32 byte end address of the memory region.
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.
4-0
—
Reserved
15.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_
WORD2)
15.4.10.1 Offset
For n = 1 to 15:
Register Offset
RGDn_WORD2 408h + (n × 10h)
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
246 NXP Semiconductors
15.4.10.2 Function
The third word of the region descriptor defines the access control rights of the memory
region. The access control privileges depend on two broad classifications of bus masters:
• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and
supervisor mode accesses. Each of these bus masters optionally includes a process
identification field (if implemented for the master) within the definition.
• Bus masters 4–7 are limited to separate read and write permissions.
For the privilege rights of bus masters 0–3, there are three flags associated with this
function:
• Read (r) refers to accessing the referenced memory address using an operand (data)
fetch
• Write (w) refers to updating the referenced memory address using a store (data)
instruction
• Execute (x) refers to reading the referenced memory address using an instruction
fetch
Writes to RGDn_WORD2 clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn
instead because stores to these locations do not affect the descriptor’s valid bit.
15.4.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
M7RE
M7WE
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
Reserved
M3SM
M3UM
Reserved
M2SM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
M2SM
M2UM
M1PE
M1SM
M1UM
M0PE
M0SM
M0UM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 247
15.4.10.4 Fields
Field Function
31
M7RE
Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
1b - Bus master 7 reads allowed
30
M7WE
Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
1b - Bus master 7 writes allowed
29
M6RE
Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
1b - Bus master 6 reads allowed
28
M6WE
Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
1b - Bus master 6 writes allowed
27
M5RE
Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
1b - Bus master 5 reads allowed
26
M5WE
Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
1b - Bus master 5 writes allowed
25
M4RE
Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
1b - Bus master 4 reads allowed
24
M4WE
Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
1b - Bus master 4 writes allowed
23
—
Reserved
This bit must be written with a zero.
22-21
M3SM
Bus Master 3 Supervisor Mode Access Control
Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18
M3UM
Bus Master 3 User Mode Access Control
Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17
—
Reserved
This bit must be written with a zero.
16-15
M2SM
Bus Master 2 Supervisor Mode Access Control
Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
248 NXP Semiconductors
Field Function
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12
M2UM
Bus Master 2 User Mode Access control
Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11
M1PE
Bus Master 1 Process Identifier enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9
M1SM
Bus Master 1 Supervisor Mode Access Control
Defines the access controls for bus master 1 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6
M1UM
Bus Master 1 User Mode Access Control
Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
5
M0PE
Bus Master 0 Process Identifier enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3
M0SM
Bus Master 0 Supervisor Mode Access Control
Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0
M0UM
Bus Master 0 User Mode Access Control
Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 249
15.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_
WORD3)
15.4.11.1 Offset
For n = 1 to 15:
Register Offset
RGDn_WORD3 40Ch + (n × 10h)
15.4.11.2 Function
The fourth word of the region descriptor contains the optional process identifier and
mask, plus the region descriptor’s valid bit.
15.4.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPID PIDMASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 VLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.4.11.4 Fields
Field Function
31-24
PID
Process Identifier
Specifies the process identifier that is included in the region hit determination if RGDn_WORD2[MxPE] is
set. PIDMASK can mask individual bits in this field.
23-16
PIDMASK
Process Identifier Mask
Provides a masking capability so that multiple process identifiers can be included as part of the region hit
determination. If a bit in PIDMASK is set, then the corresponding PID bit is ignored in the comparison.
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
250 NXP Semiconductors
Field Function
This field and PID are included in the region hit determination if RGDn_WORD2[MxPE] is set. For more
information on the handling of the PID and PIDMASK, see “Access Evaluation - Hit Determination.”
15-1
—
Reserved
0
VLD
Valid
Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit.
0b - Region descriptor is invalid
1b - Region descriptor is valid
15.4.12 Region Descriptor Alternate Access Control 0 (RGDA
AC0)
15.4.12.1 Offset
Register Offset
RGDAAC0 800h
15.4.12.2 Function
Because software may adjust only the access controls within a region descriptor
(RGDn_WORD2) as different tasks execute, an alternate programming view of this 32-
bit entity is available. Writing to this register does not affect the descriptor’s valid bit.
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 251
15.4.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
M7RE
M7WE
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
Reserved
M3SM
M3UM
Reserved
M2SM
W
Reset
10 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
M2SM
M2UM
M1PE
M1SM
M1UM
M0PE
M0SM
M0UM
W
Reset 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
1. RGDAAC0 resets to 61F7DFh. Other RGDAACn registers reset to 0h.
15.4.12.4 Fields
Field Function
31
M7RE
Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
1b - Bus master 7 reads allowed
30
M7WE
Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
1b - Bus master 7 writes allowed
29
M6RE
Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
1b - Bus master 6 reads allowed
28
M6WE
Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
1b - Bus master 6 writes allowed
27
M5RE
Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
1b - Bus master 5 reads allowed
26
M5WE
Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
1b - Bus master 5 writes allowed
25
M4RE
Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
1b - Bus master 4 reads allowed
24
M4WE
Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
1b - Bus master 4 writes allowed
23
—
Reserved
This bit must be written with a zero.
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
252 NXP Semiconductors
Field Function
22-21
M3SM
Bus Master 3 Supervisor Mode Access Control
Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18
M3UM
Bus Master 3 User Mode Access Control
Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17
—
Reserved
This bit must be written with a zero.
16-15
M2SM
Bus Master 2 Supervisor Mode Access Control
Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12
M2UM
Bus Master 2 User Mode Access Control
Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11
M1PE
Bus Master 1 Process Identifier Enable
NOTE: For RGDAAC0: Only bus master 1 can write to M1PE.
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9
M1SM
Bus Master 1 Supervisor Mode Access Control
Defines the access controls for bus master 1 in Supervisor mode.
NOTE: For RGDAAC0: Only bus master 1 can write to M1SM.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6
M1UM
Bus Master 1 User Mode Access Control
Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions.
NOTE: For RGDAAC0: Only bus master 1 can write to M1UM.
For each bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
Table continues on the next page...
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 253
Field Function
1b - Allows the given access type to occur
5
M0PE
Bus Master 0 Process Identifier Enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3
M0SM
Bus Master 0 Supervisor Mode Access Control
Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0
M0UM
Bus Master 0 User Mode Access Control
Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
15.4.13 Region Descriptor Alternate Access Control n (RGDA
AC1 - RGDAAC15)
15.4.13.1 Offset
For n = 1 to 15:
Register Offset
RGDAACn 800h + (n × 4h)
15.4.13.2 Function
Because software may adjust only the access controls within a region descriptor
(RGDn_WORD2) as different tasks execute, an alternate programming view of this 32-
bit entity is available. Writing to this register does not affect the descriptor’s valid bit.
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
254 NXP Semiconductors
15.4.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
M7RE
M7WE
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
Reserved
M3SM
M3UM
Reserved
M2SM
W
Reset
10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
M2SM
M2UM
M1PE
M1SM
M1UM
M0PE
M0SM
M0UM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1. RGDAAC0 resets to 61F7DFh. Other RGDAACn registers reset to 0h.
15.4.13.4 Fields
Field Function
31
M7RE
Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
1b - Bus master 7 reads allowed
30
M7WE
Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
1b - Bus master 7 writes allowed
29
M6RE
Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
1b - Bus master 6 reads allowed
28
M6WE
Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
1b - Bus master 6 writes allowed
27
M5RE
Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
1b - Bus master 5 reads allowed
26
M5WE
Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
1b - Bus master 5 writes allowed
25
M4RE
Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
1b - Bus master 4 reads allowed
24
M4WE
Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
1b - Bus master 4 writes allowed
23
—
Reserved
This bit must be written with a zero.
Table continues on the next page...
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 255
Field Function
22-21
M3SM
Bus Master 3 Supervisor Mode Access Control
Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18
M3UM
Bus Master 3 User Mode Access Control
Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17
—
Reserved
This bit must be written with a zero.
16-15
M2SM
Bus Master 2 Supervisor Mode Access Control
Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12
M2UM
Bus Master 2 User Mode Access Control
Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11
M1PE
Bus Master 1 Process Identifier Enable
NOTE: For RGDAAC0: Only bus master 1 can write to M1PE.
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9
M1SM
Bus Master 1 Supervisor Mode Access Control
Defines the access controls for bus master 1 in Supervisor mode.
NOTE: For RGDAAC0: Only bus master 1 can write to M1SM.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6
M1UM
Bus Master 1 User Mode Access Control
Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions.
NOTE: For RGDAAC0: Only bus master 1 can write to M1UM.
For each bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
Table continues on the next page...
MPU register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
256 NXP Semiconductors
Field Function
1b - Allows the given access type to occur
5
M0PE
Bus Master 0 Process Identifier Enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3
M0SM
Bus Master 0 Supervisor Mode Access Control
Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0
M0UM
Bus Master 0 User Mode Access Control
Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
15.5 Functional description
In this section, the functional operation of the MPU is detailed, including the operation of
the access evaluation macro and the handling of error-terminated bus cycles.
15.5.1 Access evaluation macro
The basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in the following
figure, the access evaluation macro inputs the crossbar bus address phase signals and the
contents of a region descriptor (RGDn) and performs two major functions:
• Region hit determination
• Detection of an access protection violation
The following figure shows a functional block diagram.
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 257
start end
error
≥ ≥
RGDn
MPU_EDRnAccess not allowed
≥ ≤
hit_b
Address
(hit AND error) (no hit OR error)
r,w,x
Figure 15-2. MPU access evaluation macro
15.5.1.1 Hit determination
To determine whether the current reference hits in the given region, two magnitude
comparators are used with the region's start and end addresses. The boolean equation for
this portion of the hit determination is:
region_hit = ((addr[31:5] >= RGDn_Word0[SRTADDR]) & (addr[31:5] <= RGDn_Word1[ENDADDR])) &
RGDn_Word3[VLD]
where addr is the current reference address, RGDn_Word0[SRTADDR] and
RGDn_Word1[ENDADDR] are the start and end addresses, and RGDn_Word3[VLD] is
the valid bit.
NOTE
The MPU does not verify that ENDADDR ≥ SRTADDR.
In addition to the comparison of the reference address versus the region descriptor's start
and end addresses, the optional process identifier is examined against the region
descriptor's PID and PIDMASK fields. A process identifier hit term is formed as follows:
pid_hit = ~RGDn_Word2[MxPE] |
((current_pid |
RGDn_Word3[PIDMASK]) == (RGDn_Word3[PID] | RGDn_Word3[PIDMASK]))
where the current_pid is the selected process identifier from the current bus master, and
RGDn_Word3[PID] and RGDn_Word3[PIDMASK] are the process identifier fields from
region descriptor n. For bus masters that do not output a process identifier, the MPU
forces the pid_hit term to assert.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
258 NXP Semiconductors
15.5.1.2 Privilege violation determination
While the access evaluation macro is determining region hit, the logic is also evaluating
if the current access is allowed by the permissions defined in the region descriptor. Using
the master and supervisor/user mode signals, a set of effective permissions is generated
from the appropriate fields in the region descriptor. The protection violation logic then
evaluates the access against the effective permissions as shown in the following table.
Table 15-5. Protection violation definition
Description MxUM Protection violation?
r w x
Instruction fetch read — — 0 Yes, no execute permission
— — 1 No, access is allowed
Data read 0 — — Yes, no read permission
1 — — No, access is allowed
Data write — 0 — Yes, no write permission
— 1 — No, access is allowed
15.5.2 Putting it all together and error terminations
For each slave port monitored, the MPU performs a reduction-AND of all the individual
terms from each access evaluation macro. This expression then terminates the bus cycle
with an error and reports a protection error for three conditions:
• If the access does not hit in any region descriptor, a protection error is reported.
• If the access hits in a single region descriptor and that region signals a protection
violation, a protection error is reported.
• If the access hits in multiple (overlapping) regions and all regions signal protection
violations, a protection error is reported.
As shown in the third condition, granting permission is a higher priority than denying
access for overlapping regions. This approach is more flexible to system software in
region descriptor assignments. For an example of the use of overlapping region
descriptors, see Application information.
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 259
15.5.3 Power management
Disabling the MPU by clearing CESR[VLD] minimizes power dissipation. To minimize
the power dissipation of an enabled MPU, invalidate unused region descriptors by
clearing the associated RGDn_Word3[VLD] bits.
15.6 Initialization information
At system startup, load the appropriate number of region descriptors, including setting
RGDn_Word3[VLD]. Setting CESR[VLD] enables the module.
If the system requires that all the loaded region descriptors be enabled simultaneously,
first ensure that the entire MPU is disabled (CESR[VLD]=0).
Note
If the MPU registers are protected by the MPU, a region
descriptor must be set to allow access to the MPU registers if
further changes are needed.
15.7 Application information
In an operational system, interfacing with the MPU is generally classified into the
following activities:
• Creating a new memory region—Load the appropriate region descriptor into an
available RGDn, using four sequential 32-bit writes. The hardware assists in the
maintenance of the valid bit, so if this approach is followed, there are no coherency
issues with the multi-cycle descriptor writes. (Clearing RGDn_Word3[VLD] deletes/
removes an existing memory region.)
• Altering only access privileges—To not affect the valid bit, write to the alternate
version of the access control word (RGDAACn), so there are no coherency issues
involved with the update. When the write completes, the memory region's access
rights switch instantaneously to the new value.
• Changing a region's start and end addresses—Write a minimum of three words to the
region descriptor (RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end
addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most
situations, all four words of the region descriptor are rewritten.
Initialization information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
260 NXP Semiconductors
• Accessing the MPU—Allocate a region descriptor to restrict MPU access to
supervisor mode from a specific master.
• Detecting an access error—The current bus cycle is terminated with an error
response and EARn and EDRn capture information on the faulting reference. The
error-terminated bus cycle typically initiates an error response in the originating bus
master. For example, a processor core may respond with a bus error exception, while
a data movement bus master may respond with an error interrupt. The processor can
retrieve the captured error address and detail information simply by reading
E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data.
• Overlapping region descriptors—Applying overlapping regions often reduces the
number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are
logically summed together (the boolean OR operator).
The following dual-core system example contains four bus masters:
• The two processors: CP0, CP1
• Two DMA engines: DMA1, a traditional data movement engine transferring data
between RAM and peripherals and DMA2, a second engine transferring data to/
from the RAM only
Consider the following region descriptor assignments:
Table 15-6. Overlapping region descriptor example
Region description RGDn CP0 CP1 DMA1 DMA2
CP0 code 0 rwx r-- — — Flash
CP1 code 1 r-- rwx — —
CP0 data & stack 2 rw- — — —
RAM
CP0 → CP1 shared data 2 3 r-- r-- — —
CP1 → CP0 shared data 4
CP1 data & stack 4 — rw- — —
Shared DMA data 5 rw- rw- rw rw
MPU 6 rw- rw- — — Peripheral
space
Peripherals 7 rw- rw- rw —
In this example, there are eight descriptors used to span nine regions in the three main
spaces of the system memory map: flash, RAM, and peripheral space. Each region
indicates the specific permissions for each of the four bus masters and this definition
provides an appropriate set of shared, private and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4.
Chapter 15 Memory Protection Unit (MPU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 261
The space defined by RGD2 with no overlap is a private data and stack area that provides
read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines
a shared data space for passing data from CP0 to CP1 and the access controls are defined
by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-)
permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines
are excluded from this shared processor data region. The overlapping spaces between
RGD3 and RGD4 defines another shared data space, this one for passing data from CP1
to CP0. For this overlapping space, CP0 has (r-- | ---) = (r--) permission, while CP1 has
(rw- | r--) = (rw-) permission. The non-overlapped space of RGD4 defines a private data
and stack area for CP1 only.
The space defined by RGD5 is a shared data region, accessible by all four bus masters.
Finally, the slave peripheral space mapped onto the IPS bus is partitioned into two
regions:
• One containing the MPU's programming model accessible only to the two processor
cores
• The remaining peripheral region accessible to both processors and the traditional
DMA1 master
This example shows one possible application of the capabilities of the MPU in a typical
system.
Application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
262 NXP Semiconductors
Chapter 16
Peripheral Bridge (AIPS-Lite)
Chip-specific AIPS information
16.1.1 Instantiation information
This device contains one peripheral bridge. The peripheral access protection is supported
by AIPS. The MPU will not cover peripheral access protection.
16.1.2 Memory maps
The peripheral bridge is used to access the registers of most of the modules on this
device. See S32K1xx_memory_map.xlsx attached to Reference Manual for the memory
slot assignment.
AIPS_PACR0 – PACR31 refer to on platform peripherals with corresponding AIPS
Peripheral bridge slot numbers from 0 -31. AIPS_OPACR0 – OPACR95 refer to off
platform peripherals with corresponding AIPS Peripheral bridge slot numbers from 32
-127. For logical master ID assignments see MPU Logical Bus Master Assignments.
16.1.2.1 Register reset values
The following table shows chip-specific reset values for AIPS registers:
Table 16-1. Register reset values
Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
MPRA 7770_0000 7770_0000 7770_0000 7770_0000 7770_0000 7777_0000
PACRA 5400_0000 5400_0000 5400_0000 5400_0000 5400_0000 5400_0000
PACRB 4400_0404 4400_0404 4400_0400 4400_0400 4400_0400 4400_0400
PACRD 4400_0000 4400_0000 4400_0000 4400_0000 4400_0000 4400_0000
Table continues on the next page...
16.1
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 263
Table 16-1. Register reset values (continued)
Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
OPACRA 4400_4000 4400_4000 4400_4444 4400_4444 4400_4444 4400_4444
OPACRB 0000_4000 0000_4400 0000_4400 0000_4400 0000_4400 0004_4440
OPACRC 0040_0044 0040_0044 0440_0044 0440_0044 0440_0044 0440_0044
OPACRD 4404_0444 4404_0444 4444_0400 4444_0400 4444_0400 4444_0400
OPACRE 4000_0040 4000_0040 4000_0040 4000_0040 4000_0040 4000_0040
OPACRF 4444_4400 4444_4400 4444_4400 4444_4400 4444_4400 4444_4400
OPACRG 0040_0000 0040_0000 0040_0000 0040_0000 0040_0000 0040_4400
OPACRH 0040_0000 0040_0000 0040_0000 0040_0000 0040_0000 0040_0000
OPACRI 0004_4440 0004_4440 0404_4440 0404_4440 0404_4440 0404_4444
OPACRJ 0044_0000 0044_0000 0044_0000 0044_0000 0044_4044 0044_4044
OPACRK 0004_0000 0004_0000 0004_0000 0004_0000 0004_0000 4404_0040
OPACRL 0000_0444 0000_0444 0000_0444 0000_0444 0000_0444 0400_0444
16.1.2.2 Register information
In S32K11x, CMU0 and CMU1 reside on Off-platform slots 30 and 31 respectively, and
access of the same is controlled by bits OPACRD[0:7] shown below. In S32K14x these
bits are Reserved as show in AIPS register descriptions.
Table 16-2. OPARCD register
Bit
fields
S32K14x S32K11x
Bitfiled[0:
7]
Reserved Bit 0: TP7 (Trusted Protect 7)
Bit 1: WP7 (Write Protect 7)
Bit 2: SP7 (Supervisor Protect 7)
Bit 3: Reserved
Bit 4: TP6 (Trusted Protect 6)
Bit 5: WP6 (Write Protect 6)
Bit 6: SP6 (Supervisor Protect 6)
Bit 7: Reserved
16.2 Introduction
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
264 NXP Semiconductors
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
16.2.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
• Programming model provides memory protection functionality
16.2.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map.
16.3 Memory map/register definition
The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted
bus masters. Additionally, these registers must be read from or written to only by a 32-bit
aligned access. The peripheral bridge registers are mapped into the Peripheral Access
Control Register A PACRA[PACR0] address space.
16.3.1 AIPS register descriptions
16.3.1.1 AIPS Memory map
AIPS_Lite base address: 4000_0000h
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 265
Offset Register Width
(In bits)
Access Reset value
0h Master Privilege Register A (MPRA) 32 RW 2C36_0000h
20h Peripheral Access Control Register (PACRA) 32 RW 5400_0000h
24h Peripheral Access Control Register (PACRB) 32 RW 4400_0400h
2Ch Peripheral Access Control Register (PACRD) 32 RW 4400_0000h
40h Off-Platform Peripheral Access Control Register (OPACRA) 32 RW 4400_4444h
44h Off-Platform Peripheral Access Control Register (OPACRB) 32 RW 0004_4440h
48h Off-Platform Peripheral Access Control Register (OPACRC) 32 RW 0440_0044h
4Ch Off-Platform Peripheral Access Control Register (OPACRD) 32 RW 4444_0400h
50h Off-Platform Peripheral Access Control Register (OPACRE) 32 RW 4000_0040h
54h Off-Platform Peripheral Access Control Register (OPACRF) 32 RW 4444_4400h
58h Off-Platform Peripheral Access Control Register (OPACRG) 32 RW 0040_4400h
5Ch Off-Platform Peripheral Access Control Register (OPACRH) 32 RW 0040_0000h
60h Off-Platform Peripheral Access Control Register (OPACRI) 32 RW 0404_4444h
64h Off-Platform Peripheral Access Control Register (OPACRJ) 32 RW 0044_4044h
68h Off-Platform Peripheral Access Control Register (OPACRK) 32 RW 4404_0040h
6Ch Off-Platform Peripheral Access Control Register (OPACRL) 32 RW 0400_0444h
16.3.1.2 Master Privilege Register A (MPRA)
16.3.1.2.1 Offset
Register Offset
MPRA 0h
16.3.1.2.2 Function
The MPRA specifies identical 4-bit fields defining the access-privilege level associated
with a bus master to various peripherals on the chip. The register provides one field per
bus master.
A register field that maps to an unimplemented master or peripheral behaves as read-
only-zero.
Each master is assigned a logical ID from 0 to 15. See the master logical ID assignment
table in the chip-specific AIPS information.
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
266 NXP Semiconductors
16.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
MTR0
MTW0
MPL0
0
MTR1
MTW1
MPL1
0
MTR2
MTW2
MPL2
0
MTR3
MTW3
MPL3
W
Reset 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 Reserved 0Reserved 0Reserved 0Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.3.1.2.4 Fields
Field Function
31
—
Reserved
30
MTR0
Master 0 Trusted For Read
Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
29
MTW0
Master 0 Trusted For Writes
Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
28
MPL0
Master 0 Privilege Level
Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
27
—
Reserved
26
MTR1
Master 1 Trusted for Read
Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
25
MTW1
Master 1 Trusted for Writes
Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
24
MPL1
Master 1 Privilege Level
Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 267
Field Function
23
—
Reserved
22
MTR2
Master 2 Trusted For Read
Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
21
MTW2
Master 2 Trusted For Writes
Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
20
MPL2
Master 2 Privilege Level
Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
19
—
Reserved
18
MTR3
Master 3 Trusted For Read
Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
17
MTW3
Master 3 Trusted For Writes
Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
16
MPL3
Master 3 Privilege Level
Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
15
—
Reserved
14-12
—
Reserved
11
—
Reserved
10-8
—
Reserved
7
—
Reserved
6-4
—
Reserved
3
—
Reserved
2-0 Reserved
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
268 NXP Semiconductors
Field Function
—
16.3.1.3 Peripheral Access Control Register (PACRA)
16.3.1.3.1 Offset
Register Offset
PACRA 20h
16.3.1.3.2 Function
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular on-platform peripheral. The peripheral assignment to each
PACR field is defined by the memory map slot of the peripheral. See the chip-specific
AIPS information for the field assignment of a particular peripheral.
Every PACR field to which no peripheral is assigned is reserved. Reads to reserved
locations return zeros, and writes are ignored.
16.3.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0 0
W
Reset 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.3.1.3.4 Fields
Field Function
31 Reserved
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 269
Field Function
—
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19-16
—
Reserved
15-12
—
Reserved
11-8 Reserved
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
270 NXP Semiconductors
Field Function
—
7-4
—
Reserved
3-0
—
Reserved
16.3.1.4 Peripheral Access Control Register (PACRB)
16.3.1.4.1 Offset
Register Offset
PACRB 24h
16.3.1.4.2 Function
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular on-platform peripheral. The peripheral assignment to each
PACR field is defined by the memory map slot of the peripheral. See the chip-specific
AIPS information for the field assignment of a particular peripheral.
Every PACR field to which no peripheral is assigned is reserved. Reads to reserved
locations return zeros, and writes are ignored.
16.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0 0
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 SP5 WP5 TP5 0 0
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 271
16.3.1.4.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19-16
—
Reserved
15-12 Reserved
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
272 NXP Semiconductors
Field Function
—
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4
—
Reserved
3-0
—
Reserved
16.3.1.5 Peripheral Access Control Register (PACRD)
16.3.1.5.1 Offset
Register Offset
PACRD 2Ch
16.3.1.5.2 Function
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular on-platform peripheral. The peripheral assignment to each
PACR field is defined by the memory map slot of the peripheral. See the chip-specific
AIPS information for the field assignment of a particular peripheral.
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 273
Every PACR field to which no peripheral is assigned is reserved. Reads to reserved
locations return zeros, and writes are ignored.
16.3.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0 0
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.3.1.5.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
26
SP1
Supervisor Protect
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
274 NXP Semiconductors
Field Function
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19-16
—
Reserved
15-12
—
Reserved
11-8
—
Reserved
7-4
—
Reserved
3-0
—
Reserved
16.3.1.6 Off-Platform Peripheral Access Control Register (OPACRA)
16.3.1.6.1 Offset
Register Offset
OPACRA 40h
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 275
16.3.1.6.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0 0
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SP4 WP4 TP4 0SP5 WP5 TP5 0SP6 WP6 TP6 0SP7 WP7 TP7
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
16.3.1.6.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
276 NXP Semiconductors
Field Function
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19-16
—
Reserved
15
—
Reserved
14
SP4
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13
WP4
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12
TP4
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11
—
Reserved
10
SP5
Supervisor Protect
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 277
Field Function
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3
—
Reserved
2
SP7
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1
WP7
Write Protect
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
278 NXP Semiconductors
Field Function
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0
TP7
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
16.3.1.7 Off-Platform Peripheral Access Control Register (OPACRB)
16.3.1.7.1 Offset
Register Offset
OPACRB 44h
16.3.1.7.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 SP3 WP3 TP3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SP4 WP4 TP4 0SP5 WP5 TP5 0SP6 WP6 TP6 0
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 279
16.3.1.7.4 Fields
Field Function
31-28
—
Reserved
27-24
—
Reserved
23-20
—
Reserved
19
—
Reserved
18
SP3
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17
WP3
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15
—
Reserved
14
SP4
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13
WP4
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12
TP4
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
280 NXP Semiconductors
Field Function
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3-0
—
Reserved
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 281
16.3.1.8 Off-Platform Peripheral Access Control Register (OPACRC)
16.3.1.8.1 Offset
Register Offset
OPACRC 48h
16.3.1.8.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 SP1 WP1 TP1 0SP2 WP2 TP2 0
W
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SP6 WP6 TP6 0SP7 WP7 TP7
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
16.3.1.8.4 Fields
Field Function
31-28
—
Reserved
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
282 NXP Semiconductors
Field Function
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19-16
—
Reserved
15-12
—
Reserved
11-8
—
Reserved
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 283
Field Function
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3
—
Reserved
2
SP7
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1
WP7
Write Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0
TP7
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
16.3.1.9 Off-Platform Peripheral Access Control Register (OPACRD)
16.3.1.9.1 Offset
Register Offset
OPACRD 4Ch
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
284 NXP Semiconductors
16.3.1.9.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0SP2 WP2 TP2 0SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 SP5 WP5 TP5 0 0
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
16.3.1.9.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 285
Field Function
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19
—
Reserved
18
SP3
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
286 NXP Semiconductors
Field Function
17
WP3
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15-12
—
Reserved
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4
—
Reserved
3-0
—
Reserved
16.3.1.10 Off-Platform Peripheral Access Control Register (OPACRE)
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 287
16.3.1.10.1 Offset
Register Offset
OPACRE 50h
16.3.1.10.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0 0 0
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SP6 WP6 TP6 0
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
16.3.1.10.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
288 NXP Semiconductors
Field Function
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27-24
—
Reserved
23-20
—
Reserved
19-16
—
Reserved
15-12
—
Reserved
11-8
—
Reserved
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3-0
—
Reserved
16.3.1.11 Off-Platform Peripheral Access Control Register (OPACRF)
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 289
16.3.1.11.1 Offset
Register Offset
OPACRF 54h
16.3.1.11.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0SP2 WP2 TP2 0SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SP4 WP4 TP4 0SP5 WP5 TP5 0 0
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
16.3.1.11.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
290 NXP Semiconductors
Field Function
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19 Reserved
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 291
Field Function
—
18
SP3
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17
WP3
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15
—
Reserved
14
SP4
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13
WP4
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12
TP4
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
292 NXP Semiconductors
Field Function
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4
—
Reserved
3-0
—
Reserved
16.3.1.12 Off-Platform Peripheral Access Control Register (OPACRG)
16.3.1.12.1 Offset
Register Offset
OPACRG 58h
16.3.1.12.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 293
16.3.1.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 SP2 WP2 TP2 0
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SP4 WP4 TP4 0SP5 WP5 TP5 0 0
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
16.3.1.12.4 Fields
Field Function
31-28
—
Reserved
27-24
—
Reserved
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19-16
—
Reserved
15
—
Reserved
14 Supervisor Protect
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
294 NXP Semiconductors
Field Function
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13
WP4
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12
TP4
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4
—
Reserved
3-0
—
Reserved
16.3.1.13 Off-Platform Peripheral Access Control Register (OPACRH)
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 295
16.3.1.13.1 Offset
Register Offset
OPACRH 5Ch
16.3.1.13.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 SP2 WP2 TP2 0
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.3.1.13.4 Fields
Field Function
31-28
—
Reserved
27-24
—
Reserved
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
296 NXP Semiconductors
Field Function
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19-16
—
Reserved
15-12
—
Reserved
11-8
—
Reserved
7-4
—
Reserved
3-0
—
Reserved
16.3.1.14 Off-Platform Peripheral Access Control Register (OPACRI)
16.3.1.14.1 Offset
Register Offset
OPACRI 60h
16.3.1.14.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 297
16.3.1.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 SP1 WP1 TP1 0 0 SP3 WP3 TP3
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SP4 WP4 TP4 0SP5 WP5 TP5 0SP6 WP6 TP6 0SP7 WP7 TP7
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
16.3.1.14.4 Fields
Field Function
31-28
—
Reserved
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19
—
Reserved
18
SP3
Supervisor Protect
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
298 NXP Semiconductors
Field Function
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17
WP3
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15
—
Reserved
14
SP4
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13
WP4
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12
TP4
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 299
Field Function
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3
—
Reserved
2
SP7
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1
WP7
Write Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0
TP7
Trusted Protect
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
300 NXP Semiconductors
Field Function
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
16.3.1.15 Off-Platform Peripheral Access Control Register (OPACRJ)
16.3.1.15.1 Offset
Register Offset
OPACRJ 64h
16.3.1.15.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 SP2 WP2 TP2 0SP3 WP3 TP3
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SP4 WP4 TP4 0 0 SP6 WP6 TP6 0SP7 WP7 TP7
W
Reset 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0
16.3.1.15.4 Fields
Field Function
31-28 Reserved
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 301
Field Function
—
27-24
—
Reserved
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19
—
Reserved
18
SP3
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17
WP3
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15
—
Reserved
14 Supervisor Protect
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
302 NXP Semiconductors
Field Function
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13
WP4
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12
TP4
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11-8
—
Reserved
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3
—
Reserved
2
SP7
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 303
Field Function
1
WP7
Write Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0
TP7
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
16.3.1.16 Off-Platform Peripheral Access Control Register (OPACRK)
16.3.1.16.1 Offset
Register Offset
OPACRK 68h
16.3.1.16.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 SP0 WP0 TP0 0SP1 WP1 TP1 0 0 SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SP6 WP6 TP6 0
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
304 NXP Semiconductors
16.3.1.16.4 Fields
Field Function
31
—
Reserved
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28
TP0
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19
—
Reserved
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 305
Field Function
18
SP3
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17
WP3
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15-12
—
Reserved
11-8
—
Reserved
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3-0
—
Reserved
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
306 NXP Semiconductors
16.3.1.17 Off-Platform Peripheral Access Control Register (OPACRL)
16.3.1.17.1 Offset
Register Offset
OPACRL 6Ch
16.3.1.17.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
16.3.1.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 SP1 WP1 TP1 0 0
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 SP5 WP5 TP5 0SP6 WP6 TP6 0SP7 WP7 TP7
W
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0
16.3.1.17.4 Fields
Field Function
31-28
—
Reserved
27
—
Reserved
26
SP1
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 307
Field Function
25
WP1
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20
—
Reserved
19-16
—
Reserved
15-12
—
Reserved
11
—
Reserved
10
SP5
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9
WP5
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7
—
Reserved
6
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
308 NXP Semiconductors
Field Function
5
WP6
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4
TP6
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3
—
Reserved
2
SP7
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1
WP7
Write Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0
TP7
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
16.4 Functional description
The peripheral bridge functions as a bus protocol translator between the crossbar switch
and the slave peripheral bus.
The peripheral bridge manages all transactions destined for the attached slave devices and
generates select signals for modules on the peripheral bus by decoding accesses within
the attached address space.
Chapter 16 Peripheral Bridge (AIPS-Lite)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 309
16.4.1 Access support
Aligned and misaligned 32-bit, 16-bit, and byte accesses are supported for 32-bit
peripherals. Misaligned accesses are supported to allow memory to be placed on the slave
peripheral bus. Peripheral registers must not be misaligned, although no explicit checking
is performed by the peripheral bridge. All accesses are performed with a single transfer.
All accesses to the peripheral slots must be sized less than or equal to the designated
peripheral slot size. If an access is attempted that is larger than the targeted port, an error
response is generated.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
310 NXP Semiconductors
Chapter 17
Direct Memory Access Multiplexer (DMAMUX)
Chip-specific DMAMUX information
17.1.1 Number of channels
The number of channels across S32K1xx series varies across variants. See below table
for the same.
Table 17-1. Number of channles
Chips Number of channels
S32K116 4
S32K118 4
S32K142 16
S32K144 16
S32K146 16
S32K148 16
17.1.2 DMA transfers via TRGMUX trigger
The triggers from TRGMUX module can trigger a DMA transfer on the first four DMA
channels, for example, the LPIT can trigger DMA via TRGMUX. See Figure 19-2 for
module interconnectivity details. The LPIT/DMA periodic trigger assignments are
detailed at LPIT/DMA Periodic Trigger Assignments.
Asynchronous DMA operation does not support trigger options.
In cases where multiple DMA request are routed to DMAMUX source, software needs to
make sure that only one DMA request is enabled at a time. For example DMA request of
one Ethernet timer can be enabled at a particular time, while others can enable interrupt
during that time.
17.1
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 311
17.2 Introduction
17.2.1 Overview
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots,
to any of the 16 DMA channels. See the chip-specific information to know the detailed
source numbers. This process is illustrated in the following figure.
DMA channel #0
Source #1
Source #2
Source #3
Always #1
DMA channel #n
Always #y
Source #x
Trigger #1
Trigger #z
DMA channel #1
DMAMUX
Figure 17-1. DMAMUX block diagram
17.2.2 Features
The DMAMUX module provides these features:
• Up to 61 peripheral slots and up to 2 always-on slots can be routed to 16 channels.
• 16 independently selectable DMA channel routers.
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
312 NXP Semiconductors
• The first 4 channels additionally provide a trigger functionality.
• Each channel router can be assigned to one of the possible peripheral DMA slots or
to one of the always-on slots.
17.2.3 Modes of operation
The following operating modes are available:
• Disabled mode
In this mode, the DMA channel is disabled. Because disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA channel MUX. It may also
be used to temporarily suspend a DMA channel while reconfiguration of the system
takes place, for example, changing the period of a DMA trigger.
• Normal mode
In this mode, a DMA source is routed directly to the specified DMA channel. The
operation of the DMAMUX in this mode is completely transparent to the system.
• Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer, such as when a
transmit buffer becomes empty or a receive buffer becomes full, periodically.
Configuration of the period is done by an external periodic interrupt timer (for
example, PIT). This mode is available only for channels 0–3.
17.3 Memory map/register definition
This section provides a detailed description of all memory-mapped registers in the
DMAMUX.
17.3.1 DMAMUX register descriptions
Chapter 17 Direct Memory Access Multiplexer (DMAMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 313
17.3.1.1 DMAMUX Memory map
DMAMUX base address: 4002_1000h
Offset Register Width
(In bits)
Access Reset value
0h - Fh Channel Configuration register (CHCFG0 - CHCFG15) 8 RW 00h
17.3.1.2 Channel Configuration register (CHCFG0 - CHCFG15)
17.3.1.2.1 Offset
For a = 0 to 15:
Register Offset
CHCFGa 0h + (a × 1h)
17.3.1.2.2 Function
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same source value
will result in unpredictable behavior. This is true, even if a
channel is disabled (ENBL==0).
Before changing the trigger or source settings, a DMA channel
must be disabled via CHCFGn[ENBL].
17.3.1.2.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
ENB
L
TRIG
SOURC
E
W
Reset 0 0 0 0 0 0 0 0
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
314 NXP Semiconductors
17.3.1.2.4 Fields
Field Function
7
ENBL
DMA Channel Enable
Enables the DMA channel.
0b - DMA channel is disabled. This mode is primarily used during configuration of the DMAMux.
The DMA has separate channel enables/disables, which should be used to disable or reconfigure a
DMA channel.
1b - DMA channel is enabled
6
TRIG
DMA Channel Trigger Enable
Enables the periodic trigger capability for the triggered DMA channel.
0b - Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply
route the specified source to the DMA channel. (Normal mode)
1b - Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic
Trigger mode.
5-0
SOURCE
DMA Channel Source (Slot)
Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific
DMAMUX information for details about the peripherals and their slot numbers.
17.4 Functional description
The primary purpose of the DMAMUX is to provide flexibility in the system's use of the
available DMA channels.
As such, configuration of the DMAMUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in Enabling and
configuring sources is followed, the configuration of the DMAMUX may be changed
during the normal operation of the system.
Functionally, the DMAMUX channels may be divided into two classes:
• Channels that implement the normal routing functionality plus periodic triggering
capability
• Channels that implement only the normal routing functionality
17.4.1 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism
to transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention.
Chapter 17 Direct Memory Access Multiplexer (DMAMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 315
The trigger is generated by an external periodic interrupt timer (for example, PIT); as
such, the configuration of the periodic triggering interval is done via configuring the
external periodic timer.
Note
Because of the dynamic nature of the system (due to DMA
channel priorities, bus arbitration, interrupt service routine
lengths, etc.), the number of clock cycles between a trigger and
the actual DMA transfer cannot be guaranteed.
DMA channel #0
Source #1
Source #2
Source #3
Always #1
DMA channel #m-1
Always #y
Trigger #m
Source #x
Trigger #1
Figure 17-2. DMAMUX triggered channels
The DMA channel triggering capability allows the system to schedule regular DMA
transfers, usually on the transmit side of certain peripherals, without the intervention of
the processor. This trigger works by gating the request from the peripheral to the DMA
until a trigger event has been seen. This is illustrated in the following figure.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
316 NXP Semiconductors
DMA request
Peripheral request
Trigger
Figure 17-3. DMAMUX channel triggering: normal operation
After the DMA request has been serviced, the peripheral will negate its request,
effectively resetting the gating mechanism until the peripheral reasserts its request and
the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not
requesting a transfer, then that trigger will be ignored. This situation is illustrated in the
following figure.
DMA request
Peripheral request
Trigger
Figure 17-4. DMAMUX channel triggering: ignored trigger
This triggering capability may be used with any peripheral that supports DMA transfers,
and is most useful for two types of situations:
• Periodically polling external devices on a particular bus
As an example, the transmit side of an SPI is assigned to a DMA channel with a
trigger, as described above. After it has been set up, the SPI will request DMA
transfers, presumably from memory, as long as its transmit buffer is empty. By using
a trigger on this channel, the SPI transfers can be automatically performed every 5 μs
(as an example). On the receive side of the SPI, the SPI and DMA can be configured
to transfer receive data into memory, effectively implementing a method to
periodically read data from external devices and transfer the results into memory
without processor intervention.
• Using the GPIO ports to drive or sample waveforms
By configuring the DMA to transfer data to one or more GPIO ports, it is possible to
create complex waveforms using tabular data stored in on-chip memory. Conversely,
using the DMA to periodically transfer data from one or more GPIO ports, it is
possible to sample complex waveforms and store the results in tabular form in on-
chip memory.
Chapter 17 Direct Memory Access Multiplexer (DMAMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 317
17.4.2 DMA channels with no triggering capability
The other channels of the DMAMUX provide the normal routing functionality as
described in Modes of operation.
17.4.3 Always-enabled DMA sources
In addition to the peripherals that can be used as DMA sources, there are 2 additional
DMA sources that are always enabled. Unlike the peripheral DMA sources, where the
peripheral controls the flow of data during DMA transfers, the sources that are always
enabled provide no such "throttling" of the data transfers. These sources are most useful
in the following cases:
• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO
pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA
triggering capability).
• Performing DMA transfers from memory to memory—Moving data from memory to
memory, typically as fast as possible, sometimes with software activation.
• Performing DMA transfers from memory to the external bus, or vice-versa—Similar
to memory to memory transfers, this is typically done as quickly as possible.
• Any DMA transfer that requires software activation—Any DMA transfer that should
be explicitly started by software.
In cases where software should initiate the start of a DMA transfer, an always-enabled
DMA source can be used to provide maximum flexibility. When activating a DMA
channel via software, subsequent executions of the minor loop require that a new start
event be sent. This can either be a new software activation, or a transfer request from the
DMA channel MUX. The options for doing this are:
• Transfer all data in a single minor loop.
By configuring the DMA to transfer all of the data in a single minor loop (that is,
major loop counter = 1), no reactivation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the
DMA transfer will impose on the system. For this option, the DMA channel must be
disabled in the DMA channel MUX.
• Use explicit software reactivation.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
318 NXP Semiconductors
In this option, the DMA is configured to transfer the data using both minor and major
loops, but the processor is required to reactivate the channel by writing to the DMA
registers after every minor loop. For this option, the DMA channel must be disabled
in the DMA channel MUX.
• Use an always-enabled DMA source.
In this option, the DMA is configured to transfer the data using both minor and major
loops, and the DMA channel MUX does the channel reactivation. For this option, the
DMA channel should be enabled and pointing to an "always enabled" source. Note
that the reactivation of the channel can be continuous (DMA triggering is disabled)
or can use the DMA triggering capability. In this manner, it is possible to execute
periodic transfers of packets of data from one source to another, without processor
intervention.
17.5 Initialization/application information
This section provides instructions for initializing the DMA channel MUX.
17.5.1 Reset
The reset state of each individual bit is shown in Memory map/register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.
17.5.2 Enabling and configuring sources
To enable a source with periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Configure the corresponding timer.
5. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are
set.
Chapter 17 Direct Memory Access Multiplexer (DMAMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 319
NOTE
The following is an example. See the chip-specific information
for the number of this device's DMA channels that have
triggering capability.
To configure source #5 transmit for use with DMA channel 1, with periodic triggering
capability:
1. Write 0x00 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Configure a timer for the desired trigger interval.
4. Write 0xC5 to CHCFG1.
The following code example illustrates steps 1 and 4 above:
void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE)
{
DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE;
DMAMUX_0.CHCFG[DMA_CH].B.ENBL = 1;
DMAMUX_0.CHCFG[DMA_CH].B.TRIG = 1;
}
To enable a source, without periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that CHCFG[ENBL] is setwhile CHCFG[TRIG] is
cleared.
NOTE
The following is an example. See the chip configuration details
for the number of this device's DMA channels that have
triggering capability.
To configure source #5 transmit for use with DMA channel 1, with no periodic triggering
capability:
1. Write 0x00 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Write 0x85 to CHCFG1.
The following code example illustrates steps 1 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
320 NXP Semiconductors
volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);
volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);
volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);
volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);
volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);
volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);
volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);
volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);
volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);
volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);
volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCFG1 = 0x00;
*CHCFG1 = 0x85;
To disable a source:
A particular DMA source may be disabled by not writing the corresponding source value
into any of the CHCFG registers. Additionally, some module-specific configuration may
be necessary. See the appropriate section for more details.
To switch the source of a DMA channel:
1. Disable the DMA channel in the DMA and reconfigure the channel for the new
source.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
3. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are
set.
To switch DMA channel 8 from source #5 transmit to source #7 transmit:
1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to
handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't
have triggering capability.
2. Write 0x00 to CHCFG8.
3. Write 0x87 to CHCFG8. (In this example, setting CHCFG[TRIG] would have no
effect due to the assumption that channel 8 does not support the periodic triggering
functionality.)
The following code example illustrates steps 2 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);
volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);
volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);
Chapter 17 Direct Memory Access Multiplexer (DMAMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 321
volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);
volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);
volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);
volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);
volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);
volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);
volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);
volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);
volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCFG8 = 0x00;
*CHCFG8 = 0x87;
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
322 NXP Semiconductors
Chapter 18
Enhanced Direct Memory Access (eDMA)
18.1 Chip-specific eDMA information
Wait mode is not supported. See Module operation in available low power modes for
details on available power modes.
16-byte burst and 32-byte burst is not supported on S32K11x variants.
NOTE
For S32K11x variants, when executing a large, zero wait-stated
memory-to-memory transfer, insert bandwidth control using the
TCD_CSR[BWC] bits to avoid:
• Starvation of another master accessing the memory.
• Any delay in writing a TCD during the transfer.
18.1.1 Number of channels
The number of channels across S32K1xx series varies across variants. See below table
for the same.
Table 18-1. Number of channles
Chips Number of channels
S32K116 4
S32K118 4
S32K142 16
S32K144 16
S32K146 16
S32K148 16
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 323
18.2 Introduction
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data transfers with minimal intervention from a host
processor. The hardware microarchitecture includes:
• A DMA engine that performs:
• Source address and destination address calculations
• Data-movement operations
• Local memory containing transfer control descriptors for each of the 16 channels
18.2.1 eDMA system block diagram
Figure 18-1 illustrates the components of the eDMA system, including the eDMA
module ("engine").
1
Transfer Control
Descriptor (TCD)
eDMA engine
Data Path
eDMA system
0
Program Model/
64
Control
n-1
To/From Crossbar Switch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
Internal Peripheral Bus
eDMA Peripheral
Request eDMA Done
Figure 18-1. eDMA system block diagram
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
324 NXP Semiconductors
18.2.2 Block parts
The eDMA module is partitioned into two major modules: the eDMA engine and the
transfer-control descriptor local memory.
The eDMA engine is further partitioned into four submodules:
Table 18-2. eDMA engine submodules
Submodule Function
Address path This block implements registered versions of two channel transfer control descriptors, channel x
and channel y, and manages all master bus-address calculations. All the channels provide the
same functionality. This structure allows data transfers associated with one channel to be
preempted after the completion of a read/write sequence if a higher priority channel activation is
asserted while the first channel is active. After a channel is activated, it runs until the minor loop is
completed, unless preempted by a higher priority channel. This provides a mechanism (enabled
by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time
another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from local memory and
loaded into the address path channel x registers for a normal start and into channel y registers for
a preemption start. After the minor loop completes execution, the address path hardware writes
the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major
iteration count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as
part of a scatter/gather operation.
Data path This block implements the bus master read/write datapath. It includes a data buffer and the
necessary multiplex logic to support any required data alignment. The internal read data bus is the
primary input, and the internal write data bus is the primary output.
The address and data path modules directly support the 2-stage pipelined internal bus. The
address path module represents the 1st stage of the bus pipeline (address phase), while the data
path module implements the 2nd stage of the pipeline (data phase).
Program model/channel
arbitration
This block implements the first section of the eDMA programming model as well as the channel
arbitration logic. The programming model registers are connected to the internal peripheral bus.
The eDMA peripheral request inputs and interrupt request outputs are also connected to this block
(via control logic).
Control This block provides all the control functions for the eDMA engine. For data transfers where the
source and destination sizes are equal, the eDMA engine performs a series of source read/
destination write operations until the number of bytes specified in the minor loop byte count has
moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data
are required for each reference of the larger size. As an example, if the source size references 16-
bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write.
The transfer-control descriptor local memory is further partitioned into:
Table 18-3. Transfer control descriptor memory
Submodule Description
Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA
engine as well as references from the internal peripheral bus. As noted earlier, in the event of
Table continues on the next page...
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 325
Table 18-3. Transfer control descriptor memory (continued)
Submodule Description
simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is
stalled.
Memory array TCD storage for each channel's transfer profile.
18.2.3 Features
The eDMA is a highly programmable data-transfer engine optimized to minimize any
required intervention from the host processor. It is intended for use in applications where
the data size to be transferred is statically known and not defined within the transferred
data itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 16-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
326 NXP Semiconductors
• One interrupt per channel, which can be asserted at completion of major iteration
count
• Programmable error terminations per channel and logically summed together to
form one error interrupt to the interrupt controller
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
In the discussion of this module, n is used to reference the channel number.
18.3 Modes of operation
The eDMA operates in the following modes:
Table 18-4. Modes of operation
Mode Description
Normal In Normal mode, the eDMA transfers data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with the eDMA.
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the
transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that
transfers these NBYTES per service request. Each service request executes one iteration of the
major loop, which transfers NBYTES of data.
Debug DMA operation is configurable in Debug mode via the control register:
• If CR[EDBG] is cleared, the DMA continues to operate.
• If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a
channel is active, the eDMA continues operation until the channel retires.
Wait Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer
completes, the device enters Wait mode.
18.4 Memory map/register definition
The eDMA's programming model is partitioned into two regions:
• The first region defines a number of registers providing control functions
• The second region corresponds to the local transfer control descriptor (TCD)
memory
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 327
18.4.1 TCD memory
Each channel requires a 32-byte transfer control descriptor for defining the desired data
movement operation. The channel descriptors are stored in the local memory in
sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented
as 11 registers of 16 or 32 bits.
18.4.2 TCD initialization
Prior to activating a channel, you must initialize its TCD with the appropriate transfer
profile.
18.4.3 TCD structure
SADDR
31 30
29
28
27
26
25
24
23
22 21
20
19
18
17
16
15
14
13
12
11
10 9
8
7
6
5 4
3
2
1
0
SOFF SMOD SSIZE DMOD DSIZE
SMLOE
DMLOE
MLOFF or NBYTES NBYTES
SLAST
DADDR
31 30
29
28
27
26
25
24
23
22 21
20
19
18
17
16
15
14
13
12
11
10 9
8
7
6
5 4
3
2
1
0
CITER.E_LINK
CITER or
CITER.LINKCH CITER DOFF
DLAST_SGA
BITER.E_LINK
BITER or
BITER.LINKCH BITER
START
INT_MAJ
INT_HALF
D_REQ
E_SG
MAJOR.E_LINK
ACTIVE
DONE
BWC
MAJOR.LINKCH
NBYTES
0000h
0004h
0008h
DMA_CR[EMLM] enabled
000Ch
0010h
0014h
0018h
001Ch
Reserved
DMA_CR[EMLM] disabled
{
{
{
18.4.4 Reserved memory and bit fields
• Reading reserved bits in a register returns the value of zero.
• Writes to reserved bits in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
328 NXP Semiconductors
18.4.5 DMA register descriptions
18.4.5.1 DMA Memory map
DMA base address: 4000_8000h
Offset Register Width
(In bits)
Access Reset value
0h Control Register (CR) 32 RW See
description.
4h Error Status Register (ES) 32 RO 0000_0000h
Ch Enable Request Register (ERQ) 32 RW 0000_0000h
14h Enable Error Interrupt Register (EEI) 32 RW 0000_0000h
18h Clear Enable Error Interrupt Register (CEEI) 8 WORZ 00h
19h Set Enable Error Interrupt Register (SEEI) 8 WORZ 00h
1Ah Clear Enable Request Register (CERQ) 8 WORZ 00h
1Bh Set Enable Request Register (SERQ) 8 WORZ 00h
1Ch Clear DONE Status Bit Register (CDNE) 8 WORZ 00h
1Dh Set START Bit Register (SSRT) 8 WORZ 00h
1Eh Clear Error Register (CERR) 8 WORZ 00h
1Fh Clear Interrupt Request Register (CINT) 8 WORZ 00h
24h Interrupt Request Register (INT) 32 W1C 0000_0000h
2Ch Error Register (ERR) 32 W1C 0000_0000h
34h Hardware Request Status Register (HRS) 32 RO 0000_0000h
44h Enable Asynchronous Request in Stop Register (EARS) 32 RW 0000_0000h
100h Channel Priority Register (DCHPRI3) 8 RW 03h
101h Channel Priority Register (DCHPRI2) 8 RW 02h
102h Channel Priority Register (DCHPRI1) 8 RW 01h
103h Channel Priority Register (DCHPRI0) 8 RW 00h
104h Channel Priority Register (DCHPRI7) 8 RW 07h
105h Channel Priority Register (DCHPRI6) 8 RW 06h
106h Channel Priority Register (DCHPRI5) 8 RW 05h
107h Channel Priority Register (DCHPRI4) 8 RW 04h
108h Channel Priority Register (DCHPRI11) 8 RW 0Bh
109h Channel Priority Register (DCHPRI10) 8 RW 0Ah
10Ah Channel Priority Register (DCHPRI9) 8 RW 09h
10Bh Channel Priority Register (DCHPRI8) 8 RW 08h
10Ch Channel Priority Register (DCHPRI15) 8 RW 0Fh
Table continues on the next page...
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 329
Offset Register Width
(In bits)
Access Reset value
10Dh Channel Priority Register (DCHPRI14) 8 RW 0Eh
10Eh Channel Priority Register (DCHPRI13) 8 RW 0Dh
10Fh Channel Priority Register (DCHPRI12) 8 RW 0Ch
1000h -
11E0h
TCD Source Address (TCD0_SADDR - TCD15_SADDR) 32 RW See
description.
1004h -
11E4h
TCD Signed Source Address Offset (TCD0_SOFF - TCD15_SOFF) 16 RW See
description.
1006h -
11E6h
TCD Transfer Attributes (TCD0_ATTR - TCD15_ATTR) 16 RW See
description.
1008h -
11E8h
TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBY
TES_MLNO - TCD15_NBYTES_MLNO)
32 RW See
description.
1008h -
11E8h
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and
Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD15_NBYTES_
MLOFFNO)
32 RW See
description.
1008h -
11E8h
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset
Enabled) (TCD0_NBYTES_MLOFFYES - TCD15_NBYTES_MLO
FFYES)
32 RW See
description.
100Ch -
11ECh
TCD Last Source Address Adjustment (TCD0_SLAST - TCD15_SL
AST)
32 RW See
description.
1010h - 11F0h TCD Destination Address (TCD0_DADDR - TCD15_DADDR) 32 RW See
description.
1014h - 11F4h TCD Signed Destination Address Offset (TCD0_DOFF - TCD15_DO
FF)
16 RW See
description.
1016h - 11F6h TCD Current Minor Loop Link, Major Loop Count (Channel Linking
Disabled) (TCD0_CITER_ELINKNO - TCD15_CITER_ELINKNO)
16 RW See
description.
1016h - 11F6h TCD Current Minor Loop Link, Major Loop Count (Channel Linking
Enabled) (TCD0_CITER_ELINKYES - TCD15_CITER_ELINKYES)
16 RW See
description.
1018h - 11F8h TCD Last Destination Address Adjustment/Scatter Gather Address
(TCD0_DLASTSGA - TCD15_DLASTSGA)
32 RW See
description.
101Ch -
11FCh
TCD Control and Status (TCD0_CSR - TCD15_CSR) 16 RW See
description.
101Eh -
11FEh
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking
Disabled) (TCD0_BITER_ELINKNO - TCD15_BITER_ELINKNO)
16 RW See
description.
101Eh -
11FEh
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking
Enabled) (TCD0_BITER_ELINKYES - TCD15_BITER_ELINKYES)
16 RW See
description.
18.4.5.2 Control Register (CR)
18.4.5.2.1 Offset
Register Offset
CR 0h
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
330 NXP Semiconductors
18.4.5.2.2 Function
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through (from high to low channel number) without regard to priority.
NOTE
For correct operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Minor loop offsets are address offset values added to the final source address
(TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion.
When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the
final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR),
or to both prior to the addresses being written back into the TCD. If the major loop is
complete, the minor loop offset is ignored and the major loop address offsets
(TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR
and TCDn_DADDR values.
When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion
of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to
specify the minor loop offset should be applied to the source address (TCDn_SADDR)
upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop
offset should be applied to the destination address (TCDn_DADDR) upon minor loop
completion, and the sign extended minor loop offset value (MLOFF). The same offset
value (MLOFF) is used for both source and destination minor loop offsets. When either
minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES field is reduced
to 10 bits. When both minor loop offsets are disabled (SMLOE cleared and DMLOE
cleared), the NBYTES field is a 30-bit vector.
When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
assigned to the NBYTES field.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 331
18.4.5.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ACTIVE
Reserved
0
CX
EC
X
W
Reset 0uuuuuuu00000000
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
EMLM
CLM
HALT
HOE
Reserved
ERCA
EDB
G
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.2.4 Fields
Field Function
31
ACTIVE
DMA Active Status
0b - eDMA is idle.
1b - eDMA is executing a channel.
30-24
—
eDMA version number
Reserved
23-18
—
Reserved
17
CX
Cancel Transfer
0b - Normal operation
1b - Cancel the remaining data transfer. Stop the executing channel and force the minor loop to
finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit
clears itself after the cancel has been honored. This cancel retires the channel normally as if the
minor loop was completed.
16
ECX
Error Cancel Transfer
0b - Normal operation
1b - Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing
channel and force the minor loop to finish. The cancel takes effect after the last write of the current
read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling
the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register
(DMAx_ES) and generating an optional error interrupt.
15-8
—
Reserved
7
EMLM
Enable Minor Loop Mapping
0b - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
1b - Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the
NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source
address, the destination address, or both. The NBYTES field is reduced when either offset is
enabled.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
332 NXP Semiconductors
Field Function
6
CLM
Continuous Link Mode
NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop
iteration per service request, for example, if the channel's NBYTES value is the same as either
the source or destination size. The same data transfer profile can be achieved by simply
increasing the NBYTES value, which provides more efficient, faster processing.
0b - A minor loop channel link made to itself goes through channel arbitration before being
activated again.
1b - A minor loop channel link made to itself does not go through channel arbitration before being
activated again. Upon minor loop completion, the channel activates again if that channel has a
minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop
offsets and restarts the next minor loop.
5
HALT
Halt DMA Operations
0b - Normal operation
1b - Stall the start of any new channels. Executing channels are allowed to complete. Channel
execution resumes when this bit is cleared.
4
HOE
Halt On Error
0b - Normal operation
1b - Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the
HALT bit is cleared.
3
—
Reserved
Reserved
2
ERCA
Enable Round Robin Channel Arbitration
0b - Fixed priority arbitration is used for channel selection .
1b - Round robin arbitration is used for channel selection .
1
EDBG
Enable Debug
0b - When in debug mode, the DMA continues to operate.
1b - When in debug mode, the DMA stalls the start of a new channel. Executing channels are
allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG
bit is cleared.
0
—
Reserved
Reserved
18.4.5.3 Error Status Register (ES)
18.4.5.3.1 Offset
Register Offset
ES 4h
18.4.5.3.2 Function
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 333
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
• A cancel transfer with error bit that will be set when a transfer is canceled via the
corresponding cancel transfer control bit
See Fault reporting and handling for more details.
18.4.5.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RVLD 0ECX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CPE 0ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.3.4 Fields
Field Function
31
VLD
VLD
Logical OR of all ERR status bits
0b - No ERR bits are set.
1b - At least one ERR bit is set indicating a valid error exists that has not been cleared.
30-17
—
Reserved
16
ECX
Transfer Canceled
0b - No canceled transfers
1b - The last recorded entry was a canceled transfer by the error cancel transfer input
15
—
Reserved
14
CPE
Channel Priority Error
0b - No channel priority error
1b - The last recorded error was a configuration error in the channel priorities . Channel priorities
are not unique.
13-12
—
Reserved
11-8 Error Channel Number or Canceled Channel Number
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
334 NXP Semiconductors
Field Function
ERRCHN The channel number of the last recorded error, excluding CPE errors, or last recorded error canceled
transfer.
7
SAE
Source Address Error
0b - No source address configuration error.
1b - The last recorded error was a configuration error detected in the TCDn_SADDR field.
TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6
SOE
Source Offset Error
0b - No source offset configuration error
1b - The last recorded error was a configuration error detected in the TCDn_SOFF field.
TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
5
DAE
Destination Address Error
0b - No destination address configuration error
1b - The last recorded error was a configuration error detected in the TCDn_DADDR field.
TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
4
DOE
Destination Offset Error
0b - No destination offset configuration error
1b - The last recorded error was a configuration error detected in the TCDn_DOFF field.
TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
3
NCE
NBYTES/CITER Configuration Error
0b - No NBYTES/CITER configuration error
1b - The last recorded error was a configuration error detected in the TCDn_NBYTES or
TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and
TCDn_ATTR[DSIZE], orTCDn_CITER[CITER] is equal to zero, orTCDn_CITER[ELINK] is not equal
to TCDn_BITER[ELINK]
2
SGE
Scatter/Gather Configuration Error
0b - No scatter/gather configuration error
1b - The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This
field is checked at the beginning of a scatter/gather operation after major loop completion if
TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1
SBE
Source Bus Error
0b - No source bus error
1b - The last recorded error was a bus error on a source read
0
DBE
Destination Bus Error
0b - No destination bus error
1b - The last recorded error was a bus error on a destination write
18.4.5.4 Enable Request Register (ERQ)
18.4.5.4.1 Offset
Register Offset
ERQ Ch
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 335
18.4.5.4.2 Function
The ERQ register provides a bit map for the 16 channels to enable the request signal for
each channel. The state of any given channel enable is directly affected by writes to this
register; it is also affected by writes to the SERQ and CERQ registers. These registers are
provided so the request enable for a single channel can easily be modified without
needing to perform a read-modify-write sequence to this register.
DMA request input signals and this enable request flag must be asserted before a
channel's hardware service request is accepted. The state of the DMA enable request flag
does not affect a channel service request made explicitly through software or a linked
channel request.
NOTE
Disable a channel's hardware service request at the source
before clearing the channel's ERQ bit.
18.4.5.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ERQ15
ERQ14
ERQ13
ERQ12
ERQ11
ERQ10
ERQ9
ERQ8
ERQ7
ERQ6
ERQ5
ERQ4
ERQ3
ERQ2
ERQ1
ERQ0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.4.4 Fields
Field Function
31-16
—
Reserved
15
ERQ15
Enable DMA Request 15
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
14
ERQ14
Enable DMA Request 14
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
13
ERQ13
Enable DMA Request 13
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
336 NXP Semiconductors
Field Function
12
ERQ12
Enable DMA Request 12
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
11
ERQ11
Enable DMA Request 11
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
10
ERQ10
Enable DMA Request 10
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
9
ERQ9
Enable DMA Request 9
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
8
ERQ8
Enable DMA Request 8
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
7
ERQ7
Enable DMA Request 7
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
6
ERQ6
Enable DMA Request 6
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
5
ERQ5
Enable DMA Request 5
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
4
ERQ4
Enable DMA Request 4
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
3
ERQ3
Enable DMA Request 3
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
2
ERQ2
Enable DMA Request 2
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
1
ERQ1
Enable DMA Request 1
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
0
ERQ0
Enable DMA Request 0
0b - The DMA request signal for the corresponding channel is disabled
1b - The DMA request signal for the corresponding channel is enabled
18.4.5.5 Enable Error Interrupt Register (EEI)
18.4.5.5.1 Offset
Register Offset
EEI 14h
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 337
18.4.5.5.2 Function
The EEI register provides a bit map for the 16 channels to enable the error interrupt
signal for each channel. The state of any given channel's error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI.
These registers are provided so that the error interrupt enable for a single channel can
easily be modified without the need to perform a read-modify-write sequence to the EEI
register.
The DMA error indicator and the error interrupt enable flag must be asserted before an
error interrupt request for a given channel is asserted to the interrupt controller.
18.4.5.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EEI15
EEI14
EEI13
EEI12
EEI11
EEI10
EEI
9
EEI
8
EEI
7
EEI
6
EEI
5
EEI
4
EEI
3
EEI
2
EEI
1
EEI
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.5.4 Fields
Field Function
31-16
—
Reserved
15
EEI15
Enable Error Interrupt 15
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
14
EEI14
Enable Error Interrupt 14
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
13
EEI13
Enable Error Interrupt 13
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
12
EEI12
Enable Error Interrupt 12
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
11 Enable Error Interrupt 11
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
338 NXP Semiconductors
Field Function
EEI11 0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
10
EEI10
Enable Error Interrupt 10
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
9
EEI9
Enable Error Interrupt 9
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
8
EEI8
Enable Error Interrupt 8
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
7
EEI7
Enable Error Interrupt 7
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
6
EEI6
Enable Error Interrupt 6
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
5
EEI5
Enable Error Interrupt 5
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
4
EEI4
Enable Error Interrupt 4
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
3
EEI3
Enable Error Interrupt 3
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
2
EEI2
Enable Error Interrupt 2
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
1
EEI1
Enable Error Interrupt 1
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
0
EEI0
Enable Error Interrupt 0
0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
18.4.5.6 Clear Enable Error Interrupt Register (CEEI)
18.4.5.6.1 Offset
Register Offset
CEEI 18h
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 339
18.4.5.6.2 Function
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
18.4.5.6.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
CAE
E
0
CEE
I
Reset 0 0 0 0 0 0 0 0
18.4.5.6.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
CAEE
Clear All Enable Error Interrupts
0b - Clear only the EEI bit specified in the CEEI field
1b - Clear all bits in EEI
5-4
—
Reserved
3-0
CEEI
Clear Enable Error Interrupt
Clears the corresponding bit in EEI
18.4.5.7 Set Enable Error Interrupt Register (SEEI)
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
340 NXP Semiconductors
18.4.5.7.1 Offset
Register Offset
SEEI 19h
18.4.5.7.2 Function
The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to
enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set
function, forcing the entire EEI contents to be set.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
18.4.5.7.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
SAE
E
0
SE
EI
Reset 0 0 0 0 0 0 0 0
18.4.5.7.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
SAEE
Sets All Enable Error Interrupts
0b - Set only the EEI bit specified in the SEEI field.
1b - Sets all bits in EEI
5-4
—
Reserved
3-0
SEEI
Set Enable Error Interrupt
Sets the corresponding bit in EEI
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 341
18.4.5.8 Clear Enable Request Register (CERQ)
18.4.5.8.1 Offset
Register Offset
CERQ 1Ah
18.4.5.8.2 Function
The CERQ provides a simple memory-mapped mechanism to clear a given bit in the
ERQ to disable the DMA request for a given channel. The data value on a register write
causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a
global clear function, forcing the entire contents of the ERQ to be cleared, disabling all
DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
NOTE
Disable a channel's hardware service request at the source
before clearing the channel's ERQ bit.
18.4.5.8.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
CAER
0
CERQ
Reset 0 0 0 0 0 0 0 0
18.4.5.8.4 Fields
Field Function
7 No Op enable
0b - Normal operation
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
342 NXP Semiconductors
Field Function
NOP 1b - No operation, ignore the other bits in this register
6
CAER
Clear All Enable Requests
0b - Clear only the ERQ bit specified in the CERQ field
1b - Clear all bits in ERQ
5-4
—
Reserved
3-0
CERQ
Clear Enable Request
Clears the corresponding bit in ERQ.
18.4.5.9 Set Enable Request Register (SERQ)
18.4.5.9.1 Offset
Register Offset
SERQ 1Bh
18.4.5.9.2 Function
The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ
to enable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set
function, forcing the entire contents of ERQ to be set.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
18.4.5.9.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
SAE
R
0
SER
Q
Reset 0 0 0 0 0 0 0 0
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 343
18.4.5.9.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
SAER
Set All Enable Requests
0b - Set only the ERQ bit specified in the SERQ field
1b - Set all bits in ERQ
5-4
—
Reserved
3-0
SERQ
Set Enable Request
Sets the corresponding bit in ERQ.
18.4.5.10 Clear DONE Status Bit Register (CDNE)
18.4.5.10.1 Offset
Register Offset
CDNE 1Ch
18.4.5.10.2 Function
The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the
corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a
global clear function, forcing all DONE bits to be cleared.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
344 NXP Semiconductors
18.4.5.10.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
CADN
0
CDNE
Reset 0 0 0 0 0 0 0 0
18.4.5.10.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
CADN
Clears All DONE Bits
0b - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
1b - Clears all bits in TCDn_CSR[DONE]
5-4
—
Reserved
3-0
CDNE
Clear DONE Bit
Clears the corresponding bit in TCDn_CSR[DONE]
18.4.5.11 Set START Bit Register (SSRT)
18.4.5.11.1 Offset
Register Offset
SSRT 1Dh
18.4.5.11.2 Function
The SSRT provides a simple memory-mapped mechanism to set the START bit in the
TCD of the given channel. The data value on a register write causes the START bit in the
corresponding transfer control descriptor to be set. Setting the SAST bit provides a global
set function, forcing all START bits to be set.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 345
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
18.4.5.11.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
SAS
T
0
SSR
T
Reset 0 0 0 0 0 0 0 0
18.4.5.11.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
SAST
Set All START Bits (activates all channels)
0b - Set only the TCDn_CSR[START] bit specified in the SSRT field
1b - Set all bits in TCDn_CSR[START]
5-4
—
Reserved
3-0
SSRT
Set START Bit
Sets the corresponding bit in TCDn_CSR[START]
18.4.5.12 Clear Error Register (CERR)
18.4.5.12.1 Offset
Register Offset
CERR 1Eh
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
346 NXP Semiconductors
18.4.5.12.2 Function
The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR
to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a
global clear function, forcing the ERR contents to be cleared, clearing all channel error
indicators. If the NOP bit is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
18.4.5.12.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
CAEI
0
CER
R
Reset 0 0 0 0 0 0 0 0
18.4.5.12.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
CAEI
Clear All Error Indicators
0b - Clear only the ERR bit specified in the CERR field
1b - Clear all bits in ERR
5-4
—
Reserved
3-0
CERR
Clear Error Indicator
Clears the corresponding bit in ERR
18.4.5.13 Clear Interrupt Request Register (CINT)
18.4.5.13.1 Offset
Register Offset
CINT 1Fh
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 347
18.4.5.13.2 Function
The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT
to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a
global clear function, forcing the entire contents of the INT to be cleared, disabling all
DMA interrupt requests.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
18.4.5.13.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
0
W
NOP
CAIR
0
CINT
Reset 0 0 0 0 0 0 0 0
18.4.5.13.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
CAIR
Clear All Interrupt Requests
0b - Clear only the INT bit specified in the CINT field
1b - Clear all bits in INT
5-4
—
Reserved
3-0
CINT
Clear Interrupt Request
Clears the corresponding bit in INT
18.4.5.14 Interrupt Request Register (INT)
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
348 NXP Semiconductors
18.4.5.14.1 Offset
Register Offset
INT 24h
18.4.5.14.2 Function
The INT register provides a bit map for the 16 channels signaling the presence of an
interrupt request for each channel. Depending on the appropriate bit setting in the
transfer-control descriptors, the eDMA engine generates an interrupt on data transfer
completion. The outputs of this register are directly routed to the interrupt controller.
During the interrupt-service routine associated with any given channel, it is the software's
responsibility to clear the appropriate bit, negating the interrupt request. Typically, a
write to the CINT register in the interrupt service routine is used for this purpose.
The state of any given channel's interrupt request is directly affected by writes to this
register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit
position clears the corresponding channel's interrupt request. A zero in any bit position
has no affect on the corresponding channel's current interrupt status. The CINT register is
provided so the interrupt request for a single channel can easily be cleared without the
need to perform a read-modify-write sequence to the INT register.
18.4.5.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INT15
INT14
INT13
INT12
INT11
INT10
INT9
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
W
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.14.4 Fields
Field Function
31-16 Reserved
Table continues on the next page...
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 349
Field Function
—
15
INT15
Interrupt Request 15
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
14
INT14
Interrupt Request 14
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
13
INT13
Interrupt Request 13
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
12
INT12
Interrupt Request 12
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
11
INT11
Interrupt Request 11
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
10
INT10
Interrupt Request 10
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
9
INT9
Interrupt Request 9
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
8
INT8
Interrupt Request 8
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
7
INT7
Interrupt Request 7
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
6
INT6
Interrupt Request 6
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
5
INT5
Interrupt Request 5
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
4
INT4
Interrupt Request 4
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
3
INT3
Interrupt Request 3
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
2
INT2
Interrupt Request 2
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
1
INT1
Interrupt Request 1
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
0
INT0
Interrupt Request 0
0b - The interrupt request for corresponding channel is cleared
1b - The interrupt request for corresponding channel is active
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
350 NXP Semiconductors
18.4.5.15 Error Register (ERR)
18.4.5.15.1 Offset
Register Offset
ERR 2Ch
18.4.5.15.2 Function
The ERR register provides a bit map for the 16 channels, signaling the presence of an
error for each channel. The eDMA engine signals the occurrence of an error condition by
setting the appropriate bit in this register. The outputs of this register are enabled by the
contents of the EEI register, and then routed to the interrupt controller. During the
execution of the interrupt-service routine associated with any DMA errors, it is software's
responsibility to clear the appropriate bit, negating the error-interrupt request. Typically,
a write to the CERR in the interrupt-service routine is used for this purpose. The normal
DMA channel completion indicators (setting the transfer control descriptor DONE flag
and the possible assertion of an interrupt request) are not affected when an error is
detected.
The contents of this register can also be polled because a non-zero value indicates the
presence of a channel error regardless of the state of the EEI fields. The state of any given
channel's error indicators is affected by writes to this register; it is also affected by writes
to the CERR. On writes to the ERR, a one in any bit position clears the corresponding
channel's error status. A zero in any bit position has no affect on the corresponding
channel's current error status. The CERR is provided so the error indicator for a single
channel can easily be cleared.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 351
18.4.5.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ERR1
5
ERR1
4
ERR1
3
ERR1
2
ERR1
1
ERR1
0
ERR
9
ERR
8
ERR
7
ERR
6
ERR
5
ERR
4
ERR
3
ERR
2
ERR
1
ERR
0
W
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.15.4 Fields
Field Function
31-16
—
Reserved
15
ERR15
Error In Channel 15
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
14
ERR14
Error In Channel 14
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
13
ERR13
Error In Channel 13
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
12
ERR12
Error In Channel 12
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
11
ERR11
Error In Channel 11
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
10
ERR10
Error In Channel 10
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
9
ERR9
Error In Channel 9
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
8
ERR8
Error In Channel 8
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
7
ERR7
Error In Channel 7
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
352 NXP Semiconductors
Field Function
6
ERR6
Error In Channel 6
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
5
ERR5
Error In Channel 5
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
4
ERR4
Error In Channel 4
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
3
ERR3
Error In Channel 3
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
2
ERR2
Error In Channel 2
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
1
ERR1
Error In Channel 1
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
0
ERR0
Error In Channel 0
0b - An error in this channel has not occurred
1b - An error in this channel has occurred
18.4.5.16 Hardware Request Status Register (HRS)
18.4.5.16.1 Offset
Register Offset
HRS 34h
18.4.5.16.2 Function
The HRS register provides a bit map for the DMA channels, signaling the presence of a
hardware request for each channel. The hardware request status bits reflect the current
state of the register and qualified (via the ERQ fields) DMA request signals as seen by
the DMA's arbitration logic. This view into the hardware request signals may be used for
debug purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 353
18.4.5.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HRS15
HRS14
HRS13
HRS12
HRS11
HRS10
HRS
9
HRS
8
HRS
7
HRS
6
HRS
5
HRS
4
HRS
3
HRS
2
HRS
1
HRS
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.16.4 Fields
Field Function
31-16
—
Reserved
15
HRS15
Hardware Request Status Channel 15
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 15 is not present
1b - A hardware service request for channel 15 is present
14
HRS14
Hardware Request Status Channel 14
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 14 is not present
1b - A hardware service request for channel 14 is present
13
HRS13
Hardware Request Status Channel 13
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 13 is not present
1b - A hardware service request for channel 13 is present
12
HRS12
Hardware Request Status Channel 12
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 12 is not present
1b - A hardware service request for channel 12 is present
11
HRS11
Hardware Request Status Channel 11
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
354 NXP Semiconductors
Field Function
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 11 is not present
1b - A hardware service request for channel 11 is present
10
HRS10
Hardware Request Status Channel 10
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 10 is not present
1b - A hardware service request for channel 10 is present
9
HRS9
Hardware Request Status Channel 9
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 9 is not present
1b - A hardware service request for channel 9 is present
8
HRS8
Hardware Request Status Channel 8
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 8 is not present
1b - A hardware service request for channel 8 is present
7
HRS7
Hardware Request Status Channel 7
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 7 is not present
1b - A hardware service request for channel 7 is present
6
HRS6
Hardware Request Status Channel 6
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 6 is not present
1b - A hardware service request for channel 6 is present
5
HRS5
Hardware Request Status Channel 5
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 5 is not present
1b - A hardware service request for channel 5 is present
4
HRS4
Hardware Request Status Channel 4
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 4 is not present
1b - A hardware service request for channel 4 is present
3
HRS3
Hardware Request Status Channel 3
Table continues on the next page...
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 355
Field Function
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 3 is not present
1b - A hardware service request for channel 3 is present
2
HRS2
Hardware Request Status Channel 2
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 2 is not present
1b - A hardware service request for channel 2 is present
1
HRS1
Hardware Request Status Channel 1
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 1 is not present
1b - A hardware service request for channel 1 is present
0
HRS0
Hardware Request Status Channel 0
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0b - A hardware service request for channel 0 is not present
1b - A hardware service request for channel 0 is present
18.4.5.17 Enable Asynchronous Request in Stop Register (EARS)
18.4.5.17.1 Offset
Register Offset
EARS 44h
18.4.5.17.2 Function
The EARS register is used to enable or disable the DMA requests in Enable Request
Register (ERQ) by AND'ing the bits of these two registers.
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
356 NXP Semiconductors
18.4.5.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EDREQ_15
EDREQ_14
EDREQ_13
EDREQ_12
EDREQ_11
EDREQ_10
EDREQ_
9
EDREQ_
8
EDREQ_
7
EDREQ_
6
EDREQ_
5
EDREQ_
4
EDREQ_
3
EDREQ_
2
EDREQ_
1
EDREQ_
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.5.17.4 Fields
Field Function
31-16
—
Reserved
15
EDREQ_15
Enable asynchronous DMA request in stop mode for channel 15
0b - Disable asynchronous DMA request for channel 15.
1b - Enable asynchronous DMA request for channel 15.
14
EDREQ_14
Enable asynchronous DMA request in stop mode for channel 14
0b - Disable asynchronous DMA request for channel 14.
1b - Enable asynchronous DMA request for channel 14.
13
EDREQ_13
Enable asynchronous DMA request in stop mode for channel 13
0b - Disable asynchronous DMA request for channel 13.
1b - Enable asynchronous DMA request for channel 13.
12
EDREQ_12
Enable asynchronous DMA request in stop mode for channel 12
0b - Disable asynchronous DMA request for channel 12.
1b - Enable asynchronous DMA request for channel 12.
11
EDREQ_11
Enable asynchronous DMA request in stop mode for channel 11
0b - Disable asynchronous DMA request for channel 11.
1b - Enable asynchronous DMA request for channel 11.
10
EDREQ_10
Enable asynchronous DMA request in stop mode for channel 10
0b - Disable asynchronous DMA request for channel 10.
1b - Enable asynchronous DMA request for channel 10.
9
EDREQ_9
Enable asynchronous DMA request in stop mode for channel 9
0b - Disable asynchronous DMA request for channel 9.
1b - Enable asynchronous DMA request for channel 9.
8
EDREQ_8
Enable asynchronous DMA request in stop mode for channel 8
0b - Disable asynchronous DMA request for channel 8.
1b - Enable asynchronous DMA request for channel 8.
7
EDREQ_7
Enable asynchronous DMA request in stop mode for channel 7
0b - Disable asynchronous DMA request for channel 7.
1b - Enable asynchronous DMA request for channel 7.
6 Enable asynchronous DMA request in stop mode for channel 6
Table continues on the next page...
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 357
Field Function
EDREQ_6 0b - Disable asynchronous DMA request for channel 6.
1b - Enable asynchronous DMA request for channel 6.
5
EDREQ_5
Enable asynchronous DMA request in stop mode for channel 5
0b - Disable asynchronous DMA request for channel 5.
1b - Enable asynchronous DMA request for channel 5.
4
EDREQ_4
Enable asynchronous DMA request in stop mode for channel 4
0b - Disable asynchronous DMA request for channel 4.
1b - Enable asynchronous DMA request for channel 4.
3
EDREQ_3
Enable asynchronous DMA request in stop mode for channel 3.
0b - Disable asynchronous DMA request for channel 3.
1b - Enable asynchronous DMA request for channel 3.
2
EDREQ_2
Enable asynchronous DMA request in stop mode for channel 2.
0b - Disable asynchronous DMA request for channel 2.
1b - Enable asynchronous DMA request for channel 2.
1
EDREQ_1
Enable asynchronous DMA request in stop mode for channel 1.
0b - Disable asynchronous DMA request for channel 1
1b - Enable asynchronous DMA request for channel 1.
0
EDREQ_0
Enable asynchronous DMA request in stop mode for channel 0.
0b - Disable asynchronous DMA request for channel 0.
1b - Enable asynchronous DMA request for channel 0.
18.4.5.18 Channel Priority Register (DCHPRI0 - DCHPRI15)
18.4.5.18.1 Offset
Register Offset
DCHPRI3 100h
DCHPRI2 101h
DCHPRI1 102h
DCHPRI0 103h
DCHPRI7 104h
DCHPRI6 105h
DCHPRI5 106h
DCHPRI4 107h
DCHPRI11 108h
DCHPRI10 109h
DCHPRI9 10Ah
DCHPRI8 10Bh
DCHPRI15 10Ch
DCHPRI14 10Dh
DCHPRI13 10Eh
DCHPRI12 10Fh
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
358 NXP Semiconductors
18.4.5.18.2 Function
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel. The channel priorities
are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher
priority, then 2, 3, etc. Software must program the channel priorities with unique values;
otherwise, a configuration error is reported. The range of the priority value is limited to
the values of 0 through 15.
18.4.5.18.3 Diagram
Bits 7 6 5 4 3 2 1 0
RECP DPA 0CHPRI
W
Reset
See
Register
reset values.
18.4.5.18.4 Register reset values
Register Reset value
DCHPRI0 00h
DCHPRI1 01h
DCHPRI2 02h
DCHPRI3 03h
DCHPRI4 04h
DCHPRI5 05h
DCHPRI6 06h
DCHPRI7 07h
DCHPRI8 08h
DCHPRI9 09h
DCHPRI10 0Ah
DCHPRI11 0Bh
DCHPRI12 0Ch
DCHPRI13 0Dh
DCHPRI14 0Eh
DCHPRI15 0Fh
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 359
18.4.5.18.5 Fields
Field Function
7
ECP
Enable Channel Preemption. This field resets to 0.
0b - Channel n cannot be suspended by a higher priority channel's service request.
1b - Channel n can be temporarily suspended by the service request of a higher priority channel.
6
DPA
Disable Preempt Ability. This field resets to 0.
0b - Channel n can suspend a lower priority channel.
1b - Channel n cannot suspend any channel, regardless of channel priority.
5-4
—
Reserved
3-0
CHPRI
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
18.4.5.19 TCD Source Address (TCD0_SADDR - TCD15_SADDR)
18.4.5.19.1 Offset
For n = 0 to 15:
Register Offset
TCDn_SADDR 1000h + (n × 20h)
18.4.5.19.2 Function
This register contains the source address of the transfer.
18.4.5.19.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSADDR
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSADDR
W
Reset uuuuuuuuuuuuuuuu
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
360 NXP Semiconductors
18.4.5.19.4 Fields
Field Function
31-0
SADDR
Source Address
Memory address pointing to the source data.
18.4.5.20 TCD Signed Source Address Offset (TCD0_SOFF - TCD15_
SOFF)
18.4.5.20.1 Offset
For n = 0 to 15:
Register Offset
TCDn_SOFF 1004h + (n × 20h)
18.4.5.20.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSOFF
W
Reset uuuuuuuuuuuuuuuu
18.4.5.20.3 Fields
Field Function
15-0
SOFF
Source address signed offset
Sign-extended offset applied to the current source address to form the next-state value as each source
read is completed.
18.4.5.21 TCD Transfer Attributes (TCD0_ATTR - TCD15_ATTR)
18.4.5.21.1 Offset
For n = 0 to 15:
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 361
Register Offset
TCDn_ATTR 1006h + (n × 20h)
18.4.5.21.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSMOD SSIZE DMOD DSIZE
W
Reset uuuuuuuuuuuuuuuu
18.4.5.21.3 Fields
Field Function
15-11
SMOD
Source Address Modulo
00000b - Source address modulo feature is disabled
00001-11111b - This value defines a specific address range specified to be the value after SADDR
+ SOFF calculation is performed on the original register value. Setting this field provides the ability
to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the
queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate
value for the queue, freezing the desired number of upper address bits. The value programmed into
this field specifies the number of lower address bits allowed to change. For a circular queue
application, the SOFF is typically set to the transfer size to implement post-increment addressing
with the SMOD function constraining the addresses to a 0-modulo-size range.
10-8
SSIZE
Source data transfer size
NOTE: Using a Reserved value causes a configuration error.
NOTE: The eDMA defaults to privileged data access for all transactions.
000b - 8-bit
001b - 16-bit
010b - 32-bit
011b - Reserved
100b - 16-byte burst
101b - 32-byte burst
110b - Reserved
111b - Reserved
7-3
DMOD
Destination Address Modulo
See the SMOD definition
2-0
DSIZE
Destination data transfer size
See the SSIZE definition
18.4.5.22 TCD Minor Byte Count (Minor Loop Mapping Disabled)
(TCD0_NBYTES_MLNO - TCD15_NBYTES_MLNO)
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
362 NXP Semiconductors
18.4.5.22.1 Offset
For n = 0 to 15:
Register Offset
TCDn_NBYTES_MLNO 1008h + (n × 20h)
18.4.5.22.2 Function
This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, enabled but
not used for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is disabled (CR[EMLM] = 0)
If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and
TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2.
18.4.5.22.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNBYTES
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNBYTES
W
Reset uuuuuuuuuuuuuuuu
18.4.5.22.4 Fields
Field Function
31-0
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel. As a channel activates, the
appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until
the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can,
however, be stalled by using the bandwidth control field, or via preemption. After the minor count is
exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration
count is decremented and restored to the TCD memory. If the major iteration count is completed,
additional processing is performed.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 363
Field Function
NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.
18.4.5.23 TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO -
TCD15_NBYTES_MLOFFNO)
18.4.5.23.1 Offset
For n = 0 to 15:
Register Offset
TCDn_NBYTES_MLOFF
NO
1008h + (n × 20h)
18.4.5.23.2 Function
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, enabled but
not used for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• SMLOE = 0 and DMLOE = 0
If minor loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled,
then refer to the TCD_NBYTES_MLNO register description.
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
364 NXP Semiconductors
18.4.5.23.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
NBYTE
S
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNBYTES
W
Reset uuuuuuuuuuuuuuuu
18.4.5.23.4 Fields
Field Function
31
SMLOE
Source Minor Loop Offset Enable
Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0b - The minor loop offset is not applied to the SADDR
1b - The minor loop offset is applied to the SADDR
30
DMLOE
Destination Minor Loop Offset enable
Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0b - The minor loop offset is not applied to the DADDR
1b - The minor loop offset is applied to the DADDR
29-0
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via
preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
18.4.5.24 TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (TCD0_NBYTES_MLOFFYES - TCD15_NB
YTES_MLOFFYES)
18.4.5.24.1 Offset
For n = 0 to 15:
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 365
Register Offset
TCDn_NBYTES_MLOFF
YES
1008h + (n × 20h)
18.4.5.24.2 Function
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which
register to use depends on whether minor loop mapping is disabled, enabled but not used
for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• Minor loop offset is enabled (SMLOE or DMLOE = 1)
If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then
refer to the TCD_NBYTES_MLNO register description.
18.4.5.24.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
MLOFF
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMLOFF NBYTES
W
Reset uuuuuuuuuuuuuuuu
18.4.5.24.4 Fields
Field Function
31
SMLOE
Source Minor Loop Offset Enable
Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0b - The minor loop offset is not applied to the SADDR
1b - The minor loop offset is applied to the SADDR
30 Destination Minor Loop Offset enable
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
366 NXP Semiconductors
Field Function
DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0b - The minor loop offset is not applied to the DADDR
1b - The minor loop offset is applied to the DADDR
29-10
MLOFF
If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or
destination address to form the next-state value after the minor loop completes.
9-0
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via
preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
18.4.5.25 TCD Last Source Address Adjustment (TCD0_SLAST -
TCD15_SLAST)
18.4.5.25.1 Offset
For n = 0 to 15:
Register Offset
TCDn_SLAST 100Ch + (n × 20h)
18.4.5.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSLAST
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSLAST
W
Reset uuuuuuuuuuuuuuuu
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 367
18.4.5.25.3 Fields
Field Function
31-0
SLAST
Last Source Address Adjustment
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
This register uses two's complement notation; the overflow bit is discarded.
18.4.5.26 TCD Destination Address (TCD0_DADDR - TCD15_DADDR)
18.4.5.26.1 Offset
For n = 0 to 15:
Register Offset
TCDn_DADDR 1010h + (n × 20h)
18.4.5.26.2 Function
This register contains the destination address of the transfer.
18.4.5.26.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDADDR
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDADDR
W
Reset uuuuuuuuuuuuuuuu
18.4.5.26.4 Fields
Field Function
31-0 Destination Address
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
368 NXP Semiconductors
Field Function
DADDR Memory address pointing to the destination data.
18.4.5.27 TCD Signed Destination Address Offset (TCD0_DOFF -
TCD15_DOFF)
18.4.5.27.1 Offset
For n = 0 to 15:
Register Offset
TCDn_DOFF 1014h + (n × 20h)
18.4.5.27.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDOFF
W
Reset uuuuuuuuuuuuuuuu
18.4.5.27.3 Fields
Field Function
15-0
DOFF
Destination Address Signed Offset
Sign-extended offset applied to the current destination address to form the next-state value as each
destination write is completed.
18.4.5.28 TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Disabled) (TCD0_CITER_ELINKNO - TCD15_CITER_
ELINKNO)
18.4.5.28.1 Offset
For n = 0 to 15:
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 369
Register Offset
TCDn_CITER_ELINKNO 1016h + (n × 20h)
18.4.5.28.2 Function
This register contains the minor-loop channel-linking configuration and the channel's
current iteration count. It is the same register as TCD Current Minor Loop Link, Major
Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD15_CITER_
ELINKYES), but its fields are defined differently based on the state of the ELINK field.
If the ELINK field is cleared, this register is defined as follows.
18.4.5.28.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ELINK
CITER
W
Reset uuuuuuuuuuuuuuuu
18.4.5.28.4 Fields
Field Function
15
ELINK
Enable channel-to-channel linking on minor-loop complete
As the channel completes the minor loop, this flag enables linking to another channel, defined by the
LINKCH field. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
linking.
NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported.
0b - The channel-to-channel linking is disabled
1b - The channel-to-channel linking is enabled
14-0
CITER
Current Major Iteration Count
This field is the current major loop count for the channel. It is decremented each time the minor loop is
completed and updated in the transfer control descriptor memory. After the major iteration count is
exhausted, the channel performs a number of operations, for example, final source and destination
address calculations, optionally generating an interrupt to signal channel completion before reloading the
CITER field from the Beginning Iteration Count (BITER) field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
370 NXP Semiconductors
18.4.5.29 TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (TCD0_CITER_ELINKYES - TCD15_CI
TER_ELINKYES)
18.4.5.29.1 Offset
For n = 0 to 15:
Register Offset
TCDn_CITER_ELINKYE
S
1016h + (n × 20h)
18.4.5.29.2 Function
This register contains the minor-loop channel-linking configuration and the channel's
current iteration count. It is the same register as TCD Current Minor Loop Link, Major
Loop Count (Channel Linking Disabled) (TCD0_CITER_ELINKNO - TCD15_CITER_
ELINKNO), but its fields are defined differently based on the state of the ELINK field. If
the ELINK field is set, this register is defined as follows.
18.4.5.29.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ELINK
LINKCH
CITER
W
0
Reset uuuuuuuuuuuuuuuu
18.4.5.29.4 Fields
Field Function
15
ELINK
Enable channel-to-channel linking on minor-loop complete
As the channel completes the minor loop, this flag enables linking to another channel, defined by the
LINKCH field. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
linking.
NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported.
Table continues on the next page...
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 371
Field Function
0b - The channel-to-channel linking is disabled
1b - The channel-to-channel linking is enabled
14-13
—
Reserved
12-9
LINKCH
Minor Loop Link Channel Number
If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request to the channel defined by this field by setting that channel's
TCDn_CSR[START] bit.
8-0
CITER
Current Major Iteration Count
This field is the current major loop count for the channel. It is decremented each time the minor loop is
completed and updated in the transfer control descriptor memory. After the major iteration count is
exhausted, the channel performs a number of operations, for example, final source and destination
address calculations, optionally generating an interrupt to signal channel completion before reloading the
CITER field from the Beginning Iteration Count (BITER) field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
18.4.5.30 TCD Last Destination Address Adjustment/Scatter Gather
Address (TCD0_DLASTSGA - TCD15_DLASTSGA)
18.4.5.30.1 Offset
For n = 0 to 15:
Register Offset
TCDn_DLASTSGA 1018h + (n × 20h)
18.4.5.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDLASTSGA
W
Reset uuuuuuuuuuuuuuuu
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDLASTSGA
W
Reset uuuuuuuuuuuuuuuu
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
372 NXP Semiconductors
18.4.5.30.3 Fields
Field Function
31-0
DLASTSGA
DLASTSGA
Destination last address adjustment or the memory address for the next transfer control descriptor to be
loaded into this channel (scatter/gather).
If (TCDn_CSR[ESG] = 0) then:
• Adjustment value added to the destination address at the completion of the major iteration count.
This value can apply to restore the destination address to the initial value or adjust the address to
reference the next data structure.
• This field uses two's complement notation for the final destination address adjustment.
Otherwise:
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a
configuration error is reported.
18.4.5.31 TCD Control and Status (TCD0_CSR - TCD15_CSR)
18.4.5.31.1 Offset
For n = 0 to 15:
Register Offset
TCDn_CSR 101Ch + (n × 20h)
18.4.5.31.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BWC
MAJORLINKCH
DONE
ACTIVE
MAJORELINK
ES
G
DREQ
INTHALF
INTMAJOR
START
W
0
W0C
Reset uuuuuuuuuuuuuuuu
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 373
18.4.5.31.3 Fields
Field Function
15-14
BWC
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00b - No eDMA engine stalls.
01b - Reserved
10b - eDMA engine stalls for 4 cycles after each R/W.
11b - eDMA engine stalls for 8 cycles after each R/W.
13-12
—
Reserved
11-8
MAJORLINKCH
Major Loop Link Channel Number
If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel's TCDn_CSR[START] bit.
7
DONE
Channel Done
This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count
reaches zero. The software clears it, or the hardware when the channel is activated.
NOTE: This bit must be cleared to write the MAJORELINK or ESG bits.
6
ACTIVE
Channel Active
This flag signals the channel is currently in execution. It is set when channel service begins, and is
cleared by the eDMA as the minor loop completes or when any error condition is detected.
5
MAJORELINK
Enable channel-to-channel linking on major loop complete
As the channel completes the major loop, this flag enables the linking to another channel, defined by
MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] bit of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while
the TCDn_CSR[DONE] bit is set.
0b - The channel-to-channel linking is disabled.
1b - The channel-to-channel linking is enabled.
4
ESG
Enable Scatter/Gather Processing
As the channel completes the major loop, this flag enables scatter/gather processing in the current
channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure loaded as the transfer control descriptor into the local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written
to while the TCDn_CSR[DONE] bit is set.
0b - The current channel's TCD is normal format.
1b - The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a
memory pointer to the next TCD to be loaded into this channel after the major loop completes its
execution.
Table continues on the next page...
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
374 NXP Semiconductors
Field Function
3
DREQ
Disable Request
If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current
major iteration count reaches zero.
0b - The channel's ERQ bit is not affected.
1b - The channel's ERQ bit is cleared when the major loop is complete.
2
INTHALF
Enable an interrupt when major counter is half complete.
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT
register when the current major iteration count reaches the halfway point. Specifically, the comparison
performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
provided to support double-buffered, also known as ping-pong, schemes or other types of data movement
where the processor needs an early indication of the transfer's progress.
NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead.
0b - The half-point interrupt is disabled.
1b - The half-point interrupt is enabled.
1
INTMAJOR
Enable an interrupt when major iteration count completes.
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when
the current major iteration count reaches zero.
0b - The end-of-major loop interrupt is disabled.
1b - The end-of-major loop interrupt is enabled.
0
START
Channel Start
If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag
after the channel begins execution.
0b - The channel is not explicitly started.
1b - The channel is explicitly started via a software initiated service request.
18.4.5.32 TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (TCD0_BITER_ELINKNO - TCD1
5_BITER_ELINKNO)
18.4.5.32.1 Offset
For n = 0 to 15:
Register Offset
TCDn_BITER_ELINKNO 101Eh + (n × 20h)
18.4.5.32.2 Function
If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined as
follows.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 375
18.4.5.32.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ELINK
BITE
R
W
Reset uuuuuuuuuuuuuuuu
18.4.5.32.4 Fields
Field Function
15
ELINK
Enables channel-to-channel linking on minor loop complete
As the channel completes the minor loop, this flag enables the linking to another channel, defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER
value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link
mechanism is suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
0b - The channel-to-channel linking is disabled
1b - The channel-to-channel linking is enabled
14-0
BITER
Starting Major Iteration Count
As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0)
field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents
of this field are reloaded into the CITER field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field is reloaded into the CITER field. If the channel is configured to execute a
single service request, the initial values of BITER and CITER should be 0x0001.
18.4.5.33 TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled) (TCD0_BITER_ELINKYES - TCD1
5_BITER_ELINKYES)
18.4.5.33.1 Offset
For n = 0 to 15:
Register Offset
TCDn_BITER_ELINKYE
S
101Eh + (n × 20h)
Memory map/register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
376 NXP Semiconductors
18.4.5.33.2 Function
If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows.
18.4.5.33.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ELINK
LINKCH
BITE
R
W
0
Reset uuuuuuuuuuuuuuuu
18.4.5.33.4 Fields
Field Function
15
ELINK
Enables channel-to-channel linking on minor loop complete
As the channel completes the minor loop, this flag enables the linking to another channel, defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER
value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link
mechanism is suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
0b - The channel-to-channel linking is disabled
1b - The channel-to-channel linking is enabled
14-13
—
Reserved
12-9
LINKCH
Link Channel Number
If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request at the channel defined by this field by setting that channel's
TCDn_CSR[START] bit.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
8-0
BITER
Starting major iteration count
As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0)
field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents
of this field are reloaded into the CITER field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field. If the channel is configured to execute a
single service request, the initial values of BITER and CITER should be 0x0001.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 377
18.5 Functional description
The operation of the eDMA is described in the following subsections.
18.5.1 eDMA basic data flow
The basic flow of a data transfer can be partitioned into three segments.
As shown in the following diagram, the first segment involves the channel activation:
1
eDMA Engine
Data Path
eDMA
0
Program Model/
64
Control
n-1
To/From Crossbar Switch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
Internal Peripheral Bus
eDMA Peripheral
Request eDMA Done
Transfer
Control
Descriptor (TCD)
Figure 18-2. eDMA operation, part 1
This example uses the assertion of the eDMA peripheral request signal to request service
for channel n. Channel activation via software and the TCDn_CSR[START] bit follows
the same basic flow as peripheral requests. The eDMA request input signal is registered
internally and then routed through the eDMA engine: first through the control module,
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
378 NXP Semiconductors
then into the program model and channel arbitration. In the next cycle, the channel
arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is
complete, the activated channel number is sent through the address path and converted
into the required address to access the local memory for TCDn. Next, the TCD memory
is accessed and the required descriptor read from the local memory and loaded into the
eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the
address path channel x or y registers.
The following diagram illustrates the second part of the basic data flow:
1
eDMA Engine
Data Path
eDMA
0
Program Model/
64
Control
n-1
To/From Crossbar Switch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
eDMA Peripheral
Request eDMA Done
Transfer
Control
Descriptor (TCD)
Internal Peripheral Bus
Figure 18-3. eDMA operation, part 2
The modules associated with the data transfer (address path, data path, and control)
sequence through the required source reads and destination writes to perform the actual
data movement. The source reads are initiated and the fetched data is temporarily stored
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 379
in the data path block until it is gated onto the internal bus during the destination write.
This source read/destination write processing continues until the minor byte count has
transferred.
After the minor byte count has moved, the final phase of the basic data flow is performed.
In this segment, the address path logic performs the required updates to certain fields in
the appropriate TCD, for example, SADDR, DADDR, CITER. If the major iteration
count is exhausted, additional operations are performed. These include the final address
adjustments and reloading of the BITER field into the CITER. Assertion of an optional
interrupt request also occurs at this time, as does a possible fetch of a new TCD from
memory using the scatter/gather address pointer included in the descriptor (if scatter/
gather is enabled). The updates to the TCD memory and the assertion of an interrupt
request are shown in the following diagram.
1
eDMA Engine
Data Path
eDMA
0
Program Model/
64
Control
n-1
To/From Crossbar Switch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
eDMA Peripheral
Request eDMA Done
Transfer
Control
Descriptor (TCD)
Internal Peripheral Bus
Figure 18-4. eDMA operation, part 3
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
380 NXP Semiconductors
18.5.2 Fault reporting and handling
Channel errors are reported in the Error Status register (DMAx_ES) and can be caused
by:
• A configuration error, which is an illegal setting in the transfer-control descriptor or
an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle
A configuration error is reported when the starting source or destination address, source
or destination offsets, minor loop byte count, or the transfer size represent an inconsistent
state. Each of these possible causes are detailed below:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
• All source reads and destination writes must be configured to the natural boundary of
the programmed transfer size respectively.
• In fixed arbitration mode, a configuration error is caused by any two channel
priorities being equal. All channel priority levels must be unique when fixed
arbitration mode is enabled.
NOTE
When two channels have the same priority, a channel
priority error exists and will be reported in the Error Status
register. However, the channel number will not be reported
in the Error Status register. When all of the channel
priorities within a group are not unique, the channel
number selected by arbitration in undetermined.
To aid in Channel Priority Error (CPE) debug, set the Halt
On Error bit in the DMA’s Control Register. If all of the
channel priorities within a group are not unique, the DMA
will be halted after the CPE error is recorded. The DMA
will remain halted and will not process any channel service
requests. Once all of the channel priorities are set to unique
numbers, the DMA may be enabled again by clearing the
Halt bit.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 381
• If a scatter/gather operation is enabled upon channel completion, a configuration
error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-
byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration
error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does
not equal the TCDn_BITER[E_LINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop
link errors, report as the channel activates and asserts an error interrupt request. A scatter/
gather configuration error is reported when the scatter/gather operation begins at major
loop completion when properly enabled. A minor loop channel link configuration error is
reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and
the appropriate bus error flag set. In this case, the state of the channel's transfer control
descriptor is updated by the eDMA engine with the current source address, destination
address, and current iteration count at the point of the fault. When a system bus error
occurs, the channel terminates after the next transfer. Due to pipeline effect, the next
transfer is already in progress when the bus error is received by the eDMA. If a bus error
occurs on the last read prior to beginning the write sequence, the write executes using the
data captured during the bus error. If a bus error occurs on the last write prior to
switching to the next read sequence, the read sequence executes before the channel
terminates due to the destination bus error.
A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer
request is recognized, the DMA engine stops processing the channel. The current read-
write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of
a major or minor loop, the cancel request is discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the Error Status register
(DMAx_ES) is updated with the cancelled channel number and ECX is set. The TCD of a
cancelled channel contains the source and destination addresses of the last transfer saved
in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because
the aforementioned fields no longer represent the original parameters. When a transfer is
cancelled by the error cancel transfer mechanism, the channel number is loaded into
DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be
generated if enabled.
NOTE
The cancel transfer request allows the user to stop a large data
transfer in the event the full data transfer is no longer needed.
The cancel transfer bit does not abort the channel. It simply
stops the transferring of data and then retires the channel
through its normal shutdown sequence. The application
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
382 NXP Semiconductors
software must handle the context of the cancel. If an interrupt is
desired (or not), then the interrupt should be enabled (or
disabled) before the cancel request. The application software
must clean up the transfer control descriptor since the full
transfer did not occur.
The occurrence of any error causes the eDMA engine to stop normal processing of the
active channel immediately (it goes to its error processing states and the transaction to the
system bus still has pipeline effect), and the appropriate channel bit in the eDMA error
register is asserted. At the same time, the details of the error condition are loaded into the
Error Status register (DMAx_ES). The major loop complete indicators, setting the
transfer control descriptor DONE flag and the possible assertion of an interrupt request,
are not affected when an error is detected. After the error status has been updated, the
eDMA engine continues operating by servicing the next appropriate channel. A channel
that experiences an error condition is not automatically disabled. If a channel is
terminated by an error and then issues another service request before the error is fixed,
that channel executes and terminates with the same error condition.
18.5.3 Channel preemption
Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit.
Channel preemption allows the executing channel’s data transfers to temporarily suspend
in favor of starting a higher priority channel. After the preempting channel has completed
all its minor loop data transfers, the preempted channel is restored and resumes
execution. After the restored channel completes one read/write sequence, it is again
eligible for preemption. If any higher priority channel is requesting service, the restored
channel is suspended and the higher priority channel is serviced. Nested preemption, that
is, attempting to preempt a preempting channel, is not supported. After a preempting
channel begins execution, it cannot be preempted. Preemption is available only when
fixed arbitration is selected.
A channel’s ability to preempt another channel can be disabled by setting
DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot
suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s
ECP setting. This allows for a pool of low priority, large data-moving channels to be
defined. These low priority channels can be configured to not preempt each other, thus
preventing a low priority channel from consuming the preempt slot normally available to
a true, high priority channel.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 383
18.6 Initialization/application information
The following sections discuss initialization of the eDMA and programming
considerations.
18.6.1 eDMA initialization
To initialize the eDMA:
1. Write to the CR if a configuration other than the default is desired.
2. Write the channel priority levels to the DCHPRIn registers if a configuration other
than the default is desired.
3. Enable error interrupts in the EEI register if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the ERQ register.
6. Request channel service via either:
•Software: setting the TCDn_CSR[START]
• Hardware: slave device asserting its eDMA peripheral request signal
After any channel requests service, a channel is selected for execution based on the
arbitration and priority levels written into the programmer's model. The eDMA engine
reads the entire TCD, including the TCD control and status fields, as shown in the
following table, for the selected channel into its internal address path module.
As the TCD is read, the first transfer is initiated on the internal bus, unless a
configuration error is detected. Transfers from the source, as defined by TCDn_SADDR,
to the destination, as defined by TCDn_DADDR, continue until the number of bytes
specified by TCDn_NBYTES are transferred.
When the transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted,
further post processing executes, such as interrupts, major loop channel linking, and
scatter/gather operations, if enabled.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
384 NXP Semiconductors
Table 18-5. TCD Control and Status fields
TCDn_CSR field
name Description
START Control bit to start channel explicitly when using a software initiated DMA service (Automatically
cleared by hardware)
ACTIVE Status bit indicating the channel is currently in execution
DONE Status bit indicating major loop completion (cleared by software when using a software initiated
DMA service)
D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated
DMA service
BWC Control bits for throttling bandwidth control of a channel
E_SG Control bit to enable scatter-gather feature
INT_HALF Control bit to enable interrupt when major loop is half complete
INT_MAJ Control bit to enable interrupt when major loop completes
The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
DMA request
DMA request
DMA request
Minor loop Minor loop Minor loop
Major loop
Current major
loop iteration
count (CITER)
3
2
1
Source or destination memory
Figure 18-5. Example of multiple loop iterations
The following figure lists the memory array terms and how the TCD settings interrelate.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 385
xADDR: (Starting address)
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
Minor loop
(NBYTES in
minor loop,
often the same
value as xSIZE)
Minor loop
Last minor loop
Offset (xOFF): number of bytes added to
current address after each transfer
(often the same value as xSIZE)
Each DMA source (S) and
destination (D) has its own:
Address (xADDR)
Size (xSIZE)
Offset (xOFF)
Modulo (xMOD)
Last Address Adjustment (xLAST)
where x = S or D
Peripheral queues typically
have size and offset equal
to NBYTES.
xSIZE: (size of one
data transfer)
Figure 18-6. Memory array terms
18.6.2 Programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency
in the descriptor data. Most programming errors are reported on a per channel basis with
the exception of channel priority error (ES[CPE]).
For all error types other than channel priority error, the channel number causing the error
is recorded in the Error Status register (DMAx_ES). If the error source is not removed
before the next activation of the problem channel, the error is detected and recorded
again.
If priority levels are not unique, when any channel requests service, a channel priority
error is reported. The highest channel priority with an active request is selected, but the
lowest numbered channel with that priority is selected by arbitration and executed by the
eDMA engine. The hardware service request handshake signals, error interrupts, and
error reporting is associated with the selected channel.
18.6.3 Arbitration mode considerations
This section discusses arbitration considerations for the eDMA.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
386 NXP Semiconductors
18.6.3.1 Fixed channel arbitration
In this mode, the channel service request from the highest priority channel is selected to
execute.
18.6.3.2 Round-robin channel arbitration
Channels are serviced starting with the highest channel number and rotating through to
the lowest channel number without regard to the channel priority levels.
18.6.4 Performing DMA transfers
This section presents examples on how to perform DMA transfers with the eDMA.
18.6.4.1 Single request
To perform a simple transfer of n bytes of data with one activation, set the major loop to
one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel
service request is acknowledged and the channel is selected to execute. After the transfer
is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly
enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The
eDMA is programmed for one iteration of the major loop transferring 16 bytes per
iteration. The source memory has a byte wide memory port located at 0x1000. The
destination memory has a 32-bit port located at 0x2000. The address offsets are
programmed in increments to match the transfer size: one byte for the source and four
bytes for the destination. The final source and destination addresses are adjusted to return
to their beginning values.
TCDn_CITER = TCDn_BITER = 1
TCDn_NBYTES = 16
TCDn_SADDR = 0x1000
TCDn_SOFF = 1
TCDn_ATTR[SSIZE] = 0
TCDn_SLAST = -16
TCDn_DADDR = 0x2000
TCDn_DOFF = 4
TCDn_ATTR[DSIZE] = 2
TCDn_DLAST_SGA= –16
TCDn_CSR[INT_MAJ] = 1
TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized)
All other TCDn fields = 0
This generates the following event sequence:
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 387
1. User write to the TCDn_CSR[START] bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source-to-destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32-bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32-bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32-bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop
complete.
6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 1 (TCDn_BITER).
7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1,
INT[n] = 1.
8. The channel retires and the eDMA goes idle or services the next channel.
18.6.4.2 Multiple requests
The following example transfers 32 bytes via two hardware requests, but is otherwise the
same as the previous example. The only fields that change are the major loop iteration
count and the final address offsets. The eDMA is programmed for two iterations of the
major loop transferring 16 bytes per iteration. After the channel's hardware requests are
enabled in the ERQ register, the slave device initiates channel service requests.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
388 NXP Semiconductors
TCDn_CITER = TCDn_BITER = 2
TCDn_SLAST = –32
TCDn_DLAST_SGA = –32
This would generate the following sequence of events:
1. First hardware, that is, eDMA peripheral, request for channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCDn data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32-bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32-bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32-bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32-bits to location 0x200C → last iteration of the minor loop.
6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010,
TCDn_CITER = 1.
7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0.
8. The channel retires → one iteration of the major loop. The eDMA goes idle or
services the next channel.
9. Second hardware, that is, eDMA peripheral, requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 389
12. eDMA engine reads: channel TCD data from local memory to internal register file.
13. The source to destination transfers are executed as follows:
a. Read byte from location 0x1010, read byte from location 0x1011, read byte from
0x1012, read byte from 0x1013.
b. Write 32-bits to location 0x2010 → first iteration of the minor loop.
c. Read byte from location 0x1014, read byte from location 0x1015, read byte from
0x1016, read byte from 0x1017.
d. Write 32-bits to location 0x2014 → second iteration of the minor loop.
e. Read byte from location 0x1018, read byte from location 0x1019, read byte from
0x101A, read byte from 0x101B.
f. Write 32-bits to location 0x2018 → third iteration of the minor loop.
g. Read byte from location 0x101C, read byte from location 0x101D, read byte
from 0x101E, read byte from 0x101F.
h. Write 32-bits to location 0x201C → last iteration of the minor loop → major loop
complete.
14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 2 (TCDn_BITER).
15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] =
1.
16. The channel retires → major loop complete. The eDMA goes idle or services the next
channel.
18.6.4.3 Using the modulo feature
The modulo feature of the eDMA provides the ability to implement a circular data queue
in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and
destination in the TCD, and it specifies which lower address bits increment from their
original value after the address+offset calculation. All upper address bits remain the same
as in the original value. A setting of 0 for this field disables the modulo feature.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
390 NXP Semiconductors
The following table shows how the transfer addresses are specified based on the setting
of the MOD field. Here a circular buffer is created where the address wraps to the
original value while the 28 upper address bits (0x1234567x) retain their original value. In
this example the source address is set to 0x12345670, the offset is set to 4 bytes and the
MOD field is set to 4, allowing for a 24 byte (16-byte) size queue.
Table 18-6. Modulo example
Transfer Number Address
1 0x12345670
2 0x12345674
3 0x12345678
4 0x1234567C
5 0x12345670
6 0x12345674
18.6.5 Monitoring transfer descriptor status
This section discusses how to monitor eDMA status.
18.6.5.1 Testing for minor loop completion
There are two methods to test for minor loop completion when using software initiated
service requests. The first is to read the TCDn_CITER field and test for a change.
Another method may be extracted from the sequence shown below. The second method is
to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop-
complete condition is indicated by both bits reading zero after the TCDn_CSR[START]
was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active
status may be missed if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
Stage TCDn_CSR bits State
START ACTIVE DONE
1 1 0 0 Channel service request via software
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 391
The best method to test for minor-loop completion when using hardware, that is,
peripheral, initiated service requests is to read the TCDn_CITER field and test for a
change. The hardware request and acknowledge handshake signals are not visible in the
programmer's model.
The TCD status bits execute the following sequence for a hardware-activated channel:
Stage TCDn_CSR bits State
START ACTIVE DONE
1 0 0 0 Channel service request via hardware (peripheral
request asserted)
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
For both activation types, the major-loop-complete status is explicitly indicated via the
TCDn_CSR[DONE] bit.
The TCDn_CSR[START] bit is cleared automatically when the channel begins execution
regardless of how the channel activates.
18.6.5.2 Reading the transfer descriptors of active channels
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES
values if read while a channel executes. The true values of the SADDR, DADDR, and
NBYTES are the values the eDMA engine currently uses in its internal register file and
not the values in the TCD local memory for that channel. The addresses, SADDR and
DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an
indication of the progress of the transfer. All other values are read back from the TCD
local memory.
18.6.5.3 Checking channel preemption status
Preemption is available only when fixed arbitration is selected as the channel arbitration
mode. A preemptive situation is one in which a preempt-enabled channel runs and a
higher priority request becomes active. When the eDMA engine is not operating in fixed
channel arbitration mode, the determination of the actively running relative priority
outstanding requests become undefined. Channel priorities are treated as equal, that is,
constantly rotating, when Round-Robin Arbitration mode is selected.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
392 NXP Semiconductors
The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout
the preemption. The preempted channel is temporarily suspended while the preempting
channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set
simultaneously in the global TCD map, a higher priority channel is actively preempting a
lower priority channel.
18.6.6 Channel Linking
Channel linking (or chaining) is a mechanism where one channel sets the
TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service
request for that channel. When properly enabled, the EDMA engine automatically
performs this operation at the major or minor loop completion.
The minor loop channel linking occurs at the completion of the minor loop (or one
iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a
minor loop link is requested. When enabled, the channel link is made after each iteration
of the major loop except for the last. When the major loop is exhausted, only the major
loop channel link fields are used to determine if a channel link should be made. For
example, the initial fields of:
TCDn_CITER[E_LINK] = 1
TCDn_CITER[LINKCH] = 0xC
TCDn_CITER[CITER] value = 0x4
TCDn_CSR[MAJOR_E_LINK] = 1
TCDn_CSR[MAJOR_LINKCH] = 0x7
executes as:
1. Minor loop done → set TCD12_CSR[START] bit
2. Minor loop done → set TCD12_CSR[START] bit
3. Minor loop done → set TCD12_CSR[START] bit
4. Minor loop done, major loop done→ set TCD7_CSR[START] bit
When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the
TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count.
When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the
TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The
bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER
value to increase the range of the CITER.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 393
Note
The TCDn_CITER[E_LINK] bit and the
TCDn_BITER[E_LINK] bit must equal or a configuration error
is reported. The CITER and BITER vector widths must be
equal to calculate the major loop, half-way done interrupt point.
The following table summarizes how a DMA channel can link to another DMA channel,
i.e, use another channel's TCD, at the end of a loop.
Table 18-7. Channel Linking Parameters
Desired Link
Behavior TCD Control Field Name Description
Link at end of
Minor Loop
CITER[E_LINK] Enable channel-to-channel linking on minor loop completion (current
iteration)
CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration)
Link at end of
Major Loop
CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion
CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop
18.6.7 Dynamic programming
This section provides recommended methods to change the programming model during
channel execution.
18.6.7.1 Dynamically changing the channel priority
The following two options are recommended for dynamically changing channel priority
levels:
1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities,
then switch back to Fixed Arbitration mode,
2. Disable all the channels, change the channel priorities, then enable the appropriate
channels.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
394 NXP Semiconductors
18.6.7.2 Dynamic channel linking
Dynamic channel linking is the process of setting the TCDn_CSR[MAJORELINK] bit
during channel execution (see the diagram in TCD structure). This bit is read from the
TCD local memory at the end of channel execution, thus allowing the user to enable the
feature during channel execution.
Because the user is allowed to change the configuration during execution, a coherency
model is needed. Consider the scenario where the user attempts to execute a dynamic
channel link by enabling the TCDn_CSR[MAJORELINK] bit at the same time the
eDMA engine is retiring the channel. The TCDn_CSR[MAJORELINK] would be set in
the programmer’s model, but it would be unclear whether the actual link was made
before the channel retired.
The following coherency model is recommended when executing a dynamic channel link
request.
1. Write 1 to the TCDn_CSR[MAJORELINK] bit.
2. Read back the TCDn_CSR[MAJORELINK] bit.
3. Test the TCDn_CSR[MAJORELINK] request status:
• If TCDn_CSR[MAJORELINK] = 1, the dynamic link attempt was successful.
• If TCDn_CSR[MAJORELINK] = 0, the attempted dynamic link did not succeed
(the channel was already retiring).
For this request, the TCD local memory controller forces the
TCDn_CSR[MAJORELINK] bit to zero on any writes to a channel’s TCD.word7 after
that channel’s TCD.done bit is set, indicating the major loop is complete.
NOTE
The user must clear the The TCDn_CSR[DONE] bit before
writing the TCDn_CSR[MAJORELINK] bit. The
TCDn_CSR[DONE] bit is cleared automatically by the eDMA
engine after a channel begins execution.
18.6.7.3 Dynamic scatter/gather
Scatter/gather is the process of automatically loading a new TCD into a channel. It allows
a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA
data to multiple destinations or gather it from multiple sources. When scatter/gather is
enabled and the channel has finished its major loop, a new TCD is fetched from system
memory and loaded into that channel’s descriptor location in eDMA programmer’s
model, thus replacing the current descriptor.
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 395
Because the user is allowed to change the configuration during execution, a coherency
model is needed. Consider the scenario where the user attempts to execute a dynamic
scatter/gather operation by enabling the TCDn_CSR[ESG] bit at the same time the
eDMA engine is retiring the channel. The ESG bit would be set in the programmer’s
model, but it would be unclear whether the actual scatter/gather request was honored
before the channel retired.
Two methods for this coherency model are shown in the following subsections. Method 1
has the advantage of reading the MAJORLINKCH field and the ESG bit with a single
read. For both dynamic channel linking and scatter/gather requests, the TCD local
memory controller forces the TCD MAJOR.E_LINK and E_SG bits to zero on any writes
to a channel’s TCD word 7 if that channel’s TCD.DONE bit is set indicating the major
loop is complete.
NOTE
The user must clear the TCDn_CSR[DONE] bit before writing
the MAJORELINK or ESG bits. The TCDn_CSR[DONE] bit is
cleared automatically by the eDMA engine after a channel
begins execution.
18.6.7.3.1 Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model described here
may be used for a dynamic scatter/gather request.
When the TCDn_CSR[MAJORELINK] bit is zero, the TCDn_CSR[MAJORLINKCH]
field is not used by the eDMA. In this case, the MAJORLINKCH field may be used for
other purposes. This method uses the MAJORLINKCH field as a TCD identification
(ID).
1. When the descriptors are built, write a unique TCD ID in the
TCDn_CSR[MAJORLINKCH] field for each TCD associated with a channel using
dynamic scatter/gather.
2. Write 1b to the TCDn_CSR[DREQ] bit.
Should a dynamic scatter/gather attempt fail, setting the DREQ bit will prevent a
future hardware activation of this channel. This stops the channel from executing
with a destination address (DADDR) that was calculated using a scatter/gather
address (written in the next step) instead of a dlast final offset value.
3. Write the TCDn_DLASTSGA register with the scatter/gather address.
4. Write 1b to the TCDn_CSR[ESG] bit.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
396 NXP Semiconductors
5. Read back the 16 bit TCD control/status field.
6. Test the ESG request status and MAJORLINKCH value in the TCDn_CSR register:
If ESG = 1b, the dynamic link attempt was successful.
If ESG = 0b and the MAJORLINKCH (ID) did not change, the attempted dynamic
link did not succeed (the channel was already retiring).
If ESG = 0b and the MAJORLINKCH (ID) changed, the dynamic link attempt was
successful (the new TCD’s E_SG value cleared the ESG bit).
18.6.7.3.2 Method 2 (channel using major loop channel linking)
For a channel using major loop channel linking, the coherency model described here may
be used for a dynamic scatter/gather request. This method uses the TCD.DLAST_SGA
field as a TCD identification (ID).
1. Write 1b to the TCDn_CSR[DREQ] bit.
Should a dynamic scatter/gather attempt fail, setting the DREQ bit will prevent a
future hardware activation of this channel. This stops the channel from executing
with a destination address (DADDR) that was calculated using a scatter/gather
address (written in the next step) instead of a dlast final offset value.
2. Write the TCDn_DLASTSGA register with the scatter/gather address.
3. Write 1b to the TCDn_CSR[ESG] bit.
4. Read back the ESG bit.
5. Test the ESG request status:
If ESG = 1b, the dynamic link attempt was successful.
If ESG = 0b, read the 32 bit TCDn_DLASTSGA field.
If ESG = 0b and the TCDn_DLASTSGA did not change, the attempted dynamic link
did not succeed (the channel was already retiring).
If ESG = 0b and the TCDn_DLASTSGA changed, the dynamic link attempt was
successful (the new TCD’s E_SG value cleared the ESG bit).
Chapter 18 Enhanced Direct Memory Access (eDMA)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 397
18.6.8 Suspend/resume a DMA channel with active hardware
service requests
The DMA allows the user to move data from memory or peripheral registers to another
location in memory or peripheral registers without CPU interaction. Once the DMA and
peripherals have been configured and are active, it is rare to suspend a peripheral's
service request dynamically. In this scenario, there are certain restrictions to disabling a
DMA hardware service request. For coherency, a specific procedure must be followed.
This section provides guidance on how to coherently suspend and resume a Direct
Memory Access (DMA) channel when the DMA is triggered by a slave module such as
the Serial Peripheral Interface (SPI), ADC, or other module.
18.6.8.1 Suspend an active DMA channel
To suspend an active DMA channel:
1. Stop the DMA service request at the peripheral first. Confirm it has been disabled by
reading back the appropriate register in the peripheral.
2. Check the DMA's Hardware Request Status Register (DMA_HRSn) to ensure there
is no service request to the DMA channel being suspended. Then disable the
hardware service request by clearing the ERQ bit on appropriate DMA channel.
18.6.8.2 Resume a DMA channel
To resume a DMA channel:
1. Enable the DMA service request on the appropriate channel by setting the its ERQ
bit.
2. Enable the DMA service request at the peripheral.
For example, assume the SPI is set as a master for transmitting data via a DMA service
request when the SPI_TXFIFO has an empty slot. The DMA will transfer the next
command and data to the TXFIFO upon the request. If the user needs to suspend the
DMA/SPI transfer loop, perform the following steps:
1. Disable the DMA service request at the source by writing 0 to
SPI_RSER[TFFF_RE]. Confirm that SPI_RSER[TFFF_RE] is 0.
2. Ensure there is no DMA service request from the SPI by verifying that
DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present,
disable the DMA channel by clearing the channel's ERQ bit. If a service request is
present, wait until the request has been processed and the HRS bit reads zero.
Initialization/application information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
398 NXP Semiconductors
Chapter 19
Trigger MUX Control (TRGMUX)
Chip-specific TRGMUX information
19.1.1 Module interconnectivity
The TRGMUX provides an extremely flexible mechanism for connecting various trigger
sources to multiple pins/peripherals.
See Figure 19-2 and Figure 19-3 for available input triggers.
With the TRGMUX, each peripheral that accepts external triggers usually has one
specific 32-bit trigger control register. Each control register supports up to four triggers,
and each trigger can be selected from the available input triggers.
The following figure shows the main structure of TRGMUX, using Module_A as an
example.
19.1
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 399
0
63
• • •
0
63
• • •
0
63
• • •
0
63
• • •
Module_A
LK SELx SELx SELx SELx
TRGMUX_Reg_ModuleA
Figure 19-1. TRGMUX structure example (64 inputs)
NOTE
Each TRGMUX control register supports up to four trigger
channels, but each module does not necessarily implement all
four triggers. Modules that need more than four trigger inputs
(such as for external output) have multiple control registers.
The following figures show the superset of trigger inputs, outputs, and control registers
for the S32K1xx series. See attached S32K1xx_Trigger_Muxing.xlsx for details on
recommendations which must be adhered while using the triggering scheme.
Chip-specific TRGMUX information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
400 NXP Semiconductors
in64
FTM4_INIT_TRIG
FTM4_EXT_TRIG
FTM5_EXT_TRIG
FTM6_INIT_TRIG
FTM6_EXT_TRIG
FTM7_INIT_TRIG
FTM7_EXT_TRIG
Reserved
FTM5_INIT_TRIG
Reserved
Reserved
Reserved
Reserved --------->
---------> in65
---------> in66
LPI2C1_Master_TRIG ---------> in67
---------> in68
---------> in69
---------> in70
---------> in71
---------> in72
---------> in73
---------> in74
---------> in75
---------> in76
---------> in77
---------> in78
---------> in79
---------> in80
Reserved
Reserved
LPI2C1_Slave_TRIG
Y
Y
IN Register OUT
out0 DMA_CH0
1'b1 ---------> in1 TRGMUX_DMAMUX0 out1 DMA_CH1
TRGMUX_IN0 ---------> in2 out2 DMA_CH2
TRGMUX_IN1 ---------> in3 out3 DMA_CH3
TRGMUX_IN2 ---------> in4 out4 TRGMUX_OUT0
TRGMUX_IN3 ---------> in5 TRGMUX_EXTOUT0 out5 TRGMUX_OUT1
TRGMUX_IN4 ---------> in6 out6 TRGMUX_OUT2
TRGMUX_IN5 ---------> in7 out7 TRGMUX_OUT3
TRGMUX_IN6 ---------> in8 out8 TRGMUX_OUT4
TRGMUX_IN7 ---------> in9 TRGMUX_EXTOUT1 out9 TRGMUX_OUT5
TRGMUX_IN8 ---------> in10 out10 TRGMUX_OUT6
TRGMUX_IN9 ---------> in11 out11 TRGMUX_OUT7
TRGMUX_IN10 ---------> in12 out12
------>
TRGMUX_IN11 ---------> in13 TRGMUX_ADC0 out13
------>
------>
CMP0_COUT ---------> in14 out14
------>
out15
------>
out16
------>
LPIT_CH0 ---------> in17 Y TRGMUX_ADC1 out17
------>
------>
LPIT_CH1 ---------> in18 Y out18
------>
LPIT_CH2 ---------> in19 Y out19
------>
LPIT_CH3 ---------> in20 Y out20
LPTMR0 ---------> in21 out21
FTM0_INIT_TRIG ---------> in22 out22
FTM0_EXT_TRIG ---------> in23 out23
FTM1_INIT_TRIG ---------> in24 out24
FTM1_EXT_TRIG ---------> in25 out25 X
FTM2_INIT_TRIG ---------> in26 out26 X
FTM2_EXT_TRIG ---------> in27 out27 X
FTM3_INIT_TRIG ---------> in28 TRGMUX_CMP0 out28
FTM3_EXT_TRIG ---------> in29 out29 X
ADC0_SC1A[COCO]---------> in30 out30 X
ADC0_SC1B[COCO] ---------> in31 out31 X
ADC1_SC1A[COCO] ---------> in32 out32
ADC1_SC1B[COCO] ---------> in33 out33 X
PDB0_CH0_TRIG ---------> in34 out34 X
out35 X
PDB0_PULSE_OUT ---------> in36 out36
PDB1_CH0_TRIG ---------> in37 out37 X
out38 X
PDB1_PULSE_OUT ---------> in39 out39 X
out40 FTM0_HWTRIG0
TRGMUX_FTM0 out41 FTM0_FAULT0
out42 FTM0_FAULT1
RTC_alarm2---------> in43 out43 FTM0_FAULT2
RTC_second2---------> in44 out44 FTM1_HWTRIG0
FlexIO_TRIG0 ---------> in45 TRGMUX_FTM1 out45 FTM1_FAULT0
FlexIO_TRIG1 ---------> in46 out46 FTM1_FAULT1
FlexIO_TRIG2 ---------> in47 out47 FTM1_FAULT2
FlexIO_TRIG3 ---------> in48 out48 FTM2_HWTRIG0
LPUART0_RX_data ---------> in49 TRGMUX_FTM2 out49 FTM2_FAULT0
LPUART0_TX_data ---------> in50 out50 FTM2_FAULT1
LPUART0_RX_idle ---------> in51 out51 FTM2_FAULT2
LPUART1_RX_data ---------> in52 out52 FTM3_HWTRIG0
LPUART1_TX_data ---------> in53 TRGMUX_FTM3 out53 FTM3_FAULT0
LPUART1_RX_idle ---------> in54 out54 FTM3_FAULT1
LPI2C0_Master_trigger ---------> in55 out55 FTM3_FAULT2
LPI2C0_Slave_trigger ---------> in56 TRGMUX_PDB0 out56
out57 X
out58 X
LPSPI0_Frame ---------> in59 out59 X
LPSPI0_RX_data ---------> in60 TRGMUX_PDB1 out60
LPSPI1_Frame ---------> in61 out61 X
LPSPI1_RX_data ---------> in62 out62 X
SIM_SW_TRIG ---------> in63 out63 X
PDB0_trigger_in0---------------------->
---------------------->
TRGMUX
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
ADC1_ADHWT
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
ADC Trigger
ADC0_ADHWT
CMP0_SAMPLE
---------------------->
Trigger Source
----------------------> PDB1_trigger_in0
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
Target Module
X
X
X
X
X
X
X
and
Arbitration
Unit1
Latching
ADC Trigger
and
Arbitration
Unit1
Latching
1 In the ADC Configuration chapter, see the "Trigger Latching and Arbitration" section for details.
1'b0 ---------> in0
Pre-TRIG
OUT
Pre-TRIG
IN
Y
Y
Y
Y
Y
Y
2 Interrupt enable needs to be configured before expecting RTC_alarm and RTC_second trigger from TRGMUX.
Figure 19-2. Trigger interconnectivity (part 1 of 2: outputs 0-63)
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 401
X
out108
X
X
X
out109
out110
out111
out112
X
X
X
out113
out114
out115
out120
X
X
X
out121
out122
out123
out124
X
X
X
out125
out126
out127
out116
X
X
X
out117
out118
out119
LPI2C1_TRG
---------------------->
TRGMUX_LPI2C1
---------------------->
---------------------->
---------------------->
---------------------->
FTM4_HWTRIG0
FTM5_HWTRIG0
FTM6_HWTRIG0
FTM7_HWTRIG0
TRGMUX_FTM5
TRGMUX_FTM4
TRGMUX_FTM6
TRGMUX_FTM7
Note: Above figure shows all the connections. Slots for an absent instance in a particular part are Reserved.
1 Interrupt enable needs to be configured before expecting RTC_alarm and RTC_second trigger from TRGMUX.
IN Pre-TRIG Register OUT
out64
1'b1 ---------> in1 out65 X
TRGMUX_IN0 ---------> in2 out66 X
TRGMUX_IN1 ---------> in3 out67 X
TRGMUX_IN2 ---------> in4 out68 FlexIO_TRG_TIM0
TRGMUX_IN3 ---------> in5 TRGMUX_FLEXIO out69 FlexIO_TRG_TIM1
TRGMUX_IN4 ---------> in6 out70 FlexIO_TRG_TIM2
TRGMUX_IN5 ---------> in7 out71 FlexIO_TRG_TIM3
TRGMUX_IN6 ---------> in8 out72 LPIT_TRG_CH0
TRGMUX_IN7 ---------> in9 TRGMUX_LPIT0 out73 LPIT_TRG_CH1
TRGMUX_IN8 ---------> in10 out74 LPIT_TRG_CH2
TRGMUX_IN9 ---------> in11 out75 LPIT_TRG_CH3
TRGMUX_IN10 ---------> in12 TRGMUX_LPUART0 out76 LPUART0_TRG
TRGMUX_IN11 ---------> in13 out77 X
CMP0_COUT ---------> in14 out78 X
out79 X
TRGMUX_LPUART1 out80 LPUART1_TRG
LPIT_CH0 ---------> in17 Y out81 X
LPIT_CH1 ---------> in18 Y out82 X
LPIT_CH2 ---------> in19 Y out83 X
LPIT_CH3 ---------> in20 Y TRGMUX_LPI2C0 out84 LPI2C0_TRG
LPTMR0 ---------> in21 out85 X
FTM0_INIT_TRIG ---------> in22 out86 X
FTM0_EXT_TRIG ---------> in23 out87 X
FTM1_INIT_TRIG ---------> in24 out88
FTM1_EXT_TRIG ---------> in25 out89 X
FTM2_INIT_TRIG ---------> in26 out90 X
FTM2_EXT_TRIG ---------> in27 out91 X
FTM3_INIT_TRIG ---------> in28 TRGMUX_LPSPI0 out92 LPSPI0_TRG
FTM3_EXT_TRIG ---------> in29 out93 X
ADC0_SC1A[COCO] ---------> in30 out94 X
---------> in31 out95 X
---------> in32 TRGMUX_LPSPI1 out96 LPSPI1_TRG
---------> in33 out97 X
PDB0_CH0_TRIG ---------> in34 out98 X
out99 X
PDB0_PULSE_OUT ---------> in36 TRGMUX_LPTMR0 out100 LPTMR0_ALT0
PDB1_CH0_TRIG ---------> in37 out101 X
out102 X
PDB1_PULSE_OUT ---------> in39 out103 X
RTC_alarm1---------> in43
RTC_second1---------> in44
FlexIO_TRIG0 ---------> in45
FlexIO_TRIG1 ---------> in46
FlexIO_TRIG2 ---------> in47
FlexIO_TRIG3 ---------> in48
LPUART0_RX_data ---------> in49
LPUART0_TX_data ---------> in50
LPUART0_RX_idle ---------> in51
LPUART1_RX_data ---------> in52
LPUART1_TX_data ---------> in53
LPUART1_RX_idle ---------> in54
LPI2C0_Master_trigger ---------> in55
LPI2C0_Slave_trigger ---------> in56
LPSPI0_Frame ---------> in59
LPSPI0_RX_data ---------> in60
LPSPI1_Frame ---------> in61
LPSPI1_RX_data ---------> in62
SIM_SW_TRIG ---------> in63
Trigger Source TRGMUX Target Module
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
---------------------->
X
out104
X
X
X
out105
out106
out107
X
ADC0_SC1B[COCO]
ADC1_SC1A[COCO]
ADC1_SC1B[COCO]
FTM4_INIT_TRIG
FTM4_EXT_TRIG
FTM5_EXT_TRIG
FTM6_INIT_TRIG
FTM6_EXT_TRIG
FTM7_INIT_TRIG
FTM7_EXT_TRIG
Reserved
FTM5_INIT_TRIG
Reserved
Reserved
Reserved
Reserved --------->
---------> in65
---------> in66
LPI2C1_Master_TRIG ---------> in67
---------> in68
---------> in69
---------> in70
---------> in71
---------> in72
---------> in73
---------> in74
---------> in75
---------> in76
---------> in77
---------> in78
---------> in79
---------> in80
Reserved
Reserved
LPI2C1_Slave_TRIG
in64
1'b0 ---------> in0
IN Pre-TRIG
OUT
Figure 19-3. Trigger interconnectivity (part 2 of 2: outputs 64-127)
Chip-specific TRGMUX information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
402 NXP Semiconductors
NOTE
Additional details about ADC triggers include:
• For each ADC, the four triggers are ORed together to
provide a flexible scheme for the hardware trigger of each
ADC. The pretriggers are not ORed.
• Only LPIT supports pretriggers.
• If other peripherals require pretriggers, software pretriggers
must be used. See SIM_ADCOPT[ADCxSWPRETRG] for
configuring software pretriggers.
• See ADC Trigger Sources for more information about ADC
trigger implementation, including a PDB pretrigger scheme
that does not involve TRGMUX.
19.1.2 TRGMUX register information
Some TRGMUX registers and input connections are present only on some S32K1xx
products. Registers and input connections for instances unavailable in a particular variant
are Reserved.
19.2 Introduction
The trigger multiplexer (TRGMUX) module allows software to configure the trigger
inputs for various peripherals.
19.3 Features
The TRGMUX module allows software to select the trigger source for peripherals. The
block diagram below shows the trigger selection logic of the TRGMUX module.
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 403
TRGMUX
Trigger input 1
Trigger input 2
Trigger input 6
Trigger input 3
[SELx]
...001
...010
...011
...100
...101
...110
...111
Trigger input 4
Trigger input 5
Trigger input 7
To peripheral
trigger inputs
Trigger disabled ...000
Up to four outputs per peripheral
Trigger input N*
* Up to 127 selectable trigger inputs may be available. See the chip-specific
TRGMUX information for the maximum number of trigger inputs supported on this device.
[SEL0] selects the trigger for output 0
[SEL1] selects the trigger for output 1
[SEL2] selects the trigger for output 2
[SEL3] selects the trigger for output 3
output x
Figure 19-4. TRGMUX block diagram
Each peripheral has its own dedicated TRGMUX register. See each peripheral's
TRGMUX register for details.
19.4 Memory map and register definition
The TRGMUX registers contain fields for selecting trigger sources for peripheral
modules.
TRGMUX registers can be written only in supervisor mode.
19.4.1 TRGMUX register descriptions
19.4.1.1 TRGMUX Memory map
Table 19-1. Select Bit Fields
Field Function
SELx This read/write field is used to configure the MUX select for the peripheral trigger inputs.
000_0000 - (0x00) -
000_0001 - (0x01) VDD
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
404 NXP Semiconductors
Table 19-1. Select Bit Fields
Field Function
000_0010 - (0x02) TRGMUX_IN0
000_0011 - (0x03) TRGMUX_IN1
000_0100 - (0x04) TRGMUX_IN2
000_0101 - (0x05) TRGMUX_IN3
000_0110 - (0x06) TRGMUX_IN4
000_0111 - (0x07) TRGMUX_IN5
000_1000 - (0x08) TRGMUX_IN6
000_1001 - (0x09) TRGMUX_IN7
000_1010 - (0x0A) TRGMUX_IN8
000_1011 - (0x0B) TRGMUX_IN9
000_1100 - (0x0C) TRGMUX_IN10
000_1101 - (0x0D) TRGMUX_IN11
000_1110 - (0x0E) CMP0_OUT
000_1111 - (0x0F) Reserved
001_0000 - (0x10) Reserved
001_0001 - (0x11) LPIT_CH0
001_0010 - (0x12) LPIT_CH1
001_0011 - (0x13) LPIT_CH2
001_0100 - (0x14) LPIT_CH3
001_0101 - (0x15) LPTMR0
001_0110 - (0x16) FTM0_INIT_TRIG
001_0111 - (0x17) FTM0_EXT_TRIG
001_1000 - (0x18) FTM1_INIT_TRIG
001_1001 - (0x19) FTM1_EXT_TRIG
001_1010 - (0x1A) FTM2_INIT_TRIG
001_1011 - (0x1B) FTM2_EXT_TRIG
001_1100 - (0x1C) FTM3_INIT_TRIG
001_1101 - (0x1D) FTM3_EXT_TRIG
001_1110 - (0x1E) ADC0_SC1A[COCO]
001_1111 - (0x1F) ADC0_SC1B[COCO]
010_0000 - (0x20) ADC1_SC1A[COCO]
010_0001 - (0x21) ADC1_SC1B[COCO]
010_0010 - (0x22) PDB0_CH0_TRIG
010_0011 - (0x23) Reserved
010_0100 - (0x24) PDB0_PULSE_OUT
010_0101 - (0x25) PDB1_CH0_TRIG
010_0110 - (0x26) Reserved
010_0111 - (0x27) PDB1_PULSE_OUT
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 405
Table 19-1. Select Bit Fields
Field Function
010_1000 - (0x28) Reserved
010_1001 - (0x29) Reserved
010_1010 - (0x2A) Reserved
010_1011 - (0x2B) RTC_alarm
010_1100 - (0x2C) RTC_second
010_1101 - (0x2D) FlexIO_TRIG0
010_1110 - (0x2E) FlexIO_TRIG1
010_1111 - (0x2F) FlexIO_TRIG2
011_0000 - (0x30) FlexIO_TRIG3
011_0001 - (0x31) LPUART0_RX_data
011_0010 - (0x32) LPUART0_TX_data
011_0011 - (0x33) LPUART0_RX_idle
011_0100 - (0x34) LPUART1_RX_data
011_0101 - (0x35) LPUART1_TX_data
011_0110 - (0x36) LPUART1_RX_idle
011_0111 - (0x37) LPI2C0_Master_trigger
011_1000 - (0x38) LPI2C0_Slave_trigger
011_1001 - (0x39) Reserved
011_1010 - (0x3A) Reserved
011_1011 - (0x3B) LPSPI0_Frame
011_1100 - (0x3C) LPSPI0_RX_data
011_1101 - (0x3D) LPSPI1_Frame
011_1110 - (0x3E) LPSPI1_RX_data
011_1111 - (0x3F) SIM_SW_TRIG
100_0000 - (0x40) Reserved
100_0001 - (0x41) Reserved
100_0010 - (0x42) Reserved
100_0011 - (0x43) LPI2C1_Master_trigger
100_0100 - (0x44) LPI2C1_Slave_trigger
100_0101 - (0x45) FTM4_INIT_TRIG
100_0110 - (0x46) FTM4_EXT_TRIG
100_0111 - (0x47) FTM5_INIT_TRIG
100_1000 - (0x48) FTM5_EXT_TRIG
100_1001 - (0x49) FTM6_INIT_TRIG
100_1010 - (0x4A) FTM6_EXT_TRIG
100_1011 - (0x4B) FTM7_INIT_TRIG
100_1100 - (0x4C) FTM7_EXT_TRIG
100_1101 - (0x4D) Reserved
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
406 NXP Semiconductors
Table 19-1. Select Bit Fields
Field Function
100_1110 - (0x4E) Reserved
100_1111 - (0x4F) Reserved
101_0000 - (0x50) Reserved
101_0001 - (0x51) Reserved
101_0010 - (0x52) Reserved
101_0011 - (0x53) Reserved
101_0100 - (0x54) Reserved
101_0101 - (0x55) Reserved
101_0110 - (0x56) Reserved
101_0111 - (0x57) Reserved
101_1000 - (0x58) Reserved
101_1001 - (0x59) Reserved
101_1010 - (0x5A) Reserved
101_1011 - (0x5B) Reserved
101_1100 - (0x5C) Reserved
101_1101 - (0x5D) Reserved
101_1110 - (0x5E) Reserved
101_1111 - (0x5F) Reserved
110_0000 - (0x60) Reserved
110_0001 - (0x61) Reserved
110_0010 - (0x62) Reserved
110_0011 - (0x63) Reserved
110_0100 - (0x64) Reserved
110_0101 - (0x65) Reserved
110_0110 - (0x66) Reserved
110_0111 - (0x67) Reserved
110_1000 - (0x68) Reserved
110_1001 - (0x69) Reserved
110_1010 - (0x6A) Reserved
110_1011 - (0x6B) Reserved
110_1100 - (0x6C) Reserved
110_1101 - (0x6D) Reserved
110_1110 - (0x6E) Reserved
110_1111 - (0x6F) Reserved
111_0000 - (0x70) Reserved
111_0001 - (0x71) Reserved
111_0010 - (0x72) Reserved
111_0011 - (0x73) Reserved
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 407
Table 19-1. Select Bit Fields
Field Function
111_0100 - (0x74) Reserved
111_0101 - (0x75) Reserved
111_0110 - (0x76) Reserved
111_0111 - (0x77) Reserved
111_1000 - (0x78) Reserved
111_1001 - (0x79) Reserved
111_1010 - (0x7A) Reserved
111_1011 - (0x7B) Reserved
111_1100 - (0x7C) Reserved
111_1101 - (0x7D) Reserved
111_1110 - (0x7E) Reserved
111_1111 - (0x7F) Reserved
TRGMUX base address: 4006_3000h
Offset Register Width
(In bits)
Access Reset value
0h TRGMUX DMAMUX0 Register (DMAMUX0) 32 RW 0000_0000h
4h TRGMUX EXTOUT0 Register (EXTOUT0) 32 RW 0000_0000h
8h TRGMUX EXTOUT1 Register (EXTOUT1) 32 RW 0000_0000h
Ch TRGMUX ADC0 Register (ADC0) 32 RW 0000_0000h
10h TRGMUX ADC1 Register (ADC1) 32 RW 0000_0000h
1Ch TRGMUX CMP0 Register (CMP0) 32 RW 0000_0000h
28h TRGMUX FTM0 Register (FTM0) 32 RW 0000_0000h
2Ch TRGMUX FTM1 Register (FTM1) 32 RW 0000_0000h
30h TRGMUX FTM2 Register (FTM2) 32 RW 0000_0000h
34h TRGMUX FTM3 Register (FTM3) 32 RW 0000_0000h
38h TRGMUX PDB0 Register (PDB0) 32 RW 0000_0000h
3Ch TRGMUX PDB1 Register (PDB1) 32 RW 0000_0000h
44h TRGMUX FLEXIO Register (FLEXIO) 32 RW 0000_0000h
48h TRGMUX LPIT0 Register (LPIT0) 32 RW 0000_0000h
4Ch TRGMUX LPUART0 Register (LPUART0) 32 RW 0000_0000h
50h TRGMUX LPUART1 Register (LPUART1) 32 RW 0000_0000h
54h TRGMUX LPI2C0 Register (LPI2C0) 32 RW 0000_0000h
5Ch TRGMUX LPSPI0 Register (LPSPI0) 32 RW 0000_0000h
60h TRGMUX LPSPI1 Register (LPSPI1) 32 RW 0000_0000h
64h TRGMUX LPTMR0 Register (LPTMR0) 32 RW 0000_0000h
6Ch TRGMUX LPI2C1 Register (LPI2C1) 32 RW 0000_0000h
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
408 NXP Semiconductors
Offset Register Width
(In bits)
Access Reset value
70h TRGMUX FTM4 Register (FTM4) 32 RW 0000_0000h
74h TRGMUX FTM5 Register (FTM5) 32 RW 0000_0000h
78h TRGMUX FTM6 Register (FTM6) 32 RW 0000_0000h
7Ch TRGMUX FTM7 Register (FTM7) 32 RW 0000_0000h
19.4.1.2 TRGMUX DMAMUX0 Register (DMAMUX0)
19.4.1.2.1 Offset
Register Offset
DMAMUX0 0h
19.4.1.2.2 Function
TRGMUX Register
19.4.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.2.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 409
Field Function
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.3 TRGMUX EXTOUT0 Register (EXTOUT0)
19.4.1.3.1 Offset
Register Offset
EXTOUT0 4h
19.4.1.3.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
410 NXP Semiconductors
19.4.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.3.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 411
19.4.1.4 TRGMUX EXTOUT1 Register (EXTOUT1)
19.4.1.4.1 Offset
Register Offset
EXTOUT1 8h
19.4.1.4.2 Function
TRGMUX Register
19.4.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.4.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
412 NXP Semiconductors
Field Function
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.5 TRGMUX ADC0 Register (ADC0)
19.4.1.5.1 Offset
Register Offset
ADC0 Ch
19.4.1.5.2 Function
TRGMUX Register
19.4.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 413
19.4.1.5.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.6 TRGMUX ADC1 Register (ADC1)
19.4.1.6.1 Offset
Register Offset
ADC1 10h
19.4.1.6.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
414 NXP Semiconductors
19.4.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.6.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 415
19.4.1.7 TRGMUX CMP0 Register (CMP0)
19.4.1.7.1 Offset
Register Offset
CMP0 1Ch
19.4.1.7.2 Function
TRGMUX Register
19.4.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.7.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
416 NXP Semiconductors
Field Function
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.8 TRGMUX FTM0 Register (FTM0)
19.4.1.8.1 Offset
Register Offset
FTM0 28h
19.4.1.8.2 Function
TRGMUX Register
19.4.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.8.4 Fields
Field Function
31
LK
TRGMUX register lock.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 417
Field Function
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.9 TRGMUX FTM1 Register (FTM1)
19.4.1.9.1 Offset
Register Offset
FTM1 2Ch
19.4.1.9.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
418 NXP Semiconductors
19.4.1.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.9.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 419
19.4.1.10 TRGMUX FTM2 Register (FTM2)
19.4.1.10.1 Offset
Register Offset
FTM2 30h
19.4.1.10.2 Function
TRGMUX Register
19.4.1.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.10.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
420 NXP Semiconductors
Field Function
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.11 TRGMUX FTM3 Register (FTM3)
19.4.1.11.1 Offset
Register Offset
FTM3 34h
19.4.1.11.2 Function
TRGMUX Register
19.4.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 421
19.4.1.11.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.12 TRGMUX PDB0 Register (PDB0)
19.4.1.12.1 Offset
Register Offset
PDB0 38h
19.4.1.12.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
422 NXP Semiconductors
19.4.1.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.12.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.13 TRGMUX PDB1 Register (PDB1)
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 423
19.4.1.13.1 Offset
Register Offset
PDB1 3Ch
19.4.1.13.2 Function
TRGMUX Register
19.4.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.13.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
424 NXP Semiconductors
Field Function
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.14 TRGMUX FLEXIO Register (FLEXIO)
19.4.1.14.1 Offset
Register Offset
FLEXIO 44h
19.4.1.14.2 Function
TRGMUX Register
19.4.1.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.14.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 425
Field Function
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.15 TRGMUX LPIT0 Register (LPIT0)
19.4.1.15.1 Offset
Register Offset
LPIT0 48h
19.4.1.15.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
426 NXP Semiconductors
19.4.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK SEL3 0SEL2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SEL1 0SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.15.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. For the field
setting definitions, see Memory map and register definition.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field
setting definitions, see Memory map and register definition.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. For the field
setting definitions, see Memory map and register definition.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 427
19.4.1.16 TRGMUX LPUART0 Register (LPUART0)
19.4.1.16.1 Offset
Register Offset
LPUART0 4Ch
19.4.1.16.2 Function
TRGMUX Register
19.4.1.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.16.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
428 NXP Semiconductors
Field Function
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.17 TRGMUX LPUART1 Register (LPUART1)
19.4.1.17.1 Offset
Register Offset
LPUART1 50h
19.4.1.17.2 Function
TRGMUX Register
19.4.1.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.17.4 Fields
Field Function
31
LK
TRGMUX register lock.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 429
Field Function
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.18 TRGMUX LPI2C0 Register (LPI2C0)
19.4.1.18.1 Offset
Register Offset
LPI2C0 54h
19.4.1.18.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
430 NXP Semiconductors
19.4.1.18.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.18.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.19 TRGMUX LPSPI0 Register (LPSPI0)
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 431
19.4.1.19.1 Offset
Register Offset
LPSPI0 5Ch
19.4.1.19.2 Function
TRGMUX Register
19.4.1.19.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.19.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
432 NXP Semiconductors
Field Function
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.20 TRGMUX LPSPI1 Register (LPSPI1)
19.4.1.20.1 Offset
Register Offset
LPSPI1 60h
19.4.1.20.2 Function
TRGMUX Register
19.4.1.20.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.20.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 433
Field Function
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.21 TRGMUX LPTMR0 Register (LPTMR0)
19.4.1.21.1 Offset
Register Offset
LPTMR0 64h
19.4.1.21.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
434 NXP Semiconductors
19.4.1.21.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.21.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.22 TRGMUX LPI2C1 Register (LPI2C1)
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 435
19.4.1.22.1 Offset
Register Offset
LPI2C1 6Ch
19.4.1.22.2 Function
TRGMUX Register
19.4.1.22.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.22.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
436 NXP Semiconductors
Field Function
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.23 TRGMUX FTM4 Register (FTM4)
19.4.1.23.1 Offset
Register Offset
FTM4 70h
19.4.1.23.2 Function
TRGMUX Register
19.4.1.23.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.23.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 437
Field Function
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.24 TRGMUX FTM5 Register (FTM5)
19.4.1.24.1 Offset
Register Offset
FTM5 74h
19.4.1.24.2 Function
TRGMUX Register
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
438 NXP Semiconductors
19.4.1.24.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.24.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.25 TRGMUX FTM6 Register (FTM6)
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 439
19.4.1.25.1 Offset
Register Offset
FTM6 78h
19.4.1.25.2 Function
TRGMUX Register
19.4.1.25.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.25.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
440 NXP Semiconductors
Field Function
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
19.4.1.26 TRGMUX FTM7 Register (FTM7)
19.4.1.26.1 Offset
Register Offset
FTM7 7Ch
19.4.1.26.2 Function
TRGMUX Register
19.4.1.26.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLK 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 SEL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.4.1.26.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
Table continues on the next page...
Chapter 19 Trigger MUX Control (TRGMUX)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 441
Field Function
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see Memory map and register definition.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
442 NXP Semiconductors
Chapter 20
External Watchdog Monitor (EWM)
20.1 Chip-specific EWM information
S32K14x has one instance of EWM. Products in the S32K11x series do not have EWM.
20.1.1 EWM_OUT signal configuration
EWM_out signal shares its pad with other I/Os. To know the default state of that pad, see
IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.
20.1.2 EWM Memory Map access
Only 8-bit access is supported.
20.1.3 EWM low-power modes
This table shows the EWM low-power modes and the corresponding chip low-power
modes.
Wait mode and power down mode is not supported. See Module operation in available
low power modes for details on available power modes.
20.2 Introduction
For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is
designed to monitor external circuits, as well as the MCU software flow. This provides a
back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 443
The watchdog is generally used to monitor the flow and execution of embedded software
within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an
internal reset (asynchronous) to all on-chip peripherals and optionally assert the
RESET_B pin to reset external devices/circuits. The overflow of the watchdog counter
must not occur if the software code works well and services the watchdog to re-start the
actual counter.
The EWM differs from the internal watchdog in that it does not reset the MCU's CPU
and peripherals. The EWM provides an independent EWM_OUT_b signal that when
asserted resets or places an external circuit into a safe mode. The EWM_OUT_b signal is
asserted upon the EWM counter time-out. An optional external input EWM_in is
provided to allow additional control of the assertion of EWM_OUT_b signal.
20.2.1 Features
Features of EWM module include:
• Independent LPO_CLK clock source
• Programmable time-out period specified in terms of number of EWM LPO_CLK
clock cycles.
• Windowed refresh option
• Provides robust check that program flow is faster than expected.
• Programmable window.
• Refresh outside window leads to assertion of EWM_OUT_b.
• Robust refresh mechanism
• Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 peripheral
bus clock cycles.
• One output port, EWM_OUT_b, when asserted is used to reset or place the external
circuit into safe mode.
• One Input port, EWM_in, allows an external circuit to control the assertion of the
EWM_OUT_b signal.
20.2.2 Modes of Operation
This section describes the module's operating modes.
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
444 NXP Semiconductors
20.2.2.1 Stop Mode
When the EWM is in stop mode, the CPU refreshes to the EWM cannot occur. On entry
to stop mode, the EWM's counter freezes.
There are two possible ways to exit from Stop mode:
• On exit from stop mode through a reset, the EWM remains disabled.
• On exit from stop mode by an interrupt, the EWM is re-enabled, and the counter
continues to be clocked from the same value prior to entry to stop mode.
Note the following if the EWM enters the stop mode during CPU refresh mechanism: At
the exit from stop mode by an interrupt, refresh mechanism state machine starts from the
previous state which means, if first refresh command is written correctly and EWM
enters the stop mode immediately, the next command has to be written within the next 15
peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to
executing EWM refresh instructions.
20.2.2.2 Debug Mode
Entry to debug mode has no effect on the EWM.
• If the EWM is enabled prior to entry of debug mode, it remains enabled.
• If the EWM is disabled prior to entry of debug mode, it remains disabled.
20.2.3 Block Diagram
This figure shows the EWM block diagram.
Chapter 20 External Watchdog Monitor (EWM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 445
Clock Divider
Logic
LPO_CLK Low Power
Clock Clock Gating
Cell
AND
Enable
EWM_CTRL[EWMEN]
EWM_CLKPRESCALER[CLK_DIV]
8-bit Counter
OR
Counter Value
Reset to
Counter
EWM Refresh
And
/EWM_out Output
Control
Mechanism
EWM_CMPH[COMPAREH]
EWM_CMPL[COMPAREL]
EWM Refreshed
EWM_out
Counter
overflow
EWM_in
EWM Service Register
CPU
Reset
Figure 20-1. EWM Block Diagram
20.3 EWM Signal Descriptions
The EWM has two external signals, as shown in the following table.
NOTE
All active-low signals are now represented with the suffix "_b"
throughout the chapter.
Table 20-1. EWM Signal Descriptions
Signal Description I/O
EWM_in EWM input for safety status of external safety circuits. The polarity of
EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default
polarity is active low.
I
EWM_OUT_b EWM reset out signal O
EWM Signal Descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
446 NXP Semiconductors
20.4 Memory Map/Register Definition
This section contains the module memory map and registers.
NOTE
EWM only supports 8-bit register access. 16-bit and 32-bit
access are not possible.
20.4.1 EWM register descriptions
20.4.1.1 EWM Memory map
EWM base address: 4006_1000h
Offset Register Width
(In bits)
Access Reset value
0h Control Register (CTRL) 8 RW 00h
1h Service Register (SERV) 8 WORZ 00h
2h Compare Low Register (CMPL) 8 RWONC
E
00h
3h Compare High Register (CMPH) 8 RWONC
E
FFh
5h Clock Prescaler Register (CLKPRESCALER) 8 RWONC
E
00h
20.4.1.2 Control Register (CTRL)
20.4.1.2.1 Offset
Register Offset
CTRL 0h
20.4.1.2.2 Function
The CTRL register is cleared by any reset.
Chapter 20 External Watchdog Monitor (EWM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 447
NOTE
INEN, ASSIN and EWMEN bits can be written once after a
CPU reset. Modifying these bits more than once, generates a
bus transfer error.
20.4.1.2.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
INTEN
INEN
ASSI
N
EWMEN
W
Reset 0 0 0 0 0 0 0 0
20.4.1.2.4 Fields
Field Function
7-4
—
Reserved
3
INTEN
Interrupt Enable.
This bit when set and EWM_OUT_b is asserted, an interrupt request is generated. To de-assert interrupt
request, user should clear this bit by writing 0.
2
INEN
Input Enable.
This bit when set, enables the EWM_in port.
1
ASSIN
EWM_in's Assertion State Select.
Default assert state of the EWM_in signal is logic zero. Setting the ASSIN bit inverts the assert state of
EWM_in signal to a logic one.
0
EWMEN
EWM enable.
This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the
EWM_OUT_b signal. This bit when unset, keeps the EWM module disabled. It cannot be re-enabled until
a next reset, due to the write-once nature of this bit.
20.4.1.3 Service Register (SERV)
20.4.1.3.1 Offset
Register Offset
SERV 1h
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
448 NXP Semiconductors
20.4.1.3.2 Function
The SERV register provides the interface from the CPU to the EWM module. It is write-
only and reads of this register return zero.
20.4.1.3.3 Diagram
Bits 7 6 5 4 3 2 1 0
R 0
WSERVICE
Reset 0 0 0 0 0 0 0 0
20.4.1.3.4 Fields
Field Function
7-0
SERVICE
SERVICE
The EWM refresh mechanism requires the CPU to write two values to the SERV register: a first data byte
of 0xB4, followed by a second data byte of 0x2C. The EWM refresh is invalid if either of the following
conditions is true.
• The first or second data byte is not written correctly.
• The second data byte is not written within a fixed number of peripheral bus cycles of the first data
byte. This fixed number of cycles is called EWM_refresh_time.
15 peripheral bus clock cycles are required for EWM_refresh_time
20.4.1.4 Compare Low Register (CMPL)
20.4.1.4.1 Offset
Register Offset
CMPL 2h
20.4.1.4.2 Function
The CMPL register is reset to zero after a CPU reset. This provides no minimum time for
the CPU to refresh the EWM counter.
Chapter 20 External Watchdog Monitor (EWM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 449
NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
20.4.1.4.3 Diagram
Bits 7 6 5 4 3 2 1 0
RCOMPAREL
W
Reset 0 0 0 0 0 0 0 0
20.4.1.4.4 Fields
Field Function
7-0
COMPAREL
COMPAREL
To prevent runaway code from changing this field, software should write to this field after a CPU reset
even if the (default) minimum refresh time is required.
20.4.1.5 Compare High Register (CMPH)
20.4.1.5.1 Offset
Register Offset
CMPH 3h
20.4.1.5.2 Function
The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256
clocks time, for the CPU to refresh the EWM counter.
NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
450 NXP Semiconductors
NOTE
The valid values for CMPH are up to 0xFE because the EWM
counter never expires when CMPH = 0xFF. The expiration
happens only if EWM counter is greater than CMPH.
20.4.1.5.3 Diagram
Bits 7 6 5 4 3 2 1 0
RCOMPAREH
W
Reset 1 1 1 1 1 1 1 1
20.4.1.5.4 Fields
Field Function
7-0
COMPAREH
COMPAREH
To prevent runaway code from changing this field, software should write to this field after a CPU reset
even if the (default) maximum refresh time is required.
20.4.1.6 Clock Prescaler Register (CLKPRESCALER)
20.4.1.6.1 Offset
Register Offset
CLKPRESCALER 5h
20.4.1.6.2 Function
This CLKPRESCALER register is reset to 0x00 after a CPU reset.
NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
NOTE
Write the required prescaler value before enabling the EWM.
Chapter 20 External Watchdog Monitor (EWM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 451
NOTE
The implementation of this register is chip-specific. See the
Chip Configuration details.
20.4.1.6.3 Diagram
Bits 7 6 5 4 3 2 1 0
RCLK_DIV
W
Reset 0 0 0 0 0 0 0 0
20.4.1.6.4 Fields
Field Function
7-0
CLK_DIV
CLK_DIV
Selected low power clock source for running the EWM counter can be prescaled as below.
• Prescaled clock frequency = low power clock source frequency / ( 1 + CLK_DIV )
20.5 Functional Description
The following sections describe functional details of the EWM module.
NOTE
When the BUS_CLK is lost, then EWM module doesn't
generate the EWM_OUT_b signal and no refresh operation is
possible
20.5.1 The EWM_OUT_b Signal
The EWM_OUT_b is a digital output signal used to gate an external circuit (application
specific) that controls critical safety functions. For example, the EWM_OUT_b could be
connected to the high voltage transistors circuits that control an AC motor in a large
appliance.
The EWM_OUT_b signal remains deasserted when the EWM is being regularly
refreshed by the CPU within the programmable refresh window, indicating that the
application code is executed as expected.
Functional Description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
452 NXP Semiconductors
The EWM_OUT_b signal is asserted in any of the following conditions:
• The EWM refresh occurs when the counter value is less than CMPL value.
• The EWM counter value reaches the CMPH value, and no EWM refresh has
occurred.
• If functionality of EWM_in pin is enabled and EWM_in pin is asserted while
refreshing the EWM.
• After any reset (by the virtue of the external pull-down mechanism on the
EWM_OUT_b pin)
The EWM_OUT_b is asserted after any reset by the virtue of the external pull-down
mechanism on the EWM_OUT_b signal. Then, to deassert the EWM_OUT_b signal, set
EWMEN bit in the CTRL register to enable the EWM.
If the EWM_OUT_b signal shares its pad with a digital I/O pin, on reset this actual pad
defers to being an input signal. The pad state is controlled by the EWM_OUT_b signal
only after the EWM is enabled by the EWMEN bit in the CTRL register.
Note
EWM_OUT_b pad must be in pull down state when EWM
functionality is used and when EWM is under Reset.
20.5.2 EWM_OUT_b pin state in low power modes
During Wait, Stop, and Power Down modes the EWM_OUT_b pin preserve its state
before entering Wait or Stop mode. When the CPU enters a Run mode from Wait or Stop
recovery, the pin resumes its previous state before entering Wait or Stop mode. When the
CPU enters Run mode from Power Down, the pin returns to its reset state.
20.5.3 The EWM_in Signal
The EWM_in is a digital input signal for safety status of external safety circuits, that
allows an external circuit to control the assertion of the EWM_OUT_b signal. For
example, in the application, an external circuit monitors a critical safety function, and if
there is fault with safety function, the external circuit can then actively initiate the
EWM_OUT_b signal that controls the gating circuit.
The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register
is cleared, as after any reset.
Chapter 20 External Watchdog Monitor (EWM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 453
On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM_in
functionality (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted
state prior to the CPU start refreshing the EWM. This ensures that the EWM_OUT_b
stays in the deasserted state; otherwise, the EWM_OUT_b output signal is asserted.
Note
The user must update the CMPH and CMPL registers prior to
enabling the EWM. After enabling the EWM, the counter resets
to zero, therefore the user shall provide a reasonable time after a
power-on reset for the external monitoring circuit to stabilize.
The user shall also ensure that the EWM_in pin is deasserted.
20.5.4 EWM Counter
It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral
bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock
source should be in the kHz range.
The counter is reset to zero after the CPU reset, or when EWM refresh action completes,
or at counter overflow. The counter value is not accessible to the CPU.
20.5.5 EWM Compare Registers
The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be
modified until another CPU reset occurs.
The EWM compare registers are used to create a refresh window to refresh the EWM
module.
It is illegal to program CMPL and CMPH with same value. In this case, as soon as
counter reaches (CMPL + 1), EWM_OUT_b is asserted.
20.5.6 EWM Refresh Mechanism
Other than the initial configuration of the EWM, the CPU can only access the EWM by
the EWM Service Register. The CPU must access the EWM service register with correct
write of unique data within the windowed time frame as determined by the CMPL and
CMPH registers for correct EWM refresh operation. Therefore, three possible conditions
can occur:
Functional Description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
454 NXP Semiconductors
Table 20-2. EWM Refresh Mechanisms
Condition Mechanism
An EWM refresh action completes when:
CMPL < Counter < CMPH.
The software behaves as expected and the EWM counter is reset to zero. The
EWM_OUT_b output signal remains in the deasserted state if, during the EWM
refresh action, the EWM_in input has been in deasserted state..
An EWM refresh action completes when
Counter < CMPL
The software refreshes the EWM before the windowed time frame, the counter is
reset to zero and the EWM_OUT_b output signal is asserted irrespective of the
input EWM_in signal.
Counter value reaches CMPH prior to
completion of EWM refresh action.
Software has not refreshed the EWM. The EWM counter is reset to zero and the
EWM_OUT_b output signal is asserted irrespective of the input EWM_in signal.
20.5.7 EWM Interrupt
When EWM_OUT_b is asserted, an interrupt request is generated to indicate the
assertion of the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is
set. Clearing this bit clears the interrupt request but does not affect EWM_OUT_b. The
EWM_OUT_b signal can be deasserted only by forcing a system reset.
20.5.8 Counter clock prescaler
The EWM counter clock source can be prescaled by a clock divider, by programming
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter.
NOTE
The divided clock used to run the EWM counter must be no
more than half the frequency of the bus clock.
Chapter 20 External Watchdog Monitor (EWM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 455
Functional Description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
456 NXP Semiconductors
Chapter 21
Error Injection Module (EIM)
21.1 Chip-specific EIM information
S32K1xx has one instance of the EIM.
21.1.1 EIM channel assignments
Each EIM channel corresponds to a specific RAM array target. The EIM channel can
inject errors on accesses to that specific RAM array. The following table shows the
channel assignments.
Table 21-1. RAM array targets of EIM channels
EIM channel RAM array target
S32K14x S32K11x
0 SRAM_L SRAM_U
1 SRAM_U Reserved
21.2 Introduction
The Error Injection Module (EIM) is mainly used for diagnostic purposes. It provides a
method for diagnostic coverage of the peripheral memories. See the chip-specific EIM
information to determine which peripheral memories are supported by this method.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 457
21.2.1 Overview
The Error Injection Module (EIM) provides support for inducing single-bit and multi-bit
inversions on read data when accessing peripheral RAMs. Injecting faults on memory
accesses can be used to exercise the SEC-DED ECC function of the related system.
NOTE
The following diagram shows an example of EIM
implementation with a 64-bit read data bus and an 8-bit
checkbit bus.
Module
rdata[63](MSB)
rdata[62]
rdata[61]
rdata[0](LSB)
chkbit[7]
chkbit[0]
EIM
EIMCR[GEIEN]
EICHEN[EICHnEN]
EICHDn_WORD0
EICHDn_WORD1
EICHDn_WORD2
RAM
array
Figure 21-1. EIM functional block diagram (64-bit read data bus and 8-bit check bit bus)
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
458 NXP Semiconductors
21.2.2 Features
The EIM includes these features:
• Supports 2 error injection channels
• Protection against accidental enable and reconfiguration error injection function via
two-stage enable mechanism
21.3 EIM register descriptions
The EIM provides an IPS programming model mapped to an on-platform peripheral slot.
Programming model access
All system bus masters can access the programming model:
• Only in supervisor mode
• Using only 32-bit (word) accesses
Any of the following attempted references to the programming model generates an IPS
error termination:
• In user mode
• Using non-32-bit access sizes
• To undefined (reserved) addresses
Attempted updates to the programming model while the EIM is in the midst of an
operation result in non-deterministic behavior.
Error injection channel descriptor: function and structure
Each error injection channel descriptor:
• Specifies a mask that defines which bits of the read data and checkbit bus from target
RAM are inverted on a read access.
• Consists of a 128-bit (16-byte) structure, composed of four 32-bit words, in the EIM
programming model.
•The first word, Word0 (EICHDn_WORD0), defines the checkbit mask. See
Error Injection Channel Descriptor n, Word0 for details.
•The remaining words, Word1-3 (EICHDn_WORD1-3), define the data mask.
Word2 and Word3 are used only when required by the total width of the
Chapter 21 Error Injection Module (EIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 459
channel's data mask. See Error injection channel descriptor: DATA_MASK
details and the individual registers' descriptions.
The multiple channel descriptors are organized sequentially.
Error injection channel descriptor: DATA_MASK details
For each channel: The following table shows the total width of DATA_MASK and the
distribution of its bits across the WORD registers.
Channel DATA_MASK total
width (bits)
Specific bits of DATA_MASK in
WORD1 WORD2 WORD3
0 32 31-0 — —
1 32 31-0 — —
21.3.1 EIM Memory map
EIM base address: 4001_9000h
Offset Register Width
(In bits)
Access Reset value
0h Error Injection Module Configuration Register (EIMCR) 32 RW 0000_0000h
4h Error Injection Channel Enable register (EICHEN) 32 RW 0000_0000h
100h Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0) 32 RW 0000_0000h
104h Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1) 32 RW 0000_0000h
200h Error Injection Channel Descriptor n, Word0 (EICHD1_WORD0) 32 RW 0000_0000h
204h Error Injection Channel Descriptor n, Word1 (EICHD1_WORD1) 32 RW 0000_0000h
21.3.2 Error Injection Module Configuration Register (EIMCR)
21.3.2.1 Offset
Register Offset
EIMCR 0h
EIM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
460 NXP Semiconductors
21.3.2.2 Function
The EIM Configuration Register is used to globally enable/disable the error injection
function.
21.3.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
GEIE
N
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21.3.2.4 Fields
Field Function
31-1
—
Reserved
0
GEIEN
Global Error Injection Enable
This bit globally enables or disables the error injection function of the EIM. This field is initialized by
hardware reset.
0b - Disabled
1b - Enabled
21.3.3 Error Injection Channel Enable register (EICHEN)
21.3.3.1 Offset
Register Offset
EICHEN 4h
Chapter 21 Error Injection Module (EIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 461
21.3.3.2 Function
Each field of the Error Injection Channel Enable register (EICHEN) is used to enable or
disable the corresponding error injection channel.
NOTE
To enable an error injection channel, the Global Error Injection
Enable (EIMCR[GEIEN]) field must also be asserted.
21.3.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EICH0EN
EICH1EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0000000000000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21.3.3.4 Fields
Field Function
31
EICH0EN
Error Injection Channel 0 Enable
This field enables the corresponding error injection channel. The Global Error Injection Enable
(EIMCR[GEIEN]) field must also be asserted to enable error injection.
After error injection is enabled, all subsequent read accesses incur one or more bit inversions as defined
in the corresponding EICHDn_WORD registers. Error injection remains in effect until the error injection
channel is manually disabled via software.
Any write to the corresponding EICHDn_WORD registers clears the corresponding EICHEN[EICHnEN]
field, disabling the error injection channel.
0b - Error injection is disabled on Error Injection Channel 0
1b - Error injection is enabled on Error Injection Channel 0
30
EICH1EN
Error Injection Channel 1 Enable
This field enables the corresponding error injection channel. The Global Error Injection Enable
(EIMCR[GEIEN]) field must also be asserted to enable error injection.
Table continues on the next page...
EIM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
462 NXP Semiconductors
Field Function
After error injection is enabled, all subsequent read accesses incur one or more bit inversions as defined
in the corresponding EICHDn_WORD registers. Error injection remains in effect until the error injection
channel is manually disabled via software.
Any write to the corresponding EICHDn_WORD registers clears the corresponding EICHEN[EICHnEN]
field, disabling the error injection channel.
0b - Error injection is disabled on Error Injection Channel 1
1b - Error injection is enabled on Error Injection Channel 1
29
—
Reserved
28
—
Reserved
27
—
Reserved
26
—
Reserved
25
—
Reserved
24
—
Reserved
23
—
Reserved
22
—
Reserved
21
—
Reserved
20
—
Reserved
19
—
Reserved
18
—
Reserved
17
—
Reserved
16
—
Reserved
15
—
Reserved
14
—
Reserved
13
—
Reserved
Table continues on the next page...
Chapter 21 Error Injection Module (EIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 463
Field Function
12
—
Reserved
11
—
Reserved
10
—
Reserved
9
—
Reserved
8
—
Reserved
7
—
Reserved
6
—
Reserved
5
—
Reserved
4
—
Reserved
3
—
Reserved
2
—
Reserved
1
—
Reserved
0
—
Reserved
21.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_W
ORD0 - EICHD1_WORD0)
21.3.4.1 Offset
Register Offset
EICHD0_WORD0 100h
EICHD1_WORD0 200h
EIM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
464 NXP Semiconductors
21.3.4.2 Function
The first word of the Error Injection Channel Descriptor defines a left-justified mask
field: CHKBIT_MASK. Each bit of CHKBIT_MASK specifies whether the
corresponding bit of the checkbit bus from the target RAM should be inverted or remain
unmodified on read accesses. Successful write to this field clears the corresponding error
injection channel valid bit, EICHEN[EICHnEN].
21.3.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCHKBIT_MASK 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21.3.4.4 Fields
Field Function
31-25
CHKBIT_MASK
Checkbit Mask
This field defines a bit-mapped mask that specifies whether the corresponding bit of the checkbit bus
from the target RAM should be inverted or remain unmodified.
For any unique details about the mapping of CHKBIT_MASK's bits to a channel's target RAM, see the
chip-specific EIM information.
The following table shows the width and bit range of CHKBIT_MASK for each channel.
Channel CHKBIT_MASK width (bits) CHKBIT_MASK bit range
0 7 6-0
1 7 6-0
NOTE: Because CHKBIT_MASK is left-justified, the highest bit in the bit range is always in the position
of the most significant bit. For a CHKBIT_MASK that is 7 bits wide, CHKBIT_MASK[6] is in the
position of the most significant bit. For any CHKBIT_MASK with a smaller width, the highest bit
in that width's bit range is in the position of the most significant bit.
0b - The corresponding bit of the checkbit bus remains unmodified.
Table continues on the next page...
Chapter 21 Error Injection Module (EIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 465
Field Function
1b - The corresponding bit of the checkbit bus is inverted.
24-0
—
Reserved.
21.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_W
ORD1 - EICHD1_WORD1)
21.3.5.1 Offset
Register Offset
EICHD0_WORD1 104h
EICHD1_WORD1 204h
21.3.5.2 Function
The second word of the Error Injection Channel Descriptor defines a right-justified mask
field. The bits in B0_3DATA_MASK correspond to bytes 0–3 of the read data bus. Each
bit specifies whether the corresponding bit of the read data bus from the target RAM
should be inverted or remain unmodified on read accesses. A successful write to this field
clears the corresponding error injection channel valid field, EICHEN[EICHnEN].
21.3.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB0_3DATA_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB0_3DATA_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EIM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
466 NXP Semiconductors
21.3.5.4 Fields
Field Function
31-0
B0_3DATA_MA
SK
Data Mask Bytes 0-3
This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
from the target RAM should be inverted or remain unmodified.
NOTE: For each channel: For the exact width of B0_3DATA_MASK and the specific DATA_MASK bits
to which B0_3DATA_MASK corresponds, see Error injection channel descriptor: DATA_MASK
details.
0b - The corresponding bit of bytes 0-3 on the read data bus remains unmodified.
1b - The corresponding bit of bytes 0-3 on the read data bus is inverted.
21.4 Functional description
The EIM provides protection against accidental enabling and reconfiguration of the error
injection function by enforcing a two-stage enablement mechanism. To properly enable
the error injection mechanism for a channel:
•Write 1 to the EICHEN[EICHnEN] field, where n denotes the channel number.
• Write 1 to EIMCR[GEIEN].
NOTE
When the use case for a channel requires writing any
EICHDn_WORD register, write the EICHDn_WORD register
before executing the two-stage enablement mechanism. A
successful write to any EICHDn_WORD register clears the
corresponding EICHEN[EICHnEN] field.
The EIM supports 2 error injection channels. Each channel:
• Is assigned to a single memory array interface.
• Intercepts the assigned memory read data bus and checkbit bus and injects errors by
inverting the value transmitted for selected bits on each bus line.
On a memory read access, the applicable EICHDn_WORD register defines which bit of
the read data and/or checkbit bus to invert.
Figure 21-1 depicts the interception and override of a 64-bit read data bus and an 8-bit
checkbit data bus for an example memory array.
Chapter 21 Error Injection Module (EIM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 467
21.4.1 Error injection scenarios
The EIM supports these cases of error injection:
• To generate a single-bit error, invert only 1 bit of the CHKBIT_MASK or
DATA_MASK in the EICHDn_WORD registers.
• To generate a multi-bit error, invert only 2 bits of the CHKBIT_MASK or
DATA_MASK in the EICHDn_WORD registers.
NOTE
An attempt to invert more than 2 bits in one operation might
result in undefined behavior.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
468 NXP Semiconductors
Chapter 22
Error Reporting Module (ERM)
22.1 Chip-specific ERM information
S32K1xx has one instance of the ERM.
22.1.1 Sources of memory error events
Each ERM channel n corresponds to a source of potential memory error events. The
following table shows the channel assignments.
Table 22-1. Memory error event sources for ERM channels
ERM channel nMemory n event source1
S32K14x S32K11x
0 SRAM_L SRAM_U
1 SRAM_U Reserved
1. Throughout this chapter, "Memory n" designates the memory array sourced by ERM channel n.
Introduction
22.2.1 Overview
The Error Reporting Module (ERM) provides information and optional interrupt
notification on memory error events associated with Error Correction Code (ECC). The
ERM collects ECC events on memory accesses for platform local memory arrays, such as
flash memory, system RAM, or peripheral RAMs. See the chip-specific ERM
information for details about supported memory sources and specific memory channel
assignments.
22.2
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 469
22.2.2 Features
The ERM includes these features:
• Capturing of address information on single-bit correction and non-correctable ECC
events
• Optional interrupt notification on captured ECC events
• Support for ECC event capturing for memory sources, with individual reporting
fields and interrupt configuration per memory channel
22.3 ERM register descriptions
The ERM provides an IPS programming model mapped to an on-platform peripheral slot.
All system bus masters can access the programming model:
• Only in supervisor mode
• Using only 32-bit (word) accesses
Any of the following attempted references to the programming model generates an IPS
error termination:
• In user mode
• Using non-32-bit access sizes
Attempted accesses to undefined (reserved) memory regions can result in undefined
behavior.
Attempted updates to the programming model when the ERM is in the middle of an
operation result in non-deterministic behavior.
22.3.1 ERM Memory map
ERM base address: 4001_8000h
Offset Register Width
(In bits)
Access Reset value
0h ERM Configuration Register 0 (CR0) 32 RW 0000_0000h
10h ERM Status Register 0 (SR0) 32 W1C 0000_0000h
Table continues on the next page...
ERM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
470 NXP Semiconductors
Offset Register Width
(In bits)
Access Reset value
100h ERM Memory n Error Address Register (EAR0) 32 RO 0000_0000h
110h ERM Memory n Error Address Register (EAR1) 32 RO 0000_0000h
22.3.2 ERM Configuration Register 0 (CR0)
22.3.2.1 Offset
Register Offset
CR0 0h
22.3.2.2 Function
This 32-bit control register configures the interrupt notification capability for each
supported memory channel between 0 and 7.
22.3.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ESCIE
0
ENCIE0
0
ESCIE
1
ENCIE1
0
Reserved
0
Reserved
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
0
Reserved
0
Reserved
0
Reserved
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 22 Error Reporting Module (ERM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 471
22.3.2.4 Fields
Field Function
31
ESCIE0
ESCIE0
Enable Memory 0 Single Correction Interrupt Notification
This field is initialized by hardware reset.
NOTE: See the chip-specific ERM information for details on Memory 0 mapping.
0b - Interrupt notification of Memory 0 single-bit correction events is disabled.
1b - Interrupt notification of Memory 0 single-bit correction events is enabled.
30
ENCIE0
ENCIE0
Enable Memory 0 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
NOTE: See the chip-specific ERM information for details on Memory 0 mapping.
0b - Interrupt notification of Memory 0 non-correctable error events is disabled.
1b - Interrupt notification of Memory 0 non-correctable error events is enabled.
29-28
—
Reserved
27
ESCIE1
ESCIE1
Enable Memory 1 Single Correction Interrupt Notification
This field is initialized by hardware reset.
NOTE: See the chip-specific ERM information for details on Memory 1 mapping.
0b - Interrupt notification of Memory 1 single-bit correction events is disabled.
1b - Interrupt notification of Memory 1 single-bit correction events is enabled.
26
ENCIE1
ENCIE1
Enable Memory 1 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
NOTE: See the chip-specific ERM information for details on Memory 1 mapping.
0b - Interrupt notification of Memory 1 non-correctable error events is disabled.
1b - Interrupt notification of Memory 1 non-correctable error events is enabled.
25-24
—
Reserved
23-22
—
Reserved
21-20
—
Reserved
19-18
—
Reserved
17-16
—
Reserved
15-14
—
Reserved
13-12 Reserved
Table continues on the next page...
ERM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
472 NXP Semiconductors
Field Function
—
11-10
—
Reserved
9-8
—
Reserved
7-6
—
Reserved
5-4
—
Reserved
3-2
—
Reserved
1-0
—
Reserved
22.3.3 ERM Status Register 0 (SR0)
22.3.3.1 Offset
Register Offset
SR0 10h
22.3.3.2 Function
This 32-bit register signals which types of ECC events have been detected for each
memory channel. The register signals the last memory event to be detected for each
supported memory channel between 0 and 7.
Chapter 22 Error Reporting Module (ERM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 473
22.3.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SBC0
NCE0
0
SBC1
NCE1
0
0
0
W
W1C
W1C
W1C
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.3.4 Fields
Field Function
31
SBC0
SBC0
Memory 0 Single-Bit Correction Event
This field is initialized by hardware reset.
Write 1 to clear this field. This write also clears the corresponding interrupt notification, if CR0[ESCIE0] is
enabled.
NOTE: See the chip-specific ERM information for details on Memory 0 mapping.
0b - No single-bit correction event on Memory 0 detected.
1b - Single-bit correction event on Memory 0 detected.
30
NCE0
NCE0
Memory 0 Non-Correctable Error Event
This field is initialized by hardware reset.
Write 1 to clear this field. This write also clears the corresponding interrupt notification, if CR0[ENCIE0] is
enabled.
NOTE: See the chip-specific ERM information for details on Memory 0 mapping.
0b - No non-correctable error event on Memory 0 detected.
1b - Non-correctable error event on Memory 0 detected.
29-28
—
Reserved
27
SBC1
SBC1
Memory 1 Single-Bit Correction Event
This field is initialized by hardware reset.
Write 1 to clear this field. This write also clears the corresponding interrupt notification, if CR0[ESCIE1] is
enabled.
NOTE: See the chip-specific ERM information for details on Memory 1 mapping.
Table continues on the next page...
ERM register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
474 NXP Semiconductors
Field Function
0b - No single-bit correction event on Memory 1 detected.
1b - Single-bit correction event on Memory 1 detected.
26
NCE1
NCE1
Memory 1 Non-Correctable Error Event
This field is initialized by hardware reset.
Write 1 to clear this field. This write also clears the corresponding interrupt notification, if CR0[ENCIE1] is
enabled.
NOTE: See the chip-specific ERM information for details on Memory 1 mapping.
0b - No non-correctable error event on Memory 1 detected.
1b - Non-correctable error event on Memory 1 detected.
25-24
—
Reserved
23-20
—
Reserved
19-16
—
Reserved
15-12
—
Reserved
11-8
—
Reserved
7-4
—
Reserved
3-0
—
Reserved
22.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)
22.3.4.1 Offset
Register Offset
EAR0 100h
EAR1 110h
Chapter 22 Error Reporting Module (ERM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 475
22.3.4.2 Function
Each ERM Memory n Error Address Register is a 32-bit register for capturing the address
of the last ECC event in Memory n, where n denotes the memory channel. Any attempted
write to EARn is ignored.
22.3.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.4.4 Fields
Field Function
31-0
EAR
EAR
Memory n Error Address — This field contains the faulting system address of the last recorded ECC
event on Memory n.
NOTE: See the chip-specific ERM information for details on Memory n mapping.
Functional description
22.4.1 Single-bit correction events
When a single-bit correction event on Memory n is detected, the ERM:
22.4
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
476 NXP Semiconductors
• Records the event by changing the value of the applicable Status Register bit
SRx[SBCn]to 1.
•Records the corresponding access address that initiated the event in the Memory n
Error Address Register: EARn (if this register is present for the channel).
The ERM holds event information only for the last reported event.
To clear the record of an event, write 1 to SRx[SBCn] to change its value to 0.
22.4.1.1 Optional interrupt notification for single-bit correction
events
The ERM provides an option to generate an interrupt notification upon the report of a
single-bit correction event. This sequence describes how to use the option:
1. To enable interrupt notification for single-bit correction events on Memory n, set
CRx[ESCIEn] to 1.
2. Subsequently, when a single-bit correction event on Memory n is detected, the ERM:
• Records the event and address, as usual.
• Additionally sends an interrupt notification corresponding to the event.
3. To clear both the record of an event and the corresponding interrupt notification,
write 1 to SRx[SBCn] to change its value to 0.
22.4.2 Non-correctable error events
When a non-correctable ECC error event on Memory n is detected, the ERM:
• Records the event by changing the value of the applicable Status Register bit:
SRx[NCEn]to 1.
•Records the corresponding access address that initiated the event in the Memory n
Error Address Register: EARn (if this register is present for the channel).
The ERM holds event information only for the last reported event.
To clear the record of an event, write 1 to SRx[NCEn] to change its value to 0.
Chapter 22 Error Reporting Module (ERM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 477
22.4.2.1 Optional interrupt notification for non-correctable error
events
The ERM provides an option to generate an interrupt notification upon the report of a
non-correctable ECC event. This sequence describes how to use the option:
1. To enable interrupt notifications for non-correctable error events on Memory n, set
CRx[ENCIEn] to 1.
2. Subsequently, when a non-correctable error event on Memory n is detected, the
ERM:
• Records the event and address as usual.
• Additionally sends an interrupt notification corresponding to the event.
3. To clear both the record of an event and the corresponding interrupt notification,
write 1 to SRx[NCEn] to change its value to 0.
22.5 Initialization
For each ERM channel, prepare the corresponding memory array before enabling ERM
interrupts about errors for that memory.
1. Initialize the memory to a known value so that the correct corresponding ECC
codeword is stored.
2. During the memory's initialization, if the ERM captures information about any ECC
error event, clear the corresponding SRx[SBCn] or SRx[NCEn] field that stores the
record of the event.
3. Program the applicable CRx[ESCIEn] and CRx[ENCIEn] fields to enable ERM
interrupts as desired.
Initialization
S32K1xx Series Reference Manual, Rev. 7, 04/2018
478 NXP Semiconductors
Chapter 23
Watchdog timer (WDOG)
Chip-specific WDOG information
23.1.1 WDOG clocks
The WDOG module has following selectable clock sources:
• Internal low power oscillator (LPO_CLK)
• Internal Slow IRC clock (SIRC)
• System oscillator clock (SOSC)
• Bus clock
NOTE
• For safety applications, WDOG should run on a different
clock than CMU.
• WDOG_CNT reset read value can vary depending on
timestamp, since it is a default running counter.
23.1.2 WDOG low-power modes
This table shows the WDOG low-power modes and the corresponding chip low-power
modes.
Wait mode is not supported in this device. See Module operation in available low power
modes for details on available power modes.
23.1
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 479
23.1.3 Default watchdog timeout
The timeout depends on the watchdog counter clock source. Following initial power on
the watchdog is clocked by the LPO128K_CLK and will issue a timeout after 1024
cycles. This results in the Watchdog timeout being generated after approximately 8 ms,
which will force a MCU reset. To avoid this condition, please ensure that the watchdog is
configured or refreshed before the 1024 cycles have elapsed.
23.2 Introduction
The Watchdog Timer (WDOG) module is an independent timer that is available for
system use. It provides a safety feature to ensure that software is executing as planned
and that the CPU is not stuck in an infinite loop or executing unintended code. If the
WDOG module is not serviced (refreshed) within a certain period, it resets the MCU.
23.2.1 Features
Features of the WDOG module include:
• Configurable clock source inputs independent from the bus clock
• Bus clock
• LPO clock
• INTCLK (internal clock)
• ERCLK (external reference clock)
• Programmable timeout period
• Programmable 16-bit timeout value
• Optional fixed 256 clock prescaler when longer timeout periods are needed
• Robust write sequence for counter refresh
• Refresh sequence of writing 0xA602 and then 0xB480
• Window mode option for the refresh mechanism
• Programmable 16-bit window value
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
480 NXP Semiconductors
• Provides robust check that program flow is faster than expected
• Early refresh attempts trigger a reset.
• Optional timeout interrupt to allow post-processing diagnostics
• Interrupt request to CPU with interrupt vector for an interrupt service routine
(ISR)
• Forced reset occurs 128 bus clocks after the interrupt vector fetch.
• Configuration bits are write-once-after-reset to ensure watchdog configuration cannot
be mistakenly altered.
• Robust write sequence for unlocking write-once configuration bits
• Unlock sequence of writing 0xC520 and then 0xD928 for allowing updates to
write-once configuration bits
• Software must make updates within 128 bus clocks after unlocking and before
WDOG closing unlock window.
23.2.2 Block diagram
The following figure shows a block diagram of the WDOG module.
MUX
MUX
MUX
ERCLK
(external reference clock)
UPDATE
EN
CLK PRES WIN INT
BUS_CLK
256
16-bit Window Register
0xD928
0xC520
Control Status
Bus Cycle
Disable Protect
Bit Write Control
Protect
Window
Reset
Counter
Overflow
Counter
Write Control
0xA602
0xB480
16-bit Timeout Value Register
Refresh Sequence
Compare Logic
16-bit Counter Register
Compare Logic
Control
Logic
Bus
CPU Reset
IRQ Interrupt
Clock Delay
Backup Reset
LPO_CLK
INTCLK
(internal clock)
Figure 23-1. WDOG block diagram
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 481
23.3 Memory map and register definition
23.3.1 WDOG register descriptions
23.3.1.1 WDOG Memory map
WDOG base address: 4005_2000h
Offset Register Width
(In bits)
Access Reset value
0h Watchdog Control and Status Register (CS) 32 RW 0000_2980h
4h Watchdog Counter Register (CNT) 32 RW 0000_0000h
8h Watchdog Timeout Value Register (TOVAL) 32 RW 0000_0400h
Ch Watchdog Window Register (WIN) 32 RW 0000_0000h
23.3.1.2 Watchdog Control and Status Register (CS)
23.3.1.2.1 Offset
Register Offset
CS 0h
23.3.1.2.2 Function
This section describes the function of Watchdog Control and Status Register.
NOTE
TST is cleared (0:0) on POR only. Any other reset does not
affect the value of this field.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
482 NXP Semiconductors
23.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WIN
FL
G
CMD32EN
PRE
S
ULK
RC
S
CLK
E
N
INT
UPDATE
TST
DBG
WAIT
STOP
W
W1C
Reset 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0
23.3.1.2.4 Fields
Field Function
31-16
—
Reserved
15
WIN
Watchdog Window
This write-once bit enables window mode. See the Window mode section.
0b - Window mode disabled.
1b - Window mode enabled.
14
FLG
Watchdog Interrupt Flag
This bit is an interrupt indicator when INT is set in control and status register 1. Write 1 to clear it.
0b - No interrupt occurred.
1b - An interrupt occurred.
13
CMD32EN
Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write
words
This is write-once field, and the user needs to unlock WDOG after writing this field for reconfiguration.
0b - Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is
supported.
1b - Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT
supported.
12
PRES
Watchdog prescaler
This write-once bit enables a fixed 256 pre-scaling of watchdog counter reference clock. (The block
diagram shows this clock divider option.)
0b - 256 prescaler disabled.
1b - 256 prescaler enabled.
11
ULK
Unlock status
This read-only bit indicates whether WDOG is unlocked or not.
0b - WDOG is locked.
1b - WDOG is unlocked.
10
RCS
Reconfiguration Success
Table continues on the next page...
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 483
Field Function
This read-only bit indicates whether the reconfiguration is successful or not. Default reset value is 0.This
bit is set when new configuration takes effect, and is cleared by successful unlock command.
0b - Reconfiguring WDOG.
1b - Reconfiguration is successful.
9-8
CLK
Watchdog Clock
This write-once field indicates the clock source that feeds the watchdog counter. See the Clock source
section.
00b - Bus clock
01b - LPO clock
10b - INTCLK (internal clock)
11b - ERCLK (external reference clock)
7
EN
Watchdog Enable
This write-once bit enables the watchdog counter to start counting.
0b - Watchdog disabled.
1b - Watchdog enabled.
6
INT
Watchdog Interrupt
This write-once bit configures the watchdog to immediately generate an interrupt request upon a reset-
triggering event (timeout or illegal write to the watchdog), before forcing a reset. After the interrupt vector
fetch (which comes after the reset-triggering event), the reset occurs after a delay of 128 bus clocks.
0b - Watchdog interrupts are disabled. Watchdog resets are not delayed.
1b - Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the
interrupt vector fetch.
5
UPDATE
Allow updates
This write-once bit allows software to reconfigure the watchdog without a reset.
0b - Updates not allowed. After the initial configuration, the watchdog cannot be later modified
without forcing a reset.
1b - Updates allowed. Software can modify the watchdog configuration registers within 128 bus
clocks after performing the unlock write sequence.
4-3
TST
Watchdog Test
Enables the fast test mode. The test mode allows software to exercise all bits of the counter to
demonstrate that the watchdog is functioning properly. See the Fast testing of the watchdog section.
This write-once field is cleared (0:0) on POR only. Any other reset does not affect the value of this field.
00b - Watchdog test mode disabled.
01b - Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog,
software should use this setting to indicate that the watchdog is functioning normally in user mode.
10b - Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with
TOVAL[TOVALLOW].
11b - Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with
TOVAL[TOVALHIGH].
2
DBG
Debug Enable
This write-once bit enables the watchdog to operate when the chip is in debug mode.
0b - Watchdog disabled in chip debug mode.
1b - Watchdog enabled in chip debug mode.
1
WAIT
Wait Enable
This write-once bit enables the watchdog to operate when the chip is in wait mode.
0b - Watchdog disabled in chip wait mode.
1b - Watchdog enabled in chip wait mode.
0
STOP
Stop Enable
This write-once bit enables the watchdog to operate when the chip is in stop mode.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
484 NXP Semiconductors
Field Function
0b - Watchdog disabled in chip stop mode.
1b - Watchdog enabled in chip stop mode.
23.3.1.3 Watchdog Counter Register (CNT)
23.3.1.3.1 Offset
Register Offset
CNT 4h
23.3.1.3.2 Function
This section describes the watchdog counter register.
The watchdog counter register provides access to the value of the free-running watchdog
counter. Software can read the counter register at any time.
Software cannot write directly to the watchdog counter; however, two write sequences to
these registers have special functions:
1. The refresh sequence resets the watchdog counter to 0x0000. See the "Refreshing the
Watchdog" section.
2. The unlock sequence allows the watchdog to be reconfigured without forcing a reset
(when CS[UPDATE] = 1). See the "Configure for reconfigurable" section.
NOTE
All other writes to this register are illegal and force a reset.
23.3.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCNTHIGH CNTLOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 485
23.3.1.3.4 Fields
Field Function
31-16
—
Reserved
15-8
CNTHIGH
High byte of the Watchdog Counter
7-0
CNTLOW
Low byte of the Watchdog Counter
23.3.1.4 Watchdog Timeout Value Register (TOVAL)
23.3.1.4.1 Offset
Register Offset
TOVAL 8h
23.3.1.4.2 Function
This section describes the watchdog timeout value register. TOVAL contains the 16-bit
value used to set the timeout period of the watchdog.
The watchdog counter (CNT) is continuously compared with the timeout value
(TOVAL). If the counter reaches the timeout value, the watchdog forces a reset triggering
event.
NOTE
Do not write 0 to the TOVAL register (if CS[TST]=11b, then
TOVALHIGH cannot be written as 0; if CS[TST]=10b, then
TOVALLOW cannot be 0); otherwise, the watchdog always
generates a reset.
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
486 NXP Semiconductors
23.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTOVALHIGH TOVALLOW
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
23.3.1.4.4 Fields
Field Function
31-16
—
Reserved
15-8
TOVALHIGH
High byte of the timeout value
7-0
TOVALLOW
Low byte of the timeout value
23.3.1.5 Watchdog Window Register (WIN)
23.3.1.5.1 Offset
Register Offset
WIN Ch
23.3.1.5.2 Function
This section describes the watchdog window register. When window mode is enabled
(CS[WIN] is set), The WIN register determines the earliest time that a refresh sequence is
considered valid. See the Watchdog refresh mechanism section.
The WIN register value must be less than the TOVAL register value.
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 487
23.3.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RWINHIGH WINLOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23.3.1.5.4 Fields
Field Function
31-16
—
Reserved
15-8
WINHIGH
High byte of Watchdog Window
7-0
WINLOW
Low byte of Watchdog Window
23.4 Functional description
The WDOG module provides a fail safe mechanism to ensure the system can be reset to a
known state of operation in case of system failure, such as the CPU clock stopping or
there being a run away condition in the software code. The watchdog counter runs
continuously off a selectable clock source and expects to be serviced (refreshed)
periodically. If it is not, it generates a reset triggering event.
23.4.1 Clock source
The watchdog counter has the following clock source options selected by programming
CS[CLK]:
• bus clock
• Low-Power Oscillator clock (LPO_CLK)
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
488 NXP Semiconductors
• internal clock
• external clock
The options allow software to select a clock source independent of the bus clock for
applications that need to meet more robust safety requirements. Using a clock source
other than the bus clock ensures that the watchdog counter continues to run if the bus
clock is somehow halted; see Backup reset.
NOTE
The default clock source of WDOG should be enabled after its
funcitonal reset is deasserted, for the WDOG module to
function properly.
An optional fixed prescaler for all clock sources allows for longer timeout periods. When
CS[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog
counter.
The following table summarizes the different watchdog timeout periods which could be
available, as an example.
Table 23-1. Watchdog timeout availability
Reference clock Prescaler Watchdog time-out availability
REF_CLK Pass through 1×RCP to 65535×RCP 1
Enable 256×RCP to 16776960×RCP
1. RCP means Reference Clock Period.
NOTE
When the programmer switches clock sources during
reconfiguration, the watchdog hardware holds the counter at
zero for 2.5 periods of the previous clock source and 2.5
periods of the new clock source after the configuration time
period ( 128 bus clocks) ends. This delay ensures a smooth
transition before restarting the counter with the new
configuration.
23.4.2 Watchdog refresh mechanism
The watchdog resets the MCU if the watchdog counter is not refreshed. A robust refresh
mechanism makes it very unlikely that the watchdog can be refreshed by runaway code.
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 489
To refresh the watchdog counter, software must execute a refresh write sequence before
the timeout period expires. In addition, if window mode is used, software must not start
the refresh sequence until after the time value set in the WIN register. See the following
figure.
WDOG counter
WIN Refresh opportunity
in window mode
TOVAL
0Time
Refresh opportunity (not in window mode)
Figure 23-2. Refresh opportunity for the Watchdog counter
23.4.2.1 Window mode
Software finishing its main control loop faster than expected could be an indication of a
problem. Depending on the requirements of the application, the WDOG can be
programmed to force a reset when refresh attempts are early.
When Window mode is enabled, the watchdog must be refreshed after the counter has
reached a minimum expected time value; otherwise, the watchdog resets the MCU. The
minimum expected time value is specified in the WIN register. Setting CS[WIN] enables
Window mode.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
490 NXP Semiconductors
23.4.2.2 Refreshing the Watchdog
The refresh write sequence can be
• either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4,
0x80) if WDOG_CS[CMD32EN] is 0;
• one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1.
to the CNT register. Both methods must occur before the WDG timeout; otherwise, the
watchdog resets the MCU.
Note
Before starting the refresh sequence, disable the global
interrupts. Otherwise, an interrupt could effectively invalidate
the refresh sequence, if the interrupt occurs before the refresh
writes finish. After the sequence finishes, restore the global
interrupt control state.
The example codes can be found at the end of this chapter.
Configuring the Watchdog
23.4.3.1 Configuring the Watchdog Once
All watchdog control bits, timeout value, and window value are write-once after
reset . This means that after a write has occurred they cannot be changed unless a
reset occurs. This is guaranteed by the user configuring the window and timeout value
first, followed by the other control bits, and ensuring that CS[UPDATE] is also set to 0.
This provides a robust mechanism to configure the watchdog and ensure that a runaway
condition cannot mistakenly disable or modify the watchdog configuration after
configured.
The new configuration takes effect only after all registers except CNT are written after
reset. Otherwise, the WDOG uses the reset values by default. If window mode is not used
(CS[WIN] is 0), writing to WIN is not required to make the new configuration take
effect.
23.4.3.2 Reconfiguring the Watchdog
In some cases (like when supporting a bootloader function), you may want to reconfigure
or disable the watchdog, without forcing a reset first.
23.4.3
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 491
• By setting CS[UPDATE] to 1 on the initial configuration of the watchdog after a
reset, you can reconfigure the watchdog at any time by executing an unlock
sequence.
• Conversely, if CS[UPDATE] remains 0, the only way to reconfigure the watchdog is
by initiating a reset.
The unlock sequence is similar to the refresh sequence but uses different values.
23.4.3.2.1 Unlocking the Watchdog
The unlock sequence is a write to the CNT register of 0xC520 followed by 0xD928
within 16 bus clocks at any time after the watchdog has been configured. On completing
the unlock sequence, the user must reconfigure the watchdog within 128 bus clocks;
otherwise, the watchdog closes the unlock window.
NOTE
Due to the 128 bus clocks requirement for reconfiguring the
watchdog, some delays must be inserted before executing
STOP or WAIT instructions after reconfiguring the watchdog.
This ensures that the watchdog's new configuration takes effect
before the MCU enters low power mode. Otherwise, the MCU
may not be waken up from low power mode.
The example codes can be found at end of this chapter.
23.4.4 Using interrupts to delay resets
•When interrupts are enabled (CS[INT] = 1): After a reset-triggering event (like a
counter timeout or invalid refresh attempt), the watchdog first generates an interrupt
request. Next, the watchdog delays 128 bus clocks (from the interrupt vector fetch,
not the reset-triggering event) before forcing a reset, to allow the interrupt service
routine (ISR) to perform tasks (like analyzing the stack to debug code).
•When interrupts are disabled (CS[INT] = 0): the watchdog does not delay the
forcing a reset.
23.4.5 Backup reset
NOTE
A clock source other than the bus clock must be used as the
reference clock for the counter; otherwise, the backup reset
function is not available.
Configuring the Watchdog
S32K1xx Series Reference Manual, Rev. 7, 04/2018
492 NXP Semiconductors
The backup reset function is a safeguard feature that independently generates a reset in
case the main WDOG logic loses its clock (the bus clock) and can no longer monitor the
counter. If the watchdog counter overflows twice in succession (without an intervening
reset), the backup reset function takes effect and generates a reset.
Backup reset becomes valid when interrupt is enabled and the watchdog clock is from
non bus clock. If interrupt is enabled, once the bus clock is cut off before exiting interrupt
routine, the normal watchdog reset will be blocked. Under this case, the second overflow
will cause backup reset directly.
23.4.6 Functionality in debug and low-power modes
By default, the watchdog is not functional in Debug mode, Wait mode, or Stop mode.
However, the watchdog can remain functional in these modes as follows:
•For Debug mode, set CS[DBG]. (This way the watchdog is functional in Debug
mode even when the CPU is held by the Debug module.)
•For Wait mode, set CS[WAIT].
•For Stop mode, set CS[STOP], CS[WAIT], and ensure the clock source is active in
Stop mode.
NOTE
The watchdog can generate interrupt in Stop mode.
For Debug mode and Stop mode, in addition to the above
configurations, a clock source other than the bus clock must be
used as the reference clock for the counter; otherwise, the
watchdog cannot function.
23.4.7 Fast testing of the watchdog
Before executing application code in safety critical applications, users are required to test
that the watchdog works as expected and resets the MCU. Testing every bit of a 16-bit
counter by letting it run to the overflow value takes a relatively long time (64 k clocks).
To help minimize the startup delay for application code after reset, the watchdog has a
feature to test the watchdog more quickly by splitting the counter into its constituent
byte-wide stages. The low and high bytes are run independently and tested for timeout
against the corresponding byte of the timeout value register. (For complete coverage
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 493
when testing the high byte of the counter, the test feature feeds the input clock via the 8th
bit of the low byte, thus ensuring that the overflow connection from the low byte to the
high byte is tested.)
Using this test feature reduces the test time to 512 clocks (not including overhead, such as
user configuration and reset vector fetches). To further speed testing, use a faster clock
(such as the bus clock) for the counter reference.
On a power-on reset, the POR bit in the system reset register is set, indicating the user
should perform the WDOG fast test.
23.4.7.1 Testing each byte of the counter
The test procedure follows these steps:
1. Program the preferred watchdog timeout value in the TOVAL register during the
watchdog configuration time period.
2. Select a byte of the counter to test using the CS[TST] = 10b for the low byte;
CS[TST] = 11b for the high byte.
3. Wait for the watchdog to timeout. Optionally, in the idle loop, increment RAM
locations as a parallel software counter for later comparison. Because the RAM is not
affected by a watchdog reset, the timeout period of the watchdog counter can be
compared with the software counter to verify the timeout period has occurred as
expected.
4. The watchdog counter times out and forces a reset.
5. Confirm the WDOG flag in the system reset register is set, indicating that the
watchdog caused the reset. (The POR flag remains clear.)
6. Confirm that CS[TST] shows a test (10b or 11b) was performed.
If confirmed, the count and compare functions work for the selected byte. Repeat the
procedure, selecting the other byte in step 2.
NOTE
CS[TST] is cleared by a POR only and not affected by other
resets.
23.4.7.2 Entering user mode
After successfully testing the low and high bytes of the watchdog counter, the user can
configure CS[TST] to 01b to indicate the watchdog is ready for use in application user
mode. Thus if a reset occurs again, software can recognize the reset trigger as a real
watchdog reset caused by runaway or faulty application code.
Configuring the Watchdog
S32K1xx Series Reference Manual, Rev. 7, 04/2018
494 NXP Semiconductors
As an ongoing test when using the default clock source, software can periodically read
the CNT register to ensure the counter is being incremented.
23.5 Application Information
The watchdog is enabled by default after reset. To disable or reconfigure the watchdog, it
is better to be done before the first watchdog timeout. It is suggested to disable or
reconfigure the watchdog at the very beginning of the software code, e.g. beginning of
the startup or main function.
NOTE
When the watchdog is configured by user, it needs at least 2.5
periods of watchdog clock to take effect. This means interval
between two configures by user must be larger than 2.5 clocks.
NOTE
When Chip startup from BOOT ROM then jump to flash, the
watchdog would be disabled in the beginning of bootloader,
and enabled when bootloader exits. If there is any code in the
flash program want to reconfigure the watchdog, it must be run
2.5 watchdog clocks later after the bootloader exits.
To disable or reconfigure the watchdog without forcing a reset, WDOG_CS[UPDATE]
bit must be set during the initial configuration of the WDOG module. Then, the unlock
sequence can be used at any time within the timeout limit to reconfigure the watchdog.
23.5.1 Disable Watchdog
To disable the watchdog, first do unlock sequence, then unset the WDOG_CS[EN] bit.
The code snippet below shows an example for 32-bit write.
DisableInterrupts; // disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
WDOG_CS &= ~WDOG_CS_EN_MASK; //disable watchdog
EnableInterrupts; //enable global interrupt
23.5.2 Disable Watchdog after Reset
All of watchdog registers are unlocked by reset. Therefore, unlock sequence is
unnecessary, but it needs to write all of watchdog registers to make the new configuration
take effect. The code snippet below shows an example of disabling watchdog after reset.
Chapter 23 Watchdog timer (WDOG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 495
DisableInterrupts; // disable global interrupt
WDOG_CS &= ~WDOG_CS_EN_MASK; // disable watchdog
WDOG_TOVAL= 0xFFFF;
while(WDOG_CS[ULK]); // waiting for lock
while(~WDOG_CS[RCS]); // waiting for new configuration to take effect
EnableInterrupts; // enable global interrupt
23.5.3 Configure Watchdog
The watchdog can be configured once by set the WDOG_CS[UPDATE]=0. After that,
the watchdog cannot be reconfigured until a reset. If set WDOG_CS[UPDATE]=1 when
configuring the watchdog, the watchdog can be reconfigured without forcing a reset. The
following example code shows how to configure the watchdog without window mode,
clock source as LPO, interrupt enabled and timeout value to 256 clocks. The code snippet
below shows an example for 32-bit write.
Configure once
DisableInterrupts; // disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
while(WDOG_CS[ULK]==0); //wait until registers are unlocked
WDOG_TOVAL = 256; //set timeout value
WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |
WDOG_CS_WIN(0) | WDOG_CS_UPDATE(0);
while(WDOG_CS[RCS]==0); //wait until new configuration takes effect
EnableInterrupts; //enable global interrupt
Configure for reconfigurable
DisableInterrupts; //disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
while(WDOG_CS[ULK]==0); //wait until registers are unlocked
WDOG_TOVAL = 256; //set timeout value
WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |
WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1);
while(WDOG_CS[RCS]==0); //wait until new configuration takes effect
EnableInterrupts; //enable global interrupt
23.5.4 Refreshing the Watchdog
To refresh the watchdog and reset the watchdog counter to zero, a refresh sequence is
required. The code snippet below shows an example for 32-bit write.
DisableInterrupts; // disable global interrupt
WDOG_CNT = 0xB480A602; // refresh watchdog
EnableInterrupts; // enable global interrupt
Application Information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
496 NXP Semiconductors
Chapter 24
Cyclic Redundancy Check (CRC)
24.1 Chip-specific CRC information
NOTE
All input bytes need to be byte transposed. Any additional
transpose will be governed by the CRC protocol requirement.
24.2 Introduction
The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error
detection.
The CRC module provides a programmable polynomial and other parameters required to
implement a 16-bit or 32-bit CRC standard.
The 16/32-bit code is calculated for 32 bits of data at a time.
24.2.1 Features
Features of the CRC module include:
• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
This option is required for certain CRC standards. A bytewise transpose operation is
not possible when accessing the CRC data register via 8-bit accesses. In this case, the
user's software must perform the bytewise transpose function.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 497
24.2.2 Block diagram
The following is a block diagram of the CRC.
WAS
Polynomial
MUX
CRC Engine
NOT
Logic
Reverse
Logic
Reverse
Logic
[31:24][
[23:16]
[15:8]
[7:0] CRC Data
Seed
TOT TOTRFXOR
Combine
Logic
TCRC
[31:24]
[23:16]
[15:8]
[7:0]
16-/32-bit Select
CRC Data Register
CRC Polynomial
Register
[31:24]
[23:16]
[15:8]
[7:0]
CRC Data Register
Checksum
Data
Figure 24-1. Programmable cyclic redundancy check (CRC) block diagram
24.2.3 Modes of operation
Various MCU modes affect the CRC module's functionality.
24.2.3.1 Run mode
This is the basic mode of operation.
24.2.3.2 Low-power modes (Stop)
Any CRC calculation in progress stops when the MCU enters a low-power mode that
disables the module clock. It resumes after the clock is enabled or via the system reset for
exiting the low-power mode. Clock gating for this module is dependent on the MCU.
24.3 Memory map and register descriptions
24.3.1 CRC register descriptions
Memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
498 NXP Semiconductors
24.3.1.1 CRC Memory map
CRC base address: 4003_2000h
Offset Register Width
(In bits)
Access Reset value
0h CRC Data register (DATA) 32 RW FFFF_FFFFh
4h CRC Polynomial register (GPOLY) 32 RW 0000_1021h
8h CRC Control register (CTRL) 32 RW 0000_0000h
24.3.1.2 CRC Data register (DATA)
24.3.1.2.1 Offset
Register Offset
DATA 0h
24.3.1.2.2 Function
The CRC Data register contains the value of the seed, data, and checksum. When
CTRL[WAS] is set, any write to the data register is regarded as the seed value. When
CTRL[WAS] is cleared, any write to the data register is regarded as data for general CRC
computation.
In 16-bit CRC mode, the HU and HL fields are not used for programming the seed value,
and reads of these fields return an indeterminate value. In 32-bit CRC mode, all fields are
used for programming the seed value.
When programming data values, the values can be written 8 bits, 16 bits, or 32 bits at a
time, provided all bytes are contiguous; with MSB of data value written first.
After all data values are written, the CRC result can be read from this data register. In 16-
bit CRC mode, the CRC result is available in the LU and LL fields. In 32-bit CRC mode,
all fields contain the result. Reads of this register at any time return the intermediate CRC
value, provided the CRC module is configured.
Chapter 24 Cyclic Redundancy Check (CRC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 499
24.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RHU HL
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLU LL
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
24.3.1.2.4 Fields
Field Function
31-24
HU
CRC High Upper Byte
In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming a seed value. In 32-bit
CRC mode (CTRL[TCRC] is 1), values written to this field are part of the seed value when CTRL[WAS] is
1. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation in both 16-bit
and 32-bit CRC modes.
23-16
HL
CRC High Lower Byte
In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming a seed value. In 32-bit
CRC mode (CTRL[TCRC] is 1), values written to this field are part of the seed value when CTRL[WAS] is
1. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation in both 16-bit
and 32-bit CRC modes.
15-8
LU
CRC Low Upper Byte
When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0,
data written to this field is used for CRC checksum generation.
7-0
LL
CRC Low Lower Byte
When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0,
data written to this field is used for CRC checksum generation.
24.3.1.3 CRC Polynomial register (GPOLY)
24.3.1.3.1 Offset
Register Offset
GPOLY 4h
Memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
500 NXP Semiconductors
24.3.1.3.2 Function
This register contains the value of the polynomial for the CRC calculation. The HIGH
field contains the upper 16 bits of the CRC polynomial, which are used only in 32-bit
CRC mode. Writes to the HIGH field are ignored in 16-bit CRC mode. The LOW field
contains the lower 16 bits of the CRC polynomial, which are used in both 16- and 32-bit
CRC modes.
24.3.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RHIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLOW
W
Reset 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1
24.3.1.3.4 Fields
Field Function
31-16
HIGH
High Polynominal Half-word
Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not writable in 16-bit CRC
mode (CTRL[TCRC] is 0).
15-0
LOW
Low Polynominal Half-word
Writable and readable in both 32-bit and 16-bit CRC modes.
24.3.1.4 CRC Control register (CTRL)
24.3.1.4.1 Offset
Register Offset
CTRL 8h
Chapter 24 Cyclic Redundancy Check (CRC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 501
24.3.1.4.2 Function
This register controls the configuration and working of the CRC module. Appropriate bits
must be set before starting a new CRC calculation. A new CRC calculation is initialized
by asserting CTRL[WAS] and then writing the seed into the CRC data register.
24.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
TOT
TOTR
0
FXOR
WAS
TCRC
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24.3.1.4.4 Fields
Field Function
31-30
TOT
Type Of Transpose For Writes
Defines the transpose configuration of the data written to the CRC data register. See the description of
the transpose feature for the available transpose options.
00b - No transposition.
01b - Bits in bytes are transposed; bytes are not transposed.
10b - Both bits in bytes and bytes are transposed.
11b - Only bytes are transposed; no bits in a byte are transposed.
29-28
TOTR
Type Of Transpose For Read
Identifies the transpose configuration of the value read from the CRC Data register. See the description of
the transpose feature for the available transpose options.
00b - No transposition.
01b - Bits in bytes are transposed; bytes are not transposed.
10b - Both bits in bytes and bytes are transposed.
11b - Only bytes are transposed; no bits in a byte are transposed.
27
—
Reserved
26
FXOR
Complement Read Of CRC Data Register
Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or 0xFFFF. Asserting
this bit enables on the fly complementing of read data.
0b - No XOR on reading.
1b - Invert or complement the read value of the CRC Data register.
25
WAS
Write CRC Data Register As Seed
When asserted, a value written to the CRC data register is considered a seed value. When deasserted, a
value written to the CRC data register is taken as data for CRC computation.
Table continues on the next page...
Memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
502 NXP Semiconductors
Field Function
0b - Writes to the CRC data register are data values.
1b - Writes to the CRC data register are seed values.
24
TCRC
TCRC
Width of CRC protocol.
0b - 16-bit CRC protocol.
1b - 32-bit CRC protocol.
23-0
—
Reserved
24.4 Functional description
24.4.1 CRC initialization/reinitialization
To enable the CRC calculation, the user must program CRC_CTRL[WAS],
CRC_GPOLY,necessary parameters for transposition and CRC result inversion in the
applicable registers. Asserting CRC_CTRL[WAS] enables the programming of the seed
value into the CRC_DATA register.
After a completed CRC calculation, the module can be reinitialized for a new CRC
computation by reasserting CRC_CTRL[WAS] and programming a new, or previously
used, seed value. All other parameters must be set before programming the seed value
and subsequent data values.
24.4.2 CRC calculations
In 16-bit and 32-bit CRC modes, data values can be programmed 8 bits, 16 bits, or 32 bits
at a time, provided all bytes are contiguous. Noncontiguous bytes can lead to an incorrect
CRC computation.
24.4.2.1 16-bit CRC
To compute a 16-bit CRC:
1. Clear CRC_CTRL[TCRC] to enable 16-bit CRC mode.
2. Program the transpose and complement options in the CTRL register as required for
the CRC calculation. See Transpose feature and CRC result complement for details.
Chapter 24 Cyclic Redundancy Check (CRC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 503
3. Write a 16-bit polynomial to the CRC_GPOLY[LOW] field. The
CRC_GPOLY[HIGH] field is not usable in 16-bit CRC mode.
4. Set CRC_CTRL[WAS] to program the seed value.
5. Write a 16-bit seed to CRC_DATA[LU:LL]. CRC_DATA[HU:HL] are not used.
6. Clear CRC_CTRL[WAS] to start writing data values.
7. Write data values into CRC_DATA[HU:HL:LU:LL]. A CRC is computed on every
data value write, and the intermediate CRC result is stored back into
CRC_DATA[LU:LL].
8. When all values have been written, read the final CRC result from
CRC_DATA[LU:LL].
Transpose and complement operations are performed on the fly while reading or writing
values. See Transpose feature and CRC result complement for details.
24.4.2.2 32-bit CRC
To compute a 32-bit CRC:
1. Set CRC_CTRL[TCRC] to enable 32-bit CRC mode.
2. Program the transpose and complement options in the CTRL register as required for
the CRC calculation. See Transpose feature and CRC result complement for details.
3. Write a 32-bit polynomial to CRC_GPOLY[HIGH:LOW].
4. Set CRC_CTRL[WAS] to program the seed value.
5. Write a 32-bit seed to CRC_DATA[HU:HL:LU:LL].
6. Clear CRC_CTRL[WAS] to start writing data values.
7. Write data values into CRC_DATA[HU:HL:LU:LL]. A CRC is computed on every
data value write, and the intermediate CRC result is stored back into
CRC_DATA[HU:HL:LU:LL].
8. When all values have been written, read the final CRC result from
CRC_DATA[HU:HL:LU:LL]. The CRC is calculated bytewise, and two clocks are
required to complete one CRC calculation.
Transpose and complement operations are performed on the fly while reading or writing
values. See Transpose feature and CRC result complement for details.
24.4.3 Transpose feature
By default, the transpose feature is not enabled. However, some CRC standards require
the input data and/or the final checksum to be transposed. The user software has the
option to configure each transpose operation separately, as desired by the CRC standard.
The data is transposed on the fly while being read or written.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
504 NXP Semiconductors
Some protocols use little endian format for the data stream to calculate a CRC. In this
case, the transpose feature usefully flips the bits. This transpose option is one of the types
supported by the CRC module.
24.4.3.1 Types of transpose
The CRC module provides several types of transpose functions to flip the bits and/or
bytes, for both writing input data and reading the CRC result, separately using the
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used.
The following types of transpose functions are available for writing to and reading from
the CRC data register:
1. CTRL[TOT] or CTRL[TOTR] is 00.
No transposition occurs.
2. CTRL[TOT] or CTRL[TOTR] is 01
Bits in a byte are transposed, while bytes are not transposed.
reg[31:0] becomes {reg[24:31], reg[16:23], reg[8:15], reg[0:7]}
15
15
8
7
0
0
7
8
31
31
24
23
16
16
23
24
Figure 24-2. Transpose type 01
3. CTRL[TOT] or CTRL[TOTR] is 10.
Both bits in bytes and bytes are transposed.
reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]}
31
31 0
0
Figure 24-3. Transpose type 10
4. CTRL[TOT] or CTRL[TOTR] is 11.
Chapter 24 Cyclic Redundancy Check (CRC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 505
Bytes are transposed, but bits are not transposed.
reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]}
15
24 16
0
31
23
7
8
31
8
0
16
15
7
23
24
Figure 24-4. Transpose type 11
NOTE
For 8-bit and 16-bit write accesses to the CRC data register, the
data is transposed with zeros on the unused byte or bytes
(taking 32 bits as a whole), but the CRC is calculated on the
valid byte(s) only. When reading the CRC data register for a
16-bit CRC result and using transpose options 10 and 11, the
resulting value after transposition resides in the CRC[HU:HL]
fields. The user software must account for this situation when
reading the 16-bit CRC result, so reading 32 bits is preferred.
24.4.4 CRC result complement
When CTRL[FXOR] is set, the checksum is complemented. The CRC result complement
function outputs the complement of the checksum value stored in the CRC data register
every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the
CRC data register accesses the raw checksum value.
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
506 NXP Semiconductors
Chapter 25
Reset and Boot
25.1 Introduction
This table shows the reset sources that are supported.
Table 25-1. Reset sources
Reset sources Description
POR reset • Power-on reset (POR)
System resets • External pin reset (PIN)
•Low voltage detect (LVD)
•Watchdog reset
•Loss-of-clock (LOC) reset
•Loss-of-lock (LOL) reset
•Stop mode acknowledge error (SACKERR)
•Software reset (SW)
•Lockup reset (LOCKUP)
•MDM DAP system reset
Debug reset • JTAG reset
25.2 Reset
This section discusses basic reset mechanisms and sources. Some peripheral modules that
cause resets can be configured to cause interrupts instead. See the individual module
chapters for more information.
Each reset source has an associated field in the Reset Control Module (RCM) System
Reset Status (RCM_SRS) register. Besides immediate system reset, the RCM also
supports optional configurable delayed system reset while an interrupt is generated. This
provides software an option to perform a graceful shutdown.
The MCU exits reset in RUN mode where the CPU is executing code. See Boot for more
details.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 507
25.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the
POR detect voltage (VPOR), the POR circuit causes a POR reset condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has
risen above the LVD low voltage detect threshold (VLVD). Following a POR, the MCU
writes 1 to the POR and LVD fields in RCM_SRS register.
Out of POR, both RCM_SRS[POR] and RCM_SRS[LVD] are configured as 1 by MCU.
While normal operation, if device supply goes below VPOR, MCU writes 1 to both
RCM_SRS[POR] and RCM_SRS[LVD]. While normal operation, if device supply goes
below VLVD (provided LVD is enabled to generate a reset) or VLVR but above VPOR,
MCU writes 1 to RCM_SRS[LVD].
25.2.2 System reset sources
Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it:
• Reads the start stack pointer (SP) (SP_main) from vector-table offset 0
• Reads the start program counter (PC) from vector-table offset 4
• Writes 0xFFFF_FFFF to the Link Register (LR)
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them are configured
for their analog functions after reset.
During and following a reset, the JTAG pins have their associated input pins configured
as:
• TDI as pullup (PU)
• TCK as pulldown (PD)
• TMS as pullup
and associated output pin configured as:
• TDO with no pull-down or pull-up
Reset
S32K1xx Series Reference Manual, Rev. 7, 04/2018
508 NXP Semiconductors
25.2.2.1 External pin reset
RESET_B is a shared pin (See IO Signal Description Input Multiplexing sheet(s)
attached to the Reference Manual). The user must configure the corresponding
PORT_PCR register prior to using this pin as RESET_B. On any reset event, the MCU
configures the corresponding pad as RESET_B pad. Asserting RESET_B wakes the
MCU from any mode. During a pin reset, the MCU writes 1 to RCM_SRS[PIN].
25.2.2.1.1 RESET_B pin filter
The RESET_B pin filter supports filtering from both the 128 kHz LPO clock and the bus
clock. RCM_RPC[RSTFLTSS], RCM_RPC[RSTFLTSRW], and
RCM_RPC[RSTFLTSEL] control this functionality. The filters are asynchronously reset
on chip POR. The reset value for each filter assumes the RESET_B pin is negated.
For all stop modes where LPO clock is still active, the only filtering option is the LPO
clock filter. The filtering logic either switches to bypass operation or has continued
filtering operation depending on the filtering mode selected as described in RCM_RPC
register.
The LPO filter has a fixed filter value. The pulses upto 2 LPO128K_CLK cycles will
always be filtered. The pulses longer than 3 LPO128K_CLK cycles will always get
passed and generate a RESET. The pulses in between 2 to 3 LPO128K_CLK cycles may
or may not generate reset based on reset alignment with clock edge.
25.2.2.2 Low voltage detect (LVD)
The chip includes a system for managing low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a POR circuit and an LVD circuit. The LVD system is always enabled in
HSRUN and Normal Run. The LVD system is disabled when entering VLPx modes.
The LVD system can be configured to generate a reset upon detection of a low voltage
condition by writing 1 to PMC_LVDSC1[LVDRE] . After an LVD reset has occurred,
the LVD system holds the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The MCU writes 1 to RCM_SRS[LVD] bit is set following
either an LVD reset or POR.
Besides LVD operation, the device also supports LVR(Low Voltage Reset) operation. If
the supply voltage falls below the reset trip point (VLVR), a system reset will be
generated. LVR system is enabled in all modes. LVDRE has effect on LVD operation
only.
Chapter 25 Reset and Boot
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 509
Out of POR, both RCM_SRS[POR] and RCM_SRS[LVD] are configured as 1 by MCU.
While normal operation, if device supply goes below VPOR, MCU writes 1 to both
RCM_SRS[POR] and RCM_SRS[LVD]. While normal operation, if device supply goes
below VLVD (provided LVD is enabled to generate a reset) or VLVR but above VPOR,
MCU writes 1 to RCM_SRS[LVD].
25.2.2.3 Watchdog reset
Watchdog timer (WDOG) monitors the operation of the system by expecting periodic
communication from the software. This communication is generally known as servicing
or refreshing the watchdog. If this periodic refreshing does not occur, the watchdog
issues a system reset. The watchdog reset causes the MCU to write 1 to
RCM_SRS[WDOG] .
25.2.2.4 Loss-of-clock (LOC) reset
LOC reset is enabled when SOSC clock monitor is enabled (by writing 1 to SOSCCM)
and configured to generate a reset on error (by writing 1 to SOSCCMRE). If the error bit
(SOSCERR) is written to 1 and LOC reset is enabled (as mentioned above), the MCU
resets. The MCU writes 1 to the LOC field to indicate this reset source.
NOTE
To prevent unexpected loss of clock reset events, all clock
monitors should be disabled before entering any low power
modes, including VLPR.
25.2.2.5 Loss-of-lock (LOL) reset
LOL reset is enabled when PLL clock monitor is enabled (by writing 1 to
SCG_SPLLCSR[SPLLCM]) and configured to generate a reset on error (by writing 1 to
SCG_SPLLCSR[SPLLCMRE]). If the error bit (SCG_SPLLCSR[SPLLERR]) is written
to 1 and LOL reset is enabled (as mentioned above), the MCU resets. The MCU writes 1
to RCM_SRS[LOL] field is set to indicate this reset source.
NOTE
This reset source does not cause a reset if the chip is in any
Stop mode.
SPLL also flags LOL in case if the reference to SPLL goes faulty. So while using SPLL,
any failure in reference clock source, i.e., SOSC might lead to either LOC or LOL event.
Reset
S32K1xx Series Reference Manual, Rev. 7, 04/2018
510 NXP Semiconductors
25.2.2.6 Stop mode acknowledge error (SACKERR)
The Stop mode acknowledge error (SACKERR) reset is generated if the core attempts to
enter Stop mode, but not all modules acknowledge stop mode within (2^16 +1
(corresponding to 0.5s)) cycles of the LPO128K_CLK.
A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.
The RCM_SRS[SACKERR] bit is written to 1 to indicate this reset source.
25.2.2.7 Software reset (SW)
The SYSRESETREQ bit in the NVIC application interrupt and reset control register can
be written to 1 to force a software reset. (See Arm's NVIC documentation for the full
description of the register fields, especially the VECTKEY field requirements.) Writing 1
to SYSRESETREQ generates a software reset request. This reset forces a system reset of
all major components except for the debug module. A software reset causes the MCU to
write 1 to RCM_SRS[SW] field.
25.2.2.8 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes the MCU to write 1 to
RCM_SRS[LOCKUP] field.
25.2.2.9 MDM-AP system reset request
Writing 1 to the system reset request field in the MDM-AP control register initiates a
system reset. This is the primary method for resets via the JTAG/SWD interface. The
system reset is held until this field is written to 0.
Writing 1 to the core hold reset bit in the MDM-AP control register holds the core in
reset as the rest of the chip comes out of system reset.
Chapter 25 Reset and Boot
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 511
25.2.3 MCU Resets
A variety of resets are generated by the MCU to reset different modules.
25.2.3.1 POR Only
The POR Only reset asserts on the POR reset source only. It resets the PMC registers.
The POR Only reset also causes all other reset types to occur.
25.2.3.2 Chip POR
The Chip POR asserts on POR, LVR or LVD.
The Chip POR also causes the chip reset (including early chip reset) to occur.
25.2.3.3 Early chip reset
The early chip reset asserts on all reset sources. It resets only the flash memory module. It
deasserts before flash memory initialization begins (earlier than the chip reset
deassertion).
25.2.3.4 Chip reset
Chip reset asserts on all reset sources and only deasserts after flash memory initialization
has completed and the RESET_B pin has also negated.
25.2.3.5 Core reset
The core comes out of reset after one cycle of chip reset. The core can be held in reset
using the core hold reset bit in the MDM-AP control register as the rest of the chip comes
out of system reset.
25.2.4 Reset pin
For all reset sources, the RESET_B pin is driven low by the MCU for at least 128 bus
clock cycles and until flash memory initialization has completed.
Reset
S32K1xx Series Reference Manual, Rev. 7, 04/2018
512 NXP Semiconductors
After flash memory initialization has completed, the RESET_B pin is released and the
internal chip reset deasserts. Keeping the RESET_B pin asserted externally delays the
negation of the internal chip reset.
25.2.5 Debug resets
The following sections detail the debug resets.
25.2.5.1 JTAG reset
The JTAG module generate a system reset when certain IR codes are selected. This
functional reset is asserted when EXTEST, HIGHZ and CLAMP instructions are active.
The reset source from the JTAG module is released when any other IR code is selected.
A JTAG reset causes the MCU to write 1 to RCM_SRS[JTAG] field.
25.2.5.2 Resetting the debug subsystem
Use the CDBGRSTREQ field within the SWJ-DP CTRL/STAT register to reset the
debug modules. However the CDBGRSTREQ field does not reset all debug-related
registers.
CDBGRSTREQ resets only the debug-related registers within the following modules:
• SWJ-DP
• AHB-AP
• TPIU
• MDM-AP (MDM control and status registers)
CDBGRSTREQ does not reset the debug-related registers within these modules:
• CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• FPB
• DWT
• ITM
• NVIC
• Crossbar bus switch
• Private peripheral bus
Chapter 25 Reset and Boot
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 513
25.3 Boot
This section describes the boot sequence, including sources and options.
25.3.1 Boot sources
This MCU supports cold booting from internal flash memory.
When the MCU boots from internal flash memory, the reset vectors are located at address
0x0 (initial SP_main) and 0x4 (initial PC).
The MCU also supports boot from RAM by relocating the exception vector table to
RAM. This is implemented through a programmable Vector Table Offset Register
(VTOR) in NVIC module.
The MCU supports serial code download via
• CAN
• LIN
• SPI etc.
The application developer can write their own flash memory based boot loaders or adapt
the ones available at http://www.nxp.com. These boot loaders are then used to configure
and use the communication protocol to perform mass serial download. For instance, the
CAN module can be used to transfer data into its own message buffers, then the DMA
module can be used to move the data into the main system RAM. Once the download is
completed, the core can be used to transfer the new downloaded code into the flash
memory area.
25.3.2 FOPT boot options
The FOPT register in the Flash Memory module allows the user to customize the
operation of the MCU at boot time. The register contains read-only bits that are loaded
from the NVM's option byte in the flash memory configuration field. The default setting
for all values in the FTFC_FOPT register is logic 1 since it is copied from the option byte
residing in flash memory, which has all bits as logic 1 in the flash memory erased state.
To configure for alternate settings, program the appropriate bits in the NVM option byte.
The new settings take effect on subsequent POR and any system reset. For more details
on programming the option byte, see the flash memory chapter.
Boot
S32K1xx Series Reference Manual, Rev. 7, 04/2018
514 NXP Semiconductors
The MCU uses FOPT to configure the MCU at reset as shown in this table.
Table 25-2. FTFC_FOPT definition
Bit
numb
er
Field Value Definition
7-6 Reserved Reserved for future expansion
5 Reserved Reserved
4 Reserved Reserved for future expansion
3 RESET_PIN_CFG Enables/disables control for the RESET pin.
0 RESET_B pin is disabled following a POR and cannot be enabled as reset
function. When this option is selected, there could be a short period of contention
during a POR ramp where the MCU drives the pin low prior to establishing the
setting of this option and releasing the reset function on the pin.
This bit is preserved through system resets and low-power modes. When
RESET_B pin function is disabled, it cannot be used as a source for low-power
mode wake-up.
1 The port is configured with pullup enabled, passive filter enabled.
2 NMI_PIN_CFG Enables/disables control for the NMI function.
0 NMI interrupts are always blocked. The associated pin continues to default to
NMI_b pin controls with internal pullup enabled. When NMI_b pin function is
disabled, it cannot be used as a source for low-power mode wake-up.
If the NMI function is not required, either for an interrupt or wake up source, it is
recommended that the NMI function be disabled by writing 0 to NMI_PIN_CFG.
1 NMI_b pin/interrupts reset default to enabled.
1 Reserved Reserved for future expansion.
0 LPBOOT Controls the reset value of clock divider of IRC 48 Mhz to feed the Core and platform
clocks. Larger divide value selections produce lower average power consumption during
POR and reset sequencing and after reset exit.
0 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
1 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
25.3.3 Boot sequence
At power up, the on-chip regulator holds the system in a POR state until the input supply
is above the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The mode controller reset logic then controls this sequence to exit reset:
1. A system reset is held on internal logic, the RESET_B pin is driven out low, and the
SCG is enabled in its default clocking mode.
2. Required clocks are enabled (core clock, system clock, flash clock, and any bus
clocks that do not have clock gate control reset to disabled).
Chapter 25 Reset and Boot
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 515
3. The system reset on internal logic continues to be held, but the flash controller is
released from reset and begins initialization operation while the reset control logic
continues to drive the RESET_B pin low.
4. Early in reset sequencing, the NVM option byte is read and stored to the flash
memory module's FOPT register. If the LPBOOT is programmed for an alternate
clock divider reset value, the system/core clock is switched to a slower clock speed.
5. When flash memory initialization completes, the RESET_B pin is released. If
RESET_B continues to be asserted (an indication of a slow rise time on the
RESET_B pin or external drive in low), the system continues to be held in reset.
Once the RESET_B pin is detected high, the core clock is enabled and the system is
released from reset.
6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is written to
0xFFFF_FFFF.
7. If FlexNVM is enabled, the flash memory controller continues to restore the
FlexNVM data. This data is not available immediately out of reset and the system
should not access this data until the flash controller completes this initialization step
as indicated by the EEERDY flag.
Subsequent system resets follow this same reset flow.
Boot
S32K1xx Series Reference Manual, Rev. 7, 04/2018
516 NXP Semiconductors
Chapter 26
Reset Control Module (RCM)
26.1 Chip-specific RCM information
High voltage detect reset is not supported on this device. The SACKERR timing is 0.5 s.
On this device, LVD (Low voltage detect) and LVR (Low voltage reset) events trigger
LVD reset and hence Chip POR. Chip POR is triggered by POR, LVR or LVD events.
The PMC_LVDSC1[LVDRE] is used to gate LVD only, and has no effect on LVR
generation. With PMC_SC1[LVDRE] disabled, LVRs can still generate reset to system.
See Low Voltage Detect (LVD) System.
Wait mode is not supported on this device. See Module operation in available low power
modes for details on available power modes.
LPO128K_CLK is used as low power clock for reset pin filter.
26.1.1 RCM register information
RCM_PARAM_ECMU_LOC, RCM_SRS_CMU_LOC, RCM_SSRS_SCMU_LOC, and
RCM_SRIE_CMU_LOC details CMU reset source and are available in S32K11x
variants only.
26.2 Reset pin filter operation in STOP1/2 modes
The reset pins filtering in STOP1/2 mode is as follows:
• STOP1: Both RUN mode and STOP mode filters can operate. The filter with lower
pulse duration dominates.
• STOP2: RUN mode filter operates.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 517
26.3 Introduction
Information found here describes the registers of the Reset Control Module (RCM). The
RCM implements many of the reset functions for the chip. See the chip's reset chapter for
more information.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on
using the RCM.
26.4 Reset memory map and register descriptions
The RCM Memory Map/Register Definition can be found here.
The Reset Control Module (RCM) registers provide reset status information and reset
filter control.
NOTE
The RCM registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
RCM memory map
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
0 Version ID Register (RCM_VERID) 32 R 0300_0003h 26.4.1/518
4 Parameter Register (RCM_PARAM) 32 R See section 26.4.2/520
8 System Reset Status Register (RCM_SRS) 32 R 0000_0082h 26.4.3/522
C Reset Pin Control register (RCM_RPC) 32 R/W 0000_0000h 26.4.4/525
18 Sticky System Reset Status Register (RCM_SSRS) 32 R/W 0000_0082h 26.4.5/527
1C System Reset Interrupt Enable Register (RCM_SRIE) 32 R/W 0000_0000h 26.4.6/529
26.4.1 Version ID Register (RCM_VERID)
Address: 0h base + 0h offset = 0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMAJOR MINOR FEATURE
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
518 NXP Semiconductors
RCM_VERID field descriptions
Field Description
31–24
MAJOR
Major Version Number
This read only field returns the major version number for the specification.
23–16
MINOR
Minor Version Number
This read only field returns the minor version number for the specification.
FEATURE Feature Specification Number
This read only field returns the feature set number.
0x0003 Standard feature set.
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 519
26.4.2 Parameter Register (RCM_PARAM)
Address: 0h base + 4h offset = 4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
ECORE1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ETAMPER
0
ESACKERR
0
EMDM_AP
ESW
ELOCKUP
EJTAG
EPOR
EPIN
EWDOG
ECMU_LOC
ELOL
ELOC
ELVD
EWAKEUP
W
Reset 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0
RCM_PARAM field descriptions
Field Description
31–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
ECORE1
Existence of SRS[CORE1] status indication feature
Table continues on the next page...
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
520 NXP Semiconductors
RCM_PARAM field descriptions (continued)
Field Description
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
15
ETAMPER
Existence of SRS[TAMPER] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
ESACKERR
Existence of SRS[SACKERR] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
EMDM_AP
Existence of SRS[MDM_AP] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
10
ESW
Existence of SRS[SW] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
9
ELOCKUP
Existence of SRS[LOCKUP] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
8
EJTAG
Existence of SRS[JTAG] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
7
EPOR
Existence of SRS[POR] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
Table continues on the next page...
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 521
RCM_PARAM field descriptions (continued)
Field Description
6
EPIN
Existence of SRS[PIN] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
5
EWDOG
Existence of SRS[WDOG] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
4
ECMU_LOC
Existence of SRS[CMU_LOC] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
3
ELOL
Existence of SRS[LOL] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
2
ELOC
Existence of SRS[LOC] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
1
ELVD
Existence of SRS[LVD] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
0
EWAKEUP
Existence of SRS[WAKEUP] status indication feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
26.4.3 System Reset Status Register (RCM_SRS)
This register includes read-only status flags to indicate the source of the most recent
reset. Note that multiple flags can be set if multiple reset events occur at the same time.
The reset state of these bits depends on what caused the MCU to reset.
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
522 NXP Semiconductors
NOTE
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x82
• LVD (without POR) — 0x02
• Other reset — a bit is set if its corresponding reset source
caused the reset
Address: 0h base + 8h offset = 8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
SACKERR
0
MDM_AP
SW
LOCKUP
JTAG
POR
PIN
WDOG
CMU_LOC
LOL
LOC
LVD
0
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0
RCM_SRS field descriptions
Field Description
31–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 523
RCM_SRS field descriptions (continued)
Field Description
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
SACKERR
Stop Acknowledge Error
Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more
peripherals to acknowledge within approximately one second to enter stop mode.
0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
MDM_AP
MDM-AP System Reset Request
Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit
in the MDM-AP Control Register.
0 Reset was not caused by host debugger system setting of the System Reset Request bit
1 Reset was caused by host debugger system setting of the System Reset Request bit
10
SW
Software
Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and
Reset Control Register in the Arm core.
0 Reset not caused by software setting of SYSRESETREQ bit
1 Reset caused by software setting of SYSRESETREQ bit
9
LOCKUP
Core Lockup
Indicates a reset has been caused by the Arm core indication of a LOCKUP event.
0 Reset not caused by core LOCKUP event
1 Reset caused by core LOCKUP event
8
JTAG
JTAG generated reset
Indicates a reset has been caused by the JTAG selection of certain IR codes: EXTEST, HIGHZ, and
CLAMP.
0 Reset not caused by JTAG
1 Reset caused by JTAG
7
POR
Power-On Reset
Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset
occurred while the internal supply was below the LVD threshold.
0 Reset not caused by POR
1 Reset caused by POR
6
PIN
External Reset Pin
Indicates a reset has been caused by an active-low level on the external RESET (RESET_b) pin.
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
Table continues on the next page...
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
524 NXP Semiconductors
RCM_SRS field descriptions (continued)
Field Description
5
WDOG
Watchdog
Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by
disabling the watchdog.
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
4
CMU_LOC
CMU Loss-of-Clock Reset
Indicates a reset has been caused by the CMU loss-of-clock circuit. CMU_FC_GCR[FCE] must be set to
enable the frequency check circuit. See the CMU chapter for details.
0 Reset not caused by the CMU loss-of-clock circuit.
1 Reset caused by the CMU loss-of-clock circuit.
3
LOL
Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the SCG PLL/FLL.
0 Reset not caused by a loss of lock in the PLL/FLL
1 Reset caused by a loss of lock in the PLL/FLL
2
LOC
Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The SCG SOSC clock monitor must be
enabled for a loss of clock to be detected. Refer to the detailed SCG description for information on
enabling the clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
LVD
Low-Voltage Detect Reset or High-Voltage Detect Reset
If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs. If
PMC_HVDSC1[HVDRE] is set and the supply rises above the HVD trip voltage, an HVD reset occurs.
This field is also set by POR.
0 Reset not caused by LVD trip, HVD trip or POR
1 Reset caused by LVD trip, HVD trip or POR
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26.4.4 Reset Pin Control register (RCM_RPC)
NOTE
This register is reset on Chip POR only, it is unaffected by
other reset types.
NOTE
The bus clock filter is reset when disabled or when entering
stop mode. The LPO filter is reset when disabled.
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 525
Address: 0h base + Ch offset = Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
RSTFLTSEL
0
RSTFLTSS
RSTFLTSR
W
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCM_RPC field descriptions
Field Description
31–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12–8
RSTFLTSEL
Reset Pin Filter Bus Clock Select
Selects the reset pin bus clock filter width:
• Transition lengths less than RSTFLTSEL cycles are filtered.
• Transition lengths between RSTFLTSEL and (RSTFLTSEL+1) cycles (inclusive) may be filtered.
• Transition lengths greater than (RSTFLTSEL+1) cycles are not filtered.
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
RSTFLTSS
Reset Pin Filter Select in Stop Mode
Selects how the reset pin filter is enabled in any stop mode.
0 All filtering disabled
1 LPO clock filter enabled
RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes
Selects how the reset pin filter is enabled in run and wait modes.
00 All filtering disabled
01 Bus clock filter enabled for normal operation
10 LPO clock filter enabled for normal operation
11 Reserved
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
526 NXP Semiconductors
26.4.5 Sticky System Reset Status Register (RCM_SSRS)
This register includes status flags to indicate all reset sources since the last POR or LVD
that have not been cleared by software. Software can clear the status flags by writing a
logic one to a flag.
Address: 0h base + 18h offset = 18h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
SSACKERR
0
SMDM_AP
SSW
SLOCKUP
SJTAG
SPOR
SPIN
SWDOG
SCMU_LOC
SLOL
SLOC
SLVD
0
Ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0
RCM_SSRS field descriptions
Field Description
31–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
SSACKERR
Sticky Stop Acknowledge Error
Table continues on the next page...
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 527
RCM_SSRS field descriptions (continued)
Field Description
Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more
peripherals to acknowledge within approximately one second to enter stop mode.
0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
SMDM_AP
Sticky MDM-AP System Reset Request
Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit
in the MDM-AP Control Register.
0 Reset was not caused by host debugger system setting of the System Reset Request bit
1 Reset was caused by host debugger system setting of the System Reset Request bit
10
SSW
Sticky Software
Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and
Reset Control Register in the Arm core.
0 Reset not caused by software setting of SYSRESETREQ bit
1 Reset caused by software setting of SYSRESETREQ bit
9
SLOCKUP
Sticky Core Lockup
Indicates a reset has been caused by the Arm core indication of a LOCKUP event.
0 Reset not caused by core LOCKUP event
1 Reset caused by core LOCKUP event
8
SJTAG
Sticky JTAG generated reset
Indicates a reset has been caused by the JTAG selection of certain IR codes: EXTEST, HIGHZ, and
CLAMP.
0 Reset not caused by JTAG
1 Reset caused by JTAG
7
SPOR
Sticky Power-On Reset
Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset
occurred while the internal supply was below the LVD threshold.
0 Reset not caused by POR
1 Reset caused by POR
6
SPIN
Sticky External Reset Pin
Indicates a reset has been caused by an active-low level on the external RESET (RESET_b) pin.
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
5
SWDOG
Sticky Watchdog
Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by
disabling the watchdog.
Table continues on the next page...
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
528 NXP Semiconductors
RCM_SSRS field descriptions (continued)
Field Description
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
4
SCMU_LOC
Sticky CMU Loss-of-Clock Reset
Indicates a reset has been caused by the CMU loss-of-clock circuit. CMU_FC_GCR[FCE] must be set to
enable the frequency check circuit. See the CMU chapter for details.
0 Reset not caused by the CMU loss-of-clock circuit.
1 Reset caused by the CMU loss-of-clock circuit.
3
SLOL
Sticky Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the SCG PLL/FLL. See the SCG description for
information on the loss-of-lock event.
0 Reset not caused by a loss of lock in the PLL/FLL
1 Reset caused by a loss of lock in the PLL/FLL
2
SLOC
Sticky Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The SCG SOSC clock monitor must be
enabled for a loss of clock to be detected. Refer to the detailed SCG description for information on
enabling the clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
SLVD
Sticky Low-Voltage Detect Reset
If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs.
This field is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26.4.6 System Reset Interrupt Enable Register (RCM_SRIE)
This register provides the option to delay the assertion of a system reset for a period of
time (DELAY field) while an interrupt is generated. When an interrupt for a reset source
is enabled, software has time to perform a graceful shutdown. A Chip POR source cannot
be delayed by this feature. The SRS updates only after the system reset occurs.
NOTE
The reset delay feature requires the LPO clock to remain active.
NOTE
This register is reset on Chip POR only, it is unaffected by
other reset types.
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 529
Address: 0h base + 1Ch offset = 1Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
SACKERR
0
MDM_AP
SW
LOCKUP
JTAG GIE PIN
WDOG
CMU_LOC
LOL LOC DELAY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCM_SRIE field descriptions
Field Description
31–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
SACKERR
Stop Acknowledge Error Interrupt
0 Interrupt disabled.
1 Interrupt enabled.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
MDM_AP
MDM-AP System Reset Request
0 Interrupt disabled.
1 Interrupt enabled.
10
SW
Software Interrupt
0 Interrupt disabled.
1 Interrupt enabled.
9
LOCKUP
Core Lockup Interrupt
NOTE: The LOCKUP bit is useful only in devices with more than one core processor.
0 Interrupt disabled.
1 Interrupt enabled.
8
JTAG
JTAG generated reset
0 Interrupt disabled.
1 Interrupt enabled.
Table continues on the next page...
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
530 NXP Semiconductors
RCM_SRIE field descriptions (continued)
Field Description
7
GIE
Global Interrupt Enable
0 All interrupt sources disabled.
1 All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to
generate interrupts.
6
PIN
External Reset Pin Interrupt
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
5
WDOG
Watchdog Interrupt
0 Interrupt disabled.
1 Interrupt enabled.
4
CMU_LOC
CMU Loss-of-Clock Interrupt
0 Interrupt disabled.
1 Interrupt enabled.
3
LOL
Loss-of-Lock Interrupt
0 Interrupt disabled.
1 Interrupt enabled.
2
LOC
Loss-of-Clock Interrupt
0 Interrupt disabled.
1 Interrupt enabled.
DELAY Reset Delay Time
Configures the maximum reset delay time from when the interrupt is asserted and the system reset
occurs.
00 10 LPO cycles
01 34 LPO cycles
10 130 LPO cycles
11 514 LPO cycles
Chapter 26 Reset Control Module (RCM)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 531
Reset memory map and register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
532 NXP Semiconductors
Chapter 27
Clock Distribution
27.1 Introduction
This chapter presents the clock architecture overview of this device, clock distribution,
module clocks, and clock terminology. The System Clock Generator (SCG) module is
used to generate most of the clocks used by the device. The SCG module controls which
clock source (internal references, external crystals, external clocks) is used to derive
system clocks. The SCG also divides the selected clock source into a variety of clock
domains, including clocks for system bus masters, system bus slaves, and flash memory.
The clock generation circuitry provides several clock dividers and selectors allowing
different modules to be clocked at a frequency specific for that module. Clock generation
logic also implements module specific clock gating allowing modules to be individually
disabled. Thus, allowing optimization for performance or low power.
Various modules have specific clocks that can be generated from FIRC_CLK,
SIRC_CLK, SOSC_CLK, SPLL_CLK, or Power Management Controller (PMC) clock
signal (LPO128K_CLK). In addition, modules specific clocks that can be configured
from alternate sources. Clock selection for most modules is controlled by the PCC
module.
27.2 High level clocking diagram
The following diagram shows the high-level clocking architecture and various clock
sources for this device.
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 533
Fast
IRC
Slow
IRC
DIV1
DIV2
DIV1
DIV2
OSC
SOSC
System PLL3
SPLLDIV1_CLK
SPLLDIV2_CLK
FIRCDIV1_CLK
FIRCDIV2_CLK
SCG
EXTAL
XTAL
PMC
LPO
128Khz
RTC
RTC
CLKOUT
÷ 2
PREDIV Analog
SCG_CLKOUTCNFG[CLKOUTSEL]
Asynchronous
Peripheral
Sources
SCG_SOSCCFG[EREFS]
LPO128K_CLK
SIM_LPOCLKS[RTCCLKSEL]
SPLL_CLK
FIRC_CLK
SIRC_CLK
SOSC_CLK
SIM_LPOCLKS[LPOCLKSEL]
SIM_CHIPCTL[CLKOUTDIV]
SIM_CHIPCTL[CLKOUTSEL]
SIRCDIV1_CLK
SIRCDIV2_CLK
SOSCDIV1_CLK
SOSCDIV2_CLK
÷ 4
DIV
FLASH_CLK
BUS_CLK
CORE_CLK
SYS_CLK
LPO_CLK
LPO32K_CLK
LPO128K_CLK
LPO32K_CLK
00
01
10
11
1000
0110
0100
0010
0000
0111
1100
1001
1010
1110
0101
1011
1101
1111
00
01
10
11
RTC_CLKIN
0000
0110
0001
0010
0011
SCG_SLOW_CLK
0110
0011
0010
0001
LPO1K_CLK
RTC_CLK
VCO_CLK
SCG_SPLLDIV[SPLLDIV1]
SCG_SPLLDIV[SPLLDIV2]
DIV1
DIV2
SCG_FIRCDIV[FIRCDIV1]
SCG_FIRCDIV[FIRCDIV2]
DIV1
DIV2
SCG_SIRCDIV[SIRCDIV1]
SCG_SIRCDIV[SIRCDIV2]
SCG_CLKOUT
SCG_SOSCDIV[SOSCDIV1]
SCG_SOSCDIV[SOSCDIV2]
SCG_xCCR[DIVSLOW]
DIVSLOW
SCG_xCCR[DIVBUS]
DIVBUS
SCG_xCCR[DIVCORE]
DIVCORE
SPLL_CLK
System OSC
Clock Monitor
(Loss of clock)
System PLL
clock monitor
(Loss of lock)
(SOSC is monitored,
SIRC is module clock)
0
1
÷ 32
RTC_CLKOUT
1 kHz Clock
RTC_CLK
SCG_xCCR[SCS]
(where x = R, V, or H)
PREDIV_SYS_CLK
HCLK1
BUS_CLK1
QSPI_Module clock2
QSPI_2xSFIF_CLK2
QSPI_SFIF_CLK2
QSPI_SFIF_CLK_HYP_PREMUX2
1. The source of HCLK (to Arm® Cortex® modules) is CORE_CLK. See section 'Clock definitions' for CORE_CLK and BUS_CLK
2. QSPI clocks are applicable for S32K148 only and Reserved for others. See QuadSPI clicking diagram in table 'Peripheral module clocking'
3. For S32K11x, inputs and muxes connected to PCC are Reserved. Also SPLLDIVx_CLK are Reserved as indicated in RED
CMU4
(FIRC is monitored,
SIRC is reference clock)
4. Available only in S32K11x as indicated in BLUE
Figure 27-1. Clocking diagram
27.3 Clock definitions
The following table describes clocks shown in Figure 27-1 and other sections of this
document.
Clock definitions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
534 NXP Semiconductors
Table 27-1. Clock descriptions
Clock name Related clock selector Related clock divider Description
PREDIV_SYS_C
LK 1SCG_xCCR[SCS] — Clocks the QSPI memory in HSRUN
80 mode.
CORE_CLK2SCG_xCCR[SCS] SCG_xCCR[DIVCORE]
(÷ 1...16) Clocks the Arm core, divided by
DIVCORE bits inside SCG.
SYS_CLK2SCG_xCCR[SCS] SCG_xCCR[DIVCORE]
(÷ 1...16) Clocks the Crossbar, NVIC, Flash
controller, FTM, PDB, and so on.
BUS_CLK SCG_xCCR[SCS] SCG_xCCR[DIVBUS]
(÷ 1...16) Clocks the chip peripherals.
FLASH_CLK 3
(SCG_SLOW_CL
K in SCG)
SCG_xCCR[SCS] SCG_xCCR[DIVSLOW]
(÷ 1...8) Clocks the flash module.
SPLL_CLK 4— — Output of PLL (VCO_CLK ÷ 2)
SIRC_CLK — — Output clock of Slow IRC.
FIRC_CLK — — Output clock of Fast IRC.
SOSC_CLK SCG_SOSCCFG[EREFS] — System oscillator clock. Can be either
the EXTAL pin or output of oscillator
(SOSC).
NOTE: ERCLK/OSCERCLK stands
for the same clock source, in
some module chapters.
RTC_CLKOUT — — RTC oscillator output driving external
pin.
LPO32K_CLK SIM_LPOCLKS[CLK32SEL] A fixed divide by 4 of LPO_CLK
drives 01b input of RTC_CLK
multiplexer.
Source clock for RTC.
LPO128K_CLK — — Always on low power oscillator clock
generated by PMC.
SCG_CLKOUT SCG_CLKOUTCNFG[CLKOUT
SEL]
— SCG output clock that can be driven by
SOSC_CLK, SIRC_CLK, FIRC_CLK,
SPLL_CLK4, or SCG_SLOW_CLK
(FLASH_CLK).
LPO_CLK SIM_LPOCLKS[LPOCLKSEL] — Clock output generated from one of
three LPO clocks sources
(LPO128K_CLK, LPO32K_CLK,
LPO1K_CLK).
CLKOUT SIM_CHIPCTL[CLKOUTSEL] SIM_CHIPCTL[CLKOUTDIV]
(÷ 1...8) Selected from one of eight internal
clock sources.
VCO_CLK 4— — VCO output clock within PLL. Its
frequency = SPLL_CLK × 2.
SPLLDIV1_CLK 4—SCG_SPLLDIV[SPLLDIV1]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SPLL_CLK
This should be configured to 80MHz or
less in RUN mode and to 112 MHz or
less in HSRUN mode.
SPLLDIV2_CLK
4
—SCG_SPLLDIV[SPLLDIV2]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SPLL_CLK
This should be configured to 40 MHz
or less in RUN mode and 56 MHz or
less in HSRUN mode.
Table continues on the next page...
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 535
Table 27-1. Clock descriptions (continued)
Clock name Related clock selector Related clock divider Description
FIRCDIV1_CLK — SCG_FIRCDIV[FIRCDIV1]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided FIRC_CLK
This should be configured to 48 MHz
or less in RUN/HSRUN mode.
FIRCDIV2_CLK — SCG_FIRCDIV[FIRCDIV2]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided FIRC_CLK
This should be configured to 48 MHz
or less in RUN/HSRUN mode.
SIRCDIV1_CLK — SCG_SIRCDIV[SIRCDIV1]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SIRC_CLK
This should be configured to 8 MHz or
less in RUN/HSRUN mode and to 4
MHz or less in VLPR/VLPS mode.
SIRCDIV2_CLK — SCG_SIRCDIV[SIRCDIV2](÷
1, 2, 4, 8, 16, 32, 64, or
output disabled
)
Divided SIRC_CLK
This should be configured to 8 MHz or
less in RUN/HSRUN mode and to 4
MHz or less in VLPR/VLPS mode.
SOSCDIV1_CLK — SCG_SPLLDIV[SOSCDIV1]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SOSC_CLK
This should be configured to 40 MHz
or less in RUN/HSRUN mode.
SOSCDIV2_CLK — SCG_SPLLDIV[SOSCDIV2]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SOSC_CLK
This should be configured to 40 MHz
or less in RUN/HSRUN mode.
1. Only available in S32K148
2. SYS_CLK/CORE_CLK must not be configured to less than BUS_CLK.
3. For FLASH_CLK operating range during parallel boot see Device Boot modes
4. Only available in S32K14x series
27.4 Internal clocking requirements
The clock dividers are programmed via the SCG module’s clock divider registers. The
following requirements must be met when configuring the clocks for this chip:
• CORE_CLK and SYS_CLK clock frequency must be 112 MHz or less in HSRUN
mode and 80 MHz in normal RUN mode (but not configured to be less than
BUS_CLK).
• BUS_CLK frequency must be programmed to 56 MHz or less in HSRUN, 48 MHz
or less in RUN(when using PLL as system clock source maximum bus clock
frequency is 40 MHz. See Option 1 and 3 below ), and an integer divide of the
CORE_CLK.
• FLASH_CLK frequency must be programmed to 28 MHz or less in HSRUN, 26.67
MHz or less in RUN, and an integer divide of the CORE_CLK. The core clock to
flash clock ratio is limited to a max value of 8.
Internal clocking requirements
S32K1xx Series Reference Manual, Rev. 7, 04/2018
536 NXP Semiconductors
The following are a few of the common clock configurations for this chip in the four
clocking modes:
Option 1: Slow RUN (typically using the undivided FIRC)1, using the following
Memory Map/Register Definition register settings:
• SCG_RCCR[SCS] = 0011b
• SCG_RCCR[DIVCORE] = 0000b
• SCG_RCCR[DIVBUS] = 0000b
• SCG_RCCR[DIVSLOW] = 0001b
Table 27-2. Slow RUN example
Clock Frequency
CORE_CLK 48 MHz
SYS_CLK 48 MHz
BUS_CLK 48 MHz (max freq. in RUN mode)
FLASH_CLK 24 MHz
Option 2: Normal RUN (with VCO_CLK = 320 MHz, SPLL_CLK = 160 MHz), using
the following Memory Map/Register Definition register settings:
• SCG_RCCR[SCS] = 0110b
• SCG_RCCR[DIVCORE] = 0001b
• SCG_RCCR[DIVBUS] = 0001b
• SCG_RCCR[DIVSLOW] = 0010b
Table 27-3. Normal RUN example
Clock Frequency
CORE_CLK 80 MHz
SYS_CLK 80 MHz
BUS_CLK 40 MHz
FLASH_CLK 26.67 MHz (max freq. in RUN
mode)
Option 3: Normal RUN (with VCO_CLK = 256 MHz, SPLL_CLK = 128 MHz), using
the following Memory Map/Register Definition register settings:
• SCG_RCCR[SCS] = 0110b
• SCG_RCCR[DIVCORE] = 0001b
• SCG_RCCR[DIVBUS] = 0001b
• SCG_RCCR[DIVSLOW] = 0010b
1. Default configuration after reset. FIRC_CLK = 48 MHz.
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 537
Table 27-4. Normal RUN example
Clock Frequency
CORE_CLK 64 MHz
SYS_CLK 64 MHz
BUS_CLK 32 MHz
FLASH_CLK 21.33 MHz
Option 4: High Speed RUN (with VCO_CLK = 224 MHz, SPLL_CLK = 112 MHz),
using the following Memory Map/Register Definition register settings:
• SCG_HCCR[SCS] = 0110b
• SCG_HCCR[DIVCORE] = 0000b
• SCG_HCCR[DIVBUS] = 0001b
• SCG_HCCR[DIVSLOW] = 0011b
Table 27-5. High Speed RUN example
Clock Frequency
CORE_CLK 112 MHz
SYS_CLK 112 MHz
BUS_CLK 56 MHz
FLASH_CLK 28 MHz
NOTE
All frequencies listed in table above are maximum for HSRUN
mode.
Option 5: High Speed RUN 80 (with VCO_CLK = 320 MHz, SPLL_CLK = 160 MHz),
using the following Memory Map/Register Definition register settings:
• SCG_HCCR[SCS] = 0110b
• SCG_HCCR[DIVCORE] = 0001b
• SCG_HCCR[DIVBUS] = 0001b
• SCG_HCCR[DIVSLOW] = 0010b
Table 27-6. High Speed RUN 80 example (mode used by QuadSPI only)
Clock Frequency
CORE_CLK 80 MHz
SYS_CLK 80 MHz
BUS_CLK 40 MHz
FLASH_CLK 26.67 MHz (maximum frequency
in RUN mode)
Internal clocking requirements
S32K1xx Series Reference Manual, Rev. 7, 04/2018
538 NXP Semiconductors
Option 6: Very Low Power RUN, VLPR (with SIRC_CLK = 8 MHz), using the
following Memory Map/Register Definition register settings:
• SCG_VCCR[SCS] = 0010b (SIRC_CLK)
• SCG_VCCR[DIVCORE] = 0001b
• SCG_VCCR[DIVBUS] = 0000b
• SCG_VCCR[DIVSLOW] = 0011b
Table 27-7. Very low power RUN example
Clock Frequency
CORE_CLK 4 MHz
SYS_CLK 4 MHz
BUS_CLK 4 MHz
FLASH_CLK 1 MHz
Following table summarizes the S32K14x/S32K11x maximum frequencies and example
configurations for each internal clock
Clock HSRUN RUN VLPR Notes
S32K14x only S32K14x S32K11x
CORE_CLK
SYS_CLK
112MHz 80MHz 48MHz 4MHz Must be configured to be more than or
equal to BUS_CLK.
BUS_CLK 56MHz 48MHz
(40MHz when
using PLL as
system clock
source)
48MHz 4MHz Must be integer divide of the
CORE_CLK.
FLASH_CLK 28MHz 26.67MHz 24MHz 1MHz Must be integer divide of the
CORE_CLK. The core clock to flash
clock ratio is limited to a max value of
8.
NOTE
All frequencies listed in table above are maximum for VLPR
mode.
NOTE
All asynchronous clock sources will also be restricted to 4 MHz
in VLPR/VLPS mode as configured in SCG_SIRCDIV.
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 539
27.4.1 Clock divider values after reset
The default configuration out of reset has the CPU clocked by the Fast IRC
(FIRC_CLK). The clocks (for example, CORE_CLK, FLASH_CLK, and BUS_CLK) are
configured in the SCG module (see Memory Map/Register Definition).
27.4.2 HSRUN mode clocking
Clock dividers should not be modified while the chip is operating in HSRUN mode. They
must be configured prior to entering HSRUN mode to guarantee:
• CORE_CLK/SYS_CLK is less than or equal to 112MHz
• BUS_CLK is less than or equal to 56 MHz
• FLASH_CLK is less than or equal to 28 MHz
27.4.3 VLPR mode clocking
Clock dividers should not be modified while the chip is operating in VLPR mode. They
must be configured prior to entering VLPR mode to guarantee:
• CORE_CLK/SYS_CLK and BUS_CLK are less than or equal to 4 MHz
• FLASH_CLK is less than or equal to 1 MHz
NOTE
All asynchronous clock sources will also be restricted to 4 MHz
in VLPR/VLPS mode as configured in SCG_SIRCDIV.
27.4.4 VLPR/VLPS mode entry
When entering VLPR/VLPS mode, the system clock should be SIRC. The FIRC, SOSC,
and SPLL must be disabled by software in RUN mode before making any mode
transition. Ensure that CMU is gated by its PCC.CGC before entering STOP/VLPS/CPO
mode.
Internal clocking requirements
S32K1xx Series Reference Manual, Rev. 7, 04/2018
540 NXP Semiconductors
27.5 Clock Gating
The clock to each module can be individually gated on and off using the PCC module.
After any reset, PCC disables the clock to the corresponding module to conserve power.
Prior to initializing a module, set the corresponding clock gating control bits in PCC
register to enable the clock. Before turning off the clock, make sure to disable the
module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
27.6 Module clocks
The following table summarizes the clocks that can be used by each of the modules.
Table 27-8. Peripheral clock summary
Module name Bus interface
clock 1
Bus interface
clock1 gating
Peripheral
functional clock
Additonal clocks Comments and
maximum frequencies
Gated by
[CGC] of
PCC
Clocks controlled
by [PCS] of PCC
Communications
LPUART BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
—Maximum frequency
governed by BUS_CLK
LPSPI BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
—Maximum frequency
governed by BUS_CLK
LPI2C BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
—Maximum frequency
governed by BUS_CLK
FlexIO 3BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
—Maximum frequency
governed by BUS_CLK
FlexCAN SYS_CLK Yes — SYS_CLK,
SOSCDIV2_CLK
Support 40 MHz from
OSC; SYS_CLK must be
> 1.5x the protocol clock;
while synchronous
operation (when protocol
clock is selected to
SYS_CLK) can be done at
1:1 clock frequency.4
Table continues on the next page...
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 541
Table 27-8. Peripheral clock summary (continued)
Module name Bus interface
clock 1
Bus interface
clock1 gating
Peripheral
functional clock
Additonal clocks Comments and
maximum frequencies
Gated by
[CGC] of
PCC
Clocks controlled
by [PCS] of PCC
Timers
LPTMR BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
RTC_CLK2,
SIRCDIV2_CLK,
LPO1K_CLK
Maximum frequency
governed by BUS_CLK
LPIT BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
—Maximum frequency
governed by BUS_CLK
RTC BUS_CLK Yes — RTC_CLK2,
LPO1K_CLK Maximum frequency
governed by BUS_CLK
PDB SYS_CLK Yes — — Maximum frequency
governed by SYS_CLK
FlexTimer SYS_CLK Yes
SPLLDIV1_CLK,
FIRCDIV1_CLK,
SIRCDIV1_CLK,
SOSCDIV1_CLK
RTC_CLK2,
SYS_CLK,
TCLKx
Maximum frequency
governed by SYS_CLK
System Modules
WDOG BUS_CLK No —
LPO_CLK 5,
SOSC_CLK,
SIRC_CLK
Maximum frequency
governed by BUS_CLK
EWM BUS_CLK Yes — LPO_CLK5Maximum frequency
governed by BUS_CLK
PMC BUS_CLK No — — Maximum frequency
governed by BUS_CLK
SIM BUS_CLK No — — Maximum frequency
governed by BUS_CLK
RCM BUS_CLK No — LPO128K_CLK Maximum frequency
governed by BUS_CLK
CRC BUS_CLK Yes — — Maximum frequency
governed by BUS_CLK
PORT BUS_CLK Yes — LPO128K_CLK Maximum frequency
governed by BUS_CLK
GPIO SYS_CLK No — — Maximum frequency
governed by SYS_CLK
TRGMUX BUS_CLK No — — Maximum frequency
governed by BUS_CLK
DMAMUX BUS_CLK Yes — — Maximum frequency
governed by BUS_CLK
DMA SYS_CLK No — — Maximum frequency
governed by SYS_CLK
MPU SYS_CLK No — — Maximum frequency
governed by SYS_CLK
Table continues on the next page...
Module clocks
S32K1xx Series Reference Manual, Rev. 7, 04/2018
542 NXP Semiconductors
Table 27-8. Peripheral clock summary (continued)
Module name Bus interface
clock 1
Bus interface
clock1 gating
Peripheral
functional clock
Additonal clocks Comments and
maximum frequencies
Gated by
[CGC] of
PCC
Clocks controlled
by [PCS] of PCC
EIM SYS_CLK No — — Maximum frequency
governed by SYS_CLK
ERM SYS_CLK No — — Maximum frequency
governed by SYS_CLK
MSCM SYS_CLK No — — Maximum frequency
governed by SYS_CLK
CMU BUS_CLK Yes — FIRC_CLK
SIRC_CLK —
Memory Modules
FTFC6FLASH_CLK Yes — — Maximum frequency
governed by FLASH_CLK
System RAM SYS_CLK No — — Maximum frequency
governed by SYS_CLK
Analog Modules
ADC BUS_CLK Yes
SPLLDIV2_CLK,
FIRCDIV2_CLK,
SIRCDIV2_CLK,
SOSCDIV2_CLK
—
50 MHz7
CMP BUS_CLK Yes — — Maximum frequency
governed by BUS_CLK
QuadSPI BUS_CLK/
SYS_CLK Yes SPLLDIV1_CLK
FIRCDIV1_CLK — —
SAI BUS_CLK Yes — MCLK (from PAD)
BCLK (from PAD) —
ENET8SYS_CLK Yes
SPLLDIV1_CLK
SIRCDIV1_CLK
FIRCDIV1_CLK
SOSCDIV1_CLK
ENET_MII_RMII_TX_
CLK (from PAD)
MAC timestamp clock
period must be integer
nano-seconds.
1. Refers to module's interface clock and should not be misinterpreted as BUS_CLK
2. RTC_CLK is the output from the multiplexer that uses SIM_LPOCLKS[RTCCLKSEL] for source selection (See Figure 1 for
details).
3. FlexIO peripheral clock should not be more than twice of FlexIO bus interface clock. For fast access to FlexIO register
(FLEXIO_CTRL[FASTACC]=1), FlexIO peripheral clock can be twice of FlexIO Bus interface clock.
4. In S32K11x variants, 'SYS_CLK > 1.5x the protocol clock' requirement is not applicable but the software needs to maintain
following relationship:
• CAN bit time > (3 x CANCLK) + (3 x SYS_CLK)
5. LPO_CLK is the output from the multiplexer that uses SIM_LPOCLKS[LPOCLKSEL] for source selection (See Figure 1 for
details).
6. Do not change the clock control settings to the flash memory whilst simultaneously accessing the flash memory. Instead, it
is recommended to execute from SRAM when a change in frequency is needed.
7. The maximum conversion clock frequency is 50 MHz. At any time, the conversion clock frequency should be less than the
ADC bus interface clock frequency. See the device datasheet for ADC specifications.
8. Refer to External signal description for clocking restrictions.
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 543
NOTE
The above clock selections are controlled in the PCC module
(column 4 of Table 27-8).
NOTE
• SIRC and LPO_CLK are the valid clock sources for VLP*
modes.
• SPLL and FIRC are the valid clock sources for HSRUN
mode.
The following table summarizes the clocks that can be used by each of the modules.
Table 27-9. Peripheral module clocking
Modules PCC multiplexer
LPSPI
LPIT
FlexIO
LPI2C
LPUART
PCC module
SOSCDIV2_CLK
SIRCDIV2_CLK
SPLLDIV2_CLK
FIRCDIV2_CLK
PCC_<module>[PCS]
000
001
010
011
100
101
110
111
Reserved
Reserved
Reserved
to module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
BUS_CLK
to module
PDB
PCC module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
SYS_CLK
to module
DMAMUX
CMP0
CRC
PCC module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
BUS_CLK
to module
Table continues on the next page...
Module clocks
S32K1xx Series Reference Manual, Rev. 7, 04/2018
544 NXP Semiconductors
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
GPIO
GPIO bus interface clock
GPIO
SYS_CLK
PORT
PORT[x]
bus clock
PORT_DFCR[CS]
0
1
lpo clock Filter
PCC module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
BUS_CLK
LPO128K_CLK
bus clock
FlexCAN
SYS_CLK
FlexCANn module
0
1
Clock gate enable
PCC_FLEXCANn[CGC]
(where 1 = clock enabled)
PCC module
Module Clock
SOSCDIV2_CLK
SYS_CLK
CAN_CTRL1[CLKSRC]
CHI Clock
PE Clock
Table continues on the next page...
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 545
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
EIM
ERM
MSCM
DMA
MPU
SYS_CLK
to module
Clock gate enable
SIM_PLATCGC[CGC<module>]
(where 1b = clock enabled)
SIM module
EWM
BUS_CLK
EWM module
Clock gate enable
PCC_EWM[CGC]
(where 1 = clock enabled)
PCC module
SIM_LPOCLKS[LPOCLKSEL]
LPO_CLK
LPO128K_CLK
LPO32K_CLK
00
01
10
11
LPO1K_CLK
Low power clock
Peripheral bus clock
WDOG
SOSC_CLK
SIRC_CLK
WDOG module
BUS_CLK
LPO_CLK
WDOG_CS[CLK]
00
01
10
11
WDOG clock
bus_clk
bus_clk
internal LPO clk
internal clk
external clk
SIM_LPOCLKS[LPOCLKSEL]
LPO128K_CLK
LPO32K_CLK
00
01
10
11
LPO1K_CLK
Table continues on the next page...
Module clocks
S32K1xx Series Reference Manual, Rev. 7, 04/2018
546 NXP Semiconductors
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
SIM
PMC
TRGMUX
bus interface clock
SIM/PMC/TRGMUX
BUS_CLK
RCM
RCM
bus clock
RCM_RPC[RSTFLTSRW]
00
01
10
11
lpo clock Filter
BUS_CLK
LPO128K_CLK
Reserved
System RAM
memory clock
System RAM
SYS_CLK
FTFC
FLASH_CLK
FTFC
Clock gate enable
PCC_FTFC[CGC]
(where 1 = clock enabled)
PCC module
Table continues on the next page...
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 547
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
ADC
PCC_ADCnADCn
BUS_CLK Module Clock
Clock
Divide
00
01
10
11
ALTCLK1
ALTCLK2
ALTCLK3
ALTCLK4
Clock gate enable
PCC_ADCn[CGC]
(where 1 = clock enabled)
see PCC chapter
for details
SOSCDIV2_CLK
SIRCDIV2_CLK
SPLLDIV2_CLK
FIRCDIV2_CLK
PCC_ADCn[PCS]
000
001
010
011
100
101
110
111
Reserved
Reserved
Reserved
ADC_CFG1[ADICLK]
ADCK
ADC_CFG1[ADIV]
Bus interface clk
The ADC has multiple clock sources. Selection is determined by the configuration of
PCC_ADCx[PCS]. The dividers should be configured such that the ADC conversion clock
frequency lies within the valid range as per the ADC requirement (see the Data Sheet).
FTM
Clock gate enable
PCC module FTMn module
SYS_CLK
FTMn_SC[CLKS]
see PCC chapter
for details
Counter
00
01
10
11
RTC_CLK
PCC_FLEXTMRn[CGC]
(where 1 = clock enabled)
SIM_FTMOPT0[FTMnCLKSEL]
SOSCDIV1_CLK
SIRCDIV1_CLK
SPLLDIV1_CLK
FIRCDIV1_CLK
000
001
010
011
100
101
110
111
Reserved
Reserved
Reserved
PCC_FLEXTMRn[PCS]
00
01
10
11
TCLK0
TCLK1
TCLK2
External clock
Fixed frequency clock
FTM_CLK
FTM System clock
FTM System clock
The FTM module is clocked by the internal SYS_CLK (the FTM module refers to it as system
clock) which could be up to CPU frequency, but the FTM counter allows to be clocked by three
clock sources:
• System clock (SYS_CLK) from PCC
• Internal fixed frequency clock
• External clocks from pins (TCLK[2:0])
The counter clock source selection is controlled by CLKS bits in FTMn_SC register. The
FTM_CLK is controlled by PCC module and could run up to CPU frequency and provide higher
resolution for the FTM timer.
The fixed frequency clock is a fixed clock driven by RTC_CLK. SIM_LPOCLKS[RTCCLKSEL] is
used to select the RTC_CLK source.
Table continues on the next page...
Module clocks
S32K1xx Series Reference Manual, Rev. 7, 04/2018
548 NXP Semiconductors
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
There are three clocks that can be accessed externally to the chip (TCLK0, TCLK1, TCLK2). One
of these clocks are selected to drive the 000b input of the multiplexer in the PCC
(PCC_FLEXTMRn[PCS] = 000b) by configuring SIM_FTMOPT0[FTMnCLKSEL].
The fixed frequency clock and external clocks provide the user more clock options for FTM
counter.
RTC
1 kHz clock
RTC
LPO1K_CLK
RTC_CLK
RTC_CLKOUT
RTC_CLK
RTC_CLKOUT pin
LPTMR
PCC module LPTMR0 module
BUS_CLK
LPTMR0_PSR[PCS]
Module Clock
see PCC chapter
for details
00
01
10
11
SOSCDIV2_CLK
SIRCDIV2_CLK
SPLLDIV2_CLK
FIRCDIV2_CLK
PCC_LPTMR0[PCS]
000
001
010
011
100
101
110
111
Reserved
Reserved
Reserved
SIRCDIV2_CLK
RTC_CLK
LPO1K_CLK
LPTMR0_CSR[TPS]
Prescaler
00
01
10
11
TRGMUX_LPTMR0
LPTMR_ALT1
LPTMR_ALT2
LPTMR_ALT3
LPTMR0_PSR[PRESCALE]
LPTMR_PSR[PBYP]
0
1
Pulse
Counter
Divider
PCC_LPTMR0[PCD]
Prescaler/glitch filter clock0
Prescaler/glitch filter clock1
Prescaler/glitch filter clock2
Prescaler/glitch filter clock3
Pulse counter input0
Pulse counter input1
Pulse counter input2
Pulse counter input3
(see 'Clocking diagram' for details)
Clock gate enable
PCC_LPTMR0[CGC]
(where 1 = clock enabled)
The prescaler and glitch filter of the LPTMR0 module can be clocked from misc sources
determined by the PCC_LPTMR[PCS] control bitfield and LPTMR0_PSR[PCS] bitfield. The
LPTMR_PSR[PCS] bitfield is used for internal LPTMR to select the clock source. The supported
clock sources on this device are shown in following figure.
NOTE: The clock selected must remain enabled if the LPTMR is to continue operating in all
required low power modes.
TPIU
Core clk
Platform clk
SIM_CHIPCTL[12]
Divider
SIM_CLKDIV4[3:0]
TPIU Trace clk
SWO
0
1
SAI
Table continues on the next page...
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 549
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
SAIx_BCLK
PCC_SAIx
Module_clock SAIx
11
10
01
00
MCLK_SAI
SOSCDIV1
SAIx_MCLK
BUS_CLK
PCC
Clock gate enable
SAI_RCR2[MSEL]/
SAI_TCR2[MSEL]
SAIy_MCLK
The BCLK can either be externally provided through BCLK pin or can be internally generated in
internal bit clock mode using SAI internal divider by configuring SAIn_RCR2[MSEL]/
SAIn_TCR2[MSEL] and SAIn_RCR2[DIV]/SAIn_TCR2[DIV].
NOTE: BCLK should never be greater than the Bus interface clock as it will lead to underrun or
overflow of FIFO inside SAI.
Table 27-10. Clocking option
SAI instance MCLK source Description
SAI0 SAIx_MCLK SAI0 MCLK
SAI0 SAIy_MCLK SAI1 MCLK
SAI1 SAIx_MCLK SAI1 MCLK
SAI1 SAIy_MCLK SAI0 MCLK
QuadSPI
Table continues on the next page...
Module clocks
S32K1xx Series Reference Manual, Rev. 7, 04/2018
550 NXP Semiconductors
Table 27-9. Peripheral module clocking (continued)
Modules PCC multiplexer
QuadSPI_MCR[SCLKCFG][0]
SCKB
loopback
clock
A
DQS_B
0
1
0
10
RWDS
QuadSPI_MCR[SCLKCFG][5]
Delay
chain
QuadSPI_SOCCR[SOCCFG][15:8]
1
QuadSPI_MCR[SCLKCFG][2]
QuadSPI_MCR[SCLKCFG][3]
SCKA
loopback
clock
A
0
1
0
1Delay
chain
QuadSPI_SOCCR[SOCCFG][7:0]
DQS_A
Bus interface clock
Module clock
AHB read interface clock
1
0
QuadSPI_MCR[SCLKCFG][6]
1
0
BUS_CLK
SYS_CLK
Clock gate enable
BUS_CLK
SYS_CLK
QuadSPI_MCR[SCLKCFG][1]
QuadSPI
SCKA (PAD)
SCKB (PAD)
A
2xSFIF_CLK
2xSFIF_B_CLK
1
0
QuadSPI_MCR[SCLKCFG][5]
SFCK
Div by 2
0
1
SFIF_CLK
SFIF_B_CLK
0
1
QuadSPI_MCR[SCLKCFG][6] QuadSPI_AHB_Buffer
QuadSPI
Memory
128x7
(1 KB)
PREDIV_SYS_CLK
SYS_CLK
0
1
QuadSPI_MCR[SCLKCFG][4]
SPLLDIV1
FIRCDIV1
Clock gate enable1Programmable
Divider2
Clock gate enable
PCC_QSPI[CGC]
(where 1 = clock enabled)
PCC_QSPI[CGC]
(where 1 = clock enabled)
Clock gate enable
PCC_QSPI[CGC]
(where 1 = clock enabled)
SIM_MISCTRL0[QSPI_CLK_SEL]
(where 1 = clock enabled)
QuadSPI_SOCCR[SOCCFG]
QSPI_SFIF_CLK_HYP_PREMUX
NOTE: 1. Clock gate enable: SIM_MISCTRL0[QSPI_CLK_SEL]
2. For programmable divider configuration, see QuadSPI_SOCCR[SOCCFG]
implementation
ENET
Clock gate enable
PCC module ENET module
SYS_CLK
see PCC chapter
for details
PCC_ENET[CGC]
(where 1 = clock enabled)
SOSCDIV1_CLK
SIRCDIV1_CLK
SPLLDIV1_CLK
FIRCDIV1_CLK
000
001
010
011
100
101
110
111
Reserved
Reserved
Reserved
PCC_ENET[PCS]
SYS_CLK
X
ENET_1588_CLKIN Timers
DMA
Tx_clk (PAD)
Rx_clk (PAD)
RMII CLK
MII Tx CLK
MII Rx CLK
1
SOSCDIV1_CLK
SIM_MISCTRL0[25]
MAC
RMII CLK
MII Tx CLK
MII Rx CLK
MAC
Clock gate enable
NOTE: SIM_MISCTRL0 bit 24 and 25 are used to control which clock (external or internally
generated) is used by MAC in RMII mode only.
CMU
Chapter 27 Clock Distribution
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 551
Table 27-9. Peripheral module clocking
Modules PCC multiplexer
CMUx
MON_CLK
PCC module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
FIRC_CLK
SIRC_CLK
PCC module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
REF_CLK
PCC module
Clock gate enable
PCC_<module>[CGC]
(where 1b = clock enabled)
BUS_CLK Module clock
NOTE
While changing peripheral clock source/divider configuration,
the corresponding module should be disabled.
Module clocks
S32K1xx Series Reference Manual, Rev. 7, 04/2018
552 NXP Semiconductors
Chapter 28
System Clock Generator (SCG)
28.1 Chip-specific SCG information
Wait mode is not supported on this device. See Module operation in available low power
modes for details on available power modes.
NOTE
• SPLL and HSRUN mode is not available in S32K11x
series of devices.
• SCG_SIRCCSR[SIRCLPEN] bit field is applicable for
VLPS mode only.
• SCG_SIRCCSR[SIRCSTEN] bit field is not applicable and
should be ignored.
• For S32K11x variants, writing to SCG_HCCR will give
transfer error.
28.1.1 Supported frequency ranges
This section describes the supported frequency ranges.
1. SCG_SOSCCFG[RANGE]
• 00 Reserved
• 01 Reserved
• 10 Medium frequency range selected for the crystal oscillator of 4 MHz to 8
MHz.
• 11 High frequency range selected for the crystal oscillator of 8 MHz to 40 MHz.
2. SCG_FIRCCFG[RANGE]
• 00 Fast IRC is trimmed to 48 MHz
• 01 Reserved
• 10 Reserved
• 11 Reserved
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 553
NOTE
Software should not configure the
SCG_FIRCCFG[RANGE] to any value other than 00.
3. SCG_SIRCCFG[RANGE]
• 0 Reserved
• 1 Slow IRC high range clock (8 MHz )
28.1.2 Oscillator and SPLL guidelines
If PLL is used, then oscillator needs to be in high range only, SCG_SOSCCFG[RANGE]
on 11 as used in reference clock.
If the current system clock is SOSC, then following should be taken care by software:
• Configure all reset sources as 'Interrupt' (not as 'Reset') via RCM_SRIE
• The SOSC should be disabled via SCG_SOSCCSR[SOSCEN]
• After disabling SOSC, configure the reset source back to reset via RCM_SRIE
• When SPLL is enabled, both LOC and LOL must be configured as reset only
(SOSCCSR[SOSCCMRE] and SPLLCSR[SPLLCMRE] must be 1 and
RCM_SRIE[LOC], RCM_SRIE[LOL] must be 0). The only exception is during
standard clock switching, in which case the ‘clock switching sequence’ protocol must
be followed.
See note in section IO Signal Table
28.1.3 System clock switching
For any clock switching of system clock, follow the below steps:
• Before doing a clock switch, configure all reset sources to be ‘Reset' (not as
Interrupt) via RCM_SRIE.
• Program each reset source as Interrupt via RCM_SRIE for a minimum delay time of
10 LPO.
• Execute the clock switch
• Wait/Poll for the clock switch to complete
• Configure every reset source back to original intended reset configuration (Interrupt
or Reset) via RCM_SRIE
NOTE
LOC flag would be raised when SOSC pulses are not detected
for 8 to 16 clock cycles of SIRC/256. Hence, the LOC
Chip-specific SCG information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
554 NXP Semiconductors
indication through reset to the system from the time when
oscillator is cut off will vary from 256 μs to 512 μs.
28.1.4 System clock and clock monitor requirement
1. System clock source XOSC/SPLL requirement: Ensure below sequence is
followed while switching system clock to XOSC/SPLL:
a. System clock source (XOSC/SPLL) is enabled
b. Clock monitors and their corresponding reset events are enabled for XOSC/
SPLL
c. XOSC/SPLL is selected as system clock source
2. XOSC/SPLL clock monitor disable sequence requirement: Ensure below
sequence for disabling clock monitors while switching system clock source from
XOSC/SPLL:
a. System clock source switched from XOSC/SPLL
b. Disable clock monitors and their corresponding reset events for XOSC/SPLL
It is imperative to follow the above guidelines to safeguard the device operation
against loss of clock scenarios if system clock source malfunction due to any reason.
28.2 Introduction
The system clock generator (SCG) module provides the system clocks of the MCU. The
SCG contains a system phase-locked loop (SPLL), a slow internal reference clock
(SIRC), a fast internal reference clock (FIRC), and the system oscillator clock (SOSC).
The SPLL is sourced by the SOSC reference clock. The SCG can select either the output
clock of the SPLL or a SCG reference clock (SIRC, FIRC, and SOSC) as the source for
the MCU system clocks. The SCG also supports operation with crystal oscillators, which
allows an external crystal, ceramic resonator, or another external clock source to produce
the external reference clock (which are also available as clock sources for the MCU
systems clocks).
28.2.1 Features
Key features of the SCG module are:
• System Phase-locked loop (SPLL):
• Voltage-controlled oscillator (VCO)
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 555
• External reference clock is used as the PLL source
• Modulo VCO frequency divider
• Phase/Frequency detector
• Integrated loop filter
• Can be selected as the clock source for the MCU system clocks
• 2 programmable post-dividers clock outputs, which can be used as clock sources
for other on-chip peripherals
• 2 Internal reference clock (IRC) generators:
• Fast IRC clock with programmable High and Low frequency range
• Either the slow or the fast clock can be selected as the clock source for the MCU
system clocks
• 2 programmable post-divider clock outputs for each IRC, which can be used as
clock sources for other on-chip peripherals
• System Crystal Oscillator:
• Used as the source for the System PLL
• Can be selected as the clock source for the MCU system clocks
• Clock monitor with reset and interrupt request capability for SPLL, SOSC, clocks
• Lock detector with interrupt request capability for use with the SPLL
• Each of the clock sources have reference dividers for clocking on-chip modules and
peripherals, namely:
• SPLLDIV1_CLK / SPLLDIV2_CLK
• FIRCDIV1_CLK / SCG_FIRCDIV2_CLK
• SIRCDIV1_CLK / SIRCDIV2_CLK
• SOSCDIV1_CLK / SOSCDIV2_CLK
See the Clock Distribution Chapter for more information.
28.3 Memory Map/Register Definition
This section includes the memory map and register definition.
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
556 NXP Semiconductors
The SCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus transfer error. Read accesses may be performed in both
supervisor and user mode.
NOTE
For any writeable SCG registers, only 32-bit writes are allowed.
8-bit or 16-bit writes will result in transfer errors.
SCG memory map
Address
offset (hex) Register name Width
(in bits) Access Reset value Section/
page
0 Version ID Register (SCG_VERID) 32 R 0100_0000h 28.3.1/558
4 Parameter Register (SCG_PARAM) 32 R See section 28.3.2/558
10 Clock Status Register (SCG_CSR) 32 R See section 28.3.3/559
14 Run Clock Control Register (SCG_RCCR) 32 R/W See section 28.3.4/561
18 VLPR Clock Control Register (SCG_VCCR) 32 R/W See section 28.3.5/564
1C HSRUN Clock Control Register (SCG_HCCR) 32 R/W See section 28.3.6/566
20 SCG CLKOUT Configuration Register
(SCG_CLKOUTCNFG) 32 R/W 0300_0000h 28.3.7/568
100 System OSC Control Status Register (SCG_SOSCCSR) 32 R/W See section 28.3.8/569
104 System OSC Divide Register (SCG_SOSCDIV) 32 R/W 0000_0000h 28.3.9/571
108 System Oscillator Configuration Register (SCG_SOSCCFG) 32 R/W 0000_0010h 28.3.10/
572
200 Slow IRC Control Status Register (SCG_SIRCCSR) 32 R/W 0100_0005h 28.3.11/
574
204 Slow IRC Divide Register (SCG_SIRCDIV) 32 R/W 0000_0000h 28.3.12/
575
208 Slow IRC Configuration Register (SCG_SIRCCFG) 32 R/W 0000_0001h 28.3.13/
576
300 Fast IRC Control Status Register (SCG_FIRCCSR) 32 R/W See section 28.3.14/
577
304 Fast IRC Divide Register (SCG_FIRCDIV) 32 R/W 0000_0000h 28.3.15/
579
308 Fast IRC Configuration Register (SCG_FIRCCFG) 32 R/W 0000_0000h 28.3.16/
580
600 System PLL Control Status Register (SCG_SPLLCSR) 32 R/W 0000_0000h 28.3.17/
581
604 System PLL Divide Register (SCG_SPLLDIV) 32 R/W 0000_0000h 28.3.18/
583
608 System PLL Configuration Register (SCG_SPLLCFG) 32 R/W 0000_0000h 28.3.19/
584
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 557
28.3.1 Version ID Register (SCG_VERID)
Note: Writing to this register will result in a transfer error.
Address: 0h base + 0h offset = 0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVERSION
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_VERID field descriptions
Field Description
VERSION SCG Version Number
28.3.2 Parameter Register (SCG_PARAM)
Note: Writing to this register will result in a transfer error.
Address: 0h base + 4h offset = 4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDIVPRES 0 0 CLKPRES
W
Reset * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * *
* Notes:
DIVPRES field: The reset value is controlled by which SCG System Dividers are used by Soc.•
CLKPRES field: The reset value is controlled by which SCG Clock Sources are used by Soc. Please reference the
Reference manual clocking chapter.
•
SCG_PARAM field descriptions
Field Description
31–27
DIVPRES
Divider Present
Indicates which system clock dividers are present in this instance of SCG.
DIVPRES[27]=1 System DIVSLOW is present.
DIVPRES[28]=1 System DIVBUS is present
DIVPRES[31]=1 System DIVCORE is present
26–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
558 NXP Semiconductors
SCG_PARAM field descriptions (continued)
Field Description
CLKPRES Clock Present
Indicates which clock sources are present in this instance of SCG. Any bits not defined in this bit field are
Reserved and always has the value 0 when read.
CLKPRES[0] Reserved
CLKPRES[1]=1System OSC (SOSC) is present
CLKPRES[2]=1Slow IRC (SIRC) is present
CLKPRES[3]=1Fast IRC (FIRC) is present
CLKPRES[6]=1System PLL (SPLL) is present
28.3.3 Clock Status Register (SCG_CSR)
This register returns the currently configured system clock source and the system clock
dividers for the core (DIVCORE) and peripheral interface clock (DIVSLOW). The
SCG_CSR reflects the configuration set by one of three clock control registers
SCG_RCCR, SCG_VCCR, SCG_HCCR.
Note: Writing to this register will result in a transfer error.
Address: 0h base + 10h offset = 10h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 SCS 0 DIVCORE 0 0 DIVBUS DIVSLOW
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The valid reset values are
div-by-1 or div-by-2 when resetting into RUN mode or div-by-4 or div-by-8 when resetting into VLPR mode.
•
SCG_CSR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
SCS
System Clock Source
Returns the currently configured clock source generating the system clock.
0000 Reserved
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Fast IRC (FIRC_CLK)
0100 Reserved
0101 Reserved
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 559
SCG_CSR field descriptions (continued)
Field Description
0110 System PLL (SPLL_CLK)
0111 Reserved
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
If SPLL is selected as system clock source, the maximum DIVCORE value is Divide-by-4.
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
DIVBUS
Bus Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
DIVSLOW Slow Clock Divide Ratio
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
560 NXP Semiconductors
SCG_CSR field descriptions (continued)
Field Description
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
28.3.4 Run Clock Control Register (SCG_RCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in Run mode only. This register can only
be written using a 32-bit write. Selecting a different clock source when in RUN requires
that clock source to be enabled first and be valid before system clocks switch to that
clock source. If system clock divide ratios also change when selecting a different clock
mode when in RUN, new system clock divide ratios will not take affect until new clock
source is valid.
Address: 0h base + 14h offset = 14h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SCS 0DIVCORE Reserved 0DIVBUS DIVSLOW
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The two valid reset values
are div-by-1 and div-by-2
•
SCG_RCCR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 561
SCG_RCCR field descriptions (continued)
Field Description
27–24
SCS
System Clock Source
Selects the clock source generating the system clock in Run mode. Attempting to select a clock that is not
valid will be ignored. Selecting a different clock source when in Run mode requires that clock source to be
enabled first and be valid before system clocks are allowed to switch to that clock source.
0000 Reserved
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Fast IRC (FIRC_CLK)
0100 Reserved
0101 Reserved
0110 System PLL (SPLL_CLK)
0111 Reserved
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved. Software should write 0 to these bits to maintain compatibility.
This field is reserved.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
DIVBUS
Bus Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
562 NXP Semiconductors
SCG_RCCR field descriptions (continued)
Field Description
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
DIVSLOW Slow Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 563
28.3.5 VLPR Clock Control Register (SCG_VCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in VLPR mode only. This register can
only be written using a 32-bit write. Selecting a different clock source when in VLPR
requires that clock source to be enabled first and be valid before system clocks switch to
that clock source. If system clock divide ratios also change when selecting a different
clock mode when in VLPR, new system clock divide ratios will not take affect until new
clock source is valid.
Address: 0h base + 18h offset = 18h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SCS 0DIVCORE Reserved 0DIVBUS DIVSLOW
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The two option reset values
are div-by-4 and div-by-8.
•
SCG_VCCR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
SCS
System Clock Source
Selects the clock source generating the system clock in VLPR mode. Attempting to select a clock that is
not valid will be ignored. Selects the clock source generating the system clock. Selecting a different clock
source when in VLPR mode requires that clock source to be enabled first and be valid before system
clocks switch to that clock source.
0000 Reserved
0001 Reserved
0010 Slow IRC (SIRC_CLK)
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
564 NXP Semiconductors
SCG_VCCR field descriptions (continued)
Field Description
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved. Software should write 0 to these bits to maintain compatibility.
This field is reserved.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
DIVBUS
Bus Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
DIVSLOW Slow Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Reserved
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 565
SCG_VCCR field descriptions (continued)
Field Description
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
28.3.6 HSRUN Clock Control Register (SCG_HCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in HSRUN mode only. This register can
only be written using a 32-bit write. Selecting a different clock source when in HSRUN
requires that clock source to be enabled first and be valid before system clocks switch to
that clock source. If system clock divide ratios also change when selecting a different
clock mode when in HSRUN, new system clock divide ratios will not take affect until
new clock source is valid.
Address: 0h base + 1Ch offset = 1Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SCS 0DIVCORE Reserved 0DIVBUS DIVSLOW
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SCG_HCCR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
SCS
System Clock Source
Selects the clock source generating the system clock in HSRUN mode. Attempting to select a clock that is
not valid will be ignored. Selecting a different clock source when in HSRUN mode will enable that clock
source and switch to that clock mode when it is valid.
0000 Reserved
0001 Reserved
0010 Reserved
0011 Fast IRC (FIRC_CLK)
0100 Reserved
0101 Reserved
0110 System PLL (SPLL_CLK)
0111 Reserved
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
566 NXP Semiconductors
SCG_HCCR field descriptions (continued)
Field Description
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved. Software should write 0 to these bits to maintain compatibility.
This field is reserved.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
DIVBUS
Bus Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
DIVSLOW Slow Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 567
SCG_HCCR field descriptions (continued)
Field Description
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
28.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG)
This register controls which SCG clock source is selected to be ported out to the
CLKOUT pin.
Address: 0h base + 20h offset = 20h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0CLKOUTSEL 0
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_CLKOUTCNFG field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
CLKOUTSEL
SCG Clkout Select
Selects the SCG system clock.
0000 SCG SLOW Clock
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Fast IRC (FIRC_CLK)
0100 Reserved
0101 Reserved
0110 System PLL (SPLL_CLK)
0111 Reserved
1111 Reserved
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
568 NXP Semiconductors
28.3.8 System OSC Control Status Register (SCG_SOSCCSR)
Address: 0h base + 100h offset = 100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
SOSCERR
SOSCSEL
SOSCVLD
LK
0
SOSCCMRE
SOSCCM
Ww1c
Reset 0 0 0 0 0 * 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
Reserved
Reserved
SOSCEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
SOSCERR field: This flag is reset on Chip POR only•
SCG_SOSCCSR field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
SOSCERR
System OSC Clock Error
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one.
0 System OSC Clock Monitor is disabled or has not detected an error
1 System OSC Clock Monitor is enabled and detected an error
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 569
SCG_SOSCCSR field descriptions (continued)
Field Description
25
SOSCSEL
System OSC Selected
0 System OSC is not the system clock source
1 System OSC is the system clock source
24
SOSCVLD
System OSC Valid
The SOSC is considered valid after 4096 xtal counts.
0 System OSC is not enabled or clock is not valid
1 System OSC is enabled and output clock is valid
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 This Control Status Register can be written.
1 This Control Status Register cannot be written.
22–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17
SOSCCMRE
System OSC Clock Monitor Reset Enable
0 Clock Monitor generates interrupt when error detected
1 Clock Monitor generates reset when error detected
16
SOSCCM
System OSC Clock Monitor
Enables the clock monitor when SOSCVLD is set. If the clock source is disabled in a low power mode then
the clock monitor is also disabled in the low power mode. When the clock monitor is disabled in a low
power mode, it remains disabled until the clock valid flag is set following exit from the low power mode.
0 System OSC Clock Monitor is disabled
1 System OSC Clock Monitor is enabled
15–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
Reserved
This field is reserved.
This field is reserved. Software should write 0 to these bits to maintain compatibility.
2–1
Reserved
This field is reserved.
This field is reserved. Software should write 0 to these bits to maintain compatibility.
0
SOSCEN
System OSC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 System OSC is disabled
1 System OSC is enabled
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
570 NXP Semiconductors
28.3.9 System OSC Divide Register (SCG_SOSCDIV)
The SCG_SOSCDIV register provides the control of 2 clock trees which can be used to
provide optional peripheral functional clocks, or alternative module clocks. Each clock
tree has optional dividers of the input SOSC clock. Changes to SOSCDIV should be done
when System OSC is disabled to prevent glitches to output divided clock.
Address: 0h base + 104h offset = 104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SOSCDIV2 0SOSCDIV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SOSCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
SOSCDIV2
System OSC Clock Divide 2
Clock divider 2 for System OSC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SOSCDIV1 System OSC Clock Divide 1
Clock divider 1 for System OSC. Used to generate the clock source for modules that need an
asynchronous clock source.
000 Output disabled
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 571
SCG_SOSCDIV field descriptions (continued)
Field Description
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
28.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)
The SOSCCFG register cannot be changed when the System OSC is enabled. When the
System OSC is enabled, writes to this register are ignored, and there is no transfer error.
Address: 0h base + 108h offset = 108h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
Reserved
0
RANGE HGO
EREFS
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
SCG_SOSCCFG field descriptions
Field Description
31–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
Reserved
This field is reserved.
This bit is reserved. Software should write 0 to this bit field.
7–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–4
RANGE
System OSC Range Select
Selects the frequency range for the system crystal oscillator (OSC)
See chip-specific information for supported crystal oscillator ranges.
00 Reserved
01 Low frequency range selected for the crystal oscillator
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
572 NXP Semiconductors
SCG_SOSCCFG field descriptions (continued)
Field Description
10 Medium frequency range selected for the crytstal oscillator
11 High frequency range selected for the crystal oscillator
3
HGO
High Gain Oscillator Select
Controls the crystal oscillator power mode of operations.
0 Configure crystal oscillator for low-gain operation
1 Configure crystal oscillator for high-gain operation
2
EREFS
External Reference Select
Selects the source for the external reference clock. This bit selects which clock is output from the System
OSC (SOSC) into the SCG, thus either the crystal oscillator or from an external clock input
0 External reference clock selected
1 Internal crystal oscillator of OSC selected.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 573
28.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)
Address: 0h base + 200h offset = 200h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
SIRCSEL
SIRCVLD
LK
Reserved
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RReserved 0
SIRCLPEN
SIRCSTEN
SIRCEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
SCG_SIRCCSR field descriptions
Field Description
31–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25
SIRCSEL
Slow IRC Selected
0 Slow IRC is not the system clock source
1 Slow IRC is the system clock source
24
SIRCVLD
Slow IRC Valid
0 Slow IRC is not enabled or clock is not valid
1 Slow IRC is enabled and output clock is valid
23
LK
Lock Register
This bit field can be cleared/set at any time.
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
574 NXP Semiconductors
SCG_SIRCCSR field descriptions (continued)
Field Description
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–4
Reserved
This field is reserved and is always has the value 0
This field is reserved.
3
Reserved
This field is reserved and is always has the value 0
This field is reserved.
This read-only field is reserved and always has the value 0.
2
SIRCLPEN
Slow IRC Low Power Enable
0 Slow IRC is disabled in VLP modes
1 Slow IRC is enabled in VLP modes
1
SIRCSTEN
Slow IRC Stop Enable
0 Slow IRC is disabled in supported Stop modes
1 Slow IRC is enabled in supported Stop modes
0
SIRCEN
Slow IRC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 Slow IRC is disabled
1 Slow IRC is enabled
28.3.12 Slow IRC Divide Register (SCG_SIRCDIV)
To prevent glitches to the output divided clock, change SIRDIV when the Slow IRC is
disabled.
Address: 0h base + 204h offset = 204h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0Reserved 0 SIRCDIV
2
0 SIRCDIV
1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SIRCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
SIRCDIV2
Slow IRC Clock Divide 2
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 575
SCG_SIRCDIV field descriptions (continued)
Field Description
Clock divider 2 for Slow IRC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SIRCDIV1 Slow IRC Clock Divide 1
Clock divider 1 for Slow IRC. Used to generate the clock source for modules that need an asynchronous
clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
28.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)
The SIRCCFG register cannot be changed when the slow IRC clock is enabled. When the
slow IRC clock is enabled, writes to this register are ignored, and there is no transfer
error.
Address: 0h base + 208h offset = 208h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
RANGE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
576 NXP Semiconductors
SCG_SIRCCFG field descriptions
Field Description
31–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
RANGE
Frequency Range
See chip-specific information for supported frequency ranges.
0 Slow IRC low range clock (2 MHz)
1 Slow IRC high range clock (8 MHz )
28.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)
Address: 0h base + 300h offset = 300h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
FIRCERR
FIRCSEL
FIRCVLD
LK
0
Ww1c
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
Reserved
0
FIRCREGOFF
Reserved
FIRCEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 577
SCG_FIRCCSR field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
FIRCERR
Fast IRC Clock Error
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one
0 Error not detected with the Fast IRC trimming.
1 Error detected with the Fast IRC trimming.
25
FIRCSEL
Fast IRC Selected status
0 Fast IRC is not the system clock source
1 Fast IRC is the system clock source
24
FIRCVLD
Fast IRC Valid status
0 Fast IRC is not enabled or clock is not valid.
1 Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the
FIRC analog.
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–8
Reserved
This field is reserved.
This field is reserved. Software should write 0 to these bits to maintain compatibility.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
FIRCREGOFF
Fast IRC Regulator Enable
0 Fast IRC Regulator is enabled.
1 Fast IRC Regulator is disabled.
2–1
Reserved
This field is reserved. Software should write 0 to these bits to maintain compatibility.
This field is reserved.
0
FIRCEN
Fast IRC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 Fast IRC is disabled
1 Fast IRC is enabled
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
578 NXP Semiconductors
28.3.15 Fast IRC Divide Register (SCG_FIRCDIV)
Changes to FIRCDIV should be done when FAST IRC is disabled to prevent glitches to
output divided clock.
Address: 0h base + 304h offset = 304h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0Reserved 0FIRCDIV2 0FIRCDIV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_FIRCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
FIRCDIV2
Fast IRC Clock Divide 2
Clock divider 2 for the Fast IRC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FIRCDIV1 Fast IRC Clock Divide 1
Clock divider 1 for Fast IRC. Used to generate the clock source for modules that need an asynchronous
clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 579
28.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)
The FIRCCFG register cannot be changed when the Fast IRC is enabled. When the Fast
IRC is enabled, writes to this register are ignored, and there is no transfer error.
Address: 0h base + 308h offset = 308h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0RANGE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_FIRCCFG field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
RANGE Frequency Range
See chip-specific information for supported frequency ranges.
00 Fast IRC is trimmed to 48 MHz
01 Fast IRC is trimmed to 52 MHz
10 Fast IRC is trimmed to 56 MHz
11 Fast IRC is trimmed to 60 MHz
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
580 NXP Semiconductors
28.3.17 System PLL Control Status Register (SCG_SPLLCSR)
Address: 0h base + 600h offset = 600h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
SPLLERR
SPLLSEL
SPLLVLD
LK
0
SPLLCMRE
SPLLCM
Ww1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
Reserved
SPLLEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SPLLCSR field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
SPLLERR
System PLL Clock Error
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one
NOTE: The LOL Flag is set when the PLL reference is out of range (Dunl in datasheet) and is constantly
modulated such that 3 consecutive un-locked samples of the reference clock are generated.
0 System PLL Clock Monitor is disabled or has not detected an error
1 System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set
when System OSC is selected as its source and SOSCERR has set.
25
SPLLSEL
System PLL Selected
0 System PLL is not the system clock source
1 System PLL is the system clock source
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 581
SCG_SPLLCSR field descriptions (continued)
Field Description
24
SPLLVLD
System PLL Valid
Indicates when the SPLL clock is valid. When the System PLL (SPLL) is disabled, the System PLL Valid
bit (SPLLVLD) will clear without causing the System PLL Clock Error bit (SPLLERR) to get set. In a similar
way, if the System PLL (SPLL) is using the System Oscillator (SOSC) as its reference clock, and a System
OSC Clock Error (SOSCCSR[SOSCERR]) is detected, then the System PLL Valid bit (SPLLVLD) will clear
without asserting a System PLL Clock Error (SPLLERR).
Lock detect is determined by a lock detect circuit. Three samples of lock detect determines whether or not
the clock is valid.
NOTE: The System PLL Valid bit (SPLLVLD) should only be used to verify that the SPLL is locked after
initialization. To monitor the SPLL clock, ensure that the System PLL Clock Monitor is enabled,
using the System PLL Clock Monitor bit (SPLLCM).
0 System PLL is not enabled or clock is not valid
1 System PLL is enabled and output clock is valid
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17
SPLLCMRE
System PLL Clock Monitor Reset Enable
0 Clock Monitor generates interrupt when error detected
1 Clock Monitor generates reset when error detected
16
SPLLCM
System PLL Clock Monitor
Enables the clock monitor, if the clock source is disabled in a low power mode then the clock monitor is
also disabled in the low power mode. When the clock monitor is disabled in a low power mode, it remains
disabled until the clock valid flag is set following exit from the low power mode.
0 System PLL Clock Monitor is disabled
1 System PLL Clock Monitor is enabled
15–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
Reserved
This field is reserved.
This field is reserved. Software should write 0 to this bit to maintain compatibility.
0
SPLLEN
System PLL Enable
NOTE: If this bit written during clock switching, it should be read back and confirmed before proceeding.
As the device exits reset, the SCG_RCCR register should be configured as per the supported
frequency ranges of the device BEFORE enabling the SPLL (SPLLEN =1).
0 System PLL is disabled
1 System PLL is enabled
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
582 NXP Semiconductors
28.3.18 System PLL Divide Register (SCG_SPLLDIV)
Changes to SPLLDIV should be done when System PLL is disabled to prevent glitches to
output divided clock.
Address: 0h base + 604h offset = 604h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SPLLDIV2 0SPLLDIV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SPLLDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
SPLLDIV2
System PLL Clock Divide 2
Clock divider 2 for System PLL. Used by modules that need an asynchronous clock source.
000 Clock disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SPLLDIV1 System PLL Clock Divide 1
Clock divider 1 for System PLL. Used to generate the clock source for modules that need an
asynchronous clock source.
000 Clock disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 583
SCG_SPLLDIV field descriptions (continued)
Field Description
101 Divide by 16
110 Divide by 32
111 Divide by 64
28.3.19 System PLL Configuration Register (SCG_SPLLCFG)
The SPLLCFG register cannot be changed when the System PLL is enabled. When the
System PLL is enabled, writes to this register are ignored, and there is no transfer error.
The below information applies to VCO_CLK.
The SPLL_CLK = (VCO_CLK)/2
The VCO_CLK = SPLL_SOURCE/(PREDIV + 1) X (MULT + 16)
SPLL_SOURCE is the clock source selected from the SOURCE bitfield of this register.
Address: 0h base + 608h offset = 608h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
MULT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
PREDIV
0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SPLLCFG field descriptions
Field Description
31–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20–16
MULT
System PLL Multiplier
Table continues on the next page...
Memory Map/Register Definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
584 NXP Semiconductors
SCG_SPLLCFG field descriptions (continued)
Field Description
Multiplier for the System PLL. The MULT bits establish the multiplication factor applied to the PLL
reference clock frequency.
Table 28-1. PLL VCO Multiply Factor
MULT Multiply
Factor
MULT Multiply
Factor
MULT Multiply
Factor
MULT Multiply
Factor
00000 16 01000 24 10000 32 11000 40
00001 17 01001 25 10001 33 11001 41
00010 18 01010 26 10010 34 11010 42
00011 19 01011 27 10011 35 11011 43
00100 20 01100 28 10100 36 11100 44
00101 21 01101 29 10101 37 11101 45
00110 22 01110 30 10110 38 11110 46
00111 23 01111 31 10111 39 11111 47
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
PREDIV
PLL Reference Clock Divider
Selects the amount to divide down the reference clock for the System PLL. The resulting frequency must
be in the range specified in the datasheet.
Table 28-2. System PLL Reference Divide Factor
PREDIV Divide Factor
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8
7–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
This field is reserved. Software should write 0 to this bit to maintain compatibility.
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 585
28.4 Functional description
28.4.1 SCG Clock Mode Transitions
The following figure shows the valid clock mode transitions supported by SCG.
Slow IRC (SIRC) boot mode is not supported on this device.
Reset
SIRC
RUN Valid
SCG Modes
HSRUN Valid
SCG Modes
FIRC
VLPRUN Valid
SCG Modes
SYS
PLL
SYS
PLL
SOSC
FIRC
SIRC
Run
Run
High Speed
Run
Very Low Power
SCG Valid Mode Transitions
Figure 28-1. SCG Valid Mode Transition Diagram
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
586 NXP Semiconductors
NOTE
When a transition between run modes (RUN, HSRUN,
VLRUN) is required, the SCG should complete the switch to
the clock mode as defined in the SCG clock control register
first. Once the switch to the clock mode is completed, the
system can then initiate the request for the selected run mode.
For example, if a transition from RUN mode to VLRUN is
required, first complete any required clock change. Initiate the
VLRUN request after the clock change has completed.
The power modes are chip specific. For more details about power mode assignments, see
power management and system mode control information.
The modes of operation listed in the following table are the valid modes for this
implementation of the SCG.
Table 28-3. SCG modes of operation
Mode Description
System Oscillator Clock
(SOSC)
System Oscillator Clock (SOSC) mode is entered when all the following conditions occur:
• RUN MODE: 0001 is written to RCCR[SCS].
• SOSCEN = 1
• SOSCVLD = 1
In SOSC mode, SCGCLKOUT and system clocks are derived from the external System Oscillator
Clock (SOSC).
Slow Internal Reference
Clock (SIRC)
Slow Internal Reference Clock (SIRC) mode is entered when all the following conditions occur:
• RUN MODE: 0010 is written to RCCR[SCS].
VLRUN MODE: 0010 is written to VCCR[SCS] and 1 is written to SIRCCSR[SIRCLPEN].
• SIRCEN = 1
• SIRCVLD = 1
In SIRC mode, SCGCLKOUT and system clocks are derived from the slow internal reference clock.
Two frequency ranges are available for SIRC clock as described in the SIRCCFG[RANGE] register
definition. Changes to SIRC range settings will be ignored when SIRC clock is enabled.
Information regarding SIRC operation during normal and low power stop modes is found in the
"Stop" row of this table.
Fast Internal Reference
Clock (FIRC)
Fast Internal Reference Clock (FIRC) mode is the default clock mode of operation and is entered
when all the following conditions occur:
• RUN MODE: 0011 is written to RCCR[SCS].
HSRUN MODE: 0011 is written to HCCR[SCS].
• FIRCEN = 1
• FIRCVLD = 1
Table continues on the next page...
Chapter 28 System Clock Generator (SCG)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 587
Table 28-3. SCG modes of operation (continued)
Mode Description
In FIRC mode, SCGCLKOUT and system clocks are derived from the fast internal reference clock.
Four frequency range settings are available for FIRC clock as described in the FIRC[RANGE]
register definition. Changes to FIRC range settings will be ignored when FIRC clock is enabled.
Sys PLL (SPLL) Sys PLL (SPLL) mode is entered when all the following conditions occur:
• RUN MODE: 0110 is written to RCCR[SCS].
HSRUN MODE: 0110 is written to HCCR[SCS].
• SPLLEN = 1
• SPLLVLD = 1
In SPLL mode, the SCGCLKOUT and system clocks are derived from the output of PLL which is
controlled by the System Oscillator (SOSC) clock. The selected PLL clock frequency locks to a
multiplication factor, as specified by its corresponding SCG_SPLLCFG[MULT], times the selected
PLL reference frequency. The PLL's programmable reference divider must be configured to produce
a valid PLL reference clock. This divide value is defined by the SCG_SPLLCFG[PREDIV] bits.
Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power
mode assignments, see the chapter that describes how modules are configured and SCG behaviour
during Stop recovery. Entering Stop mode, all SCG clock signals are static except the following
clocks which can continue to run and stay enabled in the following cases:
SIRCCLK is available in Normal Stop and VLPS mode when all the following conditions become
true:
• SIRCCSR[SIRCEN] = 1
• SIRCCSR[SIRCSTEN] = 1
• SIRCCSR[SIRCLPEN] = 1 in VLPS
Functional description
S32K1xx Series Reference Manual, Rev. 7, 04/2018
588 NXP Semiconductors
Chapter 29
Peripheral Clock Controller (PCC)
29.1 Chip-specific PCC information
For module specific clocking, see Module clocks.
NOTE
While changing a peripheral clock source, the corresponding
module should be disabled:
• Clock should be CGC gated
• Module should be disabled by MDIS bit, if available
After clock switching, the module should be soft reset using
soft reset bit (module software reset bit), if available.
SIM_SDID[FEATURES] bit field overrides the PCC.PR status for the chip.
29.1.1 PCC register information
The PCC Memory map shows a superset of registers implemented for the S32K1xx
series. Registers for instances unavailable in a particular variant are reserved.
S32K11x has two registers for CMU0 and CMU1 instances as described in the below
sections
29.1.1.1 PCC CMU0 Register (PCC_CMU0)
29.1.1.1.1 Offset
Register Offset
PCC_CMU0 F8h
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 589
29.1.1.1.2 Function
PCC Register
29.1.1.1.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.1.1.1.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0 This read-only bit field is reserved and always has the value 0.
Chip-specific PCC information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
590 NXP Semiconductors
Field Function
—
29.1.1.2 PCC CMU1 Register (PCC_CMU1)
29.1.1.2.1 Offset
Register Offset
PCC_CMU1 FCh
29.1.1.2.2 Function
PCC Register
29.1.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.1.1.2.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 591
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.2 Introduction
The Peripheral Clock Control (PCC) module provides clock control and configuration for
on-chip peripherals. Each peripheral has its own clock control and configuration register.
29.3 Features
The PCC module enables software to configure the following clocking options for each
peripheral:
• Interface clock gating
• Functional clock source selection
• Functional clock divide values
Below is a block diagram of the PCC module:
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
592 NXP Semiconductors
Interface clock control
Functional clock control (when available)
PCC
Clock option 1
Clock option 2
Clock option 6
Clock option 3
[PCS]
001
Clock option 4
Clock option 5
Clock option 7
to module
functional clock
Gate
[CGC]
Chip-specific clock
to module
interface clock
Divider
[FRAC, PCD]
OFF
External
clock
000
= Not all module functional clocks have a divider or an external clock option.
111
110
010
011
100
101
= Internal bus interface clock for module registers and logic
= Clock for module applications (Not all modules have functional clocks.)
Interface clock
Functional clock
Figure 29-1. PCC Block Diagram
29.4 Functional description
The PCC module provides on-chip peripherals (modules) their own dedicated PCC
registers for clock gating and configuration options. Each module's PCC register contains
a clock gating control bit (CGC) for the module's interface clock. Before a module can be
used, its interface clock must be enabled (CGC = 1) in the module's PCC register.
If a module has a functional clock, its PCC register may provide options for the clock
source, selected by programming the Peripheral Clock Select (PCS) field. Optionally, a
module may also have a clock divider, selected by programming the Peripheral Clock
Divider (PCD) field along with a Fraction (FRAC) field. Before configuring a functional
clock, the module's interface clock must be disabled (CGC = 0).
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 593
29.5 Memory map and register definition
Each module has its own dedicated PCC register, which controls the clock gating, clock
source and divider (when applicable) for that specific module. See each module's PCC
register for details.
PCC registers can be written only in supervisor mode using 32-bit accesses.
NOTE
To configure the clocking options available to a given module
or to modify an existing configuration, first disable the
module's interface clock by writing 0 to its CGC bit.
29.6 PCC register descriptions
29.6.1 PCC Memory map
PCC base address: 4006_5000h
Offset Register Width
(In bits)
Access Reset value
80h PCC FTFC Register (PCC_FTFC) 32 RW C000_0000h
84h PCC DMAMUX Register (PCC_DMAMUX) 32 RW 8000_0000h
90h PCC FlexCAN0 Register (PCC_FlexCAN0) 32 RW 8000_0000h
94h PCC FlexCAN1 Register (PCC_FlexCAN1) 32 RW 8000_0000h
98h PCC FTM3 Register (PCC_FTM3) 32 RW 8000_0000h
9Ch PCC ADC1 Register (PCC_ADC1) 32 RW 8000_0000h
ACh PCC FlexCAN2 Register (PCC_FlexCAN2) 32 RW 8000_0000h
B0h PCC LPSPI0 Register (PCC_LPSPI0) 32 RW 8000_0000h
B4h PCC LPSPI1 Register (PCC_LPSPI1) 32 RW 8000_0000h
B8h PCC LPSPI2 Register (PCC_LPSPI2) 32 RW 8000_0000h
C4h PCC PDB1 Register (PCC_PDB1) 32 RW 8000_0000h
C8h PCC CRC Register (PCC_CRC) 32 RW 8000_0000h
D8h PCC PDB0 Register (PCC_PDB0) 32 RW 8000_0000h
DCh PCC LPIT Register (PCC_LPIT) 32 RW 8000_0000h
E0h PCC FTM0 Register (PCC_FTM0) 32 RW 8000_0000h
E4h PCC FTM1 Register (PCC_FTM1) 32 RW 8000_0000h
Table continues on the next page...
Memory map and register definition
S32K1xx Series Reference Manual, Rev. 7, 04/2018
594 NXP Semiconductors
Offset Register Width
(In bits)
Access Reset value
E8h PCC FTM2 Register (PCC_FTM2) 32 RW 8000_0000h
ECh PCC ADC0 Register (PCC_ADC0) 32 RW 8000_0000h
F4h PCC RTC Register (PCC_RTC) 32 RW 8000_0000h
100h PCC LPTMR0 Register (PCC_LPTMR0) 32 RW 8000_0000h
124h PCC PORTA Register (PCC_PORTA) 32 RW 8000_0000h
128h PCC PORTB Register (PCC_PORTB) 32 RW 8000_0000h
12Ch PCC PORTC Register (PCC_PORTC) 32 RW 8000_0000h
130h PCC PORTD Register (PCC_PORTD) 32 RW 8000_0000h
134h PCC PORTE Register (PCC_PORTE) 32 RW 8000_0000h
150h PCC SAI0 Register (PCC_SAI0) 32 RW 8000_0000h
154h PCC SAI1 Register (PCC_SAI1) 32 RW 8000_0000h
168h PCC FlexIO Register (PCC_FlexIO) 32 RW 8000_0000h
184h PCC EWM Register (PCC_EWM) 32 RW 8000_0000h
198h PCC LPI2C0 Register (PCC_LPI2C0) 32 RW 8000_0000h
19Ch PCC LPI2C1 Register (PCC_LPI2C1) 32 RW 8000_0000h
1A8h PCC LPUART0 Register (PCC_LPUART0) 32 RW 8000_0000h
1ACh PCC LPUART1 Register (PCC_LPUART1) 32 RW 8000_0000h
1B0h PCC LPUART2 Register (PCC_LPUART2) 32 RW 8000_0000h
1B8h PCC FTM4 Register (PCC_FTM4) 32 RW 8000_0000h
1BCh PCC FTM5 Register (PCC_FTM5) 32 RW 8000_0000h
1C0h PCC FTM6 Register (PCC_FTM6) 32 RW 8000_0000h
1C4h PCC FTM7 Register (PCC_FTM7) 32 RW 8000_0000h
1CCh PCC CMP0 Register (PCC_CMP0) 32 RW 8000_0000h
1D8h PCC QSPI Register (PCC_QSPI) 32 RW 8000_0000h
1E4h PCC ENET Register (PCC_ENET) 32 RW 8000_0000h
29.6.2 PCC FTFC Register (PCC_FTFC)
29.6.2.1 Offset
Register Offset
PCC_FTFC 80h
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 595
29.6.2.2 Function
PCC Register
29.6.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.2.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
596 NXP Semiconductors
Field Function
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.3 PCC DMAMUX Register (PCC_DMAMUX)
29.6.3.1 Offset
Register Offset
PCC_DMAMUX 84h
29.6.3.2 Function
PCC Register
29.6.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.3.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 597
Field Function
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)
29.6.4.1 Offset
Register Offset
PCC_FlexCAN0 90h
29.6.4.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
598 NXP Semiconductors
29.6.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.4.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 599
29.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)
29.6.5.1 Offset
Register Offset
PCC_FlexCAN1 94h
29.6.5.2 Function
PCC Register
29.6.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.5.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
600 NXP Semiconductors
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.6 PCC FTM3 Register (PCC_FTM3)
29.6.6.1 Offset
Register Offset
PCC_FTM3 98h
29.6.6.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 601
29.6.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.6.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
602 NXP Semiconductors
Field Function
—
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.7 PCC ADC1 Register (PCC_ADC1)
29.6.7.1 Offset
Register Offset
PCC_ADC1 9Ch
29.6.7.2 Function
PCC Register
29.6.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 603
29.6.7.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)
29.6.8.1 Offset
Register Offset
PCC_FlexCAN2 ACh
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
604 NXP Semiconductors
29.6.8.2 Function
PCC Register
29.6.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.8.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 605
Field Function
—
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.9 PCC LPSPI0 Register (PCC_LPSPI0)
29.6.9.1 Offset
Register Offset
PCC_LPSPI0 B0h
29.6.9.2 Function
PCC Register
29.6.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.9.4 Fields
Field Function
31 Present
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
606 NXP Semiconductors
Field Function
PR This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.10 PCC LPSPI1 Register (PCC_LPSPI1)
29.6.10.1 Offset
Register Offset
PCC_LPSPI1 B4h
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 607
29.6.10.2 Function
PCC Register
29.6.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.10.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
608 NXP Semiconductors
Field Function
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.11 PCC LPSPI2 Register (PCC_LPSPI2)
29.6.11.1 Offset
Register Offset
PCC_LPSPI2 B8h
29.6.11.2 Function
PCC Register
29.6.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 609
29.6.11.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.12 PCC PDB1 Register (PCC_PDB1)
29.6.12.1 Offset
Register Offset
PCC_PDB1 C4h
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
610 NXP Semiconductors
29.6.12.2 Function
PCC Register
29.6.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.12.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 611
Field Function
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.13 PCC CRC Register (PCC_CRC)
29.6.13.1 Offset
Register Offset
PCC_CRC C8h
29.6.13.2 Function
PCC Register
29.6.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
612 NXP Semiconductors
29.6.13.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.14 PCC PDB0 Register (PCC_PDB0)
29.6.14.1 Offset
Register Offset
PCC_PDB0 D8h
29.6.14.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 613
29.6.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.14.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
614 NXP Semiconductors
29.6.15 PCC LPIT Register (PCC_LPIT)
29.6.15.1 Offset
Register Offset
PCC_LPIT DCh
29.6.15.2 Function
PCC Register
29.6.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.15.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 615
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.16 PCC FTM0 Register (PCC_FTM0)
29.6.16.1 Offset
Register Offset
PCC_FTM0 E0h
29.6.16.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
616 NXP Semiconductors
29.6.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.16.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 617
Field Function
—
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.17 PCC FTM1 Register (PCC_FTM1)
29.6.17.1 Offset
Register Offset
PCC_FTM1 E4h
29.6.17.2 Function
PCC Register
29.6.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
618 NXP Semiconductors
29.6.17.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.18 PCC FTM2 Register (PCC_FTM2)
29.6.18.1 Offset
Register Offset
PCC_FTM2 E8h
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 619
29.6.18.2 Function
PCC Register
29.6.18.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.18.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
620 NXP Semiconductors
Field Function
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.19 PCC ADC0 Register (PCC_ADC0)
29.6.19.1 Offset
Register Offset
PCC_ADC0 ECh
29.6.19.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 621
29.6.19.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.19.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
622 NXP Semiconductors
Field Function
—
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.20 PCC RTC Register (PCC_RTC)
29.6.20.1 Offset
Register Offset
PCC_RTC F4h
29.6.20.2 Function
PCC Register
29.6.20.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 623
29.6.20.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.21 PCC LPTMR0 Register (PCC_LPTMR0)
29.6.21.1 Offset
Register Offset
PCC_LPTMR0 100h
29.6.21.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
624 NXP Semiconductors
29.6.21.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FRAC
PCD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.21.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 625
Field Function
—
3
FRAC
Peripheral Clock Divider Fraction
This read/write bit field sets the fraction multiply value for the fractional clock divider used as a clock
source. Divider output clock = Divider input clock x [(FRAC+1)/(PCD+1)].
This field can be written only when the clock is disabled (CGC = 0).
NOTE: When dividing by 1 (PCD = 000), do not set the FRAC bit; otherwise, the output clock is
disabled.
0b - Fractional value is 0.
1b - Fractional value is 1.
2-0
PCD
Peripheral Clock Divider Select
This read/write bit field is used for peripherals that require a clock divider. Divider output clock = Divider
input clock x [(FRAC+1)/(PCD+1)].
This field can be written only when the clock is disabled (CGC = 0).
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
011b - Divide by 4.
100b - Divide by 5.
101b - Divide by 6.
110b - Divide by 7.
111b - Divide by 8.
29.6.22 PCC PORTA Register (PCC_PORTA)
29.6.22.1 Offset
Register Offset
PCC_PORTA 124h
29.6.22.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
626 NXP Semiconductors
29.6.22.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.22.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 627
29.6.23 PCC PORTB Register (PCC_PORTB)
29.6.23.1 Offset
Register Offset
PCC_PORTB 128h
29.6.23.2 Function
PCC Register
29.6.23.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.23.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
628 NXP Semiconductors
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.24 PCC PORTC Register (PCC_PORTC)
29.6.24.1 Offset
Register Offset
PCC_PORTC 12Ch
29.6.24.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 629
29.6.24.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.24.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
630 NXP Semiconductors
29.6.25 PCC PORTD Register (PCC_PORTD)
29.6.25.1 Offset
Register Offset
PCC_PORTD 130h
29.6.25.2 Function
PCC Register
29.6.25.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.25.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 631
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.26 PCC PORTE Register (PCC_PORTE)
29.6.26.1 Offset
Register Offset
PCC_PORTE 134h
29.6.26.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
632 NXP Semiconductors
29.6.26.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.26.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 633
29.6.27 PCC SAI0 Register (PCC_SAI0)
29.6.27.1 Offset
Register Offset
PCC_SAI0 150h
29.6.27.2 Function
PCC Register
29.6.27.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.27.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
634 NXP Semiconductors
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.28 PCC SAI1 Register (PCC_SAI1)
29.6.28.1 Offset
Register Offset
PCC_SAI1 154h
29.6.28.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 635
29.6.28.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.28.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
636 NXP Semiconductors
29.6.29 PCC FlexIO Register (PCC_FlexIO)
29.6.29.1 Offset
Register Offset
PCC_FlexIO 168h
29.6.29.2 Function
PCC Register
29.6.29.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.29.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 637
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.30 PCC EWM Register (PCC_EWM)
29.6.30.1 Offset
Register Offset
PCC_EWM 184h
29.6.30.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
638 NXP Semiconductors
29.6.30.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.30.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 639
29.6.31 PCC LPI2C0 Register (PCC_LPI2C0)
29.6.31.1 Offset
Register Offset
PCC_LPI2C0 198h
29.6.31.2 Function
PCC Register
29.6.31.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.31.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
640 NXP Semiconductors
Field Function
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.32 PCC LPI2C1 Register (PCC_LPI2C1)
29.6.32.1 Offset
Register Offset
PCC_LPI2C1 19Ch
29.6.32.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 641
29.6.32.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.32.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
642 NXP Semiconductors
Field Function
—
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.33 PCC LPUART0 Register (PCC_LPUART0)
29.6.33.1 Offset
Register Offset
PCC_LPUART0 1A8h
29.6.33.2 Function
PCC Register
29.6.33.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 643
29.6.33.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.34 PCC LPUART1 Register (PCC_LPUART1)
29.6.34.1 Offset
Register Offset
PCC_LPUART1 1ACh
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
644 NXP Semiconductors
29.6.34.2 Function
PCC Register
29.6.34.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.34.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 645
Field Function
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.35 PCC LPUART2 Register (PCC_LPUART2)
29.6.35.1 Offset
Register Offset
PCC_LPUART2 1B0h
29.6.35.2 Function
PCC Register
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
646 NXP Semiconductors
29.6.35.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.35.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 647
Field Function
—
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.36 PCC FTM4 Register (PCC_FTM4)
29.6.36.1 Offset
Register Offset
PCC_FTM4 1B8h
29.6.36.2 Function
PCC Register
29.6.36.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
648 NXP Semiconductors
29.6.36.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.37 PCC FTM5 Register (PCC_FTM5)
29.6.37.1 Offset
Register Offset
PCC_FTM5 1BCh
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 649
29.6.37.2 Function
PCC Register
29.6.37.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.37.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
650 NXP Semiconductors
Field Function
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.38 PCC FTM6 Register (PCC_FTM6)
29.6.38.1 Offset
Register Offset
PCC_FTM6 1C0h
29.6.38.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 651
29.6.38.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.38.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
652 NXP Semiconductors
Field Function
—
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.39 PCC FTM7 Register (PCC_FTM7)
29.6.39.1 Offset
Register Offset
PCC_FTM7 1C4h
29.6.39.2 Function
PCC Register
29.6.39.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 653
29.6.39.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off. An external clock can be enabled for this peripheral.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.40 PCC CMP0 Register (PCC_CMP0)
29.6.40.1 Offset
Register Offset
PCC_CMP0 1CCh
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
654 NXP Semiconductors
29.6.40.2 Function
PCC Register
29.6.40.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.40.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 655
Field Function
—
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.41 PCC QSPI Register (PCC_QSPI)
29.6.41.1 Offset
Register Offset
PCC_QSPI 1D8h
29.6.41.2 Function
PCC Register
29.6.41.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
0
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.41.4 Fields
Field Function
31 Present
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
656 NXP Semiconductors
Field Function
PR This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
—
This read-only bit field is reserved and always has the value 0.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
29.6.42 PCC ENET Register (PCC_ENET)
29.6.42.1 Offset
Register Offset
PCC_ENET 1E4h
29.6.42.2 Function
PCC Register
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 657
29.6.42.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P
R
CGC
Reserved
0
PC
S
0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FRAC
PCD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.6.42.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the clock for the peripheral.
0b - Clock disabled
1b - Clock enabled. The current clock selection and divider options are locked.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
111b - Clock option 7
23-4 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
658 NXP Semiconductors
Field Function
—
3
FRAC
Peripheral Clock Divider Fraction
This read/write bit field sets the fraction multiply value for the fractional clock divider used as a clock
source. Divider output clock = Divider input clock x [(FRAC+1)/(PCD+1)].
This field can be written only when the clock is disabled (CGC = 0).
NOTE: When dividing by 1 (PCD = 000), do not set the FRAC bit; otherwise, the output clock is
disabled.
0b - Fractional value is 0.
1b - Fractional value is 1.
2-0
PCD
Peripheral Clock Divider Select
This read/write bit field is used for peripherals that require a clock divider. Divider output clock = Divider
input clock x [(FRAC+1)/(PCD+1)].
This field can be written only when the clock is disabled (CGC = 0).
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
011b - Divide by 4.
100b - Divide by 5.
101b - Divide by 6.
110b - Divide by 7.
111b - Divide by 8.
Chapter 29 Peripheral Clock Controller (PCC)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 659
PCC register descriptions
S32K1xx Series Reference Manual, Rev. 7, 04/2018
660 NXP Semiconductors
Chapter 30
Clock Monitoring Unit (CMU)
30.1 CMU chip-specific information
CMU is available in only S32K11x series of devices. Other products in the S32K1xx
series do not have CMU.
S32K11x has two instances of CMU: CMU0 and CMU1. It monitors FIRC which is the
main source of system clock. CMU needs to be enabled through software as it is not
enabled by default. CMU0 is used for reset generation on loss of clock detection, mapped
to RCM_SRS[4]. The loss of clock is indicated when FIRC goes below the threshold
programmed. Set FC_IER[FHHAEE] and FC_IER[FLLAEE] along with threshold
programming to enable reset functionality. CMU1 is used for interrupt generation when
FIRC goes below or above the programmed threshold limits. Set FC_IER[FHHIE] and
FC_IER[FLLIE] along with threshold programming in CMU1 to enable interrupt
functionality.
Following figure shows connection of CMU with the chip:
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 661
Figure 30-1. CMU on chip
Loss of Clock Indication Time Example: Conditions applied:
• CMU is enabled
• Monitored clock is lost
• 5 us LOC indication time requirement with
• bus clock at 48 MHz
• reference clock at 8 MHz
Formula for LOC indication time: ( 2*REF_CNT + 2 )*reference clock cycle + 3*bus
clock cycles
Calculation: 5 us > (2*REF_CNT + 2)*0.125 us + 3*0.0208 us
Result: REF_CNT < 18
Interpretation: The FLL REF_CNT should be programmed less than 18.
NOTE
• CMU needs to be disabled before disabling either FIRC or
SIRC. If system clock is FIRC, CMU cannot be enabled if
FIRC is not present from start, since system clock is
required to enable CMU.
• For safety applications , CMU should run on a different
clock than WDOG.
CMU chip-specific information
S32K1xx Series Reference Manual, Rev. 7, 04/2018
662 NXP Semiconductors
30.2 Introduction
CMU_FC modules are required to ensure clock signal integrity on the chip.
CMU_FC checks if the frequency of a monitored clock is within a programmable
frequency range specified by the user. If the frequency is outside the specified limits, it
could lead to performance, protocol, and timing failures. CMU_FC requires a clock that
is uses as a base reference for the frequency check operation. This reference clock must
be within documented limits for correct CMU_FC operation. If a reference clock is
outside operating parameters, CMU_FC behavior cannot be guaranteed.
30.2.1 Basic operation
CMU_FC counts clock cycles of the monitored clock during time duration of n clock
cycles of the reference clock. The number n reference cycles is user programmable. The
final count of the monitored clock after this time is compared against the user
programmable upper and lower threshold count limits. The cycle count is then checked to
see if it is within programmed limits. If the monitored clock count is not within
programmed limits, a register status field is set. If needed, an interrupt can be configured
to assert when the status flag sets.
CMU_FC cannot detect the following:
• Duty cycle variations of a monitored clock.
• Instantaneous monitored clock frequency variations which do not cross the upper or
lower measurement thresholds.
Chapter 30 Clock Monitoring Unit (CMU)
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 663
Checking Window
Reference Counter
=
Control Logic
Enable
ref_clk
Monitor Counter
High Threshold
mon_clk
Low Threshold
<
FHH
FLL
>
Figure 30-2. CMU_FC block diagram
30.2.2 Features
The CMU_FC features are:
• If a monitored clock frequency is higher than high frequency reference (FHH), an
event occurs.
• If a monitored clock frequency is lower than low frequency reference (FLL), an
event occurs.
• Programmable duration of reference clock cycles.
• Time out functionality to generate an FLL event when a monitored clock is lost.
• Masking of FHH interrupt.
• Masking of FLL interrupt.
Table 30-1. Clock description
Signal Name I/O Description
ref_clk I Reference Clock - Clock signal CMU_FC
uses as reference for evaluating
monitored clock.
mon_clk I Monitored Clock - Clock signal CMU_FC
compares to lower and higher frequency
limits to determine if the clock is
operating within defined frequency
range.
Introduction
S32K1xx Series Reference Manual, Rev. 7, 04/2018
664 NXP Semiconductors
NOTE
See the Clocking chapter for details of monitored and reference
clocks used on this chip.
30.3 CMU_FC register descriptions
30.3.1 CMU_FC Memory map
This section describes the address order of all the CMU_FC registers. Each description
includes a standard register diagram and associated field descriptions.
CMU0 base address: 4003_E000h
CMU1 base address: 4003_F000h
Offset Register Width