_REV1.18 SEC S5P6818X Users Manual Preliminary Ver 0.00

User Manual:

Open the PDF directly: View PDF .
Page Count: 1670 [warning: Documents this large are best viewed by clicking the View PDF Link!]

Scroll down to view the document on your mobile browser.

S5P6818
- Important Notice
- Trademarks
- Chip Handling Guide
- Revision History
- Table of Contents
- List of Figures
- List of Tables
- List of Examples
- List of Conventions
- List of Acronyms
1 Product Overview
- 1.1 Introduction
- 1.2 Features
- 1.3 Block Diagram
- 1.4 Brief Functional Specification
2 Mechanical Dimension & IO Function Description
- 2.1 Mechanical Dimension
- 2.2 FCBGA Ball Map
- 2.3 I/O Function Description
  - 2.3.1 Ball List Table
- 2.4 Ball List Table: sorted by Function
3 System Boot
- 3.1 Overview
- 3.2 Functional Description
  - 3.2.1 System Configuration
- 3.3 External Static Memory Boot
- 3.4 Internal ROM Boot
4 System Control
- 4.1 Overview
- 4.2 Features
- 4.3 Block Diagram
- 4.4 Clock Manager Functional Description
- 4.5 Power Manager
  - 4.5.1 Power Manager Overview
  - 4.5.2 Power Down Mode Operation
- 4.6 Reset Generation
- 4.7 Tie Off
- 4.8 AXI BUS
  - 4.8.1 Programmable Quality of Service (ProgQoS)
  - 4.8.2 Arbitration Scheme
    - 4.8.2.1 RR Schemes
- 4.9 Register Description
5 Clock Generator
- 5.1 IP Clock Generator Overview
- 5.2 Clock Generator Level 0
  - 5.2.1 Block Diagram
  - 5.2.2 Register Description
    - 5.2.2.1 Register Map Summary
- 5.3 Clock Generator Level 1
  - 5.3.1 Block Diagram
  - 5.3.2 Register Description
    - 5.3.2.1 Register MAP Summary
- 5.4 Clock Generator Level 2
  - 5.4.1 Block Diagram
  - 5.4.2 Register Description
    - 5.4.2.1 Register Map Summary
6 BUS
- 6.1 Overview
- 6.2 Features
- 6.3 Description
  - 6.3.1 AXI BUS Description
  - 6.3.2 Programmable Quality of Service (ProgQoS)
- 6.4 Register Description
  - 6.4.1 Register Map Summary
    - 6.4.1.1 AXI BUS
    - 6.4.1.2 CCI BUS
7 TrustZone Protection Controller (TZPC)
- 7.1 Overview
- 7.2 Features
- 7.3 TZPC Configuration
- 7.4 Register Descriptions
  - 7.4.1 Register Map Summary
8 System L2 Cache (PL-310 L2C)
- 8.1 Overview
- 8.2 Features
- 8.3 Block Diagram
- 8.4 Functional Description
  - 8.4.1 L2 Cache User Configure
  - 8.4.2 Initialization Sequence
- 8.5 Register Description
  - 8.5.1 Register Map Summary
9 DMA
- 9.1 Overview
- 9.2 Features
- 9.3 Block Diagram
- 9.4 Functional Description
  - 9.4.1 Software Considerations
  - 9.4.2 Programmer's Model
- 9.5 Register Description
  - 9.5.1 Register Map Summary
10 Interrupt Controller
- 10.1 Overview
- 10.2 Features
- 10.3 Security Extensions Support
- 10.4 Virtualization Support
- 10.5 Terminology
- 10.6 Functional Overview
- 10.7 Interrupt Handling and Prioritization
  - 10.7.1 About Interrupt Handling and Prioritization
    - 10.7.1.1 Handling Different Interrupt Types in a Multiprocessor System
    - 10.7.1.2 Identifying the Supported Interrupt
  - 10.7.2 General Handling of Interrupts
- 10.8 Interrupt Source
- 10.9 Register Description
  - 10.9.1 Register Map Summary
11 Watch Dog Timer
- 11.1 Overview
- 11.2 Features
- 11.3 Functional Description
- 11.4 Register Description
  - 11.4.1 Register Map Summary
12 RTC
- 12.1 Overview
- 12.2 Features
- 12.3 Block Diagram
- 12.4 Functional Description
- 12.5 Register Description
  - 12.5.1 Register Map Summary
13 Alive
- 13.1 Overview
- 13.2 Features
- 13.3 Power Isolation
  - 13.3.1 Core Power Off
  - 13.3.2 Power Gating
- 13.4 Alive Registers
- 13.5 Momentary Power Control
  - 13.5.1 CoreVDD Powering On
  - 13.5.2 CoreVDD Powering Off
- 13.6 SLEEP Mode
- 13.7 PMU (Power management Unit)
- 13.8 Register Description
  - 13.8.1 Register Map Summary
14 ID Register
- 14.1 Overview
- 14.2 Features
- 14.3 Functional Description
- 14.4 Register Description
  - 14.4.1 Register Map Summary
- 14.5 Application Notes
15 Memory Controller
- 15.1 Overview
  - 15.1.1 Unified Memory Architecture (UMA)
- 15.2 Block Diagram
- 15.3 Functional Description
- 15.4 Register Description
  - 15.4.1 Register Map Summary
16 GPIO Controller
- 16.1 Overview
- 16.2 Features
- 16.3 Block Diagram
- 16.4 Functional Description
- 16.5 Register Description
  - 16.5.1 Register Map Summary
17 Ethernet MAC
- 17.1 Overview
- 17.2 Features
  - 17.2.1 MAC Core Features
  - 17.2.2 DMA Block Features
- 17.3 Block Diagram
- 17.4 Register Description
  - 17.4.1 Register Map Summary
    - 17.4.1.1 MAC DMA
    - 17.4.1.2 MAC Core
18 SD/MMC Controller
- 18.1 Overview
- 18.2 Features
  - 18.2.1 Features of Mobile Storage Host
- 18.3 Block Diagram
  - 18.3.1 Clock Phase Shifter
- 18.4 Register Description
  - 18.4.1 Register Map Summary
19 Pulse Period Measurement (PPM)
- 19.1 Overview
- 19.2 Features
- 19.3 Block Diagram
- 19.4 Functional Description
- 19.5 Register Description
  - 19.5.1 Register Map Summary
20 Pulse Width Modulation (PWM) Timer
- 20.1 Overview
- 20.2 Features
- 20.3 PWM Operation
- 20.4 Register Description
  - 20.4.1 Register Map Summary
21 Analog Digital Converter (ADC)
- 21.1 Overview
- 21.2 Features
- 21.3 Block Diagram
- 21.4 Functional Description
- 21.5 Register Description
  - 21.5.1 Register Map Summary
22 I2C Controller
- 22.1 Overview
- 22.2 Features
- 22.3 Block Diagram
- 22.4 Functional Description
- 22.5 Programming Guide
  - 22.5.1 Flowcharts of Operations in Each Mode
- 22.6 Register Description
  - 22.6.1 Register Map Summary
23 SPI/SSP
- 23.1 Overview
- 23.2 Features
- 23.3 Block Diagram
- 23.4 Functional Description
- 23.5 Register Description
  - 23.5.1 Register Map Summary
24 MPEG-TS Interface
- 24.1 Overview
- 24.2 Features
- 24.3 Functional Description
  - 24.3.1 Timing
- 24.4 Register Description
  - 24.4.1 Register Map Summary
- 24.5 PID Filter Data Structure
25 UART_ISO7816
- 25.1 Overview
- 25.2 Features
- 25.3 UART Description
- 25.4 Register Description
  - 25.4.1 Register Map Summary
26 USB2.0 OTG
- 26.1 Overview
- 26.2 Features
- 26.3 Block Diagram
- 26.4 I/O Pin Description
- 26.5 Functional Description
- 26.6 Programming User Configure of PHY and OTG LINK
- 26.7 Register Description
  - 26.7.1 Register Map Summary
27 USB2.0 HOST
- 27.1 Overview
- 27.2 Features
- 27.3 Block Diagram
- 27.4 Functional Description
- 27.5 Register Description
  - 27.5.1 Register Map Summary
28 I2S
- 28.1 Overview
- 28.2 Features
- 28.3 Block Diagram
- 28.4 Functional Description
- 28.5 Programming Guide
- 28.6 Register Description
  - 28.6.1 Register Map Summary
29 AC97
- 29.1 Overview
- 29.2 Features
- 29.3 Block Diagram
- 29.4 Functional Description
- 29.5 Register Description
  - 29.5.1 Register Map Summary
30 SPDIF TX
- 30.1 Overview
- 30.2 Features
- 30.3 Block Diagram
- 30.4 Functional Description
- 30.5 Channel Coding
- 30.6 Preamble
- 30.7 Non-Linear PCM Encoded Source (IEC 61937)
- 30.8 SPDIF Operation
- 30.9 Shadowed Register
- 30.10 Register Description
  - 30.10.1 Register Map Summary
31 SPDIF RX
- 31.1 Overview
- 31.2 Features
- 31.3 Block Diagram
- 31.4 Functional Description
- 31.5 Register Description
  - 31.5.1 Register Map Summary
32 PDM
- 32.1 Overview
- 32.2 Features
- 32.3 Block Diagram
- 32.4 PDM Application Note
  - 32.4.1 Butterworth Filter Configuration
- 32.5 Register Description
  - 32.5.1 Register Map Summary
33 Display Architecture
- 33.1 Overview
- 33.2 Features
- 33.3 Block Diagram
- 33.4 TFT/MPU Interface
- 33.5 Register Description
  - 33.5.1 Register Map Summary
34 Multi Layer Controller (MLC)
- 34.1 Overview
- 34.2 Features
- 34.3 Block Diagram
- 34.4 Dual Register Set Architecture
- 34.5 MLC Global Parameters
- 34.6 Clock Generation
- 34.7 Register Description
  - 34.7.1 Register Map Summary
35 Display Controller (DPC)
- 35.1 Overview
- 35.2 Features
- 35.3 Block Diagram
- 35.4 Sync Generator
- 35.5 Register Description
  - 35.5.1 Register Map Summary
36 De-Interlace
- 36.1 Overview
- 36.2 Features
- 36.3 Operation
- 36.4 Register Description
  - 36.4.1 Register Map Summary
37 Scaler
- 37.1 Overview
- 37.2 Features
- 37.3 Block Diagram
- 37.4 Functional Description
  - 37.4.1 Digital Filter Characteristics
    - 37.4.1.1 Horizontal Filter (5-Tab FIR Filter) Frequency Response and Group Delay
    - 37.4.1.2 Vertical Filter (3-Tab FIR Filter) Frequency Response and Group Delay
- 37.5 Programming Guide
  - 37.5.1 Configuration
  - 37.5.2 RUN
- 37.6 Register Description
  - 37.6.1 Register Map Summary
38 LVDS
- 38.1 Overview
- 38.2 Features
- 38.3 Block Diagram
- 38.4 Functional Description
- 38.5 Register Description
  - 38.5.1 Register Map Summary
  - 38.5.2 DisplayTop Register
    - 38.5.2.1 LVDS_MUXCTRL
39 HDMI
- 39.1 Overview
- 39.2 Features
- 39.3 Block Diagram
- 39.4 Functional Description
- 39.5 Register Description
  - 39.5.1 Register Map Summary
- 39.6 HDMI PHY
40 MIPI
- 40.1 Overview
- 40.2 Features
  - 40.2.1 DSI Master Features (DSIM)
  - 40.2.2 CSI Slave Features (CSIS)
- 40.3 D-PHY Features
- 40.4 Block Diagram for DSIM
- 40.5 Interfaces and Protocol
- 40.6 Configuration
- 40.7 PLL
- 40.8 Buffer
- 40.9 DSIM
  - 40.9.1 Register Description
    - 40.9.1.1 Register Map Summary
- 40.10 CSIS
- 40.11 D-PHY
  - 40.11.1 Architecture
41 Video Input Processor (VIP)
- 41.1 Overview
- 41.2 Features
- 41.3 Block Diagram
- 41.4 VIP Interconnection
- 41.5 Clipper & Decimator
- 41.6 Interrupt Generation
- 41.7 Register Description
  - 41.7.1 Register Map Summary
42 Multi-Format Video Codec
- 42.1 Overview
- 42.2 Functional Description
43 3D Graphic Engine
- 43.1 Overview
- 43.2 Features
- 43.3 Operation
44 Crypto Engine
- 44.1 Overview
- 44.2 Features
- 44.3 Block Diagram
- 44.4 Functional Description
  - 44.4.1 Polling Mode
  - 44.4.2 Mode
- 44.5 Register Description
  - 44.5.1 Register Map Summary
45 Secure JTAG
- 45.1 Overview
- 45.2 Features
- 45.3 Block Diagram
- 45.4 Secure JTAG User Configure
46 Temperature Monitor Unit (TMU)
- 46.1 Overview
- 46.2 Temperature Sensing Auto Mode with External Clocks
- 46.3 Temperature Code Table
- 46.4 I/O Description
- 46.5 Programming Guide
- 46.6 Register Description
  - 46.6.1 Register Map Summary
47 Electrical Characteristics
- 47.1 Absolute Maximum Ratings
- 47.2 Recommended Operating Conditions
- 47.3 D.C. Electrical Characteristics

Navigation menu