STM32F75xxx And STM32F74xxx Advanced Arm® Based 32 Bit MCUs STM32F7[45]xxx Reference Manual
User Manual:
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- 1 Documentation conventions
- 2 System and memory overview
- 2.1 System architecture
- Figure 1. System architecture for STM32F75xxx and STM32F74xxx devices
- 2.1.1 Multi AHB BusMatrix
- 2.1.2 AHB/APB bridges (APB)
- 2.1.3 CPU AXIM bus
- 2.1.4 ITCM bus
- 2.1.5 DTCM bus
- 2.1.6 CPU AHBS bus
- 2.1.7 AHB peripheral bus
- 2.1.8 DMA memory bus
- 2.1.9 DMA peripheral bus
- 2.1.10 Ethernet DMA bus
- 2.1.11 USB OTG HS DMA bus
- 2.1.12 LCD-TFT controller DMA bus
- 2.1.13 DMA2D bus
- 2.2 Memory organization
- 2.3 Embedded SRAM
- 2.4 Flash memory overview
- 2.5 Boot configuration
- 2.1 System architecture
- 3 Embedded Flash memory (FLASH)
- 3.1 Introduction
- 3.2 Flash main features
- 3.3 Flash functional description
- 3.4 FLASH Option bytes
- 3.5 FLASH memory protection
- 3.6 One-time programmable bytes
- 3.7 FLASH registers
- 3.7.1 Flash access control register (FLASH_ACR)
- 3.7.2 Flash key register (FLASH_KEYR)
- 3.7.3 Flash option key register (FLASH_OPTKEYR)
- 3.7.4 Flash status register (FLASH_SR)
- 3.7.5 Flash control register (FLASH_CR)
- 3.7.6 Flash option control register (FLASH_OPTCR)
- 3.7.7 Flash option control register (FLASH_OPTCR1)
- 3.7.8 Flash interface register map
- 4 Power controller (PWR)
- 4.1 Power supplies
- 4.2 Power supply supervisor
- 4.3 Low-power modes
- 4.4 Power control registers
- 4.5 PWR register map
- 5 Reset and clock control (RCC)
- 5.1 Reset
- 5.2 Clocks
- Figure 13. Clock tree
- 5.2.1 HSE clock
- 5.2.2 HSI clock
- 5.2.3 PLL
- 5.2.4 LSE clock
- 5.2.5 LSI clock
- 5.2.6 System clock (SYSCLK) selection
- 5.2.7 Clock security system (CSS)
- 5.2.8 RTC/AWU clock
- 5.2.9 Watchdog clock
- 5.2.10 Clock-out capability
- 5.2.11 Internal/external clock measurement using TIM5/TIM11
- 5.2.12 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy)
- 5.3 RCC registers
- 5.3.1 RCC clock control register (RCC_CR)
- 5.3.2 RCC PLL configuration register (RCC_PLLCFGR)
- 5.3.3 RCC clock configuration register (RCC_CFGR)
- 5.3.4 RCC clock interrupt register (RCC_CIR)
- 5.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 5.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 5.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
- 5.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)
- 5.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 5.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR)
- 5.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 5.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
- 5.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- 5.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 5.3.15 RCC AHB1 peripheral clock enable in low-power mode register (RCC_AHB1LPENR)
- 5.3.16 RCC AHB2 peripheral clock enable in low-power mode register (RCC_AHB2LPENR)
- 5.3.17 RCC AHB3 peripheral clock enable in low-power mode register (RCC_AHB3LPENR)
- 5.3.18 RCC APB1 peripheral clock enable in low-power mode register (RCC_APB1LPENR)
- 5.3.19 RCC APB2 peripheral clock enabled in low-power mode register (RCC_APB2LPENR)
- 5.3.20 RCC backup domain control register (RCC_BDCR)
- 5.3.21 RCC clock control & status register (RCC_CSR)
- 5.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)
- 5.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
- 5.3.24 RCC PLLSAI configuration register (RCC_PLLSAICFGR)
- 5.3.25 RCC dedicated clocks configuration register (RCC_DKCFGR1)
- 5.3.26 RCC dedicated clocks configuration register (DCKCFGR2)
- 5.3.27 RCC register map
- 6 General-purpose I/Os (GPIO)
- 6.1 Introduction
- 6.2 GPIO main features
- 6.3 GPIO functional description
- Figure 17. Basic structure of an I/O port bit
- Figure 18. Basic structure of a 5-Volt tolerant I/O port bit
- Table 21. Port bit configuration table
- 6.3.1 General-purpose I/O (GPIO)
- 6.3.2 I/O pin alternate function multiplexer and mapping
- 6.3.3 I/O port control registers
- 6.3.4 I/O port data registers
- 6.3.5 I/O data bitwise handling
- 6.3.6 GPIO locking mechanism
- 6.3.7 I/O alternate function input/output
- 6.3.8 External interrupt/wakeup lines
- 6.3.9 Input configuration
- 6.3.10 Output configuration
- 6.3.11 Alternate function configuration
- 6.3.12 Analog configuration
- 6.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 6.3.14 Using the GPIO pins in the backup supply domain
- 6.4 GPIO registers
- 6.4.1 GPIO port mode register (GPIOx_MODER) (x =A..K)
- 6.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..K)
- 6.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..K)
- 6.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..K)
- 6.4.5 GPIO port input data register (GPIOx_IDR) (x = A..K)
- 6.4.6 GPIO port output data register (GPIOx_ODR) (x = A..K)
- 6.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..K)
- 6.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..K)
- 6.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..K)
- 6.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..J)
- 6.4.11 GPIO register map
- 7 System configuration controller (SYSCFG)
- 7.1 I/O compensation cell
- 7.2 SYSCFG registers
- 7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 7.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
- 7.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 7.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 7.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 7.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 7.2.7 Compensation cell control register (SYSCFG_CMPCR)
- 7.2.8 SYSCFG register maps
- 8 Direct memory access controller (DMA)
- 8.1 DMA introduction
- 8.2 DMA main features
- 8.3 DMA functional description
- 8.3.1 DMA block diagram
- 8.3.2 DMA overview
- 8.3.3 DMA transactions
- 8.3.4 Channel selection
- 8.3.5 Arbiter
- 8.3.6 DMA streams
- 8.3.7 Source, destination and transfer modes
- 8.3.8 Pointer incrementation
- 8.3.9 Circular mode
- 8.3.10 Double-buffer mode
- 8.3.11 Programmable data width, packing/unpacking, endianness
- 8.3.12 Single and burst transfers
- 8.3.13 FIFO
- 8.3.14 DMA transfer completion
- 8.3.15 DMA transfer suspension
- 8.3.16 Flow controller
- 8.3.17 Summary of the possible DMA configurations
- 8.3.18 Stream configuration procedure
- 8.3.19 Error management
- 8.4 DMA interrupts
- 8.5 DMA registers
- 8.5.1 DMA low interrupt status register (DMA_LISR)
- 8.5.2 DMA high interrupt status register (DMA_HISR)
- 8.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
- 8.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
- 8.5.5 DMA stream x configuration register (DMA_SxCR)
- 8.5.6 DMA stream x number of data register (DMA_SxNDTR)
- 8.5.7 DMA stream x peripheral address register (DMA_SxPAR)
- 8.5.8 DMA stream x memory 0 address register (DMA_SxM0AR)
- 8.5.9 DMA stream x memory 1 address register (DMA_SxM1AR)
- 8.5.10 DMA stream x FIFO control register (DMA_SxFCR)
- 8.5.11 DMA register map
- 9 Chrom-ART Accelerator™ controller (DMA2D)
- 9.1 DMA2D introduction
- 9.2 DMA2D main features
- 9.3 DMA2D functional description
- 9.3.1 General description
- 9.3.2 DMA2D control
- 9.3.3 DMA2D foreground and background FIFOs
- 9.3.4 DMA2D foreground and background pixel format converter (PFC)
- 9.3.5 DMA2D foreground and background CLUT interface
- 9.3.6 DMA2D blender
- 9.3.7 DMA2D output PFC
- 9.3.8 DMA2D output FIFO
- 9.3.9 DMA2D AHB master port timer
- 9.3.10 DMA2D transactions
- 9.3.11 DMA2D configuration
- 9.3.12 DMA2D transfer control (start, suspend, abort and completion)
- 9.3.13 Watermark
- 9.3.14 Error management
- 9.3.15 AHB dead time
- 9.4 DMA2D interrupts
- 9.5 DMA2D registers
- 9.5.1 DMA2D control register (DMA2D_CR)
- 9.5.2 DMA2D Interrupt Status Register (DMA2D_ISR)
- 9.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)
- 9.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)
- 9.5.5 DMA2D foreground offset register (DMA2D_FGOR)
- 9.5.6 DMA2D background memory address register (DMA2D_BGMAR)
- 9.5.7 DMA2D background offset register (DMA2D_BGOR)
- 9.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)
- 9.5.9 DMA2D foreground color register (DMA2D_FGCOLR)
- 9.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)
- 9.5.11 DMA2D background color register (DMA2D_BGCOLR)
- 9.5.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR)
- 9.5.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR)
- 9.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)
- 9.5.15 DMA2D output color register (DMA2D_OCOLR)
- 9.5.16 DMA2D output memory address register (DMA2D_OMAR)
- 9.5.17 DMA2D output offset register (DMA2D_OOR)
- 9.5.18 DMA2D number of line register (DMA2D_NLR)
- 9.5.19 DMA2D line watermark register (DMA2D_LWR)
- 9.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)
- 9.5.21 DMA2D register map
- 10 Nested vectored interrupt controller (NVIC)
- 11 Extended interrupts and events controller (EXTI)
- 11.1 EXTI main features
- 11.2 EXTI block diagram
- 11.3 Wakeup event management
- 11.4 Functional description
- 11.5 Hardware interrupt selection
- 11.6 Hardware event selection
- 11.7 Software interrupt/event selection
- 11.8 External interrupt/event line mapping
- 11.9 EXTI registers
- 12 Cyclic redundancy check calculation unit (CRC)
- 13 Flexible memory controller (FMC)
- 13.1 FMC main features
- 13.2 FMC block diagram
- 13.3 AHB interface
- 13.4 External device address mapping
- 13.5 NOR Flash/PSRAM controller
- Table 56. Programmable NOR/PSRAM access parameters
- 13.5.1 External memory interface signals
- 13.5.2 Supported memories and transactions
- 13.5.3 General timing rules
- 13.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Figure 35. Mode1 read access waveforms
- Figure 36. Mode1 write access waveforms
- Table 62. FMC_BCRx bit fields
- Table 63. FMC_BTRx bit fields
- Figure 37. ModeA read access waveforms
- Figure 38. ModeA write access waveforms
- Table 64. FMC_BCRx bit fields
- Table 65. FMC_BTRx bit fields
- Table 66. FMC_BWTRx bit fields
- Figure 39. Mode2 and mode B read access waveforms
- Figure 40. Mode2 write access waveforms
- Figure 41. ModeB write access waveforms
- Table 67. FMC_BCRx bit fields
- Table 68. FMC_BTRx bit fields
- Table 69. FMC_BWTRx bit fields
- Figure 42. ModeC read access waveforms
- Figure 43. ModeC write access waveforms
- Table 70. FMC_BCRx bit fields
- Table 71. FMC_BTRx bit fields
- Table 72. FMC_BWTRx bit fields
- Figure 44. ModeD read access waveforms
- Figure 45. ModeD write access waveforms
- Table 73. FMC_BCRx bit fields
- Table 74. FMC_BTRx bit fields
- Table 75. FMC_BWTRx bit fields
- Figure 46. Muxed read access waveforms
- Figure 47. Muxed write access waveforms
- Table 76. FMC_BCRx bit fields
- Table 77. FMC_BTRx bit fields
- Figure 48. Asynchronous wait during a read access waveforms
- Figure 49. Asynchronous wait during a write access waveforms
- 13.5.5 Synchronous transactions
- 13.5.6 NOR/PSRAM controller registers
- 13.6 NAND Flash controller
- Table 82. Programmable NAND Flash access parameters
- 13.6.1 External memory interface signals
- 13.6.2 NAND Flash supported memories and transactions
- 13.6.3 Timing diagrams for NAND Flash memory
- 13.6.4 NAND Flash operations
- 13.6.5 NAND Flash prewait functionality
- 13.6.6 Computation of the error correction code (ECC) in NAND Flash memory
- 13.6.7 NAND Flash controller registers
- 13.7 SDRAM controller
- 13.8 FMC register map
- 14 Quad-SPI interface (QUADSPI)
- 14.1 Introduction
- 14.2 QUADSPI main features
- 14.3 QUADSPI functional description
- 14.3.1 QUADSPI block diagram
- 14.3.2 QUADSPI pins
- 14.3.3 QUADSPI command sequence
- 14.3.4 QUADSPI signal interface protocol modes
- 14.3.5 QUADSPI indirect mode
- 14.3.6 QUADSPI status flag polling mode
- 14.3.7 QUADSPI memory-mapped mode
- 14.3.8 QUADSPI Flash memory configuration
- 14.3.9 QUADSPI delayed data sampling
- 14.3.10 QUADSPI configuration
- 14.3.11 QUADSPI usage
- 14.3.12 Sending the instruction only once
- 14.3.13 QUADSPI error management
- 14.3.14 QUADSPI busy bit and abort functionality
- 14.3.15 nCS behavior
- 14.4 QUADSPI interrupts
- 14.5 QUADSPI registers
- 14.5.1 QUADSPI control register (QUADSPI_CR)
- 14.5.2 QUADSPI device configuration register (QUADSPI_DCR)
- 14.5.3 QUADSPI status register (QUADSPI_SR)
- 14.5.4 QUADSPI flag clear register (QUADSPI_FCR)
- 14.5.5 QUADSPI data length register (QUADSPI_DLR)
- 14.5.6 QUADSPI communication configuration register (QUADSPI_CCR)
- 14.5.7 QUADSPI address register (QUADSPI_AR)
- 14.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR)
- 14.5.9 QUADSPI data register (QUADSPI_DR)
- 14.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR)
- 14.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
- 14.5.12 QUADSPI polling interval register (QUADSPI _PIR)
- 14.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)
- 14.5.14 QUADSPI register map
- 15 Analog-to-digital converter (ADC)
- 15.1 ADC introduction
- 15.2 ADC main features
- 15.3 ADC functional description
- Figure 70. Single ADC block diagram
- Table 92. ADC pins
- 15.3.1 ADC on-off control
- 15.3.2 ADC1/2 and ADC3 connectivity
- 15.3.3 ADC clock
- 15.3.4 Channel selection
- 15.3.5 Single conversion mode
- 15.3.6 Continuous conversion mode
- 15.3.7 Timing diagram
- 15.3.8 Analog watchdog
- 15.3.9 Scan mode
- 15.3.10 Injected channel management
- 15.3.11 Discontinuous mode
- 15.4 Data alignment
- 15.5 Channel-wise programmable sampling time
- 15.6 Conversion on external trigger and trigger polarity
- 15.7 Fast conversion mode
- 15.8 Data management
- 15.9 Multi ADC mode
- 15.10 Temperature sensor
- 15.11 Battery charge monitoring
- 15.12 ADC interrupts
- 15.13 ADC registers
- 15.13.1 ADC status register (ADC_SR)
- 15.13.2 ADC control register 1 (ADC_CR1)
- 15.13.3 ADC control register 2 (ADC_CR2)
- 15.13.4 ADC sample time register 1 (ADC_SMPR1)
- 15.13.5 ADC sample time register 2 (ADC_SMPR2)
- 15.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 15.13.7 ADC watchdog higher threshold register (ADC_HTR)
- 15.13.8 ADC watchdog lower threshold register (ADC_LTR)
- 15.13.9 ADC regular sequence register 1 (ADC_SQR1)
- 15.13.10 ADC regular sequence register 2 (ADC_SQR2)
- 15.13.11 ADC regular sequence register 3 (ADC_SQR3)
- 15.13.12 ADC injected sequence register (ADC_JSQR)
- 15.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 15.13.14 ADC regular data register (ADC_DR)
- 15.13.15 ADC Common status register (ADC_CSR)
- 15.13.16 ADC common control register (ADC_CCR)
- 15.13.17 ADC common regular data register for dual and triple modes (ADC_CDR)
- 15.13.18 ADC register map
- 16 Digital-to-analog converter (DAC)
- 16.1 DAC introduction
- 16.2 DAC main features
- 16.3 DAC functional description
- 16.4 Dual DAC channel conversion
- 16.4.1 Independent trigger without wave generation
- 16.4.2 Independent trigger with single LFSR generation
- 16.4.3 Independent trigger with different LFSR generation
- 16.4.4 Independent trigger with single triangle generation
- 16.4.5 Independent trigger with different triangle generation
- 16.4.6 Simultaneous software start
- 16.4.7 Simultaneous trigger without wave generation
- 16.4.8 Simultaneous trigger with single LFSR generation
- 16.4.9 Simultaneous trigger with different LFSR generation
- 16.4.10 Simultaneous trigger with single triangle generation
- 16.4.11 Simultaneous trigger with different triangle generation
- 16.5 DAC registers
- 16.5.1 DAC control register (DAC_CR)
- 16.5.2 DAC software trigger register (DAC_SWTRIGR)
- 16.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 16.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 16.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 16.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 16.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 16.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 16.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 16.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 16.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 16.5.12 DAC channel1 data output register (DAC_DOR1)
- 16.5.13 DAC channel2 data output register (DAC_DOR2)
- 16.5.14 DAC status register (DAC_SR)
- 16.5.15 DAC register map
- 17 Digital camera interface (DCMI)
- 17.1 DCMI introduction
- 17.2 DCMI main features
- 17.3 DCMI clocks
- 17.4 DCMI functional overview
- 17.4.1 DCMI block diagram
- 17.4.2 DMA interface
- 17.4.3 DCMI physical interface
- Table 104. DCMI external signals
- Figure 104. DCMI signal waveforms
- Table 105. Positioning of captured data bytes in 32-bit words (8-bit width)
- Table 106. Positioning of captured data bytes in 32-bit words (10-bit width)
- Table 107. Positioning of captured data bytes in 32-bit words (12-bit width)
- Table 108. Positioning of captured data bytes in 32-bit words (14-bit width)
- 17.4.4 Synchronization
- 17.4.5 Capture modes
- 17.4.6 Crop feature
- 17.4.7 JPEG format
- 17.4.8 FIFO
- 17.5 Data format description
- 17.6 DCMI interrupts
- 17.7 DCMI register description
- 17.7.1 DCMI control register (DCMI_CR)
- 17.7.2 DCMI status register (DCMI_SR)
- 17.7.3 DCMI raw interrupt status register (DCMI_RIS)
- 17.7.4 DCMI interrupt enable register (DCMI_IER)
- 17.7.5 DCMI masked interrupt status register (DCMI_MIS)
- 17.7.6 DCMI interrupt clear register (DCMI_ICR)
- 17.7.7 DCMI embedded synchronization code register (DCMI_ESCR)
- 17.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR)
- 17.7.9 DCMI crop window start (DCMI_CWSTRT)
- 17.7.10 DCMI crop window size (DCMI_CWSIZE)
- 17.7.11 DCMI data register (DCMI_DR)
- 17.7.12 DCMI register map
- 18 LCD-TFT display controller (LTDC)
- 18.1 Introduction
- 18.2 LTDC main features
- 18.3 LTDC functional description
- 18.4 LTDC programmable parameters
- 18.5 LTDC interrupts
- 18.6 LTDC programming procedure
- 18.7 LTDC registers
- 18.7.1 LTDC synchronization size configuration register (LTDC_SSCR)
- 18.7.2 LTDC back porch configuration register (LTDC_BPCR)
- 18.7.3 LTDC active width configuration register (LTDC_AWCR)
- 18.7.4 LTDC total width configuration register (LTDC_TWCR)
- 18.7.5 LTDC global control register (LTDC_GCR)
- 18.7.6 LTDC shadow reload configuration register (LTDC_SRCR)
- 18.7.7 LTDC background color configuration register (LTDC_BCCR)
- 18.7.8 LTDC interrupt enable register (LTDC_IER)
- 18.7.9 LTDC interrupt status register (LTDC_ISR)
- 18.7.10 LTDC Interrupt Clear Register (LTDC_ICR)
- 18.7.11 LTDC line interrupt position configuration register (LTDC_LIPCR)
- 18.7.12 LTDC current position status register (LTDC_CPSR)
- 18.7.13 LTDC current display status register (LTDC_CDSR)
- 18.7.14 LTDC layer x control register (LTDC_LxCR)
- 18.7.15 LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR)
- 18.7.16 LTDC layer x window vertical position configuration register (LTDC_LxWVPCR)
- 18.7.17 LTDC layer x color keying configuration register (LTDC_LxCKCR)
- 18.7.18 LTDC layer x pixel format configuration register (LTDC_LxPFCR)
- 18.7.19 LTDC layer x constant alpha configuration register (LTDC_LxCACR)
- 18.7.20 LTDC layer x default color configuration register (LTDC_LxDCCR)
- 18.7.21 LTDC layer x blending factors configuration register (LTDC_LxBFCR)
- 18.7.22 LTDC layer x color frame buffer address register (LTDC_LxCFBAR)
- 18.7.23 LTDC layer x color frame buffer length register (LTDC_LxCFBLR)
- 18.7.24 LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR)
- 18.7.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR)
- 18.7.26 LTDC register map
- 19 True random number generator (RNG)
- 20 Cryptographic processor (CRYP)
- 20.1 Introduction
- 20.2 CRYP main features
- 20.3 CRYP functional description
- 20.3.1 CRYP block diagram
- 20.3.2 CRYP internal signals
- 20.3.3 CRYP DES/TDES cryptographic core
- 20.3.4 CRYP AES cryptographic core
- 20.3.5 CRYP procedure to perform a cipher operation
- 20.3.6 CRYP busy state
- 20.3.7 Preparing the CRYP AES key for decryption
- 20.3.8 CRYP stealing and data padding
- 20.3.9 CRYP suspend/resume operations
- 20.3.10 CRYP DES/TDES basic chaining modes (ECB, CBC)
- 20.3.11 CRYP AES basic chaining modes (ECB, CBC)
- 20.3.12 CRYP AES counter mode (AES-CTR)
- 20.3.13 CRYP AES Galois/counter mode (GCM)
- 20.3.14 CRYP AES Galois message authentication code (GMAC)
- 20.3.15 CRYP AES Counter with CBC-MAC (CCM)
- 20.3.16 CRYP data registers and data swapping
- 20.3.17 CRYP key registers
- 20.3.18 CRYP initialization vector registers
- 20.3.19 CRYP DMA interface
- 20.3.20 CRYP error management
- 20.4 CRYP interrupts
- 20.5 CRYP processing time
- 20.6 CRYP registers
- 20.6.1 CRYP control register (CRYP_CR)
- 20.6.2 CRYP status register (CRYP_SR)
- 20.6.3 CRYP data input register (CRYP_DIN)
- 20.6.4 CRYP data output register (CRYP_DOUT)
- 20.6.5 CRYP DMA control register (CRYP_DMACR)
- 20.6.6 CRYP interrupt mask set/clear register (CRYP_IMSCR)
- 20.6.7 CRYP raw interrupt status register (CRYP_RISR)
- 20.6.8 CRYP masked interrupt status register (CRYP_MISR)
- 20.6.9 CRYP key register 0L (CRYP_K0LR)
- 20.6.10 CRYP key register 0R (CRYP_K0RR)
- 20.6.11 CRYP key register 1L (CRYP_K1LR)
- 20.6.12 CRYP key register 1R (CRYP_K1RR)
- 20.6.13 CRYP key register 2L (CRYP_K2LR)
- 20.6.14 CRYP key register 2R (CRYP_K2RR)
- 20.6.15 CRYP key register 3L (CRYP_K3LR)
- 20.6.16 CRYP key register 3R (CRYP_K3RR)
- 20.6.17 CRYP initialization vector register 0L (CRYP_IV0LR)
- 20.6.18 CRYP initialization vector register 0R (CRYP_IV0RR)
- 20.6.19 CRYP initialization vector register 1L (CRYP_IV1LR)
- 20.6.20 CRYP initialization vector register 1R (CRYP_IV1RR)
- 20.6.21 CRYP register map
- 21 Hash processor (HASH)
- 21.1 Introduction
- 21.2 HASH main features
- 21.3 HASH functional description
- 21.4 HASH interrupts
- 21.5 HASH processing time
- 21.6 HASH registers
- 21.6.1 HASH control register (HASH_CR)
- 21.6.2 HASH data input register (HASH_DIN)
- 21.6.3 HASH start register (HASH_STR)
- 21.6.4 HASH digest registers (HASH_HR0..7)
- 21.6.5 HASH interrupt enable register (HASH_IMR)
- 21.6.6 HASH status register (HASH_SR)
- 21.6.7 HASH context swap registers (HASH_CSRx)
- 21.6.8 HASH register map
- 22 Advanced-control timers (TIM1/TIM8)
- 22.1 TIM1/TIM8 introduction
- 22.2 TIM1/TIM8 main features
- 22.3 TIM1/TIM8 functional description
- 22.3.1 Time-base unit
- 22.3.2 Counter modes
- Figure 152. Counter timing diagram, internal clock divided by 1
- Figure 153. Counter timing diagram, internal clock divided by 2
- Figure 154. Counter timing diagram, internal clock divided by 4
- Figure 155. Counter timing diagram, internal clock divided by N
- Figure 156. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 157. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 158. Counter timing diagram, internal clock divided by 1
- Figure 159. Counter timing diagram, internal clock divided by 2
- Figure 160. Counter timing diagram, internal clock divided by 4
- Figure 161. Counter timing diagram, internal clock divided by N
- Figure 162. Counter timing diagram, update event when repetition counter is not used
- Figure 163. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
- Figure 164. Counter timing diagram, internal clock divided by 2
- Figure 165. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 166. Counter timing diagram, internal clock divided by N
- Figure 167. Counter timing diagram, update event with ARPE=1 (counter underflow)
- Figure 168. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 22.3.3 Repetition counter
- 22.3.4 External trigger input
- 22.3.5 Clock selection
- 22.3.6 Capture/compare channels
- Figure 176. Capture/compare channel (example: channel 1 input stage)
- Figure 177. Capture/compare channel 1 main circuit
- Figure 178. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)
- Figure 179. Output stage of capture/compare channel (channel 4)
- Figure 180. Output stage of capture/compare channel (channel 5, idem ch. 6)
- 22.3.7 Input capture mode
- 22.3.8 PWM input mode
- 22.3.9 Forced output mode
- 22.3.10 Output compare mode
- 22.3.11 PWM mode
- 22.3.12 Asymmetric PWM mode
- 22.3.13 Combined PWM mode
- 22.3.14 Combined 3-phase PWM mode
- 22.3.15 Complementary outputs and dead-time insertion
- 22.3.16 Using the break function
- Figure 191. Break and Break2 circuitry overview
- Figure 192. Various output behavior in response to a break event on BRK (OSSI = 1)
- Table 143. Behavior of timer outputs versus BRK/BRK2 inputs
- Figure 193. PWM output state following BRK and BRK2 pins assertion (OSSI=1)
- Figure 194. PWM output state following BRK assertion (OSSI=0)
- 22.3.17 Clearing the OCxREF signal on an external event
- 22.3.18 6-step PWM generation
- 22.3.19 One-pulse mode
- 22.3.20 Retriggerable one pulse mode (OPM)
- 22.3.21 Encoder interface mode
- 22.3.22 UIF bit remapping
- 22.3.23 Timer input XOR function
- 22.3.24 Interfacing with Hall sensors
- 22.3.25 Timer synchronization
- 22.3.26 ADC synchronization
- 22.3.27 DMA burst mode
- 22.3.28 Debug mode
- 22.4 TIM1/TIM8 registers
- 22.4.1 TIM1/TIM8 control register 1 (TIMx_CR1)
- 22.4.2 TIM1/TIM8 control register 2 (TIMx_CR2)
- 22.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR)
- 22.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER)
- 22.4.5 TIM1/TIM8 status register (TIMx_SR)
- 22.4.6 TIM1/TIM8 event generation register (TIMx_EGR)
- 22.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1)
- 22.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2)
- 22.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER)
- 22.4.10 TIM1/TIM8 counter (TIMx_CNT)
- 22.4.11 TIM1/TIM8 prescaler (TIMx_PSC)
- 22.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR)
- 22.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR)
- 22.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1)
- 22.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2)
- 22.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3)
- 22.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4)
- 22.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR)
- 22.4.19 TIM1/TIM8 DMA control register (TIMx_DCR)
- 22.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR)
- 22.4.21 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3)
- 22.4.22 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5)
- 22.4.23 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6)
- 22.4.24 TIM1 register map
- 22.4.25 TIM8 register map
- 23 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
- 23.1 TIM2/TIM3/TIM4/TIM5 introduction
- 23.2 TIM2/TIM3/TIM4/TIM5 main features
- 23.3 TIM2/TIM3/TIM4/TIM5 functional description
- 23.3.1 Time-base unit
- 23.3.2 Counter modes
- Figure 210. Counter timing diagram, internal clock divided by 1
- Figure 211. Counter timing diagram, internal clock divided by 2
- Figure 212. Counter timing diagram, internal clock divided by 4
- Figure 213. Counter timing diagram, internal clock divided by N
- Figure 214. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 215. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 216. Counter timing diagram, internal clock divided by 1
- Figure 217. Counter timing diagram, internal clock divided by 2
- Figure 218. Counter timing diagram, internal clock divided by 4
- Figure 219. Counter timing diagram, internal clock divided by N
- Figure 220. Counter timing diagram, Update event when repetition counter is not used
- Figure 221. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 222. Counter timing diagram, internal clock divided by 2
- Figure 223. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 224. Counter timing diagram, internal clock divided by N
- Figure 225. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 226. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 23.3.3 Clock selection
- 23.3.4 Capture/compare channels
- 23.3.5 Input capture mode
- 23.3.6 PWM input mode
- 23.3.7 Forced output mode
- 23.3.8 Output compare mode
- 23.3.9 PWM mode
- 23.3.10 Asymmetric PWM mode
- 23.3.11 Combined PWM mode
- 23.3.12 Clearing the OCxREF signal on an external event
- 23.3.13 One-pulse mode
- 23.3.14 Retriggerable one pulse mode (OPM)
- 23.3.15 Encoder interface mode
- 23.3.16 UIF bit remapping
- 23.3.17 Timer input XOR function
- 23.3.18 Timers and external trigger synchronization
- 23.3.19 Timer synchronization
- 23.3.20 DMA burst mode
- 23.3.21 Debug mode
- 23.4 TIM2/TIM3/TIM4/TIM5 registers
- 23.4.1 TIMx control register 1 (TIMx_CR1)
- 23.4.2 TIMx control register 2 (TIMx_CR2)
- 23.4.3 TIMx slave mode control register (TIMx_SMCR)
- 23.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 23.4.5 TIMx status register (TIMx_SR)
- 23.4.6 TIMx event generation register (TIMx_EGR)
- 23.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 23.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 23.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 23.4.10 TIMx counter (TIMx_CNT)
- 23.4.11 TIMx prescaler (TIMx_PSC)
- 23.4.12 TIMx auto-reload register (TIMx_ARR)
- 23.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 23.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 23.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 23.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 23.4.17 TIMx DMA control register (TIMx_DCR)
- 23.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 23.4.19 TIM2 option register (TIM2_OR)
- 23.4.20 TIM5 option register (TIM5_OR)
- 23.4.21 TIMx register map
- 24 General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14)
- 24.1 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction
- 24.2 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 main features
- 24.3 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description
- 24.3.1 Time-base unit
- 24.3.2 Counter modes
- Figure 260. Counter timing diagram, internal clock divided by 1
- Figure 261. Counter timing diagram, internal clock divided by 2
- Figure 262. Counter timing diagram, internal clock divided by 4
- Figure 263. Counter timing diagram, internal clock divided by N
- Figure 264. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 265. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 24.3.3 Clock selection
- 24.3.4 Capture/compare channels
- 24.3.5 Input capture mode
- 24.3.6 PWM input mode (only for TIM9/TIM12)
- 24.3.7 Forced output mode
- 24.3.8 Output compare mode
- 24.3.9 PWM mode
- 24.3.10 Combined PWM mode (TIM9/TIM12 only)
- 24.3.11 One-pulse mode
- 24.3.12 Retriggerable one pulse mode (OPM) (TIM12 only)
- 24.3.13 UIF bit remapping
- 24.3.14 Timer input XOR function
- 24.3.15 TIM9/TIM12 external trigger synchronization
- 24.3.16 Slave mode – combined reset + trigger mode
- 24.3.17 Timer synchronization (TIM9/TIM12)
- 24.3.18 Debug mode
- 24.4 TIM9/TIM12 registers
- 24.4.1 TIM9/TIM12 control register 1 (TIMx_CR1)
- 24.4.2 TIM9/TIM12 slave mode control register (TIMx_SMCR)
- 24.4.3 TIM9/TIM12 Interrupt enable register (TIMx_DIER)
- 24.4.4 TIM9/TIM12 status register (TIMx_SR)
- 24.4.5 TIM9/TIM12 event generation register (TIMx_EGR)
- 24.4.6 TIM9/TIM12 capture/compare mode register 1 (TIMx_CCMR1)
- 24.4.7 TIM9/TIM12 capture/compare enable register (TIMx_CCER)
- 24.4.8 TIM9/TIM12 counter (TIMx_CNT)
- 24.4.9 TIM9/TIM12 prescaler (TIMx_PSC)
- 24.4.10 TIM9/TIM12 auto-reload register (TIMx_ARR)
- 24.4.11 TIM9/TIM12 capture/compare register 1 (TIMx_CCR1)
- 24.4.12 TIM9/TIM12 capture/compare register 2 (TIMx_CCR2)
- 24.4.13 TIM9/TIM12 register map
- 24.5 TIM10/TIM11/TIM13/TIM14 registers
- 24.5.1 TIM10/TIM11/TIM13/TIM14 control register 1 (TIMx_CR1)
- 24.5.2 TIM10/TIM11/TIM13/TIM14 Interrupt enable register (TIMx_DIER)
- 24.5.3 TIM10/TIM11/TIM13/TIM14 status register (TIMx_SR)
- 24.5.4 TIM10/TIM11/TIM13/TIM14 event generation register (TIMx_EGR)
- 24.5.5 TIM10/TIM11/TIM13/TIM14 capture/compare mode register 1 (TIMx_CCMR1)
- 24.5.6 TIM10/TIM11/TIM13/TIM14 capture/compare enable register (TIMx_CCER)
- 24.5.7 TIM10/TIM11/TIM13/TIM14 counter (TIMx_CNT)
- 24.5.8 TIM10/TIM11/TIM13/TIM14 prescaler (TIMx_PSC)
- 24.5.9 TIM10/TIM11/TIM13/TIM14 auto-reload register (TIMx_ARR)
- 24.5.10 TIM10/TIM11/TIM13/TIM14 capture/compare register 1 (TIMx_CCR1)
- 24.5.11 TIM11 option register 1 (TIM11_OR)
- 24.5.12 TIM10/TIM11/TIM13/TIM14 register map
- 25 Basic timers (TIM6/TIM7)
- 25.1 TIM6/TIM7 introduction
- 25.2 TIM6/TIM7 main features
- 25.3 TIM6/TIM7 functional description
- 25.3.1 Time-base unit
- 25.3.2 Counting mode
- Figure 285. Counter timing diagram, internal clock divided by 1
- Figure 286. Counter timing diagram, internal clock divided by 2
- Figure 287. Counter timing diagram, internal clock divided by 4
- Figure 288. Counter timing diagram, internal clock divided by N
- Figure 289. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
- Figure 290. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 25.3.3 UIF bit remapping
- 25.3.4 Clock source
- 25.3.5 Debug mode
- 25.4 TIM6/TIM7 registers
- 25.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
- 25.4.2 TIM6/TIM7 control register 2 (TIMx_CR2)
- 25.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 25.4.4 TIM6/TIM7 status register (TIMx_SR)
- 25.4.5 TIM6/TIM7 event generation register (TIMx_EGR)
- 25.4.6 TIM6/TIM7 counter (TIMx_CNT)
- 25.4.7 TIM6/TIM7 prescaler (TIMx_PSC)
- 25.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR)
- 25.4.9 TIM6/TIM7 register map
- 26 Low-power timer (LPTIM)
- 26.1 Introduction
- 26.2 LPTIM main features
- 26.3 LPTIM implementation
- 26.4 LPTIM functional description
- 26.5 LPTIM interrupts
- 26.6 LPTIM registers
- 26.6.1 LPTIM interrupt and status register (LPTIM_ISR)
- 26.6.2 LPTIM interrupt clear register (LPTIM_ICR)
- 26.6.3 LPTIM interrupt enable register (LPTIM_IER)
- 26.6.4 LPTIM configuration register (LPTIM_CFGR)
- 26.6.5 LPTIM control register (LPTIM_CR)
- 26.6.6 LPTIM compare register (LPTIM_CMP)
- 26.6.7 LPTIM autoreload register (LPTIM_ARR)
- 26.6.8 LPTIM counter register (LPTIM_CNT)
- 26.6.9 LPTIM register map
- 27 Independent watchdog (IWDG)
- 28 System window watchdog (WWDG)
- 29 Real-time clock (RTC)
- 29.1 Introduction
- 29.2 RTC main features
- 29.3 RTC functional description
- 29.3.1 RTC block diagram
- 29.3.2 GPIOs controlled by the RTC
- 29.3.3 Clock and prescalers
- 29.3.4 Real-time clock and calendar
- 29.3.5 Programmable alarms
- 29.3.6 Periodic auto-wakeup
- 29.3.7 RTC initialization and configuration
- 29.3.8 Reading the calendar
- 29.3.9 Resetting the RTC
- 29.3.10 RTC synchronization
- 29.3.11 RTC reference clock detection
- 29.3.12 RTC smooth digital calibration
- 29.3.13 Time-stamp function
- 29.3.14 Tamper detection
- 29.3.15 Calibration clock output
- 29.3.16 Alarm output
- 29.4 RTC low-power modes
- 29.5 RTC interrupts
- 29.6 RTC registers
- 29.6.1 RTC time register (RTC_TR)
- 29.6.2 RTC date register (RTC_DR)
- 29.6.3 RTC control register (RTC_CR)
- 29.6.4 RTC initialization and status register (RTC_ISR)
- 29.6.5 RTC prescaler register (RTC_PRER)
- 29.6.6 RTC wakeup timer register (RTC_WUTR)
- 29.6.7 RTC alarm A register (RTC_ALRMAR)
- 29.6.8 RTC alarm B register (RTC_ALRMBR)
- 29.6.9 RTC write protection register (RTC_WPR)
- 29.6.10 RTC sub second register (RTC_SSR)
- 29.6.11 RTC shift control register (RTC_SHIFTR)
- 29.6.12 RTC timestamp time register (RTC_TSTR)
- 29.6.13 RTC timestamp date register (RTC_TSDR)
- 29.6.14 RTC time-stamp sub second register (RTC_TSSSR)
- 29.6.15 RTC calibration register (RTC_CALR)
- 29.6.16 RTC tamper configuration register (RTC_TAMPCR)
- 29.6.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 29.6.18 RTC alarm B sub second register (RTC_ALRMBSSR)
- 29.6.19 RTC option register (RTC_OR)
- 29.6.20 RTC backup registers (RTC_BKPxR)
- 29.6.21 RTC register map
- 30 Inter-integrated circuit (I2C) interface
- 30.1 Introduction
- 30.2 I2C main features
- 30.3 I2C implementation
- 30.4 I2C functional description
- 30.4.1 I2C block diagram
- 30.4.2 I2C clock requirements
- 30.4.3 Mode selection
- 30.4.4 I2C initialization
- 30.4.5 Software reset
- 30.4.6 Data transfer
- 30.4.7 I2C slave mode
- Figure 309. Slave initialization flowchart
- Figure 310. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0
- Figure 311. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1
- Figure 312. Transfer bus diagrams for I2C slave transmitter
- Figure 313. Transfer sequence flowchart for slave receiver with NOSTRETCH=0
- Figure 314. Transfer sequence flowchart for slave receiver with NOSTRETCH=1
- Figure 315. Transfer bus diagrams for I2C slave receiver
- 30.4.8 I2C master mode
- Figure 316. Master clock generation
- Table 178. I2C-SMBUS specification clock timings
- Figure 317. Master initialization flowchart
- Figure 318. 10-bit address read access with HEAD10R=0
- Figure 319. 10-bit address read access with HEAD10R=1
- Figure 320. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes
- Figure 321. Transfer sequence flowchart for I2C master transmitter for N>255 bytes
- Figure 322. Transfer bus diagrams for I2C master transmitter
- Figure 323. Transfer sequence flowchart for I2C master receiver for N≤255 bytes
- Figure 324. Transfer sequence flowchart for I2C master receiver for N >255 bytes
- Figure 325. Transfer bus diagrams for I2C master receiver
- 30.4.9 I2C_TIMINGR register configuration examples
- 30.4.10 SMBus specific features
- 30.4.11 SMBus initialization
- 30.4.12 SMBus: I2C_TIMEOUTR register configuration examples
- 30.4.13 SMBus slave mode
- Figure 327. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC
- Figure 328. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
- Figure 329. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC
- Figure 330. Bus transfer diagrams for SMBus slave receiver (SBC=1)
- Figure 331. Bus transfer diagrams for SMBus master transmitter
- Figure 332. Bus transfer diagrams for SMBus master receiver
- 30.4.14 Error conditions
- 30.4.15 DMA requests
- 30.4.16 Debug mode
- 30.5 I2C low-power modes
- 30.6 I2C interrupts
- 30.7 I2C registers
- 30.7.1 Control register 1 (I2C_CR1)
- 30.7.2 Control register 2 (I2C_CR2)
- 30.7.3 Own address 1 register (I2C_OAR1)
- 30.7.4 Own address 2 register (I2C_OAR2)
- 30.7.5 Timing register (I2C_TIMINGR)
- 30.7.6 Timeout register (I2C_TIMEOUTR)
- 30.7.7 Interrupt and status register (I2C_ISR)
- 30.7.8 Interrupt clear register (I2C_ICR)
- 30.7.9 PEC register (I2C_PECR)
- 30.7.10 Receive data register (I2C_RXDR)
- 30.7.11 Transmit data register (I2C_TXDR)
- 30.7.12 I2C register map
- 31 Universal synchronous asynchronous receiver transmitter (USART)
- 31.1 Introduction
- 31.2 USART main features
- 31.3 USART extended features
- 31.4 USART implementation
- 31.5 USART functional description
- Figure 334. USART block diagram
- 31.5.1 USART character description
- 31.5.2 USART transmitter
- 31.5.3 USART receiver
- 31.5.4 USART baud rate generation
- 31.5.5 Tolerance of the USART receiver to clock deviation
- 31.5.6 USART auto baud rate detection
- 31.5.7 Multiprocessor communication using USART
- 31.5.8 Modbus communication using USART
- 31.5.9 USART parity control
- 31.5.10 USART LIN (local interconnection network) mode
- 31.5.11 USART synchronous mode
- 31.5.12 USART Single-wire Half-duplex communication
- 31.5.13 USART Smartcard mode
- 31.5.14 USART IrDA SIR ENDEC block
- 31.5.15 USART continuous communication in DMA mode
- 31.5.16 RS232 hardware flow control and RS485 driver enable using USART
- 31.6 USART low-power modes
- 31.7 USART interrupts
- 31.8 USART registers
- 31.8.1 Control register 1 (USART_CR1)
- 31.8.2 Control register 2 (USART_CR2)
- 31.8.3 Control register 3 (USART_CR3)
- 31.8.4 Baud rate register (USART_BRR)
- 31.8.5 Guard time and prescaler register (USART_GTPR)
- 31.8.6 Receiver timeout register (USART_RTOR)
- 31.8.7 Request register (USART_RQR)
- 31.8.8 Interrupt and status register (USART_ISR)
- 31.8.9 Interrupt flag clear register (USART_ICR)
- 31.8.10 Receive data register (USART_RDR)
- 31.8.11 Transmit data register (USART_TDR)
- 31.8.12 USART register map
- 32 Serial peripheral interface / inter-IC sound (SPI/I2S)
- 32.1 Introduction
- 32.2 SPI main features
- 32.3 I2S main features
- 32.4 SPI/I2S implementation
- 32.5 SPI functional description
- 32.5.1 General description
- 32.5.2 Communications between one master and one slave
- 32.5.3 Standard multi-slave communication
- 32.5.4 Multi-master communication
- 32.5.5 Slave select (NSS) pin management
- 32.5.6 Communication formats
- 32.5.7 Configuration of SPI
- 32.5.8 Procedure for enabling SPI
- 32.5.9 Data transmission and reception procedures
- 32.5.10 SPI status flags
- 32.5.11 SPI error flags
- 32.5.12 NSS pulse mode
- 32.5.13 TI mode
- 32.5.14 CRC calculation
- 32.6 SPI interrupts
- 32.7 I2S functional description
- 32.7.1 I2S general description
- 32.7.2 I2S full duplex
- 32.7.3 Supported audio protocols
- Figure 377. I2S Philips protocol waveforms (16/32-bit full accuracy)
- Figure 378. I2S Philips standard waveforms (24-bit frame)
- Figure 379. Transmitting 0x8EAA33
- Figure 380. Receiving 0x8EAA33
- Figure 381. I2S Philips standard (16-bit extended to 32-bit packet frame)
- Figure 382. Example of 16-bit data frame extended to 32-bit channel frame
- Figure 383. MSB Justified 16-bit or 32-bit full-accuracy length
- Figure 384. MSB justified 24-bit frame length
- Figure 385. MSB justified 16-bit extended to 32-bit packet frame
- Figure 386. LSB justified 16-bit or 32-bit full-accuracy
- Figure 387. LSB justified 24-bit frame length
- Figure 388. Operations required to transmit 0x3478AE
- Figure 389. Operations required to receive 0x3478AE
- Figure 390. LSB justified 16-bit extended to 32-bit packet frame
- Figure 391. Example of 16-bit data frame extended to 32-bit channel frame
- Figure 392. PCM standard waveforms (16-bit)
- Figure 393. PCM standard waveforms (16-bit extended to 32-bit packet frame)
- 32.7.4 Start-up description
- 32.7.5 Clock generator
- 32.7.6 I2S master mode
- 32.7.7 I2S slave mode
- 32.7.8 I2S status flags
- 32.7.9 I2S error flags
- 32.7.10 DMA features
- 32.8 I2S interrupts
- 32.9 SPI and I2S registers
- 32.9.1 SPI control register 1 (SPIx_CR1)
- 32.9.2 SPI control register 2 (SPIx_CR2)
- 32.9.3 SPI status register (SPIx_SR)
- 32.9.4 SPI data register (SPIx_DR)
- 32.9.5 SPI CRC polynomial register (SPIx_CRCPR)
- 32.9.6 SPI Rx CRC register (SPIx_RXCRCR)
- 32.9.7 SPI Tx CRC register (SPIx_TXCRCR)
- 32.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR)
- 32.9.9 SPIx_I2S prescaler register (SPIx_I2SPR)
- 32.9.10 SPI/I2S register map
- 33 Serial audio interface (SAI)
- 33.1 Introduction
- 33.2 SAI main features
- 33.3 SAI functional description
- 33.3.1 SAI block diagram
- 33.3.2 SAI pins and internal signals
- 33.3.3 Main SAI modes
- 33.3.4 SAI synchronization mode
- 33.3.5 Audio data size
- 33.3.6 Frame synchronization
- 33.3.7 Slot configuration
- 33.3.8 SAI clock generator
- 33.3.9 Internal FIFOs
- 33.3.10 AC’97 link controller
- 33.3.11 SPDIF output
- 33.3.12 Specific features
- 33.3.13 Error flags
- 33.3.14 Disabling the SAI
- 33.3.15 SAI DMA interface
- 33.4 SAI interrupts
- 33.5 SAI registers
- 33.5.1 Global configuration register (SAI_GCR)
- 33.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1)
- 33.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2)
- 33.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR)
- 33.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR)
- 33.5.6 Interrupt mask register 2 (SAI_AIM / SAI_BIM)
- 33.5.7 Status register (SAI_ASR / SAI_BSR)
- 33.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR)
- 33.5.9 Data register (SAI_ADR / SAI_BDR)
- 33.5.10 SAI register map
- 34 SPDIF receiver interface (SPDIFRX)
- 34.1 SPDIFRX interface introduction
- 34.2 SPDIFRX main features
- 34.3 SPDIFRX functional description
- Figure 413. SPDIFRX block diagram
- 34.3.1 S/PDIF protocol (IEC-60958)
- 34.3.2 SPDIFRX decoder (SPDIFRX_DC)
- 34.3.3 SPDIFRX tolerance to clock deviation
- 34.3.4 SPDIFRX synchronization
- 34.3.5 SPDIFRX handling
- 34.3.6 Data reception management
- 34.3.7 Dedicated control flow
- 34.3.8 Reception errors
- 34.3.9 Clocking strategy
- 34.3.10 DMA Interface
- 34.3.11 Interrupt Generation
- 34.3.12 Register protection
- 34.4 Programming procedures
- 34.5 SPDIFRX interface registers
- 34.5.1 Control register (SPDIFRX_CR)
- 34.5.2 Interrupt mask register (SPDIFRX_IMR)
- 34.5.3 Status register (SPDIFRX_SR)
- 34.5.4 Interrupt flag clear register (SPDIFRX_IFCR)
- 34.5.5 Data input register (SPDIFRX_DR)
- 34.5.6 Data input register (SPDIFRX_FMT1_DR)
- 34.5.7 Data input register (SPDIFRX_FMT2_DR)
- 34.5.8 Channel status register (SPDIFRX_CSR)
- 34.5.9 Debug information register (SPDIFRX_DIR)
- 34.5.10 SPDIFRX interface register map
- 35 SD/SDIO/MMC card host interface (SDMMC)
- 35.1 SDMMC main features
- 35.2 SDMMC bus topology
- 35.3 SDMMC functional description
- Figure 434. SDMMC block diagram
- Table 218. SDMMC I/O definitions
- 35.3.1 SDMMC adapter
- Figure 435. SDMMC adapter
- Figure 436. Control unit
- Figure 437. SDMMC_CK clock dephasing (BYPASS = 0)
- Figure 438. SDMMC adapter command path
- Figure 439. Command path state machine (SDMMC)
- Figure 440. SDMMC command transfer
- Table 219. Command format
- Table 220. Short response format
- Table 221. Long response format
- Table 222. Command path status flags
- Figure 441. Data path
- Figure 442. Data path state machine (DPSM)
- Table 223. Data token format
- Table 224. DPSM flags
- Table 225. Transmit FIFO status flags
- Table 226. Receive FIFO status flags
- 35.3.2 SDMMC APB2 interface
- 35.4 Card functional description
- 35.4.1 Card identification mode
- 35.4.2 Card reset
- 35.4.3 Operating voltage range validation
- 35.4.4 Card identification process
- 35.4.5 Block write
- 35.4.6 Block read
- 35.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 35.4.8 Erase: group erase and sector erase
- 35.4.9 Wide bus selection or deselection
- 35.4.10 Protection management
- 35.4.11 Card status register
- 35.4.12 SD status register
- 35.4.13 SD I/O mode
- 35.4.14 Commands and responses
- 35.5 Response formats
- 35.6 SDIO I/O card-specific operations
- 35.7 HW flow control
- 35.8 SDMMC registers
- 35.8.1 SDMMC power control register (SDMMC_POWER)
- 35.8.2 SDMMC clock control register (SDMMC_CLKCR)
- 35.8.3 SDMMC argument register (SDMMC_ARG)
- 35.8.4 SDMMC command register (SDMMC_CMD)
- 35.8.5 SDMMC command response register (SDMMC_RESPCMD)
- 35.8.6 SDMMC response 1..4 register (SDMMC_RESPx)
- 35.8.7 SDMMC data timer register (SDMMC_DTIMER)
- 35.8.8 SDMMC data length register (SDMMC_DLEN)
- 35.8.9 SDMMC data control register (SDMMC_DCTRL)
- 35.8.10 SDMMC data counter register (SDMMC_DCOUNT)
- 35.8.11 SDMMC status register (SDMMC_STA)
- 35.8.12 SDMMC interrupt clear register (SDMMC_ICR)
- 35.8.13 SDMMC mask register (SDMMC_MASK)
- 35.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT)
- 35.8.15 SDMMC data FIFO register (SDMMC_FIFO)
- 35.8.16 SDMMC register map
- 36 Controller area network (bxCAN)
- 36.1 Introduction
- 36.2 bxCAN main features
- 36.3 bxCAN general description
- 36.4 bxCAN operating modes
- 36.5 Test mode
- 36.6 Behavior in debug mode
- 36.7 bxCAN functional description
- 36.8 bxCAN interrupts
- 36.9 CAN registers
- 37 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
- 37.1 Introduction
- 37.2 OTG main features
- 37.3 OTG implementation
- 37.4 OTG functional description
- 37.5 OTG dual role device (DRD)
- 37.6 USB peripheral
- 37.7 USB host
- 37.8 SOF trigger
- 37.9 OTG low-power modes
- 37.10 Dynamic update of the OTG_HFIR register
- 37.11 USB data FIFOs
- 37.12 OTG_FS system performance
- 37.13 OTG_FS/OTG_HS interrupts
- 37.14 OTG_FS/OTG_HS control and status registers
- 37.15 OTG_FS/OTG_HS registers
- 37.15.1 OTG control and status register (OTG_GOTGCTL)
- 37.15.2 OTG interrupt register (OTG_GOTGINT)
- 37.15.3 OTG AHB configuration register (OTG_GAHBCFG)
- 37.15.4 OTG USB configuration register (OTG_GUSBCFG)
- 37.15.5 OTG reset register (OTG_GRSTCTL)
- 37.15.6 OTG core interrupt register (OTG_GINTSTS)
- 37.15.7 OTG interrupt mask register (OTG_GINTMSK)
- 37.15.8 OTG receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP)
- 37.15.9 OTG receive FIFO size register (OTG_GRXFSIZ)
- 37.15.10 OTG host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0)
- 37.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS)
- 37.15.12 OTG general core configuration register (OTG_GCCFG)
- 37.15.13 OTG core ID register (OTG_CID)
- 37.15.14 OTG core LPM configuration register (OTG_GLPMCFG)
- 37.15.15 OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ)
- 37.15.16 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the FIFO number)
- 37.15.17 Host-mode registers
- 37.15.18 OTG host configuration register (OTG_HCFG)
- 37.15.19 OTG host frame interval register (OTG_HFIR)
- 37.15.20 OTG host frame number/frame time remaining register (OTG_HFNUM)
- 37.15.21 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS)
- 37.15.22 OTG host all channels interrupt register (OTG_HAINT)
- 37.15.23 OTG host all channels interrupt mask register (OTG_HAINTMSK)
- 37.15.24 OTG host port control and status register (OTG_HPRT)
- 37.15.25 OTG host channel x characteristics register (OTG_HCCHARx) (x = 0..15[HS] / 11[FS], where x = Channel number)
- 37.15.26 OTG host channel x split control register (OTG_HCSPLTx) (x = 0..15, where x = Channel number)
- 37.15.27 OTG host channel x interrupt register (OTG_HCINTx) (x = 0..15[HS] / 11[FS], where x = Channel number)
- 37.15.28 OTG host channel x interrupt mask register (OTG_HCINTMSKx) (x = 0..15[HS] / 11[FS], where x = Channel number)
- 37.15.29 OTG host channel x transfer size register (OTG_HCTSIZx) (x = 0..15[HS] / 11[FS], where x = Channel number)
- 37.15.30 OTG host channel x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel number)
- 37.15.31 Device-mode registers
- 37.15.32 OTG device configuration register (OTG_DCFG)
- 37.15.33 OTG device control register (OTG_DCTL)
- 37.15.34 OTG device status register (OTG_DSTS)
- 37.15.35 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)
- 37.15.36 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK)
- 37.15.37 OTG device all endpoints interrupt register (OTG_DAINT)
- 37.15.38 OTG all endpoints interrupt mask register (OTG_DAINTMSK)
- 37.15.39 OTG device VBUS discharge time register (OTG_DVBUSDIS)
- 37.15.40 OTG device VBUS pulsing time register (OTG_DVBUSPULSE)
- 37.15.41 OTG device threshold control register (OTG_DTHRCTL)
- 37.15.42 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK)
- 37.15.43 OTG device each endpoint interrupt register (OTG_DEACHINT)
- 37.15.44 OTG device each endpoint interrupt mask register (OTG_DEACHINTMSK)
- 37.15.45 OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1)
- 37.15.46 OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1)
- 37.15.47 OTG device control IN endpoint 0 control register (OTG_DIEPCTL0)
- 37.15.48 OTG device IN endpoint x control register (OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = endpoint number)
- 37.15.49 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number)
- 37.15.50 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0)
- 37.15.51 OTG device IN endpoint x DMA address register (OTG_DIEPDMAx) (x = 0..8, where x = endpoint number)
- 37.15.52 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = endpoint number)
- 37.15.53 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) (x = 1..5[FS] /8[HS], where x = endpoint number)
- 37.15.54 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0)
- 37.15.55 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number)
- 37.15.56 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0)
- 37.15.57 OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) (x = 0..8, where x = endpoint number)
- 37.15.58 OTG device OUT endpoint x control register (OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint number)
- 37.15.59 OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint number)
- 37.15.60 OTG power and clock gating control register (OTG_PCGCCTL)
- 37.15.61 OTG_FS/OTG_HS register map
- 37.16 OTG_FS/OTG_HS programming model
- 37.16.1 Core initialization
- 37.16.2 Host initialization
- 37.16.3 Device initialization
- 37.16.4 DMA mode
- 37.16.5 Host programming model
- Figure 469. Transmit FIFO write task
- Figure 470. Receive FIFO read task
- Figure 471. Normal bulk/control OUT/SETUP
- Figure 472. Bulk/control IN transactions
- Figure 473. Normal interrupt OUT
- Figure 474. Normal interrupt IN
- Figure 475. Isochronous OUT transactions
- Figure 476. Isochronous IN transactions
- Figure 477. Normal bulk/control OUT/SETUP transactions - DMA
- Figure 478. Normal bulk/control IN transaction - DMA
- Figure 479. Normal interrupt OUT transactions - DMA mode
- Figure 480. Normal interrupt IN transactions - DMA mode
- Figure 481. Normal isochronous OUT transaction - DMA mode
- Figure 482. Normal isochronous IN transactions - DMA mode
- 37.16.6 Device programming model
- 37.16.7 Worst case response time
- 37.16.8 OTG programming model
- 38 Ethernet (ETH): media access control (MAC) with DMA controller
- 38.1 Ethernet introduction
- 38.2 Ethernet main features
- 38.3 Ethernet pins
- 38.4 Ethernet functional description: SMI, MII and RMII
- 38.5 Ethernet functional description: MAC 802.3
- 38.6 Ethernet functional description: DMA controller operation
- Figure 517. Descriptor ring and chain structure
- 38.6.1 Initialization of a transfer using DMA
- 38.6.2 Host bus burst access
- 38.6.3 Host data buffer alignment
- 38.6.4 Buffer size calculations
- 38.6.5 DMA arbiter
- 38.6.6 Error response to DMA
- 38.6.7 Tx DMA configuration
- 38.6.8 Rx DMA configuration
- 38.6.9 DMA interrupts
- 38.7 Ethernet interrupts
- 38.8 Ethernet register descriptions
- 39 HDMI-CEC controller (HDMI-CEC)
- 39.1 Introduction
- 39.2 HDMI-CEC controller main features
- 39.3 HDMI-CEC functional description
- 39.4 Arbitration
- 39.5 Error handling
- 39.6 HDMI-CEC interrupts
- 39.7 HDMI-CEC registers
- 40 Debug support (DBG)
- 40.1 Overview
- 40.2 Reference Arm® documentation
- 40.3 SWJ debug port (serial wire and JTAG)
- 40.4 Pinout and debug port pins
- 40.5 STM32F75xxx and STM32F74xxx JTAG Debug Port connection
- 40.6 ID codes and locking mechanism
- 40.7 JTAG debug port
- 40.8 SW debug port
- 40.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 40.10 Core debug
- 40.11 Capability of the debugger host to connect under system reset
- 40.12 FPB (Flash patch breakpoint)
- 40.13 DWT (data watchpoint trigger)
- 40.14 ITM (instrumentation trace macrocell)
- 40.15 ETM (Embedded trace macrocell)
- 40.16 MCU debug component (DBGMCU)
- 40.17 Pelican TPIU (trace port interface unit)
- 40.17.1 Introduction
- 40.17.2 TRACE pin assignment
- 40.17.3 TPIU formatter
- 40.17.4 TPIU frame synchronization packets
- 40.17.5 Transmission of the synchronization frame packet
- 40.17.6 Synchronous mode
- 40.17.7 Asynchronous mode
- 40.17.8 TRACECLKIN connection inside the STM32F75xxx and STM32F74xxx
- 40.17.9 TPIU registers
- 40.17.10 Example of configuration
- 40.18 DBG register map
- 41 Device electronic signature
- 42 Revision history