STM8S Series And STM8AF 8 Bit Microcontrollers STM8 Reference Manual

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1 Central processing unit (CPU)
- 1.1 CPU introduction
- 1.2 CPU registers
  - 1.2.1 Description of CPU registers
  - 1.2.2 STM8 CPU register map
    - Table 2. CPU register map
- 1.3 Global configuration register (CFG_GCR)
2 Boot ROM
3 Memory and register map
- 3.1 Memory layout
  - 3.1.1 Memory map
    - Figure 3. Memory map
  - 3.1.2 Stack handling
    - Figure 4. Default stack model
    - Figure 5. Customized stack model
- 3.2 Register description abbreviations
  - Table 4. List of abbreviations
4 Flash program memory and data EEPROM
- 4.1 Flash and EEPROM introduction
- 4.2 Flash and EEPROM glossary
- 4.3 Main Flash memory features
- 4.4 Memory organization
- 4.5 Memory protection
- 4.6 Memory programming
- 4.7 ICP (in-circuit programming) and IAP (in-application programming)
  - Table 6. Memory access versus programming method
- 4.8 Flash registers
5 Single wire interface module (SWIM) and debug module (DM)
- 5.1 SWIM and DM introduction
- 5.2 SWIM main features
  - Figure 12. SWIM pin connection
- 5.3 SWIM modes
6 Interrupt controller (ITC)
- 6.1 ITC introduction
- 6.2 Interrupt masking and processing flow
- 6.3 Interrupts and low power modes
- 6.4 Activation level/low power mode control
- 6.5 Concurrent and nested interrupt management
  - 6.5.1 Concurrent interrupt management mode
    - Figure 15. Concurrent interrupt management
  - 6.5.2 Nested interrupt management mode
    - Table 10. Vector address map versus software priority bits
    - Figure 16. Nested interrupt management
- 6.6 External interrupts
- 6.7 Interrupt instructions
  - Table 11. Dedicated interrupt instruction set (continued)
- 6.8 Interrupt mapping
- 6.9 ITC and EXTI registers
7 Power supply
- Figure 17. Power supply overview
8 Reset (RST)
- Figure 18. Reset circuit
- 8.1 “Reset state” and “under reset” definitions
- 8.2 Reset circuit description
- 8.3 Internal reset sources
- 8.4 RST register description
  - 8.4.1 Reset status register (RST_SR)
- 8.5 RST register map
  - Table 13. RST register map
9 Clock control (CLK)
- Figure 20. Clock tree
- 9.1 Master clock sources
- 9.2 Master clock switching
  - 9.2.1 System startup
  - 9.2.2 Master clock switching procedures
    - Figure 22. Clock switching flowchart (automatic mode example)
    - Figure 23. Clock switching flowchart (manual mode example)
- 9.3 Low-speed clock selection
- 9.4 CPU clock-divider
- 9.5 Peripheral clock-gating (PCG)
- 9.6 Clock security system (CSS)
- 9.7 Clock-out capability (CCO)
- 9.8 CLK interrupts
  - Table 16. CLK interrupt requests
- 9.9 CLK register description
- 9.10 CLK register map and reset values
  - Table 19. CLK register map and reset values
10 Power management
- 10.1 General considerations
  - 10.1.1 Clock management for low consumption
- 10.2 Low power modes
- 10.3 Additional analog power controls
  - 10.3.1 Fast Flash wakeup from Halt mode
  - 10.3.2 Very low Flash consumption in Active-halt mode
11 General purpose I/O ports (GPIO)
- 11.1 Introduction
- 11.2 GPIO main features
  - Figure 24. GPIO block diagram
- 11.3 Port configuration and usage
- 11.4 Reset configuration
- 11.5 Unused I/O pins
- 11.6 Low power modes
  - Table 22. Effect of low power modes on GPIO ports
- 11.7 Input mode details
- 11.8 Output mode details
  - 11.8.1 Alternate function output
  - 11.8.2 Slope control
- 11.9 GPIO registers
12 Auto-wakeup (AWU)
- 12.1 AWU introduction
- 12.2 LSI clock measurement
  - Figure 25. AWU block diagram
- 12.3 AWU functional description
- 12.4 AWU registers
13 Beeper (BEEP)
- 13.1 Beeper introduction
  - Figure 26. Beep block diagram
- 13.2 Beeper functional description
  - 13.2.1 Beeper operation
  - 13.2.2 Beeper calibration
- 13.3 Beeper registers
  - 13.3.1 Beeper control/status register (BEEP_CSR)
  - 13.3.2 Beeper register map and reset values
    - Table 27. Beeper register map
14 Independent watchdog (IWDG)
- 14.1 IWDG introduction
- 14.2 IWDG functional description
  - Figure 27. Independent watchdog (IWDG) block diagram
  - Table 28. Watchdog timeout period (LSI clock frequency = 128 kHz)
- 14.3 IWDG registers
15 Window watchdog (WWDG)
- 15.1 WWDG introduction
- 15.2 WWDG main features
- 15.3 WWDG functional description
  - Figure 28. Watchdog block diagram
- 15.4 How to program the watchdog timeout
- 15.5 WWDG low power modes
  - Table 31. Effect of low power modes on WWDG
- 15.6 Hardware watchdog option
- 15.7 Using Halt mode with the WWDG (WWDGHALT option)
- 15.8 WWDG interrupts
- 15.9 WWDG registers
  - 15.9.1 Control register (WWDG_CR)
  - 15.9.2 Window register (WWDG_WR)
- 15.10 Window watchdog register map and reset values
  - Table 32. WWDG register map and reset values
16 Timer overview
- Table 33. Timer characteristics
- 16.1 Timer feature comparison
  - Table 34. Timer feature comparison
- 16.2 Glossary of timer signal names
  - Table 35. Glossary of internal timer signals (continued)
  - Table 36. Explanation of indices‘i’, ‘n’, and ‘x’
17 16-bit advanced control timer (TIM1)
- 17.1 TIM1 introduction
- 17.2 TIM1 main features
  - Figure 31. TIM1 general block diagram
- 17.3 TIM1 time base unit
- 17.4 TIM1 clock/trigger controller
- 17.5 TIM1 capture/compare channels
- 17.6 TIM1 interrupts
- 17.7 TIM1 registers
18 16-bit general purpose timers (TIM2, TIM3, TIM5)
- 18.1 TIM2, TIM3 and TIM5 introduction
- 18.2 TIM2/TIM3 main features
- 18.3 TIM5 main features
- 18.4 TIM2/TIM3/TIM5 functional description
- 18.5 TIM2/TIM3/TIM5 interrupts
- 18.6 TIM2/TIM3/TIM5 registers
19 8-bit basic timer (TIM4, TIM6)
- 19.1 TIM4, TIM6 introduction
  - Figure 89. TIM4 block diagram
  - Figure 90. TIM6 block diagram
- 19.2 TIM4 main features
- 19.3 TIM6 main features
- 19.4 TIM4/TIM6 interrupts
- 19.5 TIM4/TIM6 clock selection
- 19.6 TIM4/TIM6 registers
20 Serial peripheral interface (SPI)
- 20.1 SPI introduction
- 20.2 SPI main features
- 20.3 SPI functional description
- 20.4 SPI registers
- 20.5 SPI register map and reset values
  - Table 47. SPI register map and reset values
21 Inter-integrated circuit (I2C) interface
- 21.1 I2C introduction
- 21.2 I2C main features
- 21.3 I2C general description
  - Figure 100. I2Cbus protocol
  - Figure 101. I2C block diagram
- 21.4 I2C functional description
- 21.5 I2C low power modes
  - Table 48. I2C interface behavior in low power modes
- 21.6 I2C interrupts
  - Table 49. I2C Interrupt requests
  - Figure 109. I2C interrupt mapping diagram
- 21.7 I2C registers
22 Universal asynchronous receiver transmitter (UART)
- 22.1 Introduction
  - Table 52. UART configurations
- 22.2 UART main features
- 22.3 UART functional description
- 22.4 LIN mode functional description
- 22.5 UART low power modes
  - Table 59. UART interface behavior in low power modes
- 22.6 UART interrupts
  - Table 60. UART interrupt requests
  - Figure 139. UART interrupt mapping diagram
- 22.7 UART registers
23 Controller area network (beCAN)
- 23.1 Introduction
- 23.2 beCAN main features
- 23.3 beCAN general description
- 23.4 Operating modes
- 23.5 Test modes
- 23.6 Functional description
- 23.7 Interrupts
  - Figure 156. Event flags and interrupt generation
- 23.8 Register access protection
- 23.9 Clock system
- 23.10 beCAN low power modes
  - Table 68. beCAN behavior in low power modes
- 23.11 beCAN registers
- 23.12 CAN register map
  - Figure 157. CAN register mapping
  - 23.12.1 Page mapping for CAN
24 Analog/digital converter (ADC)
- 24.1 Introduction
- 24.2 ADC main features
- 24.3 ADC extended features
  - Figure 159. ADC1 block diagram
  - Figure 160. ADC2 block diagram
- 24.4 ADC pins
  - Table 72. ADC pins
- 24.5 ADC functional description
- 24.6 ADC low power modes
  - Table 73. Low power modes
- 24.7 ADC interrupts
- 24.8 Data alignment
  - Figure 164. Right alignment of data
  - Figure 165. Left alignment of data
- 24.9 Reading the conversion result
- 24.10 Schmitt trigger disable registers
- 24.11 ADC registers
- 24.12 ADC register map and reset values
  - Table 77. ADC1 register map and reset values (continued)
  - Table 78. ADC2 register map and reset values
25 Revision history
- Table 79. Document revision history

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