Saturn_V_LVDC_Vol2_Jan65 Saturn V LVDC Vol2 Jan65

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ASA-CB-12^280)

LAUNCH VEHICLE

i- %>w M « v «»*w » ™, _
~_ _
Laboratory
JUd
vu La t-v/«. | Maintenance
.»i»-...^.-...,„

Instructions.
(International Business Machines Corp.)
JJi'-LR

VOLUME II OF II

Laboratory Maintenance Instructions

SATURN V
LAUNCH VEHICLE DIGITAL COMPUTER
Simplex Models
NASA Part No. 50M35010
IBM Part No. 6109030

W

~L°fl'h IDT

(International Business Machines CorpOTOfthgV1rHU.:' r^az
'
^ °O» ^

Contract MAS 8-11561
LATEST CHANGED PAGES SUPERSEDE
THE SAME PAGES OF PREVIOUS DATE
Insert changed pages into basic
publication. Destroy superseded pages.

VOLUME II

MAINTENANCE DATA

30 NOVEMBER 1964
CHANGED 4 JANUARY 1965

INSERT LATEST CHANGED PAGES. DESTROY SUPERSEDED PAGES.

LIST OF EFFECTIVE PAGES
TOTAL NUMBER OF PAGES IN VOLUME H IS 230 CONSISTING OF THE FOLLOWING:
Page No.

Issue

*Title
4 Jan 65
*A . .
. 4 Jan 65
*i
4 Jan 65
ii Blank
Original
*iii
4 Jan 65
iv thru v
Original
vi Blank
Original
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4 Jan 65
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4 Jan 65
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4 Jan 65
4-5
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4 Jan 65
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4 Jan 65
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10-159
4 Jan 65
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4 Jan 65
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Page No.
10-176 thru
10-180 . . .
*10-181 thru
10-184 . . .
10-185
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10-190 . . .
*10-191
10-192

Issue
Original
4 Jan 65
Original
4 Jan 65

Original
4 Jan 65
Original

;

*The asterisk indicates pages changed, added, or deleted by the current change.

A

Changed 4 January 1965

MAY 9
*

)

\1966

VOLUME II OF II

L a b o r a t o r y Maintenance Instructions

SATURN V
LAUNCH VEHICLE DIGITAL COMPUTER
S i m p l e x Models
N A S A P a r t No. 50M35010'

r

.-,&- -

IBM Part No. 6109030
f

S^

'•

^^
\

--

'-K

'

- ' .*

J

•-

i • '•'~ •

:',

i *

"l;.*r"
(International Business Machines Corporation]
C o n t r a c t MAS 8-11561

VOLUME II

MAINTENANCE D A T A

30 NOVEMBER 1964

Technical Library, Bellcomm, !ncs

•r
INSERT LATEST CHANGED PAGES. DESTROY SUPERSEDED PAGES.

LIST OF EFFECTIVE PAGES

NOTE: The portion of the text affected by the changes is indicated
by 3 vertical line in the outer margins of the page.

TOTAL NUMBER OF PAGES IN VOLUME H IS 228 CONSISTING OF THE FOLLOWING:
Page No.

Issue

Title
Original
A
Original
i
Original
ii Blank
Original
iii thru v
Original
vi Blank,
Original
3-1 thru 3-12
Original
4-1 thru 4-5
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4-6 Blank .
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5-6 Blank .
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9-1 thru 9-7 . ... .Original
9-8 Blank
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10-1 thru 10-192 . .Original

^Thc ;istcri.sk indicates pai;es chunked, added, or deleted bv the current clunije

Volume II

TABLE OF CONTENTS
Section
m

IV

Title
INTERFACE AND ADJUSTMENTS. . , . ... . . . . . . . . . . . .

3-1

3-1.
3-3.

3-1
3-1

Interface
Adjustments

.
.

TEST EQUIPMENT AND SPECIAL TOOLS . . . . . . . . . . . . .

4-1.
4-2.
4-4.
4-6.
V

Page

4-1

Test Equipment . . .
4-1
Standard Test Equipment. . . . . . . . . . . . . . . . . . . . 4-1
Special Test Equipment.
4-1
Special Tools. . . . . . . .
f 4-1

PREPARATION FOR USE, STORAGE AND S H I P M E N T . . . . .

5-1

5-1.
5-2A.
5-3.
5-5.
5-7

5-1
5-4
5-4
5-5
5-7

Preparation for Use
Inspection and Test . . . . . . '.'. . . . . .".' . . . . . . . . .
Preparation for Storage . .
'.'....'
Preparation for Shipment. . . . . . . . . . . . . . . . . . .. .
General Computer Handling . . . . . . . . . . .

Vl"

PREVENTIVE MAINTENANCE. . . . . . . . . . . . . . . . . . . . .

6-1

VH

CHECKOUT

7-1

7-1.

7-1

Operating Test Procedures

VEQ

TROUBLE ISOLATION

8-1

IX

REPAIR

9-1

9-1.

9-1

X

Repair

DIAGRAMS

10-1.
10-3.

Diagrams
Signal Tracing

Changed 4 January 1965

10-1

10-1
10-2

i/ii

Volume

LIST OF ILLUSTRATIONS

Title

Page

3-1
3-2
3-3
3-4
3-5

Computer Connectors By Signal Function^. . ... . . . . . . . . .
Computer Interface Signals (8 Sheets) . . . . . . . ... . . . . . .
Computer — Data Adapter Interconnection Block Diagram.. .
Computer and LVDC-ME Interconnection Block Diagram . . .
Computer - ATOM Interconnection Block Diagram . . . . . . . .

, 3-1
3-2
3-10
3-11
3-12

4-1
4-2
4-3
4-4
4-5

Standard Test Equipment Table. . . . . . . ... . . ... . . . .'..- . .
Special Test Equipment Table. . . . . . . . . . . . . ;..;.'•. . . . . .
Special Test Equipment. .
• ... ... . . . . . . . . . . . . .
Special Tools Table . . .
........
Special Tools
. . . . . . . . . . . . . . . . . . . . . . . . "."

5-1
5-2
5-3
5-4

Reuseable Shipping Container. . . . . . .... . . . . . . . . . . . . . . 5-^2
Removing Roll Chart from Shock Recorder . . . . . ,'. . . . . . . 5-2
Installing Roll Chart in Shock Recorder . . . . ; . . . . . . . . . . 5-3
Computer Lift Handle, Mounted
5-8

9-1
9-2
9-3
9-4

Laboratory Replaceable Assemblies ... . . . . . . . . . . . . . .
Computer, Partially Disassembled
Page Assembly Location Guide.
Memory Handle Secured to Memory Assembly. . . . . . . . . . .

10-1
10-2

Clock Drivers, Logic Diagram (4 Sheets)
10-4
Decoupling Capacitors (Channel 1), Logic Diagram
(4 Sheets)
.
10-8
Delay Lines, Logic Diagram (2 Sheets)
10-12
Multiply-Divide Element, Logic Diagram (12 Sheets)
10-14
Add-Subtract Element, Logic Diagram (4 Sheets). . . . . . . . . 10-26
Transfer Register Bits 10 — TRS and Control,
Logic Diagram (2 Sheets)
10-30
Memory Buffer Control and Parity Counter,
Logic Diagram (2 Sheets).
10-32
Operation Code Register, Logic Diagram (4 Sheets). . . . . . . 10-34
Timing Gate Generator, Logic Diagram (2 Sheets). . . . •.'.. . . 10-38
Phase Generator, Logic Diagram (2 Sheets) . . . . . . . . . . . . 10-40
Memory Module Registers, Logic Diagram (2 Sheets)
10-42
HOP Constant Serializer and Memory Read Latches,
Logic Diagram (2 Sheets). .
10-44
Memory Timing, Logic Diagram (4 Sheets). . . .
10-46
Memory Error Detector, Logic Diagram (8 Sheets) . . . . . . . 10-50
Transfer Register Bits'1 - 9, Logic Diagram (4 Sheets) . . ... 10-58
Address Register and Memory Address Decoder,
Logic Diagram (4 Sheets)
10-62
Memory Sector Registers, Logic Diagram (2 Sheets)
10-66
Hi-Y Memory Address Decoder, Logic Diagram
(2 Sheets)
10-68

Figure

10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18

Changed 4 January 1965

4-1
4-2
4-3
4-4
4-5

9-1
9-2
9-3
9-6

iii

Volume II

LIST OF ILLUSTRATIONS (Cont)
Figure

Title

Decoupling Capacitors (Channel 4), Logic Diagram
(4 Sheets)
10-20
Operation Code Voters, Logic Diagram (4 Sheets)
10-21
Timing Gate and Operation Code Voters,
Logic Diagram (4 Sheets)
10-22
Timing and Add-Subtract Voters, Logic Diagram
(4 Sheets)
10-23
Timing Voters, Logic Diagram (4 Sheets)
10-24
Timing and Multiply-Divide Voters, Logic Diagram
(4 Sheets)
10-25
Oscillator and Buffer, Logic Diagram (2 Sheets)
10-26
Clock Generator Timing Logic, Logic Diagram
(4 Sheets)
10-27
Timing and Multiply-Divide Voters, Logic Diagram
(4 Sheets)
10-28
Multiply-Divide Voters, Logic Diagram (4 Sheets)
10-29 Decoupling Capacitors (Channel 5), Logic Diagram
(4 Sheets)
10-30
Memory Timing Voters, Logic Diagram (8 Sheets)
10-31
Memory Address Decoder Voters, Logic Diagram
(8 Sheets)
10-32
Memory Buffer Registers, Logic Diagram (12 Sheets) . . . .
10-33
Address Register and Memory Module Register
Voters, Logic Diagram (4 Sheets)
10-34 . Transfer Register and Memory Module Register
Voters, Logic Diagram (4 Sheets)
10-35
Transfer Register Voters, Logic Diagram (6 Sheets)
10-36
Memory Clock Driver and TCV, Logic Diagram
(2 Sheets)
10-37
Memory Sense Amplifiers, Logic Diagram (2 Sheets)
10-38
Memory Inhibit Drivers, Logic Diagram (2 Sheets) ;
10-39
Memory Y-Address Drivers, Logic Diagram
(4 Sheets)
10-40
Memory Hi-X Address Drivers, Logic Diagram
(4 Sheets)
10-41
Memory Lo-X Address Drivers, Logic Diagram
(2 Sheets)
'
10-42
X Memory Address Diode Matrix, Schematic Diagram
(2 Sheets)
10-43
Y Memory Address Diode Matrix, Schematic Diagram
(2 Sheets)
10-44
Memory Input-Output Panel, Schematic Diagram
(2 Sheets)
10-45
Memory Distribution Panel, Schematic Diagram
(4 Sheets)
10-46
Signal Origin List (8 Sheets)

Page

10-19

IV

10-70
10-74
10-78
10-82
10-86
10-90
10-94
10-96
10-100
10-104
10-108
10-112
10-120
10-128
10-140
10-144
10-148
10-154
10-156
10-158
10-160
10-164
10-168
10-170
10-172
10-174
10-176
10-180

Volume H

LIST OF ILLUSTRATIONS (Cont)

Figure

Title

10-47
10-48
10-49
10-50
10-51

Interconnection Al Back Panel, List for LVDC
Interconnection A4 Back Panel, List for LVDC
Interconnection A5 Back Panel, List for LVDC
Computer, Rear View
Terminal Block Pin Identification, Channels 1, 4, and 5. . .

Page
10-188
10-189
10-190
10-191
10-192

v/vi

SECTION III
INTERFACE AND ADJUSTMENTS
3-1.

INTERFACE

3-2 Figure 3-1 shows the connector interface by function and the direction of signal
flow relative to the computer. Figure 3-2 lists the computer interface signal names and
functions alphabetically by connector number. Figure 3-3 is a functional block diagram
which shows the interconnection of groups of similar signals between the computer and
the data adapter Figure 3-4 shows the interconnection of groups of similar signals
between the computer and the LVDC-ME. Figure 3-5 shows the interconnection of
groups of similar signals between the computer and the ATOM.
NOTE

All the channel reference designations (Al
through A3) have been left off the functional
signal names in all diagrams in this section.
3-3.

ADJUSTMENTS

3-4. No adjustments are made on the computer.

Misc.

-OJ4

Timing

-OJ3

LTE (only)
Module Switching Power

J80-

LVDC

J7o«-

HOJ2

J604-

-»OJ1

J5o^-

Address Reg & TRS
• Memory Power
Logic Power
External Control
• Error Data

Figure 3-1. Computer Connectors By Signal Function

3-1

NAME

CONNECTOR

.*A1V4M1
*A2V4M1
*A3V4M1
*A1V4M2
*A2V4M2
*A3V4M2
*A1V4M3
*A2V4M3
*A3V4M3
*A1V4M4
*A3V4M4
*A1V4M5
*A2V4M5
*A3V4M5
*A1V4M6
*A2V4M6
*A3V4M6
*A1V4M7
*A2V4M7
*A3V4M7
*A1V5M1
*A2V5M1
*A3V5M1
*A1V5M2
*A2V5M2
*A3V5M2
*A1V5M3
*A2V5M3
*A3V5M3
*A1V5M4
*A2V5M4
*A3V5M4
*A1V5M5
*A2V5M5
*A3V5M5
*A1V5M6
*A2V5M6
*A3V5M6
*A1V5M7
*A2V5M7
*A3V5M7
INTRLK
INTRLK
SR01
SR02
SR03
SR04
SR05
SR06
SPARE
SPARE
SPARE
SPARE
SPARE
NOTE

Jl
Jl

Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
.Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji .
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji

HH
J
FF
BB

nE
nw
AA

nF
nl
CC
0G
EE
nQ
no
nv
GG
K
nu

ny
DY
DD
Y
nT
np
nR
G
V

c
nC
W
H
H
A
nS
nA
ON
D
F
T
Z
nB

u

N
P
E
M
X
nM

nx
nZ
R
S

CHANNEL 1. 6 VDC» MODULE 1 SWITCHING
CHANNEL 2» 6 VDC» MODULE 1 SWITCHING
CHANNEL 3» 6 VDC » MODULE 1 SWITCHING
CHANNEL 1> 6 VDC» MODULE 2 SWITCHING
CHANNEL 2, 6 VDC. MODULE 2 SWITCHING
CHANNEL 3> 6 VDC» MODULE 2 SWITCHING
CHANNEL 1> 6 VDC » MODULE 3 SWITCHING
CHANNEL 2> 6 VDC» MODULE 3 SWITCHING
CHANNEL 3» 6 VDC » MODULE 3 SWITCHING
CHANNEL 1» 6 VDC f MODULE 4 SWITCHING
CHANNEL 2/6 VDC. MODULE 4 SWITCHING
CHANNEL 3> 6 VDC , MODULE 4 SWITCHING
CHANNEL 1> 6 VDC» MODULE 5 SWITCHING
CHANNEL 2. 6 VDC» MODULE 5 SWITCHING
CHANNEL 3. 6 VDC, MODULE 5 SWITCHING
CHANNEL 1, 6 VDC» MODULE 6 ':
SWITCHING
CHANNEL 2» 6 VDC» MODULE 6 SWITCHING
CHANNEL 3» 6 VDC » MODULE 6' SWITCHING
CHANNEL 1» 6 VDC» MODULE 7 SWITCHING
CHANNEL 2> 6 VDC, MODULE 7 SWITCHING
CHANNEL 3» 6 VDC, MODULE 7 SWITCHING
CHANNEL 1, 12 VDC, MODULE 1 SWITCHING
CHANNEL 2, 12 VDC, MODULE 1 SWITCHING
CHANNEL 3, 12 VDC, MODULE 1 SWITCHING
CHANNEL 1, 12 VDC, MODULE 2 SWITCHING
CHANNEL 2, 12 VDC, MODULE 2 SWITCHING
CHANNEL 3, 12 VDC, MODULE 2 SWITCHING
CHANNEL 1, 12 VDC, MODULE 3 SWITCHING
CHANNEL 2, 12 VDC, MODULE 3 SWITCHING
CHANNEL 3, 12 VDC, MODULE 3 SWITCHING
CHANNEL 1, 12 VDC, MODULE 4 SWITCHING
CHANNEL 2, 12 VDC, MODULE 4 SWITCHING
CHANNEL 3, 12 VDC, MODULE 4 SWITCHING
CHANNEL 1, 12 VDC, MODULE 5 SWITCHING
CHANNEL 2, 12 VDC, MODULE 5 SWITCHING
CHANNEL 3, 12 VDC, MODULE 5 SWITCHING
CHANNEL 1, 12 VDC, MODULE 6 SWITCHING
CHANNEL 2, 12 VDC, MODULE 6 SWITCHING
CHANNEL 3, 12 VDC, MODULE 6 SWITCHING
CHANNEL 1, 12 VDC, MODULE 7 SWITCHING
CHANNEL 2, 12 VDC, MODULE 7 SWITCHING
CHANNEL 3, 12 VDC, MODULE 7 SWITCHING
LTE INTERLOCK FOR LTE USE 01
LTE INTERLOCK FOR LTE USE 01
SIGNAL RETURN, LINE 01 A2V5I
SIGNAL RETURN, LINE 02 A2V4I
SIGNAL RETURN, LINE 03 A1V5!
SIGNAL RETURN, LINE 04 A3V5I
SIGNAL RETURN, LINE 05 A3V4I
SIGNAL RETURN, LINE 06 A1V4I

BH
nj
n<

^DENOTES INPUTS TO COMPUTER* niNDICATES LOWER CASE LETTER

Figure 3-2.

3-2

Jl

FUNCTION

PIN

Computer Interface Signals (Sheet 1 of 8)

NAME

CONNECTOR

*A1CSTN
*A2CSTN
*A3CSTN .
*A1DIN
*A2DIN
*A3DIN
A1HOPC1V
A2HOPC1V
A3HOPC1V
*A1MCL
#A2MCL
*A1MCN
*A2MCN
A1MD7V
A2MD7V
A3MD7V
A1MR1V
A2MR1V
A3MR1V
A10P1V
A20P1V
A30P1V
A10P2V
A20P2V
A30P2V
A10P3V
A20P3V
A30P3V
A10P4
A20P4V
A30P4V
A1PROV
A2PROV
A3PROV
*A1TER
*A2TER
*A3TER
BRA14P
BRB14P
INTRLK
INTRLK
SIGRET
SIGRET
SIGRET
SIGRET
SIGRET
SPARE
SPARE
SPARE
SPARE
SPARE.
SPARE
SPARE
SPARE
SPARE
NOTE

J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2

PIN

nK
E
K
DM
DA

L
R
HH
nC
D
U
CC
an
N
M

F
nu
J
H
G
B
C
A
np

Z
nx
S
ns
DG

nD
av
EE
W
aw
DD
nB
nY
az
P
X
Y
BB
FF
T
V
aF
aj
n(\|
no
PR
AA
GG

FUNCTION
CHANNEL 1, SINGLE STEP CONTROL
CHANNEL 2» SINGLE STEP CONTROL
CHANNEL 3» SINGLE STEP CONTROL
CHANNEL 1» MEMORY LOAD
CHANNEL 2» MEMORY LOAD
CHANNEL 3. MEMORY LOAD
CHANNEL 1. HOP CONSTANT
CHANNEL 2» HOP CONSTANT
CHANNEL 3» HOP CONSTANT
CHANNEL 1» M A R G I N A L CHECK LATE» STROBE CONTROL
CHANNEL 2» M A R G I N A L CHECK STROBE CONTROL
CHANNEL 1, M A R G I N A L CHECK STROBE CONTROL
CHANNEL 2» M A R G I N A L CHECK STROBE CONTROL
CHANNEL 1. MULTIPLICAND DIVISOR REGISTER LATCH 7
CHANNEL 2. MULTIPLICAND D I V I S O R REGISTER LATCH 7
CHANNEL 3, MULTIPLICAND DIVISOR REGISTER LATCH 7
CHANNEL 1» M U L T I P L I E R REGISTER LATCH
CHANNEL 2. M U L T I P L I E R REGISTER LATCH
CHANNEL 3» M U L T I P L I E R REGISTER LATCH
CHANNEL 1. OPERATION CODE REGISTER LATCH
CHANNEL 2. O P E R A T I O N CODE REGISTER LATCH
CHANNEL 3, OPERATION CODE REGISTER LATCH
CHANNEL 1» O P E R A T I O N CODE REGISTER LATCH
CHANNEL 2» O P E R A T I O N CODE RREEGGIISSTTEERR LATCH
CHANNEL 3, OPERATION CODE RREEGGIISSTTEERR LATCH
CHANNEL 1> O P E R A T I O N CODE R E G I S T E R LATCH
CHANNEL 2» OPERATION CODE REGISTER LATCH
CHANNEL 3. O P E R A T I O N CODE REGISTER LATCH
CHANNEL 1. OPERATION CODE REGISTER LATCH
CHANNEL 2. OPERATION CODE R E G I S T E R LATCH
CHANNEL 3. O P E R A T I O N CODE REGISTER L A T C H
CHANNEL 1. PRODUCT R E M A I N D E R LATCH
CHANNEL 2» PRODUCT R E M A I N D E R LATCH.
CHANNEL 3. PRODUCT R E M A I N D E R LATCH
CHANNEL 1, RESET M E M O R Y tRROR I N D I C A T I O N
CHANNEL 2. RESET MEMORY ERROR I N D I C A T I O N
CHANNEL 3. RESETS MEMORY ERROR I N D I CAT I ON
BUFFER R E G I S T E R A, P A R I T Y BIT
BUFFER REGISTER B P A R I T Y SIT
LTE INTERLOCK FOR LTE USE ONLY
LTE INTERLOCK FOR LTE USE ONLY
SIGNAL RETURN. DC R E G U L A T E D
SIGNAL R E T U R N . DC R E G U L A T E D
SIGNAL R E T U R N . DC R E G U L A T E D
SIGNAL RETURN. REGULATED DC
SIGNAL RETURN. R E G U L A T E D i;C

*DENOTES INPUTS TO COMPUTER. n l N D I C A T E S LOWER CASE LETTER

Figure 3-2. Computer Interface Signals (Sheet 2)
3-3

NAME
A1G5VN
A2.G5VN
A3G5VN
A1PBVN
A2PBVN
A3PBVN
A1WDA
A2WDA
A3WDA
A1XDA
A2XDA
A3XDA
A1YDA
A2YDA
A3YDA
A1ZDA
A2ZDA
A3ZDA
B01N
B02N
B03N
INTRLK
INTRLK
SR07
SR08
SR09
SR1.0
SR11
SR12
SR13
SR14SRI 5
SRI 6
SR17
SR18
SR19
SR20
SR21
SR22
SR23
SR24
SR25
SR26
SR27
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
NOTE

CONNECTOR

C
n'Y
np
ns
nA
.
R
nB
K
N
F
J
HH
H
nH

J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3

J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3.
J3
J3
J3
J3
J3
J-3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3 .

J3
J3

PIN

•

CHANNEL 1, T I M I N G SYNC FOR DATA
CHANNEL 2, T I M I N G SYNC FOR DATA
CHANNEL 3, TIMING SYNC FOR DATA
CHANNEL 1, T I M I N G SYNC FOR DATA
CHANNEL 2, T I M I N G SYNC FOR DATA
CHANNEL 3, T I M I N G SYNC FOR DATA
CHANNEL 1, T I M I N G SYNC FOR DATA
CHANNEL 2, T I M I N G SYNC FOR DATA
CHANNEL 3, T I M I N G SYNC FOR DATA
CHANNEL 1, T I M I N G SYNC FOR DATA
CHANNEL 2, T I M I N G SYNC FOR DATA
CHANNEL 3, T I M I N G SYNC FOR DATA
CHANNEL 1, T I M I N G SYNC FOR DATA
CHANNEL 2, T I M I N G SYNC FOR DATA
QK
CHANNEL 3, T I M I N G SYNC FOR DATA
G
CHANNEL 1, T I M I N G SYNC FOR DATA
M
CHANNEL 2, T I M I N G SYNC FOR DATA
nj
CHANNEL 3». T I M I N G SYNC FOR DATA
DD
2.048 MC T I M I N G
nF
2.048 MC T I M I N G
a\f
2.048 MC T I M I N G
W
LTE INTERLOCK FOR LTE USE ONLY
LTE INTERLOCK FOR LTE USE ONLY
X
E .
SIGNAL RETURN.. L I N E 07-A1XDA
SIGNAL RETURN.. LINE 08-A2WUA
L
P ..
SIGNAL RETURN. L I N E 09-A3PBVN .
SIGNAL RETURN. L I N E 10-A3YDA
S
z
SIGNAL RETURN, L I N E 11-A2PBVN
n
. SIGNAL RETURN, L I N E 12-A1ZOA
C
. SIGNAL R.ETURN, L I N E 13-A1YDA
Q^
QE
SIGNAL RETURN, L I N E 14-A2XOA .
SIGNAL R E T U R N , L I N E 15-A2ZDA
nG
nl
SIGNAL R E T U R N , L I N E 16-A3WDA
nN
SIGNAL RETURN, L I N E 17-A3G5VN
nR
SIGNAL RETURN, L I N E 18-A1G5N
SIGNAL R E T U R N , L I N E 19-A1WDA
nT
SIGNAL RETURN, L I N E 20-B01N
nu
nw .
SIGNAL RETURN, L I N E 21-B02N
SIGNAL R E T U R N , L I N E 22-A2YJA
nx
SIGNAL R E T U R N , L I N E 23-A3ZDA
nz
SIGNAL R E T U R N / L I N E 24-A3XOA
CC
EE
SIGNAL RETURN, L I N E 25-BC3N
FF
SIGNAL R E T U R N , L I K E 26-A3XDA
GG
SIGNAL R E T U R N , L I N E 27-A2G5VN
A
B
D
T
U
V
Y
nM
nQ
AA
BB

ADAPTER
ADAPTER
ADAPTER,
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER.
ADAPTER
ADAPTER
ADAPTER

#DENOTES INPUTS TO COMPUTER, n l N D I C A T E S LOWER CASE LETTER

Figure 3-2. Computer Interface Signals (Sheet 3)
3-4

FUNCTION

NAME

CONNECTOR
J4

A1AI3V
A2AI3V
A3AI3V
A1PIOV

J4
J4
J4
J4
J4
J4
J4
J4

A2PIOV
A3PIOV
EP01
EP02
EP03
EP04

J4
J4
J4
J4
J4
J4

EP06
EP07
INTRLK
INTRLK
SR28
SR29

J4

SR30

J4
J4
J4

SR31

SR32
SR33
SR34
SR35
SR36
SR37
SR38

THERM1
THERM2
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
NOTE

FUNCTION,

PIN
nM
nz
nQ
GG
U

u
w

nR
T
AA
V
nN
nG
nH
A
B
P
S
X

J4

z

J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4

np
as
BB
CC
HH
Y

D
E
F
G

CHANNEL 1» ACCUMULATOR THIRD DELAY LATCH
CHANNEL 2. ACCUMULATOR THIRD DELAY LATCH
CHANNEL 3» ACCUMULATOR THIRD DELAY LATCH
CHANNEL 1, PROCESS INPUT-OUTPUT
CHANNEL 2» PROCESS INPUT-OUTPUT
CHANNEL 3» PROCESS INPUT-OUTPUT
ERROR SIGNAL 01
ERROR SIGNAL 02
.
.
ERROR SIGNAL 03
ERROR SIGNAL 04
ERROR SIGNAL 06
'
• .
ERROR SIGNAL 07
LTE INTERLOCK FOR LTE USE ONLY

LTE INTERLOCK FOR LTE USE ONLY
SIGNAL R E T U R N * L I N E 28-EP06
SIGNAL R E T U R N * L I N E 29-A1PIOV.A3PIOV
SIGNAL R E T U R N * L I N E 30-A2AI.3
SIGNAL RETURN. L I N E 31-EP03
SIGNAL RETURN. L I N E 32-EP01
THERM
SIGNAL RETURN. L I N E 33-THEKM
SIGNAL RETURN. L I N E 34-EPC7
SIGNAL RETURN. LINE 35-EPC2
SIGNAL RETURN. L I N E . 36-EP04
SIGNAL RETURN. L I N E 37-A3AI3V
SIGNAL RETURN, L I N E 38-A1AI3V
THERMISTOR 1 LEAD 1
THERMISTOR 1 LEAD 2

H
J
K
L
M

N
R

aA
nB
aC
nD
a£
nF
nl
nj
nK
nT
PU

av
nw
nx

QY
DD
EE
FF

*DENOTES INPUTS TO COMPUTER, n I N D I C A T E S

Figure 3-2.

2,

LOWER CASE LETTER

Computer Interface Signals (Sheet 4)
3-5

CONNECTOR \ PIN

NAME.
A1EAMV
A2EAMV
A3EAMV
A1EBMV
A2EBMV
A3EBMV
*A1DATAV
*A2DATAV
*A3DATAV
*A1HALTV
*A2HALTV
*A3HALTV
*A1INTCV
*A2INTCV
*A3INTCV
A1TLCV
A2TLCV
A3TLCV
EP05
;
EP08
EP09
EP10
EP11
EP12
EP13
INTRLK
INTRLK
SR39
SR40
SR41
SR42
SR43
SR44
SR45
SR46
SR47
SR90
THERM4
THERMS
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
NOTE

•

J5
J5

:

J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5 .

J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5

np

nz
AA
U
nj
'

n<

R
GG
nB
P
A
G
N
FF
nC
T
S
al
H
Z

EN
V

E
DQ

B5
'K

L
6
C

.w
QA

a'D
nH
ns
nx

cc

nR
D
Y
F
J
M
X
aE
nF
nG
aw
nT
nu
nv
nw

FUNCTION.
CHANNEL •!» EVEN' MEMORY, ERROR
:' „
CHANNEL 2..EVEN MEMORY ERROR
.;,
CHANNEL 3» EVEN MEMORY ERROR .
^
•
CHANNEL 1 » O D D MEMORY ERROR
. .. . . .
CHANNEL 2» ODD•MEMORY .ERROR .
.
. .
CHANNEL 3» ODD MEMORY. ERROR
••
,.
CHANNEL 1, COMPUTER DATA INPUT
CHANNEL 2» COMPUTER DATA INPUT
CHANNEL 3» COMPUTER DATA INPUT
CHANNEL 1> HALT SIGNAL
-.' .
,
CHANNEL 2» HALT SIGNALCHANNEL 3» HALT SIGNAL
"
.
•.
CHANNEL 1» INTERRUPT COMPUTER
CHANNEL 2» I N T E R R U P T COMPUTER
-CHANNEL 3» INTERRUPT COMPUTERCHANNEL 1» SIMULTANEOUS MEMORY ERROR
CHANNEL 2» SIMULTANEOUS M E M O R Y ERROR
CHANNEL 3» SIMULTANEOUS MEMORY ERROR
ERROR SIGNAL 05
ERROR SIGNAL 08
ERROR SIGNAL 09
ERROR SIGNAL 1C
ERROR SIGNAL 11
. .
..
ERROR.SIGNAL 12
..
;.
ERROR SIGNAL 13
LTE INTERLOCK FOR LTfc USE ONLY
. ,
LTE INTERLOCK FOR LTE USE ONLY
SIGNAL RETURN. L I N E 39-EP10
SIGNAL R E T U R N * L I N E 40-.THERM3»THERM4
SIGNAL RETURN. L I N E 41-EP09
SIGNAL R E T U R N * L I N E 42-EP11
SIGNAL R E T U R N , L I N E 43-EPG5
.
SIGNAL RETURN 44-1 N T C » HALT, TLC, EAK AND t.BM
SIGNAL RETURN L I N E 45-EP08
SIGNAL RETURN, L I N E 46-DATAV FOR CHANNELS. 1, 2,
SIGNAL RETURN, L I N E 47-EP13 .
:
SIGNAL RETURN L I N E 90-EP12 . .
THERMISTOR 2 LEAD 2
.
THERMISTOR 2 LEAD 1
'

ay
DD
EE
HH

^DENOTES INPUTS TO COMPUTER, n l N D I C A T E S LOWER CASE LETTER

Figure 3-2. Computer Interface Signals (Sheet 5)
3-6

NAME
INTRLK
INTRLK
SR48
SR49
SR50
SR51
SR52
SR53
SR54
SR55
SR56
SR57
SR58
SR59
SR60
SR61
SR62
SR63
SR64
SR65
SR66
SR67
SR68
SR69
SR70
SR71
*V1 01
*V1 02
*V1 03
*V1 04
*V1 05
*V1 06
*V1 07
*V1 08
*V1 09
*V1 10
*V1 11
*V1 12
*V1 13
*V1 14
*V1 15
*V1 16
*V1 17
*V1 18
*V1 19
*V1 20
*V1 21
*V1 22
*V1 23
*V1 24
SPARE
SPARE
SPARE
SPARE
SPARE
NOTE

FUNCTION'

CONNECTOR i PIN
J6
J6

J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6

J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6

J6
J6
J6
J6

K
L
H

N
P
R
nC
nD
n£
aF
QG
J
nH
Ql

nj
nK
nM
DU

nv
aw
ax

DY
EE
FF
GG
HH
A
B
C
D
E
F
T
U
V

w
X
Y
Z

nA
S
aN
ap
no
aR
nS
DZ

AA
BB
CC
G
M
aB

LTE INTERLOCK FOR LTE USE
LTE INTERLOCK FOR LTE USE
SIGNAL RETURN, L I N E 48-V1
SIGNAL RETURN, L I N E 49-V1
SIGNAL RETURN, L I N E 50-V1
SIGNAL RETURN, LINE 51-V1
SIGNAL RETURN, L I N E 52-V1
SIGNAL RETURN, LINE. 53-V1
SIGNAL RETURN, LINE 54-V1
SIGNAL RETURN, L I N E 55-V1
SIGNAL RETURN, L I N E 56-V1
SIGNAL RETURN, L I N E 57-V1
SIGNAL RETURN, L I N E 58-V1
SIGNAL RETURN, LINE- 59-V1
SIGNAL RETURN, L I N E 60-V1
SIGNAL R E T U R N , L I N E 61-V1
SIGNAL R E T U R N , L I N E 62-V1
SIGNAL RETURN, L I N E 63-V1
SIGNAL RETURN, LINE 64-V1
SIGNAL RETURN, LINE 65-V1
SIGNAL R E T U R N , L I N E 66-V1
SIGNAL R E T U R N , L I N E 67-V1
SIGNAL R E T U R N , L I N E 68-V1
SIGNAL R E T U R N , L I N E 69-V1
SIGNAL R E T U R N , L I N E 70-V1
' SIGNAL RETURN, LINE 71-V1
6 VDC,LINE 1
6 VDC, LINE 2
6 VDC, LINE 3
6 VDC, L I N E 4
6 VDC, L I N E 5
6 VDC, LINE 6
6 VDC, L I N E 07
6 VDC, L I N E 08
6 VDC, LINE 09
6 VDC, LINE 10
6 VDC, LINE 11
6 VDC, LINE 12
6 VDC, LINE 13
6 VDC,L I N E 14
6 VDC, L I N E 15
6 VDC, L I N E 16
6 VDC,LINE 17
6 VDC, LINE 18
6 VDC,L I N E 19
6 VDC,LINE 20
6 VDC,L I N E 21
6 VDC, L I N E 22
6 VDC,LINE 2?
6 VOC,L I N E 24

ONLY
ONLY
05
21
15
07
04
13
14
20
24 •
06
23
22'
16
Oo" '
01
12
19 .
18
17
09
17
10
02 .
03

DO

*OENOTES INPUTS TO COMPUTER, n I N D I C A T t S LOWER CASE L E T T E R

Figure 3-2. Computer Interface Signals (Sheet 6)

3-7

NAME

CONNECTOR

*ETI-1
*ETI-2
INTRLK
INTRLK
SRMEMOl
SRMEM02
SRMEM03
SRMEM04
SRMEM05
SRMEM06
SRMEM07
SRMEM08
SRMEM09
SRMEM10
SRMEM11
SRMEM12
SR73
SR75
SR76
SR77
SR78
SR79
SR80
SR82
SR83
SR85
*V1MEM1
*V1MEM2
*V1MEM3
*V20AM1
*V20BM2
*V20BM1
*V20AM2
*V20 01
*V20 02
*V3MEM1
»V3MEM2
*V3 01
*V3 02
*V3 03
*V3 04
*V3 05
*V3 06
*V3 07
*V3 08
*V3 09
*V3 10
*V5MEM1
#V5MEM2
*V5 01
*V5 02
SPARE
SPARE
SPARE
SPARE
NOTE

E
F
GG

J7

J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7.
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7

PIN

HH
:

A

B
.
C
D
..U
V
Y
aB
G
no
AA
.H
nD
J
M
nG
nl
. nj
DM

nx
nZ
"
EE
nR
BB
CC
nA
nN
W
nT
L
nF
X

np
nH
N
P
R
S
nv
nY
nH
aw
FF
Z
ns
K
n£
T
aC
DU
DD

FUNCTION
ELAPSED TIME INDICATOR 1
ELAPSED TIME INDICATOR 2
LTE. INTERLOCK FOR LTt USE ONLY
LTE INTERLOCK FOR LTE USE ONLY
MEMORY SIGNAL RETURN*. LINc 01-V20bMl
MEMORY SIGNAL RETURN. LINE 02-V3MEM1
MEMORY SIGNAL RETURN. LINE 03-V1MEM1
MEMORY SIGNAL RETURN. LINE 04-V20AM1
MEMORY SIGNAL RETURN. LINE 05-V20BM2
MEMORY SIGNAL RETURN. LINE .06-V3MEM2
MEMORY SIGNAL RETURN, L I N E 07-V5MEM1
MEMORY SIGNAL RETURN. L I N E 0-V5MEM2
MEMORY SIGNAL RETURN, LINE 09-V20AM2
MEMORY SIGNAL R E T U R N L I N E 10-V1MEM3
MEMORY SIGNAL RETURN, LINE 11-V1MEM2
SIGNAL RETURN. L I N E 73-V5 02
SIGNAL, RETURN. L I N E 75-V5 01
SIGNAL RETURN. L I N E 76-V20 01
SIGNAL RETURN. LINE 77-V20 02
SIGNAL RETURN. L I N E 78-V3 01. V3 02
SIGNAL RETURN. L I N E 79-V3 03, V3 04
SIGNAL RETURN. L I N E SO-V3 05, V3 08
.SIGNAL RETURN. L I N E 82-V3 09.
.
SIGNAL RETURN. L I N E 83-V3 07. V3 10
SIGNAL RETURN, L I N E 85-V3 06
6 VDC, LINE 01, MEMORY
6 VDC, LINE 02, MEMORY
6 VDC, L I N E ..03, MEMORY
20 VDC, LINE 1, EVEN MEMORY
20 VDC, L I N E 02, ODD MEMORY
20 VDC L I N E 01 ODD MEMORY
20 VDC, LINE 2, EVEN MEMORY
20 VDC. LINE 01
20 VDC. LINE 02.
-3 VDC, LINE 01 MEMORY
-3 VDC. LINE 02, MEMORY
-3 VDC, LINE 01
-3 VDC. LINE 02
-3 VDC, L I N E 03
-3 VDC, LINE 04
-3 VDC, LINE 05
-3 VDC, LINE 06
-3 VDC. LINE 07
-3 VDC, LINE 08
-3 VDC, LINE 09
-3 VDC, LINE 10
12 -VDC, LINE 01, MEMORY
12 VDC, LINE 02, MEMORY
12 VDC, L I N E 01
12 VDC, LINE 02

*DENOTES INPUTS TO COMPUTER. nINDICATtS LOWER CASt LETTER

Figure 3-2. Computer Interface Signals (Sheet 7)
3-8

NAME

CONNECTOR

A1A1V
A2A1V
A3A1V
A1A2V
A2A2V
A3A2V
A1A3V
A2A3V
A3A3V
A1A4V
A2A4V
A3A4V
A1A5V
A2A5V
A3A5V
A1A6V
A2A6V
A3A6V
A1A7V
A2A7V
A3A7V
A1A8V
A2A8V
A3A8V
A1A9V
A2A9V
A3A9V
A1TRSV
A2TRSV
A3TRSV
INTRLK
INTRLK
SR86

J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8

SR87
SR88

J8
J8

SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE

J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8

NOTE

PIN

T
nM
np
DD
BB
AA
nN
CC
nQ
FF
GG
ol
R
aw
nj

nv
QY
nK
A
X
nR
EE
HH
S
Y
C
W
F
E
D
K
L
V

z
nl

FUNCTION
CHANNEL 1, OPERAND ADDRESS 3IT 1
CHANNEL 2» OPERAND ADDRESS BIT 1
CHANNEL 3. OPERAND ADDRESS BIT 1
CHANNEL 1» OPERAND ADDRESS BIT 2
CHANNEL 2» OPERAND ADDRESS BIT 2
CHANNEL 3» OPERAND ADDRESS BIT 2
CHANNEL 1» OPERAND ADDRESS oIT 3
CHANNEL 2. OPERAND ADDRESS BIT 3
CHANNEL 3» OPERAND ADDRESS oIT 3
CHANNEL 1» OPERAND ADDRESS BIT 4
CHANNEL 2» OPERAND ADDRESS BIT 4
CHANNEL 3» OPERAND ADDRESS BIT 4
CHANNEL .1* OPERAND ADDRESS BIT 5
CHANNEL 2» OPERAND ADDRESS BIT 5
CHANNEL 3» OPERAND ADDRESS BIT 5
CHANNEL 1» OPERAND ADDRESS BIT 6
CHANNEL 2» OPERAND ADDRESS 3IT 6
CHANNEL 3» OPERAND ADDRESS BIT 6
CHANNEL 1, OPERAND ADDRESS BIT 7
CHANNEL 2» OPERAND ADDRESS BIT 7
CHANNEL 3» OPERAND ADDRESS BIT 7
CHANNEL 1, OPERAND ADDRESS BIT 8
CHANNEL 2. OPERAND ADDRESS BIT 8
CHANNEL 3» OPERAND ADDRESS BIT 8
CHANNEL 1» OPERAND ADDRESS BIT 9
CHANNEL 2» OPERAND ADDRESS BIT 9
CHANNEL 3» OPERAND ADDRESS BIT 9
CHANNEL 1. TRANSFER REGISTER OUTPUT
CHANNEL 2. TRANSFER REGISTER OUTPUT
CHANNEL 3» TRANSFER REGISTER OUTPUT
LTE INTERLOCK FOR LTE USE ONLY
LTE INTERLOCK FOR LTE USE ONLY .
SIGNAL RETURN* LINE 86 OPERAND ADDRESS BITS Al,A2»
A3»A7, AND A9 FOR CHANNELS 1.2.AND3
SIGNAL RETURN. LINE 87 TRSV» CHANNELS 1 » 2 » AND 3
SIGNAL RETURN. L I N E 88 OPERAND ADDRESS BITS A4.A5»
A6. AND A8 FOR CHANNELS 1..2. AND 3

B
G
H
J
M
N
P

u'
aA
nB
nC
nD
nE

nF
nG
nH
as
nT
nu
nx

*DENOTES INPUTS TO COMPUTER. ^INDICATES LOWER CASE LETTER

Figure 3-2.

Computer Interface Signals (Sheet 8)

3-9

COMPUTER
DATA ADAPTER
i
I •

iH
Power
Supply

'ower
Sequencing

C4RDN
Real Time

CCSL

+20

+6
+12
-3

Computer
Data
Selector

Relay
Assy

DOMS

C1RD
Interrupt
Processor

Power

1

J20 vv |

Power

1

J15 y. B
»'|

HALTV

J10

\

Power

J21 w \
^-»-

TB«v

JN

C4RD
Accel
Processor

J

vv

vv

°9»

B

AI3V

« J°5

1
i

„ JOS

1

„ J04

r
1
1
i~

Tags

1 Arithmetic
Element

Prog
Program
Control Element

1
Rur
* Lotch

'

Data Control Element
TRS
Lotch

s
9' ste r Bits
Al Thr .. A9

Addres
Re

—

i
*-

AI3
Latch

EXTERNAL
EQUIPMENT

DATAV

'

A1V thru A9V
PIOV

JlSvv

INTCV

«J05

tJOS
, J04

„ JOS

Timing Element I
60(1-2-3) N

G5VN

J05

(W-X-Y-Z) DA

, JOS

. JOS

J03

PBVN
I

I
JlSvv

TLCV

I

Memory Control
Element

,J05

|
I

I

I
Error
Monitor
Registers

EAMV

Error
Monitor
EBMV

Figure 3-3. Computer - Data Adapter Interconnection Block Diagram

3-10

JOS

Memory
Select

Changed 4 January 1965

J05

COMPUTER
Module Switching Voltages*
.

Timing Element

Memory & Logic Voltages *
+6 VDC to Logic*

Timing
Gate
Generator

Phase
Generator

JOKvl
"\
V,
1
ff 1
J07vv 1
1

J06

Power

„ J19

Power

jj J07
V.V
xx J06

Power

\v

Power
j
Sequencing
&
Relay Assy

Clock
Generator

1

1
ff J14

!

TO Error Checking

' Muitiply-Divide Element

Figure 3-4. Computer and LVDC-ME Interconnection Block Diagram

3-11

J'6«
J03

«

J03 < (

AI3V

:

PBAVN

W6

TRSV

1 ^x J02

V> J02
»J°2

ATOM

~1

Sel A c e .
f

»

Timing
Generator

Display
Selection
Switch

. J02

DATA ADAPTER
Instruction Module, Sector
Syllable, Duplex/Simplex

HOP-

JI6

A1V thru A9V
HLTX

JI6 „

*^«

h»

Data Module, Sector,
Syllab1e,Duplex/Simpl

J02

w J02

INTCV

CST

.J02

CSTN

.J02

DIN

.J02

Note 1

r

COMPUTER

Data Control Element

r

Program Control Element

"I

Operation
Code
Register

L

L

HOPC1V

JU/ ss |-

^^r
OP1V
iv iniu
thru OP4V
v^f •* T

;xv JC2
j

Note:
1. See Figure 3-3 for Computer and
Data Adapter Interconnections

Figure 3-5. Computer - ATOM Interconnection
Block Diagram

3-12

SECTION IV
TEST EQUIPMENT AND SPECIAL TOOLS.
4-1.

TEST EQUIPMENT.

4-2. STANDARD TEST EQUIPMENT.
4-3. The standard test equipment recommended to maintain the computer is listed in
figure 4-1.
4-4. SPECIAL TEST EQUIPMENT.
4-5. The special test equipment required to maintain the computer is listed in figure
4-2.
-..
' ' .'
. .
'. ; '.-•'.-•
' ' ' • ' ' • . - ' " . . • '
'•'•• :
4-6.

SPECIAL TOOLS.

4-7.

The special tools recommended to maintain the computer are listed in figure 4-4.

Name

Model or Type

Vendor

Differential Voltmeter

803- B

John Fluke Mfg. Co. , Inc.

Volt- Ohm- Ammeter

630- A

Triplett Electrical
Instrument Co,

Oscilloscope

58 5 A

Tektronix, Inc.

Oscilloscope Adapter

81

Tektronix, Inc.

Oscilloscope Plug- In Unit

M

Tektronix, Inc.

Figure 4-1.

Standard Test Equipment Table

4-1

Name

Manufacturer's
Designation

Index No.
(Figure 4-3)

Description

Book Cart

IBM 6900039

Movable book case, used for .
storage of prime and test
equipment manuals and logic
diagrams.

Equipment Test
Stand

IBM 6940100

Supports the computer and
provides cooling air during
test.

Launch Vehicle
Digital Computer-Manual
Exerciser

IBM 6902000 MD1

Used to test and evaluate computer operation.

Test Program
Tape

IBM 6001225

Contains a program which,
when loaded into the computer memory, permits the
Launch Vehicle Digital
^Computer-Manual Exerciser
to check each functional
part of the computer that
can be exercised by a program.

Figure 4-2. Special Test Equipment Table

4-2

Changed 4 January 1965

. ...'.-ii^i-rt-'-vtr

Figure 4-3. Special Test Equipment
4-3

Name

Manufacturer's
Designation

Index No.
(Figure 4-5)

Description
Supports computer while being
maintained.

Handling Dolly

IBM 658042

Lift Handles

IBM D-656101

3

Provide a means for handling
and lifting the computer
during general handling
activity.

Memory Handle

IBM 658044

2

Used to disengage memory
from its mating receptacle.
Also recommended for
general handling of memory.

Page Extractor

IBM 657922

1

Used to mechanically engage
or disengage the page connector from its mating receptacle.

Test Point
Adapter

Number to be supplied.

Use to provide access to test
points on page assemblies.

Torque Tool Kit

Number to be supplied.

Contains special torque tools
required for torquing those
items replaced during laboratory maintenance.

Figure 4-4. Special Tools Table

4-4

Changed 4 January 1965

Figure 4-5. Special Tools
4-5/4-6

SECTION V
PREPARATION FOR USE, STORAGE AND SHIPMENT

5-1. PREPARATION FOR USE.

.

5-2. The computer is shipped in a reuseable shipping container (part number 6019994,
figure 5-1). Included in the container, although not shown in figure 5-1, is a shock recorder (part number 6019637). To remove the computer from the container,
proceed
J
as follows:
,
:
a. Turn pressure equalizer screw (on shipping container) two turns counterclockwise.
b. Unlatch and remove container cover.
c. Remove the four mounting bolts securing the computer to the container frame.
, ' • . " . . " . WARNING

••• .

:

The computer shall be lifted by at least
two persons. Otherwise, a person may be
injured or the computer damaged.
d. Attach the lift handles to the computer, as described in paragraph 5-8; remove the
computer from the container and place on a handling dolly or test stand. (Refer to
section IV.)
e. Reinstall the mounting bolts for safekeeping.
f. Remove the shock recorder after removing the four socket head screws which attach
it to its bracket; then replace socket head screws in bracket for safekeeping.
g. Open the shock recorder.
gl. Remove the spool that contains the recorded portion of chart paper (figure 5-2).
CAUTION
When removing chart paper, handle chart
paper carefully. Cut (do not tear) the chart
paper to detach recorded portion. The
paper is pressure sensitive, and data may
be obliterated by rough or excessive handling.
g2. Cut the chart paper, remove it from the spool, and replace the spool in the
recorder.
Changed 4 January 1965

5-1

Desiccant Receptacle

Mounting Bolts (4)

Shock Recorder
Bracket

Pressure
Equalizer
Screw

Figure 5-1. Reuseable Shipping Container

Figure 5-2. Removing Roll Chart From Shock Recorder
5-2

Changed 4 January 1965

NOTE
The recorder clock mechanism will operate
until its spring mechanism has unwound. If
the recorder is not to be used immediately,
do not rethread the chart paper. Instead,
tape the loose end of the chart paper to the
writing plate. (See figure 5-2.) This procedure
saves paper and protects the styluses which
would otherwise rest on the hard surface of
the plate.
g3. Rethread the chart paper onto the takeup spool (figure 5-3), or tape the paper to
the writing plate.
g4. Close and latch the shock recorder.
g5. Reinstall the shock recorder (handle side up) in the shipping container.
g6. On a blank portion of the removed section of chart paper, record the
Government Bill of Lading Number
Receiving Location and Receiving Individual's Signature
Unit Name, Part Number, and Serial Number
Container Serial Number and Recorder Serial Number
Data and Local Time recorder was opened.

TAKEUP
( B)
(A)

ROLL CHART PARTIALLY INSTALLED

SUPPLY

FEED DIAGRAM
(C )

ROLL CHART COMPLETELY INSTALLED

Figure 5-3. Installing Roll Chart in Shock Recorder

Changed 4 January 1965

5-3

h. Ship removed section of chart paper to:
Saturn Programs Office, Department 839
IBM Space Guidance Center
Owego, New York, 13827

'

hi. Use a vacuum cleaner to clean the interior of container if foreign material or debris
is in the shipping container.
i. Secure cover on shipping container; then store container for reuse.
5-2A. INSPECTION AND TEST.
5-2B. After the computer has been unpacked, proceed as follows:
a. Examine the exterior of the computer for mechanical damage, noting any evidence
of impact or other severe mechanical stress. Check for loose screws and broken or
missing connector dust covers. If extensive abnormalities are noted, remove covers
and inspect interior of the computer. (Refer to Section K for disassembly instructions.)
b. Remove and store connector dust covers.
c. Perform an electrical checkout of the computer. (Refer to Technical Manual, Checkout Procedures for Saturn LVDC and LVDA.)
5-3.

PREPARATION FOR STORAGE.

5-4. The computer is stored in a reuseable shipping container (part number 6019994,
figure 5-1). The computer is prepared for storage as follows:
a. Install dust covers (part number 6036037) on the eight computer connector jacks.
al.

Unlatch and remove shipping container cover.

a2. Use a vacuum cleaner to clean interior of container if foreign material or debris
is in the shipping container.
b. Remove mounting bolts from computer shipping container.
bl.

Attach lift handles to computer as described in paragraph 5-8.

WARNING
The computer shall be lifted by at least
two persons. Otherwise, a person may be
injured or the computer damaged.
c. Place computer on container mounting frame and secure with mounting bolts. Tighten
mounting bolts with a torque of 250 inch-pounds.
d. Place 17 units of desiccant in receptacle provided.
5-4

Changed 4 January 1965

NOTE
The 17 units of desiccant are packaged in
three bags. The package part number,
units of desiccant per package, and the
quantity of each part number used are as
follows:
IBM Part Number

No. of Units Quantity Used

6019623
6019653

8
1

2
1

e. Secure cover on shipping container.
f. Turn pressure equalizer screw fully clockwise.
NOTE
During storage, the container humidity
indicator should be checked at least once
a week (more often if high humidity conditions.prevail). If the "40" sector of the
humidity indicator turns pink, the
tainer dessicant should be replaced.

5-5.

PREPARATION FOR SHIPMENT.

5-6. The computer is shipped in a reuseable shipping container (part number 6019994,
figure 5-1). Included in the container is a shock recorder (part number 6019637). The
computer is prepared for shipment as follows:
a. Install dust covers (part number 6036037) on the eight computer connector jacks,
al.

Unlatch and remove container cover.

b. Remove mounting bolts from computer shipping container.
WARNING
The computer shall be lifted by at least
two persons. Otherwise, a person may be
injured or the equipment damaged.
c. Place computer on container mounting frame and secure with mounting bolts. Tighten
mounting bolts with a torque of 250 inch-pounds.
Changed 4 January 1965

5-5

CAUTION

Verify that shock recorder styluses are
marked "100g". Otherwise, recorder
will not be capable of recording excessive
shock with accuracy.
cl. Remove the shock recorder after removing the four socket head screws which
attach the recorder to its bracket. Replace socket head screws in bracket for safekeeping.
c2. Open the shock recorder and check for damage.
d. Thread roll chart onto takeup spool of shock recorder.

(See figure 5-3.)

dl. Close cover and strike recorder sharply against floor. Open cover and verify that
all three styluses have made a discernable impression on the chart paper.
NOTE
A full roll of chart paper is long enough
to record shock for a period of 60 half
days (30 days). The numbers on the lefthand margin indicate the number of half
days remaining on the roll. The mechanism
is capable of running for eight days (16 half
days). Verify that the number on the lefthand margin is 16 or greater at the point
where recording starts. Reorder chart
paper from the following address: Electrical Standards, Dept. 331
Attention: Manager
IBM Space Guidance Center
Owego, New York, 13827
d2. On the chart paper record the
Government Bill of Lading Number
Sending Location and Sending Individual's Signature
Unit Name, Part Number and Serial Number
Container Serial Number and Recorder Serial Number
Date and Local Time recorder was started

5-6

Changed 4 January 1965

NOTE

The chart paper is calibrated in A.M. and
P.M. hours, but it is not necessary to
align the paper with the local time. Simply
write the local time at the point where the
recorder was started.
•:,.••

.

d3. Wind the shock recorder, and verify that the paper is moving and that all three
styluses are tracking.
d4. Close and latch the shock recorder,, but do not lock the latch.
e. Remove socket head screws from shock recorder mounting bracket.
f. Install shock recorder on bracket, using socket head screws previously removed.
g. Place 17 units of desiccant in receptacle provided.

'

. '-. '•'.'••"-. •'••-•;• '•'•:••.': '•;•-;•'..' NOTE.-' '-^'''••v- : "':,.;.- : 'v^--'v ' • ' , - . • ••
; . . ' . The 17 units of desiccant are packaged in
< three ;bags. ; The package part number,
units of desiccant per package, and the
quantity of each part number used are as
follows:
IBM Part Number

No. of Units Quantity Used

6019623
6019653

8
1

2
1

h. Secure cover on shipping container.
i. Turn pressure equalizer screw fully clockwise.
5-7.

GENERAL COMPUTER HANDLING.

5-8. Computer lift handles (IBM Tool Number D-656101) are used for general handling
of the computer. Two computer lift handles .are needed for computer handling; one
handle is mounted on the left side of the computer and the other handle is mounted on the
right side of the computer. Mount the computer lift handles as shown in figure 5-4.

Changed 4 January 1965

'

5-7

Figure 5-4. Computer Lift Handle, Mounted

5-8

Changed 4 January 1965

SECTION VI
PREVENTIVE MAINTENANCE

No preventive maintenance is performed
on the breadboard models.

6-1/6-2

SECTION VH
CHECKOUT
7-1. OPERATING TEST PROCEDURES.
7-2. Instructions for testing the computer are located in the Saturn V Launch Vehicle
Digital Computer and Data Adapter Checkout Procedures Laboratory Maintenance
Instructions.

7-1/7-2

SECTION vm
TROUBLE ISOLATION

This section is not applicable
for breadboard equipments.

8-1/8-2

SECTION DC
REPAIR
9-1. REPAIR.
9-2. Laboratory repair of the computer is limited to replacing page assemblies and
toroid memory assemblies. Laboratory replaceable assemblies are listed in figure 9-1.
The methods for replacing such assemblies are described in this section. The computer
is mounted on an equipment test stand (IBM part number 6940100) during repair.
9-3. PAGE ASSEMBLY REPLACEMENT. (See figure 9-2.) The page assemblies are
accessable after removing the computer logic cover. To replace a page assembly proceed as follows:
a. Remove the logic cover by removing and storing the 14 mounting screws and washers
located around the outer edge of the cover.
b. Locate the page assembly to be replaced.

(Refer to figure 9-3.)

NOTE
Do not remove page assembly captive mounting screws from page assembly until after
the page assembly is removed from computer.
Assembly
6110211
6110212
6110213
6110214
6110215
6110216
6110217
6110218
6110219
6110230
6110231
6110232
6110233
6110234
6110235
6110236
6110237
Figure 9-1.

Location

A4A11
A4A12
A1A3, A2A3, A3 A3
A1A7
A1A8
A1A9
A1A10
A1A5
A1A11
A1A12
A1A13
A1A14
A1A15
A1A16
A1A17
A1A18
A1A19

Assembly
6110238
6110239
6110240
6110251
6110252
6111500
6125408
6125409
6125420
6125423
6125424
6125425
6125426
6125427

Location
A1A20
A5A9, A5A10
A5A11
A1A4, A2A4, A3A4,
A4A4
A5A3
A6A2, A6A3
A5A5
A5A6
A4A5, A4A6, A4A7,
A4A8, A4A9,
A4A13, A4A14
A5A7, A5A8
A5A12
A5A13
A5A14
A5A15

Laboratory Replaceable Assemblies

9-1

MEMORY COVER

COVER MOUNTING SCREW (22)
AND WASHER

TOROID
MEMORY
ASSEMBLIES

ELECTRICAL CONNECTORS
U5 THROUGH J8)

MOUNTING SCREW
(4 PER ASSY)
AND WASHER
ELECTRICAL CONNECTORS
(Jl THROUGH J4)
PAGE ASSEMBLY (43)
LOGIC COVER
PAGE MOUNTING SCREW (2)
AND WASHER

COVER MOUNTING SCREW (14)
AND WASHER

Figure 9-2. Computer, Partially Disassembled
9-2

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MINAL BIOCK

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6II02SI CAPACITY ASSY

| . 611 2995 TERMI NAL BLOCK

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9-3

c. Unscrew the two page assembly captive mounting screws until free of mounting holes.
NOTE
Remove page assemblies with a page insertionextraction tool (figure 4-4), hereafter referred
to as extractor tool.
d. Place extractor tool over top of page assembly; then push locking knob toward page
assembly, thus locking tool to assembly.
e. Squeeze extractor tool handle to its limit (disengaging page assembly connector);
then pull page assembly straight out.
CAUTION
Hold page assembly firmly to safeguard dropping
when releasing extractor tool.
f. Release page assembly from extractor tool by pushing in the locking knob and moving
knob away from page assembly.
g. Remove and store mounting screws and associated fiber washers from page assembly.
NOTE
Page assembly removal is now complete. To
install the replacement page assembly proceed
with step h.
h. Install previously removed page assembly mounting screws and fiber washers (IBM
part numbers 6110636 and 6113634) in replacement page assembly.
i. Place extractor tool over top of replacement page assembly; then push locking knob
toward page assembly, thus locking tool to assembly.
CAUTION
Verify that A side of page assembly faces
downward when inserting page assembly into
computer. Otherwise connector pins will not
mate with receptacle.
j. Insert page assembly into proper computer logic channel location.

9-4

k. Push in extractor tool locking knob; then move knob away from page assembly, thus
releasing tool from page assembly.
1. Turn in the two page assembly mounting screws; then torque screws to 15 inchpounds.
' • . : • - . - . . . . . . "-.'-.
'
V: - i '
m. Secure computer logic cover by turning in cover mounting screws and washers
(IBM
part numbers 6072520 and 6048641); then, using the cross-over method, torque
cover mounting screws to 10 inch-pounds;
•-•'
9-4. TOROID MEMORY ASSEMBLY REPLACEMENT. (See figure 9-2.) The toroid
memory is accessable after removal of the computer memory cover. To replace a
toroid memory assembly proceed as follows:
a. Remove the memory cover by removing and storing the 22 mounting screws and
washers located around cover edge.
NOTE
Memory assembly connectors mate with connectors J2 and J3 of memory mounting plate
assembly.
NOTE

,

•

The replacement of the toroid memory assembly
is simplified by the use of the memory handle.
(Refer to figure 4-4.)
•
When attaching memory handle to memory
assembly, attach gripper marked CONNECTOR .
END to shoulder screws at connector end of
memory assembly.

b. Slide memory handle grippers under four shoulder screws on top of memory
assembly; then place tool keeper over memory handle shoulder screw, thus securing
tool to assembly. (See figure 9-4.)
• .
CAUTION
Hold memory handle firmly to safeguard dropping
memory assembly during removal of memory
assembly mounting screws. • . • : • •
c. Remove and store the four memory assembly mounting screws and associated
washers.

9-5

MEMORY HANDLE
KEEPER

b.

MEMORY HANDLE
GRIPPER
MEMORY HANDLE
SHOULDER SCREW

jvr-j

MEMORY ASSEMBLY
SHOULDER SCREW

I©

'nnnnnnnnnani
NOTE: PHANTOM AREA INDICATES MEMORY ASSEMBLY

Figure 9-4.

Memory Handle Secured to Memory Assembly
NOTE
The memory assembly connector is a rackand-panel type and will disengage from its
mating receptacle on the memory distribution board as the memory assembly is lifted
out.

<

d. Pull on memory handle just enough to disengage memory assembly connector; then
offset assembly enough to clear adjacent memory assembly and pull assembly straight
out.
e. Remove memory handle from memory assembly.
NOTE
Toroid memory assembly removal is now
complete. To install a replacement memory
assembly proceed with step f.
NOTE
When attaching memory handle to memory
assembly, attach gripper marked CONNECTOR
END to shoulder screws at connector end of
memory assembly.

9-6

I. Slide memory handle grippers under four shoulder screws on top of replacement
memory assembly; then place tool keeper over memory handle shoulder screw, thus
securing tool to assembly. (See figure 9-4.)
CAUTION
Hold memory assembly and memory handle
firmly to safeguard dropping during installation.
g. Insert replacement memory assembly into proper memory distribution board location; then verify that connector and receptacle are properly mated.
h. Turn in memory assembly mounting screws with associated washers (IBM part
numbers 6035770 and 6113635); then torque screws to 15 foot-pounds.
i. Install memory cover and turn in mounting screws with associated washers (IBM
part numbers 6076307 and 6048641); then using the cross-over method torque screws to
10 inch-pounds.

9-7/9-8

SECTION X
DIAGRAMS
10-1.

DIAGRAMS.

10-2. The diagrams included in this section are the drawings required to maintain the
computer. The drawings consist of the following:
Figure
Figure
Figure
Figure
Figure

10-1.
10-2.
10-3.
10-4.
10-5.

Clock Drivers Logic Diagram (4 Sheets)
Decoupling Capacitors (Channel 1) Logic Diagram (4 Sheets)
Delay Lines Logic Diagram (2 Sheets)
Multiply-Divide Element Logic Diagram (12 Sheets)
Add-Subtract Element Logic Diagram (4 Sheets)

Figure
Figure
Figure
Figure
Figure

10-6.
10-7.
10-8.
10-9.
10-10.

Transfer Register Bits 10-TRS and Control Logic Diagram (2 Sheets)
Memory Buffer Control and Parity Counter Logic Diagram (2 Sheets)
Operation Code Register Logic Diagram (4 Sheets)
Timing Gate Generator Logic Diagram (2 Sheets)
Phase Generator Logic Diagram (2 Sheets)

Figure 10-11. Memory Module Registers Logic Diagram (2 Sheets)
Figure 10-12. HOP Constant Serializer and Memory Read Latches Logic Diagram
(2 Sheets)
Figure 10-13. Memory Timing Logic Diagram (4 Sheets)
Figure 10-14. Memory Error Detector Logic Diagram (8 Sheets)
Figure
Figure
Figure
Figure
Figure

10-15.
10-16.
10-17.
10-18.
10-19.

Transfer Register Bits 1-9 Logic Diagram (4 Sheets)
Address Register and Memory Address Decoder Logic Diagram (4 Sheets)
Memory Sector Registers Logic Diagram (2 Sheets)
Hi-Y Memory Address Decoder Logic Diagram (2 Sheets)
Decoupling Capacitors (Channel 4) Logic Diagram (4 Sheets)

Figure
Figure
Figure
Figure
Figure

10-20.
10-21.
10-22.
10-23.
10-24.

Operation Code Voters Logic Diagram (4 Sheets)
Timing Gate and Operation Code Voters Logic Diagram (4 Sheets)
Timing and Add-Subtract Voters Logic Diagram (4 Sheets)
(
Timing Voters Logic Diagram (4 Sheets)
Timing and Multiply-Divide Voters Logic Diagram (4 Sheets)

Figure
Figure
Figure
Figure
Figure

10-25.
10-26.
10-27.
10-28.
10-29.

Oscillator and Buffer Logic Diagram (2 Sheets)
Clock Generator Timing Logic, Logic Diagram (4 Sheets)
Timing and Multiply-Divide Voters Logic Diagram (4 Sheets)
Multiply-Divide Voters, Logic Diagram (4 Sheets)
Decoupling Capacitors (Channel 5) Logic Diagram (4 Sheets)

Figure
Figure
Figure
Figure

10-30.
10-31.
10-32.
10-33.

Memory Timing Voters Logic Diagram (8 Sheets)
Memory Address Decoder Voters Logic Diagram (8 Sheets)
Memory Buffer Registers Logic Diagram (12 Sheets)
Address Register and Memory Module Register Voters Logic Diagram
(4 Sheets)

10-1

Figure 10-34. Transfer Register and Memory Module Register Voters Logic Diagram
(4 Sheets)
Figure 10-35. Transfer Register Voters Logic Diagram (6 Sheets)
Figure 10-36. Memory Clock Driver and TCV Logic Diagram (2 Sheets)
Figure 10-37. Memory Sense Amplifiers Logic Diagram (2 Sheets)
Figure
Figure
Figure
Figure
Figure

10-38.
10-39.
10-40.
10-41.
10-42.

Memory Inhibit Drivers Logic Diagram (2 Sheets)
Memory Y-Address Drivers Logic Diagram (4 Sheets)
Memory Hi-X Address Drivers Logic Diagram (4 Sheets)
Memory Lo-X Address Drivers Logic Diagram (2 Sheets)
X Memory Address Diode Matrix Schematic Diagram (2 Sheets)

Figure
Figure
Figure
Figure
Figure

10-43.
10-44.
10-45.
10-47.
10-48.

Y Memory Address Diode Matrix Schematic Diagram (2 Sheets)
Memory Input-Output Panel Schematic Diagram (2 Sheets)
Memory Distribution Panel Schematic Diagram (4 Sheets)
Interconnection Al Back Panel, List for LVDC
Interconnection A4 Back Panel, List for LVDC

Figure 10-49. Interconnection A5 Back Panel, List for LVDC
Figure 10-50. Computer, Rear View
Figure 10-51. Terminal Block, Pin Identification, Channels 1, 4, and 5
10-3.

SIGNAL TRACING.

10-4. Signals may be categorized into two groups:
•

Signals that appear at the input-output connectors.

•

Signals that originate in, and are used solely by, the computer.

Locating these two types of signals and finding points in the computer where they may
be observed requires two different procedures.
10-5. TRACING INPUT-OUTPUT SIGNALS. These signals may be located by referring
to the interface listing, figure 3-2. The signals may be checked by probing the A4 and
A5 back panels at terminal blocks A4J1 through A4J4, and A5J5 through A5J8. (See
figure 10-50.)
NOTE
The A5J7 terminal block has the same pin
layout as A4J4, with a different orientation.
The terminal blocks are directly wired to the input-output connectors and the terminal
block pins have the same corresponding designation as the connector pins. To trace an
input-output signal into the logic, refer to the interconnection back panel listings, figures
10-47 through 10-49. The signal can be found under the "Net Name" column.

10-2

j

NOTE

Signals originating outside the back panel
(listing) being used, may require the reference designator prefix that is automatically assigned to all signals. Thus, if a
signal cannot be found under the alphabetic
portion of the listing, be sure to look
under the portion of the listing which contains reference designator prefixes.
Once the signal is found in the listing, all the pin locations, by reference designator,
are listed under the "Page-Pin" and "Bib-Pin" columns. The reference designator can
then be used to find the signal in the logic. (See figures 10-1 through 10-35.)
NOTE
The reference designator for each MIB-logic
diagram is located on the right hand margin,
white symbols on a black background.
10-6. TRACING INTERNALLY GENERATED SIGNALS. These signals may be located
by referring to the Signal-Origin List, figure 10-46. The signal-origin list refers the
reader to the appropriate MIB-logic diagram by reference designator. (See figures 10-1
through 10-41.) On the MIB-logic diagram are references to test point locations on the
logic page. If a signal is to be checked for which a test point is not provided, then one
of the terminal blocks on the A4 or A5 back panels may make the desired signal available.
(In addition, most of the channel 4 page pins are available from the rear of the A4 back
panel.) Look up the signal name in the appropriate interconnection back panel listing and
determine whether or not the signal goes to a terminal block. If the signal is used on
both panels Al (A2 and A3 also apply for redundant circuits) and A4, the listing will show
a reference to a terminal block, reference designator A1EX or A4EX. (See figure 10-51
to identify pin locations.)
NOTE
A one-to-one correspondence exists between
pins on the A4 and Al terminal blocks due to
the printed circuit cables interconnecting the
terminal blocks. (See figure 1-2.)
If the signal goes to a memory module from a location in channel 5, a reference to
terminal blocks A5E3, A5E5, or A5E7 will occur. Some of these locations are available
for probing. (See figure 10-51 to identify pin locations. Only the upper pins, rows A
and B, are available for probing.) The points where signals appear on the memory
module and memory distribution panel are illustrated in figures 10-44 and 10-45. These
points are not available for probing.

10-3

Wl

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
Dotted Line (if any) Indicates Internal ULD
Connection
"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
Prefix Reference Designations as Follows: A1A3A

•WN

Figure 10-1.

10-4

Clock Drivers, Logic Diagram (Sheet 1 of 4)

XI
BOP

CGPNP

CGQP'

THRU - PINS
PIN

1
2
3
i4
5
6
7
8
9
10
11
12
13
14
15

SIGNAL

CGPP

Figure 10-1.

PIN

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

SIGNAL

ZF
YF
CGPNP
WF
XF

PIN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

CONNECTOR PINS
PIN
SIGNAL
SIGNAL
WN
51
V5
V5
53
W5
VI
WDA
55
57
SIG RET
SIG RET
59
W7
SIG RET
SIG RET
61
V3
SIG RET
Wl
63
SIG RET ••
65
W8
67
CGPNP
W2
69
X3
W3
71
XI
SIG RET
SIG RET
73
V3
75
V3
W4
77
V3
W6
79
X2
VI
81
X4
VI
X6
CGRP
83
X5
SIG RET
85
87
SIG RET
V3
89
XN
BOP
91
SIG RET
CGQP
X8
VI
93
X7
95
CGPP
97
XDA
V5
V5

Clock Drivers, Logic Diagram (Sheet 2)

10-5

Yl

CGRNP'

NOTES:
I See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (if any) Indicates Internal ULD
Connection
4. "N .U ." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A3B

Figure 10-1. Clock Drivers, Logic Diagram (Sheet 3)

10-6

Y8

YN

LVDC

BOP

CGPNP

CGQNP

-24

ZDA

PIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

THRU - PINS
SIGNAL
PIN

CGPP

Figure 10-1;

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

SIGNAL

ZF
YF
CGPNP
WF
XF

•*,

CONNECTOR PINS
SIGNAL
PIN SIGNAL
.52
V5
2 . ZDA
CGPP
Z7 •:
54
4
VI
Z8
56
6
CGQNP
58
8 • SIG RET
BOP
ZN
60
10
62
V3
12
SIG RET
64
SIG RET
Z5
14
CGRNP
66
Z6.
16
VI
68
18
Z4
VI
Z2
70
20
72
Y6
22 ;V3
74' Y4
24
V3
SIG RET
76
26
V3
78
SIG RET
28
Zl
80 • Y3
30 • Z 3
82
Y2
32
CGPNP Y8 .
84
34
SIG RET
86
Yl
SIG RET
36
88
SIG RET
38
V3
Y7
90
SIG RET
40
92
SIG RET
42
SIG RET
YDA
VI
94
44
Y5
96
46
V5
YN
98
48
V5
V5
50

-25

PIN

-7.8

Clock Drivers, Logic Diagram (Sheet 4)

10-7

HOI'f. 1,2

1
e
16 Cl 1
?
(i
14 Al f

i
1
f <:/
7

g

M
//

ri

A
•

''
7

7
,»

f
1

;
6
"1$ Cl J
?
/f
ft A3 f

a
fo
11

H

tr^
u
>i

/

A

a

Cl 7
AH

4

Cl 7
All

f t •i —
A4 ''

a
tli
li

g

<:; 16

SIG RET

Cl J '
f
14 AS f
\
1
Tl"4
«

7

7 Cl

Cl (f
Aft

AIS *

Tf 3
C

7 Ci

a

Cl
A3

a

7 Cl
All

a

A^^

7

7 Ci
A19

e

7

C£
AI6

a

7

Ci
AJO

r/'6
<\
/-/'7

<\
Tl"e
w a

jpf5

CJ

•

Signal

51 ; SIG RET
5 3 - ' SIG RET
55
SIG R E T .
57
SIG R;ET
59
SIG RET
61
SIG RET
63
V3
65
V3
67
V3
69
V3
71
SIG RET
VI
73
VI
75
77
VI
VI
79
81
SIG RET
83
SIG RET
85
SIG RET
87
SIG RET
89
SIG RET
91
SIG RET
93
SIG RET
MSVB2
95
97
MSVB2

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A4A

Figure 10-2.v- Decoupling-Capacitors^(Channel 1),; Logic Diagram (Sheet 2)

10-9

Tf*

.\.
Vo-*— 3

NOTl I

l(.

i4 Al

?J7

e

1

10

A/I/I

~1?
W tf
*

J

s

It
7 A6 t*

}i
I

j

1

10

/{

14 A4
NU 4

HUS

Y4HIOD t

fi
~Tl
ii
l-t
s

~v
/^
14

Figure 10-2.

10-10

iJ—

Cf

•) —

A&

1
7—
?

1
—?
J
1

f
J

S

/«



10
11

3
S

/<

7

g;

ft

W~
tf
>* .

TP6

—T

7

s
7 A >0

Ct i

7

e
1 3' C/ 16
Jf*
/lA

*

Tf6

vs
NV3

>/^

9 I*— 'j
w—
It
3

f

s

1
B
3
>i cr S
14 A3 7
fl

a
ie
/•t

73-

TfS

7

NU2

S
7

1

1

orr i

3

S~
7

a
' I
^
* i' CJ ^ra
7
/<

<9

T

C 1 /«"'
/*

1

ff/V

7

All

/
J

a
r.i ia

7

n
f*

sic.

Decoupling Capacitors (Channel 1), Logic Diagram (Sheet 3)

CONNECTOR PINS

TPII
.

a
%
W

"15

[
*

f4

7

7

T

a 1

'T

7S-*

7

M.

11

5

/
j
1

ft

Pin

)l

2

/*

4
6

e

/
T
i.J

0
73—

V

H

'liS

5

I
3

14

7

7

. r/>>4

• f1
i

" *I
16
/4
•-• j"

'

V4 MODI

28
30

It

1

10

22
24
26

e
/i

V3

12
14
16
18
20

TPI3

Signal

C.1

iq
fi
&—

•j/c nt r

Figure 10-2. Decoupling Capacitors (Channel 1), Logic-Diagram (Sheet 4)

TP5

TPI5

W7

A

Up]

vn
LL44SX

DDISAIN

\
\

"

a

X)

AM

1 i

f

5TP

A 14

I>I4 CiH

7.6 t,lZ

u

f- — \i
ft

A 13

y

>U3

S

J TPft

—\io

X3

|/e*
/,/

e.n

Figure 10-3. Delay Lines, Logic Diagram (Sheet 1 of 2)

10-12

~\
OL44
BOH

OLD 10

<•

^"!1 2

,

*«,

OLD

/>^ J_
TPi

1

V
'
fi

9

,I

TP

si
L."
9,i3

JO

3,5

2412
A4- IZ

i

! i
«ij-'

H^^tJ
|
/
| J

|

7
•• —-M
— rih,-

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-^
rj

2L£^J

!

' J!

JTP4-I

•L.

«-|OLD

DL-31 — 5
At
BOW— ^

*

.

J

10

1 cir,»«

'>

- 3

L__j

CONNECTOR PINS
Pm

Signal

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

WN
SIGRET
MRON
MRO

51
53
55
57
"59
61
63
65
67
69
71
73
75'
77
79
81
83
85
87
89
91
93
95
97

31 •
33
35
37
39
41
43
45
47
49

V3

ACCON
YN
PQR

ACCO
MDON
VI
'
STP

PQRN
PRN

Signal
ZN
PR
NU

A ION
XN

. NUN

*

i T*

L

r.»».
»

'

-L*
|I0««>' ^/>V£|

1

wr

• •

1 1i
-- \ - j \ \

l^r^lr
3
1
1 -L'

1

4
Vf,
rftff
'
1

•

L.s,c

Tf>i8
a n
r/=/'?^'~i
r
^
'^-^
•'•'^
8l -s'^^i t i
;TPIO TP i

i

TI

,

f/-,

pl'J
7

'M
• ^i/4

•

in

ll

f.i,

77

!

NOTES:
1. See Glossary or Index for Signal Definitions
See Logic Symbols-Appendix for Definition
of Logic Symbols
Dotted Line (if any) Indicates Internal ULD
Connection
"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
Prefix Reference Designations as Follows: A1A5A

.Z2
Y8

X3 '
A10

. W7

•"MDO
' STPN
DL31

-

DL44

BON
V5

Figure 10-3. :; Delay Lines, ;Logic Diagram (Sheet 2)

10-13

DL44

Figure 10-4.

10-14

Multiply-Divide Element, Logic Diagram (Sheet 1 of 12)

Yi
HQ1Y •

p^vN
P&V

n•
vow •

A 14
Alt
-~\K
A IO
Alt,

n

A
Alt 10
tlN

P3N
V4NIOD 4 •
KUNV •

A
Ali
— 1?
A
A 13

A

JL :Aid

1

7P/3
• PIN

A/9

14

TPI7

1

— I'
.A

NN

TPlO

TMM

fJM

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Figure 10-4.

CONNECTOR PINS
Signal
Pin
Signal

OPIV'
P1VN ,
PCVN
VOYN
VOY •MR 2
V]
OP4VN
DL44
G2V
PR10
PQR
MD7V
TTLV
AI3V
DL31
STP
PR 2V
HOY
OP3VN
OP2VN
HOYN
G6V
PCV
ZN

51 "
53
55 '
57
59
61
63
65
67
69
71
73.
75
77
79
81
83
85
87
89
91
93
95
97

G7VN
Q8V
DTMN
RUNV
VOYV
PBV
•
G4VN
P3N
TMVN -•'
DTM
TMV
G3VN
P2N
PIN
G7V
G1VN
TM
PAV
G6VN
G4V
DTMVN
DTMV
TMN
G5VN

THRU PINS
Pin

Signal

Pin

Signal

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

V3
G5V
NU

HOYV'N
W2
OP2V

T8CV

P2VN
DTMVN
G2V

G7VN

VI •
V4MOD4 '
P3VN
G4VN
HOYV
G3VN
TMVN
76
X7

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A7A

Multiply-Divide Element, Logic Diagram (Sheet 2)

10-15

wz
HOff

£JJ

*>
AJ

Li

T3CV

26

~Mf
A
A 10

Vf

7

rp3
O

~\8 A.
AID

r
l_

J

/

f

NIDI

/)/0

V1 —[ — — js
J

A

I8

_£/Jj
It

/ 5
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— MO
A
7
All
,

hGV .

rt

10

g-

2- A) •h

f>JV\'

X7

it

TPI5

VI

f

4

— 19
/7

1

j-

--'--

L^ /7

f

/V>i>^

— |S

MD4

r

HO r*N

•

A
AS,

j

/

X

MOSN

At

4T

«i3.

PIVH

/T7

U

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 3)

10-16

M04

MD4N

See Glossary or Index for Signal Definitions
See Logic Symbols Appendix for Definition
of Logic SymbolsDotted Line (if any) Indicates Internal ULD
Connection
"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A7B

CONNECTOR PINS
Pin

CSV

;
Pin

.1..
2
3
4
5
6
7
8
9
10
11
12
13
14

15

THRU PINS
Signal

SIG RET
HOYVN
W2

OP2V
TBCV

P2VN
DTMVN
G2V

G7VN

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29.
30

Siqnal

V3
G5V
NU
VI

V4MOD4
P3VN
G4VN
HOYV
G3VN
TMVN
26
X7

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
MD5N

MD5
MD6

MD6N
MD7N
X7
MD7

MD4N
MD3

V4MOD4
V3

SIG RET
NU
MD4
MD2
W2

OP2V
MD3N
TRSV
MDO
VI
V]
G5V

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal
Z6

MD2N
TBCV
MDON
Kl
KIN
K2N

P2VN
P3VN 'K2

HOYVN
SG2N
SG2

HOYV
PROVN
PROV .
ESDV
ESDVN
SG1N
PR IN
TFDVN
PR1
SGI

TFDV

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 4)

10-17

A*

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ft

¥

It?

H'i

#

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tei -

MY* -

6/W

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se/,v
AK2
6IM
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feitt—4
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x/C/V — '

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gffH.V-

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"<-r~\

1

TMON

S7

-^EH
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set
wv^
ft

4?
Z+

10

AY
X7

4I5\

•>TP4

fif

TKVN

—

r}
\4>\"

sec*
SC2

10

Figure 10-4.

10-18

Multiply-Divide Element; Logic Diagram (Sheet1 5)

NOTES:
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U. Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
^ 4W
5. Prefix Reference Designations as Follows: Al ASA

CONNECTOR PINS

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

-17

£

~/ \

xv^ —24-

M—.

ruM

A.
A!T_
H'l
f£f

L
J?

e?v

~\7
£
A 10

>f

G7V

A

omvw — ^
—\j

«/'f —|
HOf^
GIV

\AX
«

f

1
ID

Pin

Siqnal
MR2N
MD7N
PR6
G6V
'
Y7
MR2
VOYVN
HOYV
AV
G2V

51
53 _
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95 :
97

G7VN
MD7V
SG2N
SG2
Ql
PR6N
P1VN

Signal

X7
,W2

G3V
Z4
TMVN
P3VN
HOYVN
G4V
G1V
G1V
G1VN
AVN
Q1N
G6VN
G4VN
DTMVN
DTMV
SGI
SG1N

f4f0/V

lew —IL

//?

/

'

r?S

— ,,

SMW— &•

A
A 13

J_]

J
413 '

THRU P INS
Pir

H2

TF'O

—\7
A

,

fSf
4f

A

=£f

fl
f \
fl

errtw-

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if

SfM-

1
/H

=
1

J

am

AY

S iqnal

1
2

SIG RET

3
4
5
i
8
9
11
12
13
14
15

Pin

Siqnal

EMDN
SMDN
FMDN

' 16
17
,•
1R
19
20

V3
ZDHN
VOYV
PR6
ZDLN

G2VN
CDN
G6VN

22
23
24

G1YN
G7V
G7VN

TMVN
CD
G6V
PR6N
G5V

26
27
28
29
30

DTMVN
DTMV
VI
Y7
G1V

"^

.-a.
*1
Ft'PK-

S

—\s
^J
A?4

1'PI
S ]
S 1
A 24

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 6)

10-19

.:;,=
I
.

GIM

UOYVN

MMV

"iD:*
(

UOY V N

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 7)

10-20

-

T 10

5MDN
§1
MO4
2J AilJ
Y7 ^^~^^
ZDHN — £
14
EMDN —aS
MD5
- A35
V4MOD4
~lft
A

IT
A

TFDN

V4MOM

H

A

VID4N — LS

A

V7
EMDN

^

MD5N
Y7

^ A/53
—17

I

Si

DTMVN

S-

HOYV

!2

Y7

CONNECTOR PINS

TFD
MD4N
MD5

MD5N
TFDN
MD2
BSD
M03
V4MOD4
V3
PR4N
ESDN
SIG RET
MD4

MD2N
MD3N
MD6
G3VN
VI

50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
9G
92
94
96
98

G5V

MR IV

MD6N
PR4

SG2N
SG2

Z4

SG1N

SGI
G2VN

ESDN

K3

TPIT

_,

A
A

1
6

~~13
£
g

ALc_

HOfVN
TMVM

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48

f

A?*

A3 3

Signal

fe

— |io

!^

SMDN

Pin

T

h?
A

A54

Y7

Signal

3

,

TFO

Pin

.

A33l

THRU PINS
Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Siqnal
SIG RET

EMDN
SMDN
FMDN
HOYVN
G2VN
CDN
GGVN
HOYV
TMVN
CD
G6V
PR6N
G5V

Pin

Signal

V3
16
ZDHN
17
VOYVN
18
19 ' PR6
ZDLN
20
TMDN
21
G1VN
22
G7V
23
G7VN
24
G2V
25
DTMVN
26
DTMV
27
VI
28
Y7
29
30 . GIV

NOTES:
1 , See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line {if any) Indicates Internal ULD J
Connection
4. "N..U," Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A8B

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 8)

10-21

HCYV

YS
Jt

rff
ff'

6

/i
* 7
\/itsr-

AttfM

rtf

\3P}
•tt,

M-\9

-as

O2

7X^9

46
li

yg-

zu?

*v-

rr\Af9

~\

kJ

Figure 10-4.

10-22

\A&>
C6

Multiply-Divide Element, Logic Diagram (Sheet 9)

THRU PINS
Pin

Signal

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

HOYVN
26
Y8
XI
P2VN
ZN
VI

PRN

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal
TMVN

G4VN
W8

V4MOD4
SIG RET
V3
P3VN

PR
TMV

CONNECTOR PINS
Pin

1
3
5
7
9
11
13
15

Siqnal
MR]

MR2N
MRO
MRON
AI2V
MR 2
MR1VN
HOYV

17 '

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows: A1A9A

Figure 10-4.

19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

V3
SIG RET
AI2VN
TTLV
SG2
Ql
STP
AV

OP3VN
PIVN

VI
OP2V

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal
MR1V
G7V

PAV

MR IN
XN

SG2N
AVN
Q1N
V4MOD4
Q8
OP1V

G5VN
G3V

SGI
G2V

Multiply-Divide Element,: Logic Diagram (Sheet 10)

10-23

Y£

—I7
A
5
A??

PRN

HOYVM

A
42.2

2

WS

A
14
•
A25
^

E.5DVKJ Kl
W8

^•^10

f

^— 1

Xf

~17

—| 2

C e nW

^

K1M

«l

we

A
10
Ai£>

— )7
A
14
C 3 V • ^«
A13

~)3
A '0

Kl
XI

^ A J4
-— ]7

K2N

A
Lt A Z 3

u

—T— 15

K2

2. A25

A

p

Y8

-~lio
A

—

PPM

wa

A

A

/U3

—17
A 14
&?4
"]9

g

T
A
AZ9

A
^ AH 7

PROV

TPI

|

1

VI

1

A
A30

3

1

5

DD^ikl

PR N

A30

r

A
Altt

r-8

FPO

Ac3

r
L_
r-fi

z N

3 1 = ,

10

i?

)t

1

Y4MOD4

U

XI
PR1

tt,

|
J

2

KIN

ij

V'IMOD't

—|io

11

If

•

3

A
Alb

—— i a

3

A

)"_

1 a

18

A
AH

°

I 5
Alb

Alb

~po

PR1

AH

I 5
A15
TP2

13
A
AI5

Y8
1 1

re

z 13

HOYVKI
XI

^
•

PR4N

TP3

A 14
!i A 3 1

TMV

A
10
A31
W8

~~|ir
A
li
A4

7
Y

VI

8

UL

,.

1

A

yi
L

A&

we
TPIO

PRS

-LAfcL

.
1

^ -1

~ .',

.

p A14

v.-p

*

PRfc

N

—lie
A
A7

7

3

ifc
PK6—Slj

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 11)

10-24

1

5,

A14

"19

LS
AI3

13

TP16

~I"
3

PRfe

.
5

7

All

o

>-& A

or,r

— |io

7

v,-p"19

0

7

A
At,

"~|3

1c

A5

|!C
A
A5

V!

1
5i

A

•

,.

L-^5-— '« £

"H9
A
A4

VI — I —^~|9
1 ft

11

T p tc.
5

Z6

—|IO

PR5U

1 |5
A13[
O

wa
p
TBCV—nnn
A

A13VN- -13
P1VN-

TP3
Z6

—110

THRU PINS

A 1
A9

TPfc
?

—19

VI

6

r
L
».-p

1 I 5

A
A3

~|3

u

16

3

A

1 S

A 10

"~110
1
A
A 10

ws
A

M"
P3VM

*
2

P2.VKJ

1 A

T
< I

<
TP

Pin

1

2
3
4
.5
6
7
8
9
10
11
12
13
14
15

VI-

HOYVN
26
Y8
XI
P2VN
ZN
VI

PRN

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal
TMVN
G4VN
W8

V4MOD4
SIG RET
V3
P3VN

PR
TMV

2

Yfi-

PR1KJ-

Signal

CONNECTOR PINS
Pin

Signal

2
Z6
4
Y8 .
PR6
6
8
10
12
14
'PR 10
16 . XI
18
PR6N
20
22
PR4N
24
26
PR4
28
30
32
PR IN
34
VV8
36
PR2
38
PR1
G2V
40
42
TMVN
44
G4VN
ZN
46
48
PR2N
50
PRON

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Siqnal
VOYV

PR
. TBCV
P1VN
Kl
KIN
K2N
P2VN
P3VN
K2
HOYVN
PRN
PRO
AI3V
PROVN
PROV
ESDV
ESDVN
TMV
PR 2V
TFDVN
PR2VN
AI3VN
TFDV

NOTES
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A9B

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 12)

10-25

TP7
«

A

a

^*l

L *•>
1

.040
°

JUJ

•*w—f=—I1*>
TP)0

VJ

W1
OP1VN

IB

T
A7

A
AT

«1

3

A ',

S

23

13

A^MI^ — §

£*

4

EN

CP2V

ASS

A
AJ4wIZI A27

1

S_

A

-

'1V

<
jf'

G/y_?Q
17
14
13

~

IV f
fe

/a 6

13
i A
A6

——
'

1

"1"
H A
A 35

IHTV

«C

i*4

Ji

fi

W

'I5

t

=5q 7

A;/

• ?s

A
X»»

~" 1»
A tf
A 19

»J

]

£J
GSV —£\
Atv — ^J A
/>«v
'-*] MB f
B3

~~\7
A

.

S

I *\

n
\
\

2^ A»E 10

H3

JlJ

AI7 4-,
1
G 7 V —'£
.
LJ
PCV — «- At»

AIO

a

,

A
G4V

0

I

— lw
/J

y

TP 9

3

AO

*••»*

oev — 1=

?3

wry

A3s|

OP3V—2.

JZ_^
Is A.

HM

j 1

A

~in

•2 — 1

A.

3 / 5

14
A
A 12

^

G /Vw — £L

TBCV—<-£ A
OPZVN—*- A34

/*

AT~TMCV
T 1C

17

.,

VI

1»
/I
-4 1/

1^

BW— &|

K3

t

A l » --'

rL «

1

J.

A
1- A3«

C»k

TP4

~l'

v

n
J

G3l/A/-^-

>v

T

V1

P^V ~7T

fj

OfiVN

)J
A 10
i- X^i

A
A33 5
A
A 32

1

(7 1
-i
JfJ A I4_
ti| >«2<

0*?kW
OP4W

» X33 8

,-Jf
f t
^ /<3/

OP/K
QP3VN
PAV
OP)KN
OP4V
«i

S-,

i^ 1

SHf V—il

to

i A 14

X ^

C5TV
£3

'

H

AVW— 1& 5 V W — f-

F3VN
X3
AV

E3 -

J

A13V--J-

X3
t,.^u

usivu
\ii-**\i*i

r
—i

— 17

|3

?.

PAV

AM*/

TP17

'

13

O/>2/

j

s

A

^J A «
A25

OP31/W—2

»

w

A

1— •— 1
OP3 V»V
;£
flv — if A
AI4

'e^Z

\1Z
n

- — '
— - AMOM
A5.

Z3

Z3

J3

1

.

1

if

A21

I]

A

A

A
AS

rac^ — ^

AZ8 «
A

w
>

A

SHFV — *- - QftDVI

*24

~\•P6

Figure 10-5. Add-Subtract Element, Logic Diagram (Sheet 1 of 4)

10-26

'

S_
<*4

/£g

/

1

|7

2.

...

A
A MOV — '^

*• 7
A3

[ra

I

MC
c

'"'

TP*

ZER

ZERW

CONNECTOR PINS
Pin

THRU PINS
Pin

1

2
3
4
5
6
7
8
9
10
11
12
13
14
1,1

Figure 10-5.

Signal

ZERN
A1V
AI1V

G4V

OP2VN
CSTV
ANDN
AUN
AI4
OP4V
PCV
BN
TBCV

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29

ACCO

30

G5VN

G6VN
RAC
PAVN
OP1VN
OP2V
AI3V
C
CN
OP3VN
B
G3VN

Signal

Pin

Signal

1 SIGRET
3 V3
5 PBV
7 AVN
9 TRSVN
11
G6V
13 TRSV
15 A2V
17 AI2V •
19 TBCV
21 TTLV
23 Q8V .
25 OP4V
27 IOREG
29 PIOV
31 G2VN
33 Wl
35 G1V
37 G6VN
39 X3
41 VI
43 ZN
45 G5VN
47 G7V
49 PAV

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

PBVN
OP3V
CSTV
G4V,
A5V
SHFV
A6V
Z3
G7VN
'PCV
OP4VN
G5V
V7
INTV
G1VN
P3VN
AV
HOYV
VOYVN
EXMVN
OP1V
OP3VN
G3VN

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A10A

Add-Subtract Element, Logic Diagram (Sheet 2)

10-27

TPK

Y4M0DJ

t

[
OL.44

AI3M

AI3
V4MOD3

NOTES:
I . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: Al A10B

Figure 10-5. Add-Subtract Element, Logic Diagram (Sheet 3)

10-28

TP*

ypia
V4MOD3

/ICC IN

V4M003
•ACC1

DL3I

HOFC1V

CONNECTOR PINS

TBCK

THRU PINS
Pin

1

2
3
4
5
'6.
7
8
9
10
11
12
13
14
15

Signal
ZERN
A1V
AI1V

G4V

OP2VN
CSTV
ANDN
AUN
AI4
OP4V
PCV
BN
TBCV

Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal

ACCO
G6VN
RAC
PAVN
OP1VN
OP2V
A13V

C
CN
OP3VN
B
G3VN

G5VN

Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
OP2VN

OP1VN
ACCO
ACC1
UTR
DL44
PBV
SHFV
AUN
TRSV

PAVN
AI1V
UTRV
HOPC1V
DL31
ACC1V
WN
A1V
A2V
AI3VN
OP1V
AI3V

Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal
PIOV

PCVN
OP2V
OP3V
Y7
Wl
VI
X3
AION
23
V4MOD3
AI2VN
AI1N

AI2
AI3N
AI2N
AIO
AI2V
AI3
All

SIG RET
-3VDC(V3)

Figure 10-5. Add-Subtract. Element, Logic Diagram (Sheet 4)

10-29

TSR — TT ( \ #
MA, 0 V — ^ A3)\
r6
jr

7BP
MQQ y

f
2. 433

Xi

A

t

'

c;

V4MODI —\ —

L«

XI

$'f

/«
nit—*- /f/J
xt
—i j

«•

^^^

r

A

s " /

\

*J*

A»\

Ti'iiv — <~

i-i
r ,6-: ^-

~1»

1

» '•"
— \lt

i

#1

TKIJN

X

id

3

1

s

yfMoez —J —

Vs.

Y6
T '*

V4/XOD!

~\}
A
li
S. A5

jfia

1?
jS

L

4
All

1—i J;/

—

T-

1

i»

WJV MMOC2 —1

r

-1

ni

— \'* 7
A
A 4 *,

T ft 11 ON — —

S

n
(

ft

- AZ

Hfl

— \'

/ 5
^ ^-^-Wj

'^^
7

Alf

^

~\ 9

A IO

A3

^
"•

|

— \/f
A
7
Afl

A
—1 1

p

•-'*

j

r s

••

AJO

,.,„
r/r

/fjtf"

^

h
K

~l^
'~F
Ls A

.
'

Af)

/-e
0

/''^K — ^
^
CJCA'

~~\3

A

A^3
A

6^K — ii

Ae

r6
A

61 VN — '* Alt

6

A
All

1*

Ali

>»/«
7

r1^,^—



A

7

T
e»»
U—
rs
TSR
—Li
>• J±

VI

'

L7L — *""

A

— \io
H-

—| 7
A 14

—e

IPII
o

\>9

*l

SRTK

Tl/>

/,V5

i£-.

14

—\i
A It
/neof — — All
13
—|J

10

—I s
1 6

A

A/6

Xi

a, '7

" "-"

~~\l

U A 19

MAOV

~~p

T

u ™ — ^AA }4

T/iliZ

TSK — -4

,

A
10
A IS

r
"—

7/

A J
Al<-

Xi

W,

T

VI

A
A IS

.S.Y'."!

/<^
r~1 J

10

•*•

wi
1*

Xi

~IJ
r /

A

Any — "

-*•

MSOV

An
~\°

r
i

A
14
~^
Ait

6 A 61 1

If

fy

 J*

~~\3

Bf.BIC

'e
ASV

^ — ^— \ 7

Y6—TT-"1 7

e*A ic —'-£

7

KUfJi'

A
Af3

<^
a;X>/V

,«.?3

s

r/5/
<

1

"n
^j
a
s
\
£J

j*1^^- .,..^j~ "~i

C/i/^ —& /

/

TJT-M
ri

, IAS
ix ./«? 1 ,
4 V

7

Figure 10-6. Transfer Register Bits 10-TRS and Control, Logic Diagram (Sheet 1 of 2)

10-30

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A11A

A

7

TfIS

"
VI

—\3
8 A
Al

VI — I

1 a_

J

I i
A?

3

I .
At

~\9

At

rt

—\/e
A
7
At

Yt

777

n

-— |J
A
1
A IS
A

GIV

*—17

'A
A3

'-f

A

ft

— 17

CDS

A
*• AH

PdV
C.7VN
dlVN
VI

—<*•

*'

Tt13DH
°CVN
I

fe
^

,
•*

Sf ?rxv

— s A^ ^

TRW

a 1

S
1

Ib

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

G3V
RUNV
RUNVN
G3VN

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Y6
OP2V

EXMVN
CLTR
G2VN
TRSN
HOPV

TRS
SHFV

TR13
A6V

PCY

& A3?

*//

^

TRIO
BRB12
BRA12
TR12
TR9D

X2
TR9DN
TR11

C

p3—-43^-

V4 MCUi —

19

1 al A \
\ A *-*

zs — — 17
*^

.= 1 s
i

AJ

|
THRU PINS

f£ A 'f

Signal

ft
AB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
AV
G7V

^M

— 15
j

BRB11
A5V
BRB13
MBOV
8RB10
BRA 10
BRA 11
MAOV
BRA 13

ij

Pin

A
Al

Signal
AI2V

H O f t —L-f- u

n
i.

Signal

—I 9

"~t

67 y

JTI

— '-h A f

TRII —^ >,,
3

j? A
f16
— A14

f

fAf

TP t£

T "I'SH
T".no

5
=2 A 15

C2SH
GSv

n

1

—| 7

A
AH

G£ VN

CONNECTOR PINS

Pin

i
/>!

"

5/f 7KN

PAV
GIV
G1VN
PCVN
SRTR
TBR
Wl

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal

V3
G5V
TTT
PBV
G7VN
STO
G2V
VI
X2
V4MOD2
Z8
PCV
CDS
G6VN

Figure 10-6. Transfer Register Bits 10-TRS and Control, Logic Diagram (Sheet 2)

10-31

f

PAV — 4f
S Iff,

(

/f

n>v — £•
•tl-fij

*
A30

M~ 7

s

7V

AVN
,/f

1}

-^

_J

r
i
K/-p

' AiC It

A
tit

'

\1
6 A
AM

\ / t
Givtt —IjL A
%QY — I*. Alt
f

TP/7

A3S

,

£-,
n
d

LA

/ 5
X^5

— 1*
/ ?
*34

A
A34

CA-/"

-1* 10
eiy
e *•
6J\fH — 2 A23

pcv — it ~~A~
XK — Z

i';

A 15

p^

— 19
4

wi
o
L^ /.,. i.

tf A^^
|

TSW
\A't

*tt

1}

tf^l-'ODi —1—

"19
A

U

n;
Ay

IZ,

ptvn — £•
ni

J

Alt,

•'

>/5

5

•

,„.
a/r

|7
A
,'4
Alb

rn .

£
g/>,?/
/v/A/ —/o
4V

=-

tyi
fcv

'^

A
K
2 A It

A
A3

A
2- At

VI
OP1VN

^

A£

r/v

7

VI

r
L_
VJMC3?

5 TC I'M

/*

(

2U

.

£J

TP&
<

— ^L

rrr

&6V

A

A
AS

^1
J
T
r
/ i_l

V4MOD2

A IK

A33
V4MOD2

PC/W

/ 5
AH

I
AS

/•

_JlA A33

7

G7VM
G1VM

J

All.

—I 3

U

n

A
Ai
~\IO

/J

A

—19

s

10

rj

£-

\

jj

A f,M — 8-

\/0

op^ vtj — ii
OP4Y

A
AS

GJ V,M — -JCiv - - 4-

1 10

rj

a

—\io ;

STO—&

|J
OfJV

fy

*

AVM — -%
G2V
¥1

A
Alt

7

'"a

J

I 5
A 33

T »4
A
4~- AI9
^

*1
A «J
AD

Figure 10-7. Memory Buffer Control and Parity Counter, Logic Diagram (Sheet 1 of 2)

10-32

IB

TRtr —A
SBR2H

-\>
A
Alt

'

T»/3

y

Ail ~

All

^' H—

—\i
5

- —— —

1 .P

U_

-

—i

— \7

A

'
/ fit

n
Al

—

1

/

j

f>ct>
1

/
A
A HO

.

/J

,.,,

A

7
9

IN
7

—1?
6

r
L

7

A3*

/ •

f

A

A4

A*

V4MOD2 -f—— \ 9

ze
TfllN

A

,j

—\/o
1} A

/ j

^"—\/o

PODN

1

1*

IV 1 "^

>

/6

J

—\3

\

\A

^

CKP — -fj

"

A

r

\

Tftiv — ¥; A
PDDN — '*
IB
~~\IO

r*

1

j

M

Ai&

1

"I*

a

Aft

U

A
All

*->

~~\9

PAV — —

~\IO

/}

If
U-l

CKf —'-£

Sff#2

Wl

La

A

f

1

J
Y6

Al)

16
—\ 7
TR1V —&• A »

sgKr

0

At

WN

YN
a

r
L

A
A 14

JL

V4MOW-I —— ]3

L

f

Al

u

Signal

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

OP2VN

OP1VN
SRTR
SBRZ
PAR
TR1N
OP3V
G7V
PAY
V3
SIG RET
Z8
YN
G5VN
G1VN
G6V
CBRN
V4MOD2
TR1V
G7VN
AV
STOVN
G6VN
SBRX
WN

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
. 84
8688
90
92
' 94
96
98

o

J /

.r

|3

Signal

V]
ZN
TTT
SBRY
STO
CDS
Y6
Wl
G5V
PCVN
OP4V
G2V

AVN
PBV
RDV
G4VN
G3VN
TBR
G1V
PCV

J"

\1 A*J

aA a

SBKl

^~-

FAR

CONNECTOR PINS
Pin

Jfa

A 10

—\y
4

VZON

& A
fi
<*=:=> — 2 A3O
V4 MOD 6 ~~]|0
IMa
^ A
1H/3N
— A31
DM2
CM3N

REI—§

A
A31

V4 MOD 6^—13
DM2
DM3
RED
V4 MOD 6
IMS

a.

J

3

I
A31

MTTN

REI

MSSN

Figure 10-11. Memory Module Registers, Logic Diagram (Sheet 1 of 2)

10-42

EB-—\7
DSS
j| A
M.
G1V — K
rj
S7V — Ate

DUPDN — 13

A

AI5

12i

TP8

,11

DM1

DM2

I

VI-— \a
A
-U 1 M-DMO
&.
A15

DMZN

TP5

CDSVC1VN-

G2V-

3

A 10
A17

VI-

—I9
e A
A3

TP13

IM1

VI

1

za-—17
G2VNG3V-

I 5
A3

I

A
AtO

DSS-

V4 MOD 6

J)

=rr

H

IMO

DUPIN

Tf »3
i

El

A
A3

DM3

5_

OM3N

A1O

,1

1

TF

IMBN

REI
V4MODS

|io

DMBN

IMO

-IMAN

REI

V4 MODC_—|io
DMO
RED

CONNECTOR PINS
Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
ISS
G1VN

G7VN
HOPV
MZON
PCV
ISSN

V4MOD6

G7V
G6V
DSSN
CDSV
GIV
DSS
G2V
MTTN
G2VN
VI

Pin

Signal

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

SIG RET
MFFN
OMAN
DMBN
28

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A14A
THRU PINS

IMBN

Pin

1

G5V

MSSN
G6VN
G3V
G4VN
V3
IMAN
G4V
PBV
G5VN

2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

DUPDN
G6V
G1VN

G7VN
GIV
PAV
G2V
G3V
RED
IM2
G5V
G4V
PBV
IM3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal
DM0
DM1

PCV
DM2
DM3
G7V
G2VN
REI
IMO
IM1
G6VN
G4VN
DUPIN
G5VN

Figure 10-11. Memory Module Registers, Logic Diagram (Sheet 2)

10-43

warns

W5—17

AID j

PCV

WS
053PCV-

G3VNG5V-

W5

PCV

NOTES:

G5VN
G~7V

1 . See Glossary or Index for Signal Definitions

PAV
G5VN
G7V

DM I

PCV
G4V
G6VN
DMO - S

DSIM

VI-

8

~1«

A
-- L3
A9

1

\

"

AA2

3.

Dotted Line (if any) Indicates Internal ULD
Connection

4.

"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It

5.

Prefix Reference Designations as Follows: Al A14B

[ 3 1 5

A)7

• HP1N

—i—

~\s-

U

13
A

PA17

-4-,

1
1

8

See Logic Symbols Appendix for Definition
of Logic Symbols

TPG
O

A17|
V1

2.

3

-HPI

Iz



6

f

MOP
M

M^LTV

A
A34

A 31

~|9

t,
A 3q

315
AV>

RUN

,J,

A

.__

[2 i s ,

A2G

~~ts-

u.

=1^
t^
f. ?s

3| I |5(
lA23| *

„ .. ,

RUNN

[
La.

A
-"

A1o

=*

Y1 -

~] 10

C7VN

C6V

U

TP9

A1,

13
*

>
A

?r

*
J

_
V4 MOD7CSTN

S.

s
>!V
A 2?

"

-££*-«T

Figure 10-13. Memory Timing, Logic Diagram (Sheet 1 of 4)

10-46

SINKN

SINK

PBV
G7VN

»

A

1

G G V —K A2

RD
G7VN

13
-

A

IS

2 A9

Z7—13
PCV
1 A
CSV
i
2 A.Z
G7VN
V4 MOD 7 - 9
~1
8. A

f
18

!j

3 1 5 ,

-bA
All

SYLIKl

AIO

AIO

1

3 1 5
All

SYLON

G7VN

CONNECTOR PINS

Pin

EXMVN
SVI.C1N

SYLC1N

V4 MOD 7

UTRV
SL.DN

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A15A

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Siqnol
CSTN
G1VN

HOPV
OP4V

PCV
C5T
UTRV
STOVN '
RUNN
HAL TV
RUN
• •
OP2VN
:
TTLV
INTV
SYLCI
G6V
EXMVN
X4 •
OP1VN
OP3V
TR4V
G7VN .
RUNVN

Pin

51
.53
5557
59
61
63
65
•,67

69
71
-73
75
77
79
'81
83
85
87
89
91
93
95
97

Signal

Yl
SYLON
PAVN
SYLIN

Z7. PBVN
RD
G2VN
INHBS

PBV
PCVN
TR'l 3V
G3V

XN

EXMV
GSVN

THRU PINS
Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Sianal

PAV
PBV
RD

Pin

Signal

16

PCV

17
18
G7V
•' . 19
20
G2V
21
22
G2VN
23
24
VI
25
26
SIGRET
27
28
29
30

G3VN
G1V

SINK
G4V

PAVN
XN
V3

G6VN
V4MOD7

Figure 10-13. Memory Timing, Logic Diagram (Sheet 2)
10-4-7

W3
13

SYNC-

VI—TS

vt

"=t5~

N

SYNCN

A

X4-~|10

SYMC

13 A
A4

coc-

.-U

A
AS

8

SINK

5

CMC

AB

J

r

§_

CNCN

A4
i ai
TF e

EA.C
TP4

/-

8

~~13
A

r
i
i -Is-

1 S
"— H
At 7

MAO

I5
A1B

MBO

... 3

A17

V4 MOD7

la

A
A18

3

ZS

~110

eec

EBP^^ to

^f^aiAel

h/FFVN

NOTES:
}
See Glossary or Index for Signol Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Infernal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A15B

MSSVN

Figure 10-13. Memory Timing, Logic Diagram (Sheet 3)

10-48

"—110
A

CMC — S

7

TER

A3

VI~l»
r-,
e A 1
L^ I 5
'
—-r-coc
f A3 HA3

TfS
TE.R

RE.CN

L

v,
l~

u A M^F"*COCN
PAZ

Y3-

"3"

~l«>

I

Y3
G3VN
G4V
RD

A

CNCN

—

A2 £

TP7

A J
9
A3

YNCN

Z

PAV

13
J
!g
1 A
A
14
Z

a

A
AZO

PBV

Y3

«!i

— 17
5
12.
A
iV
14
la
AM
-

G3VK4
GEV
RD

Y3
PAVW

PAV
G3VN
G4V

421 "l

— 13

2. A
10

PCV

& 2 V M — 14

Giv — 54
li
RD

XM

1

A7

A
A 7 14
TP1

~~l»

J A
P A^l
I

RDM

J

I 5
All

TIMEM

V1
I

RDMN

~!LL
19

A
La A£0

J

I 5

TIME

A20

CONNECTOR PINS
Pin

THRU PINS
Pin

Signal

Pin

Siqnal

1

PAV

2
3
4
5
6
7
8
9
10
11
12
13
14
15

PBV

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

PCV
G3VN
GIV
SINK

RD
G7V
G2V

G2VN
VI

SIG RET

G4V

PAVN
XN
V3

G6VN
V4MOD7

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Siqnal
G3VN
DMA
CNC

V3
VI
PAV
RDM

RDMN
IMA
MSS
MBO
G7V
MFF
MAO

W3
X4

EAP
TIME
RECN
COC

Pin

Signal

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

SYNC
Y3
EAC
MTT
MTTVN
Z5
GIV
MSSVN
TER
G2V
EBC
1MB
G4V
SYNCN
EBP
TLC
G6VN
MFFVN
ZN
SIG RET
MZOVN
DMB
V4MOD7
MZO

Figure 10-13. Memory Timing, Logic Diagram (Sheet 4)

10-49

W3

W3

coc —» A
FSAN —&* A3Z
IMA —
CN4C
PSA
IMA

W3~~I3
1 A
8 A32
"

14

!2

13 A IZ
AZ5
VI

H9
A

•EDACIM

HOPV
RUNVN

EIACN

3J I [5,
|A18|

—)7
- A 0,
- A) 3

O
TPS

A16

IMA

]3£

E.IAC

VI-~13
&rA
3.
- A13

EDOX

EDOY

AG

DMA-

-ty
A

I 5
AZS

—

J)

SYNC

W3-

3

AZ5

•EDAC

E.ADM

TP
i

MZO

W3
EAIM
!

!

IMA

AG

V4 MOO 7

8
V4 MOD7

i

A
§
...
^ A13
A13

L-fsr
A

A14

I 5
_a A14

...

BRAO

BRAON

W3
E.ADMN

FSAN

S

•

DMA

FSA

W3
IMA-

EAIMNV4MOD 7
DMAVN—

17
~^—

V4MOD7—I3
DMAVN
^ A 9
A34
IMAVN
V4 M O D 7 -— ]io

IMAVN

SYNCN

—

V4MOD7-M05YN

MTTVN

&

A 7
A33

r^i
A3 3

NOTES:
See Glossary or Index for Signal Definitions
See Logic Symbols Appendix for Definition
of Logic Symbols
3 Dotted Line .if any) Indicates Internal ULD
Connection
4 "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5 Prefix Reference Designations as Follows: AT A16A

[3 I
LA33

-MZSYNC

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 1 of 8)

10-50

E7
S A 14
ii
A3
VI-

EAR
DMA
TIME

a

~~P9
A

ED AC

T^

A17

13
VI - —

e

A

1Z

A1O

3

— 13
A

TP9
o

EA1MN

A1O

A1O

VI"

&.

\$
A

EAPN-J2

A
AZ

H7- 3
~l
EDACN
1 A
TIME
* A3
a

1

V1-

EDACN

-

TP7

d

T1O
A
AZZ

A
±
AZ3

VI-—)io
A 1Z
S
A15

EIACN

A
^ A15

DMAVN

V4MOD7
DMAVN) —

EAIM

!f
1

DMA —

IMAVN - —

CONNECTOR PINS

r* z -— E^OM
4
7

A3

J Is

DMAVN

DMA

IMAVN

IMA

E.APN
X

A15

-EAC

TP5

17

Pin

Signal

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

YN
MZO
ED2X
ED2Y
MTT
V3
VI
EDOX
EDOY
ED6X
ED6Y
MSS
ED4X
ED4Y
MFF
MZOVN
W3
EAC
HOPV
RUNVNEAP
TIME
RECN
COC

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal
SYNC
Y3
DMA
MTTVN
27
CNC
DMAVN
MOSYN
M2SYNC
IMAVN
IMA
SYNCN
BRAO
BRAON
MSSVN
MFFVN
M4SYNC
SIG RET
M6SYNC
EAM
V4MOD7

IMAVN

EAM

THRU PINS
M4SYNC

V.SSVN

M6SYNC

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 2)

10-51

coc

COC
FSBM

FSBN
DMB
CNC
FS3
DMB

W3 —
EBDM-

E.IBCN

EDBC

ELIBC

13

AC

0MB -

•EDBCN

y/3EBIM

1MB
V4 MOOT

e

A

L.La

A13j

i

5

AI3

BRBO

.'

V4MOD7

L|

!}
A
A14

3

I 5,

A)4

BRBON

W3

FSBN
E.BDMNI

FSB

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates rha: ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A16B
V4MOO 7DMBVN
*

V4MOD7
OMBVN

113

IMBVN V4 MOD 7 ~~11O_

IMBVNV4 MOD 7

SYNCN

SYNCN-

V4 MOD 7

MHOVN

V4 M OD 7

Ml SYNC

MTTVN

A33

-M3SYNC

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 3)

10-52

Z7

E.BDMN

EBIMN

ELBDM

EBIM

v—lio
DMBVN —

IMBVN

E.DBCN

IMBVN

E.IBCN
EBP-

-eac

DMBVN

CONNECTOR PINS

Pin

-ELBM

THRU PINS

MSSYNC

MFFVN

Pin
V4 MOO 7 - 3
2 —I
DMBVN

9

IMBVN
/^7
V4 MOD 7-—lio
5YNCN

a

A
A35

V4MOD7 -— is
MSSVN

A

A35

A3S

-M1SYNC

'1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

Pin

16
17
18

19
20
21
22
23
24
25
26
27
28
29
30

'
Signal

Pin

Signal

2
4
V4MOD7
EBM
6
8
M7SYNC
10
SIG RET
12
M5SYNC
14
MFFVN
MSSVN
16
18 . BRBON
20
BRBO
22
SYNCN
24
26
1MB
28
IMBVN
30
M3SYNC
32
M1SYNC
DMBVN
34
36
CMC
38
27.
MTTVN
40
42
44
DMB
46
Y3
48
SYNC
50
COC

.

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal
RECN
TIME

EBP
RUNVN
HOPV
EBC
W3
MZOVN
MFF
ED5Y
ED5X
.MSS
ED7Y
ED7X
EDIY
ED1X
VI
V3
MTT
ED3Y
ED3X
MZO
YN

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 4)

10-53

ff#4?
g#^2

4 14
U- 429

A
4?? *y
Yl
~~[tP
. /J A H
AH
VI
—\>o
A IZ
filS
t>

fPS

j

/

A

VI

a A

I 5 PAD/
A22

AS

|
^

3

/SIS

VI
• 0

I 5PAO?l
Atf

Q

VI —

/ 5PAE/1
48

S

\9
S

—\7

VI

\ff
A 7
AS

a

VI — j-—iV

A

$#44

& A?9

/J

A 12
A!J

J

1 SPAOS

.n

AH

ffiS

/XIT
c)

VI

A
J / i PA03.
A23
AM
VI — Jf —\?
ffMSA/—
A J4 \ AjO

vi —~~\to
\
—1
A ^

r

416

AI6

\9
S A
,19

rps
9

SW7-& *tf

VI— r— \J
K
e A.W
VI ——\(ft
a A
6fiA9 — A2S

Aft £_.

A/t

f

Bftdc

—\9
A .

tf A V

fO

vi ——\IO

**4S

A \>4
4tt\

VI

1

A9

~1(2

9

A /J
AM

\JO
IS A 7
49

\fLwL

I

\ii

VI ~

—\9

8 A
4/ff~f

to

13
r"If

J I SfA09
4/3

, fl
' ^

/

. ,.

A 12
AM

Ci

Vl
y

A

/

SPAOS

A26

A26

\fff

w A r
45

VI
—\7
6#A9N —*- A 14
aoAMf/—^ AM

vi ——\v

c)

VI
6&!/c

g A

•^—1

j

/

Ata

4/9
VI —1— \J
BMffN—*- A 90

SPAPf

VI —— \f6
ff

A
A27
X

J 1 S \
45 PAtS

fAOf

8 A

f

4K>

VI ——\ff
S

1

4f V

a
\
,
LJ

P40S

r">'S
j

\

fj * (L.
Af

\

i s PAW' ,

AH

A27
—!/•
/' —
6fi/4t3N
—?1 -*

\vi —— \J

\S

a A

AS

/.yy

SfafJ

rsrr
\ ,

n>/i 7

A 19 ^-,

ft

/e^/tev —\A34

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 5)

10-54

/ SfHOW
46

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U. Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A17A

rtJ
A
412

ft »VI-

J I SK4f4\
All

S A 14
AI3

—\io

a

A 7
AI2

?/

e

TPI4

—\9
A

CONNECTOR PINS
Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33.
35
37
39
41
43
45
47
49

Siqnal
BRA4N
BRA2N
BRA3
BRA4
BRA1

BRA2
BRAS
BRAIN
BRA3N
BRA6
BRA8N BRA6N
BRA5N
BRA7N
BRAS
BRA7
SIG RET
V3

VI

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

BRA12
BRA 10
PAO1

BRA12N
BRA) IN
BRA ION
BRA9N
BRA9
BRA 11
BRA 14
BRA14N
BRA13N
BRA 13

EAP

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 6)

10-55

VI —-~~\7
A
fffiSS-K- /!&

e#£f -eanoyt/

*• /

A
AH

&

Iff —— \/f

e/tsiN -&• AA22

rps
?I ,,,VI-

H
/

J / S PSO>
AH

—\9
e A
AS

—[7
S A t*
AW

3 I Sf8f/\
A3

>n

vt —~\ft

gagju
.
"

A jf

tj

IPS

AtS

££8-fJV

A15

A
AM

9
V
|

A
/IJ3 —— '

/•/

yt —~\ff
fffffif t3 A

//

,

g A L 1

JK33

Af6

VI—

t — \J

_£

VI

n

— \I6

A
£#£9 li 4X

£/?£?

I

SfSf!\

If/ ••

/Iff

\S
S A

A18 2—|

?
I
*7

/

Jfffffji

J /

S

.r

J3 A V
J/6

TDt?

/7S&

^'~7—\7

£#£3N —

t —~\9
sA

ffl

tr_
,
JL-\

*

TP7

t

£Q86# -£• 440

1

t3

If

VI ~~r
£#£S# —c- —A1^

—1*
S A
At/ ^

1

to

A
£fiS4 — ^ AH)
V!
~\ff

£...

VI

AS

A15

VI

ffftfff

vi——\/6
a A 7

T

j i srsM\

g A

VI ——\»

tj

A 7
/fS

*

eABffftf-^. V!

sfte/r

»« « .-» <^

effort

rf>*>
vt ——15

AIS
VI —y— I/
wen ft — A ID
anojpfJ _-£j A33
W —
~\ K>
jrj
A I?
"
A27
~l—A\? 14
A#ff>4//-&- AM
eRolw

8 A
/45

A

J

?

\VI

3 / sflea\
AS

vt

s

""!•*

A f
AIP
——\9
S A
Af 7

At

l<

-

tJ A £_
AS

/ SFB07\
A?f
'

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 1)

10-56

J 1 SfSff/0

1 ft

I I)

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A17B

CONNECTOR PINS
Pin

rt/7
o

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
EBP

BRB13
BRB13N
BRB14N
BRB14
BRB11
BRB9
BRB9N
BRB10N
BRBUN
BRB12N
PB01
BRB10
BRB12

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

V.I

V3
SIG RET
BRB7
BRB5
BRB7N
BRB5N
BRB6N
BRB8N
BRB6
BRB3N
BRB1N
BRB8
BRB2
BRB1
BRB4
BRB3
BRB2N
BRB4N

Figure 10-14. Memory Error Detector, Logic Diagram (Sheet 8)

10-57

RUNVU

THiN

Tflt

Figure 10-15. Transfer Register Bits 1-9, Logic Diagram (Sheet 1 of 4)

10-58

7V?J/V

CONNECTOR PINS
Pin

Signal

1
3

SIG RET

5
1
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

TR3

VI
BRB2
BRA3
BRA2
BRB3

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

BRB1
BRA1

AI1V
G6VN
RUNV
G7V
TR1N
MD2V
G1V
SRTR
PAV
DIN
RUNVN
PBVN
PCV
G1VN
G7VN
V4MOD2
TR1
TR2
W6
STO

THRU PINS

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Slqnol

SIG RET
TR3D
TR7
TR5
TR4
TR9
V4
TR6

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Sianal
TR3DN
-3VDC(V3)
Y4
X8

V)

CLTR
TBR
MBOV
SRTR

n

MAOV

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows: Al A18A

Figure 10-15. Transfer Register Bits 1-9, Logic Diagram (Sheet 2)

10-59

r* — -—\7
0? A 4
T'R
MAW
Y4

A
Hii AS

BFB4

i A

— |-

/«

to

<• A S
XB — —— 17

McOV

3RTR

'-i

T/?3D

-

^a —-—\J
e#ee> —|
•_
TBK
f
/K£oy — 2 I*
£•?
—IJ a

wt

A

n\
?"

»

AJt

¥\

K8
—17
BRAt, — 4 A 14
r«>? — ii
A/xOl' — il Alt

X 8 — -— 17
MAS — 77
ran — J4 /.

VI

—Is

A
/e
TKJDN — '-£ f^l
A7

A
A20

J

U A
A 14

~T f
Al

(*«

7

XB

P^ A14

£*MVN

A
7
CLTK ••'?A6
LIU VN

/TiJ

— 17

3

Y4

~~[J
£1 A

BKB7

TBK

%

MBOV

*

SKTK

4

TR(,D
VI

S All

5?

7T
'•§•

S^°"
A^/7

—-1-

Tl
(
""

A
AZ

^

J

*a
CLTK

F>
fi

~\7
A

A

J

t5

~~\'°
— Li. A
At

A
AIB

2

I
Al

INTV
G3VH
fy yfl

JIB — rr~i7

' •••
TBR
TT
NIAOV — ^ All
XS
—[J
BAB3
& A \ /e
TdK
%
MBOV
*•

—\} 8
A

li

TS>S

^

1

TK8N

it
l£

I

/

—\/o

SRTK — £i

y

X*

(3

A
AB

J

7 —1/0

j/crv? — H

xe

a rtf

All

fj

U
cs

j

n»/

I
AS

S
--TX8

n?
A
[

K*»r^ ^ —1—
U

SffTft

x U1
/«/«!

J

Alt

-f £

A
A IS

-fH

"-7-]-»
JCS

XSJiV

A
A 16

10

&•

—^
\io
A
7
All

^

Figure 10-15. Transfer Register Bits 1-9, Logic Diagram (Sheet 3)

10-60

a
?

BffA 3 —'—

VIMODi — )

— r/f7

An

4
A
%
*.Aft 10

VI
—

~A~

XS ~ -— |J

i

TRTH

/*

— 1 /^ 7
A
Ail If

GSV — &•

1

X/

iXMVN

TBK—'•£ A
MAOV
ii A l 14
EIM VN

AJT_

—i 8

AH
£o

I L
—

—\io

/J

'/T7-J

It

J

A
3-

— \3

V4MOD1 — PI— 15

La

SRTR

SH

/wt*™—'*'
ft 5f<

t
\

\

Aie\i

'"

5 />4

CONNECTOR PINS

rff

Pin

7K6OH

Tf> 9

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
3.

of Logic Symbols
Dotten Line (if any) Indicates Internal ULD

4.

Connection
"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It

5.

Prefix Reference Designations as Follows: A1A18B

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal

Pin

52
54

TR6

TR4
SRTR

56
58
60
62
64
66
68
70
72
74
76
78
80
'82
84
86
88
90
92
94
96
98

TR5

X8
BRA4
BRAS
MAOV
BRB5
6RA6

G5V
CLTR
BRB6
MBOV
BRB4
INTV
G3VN

Signal

Y4
BRA7

.

BRAS
BRA9
BRB9

AVN
EXMVN
X5
TBR
BRB7
BRB8
TR8

TR7
TR9DN

TR9

TR9D

W6
Z2

THRU PINS

Pin

Tfl

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

SIG RET
TR3D

TR7
TR5
TR4
TR9
V4MOD2
TR6

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Slqnol
TR3DN

V3
V4.
X8
VI

-

CLTR

TBR
MBOV
SRTR

Z2
MAOV

Figure 10-15. Transfer Register Bits 1-9, Logic Diagram (Sheet 4)

10-61

Z(

—C5.
12

131

TRSV

ZJ—>7
TR7V

All 13,
VI—19

p2_

TP9

,

TA

.

M-Un^

AZAN

TPC

f-E

fi
TA

TP1

V4 MODS

\ '4 V006A\N

AZN

AH

*

Y*—|to
—

EXMV

TRZV- 13

TR1V

EXMV

^l
«—110
12

TP14
B

1

A8AN
TP15

s

V4 MODS

Yf

aA8N
110

~

uAa

TA

v4Miope—up

ZJ-17
TR3V
TA
G6VN

V4 MOD 6

Al\y

AIM

i|

|1Q

.. '

4J
AZ5
EXl/DN

TA

2J^

GSVN
154
TA
G1V

5P^
TP4
'—19

p AZ5

§,

-S*
A3N

TA

Figure 10-16. Address Register and Memory Address Decoder,
Logic Diagram (Sheet 1 of 4)

10-62

21
TRCV

*• A
A£ »|
TA— &
VI"
— I9
A
.-L3JAI7[S_H_A3^N
r* AT

CONNECTOR PINS "
Pin

l._.

-Ivl-ig
A
AU

La

A
I
S A13 A13,

315
A14

Y4
-r»
TA

Y4

EXMV

2,

A
A7

13

Q

[AM

LAJ

r

Z1 —lie
AZ7

TA-^2

|A

5
7

1 T P 1 B

VI-

—I 9

r-,

A

V4 K/OD6

^4^-

A3<»

f
1

T
ASM

IS
A
|A3b

3 1 5 ,
A3S

, s
*=

AX7N
V4MOD6
AX3N
TR8V
AX1N
A2V
A1V
AX5N
EXMDN
AXON
TR9V
EXMV
Al
A2
VI

51
53
55
57
59'
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

Y4

OS 4

A8
IS4
Zl
TR1V

TR6V
A3
A9

TR2V
TR7V
G6VN
A7

1

V4MOD6 —~|IO
A1N
^ A
- A8 V

-G>A*6N

J
S.

«l

r-,

V4 MOD 6 -

~1'0

A) V

A
A2V-^ AS

S.

A
AS

THRU P.INS
Pin

A iJ
A35

TA— ^

A3V

SIGRET
V3
AX2N

Pin

—1

X* —pc

A3V

AX6N
AX4N
A3V

r~.
[6

AZV

A3N

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal

1
J
A ^ — AX7N

2
3
4
5
6
7
8
. 9
10
11
12
13
14
15

Signal

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal

S4

TA
S4N
G1V
A7N
EXMV

A8N

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A19A

Figure 10-16. Address Register and Memory Address Decoder,
Logic Diagram (Sheet 2)

10-63

TR5V
TR5V

TR4V
TPC

TA - 12
^ All
'1

VI-—| 9

XV.

A4AN

r* A 10

Tpa

V4 MODS

V4 MOD 6

..ll

A1O

5.— -H

S
/k
A 7

A4N

Y5

3

I 5,

A17

uo

XS—no

PAV - S3
AYON

CSV
AVN

AY3N

TP1O

o

N-

~~|9

A
[" A26
1
I

s.

...Li
A.26

TAM

V4 MCDG
A4 N
ASV

S

A
La A19

1

A19

s

•TA

V4 MOD

V4 MOD
A7V —

A7NI
A8N—a

_B| A
|A34

A6V

AYGN

V~no

ASM

I
^-AXCON
A34

-AX1ON

S4

Figure 10-16. Address Register and Memory Address Decoder,
Logic Diagram (Sheet 3)

10-64

Nfl— 13
8 A
A24

M

P

EXMV

civ

-ASA

1—

TPS

>!

ASN

Z2—110

CONNECTOR PINS

TR3V

Pin

2
4
6
8
10

TA-

ACAN

TP1

V<1 MOD 6
AGN

TA

V4 MOD6- T10
A4VA5N

^Aaol

A

AGN

V4 MOD G
A4N

-AY2N

A30

|1Q

2J—1~1.

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
AX7ON
A7V
ASV
AX10N
AX5ON .
VI
51G RET
PAV
AXOON
V4MOD6
AX4ON
AX6ON
TA
AX2ON
G7V
WN
G6V
EXMVN
X5
AVN
AX SON
TR4V
TR3V
G5VN
:

Pin

Signal'

52
54
Y5
56
A6
58
60
TR5V
62
Z2
64
G1V
66
AY7N
68
A5
70
72
A4V
74
AY5N
76
AY4N
78
AY3N
80
AY1N
82 , ASV
84
A YON
86
Y3
88
.90
92 ' AY2N
94
A6V
96
A4
98
AY6N

A5N—SA

THRU PINS

P-AY5N
P,'n
V4 MOD 6—310
A4VASV

ASV

AY7N

AXIOM

S4

AXBON

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

S ignal

Pin
-16

-

.-

- Signal
"''.'

'

•'.'"•;

17" • -"54 - "'
18
19
20
21
TA
22
23
S4N
G1V
24
25
A7N
26
EXMV
27
28
29
ASN .
30

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A19B

Figure 10-16. Address Register and Memory Address Decoder,
Logic Diagram (Sheet 4)

10-65

Z1-

PBV

A
All

C6V
HOPV

a

&7VM

V1-

1

A17

L
PBV

A(7

I
A

I 5, _

Aia

Aie

JA

Aia

J

Zl

(
TPS

G7V— a

A4

3
A
AS

AS

ISZ

I £.

A
1Z
AS

Z! -17

I5S—S

I5

A ..ll
A.4

PBV — -1 A
GW — a A1Z

An

G~7VN-

e

q

IStN

*

ISSGGV-

.

I SI

1

(

1SZN

1

TFSU

1

il

DS4

C4VN

A
AS

8

..U

-tr
Gj AAl
21 — ]7
DSS-— £
A
C5VN— U
£
A3
GSV

I 5
AS

053

1 5_
Al

DS3N

1

DS4N

DSS — ^

GGVN - 23

1

T ?l

G7V

VIA
AZ3

8

WN

I I

Q^i

3| I •>

|A30

CDSV

DSS

IAZS

[A30

DSSN
Z

j—110

. Jg-lio
u

J-|3

CDSVG3VN-

A M
A3O

PCV

G4V-

ru

V—19

TRSV^

A
^
AZ9

£1
VI

VI~1»
6 A
A3)

DS1
X
1|AJ:

E

ISS

A ...U
A16

-tr
A
A3

21 —110
"Iff

A
1* A3Z

3| I S
]A3Z

DSIN

DSS

__3
1

S

ISSN

X3

— I'o

HOPV-—13

A IZ
A32

TRSV

A
A?)

TPZ

»
—

rJ

Figure 10-17. Memory Sector Registers, Logic Diagram (Sheet 1 of 2)

10-66

I5
Ate
i 5,
A3

O
TP3

DSZ

DSZN

z

:^3

1

PBV

A

,

CIVN^5 A*|«»"

HOPV—* A1Z 1
I
c-,v_!3

VI

1
6
1

VI '
" 1

v

* pL

HOPV—!2^CZ,
VI

1

A
AS

3 I 5 .T_,
IS3
AS
1

1

11,—
A J
n
"V—

™^L\"
IS<;
•> A13

k

o

N

A A Z S - f i8—"*

r-J

1

Iss^3gZl
V3

-TIO_
A
*«**— AZO
if A
»
A33
Y5 —IID
A
a
AZ7

«vN=fr£J

TBRV
MAOV
EXMV

I

iBTJl

TP8
O

i

li

A£0

5

—17

A
EXMVN — — A3S

I 5,
A27

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

4 A
¥
a A34

AZB

)

..
o

"19
A ...U I 5_
D52MN
r§ A21
AZ1
1
VI
f,
1

LQ

n^iu

1

S ignal
Y5
DS4
HOPV ••
IS4
Zl
G1V
MAOV
G1VN
G2V
TBRV

MBOV
BRB8
BRA8
G6VN

BRB7
BRA7

A
A28
~)3
A

a

EXMVN

CONNECTOR PINS

PCV
G4V
G3VN
DSSN
V3
SIG RET
VI
G2VN
G3V
DSS
G5VN
CDSV
G4VN
G5V
G7V
WN
G6V
ISSN
X5
PBV
TRSV
ISS
G7VN

TBRV
MBOV
E.XMV

1

__3
1

A27

Pin

BRB7

1 A
1
* .A33
YS—|IO
A
S

— -DS1WN

1

A

TA— *

A
Ail

VI

L"-N-

Signal

^—

2|AZ4

u

TBRV — § A.
MBOV
»
u A34
EXMV
VI — ,s
A

V5- —I'o

BR

1*1

BRB8

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

T*f

z'-isH

G3V

intr

TBRV
MAOV
EXMV

Pin

&
• ISJI
IS4
AZ6

'°

Sfl

Z<-|3

3 l

AZ6

1
IS3f4

TP

A13*

A

|
1

'

A13 "T~ A13 ""

1
8

~J
a

A35

3 1 5
A28

J

THRU PINS
Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal
DS2M
EXMV
DS1MN
TA
DS1M

IS IN

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal
DS2MN
DS1
EXMVN
DS1N
DS3
DS2N
IS3
IS2
IS1
IS2N
DS2
DS3N
IS3N

NOTES:
1 . See Glossary or Index for Signal Definitions
2. Sec Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A1A20A

Figure 10-17. Memory Sector Registers,. Logic Diagram (Sheet 2)

10-67

V4 MOD S —
- ]3

V4 MOD 6 -

A3PAONI

DS1

DSIN-^
CS2N —
DS3N —

DSZN
D53N

1

*

A L

* A2Z

K

A r.
A30
V4 MOD £ —
- ]3
PAD
1
IS1
1 A
I SEN L
-3 I
A14

AYSON

EXMD-

PAD-

PADN

A3-

A3PADN

PAD
NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5.

Prefix Reference Designations as Follows: A1A20B

Figure 10-18. Hi-Y Memory Address Decoder, Logic Diagram (Sheet 1 of 2)

10-68

V4 MODS
DS1N
iU
DSZ
ft
STM
«
053N

V4 MODS

A9PADN-

A3PADN

TP3

AY3ON

V4 MODS
13
A3 PADN
8(~T~
DS1N • ^ *•
DST

V4 MOD £ —
- 17

A9PA.DN

DS1
DS2
DS3

DS:

4

^f A 1
1| AZO
«

DS1M

TPI7

DS2M

AY7ON

TA'

CONNECTOR PINS

E.XMVN

E.X.MDN
THRU PINS
EXMV-

Pin

]

TA-

2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal
DS2M
EXMV
DS1MN
TA
DSIM

IS1N

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal
DS2MN
DS1
EXMVN
DS1N

DS3
DS2N
IS3
IS2
ISI
IS2N
DS2

DS3N
ISSN

Pin

Signal

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

AY5ON
AY7ON
AY4ON
AY6ON

DS2M
PAV
DSIM
V4MOD6
IS3
DS3
TA
DS2
G7V
EXMDN
EXMVN
EXMD
EXMV
IS2

Signal

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

V]
Y5

A9

Zl
G1V

AY20N
AVION
AY3ON

AYOON
IS!
G6VN
V3

SIG RET

DS1

Figure 10-18. Hi-Y Memory Address Decoder, Logic Diagram (Sheet 2)

10-69

NOTC.I.Z
g.

J
/o C1 \

«
/4

A3V5MOD1

1

.

5

A1 r

a

I

a

14

,7 Cl 16
if
jIt
^

s
r
I" Cl •
3
-# A.I
8
/
—io Cl
j
Ii
^
14
/

14. AS

%n
/2

7

a
i
W Cl
ii
i
H

a
10 Cl
If

) Cl
.1

« Cl

7

*I4

e

i
f
t

Cl 7
Ail

-SJG RET

I

MSVBZ i

p^ fa

CZ

8

\

7 Cl &_^

*IS

TP5

r Ci

A^^

a \ n ci

6

A 13

TP«
7

C2 a
A3

f

; Ct 6
A 16

7P7

7 Cl

AZS

«

7 C3

8

\

>

Ct f
430

TP8

A 10

f

7 C3 0

An

TP9

7 C3

Alt

a I r

CJ
431

a

Figure 10-19. Decoupling Capacitors (Channel 4), Logic. Diagram (Sheet 1 of 4)

10-70

CONNECTOR PINS
7 f«f

8

[

C4 8
A IS

7

All

TP11

7

C4
ff 1
Ail

7

«

'

C4 6
til

7

C4

TPtZ
\

a

Alt

TPI3

7
Alt,

«

I >

C4
A33

a

C3

V

TPf4

7

CJ
Ali

»

1 '

\AIO\

TP15

^lf.

^py

7

CJ
Ail

' I'

CJ
AJ4

NOTES:
1 . See Glossar)
^ or Index for Signal Defini
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page Is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A3A

Pin

Signal

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

MSVB1
MSVB1
SIG RET
S1G RET
A2V5MOD5
V3
V3
V3
V3
A3V5MOD1
V5
V5
V5 .
V5
A3V5MOD3
VI
VI
VI
VI
A3V5MOD4
SIG RET
SIG RET
SIG RET
SIG RET
A3V5MOD5

51
53
55
57
:59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
V3
V3
V3
V3
SIG RET
VI
VI
VI
VI
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
MSVB2
MSVB2

.

Figure 10-19. Decoupling Capacitors (Channel 4), Logic Diagram (Sheet 2)

10-71

;
j

10

11

&

Al

e

/f 1 VSMOC •

—
A1VSMOD5

Nore. i

ft

A 1V 5 Ml 001

7

16 d
li
It A t

3
s

g

1
3
1
J

fi
_Ji
a
to
11
'+

(j

ViO

s

7

1
)
f
7

g.

1

•4

•f

to C t f
/f
f

A I V5 HI OH 3

g:

10

11

A 2 Y!, HIOD4-

ff

}

/*

S
7

a

1

14

7

—To C 7 T
li
s

o TPI
S/6

Figure 10-19. Decoupling Capacitors (Channel 4), Logic Diagram (Sheet 3)

10-72

Tfll

CONNECTOR PINS
Pin

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

TPI3

TPIS

Signal
V3
V3
V3
V3

A2V5MOD4
VI
VI
VI
VI
SIGRET
SIGRET
SIGRET
SIGRET
SIGRET
VI
VI
VI
VI
A2V5MOD3
SIG RET
SIGRET
SIG RET
SIG RET
A2V5MOD1
V3

Pin

Signal

52
V3
54
V3
56
V3
- ,
58 , A1V5MOD5
60
VI
VI
62
64
VI
66
VI
68
SIG RET
70
SIG RET
72
SIGRET
74
SIG RET
SlGRET . .
76
78
A1V5MOD4
80
V5
82
V5 .
84
V5
86
V5
88
A1V5MOD3
90
V20
92
V20
94
V20
V20
96
A1V5MOD1
98

SIG f?£T

NOTES:
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U. Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A3B

Figure 10-19. Decoupling Capacitors (Channel 4), Logic Diagram (Sheet 4)

10-73

AfYSMODS
A3VSMODS
JIPIO
(3)
(7)

AfSI-tF (87)-

NU

NU

. 13

41SHFV

1.8 CtM

t.3

>1SF~

(.Jl-

(77)

4
/ 8 NU

a

r\eJNU

j/r&taPS'SMOIO A1W4 -

NU

(57;-

-OTP/f

-*4

u

&— AISTOVN

I NU

Af

l/rlU2^-'

lj^f-H5^-w

Figure 10-20. Operation Code Voters, Logic Diagram (Sheet 1 of 4)

10-74

(«l)

/.jfNU

CONNECTOR PINS

trysts
AirsMOOs

A&S4tO03
AIM

4

NU

/y

j

NU
XJ/J1

Pin

Signal

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

A3V4MOD5

51
53
55
57
59
61
63
65
67
"69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

A2V5MOD5
A1PIO
A1V5MOD5
V3
VI
SIGRET
A1HOPV

A3V5MOD5
A2V5MOD5
A1V5MOD5
A1X1

A1HOP
A3V5MOD5
A2V5MOD5
A1V5MOD5
A1W4

Signal

A1STON
V3
VI
SIG RET
AIPIOV

V3
VI

A1SHFV
A1W4
SIG RET

A1SHF
A1STOVN

THRU PINS
NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition "
of Logic Symbols
3. Dotted Line (if any) Indicates Infernal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A5A

Pin

1
2
3
4

Signal
SIGRET
VI
V3

5
6
7
8
9
10
11
12
13
14
15

SIG RET
VI
V3 .

SIGRET
VI
V3

Pin

Siqnal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Figure 10-20. Operation Code Voters, Logic Diagram (Sheet 2)

10-75

JtVSMODS
AJVSMOD^.
A3\&*OO5

xl/OPIN

(48)

Figure 10-20. Operation Code Voters, Logic Diagram (Sheet 3)

10-76

CONNECTOR PINS
Pin

s
t)
ft

.,,nn»u

f?

(L,t)
CM) - ;. /

' >

^

NU

/O

#

N
6

n TP1

/ «l t

r*rA

>J

V AH

7 '\>

4i4NU?s

/J

»l
6I
NU //
/ J ^7

S Kf
£3

7 NU

|r

^C«

e NU ^--(,9)

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
NU1
NU2
NU3
A10P3

A1W4

A10P3VN

A10P2

A1W4

A10P2V

A10P3V

A10P1V

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

A10P2VN
A10P3N

A10P2N

A1W4
A1W4

A1V5MOD5
A2V5MOD5
A3V5MOD5

A10P1VN
AIOPJN

A10P1

THRU PINS
Pin

A1VV4 —| .

t; I" .

t°
f

NU

1
2.
3

T- (Ml ?8)
H,

7 81'
/>»r^

/y

XV'f

f »l

2 NU ^J

tf *7 ^-^/OP3V
A tO

S_ NU

-<30

kk
^_

NU /j

^< /

r

NU

^ (_48)

4
5
6
7
8
9
10
11
12
13
14
15

Signal
SIGRET
VI
V3

SIGRET
VI
V3

SIG RET
VI
V3

Pin

Slqnal

16

A3V5MOD5

17
18
19
20
2!
22
23
24
25
26
27
28
29
30

NU)
NU2
NU3

A2V5MOD5

A1V5MOD5

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows: A4A5B

Figure 10-20. Operation Code Voters, Logic Diagram (Sheet 4)

10-77

AtrSMODI
AfYSMOOl
A3¥S#ODI
AIY2

4166

4/66N .
t»7 ) •
CJ1>

NU

(3)
(7)

A*

TP9

NU
g^/^

_ it, 51, S3

-0/-PS

//r/U. fJ_

\ 1.8

^ A If
^

a?)

1.8 CIM

J NU g.

NU

NU

NU

(70

(^

.JI, S3)

\ NU i

a

(«)

13

I.

LjfNU
i4JS

a

tf—

Figure 10-21. Timing Gate and Operation Code Voters, Logic Diagram (Sheet 1 of 4)

10-78

CONNECTOR PINS

4W54tat>l
Ail/SMOfil
ASt&MOfl
A1Y2

Pin

Signal

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

A3V5MOD1
A2V5MOD1
A1G6

A1V5MOD1

V3
VI
SIG RET
A1G7VN

A3V5MOD1
A2V5MOD1
A1V5MOD1
A1Y2

A1G7N
A3V5MOD 1
A2V5MOD1
A1V5MOD1

Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91

93
95
97

Signal

A1G3N

V3
VI
SIG RET
A1G6V

V3
VI
A1G6VN
A1Y2

SIG RET

A1G6N
A1G3VN

A1Y2

THRU PINS
Pin

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3.

Dotten Line (if any) Indicates Internal ULD
Connection

4.

"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
Prefix Reference Designations as Follows: A4A6A

5.

Siqnal

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
V]
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

Siqnal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Figure 10-21. Timing Gate and Operation Code Voters, Logic Diagram (Sheet 2)

10-79

t'VSMODl
A3IKW.*

-f C
A1X3-

-f 0

/f/EXM -

m£

fjNU
SM7

C7Z)
(70)

rj

— ^/EXMV

1_
NU

4^
ifNU

NU

M>

^fNuUe—4lNu JL(?t)

7

/?/TTLV

J.4/S

zisJ

i NU

NU /j

(34)

NU .£_

(JO >

r^iu^pL^j
|_ DDI

_ _1
'

/ ^.5 N

Figure 10-21. Timing Gate and Operation Code Voters, Logic Diagram (Sheet 3)

10-80

CONNECTOR PINS
Pin

2
4
6
8
10
12
l"4
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
NU1
NU2
NU3

AUNT

A1W2

A10P4V

A1TTL

A1W8

A1TTLV

A1INTV

A10P4VN

Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

A1EXMVN
A10P4

A1EXMN

A1W2
A1X3

A1V5MOD5
A2V5MOD5
A3V5MOD5

A1EXMV
A1EXM

A10P41

Ft

THRU PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal
SIGRET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal
A3V5MOD5
NU1
NU2
NU3

A2V5MOD5

A1V5MOD5

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A6B

Figure 10-21. Timing Gate and Operation Code Voters, Logic Diagram (Sheet 4)

10-81

A! V5MOOI
AfYSMOW
A3t5*OPi
A2V2

or

A/GIN
C8T>

NU

(81*)

7P9

3 "CI 6,13. 4IGIV

NU (,g

NU

rj

j NU »i*?r n,)

rH ,

MI
^INU

hi
^

(51,53)

Atf

NU

NU

f.fJ

(80
>.S NU
A7

AMMOD3 ~
MZZ

—

J/ACC/ ~
(55) ~

. — ( 2.7 )
-oTPIl

,if

Z-",

^—/!ACCIV

/ NU

Lg_
|

L

tf—

Figure 10-22. Timing and Add-Subtract Voters, Logic Diagram (Sheet 1 of 4)

10-82

CONNECTOR PINS
JW5*fOt>/
A!i>5At00l
ASf5#ff0/
A2Y2
Jf

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
A3V5MOD1
A2V5MOD1
A1G1

A1V5MOD1
V3
VI

SIG RET

A1G2VN

A3V5MOD1
A2V5MOD1
A1V5MOD1
A2Y2

A1G2N
A3V5MOD3
A2V5MOD3
A1V5MOD3
A2Y2

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

A1ACC1
V3
VI

SIG RET
A1G1V

V3
VI

AJG1VN
A1Z2

SIG RET

A1G1N

A1ACC1V

THRU PINS
Pin

NOTES:
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates rhat ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A7A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal
SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Figure 10-22. Timing and Add-Subtract Voters, Logic Diagram (Sheet 2)

10-83

<"l/3V00;
;
2V5MOD?.
A3YZ,VOO*

Figure 10-22. Timing and Add-Subtract Voters, Logic Diagram (Sheet 3)

10-84

CONNECTOR PINS
Pin

'i
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal

NU1
NU2
NU3

A1AI1

A2Y2
A1AI3VN

A1AI3

A2W2
A1AI3V

A1AMV

AIAI2VN

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

A1AI2V
A1AI3N

A1AI2

A2W8
A2W2
A1V5MOD3
A2V5MOD3
A3V5MOD3

A1UTRV
A1UTR

A1AI2N

ftTHRU PINS
Pin

I
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
V)
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal

A3V5MOD3
NU1
NU2
NU3

A2V5MOD3

A1V5MOD3

NOTES:
J . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A7B

Figure 10-22. Timing and Add-Subtract Voters, Logic Diagram (Sheet 4)

10-85

A3VSMOP1

4/PB
(87)

NU

fJL.

.-.
^=

4/PAV

tf.W.

r.s
t
A2YSM00I
A3r5#0£t
All 2

CONNECTOR PINS
Pin

.NU

/y

j

NU f./J
AIJ

li'
7.14

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
A3V5MOD1
A2V5MOD1
A1PA

A1V5MOD1
V3
VI
SIG RET
A1PCV

A3V5MOD1
A2V5MOD1
A1V5MOD1
A1Z2

At PC
A3V5MOD1
A2V5MOD1
A1V5MOD1
A2Z2

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

A1G5

V3
VI
SIG RET
A1PAV

V3
VI

A1PBV
A2Y2
SIG RET

A1PB

A1G5V

THRU PINS
NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line {if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A8A

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Figure 10-23. Timing Voters, Logic Diagram (Sheet 2)

10-87

(C

A3V5MQD\

in

*

tl

1

r/

;

T" NUJsJ
1C

^

70)

•

•

1C

• •.

/

1

f 5(7
_£

T

-%£\2- < NU |# ,R85

NU V

£ NU /

^. AV

X.W

^y^

( ,„
c
;

; j|/

jfjNU L/_ (8fc)

NU ,/

?

^/

NU
«4

A(•

/e
A2X3 —

(54}

— ffi NU

A2XI -

nJ"

u«

,J

NU

10

^ij

^ 1 o mi
£*_l^
\

f 'W

7 S\1

?

A. "a-*

T ™y fj

*\"f ^-*™>™
(

I

i,

NU ry
^/5

«y NU /
X^

M?,

/4

^rnn\(fci

. ,

ikr

us It
£

/ w

NU /y
4//

^ NU //
^«

V

(3,,

1

, - *!/
NU | /y
^- ^/ffj

7 SI'
-7 NU /<
4tJ

*. —^£

f

A1VI-]

[

3$
(7t,'

8)- _![ NU ho
All

I

Figure 10-23. Timing Voters, Logic Diagram (Sheet 3)

10-88

I;MR

Figure 10-24.

10-92

Timing and Multiply-Divide Voters, Logic Diagram (Sheet 3)

IA4A9BI
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

A1PR2N

Pin

Signal

Signol
NU1
NU2
NU3
AIPRON

A2W5
A1PR2V

A1PRO

A2W5
A1PROV

A1PROVN

A1PR2VN

Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

A1MR1VN
A1PR2

A1MR1N

A2Z4
A3Z2
A1V5MOD4
A2V5MOD4
A3V5MOD4

A1MR1V '•'A1MR1

MTHRU PINS
1
2

_r

NU /£

(38)

3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
VI
V3

SIG RET
V)
V3

SIG RET
Vi
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal

A3V5VOD4
NU1
NU2
NU3

A2V5MOD4

A1V5MOD4

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Doffed Line (if any) Indicates Inferno) ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A9B

Figure 10-24. Timing and Multiply-Divide Voters, Logic Diagram (Sheet 4)

10-93

TP16

osc

BFR
SHP

[

TP10

IA1

TP6
BFR
SHP

I

TP9
IA1
TP13

TP18

BFR
SHP

1

IA1

•

BOT3

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows:
A4A11A (left page), A4A11B (right page)

Figure 10-25. Oscillator and Buffer, Logic Diagram (Sheet 1 of 2)

10-94

CONNECTOR PINS
PIN

BOT1

BO1N

BO1

BO2N

BOT2

B02

BO3N

BOS

1
3
5
.7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

BOS

THRU - PINS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIGNAL

PIN

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

SIGNAL

BOT2

BOT1

BOT3

SIGNAL
SIGRET
SIGRET
SIGRET
SIGRET
SIGRET
V20
V20
V5
V5 !
VI
VI
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
V3
V3
V20
V20
V5
V5
SIGRET
SIG RET
SIG RET

PIN

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

SIGNAL
SIG RET
SIG RET
VI •
VI
V3
V3
V20
V20
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
V5
V5
VI
VI
V3
V3
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET

CONNECTOR PINS
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

SIGNAL
V5

1
VI
VI
BO2
SIG RET

1
V3
V3
BO2N
SIG RET

1
V3
V3
SIG RET
SIG RET
THERM1
VI
VI
BO1
THERM2

PIN
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

SIGNAL
V5
'
V5
BO1N
SIG RET

1
VI

1
SIGRET
SIG RET
V3,
V3
BO3N
SIG RET

1
BO3
VI
VI
V5

1

Figure 10-25. Oscillator and Buffer, Logic Diagram (Sheet 2)

10-95

CONNECTOR PINS

AJAVH

Pin

Signal

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

A2RPN
VI
A2RP
VI

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91 .
93
95
97

i

A1RPN
VI
A1RP
VI
BOS
V3
BO1
V3
1
SIG RET.

1
BO2
SIG RET
SIG RET
V5
V5

THRU PINS
Pin

Signal

,

-AJ*N

2
3
4
5
6
7
8
9
10
11
12
13
14
15

A3P

A1SN
A2SN

A2P
A3SN
ASS
A3Q
AIP
A2Q
A1Q

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

BOS

A3PN
A1S
A2S
A3R
A3RN
BO2
A2PN
BO1
A3QN

A1PN
A2QN

A1QN

Figure 10-26. Clock Generator Timing Logic, Logic Diagram (Sheet 1 of 4)

10-96

Signal .

. vs.
V5
SIG RET

V3

1
VI

i

r^i
f-Ifl

A
Alt

Li

T
A
ASS

3

A3*

f.

1 5
A35

AZS

AJPN

NOTES:
1 See Glossory or Index for Signal Definitions
2. See Logic. Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A12A
6. Asterisk indicates load resistor not connected.

Figure 10-26. Clock Generator Timing Logic, Logic Diagram (Sheet 2)

10-97

VI

—\r

A1SVN

A
AIS

V!

_.

**-*

A
Aft
BOI
VI

A
A33

—\tc „ 1

r-AIPf

•
1—I

£

MS
— 19

r

t7/>»

^

.4
X33 '—

8

VJ

At?

•

7 — -^

?"K.*'/
ff/f.5 *4AI7

A

to

~~Ty

A
A9

3

-,-

I
A9

vl

S
*-

AIPN

BOIA
VI

r

/IIP—2 A
VI

~\K

n
A2SVN

3

/

\

BOJA

I S
A27

C

z_

y —

S

A3SV

A34

\

— \'°
A
t??
i A
AZ9

L
» r -r—

„

&
1

—1

<.,tcfn'

Ij

3

t~*rnn

11

13 S4K

CFL

B01

id

AIO

__|
j

/

i

fftl*

5

XZ,?

6 7 CFL

a 2*12
A25

/t24

1

Is.

—1*
c -7

3/5

«, 7 F.FL

"

A28

-,MT
'3

'

/4

/123 12

.

(

i-J i/^

|

^''"'^

*

9 >/",

\ A 3 0 \ r./in

1

J

— 1«
42>

..
'

J

"~A31

f^

1

S'OJ/'
'^1-1—1
13

CKD

I

BOIA
VI

BO2 f3

^^^

VI —I—

AtSV

•*- A 2 I
TPI3

151'

r^

—'' TMV 0
* A5
AJS
?!,i

7
TPIt

Ms if
1

A3S

Hk' n

\TA 6

7

Y

*JS*

"Tyr

J2

Wf

It (S

11

t

"*™

,.„,
At2J

•"

. f 7^8 II

a

/«/^/V
42.SH .^^_ V TMV 13
1i. A20
A3SH

S

MV
* T19
-A

tfu

L

~^ AISVN

rrtr

rMsv

Figure 10-26.

^"s*

A,4 '^

a

/ T M 13
A3l

'^"S*

"tt

1

1"

(

10-98

10
3 A35

ao IP

A
Ail

VI

c^.

/» !£43J

A
AZ9

—

VI

* ,„

A3PPN

—|7

VI

801

A IPPN
,„

,o\

A
AtS

—1 1»
1
A

1

p^-LxjJw

Clock Generator Timing Logic, Logic Diagram (Sheet 3)

CONNECTOR PINS

aoi

Pin

eoj

•BOS*

*IQ

AIQP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal

VI
BO3P
V3
V3
A3PP
V3
V)
J_
SIGRET

1
A3PPN
SIGRET

A3RP
SIG RET
V5
V5

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

V5
A3RPN
A2QP
BO1P
BO2P
SIGRET
SIG RET
A2PPN
A3QPN
A2QP
A1PP
A2PP
VI
1
A1PPN
A2QPN
A1QP
SIG RET
V3
J_
A1QPN
VI

THRU PINS
Pin
A3K

A31H

A3KPN

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Doited Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows: A4A12B

Figure 10-26.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

A3P

A1SN
A2SN

A2P
A3SN
A3S
A3Q
A1P
A2Q
A1Q

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

BO3

A3PN
A1S
A2S
A3R
'
A3RN
BO2
A2PN
BO1
A3QN
A1PN
A2QN
A1QN

Clock Generator Timing Logic, Logic Diagram (Sheet 4)

10-99

t> V5MX1 •

-IB

A3V2-

NU
xJ?

1

C ?)

TP9

\I3_

^ HCI g,IS
1.8 CIM

6.13

--W(NU

-2jj/

1,8 NU;

La

1,8

/>rysi<00'fAJt'SMODtA3W2 JIP3N -

NU

/J

NU

y/^

Us

'If=r
k_^

(97)

Figure 10-27. Timing and Multiply-Divide Voters, Logic Diagram (Sheet 1 of 4)
10-100

THRU PINS
Pin
1

Signal

2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIGRET
VI
V3

SIGRET
VI
V3

SIGRET
VI
V3

Pin

Sianal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CONNECTOR PINS
Pin

4W5M00I
/WSM00I

Awssawi
A2>ra

1
3
5.
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
A3V5MOD1
A2V5MOD1
A1G2

•A1V5MOD1
V3
VI

SIG RET
A1G5VN

A3V5MOD1
A2V5MOD1
A1V5MOD1
A3Y2

A1G5N
A3V5MOD4
A2V5MOD4
A1V5MOD4
A3Y2

Pin

51
53
55
57
59.
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

A1P3N
V3
VI

SIG RET
A1G2V

V3
VI

A1G3V
A3W2 .
SIG RET

A1G3

A1P3VN

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (If any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A13A

Figure 10-27. Timing and Multiply-Divide Voters, Logic Diagram (Sheet 2)
10-101

*s*wou,

IB

A3WWO4

43*
^/MOVM—
* • d

I4A\

r-

a

\

NU

sj

( W)

—t

^

1C

Nl) 3_
4;

/ 8\r
f /*y 15
/ XfV7

7 8\t
w 13
^;
-£- >»/9

s

-

r

,y <7
/ y/f/oYvM
4^

/ //

^^/

/ NU M
^/J

,jj»

MU /y

^ NU /

NU- SJ

,„, ,

^ /VC>VV»J

NU x
4JJ

,»\ f

7gl/

*
i

^

7 NU-

^

—

158)

-,£

«x? —
,,.^.

_£_

5
rs«) — r-iyrx\1U
f &

C5ZJ — ^

t^

C\T prn

43XJ —i *
// I*'
— NU
10

.
X.

f

J_

7 //
^5

r*'r fS

^

/^r

f

6

(7t )
or/»//

r

7 8\l
II? 13
42/

4t

J. Afi

7

"u

1

X

9

7l«ir

I 7 fll

NUlii
#/5|^

-A.
•
j ^U
-i.'

^NU jj_
>*/V

NU

f42)

i41/

'

7 NU

^^ f34)

-*/^

j

7

7g|/

^/

t

a

.NU

7

NU

r

,f

NU //

e NU

x

fiB)

/

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

Signal
NU1
NU2
NU3

A1P2N

A3W2
A1PIVN

AWOY

A3XJ
A1VOYV

A1P2VN

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

46
48
50

A1HOYV

Pin

Signal

Pin

SIG RET

16
17

Signal

A1VOYVN
A1P1N

AWOYN

A3X3
A3W8
A1V5MOD4
A2V5MOD4
A3V5MOD4

A1HOYVN
A1HOYN

A1HOY

r'f

(J7)(10)

,i ,

.

' NU

1C

THRU PINS

,f

47 <,

'H,

1

7|8f r

f

}

TMV V

3 r/

I

'W
3 NU
J 4ft

f3

ff NU

./

,

/ 71 )

1
2
^

?\t\
NU

NU

•&• (38)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

18 .
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal

A3V5MOD4
NU1
NU2
NU3

A2V5MOD4

A1V5MOD4

NOTES:
1 , See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Doffed Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A13B

Figure 10-27. Timing and Multiply-Divide Voters, Logic Diagram (Sheet 4)
10-103

A3V5HOD1
/«3YZM9)-

"^a
NU

4ITFD
C3 J
(1)

AfTFDN-

-o TP9

(8f)

NU

I

-o 7X=S

1^"

a

6,13

4ITFDV

I.S

-=

6. a.

&

r.s

.W£Z~
6,13^.

(77 J

69

I.S NU
-*;*

a

NU
/*«

^7=^
siul-y

6,13
',8

j*

Lhi

6>3.

(SO

NU
47

AlV^HOD
(49•" 4rfi4JI_

; (83 —
4/ESDN-

NU

a

l£Z=r
W.--.NU

L^ZUw

Figure 10-28. Multiply-Divide Voters, Logic Diagram (Sheet 1 of 4)
10-104

15

•* NU
» -05

—4

J1ESD

^

-

tf

(.53)
_o rrHQ

i— fP
/•/w //

1422

J HCf (,'J,

4S

JTWJ

'

'

7,/£ f/tf
41
7fcc'

NU
I
2 A£4

//

?!?;?
f
^

.NU /y
^7

/ NU' f.V
41?

1
3
5
7
9
11
13
15
17
1.9
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
A3V5MOD4
A2V5MOD4
A1TFD
A1V5MOD4

V3

.. .

VI
SIGRET
A1ESDV

A3V5MOD4
A2V5MOD4
A1V5MOD4
A3W8

A1ESD
A3V5MOD4
A2V5MOD4
A1V5MOD4
A3Y2

Pin

i

1

NU

J NU rf'./i / p e l
l J
4V
7,/,S

;

CONNECTOR PINS

Pin

tiv

I

A1ESDN

V3
VI

SIG RET
A1TFDV

V3
VI

'AITFDVN

Slqnal

SIG RET
VI
V3
-

SIG RET
VI
V3

SIG RET
VI -.
V3

Pin

Siqnal

16
17
18,
19
20
21
22
23
24
25
26 '
27 '
28
29
30

^

A3W6

SIG RET

NOTES:
1 . See Glossary or Index for Signal Definitions
2.

A1TFDN
3.
A1ESDVN

See Logic Symbols Appendix for Definition
of Logic Symbols
Dotted Line {If any) Indicates Internal ULD
Connection

4.

"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It

5.

Prefix Reference Designations as Fol lows: A4A14A

Figure 10-28. Multiply^-Divide Voters, Logic Diagram (Sheet 2)
10-105

»e

*JVywQD*r ~~—'

,

\it)

^r

«rr

7

/, 7 sf
i)NU *L.
2(££/_

b*

%

NU %- (88)
AM

f 51r-2
LSI)—

fa

-OTf/

c

7

t

X?,

r
7 «r/
*s—

NU {•?
^<

w

NU

\

/ g,^

>4

5 f

—OTPII

1

a

,

»

» &\i
NU'

NU

4ft -f- (+z>

7

*y

^

7 (9IJ r

f NU

J NU _£_

413 •*- («)

7 NU

JI3

"[

-«^

. "-nT-i
) S

(
GDI

-^
10

^- (34

NU ,
^/V

.__ T
1
1
NU
1
1
J
?Jfl">

Figure 10-28. Multiply-Divide Voters, Logic Diagram (Sheet 3)
10-106

/

X/5

,

NU'

7

-ir f
IS
_£ /^^

f!

—
X

S_ NU

.

e\

rfr

ir>rr
T|-tf ?3

J /MD?V

g\f

"j~ NU
to <*tf

NU f
r

74

^

,

£

r

8)

//

rr

k

!h—*^.««

7^
/O

-r—

*rf

li1
V NLJ
3
?<

A>

*

7

/*
Xjiff

NUl^
2 JU
\

N
—,

^~

7
7_

f 4

10

sa
AS

13

T**'

f

C7?-)

1

rf
NU

x/

NU J

|A4A14B|

CONNECTOR PINS

Pin

Signal

2 NU1
4 . NU2
6 NU3
8 A1DTMN
10
12
14 A3Y2
16 A1TMV
18
20
22 A1DTM
24
26
28 A3Y2
30
32 A1DTMV
34
36
38
40 A1DTMVN
42
44
46 A1TMVN
48
50 A1TMN

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

A1MD2V
A1TM

A1MD2

A3Y2
A3W6
A1V5MOD4
A2V5MOD4
A3V5MOD4

A1MD7V
A1MD7

THRU PINS
Pin

]
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal
SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
V)
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal

A3V5MOD4
NU1
NU2
NU3

A2V5MOD4

A1V5MOD4

NOTES:
I . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A4A14B

Figure 10-28. Multiply-Divide Voters, Logic Diagram (Sheet 4)
10-107

More i.z
NU1

/

A

— Jo
'.T

NU2

/u

f-

a

;
J

10

'+

»2

7

c»
/ij

5
7

8.
~~>S"

/*

J

/

M

t

"?
li

M 14

'
c.\ i

to
J2
If-

A4

e.
/o Cl

12
ft

A5

5-

7

m

r 'f-

7

8 Cl
All

| f«CK
| PANEL
|CONN£CTION
MS V B ?

Ct
A 14

f

A" SVgf

7

Cl IO
A6

s ft

s
7

<5

6

/

—J

• SJG

RET

i

C J

a

| 7

/33

C5
»/5

a

C3
A19

a

V1

TP5

7

U.J

»J

TP1*
7 C4

AI3

a

7
]

7 04 a

>t^0

TPIS
0

SIG RFT-

7 C4- 5
AZ7

[

7

r^ a

A34

V3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal

Pin

Signal

MSVB1
MSVB1
SIGRET
SIGRET
NU1
V3
V3
V3
V3
NU2
VI
VI
VI
VI
A3V5MOD2

51
53

SIG RET '
A3V5MOD7

97

SIGRET
SIGRET
SIGRET
SIG RET
SIGRET
SIG RET
V3
V3
V3
V3
SIGRET
V3
V3
:
V3
V3
SIGRET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
MSVB2
MSVB2

55
57
59
61 '
63
65
67
69
71
73
75
77
79
vi
81
VI
83
VI
85
87
VI
A3V5MOD6 89
91
SIG RET
SIG RET
93
SIG'RET
95

NOTES:
I . See Glossary or Index for Signal Definitions
2.

See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate If
5. Prefix Reference Designations as Follows: A5A3A

Figure 10-29. Decoupling Capacitors (Channel 5), Logic Diagram (Sheet 2)
10-109

NOTE. I
AlVSMODt

u

1
)
f

e

,/

B

—ns

7

r4

A I V 5 HOD I

A1V5MOD1

,
NUZ

'f>
>f.

Cl

Ai VSMOD 7

1C

rz
i&
AlVSMODt

S
1"
li.

to

It

7

/i

a
i
a ~'j
It
S
I* . ' J,

S
1

A

7?
/^
14

I

)
f

1

i
S

'

-T -

7
/Vl/J

e

a

7

~r<>>t ci Jf '"
14
1

—M.

« 1— :
is-*
11
j

J
jr

1

10

?
f
7

a

TS—

}

it
i
J Afc /4

It
14

7

lg

/

t

t1

ifl

/i

N>

1

li

s

7

7 Ail 14

/^

14

7

14 AS 7
3

I
• 1 • J•

/

fl J
S

1
i
If *
J C 1 11

7

A/1//

7 A 10

It

J

li
11

e

ft
J C/ ,'£
7 Ail :«

e

/
" '15
j
j
l£
f> A / ?

8

or/" f

S

Alt
-

S

/j

J
J

•It

1£

AM

}4 •

5/6 Kf.T

i
TP3

Figure 10-29. Decoupling Capacitors (Channel 5), Logic Diagram (Sheet 3)
10-110

Til
CONNECTOR PINS

—3
5

Cl
A/I

* ] J'
73-*

c;
J >4/a
i

If
It

1 ^i v
i

Cl W~

'?
All 'a

'

L
T.

—^
—7
j

*— 3
C.1 W—
li
S
7
7 All 0<9

1

If
1*

a

10

li

AI3 /4

/

e

j fl 'O
f AU f£
416
/4
H.
7
!

n ro
il

J

J"

ATW*
.

VI •

5

,a

VTPtS
1 /,

73-""
Cl /;

7 A 13 /*

3
S
7

a

7 AID 1+

/

10
li
Ail 14

,e

J
77T~
5 Cl It

3
S Cl
7 A34

a
if
/•f

Pin

2
A
6
8
10
12
14
16
16
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Sianal

V3

1
NU1
VI

SIGRET
1
J_
VI

1

A2V5MOD2
SIG RET

i

A2V5MOD6
V3

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal
V3

i
A2V5MOD7
V)

1
SIGRET
1

JL
A1V5MOD7
NU3

1

A1V5MOD2
NU2

i

A1V5MOD6

10

A TV/6
o JPn

a

I

—r

Cl 10
11
7 AM ]&

s

1
J
S

7

3

Cl

'*-r—
1

3
ID
S Cl if
7 A/I n
1

a

Cl if
K
l A3S /*

NOTES.
1. Sec Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U. indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. P-'cfix Reference Designations as Follows: A5A3B

Figure 10-29. Decoupling Capacitors (Channel 5), Logic Diagram (Sheet 4)
10-111

A1Y3

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows: A5A5A

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 1 of 8)
10-112

Al VS MOD7
AZV5MCD7
A3V5M3D7
CONNECTOR PINS
Pin

1
3
;
4

LSI)

kill

.*••

K.1I

I

THRU PINS
Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Sianal

]
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signol

A1Y3
A1Y3
A1Y3
A1Y3
SIG RET
SIG RET
A1M3SYNC
A2M3SVNC
A3M3SYNC
A1M1SYNC
A2M1SYNC
A3M1SYNC
A1M5SYNC
A2M5SYNC
A3M5SYNC
A1M7SYNC
A2M7SYNC
A3M7SYNC
A1EBMV
A2EBMV
A3EBMV
EP16A
VI
VI

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
8!
83
85
87
89
91
93
95
97

Signal
EP15A
A1M7SYNCV
A1M5SYNCV
A1EBM
A2EBM
A3EBM
A1M3SYNCV
A1M1SYNCV
A3V5MOD7
A2V5MOD7
A1V5MOD7
A1BRBO
A2BR80
A3BRBO
A1BRBON
A2BRBON
A38RBON
EP15

V3
V3
A1X4
A1Y3

A1BRBOV
A1BRBOVN

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 2)
10-113

n NU

«

A >lf

A3VSMflD7
AZVSMOD7
AIVSM007 •
AllNWES

3 TP1

I A

\
* T«

1

ll I

IB i

1

7

.

T,AV
A 31

VI
A30

— MIWHBSV

NUA —

'NU
i
6

*

!i^VjJi_Nu2

A!

XP

i

Jl I
(to)

T

A

'•f

L f

J| T

7

*V

U
~7

2
4

— A2INHBSV
£,

N

«*v

"1^1"
A9

J—MIM

1-is

NU LJ
oTPg

Alt

i r.

(Sfcl

- T

Is t 7

:i

"J

,4

A1PUMN

^^

T?l<

7

iA.Z9

TMV

—

A 30

1— /HUNVN

^

|8 t 7
9,
NU U NU
. I
6 A)0
7 A3

-_ W |.

19, J0 1
INU

7
IJ

A? 2

»

VI
A23

»
1 W

\t '

I

NU
AIT

7
13

NU
A 16

^^;o

]e i
NU
c All

7

:
U

NU
A16

^

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (if any) Indicates Infernal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A5B

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 3)
10-114

IQ

W<0

CONNECTOR PINS
Pin

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

THRU PINS

Signal

Pin

Signal

Pin

A1CSTV

A1TLCV

52
54
56
58
60

1
2
3
4
5
6
7
8
9
10
11
12
13
14

A1SYLOVN
A2SYLOVN

A1TLC
A1X4

AIX4
A1X4

A1CST
A3V5MOD7
A2V5MOD7
A1V5MOD7

A1SYLON
A1Z5

*2
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

A1RUN
A1X4

A2INHBSV
A1INHBSV

A1INHBS
A1RUNV

NU1
NU2
NU3
NU4
NU5

'5

Signal

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

A1RUNVN

A1RUNN

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 4)
10-115 »

A2Y3

AlBRAO
(75>

(.77)

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A6A

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 5)
10-116

.(45")
TMI

T-II .T

J> NL HI
g A11

t-f
H>i

a
A1EAM

t TM ' 13
7
t A32

<£o™

«i ^e*Mv

J.S.'-. S
i NU13 V I
7
t A2<»

*-«M

At ^
A 2V
A>V

?j^L

^t NL
* A18

r

H_

VI 14
•
AI7

VI — i

—h
Is .1..
1
(43-)-—^_3JNLsP
1*3 O A34J
LD D I _ _ L

THRU PINS
Pin

Signal

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Si qnol

1
1

|
J

e»«

CONNECTOR PINS
Pin

3
5
7
9
II
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

S ignol

Pin

A2Y3 .
A2Y3
A2Y3
A2Y3"

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

SIG RET
SIG RET
A1M2SYNC

A1MOSYN

A1M4SYNC

A1M6SYNC

A1EAMV

VI
VI

Signal

A1M6SYNCV
A1M4SYNCV
A1EAM

A1M2SYNCV
A1MOSYNV
A3V5MOD7
A2V5MOD7
A1V5MOD7
A 1 BRAO

A1BRAON

V3
V3
A1X5
•A2Y3
A1BRAOV
A1BRAOVN

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 6)
10-117

;ZLL

AIXS

fTg NU
Ji A3Z

41

A.SVSM3D7•
A1V5MOD7AIRDM •

ffl

A1ROMM

(8JL}

TM/ 13
A1

8

32
-I F

I5IM7

IS

a,

IS]AZ4

A1X5

6

i.A8

1 . bill 5
12 A 11 IC

[N

A1MAO
(5fc>
CS+)

n

,

t '
13

I"
~~2" T
yiv
A3

oTPB

;

^

VI
AZ

7 r- H
14

AlfeJBO

, |e1 '

Z T'*v 13
6 ,4< » |

»

vr

1

y«3a

> K
l« t 7

~ ANIDII

13

i

>.

7 VI
A9

14

,TJ.

< r-|

7

-? N U 13

_g. Ai i

e

VI 1
A2 3

e

Nil
A16

(90)

,

q If 1 7
P N U 13
6 A 7

AIZS-

.
1 l« i 7
7 Nil ^4
A14

TS^i
~3?lVl8.

(7t)

? NII '3
« A: S

1
I /i
w

TPS

-)R
-? s
HT
A1 KD -

13

8

13

a

1

7 VI ^
A12

T
a

Is|l

n6 NU
A6

A1SYLC1V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

13

A1SYLIVN

A1SYLC1
A1X5
A1T5
A1X5

A1RD

A3V5MOD7
A2V5MOD7
A1V5MOD7

A1SYLIN
A1X5

7 NU

A14

14

1
2
3
4
5
6
7
8
9
10

Signal
SIG RET
V]
V3

SIG RET
VI
V3

11
12
13
14
15

Jt I\

L J

A1RDV

A1MAO
A1Z5
A2RDMV
A1RDMV

A1RDM
A1MAOV

A2RDMVN
A1RDMVN

A1RDMN
A1MBOV

A1MBO

THRU PINS

r

L)|?3

V f

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

7 NU 14

A13

LJ
^

A1SYLC1V

Pin

r

Pin
«* f fl 1

Signal

SIG RET
VI
V3

Pin

Signal

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

NOTES:
See Glossary or Index for Signal Definitions
1. S
See Logic Symbols Appendix for Definition
2. S
of Logic Symbols
0
3. CDotted Line (if any) Indicates Internal ULD
Connection
C
4. '"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A6B

Figure 10-30. Memory Timing Voters, Logic Diagram (Sheet 8)
10-119

/t/l/S AtODi-

-I/I
-18
-1C
-10

• #OOt--

AIXSJMXON-

NU'

l

07)
111).

-o TPt

(^)-

a

ifl

7

-46

e

Nl

A1114N -

1

NU

• rp/o

Mll

e v/

I.?

I 3 TAIY ij

-AtjrjVN

.

//

AlAJtlN

NU
-cTPff

-/»//? X4YN

/ //

//I J£
NU

-CTP8

(^l)

18
9TMr i*

/in

#*7

/

M:

M

Tttr

4/9

^X JPI2

£
&

— il/.<3VN

£

Alt!:

-—/«/X//KA'

-4Z4XOVN

J.?,f

.
CO

S //

7\M

7£

(55)
(S1)-

IJ

7^//
^iT

42.9

J1X 5-

•.,_J£NU
49

\4/4

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 1 of 8)
10-120

CONNECTOR PINS
Pin

Signal

Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

A1AX3VN
A2AX3VN

A1AX1N
A2AX4VN
AIAX4VN
A1AX2VN
A2AX2VN

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Pin

Signal

A1AXON

A1AX6N

A1AX2N
A2AX7VN
A1AX7VN
A2X5
A1AXOVN
A2AXOVN

Signal

A1AX3N
A2AX1VN
A1AX1VN
A1AX4N

A2X5
A2X5
A1X6

A1AX5VN
A2AX5VN

A1AX5N

A1AX7N
A2AX6VN
A1AX6VN

THRU PINS

NOTES:
I . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A7A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
V3
VI

Pin

16
17
18
19

Siqnal

A 1X6

(47,49,51,
53)

SIG RET
V3
VI

20
21
22
23
24
25
26
27
28
29
30

A2V5MOD6
A3V5MOD6
A1V5MOD6

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 2)
10-121

—

6

A3V5 MO46

J
I
\

1

f

NU /

At

4 9 ^ ——c

,m

e '\

~i 7MY
jS
'\
-i.

>J

7

7

A/X6

"ss "—

•4- fAff
IAJ0

•

"n

S

-^

ft

— r —i

2

JJ4

fr

V

4A

'2

a

<\

_s. r*7

*

jatjiia.

AW40WI

S'[

T// - — Vy r-*-*»"'3m

... \f
Jf

NU S

f /*•4

\O

i

-?—Al4X50VH

*

JtAXtOH
(88V
(.8t)

*™*IOM

* j)t

8 f]

e

f7

rj

/ . jfjiifiAvtJ

NU s

46 f
• •

oTPIO

S //
Aff

S l\

^

'1
-1 f
1}
r*

13

67

ft

N S
4 6

0rP2

a }\ .

7

>J

At.?

JMXXN -

NU /
J9 *

to

C so) \ "1

6

-C7P9

j£j >\
y TMf tf

7 f/

8

4 '•»

AIS

\ff_

,; S /[
TM? 13
i- 4 It

ft

NU r

(.^t-1
— v^.) _

AJ \t
7

o ron

"\

2 4/6
;

\

4f6

t 8 f\
A/4

t-wtie™

-i

Wy

ff

? M

&

rtJdJf?^^

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 3)
10-122

,

V

CONNECTOR PINS
Pin

Signal

Pin

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

A1AX70N

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

A2AX60VN
A1AX60VN
A1AX50N

SIG RET
A2AX40VN
AIAX40VN
V3

AIAX40N

A2AX20VN
A1AX20VN
A2AX10VN
A1AX10VN
A1AX30N

VI

A2AX30VN
A1AX30VN

Signal
A1AXOOVN
A2AXOOVN
SIG RET
V3

A1AX70VN
A2AX70VN
A1AX20N

A2AX50VN
A1AX50VN
V]

A1V5MOD6
A1AXION

A1AX60N

A1AXOON

A2V5MOD6
A3V5MOD6

THRU PINS
Pin

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of .Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A7B

].
2
3
4
5
6
7
8
9
10

Signal

SIG RET
V3
VI

11
12
13
14
15

SIG RET
V3
VI

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal
A1X6

A2V5MOD6
A3V5MOD6
A1V5MOD6

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 4)
10-123

»«
.. ? MOQ
•

f E

ft

t7

f?

'0 N U f

(S) -

t

(?) -•

^(y

/ « /I
*•§ 7>if
L ^/">

,J

f

6

7T>>



i\

7 8

,1 S /I

r* U
-A /i.'2•

f/

f

^?)

• TPIo

(70-r

f

/t/S

1

^a r*V

4 ^5

4 11

8 'I
' f1 r*tr
i 4 >?

IS

—r

/

4/4

f

r/

14

417

tt

7 H

//

it/J

-nTt

•>g

j xr-ftrf,

,
*^

f

r/

'I

rj

jfff

4 >f>

7

/f

7

f

-k. *
f

I'/
AW

a

8/
r*

$

•i

7

# t\
^iif /}

1

NU f /Ol )

;|

/* ^

ft

>\

f

47

7

r/

8

r.

V

8

i 4,'7

All

s

4I

r?

•^ AtN J•

^7

fw

$
—-«

r If ?

^

^T

e VI

'

f

T/lif 13
2 4 '4

/?//

^

(. II) '

a

1 T*ir
f 4W

7 H

8

r? 8

a>

-<

4JJ

NU f
-m
f\ /I :

/^O)

:

19 NU

•>
/J

9 />if ,3
 i

„

—-

(j7 )

'I

'f /J
1 ru

4.'0

7

w

14

A/4

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 5)
10-124

CONNECTOR PINS
Pin

Signal

Pin

1
3
5
7
9
11
13
15
17
19

A1AY3VN
A2AY3VN

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

A 1 AVON

A1AY6N

A1AYIN
A2AY4VN
A1AY4VN
A1AY2VN
A2AY2VN

21
23
25
27
29
31
33
35
37
39
41
43
45

A1AY2N
A2AY7VN
A1AY7VN
A2X4
A1AYOVN
A2AYOVN

47
49

Signal

A1AY3N
A2AY1VN
A1AY1VN
A1AY4N

A2X4
A2X4
A2X6
A1AY5VN
A2AY5VN

A1AY5N

A1AY7N
A2AY6VN
A1AY6VN

THRU PINS
Pin

Signal

1

TUP 11 (*V)'

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Referenco Designations as Follows: A5A8A

2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
V3
VI

SIG RET
V3
VI

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal

A2X6

A2V5MOD6
A3V5MOD6
A1V5MOD6

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 6)
10-125

A1VSM0D6

1*8
-sc
-fD
-f£

A3V5 #006

AWOOH

4M/T0//—
(««-

NU
-OTP£

iW
'—

4A7

AIAYWM

M
414

-16

n/irzott-

AUY4CH
(3o) _

Nil

<$ -

NU

-oTPIO

M4

Li

M

a

/j/j

^//

/UAY4MN

7S

\AI2

—A2A/30W

Mir

fJ

7

AZXf
4'AYtOft

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 7)
10-126

CONNECTOR PINS
Pin

S ignal
A1AY70N

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

VI
A2AY30VN
A1AY30VN

Pin

Signal

A2AY60VN
A1AY60VN
A1AY50N

SIG RET
A2AY40VN
A1AY40VN
V3
A1AY40N

A2AY20VN
A1AY20VN
A2AY10VN
A1AY10VN
A1AY30N

Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal
A1AYOOVN
A2AYOOVN
SIG RET
V3
A1AY70VN
A2AY70VN
A1AY20N

A2AY50VN
A1AY50VN
VI
A1V5MOD6
A1AY10N

A1AY60N

A1AYOON

A2V5MOD6
A3V5MOD6

THRU PINS
1

NOTES
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
Dotted Line (if any) Indicates Internal ULD
Connection
"N.U. Indicates that ULD is Not Installed
although Page is ''Wired" to Accommodate It
Prefix Reference Designations as Follows: A5A8B

2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
V3
VI

SIG RET
V3
VI

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal
A2X6

A2V5MOD6
A3V5MOD6
A1V5MOD6

Figure 10-31. Memory Address Decoder Voters, Logic Diagram (Sheet 8)
10-127

14

rj
430

a

A15BKIV•

a

A/TKIV

—

J^ff

A\J2

-£•

//>/

rr

V!

fl

7/V

~\
At5

A
422

•SffiAM

-S#At

0

AfSS/W
M4SA4

*•/

r
f2

A'CffRM

vr •

j

'

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 1 of 12)
10-128

CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
BRA2N
BRA2
BRAIN
BRA1
M2SA4
M6SA2
A1CERVN
A1TR1V
M4SA1
MOSA4
A1SBRZV
M4SA2
M2SA2
M2SA1
MOSAIC
M6SA1
MOSA2
BRA4N
A1TR2V
SIG RET
VI
BRA4
V3

Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal
A1TR4V
M6SA4
M4SA4

MOSAIC
A1TR7V

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A9A

M4SA7
M6SA10
M4SA10
M2SA7
M2SA10
MOSA7
M6SA7
BRA7
A1TR10V
BRA 10
BRA7N
BRA10N

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 2)
10-129

tiffS M

MM *3
13

-M6S/I5
U

A13

rr

to

A1TR3V —

TPt
o

TP2
o

rr

rr

9
o

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 5)
10-132

JISAT4

t4

A

4J4
jff

r A 7

— |/
4

j

A

434
MSSA7

JfSSafO

~~\>l

2

A

434

M7SA7

~\7
4

417JAW

~~\J

f4

A

rr ——\7
Ai TKIOV — ^ A ^-|
413

n
f2\

A
Aisatiy-L 414

rt7/7
c•\

>

436 ~\

rr —~\9 / I
4
p4JS

Jl

iss

S-

A
AtceRM M. 421

- gtBflf

1

1 W'~\9
4

y f
438

426

CONNECTOR PINS

1
3
5
7
9
11
13
\5
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
BRB2N
BRB2
BRB1N
BRB1
M3SA4
M7SA2
A2CBRVN
A2TR1V
M5SA1
M1SA4
A2BRZV
M5SA2
M3SA2
M3SA1
M1SA1
M7SA1
M1SA2
BRB4N
A2TR2V
SIG RET
VI
BRB4
V3

r^-

A
421

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

A2TR4V
M7SA4
M5SA4

~\f
0007

/3
t?

w —~\9 ~\
(_

LA

/

420

W
)
~]'<
to
A^T/t7^ —£ 4
427

4lf£KM J2-

tJ

A20

A27

A2SBKIY —7_ 4

X

420

— ]/
4

Pin

?

4J7

\ &

4
414

rf

-*{L*f

f

4f4

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A10A

M1SA10
A2TR7V
M5SA7
M7SAIO
M5SA10
M3SA7
M3SA10
M1SA7
M7SA7
BRB7
A2TR10V
BRB10
BRB7N
BRB10N

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 6)
10-133

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 7)
10-134

CONNECTOR PINS
Pin

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal
BRB13N
BRB11N
BRB13
A2TR13V
BRB11
M7SA1 1
M1SA11
M3SA13
M3SA11
M5SA13
M7SA13
M55A11
A2TR1V
M1SA13

M5SA8
M75A8
A2TR8V

Pin

Signal

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

V3
BRB8
VI
SIGRET
A2TR5V
BRB8N
M1SA5
M7SA3
M1SA3
M3SA3
M3SA5
M5SA5
A2SBRYV
M1SA8
M5SA3
A2TR3V
A2CBRVN
M7SA5
M3SA8
BRB3
BRB3N
BRB5
BRB5N

NOTES:
1 See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A10B

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 8)
10-135

410S/I6

13

MffMf-

vi -

VI-

io
,m
A??

A/TRIV

13
TPI

AtCBftVH

W-

~~|9
a A
A2-)

\
VI

VI

nLJI

J

i *-i A^9

BRA&tJ

VI-

T

Ie

e A

A

A 22

Ail

I—

AST

1

I5

a

~v

A 2

A9

—\7
A

14

All
~\V

A

13

All

VI
A/PAftV

/3

/_3_

vl

~~I»
A 7

An

TP**
o

A
A/O *|

~~|9 J

e A

AlO

3|

T

6

\AIO

VI ~\9

e A

An

1

Art]

\S

,L
BRA 14

'

VI — \ 9

a A
A 16

/ s

Ate

BRA HP

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 9)
10-136

•BRA'S

AirK/ZV

A1SBRXV

TP/8

AlCBfiM
VI

—1»
a A J
A 28

VI

~l»

a A

A35

J

r

f

i5

45S

a**/:

CONNECTOR PINS
Pin
\
3
5
7
9
\\
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Signal
BRA9
BRA6N
BRA6
A1TR6V
BRA9N
M2SA1 4
MOSA14
A1TR9V
MOSA6
M4SA6
M2SA6
MOSA6
M6SA6
M4SA9
M2SA9
M6SA9
BRA14N
V3
VI
BRA 14
A1PARV
A10BRVN
SIGRET
BRA14P

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

Signal

M6SA14
M4SA14

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A11A

M6SA12

MOSA12
A1TR12V
M4SA12
M2SA12
BRA12N

A1SBRXV
BRA 12

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 10)
10-137

14

A

4

Z

A3O

xyjj"A 6

—\fc

A

}

A4JS49

— 17

A

13

A30

M5SA6

M5S49

— |/

"A

9

~\k
A 13
Aft.

2

430

/tf7SA6

~\7
A

417S49

— jj>
4

14

-423

VI
AtSBRXV

7

AiTP&V

A
AZ3

A

VJ

VI

a
VI
8

~\9

A
429

T
A
A2Z

—17

to
~1

•?9

J

A1'3 /J

AICBKVM — — A1
A2 )

2

X?/li

—1/2
9

t4

AtC,

"n
J
—'
r

/<
/3S

A2.SBRXV

£

JiJ

TPI

7"X
JZCBW^2 XI
, '
< '-:
/1/5

'VI
3

r

S

j

5

AZ2

_„.

—15

«

I

J

X ^
X/5

kT ~|9
^ x5
46

3 / 5
AfS

I

xs

5

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 11)
10-138

Jf/J/l/S •

— }//
A />

MJ5/I/Z

—\r

A3*

«W4

~\f
A

13

A

x)9

'4JS4f4

A21

MSSJ/2

—\j

A 2
49

KSSAU

~}fS
A

_

M7SAr?

— jj.

14

A

AH

A

V)

VI
13-

S

fl

—| 7
A 6
A34

—|W
13

A

7

7

A/7

13

A

tz

/

A/0 ~|

VI
a

rp<-'
o

AZCBRVU — —
VI

~\9
J
A
A/0

.3-

r

S

8

IS

A
AZB
x)
AZB

VI
IS
All

A
A, 7

A

AT;

1
J
Z±J

0

—] 9 / 1

AIO

vr T
a

2

All

t
~\k

M7S/I/4

/J

A21

~~\7

A

A*

e

^

3j

7

S

BffBIZH

|>4?«

~l*
/

7

-4J5

X35

5

,

B&BI2

VI — \ 9

a

Is

A

Ata

Aie

CONNECTOR PINS

Pin

Signal

Pin

Signal

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

BRB12
A2SBRXV

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

SIG RET
A2CBRVN
A2PARV
BRB14
VI
V3
BRB14N
M7SA9
M3SA9

BRB12N
M3SA12
M5SA12
A2TR12V
M1SA12

M7SAI2

NASSAU
M7SA14

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dorted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A11B

M5SA9
M7SA6
M1SA6
M3SA6
M5SA6
M1SA9
A2TR9V
M1SA14
M3SA14
BRB9N
A2TR6V
BRB6
BRB6N
BRB9

BRBUP

Figure 10-32. Memory Buffer Registers, Logic Diagram (Sheet 12)
10-139

41 VSUODt •
4?&MODtA3\/SMOO •

-ia
-ic

(as)

HO
NU
41

NU

•orPS

ras;-

c

rW

~f TMY

-

/J

4wr

?W

76\!

.NU
AS!

7

NU M

1
NU

(5)

/J

<*NU

X-

8l

.NU
_z A34

NU
4J5

All/OKI

tll'MW
(73)(TSlr

-OTP/0

h^-r55)

NU

iff

JICNAM

JNU

NU /y

NU

y- can
fT9)

NU

if
NU «

an

£ NU

Figure 10-33. Address Register and Memory Module Register Voters,
Logic Diagram (Sheet 1 of 4)
10-140

CONNECTOR PINS
Pin

r?
(37) ——\
(39)— »

1
3
5
7
9
11
13
15
\7
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

I

14,

,i NU sj
to 4^
OTP3

s 7 SI/
-7 Uir
i AU

a

7 S\f
Nu 1
7 i
^ (V|

«L

7
.? t\ u
i A /;

(89)— •

a

AS

/|NU"| 14 ftT-f
|^/tf

|^

,

,

7 NU ,*
.
^/y
"'^

A1A7V

A1A7

A1A9V

A1DMAVN

VI
V3

SIGRET

A1A8

A1A9

VI
V3

SIG RET

Signal

Pin

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

A1HOPC1
A1A8V
A1IMAVN

A 1 OMAN

A1HOPC1V

A1IMAN
SIG RET
VI
V3

THRU PINS

(/9
fn) —~""1

a

f ff / j*j 3i >

Signal

Pin

!£.

Ni j f
10 4 7 6

'TPIL

.

1

|; ni

r*f r a

I/i>f

k

a f/ / JUM/IVN
j 10
j

r \i
2

N U /J
X rg

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15



/

SI NU //
J X<'/

x' NU //
W

Signal

SIG RET

VI
V3

SIG RET

VI
V3

SIG RET

VI
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal

A3V5MOD6
(74, 2)
(4, 6)
(4, 6)

A2V5MOD6

A1V5MOD6

,6;r)

NOTES:
1 . Sec Glossary or Index for Signal Definitions
2.

See Logic Symbols Appendix for Definition
of Logic Symbols

3.
4.

Dotted Line (if any) Indicates Internal ULD
Connection
"N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It

5.

Prefix Reference Designations as Follows: A5A12A

Figure 10-33. Address Register and Memory Module Register Voters,
Logic Diagram (Sheet 2)
10-141

4/VSMOD6A3VSMOO6 '
(•79)
tt,

Ob)

-OTfJ

4

ft

41 At

NU

(581

w~

NU
4}

(98)
—orrg

w
— JIAIY

*]!

NU

a

7

W

•4jNu14

7

(34)

r—n
tf.NUl/_
"^//|~ (30)
(0
\
I IAMJI—aLM
*u!
LP?JZ_
_~ J
I- f48J
(43)

Figure 10-33. Address Register and Memory Module Register Voters,
Logic Diagram (Sheet 3)
10-142

/)S-

BfC J-

A1A3

NU
AS

-OTP3

ma
AN

lit
i fj
NU

CONNECTOR PINS
Pin

a

J—AH3V

NU
AJ6

w

NU a

-!— (18)

(14)

-OTPIt

1
J/JsF
_ 2 TMV a

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Signal

Pin

52
54
56
58
60
62
64
66
68
70
-72
74
76
78
80
82
84
86
88
90
92
94
96
98

A1A6

A1A3V

A1A5

A1A5V

A1A6V

A1A4V

Signal

A1A2V
A1A3

A1A2

A1V5MOD6
A2V5MOD6
A3V5MOD6

A1A1V
A1A1

A1A4

THRU PINS

NU
JtS

a

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A12B

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
VI
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Siqnal
A3V5MOD6
(74, 2)
(4, 6)
(4, 6)

A2V5MOD6

A1V5MOD6

Figure 10-33. Address Register and Memory Module Register Voters,
Logic Diagram (Sheet 4)
10-143

AZZff

A1CBRW

00

NOTES
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U. Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A13A

Figure 10-34. Transfer Register and Memory Module Register Voters,
Logic Diagram (Sheet 1 of 4)
a

10-144

THRU PINS

Pin

1
2
3
4

Signal

SIGRET

VI
V3

5
6
7
8
9
10
TM

1
TO

NU

> -

1

7|«l'
T"MIS 1 3

7 Jl'
.f K^

/
—

;$

7 /y v
*a

^ fiffTfn

^
7?i
NU //

J

w«
"fix. w

^ .-^

7 NU //
^yj

*!'
«T

7
Nultf

..„„.

(88J

/5

» ^.' . vr

2

^5-

<*!•

fy

'/

7

(98)

x- NU r/

,-,„,
"" "

X?.V

el1
•«r
-,
—il

1

fjf

XV

si
NU /y

3NU fj
~^T' V

f44)

, MI

£ NU r
X/V

~i

10 » . ,,r^

NU r0 * >z^

'

Figure 10-34. Transfer Register and Memory Module Register Voters,
Logic Diagram (Sheet 3)
10-146

/-a^i
'^

CONNECTOR PINS
Pin

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

A>

Signal
NU1

NU2
NU3
A1IMBN

A1MFFVN

A1DMBN

A1DMBVN

A1IMBVN

A1MSSVN

Pin

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Signal

A1MTTVN
A1MFFN

A1MTTN

A1V5MOD6
A2V5MOD6
A3V5MOD6

A1MZOVN
A1MZON

A1MSSN

THRU PINS

Pin

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A13B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Signal

SIG RET

VI
V3

SIG RET

VI
V3

SIG RET

VI
V3

Pin

16
17
18
19
20.
21
22
23
t-i
25
26
27
28
29
30

Siqnal

A3V5MOD6
NU1
NU2
NU3

A2V5MOD6

A1V5MOD6

Figure 10-34. Transfer Register and Memory Module Register Voters,
Logic Diagram (Sheet 4)
10-147

xJ / vSMODf •

•Vi?
•vt

A3\/SMOOi '

f85)

To

NU 5

NlTU

. f67)

(33V

/ £!/

/a

4lf-iJS.<>

m

NU

NU

—

i
NU

(S)

A ITK9V

0 NU

^-(5
f€3)

.

/ NU -v- .10_1_ 5
xJjj"
v- -

?
^

^1U /y

^

NU

/

£ J2

fo/\

?& u

a NU ] / (-56,

NU

A/./I

/

/*/

>f//'^5

NU s
^ I6—-oTPIO

-n«y
[ SI

1
<*

NU /.,-

f

£

^5

/*/..-.»

<$• NU /

7 VI #
A,0

7 flF
hfjNU /y
7

-„,,

A/rvfv
*' I**'

;

,,,,

/NU v

IZJ^//

V/^"

r

^~ :

1

' (24)

—;
tOff-f^~n

'

w '

.9 Lv*l '

V

J xrf I

.

(48)

Figure 10-35. Transfer Register Voters, Logic Diagram (Sheet 3)
10-150

14 i f ra} V

(28)

(, dal/

f,

r]n

^JNU

Ob)

~9

'vj

7 S\f
if

7 at

^ «(/
GJ4

k,
(Llt ,-/»,*
«
s

™so

781;
NU y

a -*/'

^

<-J,TK,V

-fD

CONNECTOR PINS
Signal

Pin

2
4
6
8
AITR6
10
12
14
A1TR2V
16
18
20.
22
A1TR5
24
26
28
30
A1TR5V
32
34
36
38
AITR6V
40

52
54
56
58
.60
62
64
66
68
70
72
74
76
78
80
82
.84
86
88
90
92
94
96
98

Pin

42 '
44
46
48
50

A1TR4V

Signal

A1TR3V
A1TR2

A1TR3 .

A1V5MO02

A1TR1V
A1TR1

A1TR4

THRU PINS
Pin

Signal

1
2

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotten Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A14B

3
4
5
6
7
8
9
10
11
12
13
14
15

SIG RET
VI
V3

SIG RET
VI
V3

SIG RET
V4
V3

Pin

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Signal

A3V5MOD2
(28, 2, 78)
(4, if.)
(4, 6)

A2V5MOD2

A1V5MOD2

Figure 10-35. Transfer Register Voters, Logic Diagram (Sheet 4)
10-151

A3W4 —

e
t
10 NU
12 A f l

5
6

OTPt

.

A3V5M0D2
1 8 17
VI
J. TMV 13
t A? 9
£ A 30

A1TR12.

- o

Id
A1TKW

(35^-1

T

1 7
TMV 13

VI
A30

14.

_{ ^

r |b 1 7
iTM/ 12
A? 2

2.
-

1

IB

VI

e A23

1 7
NU|n
VI
I
A ^ 4 | 7 A23

i-Ae™

? T» 1
NU f3 NU
A17 7 A16

7

NU
A15

13

*-(*>

NU
Alt

^.

/ M

A3K5 —

A3X5-

t— I8

NU

5
£_o

A1

T»5

l»
1,
w NU
AS

S— oTP1l

,t
A1SBR7 -

(i7; —
(IT)

—i

It

rn.v

I

r

*s

VI .
A.10

9 e 1
T
13 _ VI
i, AZ
Al

AISBkt/

AlPAR—
(451- —

c*?;—'

g

J«J '-H
Thwin

i 17

^.

Ic i

A2SBRZV

TMV
A4

I

13
7

VI
A10

,4

vr

li
— A 2 PA Rv

A3

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate It
5. Prefix Reference Designations as Follows: A5A15A

Figure 10-35. Transfer Register Voters,. Logic Diagram (Sheet 5)
10-152

A3W4

A

NU
A12 *—OTP|!

iZ

. 8 NU
S—oTPI?

~ n?'L

- T1
I*!

L>f



TERMINAL AREA - El
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SIGNAL
MmSL14B
MmSL14A
MmSL13B
MmSL13A
MmSL12B
MmSL12A
MmSLllB
MmSLllA
MmSLlOB
MmSLlOA
MmSL9B
MmSL9A
MmSLSB
MmSLSA
MmSL7B

PIN
16
17
18
19
20
21
22
23
24
25
26
27
28

SIGNAL
MmSL7A
MmSL6B
MmSL6A
MmSLSB
MmSLSA
MmSL4B
MmSL4A
MmSL3B
MmSL3A
MmSL2B
MmSL2A
MmSLIB
MmSLlA

TERMINAL AREA -E 3
Pin

1
2
3
4
5
6
7
8
9
10.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

Signal
MmSTROB

TPSA14
TPSA13
TPSA12
TPSA1 1
TPSA10
TPSA9
V3
TPSA7

VI
V5
SIG RET
SIGRET
V5
VI
TPSA8
V3
TPSA6
TPSA5.
TPSA4
TPSA3
TPSA2 TPSA1

Pin

30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

Signal

;

MmSTROB

MmSA14
MmSA13
MmSA12 .
MmSAll
MmSAlO
MmSA9
V3
MmSA7

VI
V5
SIG RET
SIGRET
V5
VI
MmSAS
V3
MmSA6
MmSAS
MmSA4
MmSA3
MmSA2
MmSAl"

Figure 10-37. Memory Sense Amplifiers, Logic Diagram (Sheet 2)
Changed 4 January 1965

10-157

BRA1 —

BRA2—

a —

ID

BRB1 —

— MmlNHl

B—

BRA3 —
ID

BRB° —

— MmlNH2

P—

BRB3 —

— MmlNH3

ID

P—

,1

MmSTRPl .
••
MmSTRP2
r
MmTVC— »—

'1

TP4
)

TP3

BRA6 —

1_
ID

BRB6—

1

BRA7 —
— MmlNH6

TP11

a
BRB 7H

f

BRAS —

ID

— MmlNH7

fl —

P

f r

TP13

TP14

TP9

BRA 13 —

BRA 12—

ID

— MmlNHl 1

BRB1° —

&~~

.,

-MmlNHS.

ID

P—

,,

"

BRA 11 —
a —
BRB11 —
P —

BRB8—

ID

MmlNHl 2

BRB?3—

ID

— MmlNH13

P—

T
.

I

NOTES:
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows:
A6AMA7A1, where M = Memory Module
Assembly Number iTFirough 4
6. m Represents the Memory Module Number
0 through 3
7. n is a 1 if m is an Even Number, and a 2 if
m it an Odd Number
8. If m is an Even' Number, a =AlBRAOVand
0=A2BRAOVN
9. If m is an Odd Number, a =AlBRBOVNand
0 = A2BRBOV

Figure 10-38. Memory Inhibit Drivers, Logic Diagram (Sheet 1 of 2)
10-158

ChangecM January 1965

f

Li

TP2

iD

a—
BRB4 —

.[A6AMA7A1I

TP5

BRAS—
— MmlNHf

BRB5 —

1
D

—MmlNHS

1
B r

<- r

•

•'
TPIO

TP12
:.

BRA9 —

• • •

a —
BRB9 —
B—

10

— MmlNH9

• '•'

F /

.

BRA10—

..

BRB10—

' . - . - .

•

1D

-MmlNHlO

'

— MmlNHH

H f-

TERMINAL AREA E4

PIN

TERMINAL AREA E2

PIN

1
2
3
4
5

SIGNAL
AnM20
MmlNHl .
MmlNH5
MmlNHS
MmlNH7

PIN

SIGNAL

6
7
8
9

MmlNH9
MmlNHl 1
MmlNHl 3
AnM20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

SIGNAL

0

a
BRA1

BRB1
BRA3
BRB3
BRA5
BRB5
BRA7
BRB7
BRA6
BRB6
BRA4
BRB4
BRA2
BRB2
BRB10
BRA12
BRB12
BRA14
BRB14
BRA10
BRB8
BRAS
BRB9

SIGNAL

P|N

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

BRA9
BRB11
BRA 11
BRB13
BRA13
PWR RET
PWR RET
PWR RET
MmSTRPl
MmSTRP2
AnM20
AnM20
MmlNH2
MmlNH4
MmlNH6
MmlNHS
MmlNHtO
MmlNH12
MmlNHM
V3
MmTCV
MmTCV
SIG RET
SIGRET

Figvire 10-38. Memory Inhibit Drivers, Logic Diagram (Sheet 2)
Changed 4 January 1965

10-159

MmSTRP1

r R

E

E
MmHEYO
lAYOOVN

MmHEYl

AnAYlOVN—4 i

<
MmHIYO

MmHIYl

MmCRY

II

i >— MmEDIYl

MmEDIYO

1
1
^AmLIYl

MmLIYO
XnAYOVN

(1

MmLEYO

E

AnAYWN

( 1
MmLEYl

E

i

rH

Figure 10-39. Memory Y-Address Drivers, Logic Diagram (Sheet 1 of 4)
10-160

A r.

A6AMA5A1
E

E

MmHEY2
AnAY20VN—(

MmHEY3

AnAYSOVN—4 i

1

MmHIY2

MmHIYS

1

c r

D f
r

E

< I— MmEOIYZ

F

r

>

1

I
— p- MmLIY2

AnAY2VN-H

— -MmLIY3
AnAYSVN

I

(

:'

MmLEY2

E

1

C

TERMINAL AREA - E 1

PIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

MmLEY3

':

I
H

-MmEDIY3

SIGNAL

MmLEYO
MmLlYO
MmLEY2
MmLIY2
MmLEY4
MmLIY4
MmLEY6

PIN

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

SIGNAL
MmLIY6
MmLEY7
MmL|Y7
MmLEYS
MmLlYS
MmLEYS
MmLIY3
MmLEYl
MmLIYl

PIN

1
2
3
4
.5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

TERMINAL AREA- E3
SIGNAL
PIN
SIGNAL
MmHEYO
MmHIYO
MmHEYl
MmHIYl

MmHEY2
MmHIY2
MmHEY3
MmHIY3

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

MmHIY4
MmHEYS
MmHIYS

MmHEY6
MmHIY6
MmHEY7
MmHIY7
MmCRY
MmCRY
AAnTCV
MmTCV

PIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

TERMINAL AREA - E 4
SIGNAL
PIN
SIGNAL
MmTCV
AnM20
AnAYTVN
AnAYSVN
AnAYSVN
AnAYOVN
AnAYlVN
AnAY2VN
AnAY4VN
AnAY6VN
SIG RET
SIGRET

VI
EDmY
V3

18
19
20
21
•22
23
24
25
26
27
28
29
30
31
32
33
34

V3
EDMY
VI
PWRRET
PWR RET
AnAY60VN
AnAY40VN
AnAY20VN .
AnAYlOVN
AnAYOOVN
AnAYSOVN
AnAYSOVN
AnAY70VN
AnM20.
MmTCV

MmRDP2
MmSTRPl
MmSTRPZ
MmRDPl

MmHEY4

Figure 10-39. Memory Y-Address Drivers, Logic Diagram (Sheet 2)
Changed 4 January 1965

10-161

(B)

MmSTRP1

/B

I

f

AnAY'HWN

MmHEY4

<

MmHEYS
AnAY50VN_

MmHIY4

(C)

1

MmRDP2

(D)

MmTCV • "••

(E)

MmCRY

1
r T>,

J" E
1

(F)

AAmHIYS

1

_ ' i t— MmEDlYS

MmEDIY4

MmSTRP2

MmLlYS

• MmLIY4
Ar.AY4VN

AnAY5VN^—<

<
-MmLEY4

MmLEYS

F

//-^\

MmRDPl

(H)

MmEDEY

,,
k

Figure 10-39. Memory Y-Address Drivers, Logic Diagram (Sheet 3)
10-162

/• u

A-»

oj

\

1>

F

AnAY60VN— <

— MmHEY6

[

MmEDIYO
MmHEY7

AnAY70VN

^

MmMIVA

MmEDIYl
MmEDIY2 ——
MitiEDIY3
MmEDIY4

1

MmEDlYS

'

< >—MmEDIYZ

'

ED

—EDmY

MmEDIY6
MmEDIY7^
MmCRY

i1

MmEDIY6

MmEDEY

f
1
Mml IY7

Mm) FVA

JuLml FV7

:

F

1

AnAYTVN^— <

i

NOTES:
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows:
A6AMA5A1, where M = Memory Module
Assembly Number 1 TRrough 4
6. m Represents the Memory Module Number
0 through 3
7. n is a 1 if m is an Even Number, and a 2 if
m is an Odd Number.

Figure 10-39. Memory Y-Address Drivers, Logic Diagram (Sheet 4)
Changed 4 January 1965

10-163

,

,

,i

1 f*.

Mm SIR PI

1

E

AnAXOOVN^—< »

—

MmSlEO

AnAXlOVN—<

B

E
1

MmSlEl

i—

MmSllO

MmSlll

1 ^-~

1

>—

I

MmCRX

( 1

f P

MmEDIO

1i

MmEDM ' '

f U

MmRDP3

AnAXOOVN

1

(

»—

I

MmSOlO

AnAXlOVN—,

'

(

MmSOIl

>—

MmSOEl

—

E

E
—

1

MmSTRPl

5 J

NOTES:
1 . See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Follows:
A6AMA1A1 where M_= Memory Module
Assembly Number 1 through 4
6. m Represents the Memory Module Number
0 through 3
7. n is a 1 if m is an Even Number, and a 2 if
m is an Odd Number

Figure 10-40. Memory Hi-X Address Drivers, Logic Diagram (Sheet 1 of 4)
10-164

Changed 4 January 1965

A6AMA1A1I

8 )

MmSTRPI

(0)

.... MmRDP3

(C)

1
i

AnAX20VN— < (

__

-

MmSlE2

AnAXSOVN

1

_

(>

MmSlES

kl—CllO

>~

^—

1
D

:

-AnSYLlVN

f

(D)

MmTCV

/[)

f

1

r,

AnAX20VN H

1

« >—

MmEDI2

MmSOI2

1

AnAXSOVN—< ' (

••
K

MmSOI3

^«

MmSOE3

'

E

i— MmEDIS

1

1

I

1

TERMINAL AREA - E 2

TERMINAL AREA - E 1
PIN

SIGNAL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

MmLEX7
MmLIX7
MmEDI7
MmLEX6
MmLIX 6
MmLEXS
MmLIXS
MmLEX4
MmLIX4
MmEDI6
MmSOI7
MmSOE7
MmSOI6
MmSOE6
MmEDIS
MmSOIS
MmSOES
MmSOH
MmSOE4
MmEDU

PIN

23
24
25
26
•27
28
29
30
31
32
33

34
35
36
37
38

PIN

SIGNAL
MmEDI3
MmSOIS
MmSOE3
MmSOI2
MmSOE2
MmEDI2
MmSOIl
MmSOEl
MmEDIl
MmSOlO
MmSOEO
MmEDIO

MmEDEX

*

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SIGNAL
MmTCV
AnM20
AnAX70VN
AnAXTVN
AnAXSOVN
AnAXSVN
AnAXSOVN
AnAX4VN
AnAXlOVN
AnAX6VN
SIG RET
SIG RET
AnSYLOVN
VI
EDmX
V3
V3
EDmX
VI
AnSYLlVN
PWRRET

PIN

23
24
25
26
27
28
26
30
31
32
33
34
35
36

SIGNAL
PWRRET
AnAX2VN
AnAXOOVN
AnAXOVN
AnAX20VN
AnAXlVN
AnAX40VN
AnAXSVN
AnAX60VN
AnM20
MmTCV

X

'•

MmEDEX

flO

TERMINAL AREA - E 3

PIN

SIGNAL

PIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

MmRDP2
MmRDP3
MmSTRPS
MmSTRPl

23
M
25
26

T7
MmTCV
MmTCV
MmCRX
MmCRX
MmSll7
MmSlE7
MmSH6
MmSlE6
MmSllS
MmSllES

MmSlU

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

SIGNAL
MmSIE4
MmSllS
MmSlES
MmSll2
MmSlE2
MmSllI
MmSlEl
MmSllO
MmSlEO
MmLIXS
MmLEXS
MmLIX2
MmLEX2
MmLIX 1
MmLEXl
MwiLIXO
MmLEXO

Figure 10-40. Memory Hi-X Address Drivers, Logic Diagram (Sheet 2)
Changed 4 January 1965

10-165

(A)

MmEDEX-

(B)

MmSTRPl-

,; :

—(

AnAX'(CYN-

-

1

•

E

E

MmSlE4

r"

1

AnAXSOVN—,

I

(C)

)«

MmSlES.
MmSllS

MmSlU
(

_

;

\

»—

( h-

MinRDPS-

(D) AnSYLlVN(E)

/
MmTCV-

ff)

MmCRX-

i H-MmEDI4

(G) AnSYLOVN(H)

MmRDP3-

'

AnAX40VNJ— <

1

T

H- MmEDIS

fr
/i/

*

1

•—

MmSOU

AnAX50VN — <

I

(

MmSOlS
t—

MmSOES

—
(J)

MmSTRPl-

(K)

E7
E

1

•J i
*<

NOTES:
1. See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition
of Logic Symbols
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. Prefix Reference Designations as Fol lows:
A6AMA1A1 where _M = Memory Module
Assembly Number 1 through 4
6. m Represents the Memory Module Number
0 through 3
7. n is a 1 if m is an Even Number, and a 2 if
m is an Odd Number

Figure 10-40. Memory Hi-X Address Drivers, Logic Diagram (Sheet 4)
Changed 4 January 1965

10-167

_

MmRDP2

1 B

1
E

E

AnAXOVN-

MmLEXl

MmLEXO

< »
-

MmLIXO

AnAXlVN—-<

I

MmLIXl

MmEDIO

MmEDU

.,

1
•*

> cr
'

MmTCV
)
f

tr

•> r
1 '

MmEDIS

•MmEDU
'

1

MmLIXS

MmLIX4
AnAX4VN

(»
MmLEX4

AnAXSVN

1I

E

MmLEXS
-E

MmRDP?
I.

3W

NOTES:
1 . See Glossary or Index for Signal Definitions
1. See Logic Symbols Appendix for Definition
of Logic Symbols
..
3. Dotted Line (if any) Indicates Internal ULD
Connection
4. "N.U." Indicates that ULD is Not Installed
although Page is "Wired" to Accommodate it
5. frefix Reference Designations as Follows:
A6AMA1A2, where _M = Memory Module
Assembly Number 1 through 4
6. m Represents the Memory Module Number
0 through 3
7. n is a 1 if m is an Even Number, and a 2 if
m'is an Odd Number

Figure 10-41. Memory Lo-X Address Drivers, Logic Diagram (Sheet 1 of 2)
10-168

Changed 4 January 1965

M 1

| A6AMA1A2|
,

A „ A V OV / M

AnAX3VN^—4

..

kjmi iya

MmLIX2

Mm EDI 2

i
-MmEDEX

D >

rf r)
MmEDI7

Mm£DI6
AnAXTVN ^-^

\

C

... — MmLEX7

1

r r
H C

PIN

1
2
3
4.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

TERMINAL AREA- E 1
SIGNAL
PIN
SIGNAL
MmEDIO
MmSOEO
MmSOlO
Mm EDI 1
MmSOEl
MmSOIl
MmEDI2
MmSOE2
MmSOI2
MmSOES
MmSOIS
MmEDIS
MmEDEX
MmEDU

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

MmSOE4
MmSOI4
MmSOES
MmSOIS
MmEDI5
MmSOE6
MmSOI6
MmSOE7
MmSOI7
MmEDI6
MmLIX4
MmLEX4
MmLIXS
MmLEXS
MmLIX6
MmLEX6
Mm EDI 7
MmLIX7
MmLEX7

PIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

TERMINAL AREA- E3
SIGNAL
PIN
SIGNAL

MmLEXO
MmLIXO
MmLEXl
MmLIXl
MmLEX2
MmLIX2
MmLEXS
MmLIXS
MmSlEO
MmSllO
MmSlEl
MmSlll
MmSlE2
MmSH2
MmSlE3
MmSllS
MmSlE4

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

MmSlES
MmSllS
MmSlE6
MmSll6
MmSlE7
MmSH7
MmCRX
MmCRX
MmTCV
MmTCV
.
MmSTRPl
MmSTRP3
MmRDP3
MmRDP2

TERMINAL AREA - E 4
PIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

SIGNAL
MmTCV
AnM20
AnAX70VN
AnAXTVN
AnAXSOVN
AnAXSVN
AnAXSOVN
AnAX4VN
AnAXlOVN
AnAX6VN
SIG RET
SIG RET
AnSYLOVN
VI
EDmX
V3
V3

PIN

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

SIGNAL
EDmX
VI
AnSYLlVN
PWRRET
PWRRET
AnAX2VN
AnAXOOVN
AnAXOVN
AnAX20VN
AnAXIVN
AnAX40VN
AnAXSVN
AnAX60VN
AnM20
MmTCV

MmSlU

Figure 10-41. Memory Lo-X Address Drivers, Logic Diagram (Sheet 2)
Changed 4 January 1965

10-169

Figure 10-42. X Memory Address Diode Matrix, Schematic Diagram (Sheet 1 of 2)
10-170

|A6AMA2|

*<,

•- *<«« r:M

A6AMA2, where _M = Memory Module
Assembly Number

Figure 10-42. X Memory Address Diode Matrix, Schematic Diagram (Sheet 2)
Changed4 January 1965

10-171

Figure 10-43. Y Memory Address Diode Matrix, Schematic Diagram (Sheet 1 of 2)
10-172

|A6AMA4|

1

rTI
uO r"3
51 r"

^..t-.i ..

:

r ~i r ^an

.~,,f if>£,. I*>~
'£,%

A
B
C
P

-

E

>•

-OILIV718Z

f

t

G

»•

-OILEY7180
-OILIY6I78

H
J
K
L


40
4)
42
43
44
-45
46
47
48
49

SIGNAL
AISYLIVN
A1AX60VN
MOSA13
A1AX3VN
A1SYLOVN
AIMCL
MOSAI1
AIMCN . ••
MOSA2
A1INHSV
A1AX40VN
MOSYNCV
MOSA1
SIG-RET
A1AX4VN
SIG-RET
MOSA4
AIRDMVN
A1AX2VN
V3
MOSA8
A 1 RDMV •
AIAX20VN
AIM20ID"
M05A5
A1M20ID
MOSA3
VI
MOSA7
V5
A1AX7VN
PWR-RET
MOSAIC
PWR-RET
A1AX10VN.
BRA 13
MOSA14
BRB13
AIAXOVN
BRA 11
MOSA6
BRBII
A1AX30VN
MA9
MOSAI2
MB9
MOSA9
BRAS
AIAY6VN

PIN

TERMINAL AREA J7
SIGNAL

50
BXB8
51, ' A1AY5VN
52
BRA 10
A1AYIVN
53
54
BRB14
A1AYOOVN
55
BRAU
56
57
AIAXOOVN
58
BRBI2
59
AIAY30VN
BRA 12
60
61
AIAX70VN
62
BRB10
63
A1AY10VN
Bit 62
64
A1AX1VN
65
BRA2
66
AIAYOVN
67
BRB4
68
69
A1AX50VN
BRA 4
70
71
EDOX
72
BRB6
73
AIM20
74
BRA6
MOTCV
75
BRB7
76
77
EDOY
78
BRA7
79 AIAY20VN
80
BIBS
81
A1AY7VN
82
BRA5
A1AY2VN
83
84
BRB3
B5
AIAX6VN
BRA 3
86
87
AIAY4VN
S8
BttBI
89
A1AY40VN
90
BKAI
91
AIAY60VN
IBHAOVfcO
92
93
1AX5VN
94
IBRAOVN(£)
1AY3VN
95
96
1AY50VN
97
1M20
58
A1AY70VN

PIN

SIGNAL

PIN

BRA7
BRA 10
MOSA8
1
1
12
13

M2SAIO
AIAY6VN

MOSA7
15
A2AY5VN
16
17
M2SA7
18
19
M2SA3
AIAY5VN
20
21
22
M2SA5
23
24 ' A1AY50VN
M3SA3
25
A2AY6VN
26
27
M3SA5
28
29
30
31
MOSA3
32
A2AY50VN
33
M3SA10
34
AIAY1VN
35
MOSA5
A2AY1VN
36
37
M2SA8
A1AY70VN
38
39
A2AY70VN
40
14

41
tf
43
44
45
46
47
48

BRAS
M1SA10
MISA2
MOSA10
M1SAI3
A2AYOOVN

49

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
" 65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

85
86
87
68
89
90
91
92
93
94
95
96
97
98

SIGNAL
A1AYOOVN
M1SA1
A1AY30VN
M1SA7

A2AYOVN
BRA4
A2AY30VN
MOSA13
AIAY10VN
AIAYOVN
A2AY7VN
MOSA2
A1AY7VN
A2AY10VN
MOSAI
A1AY20VN
M2SA1
A2AY20VN
M2SA2
A2AY2VN
M2SA11
AIAY2VN
A1AY4VN
A1AY40VN
A2AY4VN
MQSA4
A2AY40VN
M2SAI3
BRA II
MOSM1
BRA 13
BRA1

A1AY60VN
A2AY3VN
BRA2
A2AY60VN
M2SA4
A1AY3VN

Figure 10-45. Memory Distribution Panel, Schematic Diagram (Sheet 4)
10-179

SIGNAL

ORIGIN

A
AB
ABN

A1A13-A

ACCO
ACCON

A1A5-A

ACC1

A1A10-B

ACC1N
ACC1V

AID
AION

1
_L

A4A7-A
A1A5-A

J_

All
AI1N
AI1V
AI2
AI2N
AI2V
AI2VN

A1A10-B
_L
A4A7-B
A1A10-B
1
A4A7-B

J_

AI3

A1A10-B

AI3N
AI3V
AI3VN

A4A7-B

AI4

A1A10-B

_L

_L

_L

AI4N

AN
AND

A1A13-A
A1A10-A

ANDN

AV
AVN
AXON
AXOVN

AX1N
AX1VN
AX2N
AX2VN
AX3N
AX3VN
AX4N
AX4VN
AX5N
AX5VN
AX6N
AX6VN
AX7N
AX7VN
AXOON
AXOOVN
AX10N

1
A4A9-A
_L
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-B
A5A7-B
A1A19-B

SIGNAL
AX10VN
AX20N
AX20VN
AX30N
AX30VN
AX40N
AX40VN
AX50N
AX50VN
AX60N
AX60VN
AX70N
AX70VN
AYON
AYOVN
A YIN
AY1VN
AY2N
AY2VN
AY3N
AY3VN
AY4N
AY4VN
AY5N
AY5VN
AY6N
AY6VN
AY7N
AY7VN
AYOON
AYOOVN
AY10N
AY10VN
AY20N
AY20VN
AY30N
AY30VN
AY40N
AY40VN
AY50N
AY50VN
AY60N
AY60VN
AY70N
AY70VN
Al
A1AN

ORIGIN
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A19-A

_L

SIGNAL

A1N
A1V
A2
A2AN

A2N
A2V
A3
A3AN

A3N
A3V
A4
A4AN

A4N
A4V
A5
A5AN
' A5N
A5V
A6
A6AN
A6N
A6V
A7
A7AN
A7N
A7V
A8
A8AN
A8N
A8V
A9
A9N
A9PADN
A9V

B
BD
BDN
BN
BOT1
BOT2
BOT3
BRAO
BRAON
BRAOV
BRAOVN
BRA1

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 1 of 8)
10-180

ORIGIN
A1A19-A
A5A12-B
A1A19-B

1

A5A12-B
A1A19-A

1

A5A12-B
A1A19-B

1
1
A5A12-B
A1A19-B

1

A5A12-B
A1A19-B

1

A5A12-B
A1A19-A

1

A5A12-A
A1A19-A

1

_L

A5A12-A
A1A19-A
J_
A1A20-B
A5A12-A
A1A10-A
A1A8-A

_L_

A1A10-A
A4A11-A

1

A1A16-A
J_
A5A6-A
J_
A5A9-A

SIGNAL
BRAIN
BRA2
BRA2N
BRAS
BRA3N
BRA4
BRA4N
BRAS
BRA5N
BRAG
BRA6N
BRA7
BRA7N
BRAS
BRA8N
BRA9
BRA9N
BRA10
BRA10N
BRA11
BRA11N
BRA12
BRA12N
BRA13
BRA13N
BRA14
BRA14N
BRA14P
BRBO
BRBON
BRBOV
BRBOVN
BRB1
BRB1N
BRB2
BRB2N
BRB3
BRB3N
BRB4
BRB4N
BRB5
BRB5N
BRB6
BRB6N
BRB7
BRB7N
BRB8

ORIGIN
A5A9-A
1
J_
A5A9-B
1
A5A9-A
|
A5A9-B
|
A5A11-A
1
A5A9-A
|
A5A9-B
1
A5A11-A
|
A5A9-A
|
A5A9-B
1
A5A11-A
1
A5A9-B
1
A5A11-A
1
1
A1A16-B
1
A5A5-A
I
A5A10-A
1
A5A10-B
1
A5A10-A
|
A5A10-B
1
A5A11-B
I
A5A10-A
|
A5A10-B

SIGNAL

ORIGIN

SIGNAL

ORIGIN

BRB8N
BRB9
BRB9N
BRB10
BRB10N
BRB11
BRB11N
BRB12
BRB12N
BRB13
BRB13N
BRB14
BRB14N
BRB14P
BO1
BO1A
BO1N
BQ1P
BO2
BO2A
BO2N
BO2P
BO3
BO3A
BO3N
BO3P

A5A10-B
A5A11-B
_j_
A5A10-A
1
A5A10-B
1
A5A11-B
1
A5A10-B
|
A5A11-B
|
1
A4A11-B
A4A12-B
A4A11-B
A4A12-B
A4A11-B
A4A12-B
A4A11-B
A4A12-B
A4A11-B
A4A12-B
A4A11-B
A4A12-B

External
|
A1A5-A
|
A1A7-A,
A1A10-B
A1A5-A
A1A7-A,
A1A10-B
A1A5-A
A1A16-A
A1A14-A
A5A12-A
A1A16-B
A1A14-A
A5A13-B
A1A14-A

C
CBRN
CBRVN
CD
CDN
CDS
CDSN
CDSV
CKP
CKPN
CLTR
CLTRN
CN
CNC
CNCN
COC
COCN
CST
CSTN
CSTV

A1A10-A
A1A11-B
A5A13-A
A1A8-A
|
A1A11-A
|
A5A15-A
A1A11-B
1
A1A11-A
|
A1A10-A
A1A15-B
1

DATAV
DIN
DLD31B
DLD44B
DL31
J_
DL31SA
DL44
1
DL44SA
DMA
OMAN
DMAVN
DMB
DMBN
DMBVN
DM0
DM1
DM2
DM2N
DM3
DM3N
DSS
DSSN
DS1
DS1M
DS1MN
DS1N
DS2
DS2M
DS2MN
DS2N
DSS
DS3N
DS4
DS4N
DTM
DTMN
DTMV
DTMVN
DUPDN
DUPBST

J
A1A7-A
_[_
A4A14-B
1
A1A14-A
I

EAC
EADM
EADMN

A1A16-A
1
|

J_
A1A15-A
External
A5A5-B

J
A1A20-A

_
A1A20-A

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46.

Signal Origin List (Sheet 2)

Changed 4 January 1965

10-181

SIGNAL
EAIM
EAIMN
EAM
EAMV
EAP
EAPN
EEC
EBDM
EBDMN
EBIM
EBIMN
EBM
EBMV
EBP
EBPN
EDAC
EDACN
EDBC
EDBCN
EDmX
EDmY
EIAC
EIACN
EIBC
EffiCN
EMDN
ESD
ESDN
ESDV
ESDVN
EXM
EXMD
EXMDN
EXMN
EXMV
EXMVN
J_lJ_fX^

ORIGIN
A1A16-A
1
1
A5A6-A
A1A17-A
A1A16-A
A1A16-B

A5A5-A
A1A17-B
A1A16-B
A1A16-A
1
A1A16-B
_|
A6AMA1A1
A6AMA5A1
A1A16-A
1
A1A16-B
I
A1A8-A
A1A8-B
1
A4A14-A
_|
A1A12-A
A1A20-B
_|
A1A12-A
A4A6-B
_L_
XLXXAj. I

JJ

FCD
FMDN
FSA
FSAN
FSB
FSBN

A1A12-A
A1A8-A
A1A16-A
1
A1A16-B
— 1—

Gl
GIN

A1A13-A
1

SIGNAL

ORIGIN

G1V
G1VN
G2
G2N
G2V
G2VN
G3
G3N
G3V
G3VN
G4
G4N
G4V
G4VN
G5
G5N
G5V
G5VN
G6
G6N
G6V
G6VN
G7
G7N
G7V
G7VN

A4A7-A
J_
A1A13-A
J_
A4A13-A
A4A7-A
A1A13-A
J_
A4A13-A
A4A6-A
A1A13-A
_|
A4A8-B
1
A1A13-A
1
A4A8-A
A4A13-A
A1A13-A
1
A4A6-A
1
A1A13-A
1
A4A9-A
A4A6-A

HALTV
HOP
HOPC1
HOPC1N
HOPC1V
HOPN
HOPV
HOY
HOYN
HOYV
HOYVN
HP1
HP1N

External
A1A12-A
A1A14-B
1
A5A12-A
A1A12-A
A4A5-A
A1A7-A
J
A4A13-B
_|
A1A14-B
1

IMA
IMAN
IMAVN
1MB
IMBN

A1A16-A
A1A14-A
A5A12-A
A1A16-B
A1A14-A

V-PI

V Al

^^^^^»

SIGNAL
IMBVN
IMO
IM1
IM2
IM2N
IMS
IM3N
INHBS
INHBSV
INT
INTA
INT AN
INTB
TNTRN
ESTTCV
INTN
INTV
ISS
ISSN
IS1
IS1N
IS2
IS2N
133
ISSN
IS4
IS4N

ORIGIN
A5A13-B
A1A 14-A

—
A1A15-A
A5A5-B
A1A12-A

External
A1A12-A
A4A6-B
A1A20-A

JBN

A1A12-B

Kl
KIN
K2
K2N

A1A7-B
1

MAO
MAOV
MBO
MBOV
MDO
MDON
MD1
MD1N
MD2
MD2N
MD2V

A1A15-B
A5A6-B
A1A15-B
A5A6-B
A1A5-A
— L_
A1A7-B

— l—

J
A4A14-B

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 3)
10-182

Changed 4 January 1965

SIGNAL
MD3
MD3N
MD4
MD4N
MD5
MD5N
MD6
MD6N
MD7
MD7N
MD7V
MFF
MFFN
MFFVN
MOP
MRO
MRON
MR1
MR1N
MR1V
MR1VN
MR2
MR2N
MSS
MSSN
MSSVN
MSVB1
1
J_
MSVB2
1
J_
MTT
MTTN
MTTVN
MZO
MZON
MZOVN
MmCRX
J_
MmCRY
MmEDEX
MmEDEY
MmEDIYO
MmEDIYl
MmEDIY2
MmEDIYS
MmEDIY4

ORIGIN
A1A7-B

J
A4A14-B
A1A15-B
A1A14-A
A5A13-B
A1A15-A
A1A5-A
J_
A1A9-A
J_
A4A9-B
J_
A1A9-A
J_
A1A15-A
A1A14-A
A5A13-A
A1A4-A
A4A3-A
A5A3-A
A1A4-A
A4A3-A
A5A3-A
A1A15-A
A1A14-A
A5A13-A
A1A15-A
A1A14-A
A5A13-A
A6AMA1A1
A6AMA1A2
A6AMA5A1
A6AMA1A2
A6AMA5A1
A6AMA7A1

SIGNAL
MmEDIYS
MmEDIYG
MmEDIY7
MmEDIO
MmEDIl
MmEDI2
MmEDI3
MmEDI4
MmEDIS
MmEDIG
MmEDI7
MmHEYO
MmHEYl
MmHEY2
MmHEYS
MmHEY4
MmHEYS
MmHEY6
MmHEY7
MmHIYO
MmHIYl
MmHIY2
MmHIYS
MmHIY4
MmHIYS
MmHIYG
MmHIY7
MmlNHl
MmINH2
MmINH3
MmINH4
MmlNHS
MmlNHG
MmINH7
MmlNHS
MmINH9
MmlNHIO
MmlNHll
MmINH12
MmlNHlS
MmINH14
MmLEXO
MmLEXl
MmLEX2
MmLEX3
MmLEX4
MmLEXS
MmLEX6

ORIGIN
A6AMA7A1
1
J_
A6AMA1A1, 2

J
A6AMA5A1

J
A6AMA7A1

J
A6AMA1A2

J

SIGNAL

ORIGIN

MmLEX7
A6AMA1A2
MmLEYO
A6AMA5A1
MmLEYl
MmLEY2
MmLEYS
MmLEY4
MmLEYS
MmLEYG
MmLEY7
J_
MmLKO
A6AMA1A2
MmLDCl
MmLEX2
MmLDCS
MmLK4
MmLIXS
MmLK6
MmLK7
J
MmLIYO
A6AMA5A1
MmLIYl
MmLIY2
MmLIY3
MmLIY4
MmLIYS
MmLIY6
MmLIY7
J
MmRDPl
A6AMA6A1
MmRDP2
I
MmRDPS
J_
MmSAl
A6AMA3A1
MmSA2
A6AMA3A2
MmSAS
A6AMA3A1
MmSA4
A6AMA3A2
MmSAS
A6AMA3A1
MmSA6
A6AMA3A2
MmSA7
A6AMA3A1
MmSAS
A6AMA3A2
MmSA9
A6AMA3A1
MmSAlO
A6AMA3A2
MmSAll
A6AMA3A1
MmSA12
A6AMA3A2
MmSAlS
A6AMA3A1
MmSA14
A6AMA3A2
MmSLlAthru Core Array
MmSL14A
MmSLlBthru
MmSL14B
MmSTROB A6AMA6A1
MmSTRPl
|
MmSTRP2
-L

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 4)
Changed 4 January 1965

10-183

SIGNAL
MmSTRPS
MmSOEO
MmSOEl
MmSOE2
MmSOES
MmSOE4
MmSOES
MmSOE6
MmSOE7
MmSOIO
MmSOIl
MmSOI2
MmSOIS
MmSOI4
MmSOIS
MmSOIG
MmSOI7
MmSlEO
MmSlEl
MmSlE2
MmSlES
MmSlE4
MmSlES
MmSlE6
MmSlE7
MmSlIO
MmSlIl
MmSlI2
MmSlIS
MmSlI4
MmSlIS
MmSlK
MmSin
MmTCV
MOSYN
MOSYNV
M1SYNC
M1SYNCV
M2SYNC
M2SYNCV
M3SYNC
M3SYNCV
M4SYNC
M4SYNCV
M5SYNC
M5SYNCV

ORIGIN
A6AMA6A1
A6AMA1A1

J
A6AMA6A1
A1A16-A
A5A6-A
A1A16-B
A5A5-A
A1A16-A
A5A6-A
A1A16-B
A5A5-A
A1A16-A
A5A6-A
A1A16-B
A5A5-A

SIGNAL

ORIGIN

M6SYNC
M6SYNCV
M7SYNC
M7SYNCV

A1A16-A
A5A6-A
A1A16-B
A5A5-A

NU
NUN

A1A5-A
— 1L_

OC
OCN
OP1
OP1N
OP1V
OP1VN
OP2
OP2N
OP2V
OP2VN
OPS
OP3N
OP3V
OP3VN
OP4
OP4N
OP4V
OP4VN

A1A14-B
|
A1A12-A
1
A4A5-B
|l_
A1A12-A
|1
A4A5-B
|_
A1A12-A
|1
A4A5-B
_| _
A1A12-A
|
A4A6-B
_|l_

P
PA
PAD
PADN
PAE1
PAE2
PAE3
PAE4
PAE5
PAE6N
PAN
PAO1
PAO2
PAO3
PAO4
PAO5
PAO6
PAO7
PAO8

A4A12-B
A1A13-B
A1A20-B
|L_
A1A17-A

1
A1A13-B
A1A17-A

—

SIGNAL
PAO9
PAO10
PAO11
PAO12
PAR
PARN
PARV
PAV
PAVN
PB
PBE1
PBE2
PBE3
PBE4
PBE5
PBE6N
PEN
PBO1
PBO2
PBO3
PBO4
PBO5
PBO6
PBO7
PBO8
PBO9
PBO10
PBO11
PB012
PBV
PBVN
PC
PCN
PCV
PCVN
FDD
PDDN
PIO
PIOV
PN
POD
PGDN
PP
PPN
PQR
PQRN

ORIGIN
A1A17-A
J
A1A11-B
1
A5A15-A
A4A8-A
A4A8-B
A1A13-B
A1A17-B

^

|
A1A13-B
A1A17-B

_J
A4A8-A
A4A8-B
A1A13-B
|
A4A8-A
A4A8-B
A1A11-B
_J
A1A12-B
A4A5-A
A4A12-B
A1A11-B
1
A4A12-B
|
A1A5-A
1

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 5)
10-184

Changed 4 January 1965

SIGNAL

ORIGIN

PR
PRN
PRO
PRON
PROV
PROVN
PR1
PR1N
PR2
PR2N
PR2V
PR2VN
PR3
PR3N
PR4
PR4N
PR5
PR5N
PR6
PR6N
PR7
PR7N
PR8
PR8N
PR9
PR9N
PR10
PR10N
PWR RET
PIN
P1VN
P2N
P2VN
P3N
P3VN

A1A5-A
1
A1A9-B
|
A4A9-B
1
A1A9-B
1

Q
QN
QP
QPN
Ql
Q1N
Q2
Q2N
Q3
Q3N

|
A4A9-B
1
A1A9-B

External
A1A7-A
A4A13-B
A1A7-A
A4A13-B
A1A7-A
A4A13-A
A4A12-A
1
A4A12-B
|
A1A9-A

_

SIGNAL
Q4
Q4N
Q5
Q5N
Q6
Q6N
Q7
Q7N
Q8
Q8D
Q8DN
Q8N
Q8V
Q9
Q9N

ORIGIN

SIGNAL

ORIGIN

A1A 9-A

SBRYN
SBRYV
SBRZ
SBRZN
SBRZV
SGI
SG1N
SG2
SG2N
SHF
SHFV
SIG RET
SINK
SENKN
SLD
SLDN
SMDN
SN
SRTR
SRTRN
SS
SSF
SSFSN
SSN
STMD
STMDN
STO
STON
STOVN
STP
STPN
SV
SVN
SYLC1
SYLC1N
SYLC1V
SYLON
SYLOVN
SYL1N
SYL1VN
SYNC
SYNCN
S4
S4N

A1A11-B
A5A13-A
A1A11-B
|
A5A15-A
A1A8-B
1

_|
A1A8-A
A4A12-A
A1A11-A
|
AfAT8~-A
A1A12-B
|
A1A18-A
1
1
A1A11-B
A1A12-B
A4A5-A
A1A5-A
|
A4AT2~-B
|
A1A15-A
|
ASAfPB
A1A15-A
A5A5-B
A1A15-A
A5A6-B
A1A15-B
|
A1A19-A
_L

TA

A1A19-B

A1A 10-A
|L
A1A9-A
A4A9-A
A1A7-A
_l_

R
RAC
RACN
RD
RDM
RDMN
RDMV
RDMVN
RDV
RECN
RED
REDN
REI
REIN
RN
RP
RPN
RUN
RUNN
RUNV
RUNVN
RV
RVN

A4A12-A
A1A10-A
1
A1A15-A
A1A15-B
[
A5A6-B
1
I
A1A15-B
A1A14-B
|
A4A12-A
1
|
A1A15-A
|
A5A5^B
|
A4A1T-A
_|

S
SAPO
SBRX
SBRXN
SBRXV
SBRY

A4A12-A
A1A12-B
A1A11-B
|
A5A13-A
A1A11-B

1
A1A12-B
A4A5-A
External
A1A15-A

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 6)
10-185

SIGNAL

ORIGIN

SIGNAL

ORIGIN

SIGNAL

ORIGIN

TAN
TBC
TBCN
TBCV
TBR
TBRN
TBRV
TER
TFD
TFDN
TFDV
TFDVN
THERM1
THERM2
TIME
TIMEN
TLC
TLCN
TLCV
TM
TMDN
TMN
TMV
TMVN
TR1
TR1D
TR1DN
TR1N
TR1V
TR2
TR2N
TR2V
TR3
TR3D
TR3DN
TR3N
TR3V
TR4
TR4N
TR4V
TR5
TR5N
TR5V
TR6
TR6D
TR6DN

A1A19-B
A1A13-B
1
A4A8-B
A1A11-B
_|
A5A13-A
External
A1A8-B
I
A4A14-A
_]
A4A11-B
_J
A1A15-B

TR6N
TR6V
TR7
TR7N
TR7V
TR8
TR8N
TR8V
TR9
TR9D
TR9DN
TR9N
TR9V
TRIO
TR10N
TR10V
TR11
TR11N
TR11V
TR12
TR12D
TR12DN
TR12N
TR12V
TR13
TR13N
TR13V
TRS
TRSN
TRSV
TRSVN
TTL
TTLN
TTLV
TTT

A1A18-B
A5A14-B
A1A18-B
1
A5A14-A
A1A18-B
1
A5A14-A
A1A18-B
1

V4MOD1
V4MOD2
V4MOD3
V4MOD4
V4MOD5
V4MOD6
V4MOD7
V5
V5MOD1
V5MOD2
V5MOD3
V5MOD4
V5MOD5
V5MOD6
V5MOD7
V20

External

WDA
WF
WN
Wl
W2
W3
W4
W5
W6
W7
W8

A1A3-A

XDA
XF

A1A3-A

A5A5-B
A1A7-A
A1A8-A
A1A7-A
A4A14-B
1 .
A1A18-A
1
-LA5A14-B
A1A18-A
— 1—
A5A14-B
A1A18-A
1

-LA5A14-B
A1A18-B
1
A5A14-B
A1A18-B
1
A5A14-B
A1A18-B
1
J_

—L
A5A14-A
A1A11-A
1
A5A14-A
A1A11-A
_J_
A5A14-A
A1A11-A
1
— LA5A15-A
A1A11-A
|
A5A14-A
A1A11-A
I
A5A15-A
|
A1A12-B
I
A4A6-B
A1A11-B

UACCO
UTR
UTRV

A1A10-B
1
A4A7-B

VOY
VOYN
VOYV
VOYVN
VI
V3

A1A7-A
1
A4A13-B
__[_
External
1

XN
XI
X2
X3
X4
X5
X6
X7
X8

J

J

J

YDA
YF
YN
Yl

A1A3-B
1
J_

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 7)
10-186

Changed 4 January 1965

SIGNAL
Y2
Y3
Y4
Y5
Y6
Y7
Y8

ORIGIN
A1A3-B

_

SIGNAL
ZDA
ZDHN
ZDLN
ZER
ZERN
ZF
ZN

ORIGIN
A1A3-B
A1A8-A
1
A1A10-A
J_
A1A3-B
11

SIGNAL
Zl
Z2
Z3
Z4
Z5
Z6
Z7
Z8

ORIGIN
A1A3-B

Note: Origins of TMR signals are shown for channel 1 only.
Figure 10-46. Signal Origin List (Sheet 8)

10-187

Refer to Back Panel Lists for the Saturn
V Launch Vehicle Digital Computer.
(Supplied under separate cover.)

Figure 10-47. Interconnection Al Back Panel, List for LVDC
10-188

Refer to Back 3?anel Lists for,the Saturn
V Launch Vehicle Digit'al.Computer.. !
(Supplied under separate cover.)

Figure 10-48. Interconnection A4sBack Panel,, List for. LVDC .,
10-189

Refer to Back Panel Lists for the Saturn
V Launch Vehicle Digital Computer.
(Supplied under separate cover. )

Figure 10- 49. ~ntercomectionA5 Back Panel, list for LVDC
10-190

A6J3

A4E2
A4J1

A6J2

A6J1

A6J4

A4E1

Figure 10-50. Computer, Rear View

Changed 4 January 1965

10-191

10-192

§

K;

i

2
3

i
ii
ii
9

(SI

BU««

ii

ilj

ij

f
II

N

ji
—

Ou*«

li
o

II
ii

6
||

" 1 :":
1

O

1
ii,

ii

•a

ID

CO

§
U

cf
.2

•ao

(U

ia
S

.a

m
rt

I-H

a

.3

0)

H

1

0
0)

COMMENT SHEET

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the usefulness and readability of this publication. Suggest additions and
deletions, and indicate any specific errors or omissions. The completed comment sheets should be forwarded to the following address:
Manager
Department 913
IBM Corporation
Space Guidance Center
Owego, N. Y.

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