Saturn_V_LVDC_Vol2_Jan65 Saturn V LVDC Vol2 Jan65

Saturn_V_LVDC_Vol2_Jan65 Saturn_V_LVDC_Vol2_Jan65

User Manual: Saturn_V_LVDC_Vol2_Jan65

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LAUNCH
VEHICLE
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»
™,
_
~_
_
Laboratory
Maintenance
Instructions.
JJi'-LR
JUd
vu
La
t-v/«.
|
.»i»-...^.-...,„
(International
Business
Machines Corp.)
VOLUME
II OF II
Laboratory
Maintenance
Instructions
SATURN
V
LAUNCH
VEHICLE
DIGITAL
COMPUTER
Simplex
Models
NASA
Part
No.
50M35010
IBM
Part
No.
6109030
W
~L°fl'h
IDT
(International
Business Machines
CorpOTOfthgV1rH.:'
r^az
'
^
U°O»
^
Contract
MAS
8-11561
LATEST
CHANGED
PAGES SUPERSEDE
THE
SAME
PAGES
OF
PREVIOUS
DATE
Insert
changed
pages
into
basic
publication.
Destroy
superseded
pages.
VOLUME
II
MAINTENANCE
DATA
30
NOVEMBER
1964
CHANGED
4
JANUARY
1965
LIST
OF
EFFECTIVE PAGES
INSERT
LATEST
CHANGED
PAGES.
DESTROY SUPERSEDED PAGES.
TOTAL
NUMBER
OF
PAGES
IN
VOLUME
H IS 230
CONSISTING
OF THE
FOLLOWING:
Page
No.
Issue
Page
No.
*Title
4 Jan 65
10-176
thru
*A
. . . 4 Jan 65
10-180
. . .
*i 4 Jan 65
*10-181
thru
ii
Blank Original 10-184
. . .
*iii
4 Jan 65
10-185
iv
thru
v
Original *10-186
. . . .
vi
Blank Original 10-187 thru
3-1
thru
3-9
.... Original 10-190
. . .
*3-10
4 Jan 65
*10-191
3-11 thru 3-12.
. .
Original 10-192
4-1
Original
*4-2
4 Jan 65
4-3
Original
*4-4
4 Jan 65
4-5
Original
4-6
Blank Original
;
*5-l thru
5-6
....
4 Jan 65
*5-7 thru
5-8
Added
4 Jan 65
6-1
Original
6-2
Blank Original
7-1
Original
7-2
Blank Original
8-1
Original
8-2
Blank Original
9-1
thru
9-2
.... Original
*9-3
4 Jan 65
9-4
thru
9-7
....
Original
9-8
Blank Original
10-1 thru 10-153
.
Original
*10-154 thru
10-159
4 Jan 65
10-160 Original
*10-161
4 Jan 65
10-162 Original
*10-163 thru
10-169
4 Jan 65
10-170 Original
*10-171
4 Jan 65
10-172
Original
*10-173
4 Jan 65
10-174 Original
*10-175
4 Jan 65
Issue
Original
4
Jan 65
Original
4
Jan 65
Original
4
Jan 65
Original
*The
asterisk indicates pages changed, added,
or
deleted
by the
current
change.
A
Changed
4
January 1965
MAY
9
\1966
*
)
VOLUME
II OF II
Laboratory
Maintenance
Instructions
SATURN
V
LAUNCH
VEHICLE
DIGITAL
COMPUTER
Simplex
Models
NASA
Part
No.
50M35010'
r
.-,&-
-
IBM
Part
No.
6109030
^^
f S^ '• \ - - ' J •- :',
'-K
- ' .* i •
'•'~
• i *
"l;.*r"
(International
Business
Machines
Corporation]
Contract
MAS
8-11561
VOLUME
II
MAINTENANCE
DATA
30
NOVEMBER
1964
Technical
Library,
Bellcomm,
!ncs
•r
LIST
OF
EFFECTIVE PAGES
INSERT
LATEST
CHANGED
PAGES.
DESTROY
SUPERSEDED
PAGES.
NOTE:
The
portion
of the
text
affected
by the
changes
is
indicated
by 3
vertical
line
in the
outer
margins
of the
page.
TOTAL
NUMBER
OF
PAGES
IN
VOLUME
H IS 228
CONSISTING
OF THE
FOLLOWING:
Page
No.
Issue
Title Original
A
Original
i
Original
ii
Blank Original
iii
thru
v
Original
vi
Blank,
Original
3-1
thru 3-12 Original
4-1
thru
4-5
Original
4-6
Blank
.
Original
5-1
thru
5-5
....
.Original
5-6
Blank
.
Original
6-1
..........
.Original
6-2
Blank Original
7-1
Original
7-2
Blank Original
8-1
Original
8-2
Blank
......
.Original
9-1
thru
9-7 . ...
.Original
9-8
Blank
Original
10-1 thru 10-192
.
.Original
^Thc
;istcri.sk
indicates
pai;es
chunked,
added,
or
deleted
bv the
current
clunije
Volume
II
TABLE
OF
CONTENTS
Section
Title
Page
m
INTERFACE
AND
ADJUSTMENTS.
. , . ...
....
.
.......
3-1
3-1.
Interface
. 3-1
3-3. Adjustments
. 3-1
IV
TEST
EQUIPMENT
AND
SPECIAL TOOLS
.............
4-1
4-1. Test Equipment
. . . 4-1
4-2. Standard Test Equipment.
........
.....
. .
....
4-1
4-4. Special Test Equipment.
4-1
4-6. Special Tools.
. . .
....
f 4-1
V
PREPARATION
FOR
USE,
STORAGE
AND
SHIPMENT.....
5-1
5-1. Preparation
for Use 5-1
5-2A.
Inspection
and
Test
......
'.'.
....
.".'
.........
5-4
5-3. Preparation
for
Storage
. .
'.'....'
5-4
5-5. Preparation
for
Shipment.
................
. .. . 5-5
5-7
General
Computer
Handling
..........
. 5-7
Vl"
PREVENTIVE MAINTENANCE.
....................
6-1
VH
CHECKOUT
7-1
7-1. Operating Test Procedures
7-1
VEQ
TROUBLE ISOLATION
8-1
IX
REPAIR
9-1
9-1. Repair
9-1
X
DIAGRAMS
10-1
10-1. Diagrams
10-1
10-3. Signal Tracing
10-2
Changed
4
January 1965
i/ii
Volume
LIST
OF
ILLUSTRATIONS
Figure
Title
Page
3-1
Computer Connectors
By
Signal
Function^.
. ... . . . .
.....
, 3-1
3-2
Computer Interface Signals
(8
Sheets)
.......
...
......
3-2
3-3
Computer
—
Data Adapter Interconnection Block
Diagram..
.
3-10
3-4
Computer
and
LVDC-ME
Interconnection Block Diagram
. . .
3-11
3-5
Computer
-
ATOM
Interconnection Block Diagram
........ 3-12
4-1
Standard
Test
Equipment
Table.
......
... . . ... . . .
.'..-
. . 4-1
4-2
Special
Test
Equipment
Table.
..........
. .
;..;.'•.
.....
4-2
4-3
Special
Test
Equipment.
. • ... ...
......
. . . . . . . 4-3
4-4
Special Tools Table
. . .
........
4-4
4-5
Special Tools
........................
"." 4-5
5-1
Reuseable Shipping Container.
. . . . .
....
..... ......... 5-^2
5-2
Removing Roll Chart
from
Shock Recorder
....
. ,'.
......
5-2
5-3
Installing
Roll Chart
in
Shock Recorder
.
...;..........
5-3
5-4
Computer Lift Handle,
Mounted
5-8
9-1
Laboratory Replaceable Assemblies
...
..............
9-1
9-2
Computer,
Partially
Disassembled
9-2
9-3
Page
Assembly Location Guide.
9-3
9-4
Memory Handle Secured
to
Memory Assembly.
..........
9-6
10-1 Clock
Drivers,
Logic Diagram
(4
Sheets)
10-4
10-2 Decoupling Capacitors (Channel
1),
Logic Diagram
(4
Sheets)
.
10-8
10-3 Delay Lines, Logic Diagram
(2
Sheets)
10-12
10-4 Multiply-Divide Element, Logic Diagram
(12
Sheets)
10-14
10-5 Add-Subtract Element, Logic Diagram
(4
Sheets).
........
10-26
10-6 Transfer Register
Bits
10 — TRS and
Control,
Logic Diagram
(2
Sheets)
10-30
10-7 Memory
Buffer
Control
and
Parity
Counter,
Logic Diagram
(2
Sheets).
10-32
10-8 Operation
Code
Register,
Logic Diagram
(4
Sheets).
.
.....
10-34
10-9 Timing Gate Generator, Logic Diagram
(2
Sheets).
. . .
•.'..
. .
10-38
10-10
Phase
Generator, Logic Diagram
(2
Sheets)
............ 10-40
10-11 Memory Module
Registers,
Logic Diagram
(2
Sheets)
10-42
10-12
HOP
Constant
Serializer
and
Memory Read Latches,
Logic Diagram
(2
Sheets).
.
10-44
10-13 Memory Timing, Logic Diagram
(4
Sheets).
. . .
10-46
10-14 Memory
Error
Detector, Logic Diagram
(8
Sheets)
.......
10-50
10-15 Transfer Register
Bits'1
- 9,
Logic Diagram
(4
Sheets)
. . ...
10-58
10-16 Address
Register
and
Memory
Address
Decoder,
Logic Diagram
(4
Sheets)
10-62
10-17 Memory Sector
Registers,
Logic Diagram
(2
Sheets)
10-66
10-18 Hi-Y Memory Address Decoder, Logic Diagram
(2
Sheets)
10-68
Changed
4
January 1965
iii
Volume
II
LIST
OF
ILLUSTRATIONS
(Cont)
Figure
Title
Page
10-19 Decoupling
Capacitors
(Channel
4),
Logic Diagram
(4
Sheets) 10-70
10-20
Operation
Code
Voters, Logic Diagram
(4
Sheets) 10-74
10-21 Timing Gate
and
Operation
Code
Voters,
Logic
Diagram
(4
Sheets) 10-78
10-22
Timing
and
Add-Subtract Voters, Logic Diagram
(4
Sheets) 10-82
10-23 Timing Voters, Logic Diagram
(4
Sheets) 10-86
10-24
Timing
and
Multiply-Divide Voters, Logic Diagram
(4
Sheets) 10-90
10-25
Oscillator
and
Buffer,
Logic Diagram
(2
Sheets) 10-94
10-26
Clock Generator Timing Logic, Logic Diagram
(4
Sheets) 10-96
10-27
Timing
and
Multiply-Divide Voters, Logic Diagram
(4
Sheets) 10-100
10-28 Multiply-Divide Voters, Logic Diagram
(4
Sheets) 10-104
10-29 Decoupling Capacitors (Channel
5),
Logic Diagram
(4
Sheets) 10-108
10-30 Memory Timing Voters, Logic Diagram
(8
Sheets) 10-112
10-31 Memory Address Decoder Voters, Logic Diagram
(8
Sheets) 10-120
10-32
Memory
Buffer
Registers,
Logic Diagram
(12
Sheets) .... 10-128
10-33 Address Register
and
Memory
Module
Register
Voters, Logic Diagram
(4
Sheets) 10-140
10-34
.
Transfer
Register
and
Memory
Module
Register
Voters, Logic Diagram
(4
Sheets) 10-144
10-35 Transfer Register Voters, Logic Diagram
(6
Sheets) 10-148
10-36 Memory Clock Driver
and
TCV, Logic Diagram
(2
Sheets) 10-154
10-37 Memory Sense Amplifiers, Logic Diagram
(2
Sheets) 10-156
10-38 Memory Inhibit Drivers, Logic Diagram
(2
Sheets)
;
10-158
10-39 Memory Y-Address Drivers, Logic Diagram
(4
Sheets) 10-160
10-40
Memory Hi-X Address Drivers, Logic Diagram
(4
Sheets) 10-164
10-41 Memory Lo-X Address
Drivers,
Logic Diagram
(2
Sheets)
'
10-168
10-42
X
Memory Address
Diode
Matrix, Schematic Diagram
(2
Sheets) 10-170
10-43
Y
Memory Address
Diode
Matrix, Schematic Diagram
(2
Sheets) 10-172
10-44
Memory
Input-Output Panel, Schematic Diagram
(2
Sheets) 10-174
10-45 Memory Distribution Panel, Schematic Diagram
(4
Sheets) 10-176
10-46 Signal Origin
List
(8
Sheets) 10-180
IV
Volume
H
LIST
OF
ILLUSTRATIONS (Cont)
Figure
Title
Page
10-47 Interconnection
Al
Back
Panel,
List
for
LVDC
10-188
10-48 Interconnection
A4
Back Panel, List
for
LVDC
10-189
10-49 Interconnection
A5
Back
Panel,
List
for
LVDC
10-190
10-50 Computer, Rear
View
10-191
10-51 Terminal
Block
Pin
Identification, Channels
1, 4, and 5. . .
10-192
v/vi
SECTION
III
INTERFACE
AND
ADJUSTMENTS
3-1.
INTERFACE
3-2
Figure
3-1
shows
the
connector interface
by
function
and the
direction
of
signal
flow
relative
to the
computer. Figure
3-2
lists
the
computer interface signal names
and
functions
alphabetically
by
connector number. Figure
3-3 is a
functional block
diagram
which
shows
the
interconnection
of
groups
of
similar
signals
between
the
computer
and
the
data
adapter
Figure
3-4
shows
the
interconnection
of
groups
of
similar
signals
between
the
computer
and the
LVDC-ME.
Figure
3-5
shows
the
interconnection
of
groups
of
similar
signals
between
the
computer
and the
ATOM.
NOTE
All
the
channel reference designations
(Al
through
A3)
have been left
off the
functional
signal
names
in all
diagrams
in
this
section.
3-3. ADJUSTMENTS
3-4.
No
adjustments
are
made
on the
computer.
Misc.
Timing
LTE
(only)
Module
Switching
Power
-OJ4
-OJ3
HOJ2
-»OJ1
LVDC
J80-
J7o«-
J604-
J5o^-
Address
Reg & TRS
•
Memory
Power
Logic
Power
External
Control
•
Error
Data
Figure
3-1. Computer Connectors
By
Signal Function
3-1
NAME
CONNECTOR
PIN
FUNCTION
.*A1V4M1
*A2V4M1
*A3V4M1
*A1V4M2
*A2V4M2
*A3V4M2
*A1V4M3
*A2V4M3
*A3V4M3
*A1V4M4
*A3V4M4
*A1V4M5
*A2V4M5
*A3V4M5
*A1V4M6
*A2V4M6
*A3V4M6
*A1V4M7
*A2V4M7
*A3V4M7
*A1V5M1
*A2V5M1
*A3V5M1
*A1V5M2
*A2V5M2
*A3V5M2
*A1V5M3
*A2V5M3
*A3V5M3
*A1V5M4
*A2V5M4
*A3V5M4
*A1V5M5
*A2V5M5
*A3V5M5
*A1V5M6
*A2V5M6
*A3V5M6
*A1V5M7
*A2V5M7
*A3V5M7
INTRLK
INTRLK
SR01
SR02
SR03
SR04
SR05
SR06
SPARE
SPARE
SPARE
SPARE
SPARE
Jl
Jl
Jl
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
.Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji .
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
Ji
HH
J
FF
BB
nE
nw
AA
nF
nl
CC
0G
EE
nQ
no
nv
GG
K
nu
ny
DY
DD
Y
nT
np
nR
G
V
c
nC
W
H
H
A
nS
nA
ON
D
F
T
Z
nB
u
N
P
E
M
X
nM
nx
nZ
R
S
BH
nj
n<
CHANNEL
1. 6
VDC» MODULE
1
CHANNEL
2» 6
VDC» MODULE
1
CHANNEL
3» 6 VDC »
MODULE
1
CHANNEL
1> 6
VDC» MODULE
2
CHANNEL
2, 6
VDC. MODULE
2
CHANNEL
3> 6
VDC»
MODULE
2
CHANNEL
1> 6 VDC »
MODULE
3
CHANNEL
2> 6
VDC»
MODULE
3
CHANNEL
3» 6 VDC »
MODULE
3
CHANNEL
1» 6 VDC f
MODULE
4
CHANNEL
2/6
VDC. MODULE
4
CHANNEL
3> 6 VDC ,
MODULE
4
CHANNEL
1> 6
VDC» MODULE
5
CHANNEL
2. 6
VDC» MODULE
5
CHANNEL
3. 6
VDC, MODULE
5
CHANNEL
1, 6
VDC» MODULE
6 ':
CHANNEL
2» 6
VDC»
MODULE
6
CHANNEL
3» 6 VDC »
MODULE
6'
CHANNEL
1» 6
VDC»
MODULE
7
CHANNEL
2> 6
VDC, MODULE
7
CHANNEL
3» 6
VDC,
MODULE
7
CHANNEL
1, 12
VDC, MODULE
1
CHANNEL
2, 12
VDC, MODULE
1
CHANNEL
3, 12
VDC, MODULE
1
CHANNEL
1, 12
VDC, MODULE
2
CHANNEL
2, 12
VDC, MODULE
2
CHANNEL
3, 12
VDC, MODULE
2
CHANNEL
1, 12
VDC, MODULE
3
CHANNEL
2, 12
VDC, MODULE
3
CHANNEL
3, 12
VDC, MODULE
3
CHANNEL
1, 12
VDC, MODULE
4
CHANNEL
2, 12
VDC,
MODULE
4
CHANNEL
3, 12
VDC, MODULE
4
CHANNEL
1, 12
VDC, MODULE
5
CHANNEL
2, 12
VDC, MODULE
5
CHANNEL
3, 12
VDC,
MODULE
5
CHANNEL
1, 12
VDC, MODULE
6
CHANNEL
2, 12
VDC, MODULE
6
CHANNEL
3, 12
VDC, MODULE
6
CHANNEL
1, 12
VDC, MODULE
7
CHANNEL
2, 12
VDC, MODULE
7
CHANNEL
3, 12
VDC, MODULE
7
LTE
INTERLOCK
FOR LTE USE 01
LTE
INTERLOCK
FOR LTE USE 01
SIGNAL RETURN, LINE
01
A2V5I
SIGNAL RETURN, LINE
02
A2V4I
SIGNAL RETURN, LINE
03
A1V5!
SIGNAL
RETURN,
LINE
04
A3V5I
SIGNAL
RETURN, LINE
05
A3V4I
SIGNAL
RETURN, LINE
06
A1V4I
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
SWITCHING
NOTE
^DENOTES
INPUTS
TO
COMPUTER* niNDICATES LOWER
CASE
LETTER
Figure
3-2.
Computer
Interface
Signals
(Sheet
1 of 8)
3-2
NAME
CONNECTOR
PIN
FUNCTION
*A1CSTN
*A2CSTN
*A3CSTN
.
*A1DIN
*A2DIN
*A3DIN
A1HOPC1V
A2HOPC1V
A3HOPC1V
*A1MCL
#A2MCL
*A1MCN
*A2MCN
A1MD7V
A2MD7V
A3MD7V
A1MR1V
A2MR1V
A3MR1V
A10P1V
A20P1V
A30P1V
A10P2V
A20P2V
A30P2V
A10P3V
A20P3V
A30P3V
A10P4
A20P4V
A30P4V
A1PROV
A2PROV
A3PROV
*A1TER
*A2TER
*A3TER
BRA14P
BRB14P
INTRLK
INTRLK
SIGRET
SIGRET
SIGRET
SIGRET
SIGRET
SPARE
SPARE
SPARE
SPARE
SPARE.
SPARE
SPARE
SPARE
SPARE
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
nK
E
K
DM
DA
L
R
HH
nC
D
U
CC
an
N
M
F
nu
J
H
G
B
C
A
np
Z
nx
S
ns
DG
nD
av
EE
W
aw
DD
nB
nY
az
P
X
Y
BB
FF
T
V
aF
aj
n(\|
no
PR
AA
GG
CHANNEL
1,
SINGLE
STEP
CONTROL
CHANNEL
2»
SINGLE
STEP
CONTROL
CHANNEL
3»
SINGLE
STEP
CONTROL
CHANNEL
1»
MEMORY
LOAD
CHANNEL
2»
MEMORY
LOAD
CHANNEL
3.
MEMORY
LOAD
CHANNEL
1. HOP
CONSTANT
CHANNEL
2» HOP
CONSTANT
CHANNEL
3»
CHANNEL
1»
CHANNEL
2»
CHANNEL
1,
CHANNEL
2»
CHANNEL
1.
CHANNEL
2.
CHANNEL
3,
CHANNEL
1»
CHANNEL
2.
CHANNEL
3»
CHANNEL
1.
CHANNEL
2.
OPERATION CODE REGISTER
CHANNEL
3,
OPERATION
CODE
REGISTER
CHANNEL
1»
OPERATION CODE REGISTER
CHANNEL
2»
OPERATION CODE REGISTER
CHANNEL
3,
OPERATION
CODE
REGISTER
CHANNEL
1>
OPERATION CODE REGISTER
CHANNEL
2»
OPERATION CODE REGISTER
CHANNEL
3.
OPERATION CODE REGISTER
CHANNEL
1.
OPERATION CODE REGISTER
CHANNEL
2.
OPERATION
CODE
REGISTER
CHANNEL
3.
OPERATION CODE REGISTER
CHANNEL
1.
PRODUCT
REMAINDER
LATCH
CHANNEL
2»
PRODUCT
REMAINDER
LATCH.
CHANNEL
3.
CHANNEL
1,
CHANNEL
2.
CHANNEL
3.
BUFFER REGISTER
BUFFER REGISTER
LTE
INTERLOCK
FOR
LTE
INTERLOCK
FOR
HOP
CONSTANT
MARGINAL
CHECK
MARGINAL
CHECK
MARGINAL
CHECK
MARGINAL
CHECK
MULTIPLICAND DIVISOR REGISTER
MULTIPLICAND DIVISOR REGISTER
MULTIPLICAND DIVISOR REGISTER
MULTIPLIER
REGISTER LATCH
MULTIPLIER REGISTER LATCH
MULTIPLIER
REGISTER LATCH
OPERATION
CODE
REGISTER LATCH
OPERATION CODE REGISTER LATCH
OPERATION
CODE
REGISTER LATCH
OPERATION
CODE REGISTER LATCH
OPERATION CODE REGISTER LATCH
OPERATION
CODE
REGISTER LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATE»
STROBE
CONTROL
STROBE
CONTROL
STROBE
CONTROL
STROBE
CONTROL
LATCH
7
LATCH
7
LATCH
7
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
PRODUCT
REMAINDER
LATCH
RESET MEMORY tRROR
INDICATION
RESET MEMORY ERROR
INDICATION
RESETS MEMORY ERROR
INDI
CAT I ON
A,
PARITY
BIT
B
PARITY
SIT
LTE
USE
ONLY
LTE
USE
ONLY
RETURN.
DC
REGULATED
RETURN.
DC
REGULATED
RETURN.
DC
REGULATED
RETURN. REGULATED
DC
RETURN. REGULATED
i;C
NOTE
*DENOTES
INPUTS
TO
COMPUTER.
nlNDICATES LOWER CASE LETTER
Figure
3-2.
Computer
Interface
Signals
(Sheet
2)
3-3
NAME
CONNECTOR
PIN
FUNCTION
A1G5VN
A2.G5VN
A3G5VN
A1PBVN
A2PBVN
A3PBVN
A1WDA
A2WDA
A3WDA
A1XDA
A2XDA
A3XDA
A1YDA
A2YDA
A3YDA
A1ZDA
A2ZDA
A3ZDA
B01N
B02N
B03N
INTRLK
INTRLK
SR07
SR08
SR09
SR1.0
SR11
SR12
SR13
SR14-
SRI
5
SRI
6
SR17
SR18
SR19
SR20
SR21
SR22
SR23
SR24
SR25
SR26
SR27
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3 •
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3.
J3
J3
J3
J3
J3
J-3
J3
J3
J3
J3
J3
J3
J3
J3
J3
J3 .
J3
J3
C
n'Y
np
ns
nA
.
R
nB
K
N
F
J
HH
H
nH
QK
G
M
nj
DD
nF
a\f
W
X
E .
L
P . .
S
z
nC
Q
^
Q
E
nG
nl
nN
nR
nT
nu
nw .
nx
nz
CC
EE
FF
GG
A
B
D
T
U
V
Y
nM
nQ
AA
BB
CHANNEL
1,
TIMING
SYNC
FOR
DATA
CHANNEL
2,
TIMING SYNC
FOR
DATA
CHANNEL
3,
TIMING
SYNC
FOR
DATA
CHANNEL
1,
TIMING SYNC
FOR
DATA
CHANNEL
2,
TIMING
SYNC
FOR
DATA
CHANNEL
3,
TIMING SYNC
FOR
DATA
CHANNEL
1,
TIMING SYNC
FOR
DATA
CHANNEL
2,
TIMING SYNC
FOR
DATA
CHANNEL
3,
TIMING
SYNC
FOR
DATA
CHANNEL
1,
TIMING
SYNC
FOR
DATA
CHANNEL
2,
TIMING
SYNC
FOR
DATA
CHANNEL
3,
TIMING
SYNC
FOR
DATA
CHANNEL
1,
TIMING SYNC
FOR
DATA
CHANNEL
2,
TIMING
SYNC
FOR
DATA
CHANNEL
3,
TIMING SYNC
FOR
DATA
CHANNEL
1,
TIMING
SYNC
FOR
DATA
CHANNEL
2,
TIMING
SYNC
FOR
DATA
CHANNEL
3».
TIMING
SYNC
FOR
DATA
2.048
MC
TIMING
2.048
MC
TIMING
2.048
MC
TIMING
LTE
INTERLOCK
FOR LTE USE
ONLY
LTE
INTERLOCK
FOR LTE USE
ONLY
SIGNAL RETURN.. LINE 07-A1XDA
SIGNAL RETURN.. LINE
08-A2WUA
SIGNAL RETURN. LINE 09-A3PBVN
.
SIGNAL RETURN. LINE 10-A3YDA
SIGNAL RETURN, LINE 11-A2PBVN
.
SIGNAL RETURN, LINE
12-A1ZOA
.
SIGNAL R.ETURN, LINE 13-A1YDA
SIGNAL RETURN, LINE
14-A2XOA
.
SIGNAL RETURN, LINE
15-A2ZDA
SIGNAL RETURN, LINE 16-A3WDA
SIGNAL
RETURN, LINE 17-A3G5VN
SIGNAL RETURN, LINE 18-A1G5N
SIGNAL RETURN, LINE 19-A1WDA
SIGNAL RETURN, LINE
20-B01N
SIGNAL RETURN, LINE
21-B02N
SIGNAL RETURN, LINE 22-A2YJA
SIGNAL RETURN, LINE
23-A3ZDA
SIGNAL RETURN/LINE 24-A3XOA
SIGNAL RETURN, LINE
25-BC3N
SIGNAL RETURN, LIKE
26-A3XDA
SIGNAL RETURN, LINE 27-A2G5VN
ADAPTER
ADAPTER
ADAPTER,
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER
ADAPTER.
ADAPTER
ADAPTER
ADAPTER
NOTE
#DENOTES
INPUTS
TO
COMPUTER, nlNDICATES LOWER CASE LETTER
Figure 3-2. Computer
Interface
Signals
(Sheet
3)
3-4
NAME
CONNECTOR
PIN
FUNCTION,
A1AI3V
A2AI3V
A3AI3V
A1PIOV
A2PIOV
A3PIOV
EP01
EP02
EP03
EP04
EP06
EP07
INTRLK
INTRLK
SR28
SR29
SR30
SR31
SR32
SR33
SR34
SR35
SR36
SR37
SR38
THERM1
THERM2
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
J4
nM
nz
nQ
GG
U
u
w
nR
T
AA
V
nN
nG
nH
A
B
P
S
X
z
np
as
BB
CC
HH
Y
D
E
F
G
H
J
K
L
M
N
R
aA
nB
aC
nD
a£
nF
nl
nj
nK
nT
PU
av
nw
nx
QY
DD
EE
FF
CHANNEL
1»
ACCUMULATOR THIRD DELAY LATCH
CHANNEL
2.
ACCUMULATOR THIRD DELAY LATCH
CHANNEL
3»
ACCUMULATOR THIRD DELAY LATCH
CHANNEL
1,
PROCESS INPUT-OUTPUT
CHANNEL
2»
PROCESS INPUT-OUTPUT
CHANNEL
3»
PROCESS
INPUT-OUTPUT
ERROR
SIGNAL
01
ERROR
SIGNAL
02 . .
ERROR
SIGNAL
03
ERROR
SIGNAL
04
ERROR
SIGNAL
06 ' • .
ERROR
SIGNAL
07
LTE
INTERLOCK
FOR LTE USE
ONLY
LTE
INTERLOCK
FOR LTE USE
ONLY
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
THERMISTOR
THERMISTOR
RETURN*
RETURN*
RETURN*
RETURN.
RETURN.
RETURN.
RETURN.
RETURN.
RETURN.
RETURN.
RETURN,
1
1
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE.
LINE
LINE
LEAD
1
LEAD
2
28-EP06
29-A1PIOV.A3PIOV
30-A2AI.3
31-EP03
32-EP01
33-THEKM
34-EPC7
35-EPC2
36-EP04
37-A3AI3V
38-A1AI3V
THERM
2,
NOTE
*DENOTES
INPUTS
TO
COMPUTER,
nINDICATES
LOWER
CASE
LETTER
Figure
3-2.
Computer
Interface
Signals
(Sheet
4)
3-5
NAME.
CONNECTOR
\ PIN
FUNCTION.
A1EAMV
A2EAMV
A3EAMV
A1EBMV
A2EBMV
A3EBMV
*A1DATAV
*A2DATAV
*A3DATAV
*A1HALTV
*A2HALTV
*A3HALTV
*A1INTCV
*A2INTCV
*A3INTCV
A1TLCV
A2TLCV
A3TLCV
EP05
EP08
;
EP09
EP10
EP11
EP12
EP13
INTRLK
INTRLK
SR39
SR40
SR41
SR42
SR43
SR44
SR45
SR46
SR47
SR90
THERM4
THERMS
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
J5
J5 :
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5 .
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
•
np
nz
AA
U
nj
'
n<
R
GG
nB
P
A
G
N
FF
nC
T
S
al
H
Z
EN
V
E
DQ
B5
'
K
L
6
C
.w
QA
a'D
nH
ns
nx
cc
nR
D
Y
F
J
M
X
aE
nF
nG
aw
nT
nu
nv
nw
ay
DD
EE
HH
CHANNEL
•!»
EVEN' MEMORY, ERROR
: ' „
CHANNEL
2..EVEN
MEMORY ERROR
- .;,
CHANNEL
3»
EVEN MEMORY ERROR
. ^ •
CHANNEL
1» ODD
MEMORY ERROR
..
....
CHANNEL
2»
ODD•MEMORY
.ERROR
. . . .
CHANNEL
3» ODD
MEMORY. ERROR
- •• ,.
CHANNEL
1,
COMPUTER DATA INPUT
CHANNEL
2»
COMPUTER
DATA INPUT
CHANNEL
3»
COMPUTER
DATA INPUT
CHANNEL
1>
HALT SIGNAL
-.' . ,
CHANNEL
2»
HALT
SIGNAL-
CHANNEL
3»
HALT SIGNAL
" . • .
CHANNEL
1»
INTERRUPT COMPUTER
CHANNEL
2»
INTERRUPT COMPUTER
-CHANNEL
3»
INTERRUPT COMPUTER-
CHANNEL
1»
SIMULTANEOUS
MEMORY ERROR
CHANNEL
2»
SIMULTANEOUS MEMORY ERROR
CHANNEL
3»
SIMULTANEOUS MEMORY ERROR
ERROR
SIGNAL
05
ERROR
SIGNAL
08
ERROR SIGNAL
09
ERROR
SIGNAL
1C
ERROR SIGNAL
11 . . . .
ERROR.SIGNAL
12 . . ; .
ERROR SIGNAL
13
LTE
INTERLOCK
FOR
LTfc
USE
ONLY
. ,
LTE
INTERLOCK
FOR LTE USE
ONLY
SIGNAL RETURN. LINE
39-EP10
SIGNAL RETURN* LINE 40-.THERM3»THERM4
SIGNAL RETURN. LINE
41-EP09
SIGNAL RETURN*
LINE
42-EP11
SIGNAL
RETURN, LINE
43-EPG5
.
SIGNAL RETURN 44-1
NTC»
HALT, TLC,
EAK AND
t.BM
SIGNAL RETURN
LINE
45-EP08
SIGNAL
RETURN,
LINE
46-DATAV
FOR
CHANNELS.
1, 2,
SIGNAL RETURN, LINE
47-EP13
. :
SIGNAL RETURN LINE
90-EP12
..
THERMISTOR
2
LEAD
2 .
THERMISTOR
2
LEAD
1 '
NOTE
^DENOTES
INPUTS
TO
COMPUTER, nlNDICATES LOWER
CASE
LETTER
Figure
3-2. Computer
Interface Signals (Sheet
5)
3-6
NAME
CONNECTOR
i PIN
FUNCTION'
INTRLK
INTRLK
SR48
SR49
SR50
SR51
SR52
SR53
SR54
SR55
SR56
SR57
SR58
SR59
SR60
SR61
SR62
SR63
SR64
SR65
SR66
SR67
SR68
SR69
SR70
SR71
*V1
01
*V1
02
*V1
03
*V1
04
*V1
05
*V1
06
*V1
07
*V1
08
*V1
09
*V1 10
*V1 11
*V1 12
*V1 13
*V1
14
*V1 15
*V1 16
*V1 17
*V1 18
*V1 19
*V1
20
*V1 21
*V1
22
*V1 23
*V1
24
SPARE
SPARE
SPARE
SPARE
SPARE
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
J6
K
L
H
N
P
R
nC
nD
n£
aF
QG
J
nH
Ql
nj
nK
nM
DU
nv
aw
ax
DY
EE
FF
GG
HH
A
B
C
D
E
F
T
U
V
w
X
Y
Z
nA
S
aN
ap
no
aR
nS
DZ
AA
BB
CC
G
M
aB
LTE
INTERLOCK
FOR LTE USE
LTE
INTERLOCK
FOR LTE USE
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
'
SIGNAL
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VDC,
6
VOC,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
RETURN,
LINE
1
LINE
2
LINE
3
LINE
4
LINE
5
LINE
6
LINE
07
LINE
08
LINE
09
LINE
10
LINE
11
LINE
12
LINE
13
LINE
14
LINE
15
LINE
16
LINE
17
LINE
18
LINE
19
LINE
20
LINE
21
LINE
22
LINE
2?
LINE
24
LINE
LINE
LINE
LINE
LINE
LINE.
LINE
LINE
LINE
LINE
LINE
LINE-
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
48-V1
49-V1
50-V1
51-V1
52-V1
53-V1
54-V1
55-V1
56-V1
57-V1
58-V1
59-V1
60-V1
61-V1
62-V1
63-V1
64-V1
65-V1
66-V1
67-V1
68-V1
69-V1
70-V1
71-V1
ONLY
ONLY
05
21
15
07
04
13
14
20
24 •
06
23
22'
16
Oo" '
01
12
19 .
18
17
09
17
10
02 .
03
DO
NOTE
*OENOTES
INPUTS
TO
COMPUTER,
nINDICATtS
LOWER
CASE
LETTER
Figure
3-2. Computer Interface Signals
(Sheet
6)
3-7
NAME
CONNECTOR
PIN
FUNCTION
*ETI-1
*ETI-2
INTRLK
INTRLK
SRMEMOl
SRMEM02
SRMEM03
SRMEM04
SRMEM05
SRMEM06
SRMEM07
SRMEM08
SRMEM09
SRMEM10
SRMEM11
SRMEM12
SR73
SR75
SR76
SR77
SR78
SR79
SR80
SR82
SR83
SR85
*V1MEM1
*V1MEM2
*V1MEM3
*V20AM1
*V20BM2
*V20BM1
*V20AM2
*V20
01
*V20
02
*V3MEM1
»V3MEM2
*V3 01
*V3
02
*V3
03
*V3
04
*V3 05
*V3
06
*V3
07
*V3 08
*V3
09
*V3 10
*V5MEM1
#V5MEM2
*V5 01
*V5
02
SPARE
SPARE
SPARE
SPARE
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7.
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
E
F
GG
HH
: A
B
.
C
D
..U
V
Y
aB
G
no
AA
.
H
nD
J
M
nG
nl
.
nj
DM
nx
nZ
"
EE
nR
BB
CC
nA
nN
W
nT
L
nF
X
np
nH
N
P
R
S
nv
nY
nH
aw
FF
Z
ns
K
n£
T
aC
DU
DD
ELAPSED
TIME INDICATOR
1
ELAPSED
TIME INDICATOR
2
LTE.
INTERLOCK
FOR LTt USE
ONLY
LTE
INTERLOCK
FOR LTE USE
ONLY
MEMORY SIGNAL
RETURN*.
LINc
01-V20bMl
MEMORY SIGNAL RETURN. LINE
02-V3MEM1
MEMORY SIGNAL RETURN. LINE
03-V1MEM1
MEMORY SIGNAL RETURN. LINE
04-V20AM1
MEMORY SIGNAL RETURN. LINE
05-V20BM2
MEMORY SIGNAL RETURN. LINE
.06-V3MEM2
MEMORY SIGNAL RETURN, LINE
07-V5MEM1
MEMORY SIGNAL RETURN. LINE
0-V5MEM2
MEMORY SIGNAL RETURN, LINE
09-V20AM2
MEMORY SIGNAL RETURN LINE
10-V1MEM3
MEMORY SIGNAL RETURN, LINE 11-V1MEM2
SIGNAL RETURN. LINE
73-V5
02
SIGNAL,
RETURN. LINE
75-V5
01
SIGNAL
RETURN.
LINE
76-V20
01
SIGNAL RETURN. LINE
77-V20
02
SIGNAL
RETURN.
LINE
78-V3
01. V3 02
SIGNAL RETURN. LINE
79-V3
03, V3 04
SIGNAL RETURN. LINE
SO-V3
05, V3 08
.SIGNAL RETURN. LINE
82-V3
09. .
SIGNAL RETURN. LINE
83-V3
07. V3 10
SIGNAL RETURN, LINE
85-V3
06
6
VDC,
LINE
01,
MEMORY
6
VDC,
LINE
02,
MEMORY
6
VDC,
LINE
..03,
MEMORY
20
VDC,
LINE
1,
EVEN MEMORY
20
VDC,
LINE
02, ODD
MEMORY
20 VDC
LINE
01 ODD
MEMORY
20
VDC,
LINE
2,
EVEN MEMORY
20
VDC.
LINE
01
20
VDC.
LINE
02.
-3
VDC,
LINE
01
MEMORY
-3
VDC.
LINE
02,
MEMORY
-3
VDC,
LINE
01
-3
VDC.
LINE
02
-3
VDC,
LINE
03
-3
VDC,
LINE
04
-3
VDC,
LINE
05
-3
VDC,
LINE
06
-3
VDC.
LINE
07
-3
VDC,
LINE
08
-3
VDC,
LINE
09
-3
VDC,
LINE
10
12
-VDC, LINE
01,
MEMORY
12
VDC,
LINE
02,
MEMORY
12
VDC,
LINE
01
12
VDC,
LINE
02
NOTE
*DENOTES
INPUTS
TO
COMPUTER.
nINDICATtS LOWER
CASt
LETTER
Figure
3-2.
Computer
Interface Signals (Sheet
7)
3-8
NAME
CONNECTOR
PIN
FUNCTION
A1A1V
A2A1V
A3A1V
A1A2V
A2A2V
A3A2V
A1A3V
A2A3V
A3A3V
A1A4V
A2A4V
A3A4V
A1A5V
A2A5V
A3A5V
A1A6V
A2A6V
A3A6V
A1A7V
A2A7V
A3A7V
A1A8V
A2A8V
A3A8V
A1A9V
A2A9V
A3A9V
A1TRSV
A2TRSV
A3TRSV
INTRLK
INTRLK
SR86
SR87
SR88
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
T
nM
np
DD
BB
AA
nN
CC
nQ
FF
GG
ol
R
aw
nj
nv
QY
nK
A
X
nR
EE
HH
S
Y
C
W
F
E
D
K
L
V
z
nl
B
G
H
J
M
N
P
u'
aA
nB
nC
nD
nE
nF
nG
nH
as
nT
nu
nx
CHANNEL
1,
OPERAND ADDRESS
3IT 1
CHANNEL
2»
OPERAND ADDRESS
BIT 1
CHANNEL
3.
OPERAND ADDRESS
BIT 1
CHANNEL
1»
OPERAND ADDRESS
BIT 2
CHANNEL
2»
OPERAND ADDRESS
BIT 2
CHANNEL
3»
OPERAND ADDRESS
BIT 2
CHANNEL
1»
OPERAND ADDRESS
oIT 3
CHANNEL
2.
OPERAND ADDRESS
BIT 3
CHANNEL
3»
OPERAND ADDRESS
oIT 3
CHANNEL
1»
OPERAND ADDRESS
BIT 4
CHANNEL
2»
OPERAND ADDRESS
BIT 4
CHANNEL
3»
OPERAND ADDRESS
BIT 4
CHANNEL
.1*
OPERAND ADDRESS
BIT 5
CHANNEL
2»
OPERAND ADDRESS
BIT 5
CHANNEL
3»
OPERAND ADDRESS
BIT 5
CHANNEL
1»
OPERAND ADDRESS
BIT 6
CHANNEL
2»
OPERAND ADDRESS
3IT 6
CHANNEL
3»
OPERAND ADDRESS
BIT 6
CHANNEL
1,
OPERAND ADDRESS
BIT 7
CHANNEL
2»
OPERAND
ADDRESS
BIT 7
CHANNEL
3»
OPERAND ADDRESS
BIT 7
CHANNEL
1,
OPERAND ADDRESS
BIT 8
CHANNEL
2.
OPERAND
ADDRESS
BIT 8
CHANNEL
3»
OPERAND ADDRESS
BIT 8
CHANNEL
1»
OPERAND
ADDRESS
BIT 9
CHANNEL
2»
OPERAND ADDRESS
BIT 9
CHANNEL
3»
OPERAND ADDRESS
BIT 9
CHANNEL
1.
TRANSFER REGISTER OUTPUT
CHANNEL
2.
TRANSFER
REGISTER OUTPUT
CHANNEL
3»
TRANSFER REGISTER OUTPUT
LTE
INTERLOCK
FOR LTE USE
ONLY
LTE
INTERLOCK
FOR LTE USE
ONLY
.
SIGNAL
RETURN*
LINE
86
OPERAND ADDRESS BITS
Al,A2»
A3»A7,
AND A9 FOR
CHANNELS
1.2.AND3
SIGNAL
RETURN.
LINE
87
TRSV»
CHANNELS 1»2»
AND 3
SIGNAL RETURN.
LINE
88
OPERAND ADDRESS BITS A4.A5»
A6. AND A8 FOR
CHANNELS 1..2.
AND 3
NOTE
*DENOTES
INPUTS
TO
COMPUTER.
^INDICATES
LOWER CASE LETTER
Figure
3-2.
Computer
Interface
Signals
(Sheet
8)
3-9
DATA
ADAPTERCOMPUTER
Power
Supply
i JN vv B
Power
I •
H +20
'ower
Sequencing
+6
+12
-3
C4RDN
Real
TimeCCSL
Relay
Assy
DOMS
i-
C1RD
Interrupt
Processor
C4RD
Accel
Processor
Computer
Data
Selector
Tags
J20
vv
|
Power
J15
y. B
HALTV
»'|
J10
vv \
Power
J21
w \
TB«v
^-»-
J°9»
AI3V
« J°5
„
JOS
„
J04
r
1
1
i
1
Arithmetic
i
Element
*-
AI3
Latch
1
1 1
1 Rur
i * Lot
1
'
Prog
ch
Data
Control
Element
TRS
Addres
~
Lotch
Re9'ste
— Al Thr
s
r
Bits
.. A9
Program
Control
Element
EXTERNAL
'
EQUIPMENT
Error
Monitor
Registers
DATAV
«J05
JlSvv
A1V
thru
A9V
PIOV
INTCV
tJOS
,
J04
„
JOS
Timing
Element
I
60(1-2-3)
N
G5VN
,
JOS
.
JOS
J05
(W-X-Y-Z)
DA
J03
PBVN
JlSvv
TLCV,J05
I I
EAMV
JOS
EBMV
J05
I
Memory
Control
|
Element
I
I
I
Memory
Select
Error
Monitor
Figure
3-3.
Computer
-
Data Adapter Intercon-
nection Block Diagram
3-10
Changed
4
January 1965
COMPUTER
Timing
Element
Timing
Gate
Generator
Phase
Generator
Clock
Generator
1
1
Module
Switching
Voltages*
.
Memory
&
Logic Voltages
*
+6
VDC to
Logic*
JOKvl
"\
J06V,
1
ff 1
J07vv
1
1
Power
Power
Power
„
J19
jj
J07
V.V
xx J06
\v
Power
j
Sequencing
&
Relay
Assy
ff J14 TO
Error
Checking
! '
Muitiply-Divide
Element
Figure
3-4.
Computer
and
LVDC-ME
Intercon-
nection
Block Diagram
3-11
SECTION
IV
TEST EQUIPMENT
AND
SPECIAL TOOLS.
4-1. TEST EQUIPMENT.
4-2.
STANDARD
TEST EQUIPMENT.
4-3.
The
standard
test
equipment recommended
to
maintain
the
computer
is
listed
in
figure 4-1.
4-4. SPECIAL TEST EQUIPMENT.
4-5.
The
special
test
equipment
required
to
maintain
the
computer
is
listed
in
figure
4-2.
-.. ' ' .' . . '. ; '.-•'.-•
'''•''•.-'"..•' '•'••
:
4-6. SPECIAL TOOLS.
4-7.
The
special
tools
recommended
to
maintain
the
computer
are
listed
in
figure 4-4.
Name
Differential Voltmeter
Volt- Ohm- Ammeter
Oscilloscope
Oscilloscope
Adapter
Oscilloscope
Plug-
In
Unit
Model
or
Type
803-
B
630-
A
58
5 A
81
M
Vendor
John Fluke Mfg.
Co. ,
Inc.
Triplett
Electrical
Instrument
Co,
Tektronix,
Inc.
Tektronix,
Inc.
Tektronix,
Inc.
Figure
4-1. Standard
Test
Equipment
Table
4-1
Name
Manufacturer's
Designation
Index
No.
(Figure 4-3)Description
Book
Cart
IBM
6900039
Equipment
Test
Stand
Launch
Vehicle
Digital Com-
puter-Manual
Exerciser
Test
Program
Tape
IBM
6940100
IBM
6902000
MD1
IBM
6001225
Movable
book
case,
used
for .
storage
of
prime
and
test
equipment
manuals
and
logic
diagrams.
Supports
the
computer
and
provides
cooling
air
during
test.
Used
to
test
and
evaluate
com-
puter operation.
Contains
a
program which,
when
loaded into
the
com-
puter memory,
permits
the
Launch
Vehicle Digital
^Computer-Manual
Exerciser
to
check each functional
part
of the
computer that
can
be
exercised
by a
pro-
gram.
Figure
4-2. Special
Test
Equipment Table
4-2
Changed
4
January 1965
.
...'.-ii^i-rt-'-vtr
Figure
4-3. Special Test
Equipment
4-3
Name
Handling Dolly
Lift
Handles
Memory
Handle
Page
Extractor
Test
Point
Adapter
Torque Tool
Kit
Manufacturer's
Designation
IBM
658042
IBM
D-656101
IBM
658044
IBM
657922
Number
to be
sup-
plied.
Number
to be
sup-
plied.
Index
No.
(Figure 4-5)
3
2
1
Description
Supports computer while being
maintained.
Provide
a
means
for
handling
and
lifting
the
computer
during
general handling
activity.
Used
to
disengage memory
from
its
mating receptacle.
Also recommended
for
general handling
of
memory.
Used
to
mechanically engage
or
disengage
the
page con-
nector
from
its
mating
re-
ceptacle.
Use
to
provide
access
to
test
points
on
page
assemblies.
Contains
special torque tools
required
for
torquing those
items
replaced
during
labo-
ratory maintenance.
Figure
4-4. Special Tools Table
4-4
Changed
4
January 1965
Figure 4-5. Special Tools
4-5/4-6
SECTION
V
PREPARATION
FOR
USE, STORAGE
AND
SHIPMENT
5-1. PREPARATION
FOR
USE.
.
5-2.
The
computer
is
shipped
in a
reuseable
shipping container
(part
number 6019994,
figure
5-1). Included
in the
container, although
not
shown
in
figure 5-1,
is a
shock
re-
corder (part number 6019637).
To
remove
the
computer
from
the
container, proceed
as
follows:
, : J
a.
Turn
pressure
equalizer
screw
(on
shipping container)
two
turns
counterclockwise.
b.
Unlatch
and
remove container cover.
c.
Remove
the
four
mounting bolts securing
the
computer
to the
container frame.
,'•."..".
WARNING
••• . :
The
computer
shall
be
lifted
by at
least
two
persons.
Otherwise,
a
person
may be
injured
or the
computer damaged.
d.
Attach
the
lift
handles
to the
computer,
as
described
in
paragraph 5-8; remove
the
computer
from
the
container
and
place
on a
handling
dolly
or
test
stand.
(Refer
to
section IV.)
e.
Reinstall
the
mounting
bolts
for
safekeeping.
f.
Remove
the
shock recorder after removing
the
four
socket head screws
which
attach
it to its
bracket; then replace socket head
screws
in
bracket
for
safekeeping.
g.
Open
the
shock
recorder.
gl.
Remove
the
spool that contains
the
recorded portion
of
chart paper
(figure
5-2).
CAUTION
When
removing chart paper, handle chart
paper carefully.
Cut (do not
tear)
the
chart
paper
to
detach recorded portion.
The
paper
is
pressure
sensitive,
and
data
may
be
obliterated
by
rough
or
excessive
handling.
g2.
Cut the
chart paper, remove
it
from
the
spool,
and
replace
the
spool
in the
recorder.
Changed
4
January 1965
5-1
Desiccant
Receptacle
Mounting
Bolts
(4)
Shock Recorder Pressure
Bracket
Equalizer
Screw
Figure 5-1. Reuseable Shipping Container
Figure 5-2. Removing Roll Chart From Shock Recorder
5-2
Changed
4
January 1965
NOTE
The
recorder
clock mechanism will operate
until
its
spring mechanism
has
unwound.
If
the
recorder
is not to be
used immediately,
do
not
rethread
the
chart paper. Instead,
tape
the
loose
end of the
chart paper
to the
writing
plate. (See
figure
5-2.)
This procedure
saves paper
and
protects
the
styluses
which
would
otherwise
rest
on the
hard surface
of
the
plate.
g3.
Rethread
the
chart paper onto
the
takeup spool
(figure
5-3),
or
tape
the
paper
to
the
writing
plate.
g4.
Close
and
latch
the
shock
recorder.
g5.
Reinstall
the
shock
recorder
(handle
side
up) in the
shipping container.
g6.
On a
blank portion
of the
removed section
of
chart paper, record
the
Government
Bill
of
Lading
Number
Receiving
Location
and
Receiving Individual's Signature
Unit
Name,
Part
Number,
and
Serial
Number
Container
Serial
Number
and
Recorder
Serial
Number
Data
and
Local Time recorder
was
opened.
TAKEUP
SUPPLY
( B )
FEED
DIAGRAM
(A)
ROLL
CHART
PARTIALLY
INSTALLED
(C)
ROLL
CHART
COMPLETELY
INSTALLED
Figure
5-3.
Installing
Roll
Chart
in
Shock
Recorder
Changed
4
January 1965
5-3
h.
Ship removed section
of
chart paper
to:
Saturn
Programs
Office,
Department
839
IBM
Space Guidance Center
Owego,
New
York,
13827
'
hi. Use a
vacuum cleaner
to
clean
the
interior
of
container
if
foreign material
or
debris
is in the
shipping container.
i.
Secure cover
on
shipping container; then
store
container
for
reuse.
5-2A. INSPECTION
AND
TEST.
5-2B. After
the
computer
has
been unpacked, proceed
as
follows:
a.
Examine
the
exterior
of the
computer
for
mechanical damage, noting
any
evidence
of
impact
or
other
severe
mechanical
stress.
Check
for
loose screws
and
broken
or
missing connector dust
covers.
If
extensive abnormalities
are
noted, remove covers
and
inspect interior
of the
computer.
(Refer
to
Section
K for
disassembly instructions.)
b.
Remove
and
store
connector dust covers.
c.
Perform
an
electrical
checkout
of the
computer.
(Refer
to
Technical Manual, Check-
out
Procedures
for
Saturn
LVDC
and
LVDA.)
5-3. PREPARATION
FOR
STORAGE.
5-4.
The
computer
is
stored
in a
reuseable shipping container (part number
6019994,
figure
5-1).
The
computer
is
prepared
for
storage
as
follows:
a.
Install dust covers (part number
6036037)
on the
eight computer connector jacks.
al.
Unlatch
and
remove shipping container cover.
a2. Use a
vacuum cleaner
to
clean interior
of
container
if
foreign
material
or
debris
is in the
shipping container.
b.
Remove mounting bolts
from
computer shipping container.
bl.
Attach
lift
handles
to
computer
as
described
in
paragraph 5-8.
WARNING
The
computer
shall
be
lifted
by at
least
two
persons.
Otherwise,
a
person
may be
injured
or the
computer damaged.
c.
Place
computer
on
container
mounting
frame
and
secure
with
mounting
bolts. Tighten
mounting
bolts
with
a
torque
of 250
inch-pounds.
d.
Place
17
units
of
desiccant
in
receptacle
provided.
5-4
Changed
4
January 1965
NOTE
The
17
units
of
desiccant
are
packaged
in
three
bags.
The
package
part
number,
units
of
desiccant
per
package,
and the
quantity
of
each
part
number used
are as
follows:
IBM
Part
Number
No. of
Units Quantity Used
6019623
8 2
6019653
1 1
e.
Secure cover
on
shipping
container.
f.
Turn
pressure
equalizer
screw
fully
clockwise.
NOTE
During
storage,
the
container humidity
indicator should
be
checked
at
least
once
a
week (more
often
if
high
humidity condi-
tions.prevail).
If the
"40"
sector
of the
humidity
indicator
turns
pink,
the
tainer
dessicant
should
be
replaced.
5-5. PREPARATION
FOR
SHIPMENT.
5-6.
The
computer
is
shipped
in a
reuseable
shipping container (part number 6019994,
figure
5-1). Included
in the
container
is a
shock
recorder
(part
number 6019637).
The
computer
is
prepared
for
shipment
as
follows:
a.
Install
dust covers (part number
6036037)
on the
eight computer connector jacks,
al.
Unlatch
and
remove container cover.
b.
Remove mounting
bolts
from
computer shipping container.
WARNING
The
computer
shall
be
lifted
by at
least
two
persons.
Otherwise,
a
person
may be
injured
or the
equipment damaged.
c.
Place
computer
on
container mounting frame
and
secure with mounting
bolts.
Tighten
mounting
bolts
with
a
torque
of 250
inch-pounds.
Changed
4
January
1965
5-5
CAUTION
Verify
that shock
recorder
styluses
are
marked
"100g".
Otherwise,
recorder
will
not be
capable
of
recording excessive
shock with accuracy.
cl.
Remove
the
shock
recorder
after removing
the
four
socket head screws
which
attach
the
recorder
to its
bracket.
Replace socket head screws
in
bracket
for
safe-
keeping.
c2.
Open
the
shock recorder
and
check
for
damage.
d.
Thread
roll
chart onto takeup spool
of
shock recorder. (See figure 5-3.)
dl.
Close cover
and
strike
recorder
sharply
against
floor. Open cover
and
verify that
all
three
styluses
have made
a
discernable impression
on the
chart
paper.
NOTE
A
full
roll
of
chart paper
is
long
enough
to
record
shock
for a
period
of 60
half
days
(30
days).
The
numbers
on the
left-
hand
margin indicate
the
number
of
half
days remaining
on the
roll.
The
mechanism
is
capable
of
running
for
eight days
(16
half
days).
Verify
that
the
number
on the
left-
hand
margin
is 16 or
greater
at the
point
where
recording
starts.
Reorder chart
paper
from
the
following
address:
-
Electrical Standards, Dept.
331
Attention:
Manager
IBM
Space Guidance Center
Owego,
New
York, 13827
d2.
On the
chart paper record
the
Government
Bill
of
Lading Number
Sending
Location
and
Sending Individual's Signature
Unit
Name,
Part
Number
and
Serial
Number
Container
Serial
Number
and
Recorder
Serial
Number
Date
and
Local Time recorder
was
started
5-6
Changed
4
January 1965
NOTE
The
chart paper
is
calibrated
in
A.M.
and
P.M. hours,
but it is not
necessary
to .
align
the
paper
with
the
local time.
Simply
write
the
local time
at the
point
where
the
recorder
was
started.
•:,.••
d3.
Wind
the
shock recorder,
and
verify
that
the
paper
is
moving
and
that
all
three
styluses
are
tracking.
d4.
Close
and
latch
the
shock recorder,,
but do not
lock
the
latch.
e.
Remove
socket head screws
from
shock recorder
mounting
bracket.
f.
Install shock recorder
on
bracket, using socket head screws previously removed.
g.
Place
17
units
of
desiccant
in
receptacle provided.
' . '-. '•'.'••"-. •'••-•;•
'•'•:••.':
'•;•-;•'..'
NOTE.-' '-^'''••v-:"':,.;.-:'v^--'v
'•',-.
• ••
;..'.
The 17
units
of
desiccant
are
packaged
in
<
three ;bags.
; The
package
part
number,
units
of
desiccant
per
package,
and the
quantity
of
each
part
number used
are as
follows:
IBM
Part
Number
No. of
Units Quantity Used
6019623
8 2
6019653
1 1
h.
Secure cover
on
shipping container.
i.
Turn
pressure
equalizer screw
fully
clockwise.
5-7.
GENERAL
COMPUTER
HANDLING.
5-8.
Computer
lift
handles (IBM Tool
Number
D-656101)
are
used
for
general
handling
of
the
computer.
Two
computer
lift
handles .are needed
for
computer handling;
one
handle
is
mounted
on the
left
side
of the
computer
and the
other handle
is
mounted
on the
right side
of the
computer.
Mount
the
computer
lift
handles
as
shown
in
figure
5-4.
Changed
4
January 1965
' 5-7
Figure
5-4.
Computer Lift Handle, Mounted
5-8
Changed
4
January 1965
SECTION
VI
PREVENTIVE
MAINTENANCE
No
preventive maintenance
is
performed
on
the
breadboard models.
6-1/6-2
SECTION
VH
CHECKOUT
7-1.
OPERATING TEST PROCEDURES.
7-2.
Instructions
for
testing
the
computer
are
located
in the
Saturn
V
Launch
Vehicle
Digital Computer
and
Data Adapter Checkout Procedures Laboratory Maintenance
Instructions.
7-1/7-2
SECTION
vm
TROUBLE
ISOLATION
This section
is not
applicable
for
breadboard equipments.
8-1/8-2
SECTION
DC
REPAIR
9-1. REPAIR.
9-2. Laboratory
repair
of the
computer
is
limited
to
replacing page
assemblies
and
toroid memory
assemblies.
Laboratory replaceable
assemblies
are
listed
in
figure 9-1.
The
methods
for
replacing such
assemblies
are
described
in
this
section.
The
computer
is
mounted
on an
equipment
test
stand (IBM
part
number
6940100)
during
repair.
9-3. PAGE
ASSEMBLY
REPLACEMENT.
(See figure 9-2.)
The
page
assemblies
are
accessable
after
removing
the
computer logic cover.
To
replace
a
page assembly pro-
ceed
as
follows:
a.
Remove
the
logic cover
by
removing
and
storing
the 14
mounting
screws
and
washers
located around
the
outer edge
of the
cover.
b.
Locate
the
page assembly
to be
replaced.
(Refer
to
figure 9-3.)
NOTE
Do
not
remove page assembly captive
mount-
ing
screws
from
page assembly until
after
the
page assembly
is
removed
from
computer.
Assembly
6110211
6110212
6110213
6110214
6110215
6110216
6110217
6110218
6110219
6110230
6110231
6110232
6110233
6110234
6110235
6110236
6110237
Location
A4A11
A4A12
A1A3,
A2A3,
A1A7
A1A8
A1A9
A1A10
A1A5
A1A11
A1A12
A1A13
A1A14
A1A15
A1A16
A1A17
A1A18
A1A19
A3
A3
Assembly
6110238
6110239
6110240
6110251
6110252
6111500
6125408
6125409
6125420
6125423
6125424
6125425
6125426
6125427
Location
A1A20
A5A9,
A5A10
A5A11
A1A4,
A2A4,
A3A4,
A4A4
A5A3
A6A2,
A6A3
A5A5
A5A6
A4A5,
A4A6,
A4A7,
A4A8,
A4A9,
A4A13,
A4A14
A5A7,
A5A8
A5A12
A5A13
A5A14
A5A15
Figure
9-1. Laboratory Replaceable Assemblies
9-1
MEMORY
COVER
COVER
MOUNTING
SCREW
(22)
AND
WASHER
MOUNTING
SCREW
(4 PER
ASSY)
AND
WASHER
ELECTRICAL
CONNECTORS
(Jl
THROUGH
J4)
PAGE
ASSEMBLY
(43)
PAGE
MOUNTING
SCREW
(2)
AND
WASHER
ELECTRICAL
CONNECTORS
U5
THROUGH
J8)
TOROID
MEMORY
ASSEMBLIES
LOGIC
COVER
COVER
MOUNTING
SCREW
(14)
AND
WASHER
Figure
9-2.
Computer,
Partially
Disassembled
9-2
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9-3
c.
Unscrew
the two
page assembly captive mounting screws until free
of
mounting
holes.
NOTE
Remove
page
assemblies
with
a
page insertion-
extraction tool
(figure
4-4), hereafter referred
to
as
extractor tool.
d.
Place
extractor
tool over
top of
page assembly; then push locking knob toward page
assembly,
thus locking tool
to
assembly.
e.
Squeeze
extractor
tool handle
to its
limit (disengaging page assembly connector);
then
pull
page
assembly
straight
out.
CAUTION
Hold
page assembly
firmly
to
safeguard dropping
when
releasing
extractor
tool.
f.
Release
page assembly
from
extractor
tool
by
pushing
in the
locking
knob
and
moving
knob
away
from
page assembly.
g.
Remove
and
store
mounting
screws
and
associated fiber washers
from
page assembly.
NOTE
Page assembly removal
is now
complete.
To
install
the
replacement page assembly proceed
with
step
h.
h.
Install
previously removed page assembly
mounting
screws
and
fiber washers (IBM
part
numbers 6110636
and
6113634)
in
replacement page assembly.
i.
Place
extractor
tool over
top of
replacement page assembly; then push locking
knob
toward page assembly, thus locking tool
to
assembly.
CAUTION
Verify
that
A
side
of
page assembly faces
downward
when
inserting page assembly into
computer. Otherwise connector pins will
not
mate with
receptacle.
j.
Insert page assembly into proper computer logic channel location.
9-4
k.
Push
in
extractor
tool locking knob; then move knob away from page
assembly,
thus
releasing
tool
from
page
assembly.
1.
Turn
in the two
page
assembly
mounting
screws;
then torque
screws
to 15
inch-
pounds.
'•.:•-.-......
"-.'-.
' V: - i '
m.
Secure
computer
logic
cover
by
turning
in
cover mounting
screws
and
washers
(IBM
part
numbers
6072520
and
6048641); then, using
the
cross-over
method,
torque
cover mounting
screws
to 10
inch-pounds; •-•'
9-4. TOROID
MEMORY
ASSEMBLY
REPLACEMENT. (See figure 9-2.)
The
toroid
memory
is
accessable
after
removal
of the
computer memory cover.
To
replace
a
toroid
memory
assembly
proceed
as
follows:
a.
Remove
the
memory cover
by
removing
and
storing
the 22
mounting
screws
and
washers
located around cover edge.
NOTE
Memory
assembly
connectors mate with con-
nectors
J2 and J3 of
memory mounting plate
assembly.
NOTE
The
replacement
of the
toroid memory assembly
,
• is
simplified
by the use of the
memory handle.
(Refer
to
figure 4-4.)
•
When
attaching memory handle
to
memory
assembly, attach gripper marked
CONNECTOR
.
END
to
shoulder
screws
at
connector
end of
memory
assembly.
b.
Slide memory handle
grippers
under
four
shoulder
screws
on top of
memory
assembly;
then place tool keeper over memory handle shoulder screw, thus securing
tool
to
assembly.
(See figure 9-4.)
• - .
CAUTION
Hold
memory handle firmly
to
safeguard dropping
memory assembly during removal
of
memory
assembly mounting
screws.
•.•:••
c.
Remove
and
store
the
four memory assembly mounting screws
and
associated
washers.
9-5
b.
jvr-j
I
MEMORY HANDLE
KEEPER
MEMORY HANDLE
GRIPPER
MEMORY HANDLE
SHOULDER
SCREW
MEMORY
ASSEMBLY
SHOULDER
SCREW
©
'nnnnnnnnnani
NOTE: PHANTOM
AREA
INDICATES
MEMORY
ASSEMBLY
Figure
9-4. Memory Handle Secured
to
Memory Assembly
NOTE
The
memory assembly connector
is a
rack-
and-panel type
and
will disengage
from
its <
mating receptacle
on the
memory distribu-
tion
board
as the
memory assembly
is
lifted
out.
d.
Pull
on
memory handle just enough
to
disengage memory assembly connector; then
offset
assembly
enough
to
clear
adjacent memory assembly
and
pull assembly straight
out.
e.
Remove memory handle from memory assembly.
NOTE
Toroid memory assembly removal
is now
complete.
To
install
a
replacement memory
assembly
proceed
with
step
f.
NOTE
When
attaching memory handle
to
memory
assembly,
attach
gripper
marked
CONNECTOR
END
to
shoulder
screws
at
connector
end of
memory
assembly.
9-6
I.
Slide memory handle
grippers
under
four
shoulder screws
on top of
replacement
memory assembly; then place tool keeper over memory handle shoulder screw, thus
securing tool
to
assembly. (See figure 9-4.)
CAUTION
Hold
memory assembly
and
memory handle
firmly
to
safeguard dropping during installation.
g.
Insert replacement memory assembly into proper memory distribution board
loca-
tion; then
verify
that connector
and
receptacle
are
properly mated.
h.
Turn
in
memory assembly mounting screws
with
associated washers (IBM part
numbers
6035770
and
6113635);
then torque screws
to 15
foot-pounds.
i.
Install memory cover
and
turn
in
mounting
screws
with
associated washers (IBM
part
numbers
6076307
and
6048641);
then using
the
cross-over
method
torque screws
to
10
inch-pounds.
9-7/9-8
SECTION
X
DIAGRAMS
10-1. DIAGRAMS.
10-2.
The
diagrams included
in
this
section
are the
drawings required
to
maintain
the
computer.
The
drawings consist
of the
following:
Figure
10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure
10-10.
Figure
10-11.
Figure 10-12.
Figure
10-13.
Figure 10-14.
Figure
10-15.
Figure 10-16.
Figure
10-17.
Figure 10-18.
Figure 10-19.
Figure 10-20.
Figure 10-21.
Figure 10-22.
Figure 10-23.
Figure 10-24.
Figure 10-25.
Figure 10-26.
Figure 10-27.
Figure 10-28.
Figure 10-29.
Figure 10-30.
Figure
10-31.
Figure 10-32.
Figure 10-33.
Clock
Drivers
Logic Diagram
(4
Sheets)
Decoupling
Capacitors (Channel
1)
Logic Diagram
(4
Sheets)
Delay
Lines Logic Diagram
(2
Sheets)
Multiply-Divide
Element Logic Diagram
(12
Sheets)
Add-Subtract
Element Logic Diagram
(4
Sheets)
Transfer Register Bits 10-TRS
and
Control Logic Diagram
(2
Sheets)
Memory
Buffer
Control
and
Parity Counter Logic Diagram
(2
Sheets)
Operation
Code Register Logic Diagram
(4
Sheets)
Timing
Gate Generator Logic Diagram
(2
Sheets)
Phase Generator Logic Diagram
(2
Sheets)
Memory
Module
Registers
Logic Diagram
(2
Sheets)
HOP
Constant Serializer
and
Memory Read Latches Logic Diagram
(2
Sheets)
Memory
Timing Logic Diagram
(4
Sheets)
Memory
Error
Detector Logic Diagram
(8
Sheets)
Transfer Register Bits
1-9
Logic Diagram
(4
Sheets)
Address Register
and
Memory Address Decoder Logic Diagram
(4
Sheets)
Memory
Sector Registers Logic Diagram
(2
Sheets)
Hi-Y
Memory Address Decoder Logic Diagram
(2
Sheets)
Decoupling
Capacitors (Channel
4)
Logic Diagram
(4
Sheets)
Operation
Code Voters Logic Diagram
(4
Sheets)
Timing
Gate
and
Operation
Code
Voters Logic Diagram
(4
Sheets)
Timing
and
Add-Subtract Voters Logic Diagram
(4
Sheets)
Timing
Voters Logic Diagram
(4
Sheets)
(
Timing
and
Multiply-Divide Voters Logic Diagram
(4
Sheets)
Oscillator
and
Buffer
Logic Diagram
(2
Sheets)
Clock
Generator Timing Logic, Logic Diagram
(4
Sheets)
Timing
and
Multiply-Divide Voters Logic Diagram
(4
Sheets)
Multiply-Divide
Voters, Logic Diagram
(4
Sheets)
Decoupling
Capacitors (Channel
5)
Logic Diagram
(4
Sheets)
Memory
Timing Voters Logic Diagram
(8
Sheets)
Memory
Address Decoder Voters Logic Diagram
(8
Sheets)
Memory
Buffer
Registers Logic Diagram
(12
Sheets)
Address Register
and
Memory
Module
Register Voters Logic Diagram
(4
Sheets)
10-1
Figure
10-34.
Transfer
Register
and
Memory Module Register Voters Logic Diagram
(4
Sheets)
Figure
10-35.
Transfer
Register
Voters Logic Diagram
(6
Sheets)
Figure
10-36.
Memory Clock
Driver
and TCV
Logic
Diagram
(2
Sheets)
Figure
10-37.
Memory Sense Amplifiers Logic Diagram
(2
Sheets)
Figure
10-38.
Memory Inhibit
Drivers
Logic Diagram
(2
Sheets)
Figure
10-39.
Memory Y-Address Drivers Logic Diagram
(4
Sheets)
Figure
10-40. Memory Hi-X Address
Drivers
Logic Diagram
(4
Sheets)
Figure
10-41.
Memory Lo-X Address
Drivers
Logic Diagram
(2
Sheets)
Figure
10-42.
X
Memory Address Diode Matrix Schematic Diagram
(2
Sheets)
Figure
10-43.
Y
Memory Address Diode Matrix Schematic Diagram
(2
Sheets)
Figure
10-44. Memory Input-Output Panel Schematic Diagram
(2
Sheets)
Figure
10-45. Memory Distribution Panel Schematic Diagram
(4
Sheets)
Figure
10-47. Interconnection
Al
Back Panel,
List
for
LVDC
Figure
10-48.
Interconnection
A4
Back Panel,
List
for
LVDC
Figure 10-49. Interconnection
A5
Back Panel,
List
for
LVDC
Figure
10-50. Computer, Rear
View
Figure
10-51.
Terminal Block,
Pin
Identification, Channels
1, 4, and 5
10-3. SIGNAL TRACING.
10-4. Signals
may be
categorized into
two
groups:
•
Signals that appear
at the
input-output connectors.
•
Signals that originate
in, and are
used solely
by, the
computer.
Locating
these
two
types
of
signals
and
finding
points
in the
computer where they
may
be
observed
requires
two
different
procedures.
10-5.
TRACING
INPUT-OUTPUT
SIGNALS.
These signals
may be
located
by
referring
to the
interface listing, figure 3-2.
The
signals
may be
checked
by
probing
the A4 and
A5
back panels
at
terminal blocks A4J1 through A4J4,
and
A5J5 through A5J8. (See
figure 10-50.)
NOTE
The
A5J7 terminal block
has the
same
pin
layout
as
A4J4, with
a
different orientation.
The
terminal blocks
are
directly wired
to the
input-output connectors
and the
terminal
block pins have
the
same corresponding designation
as the
connector pins.
To
trace
an
input-output
signal
into
the
logic, refer
to the
interconnection back panel
listings,
figures
10-47 through 10-49.
The
signal
can be
found
under
the
"Net Name" column.
10-2
j
NOTE
Signals originating outside
the
back panel
(listing)
being used,
may
require
the
ref-
erence designator prefix that
is
automat-
ically assigned
to all
signals.
Thus,
if a
signal cannot
be
found
under
the
alphabetic
portion
of the
listing,
be
sure
to
look
under
the
portion
of the
listing
which
con-
tains reference designator prefixes.
Once
the
signal
is
found
in the
listing,
all the pin
locations,
by
reference designator,
are
listed
under
the
"Page-Pin"
and
"Bib-Pin"
columns.
The
reference designator
can
then
be
used
to
find
the
signal
in the
logic. (See figures 10-1 through 10-35.)
NOTE
The
reference designator
for
each MIB-logic
diagram
is
located
on the
right
hand
margin,
white
symbols
on a
black background.
10-6.
TRACING
INTERNALLY
GENERATED
SIGNALS.
These
signals
may be
located
by
referring
to the
Signal-Origin List,
figure
10-46.
The
signal-origin
list
refers
the
reader
to the
appropriate MIB-logic diagram
by
reference designator. (See figures 10-1
through
10-41.)
On the
MIB-logic diagram
are
references
to
test
point locations
on the
logic
page.
If a
signal
is to be
checked
for
which
a
test
point
is not
provided, then
one
of
the
terminal blocks
on the A4 or A5
back panels
may
make
the
desired signal available.
(In
addition, most
of the
channel
4
page pins
are
available
from
the
rear
of the A4
back
panel.)
Look
up the
signal name
in the
appropriate interconnection back panel listing
and
determine whether
or not the
signal goes
to a
terminal block.
If the
signal
is
used
on
both
panels
Al (A2 and A3
also apply
for
redundant circuits)
and A4, the
listing will
show
a
reference
to a
terminal block, reference designator A1EX
or
A4EX.
(See
figure
10-51
to
identify
pin
locations.)
NOTE
A
one-to-one correspondence
exists
between
pins
on the A4 and Al
terminal blocks
due to
the
printed circuit cables interconnecting
the
terminal blocks. (See figure 1-2.)
If
the
signal goes
to a
memory module
from
a
location
in
channel
5, a
reference
to
terminal blocks
A5E3,
A5E5,
or
A5E7
will occur.
Some
of
these locations
are
available
for
probing. (See
figure
10-51
to
identify
pin
locations.
Only
the
upper pins, rows
A
and
B, are
available
for
probing.)
The
points where signals appear
on the
memory
module
and
memory distribution panel
are
illustrated
in
figures 10-44
and
10-45. These
points
are not
available
for
probing.
10-3
Wl
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
Dotted Line
(if
any) Indicates Internal
ULD
Connection
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
Prefix
Reference
Designations
as
Follows: A1A3A
•WN
Figure
10-1. Clock Drivers, Logic Diagram (Sheet
1 of 4)
10-4
XI
BOP
CGPNP
CGQP'
THRU
-
PINS
PIN
1
2
3
i 4
5
6
7
8
9
10
11
12
13
14
15
SIGNAL
CGPP
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SIGNAL
ZF
YF
CGPNP
WF
XF
CONNECTOR
PINS
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SIGNAL
WN
W5
WDA
SIG RET
W7
SIG RET
Wl
W8
W2
W3
SIG RET
SIG RET
W4
W6
VI
VI
CGRP
SIG RET
V3
BOP
CGQP
VI
CGPP
V5
V5
PIN
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
SIGNAL
V5
V5
VI
SIG RET
SIG RET
V3
SIG RET
SIG RET ••
CGPNP
X3
XI
V3
V3
V3
X2
X4
X6
X5
SIG RET
XN
SIG RET
X8
X7
XDA
Figure 10-1. Clock Drivers, Logic Diagram (Sheet
2)
10-5
Yl
CGRNP'
NOTES:
I
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten Line
(if
any)
Indicates Internal
ULD
Connection
4. "N .U ."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A1A3B
Y8
YN
Figure
10-1.
Clock
Drivers, Logic Diagram
(Sheet
3)
10-6
LVDC
BOP
CGPNP
CGQNP
ZDA
-24
-25
THRU
-
PINS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIGNAL
CGPP
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SIGNAL
ZF
YF
CGPNP
WF
XF
•*,
CONNECTOR PINS
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
SIGNAL
. ZDA
Z7 •:
Z8
•
SIG RET
ZN
SIG RET
Z5
Z6.
Z4
Z2
;V3
V3
V3
Zl
•Z3
CGPNP
-
SIG RET
SIG RET
V3
SIG RET
SIG RET
VI
V5
V5
V5
PIN
.52
54
56
58
60
62
64
66
68
70
72
74'
76
78
80
82
84
86
88
90
92
94
96
98
SIGNAL
V5
CGPP
VI
CGQNP
BOP
V3
SIG RET
CGRNP
VI
VI
Y6
Y4
SIG RET
SIG RET
•
Y3
Y2
Y8
.
Yl
SIG RET
Y7
SIG RET
YDA
Y5
YN
-7.8
Figure
10-1; Clock
Drivers,
Logic Diagram (Sheet
4)
10-7
HOI'f.
1,2
•
\
1
e
16
(i
14
g
M
//
A
6
"1$
/f
ft
a
fo
11
H
a
tli
li
14
7
7
7
7
7
7
Cl
Al
ri
Cl
A3
ft
A4
Cl
AS
Cl
Aft
Ci
A^^
Cl
A3
Cl
All
C3
A
10
C3
AM
1
1
?
f
' '
7
;
J
?
f
/
•i
—
''
J'
f
f
Tl
«
(f
Tf
C
a
r/
<\
a
/-/
<\
a
Tl
<j
8
r/
\
a
i
1
f
7
7
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f
1
a
4
"4
7
3
7
'6
7
'7
7
"e
7
'3
)
?
<:/
<:;
Cl
AH
Cl
All
Cl
AIS
Ci
A19
C£
AI6
Ci
AJO
C3
All
CJ
A3I
tr^
u
>i
g
16
A
7
7
*
e
a
e
a
8
SIG RET
VS
Figure
10-2.
Decoupling
Capacitors
(Channel
1),
Logic
Diagram
(Sheet
1 of 4)
10-8
..
SIS
fffT
7
7
; 7
7
7
7
C*
/)/;
n!
,
TPlI
C4
A
16
?
C4
/«5
a \ 7
TPIt
^ ?
C4
/««
8 \ 7
TPl.t
¥
c*
/Jc'6
C3
A/J
CS
Ail
fl
1
7
T?r+
,}
,
jpf5
,1
,
C4
ASi
C«
AI9
C*
/•3J
CJ
»W
CJ
>w
(J
0
^
s
a
CONNECTOR PINS
•
Pin
1
3
.5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A/\SVB1
MSVB1
SIG
RET
;
SIGRET
V4MOD3
V3
V3
V3
V3
V4MOD6
V5
1
V4MOD2
VI
VI
VI
VI
V4MOD4
SIGRET
SIGRET
SIG RET
SIG RET
V4MOD5
Pin
51
53-
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
; SIG
RET
'
SIG RET
SIG
RET.
SIG
R;ET
SIG RET
SIG RET
V3
V3
V3
V3
SIG RET
VI
VI
VI
VI
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
MSVB2
MSVB2
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A4A
Figure
10-2.v-
Decoupling-Capacitors^(Channel 1),; Logic
Diagram
(Sheet
2)
10-9
NOTl
I
Tf*
A/I/I
NU2
NV3
NU
4
HUS
Y4HIOD
t
10
l(.
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e
~1?
W
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14
fl
10
/{
14
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A
fi
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ii
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14
Al
tf
cr
A3
A4
Cf
A&
Ct
J
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7
1
i
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I
1
3
S
7
1
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—
J
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J
1
7—
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7
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7
1
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vs
J
s
7
j
f
s
7
1
—?
J
1
f
J
S
7
—
T
s
7
1
3
S~
7
A6
ft
<ct
A >0
C
1
. \ .
Vo-*—
3
It
S
t* 7
TfS
9
I '
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It
3
14
1
Tf6
•
1 '
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3
7^ Jf*
/« 7
TPf
* \ >
10
3
11
S
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7
TP6
' I '
^ * i
a 7
/< 7
T
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1 /
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J
/* 7
>/^
/W9
C/
g;
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All
r.i
a
73-
ie
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*
w~
ft
14
e
16
/<?
.'.•f
-
ft
W~
tf
>*
.
a
^r-
ff
/V
a
ia
n
f*
sic.
Figure
10-2. Decoupling
Capacitors
(Channel
1),
Logic Diagram (Sheet
3)
10-10
TPII
VI-
1
.
"1
5
7
'T
5
7
5
7
•
1
f
i
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£
7
j
_$
7
j>
•-•
j"
7
T
7
/4<?6
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X^'
A14
Cf
a [ /
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W
1
f4
7
T
a
1 /
7S-*
T
11 i.
M.
J
TPI3
'S
I
li
3
14
7
.
r/>>4
"
I '
16
* i
It
S
14 7
TflS
' 1 '
id
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il
J
14 7
TPIl
n
t -
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7
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/f-
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It S
1* 7
rfia
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W
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7
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7
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SJJ
Cl
A54
All
C.1
ft
)l
/*
0
73—
V
H
e
/i
*
e
w
It
H
a
73—
it
ft
e
10
it
•y
o
10
Ig
14.
e
iq
fi
&—
CONNECTOR
PINS
Pin
2
4
6
e
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40'
42
44
46
48
50
Signal
V3
1
'
V4
MODI
VI
1
SIGRET
1
VI
1
NU5
SIGRET
1
NU4
V3
Pin
52
54
56
•
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V3
1
NU3
VI
1
SIG RET
1
1
NU2
V5
1
NU1
V5
i
V4
MOD7
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference
Designations
as
Follows: A1A4B
•j/c
nt r
Figure
10-2.
Decoupling
Capacitors
(Channel
1),
Logic-Diagram (Sheet
4)
TP5
LL44SX
TPI5
W7
DDISA-
vn
IN
"
X
3
A
Up]
a
\\
f-
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X)
AM
—
\i
ft
A
13
—\io
1
i
A
14
y
>U3
f
S
5TP
I>I4
CiH
7.6
t,lZ
J
TPft
13
|/</9f|
<£]""/'
p]A?0
-X/<7
Xl/?
ra
AA*
r/'/j
Yl
8
\
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f-
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A?7
~~\9
A
A34
—
'/f
,
/
/27
/
A34
f
S
«
yv//
A
a,i4\
....
\A33]1
/3\
A |~^
rw
a
/i
p]4££
-f>e*
/,/
e.n
Figure
10-3.
Delay Lines, Logic Diagram (Sheet
1 of 2)
10-12
~\
OL44
BOH <•
«-|
DL-31
—
5
BOW—
^
OLD
10
OLD
/>^ J_
9,i3
3,5
OLD
At
1
10
TPi
2412
A4-
;TPIO
*«,
,
TP
1
JO
IZ
TP
V
,9I fi
'
si
L."
^"!2
! i
r^-*
-M7
1
«ij-'
-L -^
••
—
—
rih,-
H^^tJ
Vf, rftff4-
i | | / | J rj i • ' 1
2L£^J
L.s,c
wr
' !J! • •
JTP4-I
J
r/=/'?^'~iTf>i8r
^
'^-^
•'•'^
a n
8l
-s'^^i
t i
r.»».
i
*
1
cir,»«
-
3
•L. 1 1 i
--
\-j\
\ » ,
f/-, pl'J
l^r^lr
' 'M7
3
1 1 -L' -L* • •
^i/4
ll
. 1
|I0««>'
^/>V£|
in
f.i,
'>
i T* TI 77
* !
L__j
L
CONNECTOR PINS
Pm
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31 •
33
35
37
39
41
43
45
47
49
Signal
WN
SIGRET
MRON
MRO
V3
ACCON
YN
PQR
ACCO
MDON
VI
'
STP
PQRN
PRN
Pin
51
53
55
57
"59
61
63
65
67
69
71
73
75'
77
79
81
83
85
87
89
91
93
95
97
Signal
ZN
PR
NU
A
ION
XN
. NUN
.Z2
Y8
X3
'
A10
.
W7
•"MDO
'
STPN
DL31
-
DL44
BON
V5
NOTES:
1.
See
Glossary
or
Index
for
Signal Definitions
See
Logic Symbols-Appendix
for
Definition
of
Logic
Symbols
Dotted Line
(if
any)
Indicates
Internal
ULD
Connection
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
Prefix
Reference
Designations
as
Follows: A1A5A
Figure
10-3.
:;
Delay
Lines,
;Logic
Diagram
(Sheet
2)
10-13
DL44
Figure
10-4. Multiply-Divide Element, Logic Diagram (Sheet
1 of 12)
10-14
Yi
HQ1Y
•
p^vN
P&V
n •
vow •
tlN
P3N
V4NIOD
4 •
KUNV
•
A
Alt
-~\K
A
Alt,
A
Alt
A
Ali
—
1?
A
A
13
14
IO
n
10
1
7P/3
A/9
•
PIN
JL
:
A
Aid
—
I'
.A
14
TPI7
1
NN
TPlO
TMM
fJM
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
OPIV'
P1VN
,
PCVN
VOYN
VOY •-
MR
2
V]
OP4VN
DL44
G2V
PR10
PQR
MD7V
TTLV
AI3V
DL31
STP
PR
2V
HOY
OP3VN
OP2VN
HOYN
G6V
PCV
ZN
Pin
51
"
53
55
'
57
59
61
63
65
67
69
71
73.
75
77
79
81
83
85
87
89
91
93
95
97
Signal
G7VN
Q8V
DTMN
RUNV
VOYV
PBV •
G4VN
P3N
TMVN
-•'
DTM
TMV
G3VN
P2N
PIN
G7V
G1VN
TM
PAV
G6VN
G4V
DTMVN
DTMV
TMN
G5VN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
HOYV'N
W2
OP2V
T8CV
P2VN
DTMVN
G2V
G7VN
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
V3
G5V
NU
VI •
V4MOD4
'
P3VN
G4VN
HOYV
G3VN
TMVN
76
X7
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A7A
Figure
10-4. Multiply-Divide Element, Logic Diagram (Sheet
2)
10-15
wz
HOff
£JJ
T3CV
Li
26
Vf
8
r
l_
V1
—
[
—
I 8
It
,
hGV
. g-
f>JV\'
2-
AJ
~Mf
A
A
10
~\-
A.
AID
—
js
A
_£/Jj
—
MO
A
All
A)
*>
7
7
10
•h
rp3
O
J
/ f
/)/0
J
/ 5
/«//
rt
NIDI
X7
it
VI
MD4 •
At
r*N
4T
r«i3.
HO
PIVH
/T7
U
TPI5
f4
1
j-
—
19
/7
—
|S
A
AS,
--'--
L^
j
/7
/
f
X
/V>i>^
MOSN
Figure
10-4. Multiply-Divide Element, Logic Diagram (Sheet
3)
10-16
M04
MD4N
See
Glossary
or
Index
for
Signal
Definitions
See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols-
Dotted Line
(if
any)
Indicates
Internal
ULD
Connection
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A7B
CSV
;
THRU
PINS
Pin
.1..
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
HOYVN
W2
OP2V
TBCV
P2VN
DTMVN
G2V
G7VN
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29.
30
Siqnal
V3
G5V
NU
VI
V4MOD4
P3VN
G4VN
HOYV
G3VN
TMVN
26
X7
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
MD5N
MD5
MD6
MD6N
MD7N
X7
MD7
MD4N
MD3
V4MOD4
V3
SIG RET
NU
MD4
MD2
W2
OP2V
MD3N
TRSV
MDO
VI
V]
G5V
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
Z6
MD2N
TBCV
MDON
Kl
KIN
K2N
P2VN
P3VN
'-
K2
HOYVN
SG2N
SG2
HOYV
PROVN
PROV
.
ESDV
ESDVN
SG1N
PR
IN
TFDVN
PR1
SGI
TFDV
Figure
10-4.
Multiply-Divide Element, Logic Diagram (Sheet
4)
10-17
A*
64W.
¥
It?
.4'
OTMVM
SGJ
***
.
feitt—4
«'"—^
x/C/V
— '
^
uL
"<-r~\
TMON
AY
X7
TKVN
fif
—
r}
1
ft
H'i
tei -
MY* -
#
6/W
se/,v
AK2
6IM
£
46
gffH.V-
Atf
S7
ft
set
wv^
4?
Z+
-^EH
,j
10
4I5\
sec*
SC2
\4>\"
10
•>TP4
Figure
10-4. Multiply-Divide Element; Logic Diagram
(Sheet1
5)
10-18
NOTES:
1. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U. Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
Al ASA
f4f0/V
^ 4W £
xv^ —
4-
ruM 2-
H'l
f£f L
e?v
J?
G7V >f
omvw
—
^
«/'f
—
|
HOf^
GIV
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—
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—
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10
A
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//?
—
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A
A 13
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—
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f
1
ID
J_]
J
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
/
413
'
Siqnal
MR2N
MD7N
PR6
G6V '
Y7
MR2
VOYVN
HOYV
AV
G2V
G7VN
MD7V
SG2N
SG2
Ql
PR6N
P1VN
Pin
51
53 _
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
:
97
Signal
X7
,W2
G3V
Z4
TMVN
P3VN
HOYVN
G4V
G1V
G1V
G1VN
AVN
Q1N
G6VN
G4VN
DTMVN
DTMV
SGI
SG1N
r?S '
TF'O
if
fSf
4f
errtw-
SfM-
AY
Ft'PK-
H2
,
=£f
;
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S
—\7
A
A
—\J
/H
am
^
—\s
A?4
fl
f\
fl
1
J
*1
J
S
1
A
Pir
1
2
3
4
5
i
8
9
11
12
13
14
15
24
1
S
THRU
P
S
iqnal
SIG RET '
EMDN
, •
SMDN
FMDN
G2VN
CDN
G6VN
TMVN
CD
G6V
PR6N
G5V
'PI
]
INS
Pin
16
17
1R
19
20
22
23
24
26
27
28
29
30
Siqnal
V3
ZDHN
VOYV
PR6
ZDLN
G1YN
G7V
G7VN
DTMVN
DTMV
VI
Y7
G1V
Figure
10-4.
Multiply-Divide
Element,
Logic
Diagram
(Sheet
6)
10-19
UOYVN
MMV
.:;,=
I
.
-
GIM
"iD:*
(
UOY
VN
Figure
10-
4.
Multiply-Divide Element,
Logic
Diagram
(Sheet
7)
10-
20
TFDN
TFO
5MDN
§1
MO4 2J
Y7
^^~^^
ZDHN
—
£
EMDN
— S
MD5
a-
V4MOD4
T
AilJ
IT
A
A35
~lft
A
10
14
.
3
T fe f
V4MOM
,
H
Y7
SMDN
!^
VID4N
—
LS
V7
EMDN
^
MD5N
^
Y7
DTMVN
S-
HOYV
!2
Y7
HOfVN
£
TMVM
g
h?
A
A54
—
|io
A
A
Si
A/53
—
17
A
A
A3 3
~~13
I
K3 _,
1
6
ALc_
A33l
A?*
TPIT
ESDN
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Signal
TFD
MD4N
MD5
MD5N
TFDN
MD2
BSD
M03
V4MOD4
V3
PR4N
ESDN
SIG RET
MD4
MD2N
MD3N
MD6
G3VN
VI
Pin
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
9G
92
94
96
98
Signal
G5V
MR
IV
MD6N
PR4
SG2N
SG2
Z4
SG1N
SGI
G2VN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Siqnal
SIG RET
EMDN
SMDN
FMDN
HOYVN
G2VN
CDN
GGVN
HOYV
TMVN
CD
G6V
PR6N
G5V
Pin
16
17
18
19
'
20
21
22
23
24
25
26
27
28
29
30
.
Signal
V3
ZDHN
VOYVN
PR6
ZDLN
TMDN
G1VN
G7V
G7VN
G2V
DTMVN
DTMV
VI
Y7
GIV
NOTES:
1
, See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
{if
any) Indicates Internal
ULD J
Connection
4.
"N..U,"
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A1A8B
Figure
10-4.
Multiply-Divide Element, Logic Diagram
(Sheet
8)
10-21
HCYV
AttfM
li
zu?
*v-
\Af9
~\
\A&>
kJ
YS
Jt
6
/i
* 7
\/itsr-
\3P}
•tt,
M-\9
O2
46
yg-
rr-
rff
ff'
rtf
-as
7X^9
C6
Figure
10-4. Multiply-Divide Element, Logic
Diagram
(Sheet
9)
10-22
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows: A1A9A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
HOYVN
26
Y8
XI
P2VN
ZN
VI
PRN
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
TMVN
G4VN
W8
V4MOD4
SIG RET
V3
P3VN
PR
TMV
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
'
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Siqnal
MR]
MR2N
MRO
MRON
AI2V
MR 2
MR1VN
HOYV
V3
SIG RET
AI2VN
TTLV
SG2
Ql
STP
AV
OP3VN
PIVN
VI
OP2V
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
MR1V
G7V
PAV
MR
IN
XN
SG2N
AVN
Q1N
V4MOD4
Q8
OP1V
G5VN
G3V
SGI
G2V
Figure
10-4. Multiply-Divide Element,: Logic Diagram (Sheet
10)
10-23
Y£
PRN
5
HOYVM
2
Y8
PPM
—
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Y4MOD4
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1
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XI
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10
14
13
7
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3
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TP16
3
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Figure
10-4.
Multiply-Divide Element, Logic Diagram
(Sheet
11)
10-24
wa
p
TBCV—nnn
A13VN-
-13 A
P1VN-
Z6
VI
6
r
L
».-p
u
16
ws
M" *
P3VM
2
P2.VKJ
1
—
110
A
A9
—
19
A
A3
~|3
A
A
10
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A
A
10
A
A
1
1
T
<
I
2
TPfc
?
1
I 5
3
1 S
<
TP
TP3
Yfi-
PR1KJ-
VI-
THRU
PINS
Pin
1
2
3
4
. 5
6
7
8
9
10
11
12
13
14
15
Signal
HOYVN
26
Y8
XI
P2VN
ZN
VI
PRN
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
TMVN
G4VN
W8
V4MOD4
SIG RET
V3
P3VN
PR
TMV
NOTES
1
.
2.
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
.
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
Z6
Y8
.
PR6
'PR
10
XI
PR6N
PR4N
PR4
PR
IN
VV8
PR2
PR1
G2V
TMVN
G4VN
ZN
PR2N
PRON
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Siqnal
VOYV
PR
.
TBCV
P1VN
Kl
KIN
K2N
P2VN
P3VN
K2
HOYVN
PRN
PRO
AI3V
PROVN
PROV
ESDV
ESDVN
TMV
PR
2V
TFDVN
PR2VN
AI3VN
TFDV
See
Glossary
or
Index
for
Signal Definitions
See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A1A9B
Figure
10-4. Multiply-Divide Element, Logic Diagram (Sheet
12)
10-25
TP7
A
MOV
—
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13
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A
ASS
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A5.
TP17
TP4
t
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A;/
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Figure
10-5.
Add-Subtract Element, Logic Diagram (Sheet
1 of 4)
10-26
TP*
ZER
ZERW
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1,1
Signal
ZERN
A1V
AI1V
G4V
OP2VN
CSTV
ANDN
AUN
AI4
OP4V
PCV
BN
TBCV
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
ACCO
G6VN
RAC
PAVN
OP1VN
OP2V
AI3V
C
CN
OP3VN
B
G3VN
G5VN
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
SIGRET
V3
PBV
AVN
TRSVN
G6V
TRSV
A2V
AI2V
•
TBCV
TTLV
Q8V
.
OP4V
IOREG
PIOV
G2VN
Wl
G1V
G6VN
X3
VI
ZN
G5VN
G7V
PAV
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
PBVN
OP3V
CSTV
G4V,
A5V
SHFV
A6V
Z3
G7VN
'PCV
OP4VN
G5V
V7
INTV
G1VN
P3VN
AV
HOYV
VOYVN
EXMVN
OP1V
OP3VN
G3VN
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A1A10A
Figure
10-5. Add-Subtract Element, Logic
Diagram
(Sheet
2)
10-27
Y4M0DJ
V4MOD3
TPK
t
[
OL.44
AI3M
AI3
NOTES:
I .
See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows:
Al
A10B
Figure
10-5. Add-Subtract Element, Logic Diagram
(Sheet
3)
10-28
ypia
V4M003
/ICC
IN
•ACC1
TP*
V4MOD3
TBCK
DL3I
HOFC1V
THRU
PINS
Pin
1
2
3
4
5
'6.
7
8
9
10
11
12
13
14
15
Signal
ZERN
A1V
AI1V
G4V
OP2VN
CSTV
ANDN
AUN
AI4
OP4V
PCV
BN
TBCV
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
ACCO
G6VN
RAC
PAVN
OP1VN
OP2V
A13V
C
CN
OP3VN
B
G3VN
G5VN
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
OP2VN
OP1VN
ACCO
ACC1
UTR
DL44
PBV
SHFV
AUN
TRSV
PAVN
AI1V
UTRV
HOPC1V
DL31
ACC1V
WN
A1V
A2V
AI3VN
OP1V
AI3V
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
PIOV
PCVN
OP2V
OP3V
Y7
Wl
VI
X3
AION
23
V4MOD3
AI2VN
AI1N
AI2
AI3N
AI2N
AIO
AI2V
AI3
All
SIG RET
-3VDC(V3)
Figure
10-5.
Add-Subtract. Element, Logic Diagram
(Sheet
4)
10-29
Y6—TT
e*A
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Figure
10-6.
Transfer Register Bits 10-TRS
and
Control, Logic Diagram
(Sheet
1 of 2)
10-30
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A11A
"
VI
8
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7KN
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
G3V
RUNV
RUNVN
G3VN
Y6
OP2V
EXMVN
CLTR
G2VN
TRSN
HOPV
TRS
SHFV
TR13
A6V
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
AI2V
BRB11
A5V
BRB13
MBOV
8RB10
BRA
10
BRA 11
MAOV
BRA
13
TRIO
BRB12
BRA12
TR12
TR9D
X2
TR9DN
TR11
fAf
67 y
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
AV
G7V
PAV
GIV
G1VN
PCVN
SRTR
TBR
Wl
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
V3
G5V
TTT
PBV
G7VN
STO
G2V
VI
X2
V4MOD2
Z8
PCV
CDS
G6VN
Figure
10-6.
Transfer Register Bits 10-TRS
and
Control, Logic Diagram
(Sheet
2)
10-31
PAV
—
4f
f
S
Iff,
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Figure
10-7.
Memory Buffer Control
and
Parity
Counter, Logic Diagram (Sheet
1 of 2)
10-32
T»/3
IB
TRtr
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1
9
f
fa
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sefir
SBKl
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
OP2VN
OP1VN
SRTR
SBRZ
PAR
TR1N
OP3V
G7V
PAY
V3
SIG RET
Z8
YN
G5VN
G1VN
G6V
CBRN
V4MOD2
TR1V
G7VN
AV
STOVN
G6VN
SBRX
WN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
.
84
86-
88
90
92
' 94
96
98
Signal
V]
ZN
TTT
SBRY
STO
CDS
Y6
Wl
G5V
PCVN
OP4V
G2V
AVN
PBV
RDV
G4VN
G3VN
TBR
G1V
PCV
THRU
PINS
Pin
I
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
AV
G7V
PAV
G1V
G1VN
PCVN
SRTR
TBR
Wl
Pin
16
17
18
19
20
21
22
23
,
24
25
26
27
28
29
30
Signal
V3
G5V
TTT
PBV
G7VN
STO
G2V
VI
X2
V4MOD2
Z8
PCV
CDS
G6VN
NOTES-.
1
. Sec
Glossary
or
Index
for
Signal Definitions
2. jec
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Lino
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
althougli
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows:
A1A11
B
Figure
10-7.
Memory
Buffer
Control
and
Parity
Counter, Logic Diagram
(Sheet
2)
10-33
FCD
V4
MOD 5—i
V4
MOD
5
TR13V
V4
MODS
r
u
A
A15
•5-
A16
"_
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3
r
i
A1S
I
Aie
s
5
OP2
OP2N
22
H2;=is
PAV
—
23
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^
C7VN
22
V4
MOD
5-
8
r
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L
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,
*ft
PAV
£
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g
GoV
*
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5
OPEN
S
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VI-
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X
A
X
A
—
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t
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1
X
A
f
A
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t
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A
k
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k
9
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10
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11
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11
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7
n
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12
1
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—
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1
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2
V4-MODS-
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f
V4MOD5
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HOP LS
1
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VOYVN
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EXMN
1
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INTBN
r
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A33
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A
AZ6
A
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T
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1
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EXMN
IN TAN
INTA
TP11
Figure
10-8.
Operation
Code
Register,
Logic
Diagram
(Sheet
1 of 4)
10-34
PAV
GSV
CGVN
FCD
-"El
V4
MODS—I;
e
1
1
1
la
A
A:
t
A.
31
3
i,
32
3
3
1
A31
1
A3Z
5
5
TRltV
13
OP3
OP3N
VOYVN
FCD
THRU
PINS
Pin
1
2
3
•
4
5
6
7
8
9
10
11
12
13
14
15
Signal
OP3N
OP1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
FCD
PAV
G6V
G5V
G6VN
A9V
A8V
G5VN
OP1N
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A12A
V4MOD5
TR1OV—22
OP4
OP4N
PAV
f
CBVN
1
CSV
»
16
-
PAV
A
CIV
S
C2VN
5
P6VN
a
INTA—
a
VI-
B
|
c
A»
—
17
A
A13
A
AC
~|9
A
AC
-tr
A
A7
J
1
iz)
1
1
^_,
..b
i i-
AC
315
I A7
INTN
INT
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
HOP
OP2N
OP1N
HOYVN
SIG RET
V3
VI
TR12V
V4MOD5
OP1
G1VN
G4VN
TR13V
G7V
WN
OP3N
W6
X2
OPS
OP4N
INTCV
G7VN
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
OP4
Y6
TR11V
OP2
TR10V
Z2
G1V
VOYVN
G2VN
CSTV
HOYV
EXMN
EXM
PBVN
INT
Figure
10-8.
Operation
Code
Register, Logic Diagram (Sheet
2)
10-35
VA
MOD
s
\'4
MOD
5
*..~
OPW
-
Figure
10-8.
Operation
Code
Register,
Iagic
Diagram
(Sheet
3)
10-
36
SSF-
PAV-
GGV-
V4
MODS
FCD
A33
TP12
o
VI-
8
r
1
...
|e
—
19
A
A3
7
-hr
A
A34
...1
1
—
l
3
3
I
AZ7
I
A34
S
5
TTLN
TTL
OP1-J3
OPZV
—
-
OP3N
-
V4
MOD5-
CP4V
A
A34
A
A35
—
13
A
A35
!i
5
1
Hi
-STON
CONNECTOR PINS
Pin
2
4
6
S
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
STON
OP2V
A8V
OP4V
SIG RET
V3
VI
PAV
TTL.
V4MOD5
G5VN
TR8V
G5V
G6V
TR9V
OP3V
TR4V
TR3V
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
Y6
A9V
TR5V
TR1V
SHF
TR6V
TR2V
TR7V
G6VN
PIO
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U.
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A1A12B
.
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
OP3N
OP1
Pin
16
17
18
IV
20
21
22
23
24
25
26
27
28
29
30
Siqnal
FCD
PAV
G6V
G5V
G6VN
A9V
A8V
G5VN
OP1N
Figure
10-8.
Operation
Code
Register, Logic Diagram
(Sheet
4)
10-37
W7
12'
^4V/N
G3VN
G2VN
G6VN
•
&TVN
•
AVN
V4MOD1
s^1
A24
AZ4
14
31
W7
InP
T?
TPI7
AZ
A
A8
V4MODI
W7
V4MOP1
-
GIN | I Aft
Y4MOD1
~F£
7*
TP3
-ez
A
A33
0_
W7
GIVN
AVN
_5t
A'?
A23
W7
AVN
—2
A
Alfel"
V4MOHI
-]9
AZ3I
TPO
6 A.
[I
Alfe
V4MOD1
W7
AV
A
.42.
A'i
-&3N
&4N
AVN
J^-
G4V
WM001-
TPII
'••4
MODI
132.
fAl
AIZ
9
A
.=5
3
m
AIZ
T
5,
A
19
&5N
C75
Figure
10-9.
Timing Gate Generator, Logic Diagram
(Sheet
1 of 2)
10-38
r?
AVM-
&6V-
V4MDP1-
V4M0DI-
^i
&a
W7
AVN
-f2
TPie
TPI3
—
19
A
A14
~~1
a
1
A
14.
•y
1
-G7M
&7
W7
TPZ
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Siqnol
G2
G2N
G1VN
G3N
G3
G2V
G4N
G3VN
G6VN
G4
G4VN
G5VN
A
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
AN
G5N
GIN
G7V
Gl
G5
G4V
G6
AV
G5V
G6N
G7N-
G7
G6V
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Siqnol
G1V
G7VN
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqna
1
G2VN
G3V
AVN
VI
W7
V4MOD1
SIG RET
Y5
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
U
5.
Prefix
Reference
Designations
as
Follows: A1A13A
Figure 10-9. Timing Gate Generator,
Logic
Diagram
(Sheet
2)
10-39
W7
GZVHI
6TVM
/XVN
V4MOB1
V4MOD1
-
-*
2
e
n
/v,
AIO
A
ftlT
~~I9
A
Leal
s
n
d
3 T
L^aJ
vs—
PBV
d
13 A hzl
-PA.N
TP.3
TBCM
TOO
Figure
10-10.
Phase Generator,
Logic
Diagram
(Sheet
1 of 2)
10-40
TP5
PBN
PB
PCN
PC
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
W7
PAV
G3V
TBC
PAVN
PB
PCV
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
VI
PEN
.PCVN
PA
G2VN
G7VN
V3
SIG RET
AVN
PBV
PAN
G1V
PBVN
Y5
PCN
V4MOD1
PC
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
G1V
G7VN
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
G2VN
G3V
AVN
VI
W7
V4MOD1
SIG RET
Y5
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix
Reference
Designations
as
Follows:
A1A13B
Figure
10-10.
Phase Generator, Logic Diagram (Sheet
2)
10-41
Zfi-
CDSV
j|
DSSN
W
G6V
»
C7VN
^
DUPDN
a
VI-
DMC
—
I7
A
A2
A
A3
A
~~]s
A
A
a
IZ
3
3
I
A6
sjl TP1
flR^]Ar-^-DMi
ISSN—$
PBV—Tj?j
A
ef«{J=SA>4
VZON
DM2 &
CM3N fi
<*=:=>
— 2
V4
MOD
6 -
IMa ^
1H/3N
—
REI—
§
A
A3O
~~]|0
A
A31
A
A31
a.
J
3
I
A31
DM
I
DM0-
_a
13
VI-
8
AZ
A
A1
—
]9
A
Al
5
[3
I
A1
TPE
-DUPDN
MTTN
V4
MOD
6^—13
DM2
DM3
RED
V4
MOD 6
IMS
REI
MSSN
Figure
10-11.
Memory Module
Registers,
Logic
Diagram
(Sheet
1 of 2)
10-42
EB-
DSS
j|
G1V
— rj
S7V
—
K
DUPDN
—
13
VI-
DM1 &.
—\7
A
Ate
A
AI5
—
\a
A
A15
M.
12
,1
i TP8
1
I
-U
1
M-DMO
DM2
DMZN
TP5
IM1
DUPIN
V4
MOD 6
TP13
IMO
CDSV-
C1VN-
G2V-
VI
DSS-
G2VN-
G3V-
3
VI-
e
H
za-
El
A
A17
—
I9
A
A3
=rr
A
AtO
—
17
A
A3
10
1
,1
I
A3
I
A1O
Tf
i
5
5_
»3
J)
1
TF
DM3
OM3N
REI
V4MODS
|io
IMO
REI
IMBN
DMBN
-IMAN
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
ISS
G1VN
G7VN
HOPV
MZON
PCV
ISSN
V4MOD6
G7V
G6V
DSSN
CDSV
GIV
DSS
G2V
MTTN
G2VN
VI
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
SIG RET
MFFN
OMAN
DMBN
28
IMBN
G5V
MSSN
G6VN
G3V
G4VN
V3
IMAN
G4V
PBV
G5VN
V4
MODC_—|io
DMO
RED
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic Symbols
3.
Dotten Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A14A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
DUPDN
G6V
G1VN
G7VN
GIV
PAV
G2V
G3V
RED
IM2
G5V
G4V
PBV
IM3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
DM0
DM1
PCV
DM2
DM3
G7V
G2VN
REI
IMO
IM1
G6VN
G4VN
DUPIN
G5VN
Figure
10-11.
Memory Module
Registers,
Logic Diagram (Sheet
2)
10-43
W5—17
warns
DM
I
PCV
G4V
G6VN
DMO
-
S
PCV
WS
053-
PCV-
G3VN-
G5V-
W5
PCV
G5VN
G~7V
PAV
G5VN
G7V
DSIM
AID j
A17|
VI-
8
1
1
U
<z-
~1«
A
A9
~\s-
AA2
—
|to
--
"
L3
3
1
Iz
\
-4-,
—
i—
V1 13
8 A
PA17
-HPI
[315
A)7
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
Al
A14B
TPG
O
•
HP1N
A3
Y7-n,o
I3J
A IT
HPI
-^A35n
Y7-^
DC
-^
1O
A
AZ6
XM
—
^
e
. la
/
2,
3
i
AZ6
5-
A
ASS
TP17
o
.1
I
I-Z&
I ,
5
5
HOPC1N
HOPCI
G1V
G6V
•RUN
•REX
C5VN
TPB
Figure
10-12.
HOP
Constant
Serializer
and
Memory
Read
Latches,
Logic
Diagram
(Sheet
1 of 2)
10-44
DUPDN
RE.DN
RE.D
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Siqnal
DUPDN
G6V
G1VN
G7VN
G1V
PAV
G2V
G3V
RED
IM2
G5V
G4V
PBV
1M3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
DM0
DM1
PCV
DM2
DM3
G7V
G2VN
REI
IMO
IM1
G6VN
G4VN
DUPIN
G5VN
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
IS
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
HOPC1
Y7
PAV
AV
V4MOD6
XN.
AVN
DS2M
OP1V
DS4
X2
DS2
IS4
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
W5
DSIM
IS2
DS1
VI
DS3
G3VN
SYLC1V
151
IS3
S1GRET
V3
Figure
10-12.
HOP
Constant
Serializer
and
Memory Read
Latches,
Logic
Diagram
(Sheet
2)
10-45
13,
MOP
*
STOVN
V4
MOD7-
V4
MOO7-
s
INHBS
VI-
TTLV
—
VI
-
1KITV
GGV-^
VI
-
PAV §•
RUNVK/^^
VI-
OP1
VN cj
OPZVN
j|
OP3V
E
VI-
OPZVN
§
OP4V
2
VI
-
OP3V-H4
OP4V
~
VI-
RUNVN
—
—
27-
G7VN
1
PAV
i
M^LTV
^
V4
MOD7-
6
c
u.
Y1
-
C7VN
U
13
C6V
*
V4
MOD7-
CSTN
S.
^
A
1
X
A
—
|
;
A
-
y
A
1
/
A
—
|
A
A^
-
t
A
1
/
A
1
t
Ai
X
A
—
1
X
A
X
A
~1
A
=
t
f.
~]
A
>
A
_
>
A
^
5
9
Xs
S
k
13
10
Z3
7
V
&
3
k
6
3
3
t,
7
7
^
31
10
!4
^
24
3
V
31
k
30
°>
t,
3q
1^
^
?s
10
1,
?r
s
!V
2?
]
" ~
J7_
13,
1^
ia
w<
1Z
J
J
...
i
M
*
J
"
C7V
2'
1
T '
'
e PAV
-A15— 1NHBS
MOP^
G3VN
!
I 5 C4V
"^3—
RD
*-
K/OP
Z"
RD
PAV
Z1
PAVN
GZV
RD^
G5VN
Y1
MOP
PB V
___
INHBS
1
TPG
PBVN
MOP
'
3]
I
§1
nD "
LlA24-J-MOP
G5VN
MOP
Y1
G6V
xr,
315
,
AV>
RUN
[
3|
I
|5(
„ . . , L
lA23|
*
RUNN
-££*-«T
I?
2.
r-
14
A
7
7-
a
r-
3
Si
Z
r-
£
7^
3.
3
4
k
.1
9
*,
i
8
-
J,
a.
A
A3Z
~|7
A
A25
A
~~|1Z
A
AZ5
—
17
A
A53
A
A71!
~~h
A
A3.1
A
AZG
A
A14
—(7
A
AZ7
A
A2O
—
)!Z
A
AZ7
A
A34
~13
A
A27
~|9
A
A2G
~~ts-
A
6
5
]
d
£
-i
]
r
^
I
j
f
1
j
4,
3
1
iJ
5
f
11
f
]
J
.__
TP
Q
[2
i s ,
-" A1o =*
TP9
SINKN
SINK
Figure
10-13.
Memory
Timing, Logic Diagram (Sheet
1 of 4)
10-46
G7VN
PBV
»
GGV—
K
13
RD
-
G7VN
2
Z7-
PCV
1
CSV
i
G7VN
2
V4
MOD
7 -
8.
f
1
8
A
A2
A
A9
—13
A
A.Z
~19
A
AIO
-b-
A
All
1
IS
!j
315,
AIO
315
1
All
G7VN
SYLC1N
EXMVN
SVI.C1N
V4
MOD 7
UTRV
SL.DN
SYLIKl
SYLON
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Siqnol
CSTN
G1VN
HOPV
OP4V
PCV
C5T
UTRV
STOVN
'
RUNN
HAL TV
RUN • •
OP2VN
:
TTLV
INTV
SYLCI
G6V
EXMVN
X4 •
OP1VN
OP3V
TR4V
G7VN
.
RUNVN
Pin
51
.53
55-
57
59
61
63
65
•,67
69
71
-73
75
77
79
'81
83
85
87
89
91
93
95
97
Signal
Yl
SYLON
PAVN
SYLIN
Z7. -
PBVN
RD
G2VN
INHBS
PBV
PCVN
TR'l
3V
G3V
XN
EXMV
GSVN
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A1A15A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Sianal
PAV
PBV
RD
G7V •' .
G2V
G2VN
VI
SIGRET
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
PCV
G3VN
G1V
SINK
G4V
PAVN
XN
V3
G6VN
V4MOD7
Figure
10-13.
Memory Timing, Logic Diagram (Sheet
2)
10-4-7
W3
SINK
SYNCN
SYMC
SYNC-
13
VI—TS
vt
coc-
8
N
X4-
13
A
AS
"=t5~
A
~|10
A
A4
.-U
J
AB
r
A4
5
§_
i
TF
i
ae
CMC
CNCN
h/FFVN
MSSVN
EA.C
V4
MOD7
TP4
/-
8
r
i
i
la
~~13
A
A17
-Is-
A
A18
...
3
3
1
At
7
I
A1B
S
5
"—
H
ZS~110
eec
EBP^^
^f^aiAel
to
MAO
MBO
NOTES:
}
See
Glossary
or
Index
for
Signol Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic Symbols
3.
Dotted
Line
(if
any) Indicates Infernal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A15B
Figure
10-13.
Memory
Timing, Logic Diagram (Sheet
3)
10-48
"—110
CMC
— S
VI-
e
f
v,L
l~
u
Y3-
CNCN
—
YNCN
A
A3
~l»
A
A3
"3"
A
~l«>
A
A2
A
A3
7
1 r-,
L^
I
5
'
HA3
M^F"*-
PAZ
I
£ TP7
J
9
—-r-coc
COCN
TER
TE.R
TfS
RE.CN
PAV
G3VN
G4V
RDM
RDMN
PAV Z
Y3
G3VN
!g
G4V
1
RD
Z
PBV
Y3
G3VK4
12.
GEV
iV
RD
la-
Y3
PAVW
2.
PCV
10
&2VM
—
14
Giv —
54
RD
li
XM
J
P
I
V1
I
La
421
13
A
A 14
A
AZO
—
17
A
AM
—
13
A
A7
A
A7
~~l»
A
A^l
~!LL
19
A
A£0
"l
J
a
«!
i
5
14
1
14
TP1
J
I 5
All
J
I 5
A20
TIMEM
TIME
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
PAV
PBV
RD
G7V
G2V
G2VN
VI
SIG RET
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
PCV
G3VN
GIV
SINK
G4V
PAVN
XN
V3
G6VN
V4MOD7
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Siqnal
G3VN
DMA
CNC
V3
VI
PAV
RDM
RDMN
IMA
MSS
MBO
G7V
MFF
MAO
W3
X4
EAP
TIME
RECN
COC
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
SYNC
Y3
EAC
MTT
MTTVN
Z5
GIV
MSSVN
TER
G2V
EBC
1MB
G4V
SYNCN
EBP
TLC
G6VN
MFFVN
ZN
SIG RET
MZOVN
DMB
V4MOD7
MZO
Figure
10-13.
Memory Timing, Logic
Diagram
(Sheet
4)
10-49
W3
W3
•EDACIM
•EDAC
coc
—
»
FSAN
—
*
IMA
— &
W3-
CN4C
1
PSA 8
IMA
"
13
VI
J)
]3£
SYNC
-
IMA
-
VI-
HOPV
&
RUNVN
-
A
A3Z
~~I3
A
A32
A
AZ5
H9
A
AZ5
-ty
A
A16
—
)7
A
A)
3
~13
rA
A13
14
!2
IZ
—
0,
3.
TP
i
3
I 5
AZS
3J
I
[5,
|A18|
O
TPS
EIACN
E.IAC
AG
AG
W3-
E.ADM
-
DMA-
W3
EAIM
!
IMA !
V4
MOO
7
V4
MOD7
W3
E.ADMN
S
DMA •
W3
IMA-
EAIMN-
V4MOD
7 17
DMAVN—
~^—
IMAVN
8
L
A
A13
-fsr
A
A14
...
...
^
_a
i
A13
I
A14
§
5
BRAO
BRAON
EDOX
EDOY
MZO
FSAN
FSA
NOTES:
-M05YN
V4MOD7-
DMAVN
^
IMAVN
V4
MOD7-
SYNCN
—
V4MOD7-
MTTVN
&
—
I3
A
A34
—
]io
A
A33
r^i
A3
3
9
7
3
4
5
[3
I
LA33
See
Glossary
or
Index
for
Signal
Definitions
See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
Dotted Line
.if
any)
Indicates Internal
ULD
Connection
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
Prefix
Reference Designations
as
Follows:
AT
A16A
-MZSYNC
Figure
10-14.
Memory
Error
Detector,
Logic
Diagram
(Sheet
1 of 8)
10-50
E7
EAR
S
DMA
ii
TIME
a
VI-
ED
AC
13
VI - —
e
VI"
&.
EAPN-J2
H7-
EDACN
1
TIME
*
DMA
— a
A
A3
~~P9
A
A17
A
A1O
—
13
A
A1O
\$
A
A3
A
AZ
~l3
A
A3
14
T^
1Z
3
7
!f
1
d
TP9
o
A1O
r*z -—
E^OM
4
1 TP7
EA1MN
EAIM
IMAVN
V1-
-
—
T1O
A
AZZ
EDACN
-
VI-
EIACN
S
DMAVN
^
A
AZ3
—
)io
A
A15
A
A15
±
1Z
J
Is X
A15
DMAVN
IMAVN
-EAC
V4MOD7
17
DMAVN)
—
IMAVN
DMA
IMA
E.APN
TP5
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
YN
MZO
ED2X
ED2Y
MTT
V3
VI
EDOX
EDOY
ED6X
ED6Y
MSS
ED4X
ED4Y
MFF
MZOVN
W3
EAC
HOPV
RUNVN-
EAP
TIME
RECN
COC
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
SYNC
Y3
DMA
MTTVN
27
CNC
DMAVN
MOSYN
M2SYNC
IMAVN
IMA
SYNCN
BRAO
BRAON
MSSVN
MFFVN
M4SYNC
SIG RET
M6SYNC
EAM
V4MOD7
EAM
M4SYNC
V.SSVN
M6SYNC
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
Figure 10-14.
Memory
Error
Detector, Logic Diagram
(Sheet
2)
10-51
coc
FSBN
DMB
CNC
FS3
DMB
COC
FSBM
•EDBCN
EDBC
E.IBCN
ELIBC
W3 —
EBDM-
0MB -
AC
13
y/3-
EBIM
1MB
V4
MOOT
V4MOD7
e
L|
AL.
A13j
!}
A
A14
.'
La
3
i
AI3
I
A)4
5
5,
W3
E.BDMNI
BRBO
BRBON
V4MOO
7-
DMBVN
*
113
IMBVN
-
V4
MOD 7
~~11O_
SYNCN
V4
MOD 7
MHOVN
Ml
SYNC
FSBN
FSB
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
rha:
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A16B
V4MOD7
OMBVN
IMBVN-
V4
MOD 7
SYNCN-
V4
M
OD
7
MTTVN
A33
-M3SYNC
Figure
10-14.
Memory
Error
Detector, Logic Diagram
(Sheet
3)
10-52
Z7
E.BDMN
ELBDM
EBIMN
EBIM
v—lio
IMBVN
E.DBCN
E.IBCN
DMBVN
-eac
MFFVN
MSSYNC
V4
MOO
7 -
DMBVN
2
IMBVN
V4
MOD
7-
5YNCN
a
V4MOD7
-
MSSVN
—I3
/^7
—lio
A
A35
—
is
A
A35
9
A3S
-M1SYNC
DMBVN
—
IMBVN
EBP-
-ELBM
THRU
PINS
'
Pin
' 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
.
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
V4MOD7
EBM
M7SYNC
.
SIG RET
M5SYNC
MFFVN
MSSVN
BRBON
BRBO
SYNCN
1MB
IMBVN
M3SYNC
M1SYNC
DMBVN
CMC
27.
MTTVN
DMB
Y3
SYNC
COC
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
RECN
TIME
EBP
RUNVN
HOPV
EBC
W3
MZOVN
MFF
ED5Y
ED5X
.MSS
ED7Y
ED7X
EDIY
ED1X
VI
V3
MTT
ED3Y
ED3X
MZO
YN
Figure 10-14.
Memory
Error
Detector, Logic Diagram
(Sheet
4)
10-53
ff#4?
g#^2
U-
Yl
. /J
VI
t>
VI
—
j-
&
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vi
—
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VI
—
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ffMSA/— -
vi
—
SW7-&
Bftdc
VI—
r
e
VI
—
a
6fiA9
—
VI
6#A9N
—*-
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vi
—
g
6&!/c
VI
—
1
BMffN—*-
VI
—
ff
SfafJ
/'
—
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—
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—
4
429
A
4??
~~[tP
A
AH
—\>o
A
filS
A
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—
iV
A
A?9
—
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A
A!J
A
A23
—\?
A
AjO
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A
416
—
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A.W
—\(ft
A
A2S
A
A26
—\7
A
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A
19
A
4/9
—
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A
/.yy
—
\f6
A
A27
X
A27
—
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1 -*
\A34
14
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H
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/
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12
f
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^
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1
to
14
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90
a
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j
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45
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VI
—
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S
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—\9
A
.
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A
V
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A
/J
AM
—\9
A
4/ff~f
A
12
AM
—
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A
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1
4f V
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Af
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SPAOS
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AH
J
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SfA09
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4/3
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46
Figure
10-14.
Memory
Error
Detector, Logic Diagram
(Sheet
5)
10-54
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U. Indicates that
ULD is Not
Installed
although Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A17A
rtJ
ft »-
VI-
a
TPI4
A
412
—\io
A
AI2
7
J
I
All
SK4f4\
S
?/
e
A
AI3
—\9
A
14
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33.
35
37
39
41
43
45
47
49
Siqnal
BRA4N
BRA2N
BRA3
BRA4
BRA1
BRA2
BRAS
BRAIN
BRA3N
BRA6
BRA8N
-
BRA6N
BRA5N
BRA7N
BRAS
BRA7
SIG RET
V3
VI
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
BRA12
BRA
10
PAO1
BRA12N
BRA)
IN
BRA
ION
BRA9N
BRA9
BRA 11
BRA
14
BRA14N
BRA13N
BRA
13
EAP
Figure
10-14.
Memory
Error
Detector, Logic Diagram (Sheet
6)
10-55
VI
—-
e#£f
-e-
fffiSS-K-
anoyt/
&
Iff
—
e/tsiN
-&•
vt
—
gagju
tj
.
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g
££8-fJV
VI
£fiS4
—
^
V!
ffftfff
£...
VI
~~r
£#£S#
—
c-
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—
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g
JK33
VI—
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VI
li
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£/?£?</
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—
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effort
VI
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wen
ft
—
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_-£j
W
—
jrj
"
<f
eRolw
v>~l
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A
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A
AH
—
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AA22
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A
AtS
A
A15
A
AH)
~\ff
A
AM
A
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—
1^
A
440
~\ff
A
A
Af6
—
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n
—
\I6
A
4X
A
426
—\7
A
AM
~\/t
A
A fQ
/V/<7
A
AIS
—
I/
A
A33
~\K
A
A27
A
A?7
—
\?
A
AM
H
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to
If
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—
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8
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A
AS
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A
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A
49
—\ro
A
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—\»
A
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—
15
A
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7
7
7
rps
? ,,,
I VI-
3
I
Sf8f/\
S
A3
VI
S
1
1
t3
0 i«
I
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SfSf!\
9
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If/ ••
S
J3
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3 /
sflea\
s
AS
vt
—
S
tJ
—[7
A
t*
AW
—
1*
A
At/
^
A
a
~\IZ
A
&
AX>
\S
A
A
18
2—
|
A
V
J/6
*
""!•*
A
f
AIP
—\9
A
Af
7
A
£_
AS
* I 5 )A
Af)
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J
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J
1
SfSff/0
At l<-
1 ft
I
I)
Figure
10-14.
Memory
Error
Detector,
Logic
Diagram
(Sheet
1)
10-56
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A1A17B
rt/7
o
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
EBP
BRB13
BRB13N
BRB14N
BRB14
BRB11
BRB9
BRB9N
BRB10N
BRBUN
BRB12N
PB01
BRB10
BRB12
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V.I
V3
SIG RET
BRB7
BRB5
BRB7N
BRB5N
BRB6N
BRB8N
BRB6
BRB3N
BRB1N
BRB8
BRB2
BRB1
BRB4
BRB3
BRB2N
BRB4N
Figure
10-14.
Memory
Error
Detector, Logic Diagram (Sheet
8)
10-57
RUNVU
THiN
Tflt
Figure
10-15.
Transfer Register Bits 1-9,
Logic
Diagram
(Sheet
1 of 4)
10-58
7V?J/V
CONNECTOR PINS
Pin
1
3
5
1
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
SIG RET
TR3
VI
BRB2
BRA3
BRA2
BRB3
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
BRB1
BRA1
AI1V
G6VN
RUNV
G7V
TR1N
MD2V
G1V
SRTR
PAV
DIN
RUNVN
PBVN
PCV
G1VN
G7VN
V4MOD2
TR1
TR2
W6
STO
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Slqnol
SIG RET
TR3D
TR7
TR5
TR4
TR9
V4
TR6
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Sianal
TR3DN
-3VDC(V3)
Y4
X8
V)
CLTR
TBR
MBOV
SRTR
n
MAOV
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows:
Al
A18A
Figure
10-15.
Transfer
Register
Bits
1-9,
Logic
Diagram
(Sheet
2)
10-59
r*
—
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10-15.
Transfer
Register
Bits
1-9,
Logic
Diagram
(Sheet
3)
10-60
rff
7K6OH
Tf>
9
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A1A18B
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
TR6
TR4
SRTR
TR5
X8
BRA4
BRAS
MAOV
BRB5
6RA6
G5V
CLTR
BRB6
MBOV
BRB4
INTV
G3VN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
'82
84
86
88
90
92
94
96
98
Signal
Y4
BRA7
.
BRAS
BRA9
BRB9
AVN
EXMVN
X5
TBR
BRB7
BRB8
TR8
TR7
TR9DN
TR9
TR9D
W6
Z2
Tfl
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
TR3D
TR7
TR5
TR4
TR9
V4MOD2
TR6
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Slqnol
TR3DN
V3
V4.
X8
VI -
CLTR
TBR
MBOV
SRTR
Z2
MAOV
Figure
10-15.
Transfer Register Bits
1-9,
Logic Diagram
(Sheet
4)
10-61
TRSV
Z(—C5.
131
12
All 13,
p2_ , .
M-Un^
VI—19
TP9
\ '4
V006-
fi
TA
EXMV
*
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TPC
f-E
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TR7V
TA
ZJ—>7
V4
MODS
AZAN
EXMV
TP1
^l
AH
AZN
TRZV
-
13
V4
MODS
TA
«—110
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12
1
TP14
B
s
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A8AN
TP15
a
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TA
G6VN
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TA
GSVN
154
TA
G1V
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p
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TP4
§,
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TA
v4Miope—up
AIM
4J
A3N
V4
MOD
6 |1Q
Al\y
i| .. '
Figure
10-16.
Address Register
and
Memory Address Decoder,
Logic
Diagram
(Sheet
1 of 4)
10-62
21
TRCV
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&
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La
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13
TA
Y4
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A
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A
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A
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A
A7
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A
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A
A8
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315
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7
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315,
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A3S
*=
iJ
V
J
r-,
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1
J
A^—
AX7N
A3N
CONNECTOR PINS
"
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
AX6N
AX4N
A3V
SIGRET
V3
AX2N
AX7N
V4MOD6
AX3N
TR8V
AX1N
A2V
A1V
AX5N
EXMDN
AXON
TR9V
EXMV
Al
A2
VI
Pin
51
53
55
57
59'
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
Y4
OS
4
A8
IS4
Zl
TR1V
TR6V
A3
A9
TR2V
TR7V
G6VN
A7
THRU
P.INS
Pin
1
2
3
4
5
6
7
8
.
9
10
11
12
13
14
15
Signal
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
S4
TA
S4N
G1V
A7N
EXMV
A8N
NOTES:
1 . See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A1A19A
Figure 10-16. Address Register
and
Memory
Address Decoder,
Logic
Diagram
(Sheet
2)
10-63
TR5V
TR5V
A4AN
V4
MODS
EXMV
TR4V
TA
12
-
^
All
'1
TPC
Tpa
V4
MOD
6
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VI-
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1
—
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—
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10
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5.
5,
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13
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A26
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A
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1
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s
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a
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AY3N
V4
MCDG
TAM
A4 N
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•TA
A6V
AYGN
V4 MOD
A7V —
ASM
V~no
_B| A
|A34
I
A34
^-AXCON
-AX1ON
S4
Figure
10-16.
Address Register
and
Memory
Address Decoder,
Logic
Diagram (Sheet
3)
10-64
Z2—110
TR3V
TA-
V<1
MOD 6
TA
V4
MOD6-
A4V-
ACAN
TP1
AGN
A5N
^Aaol
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A
A30
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2J—1~1.
A5N—SA
-AY2N
P-AY5N
V4
MOD
6—310
A4V-
ASV
ASV
AY7N
AXIOM
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
AX7ON
A7V
ASV
AX10N
AX5ON
.
VI
51G RET
PAV
AXOON
V4MOD6
AX4ON
AX6ON
TA
AX2ON
G7V
WN
G6V
EXMVN
X5
AVN
AX
SON
TR4V
TR3V
G5VN
:
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
,
84
86
88
.90
92
'
94
96
98
Signal'
Y5
A6
TR5V
Z2
G1V
AY7N
A5
A4V
AY5N
AY4N
AY3N
AY1N
ASV
A
YON
Y3
AY2N
A6V
A4
AY6N
THRU
PINS
P,'n
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S
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-
.-
Pin
-16
17" •
18
19
20
21
22
23
24
25
26
27
28
29
30
-
Signal
"''.'
'
•'.'"•;
-"54
- "'
TA
S4N
G1V
A7N
EXMV
ASN .
NOTES:
1
S4
AXBON
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A1A19B
Figure
10-16.
Address Register
and
Memory
Address Decoder,
Logic
Diagram (Sheet
4)
10-65
Z1-
PBV
ISS-
GGV-
G~7VN-
1
L
J
A17
I
A
Aie
A
Aia
J
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A1Z
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DSS
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23
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ISSN
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r
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21
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A
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I
Ate
i
A3
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1
5
5,
DSZ
DSZN
DSIN
DSS S
TPZ
O
TP3
Figure
10-17.
Memory
Sector Registers,
Logic
Diagram
(Sheet
1 of 2)
10-66
z:^3
PBV
1 A ,
HOPV—*
A1Z
1
I
c-,v_!3
* pL
VI 1 1
6
A 3 I 5 .
T_,
1
AS AS IS3
VI
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A13
"T~
A13
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,—
J
11
A n o
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TP'°
f4
Z<-|3
1
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™^L\" *«**—
IS<;
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TBRV
if
MAOV
»
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u
Y5
BRB8
a
TBRV
— §
MBOV
»
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u
VI
L"
TA
—
*
EXMVN
—
—
A
AZO
A
A33
—
IID
A
AZ7
A.
A34
—
,s
A
-N-
A
A27
—
17
A
A3S
Sfl
intr
1*1
iBTJl
i 1
a
CIVN^5
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v
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8
A 3 l & •
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1
1
kAAZS-f
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T*f
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I
TBRV
1
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1
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BRB7
S
TBRV
4
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MBOV
¥
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a
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1
A27
1
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EXMVN
a
A
A28
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A
A35
315
J
A28
D52MN
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
PCV
G4V
G3VN
DSSN
V3
SIG RET
VI
G2VN
G3V
DSS
G5VN
CDSV
G4VN
G5V
G7V
WN
G6V
ISSN
X5
PBV
TRSV
ISS
G7VN
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
S
ignal
Y5
DS4
HOPV
••
IS4
Zl
G1V
MAOV
G1VN
G2V
TBRV
MBOV
BRB8
BRA8
G6VN
BRB7
BRA7
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
DS2M
EXMV
DS1MN
TA
DS1M
IS
IN
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
DS2MN
DS1
EXMVN
DS1N
DS3
DS2N
IS3
IS2
IS1
IS2N
DS2
DS3N
IS3N
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. Sec
Logic Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A1A20A
Figure
10-17.
Memory Sector
Registers,.
Logic Diagram (Sheet
2)
10-67
V4
MOD
6 -
DSIN-^
CS2N
—
DS3N
—
V4
MOD
S -
A3PAONI
1
DS1
*
DSZN
*
D53N
K
V4
MOD £ -
PAD
1
IS1
1
I
SEN
<a
IS3N
H
—
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A
A2Z
A
A30
—
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A
A
23
A
A3O
L
r.
n
J
3
I
A30
TPE
AVION
V4
MODS-
A3PADN
^
DS1N
DSZN-
DSEMN
V4
MODS-
IS1
1
IS2N
§
is
a
—
-
PAD
-
V4
MOD
€ -
EX.MD
a
DS1M
-
DSEMN
A
A5
"15
A
A4
A
A5
—
|io
A
A14
A
AI4
U
!i
P
r1
5
-3
I
A14
TPI3
!L^>L
AYSON
EXMD-
PADN
PAD
PAD-
A3-
A3PADN
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A1A20B
Figure
10-18. Hi-Y
Memory
Address
Decoder,
Logic
Diagram
(Sheet
1 of 2)
10-68
V4
MODS
DS1N
iU
DSZ ft
STM
«
053N
A9PADN-
V4
MODS
A3PADN
TP3
AY3ON
V4
MODS
13
A3
PADN
8(~T~
DS1N
• ^ *•
DST
DS:
TA'
E.XMVN
EXMV-
TA-
E.X.MDN
V4
MOD
£ -
A9PA.DN
4
DS1
^f
DS2
1|
DS3
«
—
17
A
AZO
1
DS1M
DS2M
TPI7
AY7ON
THRU
PINS
Pin
]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
DS2M
EXMV
DS1MN
TA
DSIM
IS1N
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
DS2MN
DS1
EXMVN
DS1N
DS3
DS2N
IS3
IS2
ISI
IS2N
DS2
DS3N
ISSN
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
AY5ON
AY7ON
AY4ON
AY6ON
DS2M
PAV
DSIM
V4MOD6
IS3
DS3
TA
DS2
G7V
EXMDN
EXMVN
EXMD
EXMV
IS2
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V]
Y5
A9
Zl
G1V
AY20N
AVION
AY3ON
AYOON
IS!
G6VN
V3
SIG RET
DS1
Figure
10-18.
Hi-Y Memory
Address
Decoder, Logic
Diagram
(Sheet
2)
10-69
NOTC.I.Z
A3V5MOD1
1
.
I
MSVBZ
i
g.
/o
«
/4
a
W
ii
H
s
I"
-#
8
—io
Ii
14
a
10
If
14.
C1
A1
Cl
Cl
A.I
Cl
Cl
AS
J
\
5
r
i
i
r
•
3
/
^
j
/
i
f
t
)
.1
7
I
,7
j-
^
«
e
Cl
Cl
Cl
*I4
Cl
Ail
a
%n
/2
14
a
16
if
It
7
7
-SJG
RET
p^
r
7
7
7
7
CZ
fa
Ci
A^^
C2
A3
Cl
AZS
C3
A
10
C3
Alt
8 \ 7
TP5
Cl
*IS
a
\ n ci
TP«
a
f ;
7P7
« \ >
TP8
8 f 7
TP9
a
I r
A
13
Ct
A
16
Ct
430
C3
An
CJ
431
&_^
6
6
f
0
a
Figure
10-19.
Decoupling
Capacitors
(Channel
4),
Logic. Diagram
(Sheet
1 of 4)
10-70
^lf.
^py
7
7
7
7
7
7
f«f
All
C4
Ail
Alt
Alt,
CJ
Ali
CJ
Ail
NOTES:
1
.
See
Glossar)
8
[ 7
TP11
ff
1
'
TPtZ
« \ 7
TPI3
«
I >
TPf4
»
1 '
TP15
' I '
C4
A
IS
C4
til
C4
C4
A33
C3
\AIO\
CJ
AJ4
8
6
a
a
V
^
or
Index
for
Signal
Defini
2. See
Logic Symbols Appendix
for
Definition
of
Logic Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
Is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A4A3A
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
MSVB1
MSVB1
SIG RET
S1G RET
A2V5MOD5
V3
V3
V3
V3
A3V5MOD1
V5
V5
V5 .
V5
A3V5MOD3
VI
VI
VI
VI
A3V5MOD4
SIG RET
SIG RET
SIG RET
SIG RET
A3V5MOD5
Pin
51
53
55
57
:59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
V3
V3
V3
V3
SIG RET
VI
VI
VI
VI
SIG RET .
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
MSVB2
MSVB2
Figure
10-19.
Decoupling
Capacitors
(Channel
4),
Logic Diagram (Sheet
2)
10-71
Nore.
i
A
1V
5
Ml
001
/f
1
VSMOC
•
A1VSMOD5
A
I
V5
HI
OH
3
A
2 Y!,
HIOD4-
—
ft
10
11
&
e
16
li
It
g
fi
_Ji
a
to
11
'+
g.
to
/f
•4
g:
10
11
/*
a
—To
li
14
Al
d
At
( j
Ct
ff
C
7
;
j
s
7
3
s
7
1
3
1
J
1
)
f
7
1
f
f
•f
}
S
7
1
T
s
7
ViO
o
TPI
S/6
Figure
10-19.
Decoupling
Capacitors
(Channel
4),
Logic Diagram (Sheet
3)
10-72
Tfll
TPI3
TPIS
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
V3
V3
V3
V3
A2V5MOD4
VI
VI
VI
VI
SIGRET
SIGRET
SIGRET
SIGRET
SIGRET
VI
VI
VI
VI
A2V5MOD3
SIG RET
SIGRET
SIG RET
SIG RET
A2V5MOD1
V3
Pin
52
54
56
58 ,
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V3
V3
V3 - ,
A1V5MOD5
VI
VI
VI
VI
SIG RET
SIG RET
SIGRET
SIG RET
SlGRET
. .
A1V5MOD4
V5
V5
.
V5
V5
A1V5MOD3
V20
V20
V20
V20
A1V5MOD1
SIG
f?£T
NOTES:
1. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U.
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A4A3B
Figure
10-19.
Decoupling
Capacitors
(Channel
4),
Logic
Diagram
(Sheet
4)
10-73
AfYSMODS
A3VSMODS
JIPIO
(3)
(7)
NU
>1SF~
a
r\eJ-
.
13
t.3
(.Jl-
/ 8
NU
j/r&taPS-
'SMOIO
-
A1W4
-
(57;-
-*4
NU
u
-OTP/f
&—
AISTOVN
I
NU
Af
l/rlU2^-'
lj^f-H5^-w
AfSI-tF
-
(87)-
NU
4
NU
41SHFV
1.8 CtM
(77)
(«l)
/.jfNU
Figure
10-20. Operation
Code
Voters, Logic Diagram
(Sheet
1 of 4)
10-74
trysts
AirsMOOs
A&S4tO03
AIM
4
NU
/y
j
NU
XJ/J1
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V4MOD5
A2V5MOD5
A1PIO
A1V5MOD5
V3
VI
SIGRET
A1HOPV
A3V5MOD5
A2V5MOD5
A1V5MOD5
A1X1
A1HOP
A3V5MOD5
A2V5MOD5
A1V5MOD5
A1W4
Pin
51
53
55
57
59
61
63
65
67
"69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1STON
V3
VI
SIG RET
AIPIOV
V3
VI
A1SHFV
A1W4
SIG RET
A1SHF
A1STOVN
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
"
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Infernal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A4A5A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIGRET
VI
V3
SIG RET
VI
V3 .
SIGRET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
Figure 10-20. Operation
Code
Voters, Logic Diagram (Sheet
2)
10-75
JtVSMODS
AJVSMOD^.
A3\&*OO5
xl/OPIN
(48)
Figure
10-20. Operation Code Voters, Logic Diagram
(Sheet
3)
10-76
s
t)
ft
.,,nn»u
f? ^
(L,t)
- '
CM)
- ;. /
>
/O
#
V
4
i
6
/
NU
/
r*
N
6
n
TP
1
«l
rA
AH
7
t
>J
S
Kf
£3
|r
'\>
NU
4
I
?s
/J 7
NU
^C«
»l
NU
J
^7
// e
NU
^--(,9)
A1VV4
—
|
.
t; I" .
^_
t°
f
2
NU
7
/>»
XV
T-(Ml?
8)
H,
81'
r^
'f
f
/y tf
*7
A
tO
^-^/OP3V
»l
NU
^J S_
NU
-<30
kk
NU
^<
/
/j
r
NU
^
(_48)
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
NU2
NU3
A10P3
A1W4
A10P3VN
A10P2
A1W4
A10P2V
A10P3V
A10P1V
A10P1
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A10P2VN
A10P3N
A10P2N
A1W4
A1W4
A1V5MOD5
A2V5MOD5
A3V5MOD5
A10P1VN
AIOPJN
THRU
PINS
Pin
1
2.
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIGRET
VI
V3
SIGRET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
2!
22
23
24
25
26
27
28
29
30
Slqnal
A3V5MOD5
NU)
NU2
NU3
A2V5MOD5
A1V5MOD5
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows: A4A5B
Figure
10-20.
Operation
Code
Voters,
Logic
Diagram
(Sheet
4)
10-77
AtrSMODI
AfYSMOOl
A3¥S#ODI
AIY2
4166
(3)
(7)
NU
A*
NU
\
NU
i
a
13
LjfNU
I.
i4JS
a
TP9
\
1.8
a?)
(70
.JI,
S3)
(«)
tf—
4/66N
.
t»7 ) •
CJ1>
^
NU
g^/^
(^
_
it, 51, S3
-0/-PS
^
//r/U.
fJ_
A
If
J
NU
g.
NU
1.8 CIM
NU
Figure
10-21.
Timing Gate
and
Operation
Code
Voters,
Logic
Diagram
(Sheet
1 of 4)
10-78
4W54tat>l
Ail/SMOfil
ASt&MOfl
A1Y2
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A4A6A
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V5MOD1
A2V5MOD1
A1G6
A1V5MOD1
V3
VI
SIG RET
A1G7VN
A3V5MOD1
A2V5MOD1
A1V5MOD1
A1Y2
A1G7N
A3V5MOD
1
A2V5MOD1
A1V5MOD1
A1Y2
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1G3N
V3
VI
SIG RET
A1G6V
V3
VI
A1G6VN
A1Y2
SIG RET
A1G6N
A1G3VN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Siqnal
SIG RET
V]
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
Figure
10-21.
Timing
Gate
and
Operation
Code
Voters,
Logic
Diagram
(Sheet
2)
10-79
t'VSMODl
A3IKW.*
A1X3-
/f/EXM
-
m£
fjNU
SM7
1_
NU
—
^/EXMV
NU
^fNuUe—4lNu
JL
(?t)
C7Z)
(70)
rj
7
/</EVMVI
4^
ifNU
TNU
/
M>
,j 7
NU
4/TTI
^
(efc)
~ NU
J.4/S
7 W
•
>?/TTLV
zisJ
i
NU
(34)
NU
/j
NU
.£_
(JO>
-f C
-f
0
r^iu^pL^j
|_
DDI
_ _ 1
' / ^.5
N
-JF
Figure 10-21. Timing Gate
and
Operation
Code
Voters, Logic Diagram
(Sheet
3)
10-80
Ft
CONNECTOR PINS
Pin
2
4
6
8
10
12
l"4
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
NU2
NU3
AUNT
A1W2
A10P4V
A1TTL
A1W8
A1TTLV
A1INTV
A10P4VN
A10P41
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1EXMVN
A10P4
A1EXMN
A1W2
A1X3
A1V5MOD5
A2V5MOD5
A3V5MOD5
A1EXMV
A1EXM
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIGRET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A3V5MOD5
NU1
NU2
NU3
A2V5MOD5
A1V5MOD5
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A4A6B
Figure
10-21.
Timing
Gate
and
Operation
Code
Voters,
Logic
Diagram
(Sheet
4)
10-81
A!
V5MOOI
AfYSMOW
A3t5*OPi
A2V2
or
NU
NU
7P9
3
"CI
6,13.
4IGIV
NU
(,g
rj
j
NU
»i*?r
n,)
AMMOD3
~
MZZ —
J/ACC/
~
(55)
~
,if
.
— ( 2.7 )
-oTPIl
Z-", ^—/!ACCIV
/
NU
Lg
_
L
|
tf—
A/GIN rHMI,
C8T>
^INU
(81*)
hi
^
(51,53)
Atf
NU
f.fJ
NU
(80
>.S
NU
A7
Figure
10-22. Timing
and
Add-Subtract Voters, Logic Diagram
(Sheet
1 of 4)
10-82
JW5*fOt>/
A!i>5At00l
ASf5#ff0/
A2Y2
Jf
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V5MOD1
A2V5MOD1
A1G1
A1V5MOD1
V3
VI
SIG RET
A1G2VN
A3V5MOD1
A2V5MOD1
A1V5MOD1
A2Y2
A1G2N
A3V5MOD3
A2V5MOD3
A1V5MOD3
A2Y2
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1ACC1
V3
VI
SIG RET
A1G1V
V3
VI
AJG1VN
A1Z2
SIG RET
A1G1N
A1ACC1V
NOTES:
1. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates rhat
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A4A7A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
Figure
10-22.
Timing
and
Add-Subtract
Voters,
Logic
Diagram
(Sheet
2)
10-83
<"l/3V00;
;
2V5MOD?.
A3YZ,VOO*
Figure
10-22. Timing
and
Add-Subtract Voters, Logic Diagram
(Sheet
3)
10-84
ft-
CONNECTOR PINS
Pin
'i
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
NU2
NU3
A1AI1
A2Y2
A1AI3VN
A1AI3
A2W2
A1AI3V
A1AMV
AIAI2VN
A1AI2N
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1AI2V
A1AI3N
A1AI2
A2W8
A2W2
A1V5MOD3
A2V5MOD3
A3V5MOD3
A1UTRV
A1UTR
THRU
PINS
Pin
I
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
V)
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A3V5MOD3
NU1
NU2
NU3
A2V5MOD3
A1V5MOD3
NOTES:
J
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic Symbols
3.
Dotted
Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A4A7B
Figure
10-22.
Timing
and
Add-Subtract
Voters,
Logic
Diagram
(Sheet
4)
10-85
A3VSMOP1
NU
A2Y5MOD1
AWSMOD1
AcYS
(SB)
.
(SI)
J
NU
T*at2
13
fJL.4/PAV
tf.W.
r.s
<yn
LL
NU
(27,
SI, S3)
)7i3//
7 NU JV
4/PB
.-.
(87)
^=
Figure
10-23.
Timing Voters, Logic Diagram (Sheet
1 of 4)
10-86
4ws#a>t
A2YSM00I
A3r5#0£t
All
2
.NU
/y
j
NU
AIJ
f./J
li'
7.14
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V5MOD1
A2V5MOD1
A1PA
A1V5MOD1
V3
VI
SIG RET
A1PCV
A3V5MOD1
A2V5MOD1
A1V5MOD1
A1Z2
At PC
A3V5MOD1
A2V5MOD1
A1V5MOD1
A2Z2
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1G5
V3
VI
SIG RET
A1PAV
V3
VI
A1PBV
A2Y2
SIG RET
A1PB
A1G5V
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
{if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A4A8A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
Figure
10-23.
Timing
Voters,
Logic
Diagram
(Sheet
2)
10-87
A3V5MQD\
tl
(54}
T"
1C
if
?
/
-7
^
i
^
A2X3
—
—
ffi
?
A.
£
,
^-
* 1
NUJsJ
7
8\l
™£^
*-*gV-
4/G4V
...
7
g\l
NU
tf > NU |#
,R85
/*.?/
X.W
f
5(7
NU
_£
jfjNU
L/_
(8fc)
n
NU J"
7 S\1
"a-* *\"f
^-*™>™
I
us It
NU
ry «y NU / M?,
^/5
X^
-1
*!/
NU
| /y -7 NU /<
^/ffj
4tJ
(
r/
^ 70) • • • •.
;
1C
2
^.
* 1
NU
ii-(
74,^8)
1
7\s\r
^
T-%£\2-
<<
/£4^
7
8\r
NU
V £
NU
/ ( ,„
AV
^y^ c ;
;
j|/
NU
,/ ? NU A-
^/
«4
/<?
(•
A2XI
-
u«
,
(7t,'
J
*.
—
8)-
10
f
T
^£
f
_![
^1
NU
^ij
£*_l^
o mi
\
'W
™y fj / w /4
^rnn\(fci
i
,
ikr . ,
NU
/y ^
NU
//
(3,,
4// ^« V
7
SI'
NU
ry
<y
NU J ^0)
A1VI-]
~l
3$ [ 10 1
NU ho 0 NU 1
All
ME 7 31 A4 |
I .. _J
1
(48)
-
(C
in
—
JE
•>e
Figure
10-23. Timing Voters, Logic Diagram
(Sheet
3)
10-88
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIGRET
VI
V3
SIGRET
VI
V3
SIG RET
V]
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A3V5MOD1
NU1
NU2
NU3
A2V5MOD1
A1V5MOD1
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
NU2
NU3
A1TBC
A2W8
A1PAVN
A1PCN
A2X1
A1PCVN
A1TBCV
A1PBVN
A1PBN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1G4VN
A] PAN
A1G4N
A2X3
A2Y2
A1V5MOD1
A2V5MODI
A3V5MOD1
A1G4V
A1G4
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
os
Follows: A4A8B
Figure
10-23.
Timing
Voters,
Logic
Diagram
(Sheet
4)
10-89
ttVSMODI
AfVSMCDl
A3VSMODI
•
A2W6
•
L31
17)
r=^
'*
\-i4J4
•o
rP9
(ilL+J/AV
.NU
£tf^
(M)
^—' [
;.<?iNU
tf
1,8
I NU
V/(7(S
_
(.57)
---tS
NU
13
Ufi
-QTPfl
f<—/trQ6v
L NU ^_
(,35
J/AN
'
zijjv
NU
A/0
i
-§
13
-o TP8
f.a
NU
NU
£.'J
.(77)
£#JNU
^x««
/.J|
NU
Figure
10-24.
Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
1 of 4)
10-90
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V5MOD1
A2V5MOD1
A1A
A1V5MOD1
V3
VI
SIG RET
A1G7V
A3V5MODI
A2V5MOD1
A1V5MOD1
A2Y2
A1G7
A3V5MOD4
A2V5MOD4
AIV5MOD4
A2W6
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1Q8
V3
VI
SIG RET
A1AV
V3
VI
A1AVN
A2W6
SIG RET
A1AN
A1Q8V
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U. Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A4A9A
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
V)
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
Figure
10-24. Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
2)
10-91
4/I/5V0ZM
><A5VCD4
A3WWO4
>I;MR
Figure
10-24. Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
3)
10-92
M-
_r
NU
/£
(38)
IA4A9BI
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signol
NU1
NU2
NU3
AIPRON
A2W5
A1PR2V
A1PRO
A2W5
A1PROV
A1PROVN
A1PR2VN
A1PR2N
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1MR1VN
A1PR2
A1MR1N
A2Z4
A3Z2
A1V5MOD4
A2V5MOD4
A3V5MOD4
A1MR1V
'•'-
A1MR1
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
V)
V3
SIG RET
Vi
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A3V5VOD4
NU1
NU2
NU3
A2V5MOD4
A1V5MOD4
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Doffed Line
(if
any) Indicates Inferno)
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A4A9B
Figure
10-24. Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
4)
10-93
TP16TP10
osc
BFR
SHP
BFR
SHP
BFR
SHP
[
TP6
I
TP18
1
IA1
IA1
IA1
TP9
TP13
•
BOT3
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows:
A4A11A
(left
page),
A4A11B
(right
page)
Figure
10-25.
Oscillator
and
Buffer,
Logic
Diagram
(Sheet
1 of 2)
10-94
BOT1
BOT2
BOS
BO1N
BO1
BO2N
B02
BO3N
BOS
THRU
-
PINS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIGNAL
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SIGNAL
BOT2
BOT1
BOT3
CONNECTOR PINS
PIN
1
3
5
.7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SIGNAL
SIGRET
SIGRET
SIGRET
SIGRET
SIGRET
V20
V20
V5
V5
!
VI
VI
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
V3
V3
V20
V20
V5
V5
SIGRET
SIG RET
SIG RET
PIN
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
SIGNAL
SIG RET
SIG RET
VI •
VI
V3
V3
V20
V20
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
V5
V5
VI
VI
V3
V3
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
CONNECTOR PINS
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
SIGNAL
V5
1
VI
VI
BO2
SIG RET
1
V3
V3
BO2N
SIG RET
1
V3
V3
SIG RET
SIG RET
THERM1
VI
VI
BO1
THERM2
PIN
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
SIGNAL
V5
'
V5
BO1N
SIG RET
1
VI
1
SIGRET
SIG RET
V3,
V3
BO3N
SIG RET
1
BO3
VI
VI
V5
1
Figure
10-25. Oscillator
and
Buffer,
Logic Diagram
(Sheet
2)
10-95
AJAVH
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A2RPN
VI
A2RP
VI
i
A1RPN
VI
A1RP
VI
BOS
V3
BO1
V3
1
SIG
RET.
1
BO2
SIG RET
SIG RET
V5
V5
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
.
93
95
97
Signal
.
.
vs.
V5
SIG RET
V3
1
VI
i
-AJ*N
THRU
PINS
Pin
,
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
A3P
A1SN
A2SN
A2P
A3SN
ASS
A3Q
AIP
A2Q
A1Q
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
BOS
A3PN
A1S
A2S
A3R
A3RN
BO2
A2PN
BO1
A3QN
A1PN
A2QN
A1QN
Figure
10-26. Clock
Generator
Timing Logic, Logic Diagram (Sheet
1 of 4)
10-96
r^
i
f-
Ifl
A
Alt
T
A
ASS
Li
3
A3*
1
A35
f.
5
AZS
AJPN
NOTES:
1
See
Glossory
or
Index
for
Signal
Definitions
2. See
Logic.
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A4A12A
6.
Asterisk
indicates
load resistor
not
connected.
Figure
10-26.
Clock
Generator
Timing
Logic,
Logic
Diagram
(Sheet
2)
10-97
VI
A1SVN
V!
BOI
£
VI
r
BOIA
VI
/IIP—
2
VI
n
A2SVN
—
VI
801
i
VI
—\r
A
AIS
—\tc
„ 1
A
Aft
MS
—
19
A
AB
**-*
r-AIPf
v,
•
t<f
?"K.*'/
1
—
I
Alt ff/f.5
*4AI7
,
| ' B03 8
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s
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A
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A
A33
—
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7
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A2t\
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—
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315
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A
to
Ait
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1
r
1
A
IPPN
,„
BOJA
A
~\K
A
AtS
—
|7
A
AZ9
—
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A
t??
A
AZ9
A
Ail
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y —
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&
1 —
1
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VI
—
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—
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12
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r./in
J
"~A31
AJS
1
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A3S
A3l
VS
AISN
AJ'SN
V-i
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42.SH
A3SH
A
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A27
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ao
11
13
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A3PPN
10
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id
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(
MSH
>
T
'. A
J2
It
M
7
"Tyr
Wf
(S
. f
7^8
II
*T
MV
-A 19
rMsv
V
TMV
i.
A20
13
CKD •*-
0 7
n 7
13
7
11
t
a a
13
S
A2I
TPI3
"tt
'^"S*
TPIt
"3
^"s*
TPI,
YA,4
'^
*JS*
,.„,
"*™
At2J
tfu
L~^
AISVN
rrtr
p^-LxjJw
Figure
10-26. Clock Generator Timing Logic, Logic Diagram (Sheet
3)
10-98
aoi
eoj
*IQ
•BOS*
AIQP
A3K
A31H
A3KPN
NOTES:
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
VI
BO3P
V3
V3
A3PP
V3
V)
J_
SIGRET
1
A3PPN
SIGRET
A3RP
SIG RET
V5
V5
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V5
A3RPN
A2QP
BO1P
BO2P
SIGRET
SIG RET
A2PPN
A3QPN
A2QP
A1PP
A2PP
VI
1
A1PPN
A2QPN
A1QP
SIG RET
V3
J_
A1QPN
VI
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Doited
Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows: A4A12B
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
A3P
A1SN
A2SN
A2P
A3SN
A3S
A3Q
A1P
A2Q
A1Q
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
BO3
A3PN
A1S
A2S
A3R
'
A3RN
BO2
A2PN
BO1
A3QN
A1PN
A2QN
A1QN
Figure 10-26. Clock Generator Timing Logic, Logic Diagram (Sheet
4)
10-99
t>
V5MX1
•
A3V2-
C1?)
NU
xJ?
--W(NU
-2jj/
La
TP9
\I3_
^ HCI
g,IS
1.8
CIM
6.13
1,8 NU;
1,8
/>rysi<00'f-
AJt'SMODt-
A3W2
-
JIP3N
-
NU
/J
Us
'If=r
NU
y/^
k_^
(97)
-IB
Figure 10-27.
Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
1 of 4)
10-100
4W5M00I
/WSM00I
Awssawi
A2>ra
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIGRET
VI
V3
SIGRET
VI
V3
SIGRET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Sianal
CONNECTOR PINS
Pin
1
3
5.
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V5MOD1
A2V5MOD1
A1G2
•A1V5MOD1
V3
VI
SIG RET
A1G5VN
A3V5MOD1
A2V5MOD1
A1V5MOD1
A3Y2
A1G5N
A3V5MOD4
A2V5MOD4
A1V5MOD4
A3Y2
Pin
51
53
55
57
59.
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1P3N
V3
VI
SIG RET
A1G2V
V3
VI
A1G3V
A3W2
.
SIG RET
A1G3
A1P3VN
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten Line
(If
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A4A13A
Figure
10-27. Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
2)
10-101
*s*wou
A3WWO
^/MOVM—
I4A\
—
t
,
4
43*
* • d
r-
^;
-£- >
/,_
i±
2fc
*
i
«x? —
rs«)
—
r-iyr
C5ZJ
—
^
t^x
a \
NU
sj
7
8\t
w 13 ,y <7 /
y/f/oYvM
»/9
4<f
' '
_-^-
7*|/
NU
^/ / NU M
,jj»
>^/
^/J
7gl/
MU
/y ^ NU / ,„, ,
_£_
\1U
5
f &
C\T
prn
X.
f
J_
.
7
8\l
II? 13 7 // /^r ^
42/
^5
X
9
-A.
•
j
-i.'
1
7l«ir
NUlii
^NU jj_
f42)
#/5|^ >*/V
'
j
7g|/
^U
//
jJNU
^
f44.
.
^/<f
] v//
»
**'
-
( W) ^
r
1C
f
/
,
/
^
s
Nl)
4;
/
3_
o
r/>^
8\
/*y
XfV7
7
r
15
/
//
^<f
^ ^
/VC>VV»J
g\
NU
,
f
»\
NU-
f
SJ
43XJ
—
i *
,,.^.
// I*'
(9
—
10
J.
I
i
.a.
NU
4t
r
r*
f
6
'r
Afi
7
NU
4JJ
7
NU-
x
—
158)
(7t
or/
)
»//
fS 7
fll
NU
41
/
7
rj
"u
7
.*
Nil
4s
r
i
8)
-
0
NU
-*/^
/j <y
^^
f34)
gp-00)
3
sV'l
10
i NU lo
-All
5H
<J
NU
Z41t
i
i
i
i
IB
-,£
(48)
Figure
10-27. Timing
and
Multiply-Divide Voters, Logic Diagram (Sheet
3)
10-102
',
Of 1
*;
y,p,N '/—It
(64)
.—
r'f
T
m
\
t
,f
/
NU
kJ
I
i;|f|
rvr
tff
f
1
t
f/
A3
^,«.
78\>
.NU
a
7
NU
NU
(
J
7 ) - ,i , . '
(10)
1C
f
}
3
J
^
2
NU
47
r
//
,f
<,
e
NU
'H,
x
fiB)
1
7|8f
TMV
r
V
3
r/
I
'W
NU
4ft
f3
ff
NU
./ , / 71 )
1
?\t\
NU
NU
•&•
(38)
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
NU2
NU3
A1P2N
A3W2
A1PIVN
AWOY
A3XJ
A1VOYV
A1P2VN
A1HOYV
A1HOY
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1VOYVN
A1P1N
AWOYN
A3X3
A3W8
A1V5MOD4
A2V5MOD4
A3V5MOD4
A1HOYVN
A1HOYN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18 .
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A3V5MOD4
NU1
NU2
NU3
A2V5MOD4
A1V5MOD4
NOTES:
1
, See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Doffed
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A4A13B
Figure
10-27.
Timing
and
Multiply-Divide
Voters,
Logic
Diagram
(Sheet
4)
10-103
A3V5HOD1
/«3YZM9)-
4ITFD
C3 J
(1)
"^a
NU
a
.W£Z~
-o
TP9
6,13
4ITFDV
I.S
a
AlV^HOD
4
(49-
•" rfi4JI_
; (83
—
4/ESDN-
NU
a
l£Z=r
W.--.NU
L^ZUw
6,13^.
69
I.S
NU
-*;*
6,13
',8
AfTFDN-
(8f)
I
-
=
&
NU
1^"
-o
7X=S
6.
a.
r.s
(77 J
NU
/*«
Lhi
^7=^
siul-y
j*
6>3.
(SO
NU
47
Figure
10-28.
Multiply-Divide
Voters,
Logic Diagram
(Sheet
1 of 4)
10-104
J1ESD
^
—
4
•*
»
1
I
2
f
15
NU
-05
fP
/•/w
422
7fc
NU
A£4
?!?;
.NU
^7
^ -
tf
i
— -
//
c'
//
?
;
/y
(.53)
_o
rrHQ
J
HCf
(,'J,
JTWJ
4S
' '
7,/£
f/tf
41
/
NU'
f.V tiv
41?
I i 1
\
>,S NU
J NU rf'./i
/pel
4V
l J
7,/<f
NU
46
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
1.9
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A3V5MOD4
A2V5MOD4
A1TFD
A1V5MOD4
V3 .. .
VI
SIGRET
A1ESDV
A3V5MOD4
A2V5MOD4
A1V5MOD4
A3W8
A1ESD
A3V5MOD4
A2V5MOD4
A1V5MOD4
A3Y2
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
•
Signal
A1ESDN
V3
VI
SIG RET
A1TFDV
V3
VI
'AITFDVN
A3W6
SIG RET
A1TFDN
A1ESDVN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Slqnal
SIG RET
VI
V3 -
SIG RET
VI
V3
SIG RET
VI -.
V3
Pin
16
17
18,
19
20
21
22
23
24
25
26
'
27
'
28
29
30
Siqnal
^
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
{If
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as Fol
lows: A4A14A
Figure
10-28.
Multiply^-Divide
Voters,
Logic
Diagram
(Sheet
2)
10-105
*JVywQD*r
~~
—
'
\it)
f
b*
—
,
51
r-2
LSI)—
-r—
*s—
^r
/,
,
NU
7
J
«r
T**'
7
r
13
s
a
AS
sf
i)NU
2(££/_
*
7^
/O
rfr
N
A>
*L.
7_
NU
AM
%-
(88)
!h—
*^.««
,
NU
£
r
ir>
T|-tf
X
e\
rr
?3
,
NU'
X?,
7
f
fa
-OTf/
7
a
c
f!
NU
4ft
.
—
,
-f-
(+z>
^
x/
C7?-)
f
10
%
2
V
3
rf 1
NU
7
/*
Xj
^~
f 4
8)
*r
rr
iff
7
f
//
74
J
/MD?V
g\f
NUl^
J
k
N
^
U
\
li
LJ
?<
1
S_
7
»
r
«r/
NU
^<
w
{•?
f
NU
413
•*-
(«)
"j~
to
-ir
_£
"[
J
NU
<*tf
t
/^
X/
\
^
f
5
»
1
IS
NU
NU
/ / g,^
>4
—OTPII
7
&\
NU'
7
i
7
(9IJ
NU
-«^
r
_£_
.
"-nT-i
(
GDI
)
S
-^
10
*y
NU
JI3
NU
^/V
.__
NU
?Jfl">
^- (34
,
»e
T
1
1
1
1
J
r
5
f
Figure 10-28. Multiply-Divide Voters, Logic Diagram
(Sheet
3)
10-106
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
.
NU2
NU3
A1DTMN
A3Y2
A1TMV
A1DTM
A3Y2
A1DTMV
A1DTMVN
A1TMVN
A1TMN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1MD2V
A1TM
A1MD2
A3Y2
A3W6
A1V5MOD4
A2V5MOD4
A3V5MOD4
A1MD7V
A1MD7
|A4A14B|
NOTES:
THRU
PINS
Pin
]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
V)
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A3V5MOD4
NU1
NU2
NU3
A2V5MOD4
A1V5MOD4
I .
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A4A14B
Figure
10-28.
Multiply-Divide Voters, Logic Diagram (Sheet
4)
10-107
More
i.z
NU1
NU2
A
A"
MS
—
Jo
'.T
a
10
'+
8.
~~>S"
/*
<5
to
J2
If-
e.
/o
12
ft
SVgf
VB?
/u
»2
c»
/ij
c.\
A4
Cl
A5
/
f-
;
J
7
/
5
7
'
i
5-
7
f
r
'-
f-
/
—
J
J
t
s
s
7
|
f«CK
|
PANEL
|CONN£CTION
i
m
8
Cl
A6
ft
M
Ct
A
14
Cl
All
6
IO
M
"?
li
14
7
•
SJG RET
sicfecr-
7
7
7
7
7
7
C
J
/33
<TJ
/«**
r.?
-«s
CJ
/«?y
f
j
/«/o
CJ
x«
a
| 7
TP5
«
1 '
TP6
« 1 7
TP7
a 1 7
TP8
8
I 7
TP9
a
i 7
C5
»/5
C3
A19
C3
AI6
C3
A
10
C3
AIT
C3
*31
a
a
a
e
a
&
V1
VI
Figure 10-29.
Decoupling
Capacitors
(Channel
5),
Logic Diagram (Sheet
1 of 4)
10-108
SIG
RFT-
7
_?
7
7
7
7
All
C*
«£
fw"
Alt
C4-
Alt
C4
AI3
C4-
AZ7
TP1O
S } 7
7
9
7 r
7PI3
7
TP1*
7
a
] 7
TPIS
0
5 [ 7
C4
4/0
C4
All
•^^
••^^
C4
/«/«
04
>U.J
04
>t^0
r^
A34
a
g
6
»J
a
a
VJ
V3
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
MSVB1
MSVB1
SIGRET
SIGRET
NU1
V3
V3
V3
V3
NU2
VI
VI
VI
VI
A3V5MOD2
vi
VI
VI
VI
A3V5MOD6
SIG RET
SIG RET
SIG'RET
SIG
RET
'
A3V5MOD7
Pin
51
53
55
57
59
61
'
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
SIGRET
SIGRET
SIGRET
SIG RET
SIGRET
SIG RET
V3
V3
V3
V3
SIGRET
V3
V3
V3
:
V3
SIGRET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
SIG RET
MSVB2
MSVB2
NOTES:
I .
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
If
5.
Prefix
Reference
Designations
as
Follows: A5A3A
Figure
10-29.
Decoupling
Capacitors
(Channel
5),
Logic Diagram (Sheet
2)
10-109
NOTE.
I
AlVSMODt
AIV5
HOD
I
A1V5MOD1
Ai
VSMOD
7
AlVSMODt
A/1//
B
—ns
u
r4
e
~r<>
>t
14
'f>
>f.
—M.
e
1C
rz
i&
S
1"
li.
14
3
e
"
'15
l£
f>
ci
Cl
AS
fl
A
/
1
)
f
7
,/
J '"
f
1
)
f
7
1
i
S
7
/
t
1
7
/
J
S
7
/
j
j
?
or/"
f
NUZ
/Vl/J
,
J
jr
7
S
1
1
?
f
7
t
s
7
1
i
J
7
J
S
Ail
C
1
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10
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-
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—
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a 7
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. ' J,
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i
14
J
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14
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11
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Afc
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to
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it
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Figure
10-29.
Decoupling
Capacitors
(Channel
5),
Logic Diagram (Sheet
3)
10-110
VI •
—
3
5
—
^
—
7
j
7
1
J
J"
!
5
7
3
S
7
I
—
r
s
7
1
J
S
7
Cl
A/I
Cl
All
C.1
All
n
416
Til
*
] '
73-*
J
If
J
It
i
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1
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'a
'
L
T.
W—
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— 3
li S
0- 7
<9
/
ro
j
il
f
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. 7
c;
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^ i
AI3
fl
AU
ATW*
VTPtS
. ,a 1 /, ,
Cl
A
13
Ail
73-""
J
/; 5
/* 7
a /
10
3
li S
14 7
Cl
AID
Cl
A34
A
TV/6
o
JPn
Cl
AM
Cl
10
3
11
S
]&
7
3 1
'*-r—
l
1
Cl
A/I
Cl
A3S
If
1*
v
a
10
li
/4
e
'O
f£
/4
e
77T~
It
1+
a
10
if
/•f
a
ID
if
n
a
if
K
/*
CONNECTOR PINS
Pin
2
A
6
8
10
12
14
16
16
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Sianal
V3
1
NU1
VI
SIGRET
1
J_
VI
1
A2V5MOD2
SIG RET
i
A2V5MOD6
V3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V3
i
A2V5MOD7
V)
1
SIGRET
1
JL
A1V5MOD7
NU3
1
A1V5MOD2
NU2
i
A1V5MOD6
NOTES.
1. Sec
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U. indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
P-'cfix
Reference Designations
as
Follows: A5A3B
Figure
10-29.
Decoupling
Capacitors
(Channel
5),
Logic
Diagram
(Sheet
4)
10-111
A1Y3
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows: A5A5A
Figure
10-30.
Memory Timing Voters, Logic
Diagram
(Sheet
1 of 8)
10-112
Al VS
MOD7
AZV5MCD7
A3V5M3D7
LSI)
3;1
4
kill
.*•• K.1I
I
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Sianal
CONNECTOR PINS
Pin
]
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signol
A1Y3
A1Y3
A1Y3
A1Y3
SIG RET
SIG RET
A1M3SYNC
A2M3SVNC
A3M3SYNC
A1M1SYNC
A2M1SYNC
A3M1SYNC
A1M5SYNC
A2M5SYNC
A3M5SYNC
A1M7SYNC
A2M7SYNC
A3M7SYNC
A1EBMV
A2EBMV
A3EBMV
EP16A
VI
VI
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
8!
83
85
87
89
91
93
95
97
Signal
EP15A
A1M7SYNCV
A1M5SYNCV
A1EBM
A2EBM
A3EBM
A1M3SYNCV
A1M1SYNCV
A3V5MOD7
A2V5MOD7
A1V5MOD7
A1BRBO
A2BR80
A3BRBO
A1BRBON
A2BRBON
A38RBON
EP15
V3
V3
A1X4
A1Y3
A1BRBOV
A1BRBOVN
Figure
10-30.
Memory
Timing
Voters,
Logic
Diagram
(Sheet
2)
10-113
A3VSMflD7
AZVSMOD7
AIVSM007
•
AllNWES
Jl
n
*
1
i
N
A
T«
T,
A
I
T
A
U
>lf
\
ll
AV
31
*V
'•f
«
I1
7
U
~7
3
TP1
VI
A30
£,
—
MIWHBSV
NUA —
—
A2INHBSV
.
i
6
2
4
IB
i
'NU
A!
J| T
«*v
I
A
7
*
!i^VjJi_Nu2
X
P
L
f
N
"1^1"
J—MIM
A9
(to)
(Sfcl
1
:i
9,
.
I
6
^
-is
NU
Alt
Is t
LJ
oTPg
i
r.
7
|8 t
NU
A)0
\t
'
I
NU
AIT
"J
^^
- T
,4
A1PUMN
^
7
U
7
NU
A3
7
13
NU
A 16
-_W|.
^^;o
i
T?l<
TMV
A.Z9
7
—
A
30
19,
I
c
J0 1
NU
A?
2
]e
i
NU
All
1
—
/HUNVN
7
IJ
»
VI
A23
7 :
U
NU
A16
»
1
W
IQ
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten
Line
(if
any)
Indicates Infernal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A5A5B
Figure
10-30.
Memory Timing Voters, Logic Diagram
(Sheet
3)
10-114
W<0
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
A1TLCV
A1SYLOVN
A2SYLOVN
A1TLC
A1X4
AIX4
A1X4
A1CST
A3V5MOD7
A2V5MOD7
A1V5MOD7
A1SYLON
A1Z5
Pin
52
54
56
58
60
*2
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1CSTV
A1RUN
A1X4
A2INHBSV
A1INHBSV
A1INHBS
A1RUNV
NU1
NU2
NU3
NU4
NU5
A1RUNVN
A1RUNN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
'5
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
Figure
10-30.
Memory Timing
Voters,
Logic
Diagram
(Sheet
4)
10-115
»
A2Y3
AlBRAO
(75>
(.77)
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A6A
Figure
10-30.
Memory Timing
Voters,
Logic Diagram (Sheet
5)
10-116
TMI
.(45")
t-f
i
H>
At ^
A 2V
A>V
A1EAM
<£o™
(43-)-
r
—
h
1
—
^
L
T-II
.T
J>
NL
g
A11
t
TM
t
A32
J.S.'-.
i
NU
t
A2<
HI
a
'
13
7
«i
^e*Mv
S
13
»
7
?j^L
^t NL
* A18
VI
*-«M
H_
VI
—
i
Is
.1..
_3JNL
1*3
P
sO
DDI__L
VI
AI7
14
•
e»«
1
1
A34J
|
J
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Si
qnol
CONNECTOR PINS
Pin
3
5
7
9
II
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
S
ignol
A2Y3
.
A2Y3
A2Y3
A2Y3"
SIG RET
SIG RET
A1M2SYNC
A1MOSYN
A1M4SYNC
A1M6SYNC
A1EAMV
VI
VI
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1M6SYNCV
A1M4SYNCV
A1EAM
A1M2SYNCV
A1MOSYNV
A3V5MOD7
A2V5MOD7
A1V5MOD7
A 1
BRAO
A1BRAON
V3
V3
A1X5
•A2Y3
A1BRAOV
A1BRAOVN
Figure
10-30.
Memory Timing Voters, Logic Diagram (Sheet
6)
10-117
AIXS
A.SVSM3D7•
A1V5MOD7-
AIRDM
•
;ZLL
fTg
NU
Ji
A3Z
ffl
I5IM7
a,
IS]AZ4
A1ROMM
(8JL}
TM/
A1
13
8
i.A8
IS
6
41
32
-I F
A1X5
A1MAO
(5fc>
CS+)
,
1
.
12
n
~~2"
^
~
q
P
6
[N
A
I"
T
A
l«
N
A
If
N
A
bi-
ll
11
t
yiv
3
t
II
ID
1
U
7
5
IC
'
13
;
7
13
7
7
13
7
oTPB
VI
AZ
VI
A9
Nil
A14
14
AlfeJBO
>.
14
,TJ.
^4
(7t)
,
|e
Z
T'
6 ,4<
-?
N
_g. Ai
,
.
1 l«
?
N
« A:
1
*v
»
i
U
i
i
II
S
'
13
»
|
7
13
e
7
'3 e
vr
y«3a
VI
A2
3
Nil
A16
7
r-
-
H
1
>
K
< r-|
1
(90)
1
/i
I
w
AIZS-
TS^i
~3?lVl8.
A1
KD -
<ZM -
TPS
13 8
^
NU
13
a
M
NU
-)R
-? s
HT
-i x
j
V
Figure
10-30.
Memory Timing Voters, Logic Diagram- (Sheet
7)
10-118
AIX5
r f
1
_
•
to
NU
It At
S
5
*
,
_9^S.i
2 TMV
t
/a.6
.
.
sJi
1
'"S
TMV
f
A"^l
AIZ5-
f
II )
oo —
}
oTPIO
'
13
3
HCI
A
2.7
,
11
•
CL»V
[I
/I28
T
13
3
TO NU
72
A4
Js
1
2 TMV
t AS
s
0
HCI
["*]
*1
^-A&syLiv
6
,TV>1
~*
13
7
VI
A12
T
a
Is|l
n
NU
6
A6
^
A1SYLC1V
r
13
7
NU
A13
«*
f fl
^
V
f
J
\
t
I
L J
1
14
r
L)|?3
7
LJ
NU
A14
14
NOTES:
1
. S
2. S
0
3. C
C
4.
'
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
A1SYLC1V
A1SYLIVN
A1SYLC1
A1X5
A1T5
A1X5
A1RD
A3V5MOD7
A2V5MOD7
A1V5MOD7
A1SYLIN
A1X5
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1RDV
A1MAO
A1Z5
A2RDMV
A1RDMV
A1RDM
A1MAOV
A2RDMVN
A1RDMVN
A1RDMN
A1MBOV
A1MBO
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
1 1
12
13
14
15
Signal
SIG RET
V]
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
See
Glossary
or
Index
for
Signal Definitions
See
Logic Symbols Appendix
for
Definition
of
Logic
Symbols
Dotted
Line
(if
any) Indicates
Internal
ULD
Connection
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A6B
Figure
10-30.
Memory Timing
Voters,
Logic
Diagram
(Sheet
8)
10-119
/t/l/S
AtODi-
•
#OOt--
JMXON-
l(^)-
NU'
-o TPt
42.9
a 7
7£
J.?,f
-4Z4XOVN
J1X
5-
(55)
(S1)-
e
Nl1
•
rp/o
Mll
e
v/
—
il/.<3VN
£
I.?
-AtjrjVN
Alt!:
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CO
NU
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/in
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Tttr
4/9
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111).
NU
49
ifl
7^//
^iT
IJ S //
-—/«/X//KA'
7\M
A1114N
-
AlAJtlN
(^l)
NU
^X
JPI2
&
£
-/»//?
X4YN
I 3
TAIY
ij / //
//I
J£
NU
-CTP8
18
9TMr
i* #*7 /
M:
-I/I
-18
-1C
-10
-46
Figure
10-31.
Memory Address Decoder Voters, Logic Diagram (Sheet
1 of 8)
10-120
NOTES:
I . See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A7A
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A1AX3VN
A2AX3VN
A1AXON
A1AX6N
A1AX1N
A2AX4VN
AIAX4VN
A1AX2VN
A2AX2VN
A1AX2N
A2AX7VN
A1AX7VN
A2X5
A1AXOVN
A2AXOVN
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1AX3N
A2AX1VN
A1AX1VN
A1AX4N
A2X5
A2X5
A1X6
A1AX5VN
A2AX5VN
A1AX5N
A1AX7N
A2AX6VN
A1AX6VN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
V3
VI
SIG RET
V3
VI
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A 1X6
(47,49,51,
53)
A2V5MOD6
A3V5MOD6
A1V5MOD6
Figure
10-31.
Memory
Address
Decoder Voters, Logic Diagram (Sheet
2)
10-121
A3V5
MO46
JMXXN
-
JtAXtOH
(88V
(.8t)
6
1
f
~i
j
-i.
A/X6
-^
V
AIXt
—
-T
ft
4
_s.
NU
4
e
9
/
^
—
—
c
,m
'\
7MY
S
>J
7
"ss
"—
•
'\
At.?
N
4
-1
r*
A
S
^
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7
S
6
'1
f
'2
a
r*
*
'
f
j£j
y
,;
i-
1}
"n
oTPIO
e
"x
-?—Al4X50VH
<\
<r
a
NU
/*•
4
rj s
S
6
r/
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8
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TMf
4
'•»
S
tf 7
/[
TM?
4
It
13
f/
AIS
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ft
A/4
t-wtie™
At
C
so) \ "1
to
7
•4-
I
67
2
NU
/
J9 *
0rP2
a }\ .
fAff
13 S // / .
jfjiifiAvtJ
AJ0
Aff
S
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r*i?
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4>7
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S'[
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,
— J
8 f\
Wy
ff ? M &
rtJdJf?^^
V
I
\
Figure
10-31.
Memory Address Decoder Voters, Logic Diagram
(Sheet
3)
10-122
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
.Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A7B
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
A1AX70N
A2AX60VN
A1AX60VN
A1AX50N
SIG RET
A2AX40VN
AIAX40VN
V3
AIAX40N
A2AX20VN
A1AX20VN
A2AX10VN
A1AX10VN
A1AX30N
VI
A2AX30VN
A1AX30VN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1AXOOVN
A2AXOOVN
SIG RET
V3
A1AX70VN
A2AX70VN
A1AX20N
A2AX50VN
A1AX50VN
V]
A1V5MOD6
A1AXION
A1AX60N
A1AXOON
A2V5MOD6
A3V5MOD6
THRU
PINS
Pin
].
2
3
4
5
6
7
8
9
10
1 1
12
13
14
15
Signal
SIG RET
V3
VI
SIG RET
V3
VI
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A1X6
A2V5MOD6
A3V5MOD6
A1V5MOD6
Figure
10-31.
Memory
Address
Decoder Voters, Logic Diagram (Sheet
4)
10-123
.. ?
MOQ
•
(S)
-
(?)
-•
/^O)
(.
II) '
—
-«
t7
'0
t
/
*•§
L
f
9
„
-m
f\
,1
^
-A
r?
^a
i
•w
ii
•4
f;
^
-^
N
^(
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7>
^/
,J
/>
<?>
N
/I
S
r*
/i.
8
r*
•i
N
4
|£
/*
4
#
^i
4
ft
U
y
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if
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i\
if
i
8
U
:
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1
<r
¥
$
U
I
;|
^
^5
t\
if
11
f
6 :
/J
,3
f
U
'3
s
V
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7T>>
7
f
•
TPI
e
f
-nr(
7
a
H
4JJ
f/
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o
VI
/t/S
I
w
All
>V
I'/
AW
/f
4/4
f
f
47
(j7
)
</?>
-<
^?)
(70-r
/Ol
)
—
r
—
-
f?
19
•>
1
f
7
^
2
^T
•^
'f
i1
^7
i
r.
/
7
-k.
7
1
N
a
a
T*
4
8
T/l
4
N
At
8
r*
4
8
r*
4,
N
*
4
'
ru
4.
U
>
'
ir
W
>\
if
'4
8
J
•
'I
tr
>?
/
'7
f
U
•i
'I
f
>f>
'I
f
'0
f
r?
13
f
IS
tt
f-
rj
/J
r
If
8
ft
7
7
-nTt
f
7
?
r/
1
$
r/
417
H
it/J
•>g
r/
jfff
w
A/4
14
j
xr-ftrf,
//
,
*^
14
»«
f
E
Figure
10-31.
Memory Address Decoder Voters, Logic Diagram (Sheet
5)
10-124
TUP
11
(*V)'
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Referenco
Designations
as
Follows:
A5A8A
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A1AY3VN
A2AY3VN
A 1
AVON
A1AY6N
A1AYIN
A2AY4VN
A1AY4VN
A1AY2VN
A2AY2VN
A1AY2N
A2AY7VN
A1AY7VN
A2X4
A1AYOVN
A2AYOVN
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1AY3N
A2AY1VN
A1AY1VN
A1AY4N
A2X4
A2X4
A2X6
A1AY5VN
A2AY5VN
A1AY5N
A1AY7N
A2AY6VN
A1AY6VN
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
V3
VI
SIG RET
V3
VI
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A2X6
A2V5MOD6
A3V5MOD6
A1V5MOD6
Figure
10-31.
Memory
Address Decoder Voters,
Logic
Diagram
(Sheet
6)
10-125
A1VSM0D6
A3V5
#006
AWOOH
n/irzott-
<$ -
Nil
-oTPIO
M4
Li
a
\AI2
—A2A/30W
AZXf
4'AYtOft
4M/T0//—
(««-
NU
-OTP£
iW
4A7
'
—
AIAYWM
M
414
AUY4CH
(3o)
_
NU
M
/j/j
^//
/UAY4MN
7
S
Mir
fJ
7
1*8
-sc
-fD
-f£
-16
Figure
10-31.
Memory
Address
Decoder
Voters,
Logic Diagram (Sheet
7)
10-126
NOTES
1.
2.
See
Glossary
or
Index
for
Signal Definitions
See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
"N.U. Indicates that
ULD is Not
Installed
although
Page
is
''Wired"
to
Accommodate
It
Prefix Reference Designations
as
Follows: A5A8B
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
S
ignal
A1AY70N
A2AY60VN
A1AY60VN
A1AY50N
SIG RET
A2AY40VN
A1AY40VN
V3
A1AY40N
A2AY20VN
A1AY20VN
A2AY10VN
A1AY10VN
A1AY30N
VI
A2AY30VN
A1AY30VN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1AYOOVN
A2AYOOVN
SIG RET
V3
A1AY70VN
A2AY70VN
A1AY20N
A2AY50VN
A1AY50VN
VI
A1V5MOD6
A1AY10N
A1AY60N
A1AYOON
A2V5MOD6
A3V5MOD6
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
V3
VI
SIG RET
V3
VI
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A2X6
A2V5MOD6
A3V5MOD6
A1V5MOD6
Figure
10-31.
Memory
Address
Decoder
Voters,
Logic
Diagram
(Sheet
8)
10-127
14
rj
430
A15BKIV•
A/TKIV
a
a
—
A\J2
V!
A
422
//>/
-S#At
J^ff
-£•
rr
fl
~\
7/V
At5
•SffiAM
AfSS/W
M4SA4
*•/
A'CffRM
vr •
0
r
f2
j
'
Figure
10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
1 of 12)
10-128
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
BRA2N
BRA2
BRAIN
BRA1
M2SA4
M6SA2
A1CERVN
A1TR1V
M4SA1
MOSA4
A1SBRZV
M4SA2
M2SA2
M2SA1
MOSAIC
M6SA1
MOSA2
BRA4N
A1TR2V
SIG RET
VI
BRA4
V3
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1TR4V
M6SA4
M4SA4
MOSAIC
A1TR7V
M4SA7
M6SA10
M4SA10
M2SA7
M2SA10
MOSA7
M6SA7
BRA7
A1TR10V
BRA
10
BRA7N
BRA10N
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A9A
Figure 10-32.
Memory
Buffer
Registers, Logic Diagram
(Sheet
2)
10-129
tiffS M
MM
* 3
13
A13
U
rr
A1TR3V
—
to
rr
-M6S/I5
TPt
o
1/£
a
A9
/H6S4S
I//
A
\ff_
Aft\
/t
\AtO\
yt
rr
<S\
X
\\4fS_
t
—\9
4
AfO
F
-
y
A/0
s
\AtA
AI7\
TP2
o
Figure 10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
3)
10-130
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
BRA13N
BRA11N
BRA
13
A1TR13V
BRA
11
M6SA11
MOSA11
M2SA13
M2SA11
M4SA13
M6SA13
M4SA11
A1TR11V
MOSA13
M4SA8
M6SA8
A1TR8V
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V3
BRAS
VI
'
SIGRET
A1TR5V
BRA8N
-
MOSA5
M6SA3
MOSA3
M2SA3
M2SA5
M4SA5
A1SBRYV
MOSA8
M4SA3
A1TR3V
A1CBRVN
M6SA5
M2SA8
BRA3
BRA3N
BRAS
BRA5N
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows: A5A9B
Figure 10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
4)
10-131
M-
a
14
rf
AtCBKVN-
mA]J2_
A
429\
JPI
o
A
AH
M1SA+
MJSA4
A\i
SI7SA4-
*'/-
AZTR4V—&\
A
!
SSftt
K
—^
(3
AIT
vr
a
-ZL
VI
415
/f?
O
Uo~i
J-H
rf>9
o
Figure 10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
5)
10-132
JISAT-
jff r
A
7
MSSA7
M7SA7
W
A^T/t7^
—
£
A2SBKIY
—
7_
4lf£KM
J2-
rr
—
p
1
1
W'
LA
4
4J4
4
434
—
]/
4
434
~\7
4
A27
~]'<
4
427
4
436
~\9
4
4JS
~\9
4
426
t4
j
2
f4
)
to
n
f2\
~\
/I
Jl
iss
y
438
>
S-
f
rt
c
JfSSafO
417
JAW
rr
—
Ai
TKIOV
—
^
Aisatiy-L
7/7
AtceRM
M.
•\
w
—
-
gtBflf
r^-
(_
0007
\ &
A
4J7
—
|/
A
420
~~\>l
A
A20
~~\J
A
420
—\7
A
413
A
414
A
421
~\9
A
421
~\f
4
414
?
X
tJ
/
^-|
/3
t?
~\
rf
-*{L*-
f
f
4f4
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
\5
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
BRB2N
BRB2
BRB1N
BRB1
M3SA4
M7SA2
A2CBRVN
A2TR1V
M5SA1
M1SA4
A2BRZV
M5SA2
M3SA2
M3SA1
M1SA1
M7SA1
M1SA2
BRB4N
A2TR2V
SIG RET
VI
BRB4
V3
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A2TR4V
M7SA4
M5SA4
M1SA10
A2TR7V
M5SA7
M7SAIO
M5SA10
M3SA7
M3SA10
M1SA7
M7SA7
BRB7
A2TR10V
BRB10
BRB7N
BRB10N
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic Symbols Appendix
for
Definition
of
Logic Symbols
3.
Dotten Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A5A10A
Figure
10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
6)
10-133
Figure
10-32.
Memory
Buffer
Registers, Logic Diagram
(Sheet
7)
10-134
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
BRB13N
BRB11N
BRB13
A2TR13V
BRB11
M7SA1
1
M1SA11
M3SA13
M3SA11
M5SA13
M7SA13
M55A11
A2TR1V
M1SA13
M5SA8
M75A8
A2TR8V
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
V3
BRB8
VI
SIGRET
A2TR5V
BRB8N
M1SA5
M7SA3
M1SA3
M3SA3
M3SA5
M5SA5
A2SBRYV
M1SA8
M5SA3
A2TR3V
A2CBRVN
M7SA5
M3SA8
BRB3
BRB3N
BRB5
BRB5N
NOTES:
1
See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference Designations
as
Follows:
A5A10B
Figure 10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
8)
10-135
410S/I6
vi -
A??
io
,m
13
W-
MffMf-
VI-
A/TRIV
13
a
\
VI
e
~~|9
A
A2-)
T
A
Ail
J
nLJ
I
i
i
A^9
I
A
22
*--
e
AtCBftVH
VI
BRA&tJ
VI-
A
I
—
AST
TPI
1 I5
•BRA'S
VI
A/PAftV
vl
/3
/_3_
e
VI
e
VI
a
~v
A
A9
—\7
A
All
~\V
A
All
~~I»
A
An
A
A/O
~~|9
A
AlO
~\9
A
An
—\9
A
A
16
a
2
14
13
7
*|
J
TP**
o
3| T 6
\AIO
1 \S , L
Art]
'
/ s
Ate
BRA 14
BRA
HP
Figure 10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
9)
10-136
AirK/ZV
A1SBRXV
AlCBfiM
VI
TP/8
a
VI
a
—
1»
A
A
28
~l»
A
A35
J
J
r
i
45S
f
5
a**/:
CONNECTOR
PINS
Pin
\
3
5
7
9
\\
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
BRA9
BRA6N
BRA6
A1TR6V
BRA9N
M2SA1
4
MOSA14
A1TR9V
MOSA6
M4SA6
M2SA6
MOSA6
M6SA6
M4SA9
M2SA9
M6SA9
BRA14N
V3
VI
BRA
14
A1PARV
A10BRVN
SIGRET
BRA14P
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
M6SA14
M4SA14
M6SA12
MOSA12
A1TR12V
M4SA12
M2SA12
BRA12N
A1SBRXV
BRA 12
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols Appendix
for
Definition
of
Logic
Symbols
3.
Dotted
Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A5A11A
Figure
10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
10)
10-137
xyjj
"A
6
M5SA6
/tf7SA6
VI
AtSBRXV
AiTP&V
AICBKVM
VI
9
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14
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Figure 10-32.
Memory
Buffer
Registers,
Logic Diagram (Sheet
11)
10-138
«W4
'4JS4f4
KSSAU
M7S/I/4
V)
VI
13
13
a
vr
a
VI
a
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A
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—\j
A
49
~~\7
A
AH
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A
—
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A
A/7
A
A/0
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A
A/0
T
A
A,
7
—
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A
Ata
13
2 _
14
t
13-
7
tz
~|
J
.3-
/
r
AIO
I
All
I
Aie
rp<-
o
S
S
s
Jf/J/l/S
•
MJ5/I/Z
MSSJ/2
M7SAr?
VI
fl
'
AZCBRVU
VI
S
7
—
—
8
VI
e
—
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A
A3*
—\r
A
A21
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A
A21
—
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AZB
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/
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A*
/J
2
6
1
J
Z±J
IS
^
/ 1
0
3j 7 S
|>4?«
7 5 ,
X35
BffBIZH
B&BI2
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
BRB12
A2SBRXV
BRB12N
M3SA12
M5SA12
A2TR12V
M1SA12
M7SAI2
NASSAU
M7SA14
BRBUP
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
SIG RET
A2CBRVN
A2PARV
BRB14
VI
V3
BRB14N
M7SA9
M3SA9
M5SA9
M7SA6
M1SA6
M3SA6
M5SA6
M1SA9
A2TR9V
M1SA14
M3SA14
BRB9N
A2TR6V
BRB6
BRB6N
BRB9
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic Symbols
3.
Dorted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A11B
Figure 10-32.
Memory
Buffer
Registers,
Logic
Diagram
(Sheet
12)
10-139
41
VSUODt
•
4?&MODt-
A3\/SMOO<i>
•
All/OKI
(as)
~f TMY
NU
41
•orPS
c
-
4wr
76\!
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AS!
NU
M
(5)
_z
8l
.NU
A34
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iff
J-
NU
NU
y-
can
NU
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fT9)
ras;-
NU
rW
/J 7
1
?W
NU
/J
<*NU
X-
NU
4J5
h^-r55)
tll'MW
(73)-
(TSlr
NU
JICNAM
NU
an
if
NU
« £
NU
-ia
-ic
HO
Figure 10-33. Address
Register
and
Memory Module
Register Voters,
Logic
Diagram
(Sheet
1 of 4)
10-140
(37)
—
(39)—
»
fn)
—
(89)—
•
—\
(
~""1
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r?
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to
s
-7
i
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7
.?
i
10
I
2
SI
J
N
4
7
U
A
7
N
i
7
t\
A
N
4
1
|;
r*
/i
r
N
X
/
N
X<
I
14,
U
sj
^
OTP3
SI/
ir
a f ff /
j*j3i>
U AS
S\f
u 1 a
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14
ftT-f
(V|
|^/tf
|^
«L
, ,
u
a 7
NU
,* .
/; ^/y "'^
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ij
f
7
6
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.
ni
f
r a a f/ /
JUM/IVN
>f
j
10
k
j
\i
U
/J
<f
NU
/ ,
rg
jf9
(d3>
U
// x' NU //
,6;r)
'/
W
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
\7
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A1A7V
A1A7
A1A9V
A1DMAVN
VI
V3
SIGRET
A1A8
A1A9
VI
V3
SIG RET
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1HOPC1
A1A8V
A1IMAVN
A 1
OMAN
A1HOPC1V
A1IMAN
SIG RET
VI
V3
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A3V5MOD6
(74,
2)
(4, 6)
(4, 6)
A2V5MOD6
A1V5MOD6
NOTES:
1
. Sec
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A12A
Figure
10-33.
Address
Register
and
Memory Module
Register
Voters,
Logic
Diagram
(Sheet
2)
10-141
4/VSMOD6-
A3VSMOO6
'
Ob)
(•79)
tt,
NU
-OTfJ
4
w~
—
JIAIY
*]!
NU
a 7
—
(89)
(86)
04)
At'A
4
41
At
ft
(581
NU
4}
(98)
—orrg
w
W
•4jNu1</
<y[NTn
/
(S6)
7
t\l
NU
NU
X//
14
Cf8)
f2f)
NU
I wr tf 7 rs >4
NU
fj 7
(34)
Ur^l(
r—n
j]
NU
/y tf.NUl/_
2\4X\
"^//|~
(30)
(0
I
IAMJI—aLM
LP?JZ_
_~
I-
(43)
\
*u!
J
f48J
Figure
10-33.
Address Register
and
Memory Module
Register Voters,
Logic
Diagram
(Sheet
3)
10-142
/)S-
Bf-
C
J-
A1A3
NU
AS
-OTP3
m
AN
a a
i
lit
NU
fj
w
NU
a
(14)
J/JsF1
_
2
TMV
a
NU
JtS
a
J—AH3V
NU
AJ6
-!—
(18)
-OTPIt
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic Symbols Appendix
for
Definition
of
Logic Symbols
3.
Dotted Line
(if
any)
Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A12B
CONNECTOR PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
A1A6
A1A3V
A1A5
A1A5V
A1A6V
A1A4V
A1A4
Pin
52
54
56
58
60
62
64
66
68
70
-72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1A2V
A1A3
A1A2
A1V5MOD6
A2V5MOD6
A3V5MOD6
A1A1V
A1A1
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Siqnal
A3V5MOD6
(74,
2)
(4, 6)
(4, 6)
A2V5MOD6
A1V5MOD6
Figure 10-33. Address Register
and
Memory Module
Register Voters,
Logic
Diagram
(Sheet
4)
10-143
AZZff
A1CBRW
00
NOTES
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U. Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A13A
Figure
10-34.
Transfer
Register
and
Memory Module
Register
Voters,
Logic
Diagram (Sheet
1 of 4)
a
10-144
(
IT) -
i
in.
-.
1
TO
<l
NU
A29
TM
iL
0
,1
_
t 1
i
I'M 11
TMV
13
fi
Ail
,
A-SBR.X-
-lit
P,
XV
C"»V-
1
jo
TF3
6
NU
*u
.
!
1'
,
e
~S
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
1?
13
14
15
Signal
SIGRET
VI
V3
SIGRET
VI
V3
SIGRET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
77
28
29
30
Sianal
v
I
A?4
L-^SBRxv
(45)
(45,51)
CONNECTOR
PINS
Pin
I
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
NU
A3W4
A2Z5
NU
SIG RET
SIG RET
A1SBRX
A1SBRX
A1SBRY
A1SBRY
A1TBRV
VI
VI
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Signal
A2SBRYV
A1SBRYV
A1TBR
A2SBRXV
A1SBRXV
A3V5MOD2
A2V5MOD2
A1V5MOD2
A1CBRN
A1CBRN
V3
V3
A2Z5
A2Z5
A1CBRVN
A2CBRVN
Figure
10-34.
Transfer
Register
and
Memory
Module
Register
Voters,
Logic
Diagram
(Sheet
2)
10-145
4IV5MODC:
.
AA'UMOOt
f-
(Z?,74,7
AIHI2OH
.
(96)
r-
(2g.7<
A1MSSN
—
(SQ-
;
f-,78)
__
«)
$
J
f
4
r
<
/
~j
2
^5-
i-
^/
e
—
r,r/»r
1
7|«l'
T"MIS
1
3
.f K^ /
7?i
NU
// 7 NU //
..„„.
^ .-^ ^yj
(88J
7 8\t
NU
/^ ,y NU /
,g6.
X^1-^
A /^
5
NU 5
^'
OTf'/O
7
eli
74fA
rj » ^.' . vr
1
'!«!/
NU
fj ^
NU
<• ,„,
7
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SH
—
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f44)
1
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J/M7TN
Jf-
f»-H
—
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NUl5_
nht
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r>>
-
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"fix.
Jl'
w
« 7 /y v ^
fiffTfn
w
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7
N
^
^
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ultf
<?
NU /
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NU|/J
7 NU|
/./,«,,
X.
?)
XV| -"'
BMOW-J
ran
..
(98)
'ij
*•
i
f
A,
/
,
NU
X
<*!•
/"
/v
^
OTP//
3 1
fi,
fy , MI fjf
x>/5
XV
si
NU
/y x- NU r/
,-,„,
'/
X?.V
"" "
7
3N
~^T'
1
el1
U
fj £ NU r
/-a^i
V
X/V '^
•«r
-, ~i
—
il
10
»
.
,,r^
\&
*
*•
NU
r0 * > z^ '
Figure
10-34. Transfer Register
and
Memory
Module
Register Voters,
Logic
Diagram
(Sheet
3)
10-146
A>
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix Reference Designations
as
Follows: A5A13B
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal
NU1
NU2
NU3
A1IMBN
A1MFFVN
A1DMBN
A1DMBVN
A1IMBVN
A1MSSVN
A1MSSN
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Signal
A1MTTVN
A1MFFN
A1MTTN
A1V5MOD6
A2V5MOD6
A3V5MOD6
A1MZOVN
A1MZON
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20.
21
22
23
t-i
25
26
27
28
29
30
Siqnal
A3V5MOD6
NU1
NU2
NU3
A2V5MOD6
A1V5MOD6
Figure
10-34. Transfer
Register
and
Memory
Module
Register Voters,
Logic
Diagram (Sheet
4)
10-147
xJ
/
vSMODf
•
A3\/SMOOi
'
f85)
4lf
To
NlTU
-iJS.<>
m
NU
—
(S)
NU
INU
~-%%
-TPtO
insr
-^
zisir
NU
^ £
NU
-*-
(81)
[gjr
NUI /y e NU
(33V
NU 5
.
f67)
/ £!/
/
a
A
ITK9V
i
NU
0 NU
^-(5<I)
INU
(4,4)
r/f 13
TPII
_z"
A
tO
•^
NU
/y /• NU
•Vi?
•vt
NU
/y
NU
Y
(23)
Figure
10-35.
Transfer
Register
Voters, Logic Diagram
(Sheet
1 of 6)
10-148
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix
Reference
Designations
as
Follows:
A5A14A
CONNECTOR
PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31 "
33
35
37
39
41
43
45
47
49
Signal
A1TR7V
A1TR7
A1TR8V
A1TR13V
VI
V3
SIGRET
A1TR9
A1TR8
VI
V3
SIG RET
Pin
51
53
55
57.
59
61
63 .
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
A1TR11
A1TR9V
A1TR10V
A1TR13
A 1 TR 1 1 V
A1TR10
SIGRET
VI
V3
THRU
PINS
Pin
1-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S
iqnal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
VI
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A3V5MOD2
(2,
28, 78)
(4, 6)
(4, 6)
A2V5MOD2
A1V5MOD2
Figure 10-35. Transfer Register Voters, Logic Diagram
(Sheet
2)
10-149
A3
JIT
fit ,
(Ik)
,j-
(
^
t4
!>
f€3)
[
'
ts
—j-
6,
(
a
v
^
vj
(,
SI
<*
1
f,
i
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orf,j
7
B]l
"£•) e.»f
<-J,TK,V
781;
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k, ( t «
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7 S\f
™so
if r]n 14
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A/./I
7
at
^JNU
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,,,,
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:
1
7
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'
NU
w
'
.9
Lv*l
'
V
. J
xrf
I
SB
—
fc
-fD
tf
(48)
Figure 10-35.
Transfer
Register
Voters, Logic Diagram
(Sheet
3)
10-150
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotten Line
(if
any)
Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows:
A5A14B
CONNECTOR
PINS
Pin
2
4
6
8
10
12
14
16
18
20.
22
24
26
28
30
32
34
36
38
40
42
'
44
46
48
50
Signal
AITR6
A1TR2V
A1TR5
A1TR5V
AITR6V
A1TR4V
A1TR4
Pin
52
54
56
58
.60
62
64
66
68
70
72
74
76
78
80
82
.84
86
88
90
92
94
96
98
Signal
A1TR3V
A1TR2
A1TR3
.
A1V5MO02
A1TR1V
A1TR1
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
SIG RET
VI
V3
SIG RET
VI
V3
SIG RET
V4
V3
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
A3V5MOD2
(28,
2, 78)
(4,
if.)
(4, 6)
A2V5MOD2
A1V5MOD2
Figure 10-35. Transfer Register Voters,
Logic
Diagram
(Sheet
4)
10-151
A3W4
—
A3V5M0D2
A1TR12.
A3K5
—
A1SBR7
-
(i7;
—
(IT)
—
i
-
t
10
12
e
NU
Afl
1
J.
t
r
i
2.
t
I
9
T
i,
8
1
TMV
A?
9
|b
1
TM/
A?
2
5
6
OTPt
7
13
£
VI
A
30
A1TKW
7
12
e
VI
A23
1
NU
A15
—
I
i-Ae™
7
13
8
NU
A 1
It
rn.v
e
5
£_
NU
Alt
o
T»5
(35^-1
A3X5-
r
*s
VI
A.10
1
AZ
.
AlPAR
—
AISBkt/
(451-
—
c*?;—
'
13
_
VI
Al
A2SBRZV
T
Id
. -
o
1
TMV
7
13
VI
A30
I
IB
1
14.
7
NU|n
A^4|
7
?
^.
T»
VI
A23
1
NU
A17
1,
w
*-(*>
f3
7
NU
A16
l»
NU
AS
/
M
S—
oTP1l
, t
g
^.
J«J
Th
I
Ic
'-H
win
i 1 7
i
TMV
A4
VI
A10
,4
13
7
vr
A3
li
—
A 2
PA
Rv
^
_{
^
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
5.
Prefix
Reference
Designations
as
Follows: A5A15A
Figure
10-35.
Transfer
Register
Voters,. Logic Diagram (Sheet
5)
10-152
A3W4
L>f
<Ci}
^L.
A
iZ
NU
A12
- T
1
I*!1
TMV
. t
s
tf
Tfll'
NU
A?*
_T.
<
NU'
*—
OTP|!
^
li_
»
VI
A34
,
AICDS
.- -
(?*)
-i -
'
«
NU
A27
'''•''
F
"H
NU
A20
[(.
,:
W(il)
•
. 8
NU
1
~
n?'L
" Z TMV
. t
AJ5
1 NU
It
AZfl
1
riaiu
lilV
S—
oTPI?
T
li-
r
li_
VI
A
34
NU
U_
NU
AZO
H
!±_
-
A1COSV
(83)
CONNECTOR PINS
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Signal
A1TR12
A2TR12V
A1TR12V
A1SBRZ
A1TRSV
A2SBRZV
A1SBRZV
A1TRS
A3W4
A1PARV
A2PARV
A1PAR
SIGRET
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
Signal
SIGRET
A3X5
V3
A3X5
A1TRSN
V3
A1TRSVN
A3W4
VI
A3X5
A1CDSV
AICDS
A1V5MOD2
A2V5MOD2
A3V5MOD2
VI
'
THRU
PINS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
Figure
10-35. Transfer Register Voters,
Logic
Diagram
(Sheet
6)
10-153
AnRDMVN MmSTRP3
NOTES:
MmSYNCV1)
1
.
See Glossary or Index for Signal Definitions
2. See Logic Symbols Appendix for Definition of
Logic Symbols
3.
Dotted Line (if any) lndicates Internal ULD
Connection
4.
"N.U." Indicates that ULD is Not Installed
although Page
is
'Wired" to Accommodate it
5.
Prefix Reference Designations as Follows:
A6AMA6A1, where M
=
Memory Module
~ssealy Number 1 Trough
4
6.
Terminals with Numbers Prefixed by "A" are
Located on the MIB. All Others are Located
on the Printed Circuit Board
7.
m Represents the Memory hdule Number
0
through
3
-MmRDPl -MmRDP2 -MmRDP3
-
8.
n is a
1
if m
is
an Even Number, and a
2
if m
is
an Odd Number
9.
Asterisk Indicates Narrower Output Pulse than
,
from Receding MCD-2 Circuit
Figure 10-
36.
Memory
Clock
Driver
and TCV,
Logic
Diagram (Sheet 1
of
2)
10-154
Changed
4
January
1965
AnlNHBSV
MmMCL
MmMC N
MC
D-2.
,
AnRDMV
-
.
A
-
*
-
MmSTROB
MCD-1 MCD-2
a
-
-
-
I
A6AMA6A1J
PWR RET
SIG RET
MmTCV
SIG RET
20fl
MmCRX—-AA/V-
AnV20—<
I
MmCRY—v-
•PWR
RET
SIG RET
TERMINAL
AREA
-El
PIN
]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SIGNAL
MmTSE2
MmTSEl
V5
V5
VI
VI
TCVADJ
AnM20
AnM20ID
AnM20ID
AnRDMV
V3
V3
AnRDMVN
SIG RET
SIG RET
MnSYNCV
AnINHBSV
PIN
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SIGNAL
MmMCN
MmMCL
PWR RET
PWR RET
MmSTRPl
MmSTRP2
AnM20ID
AnM20ID
MmlNH2
MmlNH4
MmlNH6
MmlNHS
MmlNHIO
MmlNH12
MmlNHU
V3
MmTCV
MmTCV
SIG RET
SIG RET
MmSTROB
TERMINAL
AREA-
E2
PIN
1
2
3
4
5
SIGNAL
MmCRX
MmCRX
MmTCV
MmTCV
SIG RET
PIN
6
7
8
-9
SIGNAL
MmSTRPl
MmSTRPS
MmRDP3
MmRDP2
PIN
1
2
3
4
5
TERMINAL
AREA
SIGNAL
MmCRY
MmCRY
MmTCV
MmTCV
SIG RET
PIN
6
7
8
9
-E4
SIGNAL
MmRDP2
MmSTRPl
MmSTRP2
MmRDPl
1
'.
Figure 10-36.
Memory
Clock Driver
and
TCV, Logic Diagram (Sheet
2)
Changed
4
January
1965
10-155
Figure
10-37.
Memory Sense Amplifiers, Logic Diagram (Sheet
1 of 2)
10-156
Changed
4
January
1965
LVUlu-
W!»"
|A6AMA3AI|
MmSLllA(48)
—
MmSLUB(4A)
—MmSAll(4)
MmSL9A(6B)
—
MmSL9B(6A)_
A>
—MmSA9(6)
MmSL13A(2B)—
MmSL13B(2A)_
—MmSA1.3(2)
TERMINAL
AREA
- El
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIGNAL
MmSL14B
MmSL14A
MmSL13B
MmSL13A
MmSL12B
MmSL12A
MmSLllB
MmSLllA
MmSLlOB
MmSLlOA
MmSL9B
MmSL9A
MmSLSB
MmSLSA
MmSL7B
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
SIGNAL
MmSL7A
MmSL6B
MmSL6A
MmSLSB
MmSLSA
MmSL4B
MmSL4A
MmSL3B
MmSL3A
MmSL2B
MmSL2A
MmSLIB
MmSLlA
TERMINAL
AREA
-E 3
Pin
1
2
3
4
5
6
7
8
9
10.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Signal
MmSTROB
TPSA14
TPSA13
TPSA12
TPSA1
1
TPSA10
TPSA9
V3
TPSA7
VI
V5
SIG RET
SIGRET
V5
VI
TPSA8
V3
TPSA6
TPSA5.
TPSA4
TPSA3
TPSA2
-
TPSA1
Pin
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Signal
;
MmSTROB
MmSA14
MmSA13
MmSA12
.
MmSAll
MmSAlO
MmSA9
V3
MmSA7
VI
V5
SIG RET
SIGRET
V5
VI
MmSAS
V3
MmSA6
MmSAS
MmSA4
MmSA3
MmSA2
MmSAl"
Figure 10-37.
Memory
Sense Amplifiers, Logic Diagram
(Sheet
2)
Changed
4
January
1965
10-157
BRA1
—
a
—
BRB1
—
B
—
MmSTRPl
. ••
MmSTRP2
r
MmTVC—
»—
ID
BRA6
—
BRB6—
P
"
BRA
11
—
a
—
BRB11
—
P
—
BRA2—
—
MmlNHl
BRB°
—
P
—
TP3
1_
ID
BRA7
—
—
MmlNH6
BRBa7H
fl —
,
TP13
ID
.
,
BRA
12—
—
MmlNHl
1
BRB1°
—
&~~
ID
,1
'1
BRA3
—
—
MmlNH2
BRB3
—
P
—
TP4
1
)
ID
,
BRAS
—
—
MmlNH7
BRB8—
P —
TP9
ID
T
.
BRA
13
—
MmlNHl
2
BRB?3—
P —
ID
—
MmlNH3
TP11
f
ID
-MmlNHS.
f
r
TP14
ID
—
MmlNH13
I f Li
NOTES:
1. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix
Reference
Designations
as
Follows:
A6AMA7A1, where
M =
Memory Module
Assembly
Number iTFirough
4
6. m
Represents
the
Memory Module Number
0
through
3
7. n is a 1 if m is an
Even
Number,
and a 2 if
m
it an Odd
Number
8. If m is an
Even'
Number,
a
=AlBRAOVand
0=A2BRAOVN
9. If m is an Odd
Number,
a
=AlBRBOVNand
0 =
A2BRBOV
Figure 10-38.
Memory
Inhibit Drivers, Logic Diagram
(Sheet
1 of 2)
10-158
ChangecM
January
1965
TP2
a
—
BRB4
—
B
r
<-
r • •'
i
1
D
BRAS—
—
MmlNHf
BRB5
—
D
TP5
.[A6AMA7A1I
1
—MmlNHS
TP12
TPIO
BRA9
—
•
• • a —
BRB9
—
B —
F
/
1
0
:. .
BRA10—
—
MmlNH9
..
BRB10—
•
'•'
'.-.-.
• '
1
D
-MmlNHlO
H
f-
—
MmlNHH
TERMINAL
AREA
E2
PIN
1
2
3
4
5
SIGNAL
AnM20
MmlNHl
.
MmlNH5
MmlNHS
MmlNH7
PIN
6
7
8
9
SIGNAL
MmlNH9
MmlNHl
1
MmlNHl
3
AnM20
TERMINAL
AREA
E4
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SIGNAL
0
a
BRA1
BRB1
BRA3
BRB3
BRA5
BRB5
BRA7
BRB7
BRA6
BRB6
BRA4
BRB4
BRA2
BRB2
BRB10
BRA12
BRB12
BRA14
BRB14
BRA10
BRB8
BRAS
BRB9
P|N
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SIGNAL
BRA9
BRB11
BRA 11
BRB13
BRA13
PWR RET
PWR RET
PWR RET
MmSTRPl
MmSTRP2
AnM20
AnM20
MmlNH2
MmlNH4
MmlNH6
MmlNHS
MmlNHtO
MmlNH12
MmlNHM
V3
MmTCV
MmTCV
SIG RET
SIGRET
Figvire
10-38.
Memory
Inhibit
Drivers,
Logic
Diagram
(Sheet
2)
Changed
4
January
1965
10-159
MmSTRP1
lAYOOVN
<
MmCRY
XnAYOVN
(
E
1
1
E
I
MmHEYO
AnAYlOVN—
4
MmHIYO
i
E
I
MmEDIYO
MmLIYO
AnAYWN
(
MmLEYO
1
1
E
i
r
R
MmHEYl
MmHIYl
>—
MmEDIYl
^AmLIYl
MmLEYl
i r H
Figure 10-39.
Memory
Y-Address Drivers,
Logic
Diagram
(Sheet
1 of 4)
10-160
A
r.
AnAY20VN—
(
c r
D
f
E
r
F
r
AnAY2VN-H
H C
1
E
I
1
E
<
—
p-
I
MmHEY2
AnAYSOVN—
4
MmHIY2
I—
MmEOIYZ
MmLIY2
AnAYSVN
(
MmLEY2
i
E
1
I
':
MmHEY3
MmHIYS
>
-MmEDIY3
—
-MmLIY3
:'
1
MmLEY3
A6AMA5A1
TERMINAL
AREA
- E 1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SIGNAL
MmLEYO
MmLlYO
MmLEY2
MmLIY2
MmLEY4
MmLIY4
MmLEY6
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SIGNAL
MmLIY6
MmLEY7
MmL|Y7
MmLEYS
MmLlYS
MmLEYS
MmLIY3
MmLEYl
MmLIYl
TERMINAL AREA-
E3
PIN
1
2
3
4
.5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SIGNAL
MmHEYO
MmHIYO
MmHEYl
MmHIYl
MmHEY2
MmHIY2
MmHEY3
MmHIY3
MmHEY4
PIN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
SIGNAL
MmHIY4
MmHEYS
MmHIYS
MmHEY6
MmHIY6
MmHEY7
MmHIY7
MmCRY
MmCRY
AAnTCV
MmTCV
MmRDP2
MmSTRPl
MmSTRPZ
MmRDPl
TERMINAL
AREA
- E 4
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SIGNAL
MmTCV
AnM20
AnAYTVN
AnAYSVN
AnAYSVN
AnAYOVN
AnAYlVN
AnAY2VN
AnAY4VN
AnAY6VN
SIG RET
SIGRET
VI
EDmY
V3
PIN
18
19
20
21
•22
23
24
25
26
27
28
29
30
31
32
33
34
SIGNAL
V3
EDMY
VI
PWRRET
PWR RET
AnAY60VN
AnAY40VN
AnAY20VN
.
AnAYlOVN
AnAYOOVN
AnAYSOVN
AnAYSOVN
AnAY70VN
AnM20.
MmTCV
Figure
10-39.
Memory
Y-Address
Drivers,
Logic Diagram (Sheet
2)
Changed
4
January 1965
10-161
(B)
MmSTRP1
AnAY'HWN
<
(C)
MmRDP2
(D)
MmTCV
• "••
(E)
MmCRY
(F)
MmSTRP2
Ar.AY4VN
<
//-^\
MmRDPl
(H)
MmEDEY
f
1
,
,
1
MmHEY4
AnAY50VN_
MmHIY4
1
MmEDIY4
•
MmLIY4
AnAY5VN^—
<
-MmLEY4
I
1
F
_
' i
/B
MmHEYS
AAmHIYS
r T>,
J"
E
t—
MmEDlYS
MmLlYS
MmLEYS
k
/• u
Figure
10-39.
Memory Y-Address
Drivers,
Logic Diagram (Sheet
3)
10-162
A-»
oj
AnAY60VN—
<
'
\
1
f
1
F
F
1
—
i
i
MmHEY6
AnAY70VN
^
MmMIVA
'
1
MmEDIY6
AnAYTVN^—
<
Mm) FVA
[
:
<
1
MmHEY7
>—
MmEDIYZ
Mml
IY7
JuLml
FV7
>
MmEDIYO
MmEDIYl
MmEDIY2
—
—
MitiEDIY3
MmEDIY4
MmEDlYS
MmEDIY6
MmEDIY7^
MmCRY
MmEDEY
ED
—EDmY
NOTES:
1. See
Glossary
or
Index
for
Signal
Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows:
A6AMA5A1, where
M =
Memory
Module
Assembly
Number
1
TRrough
4
6. m
Represents
the
Memory
Module
Number
0
through
3
7. n is a 1 if m is an
Even
Number,
and a 2 if
m
is an Odd
Number.
Figure 10-39.
Memory
Y-Address Drivers, Logic Diagram
(Sheet
4)
Changed
4
January
1965
10-163
Mm SIR PI
AnAXOOVN^—
<
MmCRX
MmRDP3
AnAXOOVN
1
MmSTRPl
»
1
—
^-~
E
(
»—
—
I
E
(
, , ,
MmSlEO
AnAXlOVN—
<
MmSllO
1
1
i—
>—
E
I
1
MmEDIO
MmSOlO
AnAXlOVN—,
' (
>—
—
E
1
1
i 1 f*.
1 B
MmSlEl
MmSlll
f
P
i
MmEDM
' '
f
U
MmSOIl
MmSOEl
5
J
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix Reference Designations
as
Follows:
A6AMA1A1 where
M_=
Memory
Module
Assembly
Number
1
through
4
6. m
Represents
the
Memory
Module
Number
0
through
3
7. n is a 1 if m is an
Even
Number,
and a 2 if
m
is an Odd
Number
Figure
10-40.
Memory Hi-X
Address
Drivers,
Logic
Diagram
(Sheet
1 of 4)
10-164
Changed
4
January
1965
A6AMA1A1I
8
)
AnAX20VN—
<
D
f
f
r,
AnAX20VN
H
K
I
(
1 «
^—
>—
i
1
••
-
E
1
__
MmSlE2 AnAXSOVN
(
kl—CllO
1
MmEDI2
MmSOI2
AnAXSOVN—
<
>
' (
_
>~
^«
1
1
'
1
1
MmSTRPI
(0)
MmSlES
.... MmRDP3
(C)
:
-AnSYLlVN
(D)
MmTCV
/[)
i—
MmEDIS
MmSOI3
MmSOE3
1
'•
MmEDEX
flO
TERMINAL
AREA
- E 1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SIGNAL
MmLEX7
MmLIX7
MmEDI7
MmLEX6
MmLIX
6
MmLEXS
MmLIXS
MmLEX4
MmLIX4
MmEDI6
MmSOI7
MmSOE7
MmSOI6
MmSOE6
MmEDIS
MmSOIS
MmSOES
MmSOH
MmSOE4
MmEDU
MmEDEX
PIN
23
24
25
26
•27
28
29
30
31
32
33
34
35
36
37
38
SIGNAL
MmEDI3
MmSOIS
MmSOE3
MmSOI2
MmSOE2
MmEDI2
MmSOIl
MmSOEl
MmEDIl
MmSOlO
MmSOEO
MmEDIO
*
TERMINAL
AREA
- E 2
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SIGNAL
MmTCV
AnM20
AnAX70VN
AnAXTVN
AnAXSOVN
AnAXSVN
AnAXSOVN
AnAX4VN
AnAXlOVN
AnAX6VN
SIG RET
SIG RET
AnSYLOVN
VI
EDmX
V3
V3
EDmX
VI
AnSYLlVN
PWRRET
PIN
23
24
25
26
27
28
26
30
31
32
33
34
35
36
SIGNAL
PWRRET
AnAX2VN
AnAXOOVN
AnAXOVN
AnAX20VN
AnAXlVN
AnAX40VN
AnAXSVN
AnAX60VN
AnM20
MmTCV
X
TERMINAL
AREA
- E 3
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SIGNAL
MmRDP2
MmRDP3
MmSTRPS
MmSTRPl
MmTCV
MmTCV
MmCRX
MmCRX
MmSll7
MmSlE7
MmSH6
MmSlE6
MmSllS
MmSllES
MmSlU
PIN
23
M
25
26
T7
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SIGNAL
MmSIE4
MmSllS
MmSlES
MmSll2
MmSlE2
MmSllI
MmSlEl
MmSllO
MmSlEO
MmLIXS
MmLEXS
MmLIX2
MmLEX2
MmLIX
1
MmLEXl
MwiLIXO
MmLEXO
Figure
10-40.
Memory Hi-X
Address
Drivers,
Logic
Diagram
(Sheet
2)
Changed
4
January 1965
10-165
(A)
MmEDEX-
(B)
MmSTRPl-
AnAX'(CYN-
(C)
MinRDPS-
(D)
AnSYLlVN-
(E)
MmTCV-
ff)
MmCRX-
(G)
AnSYLOVN-
(H)
MmRDP3-
AnAX40VN-
(J)
MmSTRPl-
(K)
MmEDEX-
—
(
/
,; : - •
1
(
r"
»
—
E
'
J
—
<
<-
T
•
—
—
E
i
t
MmSlE4
AnAXSOVN—
,
MmSlU
I
(
h-
E
\
H-MmEDI4
MmSOU
AnAX50VN
—
<
1
:
I
(
*
t—
1
E
_
1
1
1
; )«
MmSlES.
MmSllS
fr
H-
MmEDIS
/i/
MmSOlS
MmSOES
1
f If
Figure 10-40.
Memory
Hi-X Address Drivers,
Logic
Diagram
(Sheet
3)
10-166
Changed
4
January 1965
ED
—€OmX
tn
n
(
° \
AnAX60VN
-4
F J
"-}
AnAX6QVN-<
•J
i
*<
,
i
i
*—
E
1
1
•
<
ii
»
—
^
r
1
E
(
'
.MB.S1E6
AnAX70VN—
(
MmSH6
1
1
h—
--*•
-
E
1
MmEDI6
MmS016
AnAX70VN
1
MmSOE6
1
i ,
E
^^
(
h-MmEDI7
—
MmSOI7
u_cr>E7
MmEDIO
MmFD]
1
MmED12
MmED13
MmED14
MmEDlS
MmED16
—
MmED17
MmfDEX
MmCRX
ED
NOTES:
1. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates
that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix
Reference
Designations
as Fol
lows:
A6AMA1A1 where
_M
=
Memory
Module
Assembly
Number
1
through
4
6. m
Represents
the
Memory
Module
Number
0
through
3
7. n is a 1 if m is an
Even
Number,
and a 2 if
m
is an Odd
Number
Figure 10-40.
Memory
Hi-X Address Drivers, Logic Diagram (Sheet
4)
Changed
4
January
1965
10-167
MmRDP2
AnAXOVN-
<
•*
MmTCV
AnAX4VN
(
MmRDP?
»
1
E
1
»
'
E
-
MmLEXO
AnAXlVN—
-<
MmLIXO
MmEDIO
I
_
1 B
E
.
,
•MmEDU
MmLIX4AnAXSVN
1
MmLEX4
I
1
-E
MmLEXl
MmLIXl
MmEDU
>
r
' c
)
r
f
t
•>
r
1
'
MmEDIS
MmLIXS
MmLEXS
I. 3 W
NOTES:
1
. See
Glossary
or
Index
for
Signal
Definitions
1. See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
. .
3.
Dotted Line
(if
any) Indicates Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
frefix
Reference
Designations
as
Follows:
A6AMA1A2,
where
_M
=
Memory
Module
Assembly
Number
1
through
4
6. m
Represents
the
Memory
Module
Number
0
through
3
7. n is a 1 if m is an
Even
Number,
and a 2 if
m'is
an Odd
Number
Figure
10-41.
Memory Lo-X
Address
Drivers,
Logic Diagram (Sheet
1 of 2)
10-168
Changed
4
January
1965
M 1
A
„
A
V
OV
/ M ..
D >
f r
r )
r
r
H C
i
C
1
AnAX3VN^—
4
MmLIX2
Mm EDI 2
Mm£DI6
AnAXTVN
^-^
\
,
kjmi
iya
MmEDI7
...
—
MmLEX7
|
A6AMA1A2|
-MmEDEX
TERMINAL AREA-
E 1
PIN
1
2
3
4.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SIGNAL
MmEDIO
MmSOEO
MmSOlO
Mm EDI 1
MmSOEl
MmSOIl
MmEDI2
MmSOE2
MmSOI2
MmSOES
MmSOIS
MmEDIS
MmEDEX
MmEDU
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SIGNAL
MmSOE4
MmSOI4
MmSOES
MmSOIS
MmEDI5
MmSOE6
MmSOI6
MmSOE7
MmSOI7
MmEDI6
MmLIX4
MmLEX4
MmLIXS
MmLEXS
MmLIX6
MmLEX6
Mm
EDI
7
MmLIX7
MmLEX7
TERMINAL AREA-
E3
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SIGNAL
MmLEXO
MmLIXO
MmLEXl
MmLIXl
MmLEX2
MmLIX2
MmLEXS
MmLIXS
MmSlEO
MmSllO
MmSlEl
MmSlll
MmSlE2
MmSH2
MmSlE3
MmSllS
MmSlE4
MmSlU
PIN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
SIGNAL
MmSlES
MmSllS
MmSlE6
MmSll6
MmSlE7
MmSH7
MmCRX
MmCRX
MmTCV
MmTCV
.
MmSTRPl
MmSTRP3
MmRDP3
MmRDP2
TERMINAL
AREA
- E 4
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SIGNAL
MmTCV
AnM20
AnAX70VN
AnAXTVN
AnAXSOVN
AnAXSVN
AnAXSOVN
AnAX4VN
AnAXlOVN
AnAX6VN
SIG RET
SIG RET
AnSYLOVN
VI
EDmX
V3
V3
PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SIGNAL
EDmX
VI
AnSYLlVN
PWRRET
PWRRET
AnAX2VN
AnAXOOVN
AnAXOVN
AnAX20VN
AnAXIVN
AnAX40VN
AnAXSVN
AnAX60VN
AnM20
MmTCV
Figure
10-41.
Memory Lo-X
Address
Drivers,
Logic
Diagram
(Sheet
2)
Changed
4
January
1965
10-169
Figure
10-42.
X
Memory
Address
Diode
Matrix, Schematic Diagram (Sheet
1 of 2)
10-170
*<,
•-
*<««
r:M
|A6AMA2|
A6AMA2,
where
_M
=
Memory Module
Assembly
Number
Figure 10-42.
X
Memory
Address Diode Matrix, Schematic Diagram (Sheet
2)
Changed4
January
1965
10-171
Figure
10-43.
Y
Memory
Address
Diode Matrix, Schematic Diagram (Sheet
1 of 2)
10-172
A
<r
B
*-
C
t~
P
>-
E >•
f
t
G »•
H <r
J $•
K V
L <r
M
*
H
*
P
»
R V
S V
7 V
U
*
V
*
rTI r"3 r"
uO
51
^..t-.i1..
r ~i r
^an
:f
if I*
.~,, >£,. >~
'£,%
|A6AMA4|
-OILIV718Z
-OILEY7180
-OILIY6I78
-OIIEV6I76
-O(LIYS)
86
-OILEY5I84
—OILIY*!
74
—OIIEY4172
—01LIY3190
—o|l£Y3)68
—OILIY2I70
—OIUY2168
—O(LIYI)
9*
-odEYtl
92
—0(UYO)66
-OHEWI64
NOTES:
See
Glossary
or
Index
for
Signal Definitions
See
Logic
Symbols
Appendix
for
Definition
of
Logic
Symbols
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
"N.U."
ndicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
It
Prefix Reference Designations
as
Follows:
A6AMA4,
where
M =
Memory
Module
Assembly
Number
Figure
10-43.
Y
Memory
Address
Diode
Matrix,
Schematic
Diagram
(Sheet
2)
Changed
4
January
1965
10-173
TC
t
If
X
V
p
s x
Cl
X
"^
C5
x
^
C2
s "s
C2
s
s
C3
N
S
C7
VI
C4
C8
PWR-RET
TERMINAL
AREA
El
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
•
Signal
MmSA14
MmSA13
MmSAl
2
MmSAll
MmSAlO
MmSA9
V3
MmSA7
VI
V5
SIG RET
SIG RET
V5
VI
MmSA8
V3
MmSA6
MmSAS
MmSA4
MmSA3
MmSA2
MmSAl
Pin
Signal
'
C9
Cll
CIO
C12
SIG-RET
TERMINAL
AREA
E2
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Sianal
MmTCV
AnM20
AnAYTVN
AnAYSVN
AnAYSVN
AnAYOVN
AnAYlVN
AnAY2VN
AnAY4VN
AnAY6VN
SIG RET
SIG RET
VI
EDmY
V3
V3
EDmY
VI
PWR RET
PWR RET
AnAY60VN
AnAY40VN
AnAY20VN
AnAYlOVN
AnAYOOVN
AnAY30VN
AnAYSOVN
AnAY70VN
AnM20
MmTCV
Pin
Signal
TERMINAL
AREA
E3
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Signal
AnAX60VN
AnAX3VN
AnMCL
AnMCN
AnINHSV
MmSYNCV
SIG RET
SIG RET
AnRDMVN
V3
V3
AnRDMV
AnM20ID
AnM20ID
AnM20
VI
VI
V5
V5
PWR RET
PWR'
RET
PWR RET
BRA
13
BRB13
BRA11
BRB11
BRA9
Pin
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45.
46
47
48
49
50
51
52
53
54
Siqnal
BRB9
BRAS
BRB8
BRA
10
BRB14
BRA
14
BRB12
BRA12
BRB10
BRB2
BRA2
BRB4
BRA4
BRB6
BRA6
BRB7
BRA7
BRB5
BRAS
BRB3
BRAS
BRB1
BRA1
a
/3
AnAYSOVN
AnAY70VN
Figure
10-44,
Memory
Input-Output
Panel,
Schematic
Diagram
(Sheet
1 of 2)
10-174
M20
X
?
CIS
N
7
C17
i
• i
x
?
C14
\ 7
C18
x
*
CIS
s
7
C19
MEMORY
SENSE
AMPLIFIER
SIDE
C16
C20
X
PANELS
SIDE
PWR-RET
1
Terminal Area
El 1
E4
E2
r E5 1
1
E3 1
Y
PANELS
SIDE
[A6AMA8A1]
TERMINAL
AREA
E4
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Signal
MmTCV
AnM20
AnAX70VN
AnAXTVN
AnAXSOVN
AnAXSVN
AnAXSOVN
AnAX4VN
AnAXlOVN
AnAX6VN
SIG.:RET
SIGRET
AnSYLOVN
VI
EDmX
V3
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
V3
EDmX
VI
AnSYLlVN
PWR RET
PWR
RET
AnAX2VN
AnAXOOVN
AnAXOVN
AnAX20VN
AnAXlVN
AnAX40VN
AnAXSVN
AnAX60VN
AnM20
MmTCV
NOTES:
1
. See
Glossary
or
Index
for
Signal Definitions
2. See
Logic
Symbols
Appendix
for
Definition
3.
Dotted Line
(if
any) Indicates
Internal
ULD
Connection
4.
"N.U."
Indicates that
ULD is Not
Installed
although
Page
is
"Wired"
to
Accommodate
it
5.
Prefix
Reference
Designations
as
Follows:
A6AMA8A1,
where_M
=
Memory
Module
Assembly
Number
1
through
4
6. m
Represents
the
Memory Module Number
0
through
3
7. n is a 1 if m is an
Even
Number,
and a 2 if
m
is an Odd
Number
TERMINAL
AREA
E5
Pin
1
2
3
' 4
5.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Signal
AnSYLlVN
MmSA13
AnSYLOVN
MmSAll
MmSA2
AnAX40VN
MmSAl
AnAX4VN
MmSA4
AnAX2VN
MmSAS
AnAX20VN
MmSAS
MmSA3
MmSA7
AnAXTVN
MmSAlO
AnAXlOVN
MmSAH
AnAXOVN
MmSA6
AnAXSOVN
MmSA12
MmSA9
AnAY6VN
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Signal
AnAYSVN
AnAYlVN
AnAYOOVN
AnAXOOVN
AnAXSOVN
AnAX70VN
AnAYlOVN
AnAXlVN
AnAYOVN
AnAXSOVN
EDmX
AnM20
MmTCV
EDmY
AnAY20VN
AnAYTVN
AnAY2VN
AnAX6VN
AnAY4VN
AnAY40VN
AnAY60VN
AnAXSVN
AnAYSVN
AmM20
FOR
MEMORY MODULE
0,2,4
&6
0
a
A1BRAOVN
Al
BRAOV
FOR
MEMORY MODULE
1,3,5,
&7
A1BRBOV
A1BRBOVN
Figure
10-44.
Memory
Input-Output
Panel,
Schematic
Diagram
(Sheet
2)
Changed4
January
1965
.
10-175
V20BM
*
V20AM
L4
ANODE
CR4
LI
.
ANODE
CRl
A2M20ID
°-
A1M20
O-
1
2
f
L3
ANODE
CR3
L2
ANODE
CR2
A1M20ID
CIO
-*•
C12
-^h
C16
C14
-4H
C4
-^H
C6
C2
C9
Cll
C15
-)h
C13
C7
-4h
C3
-4h
C5
C1
A
SIG-RET
SIG-RET
Figure
10-45.
Memory
Distribution
Panel,
Schematic Diagram (Sheet
1 of 4)
10-176
V3
C28 C27
-7l^—
)h
C26 C25
SIG-RET
VI
V5
^r~
~^i
—
C24
C23
lil: +-1\
<
C22 C21
^
C20
•C19
CIS
. C17
E3
SIG-RET
SIG-RET
Figure 10-45. Memory Distribution :Panel, Schematic Diagram
(Sheet
2)
10-177
TERMINAL
AREA
J3
PIN
1
2
3
4
5
6
7
8
9
10
II
2
3
4
5
6
(7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
SIGNAL
2SY11VN
2AX60VN
ISA13
2AX3VN
2SYLOVN
2MCL
ISA])
2MCN
ISA2
2INHSV
2AX40VN
1SYNCV
1SA1
GRET
2AX4VN
GRET
1SA4
RDMVN
2AX2VN
1SA8
2RDMV
2AX20VN
M20ID
SA5
M2CHD
SA3
ISA?
5
2AX7VN
PWR-RET
M1SA10
PWR-RET
A2AXIOVN
BRA13
M1SAI4
BRB13
A2AXOVN
BRA1I
M1SA6
BRBH
A2AX30VN
MISA12
BRB9
MISA9
BRA
8
A2AY6VN
PIN
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
94
95
96
97
98
SIGNAL
BRB8
A2AY5VN
BRA
10
A2AYIVN
BRBH
A2AYOOVN
BRA14
A2AXOOVN
BRB12
A2AY30VN
BRA12
A2AX70VN
BRBIO
A2AY10VN
BRB2
A2AXIVN
BRA2
A2AYOVN
BRB4
A2AX50VN
BRA
4
ED1X
BRB6
A2M20
BftA6
MITCV
B1B7
ED1Y
BRA7
A2AY20VN
BRB5
A2AY7VN
BRAS
A2AY2VN
BRB3
A2AX6VN
BRA
3
A2AY4VN
BRfil
A2AY40VN
BRA1
A2AY60VN
AlBRBOVNfet)
A1BRBOV(£)
A2AY3VN
A2AY50VN
A2M20
A2AY70VN
TERMINAL
AREA
J4
PIN
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SIGNAL
A2SYLIVN
A2AX60VN
M3SA13
A2AX3VN
A2SYLOVN
A2MCL
M3SA11
A2MCN
M3SA2
A2INHSV
A2AX40VN
M3SA1
SIG RET
A2AX4VN
SIG
RET
M3SA4
A2RDMVN
A2AX2VN
V3
M3SA8
A2ROMV
A2AX20VN
A2M20ID
M3SA5
A2M20ID
M3SA3
VI
M3SA7
V5
A2AX7VN
PWR-RET
M3SA10
PWH-RET
A2AX10VN
BRA13
M3SA14
BRB13
A2AXOVN
BRA
11
M3SA6
BRBlt
A2AX30VN
BRA9
M3SA12
BRB9
M3SA9
BRAS
A
2AY6VN
PIN
50
51
52
53
54
55
56
57
58
59
60
62
63
64
65
66
67
68
69
70
71
72
73
74
5
6
7
8
9
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
SIGNAL
BRB8
A2AY5VN
BRA
10
A2AYWN
BRB14
A2AYOOVN
BRA
14
A2AXOOVN
BR812
A2AY30VN
BRA12
BRBIO
A2AYIOVN
BRB2
A2AX1VN
BRA2
A2AYOVN
BRB4
A2AX50VN
BRA4
E03X
BRB6
A2M20
BRA6
M3TCV
BRB7
ED3Y
BRA7
A2AY20VN
BRE5
A2AY7VN
BRA5
A2AY2VN
BRB3
A2AX6VN
BSA3
A2AY4VN
BRB1
A2AY40VN
BftAl
A2AY60VN
IBRBOVNfcO
A2AX5VN
AIBRBOV(0)
2AY3VN
2AY50VN
2M20
2AY70VN
TERMINAL
AREA
J6
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SIGNAL
V20BM
V20BM
V208M
V20BM
V20BM
V20BM
V20BM
V20BM
SIG-RET
SIG-REI
PIN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SIGNAL
SIG-RET
'
SIG-RET
V3
V3
VJ
V3
SIG-RET
StG-RET
SIG-RET
SIG-RET
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SIGNAL
SIG-RET
VI
VI
VI
SIG-RET
VI
VI
VI
SIG-RET
SIG-RET
PIN
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SIGNAL
SIG-RET
SIG-RET
SIG-RET
V5
V5
V5
V5
SIG-RET
SIG-RET
SIG-RET
PIN
81
82
83
84
65
86
87
88
89
90
91
92
93
94
95
96
97
98
SIGNAL
V20AM
V20AM
V20AM
V20AM
V2QAM
V20AM
V2CAM
V20AM
TERMINAL
AREA
JB
PIN
1
2
3
4
5
6
7
a
9
10
n
12
13
14
15
16
17
18
1?
20
21
2?
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
36
39
40
41
42
43
44
45
46
47
48
49
SIGNAL
6RB9
Ml
SAB
M2SA12
BRB7
MISA14
M3SA14
M3SA7
MISA9
M3SA8
M1SA6
MOSAI2
M3SA6
BRBIO
8RB3
M1SA3
BRB5
M3SA9
M1SA5
BRA12
BRB8
BRB14
BRB4
PIN
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
8)
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
SIGNAL
M3SA
M3SA2
BRA 14
M3SAI1
M1SA4
M2SA9
M3SA13
M1SA1I
MOSA6
M2SA6
M15A12
MOSA9
BRB11
BRB13
MOSAU
A2MCN
M3SA12
BRB1
M2SA14
BRB12
BRA9
M3SA4
BRB2
BRA6
NOTE:
1. THE
SIGNAL
RETURN
AND PWR
RETURN
PLANES
ARE
COMMONED
AT ALL
POSITIONS
(WHEREVER POSSIBLE)
THAT
CONTAIN
EITHER
SIGNAL
.
2. IBM
ABBREVIATION
AND
LETTER
SYMBOL
SPECIFICATION
6109008
APPLIES.
Figure 10-45. Memory Distribution Panel, Schematic Diagram (Sheet
3)
10-178
•
-. '
TERMINAL
AREA
Jl
PIN
1
2
.3
4
' 5
6
7
8
9
10
11
12
13 •
14
15
'16
17
18
19
20
21
22
23
24
25
24
27
28
29
30
31
32
33
34
35
36
37
'
38
39
40
41
42
43
44
45
46
47.
,
48
49
AISYLIVN
A1AX60VN
M2SAI3
A1AX3VN
.A1SYLOVN
AIMCL
M2SAM
'
AtMCN
M2SA2
A1INHSV
A1AX40VN
M2SYNCV
M2SAI
'
SIG-RET
AIAX4VN
SIG-RET
M2SA4
AIRDMVN
A1AX2VN
V3
M2SA8
AIROMV
'A1AX20VN
A1M20ID
M2SA5
AIM20ID
M2SA3
VI
M2SA7
V5
A1AX7VN
PWR-HET
M2SA10
PWR-RET
•
AlAXtOVN
BRA
13
M2SAI4
BRBI3
-'
AUXQVN
BRA
1 1 '
M2SA6
BRB11
AIAX30VN
BRA9
.
M2SAI2
BRB9
M2SA9
BRAS
AIAY6VN
50
51
52
53
54
55
56
57
56
59
60
61
62
63 •
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
63
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
BRBB
A1AY5VN
BRA10
A1AY1VN
'
BRBU
AlAYOOVN
BRAU
A1AXOOVN
BRB12'
' '
AIAY30VN
BHAI2
AIAX70VN
BftBIO
A1AYIOVN
BRB2
A1AX1VN
BRA
2
A1AYOVN
BRB4
A1AX50VN
&RA4
ED2X
BRB6
A1M20
BRA6
.
M2FCV
BRB7
EOZY
BRA?
i .
A1AY20VN
MBS
A1AY7VN
BRAS
A1AY2VN
BRB3
A1AX6VN
BRA3
A1AY4VN
•
wai
A1AY40VN
'
BRA)
A1AY60VN
AIBRAOVB)
AIAX5VN
AlBRAQVNffl
A1AY3VN
A1AY50VN
A1M20
AIAY70VN'
TERMINAL
AREA
J5
PIN
•i
2
3
4
5
6
7
6
9
to
)|
12
13
U
15
16
17
IB
19
20
21
22
23
24
25
26
27
2B
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 •
49
SIGNAL
AISYLIVN
A2AX3VN
A1SYLOVN
A2AX60VN
A2SYL1VN
AIAX3VN
, ,•
A1AX60VN
A2SYLOVN
A2AX40VN
A2AX4VN
A
1
AX
40V N
BRB6
EDOX
A2MCL
AIAX4VN
EOOY
AIAX2VN
A2AX2VN
ED1X
A2AX20VN
A2AX
10VN
ED1Y
A1AX20VN
AIAX7VN
ED2X
AIAX10VN
MA3
ED2Y
A2AX7VN
BRAS
ED3X
A1AXOVN
A2AX30VN
AIMCL
A2AXOVN
PIN
50
SI
52
53
54
55
56
57
58
59
•
60
61
62
63
64
65
66
67
68 •-
69
70
71
72
73
74
75
76
77
78
'
79
80 -
Bl
82
83
84
85
"
86
. 87
68
89
90
91
92
93
94
95
96
97
98
SIGNAL
.
A2AXOOVN
A1AX3QVN
AIAXOOVN
A2AX70VN
-
A2INHSV
AIAX70VN
M2SYNCV
A2AX1VN
A2RDMV
A1AX1VN
AIRDMV
A2AX50VN
MOSYNCV
M3SYNCV
MISYNCV
A1INHSV
ED3Y
AIAX50VN
AlBRAOVN(/3)
A2RDMVN
A2AX6VN
AIBRBOVNK)
A2AX5VN
AIRDMVN
AIAX5VN
AIMCN
THERM3
AlBRAOVff)
A
1AX6VN
AIBRBOV(0)
THERM4
TERMINAL
AREA
J2
PIN
,
2
3
4
5
6
7
8
9
0
I
2
3
4
5
6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
y>
40
4)
42
43
44
-45
46
47
48
49
SIGNAL
AISYLIVN
A1AX60VN
MOSA13
A1AX3VN
A1SYLOVN
AIMCL
MOSAI1
AIMCN
. ••
MOSA2
A1INHSV
A1AX40VN
MOSYNCV
MOSA1
SIG-RET
A1AX4VN
SIG-RET
MOSA4
AIRDMVN
A1AX2VN
V3
MOSA8
A 1
RDMV
•
AIAX20VN
AIM20ID"
M05A5
A1M20ID
MOSA3
VI
MOSA7
V5
A1AX7VN
PWR-RET
MOSAIC
PWR-RET
A1AX10VN.
BRA
13
MOSA14
BRB13
AIAXOVN
BRA 11
MOSA6
BRBII
A1AX30VN
MA9
MOSAI2
MB9
MOSA9
BRAS
AIAY6VN
PIN
50
51,
'
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79 -
80
81
82
83
84
B5
86
87
S8
89
90
91
92
93
94
95
96
97
58
SIGNAL
BXB8
A1AY5VN
BRA
10
A1AYIVN
BRB14
A1AYOOVN
BRAU
AIAXOOVN
BRBI2
AIAY30VN
BRA
12
AIAX70VN
BRB10
A1AY10VN
Bit
62
A1AX1VN
BRA2
AIAYOVN
BRB4
A1AX50VN
BRA
4
EDOX
BRB6
AIM20
BRA6
MOTCV
BRB7
EDOY
BRA7
AIAY20VN
BIBS
A1AY7VN
BRA5
A1AY2VN
BRB3
AIAX6VN
BRA
3
AIAY4VN
BttBI
A1AY40VN
BKAI
AIAY60VN
IBHAOVfcO
1AX5VN
IBRAOVN(£)
1AY3VN
1AY50VN
1M20
A1AY70VN
TERMINAL
AREA
J7
PIN
1
1
12
13
14
15
16
17
18
19
20
21
22
23
24
'
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
tf
43
44
45
46
47
48
49
SIGNAL
BRA7
BRA
10
MOSA8
M2SAIO
AIAY6VN
MOSA7
A2AY5VN
M2SA7
M2SA3
AIAY5VN
M2SA5
A1AY50VN
M3SA3
A2AY6VN
M3SA5
MOSA3
A2AY50VN
M3SA10
AIAY1VN
MOSA5
A2AY1VN
M2SA8
A1AY70VN
A2AY70VN
BRAS
M1SA10
MISA2
MOSA10
M1SAI3
A2AYOOVN
PIN
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
"
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
68
89
90
91
92
93
94
95
96
97
98
SIGNAL
A1AYOOVN
M1SA1
A1AY30VN
M1SA7
A2AYOVN
BRA4
A2AY30VN
MOSA13
AIAY10VN
AIAYOVN
A2AY7VN
MOSA2
A1AY7VN
A2AY10VN
MOSAI
A1AY20VN
M2SA1
A2AY20VN
M2SA2
A2AY2VN
M2SA11
AIAY2VN
A1AY4VN
A1AY40VN
A2AY4VN
MQSA4
A2AY40VN
M2SAI3
BRA
II
MOSM1
BRA
13
BRA1
A1AY60VN
A2AY3VN
BRA2
A2AY60VN
M2SA4
A1AY3VN
Figure 10-45.
Memory
Distribution Panel, Schematic Diagram
(Sheet
4)
10-179
SIGNAL
A
AB
ABN
ACCO
ACCON
ACC1
ACC1N
ACC1V
AID
AION
All
AI1N
AI1V
AI2
AI2N
AI2V
AI2VN
AI3
AI3N
AI3V
AI3VN
AI4
AI4N
AN
AND
ANDN
AV
AVN
AXON
AXOVN
AX1N
AX1VN
AX2N
AX2VN
AX3N
AX3VN
AX4N
AX4VN
AX5N
AX5VN
AX6N
AX6VN
AX7N
AX7VN
AXOON
AXOOVN
AX10N
ORIGIN
A1A13-A
1
A1A5-A
A1A10-B
_L
A4A7-A
A1A5-A
J_
A1A10-B
_L
A4A7-B
A1A10-B
1
A4A7-B
J_
A1A10-B
_L
A4A7-B
_L
A1A10-B
_L
A1A13-A
A1A10-A
1
A4A9-A
_L
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-A
A5A7-A
A1A19-B
A5A7-B
A1A19-B
SIGNAL
AX10VN
AX20N
AX20VN
AX30N
AX30VN
AX40N
AX40VN
AX50N
AX50VN
AX60N
AX60VN
AX70N
AX70VN
AYON
AYOVN
A
YIN
AY1VN
AY2N
AY2VN
AY3N
AY3VN
AY4N
AY4VN
AY5N
AY5VN
AY6N
AY6VN
AY7N
AY7VN
AYOON
AYOOVN
AY10N
AY10VN
AY20N
AY20VN
AY30N
AY30VN
AY40N
AY40VN
AY50N
AY50VN
AY60N
AY60VN
AY70N
AY70VN
Al
A1AN
ORIGIN
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A7-B
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A19-B
A5A8-A
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A20-B
A5A8-B
A1A19-A
_L
SIGNAL
A1N
A1V
A2
A2AN
A2N
A2V
A3
A3AN
A3N
A3V
A4
A4AN
A4N
A4V
A5
A5AN
'
A5N
A5V
A6
A6AN
A6N
A6V
A7
A7AN
A7N
A7V
A8
A8AN
A8N
A8V
A9
A9N
A9PADN
A9V
B
BD
BDN
BN
BOT1
BOT2
BOT3
BRAO
BRAON
BRAOV
BRAOVN
BRA1
ORIGIN
A1A19-A
A5A12-B
A1A19-B
1
A5A12-B
A1A19-A
1
A5A12-B
A1A19-B
1
1
A5A12-B
A1A19-B
1
A5A12-B
A1A19-B
1
A5A12-B
A1A19-A
1
A5A12-A
A1A19-A
1
_L
A5A12-A
A1A19-A
J_
A1A20-B
A5A12-A
A1A10-A
A1A8-A
_L_
A1A10-A
A4A11-A
1
A1A16-A
J_
A5A6-A
J_
A5A9-A
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure
10-46.
Signal
Origin
List
(Sheet
1 of 8)
10-180
SIGNAL
ORIGIN
BRAIN
A5A9-A
BRA2
1
BRA2N
J_
BRAS
A5A9-B
BRA3N
1
BRA4
A5A9-A
BRA4N
|
BRAS
A5A9-B
BRA5N
|
BRAG
A5A11-A
BRA6N
1
BRA7
A5A9-A
BRA7N
|
BRAS
A5A9-B
BRA8N
1
BRA9
A5A11-A
BRA9N
|
BRA10 A5A9-A
BRA10N
|
BRA11 A5A9-B
BRA11N
1
BRA12
A5A11-A
BRA12N
1
BRA13 A5A9-B
BRA13N
1
BRA14
A5A11-A
BRA14N
1
BRA14P
1
BRBO A1A16-B
BRBON
1
BRBOV
A5A5-A
BRBOVN
I
BRB1 A5A10-A
BRB1N
BRB2
BRB2N
1
BRB3
A5A10-B
BRB3N
1
BRB4
A5A10-A
BRB4N
|
BRB5
A5A10-B
BRB5N
1
BRB6
A5A11-B
BRB6N
I
BRB7
A5A10-A
BRB7N
|
BRB8
A5A10-B
SIGNAL
ORIGIN
BRB8N
A5A10-B
BRB9
A5A11-B
BRB9N
_j_
BRB10 A5A10-A
BRB10N
1
BRB11 A5A10-B
BRB11N
1
BRB12
A5A11-B
BRB12N
1
BRB13 A5A10-B
BRB13N
|
BRB14
A5A11-B
BRB14N
|
BRB14P
1
BO1
A4A11-B
BO1A
A4A12-B
BO1N
A4A11-B
BQ1P A4A12-B
BO2
A4A11-B
BO2A
A4A12-B
BO2N
A4A11-B
BO2P A4A12-B
BO3
A4A11-B
BO3A
A4A12-B
BO3N
A4A11-B
BO3P A4A12-B
C
A1A10-A
CBRN
A1A11-B
CBRVN
A5A13-A
CD
A1A8-A
CDN
|
CDS
A1A11-A
CDSN
|
CDSV
A5A15-A
CKP
A1A11-B
CKPN
1
CLTR
A1A11-A
CLTRN
|
CN
A1A10-A
CNC
A1A15-B
CNCN
1
COC
COCN
J_
CST
A1A15-A
CSTN
External
CSTV
A5A5-B
SIGNAL
ORIGIN
DATAV
External
DIN
|
DLD31B A1A5-A
DLD44B
|
DL31 A1A7-A,
J_
A1A10-B
DL31SA A1A5-A
DL44
A1A7-A,
1
A1A10-B
DL44SA
A1A5-A
DMA
A1A16-A
OMAN
A1A14-A
DMAVN
A5A12-A
DMB
A1A16-B
DMBN
A1A14-A
DMBVN
A5A13-B
DM0
A1A14-A
DM1
DM2
DM2N
DM3
DM3N
J
DSS
A1A20-A
DSSN
DS1
DS1M
DS1MN
DS1N
DS2
DS2M
DS2MN
DS2N
_
DSS
A1A20-A
DS3N
DS4
DS4N
J
DTM
A1A7-A
DTMN
_[_
DTMV
A4A14-B
DTMVN
1
DUPDN
A1A14-A
DUPBST
I
EAC
A1A16-A
EADM
1
EADMN
|
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure
10-46.
Signal
Origin
List
(Sheet
2)
Changed
4
January
1965
10-181
SIGNAL ORIGIN
EAIM
A1A16-A
EAIMN
1
EAM 1
EAMV
A5A6-A
EAP
A1A17-A
EAPN A1A16-A
EEC
A1A16-B
EBDM
EBDMN
EBIM
EBIMN
EBM
EBMV
A5A5-A
EBP
A1A17-B
J_lJ_fX^
XLXXAj.
I JJ
EBPN A1A16-B
EDAC
A1A16-A
EDACN
1
EDBC A1A16-B
EDBCN
_|
EDmX A6AMA1A1
EDmY A6AMA5A1
EIAC A1A16-A
EIACN
1
EIBC A1A16-B
EffiCN
I
EMDN
A1A8-A
ESD
A1A8-B
ESDN
1
ESDV
A4A14-A
ESDVN
_|
EXM
A1A12-A
EXMD
A1A20-B
EXMDN
_|
EXMN
A1A12-A
EXMV
A4A6-B
EXMVN
_L_
FCD
A1A12-A
FMDN
A1A8-A
FSA
A1A16-A
FSAN
1
FSB
A1A16-B
FSBN
—
1
—
Gl
A1A13-A
GIN 1
SIGNAL ORIGIN
G1V
A4A7-A
G1VN
J_
G2
A1A13-A
G2N
J_
G2V
A4A13-A
G2VN
A4A7-A
G3
A1A13-A
G3N
J_
G3V
A4A13-A
G3VN
A4A6-A
G4
A1A13-A
G4N
_|
G4V
A4A8-B
G4VN
1
V-PI
V Al
^^^^^»
G5
A1A13-A
G5N 1
G5V
A4A8-A
G5VN
A4A13-A
G6
A1A13-A
G6N 1
G6V
A4A6-A
G6VN
1
G7
A1A13-A
G7N 1
G7V
A4A9-A
G7VN
A4A6-A
HALTV
External
HOP
A1A12-A
HOPC1 A1A14-B
HOPC1N
1
HOPC1V
A5A12-A
HOPN
A1A12-A
HOPV
A4A5-A
HOY
A1A7-A
HOYN
J
HOYV
A4A13-B
HOYVN
_|
HP1
A1A14-B
HP1N
1
IMA
A1A16-A
IMAN
A1A14-A
IMAVN
A5A12-A
1MB
A1A16-B
IMBN
A1A14-A
SIGNAL
ORIGIN
IMBVN
A5A13-B
IMO
A1A
IM1
IM2
IM2N
IMS
IM3N
—
14-A
INHBS
A1A15-A
INHBSV
A5A5-B
INT
A1A12-A
INTA
INT
AN
INTB
TNTRN
ESTTCV
External
INTN
A1A12-A
INTV
A4A6-B
ISS
A1A20-A
ISSN
IS1
IS1N
IS2
IS2N
133
ISSN
IS4
IS4N
JBN
A1A12-B
Kl
A1A7-B
KIN 1
K2
K2N
—
l—
MAO
A1A15-B
MAOV
A5A6-B
MBO
A1A15-B
MBOV
A5A6-B
MDO
A1A5-A
MDON
—
L_
MD1
A1A7-B
MD1N
MD2
MD2N
J
MD2V
A4A14-B
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure 10-46. Signal Origin List
(Sheet
3)
10-182
Changed
4
January 1965
SIGNAL ORIGIN
MD3
A1A7-B
MD3N
MD4
MD4N
MD5
MD5N
MD6
MD6N
MD7
MD7N
J
MD7V
A4A14-B
MFF
A1A15-B
MFFN A1A14-A
MFFVN A5A13-B
MOP
A1A15-A
MRO
A1A5-A
MRON
J
_
MR1
A1A9-A
MR1N
J_
MR1V A4A9-B
MR1VN
J_
MR2
A1A9-A
MR2N
J_
MSS
A1A15-A
MSSN
A1A14-A
MSSVN
A5A13-A
MSVB1 A1A4-A
1
A4A3-A
J_
A5A3-A
MSVB2 A1A4-A
1
A4A3-A
J_
A5A3-A
MTT
A1A15-A
MTTN A1A14-A
MTTVN A5A13-A
MZO
A1A15-A
MZON
A1A14-A
MZOVN
A5A13-A
MmCRX A6AMA1A1
J_
A6AMA1A2
MmCRY A6AMA5A1
MmEDEX A6AMA1A2
MmEDEY A6AMA5A1
MmEDIYO
A6AMA7A1
MmEDIYl
MmEDIY2
MmEDIYS
MmEDIY4
SIGNAL ORIGIN
MmEDIYS A6AMA7A1
MmEDIYG
1
MmEDIY7
J_
MmEDIO
A6AMA1A1,
2
MmEDIl
MmEDI2
MmEDI3
MmEDI4
MmEDIS
MmEDIG
MmEDI7
J
MmHEYO
A6AMA5A1
MmHEYl
MmHEY2
MmHEYS
MmHEY4
MmHEYS
MmHEY6
MmHEY7
MmHIYO
MmHIYl
MmHIY2
MmHIYS
MmHIY4
MmHIYS
MmHIYG
MmHIY7
J
MmlNHl A6AMA7A1
MmINH2
MmINH3
MmINH4
MmlNHS
MmlNHG
MmINH7
MmlNHS
MmINH9
MmlNHIO
MmlNHll
MmINH12
MmlNHlS
MmINH14
J
MmLEXO
A6AMA1A2
MmLEXl
MmLEX2
MmLEX3
MmLEX4
MmLEXS
MmLEX6
J
SIGNAL ORIGIN
MmLEX7 A6AMA1A2
MmLEYO
A6AMA5A1
MmLEYl
MmLEY2
MmLEYS
MmLEY4
MmLEYS
MmLEYG
MmLEY7
J_
MmLKO A6AMA1A2
MmLDCl
MmLEX2
MmLDCS
MmLK4
MmLIXS
MmLK6
MmLK7
J
MmLIYO
A6AMA5A1
MmLIYl
MmLIY2
MmLIY3
MmLIY4
MmLIYS
MmLIY6
MmLIY7
J
MmRDPl
A6AMA6A1
MmRDP2
I
MmRDPS
J_
MmSAl A6AMA3A1
MmSA2
A6AMA3A2
MmSAS
A6AMA3A1
MmSA4
A6AMA3A2
MmSAS
A6AMA3A1
MmSA6
A6AMA3A2
MmSA7
A6AMA3A1
MmSAS
A6AMA3A2
MmSA9
A6AMA3A1
MmSAlO
A6AMA3A2
MmSAll
A6AMA3A1
MmSA12 A6AMA3A2
MmSAlS A6AMA3A1
MmSA14 A6AMA3A2
MmSLlAthru
Core
Array
MmSL14A
MmSLlBthru
MmSL14B
MmSTROB A6AMA6A1
MmSTRPl
|
MmSTRP2
-L
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure
10-46.
Signal
Origin
List
(Sheet
4)
Changed
4
January
1965
10-183
SIGNAL
ORIGIN
MmSTRPS A6AMA6A1
MmSOEO
A6AMA1A1
MmSOEl
MmSOE2
MmSOES
MmSOE4
MmSOES
MmSOE6
MmSOE7
MmSOIO
MmSOIl
MmSOI2
MmSOIS
MmSOI4
MmSOIS
MmSOIG
MmSOI7
MmSlEO
MmSlEl
MmSlE2
MmSlES
MmSlE4
MmSlES
MmSlE6
MmSlE7
MmSlIO
MmSlIl
MmSlI2
MmSlIS
MmSlI4
MmSlIS
MmSlK
MmSin
J
MmTCV
A6AMA6A1
MOSYN
A1A16-A
MOSYNV
A5A6-A
M1SYNC
A1A16-B
M1SYNCV
A5A5-A
M2SYNC
A1A16-A
M2SYNCV
A5A6-A
M3SYNC
A1A16-B
M3SYNCV
A5A5-A
M4SYNC
A1A16-A
M4SYNCV
A5A6-A
M5SYNC
A1A16-B
M5SYNCV
A5A5-A
SIGNAL
ORIGIN
M6SYNC
A1A16-A
M6SYNCV
A5A6-A
M7SYNC
A1A16-B
M7SYNCV
A5A5-A
NU
A1A5-A
NUN —
1
L_
OC
A1A14-B
OCN
|
OP1
A1A12-A
OP1N
1
OP1V A4A5-B
OP1VN
|
l_
OP2
A1A12-A
OP2N
|
1
OP2V
A4A5-B
OP2VN
|
_
OPS
A1A12-A
OP3N
|
1
OP3V A4A5-B
OP3VN
_|
_
OP4
A1A12-A
OP4N
|
OP4V A4A6-B
OP4VN
_|
l_
P
A4A12-B
PA
A1A13-B
PAD
A1A20-B
PADN
|
L_
PAE1 A1A17-A
PAE2
PAE3
PAE4
PAE5
PAE6N
1
PAN
A1A13-B
PAO1
A1A17-A
PAO2
PAO3
PAO4
PAO5
PAO6
PAO7
PAO8
—
SIGNAL
ORIGIN
PAO9 A1A17-A
PAO10
PAO11
PAO12
J
PAR
A1A11-B
PARN
1
PARV A5A15-A
PAV
A4A8-A
PAVN
A4A8-B
PB
A1A13-B
PBE1 A1A17-B
PBE2
PBE3
PBE4
PBE5
PBE6N
|
PEN ^
A1A13-B
PBO1 A1A17-B
PBO2
PBO3
PBO4
PBO5
PBO6
PBO7
PBO8
PBO9
PBO10
PBO11
PB012
_J
PBV
A4A8-A
PBVN
A4A8-B
PC
A1A13-B
PCN
|
PCV
A4A8-A
PCVN
A4A8-B
FDD
A1A11-B
PDDN
_J
PIO
A1A12-B
PIOV A4A5-A
PN
A4A12-B
POD
A1A11-B
PGDN
1
PP
A4A12-B
PPN
|
PQR
A1A5-A
PQRN
1
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure
10-46.
Signal
Origin
List
(Sheet
5)
10-184
Changed
4
January
1965
SIGNAL
ORIGIN
PR
A1A5-A
PRN 1
PRO
A1A9-B
PRON
|
PROV
A4A9-B
PROVN
1
PR1
A1A9-B
PR1N
1
PR2
PR2N
|
PR2V A4A9-B
PR2VN
1
PR3
A1A9-B
PR3N
PR4
PR4N
PR5
PR5N
PR6
PR6N
PR7
PR7N
PR8
PR8N
PR9
PR9N
PR10
PR10N
PWR
RET
External
PIN
A1A7-A
P1VN A4A13-B
P2N
A1A7-A
P2VN
A4A13-B
P3N
A1A7-A
P3VN A4A13-A
Q
A4A12-A
QN 1
QP
A4A12-B
QPN
|
Ql
A1A9-A
Q1N
Q2
Q2N
Q3
Q3N
_
SIGNAL
ORIGIN
Q4 A1A
Q4N
Q5
Q5N
Q6
Q6N
Q7
Q7N
Q8
Q8D A1A
Q8DN
|
9-A
10-A
L
Q8N
A1A9-A
Q8V
A4A9-A
Q9
A1A7-A
Q9N
_
l_
R
A4A12-A
RAC
A1A10-A
RACN
1
RD
A1A15-A
RDM
A1A15-B
RDMN
[
RDMV
A5A6-B
RDMVN
1
RDV I
RECN
A1A15-B
RED
A1A14-B
REDN
REI
REIN
|
RN
A4A12-A
RP 1
RPN
|
RUN
A1A15-A
RUNN
|
RUNV
A5A5^B
RUNVN
|
RV
A4A1T-A
RVN
_|
S
A4A12-A
SAPO A1A12-B
SBRX
A1A11-B
SBRXN
|
SBRXV A5A13-A
SBRY
A1A11-B
SIGNAL
ORIGIN
SBRYN
A1A11-B
SBRYV
A5A13-A
SBRZ
A1A11-B
SBRZN
|
SBRZV
A5A15-A
SGI
A1A8-B
SG1N
1
SG2
SG2N
1
SHF
A1A12-B
SHFV
A4A5-A
SIG
RET
External
SINK
A1A15-A
SENKN
SLD
SLDN
_|
SMDN
A1A8-A
SN
A4A12-A
SRTR A1A11-A
SRTRN
|
SS
AfAT8~-A
SSF
A1A12-B
SSFSN
|
SSN
A1A18-A
STMD
1
STMDN
1
STO
A1A11-B
STON
A1A12-B
STOVN
A4A5-A
STP
A1A5-A
STPN
|
SV
A4AT2~-B
SVN
|
SYLC1
A1A15-A
SYLC1N
|
SYLC1V
ASAfPB
SYLON
A1A15-A
SYLOVN
A5A5-B
SYL1N
A1A15-A
SYL1VN
A5A6-B
SYNC
A1A15-B
SYNCN
|
S4
A1A19-A
S4N
_L
TA
A1A19-B
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure
10-46.
Signal
Origin
List
(Sheet
6)
10-185
SIGNAL
ORIGIN
TAN
A1A19-B
TBC
A1A13-B
TBCN
1
TBCV A4A8-B
TBR
A1A11-B
TBRN
_|
TBRV A5A13-A
TER
External
TFD
A1A8-B
TFDN
I
TFDV A4A14-A
TFDVN
_]
THERM1
A4A11-B
THERM2
_J
TIME
A1A15-B
TIMEN
TLC
TLCN
TLCV A5A5-B
TM
A1A7-A
TMDN
A1A8-A
TMN
A1A7-A
TMV
A4A14-B
TMVN
1 .
TR1
A1A18-A
TR1D
1
TR1DN
TR1N
-L-
TR1V A5A14-B
TR2
A1A18-A
TR2N
—
1—
TR2V A5A14-B
TR3
A1A18-A
TR3D
1
TR3DN
TR3N
-L-
TR3V A5A14-B
TR4
A1A18-B
TR4N
1
TR4V A5A14-B
TR5
A1A18-B
TR5N
1
TR5V A5A14-B
TR6
A1A18-B
TR6D
1
TR6DN
J_
SIGNAL
ORIGIN
TR6N
A1A18-B
TR6V A5A14-B
TR7
A1A18-B
TR7N
1
TR7V
A5A14-A
TR8
A1A18-B
TR8N
1
TR8V A5A14-A
TR9
A1A18-B
TR9D
1
TR9DN
TR9N
—
L
TR9V
A5A14-A
TRIO
A1A11-A
TR10N
1
TR10V A5A14-A
TR11 A1A11-A
TR11N
_J_
TR11V A5A14-A
TR12 A1A11-A
TR12D
1
TR12DN
TR12N
—
L-
TR12V
A5A15-A
TR13
A1A11-A
TR13N
|
TR13V A5A14-A
TRS
A1A11-A
TRSN
I
TRSV A5A15-A
TRSVN
|
TTL
A1A12-B
TTLN
I
TTLV A4A6-B
TTT
A1A11-B
UACCO
A1A10-B
UTR 1
UTRV
A4A7-B
VOY
A1A7-A
VOYN
1
VOYV
A4A13-B
VOYVN
__[_
VI
External
V3 1
SIGNAL
ORIGIN
V4MOD1
External
V4MOD2
V4MOD3
V4MOD4
V4MOD5
V4MOD6
V4MOD7
V5
V5MOD1
V5MOD2
V5MOD3
V5MOD4
V5MOD5
V5MOD6
V5MOD7
V20
J
WDA
A1A3-A
WF
WN
Wl
W2
W3
W4
W5
W6
W7
W8
J
XDA
A1A3-A
XF
XN
XI
X2
X3
X4
X5
X6
X7
X8
J
YDA
A1A3-B
YF 1
YN
Yl
J_
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure
10-46.
Signal
Origin
List
(Sheet
7)
10-186
Changed
4
January
1965
SIGNAL ORIGIN
Y2
A1A3-B
Y3
Y4
Y5
Y6
Y7
Y8
_
SIGNAL ORIGIN
ZDA
A1A3-B
ZDHN
A1A8-A
ZDLN
1
ZER
A1A10-A
ZERN
J_
ZF
A1A3-B
ZN 1
1
SIGNAL ORIGIN
Zl
A1A3-B
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Note:
Origins
of TMR
signals
are
shown
for
channel
1
only.
Figure 10-46. Signal Origin List (Sheet
8)
10-187
Refer
to
Back
Panel
Lists
for the
Saturn
V
Launch Vehicle Digital Computer.
(Supplied under
separate
cover.)
Figure
10-47. Interconnection
Al
Back Panel,
List
for
LVDC
10-188
Refer
to
Back
3?anel
Lists
for,the Saturn
V
Launch Vehicle Digit'al.Computer..
!
(Supplied
under
separate cover.)
Figure 10-48.
Interconnection
A4sBack
Panel,, List
for.
LVDC
.,
10-189
Figure
10-
49.
10-
190
Refer
to
Back
Panel
Lists
for
the
Saturn
V
Launch Vehicle Digital Computer.
(Supplied
under
separate
cover.
)
~ntercomection
A5
Back
Panel,
list
for
LVDC
A6J3
A4E2
A4J1
A6J2
A6J1
A6J4
A4E1
Figure 10-50. Computer, Rear
View
Changed
4
January 1965
10-191
i
§
2
3
ii
ii
9
ii
ilj
f
ij
II
N
ji
(SI —
BU««
Ou*«
1
O
1
ii,
ii
"
1
:":
6
||
li
o
II
ii
K;
i
ID
•a
CO
§
U
cf
.2
•a
o
ia
(U
S
.a
m
I-H
rt
.3
a
0)
H
1
0
0)
10-192
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SHEET
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The
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following
address:
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Department
913
IBM
Corporation
Space Guidance Center
Owego,
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