Sec7 VHF2_High Power VHF2 High

Sec7_VHF2_High Power Sec7_VHF2_High Power

User Manual: Sec7-VHF2_High Power

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Commercial Series
CM Radios
VHF2 (146-174MHz) High Power
Service Information

Issue: October 2004

Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royaltyfree license to use that arises by operation of law in the sale of a product.

iii

Table of Contents
Chapter 1

MODEL CHART AND TECHNICAL SPECIFICATIONS

1.0 CM140/CM160 Model Chart ................................................................................1-1
2.0 Technical Specifications ......................................................................................1-2

Chapter 2

THEORY OF OPERATION

1.0 Introduction ..........................................................................................................2-1
2.0 VHF (146-174MHz) Receiver..............................................................................2-1
2.1 Receiver Front-End .......................................................................................2-1
2.2 Receiver Back-End.........................................................................................2-2
3.0 VHF (146-174MHz) Transmitter Power Amplifier ...............................................2-2
3.1 First Power Controller Stage...........................................................................2-2
3.2 Power Controlled Driver Stage .......................................................................2-3
3.3 Final Stage......................................................................................................2-3
3.4 Directional Coupler.........................................................................................2-3
3.5 Antenna Switch...............................................................................................2-3
3.6 Harmonic Filter ...............................................................................................2-4
3.7 Power Control.................................................................................................2-4
4.0 VHF (146-174MHz) Frequency Synthesis ..........................................................2-4
4.1 Reference Oscillator .......................................................................................2-4
4.2 Fractional-N Synthesizer ................................................................................2-5
4.3 Voltage Controlled Oscillator (VCO) ...............................................................2-6
4.4 Synthesizer Operation ....................................................................................2-7
5.0 Controller Theory of Operation ............................................................................2-8
5.1 Radio Power Distribution ................................................................................2-8
5.2 Protection Devices........................................................................................ 2-10
5.3 Automatic On/Off ..........................................................................................2-10
5.4 Microprocessor Clock Synthesiser ...............................................................2-11
5.5 Serial Peripheral Interface (SPI)...................................................................2-12
5.6 SBEP Serial Interface................................................................................... 2-12
5.7 General Purpose I/O.....................................................................................2-12
5.8 Normal Microprocessor Operation................................................................2-13
5.9 Static Random Access Memory....................................................................2-14
6.0 Control Board Audio and Signalling Circuits ......................................................2-14
6.1 Audio Signalling Filter IC and Compander (ASFIC CMP) ............................2-14
7.0 Transmit Audio Circuits......................................................................................2-15
7.1 Microphone Input Path .................................................................................2-15
7.2 PTT Sensing and TX Audio Processing ....................................................... 2-16

8.0 Transmit Signalling Circuits ............................................................................... 2-17
8.1 Sub-Audio Data (PL/DPL) ............................................................................ 2-17
8.2 High Speed Data .......................................................................................... 2-18
8.3 Dual Tone Multiple Frequency (DTMF) Data ............................................... 2-18
9.0 Receive Audio Circuits....................................................................................... 2-19
9.1 Squelch Detect ............................................................................................. 2-19
9.2 Audio Processing and Digital Volume Control.............................................. 2-20
9.3 Audio Amplification Speaker (+) Speaker (-) ................................................ 2-20
9.4 Handset Audio.............................................................................................. 2-21
9.5 Filtered Audio and Flat Audio ....................................................................... 2-21
10.0 Receive Audio Circuits ..................................................................................... 2-21
10.1 Sub-Audio Data (PL/DPL) and High Speed Data Decoder .......................... 2-21
10.2 Alert Tone Circuits........................................................................................ 2-22

Chapter 3

TROUBLESHOOTING CHARTS

1.0 Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)................................ 3-2
1.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2) ................................ 3-3
2.0 Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 3) ........................ 3-4
2.1 Troubleshooting Flow Chart for 45W Transmitter (Sheet 2 of 3)................... 3-5
2.2 Troubleshooting Flow Chart for 45W Transmitter (Sheet 3 of 3)................... 3-6
3.0 Troubleshooting Flow Chart for Synthesizer ....................................................... 3-7
4.0 Troubleshooting Flow Chart for VCO................................................................... 3-8
5.0 Troubleshooting Flow Chart for DC Supply (Sheet 1 of 2) .................................. 3-9
5.1 Troubleshooting Flow Chart for DC Supply (Sheet 2 of 2) ........................... 3-10

Chapter 4

VHF PCB/SCHEMATICS/PARTS LISTS

1.0 Allocation of Schematics and Circuit Boards ....................................................... 4-1
1.1 VHF2 25-45W and Controller Circuits ............................................................ 4-1
2.0 VHF2 25-45W PCB 8486487Z03-B / Schematics ............................................... 4-3
2.1 VHF2 25-45W PCB 8486487Z03-B Parts List ............................................. 4-19
3.0 VHF2 25-45W PCB 8486487Z04 / Schematics................................................. 4-29
3.1 VHF2 25-45W PCB 8486487Z04 Parts List ................................................. 4-45

Chapter 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0

CM140/CM160 Model Chart

CM Series, VHF2, 146-174 MHz
Model
MDM50KQC9AA2
MDM50KQF9AA2

Description
CM140 146-174 MHz, 45W, 8CH, BNC
CM160 146-174 MHz, 45W, 64CH, BNC

Item
X

Description

PMUD1848_

CM140 Super Tanapa VHF2, 45W, 8CH, BNC

PMUD1894_

CM160 Super Tanapa VHF2, 45W, 64CH, BNC

PMUD1885_

CM140 Tanapa VHF2, 45W, 8CH, BNC

PMUD1887_

CM160 Tanapa VHF2, 45W, 64CH, BNC

FCN6288_

Control Head

FCN5523_

Control Head

PMUD1885_S

CM140 UHF2 U/C BNC Service Board

PMUD1887_S

CM160 UHF2 U/C BNC Service Board

RMN5018

Mag One Microphone

6866546D02_

RTTE Leaflet

6866537D37_

Safety Leaflet

GLN7324_

Low Profile Trunnion

X
X
X
X
X
X

x = Indicates one of each is required.

1-2

2.0

MODEL CHART AND TECHNICAL SPECIFICATIONS

Technical Specifications
Data is specified for +25°C unless otherwise stated.
General
Specification
Frequency Range:
Frequency Stability
(-30°C to +60°C, 25°C Ref.)
Channel Capacity:

Channel Spacing:

VHF2
146-174 MHz
±2 PPM

CM140 - 8
CM160 - 64
12.5/20/25 kHz

Power Output:

25-45W

Power Supply:

13.2Vdc (10.8 - 15.6 Vdc) negative vehicle ground

Dimensions (L X W X H)
Weight:
Low power (1-25W)

118mm X 169mm X 44mm

1.02 Kg

Operating Temperature

-30 to 60 o C

Storage temperature

-40 to 80o C

Shock and Vibration

Meets MIL-STD 810-C,D&E and TIA/EIA 603

Dust

Meets MIL-STD 810-C,D&E and TIA/EIA 603

Humidity

Meets MIL-STD 810-C,D&E and TIA/EIA 603

Technical Specifications

1-3

Transmitter
Specification

VHF2

Frequency Stability:

+/- 2.5ppm

Modulation Limiting:

±2.5 kHz @ 12.5 kHz
±4.0 kHz @ 20 kHz
±5.0 kHz @ 20/25 kHz

Current Drain Transmit:

7A (25W)

FM Hum and Noise:

-40 dB@12.5 kHz
-45 dB@ 20/25 kHz

Conducted/Radiated
Emissions:

-36 dBm < 1 GHz
-30 dBm > 1 GHz

Adjacent Channel Power

-60dB @12.5,
-70dB @ 20/25kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Audio Distortion:
@ 1000 Hz, 60%
Rated Maximum Deviation:

3% Typical

Receiver
Specification
Sensitivity (12dBSINAD): (ETS)
Intermodulation : (ETS)
Adjacent Channel
Selectivity: (ETS)
Spurious Rejection: (ETS)
Rated Audio: (ETS) (Extended audio with 4 Ohm
speaker)
Audio Distortion @ Rated Audio:

VHF2
0.35µV (12.5kHz) 0.30µV (25kHz) Typical
>65dB
75 dB @ 25 kHz
65 dB @ 12.5 kHz
75 dB
4W Internal , 13W External
3% Typical

Hum and Noise:

-40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Conducted Spurious
Emission per FCC Part 15:

-57 dBm <1 GHz
-47 dBm >1 GHz

*Availability subject to the laws and regulations of individual countries.

1-4

MODEL CHART AND TECHNICAL SPECIFICATIONS

Chapter 2
THEORY OF OPERATION
1.0

Introduction
This Chapter provides a detailed theory of operation for the VHF circuits in the radio. Details of the
theory of operation and trouble shooting for the the associated Controller circuits are included in this
Section of the manual.

2.0

VHF (146-174MHz) Receiver

2.1

Receiver Front-End
The received signal is applied to the radio’s antenna input connector and routed through the
harmonic filter and antenna switch. The insertion loss of the harmonic filter/antenna switch is less
than 1 dB. The signal is routed to the first filter (4-pole), which has an insertion loss of 2 dB typically.
The output of the filter is matched to the base of the LNA (Q303) that provides a 16 dB gain and a
noise figure of better than 2 dB. Current source Q301 is used to maintain the collector current of
Q303. Diode CR301 protects Q303 by clamping excessive input signals. Q303 output is applied to
the second filter (3-pole) which has an insertion loss of 1.5 dB. In Distance mode, Q304 turns on and
causes D305 to conduct, thus bypassing C322 and R337. In Local mode, the signal is routed
through C322 and R337, thus inserting 7 dB attenuation. Since the attenuator is located after the RF
amplifier, the receiver sensitivity is reduced only by 6 dB, while the overall third order input intercept
is raised.
The first mixer is a passive, double-balanced type, consisting of T300, T301 and U302. This mixer
provides all of the necessary rejection of the half-IF spurious response. High-side injection at +15
dBm is delivered to the first mixer. The mixer output is then connected to a duplex network which
matches its output to the XTAL filter input (FL300) at the IF frequency of 44.85 MHz. The duplex
network terminates into a 50 ohm resistor (R340) at all other frequencies.

Antenna
Front Filter

12.5kHzFilter 12.5kHzFilter
LNA

Second Filter

Mixer

4- Pole
Xtal Filter

IF Amp

First LO

25kHzFilter

IFIC

2nd LO Xtal Osc

Phase Shift
Element
Controller

Figure 2-1 VHF Receiver Block Diagram

2-2

THEORY OF OPERATION

2.2

Receiver Back End
The IF signal from the crystal filter enters the IF amplifier which provides 20 dB of gain and feeds
the IF IC at pin 1. The first IF signal at 44.85 MHz mixes with the second local oscillator (LO) at
44.395 MHz to produce the second IF at 455 kHz. The second LO uses the external crystal Y301.
The second IF signal is amplified and filtered by two external ceramic filters (FL303/FL302 for
12.5KHz channel spacing and FL304/FL301 for 25KHz channel spacing). The IF IC demodulates
the signal by means of a quadrature detector and feeds the detected audio (via pin 7) to the audio
processing circuits. At IF IC pin 5, an RSSI signal is available with a dynamic range of 70 dB.

3.0

VHF Transmitter Power Amplifier (146-174 MHz)
The radio’s 45W PA is a three-stage amplifier used to amplify the output from the TX_INJ to the
antenna port. All three stages utilize LDMOS technology. The gain of the first stage (U101) is
adjustable and is controlled by pin 7 of U103-2 via U103-3 and U102-1. It is followed by an LDMOS
driver Q105 and final stage Q100.

Antenna
Pin Diode
Antenna
Switch

From VCO (TX_INJ)
Controlled
Stage

PA-Final
Stage

Driver

Coupler

Bias

Harmonic
Filter
RF Jack

Forward

A S FI C _C M P
SPI BUS

PA
PWR
SET
L oo p
C ont r ol le r
U 103 - 2

Temperature
Sense

Figure 2-2 VHF Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted.Two screws with Belleville washers provide
direct pressure ensuring good thermal contact between both the driver and final stage, and the
chassis.

3.1

First Power Controller Stage
The first stage (U101) is a 20dB gain integrated circuit containing two LDMOS FET amplifier stages.
It amplifies the RF signal from the VCO (TX_INJ). The output power of stage U101 is controlled by a
DC voltage applied to pin 1 from the op-amp U103-3, pin 8. The control voltage simultaneously
varies the bias of two FET stages within U101. This biasing point determines the overall gain of
U101 and therefore its output drive level to Q105, which in turn controls the output power of the PA.

VHF Transmitter Power Amplifier (146-174 MHz)

2-3

Op-amp U103-3 monitors the drain current of U101 via resistor R122 and adjusts the bias voltage of
U101.
In receive mode, the DC voltage from RX_EN line turns on Q101, which in turn switches off the
biasing voltage to U101.

3.2

Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the V_cntrl_driver which is set to provide 100-150mA of quiescent current by the factory,
and fed to the gate of Q105 via the resistive network.
The V_cntrl_driver is directly controlled by the ASFIC CMP. In receive mode, the ASFIC CMP
(U504) sets V_cntrl_driver to 0V (DACR pin 5).

3.3

Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134,
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage
input, B+, via L117 and L115.
A matching network consisting of C1004-5, C1007-9, C1096, C1021, C1013, C1019, L116: and two
striplines, transforms the impedance to 50 ohms and feeds the directional coupler.

3.4

Bi-Directional Coupler
The bi-directional Coupler is a microstrip printed circuit, which couples a small amount of the
forward and reverse power of the RF power from Q100.The coupled signal is rectified to an output
power which is proportional to the DC voltage rectified by diode D105; and the resulting DC voltage
is routed to the power control section to ensure that the forward power out of the radio is held to a
constant value.

3.5

Antenna Switch
The antenna switch utilizes the existing dc feed (B+) to the last stage device (Q100). The basic
operation is to have both PIN diodes (D103, D104) turned on during key-up by forward biasing
them. This is achieved by pulling down the voltage at the cathode end of D104 to around 12.4V
(0.7V drop across each diode). The current through the diodes needs to be set around 100 mA to
fully open the transmit path through resistor R108. Q106 is a current source controlled by Q103
which is turned on in Tx mode by TX_EN. VR102 ensures that the voltage at resistor R107 never
exceeds 5.6V.

2-4

3.6

THEORY OF OPERATION

Harmonic Filter
Inductors L111, L112, L124 and L113 along with capacitors C11321, C1022, C1020, C1137, C1018
and C1017 form a low-pass filter to attenuate harmonic energy coming from the transmitter.
Resistor R150 drains any electrostatic charges that might otherwise build up on the antenna. The
harmonic filter also prevents high level RF signals above the receiver passband from reaching the
receiver circuits to improve spurious response rejection.

3.7

Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error
output current is then routed to an integrator, and converted into the control voltage. This voltage
controls the bias of the pre-driver (U101) stage. The output power level is set by way of a DAC,
PWR_SET, in the audio processing IC (U504), which acts at the forward power control loop
reference.
The sampled reflected power is rectified by diode D107. The resulting DC voltage is amplified by an
operational amplifier U100 and routed to the summing junction. This detector protects the final stage
Q100 from reflected power by increasing the error current. The temperature sensor protects the
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage
below 5.6V and eliminates the DC current from the 9.3 regulator U501.
A local loop for the Pre Driver (U101) is used in order to stabilize the current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by
applying ground to the Pre Driver U101.

4.0

VHF (146-174MHz) Frequency Synthesis
The synthesizer consists of a reference oscillator (Y201), low voltage Fractional-N (LVFRAC-N)
synthesizer (U200), and a voltage controlled oscillator (VCO) (U201).

4.1

Reference Oscillator
The reference oscillator is a crystal (Y201) controlled Colpitts oscillator and has a frequency of
16.8MHz. The oscillator transistor and start-up circuit are located in the LVFRAC-N (U200) while the
oscillator feedback capacitors, crystal, and tuning varactors are external. An analog-to-digital (A/D)
converter internal to the LVFRAC-N (U200) and controlled by the microprocessor via SPI sets the
voltage at the warp output of U200 pin 25. This sets the frequency of the oscillator. Consequently,
the output of the crystal Y201 is applied to U200 pin 23.
The method of temperature compensation is to apply an inverse Bechmann voltage curve, which
matches the crystal’s Bechmann curve to a varactor that constantly shifts the oscillator back on
frequency. The crystal vendor characterizes the crystal over a specified temperature range and
codes this information into a bar code that is printed on the crystal package. In production, this
crystal code is read via a 2-dimensional bar code reader and the parameters are saved.

VHF (146-174MHz) Frequency Synthesis

2-5

This oscillator is temperature compensated to an accuracy of +/-2.5 PPM from -30 to 60 degrees C.
The temperature compensation scheme is implemented by an algorithm that uses five crystal
parameters (four characterize the inverse Bechmann voltage curve and one for frequency accuracy
of the reference oscillator at 25 degrees C). This algorithm is implemented by the LVFRAC-N (U200)
at the power up of the radio.

4.2

Fractional-N Synthesizer
The LVFRAC-N U200 consists of a pre-scaler, programmable loop divider, control divider logic,
phase detector, charge pump, A/D converter for low frequency digital modulation, balanced
attenuator used to balance the high and low frequency analog modulation, 13V positive voltage
multiplier, serial interface for control, and a super filter for the regulated 5 volts.

DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)

7
8
9
10
13, 30

+5V (U503 PIN 1)
+5V (U503 PIN 1)

5, 20, 34, 36
23

REFERENCE
OSCILLATOR

FREFOUT

CLK

GND

CEX
MODIN

LOCK (U403 PIN 56)

VCC, DC5V

43
45

VDD, DC5V

MODOUT

XTAL1

U200

XTAL2

FRACTIONAL-N
SYNTHESIZER

WARP

PREIN
VCP
VMULT2
14

AUX4 3
1
AUX2
AUX3 2

LOW VOLTAGE

SFOUT

FREF (U504 PIN 34)

6, 22, 33, 44

IOUT
IADAPT

47
VOLTAGE
MULTIPLIER

LOCK
DATA

STEERING
LINE
LOOP
FILTER
VCO Bias

LO RF INJECTION

TRB

VOLTAGE
28 FILTERED 5V CONTROLLED
OSCILLATOR

BIAS1
40
VMULT1

TX RF INJECTION
(1ST STAGE OF PA)

AUX1 BIAS2
39

BWSELECT

To IF
Section

PRESCALER IN

Figure 2-3 VHF Synthesizer Block Diagram

A voltage of 5V applied to the super filter input (U200, pin 30) supplies an output voltage of 4.5Vdc
(VSF) at U200, pin 28. This supplies 4.5 V to the VCO Buffer IC U201.
To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP
(U200, pin 47) while using a low voltage 3.3Vdc supply, a 13V positive voltage multiplier is used
(D200, D201, and capacitors C2024, 2025, 2026, 2055, 2027, 2001).
Output lock (U200, pin 4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. A 16.8 MHz reference frequency is provided at U200, pin
19.

2-6

THEORY OF OPERATION

4.3

Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U201), the TX and
RX tank circuits, the external RX amplifier, and the modulation circuitry.
AUX3 (U200 Pin 2)

U200 Pin 32
Prescaler Out

TRB IN
Pin 20
Rx-SW

Pin7

Tx-SW

Pin13

Pin 19

Pin 12

TX/RX/BS
Switching Network
LO RF INJECTION

(U200 Pin 28)

Vcc-Superfilter
Pin3

Presc

U201
VCOBIC

Q200
Buffer

Low Pass
Filter

Collector/RF in

Steer Line
Voltage
(VCTRL)

Pin4
RX

RX
RX Tank

RX VCO
Circuit

Rx
Active Bias

Pin5

Pin8
(U200 Pin28)
Pin14

Pin6

TX
TX Tank

TX VCO
Circuit

Tx
Active Bias

Pin16

Pin10

VCC Buffers
TX RF Injection
Attenuator

Pin15

Vsens
Circuit

Pin18
Vcc-Logic

Pin2

Pin1

Rx-I adjust

Tx-I adjust

Pins 9,11,17

(U200 Pin 28)

Figure 2-4 VHF VCO Block Diagram

The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32
(PREIN).
A steering line voltage between 3.0V and 10.0V at varactor D204 tunes the TX VCO through the
frequency range of 146-174MHz, and at D203 tunes the RX VCO through the frequency range of
190-219MHz.
The external RX amplifier is used to increase the output from U201, pin 9 from 3-4 dBm to the
required 15dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.

VHF (146-174MHz) Frequency Synthesis

4.4

2-7

Synthesizer Operation
The synthesizer consists of a low voltage FRAC-N IC (LVFRAC-N), reference oscillator, charge
pump circuits, loop filter circuit, and DC supply. The output signal (PRESC_OUT) of the VCOBIC
(U201, pin 12) is fed to the PREIN, pin 32 of U200 via a low pass filter which attenuates harmonics
and provides a correct input level to the LVFRAC-N in order to close the synthesizer loop.
The pre-scaler in the synthesizer (U200) is a dual modulus pre-scaler with selectable divider ratios.
The divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs
via the SPI. The output of the pre-scaler is applied to the loop divider. The output of the loop divider
is connected to the phase detector, which compares the loop divider’s output signal with the
reference signal. The reference signal is generated by dividing down the signal of the reference
oscillator (Y201).
The output signal of the phase detector is a pulsed dc signal that is routed to the charge pump. The
charge pump outputs a current from U200, pin 43 (IOUT). The loop filter (consisting of R224, R217,
R234, C2074, C2075, C2077, C2078, C2079, C2080, C2028, and L205) transforms this current into
a voltage that is applied the varactor diodes D203 and D204 for RX and TX respectively. The output
frequency is determined by this control voltage. The current can be set to a value fixed in the
LVFRAC-N or to a value determined by the currents flowing into BIAS 1 (U200, pin 40) or BIAS 2
(U200, pin 39). The currents are set by the value of R200 or R206 respectively. The selection of the
three different bias sources is done by software programming.
To modulate the synthesizer loop, a two-spot modulation method is utilized via the MODIN (U200,
pin 10) input of the LVFRAC-N. The audio signal is applied to both the A/D converter (low frequency
path) and the balance attenuator (high frequency path). The A/D converter converts the low
frequency analog modulating signal into a digital code which is applied to the loop divider, thereby
causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s deviation
sensitivity to high frequency modulating signals. The output of the balance attenuator is presented
at the MODOUT port of the LVFRAC-N (U200,pin 41) and connected to the VCO modulation
varactor D205.

2-8

5.0

THEORY OF OPERATION

Controller Theory of Operation
This section provides a detailed theory of operation for the radio and its components. The main
radio is a single-board design, consisting of the transmitter, receiver, and controller circuits. A
control head is connected by an extension cable. The control head contains LED indicators, a
microphone connector, buttons, and speaker.
In addition to the power cable and antenna cable, an accessory cable can be attached to a
connector on the rear of the radio. The accessory cable enables you to connect accessories to the
radio, such as an external speaker, emergency switch, foot-operated PTT, and ignition sensing, etc.

External
Microphone

To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer

Audio/Signaling
Architecture

Disc Audio

ASFIC_CMP

Internal
Microphone
External
Speaker

Audio
PA
Internal
Speaker

µP Clock

SPI

To RF Section
Digital
Architecture

SCI to
Accessory &
Control Head
Connector

RAM
EEPROM

3.3V
Regulator

HC11FL0

FLASH

Figure 2-5 Controller Block Diagram

5.1

Radio Power Distribution
Voltage distribution is provided by five separate devices:
■

U514 P-cH FET - Batt + (Ext_SWB+)

■

U501 LM2941T - 9.3V

■

U503 LP2951CM - 5V

■

U508 MC 33269DTRK - 3.3V

■

U510 LP2986ILDX - 3.3V Digital

Handset

Controller Theory of Operation

2-9

The DC voltage applied to connector P2 supplies power directly to the following circuitry:
■

Electronic on/off control

■

RF power amplifier

■

12 volts P-cH FET -U514

■

9.3 volt regulator

■

Audio PA

Ignition

B+

Control Head
RF_PA
Audio_PA

Auto
On/Off
Switch
Control

Mic Connector

Ferrite Bit

Keypad

Mic Bias
9V, 5mA

Filt_B+
Antenna Switch
Power Control

500mA

FET
P-CH
On/Off
Control

SW_Filt_B+

Status LEDs

7_Seg

7_Seg
DOT

Bed
to
7-Seg

Back
light

Shift
Reg

Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp
9.3V
65mA

11-16.6V
0.9A
U501
9.3V Regulator

0.85A

Reset

9.3V
45mA

On/Off
Control

U503
5V RF Regulator
500mA
Rx_Amp
PA_Pre-driver
PA Driver

3.2V
72mA

45mA
LVFRAC_N
IF_Amp

9.3V
75mA

9.3V
162mA

U508
3.3V RF Reg
50mA

25mA
ASFIC_CMP
IFIC
RX Cct

U510
3.3V D Reg
90mA
micro P
RAM
Flash
EEPROM

Figure 2-6 DC Power Distribution Block Diagram
Regulator U501 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry
and power control circuitry. Input and output capacitors are used to reduce high frequency noise.
Resistors R5001 / R5081 set the output voltage of the regulator. This regulator output is
electronically enabled by a 0 volt signal on pin 2. Q502, Q505 and R5038 are used to disable the
regulator when the radio is turned off.
Voltage regulator U510 provides 3.3 volts for the digital circuitry. Operating voltage is from the
regulated 9.3V supply. Input and output capacitors are used to reduce high frequency noise and
provide proper operation during battery transients. U510 provides a reset output that goes to 0 volts
if the regulator output goes below 3.1 volts. This is used to reset the controller to prevent improper
operation.
Voltage regulator U508 provides 3.3V for the RF circuits and ASFIC_CMP. Input and output
capacitors are used to reduce the high frequency noise and provide proper operation during battery
transients.

2-10

THEORY OF OPERATION

Voltage regulator U503 provides 5V for the RF circuits. Input and output capacitors are used to
reduce the high frequency noise and provide proper operation during battery transients.
VSTBY is used only for CM360 5-tone radios.
The voltage VSTBY, which is derived directly from the supply voltage by components R5103 and
VR502, is used to buffer the internal RAM. Capacitor C5120 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Dual diode D501 prevents
radio circuitry from discharging this capacitor. When the supply voltage is applied to the radio,
C5120 is charged via R5103 and D501.

5.2

Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.

5.3

Automatic On/Off
The radio can be switched ON in any one of the following three ways:

5.3.1

■

On/Off switch. (No Ignition Mode)

■

Ignition and On/Off switch (Ignition Mode)

■

Emergency

No Ignition Mode
When the radio is connected to the car battery for the first time, Q500 will be in saturation, Q503 will
cut-off, Filt_B+ will pass through R5073, D500, and S5010-pin 6 (On/Off switch). When S5010 is
ON, Filt_B+ will pass through S5010-pin5, D511, R5069, R5037 and base of Q505 and move Q505
into saturation. This pulls U501-pin2 through R5038, D502 to 0.2V and turns On U514 and U501
9.3V regulator which supplies voltage to all other regulators and consequently turns the radio on,
When U504 (ASFIC_CMP) gets 3.3V, GCB2 goes to 3.3V and holds Q505 in saturation, for soft turn
off.

5.3.2

Ignition Mode
When ignition is connected for the first time, it will force high current through Q500 collector, This
will move Q500 out of saturation and consequently Q503 will cut-off. S5010 pin 6 will get ignition
voltage through R601 (for load dump), R610, (R610 & C678 are for ESD protection), VR501,
R5074, and D500. When S5010 is ON, Filt_B+ passes through S5010-pin 5, D511, R5069, R5037
and base of Q505 and inserts Q505 into saturation. This pulls U501-pin 2 through R5038, D502 to
0.2V and turns on U514 and U501 9.3V regulator which supply voltage to all other regulators and
turns the radio on, When U504 (ASFIC_CMP) get 3.3V supply, GCB2 goes to 3.3V and holds Q505
in saturation state to allow soft turn off,
When ignition is off Q500, Q503 will stay at the same state so S5010 pin 6 will get 0V from Ignition,
Q504 goes from Sat to Cut, ONOFF_SENSE goes to 3.3V and it indicates to the radio to soft turn
itself by changing GCB2 to ‘0’ after de registration if necessary.

Controller Theory of Operation

5.3.3

2-11

Emergency Mode
The emergency switch (P1 pin 9), when engaged, grounds the base of Q506 via EMERGENCY
_ACCES_CONN. This switches Q506 to off and consequently resistor R5020 pulls the collector of
Q506 and the base of Q506 to levels above 2 volts. Transistor Q502 switches on and pulls U501
pin2 to ground level, thus turning ON the radio. When the emergency switch is released R5030 pulls
the base of Q506 up to 0.6 volts. This causes the collector of transistor Q506 to go low (0.2V),
thereby switching Q502 to off.
While the radio is switched on, the µP monitors the voltage at the emergency input on the accessory
connector via U403-pin 62. Three different conditions are distinguished: no emergency kit is
connected, emergency kit connected (unpressed), and emergency press.
If no emergency switch is connected or the connection to the emergency switch is broken, the
resistive divider R5030 / R5049 will set the voltage to about 3.14 volts (indicates no emergency kit
found via EMERGENCY_SENSE line). If an emergency switch is connected, a resistor to ground
within the emergency switch will reduce the voltage on EMERGENCY _SENSE line, and indicate to
the µP that the emergency switch is operational. An engaged emergency switch pulls line
EMERGENCY _SENSE line to ground level. Diode VR503 limits the voltage to protect the µP input.
While EMERGENCY _ACCES_CONN is low, the µP starts execution, reads that the emergency
input is active through the voltage level of µP pin 64, and sets the DC POWER ON output of the
ASFIC CMP pin 13 to a logic high. This high will keep Q505 in saturation for soft turn off.

5.4

Microprocessor Clock Synthesiser
The clock source for the µP system is generated by the ASFIC CMP (U504). Upon power-up the
synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the
ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference
input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, has a
programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to
32.769MHz in 1200Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864MHz CMOS square
wave UP CLK (on U504 pin 28) and this is routed to the µP (U403 pin 90). After the µP starts
operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually
7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing. In addition, the clock frequency of the
synthesizer is changed in small amounts if there is a possibility of harmonics of the clock source
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C5025, C5024 and R5033 to set the switching time and jitter
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch
back to its default 3.6864MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz
reference clock it (and the voltage regulators) should be checked first when debugging the system.

2-12

5.5

THEORY OF OPERATION

Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U403-pin100), SPI RECEIVE DATA (MISO) (U403-pin 99), SPI CLK (U0403-pin1)
and chip select lines going to the various IC’s, connected on the SPI PORT (BUS). This BUS is a
synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA
or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT
DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA
is used to send serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a
device to a µP.
In the controller section, there are two IC’s on the SPI BUS, ASFIC CMP (U504 pin 22), and
EEPROM (U400). In the RF sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The
chip select line CSX from U403 pin 2 is shared by the ASFIC CMP and FRAC-N Synthesizer. Each
of these IC’s check the SPI data and when the sent address information matches the IC’s address,
the following data is processed.
When the µP needs to program any of these Is it brings the chip select line CSX to a logic “0” and
then sends the proper data and clock signals. The amount of data sent to the various IC’s are
different; e.g., the ASFIC CMP can receive up to 19 bytes (152 bits). After the data has been sent
the chip select line is returned to logic “1”.

5.6

SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB) or the cable with internal
RIB. This interface connects to the SCI pin via control head connector (J2-pin 17) and to the
accessory connector P1-6 and comprises BUS+. The line is bi-directional, meaning that either the
radio or the RIB can drive the line. The µP sends serial data and it reads serial data via pin 97.
Whenever the µP detects activity on the BUS+ line, it starts communication.

5.7

General Purpose Input/Output
The controller provides six general purpose lines (PROG I/O) available on the accessory connector
P1 to interface to external options. Lines PROG IN 3 and 6 are inputs, PROG OUT 4 is an output
and PROG IN OUT 8, 12 and 14 are bi-directional. The software and the hardware configuration of
the radio model define the function of each port.
■

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this
port via pin 72 and Q412.

■

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is
controlled by the µP (U403 pin 55)

■

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

■

DIG IN OUT 8,12,14 are bi-directional and use the same circuit configuration. Each port uses
an output Q416, Q404, Q405 controlled by µP pins 52, 53, 54. The input ports are read
through µP pins 74, 76, 77; using Q409, Q410, Q411

Controller Theory of Operation

5.8

2-13

Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
During normal operation, the µP (U403) is operating in expanded mode and has access to 3
external memory devices; U400 (EEPROM), U402 (SRAM), U404 (Flash). Also, within the µP there
are 3 Kilobytes of internal RAM, as well as logic to select external memory devices.
The external EEPROM (U400) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information.
The external SRAM (U402) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off.
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U403-38) to chip select U404-pin
30 (FLASH), CSGP2 (U403-pin 41) to chip select U404-pin 20 (SRAM) and PG7_R_W (U403-pin 4)
to select whether to read or to write.
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 3.1 and 3.3V, and the logic low levels
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and
fall times should be <30ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e.g., you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U403-pin 48), MODA LIR (U403-pin 58), MODB VSTPY (U403-pin 57)
and RESET (U403-pin 94) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20ms. In the case of shorted lines you
may also detect the line periodically at an intermediate level, i.e. around 2.5V when two shorted
lines attempt to drive to opposite rails.
The MODA LIR (U403-pin 58) and MODB VSTPY (U403-pin 57) inputs to the µP must be at a logic
“1” for it to start executing correctly. After the µP starts execution it will periodically pulse these lines
to determine the desired operating mode. While the Central Processing Unit (CPU) is running,
MODA LIR is an open-drain CMOS output which goes low whenever the µP begins a new
instruction. An instruction typically requires 2-4 external bus cycles, or memory fetches.
There are eight analog-to-digital coverter ports (A/D) on U403 labelled within the device block as
PEO-PE7. These lines sense the voltage level ranging from 0 to 3.3V of the input line and convert
that level to a number ranging from 0 to 255 which is read by the software to take appropriate action.

2-14

5.9

THEORY OF OPERATION

Static Random Access Memory (SRAM)
The SRAM (U402) contains temporary radio calculations or parameters that can change very
frequently, and which are generated and stored by the software during its normal operation. The
information is lost when the radio is turned off.
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS
signal U402 (which comes from U403-CSGP2) going low. U402 is commonly referred to as the
external RAM as opposed to the internal RAM which is the 3 kilobytes of RAM which is part of the
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the
calculated values which are accessed most often.
Capacitor C402 and C411 serves to filter out any AC noise which may ride on +3.3 V at U402

6.0

Control Board Audio and Signalling Circuits

6.1

Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signaling, PL/DPL/HST/MDC

Squelch detection

µP clock signal generation

The ASFIC CMP is programmable through the SPI BUS (U504 pins-20/21/22), normally receiving
19 bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or
signaling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for the following:
■

GCBO - BW Select

■

GCBI - switches the audio PA On/Off

■

GCB2 - DC Power On switches the voltage regulator (and the radio) on and off

■

GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path

■

GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the
accessory connector.

■

GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path

Transmit Audio Circuits

7.0

2-15

Transmit Audio Circuits

24kOhms

U509

MIC

46
35

FLAT TX
AUDIO

MIC
INT

GCB3
MIC
EXT

U509

36
TX RTN

MUX

CONTROL HEAD
CONNECTOR

EXT MIC

44
TX SND

MUX

AUX
TX
ACCESSORY
CONNECTOR

FILTERS AND
PREEMPHASIS
MIC
ASFIC_CMP
IN
U504 LIMITER
HS SUMMER
SPLATTER
FILTER
LS SUMMER

GCB5

FLAT TX
AUDIO MUTE

VCO
ATN
ATTENUATOR

MOD IN
40

TO
RF
SECTION
(SYNTHESIZER)

Figure 2-7 Transmit Audio Paths

7.1

Microphone Input Path
The radio supports 2 distinct microphone paths known as internal (from control head J2-15) and
external mic (from accessory connector P1-2) and an auxiliary path (FLAT TX AUDIO, from
accessory connector P1-5). The microphones used for the radio require a DC biasing voltage
provided by a resistive network.
The two microphone audio input paths enter the ASFIC CMP at U504-pin 48 (external mic) and
U504-pin 46 (internal mic). The microphone is plugged into the radio control head and connected to
the audio DC via J2-pin 15. The signal is then routed via C5045 to MUX U509 that select between
two paths with different gain to support Low Cost Mic (Mic with out amplifier in it) and Standard Mic.

7.1.1

Low Cost Microphone
Hook Pin is shorted to Pin 1(9.3V) inside the Low Cost Mic, This routes 9.3V to R429, and creates
2.6V on MIC_SENSE (u.P U403-67) by Voltage Divider R429/R430. U403 senses this voltage and
sends command to ASFIC_CMP U504 to get GCB3 = ‘0’. The audio signal is routed from C5045 via
U509-5 (Z0), R5072, U507, R5026, C5091, R5014 via C5046 to U504- 46 int. mic (C5046 100nF
creates a 159Hz pole with U504- 46 int mic impedance of 16k ohm).

2-16

7.1.2

THEORY OF OPERATION

Standard Microphone
Hook Pin is shorted to the hook mic inside the standard Mic, If the mic is out off hook, 3.3V is routed
to R429 via R458, D401, and it create 0.7V on MIC_SENSE (u.P U403-67) by Voltage Divider
R429/R430. U403 senses this voltage and sends command to ASFIC_CMP U504 to get GCB3 =‘1’.
The audio signal is routed from C5045 via U509-3 (Z1), R5072, U507, R5026, C5091, R5014 via
C5046 to U504- 46 int mic (C5046 100nF create a159Hz pole with U504- 46 int mic impedance of
16Kohm). 9.3VDC is routed via R5077, R5075 to J2-15, It create 4.65V with Mic Impedance. C5010
supplies AC Ground to create AC impedance of 510 Ohms via R5075. and Filter 9.3V DC mic bias
supply.
Note: The audio signal at U504-pin 46 should be approximately 12mV for 1.5kHz or 3kHz of
deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector P1 pin 2 and is routed via
line EXT MIC to R5054. R5078 and R5076 provide the 9.3Vdc bias. Resistive divider R5054/ R5070
divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. R5076 and
C5009 provide a 510 ohm AC path to ground that sets the input impedance for the microphone and
determines the gain based on the emitter resistor in the microphone’s amplifier circuit.
C5047 serves as a DC blocking capacitor. The audio signal at U504-pin 48 should be approximately
14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO signal from accessory connector P1-pin 5 is fed to the ASFIC CMP (U504 pin
42 through U509 pin 2 to U509 pin 15 via U506 OP-AMP circuit and C5057.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the
VOX. This circuit, along with Capacitor C5023 at U504-pin 7, provides a DC voltage that can allow
the µP to detect microphone audio. The ASFIC can also be programmed to route the microphone
audio to the speaker for public address operation.

7.2

PTT Sensing and TX Audio Processing
Internal microphone PTT is sensed by µP U403 pin 71. Radio transmits when this pin is “0” and
selects inside the ASFIC_ CMP U504 internal Mic path. When the internal Mic PTT is “0” then
external Mic PTT is grounded via D402. External Mic PTT is sensed by U403 pin 72 via Q412
circuits. The radio transmits when this pin is “0” and selects inside the ASFIC _CMP U504 External
Mic path.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 3003000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer,
which is used to add in signaling data, and then to a splatter filter to eliminate high frequency
spectral components that could be generated by the limiter. The audio is then routed to an
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The
TX audio emerges from the ASFIC CMP at U504-pin 40 MOD IN, at which point it is routed to the
RF section.

Transmit Signalling Circuits

8.0

2-17

Transmit Signalling Circuits

HS
SUMMER

MICRO
CONTROLLER

U403

19 HIGH SPEED
CLOCK IN
(HSIO)

DTMF
ENCODER

SPI
BUS

SPLATTER
FILTER

ASFIC_CMP U504

5-3-2 STATE
ENCODER

LOW SPEED
CLOCK IN
(LSIO)

PL
ENCODER

LS
SUMMER
ATTENUATOR

40
MOD IN

TO RF
SECTION
(SYNTHESIZER)

Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
■

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or
signaling,

■

DTMF data for telephone communication in trunked and conventional systems, and

■

Audible signaling including MDC and high-speed trunking.

Note: All three types are supported by the hardware while the radio software determines which
signaling type is available.

8.1

Sub-Audio Data (PL/DPL)
Sub-audible data implies signaling whose bandwidth is below 300Hz. PL and DPL waveforms are
used for conventional operation and connect tones for trunked voice channel operation. The
trunking connect tone is simply a PL tone at a higher deviation level than PL in a conventional
system. Although it is referred to as “sub-audible data”, the actual frequency spectrum of these
waveforms may be as high as 250 Hz, which is audible to the human ear. However, the radio
receiver filters out any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U504 (ASFIC CMP) at any one time. The
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper lowspeed data deviation and select the PL or DPL filters. The µP then generates a square wave which
strobes the ASFIC PL / DPL encode input LSIO U504-pin 18 at twelve times the desired data rate.
For example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U504 which generates a staircase approximation to a PL sine
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice
or data. The resulting summed waveform then appears on U504-pin 40 (MOD IN), where it is sent to
the RF board as previously described for transmit audio. A trunking connect tone would be
generated in the same manner as a PL tone.

2-18

8.2

THEORY OF OPERATION

High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signaling Words
(ISWs) used in a trunking system for high speed communication between the central controller and
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U504) to the proper filter and
gain settings. It then begins strobing U504-pin 19 (HSIO) with a pulse when the data is supposed to
change states. U504’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the postlimiter summer block and then the splatter filter. From that point it is routed through the modulation
attenuator and then out of the ASFIC CMP to the RF board. MDC is generated in much the same
way as trunking ISW. However, in some cases these signals may also pass through a data preemphasis block in the ASFIC CMP. Also these signaling schemes are based on sending a
combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during high speed data
signaling.

8.3

Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type
of tones which are heard when using a “Touch Tone” telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high
group (1209, 1336, 1477Hz). The high-group tone is generated by the µP (U403-46) strobing U50419 at six times the tone frequency for tones less than 1440Hz or twice the frequency for tones
greater than 1440Hz. The low group tone is generated by the ASFIC CMP, controlled by the µP via
SPI bus. Inside U504 the low-group and high-group tones are summed (with the amplitude of the
high group tone being approximately 2 dB greater than that of the low group tone) and then preemphasized before being routed to the summer and splatter filter. The DTMF waveform then follows
the same path as was described for high-speed data.

Receive Audio Circuits

9.0

2-19

Receive Audio Circuits
ACCESSORY
CONNECTOR
11

1
AUDIO
PA
U502
9

SPKR +

SPKR -

EXTERNAL
SPEAKER

INT
SPKR+

INT
SPKRCONTROL HEAD
CONNECTOR
19

MUTE

U509

FLT RX AUDIO

INTERNAL
SPEAKER

20
J2

HANDSET
AUDIO

U505
37

10
GCB4 U IO

43 AUX RX

URX OUT AUDIO

GCB1

VOLUME
ATTEN.

ASFIC_CMP
U504

FILTER AND
DEEMPHASIS

DISC
FROM
AUDIO
RF
SECTION
(IF IC)

2 DISC

PL FILTER
LIMITER
LIMITER, RECTIFIER
FILTER, COMPARATOR

LS IO

SQUELCH
CIRCUIT
SQ DET

CH ACT

MICRO
CONTROLLER

U403

Figure 2-9 Receive Audio Paths

9.1

Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U504-pin 2). All of
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of
view, DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs
based on the result. They are CH ACT (U504-16) and SQ DET (U504-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to
produce SQ DET (U504-17) from CH ACT. The state of CH ACT and SQ DET is high (logic “1”)
when carrier is detected, otherwise low (logic “0”).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.

2-20

9.2

THEORY OF OPERATION

Audio Processing and Digital Volume Control
The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is.DC
coupled to ASFIC CMP via the DISC input U504-pin 2. The signal is then applied to both the audio
and the PL/DPL paths
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, an LPF filter to remove any frequency components above 3000Hz, and a HPF to
strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a deemphasis filter (if it is enabled to compensate for Pre-emphasis which is used to reduce the effects
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level
is set depending on the value of the volume control. Finally the filtered audio signal passes through
an output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at AUDIO output
(U504 pin 41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum /
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signaling is summed with voice information on transmit, it must be separated
from the voice information before processing. Any sub-audible signaling enters the ASFIC CMP
from the IF IC at DISC U504-2. Once inside, it goes through the PL/DPL path. The signal first
passes through one of the two low-pass filters, either the PL low-pass filter or the DPL/LST low-pass
filter. Either signal is then filtered and goes through a limiter and exits the ASFIC CMP at LSIO
(U504-pin 18). At this point, the signal will appear as a square wave version of the sub-audible
signal which the radio received. The µP U403 pin 80 will decode the signal directly to determine if it
is the tone / code which is currently active on that mode.

9.3

Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U504-pin 41 is routed through DC blocking
capacitor C5049 to the audio PA (U502 pin 1 and 9).
The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+/SPK- (U502 pins 4 and 6)
The audio PA is enabled via the ASFIC CMP (U504-GCB1). When the base of Q501 is low, the
transistor is off and U502-pin 8 is high, using pull up resistor R5041, and the audio PA is ON. The
voltage at U502-pin 8 must be above 8.5Vdc to properly enable the device.
If the voltage is between 3.3 and 6.4V, the device will be active but has its input (U502-pins 1/9) off.
This is a mute condition which is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with B+
(U502- pin 7). B+ of 11V yields a DC offset of 5V, and B+ of 17V yields a DC offset of 8.5V. If either
of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ and SPKare routed to the accessory connector (P1-pin 1 and 16) and to the control head (connector J2-pins
19 and 20).

Receive Signalling Circuits

9.4

2-21

Handset Audio
Certain handheld accessories have a speaker within them which require a different voltage level
than that provided by U502. For these devices HANDSET AUDIO is available at control head
connector J2 pin18.
The received audio from the output of the ASFIC CMP’s digital volume attenuator is routed to U505
pin 2 where it is amplified. This signal is routed from the output of the op-amp U505 to J2-pin 18.
From the control head, the signal is sent directly to the microphone jack.

9.5

Filtered Audio and Flat Audio
The ASFIC CMP output audio at U504-pin 39 is filtered and de-emphasized, but has not gone
through the digital volume attenuator. From ASFIC CMP U504-pin 39 the signal is routed via R5034
through gate U509-pin 12 and AC coupled to U505-pin 6. The gate controlled by ASFIC CMP port
GCB4 selects between the filtered audio signal from the ASFIC CMP pin 39 (URXOUT) or the
unfiltered (flat) audio signal from the ASFIC CMP pin 10 (UIO). Resistors R5034 and R5021
determine the gain of op-amp UU505-pin 6 for the filtered audio while R5032 and R5021 determine
the gain for the flat Audio. The output of U505-pin 7 is then routed to P1 pin 11 via DC blocking
capacitor C5003. Note that any volume adjustment of the signal on this path must be done by the
accessory.

10.0

Receive Signalling Circuits

DATA FILTER
AND DEEMPHASIS
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)

LIMITER

HSIO 19

82
44

DISC

ASFIC_CMP
U504
FILTER

LIMITER

MICRO
CONTROLLER
U403

LSIO 18

80
85

PLEAP
8

PLCAP2
25

Figure 2-10 Receive Signalling Paths

10.1

Sub-Audio Data (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U504) is used to filter and limit all received data. The data enters the ASFIC CMP
at input DISC (U504 pin 2). Inside U504 the data is filtered according to data type (HS or LS), then it
is limited to a 0-3.3V digital level. The MDC and trunking high speed data appear at U504-pin 19,
where it connects to the µP U403 pin 82.

2-22

THEORY OF OPERATION

The low speed limited data output (PL, DPL, and trunking LS) appears at U504-pin18, where it
connects to the µP U403-pin 80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C5028,
and C5026 set the low frequency pole for a zero crossings detector in the limiters for PL and HS
data. The hysteresis of these limiters is programmed based on the type of received data.

10.2

Alert Tone Circuits
When the software determines that it needs to give the operator an audible feedback (for a good
key press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures),
it sends an alert tone to the speaker. It does so by sending SPI BUS data to U504 which sets up the
audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways:
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency,
and at what volume level to generate the tone. (It does not have to be related to the voice volume
setting.)
For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is
accomplished by the µP generating a square wave which enters the ASFIC CMP at U504 pin 19.
Inside the ASFIC CMP this signal is routed to the alert tone generator.
The output of the generator is summed into the audio chain just after the RX audio de-emphasis
block. Inside U504, the tone is amplified and filtered, then passed through the 8-bit digital volume
attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U504pin 41 and is routed to the audio PA like receive audio.

Chapter 3
TROUBLESHOOTING CHARTS
This section contains detailed troubleshooting flowcharts. These charts should be used as a guide in
determining the problem areas. They are not a substitute for knowledge of circuit operation and
astute troubleshooting techniques. It is advisable to refer to the related detailed circuit descriptions
in the theory of operation sections prior to troubleshooting a radio.
Most troubleshooting charts end up by pointing to an IC to replace. It is not always noted, but it is
good practice to verify supplies and grounds to the affected IC and to trace continuity to the
malfunctioning signal and related circuitry before replacing any IC. For instance, if a clock signal is
not available at a destination, continuity from the source IC should be checked before replacing the
source IC.

3-2

1.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)
START

Problem in 12 KHz and
25 KHz channel spacing

Yes

9V on Yes
R310 (LNA)
OK?

No
Go to
DC Section

Check
RX_EN

Go to
DC Section

3V
to U301
Okay ?

Yes

Check Q306, Q300
and U403

Check Q304, D305
and U403

Go to SYN
Section

Go to
DC Section

RX_EN
ON ?

Yes

No
LOC_DIST
ON?

Yes

Check
LOC_DIST

Check
TP1

LO
POWER
OK ?

Yes

Check 5V
on R336

5V
Yes
(IF AMP)
OK ?

Check 3V
on R338

Go
to A

Check D301-304
Replace IF Filters( FL304, FL301)
If problem in 25 KHz spacing

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)

1.1

3-3

Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
From
A

3V
(IFIC -Vcc)
OK ?

Go to
DC Section

Check
the component

Antenna to Mixer
circuitry problem

Check visually
all receiver
components
installation ?

Yes

Installation
OK ?

Yes

Inject - 40dBm (CW)
to RF connector
Check Power on
C332

RF
Yes
Power
> -28 dBM?

Check Power on
C336

Replace
Q305, Q300, U302
Check passive
components

Replace
Q303, Q301
Check passive
components

No
Replace Y301

No
Go to DC Section

3V to
U301
OK?

Y301
OK?

Yes

RF
Yes
Power
> -28 dBM?

Replace Q302, Y300
Check D301 - 304

Yes
Replace U300

Check Y301
44.395 MHz

3-4

2.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 3)
START

No or too low power when keyed

Check components between
Q100 and RF output,
Antenna Switch D104,
D103, VR102 and Q106

>4A

Current
increase when
keyed?

>500mA & <4A

<500mA
Check PA
Stages

Yes

Control
Voltage at
TP150
>4Vdc?

No
Check 9.3V
Regulator
U501

Voltage U103
pin 5 =
4.6V?

Yes
Check power settings, tuning
& components between U103
Pin 3 and ASFIC Pin 6 before
replacing ASFIC

U103 Pin 3
<1.6Vdc

Yes
Check
U103

Yes

Short U100
Pin 3 to
ground

U100 Pin 3
>1.8Vdc

No
Check forward
Power Sense
Circuit

Check PA
Stages

Yes

Voltage at
TP150 rises?

No
Check Forward
Power Sense
Circuit

Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 3)

2.1

3-5

Troubleshooting Flow Chart for 45W Transmitter (Sheet 2 of 3)
Check PA
Stages

No or too low power when keyed

DC
Voltage
at Q101
base=0?

Check Q101, R122,
R197, R153, R136,
R165, R168,

No
Check U510

Yes

No
DC
Voltage at
U103 Pin
10=8.9V

<2V

DC
Voltage
at U103
Pin 8

>5V

Yes
Check U103 before replacing U101

2 to 5V

DC
Voltage at
C1095

Check bias tuning
before replacing
U504

No
ASFIC
U504
Pin 5 2-3V

2-3V

Yes
Check components between ASFIC and Q105
before replacing Q105

Check Final PA Stages

Check resistive network at
Pin 9 and 10 of U103
before replacing U101

3-6

2.2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 45W Transmitter (Sheet 3 of 3)
Check Final PA Stage

Check components
between ASFIC &
Q100 before replacing Q100

Yes

PA_Bias
Voltage at
R134

Supply Voltage
Replace Q100

1-4Vdc
RF Voltage
after C1044
>100mV?

RF Voltage
after C1044
>100mV?

No
Check FGU

No
Check Bias Tuning
before replacing
ASFIC U504

Yes

Voltage
across R122
>2V?

Check components
between C1044 &
C1117

Check components
between C1117 &
Q105

Check components
between Q105 &
Q100

Yes

RF Voltage
Q105 gate
>1V?

Yes

RF Voltage
Q100 gate
>1.5V?

Yes
Check components
between Q100 &
antenna connector

Troubleshooting Flow Chart for Synthesizer

3.0

3-7

Troubleshooting Flow Chart for Synthesizer

3V at
U200 pins 5,
20, 34 & 36

Start

Check 3V
Regulator
U508

Yes
No

Correct
Problem

Visual
check of the
Board OK?
Yes

Yes

5V
at pin 6 of
D200

Yes

Is U200
Pin 47
= 13VDC?

+5V at
U200 Pins
13 & 30?

Is 16.8MHz
Signal at
U200 Pin 19?

Is
16.8MHz
signal at
U200 pin
23?

Yes

Yes
Replace
U200

Yes
Check
Y201 and associated
parts

Check 5V
Regulator
U503

Check
R228

Is U201 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)

Are signals
at Pins 14 &
15 of U200?

Yes

Yes
Is U200 pin 2
>4.5 VDC in Tx &
<40 mVDC in Rx

Check D200, D201,
C2026, C2025,
C2024 & C2027

Yes

Are Waveforms
at Pins 14 & 15
triangular?
No

Check R201

Replace U200

Is there a short
between Pin 47 and
Pins 14 & 15 of
U200?

Check programming
lines between U403
and U200 Pins 7,8 & 9

Do Pins
7,8 & 9 of
U200 toggle
when channel is
changed?

Yes

Yes
Is RF level at
U200 Pin 32
-12 < x <-25
dBm?

Yes

Replace
U200

If C2052, R208, C2067
C2068. C210, are OK, then
see VCO
troubleshooting chart

Remove
Shorts

Check µP U403
Troubleshooting
Chart

Is information
from µP U403
correct?
Yes

Replace U200

3-8

TROUBLESHOOTING CHARTS

4.0

Troubleshooting Flow Chart for VCO

RX VCO

Low or no RF Signal
at input to PA

Low or no RF Signal
at TP1

Visual check
of board
OK?

Correct
Problem

Make sure U508 is working
correctly and runner
between U508 Pin 1 and
U201 Pin 14 & 18 is OK

NO
3.3 DC at U201
Pin 14 & 18 OK?

Make sure Synthesizer is
working correctly and runner
between U200 Pin 28 and
U201 Pin 3 is OK

4.5V DC at
U201 Pin 3 OK?

YES

YES
Check runner
between U200 Pin 2
and U201 Pin 19

YES

Are Q200
Base at 2.4V
Collector at 4.5V
Emitter at 1.7V

3.3V DC at U201
Pin 14 & 18 OK?

YES

35mV DC at
U201 Pin 19
OK?

Visual check
of board
OK?
YES

YES

4.5V DC at
U201 Pin 3 OK?

TX VCO

4.8V DC at
U201 Pin 19
OK?
YES

If all parts associated
with the pins are OK
replace U201

Are U201 Pins
13 at 4.4V
15 at 1.1V
10 at 4.5V
16 at 1.9V

If all parts
associated
with the pins
are OK,
replace U201

YES

If L216, C2071, C2070,

Check 9V at R230

Is RF available
at C2060

C2060 are okay
replace U201

YES

Is RF available
at base of Q200

Check Transmiter
Pre Driver

YES

Check parts between
TP1 and Q200

If all parts from U200 Pin 8
to Base of Q200 are OK,
replace U200

NO
Power OK but
no modulation

Audio =180mVrms
at “+” side of
D205

Replace R212

YES

2.5VDC
at D205

YES

If R211 is Ok,
replace D205

NO
Replace R211

Troubleshooting Flow Chart for DC Supply (1 of 2)

5.0

3-9

Troubleshooting Flow Chart for DC Supply (1 of 2)
Since the failure of a critical voltage supply might cause the radio to automatically power down,
supply voltages should first be probed with a multimeter. If all the board voltages are absent, then
the voltage test point should be retested using a rising-edge-triggered oscilloscope. If the voltage is
still absent, then another voltage should be tested using the oscilloscope. If that voltage is present,
then the original voltage supply in question is defective and requires investigation of associated
circuitry.
5V

Check VDC on
C5006

Go to 3V

Replace U503

Yes

V=5V
?

Check Voltage on
C5042

No
Go to Start

9v
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