Sec2Cover Sect2_Power Dist_Controller_A Sect2 Power Dist Controller A
User Manual: Sect2_Power Dist_Controller_A
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Commercial Series CP040 Radios Power Distribution and Controller Service Information Issue: October 2004 ii Computer Software Copyrights The Motorola products described in this manual may include copyrighted Motorola computer programs stored in semiconductor memories or other media. Laws in the United States and other countries preserve for Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer programs contained in the Motorola products described in this manual may not be copied or reproduced in any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royaltyfree license to use that arises by operation of law in the sale of a product. iii Table of Contents Chapter 1 THEORY OF OPERATION 1.0 Overview.............................................................................................................. 1-1 2.0 Radio Power Distribution ..................................................................................... 1-1 3.0 Controller Circuits ................................................................................................ 1-3 3.1 General .......................................................................................................... 1-3 3.2 Microprocessor Circuitry ................................................................................ 1-4 3.3 Audio Circuitry................................................................................................ 1-8 Chapter 2 TROUBLESHOOTING CHARTS 1.0 Troubleshooting Flow Chart for Board and IC Signals (includes Controller, DC Regulation and Audio) .................................................. 2-1 Chapter 3 CONTROLLER SCHEMATICS 1.0 Allocation of PCBs and Schematic Diagrams...................................................... 3-1 2.0 Controller Schematics ......................................................................................... 3-3 iv Chapter 1 THEORY OF OPERATION 1.0 Overview This Chapter provides a detailed theory of operation for the controller circuits in the radio. The components of these circuits are contained on the Main Board. Refer to the RF sections of this manual for the component location details and the parts lists of the Controller Circuits. 2.0 Radio Power Distribution Accessories 20 pin Connector Audio Power Amplifier Keypad/Option Board UNSWB+ 7.5V Battery SWB+ Fuse MECH. SWB+ 3.3V Reg. LI Ion Vdda Regulator Vdda Vddd Regulator Vddd Tx Led Control MCU, ROM and EEPROM LCD Driver ASFIC_CMP FRACTN VCOBIC On/Off Switch 5V Regulator Low Battery Detect PA, Driver PCIC(ALC) 5V Antenna Switch RF AMP, IF AMP, RX/TX Buffers IFIC Figure 1-1 DC Power Distribution Block Diagram Figure 1-1 illustrates the DC distribution throughout the radio board. Battery voltage enters at connector J301 and is routed through fuse F301 to become USWB+. VR301 protects against ESD, and D301 provides reverse polarity protection. This voltage is routed to: ■ FET switch Q170 in the TX power control circuit (turned on during transmit) ■ TX power amplifier module U110 (via R150) ■ input pins of regulators U310, U320 and U330 ■ FET switch Q493 (turned on whenever the radio is on) ■ on-off switch S444 (part of on-off-volume control) to become SWB+ 1-2 THEORY OF OPERATION When the radio is turned on, SWB+ is present and is applied to: ■ transistor switch Q494 (pins 1 and 6) which turns on Q493 ■ RX audio power amplifier U490 ■ voltage divider R420/R421 and port PE0, a microprocessor A/D input which measures battery voltage and radio on/off status The output of FET switch Q493 is applied to the control pins of regulators U310, U320 and U330, turning them on. The following regulators are used: Table 1-1 Voltage Regulators Reference No. Description U310 5V Regulator U320 Digital 3.3V Regulator U330 3V Regulator Type TK71750S LP2986 TK71730S The 5V source is applied to: ■ RX back end circuitry ■ synthesizer super filter input and charge pump supply ■ RED/GRN LEDs ■ RX audio buffer U510 ■ portions of ASFIC U451 The 5V source is also applied to FET switches Q311 and Q312. Q311 is turned on by Q313 when RX_ENA (from U401 pin 49) is high, and supplies the "5R" source to the RF front end stages Q21Q22, and the VCO RX injection buffer Q280. Q312 is turned on by Q313 when TX_ENA (from U401 pin 50) is high, and supplies the "5T" source to the first transmitter stage Q100. The digital 3.3 volt source from U320 (D_3.3V) is applied to: ■ microprocessor U401 ■ EEPROM U402 ■ S-RAM U403 (not used) ■ flash ROM U404 The 3V regulated source from U330 is applied to: ■ synthesizer IC U201 ■ VCO/buffer IC U251 ■ portions of ASFIC U451 ■ microphone bias circuitry While the radio is turned on, port PH3 (U401 pin 44) is held high. When the radio is turned off, SWB+ is removed and port PE0 (U401 pin 67) goes low, initiating a power-down routine. Port PH3 (pin 44) remains high, keeping the voltage regulators on via Q493 and Q494, until the operating state of the radio has been stored in EEPROM and other turn-off data functions have been completed. PH3 then goes low, turning off Q494 and Q493, and all regulated voltages are removed. Controller Circuits 3.0 Controller Circuits 3.1 General 1-3 The controller board is the central interface between the various subsystems of the radio. It provides the following functions: ■ interface with controls and indicators ■ serial bus control of major radio circuit blocks ■ encoding and/or decoding of selective signaling formats such as PL, DPL, MDC1200 and QuikCall II ■ interface to CPS programming via the microphone connector ■ storage of customer-specific information such as channel frequencies, scan lists, and signaling codes ■ storage of factory tuning parameters such as transmitter power and deviation, receiver squelch sensitivity, and audio level adjustments ■ power-up, power-down and reset routines In the UHF and VHF sections, the Radio Block Interconnect Diagram show the interconnections between the controller and the various other radio blocks, while the Controller Interconnect Schematic diagram (in this chapter) shows the connections between the following circuit areas which comprise the controller block: ■ microprocessor circuitry ■ audio circuitry ■ DC regulation circuitry ■ rotary and pushbutton controls and switches The majority of the circuitry described below is contained in the Microprocessor Circuit schematic diagrams. However, portions are also found in the DC Regulation and UHF/VHF Audio Circuit schematics. 1-4 3.2 THEORY OF OPERATION Microprocessor Circuitry The microprocessor circuitry includes microprocessor (U401) and associated EEPROM and Flash ROM memories. The following memory IC's are used: Table 1-2 Radio Memory Requirements Reference No. 3.2.1 Description Type U402 Serial EEPROM AT25128 U403 Static RAM (not used) U404 Flash ROM AT49LV001N_70V Size 16K x 8 128K x 8 Memory Usage Radio operation is controlled by software that is stored in external Flash ROM memory (U404). Radio parameters and customer specific information is stored in external EEPROM (U402). The operating status of the radio is maintained in RAM located within the microprocessor. When the radio is turned off, the operating status of the radio is written to EEPROM before operating voltage is removed from the microprocessor. Parallel communication with U403 and U404 is via: ■ address lines A(0)-A(16), from U401 port F ADDR0-ADDR13 and port G XA14-XA16 ■ data lines D(0)-D(7), from U401 port C DATA0-DATA7 ■ chip-select for U403, from PH6 (U401 pin 41) ■ chip-enable for U404, from PH7 (U401 pin 38) ■ output enable for U404, from PA7 (U401 pin 86) ■ write-enable for both U403 and U404, from PG7_R/W (U401 pin 4) Serial communication with U402 is via: 3.2.2 ■ the SPI bus ■ chip-select for U402, from PD6 (U401 pin 3) Control and Indicator Interface Ports PI3 and PI4 are outputs which control the top-mounted LED indicator. When PI3 is high, the indicator is red. When PI4 is high, the indicator is green. When both are high, the indicator is amber. When both are low, the indicator is off. Pressing the side-mounted PTT button (S441) provides a low to port PJ0 (U401 pin 71), which indicates PTT is asserted. Side-mounted option buttons 1 and 2 (S442 and S443) are connected to Ports PJ6 (pin 77) and PJ7 (pin 78), respectively. Controller Circuits 3.2.3 1-5 Serial Bus Control of Circuit Blocks The microprocessor communicates with other circuit blocks via a SPI (serial peripheral interface) bus using ports PD2 (data into uP), PD3 (data out of uP) and PD4 (clock). The signal names and microprocessor ports are defined in Table 1-3. Table 1-3 SPI Bus Signal Definitions Signal Name Microprocessor Port Microprocessor Pin SPI-DATA_IN PD2-MISO U401 Pin 99 SPI_DATA_OUT PD3-MOSI U401 pin 100 SPI_CLK PD4-SCK U401 pin 1 These signals are routed to: ■ the audio filter IC (U451) to control internal functions such as gain change between 25 kHz and 12.5 kHz channels, transmit or receive mode, volume adjustment, etc. ■ the synthesizer IC U201 to load receive and transmit channel frequencies ■ option board connector J460-1 for internal option configuration and control (not used in CP040) ■ serial EEPROM U402 (both SPI_DATA_IN and SPI_DATA_OUT are used) In order for each circuit block to respond only to the data intended for it, each peripheral has its own chip select (or chip enable) line. The device will only respond to data when its enable line is pulled low by one of the microprocessor ports, as follows: 3.2.4 ■ port PD5 (U401 pin 2) for the audio filter IC ■ port PH0 (U401 pin 47) for the synthesizer IC ■ port PH4 (U401 pin 43) for the option board/display enable (not used in CP040) ■ port PD6 (U401 pin 3) for the serial EEPROM Interface to RSS Programming The radio can be programmed, or the programmed information can be read, using a computer with CPS (Customer Programming Software) connected to the radio via a RIB (radio interface box) or with the RIB-less cable. Connection to the radio is made via the microphone connector (part of accessory connector J471). The SCI line connects the programming contact (J471 pin 6) to ports PD0_RXD (data into uP, pin 97) and PD1_TXD (data out of uP, pin 98). Transistor Q410 isolates the input and output functions by allowing PD1 to pull the line low, but does not affect incoming data from being read by port PD0. This isolation allows high-speed 2-wire programming via TP401 and TP402 for factory programming and tuning. 3.2.5 Storage of Customer-Specific Information Information that has been programmed using CPS, such as channel frequencies or selective signaling codes, are stored in the external EEPROM, where it is retained permanently (unless reprogrammed) without needing DC power applied to the microprocessor. 1-6 3.2.6 THEORY OF OPERATION Sensing of Externally-Connected Accessories Port PJ1 is used to detect the presence of externally connected accessories. Port PJ1 (U401 pin 72) is normally low, unless accessories (lapel speaker microphone, lightweight headset, etc.) are used with the radio. This port is used to detect an accessory PTT or auto sensing of a VOX accessory. If VOX is programmed into the radio channel codeplug information, and PJ1 is high during powerup, the radio will activate VOX operation. If a low is present at port PJ1 during power-up, the radio will use this port as an external PTT indicator. 3.2.7 Microprocessor Power-Up, Power-Down and Reset Routine On power-up, the microprocessor is held in reset until the digital 3.3V regulator (U320 pin 5) provides a stable supply voltage. Once the digital supply reaches steady state and releases the reset line (U320 pin 7), the microprocessor begins to start up. The ASFIC_CMP (U451) has already started running and is providing the startup clock to the microprocessor. After reset release by all circuits, the software within the microprocessor begins executing port assignments, RAM checking, and initialization. A fixed delay of 100 ms is added to allow the audio circuitry to settle. Next, an alert beep is generated and the steady state software begins to execute (buttons are read, radio circuits are controlled). When the radio is turned off, SWB+ is removed and port PE0 (U401 pin 67) goes low, initiating a power-down routine. Port PH3 (pin 44) remains high, keeping the voltage regulators on via Q493 and Q494, until the operating state of the radio has been stored in EEPROM. PH3 then goes low, and all regulated voltages are removed. The microprocessor reset line (pin 94) can be controlled directly by the digital 3.3 V regulator (U320 pin 7), the microphone jack (part of accessory connector J471) via Q472 and Q471, and the microprocessor itself. U320 pulls the reset line low if the digital 3.3 V source loses regulation. This prevents possible MOS latch-up or overwriting of registers in the microprocessor because the reset line is higher in voltage than the microprocessor VDD ports (U401 pins 12, 39, 59, 88). The microprocessor can drive the reset line low if it detects a fault condition such as an expired watchdog timer, software attempting to execute an infinite loop, unplanned hardware inputs, static discharge, etc. Finally, the Q471 can pull the reset line low during use of the programming cable and CPS by the application of a sufficiently negative voltage to the microphone connector tip contact (J471 pin 4), however this reset method is not utilized. 3.2.8 Boot Mode Control When power-up reset occurs, the microprocessor will boot into either normal or flash mode depending on the logic level of ports MODA (U401 pin 58) and MODB (pin 57). The Flash Adapter is a programming accessory which provides negative 9 volts dc via a 1K resistor to microphone connector J471 pin 4. This turns on Q471 and Q472 via D471 and VR472, pulling MODA and MODB low and allowing booting in the flash mode by cycling power to reset the radio. Software upgrades can then performed by loading the new software code into Flash ROM U404. Controller Circuits 3.2.9 1-7 Microprocessor 7.3975 MHz Clock The 7.3975 MHz clock signal (uP_CLK) is provided from the ASFIC_CMP (U451 pin 28). Upon startup the 16.8MHz crystal provides the signal to the ASFIC_CMP, which sends out the uP_CLK at 3.8MHz until a steady-state condition is reached and the clock is increased to 7.3975MHz for the microprocessor. 3.2.10 Battery Gauge Various battery types are available having different capacities. The different battery types contain internal resistors connected from the BATT_CHARGE contact to ground (which is routed to the microprocessor as BATT_DETECT). A voltage divider is formed with R255 producing a different DC voltage for each battery type, which is read by microprocessor port PE2 (pin 65). This allows the software to recognize the battery chemistry being used and adjust the battery gauge for best accuracy. 1-8 THEORY OF OPERATION 3.3 Audio Circuitry 3.3.1 Transmit and Receive Low-Level Audio Circuitry The majority of RX and TX audio processing is performed by U451, the Audio Filter IC (ASFIC_CMP), which provides the following functions: ■ Tone PL/Digital PL encoding and decode filtering ■ Tone PL/Digital PL rejection filter in RX audio path ■ TX pre-emphasis amplifier ■ TX audio modulation limiter ■ Post-limiter (splatter) filter ■ TX deviation adjust (digitally-controlled attenuators) ■ Programmable microphone gain attenuator ■ RX audio volume control (digitally controlled attenuator) ■ Carrier squelch adjustment (digitally controlled attenuator) ■ Microprocessor output port expansion ■ 2.5 volt dc reference source ■ Microprocessor clock generation (from the 16.8 MHz reference oscillator input) The parameters of U451 that are programmable are selected by the microprocessor via the CLOCK (U451 pin 21), DATA (U451 pin 22) and chip enable (U451 pin 20) lines. RX audio buffer U510 amplifies the audio level from the DEMOD output of the IFIC before being applied to the audio filter IC input (DISC, U451 pin 2). The buffer is DC coupled to avoid corruption of low-frequency data waveforms such as DPL. Because such waveforms are polarity sensitive, this buffer is configured as a single-stage inverting amplifier (U510-1 only) for VHF models where highside first injection is used, or is configured as a two-stage non-inverting amplifier (U510-1 and -2) for UHF models using low-side first injection. The gain of the buffer is 1.5 times or 3.5 dB. U480 and associated components are not used in CP040. Stage U480-1 is bypassed by jumper R487. Volume adjustment is performed by a digital attenuator within U451. The volume control (10KO, part of S444) is connected to D_3.3V and ground via R506 and R507. When the volume control is rotated, it varies the dc voltage applied to microprocessor A/D input port PE1 (U401 pin 66) between approximately 0 volts dc at minimum volume to 3.3 volts dc at maximum volume. Depending on this voltage, the appropriate setting of the digital volume attenuator is selected. This technique is less susceptible to noise than a conventional analog volume control. Controller Circuits 3.3.2 1-9 Audio Power Amplifier The audio power amplifier IC U490 amplifies receiver audio from U451 pin 41 to a level sufficient to drive a loudspeaker. U490 is a bridge amplifier delivering 3.46 volts rms between pins 5 and 8 without distortion, which is sufficient to develop 500 milliwatts of audio power into the internal 24 ohm speaker or an external 24 ohm load. The audio power amplifier is muted whenever speaker audio is not required to reduce current drain. The audio amp is muted when U451 pin 14 is low. When U451 pin 14 is high, U490 pin 1 is pulled low by Q490, enabling the audio amplifier. Because the power amplifier is a bridge-type, neither speaker terminal is grounded. Care should be taken that any test equipment used to measure the speaker audio voltage does not ground either speaker output terminal, otherwise damage to the audio power amplifier IC may result. When a 24ohm load resistor is used it should be connected between the tip and the sleeve of accessory jack J471 (3.5mm port), never to ground. External SPKR plug insertion mechanically disconnects the internal speaker. Voltage measurements using test equipment that is not isolated from ground may be made from one side of the speaker or load resistor (either the tip or the sleeve of J471) to chassis ground, in which case the voltage indicated will be one half of the voltage applied to the speaker or load resistor. The Motorola RLN4460 Portable Test Set and PMKN4004 Programming Test Cable provide the proper interface between the radio's ungrounded audio output and ground-referenced test equipment. 3.3.3 Internal Microphone Audio Voice Path Microphone audio from internal microphone is routed from J470-1 via C475, L471, and C470 to the ASFIC_CMP mic audio input (MICINT, U451 pin 46). During transmit, Q470 is turned on by a low at U451 pin 35, providing dc bias for the internal MIC via R478. External MIC plug insertion mechanically disconnects the internal microphone. External MIC audio is coupled through L471 and C470 to the mic audio input. An input level of 10 mV at J471 pin 4 produces 200 mV at the output of U451 pin 40, which corresponds to 60% deviation. 3.3.4 PTT Circuits The internal side-mounted PTT switch (S441) is sensed directly by microprocessor port PJ0 (U401 pin 71). External mic PTT is sensed by measuring the current drawn through the accessory connector (J471-4) by the mic cartridge (which is in series with the accessory PTT switch). This current is drawn through the base (pin 5) and emitter (pin 4) of a transistor in Q470, causing its collector (pin 3) to supply a logic-high to microprocessor port PJ1 (pin 72). 3.3.5 VOX Operation VOX audio accessories do not have a PTT switch. Instead, the mic cartridge is wired directly from J471-4 to ground. If the radio has been programmed for VOX operation and the VOX accessory is plugged in prior to turning the radio on, the current drawn by the cartridge will turn on Q470 (pins 34-5) and a logic high will be seen at port PJ1 at turn-on. The microprocessor then assumes VOX operation, with PTT controlled by the presence of audio at the mic cartridge. A dc voltage proportional to the audio level at the input of the ASFIC_CMP (U451 pin 46) is fed to an A/D input of microprocessor U401 (pin 62). During VOX operation, PTT is activated when the dc level exceeds a preset threshold. 1-10 3.3.6 THEORY OF OPERATION Battery Charging Through Microphone Jack A wall-type charging power supply may be connected to the 2.5 mm microphone jack (part of accessory connector J451). The voltage present at the tip contact (pin 4) is applied to the center charging contact of the battery via diode D470. Another diode, internal to the battery, applies this voltage to the (+) battery terminal. Only the recommended charger and battery type should be charged in this manner. Different battery types contain internal resistors connected from the BATT_CHARGE contact to ground, which is routed to the microprocessor as BATT_DETECT. A voltage divider is formed with R255 producing a DC voltage which is read by microprocessor port PE2 (pin 65). This allows the software to recognize the battery chemistry being used and adjust the battery gauge for best accuracy. The value of R255 is chosen so that the voltage at the BATT_CHARGE node (cathode of D470) is never low enough to turn on the EXT_MIC_PTT sense transistor (part of Q470). 3.3.7 Programming and Flashing Through Microphone Jack The ring contact on the 2.5 mm microphone jack is used for reading, programming or re-flashing the radio using CPS. This contact (J471 pin 6) is routed to ports PD0_RXD (data into uP, pin 97) and PD1_TXD (data out of uP, pin 98). Transistor Q410 isolates the input and output functions by allowing PD1 to pull the line low, but does not affect incoming data from being read by port PD0. To re-flash the radio (overwrite the software in the Flash ROM with new software), the radio must power up in the boot mode. This is accomplished by using a flash adapter accessory, which provides SCI communication with the programming ring contact (J471 pin 6) and also allows a negative voltage (negative 9 volts dc via a 1K resistor) to be applied to the tip contact (J471 pin 4). This voltage is sufficient to turn on the base-emitter junction (pins 1 and 2) of Q472 via L471, D471, VR472 and R471. Pin 6 of Q472 goes high, turning on Q471 (pins 3 and 4) and pulling the BOOT_ENA line (ports MODA and MODB of the microprocessor) low. Cycling power generates a reset which causes the radio to boot in the flash mode. Chapter 2 TROUBLESHOOTING TABLES 1.0 Troubleshooting Tables for Board and IC Signals (includes Controller, DC Regulation and Audio) This section contains detailed troubleshooting tables. These tables should be used as a guide in determining the problem areas. They are not a substitute for knowledge of circuit operation and astute troubleshooting techniques. It is advisable to refer to the related detailed circuit descriptions in the theory of operation sections prior to troubleshooting a radio. Most troubleshooting tables end up by pointing to an IC to replace. It is not always noted, but it is good practice to verify supplies and grounds to the affected IC and to trace continuity to the malfunctioning signal and related circuitry before replacing any IC. For instance, if a clock signal is not available at a destination, continuity from the source IC should be checked before replacing the source IC. IC Designator Pin U310 5V Regulator 1 Vin 7.48 2 Ground GND 3 Control input 7.48 4 Bypass capacitor 1.26 5 Vout 4.96 1 Ground GND 2 Feedback 1.23 3 Tap (NU) 0 4 Vin 7.48 5 Vout 3.23 6 Sense (NU) 7 Error (reset output) 3.20 8 Shutdown input 7.48 1 Vin 7.48 2 Ground GND 3 Control input 7.48 4 Bypass capacitor 1.26 5 Vout 3.00 U320 3.3V Regulator U330 3V Regulator Pin Function DC Voltage 0 Comments (Condition) 2-2 TROUBLESHOOTING TABLES IC Designator Pin Pin Function DC Voltage Comments (Condition) U401 Microprocessor 1 PD4_SCK serial clock input 2 PD5_SS 3.23 ASFIC chip select 3 PD6_VLIN 3.23 EEPROM chip select 4 PG7_R_W 3.21 5 PG6_AS 3.23 6 PG0_XA13 3.23 7 PB7_ADDR15 0.026 8 PB6_ADDR14 0.028 9 PB3_ADDR11 3.06 10 PB1_ADDR9 3.05 11 PB2_ADDR10 0.16 12 VDD 3.23 13 VSS GND 14 PBO_ADDR8 3.05 15 PB5_ADDR13 0.13 16 PG1_XA14 0.20 17 PG4_XA17 3.17 18 PG5_XA18 0 19 PG3_XA16 3.21 20 PG2_XA15 0.30 21 PB4_ADDR12 0.22 22 PF7_ADDR7 3.03 23 PF6_ADDR6 3.08 24 PF5_ADDR5 3.06 25 PF4_ADDR4 0.16 26 PF3_ADDR3 0.26 27 PF2_ADDR2 3.06 28 PF1_ADDR1 3.06 29 PFO_ADDR0 3.05 30 PC0_DATA0 0.69 31 PC1_DATA1 0.96 32 PC2_DATA2 1.10 33 PC3_DATA3 0.81 34 PC4_DATA4 0.62 35 PC5_DATA5 0.68 36 PC6_DATA6 0.67 37 PC7_DATA7 0.73 0 Troubleshooting Tables for Board and IC Signals (includes Controller, DC Regulation and Audio) IC Designator Pin Pin Function DC Voltage Comments (Condition) U401 Microprocessor 38 PH7_CSPROG 3.05 39 VDDL 3.23 40 VSSL GND 41 PH6_CSGP2 3.23 42 PH5_CSGP1 3.23 43 PH4_CSIO 0 44 PH3_PW4 3.21 45 PH2_PW3 0 46 PH1_PW2 3.00 47 PH0_PW1 3.23 48 XIRQ 3.00 49 PI7 1.48 RX enable 50 PI6 0.01 TX enable 51 PI5 3.23 52 PI4 0 Green LED enable 53 PI3 0 Red LED enable 54 PI2 0 55 PI1 0 56 PI0 2.98 Lock detect from U201-4 57 MODB_VSTBY 3.22 Boot mode enable 58 MODA_LIR 3.12 59 AVDD 3.23 60 PE7_AN7 3.20 61 PE6_AN6 3.20 62 PE5_AN5 2.91 VOX threshold detect 63 PE4_AN4 0.73 RSSI input 64 PE3_AN3 0.14 65 PE2_AN2 1.62 66 PE1_AN1 0 - 3.3 V 67 PE0_AN0 2.48 68 VRL 0 69 VRH 3.20 70 AVSS GND 71 PJ0_CSGP3 3.23 72 PJ1_CSGP4 0 73 PJ2 3.23 74 PJ3 3.23 On/off control output Synth chip select Volume control wiper 33% of battery voltage Side PTT button External MIC PTT 2-3 2-4 TROUBLESHOOTING TABLES IC Designator Pin U401 Microprocessor 75 PJ4 3.23 76 PJ5 0 77 PJ6 3.23 Bottom option button 78 PJ7 3.23 Top option button 79 PA0_IC3 0 80 PA1_IC2 1.57 81 PA2_IC1 3.00 82 PA3_IC4_OC5_OC1 3.00 83 PA4_OC4_OC1 0 Squelch detect input 84 PA5_OC3_OC1 0 Channel activity input 85 PA6_OC2_OC1 0 86 PA7_PA1_OC1 0 87 VSSR GND 88 VDDR 3.23 89 ECLK (NU) 1.60 90 EXTAL 1.70 Clock from U451-28 91 XTAL 1.40 Not used 92 VDDSYN 0 93 XFC (NU) 0 94 RESET 3.20 95 LVOUT 0 96 IRQ 3.20 97 PD0_RXD 3.23 98 PD1_TXD 1.9 99 PD2_MISO 0 100 PD3_MOSI 3.23 1 Chip select 3.23 2 Serial data out 3 Write protect 3.23 4 Vss GND 5 Serial data in 3.23 6 Serial clock 7 Hold 3.23 8 Vcc 3.23 U402 EEPROM Pin Function DC Voltage 0 0 Comments (Condition) From U320 From U401-3 Troubleshooting Tables for Board and IC Signals (includes Controller, DC Regulation and Audio) IC Designator Pin U404 Flash ROM 1 A11 3.06 2 A9 3.08 3 A8 3.05 4 A13 0.13 5 A14 0.31 6 NC 3.17 7 EN_WE 3.21 8 Vcc 3.23 9 RESET 3.20 10 A16 3.17 11 A15 0.30 12 A12 0.22 13 A7 3.03 14 A6 3.08 15 A5 3.06 16 A4 0 17 A3 0.24 18 A2 3.08 19 A1 3.05 20 A0 3.05 21 D0 0.69 22 D1 0.94 23 D2 1.08 24 GND GND 25 D3 0.78 26 D4 0.59 27 D5 0.66 28 D6 0.67 29 D7 0.75 30 EN_CE 3.01 31 A10 0.16 32 EN_OE U404 Flash ROM Pin Function DC Voltage 0 Comments (Condition) From U401-4 From U401-38 From U401-86 2-5 2-6 TROUBLESHOOTING TABLES IC Designator Pin Pin Function DC Voltage Comments (Condition) U451 ASFIC_CMP 1 VDD for analog circuits 3.00 2 DISC audio input 1.34 3 Ground for analog circuits GND 4 DACU output 0 5 DACR output 0 6 DACG output 2.38 (typ) 7 VOX peak detector output 2.91 8 PLCAP for DC integrator 0.40 9 SQIN 0.01 10 Universal audio input/output 11 VDD for DACs 12 SQCAP 0 13 GCB2 general purpose output 0 14 GCB1 general purpose output 0 15 GCB0 general purpose output 3.00 16 Squelch channel activity output 0 To U401-84 17 Squelch detect digital output 0 To U401-83 18 PL/low speed data I/O 1.50 19 High speed data I/O 3.00 20 Chip select 3.23 21 Serial clock input 0 22 Serial data input 3.23 23 Ground for clock synthesizer GND 24 Loop filter cap for clock syn 0.74 25 PLCAP2 for LS integrator 1.17 26 Not used 27 Vdd for clock synthesizer 3.00 28 Clock synthesizer output 1.70 29 1200 Hz ref for MDC decode 3.00 30 GNDDO GND 31 Ground for digital circuits GND 32 Vdd for analog switches 4.96 33 Vdd for digital circuits 3.00 34 16.8 MHz master clock input 1.54 35 GCB3 general purpose output 3.00 36 TX audio return from option 0 37 GCB4 general purpose output 0 From U510 Power set (TX mode) 0 4.95 Audio PA_EN (unsquelched) BW select (25 kHz mode) From U401-2 0 Internal MIC enable Troubleshooting Tables for Board and IC Signals (includes Controller, DC Regulation and Audio) IC Designator Pin U451 ASFIC_CMP 38 GCB5 general purpose output 39 RX audio send to option 1.48 40 Modulation output 1.50 41 RX audio out to power amp 1.51 42 Flat TX audio return from option 0.20 43 RX audio return to option 1.50 44 Flat TX audio send to option 1.50 45 Vdd for audio path I/O filters 3.00 46 Mic audio input 1.50 47 Ground for audio path I/O filters GND 48 Ext mic audio input (not used) 1 Unit 1 output 2.48 2 Unit 1 (-) input 2.48 3 Unit 1 (+) input 2.46 4 Ground GND 5 Unit 2 (+) input 0.28 6 Unit 2 (-) input 0.29 7 Unit 2 output 8 Vcc 4.96 1 Enable/shutdown 0.12 (Unsquelched) 2 Bias reference 3.26 (Unsquelched) 3 (+) input 3.26 (Unsquelched) 4 (-) input 3.27 (Unsquelched) 5 (-) output 3.25 (Unsquelched) 6 Vcc 7.48 (Unsquelched) 7 Ground GND 8 (+) output 3.29 1 Unit 1 output 1.75 2 Unit 1 (-) input 1.56 3 Unit 1 (+) input 1.55 4 Ground GND 5 Unit 2 (+) input 1.55 6 Unit 2 (-) input 1.56 7 Unit 2 output 1.38 8 Vcc 4.96 U480 Dual Opamp U490 Audio Power Amp U510 Dual Opamp Pin Function DC Voltage 2-7 Comments (Condition) 0 To U201-10 0 0 (Unsquelched) 1. All voltages are measured with a high-impedance digital voltmeter and expressed in volts DC relative to ground (0V). 2. Voltages are measured with a DC input voltage of 7.50 + .02 volts DC applied to the battery connector (J301). 3. All voltages are measured in the squelched receive mode, unless otherwise indicated. 4. Voltages are identical for VHF and UHF models unless otherwise indicated. 2-8 TROUBLESHOOTING TABLES Chapter 3 CONTROLLER SCHEMATICS 1.0 Allocation of PCBs and Schematic Diagrams The Controller circuits are contained on the printed circuit board (PCB) containing the RF circuits. This Chapter shows the schematics for the Controller circuits only, refer to the relevant RF section for details of the related RF circuits, the PCB component layouts and the complete radio parts lists. The Controller schematic diagrams and the related PCBs are shown below. Table 3-1 PCBs and Schematics PCBs : 8486769Z02_A 8486342Z13_C 8486635Z03_O 8486348Z13_C 8486634Z02_O SCHEMATICS Controller Interconnect Schematic Microprocessor Circuit Schematic Audio Circuit Schematic (VHF) Audio Circuit Schematic (UHF) DC Regulation Schematic (VHF1/VHF2/UHF1/UHF2) DC Regulation Schematic (UHF3) VHF1 VHF2 UHF1 UHF2 UHF3 Page 3-3 Page 3-4 Page 3-5 Page 3-6 Page 3-7 Page 3-8 3-2 CONTROLLER SCHEMATICS Controller Schematics SW_B+ 5V 3V SW_B+ 5V 3V Controller Schematics OPT_MIC OPT_TX_AUD_FLAT_RETURN OPT_TX_AUD_RETURN PWR_SET PWR_SET OPT_TX_AUD_SEND CNTL_PWR_SET OPT_RX_AUD_SEND_DETECTOR DEMOD DEMOD CNTL_DEMOD OPT_RX_AUD_SEND_UNMUTED AUDIO OPT_RX_AUD_RETURN BW_SEL BW_SEL CNTL_BW_SEL MOD_OUT MOD_OUT CNTL_MOD_OUT VS_AUDIO_SEL 16_8_MHZ 16_8_MHZ VS_GAIN_SEL D3_3V SW_B+ 14 13 12 11 10 9 8 7 6 5 C500 1000pF BATT_CHARGE RESET SCI ASFIC_CS F1200 15 uP_CLK 17 16 BOOT_ENA 18 E500 BK1005HM471 EXT_MIC_PTT 19 HSIO 21 20 LSIO 23 VOX 24 22 CH_ACT 25 SQ_DET 27 26 SPI_DATA_OUT 28 CNTL_16_8_MHZ SPI_CLK 3V C501 1uF SPI_CLK CNTL_SPI_CLK SPI_DATA_OUT C503 1000pF 4 3 2 1 30 29 32 31 CNTL_SPI_DATA_OUT R502 100 SYNTH_CS CNTL_SYNTH_CS R504 100 R501 100 LOCK CNTL_LOCK RSSI R505 100 J460-1 ACCESSORY/KEYPAD CONNECTOR TP403 CNTL_RSSI TP404 CNTL_TX_ENA TX_ENA C405 100pF C406 100pF R503 100 C403 100pF C504 1000pF 5V SW_B+ D3_3V 3V 5V 5R 5T 3V D3_3V BATT_DETECT SCI RESET ASFIC_CS F1200 uP_CLK BOOT_ENA EXT_MIC_PTT HSIO VOX LSIO SQ_DET CH_ACT SPI_DATA_IN 3V SPI_DATA_OUT OPT_DATA_READY SPI_CLK D3_3V 5V VS_RAC SW_B+ USWB+ SW_B+ USWB+ CNTL_USWB+ 5V TP301 CNTL_5V BACKLIGHT 5R CNTL_5R KEYPAD_ROW 5T CNTL_5T KEYPAD_COL SYNTH_CS 3V CNTL_3V DISPL_COM_DATA_SEL OPT_ENA C408 1000pF C409 C407 1000pF 1000pF C404 1000pF 1 A1 B1 2 3 A2 B2 4 MICROPROCESSOR TX_ENA BATT_CHARGE RX_ENA RX_ENA VOLUME VOLUME ON_OFF ON_OFF 3V D3_3V 5T DC_REGULATION PTT S441 SWITCH OPT_BUTTON_1 TX_ENA OPT_BUTTON_2 1 A1 B1 2 3 A2 B2 4 FREQ_SEL_0 S442 SWITCH S440 SWITCH 8 1 A1 B1 2 3 A2 B2 4 PC0 PC1 PC3 PC2 9 S443 SWITCH C0 GND C402 C505 C506 C507 1000pF 1000pF 1000pF 1000pF 5V RESET VS_CS VS_INT 5R RSSI DISP_ENA SWB+ LOCK USWB+ NC GND1 2.0 3-3 C1 1 2 4 FREQ_SEL_1 C0 C1 FREQ_SEL_2 7 FREQ_SEL_3 Controller Interconnect Schematic Diagram 3-4 Controller Schematics D3_3V R410 10K R417 10K R416 20K 1 C418 0.1uF D3_3V TP405 D3_3V D425 D3_3V NC 1 6 SCI R411 820 2 D3_3V R419 4.7K 4 3 1 TP402 R406 220K Q425 R401 300K D3_3V Q426 100K R407 Q410 R412 100K C412 1000pF C413 0.1uF 1 TP401 8 6 1 3 7 5 SCK R408 100K SO WP 4 R403 10K CS D3_3V R402 10K VCC C411 0.1uF 2 LSIO R405 2 U425 LMC7101BI 1 Q427 3 5 HOLD SI 4 U402 X25128-2.7 300K VSS C410 10uF D3_3V C425 1uF C419 1000pF D3_3V CH_ACT C426 1uF EEPROM SQ_DET P13 R409 18K R404 51K HSIO SPI_DATA_IN OPT_DATA_READY SPI_DATA_OUT uP_CLK SPI_CLK D3_3V C400 NU R400 NU DISPL_COM_DATA_SEL R418 100K C414 0.1uF NC NC C415 1000pF C416 1000pF C417 1000pF R414 33K R415 33K R413 100K NC ASFIC_CS 59 39 88 12 VDD VDDL AVDD VDDR 93 92 95 LVOUT XFC VDDSYN 91 68 90 79 80 81 82 83 84 85 86 69 VRH VRL XTAL EXTAL PA0_IC3 PA1_IC2 PA2_IC1 PA3_IC4_OC5_OC1 PA4_OC4_OC1 PA5_OC3_OC1 PA6_OC2_OC1 97 PD1_TXD PD0_RXD PA7_PA1_OC1 2 98 100 99 PD2_MISO PD5_SS PE6_AN6 96 NC NC 48 94 D414 4 58 57 BOOT_ENA 71 PTT 72 73 74 EXT_MIC_PTT 75 76 77 FREQ_SEL_0 78 67 FREQ_SEL_1 66 65 64 63 VS_RAC FREQ_SEL_2 62 61 FREQ_SEL_3 AVSS 60 OPT_BUTTON_1 70 VSSL 40 PI0 PI1 VSS PI2 PI3 PI4 PI5 PI6 VSSR 87 56 13 55 54 53 52 51 50 PI7 PE7_AN7 49 22 PC7_DATA7 14 PC6_DATA6 10 PC5_DATA5 PBO_ADDR8 PC4_DATA4 PB1_ADDR9 PE5_AN5 PB2_ADDR10 37 D(7) PE4_AN4 PC3_DATA3 11 36 D(6) PE3_AN3 PC2_DATA2 PB3_ADDR11 35 D(5) PE2_AN2 PC1_DATA1 9 34 PC0_DATA0 PB4_ADDR12 D(4) PE1_AN1 21 DISP_ENA PE0_AN0 PB5_ADDR13 33 D(3) PJ7 PH6_CSGP2 PH7_CSPROG 15 32 D(2) PH5_CSGP1 PB6_ADDR14 31 D(1) PJ5 PJ6 8 D(0) PJ4 PH4_CSIO PB7_ADDR15 30 ON_OFF PH3_PW4 7 38 PJ3 U401 MC68HC11FL0 PH2_PW3 PFO_ADDR0 41 2 PJ2 PH1_PW2 PF1_ADDR1 42 PJ1_CSGP4 PH0_PW1 29 43 PJ0_CSGP3 PG6_AS PF2_ADDR2 44 PG5_XA18 PF3_ADDR3 45 RESET 89 PG4_XA17 PF4_ADDR4 46 1 Q402 RESET PG7_R_W MODA_LIR MODB_VSTBY PF5_ADDR5 47 3 R445 4.7K IRQ XIRQ PG3_XA16 28 5 ECLK PG2_XA15 27 18 A(18) NC PG1_XA14 26 A(17) PG0_XA13 25 17 PF6_ADDR6 19 A(16) 24 R446 10K 1 20 A(15) 23 Q403 16 A(14) PD4_SCK 3 2 PD3_MOSI PD6_LVIN 6 NC SW_B+ 3 BACKLIGHT PF7_ADDR7 SYNTH_CS 1 F1200 D(7:0) A(8) A(9) A(10) A(11) A(12) NC NC A(13) A(0) A(1) A(2) A(3) A(5) A(4) A(18:0) A(6) A(7) D3_3V OPT_BUTTON_2 C446 .01uF D3_3V C430 0.1uF C432 0.1uF VCC 5V D(5) D(6) D(7) SH400 SHIELD 1 6 SH401 SHIELD NC 1 GND D3_3V R433 100K R431 NU A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A(0) A(1) A(2) R430 100K A(3) D(0) A(4) D(1) A(5) D(2) A(6) D(3) A(7) D(4) A(8) D(5) A(9) D(6) A(10) D(7) 11 12 13 15 16 17 18 19 D1 D2 D3 D4 D5 D6 D7 D8 A(11) 5 A(0) A(2) 6 4 A(1) 2 Q440-2 A(3) A(4) C420 .01uF R440 4.7K R421 100K 1% C447 0.1uF R441 4.7K 3 A(5) VOLUME A(6) A(7) R442 220 A(8) A(9) R443 120 C422 .01uF A(10) A(11) A(12) RED LED D424 3V RB520S-30 GREEN LED A(13) A(14) BATT_DETECT A(12) A(13) A(14) A(15) A(16) U403 NU SRAM 20 CS 22 OE 27 WE RSSI D440 BRPY1204W VOX D3_3V R422 100K 24 KEYPAD_COL R432 0 A(17) A(18) R434 NU KEYPAD_ROW R423 100K LOCK VS_INT VS_CS OPT_ENA TX_ENA RX_ENA Microprocessor Circuit Schematic Diagram C443 .01uF SW_B+ 28 VDD 9 20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 P13 D(4) RESET D0 D1 D2 D3 D4 D5 D6 D7 VSS D(3) 21 22 23 25 26 27 28 29 C442 .01uF R420 200K 1% 1 Q440-1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 14 D(2) C441 .01uF SW_B+ C433 1000pF 8 30 EN_CE 32 EN_OE 7 EN_WE D(1) C440 .01uF C431 1000pF U404 AT49LV001N_70VI FLASH D(0) C445 .01uF R424 200K 1% C421 .01uF R425 100K 1% C444 .01uF C401 0.1uF Controller Schematics 3-5 150 mV RMS (25 kHz) (Rx) 75 mv RMS (12.5 kHz) (Rx) R523 10K R516 NU C512 6.8pF R522 100K C514 16pF R512 150K 4 2 R514 100K 3 Q520-2 IMX1 5V_A 1 R511 100K 5 2 DEMOD 6 8 1 R513 6 8 3 R515 7 4 5V_A 5 OPT_RX_AUD_SEND_DETECTOR 4 U510-1 LM2904 C513 220pF C511 220pF VHF UHF R513 Not Placed 100k R515 Not Placed 0 R516 Not Placed Not Placed OPT_RX_AUD_RETURN R521 NU R470 2.2K VR471 3V_A NC R520 100K OPT_RX_AUD_SEND_UNMUTED 2.3 V OPT_TX_AUD_FLAT_RETURN R480 0 R517 R519 100K OPT_TX_AUD_SEND C519 1uF Not Placed OPT_TX_AUD_RETURN R472 680 1 R473 680 4 VS_AUDIO_SEL 1.5 V VS_GAIN_SEL 3V_A 2 C461 1000pF PWR_SET D471 C470 0.1uF 5 R471 2.2K VR472 6 VOX 3V_A 3 Q472 NC 3V R460 24K 1 C453 4.7uF R462 24K R464 30K 3 2 AUXTN CSX AUDIO CLK MOD DATA RXSND GCB3 C465 1000pF 2 D470 10 mV RMS (Tx) 4 45 R477 2.2K 44 6 C472 0.1uF 43 42 3 C473 150pF C474 150pF 40 6 NC MMBZ5245B 20V 15V A_MOD_OUT 38 MMBZ5250B VR475 MOD_OUT 39 S3 S1 NC 7 2 M2 M3 NC 3 C475 .022uF C466 NU 1 R478 2.2K EXT_MIC_PTT 3 V (Tx) M1 J471 ACCESSORY CONNECTOR 1 2 C476 .022uF C478 150pF J470-1 MICROPHONE CONNECTOR R479 100K C458 0.1uF 3V_A SCI 20V VR474 NC 3V 5 NC MMBZ5250B Q470 S2 S4 VR473 200 mV RMS 41 C457 0.1uF C456 0.1uF OPT_MIC L471 390nH 0 V (Rx) SPI_DATA_OUT BOOT_ENA 4 Q471 5 R476 100K 46 37 4 R475 180K C471 2.2uF NC TXRTN VDDD CLK168 35 34 C464 0.1uF 48 47 3 BATT_CHARGE 36 33 VDDCP GCB4 GNDDO GCB5 LCAP PLCAP2 GNDSYN SPI_CLK R463 24K 1 DISC VDDA DACU GNDA 7 4 8 6 5 DACR VOX DACG PLCAP 11 10 9 SQIN UIO SQCAP HSIO GNDD 24 TXSND RXRTN 30C53 U451 F1200 23 ASFIC_CS SQDET LSIO 30 22 VDDRC 31 21 HSIO MICINT CHACT 32 20 GNDRC GCB0 SYN 19 GCB1 29 17 18 LSIO VDDDAC 12 16 VDDSYN 15 2 C477 0.1uF R255 3.9K R474 330 1 3V_A MICEXT NC 14 SQ_DET GCB2 27 13 26 CH_ACT C467 1200pF 1% C455 .022uF BW_SEL C463 0.1uF C462 0.1uF 5V_A C454 0.1uF RESET 6 5V C452 0.1uF C451 0.1uF 25 1 R451 47K 114 mV (RF) 3V 7.5 V 16_8_MHZ 2 SW_B+ J491-1 E451 INTERNAL SPEAKER BK1005HM471 F1200 C459 0.1uF uP_CLK 5V_B C493 1000pF 145 mV RMS R494 330K C494 2.2uF 1.5 V 3 J491-3 4 J491-4 3.5V (UNSQ) 5V_A E452 5V_B C499 39pF R487 0 BK1005HM471 5V_B R481 R493 330K R482 E453 BK1005HM471 C497 0.1uF 2 C481 1 3 4 U480-1 1 3 C483 0.22uF 8 DC Level 0.3 - 0.4 V low Supply = 7.42 1/2 Supply = 3.22 R491 R492 0 24K R484 2 4 C480 0.1uF INPOS OUTNEG SVR OUTPOS 5 7 U490 TDA8541 3 C484 150pF R490 Q481 R485 1 3.46 V RMS (Rx)(0.5 W@24 OHMS C489 470pF C492 10uF 3 R469 10 3.5V (UNSQ) 8 INNEG C479 C482 2 C488 470pF 6 MODE VCC 5V 5V GND 0 C460 0.1uF U510-2 LM2904 28 R517 R518 220K Q520-1 IMX1 C518 0.1uF R496 R497 5V_B 1 R486 R483 2 Q482 1 8 6 6 7 5V_B 2 3 R488 330K 4 1 C495 1uF 6 R499 5 R498 D491 C496 1uF 4 U480-2 NC R489 Q490 UMG5 2 3 4 R495 5.6K C490 470pF 0.15 V (UNSQ) U511 UMG5 C498 1uF 3 V (UNSQ) Audio Circuit Schematic Diagram (VHF) 3-6 Controller Schematics R516 R523 NU C512 10K C514 6.8pF R522 16pF 100K R514 R512 150K LM2904 R511 2 100K 3 DEMOD Q520 8 1 R513 C511 8 4 C513 R518 220K 220pF R519 100K C519 R515 7 1 5 IMX1 C518 6 IMX1 6 C460 0.1uF VR471 R470 OPT_RX_AUD_SEND_DETECTO R 5 4 5V_A 3 Audio Q520 5V_A 100K U510-1 4 2 U510-2 0.1uF 2.2K OPT_RX_AUD_RETURN LM2904 220pF R521 NU R520 100K 3V_A NC OPT_RX_AUD_SEND_UNMUTED R480 0 OPT_TX_AUD_FLAT_RETURN R517 OPT_TX_AUD_SEND 1uF OPT_TX_AUD_RETURN VS_AUDIO_SEL VS_GAIN_SEL 3V_A PWR_SET VOX 3V_A 0.1uF C452 0.1uF R462 24K 0.1uF 4.7uF 10 V SQCAP VDDDAC UIO SQIN PLCAP VOX DACG DACR DACU GND A DISC VDDA 12 11 10 9 8 7 6 5 4 3 2 1 C455 .022uF CH_ACT 13 14 15 16 17 18 19 20 21 22 23 24 SQ_DET LSIO HSIO ASFIC_CS GCB2 GCB1 GCB0 CHACT SQDET LSIO HSIO CSX CLK DATA GND SYN LCAP U451 30C53 C456 C457 0.1uF 0.1uF SPI_DATA_OUT 3V Not Placed Not Placed R517 0 Not Placed R463 30K 24K 3V_A R451 47K 5 Q472 2.2K Q471 3 6 5V R474 330 C464 C465 C471 0.1uF 1000pF 2.2uF R476 100K 2 4 3 5 Q470 D470 2.2K C472 6 0.1uF 3 A_MOD_OUT L471 390nH C474 C473 150pF 150pF 4 S2 5 S4 NC NC .022uF C458 0.1uF 1000pF 1 M1 1 2.2K C493 3 M3 J470-1 R478 C478 C476 2 J491-1 INTERNAL SPEAKER .022uF 150pF R494 C494 330K 2.2uF 7 S1 2 M2 VR474 MMBZ5250B 20V C475 VR475 15V MMBZ5245B NU 6 S3 SCI VR473 20V MMBZ5250B NC R479 100K C466 BOOT_ENA J471 ACCESSORY CONNECTOR OPT_MIC EXT_MIC_PTT MOD_OUT 4 BATT_CHARGE R475 180K R477 RESET 2 R255 3.9K 1% 1 6 1 0.1u F SW_B+ MICROPHONE CONNECTOR 1 E451 2 16_8_MHZ BK1005HM471 C459 F1200 0.1uF uP_CLK 5V_B C481 .01uF E452 BK1005HM471 5V E453 5V_A 2 5V BK1005HM471 C497 5V_B C482 .01uF Not:Placed:NU 3 Q481 Not_Placed:NU 1 0.1uF R486 100K Not_Placed:NU R483 150K Not_Placed:NU R487 0 5V_B 8 2 3 C499 39pF C483 0.22uF R484 2.2K 1 Not_Placed:NU 4 C484 U480-1 3 R485 100K 1 Q490 R491 R492 0 24K R490 2.2K Not_Placed:NU Not_Placed:NU .033uF LM2904 Not_Placed:NU 1 3 2 4 C488 C480 R469 0.1uF 10 3 J491-3 470pF TDA854 MODE 5 INPOS OUTNEG SVR OUTPOS 8 INNEG C479 150pF 6 VCC U490 GN D 4 J491-4 C489 1 470pF 7 C492 R496 10K Not_Placed:NU R497 1MEG 10uF Q482 Not_Placed:NU DC Level 0.3 - 0.4 V low Supply = 7.42 1/2 Supply = 3.22 5V_B Not_Placed:NU 2 UMG5 1 5V_B R488 330K C490 470pF 6 R498 U511 2 3 C495 UMG5 4 1 6 1uF 2 3 4 R495 5.6K C498 1uF Audio Circuit Schematic Diagram (UHF) R473 680 4 C477 R493 330K R516 1200pF R482 330K 0 0.1uF Not_Placed:NU Not Placed 0.1uF Not_Placed:NU R515 C467 R481 100K UHF 100k 3V_A C463 R464 Not_Placed:NU VHF 48 NC 47 46 45 44 43 42 41 40 39 38 37 NC C462 1 2 R471 NC NC 3V Not Placed 0.1uF 25 26 27 28 29 30 31 32 33 34 35 36 SPI_CLK R513 MICEXT GNDRC MICINT VDDRC TXSND RXRTN AUXTN AUDIO MOD RXSND GCB5 GCB4 PLCAP2 NC VDDSYN SYN F1200 GNDDO GNDD VDDCP VDDD CLK168 GCB3 TXRTN BW_SEL 1000pF VR472 D471 3V C454 5V_A C453 C470 R460 24K C451 R472 680 C461 D491 47 K 8 7 6 5 4 U480-2 NC Not_Placed:NU R499 270K Not_Placed:NU LM2904 Not_Placed:NU R489 91K Not_Placed:NU C496 1uF Controller Schematics 3-7 USWB+ U310 TK71750S 7.5 V 5V 1 5 VIN VOUT 3 CTRL 4 BYPASS F301 3A 5V GND POS NEG DATA NC 2 C301 390pF J301 VR301 C303 33uF D301 C304 .01uF C311 .018uF C310 .01uF C313 .01uF C312 10uF MMBZ5250B 20V 5R D3_3V BATT_CHARGE Q311 C314 1200pF NC C302 390pF C305 100pF C306 .01uF VR302 MMBZ5250B 20V R313 5.1K R312 20K R310 100K 5 V (Rx) 0 V (Tx) 0 V (Rx) 5 V (Tx) C315 1200pF RX_ENA 3.3 V (Rx) 0 V (Tx) TX_ENA 0 V (Rx) 3.3 V (Tx) 0 V (Rx) 5 V (Tx) Q313 R311 100K 5T Q312 D3_3V 5 V (Rx) 0 V (Tx) R506 100 S444 SWITCH 3 HIGH 2 4 C316 1200pF 7.5 V (ON) 0 V (OFF) 3 2 VOLUME R508 100K 5 1 6 TAB2 TAB1 R507 100 7 1 SWB+ LOW Q493 3.3 V R509 100K 7.5 V (ON) 0 V (OFF) RESET C323 150pF R322 100K R510 330K 0 V (ON) 7.5 V (OFF) 6 NC 3.3 V (ON) 0 V (OFF) 2 NC 4 8 6 3 INPUT OUTPUT SHUTDOWN SENSE ERROR FEEDBACK 3.3 V 5 7 2 GND 1 TAP 1 ON_OFF C320 .018uF 4 R320 330K 1% C321 10uF D3_3V C322 .01uF Q494 R321 200K 1% 1 TP302 U330 TK71730S 3V 1 5 VIN VOUT 3 CTRL 4 BYPASS GND 3 D3_3V U320 LP2986 C331 .01uF 2 3V C333 .01uF C334 10uF DC Regulation Schematic Diagram (VHF1/VHF2/UHF1/UHF2) 3-8 Controller Schematics DC Regulation USWB+ J301 POS NEG DATA U310 TK71750S VR301 MMBZ5250B F301 3A C301 D301 NC 47pF 20V C303 C304 33uF .01uF 1 VIN 5 VOUT 3 4 CTRL BYPASS GND 2 C310 .01uF 5V C311 C312 C313 .018uF 10uF .01uF Q311 5R D3_3V BATT_CHARGE C314 VR302 MMBZ5250B C302 C305 C306 390pF 100pF .01uF 1200pF NC R313 10K 20V R312 20K R310 100K Q313 C315 RX_ENA 1 1200pF Q312 TP302 TX_ENA 5T R311 100K D3_3V R506 100 1200pF 2 2 VOLUME 1 5 SWB+ TAB1 6 R508 100K 3 1 R509 100K RESET TAB2 LOW R507 100 C316 Q493 S444 SWITCH 3 HIGH 4 C323 R322 100K 7 Q494 R510 1 LP2986 330K ON_OFF 3 D3_3V U320 6 2 150pF NC NC 4 INPUT OUTPUT 5 8 SHUTDOWN 3 SENSE ERROR 7 6 TAP FEEDBACK 2 GND 4 1 D3_3V C320 .018uF R320 330K 1% C321 C322 10uF .01uF R321 200K 1% U330 TK71730S C331 .01uF DC Regulation Schematic Diagram (UHF3) 1 VIN VOUT 5 3 CTRL 4 BYPASS GND 2 3V C334 C333 10uF .01uF
Source Exif Data:
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