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PA70HS(-G) / PA71HS Preface Notebook Computer PA70HS(-G) / PA71HS Service Manual Preface I Preface Notice The company reserves the right to revise this publication or to change its contents without notice. Information contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication. This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes. Preface Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement of that product or its manufacturer. Version 1.0 July 2017 Trademarks Intel and Intel Core are trademarks of Intel Corporation. Windows® is a registered trademark of Microsoft Corporation. Other brand and product names are trademarks and /or registered trademarks of their respective companies. II Preface About this Manual This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and inspection of personal computers. It is organized to allow you to look up basic information for servicing and/or upgrading components of the PA70HS(-G) / PA71HS series notebook PC. The following information is included: Chapter 1, Introduction, provides general information about the location of system elements and their specifications. Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade elements of the system. Preface Appendix A, Part Lists Appendix B, Schematic Diagrams Appendix C, Updating the FLASH ROM BIOS III Preface IMPORTANT SAFETY INSTRUCTIONS Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment: 1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet basement or near a swimming pool. 2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning. 3. Do not use the telephone to report a gas leak in the vicinity of the leak. 4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may explode. Check with local codes for possible special disposal instructions. 5. This product is intended to be supplied by a Listed Power Unit as follows: Preface • AC Input of 100 - 240V, 50 - 60Hz, DC Output of 19.5V, 11.8A (230 Watts) minimum AC/DC Adapter. FCC Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: This device may not cause harmful interference. This device must accept any interference received, including interference that may cause undesired operation. IV Preface Instructions for Care and Operation The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions: 1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged. Do not expose the computer to any shock or vibration. 2. Do not place anything heavy on the computer. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged. Do not leave it in a place where foreign matter or moisture may affect the system. Don’t use or store the computer in a humid environment. Do not place the computer on any surface which will block the vents. Preface Do not expose it to excessive heat or direct sunlight. 3. Do not place it on an unstable surface. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save your work. Remember to periodically save your data as data may be lost if the battery is depleted. Do not turn off the power until you properly shut down all programs. Do not turn off any peripheral devices when the computer is on. Do not disassemble the computer by yourself. Perform routine maintenance on your computer. V Preface 4. 5. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data. Take care when using peripheral devices. Use only approved brands of peripherals. Unplug the power cord before attaching peripheral devices. Preface Power Safety The computer has specific power requirements: VI • • Power Safety Warning • Before you undertake any upgrade procedures, make sure that you have turned off the power, and disconnected all peripherals and cables (including telephone lines and power cord). It is advisable to also remove your battery in order to prevent accidentally turning the machine on. • • • Only use a power adapter approved for use with this computer. Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are unsure of your local power specifications, consult your service representative or local power company. The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one. When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire. Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices. Before cleaning the computer, make sure it is disconnected from any external power supplies. Do not plug in the power cord if you are wet. Do not use the power cord if it is broken. Do not place heavy objects on the power cord. Preface Battery Precautions • Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer. • Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire. • Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode. • Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service personnel. • Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode or leak if exposed to fire, or improperly handled or discarded. • Keep the battery away from metal appliances. • Affix tape to the battery contacts before disposing of the battery. • Do not touch the battery contacts with your hands or metal objects. Battery Guidelines Preface The following can also apply to any backup batteries you may have. • If you do not use the battery for an extended period, then remove the battery from the computer for storage. • Before removing the battery for storage charge it to 60% - 70%. • Check stored batteries at least every 3 months and charge them to 60% - 70%. Battery Disposal The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste officials for details in your area for recycling options or proper disposal. Caution Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer. Discard used battery according to the manufacturer’s instructions. Battery Level Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10% will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week. VII Preface Related Documents You may also need to consult the following manual for additional information: User’s Manual on CD/DVD This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC. System Startup Preface 1. Remove all packing materials. 2. Place the computer on a stable surface. 3. Securely attach any peripherals you want to use with the computer (e.g. keyboard and mouse) to their ports. 4. When first setting up the computer use the following procedure (as to safeguard the computer during shipping, the battery will be locked to not power the system until first connected to the AC/DC adapter and initially set up as below): • Attach the AC/DC adapter cord to the DC-In jack on the left of the computer, then plug the AC power cord into an outlet, and connect the AC power cord to the AC/DC adapter and leave it there for 6 seconds or longer. • Remove the adapter cord from the computer’s DC-In jack, and then plug it back in again; the battery will now be unlocked. 5. Use one hand to raise the lid/LCD to a comfortable viewing angle (do not exceed 135 degrees); use the other hand (as illustrated in Figure 1) to support the base of the computer (Note: Never lift the computer by the lid/LCD). 6. Press the power button to turn the computer “on”. 135° Figure 1 Opening the Lid/LCD/ Computer with AC/DC Adapter Plugged-In Shut Down Note that you should always shut your computer down by choosing the Shut down command in Windows (see below). This will help prevent hard disk or system problems. Click the icon in the Start Screen and choose Shut down from the menu. Or Right-click the Start button at the bottom of the Start Screen or the Desktop and choose Shut down or sign out > Shut down from the context menu. VIII Preface Preface IX Preface Preface X Preface Contents Introduction ..............................................1-1 Overview .........................................................................................1-1 Specifications ..................................................................................1-2 External Locator - Top View with LCD Panel Open ......................1-4 External Locator - Front & Right Side Views .................................1-5 External Locator - Left Side & Rear View .....................................1-6 External Locator - Bottom View .....................................................1-7 Mainboard Overview - Top (Key Parts) .........................................1-8 Mainboard Overview - Bottom (Key Parts) ....................................1-9 Mainboard Overview - Top (Connectors) .....................................1-10 Mainboard Overview - Bottom (Connectors) ...............................1-11 Overview .........................................................................................2-1 Maintenance Tools ..........................................................................2-2 Connections .....................................................................................2-2 Maintenance Precautions .................................................................2-3 Disassembly Steps ...........................................................................2-4 Removing the Keyboard ..................................................................2-5 Removing the Battery ......................................................................2-6 Removing the Hard Disk Drive .......................................................2-8 Removing the System Memory (RAM) ........................................2-10 Removing the M.2 SSD Module ...................................................2-11 Removing the Wireless LAN Module ...........................................2-14 Wireless LAN, Combo Module Cables .........................................2-15 Removing the CCD .......................................................................2-16 Removing the LCD Module ..........................................................2-18 Part Lists ..................................................A-1 Part List Illustration Location ........................................................ A-2 Top ................................................................................................. A-3 Schematic Diagrams................................. B-1 System Block Diagram ...................................................................B-2 Processor 1/6 ...................................................................................B-3 Processor 2/6 ...................................................................................B-4 Processor 3/6 ...................................................................................B-5 Processor 4/6 ...................................................................................B-6 Processor 5/6 ...................................................................................B-7 Processor 6/6 ...................................................................................B-8 DDR4 CHA SO-DIMM_0 ..............................................................B-9 DDR4 CHB SO-DIMM_0 ............................................................B-10 Panel, Inverter ...............................................................................B-11 Mini DP Port (Back) .....................................................................B-12 Mini DP Port (Front) ....................................................................B-13 HDMI Connector ..........................................................................B-14 VGA PCI Express .........................................................................B-15 GPU Frame Buffer Partition .........................................................B-16 Frame Buffer Partition A ..............................................................B-17 Frame Buffer Partition B ..............................................................B-18 Frame Buffer Partition A_B .........................................................B-19 GPU Frame Buffer Partition .........................................................B-20 Frame Buffer Partition C ..............................................................B-21 Frame Buffer Partition D ..............................................................B-22 Frame Buffer Partition C_D .........................................................B-23 GPU Decoupling ...........................................................................B-24 Straps and XTAL ..........................................................................B-25 IFP I/O Interface ...........................................................................B-26 XI Preface Disassembly ...............................................2-1 Bottom ........................................................................................... A-4 Main Board ................................................................................... A-5 HDD .............................................................................................. A-6 LCD ............................................................................................... A-7 Preface Preface Misc - GPIO, I2C and ROM ........................................................ B-27 NVIDIA Power Sequence ............................................................ B-28 GPU NVVDD, FBVDDQ ............................................................ B-29 GPU GND .................................................................................... B-30 PCH 1/5 ........................................................................................ B-31 PCH 2/5 ........................................................................................ B-32 PCH 3/5 ........................................................................................ B-33 PCH 4/5 ........................................................................................ B-34 PCH 5/5 ........................................................................................ B-35 KBC IT8587 ................................................................................. B-36 RGB and White KB LED ............................................................. B-37 M.2 PCIE4X SSD ........................................................................ B-38 M.2 3G/LTE/WIGIG/WLAN+BT ............................................... B-39 Audio ............................................................................................ B-40 Audio Subwoofer ......................................................................... B-41 Audio Port 1 ................................................................................. B-42 AR_TBT ....................................................................................... B-43 AR Power ..................................................................................... B-44 TPS65982ABZQZ ........................................................................ B-45 USB 3.0 Type C ........................................................................... B-46 PS8338B ....................................................................................... B-47 TPM, CCD, TP ............................................................................. B-48 Connectors .................................................................................... B-49 Fan, LID, SATA HDD ................................................................. B-50 5V, 5VS, 3.3V, 3.3VS, 3.3VA ..................................................... B-51 1.0DX_VCCSTG/VCCSFR_OC/2.5V ........................................ B-52 1V8_RUN/AON, NV3V3 ............................................................ B-53 PEX_VDD .................................................................................... B-54 VDD3, VDD5 ............................................................................... B-55 DDR 1.2V / 0.6VS ....................................................................... B-56 Power 1.0V, VCCIO .................................................................... B-57 VCC_Core .................................................................................... B-58 XII VCore & VCCGT Output .............................................................B-59 VCCSA .........................................................................................B-60 AC_In, Charger .............................................................................B-61 NVVDDS ......................................................................................B-62 NVVDD 1 .....................................................................................B-63 NVVDD 2 .....................................................................................B-64 FBVDDQ ......................................................................................B-65 LED Board ....................................................................................B-66 LID Board .....................................................................................B-67 DC Board ......................................................................................B-68 Power Board .................................................................................B-69 Click Board ...................................................................................B-70 Audio Board ..................................................................................B-71 USB Board ....................................................................................B-72 USB 3.0 Board ..............................................................................B-73 PA7 Card Reader Board 1/4 .........................................................B-74 PA7 Card Reader Board 2/4 .........................................................B-75 PA7 Card Reader Board 3/4 .........................................................B-76 PA7 Card Reader Board 4/4 .........................................................B-77 Power Sequence ............................................................................B-78 pdating the FLASH ROM BIOS............ C-1 Download the BIOS ........................................................................C-1 Unzip the downloaded files to a bootable CD/DVD or USB Flash drive ..............................................................................C-1 Set the computer to boot from the external drive ...........................C-1 Use the flash tools to update the BIOS ...........................................C-2 Restart the computer (booting from the HDD) ...............................C-2 Introduction Chapter 1: Introduction Overview This manual covers the information you need to service or upgrade the PA70HS(-G) / PA71HS series notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the computer. Operating systems (e.g. Windows 10, etc.) have their own manuals as do application softwares (e.g. word processing and database programs). If you have questions about those programs, you should consult those manuals. 1.Introduction The PA70HS(-G) / PA71HS series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please take note of the warning and safety information indicated by the “” symbol. The balance of this chapter reviews the computer’s technical specifications and features. Overview 1 - 1 Introduction Specifications Processor Options Security i7-7820HK (2.90GHz) Security (Kensington® Type) Lock Slot 6MB Smart Cache, 14nm, DDR4-2400MHz, TDP 45W i5-7700HQ (2.80GHz) 6MB Smart Cache, 14nm, DDR4-2400MHz, TDP 45W BIOS Password Intel PTT for Systems Without TPM Hardware (Factory Option) TPM 2.0 (Factory Option) Fingerprint Reader Module Latest Specification Information 1.Introduction The specifications listed here are correct at the time of sending them to the press. Certain items (particularly processor types/speeds) may be changed, delayed or updated due to the manufacturer's release schedule. Check with your service center for more details. CPU Speed & Computer in DC Mode Note that when the computer is in DC mode (powered by the battery only) the CPU may not run at full speed. This is a design feature implemented in order to protect the battery. Core Logic Intel® HM175 Express Chipset LCD Options 17.3" (43.94cm), 16:9, UHD (3840x2160)/*QHD (2560x1440)/FHD (1920x1080) *Note: QHD panels are available for systems with NVIDIA® G-SYNC™Technology only BIOS AMI BIOS (64Mb SPI Flash-ROM) Memory Video Adapter Options Microsoft Hybrid Graphics Mode Supports up to 4 Active Displays Supports NVIDIA Surround View via HDMI x 1 and MiniDP x2 Intel Integrated GPU Intel® HD Graphics 630 Dynamic Frequency Intel Dynamic Video Memory Technology Microsoft DirectX®12 Compatible NVIDIA® Discrete GPU Two 260 Pin SO-DIMM Sockets Supporting DDR4 2400MHz Memory (The real memory operating frequency depends on the FSB of the processor.) Memory Expandable from 8GB (minimum) up to 32GB (maximum) NVIDIA® GeForce GTX 1070 8GB GDDR5 Video RAM Microsoft DirectX®12 Compatible Supports GPU Overclocking Storage Compatible with 4GB, 8GB or 16GB Modules SO-DIMM Memory Types All SO-DIMM memory modules installed in the system should be identical (the same size and brand) in order to prevent unexpected system behavior. Do not mix SO-DIMM memory module sizes and brands otherwise unexpected system problems may occur. 1 - 2 Specifications One changeable 2.5" (6cm) 7.0mm/9.5mm (h) SATA (Serial) Hard Disk Drive/Solid State Drive (SSD) (Factory Option) Two SATA M.2 2280 SSDs supporting RAID level 0/1 Or (Factory Option) One PCIe Gen3 x4 M.2 2280 SSD and one PCIe Gen3 x2 M.2 2280 SSD Introduction Pointing Device Communication Interface (Factory Option) Built-In Secure Pad (with Microsoft PTP Multi Gesture & Scrolling Functionality) Built-In 10/100/1000Mb Base-TX Ethernet LAN One USB 3.0 (USB 3.1 Gen 1) Type-C Port* 2.0M FHD PC Camera Module *The maximum amount of current supplied by USB Type-C ports is 500mA (USB 2.0)/900mA (USB 3.1). Or (Factory Option) One USB 3.1 Gen 2/Thunderbolt 3 Combo Port (Type-C) Or (Factory Option) Built-in Touchpad ( (with Microsoft PTP Multi Gesture & Scrolling Functionality) Keyboard (Factory Option) Full-size Illuminated White LED Winkey Keyboard (with numeric keypad) Or (Factory Option) Full Color Illuminated Full-size Winkey Keyboard (with numeric keypad) WLAN/ Bluetooth M.2 Modules: (Factory Option) Intel® Wireless-AC 8265 Wireless LAN (802.11ac) + Bluetooth (Factory Option) Intel® Wireless-AC 3168 Wireless LAN (802.11ac) + Bluetooth (Factory Option) Qualcomm® Atheros Killer™ Wireless-AC 1535 Wireless LAN (802.11ac) + Bluetooth (Factory Option) Qualcomm® Wireless LAN (802.11ad) + Bluetooth High Definition Audio Compliant Interface S/PDIF Digital Output Two Speakers Sound BlasterX® Pro-Gaming 720° ANSP™ 3D sound technology on headphone output Built-In Array Microphone One Sub-Woofer Note: External 5.1CH Audio Output Supported by 2-in1 Audio, Microphone-In and Headphone-Out Jacks Card Reader Embedded Multi-In-1 Push-Push Card Reader MMC (MultiMedia Card)/RS MMC SD (Secure Digital)/Mini SD/SDHC/ SDXC (up to UHS-II) Slot WLAN for Combo WLAN and Bluetooth Module Slot SSD1 for SATA or PCIe Gen3 x4 SSD Slot SSD2 for SATA or PCIe Gen3 x2 SSD One RJ-45 LAN Jack One DC-In Jack Environmental Spec Intel® Optane™ SSD Module Installation Service personnel please note that Intel® Optane™ modules must be installed in the SSD1 slot. Temperature Operating: 5°C - 35°C Non-Operating: -20°C - 60°C Relative Humidity Operating: 20% - 80% Non-Operating: 10% - 90% Power Embedded 4-Cell Polymer Battery Pack, 66WH Full Range AC/DC Adapter AC Input: 100 - 240V, 50 - 60Hz DC Output: 19.5V, 11.8A (230W) Dimensions & Weight 418.5mm (w) * 287mm (d) * 24.9mm (h) 3.0kg (Barebone with 66WH Battery) Specifications 1 - 3 1.Introduction M.2 Slots Audio Four USB 3.0 (USB 3.1 Gen 1) Ports (Including one AC/DC Powered USB port) Two Mini DisplayPorts (1.3) One HDMI-Out Port One 2-In-1 Audio Jack (Line-Out & S/PDIF-Out (Optical) Combo Jack) One Microphone-In Jack One Headphone-Out Jack Introduction Figure 1 External Locator - Top View with LCD Panel Open 1.Introduction Top View 1. PC Camera 2. *PC Camera LED *When the PC camera is in use, the LED will be illuminated. 3. Built-In Array Microphone 4. LCD 5. Speakers 6. Power Button 7. Keyboard 8. Touchpad & Buttons 9. Fingerprint Reader (Optional) 3 2 1 4 5 6 7 9 8 1 - 4 External Locator - Top View with LCD Panel Open 3 5 Introduction External Locator - Front & Right Side Views Figure 2 Front View 1. LED Indicator FRONT VIEW 1 RIGHT SIDE VIEW 1 2 3 4 5 6 7 8 1. Headphone-Out Jack 2. Microphone-In Jack 3. Line & S/PDIF Combo Jack 4. Multi-in-1 Card Reader 5. USB 3.0 (USB 3.1 Gen 1) Port 6. *Powered USB 3.0 (USB 3.1 Gen 1) Port 7. RJ-45 LAN Jack 8. Security Lock Slot External Locator - Front & Right Side Views 1 - 5 1.Introduction Figure 3 Right Side View Introduction External Locator - Left Side & Rear View Figure 4 Left Side View Vent DC-In Jack HDMI-Out Port Mini Display Port 1 Mini Display Port 2 USB 3.1 Gen 2 Type-C Ports 7. USB 3.0 (USB 3.1 Gen 1) Ports / LEFT SIDE VIEW 1 2 3 4 5 6 7 1.Introduction 1. 2. 3. 4. 5. 6. Figure 5 REAR VIEW Rear View 1. Vent 1 1 - 6 External Locator - Left Side & Rear View 1 Introduction External Locator - Bottom View Figure 6 Bottom View 1. Vent 2. Sub Woofer 1 1 1.Introduction 1 1 2 1 1 Overheating To prevent your computer from overheating, make sure nothing blocks any vent while the computer is in use. External Locator - Bottom View 1 - 7 Introduction Figure 7 Mainboard Overview - Top (Key Parts) 1.Introduction Mainboard Top Key Parts 3 2 1 1 - 8 Mainboard Overview - Top (Key Parts) Introduction Mainboard Overview - Bottom (Key Parts) Figure 8 Mainboard Bottom Key Parts 6 4 5 7 8 2 3 1 Mainboard Overview - Bottom (Key Parts) 1 - 9 1.Introduction 1. Mini-Card Connector (M.2 SSD Module) 2. Mini-Card Connector (M.2 SSD Module) 3. KBC-ITE IT8587 4. Mini-Card Connector (WLAN Module) 5. PCH 6. GPU-GTX1070 7. Memory Slots DDR4 SO-DIMM 8. CPU Introduction Figure 9 Mainboard Overview - Top (Connectors) 1.Introduction Mainboard Top Connectors 1. HDMI Port 2. Mini Display Ports 3. USB 3.1 Gen 2 Type-C Port 4. Power Connector 5. RGB LED KB Connector 6. RGB LED KB Connector 7. White LED KB Connector 8. Keyboard Cable Connector 9. LID Connector 11 4 5 6 7 9 8 1 2 2 3 1 - 10 Mainboard Overview - Top (Connectors) Introduction Mainboard Overview - Bottom (Connectors) Figure 10 Mainboard Bottom Connectors 13 12 10 10 4 4 1 1 5 2 3 6 7 8 9 Mainboard Overview - Bottom (Connectors) 1 - 11 1.Introduction 11 1. Card Reader Board Connector 2. Audio Board Connector 3. Battery Connector 4. VGA Fan Connector 5. HDD Cable Connector 6. FP Cable Connector 7. Click Board Connector 8. USB Board Connector 9. LED Board Connector 10. DC Board Connector 11. CPU Fan Connector 12. LCD Connector 13. CCD Connector 1.Introduction Introduction 1 - 12 Disassembly Chapter 2: Disassembly Overview This chapter provides step-by-step instructions for disassembling the PA70HS(-G) / PA71HS series notebook’s parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated). We suggest you completely review any procedure before you take the computer apart. To make the disassembly process easier each section may have a box in the page margin. Information contained under the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also. Information A box with a will also provide any possible helpful information. A box with a contains warnings. An example of these types of boxes are shown in the sidebar. Warning Overview 2 - 1 2.Disassembly Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are repeated here for your convenience. Disassembly NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the battery is removed too). Maintenance Tools The following tools are recommended when working on the notebook PC: 2.Disassembly • • • • • • M3 Philips-head screwdriver M2.5 Philips-head screwdriver (magnetized) M2 Philips-head screwdriver Small flat-head screwdriver Pair of needle-nose pliers Anti-static wrist-strap Connections Connections within the computer are one of four types: 2 - 2 Overview Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the same way. The pin1 side is usually not indicated. Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently rock it from side to side as you pull it out. Do not pull on the wires themselves. When replacing the connection, do not try to force it. The socket only fits one way. Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When replacing the connection, make sure the connector is oriented in the same way. The pin1 side is usually not indicated. Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as you pull them apart. If the connection is very tight, use a small flat-head screwdriver - use just enough force to start. Disassembly Maintenance Precautions The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions: 1. Power Safety Warning Before you undertake any upgrade procedures, make sure that you have turned off the power, and disconnected all peripherals and cables (including telephone lines and power cord). It is advisable to also remove your battery in order to prevent accidentally turning the machine on. Cleaning Do not apply cleaner directly to the computer, use a soft clean cloth. Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer. (For Computer Models Supplied with Light Blue Cleaning Cloth) Some computer models in this series come supplied with a light blue cleaning cloth. To clean the computer case with this cloth follow the instructions below. • • • • • • Power off the computer and peripherals. Disconnect the AC/DC adapter from the computer. Use a little water to dampen the cloth slightly. Clean the computer case with the cloth. Dry the computer with a dry cloth, or allow it time to dry before turning on. Reconnect the AC/DC adapter and turn the computer on. Overview 2 - 3 2.Disassembly Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other components could be damaged. 2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. 3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor the position of magnetized tools (i.e. screwdrivers). 4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged. 5. Be careful with power. Avoid accidental shocks, discharges or explosions. •Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. •When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. 6. Peripherals – Turn off and detach any peripherals. 7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. Before handling any part in the computer, discharge any static electricity inside the computer. When handling a printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that you use an anti-static wrist strap instead. 8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements. 9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted to charged surfaces, reducing performance. 10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as screws, loose inside the computer. Disassembly Disassembly Steps The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM THE DISASSEMBLY STEPS IN THE ORDER INDICATED. To remove the Keyboard: 1. Remove the keyboard To remove the Wireless LAN Module: page 2 - 5 To remove the Battery: 2.Disassembly 1. Remove the keyboard 2. Remove the battery page 2 - 5 page 2 - 6 To remove the HDD: 1. Remove the keyboard 2. Remove the battery 3. Remove the HDD page 2 - 5 page 2 - 6 page 2 - 8 To remove the System Memory: 1. Remove the keyboard 2. Remove the battery 3. Remove the system memory page 2 - 5 page 2 - 6 page 2 - 10 To remove and install the M.2 SSD: 1. 2. 3. 4. 5. Remove the keyboard Remove the battery Remove the M.2 SSD-1 (Intel) Remove the M.2 SSD-1 Remove the M.2 SSD-2 2 - 4 Disassembly Steps page 2 - 5 page 2 - 6 page 2 - 11 page 2 - 12 page 2 - 13 1. Remove the keyboard 2. Remove the battery 3. Remove the WLAN page 2 - 5 page 2 - 6 page 2 - 14 To remove the CCD Module: 1. Remove the keyboard 2. Remove the battery 3. Remove the CCD module page 2 - 5 page 2 - 6 page 2 - 16 To remove the LCD Module: 1. 2. 3. 4. 5. 6. 7. Remove the keyboard Remove the battery Remove the HDD Remove the system memory Remove the M.2 SSD Remove the WLAN Remove the LCD module page 2 - 5 page 2 - 6 page 2 - 8 page 2 - 10 page 2 - 11 page 2 - 14 page 2 - 18 Disassembly Removing the Keyboard Figure 1 1. Turn off the computer, turn it over. 2. Remove screws 1 - 2 from the bottom of the computer. 3. Open it up with the LCD on a flat surface before pressing at point 3 to release the keyboard module (use the special eject stick 4 to do this) while releasing the keyboard in the direction of the arrow 5 as shown (Figure 1a). 4. Carefully lift the keyboard 6 up, being careful not to bend the keyboard ribbon cable 7 . Disconnect the keyboard ribbon cable 7 from the locking collar socket by using a flat-head screwdriver to pry the locking collar pins 8 away from the base (Figure 1b). 5. Carefully lift the keyboard 6 off the computer (Figure 1c). a. b. 2 8 1 7 7 8 5 4 8 Re-inserting the Keyboard When re-inserting the keyboard firstly, align the keyboard tabs at the bottom of the keyboard with the slots in the case. c. 3 a. Remove the screws from the bottom of the computer and then eject the keyboard using a special eject stick to push the keyboard out while releasing the keyboard as shown. b. Lift the keyboard up and disconnect the keyboard ribbon cable from the locking collar socket. c. Remove the keyboard. 6 4. Eject Stick 6. Keyboard • 2 Screws Removing the Keyboard 2 - 5 2.Disassembly 6 Keyboard Removal Disassembly Figure 2 Battery Removal Removing the Battery 1. 2. a. Remove the screws. 3. b. Remove the SD cover 4. and screws. c. Remove the bottom case. Turn the computer off, and remove the keyboard (page 2 - 5). Remove screw 1 (Figure 2a). Remove the SD card cover 26 and screws 3 - 13 (Figure 2b). Release the bottom case 14 by using the left thumb 15 to hold down the most prominent area of the back cover and then use the right hand 16 to lift the rear side vent’s most prominent area (Figure 2c). 5. Carefully remove the bottom case up in the direction of the arrow 17 . c. a. 2.Disassembly 16 1 15 14 b. 3 4 5 6 12 2. SD Card Cover 14. Bottom Case • 12 Screws 2 - 6 Removing the Battery 13 7 2 11 10 9 8 17 Disassembly 6. 7. 8. 9. The battery will be visible at point 18 on the computer (Figure 3d). Carefully disconnect the cable 19 , then remove screws 20 - 23 (Figure 3e). Lift the battery 24 off the computer (Figure 3f). Reverse the process to install a new battery (do not forget to replace all the screws and bottom cover). Battery Removal (cont’d.) d. Locate the battery. e. Disconnect the cable and remove the screws. f. Lift the battery off the computer. f. d. Figure 3 2.Disassembly 18 24 e. 19 20 23 22 21 24. Battery • 4 Screws Removing the Battery 2 - 7 Disassembly Figure 4 HDD Assembly Removal a. Locate the HDD. b. Remove the screws. Removing the Hard Disk Drive The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 7mm (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in Chapter 4 of the User’s Manual) when setting up a new hard disk. Hard Disk Disassembly Process 1. Turn off the computer, and remove the keyboard (page 2 - 5) and battery (page 2 - 6). 2. The HDD will be visible at point 1 on the mainboard (Figure 4a). 3. Remove the screw 2 from the HDD assembly (Figure 4b). 2.Disassembly a. HDD System Warning New HDD’s are blank. Before you begin make sure: You have backed up any data you want to keep from your old HDD. 1 You have all the CD-ROMs and FDDs required to install your operating system and programs. b. 6. Hard Disk • 1 Screw 2 - 8 Removing the Hard Disk Drive 2 If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan to install. Copy these to a removable medium. Disassembly Slightly slide and pull the hard disk out. Lift the hard disk assembly 3 out of the bay 4 (Figure 5c). Remove screws 5 - 6 and bracket 7 from the hard disk 8 (Figure 5d). Reverse the process to install a new hard disk (do not forget to replace the screws). 4. 5. 6. 7. Figure 5 HDD Assembly Removal (cont’d.) c. Slide and pull the HDD assembly out of the bay. d. Remove the screws and bracket from the HDD. d. c. 8 4 2.Disassembly 6 7 3 5 3. HDD Assembly 7. HDD Bracket 8. HDD • 2 Screws Removing the Hard Disk Drive 2 - 9 Disassembly Figure 6 RAM Module Removal 2.Disassembly a. The RAM modules will be visible at point 1 on the mainboard. b. Pull the release latches. c. Remove the module. Contact Warning Be careful not to touch the metal pins on the module’s connecting edge. Even the cleanest hands have oils which can attract particles, and degrade the module’s performance. Removing the System Memory (RAM) The computer has four memory sockets for 260 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting DDR4 Up to 2400 MHz. The main memory can be expanded up to 64GB. The total memory size is automatically detected by the POST routine once you turn on your computer. Memory Upgrade Process 1. Turn off the computer, turn it over, remove the keyboard (page 2 - 5) and battery (page 2 - 6). 2. The RAM-2 modules will be visible at point 1 on the mainboard (Figure 6a). 3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the arrows (Figure 6b). The RAM module 4 will pop-up (Figure 6c), and you can then remove it. 4. Pull the latches to release the second module if necessary. 5. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot. 6. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot as it will go. DO NOT FORCE IT; it should fit without much pressure. 7. Press the module in and down towards the mainboard until the slot levers click into place to secure the module. 8. Replace the bottom cover and the screws (see page 2 - 6). 9. Restart the computer to allow the BIOS to register the new memory configuration as it starts up. c. b. a. 2 2 4 1 6. Plate RAM Shielding 4. RAM Module • 4 Screws 2 - 10 Removing the System Memory (RAM) 3 3 Disassembly Removing the M.2 SSD Module Figure 7 M.2 SSD-1 Module Removal M.2 SSD-1 (Intel Optane) Removal Procedure 1. 2. 3. 4. 5. Turn off the computer, turn it over, remove the keyboard (page 2 - 5) and battery (page 2 - 6). The M.2 SSD module will be visible at point 1 on the mainboard (Figure 7a). Remove the screw 2 (Figure 7b). The M.2 SSD module 3 (Figure 7c) will pop-up, and you can remove it from the computer. Reverse the process to install a new module (do not forget to replace the screws and thermal pad). a. a. Locate the M.2 SSD. b. Remove the screw. c. The M.2 SSD module will pop up. c. 3 2.Disassembly 1 b. 2 3 3.M2 SSD Module • 1 Screw Removing the M.2 SSD Module 2 - 11 Disassembly Figure 8 M.2 SSD-1 Module Removal a. Locate the M.2 SSD. b. Remove the screw. c. The M.2 SSD module will pop up. M.2 SSD-1 Removal Procedure 1. 2. 3. 4. 5. Turn off the computer, turn it over, remove the keyboard (page 2 - 5) and battery (page 2 - 6). The M.2 SSD module will be visible at point 1 on the mainboard (Figure 7a). Remove the screw 2 (Figure 7b). The M.2 SSD module 3 (Figure 7c) will pop-up, and you can remove it from the computer. Reverse the process to install a new module (do not forget to replace the screws and thermal pad). a. c. 2.Disassembly 3 1 b. 2 3.M2 SSD Module • 1 Screw 2 - 12 Removing the M.2 SSD Module 3 Disassembly M.2 SSD-2 Removal Procedure 1. 2. 3. 4. 5. Figure 9 Turn off the computer, turn it over, remove the keyboard (page 2 - 5) and battery (page 2 - 6). The M.2 SSD module will be visible at point 1 on the mainboard (Figure 7a). Remove the screw 2 (Figure 7b). The M.2 SSD module 3 (Figure 7c) will pop-up, and you can remove it from the computer. Reverse the process to install a new module (do not forget to replace the screws and thermal pad). a. c. M.2 SSD-2 Module Removal a. Locate the M.2 SSD. b. Remove the screw. c. The M.2 SSD module will pop up. 3 2.Disassembly 1 b. 2 3 3.M2 SSD Module • 1 Screw Removing the M.2 SSD Module 2 - 13 Disassembly Figure 10 Wireless LAN Module Removal 2.Disassembly a. Locate the WLAN. b. Disconnect the cables and remove the screw. c. The WLAN module will pop up. Removing the Wireless LAN Module 1. 2. 3. 4. Turn off the computer, turn it over, remove the keyboard (page 2 - 5) and battery (page 2 - 6). The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a). Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b) The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer. c. a. Note: Make sure you reconnect the antenna cable to the “1 + 2” socket (Figure 10b). 1 5 b. 3 5.Wireless LAN Module 4 2 • 1 Screw 2 - 14 Removing the Wireless LAN Module 5 Disassembly Wireless LAN, Combo Module Cables Note that the cables for connecting to the antennae on WLAN, WLAN & Bluetooth Combo, and LTE modules are not labelled. The cables/covers (each cable will have either a black or transparent cable cover) are color coded for identification as outlined in the table below. Module Type WLAN/WLAN & Bluetooth Combo Antenna Type Cable Color Cable Cover Type WM 1 Black Transparent WM 2 Black White Wireless LAN, Combo Module Cables 2 - 15 2.Disassembly Cable 1 is usually connected to antenna 1 (Main) on the module, and cable 2 to antenna 2 (Aux). Disassembly Figure 11 CCD Removal a. Remove rubber and screws and then carefully release the inner frame of the LCD panel at the points indicated by the arrows. b. Remove the LCD front cover. Removing the CCD 1. Turn off the computer, turn it over to remove the keyboard (page 2 - 5) and battery (page 2 - 6). 2. Lay the computer down on a flat surface with the top case up forming a 120 degree angle. Carefully remove the mylar covers 1 - 2 and screws 3 - 4 . 3. Run your fingers around the inner frame of the LCD panel to lift it up at points 5 - 6 as indicated by the arrows, run your fingers again around the inner frame at point 7 to lift from one corner to the other as indicated by the arrows, and then lift up the outer frame at point 8 as indicated by the arrows (Figure 11e). 4. Remove the LCD front cover 5 (Figure 11b). a. 2.Disassembly 8 5 7 6 1 3 4 2 b. 9. LCD Front Cover • 2 Screws 2 - 16 Removing the CCD 9 Disassembly 5. Disconnect the cable 10 (Figure 12c). 6. Remove the CCD module 11 (Figure 12d). 7. Reverse the process to install a new CCD module. c. 10 Figure 12 CCD Removal (cont’d) c. Disconnect the cable. d. Remove the CCD module. d. 2.Disassembly 11 11. CCD Module Removing the CCD 2 - 17 Disassembly Figure 13 Top Case Removal 1. Turn off the computer, turn it over to remove the keyboard (page 2 - 5), battery (page 2 - 6), HDD (page 2 - 8), RAM (page 2 - 10), SSD module (page 2 - 11) and WLAN (page 2 - 14). 2. Lay the panel down on a flat surface (protection pad) with the top case open forming a 120 degree angle. Carefully disconnect the cables 1 - 4 and remove the screws 5 - 18 (Figure 13a). 3. Lift and remove the heatsink 19 from the mainboard (Figure 13b). a. 2.Disassembly a. Remove screws and heatsink then carefully release the inner frame of the LCD panel at the points indicated by the arrows. b. Remove the LCD front cover. Removing the LCD Module 9 5 6 8 7 3 13 1 17 2 11 10 b. 19. Heat sink 19 • 14 Screws 2 - 18 Removing the LCD Module 4 14 12 15 16 18 Disassembly 4. Remove the screws 20 - 21 from the hinge cover and the screws 22 - 27 from the hinge (Figure 14c). 5. Remove the LCD module 28 while it is open, still forming a 120 degree angle (Figure 14d). 6. Reverse the process to install a new LCD module. c. Figure 14 Top Case Removal (cont’d) c. Remove the screws. d. Remove the LCD module. 22 23 21 24 25 2.Disassembly 20 26 27 d. 28 28. LCD Module • 8 Screws Removing the LCD Module 2 - 19 Disassembly Figure 15 LCD Module Removal e. Remove rubber and screws and then carefully release the inner frame of the LCD panel at the points indicated by the arrows. f. Remove the LCD front cover. 7. Lay the LCD module down on a flat surface. Carefully remove the mylar covers 29 - 30 and screws 31 - 32 . 8. Run your fingers around the inner frame of the LCD panel to lift it up at points 33 - 34 as indicated by the arrows, run your fingers again around the inner frame at point 35 to lift from one corner to the other as indicated by the arrows and then lift up the outer frame at point 36 as indicated by the arrows (Figure 15e). 9. Remove the LCD front cover 37 (Figure 15f). e. 36 2.Disassembly 33 35 34 31 29 32 30 f. 37. LCD Front Cover • 2 Screws 2 - 20 Removing the LCD Module 37 Disassembly 10. Remove the screws 38 - 41 (Figure 12c). 11. Remove the LCD panel 42 (Figure 16b). 12. Reverse the process to install a new LCD panel. Figure 16 LCD Module Removal (cont’d) g. 39 41 40 g. Remove the screws. h. Remove the LCD panel. 2.Disassembly 38 h. 42 42. LCD Panel • 4 Screws Removing the LCD Module 2 - 21 2.Disassembly Disassembly 2 - 22 Appendix A:Part Lists This appendix breaks down the PA70HS(-G) / PA71HS series notebook’s construction into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings. Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure to cross-check any relevant documentation. Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the total number of duplicated parts used. A.Part Lists Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers. A - 1 Part List Illustration Location The following table indicates where to find the appropriate part list illustration. Table A - 1 A.Part Lists Part List Illustration Location A - 2 Part Top page A - 3 Bottom page A - 4 Main Board page A - 5 HDD page A - 6 LCD page A - 7 Top Top Top A - 3 A.Part Lists Figure A - 1 Bottom A.Part Lists Figure A - 2 Bottom A - 4 Bottom Main Board Figure A - 3 Main Board A.Part Lists Main Board A - 5 HDD A.Part Lists Figure A - 4 HDD A - 6 HDD LCD Figure A - 5 LCD A - 7 A.Part Lists LCD A - 8 A.Part Lists Schematic Diagrams Appendix B: Schematic Diagrams This appendix has circuit diagrams of the PA70HS(-G) / PA71HS notebook’s PCB’s. The following table indicates where to find the appropriate schematic diagram. Diagram - Page Diagram - Page Diagram - Page Diagram - Page System Block Diagram - Page B - 2 Frame Buffer Partition C_D - Page B - 23 AR Power - Page B - 44 FBVDDQ - Page B - 65 Processor 1/6 - Page B - 3 GPU Decoupling - Page B - 24 TPS65982ABZQZ - Page B - 45 LED Board - Page B - 66 Straps and XTAL - Page B - 25 USB 3.0 Type C - Page B - 46 LID Board - Page B - 67 Processor 3/6 - Page B - 5 IFP I/O Interface - Page B - 26 PS8338B - Page B - 47 DC Board - Page B - 68 Processor 4/6 - Page B - 6 Misc - GPIO, I2C and ROM - Page B - 27 TPM, CCD, TP - Page B - 48 Power Board - Page B - 69 Processor 5/6 - Page B - 7 NVIDIA Power Sequence - Page B - 28 Connectors - Page B - 49 Click Board - Page B - 70 Processor 6/6 - Page B - 8 GPU NVVDD, FBVDDQ - Page B - 29 Fan, LID, SATA HDD - Page B - 50 Audio Board - Page B - 71 DDR4 CHA SO-DIMM_0 - Page B - 9 GPU GND - Page B - 30 5V, 5VS, 3.3V, 3.3VS, 3.3VA - Page B - 51 USB Board - Page B - 72 DDR4 CHB SO-DIMM_0 - Page B - 10 PCH 1/5 - Page B - 31 1.0DX_VCCSTG/VCCSFR_OC/2.5V - Page B - 52 USB 3.0 Board - Page B - 73 Panel, Inverter - Page B - 11 PCH 2/5 - Page B - 32 1V8_RUN/AON, NV3V3 - Page B - 53 PA7 Card Reader Board 1/4 - Page B - 74 Mini DP Port (Back) - Page B - 12 PCH 3/5 - Page B - 33 PEX_VDD - Page B - 54 PA7 Card Reader Board 2/4 - Page B - 75 Mini DP Port (Front) - Page B - 13 PCH 4/5 - Page B - 34 VDD3, VDD5 - Page B - 55 PA7 Card Reader Board 3/4 - Page B - 76 HDMI Connector - Page B - 14 PCH 5/5 - Page B - 35 DDR 1.2V / 0.6VS - Page B - 56 PA7 Card Reader Board 4/4 - Page B - 77 VGA PCI Express - Page B - 15 KBC IT8587 - Page B - 36 Power 1.0V, VCCIO - Page B - 57 Power Sequence - Page B - 78 GPU Frame Buffer Partition - Page B - 16 RGB and White KB LED - Page B - 37 VCC_Core - Page B - 58 Frame Buffer Partition A - Page B - 17 M.2 PCIE4X SSD - Page B - 38 VCore & VCCGT Output - Page B - 59 Frame Buffer Partition B - Page B - 18 M.2 3G/LTE/WIGIG/WLAN+BT - Page B - 39 VCCSA - Page B - 60 Frame Buffer Partition A_B - Page B - 19 Audio - Page B - 40 AC_In, Charger - Page B - 61 GPU Frame Buffer Partition - Page B - 20 Audio Subwoofer - Page B - 41 NVVDDS - Page B - 62 Frame Buffer Partition C - Page B - 21 Audio Port 1 - Page B - 42 NVVDD 1 - Page B - 63 Frame Buffer Partition D - Page B - 22 AR_TBT - Page B - 43 NVVDD 2 - Page B - 64 SCHEMATIC DIAGRAMS Version Note The schematic diagrams in this chapter are based upon version 6-7P-PA70C-001. If your mainboard (or other boards) are a later version, please check with the Service Center for updated diagrams (if required). B - 1 B.Schematic Diagrams Processor 2/6 - Page B - 4 Table B - 1 Schematic Diagrams System Block Diagram 5 B.Schematic Diagrams D Sheet 1 of 77 System Block Diagram 4 DC BOARD 6-71-PA70C-D02A SHEET 67 AUDIO BOARD 6-71-PA708-D02A SHEET 70 LID BOARD 6-71-PA706-D02A SHEET 66 POWER SWITCH BOARD 6-71-PA70S-D02A SHEET 68 USB3.0 BOARD(W/REDRIVER) 6-71-PA703-D02A SHEET 72 USB3.0 BOARD 6-71-PA703-D12A SHEET 71 PA70 LED BOARD 6-71-PA704-D02A SHEET 65 PA70 CLICK BOARD 6-71-PA702-D02A SHEET 69 PA70 CARD READER BOARD 6-71-PA70Z-D02A SHEET 73~76 3 PCIE*16 <=4.5" 27 MHz DDR4/1.2V/1866, 2133MHz H-processor PROCESSOR N17E-G2 (N17E-G2 8GB) 37.5x37.5mm 2152 Ball SHEET 14~29 <=4.5" BGA1440 <=6" EDP PANEL eDP PS8331B DMI*4 <=6" <=7" SHEET 3 SHEET 10 AUDIO BOARD 5.1 channel 32.768KHz SHEET 36 SPI(Option) 24MHz TPM2.0 (Option) SHEET 35 (RESERVE) SPDIF OUT SHEET 56 AC_IN,CHARGER SHEET 60 SHEET 50 HP OUT NVVDDS SHEET 61 PEX_VDD SHEET 53 FBVDDQ SHEET 64 VCC_CORE,VCCSA SHEET 57 VCORE OUTPUT STAGE SHEET 58 VCCGT SHEET 58 C 3D AMP SV3H612 Front L Front R SHEET 41 23x23mm FCBGA AZALIA LINK 33 MHz LPC SHEET 30~34 24 MHz BIOS SPI 8MB SHEET 35 MIC IN VDD1.0,VCCIO TPA2008D2 AMP SHEET 47 EC ITE 8587A (512KB ROM) H Platform Controller Hub (PCH-H) HM175 SHEET 54 D SHEET 8,9 SHEET 2,3,4,5,6,7 SHEET 55 VDD3,VDD5 5V,3.3V,5VS,3VS 1.0DX_VCCSTG,VCCSFR_OC VPP 2.5V SHEET 51 1V8_AON,1V8_RUN SHEET 52 NV3V3 NVVDD SHEET 62~63 DDR4 SO-DIMM*2 Mini DP*2 SHEET 11,12 SHEET 13 HDMI2.0 K'B RGB BACKLIGHT SHEET57 1 1.2V(VDDQ),0.6VS PA70HS Kabylake System Block Diagram C TOUCH PAD 2 Azalia Codec REALTEK ALC892 INT MIC SHEET 39 SHEET 82 APA2607QBI SUBWOOFER SHEET 40 SHEET 30 EC SMBUS INT. K/B B B PCIE 100 MHz SHEET 35 THERMAL SENSOR SMART FANx3 SMART BATTERY AC-IN RT5 K/B RGB&White Backlight SHEET 2 SHEET 36 SHEET 50 SHEET 60 480 Mbps USB 2.0 USB 3.0 5 Gbps SATA III 6.0Gb/s 2"~7" 1"~12" 3"~9" <8" NGFF M KEY <8" <8" NGFF A KEY AR_TBT 1MB ROM WiGig SSD PCIe 7~8 (USB8) PCIe 9~12 SATA 0 SHEET 42~44 SHEET 38 SHEET 37 USB3.1 TYPE C SHEET 45,46 SATA HDD 7mm SATA 1 SHEET 49 FingerPrint (USB7) (Optional) SHEET 48 CCD (USB9) SHEET 47 NGFF B KEY 3G/LTE USB3.0 P2 (USB2) SHEET 38 A USB3.0 P1 (USB1) USB3.0 P5 (USB5) SHEET 48 (Charging) SHEET 48 (Charging) NGFF M KEY SSD PCIe 15,16 SATA 2 SHEET 75 SHEET 76 (PA7) LAN BOARD A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Size A3 Date: B - 2 System Block Diagram SD 4.0 SOCKET RJ-45 SHEET 74 Title 4 LAN SHEET 37 USB BOARD SHEET 71 5 25 RTS5250 MHz SHEET 73 (PA7) USB3.0 P4 USB3.0 P6 (USB6) (USB4) CARD READER RTL84111 3 2 [01] BLOCK DIAGRAM Document Number SCHEMATIC1 Rev D02A 6-7P-PA70A-001 W ednesday, July 05, 2017 Sheet 1 1 of 77 Schematic Diagrams Processor 1/6 5 4 3 U34C 2 1 SKYLAKE_HALO BGA1440 D VCCIO R533 B E25 D25 [14] PEG_RX1 [14] PEG_RX#1 E24 F24 [14] PEG_RX2 [14] PEG_RX#2 E23 D23 [14] PEG_RX3 [14] PEG_RX#3 E22 F22 [14] PEG_RX4 [14] PEG_RX#4 E21 D21 [14] PEG_RX5 [14] PEG_RX#5 E20 F20 [14] PEG_RX6 [14] PEG_RX#6 E19 D19 [14] PEG_RX7 [14] PEG_RX#7 E18 F18 [14] PEG_RX8 [14] PEG_RX#8 D17 E17 [14] PEG_RX9 [14] PEG_RX#9 F16 E16 [14] PEG_RX10 [14] PEG_RX#10 D15 E15 [14] PEG_RX11 [14] PEG_RX#11 F14 E14 [14] PEG_RX12 [14] PEG_RX#12 D13 E13 [14] PEG_RX13 [14] PEG_RX#13 F12 E12 [14] PEG_RX14 [14] PEG_RX#14 D11 E11 [14] PEG_RX15 [14] PEG_RX#15 F10 E10 24.9_1%_04 PEG_COMP [30] [30] DMI_IT_MR_0_DP DMI_IT_MR_0_DN [30] [30] DMI_IT_MR_1_DP DMI_IT_MR_1_DN [30] [30] DMI_IT_MR_2_DP DMI_IT_MR_2_DN [30] [30] G2 D8 E8 E6 F6 D5 E5 J8 J9 DMI_IT_MR_3_DP DMI_IT_MR_3_DN PEG_RXP[0] PEG_RXN[0] PEG_TXP[0] PEG_TXN[0] PEG_RXP[1] PEG_RXN[1] PEG_TXP[1] PEG_TXN[1] PEG_RXP[2] PEG_RXN[2] PEG_TXP[2] PEG_TXN[2] PEG_RXP[3] PEG_RXN[3] PEG_TXP[3] PEG_TXN[3] PEG_RXP[4] PEG_RXN[4] PEG_TXP[4] PEG_TXN[4] PEG_RXP[5] PEG_RXN[5] PEG_TXP[5] PEG_TXN[5] PEG_RXP[6] PEG_RXN[6] PEG_TXP[6] PEG_TXN[6] PEG_RXP[7] PEG_RXN[7] PEG_TXP[7] PEG_TXN[7] PEG_RXP[8] PEG_RXN[8] PEG_TXP[8] PEG_TXN[8] PEG_RXP[9] PEG_RXN[9] PEG_TXP[9] PEG_TXN[9] PEG_RXP[10] PEG_RXN[10] PEG_TXP[10] PEG_TXN[10] PEG_RXP[11] PEG_RXN[11] PEG_TXP[11] PEG_TXN[11] PEG_RXP[12] PEG_RXN[12] PEG_TXP[12] PEG_TXN[12] PEG_RXP[13] PEG_RXN[13] PEG_TXP[13] PEG_TXN[13] PEG_RXP[14] PEG_RXN[14] PEG_TXP[14] PEG_TXN[14] PEG_RXP[15] PEG_RXN[15] PEG_TXP[15] PEG_TXN[15] B25 A25 PEG_TX_0 PEG_TX#_0 C794 C787 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B24 C24 PEG_TX_1 PEG_TX#_1 C785 C783 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B23 A23 PEG_TX_2 PEG_TX#_2 C782 C778 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B22 C22 PEG_TX_3 PEG_TX#_3 C777 C774 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B21 A21 PEG_TX_4 PEG_TX#_4 C772 C768 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B20 C20 PEG_TX_5 PEG_TX#_5 C766 C764 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B19 A19 PEG_TX_6 PEG_TX#_6 C763 C760 0.22u_10V_X5R_04 0.22u_10V_X5R_04 B18 C18 PEG_TX_7 PEG_TX#_7 C759 C757 0.22u_10V_X5R_04 0.22u_10V_X5R_04 A17 B17 PEG_TX_8 PEG_TX#_8 C756 C755 0.22u_10V_X5R_04 0.22u_10V_X5R_04 C16 B16 PEG_TX_9 PEG_TX#_9 C754 C753 0.22u_10V_X5R_04 0.22u_10V_X5R_04 A15 B15 PEG_TX_10 PEG_TX#_10 C751 C749 0.22u_10V_X5R_04 0.22u_10V_X5R_04 C14 B14 PEG_TX_11 PEG_TX#_11 C748 C744 0.22u_10V_X5R_04 0.22u_10V_X5R_04 A13 B13 PEG_TX_12 PEG_TX#_12 C743 C739 0.22u_10V_X5R_04 0.22u_10V_X5R_04 C12 B12 PEG_TX_13 PEG_TX#_13 C738 C736 0.22u_10V_X5R_04 0.22u_10V_X5R_04 A11 B11 PEG_TX_14 PEG_TX#_14 C735 C731 0.22u_10V_X5R_04 0.22u_10V_X5R_04 C10 B10 PEG_TX_15 PEG_TX#_15 C730 C725 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEG_TX0 [14] PEG_TX#0 [14] D PEG_TX1 [14] PEG_TX#1 [14] PEG_TX2 [14] PEG_TX#2 [14] PEG_TX3 [14] PEG_TX#3 [14] PEG_TX4 [14] PEG_TX#4 [14] PEG_TX5 [14] PEG_TX#5 [14] PEG_TX6 [14] PEG_TX#6 [14] PEG_TX7 [14] PEG_TX#7 [14] PEG_TX8 [14] PEG_TX#8 [14] PEG_TX9 [14] PEG_TX#9 [14] PEG_TX10 [14] PEG_TX#10 [14] C PEG_TX11 [14] PEG_TX#11 [14] Sheet 2 of 77 Processor 1/6 PEG_TX12 [14] PEG_TX#12 [14] PEG_TX13 [14] PEG_TX#13 [14] PEG_TX14 [14] PEG_TX#14 [14] PEG_TX15 [14] PEG_TX#15 [14] PEG_RCOMP DMI_RXP[0] DMI_RXN[0] DMI_TXP[0] DMI_TXN[0] DMI_RXP[1] DMI_RXN[1] DMI_TXP[1] DMI_TXN[1] DMI_RXP[2] DMI_RXN[2] DMI_TXP[2] DMI_TXN[2] DMI_RXP[3] DMI_RXN[3] DMI_TXP[3] DMI_TXN[3] B8 A8 C6 B6 B5 A5 D4 B4 DMI_MT_IR_0_DP DMI_MT_IR_0_DN [30] [30] DMI_MT_IR_1_DP DMI_MT_IR_1_DN [30] [30] DMI_MT_IR_2_DP DMI_MT_IR_2_DN [30] [30] DMI_MT_IR_3_DP DMI_MT_IR_3_DN [30] [30] B SKL_H_CPU PLACE NEAR CPU 2 3.3V P/N 6-17-10420-734 1 RT5 EW TF02-104F4F-N THERM_VOLT [35] R654 20K_1%_04 A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [10,27,38,43,45,48,50,51,52,55,56] 3.3V [3,6,56] VCCIO Size A3 Date: 5 4 3 2 [02] Processor 1/6-DMI/PEG Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 2 of 77 1 Processor 1/6 B - 3 B.Schematic Diagrams C [14] PEG_RX0 [14] PEG_RX#0 Schematic Diagrams Processor 2/6 5 4 BGA1440 D27 E27 D H34 H33 F37 G38 F34 F35 E37 E36 EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] DDI1_AUXP DDI1_AUXN EDP_AUXP EDP_AUXN EDP_DISP_UTIL EDP_RCOMP D29 E29 F28 E28 B29 A29 B28 C28 1 D EDP_DISP_UTIL A33 VCCIO EDP_RCOMP D37 R515 Width = 5mil Space = 25mil lengh = 600mil(max) DDI3_TXP[0] DDI3_TXN[0] DDI3_TXP[1] DDI3_TXN[1] DDI3_TXP[2] DDI3_TXN[2] DDI3_TXP[3] DDI3_TXN[3] A27 B27 2 IEDP_TXP_0 IEDP_TXN_0 IEDP_TXP_1 IEDP_TXN_1 IEDP_TXN_2 IEDP_TXP_2 IEDP_TXN_3 IEDP_TXP_3 C26 IEDP_AUX B26 IEDP_AUX# DDI2_AUXP DDI2_AUXN C34 D34 B36 B34 F33 E33 C33 B33 24.9_1%_04 CLOSE TO CPU ADD I2C 䶂嶗妋 PS8331 ⼙枧panel [8,9,32,44] PROC_AUDIO_CLK PROC_AUDIO_SDI PROC_AUDIO_SDO DDI3_AUXP DDI3_AUXN G27 G25 G29 AUD_AZACPU_SCLK [32] AUD_AZACPU_SDO_R [32] AUD_AZACPU_SDI_R R174 SKL_H_CPU [8,9,32,44] 20_1%_04 AUD_AZACPU_SDI timing issue SMB_CLK_R R100 *0_04 PS8331_IN2_PEQ# SMB_DATA_R R114 *0_04 PS8331_IN1_PEQ# [32] CLOSE TO CPU 3.3VS PS8331_CTL_EN C R111 *4.7K_04 R107 *0_04 C 3.3VS U2 cap near the PS8331B(U4) iGPU [32] SB_IEDP_HPD R477 *0_04 R476 0_04 IEDP_HPD [10] INTEL EDP(INPUT) R139 100K_04 3/31 HPD㓡䓙8331廠↢ nVidia EDP (INPUT) B 1V8_AON IEDP_TXP_0 IEDP_TXN_0 C323 C325 0.1u_10V_X7R_04 IEDP_TXP_0_R 0.1u_10V_X7R_04 IEDP_TXN_0_R IEDP_TXP_1 IEDP_TXN_1 IEDP_TXP_2 IEDP_TXN_2 C341 C342 C324 C326 0.1u_10V_X7R_04 IEDP_TXP_1_R 0.1u_10V_X7R_04 IEDP_TXN_1_R 0.1u_10V_X7R_04 IEDP_TXP_2_R 0.1u_10V_X7R_04 IEDP_TXN_2_R IEDP_TXP_3 IEDP_TXN_3 C343 C344 C319 C320 C339 C340 C321 C322 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 IN2_HPD 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C336 C337 0.1u_10V_X7R_04 DEDP_D3_R 0.1u_10V_X7R_04 DEDP_D#3_R C301 C298 C291 C292 21 22 23 24 25 26 27 0.1u_10V_X7R_04 IEDP_AUX#_R 28 0.1u_10V_X7R_04 IEDP_AUX_R 0.1u_10V_X7R_04 DEDP_D_AUX#_SDA_R29 0.1u_10V_X7R_04 DEDP_D_AUX_SCL_R 30 [25] [25] DEDP_D0 DEDP_D#0 [25] [25] [25] [25] DEDP_D1 DEDP_D#1 DEDP_D2 DEDP_D#2 [25] [25] PS8331B DEDP_D3 DEDP_D#3 IEDP_TXP_3_R IEDP_TXN_3_R DEDP_D0_R DEDP_D#0_R DEDP_D1_R DEDP_D#1_R DEDP_D2_R DEDP_D#2_R 3.3VS R126 10K_04 DGPU GPIO17_IFPD_HPD_R [25] [25] DEDP_D_AUX#_SDA DEDP_D_AUX_SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IN1_D0P IN1_D0N IN1_HPD IN1_D1P IN1_D1N IN1_D2P IN1_D2N GND IN1_D3P IN1_D3N IN2_D0P IN2_D0N IN2_HPD IN2_D1P IN2_D1N IN2_D2P IN2_D2N GND IN2_D3P IN2_D3N 5*9mm 60 59 58 57 56 55 54 53 52 51 VDD3 IN1_AEQ# IN2_AEQ# GND PI0 PC1 SW I2C_CTL_EN IN1_PEQ/SDA_CTL IN2_PEQ/SCL_CTL 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PD VDD3 CA_DET CEXT OUT_D0P OUT_D0N OUT_HPD OUT_D1P OUT_D1N GND OUT_D2P OUT_D2N PC0 OUT_D3P OUT_D3N VDD3 REXT GND OUT_AUXP_SCL OUT_AUXN_SDA VDD3 IN1_SDA IN1_SCL IN2_SDA IN2_SCL VDD3 IN1_AUXN IN1_AUXP IN2_AUXN IN2_AUXP PS8331_IN1_AEQ# PS8331_IN2_AEQ# PS8331_IN1_AEQ# R137 *4.7K_04 PS8331_IN2_AEQ# R131 *4.7K_04 R113 *4.7K_04 R112 *4.7K_04 3.3VS 3.3VS PS8331_IN1_PEQ# L :PORT1 (INTEL) (DEFAULT) H: PORT2 (nVidia) PS8331_PI0 PS8331_PC1 PS8331_SW PS8331_CTL_EN PS8331_IN1_PEQ# PS8331_IN2_PEQ# PS8331_SW [10,26,32,48] ADD I2C 䶂嶗妋 PS8331 ⼙枧panel 3.3VS timing issue PS8331_IN2_PEQ# NEAR PIN 3.3VS PS8331_CA_DET PS8331_CEXT EDP_HPD [10] [10] DP_TXP1 DP_TXN1 [10] [10] DP_TXP2 DP_TXN2 [10] [10] DP_TXP3 DP_TXN3 [10] [10] R79 B R146 *100K_04 DEDP_HPD [10] 100K_04 R99 100K_04 R98 NEAR PIN 100K_04 *220p_50V_NPO_04 220p_50V_NPO_04 A 3.3VS C309 C304 0.1u_10V_X7R_04 0.01u_50V_X7R_04 PIN21 PIN26 *4.7K_04 B R78 4.7K_04 R97 *4.7K_04 R120 *4.7K_04 R118 *4.7K_04 3.3VS L :PORT1 (INTEL) H: PORT2 (NV) (DEFAULT) 3.3VS 3.3VS C285 0.1u_10V_X7R_04 PIN35 *4.7K_04 R129 3.3VS PS8331_PC1 OUTPUT to LCD NEAR PIN 3.3VS R124 3.3VS PS8331BQFN60GTR-A2 QFN60-5X9MM 6-03-83316-031 3.3VS *4.7K_04 4.99K_1%_04 DP_AUX [10] DP_AUX# [10] 61 THERMAL_PAD R140 C332 C317 Q11 BTN3904 M-SOT23-CBE *4.7K_04 R102 3.3VS PS8331_PI0 [10] PS8331_PC0 PS8331_REXT R101 2.2u_6.3V_X5R_04 EDP_HPD PS8331_PC0 3.3VS C286 DP_TXP0 DP_TXN0 C [26] IEDP_AUX# IEDP_AUX E B.Schematic Diagrams DDI1_TXP[0] DDI1_TXN[0] DDI1_TXP[1] DDI1_TXN[1] DDI1_TXP[2] DDI1_TXN[2] DDI1_TXP[3] DDI1_TXN[3] DDI2_TXP[0] DDI2_TXN[0] DDI2_TXP[1] DDI2_TXN[1] DDI2_TXP[2] DDI2_TXN[2] DDI2_TXP[3] DDI2_TXN[3] F26 E26 Sheet 3 of 77 Processor 2/6 3 SKYLAKE_HALO U34D K36 K37 J35 J34 H37 H36 J37 J38 PS8331_SW 3.3VS C287 *4.7K_04 R116 *4.7K_04 R81 1M_04 C761 0.01u_50V_X7R_04 0.1u_10V_X7R_04 PIN49 R117 PS8331_CA_DET PIN60 A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ [23,24,26,27,28,31,52,53,61,62,64] 1V8_AON [2,6,56] VCCIO [8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS Title Size A3 Date: 5 B - 4 Processor 2/6 4 3 2 [03] Processor 2/6-DISPLAY Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 3 of 77 Schematic Diagrams Processor 3/6 5 M_A_DQ[63:0] 4 3 U34A [9] ? SKYLAKE_HALO D B M_A_CB0 M_A_CB1 M_A_CB2 M_A_CB3 M_A_CB4 M_A_CB5 M_A_CB6 M_A_CB7 BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] DDR0_ECC[0] DDR0_ECC[1] DDR0_ECC[2] DDR0_ECC[3] DDR0_ECC[4] DDR0_ECC[5] DDR0_ECC[6] DDR0_ECC[7] DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_CS#[2] DDR0_CS#[3] DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_MA[3] DDR0_MA[4] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_PAR DDR0_ALERT# DDR0_DQSN[0] DDR0_DQSN[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_DQSP[0] DDR0_DQSP[1] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[8] DDR0_DQSN[8] AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1 BGA1440 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_CLK_DDR0 [8] M_A_CLK_DDR#0 [8] M_A_CLK_DDR#1 [8] M_A_CLK_DDR1 [8] AT1 AT2 AT3 AT5 AD5 AE2 AD2 AE5 AD3 AE4 AE1 AD4 AH5 AH1 AU1 M_A_CKE0 M_A_CKE1 [8] [8] M_A_CS#0 M_A_CS#1 [8] [8] M_A_ODT0 M_A_ODT1 [8] [8] M_A_BA0 M_A_BA1 M_A_BG0 AH4 AG4 AD1 [8] [8] [8] M_A_RAS# [8] M_A_W E# [8] M_A_CAS# [8] AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3 M_A_A0 [8] M_A_A1 [8] M_A_A2 [8] M_A_A3 [8] M_A_A4 [8] M_A_A5 [8] M_A_A6 [8] M_A_A7 [8] M_A_A8 [8] M_A_A9 [8] M_A_A10 [8] M_A_A11 [8] M_A_A12 [8] M_A_A13 [8] M_A_BG1 [8] M_A_ACT# [8] AG3 AU5 DDR0_A_PARITY DDR0_A_ALERT# [8] [8] BR5 BL3 BG3 BD3 AB3 V3 R3 M3 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#[3:0] M_A_DQS[7:4] [8] BP5 BK3 BF3 BC3 AA3 U3 P3 L3 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS[3:0] [8] M_A_DQS#[7:4] [8] M_B_CB0 M_B_CB1 M_B_CB2 M_B_CB3 M_B_CB4 M_B_CB5 M_B_CB6 M_B_CB7 [8] AY3 BA3 BT11 BR11 BT8 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 W8 W7 V10 V11 W11 W10 V7 V8 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3] DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_MA[3] DDR1_MA[4] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_PAR DDR1_ALERT# DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSN[6] DDR1_DQSN[7] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSP[6] DDR1_DQSP[7] DDR1_ECC[0] DDR1_ECC[1] DDR1_ECC[2] DDR1_ECC[3] DDR1_ECC[4] DDR1_ECC[5] DDR1_ECC[6] DDR1_ECC[7] DDR1_DQSP[8] DDR1_DQSN[8] AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11 M_B_CLK_DDR0 [9] M_B_CLK_DDR#0 [9] M_B_CLK_DDR#1 [9] M_B_CLK_DDR1 [9] AT8 AT10 AT7 AT11 AF11 AE7 AF10 AE10 AF7 AE8 AE9 AE11 AH10 AH11 AF8 M_B_CKE0 M_B_CKE1 [9] [9] M_B_CS#0 M_B_CS#1 [9] [9] M_B_ODT0 M_B_ODT1 [9] [9] D M_B_RAS# [9] M_B_W E# [9] M_B_CAS# [9] AH8 AH9 AR9 M_B_BA0 M_B_BA1 M_B_BG0 AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9 [9] [9] [9] M_B_A0 [9] M_B_A1 [9] M_B_A2 [9] M_B_A3 [9] M_B_A4 [9] M_B_A5 [9] M_B_A6 [9] M_B_A7 [9] M_B_A8 [9] M_B_A9 [9] M_B_A10 [9] M_B_A11 [9] M_B_A12 [9] M_B_A13 [9] M_B_BG1 [9] M_B_ACT# [9] AJ7 AR8 DDR1_B_PARITY DDR1_B_ALERT# C Sheet 4 of 77 Processor 3/6 [9] [9] BP9 BL9 BG9 BC9 AC9 W9 R9 M9 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS#[3:0] [9] M_B_DQS#[7:4] [9] BR9 BJ9 BF9 BB9 AA9 V9 P9 L9 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS[3:0] [9] M_B_DQS[7:4] [9] B AW9 AY9 DDR CHANNEL B CLOSE TO CPU R527 R541 R544 DDR CHANNEL A 121_1%_04 75_1%_04 100_1%_04 DDR_RCOMP0 G1 DDR_RCOMP1 H1 DDR_RCOMP2 J2 DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2] DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ BN13 BP13 DIMM_DQ_CPU_VREF_A BR13 DIMM_CA_CPU_VREF_A [8] DIMM_DQ_CPU_VREF_B [9] SKL_H_CPU SKL_H_CPU A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 5 4 3 2 [04] Processor 3/6-DDR4 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 4 of 77 1 Processor 3/6 B - 5 B.Schematic Diagrams C BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 1 ? SKYLAKE_HALO U34B M_B_DQ[63:0] BGA1440 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 2 [8] Schematic Diagrams Processor 4/6 5 4 3 2 1 NEAR CPU 1.0V_VCCST 1.0V_VCCST U34E R283 [31] [31] [57] [57] [57] PCH_CPU_BCLK_R_DP PCH_CPU_BCLK_R_DN B31 A32 PCH_CPU_PCIBCLK_R_DP PCH_CPU_PCIBCLK_R_DN D35 C36 R292 [31] 56.2_1%_04 [31] 100_04 D H_CPU_SVIDDAT H_CPU_SVIDALRT# H_CPU_SVIDCLK [31] [31] E31 D31 CPU_24MHZ_R_DP CPU_24MHZ_R_DN PCI_BCLKP PCI_BCLKN CLK24P CLK24N R285 R659 VCCST_PW RGD Sheet 5 of 77 Processor 4/6 R184 [31] TO EC [31] H_PM_DOW N [31] PCH_PECI [35] H_PECI PCH_THERMTRIP# R295 VCCST_PW RGD_CPU 60.4_1%_04 20_1%_04 H_PM_DOW N_R R658 R657 *0402_short [32] BT13 DDR_VTT_PG_CTRL [31] C BH31 BH32 BH29 BR30 H_PROCHOT#_R 499_1%_04 [55] H13 BT31 BP35 BM34 BP31 BT34 J31 [32] H_PW RGD PLTRST_CPU_N [31] H_PM_SYNC *12.1_1%_04 H_PECI_R H_SKTOCC_N PROC_SELECT# H_SKTOCC_N BR33 BN1 BM30 VIDALERT# VIDSCK VIDSOUT PROCHOT# CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] DDR_VTT_CNTL CFG[17] CFG[16] CFG[19] CFG[18] VCCST_PWRGD BPM#[0] BPM#[1] BPM#[2] BPM#[3] PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP# SKTOCC# PROC_SELECT# PROC_TDO PROC_TDI PROC_TMS PROC_TCK PROC_TRST# PROC_PREQ# PROC_PRDY# CATERR# CFG_RCOMP BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19 51_04 R655 51_04 3.3VA CFG2 CFG4 D H_SKTOCC_N R656 R650 100K_04 1K_04 BN23 BP23 BP22 BN22 BR27 BT27 BM31 BT30 SKL_XDP_MBP_0 SKL_XDP_MBP_1 SKL_MBP_2 SKL_MBP_3 BT28 BL32 BP28 BR28 H_TDO BP30 BL30 BP27 H_TRST# H_PREQ# H_PRDY# Ʉ CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted: — 1 = (Default) Normal Operation; No stall. — 0 = Stall. Ʉ CFG[1]: Reserved configuration lane. Ʉ CFG[2]: PCI Express* Static x16 Lane Numbering Reversal. — 1 = Normal operation — 0 = Lane numbers reversed. Ʉ CFG[3]: Reserved configuration lane. Ʉ CFG[4]: eDP enable: — 1 = Disabled. — 0 = Enabled. Ʉ CFG[6:5]: PCI Express* Bifurcation — 00 = 1 x8, 2 x4 PCI Express* — 01 = reserved — 10 = 2 x8 PCI Express* — 11 = 1 x16 PCI Express* Ʉ CFG[7]: PEG Training: — 1 = (default) PEG Train immediately following RESET# de assertion. — 0 = PEG Wait for BIOS for training. Ʉ CFG[19:8]: Reserved configuration lanes. H_TCK H_TRST# [34] H_PREQ# [34] H_PRDY# [34] BT25 CFG_RCOMP R651 49.9_1%_04 SKL_H_CPU 1.0V_VCCST VCCST_PWRGD VDD3 CFG2 B B 100K_04 6 D 1 DISPLAY PORT PRESENCE STRAP S Q17A MTDK3S6R R171 3 ALL_SYS_PW RGD 4 2 G [10,34,35,57] S Q17B MTDK3S6R C389 *0.01u_16V_X7R_04 5 G 0_04 C392 CFG4 *0.1u_10V_X7R_04 H_PROCHOT# D A [35] CFG[6:5] R660 PORT ATTACHED PORT PORT DEVICE EMBEDDED 11: 10: 01: 00: (Default) x16 - Device 1 functions 1 and 2 disabled x8, x8 - Device 1 function 1 enabled ; function 2 disabled Reserved - (Device 1 function 1 disabled ; function 2 enabled) x8,x4,x4 - Device 1 functions 1 and 2 enabled 1K_04 DEFENSIVE PULL DOWN SITE Q51 G H_PROCHOT_EC 1: DISABLED; NO PHYSICAL DISPLAY TO EMBEDDED DISPLAY 0: ENABLED; AN EXTERNAL DISPLAY IS CONNECTED TO THE DISPLAY PORT PCIE PORT BIFURCATION STRAPS 1.0DX_VCCSTG H_PROCHOT_EC 1: (DEFAULT)NORMAL OPERATION; LANE# DEFINITION MATCHES SOCKET PIN MAP DEFINITION 0: LANE REVERSAL VCCST_PW RGD R167 D C970 CFG7 2SK3018S3 47p_50V_NPO_04 A 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training R649 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ *100K_04 [30,31,32,33,34,50] 3.3VA [6,51] 1.0DX_VCCSTG [6,31,32,56,57] 1.0V_VCCST [26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [2,3,6,56] VCCIO CAD Note: Capacitor need to be placed close to buffer output pin Title Size A3 Date: 5 B - 6 Processor 4/6 C PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS R163 1K_04 S B.Schematic Diagrams CPU_VIDALERT_N H_PROCHOT# H_PROCHOT# R296 H_TCK ? SKYLAKE_HALO BGA1440 BCLKP BCLKN 220_04 [57] H_TDO 4 3 2 [05]Processor 4/6-CLK/JTAG/MISC Document Number 6-71-PA700-D02A SCHEMATIC1 W ednesday, July 05, 2017 Sheet 1 5 of Rev D02A 77 Schematic Diagrams Processor 5/6 5 4 3 2 1 ? SKYLAKE_HALO U34J ? SKYLAKE_HALO U34K BGA1440 VCORE BGA1440 D1 E1 E3 E2 ? SKYLAKE_HALO U34I VCCIO AG12 G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27 C BN35 BGA1440 VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VDDQC VCCPLL_OC VCCPLL_OC VCCST VCCSTG VCCSTG VCCPLL VCCPLL VSS RSVD RSVD RSVD RSVD N29 R14 AE29 AA14 R516 [34] [34] PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER *0402_short A36 A37 1.0DX_VCCSTG H29 R223 RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD BR35 BR31 BH30 NCTF NCTF NCTF NCTF NCTF NCTF RSVD RSVD RSVD VCCIO_SENSE VSSIO_SENSE BK28 BJ28 BJ18 BJ16 BK16 BK24 BJ24 BK21 BJ21 BT17 BR17 BK18 BJ34 BJ33 G13 AJ8 BL31 B2 B38 BP1 BR2 C1 C38 VCCIO PLACE CAPS AT BOARD EDGE R226 VCCSA_SENSE VSSSA_SENSE AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38 K13 K14 L13 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 BJ14 BJ13 SKL_H_CPU 1.0V_VCCSFR H28 J28 M38 M37 VCCSA_SENSE [59] VSS_SA_SENSE [59] CPU_TOP_VCCCORE VCORE *100_04 VCCIO_SENSE VSS_IO_SENSE H14 J14 C461 C485 R227 *100_04 SKL_H_CPU B PLACE CAP BACKSIDE VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCEOPIO_SENSE VSSEOPIO_SENSE BP17 BN16 RSVD RSVD BM14 BL14 VCC_OPC_1P8 VCC_OPC_1P8 BJ35 BJ36 RSVD RSVD AT13 AW13 ZVM# MSM# AU13 AY13 ZVM2# MSM2# BT29 BR25 BP25 OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2 VCORE CPU_BACK_VCCCORE C444 C457 C469 C466 C458 C456 C443 10u_4V_X6S_06 10u_4V_X6S_06 VSS_VCORE_SENSE C446 C484 C445 C462 [58] VCORE [8,9,32,51,55] VDDQ [2,3,56] VCCIO [59] VCCSA [5,51] 1.0DX_VCCSTG [51] VCCSFR_OC [56] 1.0V_VCCSFR [5,31,32,56,57] 1.0V_VCCST VCCSA C460 C452 C442 C465 C455 C454 C464 C471 C463 C472 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 *1u_6.3V_X6S_04 1u_6.3V_X6S_04 C542 1u_6.3V_X6S_04 C558 1u_6.3V_X6S_04 C437 1u_6.3V_X6S_04 VCCSFR_OC C438 1u_6.3V_X6S_04 1.0DX_VCCSTG 1u_6.3V_X6S_04 C403 1u_6.3V_X6S_04 C414 1u_6.3V_X6S_04 + *22u_6.3V_X5R_08 C374 22u_6.3V_X5R_06 C809 1u_6.3V_X5R_04 10u_6.3V_X5R_06 C813 1u_6.3V_X5R_04 10u_6.3V_X5R_06 1u_6.3V_X5R_04 C825 C806 10u_6.3V_X5R_06 22u_6.3V_X5R_06 C819 *220u_2V_SMD-V C420 10u_6.3V_X5R_06 VCORE C418 Date: 4 3 2 A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 5 B [57] [57] 22u_6.3V_X6S_08 VCCSA R237 *22u_6.3V_X6S_08 VCCSA C435 *22u_6.3V_X6S_08 VCCSA C436 22u_6.3V_X6S_08 PLACE CAP IN BACK SIDE PLACE CAPS AT BACK VCORE 1.0V_VCCST 10u_4V_X6S_06 1.0V_VCCSFR 10u_4V_X6S_06 10u_4V_X6S_06 VCCVDDQ_CLK 10u_4V_X6S_06 10u_4V_X6S_06 CPU_TOP_VCCSA C410 Sheet 6 of 77 Processor 5/6 *49.9_1%_04 *10u_4V_X6S_06 10u_4V_X6S_06 PLACE CAP BACKSIDE *28mil_short-p PLACE CAP IN BOARD EDGE A C RSVD RSVD RSVD BN15 BM15 VCC_VCORE_SENSE C440 VCCSA VCCEOPIO VCCEOPIO VCCEOPIO BP16 BR16 BT16 SKL_H_CPU VDDQ R229 CPU_BACK_VCCSA RSVD RSVD BP15 BR15 BT15 SKL_H_CPU AROUND_CPU VCCVDDQ_CLK *10u_4V_X6S_06 10u_4V_X6S_06 C439 10u_4V_X6S_06 10u_4V_X6S_06 C441 1u_6.3V_X6S_04 C474 1u_6.3V_X6S_04 C459 10u_4V_X6S_06 C473 10u_4V_X6S_06 C453 VCCOPC_SENSE VSSOPC_SENSE BL22 BM22 VCC_VCORE_SENSE VSS_VCORE_SENSE D RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD BL15 BM16 AG37 AG38 VCC_SENSE VSS_SENSE VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC BJ23 BJ26 BJ27 BK23 BK26 BK27 BL23 BL24 BL25 BL26 BL27 BL28 BM24 VCCIO VDDQ C501 BJ17 BJ19 BJ20 BK17 BK19 BK20 BL16 BL17 BL18 BL19 BL20 BL21 BM17 BN17 VCORE BGA1440 *28mil_short-p NEAR TO CPU PIN G30 VSS RSVD RSVD G3 J3 VCCFUSEPRG RSVD RSVD RSVD RSVD Y12 H30 RSVD RSVD PROC_TRIGIN PROC_TRIGOUT B30 C30 BH13 G11 1.0V_VCCST RSVD_TP RSVD_TP RSVD RSVD F30 E30 VCCVDDQ_CLK VCCSFR_OC RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD H23 30.1_1%_04 J23 R173 RSVD RSVD RSVD J24 H24 BN33 BL34 BM33 BL33 SKYLAKE_HALO [06] Processor 5/6-POWER Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 6 of 77 1 Processor 5/6 B - 7 B.Schematic Diagrams J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34 M35 M36 RSVD_TP RSVD_TP RSVD_TP RSVD_TP *22u_6.3V_X6S_08 D BR1 BT2 VDDQ RSVD_TP RSVD_TP 22u_6.3V_X6S_08 VCCSA RSVD_TP RSVD_TP RSVD_TP RSVD_TP U34G Schematic Diagrams Processor 6/6 5 4 3 U34M ? ? U34F Sheet 7 of 77 Processor 6/6 C BB4 BB3 BB2 BB1 BA38 BA37 BA12 BA11 BA10 BA9 BA8 BA7 BA6 B9 AY34 AY33 AY14 AY12 AW30 AW29 AW12 AW5 AW4 AW3 AW2 AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10 AU9 AU8 AU7 AU6 AT30 AT29 AT6 AR38 AR37 AR14 AR13 AR5 AR4 AR3 AR2 AR1 AP34 AP33 AP12 AP11 AP10 AP9 AP8 AN30 AN29 AN12 AN6 AN5 AM38 AM37 AM12 AM5 AM4 AM3 AM2 AM1 AL34 AL33 AL14 AL12 AL10 AL9 AL8 AL7 AL4 SKYLAKE_HALO BGA1440 BGA1440 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NCTFVSS K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27 C17 C13 C9 BT32 BT26 BT24 BT21 BT18 BT14 BT12 BT9 BT5 BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12 BR7 BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12 BP7 BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12 BN9 BN7 BN4 BN2 BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12 BM9 BM6 BM2 BL29 BK29 BK15 BK14 BJ32 BJ31 BJ25 BJ22 BH14 BH12 BH9 BH8 BH5 BH4 BH1 BG38 BG13 BG12 BF33 BF12 BE29 BE6 BD9 BC34 BC12 BB12 D38 SKL_H_CPU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5 C2 BT36 BT35 BT4 BT3 BR38 2 1 VCCGT SKYLAKE_HALO VCCGT BGA1440 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ? NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6 ? VCCGT U34H BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ37 BJ38 BL36 BL37 BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37 U34N SKYLAKE_HALO BGA1440 ? SKYLAKE_HALO BGA1440 VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AL13 AL29 AL30 AL31 AL32 AL35 AL36 AL37 AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36 SKL_H_CPU B37 B3 A34 A4 A3 SKL_H_CPU VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14 D C VCCGT_SENSE VSSGTX_SENSE VSSGT_SENSE VCCGTX_SENSE AH38 AH35 AH37 AH36 VSSGTX_SENSE VCCGT_SENSE [57] VCCGTX_SENSE VSSGT_SENSE [57] SKL_H_CPU SKL_H_CPU B B PLACE CAP IN BACK SIDE VCCGT C499 C497 C498 22u_6.3V_X6S_08 *22u_6.3V_X6S_08 *22u_6.3V_X6S_08 C508 *22u_6.3V_X6S_08 C554 22u_6.3V_X6S_08 CPU_BACK_VCCGT C878 C476 C555 C550 C551 C552 C503 C877 C475 C549 C553 C496 C483 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_6.3V_X5R_06 10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 1u_6.3V_X6S_04 1u_6.3V_X6S_04 VCCGT C486 10u_6.3V_X5R_06 VCCGT PLACE CAP IN BOARD EDGE VCCGT A A CPU_TOP_VCCGT C540 C477 C480 C481 C524 C515 C535 C478 C506 C514 C489 C482 C517 1u_6.3V_X6S_04 *1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 C536 C525 1u_6.3V_X6S_04 C547 1u_6.3V_X6S_04 C479 *1u_6.3V_X6S_04 C487 1u_6.3V_X6S_04 C530 1u_6.3V_X6S_04 C529 1u_6.3V_X6S_04 C510 22u_6.3V_X6S_08 *220u_2V_SMD-V *220u_2V_SMD-V C528 22u_6.3V_X6S_08 + 22u_6.3V_X6S_08 C579 *22u_6.3V_X6S_08 + *22u_6.3V_X6S_08 VCCGT C578 C509 *22u_6.3V_X6S_08 B.Schematic Diagrams D Y38 Y37 Y14 Y13 Y11 Y10 Y9 Y8 Y7 W34 W33 W12 W5 W4 W3 W2 W1 V30 V29 V12 V6 U38 U37 U6 T34 T33 T14 T13 T12 T11 T10 T9 T8 T7 T5 T4 T3 T2 T1 R30 R29 R12 P38 P37 P12 P6 N34 N33 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 M14 M13 M12 M6 L34 L33 L30 L29 K38 K11 K10 K9 K8 K7 K5 K4 K3 K2 U34L SKYLAKE_HALO [58] VCCGT ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size C Date: 5 B - 8 Processor 6/6 4 3 2 [07] Processor 6/6-POWER/GND Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A Sheet Wednesday, July 05, 2017 1 7 of 77 Schematic Diagrams DDR4 CHA SO-DIMM_0 5 4 3 2 TYPE Channel A SO-DIMM 0[RAM1]RVS H=8mm 1 VDDQ VTT_MEM J_DIMM1A [4] [4] [4] [4] PLACE THE CAP WITHIN 200 MILS FROM THE SODIMM [9,32] D DDR4_DRAMRST# DDR4_DRAMRST# PLACE THE CAP CLOSE TO SODIMM DDR_VREFCA_CHA_DIMM C431 C425 0.1u_10V_X7R_04 M_A_CKE0 M_A_CKE1 [4] [4] M_A_CS#0 M_A_CS#1 [4] [4] M_A_ODT0 M_A_ODT1 C368 C355 C354 10u_6.3V_X5R_06 *10u_6.3V_X5R_06 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 VTT_MEM VDDQ C364 C356 C363 10u_6.3V_X5R_06 1u_6.3V_X5R_04 *10u_6.3V_X5R_06 R240 *240_1%_04 [31] [4] 155 161 DDR4_DRAMRST# 143 116 134 108 DDR_VREFCA_CHA_DIMM 164 CHA_DIMM0=000 CHA_DIMM1=001 CHB_DIMM0=010 CHB_DIMM1=011 月DIMM䪗 䪗㒢㓦 10u_6.3V_X5R_06 DDR_VREFCA_CHA_DIMM C429 R213 B VDDQ 0.1u_10V_X7R_04 1K_1%_04 R217 [4] ACT* PARITY ALERT* EVENT* RESET* VREFCA 254 253 VDDQ 1K_1%_04 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14_WE* A15_CAS* A16_RAS* 114 M_A_ACT# 000 R203 BG0 BG1 BA0 BA1 144 133 132 131 128 126 127 122 125 121 146 120 119 158 151 156 152 [3,9,32,44] SMB_DATA_R [3,9,32,44] SMB_CLK_R C534 ODT0 ODT1 115 113 150 145 [4] DDR0_A_PARITY [4] DDR0_A_ALERT# DIMM0_CHA_EVENT# S0* S1* 1.8_1%_04 DIMM_CA_CPU_VREF_A C432 SDA SCL 166 260 256 SA2 SA1 SA0 92 91 101 105 88 87 100 104 CB0_NC CB1_NC CB2_NC CB3_NC CB4_NC CB5_NC CB6_NC CB7_NC 12 33 54 75 178 199 220 241 96 DM0*/DBI0* DM1*/DBI1* DM2*/DBI2* DM3*/DBI3* DM4*/DBI4* DM5*/DBI5* DM6*/DBI6* DM7*/DBI7* DM8*/DBI8* DQS0_T DQS1_T DQS2_T DQS3_T DQS4_T DQS5_T DQS6_T DQS7_T DQS8_T 0.022u_16V_X7R_04 DQS0_C DQS1_C DQS2_C DQS3_C DQS4_C DQS5_C DQS6_C DQS7_C DQS8_C R212 24.9_1%_04 162 165 C563 M_A_DQ[63:0] [4] 163 160 159 154 153 148 147 142 141 136 135 130 129 124 123 118 117 112 111 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VTT VPP2 VPP1 258 2.5V 259 257 3.3VS VDDSPD MT1 MT2 D 255 C353 C357 0.1u_10V_X7R_04 2.2u_6.3V_X5R_04 GND1 GND2 PLACE NEAR TO PIN 13 34 55 76 179 200 221 242 97 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS[3:0] [4] M_A_DQS[7:4] [4] 11 32 53 74 177 198 219 240 95 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS#[3:0] [4] M_A_DQS#[7:4] [4] 251 247 243 239 235 231 227 223 217 213 209 205 201 197 193 189 185 181 175 171 167 107 103 99 93 89 85 81 77 73 69 65 61 57 51 47 43 39 35 31 27 23 19 15 9 5 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 252 248 244 238 234 230 226 222 218 214 210 206 202 196 192 188 184 180 176 172 168 106 102 98 94 90 86 82 78 72 68 64 60 56 52 48 44 40 36 30 26 22 18 14 10 6 2 C Sheet 8 of 77 DDR4 CHA SODIMM_0 B D4AR0-26001-1P40 D4AR0-26001-1P40 C566 C504 C832 C488 C468 C434 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 C580 A *10u_6.3V_X5R_06 VDDQ VDDQ C591 M_A_DQ5 M_A_DQ0 M_A_DQ2 M_A_DQ3 M_A_DQ1 M_A_DQ4 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ12 M_A_DQ14 M_A_DQ11 M_A_DQ9 M_A_DQ13 M_A_DQ10 M_A_DQ15 M_A_DQ17 M_A_DQ20 M_A_DQ23 M_A_DQ18 M_A_DQ16 M_A_DQ21 M_A_DQ19 M_A_DQ22 M_A_DQ25 M_A_DQ28 M_A_DQ30 M_A_DQ31 M_A_DQ24 M_A_DQ29 M_A_DQ27 M_A_DQ26 M_A_DQ32 M_A_DQ37 M_A_DQ39 M_A_DQ34 M_A_DQ36 M_A_DQ33 M_A_DQ38 M_A_DQ35 M_A_DQ41 M_A_DQ45 M_A_DQ46 M_A_DQ42 M_A_DQ44 M_A_DQ40 M_A_DQ43 M_A_DQ47 M_A_DQ49 M_A_DQ52 M_A_DQ55 M_A_DQ51 M_A_DQ50 M_A_DQ48 M_A_DQ53 M_A_DQ54 M_A_DQ61 M_A_DQ60 M_A_DQ58 M_A_DQ63 M_A_DQ56 M_A_DQ57 M_A_DQ62 M_A_DQ59 S2*/C0 S3*/C1 VDDQ A 8 7 20 21 4 3 16 17 28 29 41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246 C601 C527 C394 C576 C448 C609 C495 *10u_6.3V_X5R_04 *10u_6.3V_X5R_04 10u_6.3V_X5R_04 *10u_6.3V_X5R_04 *10u_6.3V_X5R_04 10u_6.3V_X5R_04 *10u_6.3V_X5R_04 *10u_6.3V_X5R_04 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title + C1107 [6,9,32,51,55] VDDQ [9,55] VTT_MEM [9,51] 2.5V [3,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS *330U_2V_D2_D Size A3 Date: 5 4 3 2 [08] DDR4 CHA SO-DIMM_0 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 8 of 77 1 DDR4 CHA SO-DIMM_0 B - 9 B.Schematic Diagrams C361 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CKE0 CKE1 149 157 M_A_BG0 M_A_BG1 M_A_BA0 M_A_BA1 J_DIMM1B CK0_T CK0_C CK1_T CK1_C 109 110 [4] M_A_A0 [4] M_A_A1 [4] M_A_A2 [4] M_A_A3 [4] M_A_A4 [4] M_A_A5 [4] M_A_A6 [4] M_A_A7 [4] M_A_A8 [4] M_A_A9 [4] M_A_A10 [4] M_A_A11 [4] M_A_A12 [4] M_A_A13 [4] M_A_W E# [4] M_A_CAS# [4] M_A_RAS# 2.5V C [4] [4] [4] [4] [4] [4] *2.2u_6.3V_X5R_04 137 139 138 140 M_A_CLK_DDR0 M_A_CLK_DDR#0 M_A_CLK_DDR1 M_A_CLK_DDR#1 Schematic Diagrams DDR4 CHB SO-DIMM_0 5 4 3 2 1 TYPE H=4mm Channel B SO-DIMM 0[RAM2] RSV J_DIMM2A PLACE THE CAP WITHIN 200 MILS FROM THE SODIMM D [8,32] DDR4_DRAMRST# DDR4_DRAMRST# PLACE THE CAP CLOSE TO SODIMM B.Schematic Diagrams DDR_VREFCA_CHB_DIMM C837 C842 0.1u_10V_X7R_04 *2.2u_6.3V_X5R_04 [4] [4] M_B_CKE0 M_B_CKE1 [4] [4] M_B_CS#0 M_B_CS#1 [4] [4] M_B_ODT0 M_B_ODT1 [4] [4] [4] [4] C362 C369 C371 C370 10u_6.3V_X5R_06 *10u_6.3V_X5R_06 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 VTT_MEM VDDQ C C365 C360 C366 10u_6.3V_X5R_06 1u_6.3V_X5R_04 *10u_6.3V_X5R_06 R241 149 157 155 161 115 113 150 145 M_B_BG0 M_B_BG1 M_B_BA0 M_B_BA1 144 133 132 131 128 126 127 122 125 121 146 120 119 158 151 156 152 *240_1%_04 [4] [31] 109 110 [4] M_B_A0 [4] M_B_A1 [4] M_B_A2 [4] M_B_A3 [4] M_B_A4 [4] M_B_A5 [4] M_B_A6 [4] M_B_A7 [4] M_B_A8 [4] M_B_A9 [4] M_B_A10 [4] M_B_A11 [4] M_B_A12 [4] M_B_A13 [4] M_B_W E# [4] M_B_CAS# [4] M_B_RAS# 2.5V Sheet 9 of 77 DDR4 CHB SODIMM_0 137 139 138 140 [4] M_B_CLK_DDR0 [4] M_B_CLK_DDR#0 [4] M_B_CLK_DDR1 [4] M_B_CLK_DDR#1 114 M_B_ACT# [4] DDR1_B_PARITY [4] DDR1_B_ALERT# DIMM0_CHB_EVENT# DIMM0_CHB_EVENT# DDR4_DRAMRST# 143 116 134 108 DDR_VREFCA_CHB_DIMM 164 254 253 [3,8,32,44] SMB_DATA_R [3,8,32,44] SMB_CLK_R 010 VDDQ B CHA_DIMM0=000 CHA_DIMM1=001 CHB_DIMM0=010 CHB_DIMM1=011 C830 月DIMM䪗 䪗㒢㓦 166 260 256 3.3VS R536 1K_1%_04 10u_6.3V_X5R_06 92 91 101 105 88 87 100 104 C834 R549 0.1u_10V_X7R_04 DDR_VREFCA_CHB_DIMM 1K_1%_04 C839 12 33 54 75 178 199 220 241 96 VDDQ C843 0.1u_10V_X7R_04 0.1u_10V_X7R_04 [4] R551 DIMM_DQ_CPU_VREF_B 1.8_1%_04 C847 0.022u_16V_X7R_04 S0* S1* ODT0 ODT1 BG0 BG1 BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14_WE* A15_CAS* A16_RAS* ACT* PARITY ALERT* EVENT* RESET* VREFCA SDA SCL SA2 SA1 SA0 CB0_NC CB1_NC CB2_NC CB3_NC CB4_NC CB5_NC CB6_NC CB7_NC 24.9_1%_04 VDDQ 10u_6.3V_X5R_06 A 162 165 C956 C911 *10u_6.3V_X5R_06 10u_6.3V_X5R_06 C851 10u_6.3V_X5R_06 C419 10u_6.3V_X5R_06 C521 10u_6.3V_X5R_06 C417 10u_6.3V_X5R_06 C539 10u_6.3V_X5R_06 DQS0_T DQS1_T DQS2_T DQS3_T DQS4_T DQS5_T DQS6_T DQS7_T DQS8_T DQS0_C DQS1_C DQS2_C DQS3_C DQS4_C DQS5_C DQS6_C DQS7_C DQS8_C R550 C826 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CKE0 CKE1 DM0*/DBI0* DM1*/DBI1* DM2*/DBI2* DM3*/DBI3* DM4*/DBI4* DM5*/DBI5* DM6*/DBI6* DM7*/DBI7* DM8*/DBI8* J_DIMM2B VDDQ CK0_T CK0_C CK1_T CK1_C 8 7 20 21 4 3 16 17 28 29 41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246 M_B_DQ0 M_B_DQ5 M_B_DQ7 M_B_DQ3 M_B_DQ4 M_B_DQ2 M_B_DQ1 M_B_DQ6 M_B_DQ9 M_B_DQ14 M_B_DQ13 M_B_DQ15 M_B_DQ8 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ16 M_B_DQ18 M_B_DQ21 M_B_DQ19 M_B_DQ17 M_B_DQ22 M_B_DQ23 M_B_DQ20 M_B_DQ25 M_B_DQ31 M_B_DQ24 M_B_DQ29 M_B_DQ28 M_B_DQ27 M_B_DQ30 M_B_DQ26 M_B_DQ39 M_B_DQ35 M_B_DQ32 M_B_DQ37 M_B_DQ34 M_B_DQ38 M_B_DQ33 M_B_DQ36 M_B_DQ41 M_B_DQ45 M_B_DQ46 M_B_DQ43 M_B_DQ40 M_B_DQ44 M_B_DQ42 M_B_DQ47 M_B_DQ55 M_B_DQ48 M_B_DQ49 M_B_DQ51 M_B_DQ52 M_B_DQ54 M_B_DQ53 M_B_DQ50 M_B_DQ61 M_B_DQ62 M_B_DQ60 M_B_DQ58 M_B_DQ59 M_B_DQ57 M_B_DQ56 M_B_DQ63 M_B_DQ[63:0] [4] 163 160 159 154 153 148 147 142 141 136 135 130 129 124 123 118 117 112 111 VTT_MEM VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VTT VPP2 VPP1 VDDSPD MT1 MT2 255 C358 C359 0.1u_10V_X7R_04 2.2u_6.3V_X5R_04 GND1 GND2 13 34 55 76 179 200 221 242 97 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS[3:0] [4] M_B_DQS[7:4] [4] 11 32 53 74 177 198 219 240 95 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS#[3:0] [4] M_B_DQS#[7:4] [4] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 252 248 244 238 234 230 226 222 218 214 210 206 202 196 192 188 184 180 176 172 168 106 102 98 94 90 86 82 78 72 68 64 60 56 52 48 44 40 36 30 26 22 18 14 10 6 2 C B D4AR0-26001-1P80 PCB Footprint = ddr4_260p_rvs_h40_d4arx S2*/C0 S3*/C1 D4AR0-26001-1P80 PCB Footprint = ddr4_260p_rvs_h40_d4arx A 6-86-24260-000 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ C852 C860 1u_6.3V_X5R_04 5 B - 10 DDR4 CHB SO-DIMM_0 D PLACE NEAR TO PIN 251 247 243 239 235 231 227 223 217 213 209 205 201 197 193 189 185 181 175 171 167 107 103 99 93 89 85 81 77 73 69 65 61 57 51 47 43 39 35 31 27 23 19 15 9 5 1 Title 1u_6.3V_X5R_04 2.5V 259 257 3.3VS VDDQ C971 258 1u_6.3V_X5R_04 C910 1u_6.3V_X5R_04 C430 1u_6.3V_X5R_04 C562 1u_6.3V_X5R_04 4 C590 1u_6.3V_X5R_04 C556 [8,51] 2.5V [6,8,32,51,55] VDDQ [8,55] VTT_MEM [3,8,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS 1u_6.3V_X5R_04 3 2 Size A3 Date: [09] DDR4 CHB SO-DIMM_0 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 9 of 77 Schematic Diagrams Panel, Inverter 3 2 1 DEFAULT SHORT PANEL POWER 2 PJ3 PLVDD C161 4 S2 1u_6.3V_X5R_04 [3] [3] DRX2# DRX2 C723 C722 0.1u_10V_X7R_04 0.1u_10V_X7R_04 DRX3# DRX3 C1143 C1142 0.1u_10V_X7R_04 0.1u_10V_X7R_04 DAUX# DAUX DP_AUX# DP_AUX BRIGHTNESS_R INV_BLON HPD_L VLED PLVDD 2A 1/28 NV CHECK , C connect to J_LCD1_Pin1 R35 [26] S GPIO5_FRAME_LOCK# D C265 10K_04 NV recommend FRAME_LOCK#_R C724 0.1u_50V_Y5V_06 NV recommend 0.01u_50V_X7R_04 GND5 GND4 GND3 GND2 GND1 GND5 GND4 GND3 GND2 GND1 *100K_04 [32,34,35,41,42,50,56] SUSB# *0_04 Q2B *MTS3572G6 PANEL_VCC_EN_R 1 *0_04 PANEL_VCC_EN R73 G1 5VS 1 2 PJ2 R76 *10K_04 LVDD_EN# DEFAULT SHORT 1 S 2 PJ1 PLVDD *3mm U1 2A LVDFH-03008-TP00+ PCB Footprint = lvdfh-030xx-tx00 current = 0.3A 5 VIN 1 VOUT [27,32,35] [10,26] A D1 GC6_FB_EN_PCH [10,31] NVSR䘬PANEL⮶ℍ 暨婳BIOS 䘤ECN ⡆≈NVSR䘬ID D2 BAT54CW H 1 A C 3 2 A NB_ENAVDD GPIO11_PPEN 4 C *RB751S-40H PANEL_VCC_EN EN *100K_04 SY6288E1AAC PCB Footprint = M-SOT23-5 R28 [10,31] A C EDP_HPD AC 1K_04 BRIGHTNESS_R D5 *BAV99 RECTIFIER EDP_HPD C752 [10,31] EDP_BRIGHTNESS VGA_BKLPW M *0402_short 10 PANEL_PW M [10,26] R144 *100K_04 R134 *100K_04 5 8 [10,31] BLON VGA_BKLTEN [3,10,26,32,48] 7 BLON_R 0B0 1B0 VCC A0 GND S0 0B1 1B1 C315 PANEL_VCC_EN *0.1u_10V_X7R_04 9 VCC BLON_R 4 6 A1 GND S1 12 1 3 B *PI5A3158BZAE P/N = 6-03-53158-0J1 PS8331_SW śɥ śɨ L :PORT1 (INTEL) (DEFAULT) H: PORT2 (nVidia) PANEL_PW M BLON VGA_BKLTEN U5 2 11 GPIO11_PPEN PLVDD 3.3V R33 100K_04 PANEL POWER 3.3V U23C 74LVC08APW 14 [10,26] R38 [10,31] NB_ENAVDD [10,26] GPIO11_PPEN *100K_04 [3] D3 BAT54CW H 1 A C 3 2 A R460 *10K_04 R143 [35] 14 R36 3.3VS D21 BAT54CW H 1 A C 3 2 A 100K_04 Sheet 10 of 77 Panel, Inverter 3.3VS 枸䔁 *100K_04 R32 3 OC# [10,26] *220p_50V_NPO_04 C163 *10u_6.3V_X5R_06 *100K_04 R459 C162 R37 㬌悐↮䚖⇵㗗⃰㍸ὃPANEL䴎NV G sync,㓭䚖⇵䠔橼䶂嶗㗗ᶵ䓐 暨䡢娵GS䁢3.3V HPD_L >80 mil 2 GND C D02_03010_ℙ䓐䶂嶗 1u_6.3V_X5R_04 C142 1u_6.3V_X5R_04 2SK3018S3 GPIO11_PPEN B Q4A *MTDK3S6R S Q4B *MTDK3S6R 5G 3.3VS D 2G D *3mm Q1 G 3.3V R63 R74 6 DRX1# DRX1 0.1u_10V_X7R_04 0.1u_10V_X7R_04 1 DP_TXN3 DP_TXP3 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C719 C720 3 [3] [3] C717 C718 *150K_1%_04 R56 *100K_04 4 DP_TXN2 DP_TXP2 DRX0# DRX0 D R57 *4.7K_06 R61 6 DP_TXN1 DP_TXP1 [3] [3] 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C264 *0.22u_50V_Y5V_06 9 BKL_EN 8 BLON_R BLON1 U23B 74LVC08APW 3.3V 4 10 6 BLON2 R132 *100K_04 10 A [3] IEDP_HPD [3] DEDP_HPD [3,10,26,32,48] PS8331_SW L :PORT1 (INTEL) (DEFAULT) H: PORT2 (NV) 5 8 7 U23A 74LVC08APW 3.3VS 0B0 1B0 VCC A0 GND S0 0B1 1B1 VCC A1 GND S1 12 3.3V C333 *0.1u_10V_X7R_04 [35,49] 1 3 7 U23D 74LVC08APW R432 C711 0.1u_10V_X7R_04 12 LID_SW # 11 PANEL_PW M LID_SW #1 100K_04 13 A 9 4 6 DEL LVDS SIGNAL EDP_HPD [5,34,35,57] ALL_SYS_PW RGD ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ *PI5A3158BZAE P/N = 6-03-53158-0J1 [35,39,50,53,54,55,56,57,58,59,60] VIN [11,12,13,36,39,40,41,47,48,49,50,61,62,63,64] 5VS [2,27,38,43,45,48,50,51,52,55,56] 3.3V [3,8,9,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS śɥ śɨ 4 INV_BLON 3 2 Title Size A3 Date: 5 14 7 SB_BLON U4 2 11 [10,31] EDP_BRIGHTNESS [10,26] VGA_BKLPW M *100K_04 SB_BLON 14 *100K_04 [34] 7 R142 R433 1 ἧ䓐eDP㗪,BRIGHTNESS䚜㍍ ㍍⇘EDP CONNECTOR 枸䔁 100K_04 7 5 R436 3 2 [10] PANEL,INVERTER Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 10 of 77 1 Panel, Inverter B - 11 B.Schematic Diagrams [3] [3] 0.1u_10V_X7R_04 C710 C712 C220 VLED 3 D1 C1141 DP_TXN0 DP_TXP0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 *0.1u_50V_Y5V_06 1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 *0.1u_50V_Y5V_06 3.3VS [3] [3] C230 J_LCD1 22u_6.3V_X5R_08 D2 2 C705 D 1 *2mm Q2A *MTS3572G6 VIN G2 2A 5 4 S1 5 PANEL CONNECTOR (For coaxial cable) Schematic Diagrams Mini DP Port (Back) 5 4 3 2 1 MDP_PW R mini-Display Port E (back) U41 PLEASE CLOSE TO CONNECTOR 5 3.3VS C942 R685 4 D_MDP_E#3 Close to Display PORT *0_04 3 10u_6.3V_X5R_06 CO-LAY D 4 D_MDP_E3_L 1 2 *DVI2012F2SF-900T05_08-SHORT R683 *0_04 R674 4 D_MDP_E#2 C959 2 10u_6.3V_X5R_06 D_MDP_E#3_L L34 D_MDP_E3 1 VIN VOUT ᶵ⎗ⷞ SY6288DAAC GND 㚫㺷暣 [12,13,49,50,55] EN# 3 OC# uP7549UMA5-20 PCB Footprint = M-SOT23-5 SUSB D *0_04 3 D_MDP_E#2_L L33 Close to Display PORT D_MDP_E2 frome PS8338B R663 4 D_MDP_E1 *0_04 3 D_MDP_E#1_L D_MDP_E1_L 1 2 L32 *DVI2012F2SF-900T05_08-SHORT R653 *0_04 MDP_PW R MDP_PW R D_MDP_E0 *0_04 2 L27 D_MDP_E#0 R628 D_MDP_E0_L EMI_GND PWR GND 20 D35 MDP_AUX#_SDA 18 AUX_CHN D_MDP_E#2J D_MDP_E2J 17 15 LANE_2N LANE_2P 19 D_MDP_E2_L D_MDP_E#2_L frome NV Close to Display PORT 0.1u_10V_X7R_04 D_MDP_E#3 0.1u_10V_X7R_04 D_MDP_E3 0.1u_10V_X7R_04 D_MDP_E#2 0.1u_10V_X7R_04 D_MDP_E2 0.1u_10V_X7R_04 D_MDP_E#1 0.1u_10V_X7R_04 D_MDP_E1 0.1u_10V_X7R_04 D_MDP_E#0 0.1u_10V_X7R_04 D_MDP_E0 C1009 C1003 C989 C983 C976 C969 C961 C954 [46] MDP_E#3_R [46] MDP_E3_R [46] MDP_E#2_R [46] MDP_E2_R [46] MDP_E#1_R [46] MDP_E1_R [46] MDP_E#0_R [46] MDP_E0_R D_MDP_E3_L D_MDP_E#3_L 6 7 8 9 10 5 4 3 2 1 17 15 D_MDP_E#3J D_MDP_E3J 12 10 LANE_3N LANE_3P D_MDP_E3J D_MDP_E#3J D_MDP_E1J 9 7 LANE_1P GND R335 [46] OUT1_CA_DET 5.1M_04 G_MDPE_CEC OUT1_CA_DET D_MDP_E0J D33 3/18 ㍉岤⺢嬘ἧ䓐20KV ESD R336 D_MDP_E#1_L D_MDP_E1_L D_MDP_E#0_L D_MDP_E0_L 10 9 8 7 6 D_MDP_E#1J D_MDP_E1J 1 2 3 4 5 1M_04 D_MDP_E#0J D_MDP_E0J TVUDF1004AD0 W /O TBT MDP_AUX_SCL AUX_CHP16 16 D_MDP_E2J D_MDP_E#2J TVUDF1004AD0 W /O TBT 20 19 18 GND GND 14 C GND4 GND3 100K_1%_04 D_MDP_E#0_L 4 3 *DVI2012F2SF-900T05_08-SHORT R645 *0_04 inductor for EMI DP ESD W/O LEVELSHIFT 暨ᶲ, NET ⎗SWAP Sheet 11 of 77 Mini DP Port (Back) SHIELD6 SHIELD5 COMMON R641 1 13 12 14 13 R627 D_MDP_E#1J LANE_1N 11 11 100K_1%_04 C 10 6 4 CONFIG2 CONFIG1 3 1 LANE_0P 9 GND 8 8 7 6 D_MDP_E#0J LANE_0N 5 5 4 3 GND HPD 2 C613 0.01u_50V_X7R_04 OUT1_HPD 2 EMI_GND OUT1_HPD [46] 1 GND2 GND1 SHIELD2 SHIELD1 EMI_GND EMR8 EMR5 J_MDP1 C17722-120A9-L P/N = 6-21-14Q00-020 PCB Footprint = C17722-120XX-L 0_04 0_04 EMI_GND 5VS D02_0307_WEY CO-LAY NV TO CONN ᶲẞ W /O TBT B FCM1005KF-121T03 OUT1_HPD MDP_PW R C958 W /O TBT D31 BAV99 RECTIFIER W /O TBT 5 A A S S G S C922 0.1u_10V_X7R_04 W /O TBT Q21A Q21B W /O TBT MTDK3S6R MTDK3S6R 6 1 4 3 D ⛐dGPU㗪DDC / AUX 㗗Multiplax PIN Q47 W /O TBT R625 2SK3018S3 *0_04 0.1u_10V_X7R_04 W /O TBT CO-LAY R825 MDP_E_AUX#_SDA_R R824 D MDP_E_AUX_SCL W /O TBT R828 0_04 C926 S G [25,46] W /O TBT R829 0_04 2 G D Q48 W /O TBT 2SK3018S3 S G D R611 W /O TBT 10K_04 冯R830嶇R831 CO-LAY MDP_E_AUX#_SDA 2 R358 W /O TBT 10K_04 [25,46] G_DP_MODE_R R638 W /O TBT 10K_04 Q22B MTDK3S6R W /O TBT 3 D 5VS NV3V3 Q22A MTDK3S6R W /O TBT 1 4 S D 6 G G 5VS W /O TBT D30 BAT54CW H C 3 220p_50V_NPO_04 W /O TBT MDP_PW R 2 R815 W /O TBT 100K_04 0_04 L29 W /O TBT MDP_E_AUX_SCL_R [46] OUT1_AUXn_SDA [46] OUT1_AUXp_SCL TO PS8338 R827 R826 W /O TBT W /O TBT 0_04 MDP_AUX#_SDA 0_04 MDP_AUX_SCL TBT 0_04 0_04 MDP_AUX#_SDA MDP_AUX_SCL TBT 5 2SK3018S3 Q64 W /O TBT R643 AC MDP_E_HPD TO PS8330B D A [26,32,46] S C TO DP_E B 1 G A R633 10K_04W /O TBT OUT1_CA_DET B C A E B.Schematic Diagrams D_MDP_E#1 0.1u_10V_X7R_04 D_MDP_E#3 0.1u_10V_X7R_04 D_MDP_E3 0.1u_10V_X7R_04 D_MDP_E#2 0.1u_10V_X7R_04 D_MDP_E2 0.1u_10V_X7R_04 D_MDP_E#1 0.1u_10V_X7R_04 D_MDP_E1 0.1u_10V_X7R_04 D_MDP_E#0 0.1u_10V_X7R_04 D_MDP_E0 C1008 C1002 C988 C982 C977 C968 C960 C953 [46] OUT1_D3n [46] OUT1_D3p [46] OUT1_D2n [46] OUT1_D2p [46] OUT1_D1n [46] OUT1_D1p [46] OUT1_D0n [46] OUT1_D0p D_MDP_E2_L 1 2 *DVI2012F2SF-900T05_08-SHORT R668 *0_04 [46] IN_CA_DET IN_CA_DET R359 Q49 W /O TBT BTN3904 M-SOT23-CBE ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ [42,43] VCC3V3_S0_SYS [3,8,9,10,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [10,12,13,36,39,40,41,47,48,49,50,61,62,63,64] 5VS [12,13,14,26,46,52,53,61,62] NV3V3 *10K_04 TBT Title Size A3 Date: 5 B - 12 Mini DP Port (Back) 4 3 2 [11] MINI DP PORT(BACK)_E Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 11 of 77 Schematic Diagrams Mini DP Port (Front) 5 4 3 2 PLEASE CLOSE TO CONNECTOR D MDP_F3#_RE_C C1122 *0.1u_10V_X7R_04 MDP_F3#_RE MDP_F3_RE_C C1119 *0.1u_10V_X7R_04 MDP_F3_RE MDP_F2#_RE_C C1117 *0.1u_10V_X7R_04 MDP_F2#_RE C1111 *0.1u_10V_X7R_04 MDP_F2_RE MDP_F2_RE_C C1109 *0.1u_10V_X7R_04 MDP_F1#_RE MDP_F1_RE_C C1104 *0.1u_10V_X7R_04 MDP_F1_RE MDP_F0_RE_C C1095 *0.1u_10V_X7R_04 MDP_F0_RE C1099 *0.1u_10V_X7R_04 MDP_F0#_RE MDP_F0#_RE_C *0_04 3 D_MDP_F#3 DP ESD W/O LEVELSHIFT 暨ᶲ, NET ⎗SWAP L44 D_MDP_F3 1 2 *DVI2012F2SF-900T05_08-SHORT R759 *0_04 R756 4 D43 D_MDP_F2 D_MDP_F#2 *0_04 3 D_MDP_F#2 D_MDP_F3 D_MDP_F#3 L43 D_MDP_F2 1 2 *DVI2012F2SF-900T05_08-SHORT R755 *0_04 R754 4 D_MDP_F2J D_MDP_F#2J 5 4 3 2 1 CLOSE TO J_MDP2 CONN *0_04 3 5 3.3VS *10u_6.3V_X5R_06 D_MDP_F#0 D_MDP_F0 *0_04 2 4 10 9 8 7 6 D_MDP_F0 C1061 EN# OC# 3 [11,13,49,50,55] D_MDP_F#0J D_MDP_F0J SUSB TVUDF1004AD0 D_MDP_F#0 4 3 *DVI2012F2SF-900T05_08-SHORT R748 *0_04 D 2 uP7549UMA5-20 PCB Footprint = M-SOT23-5 D_MDP_F#1J D_MDP_F1J 1 2 3 4 5 1 10u_6.3V_X5R_06 D38 D_MDP_F#1 D_MDP_F1 D_MDP_F1 L41 VIN VOUT ᶵ⎗ⷞ SY6288DAAC GND 㚫㺷暣 C1081 D_MDP_F#1 MDP_F_PW R U50 D_MDP_F3J D_MDP_F#3J TVUDF1004AD0 1 2 L42 *DVI2012F2SF-900T05_08-SHORT R753 *0_04 R744 1 6 7 8 9 10 SHIELD6 SHIELD5 COMMON GND4 GND3 MDP_F_PW R inductor for EMI 20 5VS G CONN TO MINI DP CONN TO PS8330B DP_TDB_AUX#_F 18 AUX_CHN D_MDP_F#2J D_MDP_F2J 17 15 LANE_2N LANE_2P 19 17 16 D close to P8830B R317 R318 0_04 0_04 C1112 C1118 0.1u_10V_X7R_04 MDP_F2_RE 0.1u_10V_X7R_04 MDP_F2#_RE R319 R320 0_04 0_04 C1120 C1123 0.1u_10V_X7R_04 MDP_F3_RE 0.1u_10V_X7R_04 MDP_F3#_RE 2SK3018S3 Q63 100K_04 15 LANE_0P 9 8 D_MDP_F#1J LANE_1N 11 C Sheet 12 of 77 Mini DP Port (Front) GND 8 7 6 5 LANE_0N 5 D_MDP_F#0J HPD MDP_F_HPD_R 4 3 GND 2 C642 2 1 EMI_GND GND2 GND1 SHIELD2 SHIELD1 J_MDP2 C17722-120A9-L P/N = 6-21-14Q00-020 PCB Footprint = C17722-120XX-L EMR7 EMR3 0_04 0_04 EMI㒢 㒢㓦 EMI_GND 3 10K_04 G NV3V3 *PS8330B Q58 10K_04 G 2SK3018S3 C1124 A 2 R349 MDP_F_AUX#_SDA 100K_1%_04 0.1u_10V_X7R_04 DP_TDB_AUX#_F 0.1u_10V_X7R_04 DP_TDB_AUX_F Q60 2SK3018S3 R760 *0_04 [25] C1121 MDP_F_AUX_SCL ⛐dGPU㗪DDC / AUX 㗗Multiplax PIN Q29A Q29B MTDK3S6R MTDK3S6R 1 4 3 6 R350 100K_1%_04 G R351 A From NV DP_F [25] R369 MDP_F3_RE_C MDP_F3#_RE_C 3 R360 10K_04 MDP_F2_RE_C MDP_F2#_RE_C 4 C 5 1 MDP_F_PW R 1 5VS MDP_F1_RE_C MDP_F1#_RE_C MDP_F_HPD_R C1047 D15 BAT54CW H D [26,32] 2 G 6 MDP_F0_RE_C MDP_F0#_RE_C S 24 23 22 21 20 19 18 17 16 15 14 13 Q28B MTDK3S6R 5 GND OUT0P OUT0N DNC OUT1P OUT1N GND OUT2P OUT2N DNC OUT3P OUT3N C608 To PCH/ PS8338B(NV) Q28A MTDK3S6R S *2.2u_6.3V_X5R_04 B 5VS D 36 35 34 33 32 31 30 29 28 27 26 25 DNC IN0P IN0N EQ(DNC)(CFG1) IN1P IN1N DNC IN2P IN2N OC_0(DNC)(NC) IN3P IN3N HGND MDP_F_PW R U49 S C1023 *0.1u_10V_X7R_04 IN3P_F C1022 *0.1u_10V_X7R_04 IN3N_F 37 38 39 40 41 42 43 44 45 46 47 48 49 1 2 3 4 5 6 7 8 9 10 11 12 C1017 *0.1u_10V_X7R_04 IN2P_F C1016 *0.1u_10V_X7R_04 IN2N_F C1038 A MDP_F_HPD R731 *4.99K_1%_04 R739 *1M_04 R729 *4.7K_04 R722 *4.7K_04 R323 *4.7K_04 *0.1u_10V_X7R_04 G_MDPF_MODE PS8330B_CFG0_F *4.7K_04 PEQ_F *4.7K_04 PS8330B_CFG1_F *4.7K_04 R727 3.3VS R718 3.3VS R324 3.3VS R365 *0.01u_50V_X7R_04 10K_04 G_MDPF_MODE B Q59 BTN3904 M-SOT23-CBE Title wey_12/30 [10,11,13,36,39,40,41,47,48,49,50,61,62,63,64] [11,13,14,26,46,52,53,61,62] [3,8,9,10,11,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] [12] MINI DP(FRONT)_F+PS8330B Size A3 5VS NV3V3 3.3VS Date: 5 11 14 13 D C1021 *0.1u_10V_X7R_04 IN0P_F C1020 *0.1u_10V_X7R_04 IN0N_F PS8330B_CFG1_F C1019 *0.1u_10V_X7R_04 IN1P_F C1018 *0.1u_10V_X7R_04 IN1N_F 3.3VS A CONFIG2 CONFIG1 3 1 S MDP_F3 MDP_F#3 6 4 D_MDP_F0J 12 GND GND 10 G close to P8830B [12,25] [12,25] G_MDPF_CEC G_MDPF_MODE DP_TDB_AUX_F DP_TDB_AUX#_F V3P3 V3P3 DNC(VDDD_DREG)(CEXT) AUTO-EQ(RSTN)(RST#) OC_1(ADDR_EQ)(I2C_ADDR) SDA_DDC OP_0(SCL_CTL)(SCL_CTL/PEQ) SCL_DDC OP_1(SDA_CTL)(SDA_CTL/CFG0) V3P3 V3P3 GND CNTRL(DNC)(REXT) AUX_SRCP CAD_SRC AUX_SRCN HPD_SRC PERICOM(TI)(PARADA)AUX_SNKP CAD_SNK AUX_SNKN HPD_SNK ENABLE(ENABLE)(PD#) V3P3 V3P3 From NV DP_F MDP_F2 MDP_F#2 LANE_1P GND DP_TDB_AUX_F AUX_CHP16 3.3VS *2.2u_6.3V_X5R_04 [12,25] [12,25] 5.1M_04 R366 B MDP_F1 MDP_F#1 9 7 13 *10K_04 C604 [12,25] [12,25] R353 MDP_F_PW R D R329 D_MDP_F1J 0.01u_50V_X7R_04 3.3VS MDP_F0 MDP_F#0 220p_50V_NPO_04 1M_04 PS8330B Repeter 枸䔁 [12,25] [12,25] C1087 D39 BAV99 RECTIFIER R813 LANE_3N LANE_3P D MDP_F3 MDP_F#3 0.1u_10V_X7R_04 MDP_F1_RE 0.1u_10V_X7R_04 MDP_F1#_RE S [12,25] [12,25] 0.1u_10V_X7R_04 MDP_F0_RE 0.1u_10V_X7R_04 MDP_F0#_RE C1105 C1110 D MDP_F2 MDP_F#2 C1096 C1100 0_04 0_04 12 10 S MDP_F1 MDP_F#1 [12,25] [12,25] 0_04 0_04 R315 R316 D_MDP_F#3J D_MDP_F3J C [12,25] [12,25] R313 R314 MDP_F_HPD_R FCM1005KF-121T03 2 G MDP_F0 MDP_F#0 L11 E [12,25] [12,25] A C 0_04 AC R343 C S 20 19 18 14 MDP_F_HPD PWR GND 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 12 of 77 1 Mini DP Port (Front) B - 13 B.Schematic Diagrams MDP_F1#_RE_C R763 4 1 mini-Display Port F (FRONT) Close to Display PORT CO-LAY Schematic Diagrams HDMI Connector 5 4 2 1 HDMI_5VS 5VS 18 HDMI_SDA-C 16 14 R262 C516 *180_1%_04 TMDS_CLOCK TMDS_CLOCK#J TMDS_CLOCK# TMDS_CLOCKJ 12 10 1.5P_50V_04 TMDS_DATA1 TMDS_DATA1# R269 *180_1%_04 TMDS_DATA1#J 6 TMDS_DATA1J 4 2 R244 TMDS_DATA0 Sheet 13 of 77 HDMI Connector EMR6 EMR4 *180_1%_04 +5V DDC/CEC GND SDA SCL RESERVED CEC TMDS CLOCKCLK SHIELD TMDS CLOCK+ TMDS DATA0SHIELD0 TMDS DATA0+ TMDS DATA1SHIELD1 TMDS DATA1+ TMDS DATA2SHIELD2 0_04 0_04 TMDS DATA2+ EMI_GND GND1 GND2 GND3 GND4 TMDS_DATA2 TMDS_DATA2# GND GND GND GND TMDS_DATA0# R275 *180_1%_04 S HDMI_HPD D R190 WEY_12/13 15 HDMI_SCL-C 13 HDMI_CEC R186 2K_04 R219 20K_04 17 A C A HDMI_HPD-C HDMI_HPD-C 19 2K_04 HDMI_SCL-C HDMI_SDA-C HDMI_HPD-C D7 D9 D10 D 11 9 TMDS_DATA0#J 7 TMDS_DATA0J 5 3 TMDS_DATA2#J 1 TMDS_DATA2J EMI_GND [25] [25] [25] [25] [25] [25] HDMI_DATA2P HDMI_DATA2N HDMI_DATA1P HDMI_DATA1N HDMI_DATA0P HDMI_DATA0N [25] [25] HDMI_CLOCKP HDMI_CLOCKN PCB Footprint = c-16-a197x TMDS_DATA0 TMDS_DATA0# TMDS_CLOCK TMDS_CLOCK# EMI_GND C541 C546 C531 C526 C502 C507 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C519 C513 0.1u_10V_X7R_04 0.1u_10V_X7R_04 TMDS_DATA2_R TMDS_DATA2#_R TMDS_DATA1_R TMDS_DATA1#_R TMDS_DATA0_R TMDS_DATA0#_R 6 7 8 9 10 TMDS_DATA0#_R R248 TMDS_DATA0_R R242 TMDS_DATA2#_R R279 TMDS_DATA2_R R273 TMDS_CLOCK#_R R249 TMDS_CLOCK_R R264 TMDS_DATA1#_R R265 TMDS_DATA1_R R271 TMDS_DATA0J TMDS_DATA0#J 5 4 3 2 1 R274 R278 R270 R268 R243 R247 TMDS_CLOCK_R R263 TMDS_CLOCK#_R R252 HDMI ESD W/O LEVELSHIFT 暨ᶲ, NET ⎗SWAP Jalen_swap12/30 D12 16-A1970-1A03-0 PIN GND1~4=GND 6-21-14230-019 C TMDS_CLOCKJ TMDS_CLOCK#J 0_04 0_04 0_04 0_04 0_04 0_04 TMDS_DATA2 TMDS_DATA2# TMDS_DATA1 TMDS_DATA1# TMDS_DATA0 TMDS_DATA0# 0_04 0_04 TMDS_CLOCK TMDS_CLOCK# 499_1%_04 499_1%_04 499_1%_04 499_1%_04 499_1%_04 499_1%_04 499_1%_04 499_1%_04 C Jalen_swap12/30 TMDS_DATA2# TMDS_DATA2 NV3V3 TMDS_DATA1# TMDS_DATA1 R178 10K_04 10 9 8 7 6 1 2 3 4 5 5VS G TMDS_DATA2#J TMDS_DATA2J TMDS_DATA1#J TMDS_DATA1J Q20 2SK3018S3 2 R195 10K_04 TVUDF1004AD0 D14 S wey_1215 NV3V3 D GND_HDMI G 1 HDMI_CTRLDATA 5 TVUDF1004AD0 HDMI_SDA-C 3/18 ㍉岤⺢嬘ἧ䓐20KV ESD HDMI_SCL-C 3 D S HDMI_CTRLCLK 6 Q18A MTDK3S6R G [25] 4 D [25] S B.Schematic Diagrams 8 HOT PLUG DETECT C 22u_6.3V_X5R_08 3 AC OC# BAV99 RECTIFIER EN# uP7549UMA5-20 PCB Footprint = M-SOT23-5 BAV99 RECTIFIER 4 SUSB BAV99 RECTIFIER D Q19 2SK3018S3 AC 22u_6.3V_X5R_08 1M_04 [26,32] 1,12,49,50,55] D8 0_06 R208 J_HDMI1 C864 A kai_11/18 C859 2 C 1 G VIN VOUT ᶵ⎗ⷞ SY6288DAAC 㚫㺷暣 GND AC *10u_6.3V_X5R_06 C U33 5 C850 For ESD 3.3VS CO-LAY A HDMI_5VS 3 HDMI CONNECTOR Q18B MTDK3S6R B B A A [11,12,14,26,46,52,53,61,62] NV3V3 [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [51,54,56] VREG5 [3,23,24,26,27,28,31,52,53,61,62,64] 1V8_AON [3,8,9,10,11,12,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [10,11,12,36,39,40,41,47,48,49,50,61,62,63,64] 5VS ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 5 B - 14 HDMI Connector 4 3 2 [13] HDMI 2.0 6-71-PA700-D02A Document Number SCHEMATIC1 W ednesday, July 05, 2017 Sheet 1 13 Rev D02A of 77 Schematic Diagrams VGA PCI Express 1 2 U22A INS16508609 3 NV PCI EXPRESS 4 under GPU Midway btw GPU&VR 1/23 PCI_EXPRESS PEX_VDD under GPU [27] R803 *10K_04 GPU_PEX_RST# PEX_CLKREQ# PEG_TX5 PEG_TX#5 PEG_RX6 PEG_RX#6 [2] [2] PEG_TX6 PEG_TX#6 [2] [2] PEG_RX7 PEG_RX#7 [2] [2] PEG_TX7 PEG_TX#7 [2] [2] PEG_RX8 PEG_RX#8 [2] [2] PEG_TX8 PEG_TX#8 [2] [2] PEG_RX9 PEG_RX#9 [2] [2] PEG_TX9 PEG_TX#9 [2] [2] PEG_RX10 PEG_RX#10 [2] [2] PEG_TX10 PEG_TX#10 [2] [2] PEG_RX11 PEG_RX#11 [2] [2] PEG_TX11 PEG_TX#11 [2] [2] PEG_RX12 PEG_RX#12 [2] [2] PEG_TX12 PEG_TX#12 [2] [2] PEG_RX13 PEG_RX#13 [2] [2] PEG_TX13 PEG_TX#13 [2] [2] PEG_RX14 PEG_RX#14 [2] [2] PEG_TX14 PEG_TX#14 [2] [2] PEG_RX15 PEG_RX#15 [2] [2] PEG_TX15 PEG_TX#15 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX5 PEX_RX5# C312 C308 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX6 PEX_RX6# C307 C306 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX7 PEX_RX7# C305 C303 C302 C300 C297 C295 C294 C290 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX8 PEX_RX8# PEX_TX3 PEX_TX3 BL30 BK30 PEX_RX3 PEX_RX3 BF29 BE29 PEX_TX4 PEX_TX4 BK32 BL32 PEX_RX4 PEX_RX4 BF30 BG30 PEX_TX5 PEX_TX5 PEX_RX5 PEX_RX5 BG32 BH32 PEX_TX6 PEX_TX6 BL33 BK33 PEX_RX6 PEX_RX6 BF32 BE32 PEX_TX7 PEX_TX7 BK35 BL35 PEX_RX7 PEX_RX7 BF33 BG33 PEX_TX8 PEX_TX8 BM35 BM36 PEX_RX8 PEX_RX8 BG35 BH35 PEX_TX9 PEX_TX9 BL36 BK36 PEX_RX9 PEX_RX9 BF35 BE35 PEX_TX10 PEX_TX10 BK38 BL38 PEX_RX10 PEX_RX10 PEX_RX11 BF36 PEX_RX11# BG36 PEX_TX11 PEX_TX11 PEX_RX9 PEX_RX9# PEX_RX10 PEX_RX10# BM38 BM39 PEX_RX11 PEX_RX11 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX12 BG38 PEX_RX12# BH38 PEX_TX12 PEX_TX12 BL39 BK39 PEX_RX12 PEX_RX12 C282 C275 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX13 PEX_RX13# BF38 BE38 PEX_TX13 PEX_TX13 BK41 BL41 PEX_RX13 PEX_RX13 PEX_RX14 BF39 PEX_RX14# BG39 PEX_TX14 PEX_TX14 BM41 BM42 PEX_RX14 PEX_RX14 PEX_RX15 BH41 PEX_RX15# BG41 PEX_TX15 PEX_TX15 BL42 BK42 PEX_RX15 PEX_RX15 C271 C267 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 C727 DG P.91 recommend voltage C728 C277 Sheet 14 of 77 VGA PCI Express B 1V8_RUN BB30 PEX_PLL_HVDD_SVDDR34 DG P.91 recommend voltage 0_04 C155 GND C NV3V3 C288 C284 C274 C272 C179 C165 GND PEX_PLL_HVDD BM32 BM33 C144 0.1u_10V_X7R_04 C [2] [2] [2] [2] C314 C313 PEX_RX4 PEX_RX4# PEX_RX2 PEX_RX2 BG29 BH29 C172 DG P.252 recommend CLKREQ , is OD pin , must have a 10k pull up to 1V8_AON [27,62] R122 NVVDD_PW RGD [31] D PEG_CLKREQ# Q14 2SK3018S3 10K_04 PEX_CLKREQ# S R123 *10K_04 D ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ PEX_TERMP BL44 PEX_TERMP R421 Title 2.49K_1%_04 [11,12,13,26,46,52,53,61,62] [25,53] [15,23,24,28,52] NV3V3 PEX_VDD 1V8_RUN GND Size A3 Date: 1 2 3 4 [14] VGA PCI Express Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 14 of 77 5 VGA PCI Express B - 15 B.Schematic Diagrams PEG_RX5 PEG_RX#5 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_TX2 PEX_TX2 C176 22u_6.3V_X6S_08 [2] [2] C327 C316 BF27 BG27 BM29 BM30 C167 *10u_6.3V_X5R_06 PEG_TX4 PEG_TX#4 A 1V8_RUN 10u_6.3V_X5R_06 PEG_RX4 PEG_RX#4 [2] [2] 22u_6.3V_X6S_08 [2] [2] PEX_RX3 PEX_RX3# C82 GND 4.7u_6.3V_X6S_06 PEG_TX3 PEG_TX#3 0.22u_10V_X5R_04 0.22u_10V_X5R_04 BB26 BB27 BB29 BB32 BC26 BC27 BC29 BC30 BC32 BD27 BD30 C94 *10u_4V_X6S_06 [2] [2] C334 C328 PEX_RX2 PEX_RX2# PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD PEX_HVDD 4.7u_6.3V_X6S_06 PEG_RX3 PEG_RX#3 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_RX1 PEX_RX1 C121 C111 4.7u_6.3V_X6S_06 [2] [2] C345 C335 PEX_TX1 PEX_TX1 BK29 BL29 1u_6.3V_X6S_04 PEG_TX2 PEG_TX#2 BF26 BE26 C129 4.7u_6.3V_X6S_06 PEG_RX2 PEG_RX#2 [2] [2] PEX_RX0 PEX_RX0 C136 1u_6.3V_X6S_04 [2] [2] PEX_RX1 PEX_RX1# PEX_TX0 PEX_TX0 BL27 BK27 C119 1u_6.3V_X6S_04 PEG_TX1 PEG_TX#1 0.22u_10V_X5R_04 0.22u_10V_X5R_04 BG26 BH26 C133 1u_6.3V_X6S_04 [2] [2] C347 C346 PEX_RX0 PEX_RX0# PEX_REFCLK PEX_REFCLK 1u_6.3V_X6S_04 PEG_TX0 PEG_TX#0 PEG_RX1 PEG_RX#1 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PEX_CLKREQ 1u_6.3V_X6S_04 [2] [2] [2] [2] B C352 C349 PEG_RX0 PEG_RX#0 BL26 BM26 BM27 *1u_6.3V_X6S_04 [2] [2] D VGA_PEXCLK VGA_PEXCLK# VGA_PEXCLK VGA_PEXCLK# PEX_RST BB33 BB35 BB36 BC33 BC35 BC36 BD33 BD36 1u_6.3V_X6S_04 A [31] [31] BK26 PEX_DVDD PEX_DVDD PEX_DVDD PEX_DVDD PEX_DVDD PEX_DVDD PEX_DVDD PEX_DVDD G GND 5 1/28 Cap follow reference board design , x6s Schematic Diagrams GPU Frame Buffer Partition 1 2 3 U22B INS16512652 4 5 6 7 8 U22C INS16511324 PAGE3: GPU FRAME BUFFER PARTITION A/B 3/23 FBB 2/23 FBA B.Schematic Diagrams A Sheet 15 of 77 GPU Frame Buffer Partition B C FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 U51 U48 U50 U49 R51 R50 R47 U46 V46 Y45 Y47 Y46 V50 V47 U52 V51 AJ44 AG48 AJ45 AG49 AF46 AF47 AF48 AD47 AD49 AD48 AC46 AC47 AA47 AA46 AA45 Y44 AW51 BA52 AW50 BA51 BA50 BB50 BA49 AW49 AV48 AT49 AT47 AT48 AT46 AV51 AV52 AV49 AJ48 AJ46 AJ47 AK49 AM47 AM46 AN48 AN49 AM44 AM45 AN45 AN46 AR48 AN47 AR47 AR46 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7 U47 Y48 AG47 AC48 BB51 AV50 AM48 AR49 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7 R48 V48 AF44 AA48 BB52 AT50 AK48 AR51 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32 FBA_CMD33 FBA_CMD34 FBA_CMD35 Y51 Y52 Y49 AA52 AA51 AA50 AC50 AC51 AC52 AC49 AD52 AD51 AD50 AF50 AF51 AF52 AN50 AN51 AN52 AM49 AM52 AM51 AM50 AK50 AK51 AK52 AJ49 AJ52 AJ51 AJ50 AG50 AG51 AG52 AF49 Y50 AR50 FBA_DBG_RFU1 FBA_DBG_RFU2 AA44 AN44 FBA_CLK0 FBA_CLK0 FBA_CLK1 FBA_CLK1 AG45 AG46 AK46 AK45 FBA_WCK01 FBA_WCK01 FBA_WCKB01 FBA_WCKB01 FBA_WCK23 FBA_WCK23 FBA_WCKB23 FBA_WCKB23 FBA_WCK45 FBA_WCK45 FBA_WCKB45 FBA_WCKB45 FBA_WCK67 FBA_WCK67 FBA_WCKB67 FBA_WCKB67 FBA_DBI[7..0] FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBB_EDC[7..0] [16] FBA_CMD[31..0] FBA_D[63..0] FBB_DBI[7..0] [16] FBA_EDC[7..0] FBA_CMD[31..0] FBA_D[63..0] FBB_D[63..0] [16] GB3B-256 ch0 0..31 1.35V FBVDDQ R14 *60.4_1%_04 R18 *60.4_1%_04 FBA_DEBUG0 FBA_DEBUG1 FBA_CLK0 FBA_CLK0* FBA_CLK1 FBA_CLK1* U45 U44 V45 V44 AC45 AC44 AD46 AD45 AV47 AV46 AW48 AW47 AR45 AR44 AT45 AT44 FB_CLK DP_FBA_CLK0 DP_FBA_CLK0 FB_CLK DP_FBA_CLK1 FB_CLK DP_FBA_CLK1 FBA_WCK01 FBA_WCK01* FBA_WCK01 FBA_WCK23 FBA_WCK23* FBA_WCK23 FBA_WCK45 FBA_WCK45* FBA_WCK45 FB_WCK FB_WCK FBA_WCK01 FB_WCK FB_WCK FBA_WCK23 FB_WCK FB_WCK FBA_WCK45 FBA_WCK67 FBA_WCK67* FBA_CLK0 FBA_CLK0* FBA_CLK1 FBA_CLK1* FB_CLK FB_WCK FBA_WCK67 FBA_WCK01 FBA_WCK01* [16] [16] FBA_WCK23 FBA_WCK23* [16] [16] FBA_WCK45 FBA_WCK45* [16] [16] FBA_WCK67 FBA_WCK67* FB_WCK FBA_WCK67 [16] [16] [16] [16] [16] [16] PLACE AT BALLS FBA_PLL_AVDD FB_PLL_AVDD AN42 GND GND GND GND GND GND GND GND FBB_CMD[31..0] [16] FBB_DBI[7..0] [17] FBB_EDC[7..0] FBB_CMD[31..0] FBB_D[63..0] L2 . HCB1608KF-300T60 CMD0 CAS* CMD1 CKE* CMD2 RST* CMD3 RAS* CMD4 A1_A9 CMD5 A0_A10 CMD6 A12_RFU CMD7 ABI* CMD8 A6_A11 CMD9 A7_A8 CMD10 WE* CMD11 A5_BA1 CMD12 A4_BA2 CMD13 A2_BA0 CMD14 A3_BA3 CMD15 CS* ch1 32..63 CMD16 CAS* CMD17 CKE* CMD18 RST* CMD19 RAS* CMD20 A1_A9 CMD21 A0_A10 CMD22 A12_RFU CMD23 ABI* CMD24 A6_A11 CMD25 A7_A8 CMD26 WE* CMD27 A5_BA1 CMD28 A4_BA2 CMD29 A2_BA0 CMD30 A3_BA3 CMD31 CS* [17] [17] [17] GDDR5 Mode F Mapping C106 W47 W49 W51 W6 W8 Y14 Y15 Y16 FBA_DBI[7..0] FBA_EDC[7..0] FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 H32 D32 A33 B32 E32 G32 J30 F32 H36 G36 J36 F36 F33 D33 J32 G33 E45 D45 F45 G45 D42 E42 F42 H41 E41 F39 E39 D39 F38 E38 D36 E36 M50 P48 M51 M49 P47 P52 R46 P46 L50 L51 L52 L49 M46 L47 M48 M47 D48 C50 C48 C49 E49 E50 F49 F48 F50 D52 J50 H48 H51 J51 H49 H52 FBB_DBI0 FBB_DBI1 FBB_DBI2 FBB_DBI3 FBB_DBI4 FBB_DBI5 FBB_DBI6 FBB_DBI7 FBB_EDC0 FBB_EDC1 FBB_EDC2 FBB_EDC3 FBB_EDC4 FBB_EDC5 FBB_EDC6 FBB_EDC7 22u_4V_X6S_06 GND C32 E33 E44 G39 P49 L48 D50 H50 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 B33 E35 G44 H38 P50 J48 D51 F51 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 GND GND GND GND GND GND GND GND FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 FBB_CMD32 FBB_CMD33 FBB_CMD34 FBB_CMD35 B35 A35 D35 A36 B36 C36 C38 B38 A38 D38 A39 B39 C39 C41 B41 A41 B49 A49 A48 D47 A47 B47 C47 C45 B45 A45 D44 A44 B44 C44 C42 B42 A42 D41 C35 B50 FBB_DBG_RFU1 FBB_DBG_RFU2 J35 J41 FBB_CLK0 FBB_CLK0 FBB_CLK1 FBB_CLK1 H42 G42 F47 E47 FBB_CLK0 FBB_CLK0* FBB_CLK1 FBB_CLK1* FBB_WCK01 FBB_WCK01 FBB_WCKB01 FBB_WCKB01 FBB_WCK23 FBB_WCK23 FBB_WCKB23 FBB_WCKB23 FBB_WCK45 FBB_WCK45 FBB_WCKB45 FBB_WCKB45 FBB_WCK67 FBB_WCK67 FBB_WCKB67 FBB_WCKB67 J33 H33 G35 H35 J39 H39 F41 G41 L46 L45 M44 M45 H47 H46 J47 J46 FBB_WCK01 FBB_WCK01* A 1.35V FBVDDQ R29 *60.4_1%_04 R19 *60.4_1%_04 FBB_DEBUG0 FBB_DEBUG1 B DP_FBB_CLK0 FB_CLK DP_FBB_CLK0 FB_CLK DP_FBB_CLK1 FB_CLK DP_FBB_CLK1 FB_CLK FBB_WCK01 FB_WCK FBB_WCK01 FB_WCK FBB_WCK23 FBB_WCK23* FBB_WCK23 FB_WCK FBB_WCK23 FB_WCK FBB_WCK45 FBB_WCK45* FBB_WCK45 FB_WCK FBB_WCK45 FB_WCK FBB_WCK67 FBB_WCK67* FBB_WCK67 FB_WCK FBB_WCK67 FB_WCK FBB_CLK0 FBB_CLK0* FBB_CLK1 FBB_CLK1* [17] [17] [17] [17] FBB_WCK01 FBB_WCK01* [17] [17] FBB_WCK23 FBB_WCK23* [17] [17] FBB_WCK45 FBB_WCK45* [17] [17] FBB_WCK67 FBB_WCK67* [17] [17] C PLACE AT BALLS FBB_PLL_AVDD L38 FB_PLL_AVDD FB_PLL_AVDD [15,19] 1V8_RUN C92 0.1u_10V_X7R_04 FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 GND FBVDDQ C168 0.1u_10V_X7R_04 GND FBVDDQ GND FB_PLL_AVDD GND AF42 L29 FB_REFPLL_AVDD0 FB_REFPLL_AVDD1 R9 10K_04 C107 R12 10K_04 R27 10K_04 R10 10K_04 C122 D 0.1u_10V_X7R_04 0.1u_10V_X7R_04 FBA_CMD1 FBA_CMD17 FBB_CMD1 FBB_CMD17 FBA_CMD2 FBA_CMD18 FBB_CMD2 FBB_CMD18 R13 10K_04 GND D R2 10K_04 R11 10K_04 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ R26 10K_04 Title [15,19] FB_PLL_AVDD [14,23,24,28,52] 1V8_RUN [16,17,18,19,20,21,22,23,28,64] FBVDDQ GND Date: 1 B - 16 GPU Frame Buffer Partition 2 3 4 5 6 [15] GPU Frame Buffer Partition Size Document Number Custom SCHEMATIC1 GND 7 Rev D02A 6-71-PA700-D02A Wednesday, July 05, 2017 Sheet 15 8 of 77 Schematic Diagrams Frame Buffer Partition A 1 [15] [15] [15] [15] [15] [15] [15] [15] 2 FBA_WCK01 FBA_WCK01* FBA_WCK23 FBA_WCK23* FBA_WCK45 FBA_WCK45* FBA_WCK67 FBA_WCK67* FBA_W CK01 FBA_W CK01* FBA_W CK23 FBA_W CK23* FBA_W CK45 FBA_W CK45* FBA_W CK67 FBA_W CK67* 3 [15] 4 5 6 7 8 FBA_CMD[31..0] FBA_CMD[31..0] FRAME BUFFER PARTITION A FBA_D[63..0] [15] FBA_D[63..0] [15] FBA_DBI[7..0] [15] FBA_EDC[7..0] FBA_DBI[7..0] FBA_EDC[7..0] M2D INS16517002 A NORMAL M3D INS16516134 M3B MIRRORED INS16516336 x32 V4 V2 T4 T2 N4 N2 M4 M2 FBA_EDC0 FBA_DBI0 R2 P2 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 V11 V13 T11 T13 N11 N13 M11 M13 FBA_EDC1 FBA_DBI1 R13 P13 NC FBA_CMD3 FBA_CMD0 FBA_CMD10 FBA_CMD15 NC NC NC NC FBA_CMD7 NC RAS CAS WE CS J4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 FBA_EDC4 FBA_DBI4 C2 D2 EDC0 DBI0 FBA_CMD5 FBA_CMD4 FBA_CMD13 FBA_CMD14 FBA_CMD12 FBA_CMD11 FBA_CMD8 FBA_CMD9 FBA_CMD6 NC NC V10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 FBA_CMD2 FBA_CMD1 EDC1 DBI1 WCK01 WCK01 [15] [15] K4 K5 K11 K10 H11 H10 H5 H4 J5 J2 J3 J12 J11 FBA_CLK0 FBA_CLK0* FBA_CMD19 FBA_CMD16 FBA_CMD26 FBA_CMD31 A10 VREFD ABI NC VREFD P4 P5 L3 G3 G12 L12 NC EDC0 DBI0 B FBA_W CK01 FBA_W CK01* x16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A4 A2 B4 B2 E4 E2 F4 F2 x32 A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 x16 A11 A13 B11 B13 E11 E13 F11 F13 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC FBA_EDC5 C13 FBA_DBI5 D13 EDC1 DBI1 GND FBA_W CK45 D4 FBA_W CK45* D5 WCK01 WCK01 RESET CKE NC NC NC NC FBA_CMD23 J4 FBA_CMD21 FBA_CMD20 FBA_CMD29 FBA_CMD30 FBA_CMD28 FBA_CMD27 FBA_CMD24 FBA_CMD25 FBA_CMD22 H4 H5 H11 H10 K11 K10 K5 K4 J5 RAS CAS WE CS ABI A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 NC NC NC FBA_CMD18 FBA_CMD17 NC [15] [15] K4G80325FB-HC25 CLK CLK G3 L3 L12 G12 R3 40.2_1%_04 M2A INS16517224 J2 J3 RESET CKE J12 J11 FBA_CLK1 FBA_CLK1* B CLK CLK Sheet 16 of 77 Frame Buffer Partition A R4 40.2_1%_04 K4G80325FB-HC25 K4G80325FB-HC25 R6 40.2_1%_04 M3A R5 40.2_1%_04 NORMAL K4G80325FB-HC25 INS16516780 A5 V5 MIRRORED x32 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 C3 x16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 NC FBA_EDC2 C13 FBA_DBI2 D13 EDC2 DBI2 GND 0.01u_50V_X7R_04 NC NC NC GND NC NC FBA_EDC3 FBA_DBI3 C2 D2 EDC3 DBI3 FBA_W CK23 D4 FBA_W CK23* D5 EDC2 DBI2 J14 VREFC J13 ZQ J10 SEN NC FBA_ZQ0 C678 A10 R409 1.33K_1%_04 R413 121_1%_04 GND GND GND GND V10 FBA_VREFC 0.300 J14 VREFC J13 ZQ J10 SEN x16 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 V4 V2 T4 T2 N4 N2 M4 M2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NC FBA_EDC7 FBA_DBI7 R2 P2 EDC3 DBI3 NC FBA_W CK67 P4 FBA_W CK67* P5 GND NC_RFU_A5 NC_RFU_V5 0.01u_50V_X7R_04 VREFD 0.300 A5 V5 C2 x32 FBA_VREFC ŇŃłŠŗœņŇń DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 FBA_EDC6 R13 FBA_DBI6 P13 R410 549_1%_04 NC 820p_50V_X7R_04 A4 A2 B4 B2 E4 E2 F4 F2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 FBVDDQ NC VREFD FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 NC_RFU_A5 NC_RFU_V5 V11 V13 T11 T13 N11 N13 M11 M13 FBA_ZQ2 C679 NC NC NC NC NC NC NC GND 820p_50V_X7R_04 A11 A13 B11 B13 E11 E13 F11 F13 C FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 R414 121_1%_04 GND C GND NC WCK23 WCK23 K4G80325FB-HC25 WCK23 WCK23 K4G80325FB-HC25 FBA_VREF_L R408 931_1%_04 FBA_VREFC D 0.300 GPIO10_ALT_MEM_VREF Q30 MTN2002ZS3 G S [17,20,21,26] D [15,17,18,19,20,21,22,23,28,64] D FBVDDQ GND ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title VRAM=K4G80325FB-HC03, HC28 Size A3 Date: 1 2 3 4 5 6 [16] Frame Buffer Partition A Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 16 of 77 8 Frame Buffer Partition A B - 17 B.Schematic Diagrams FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 A M2B INS16516538 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 Schematic Diagrams Frame Buffer Partition B 1 [15] [15] [15] [15] [15] [15] [15] [15] 2 FBB_WCK01 FBB_WCK01* FBB_WCK23 FBB_WCK23* FBB_WCK45 FBB_WCK45* FBB_WCK67 FBB_WCK67* FBB_W CK01 FBB_W CK01* FBB_W CK23 FBB_W CK23* FBB_W CK45 FBB_W CK45* FBB_W CK67 FBB_W CK67* 3 [15] FBB_D[63..0] [15] FBB_DBI[7..0] [15] FBB_EDC[7..0] FBB_DBI[7..0] M4B M5B M4D INS16519868 INS16519158 INS16520090 FBB_CMD3 FBB_CMD0 FBB_CMD10 FBB_CMD15 FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 V4 V2 T4 T2 N4 N2 M4 M2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 FBB_EDC0 FBB_DBI0 R2 P2 EDC0 DBI0 V11 V13 T11 T13 N11 N13 M11 M13 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 FBB_EDC1 FBB_DBI1 R13 P13 EDC1 DBI1 P4 P5 NC NC FBB_CMD7 NC NC J4 FBB_CMD5 FBB_CMD4 FBB_CMD13 FBB_CMD14 FBB_CMD12 FBB_CMD11 FBB_CMD8 FBB_CMD9 FBB_CMD6 NC NC NC NC NC NC VREFD FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_W CK01 FBB_W CK01* x16 L3 G3 G12 L12 A K4 K5 K11 K10 H11 H10 H5 H4 J5 V10 FBB_CMD2 FBB_CMD1 [15] [15] J2 J3 J12 J11 FBB_CLK0 FBB_CLK0* R17 40.2_1%_04 WCK01 WCK01 FBB_CMD19 FBB_CMD16 FBB_CMD26 FBB_CMD31 NORMAL RAS CAS WE CS ABI A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 A4 A2 B4 B2 E4 E2 F4 F2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 FBB_EDC4 FBB_DBI4 C2 D2 EDC0 DBI0 VREFD x32 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 RESET CKE A11 A13 B11 B13 E11 E13 F11 F13 FBB_EDC5 FBB_DBI5 CLK CLK C13 D13 FBB_W CK45 FBB_W CK45* R16 40.2_1%_04 D4 D5 A10 x16 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 G3 L3 L12 G12 FBB_CMD23 J4 FBB_CMD21 FBB_CMD20 FBB_CMD29 FBB_CMD30 FBB_CMD28 FBB_CMD27 FBB_CMD24 FBB_CMD25 FBB_CMD22 H4 H5 H11 H10 K11 K10 K5 K4 J5 RAS CAS WE CS ABI A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 NC NC NC NC NC FBB_CMD18 FBB_CMD17 NC NC J2 J3 NC EDC1 DBI1 [15] [15] GND J12 J11 FBB_CLK1 FBB_CLK1* RESET CKE CLK CLK NC B WCK01 WCK01 R7 40.2_1%_04 R8 40.2_1%_04 K4G80325FB-HC25 K4G80325FB-HC25 K4G80325FB-HC25 K4G80325FB-HC25 M5A INS16518908 C43 FBVDDQ A11 A13 B11 B13 E11 E13 F11 F13 FBB_EDC2 FBB_DBI2 C C13 D13 NC NC NC NC FBB_EDC3 FBB_DBI3 C2 D2 EDC3 DBI3 FBB_W CK23 FBB_W CK23* D4 D5 FBB_VREFC NC NC FBB_ZQ0 GND NC VREFD DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 GND NC EDC2 DBI2 A4 A2 B4 B2 E4 E2 F4 F2 R412 549_1%_04 NC C697 A10 R418 1.33K_1%_04 J14 VREFC J13 ZQ J10 SEN GND GND V11 V13 T11 T13 N11 N13 M11 M13 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 FBB_EDC6 FBB_DBI6 R13 P13 EDC2 DBI2 GND FBB_VREFC 0.300 FBB_ZQ2 x32 GND NC_RFU_A5 NC_RFU_V5 0.01u_50V_X7R_04 VREFD R419 121_1%_04 820p_50V_X7R_04 GND 0.300 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 A5 V5 C1 NORMAL x16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 M4A NC_RFU_A5 NC_RFU_V5 0.01u_50V_X7R_04 MIRRORED x32 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 A5 V5 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 V4 V2 T4 T2 N4 N2 M4 M2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 FBB_EDC7 FBB_DBI7 R2 P2 EDC3 DBI3 FBB_W CK67 FBB_W CK67* P4 P5 WCK23 WCK23 V10 J14 VREFC J13 ZQ J10 SEN C680 820p_50V_X7R_04 x16 NC NC NC NC NC NC R415 121_1%_04 C NC NC GND NC GND GND NC WCK23 WCK23 K4G80325FB-HC25 FBB_VREFC D FBB_VREF_H [16,20,21,26] R411 931_1%_04 0.300 Q31 MTN2002ZS3 G GPIO10_ALT_MEM_VREF S B.Schematic Diagrams 8 INS16519380 x32 B 7 FBB_EDC[7..0] MIRRORED Sheet 17 of 77 Frame Buffer Partition B 6 FRAME BUFFER PARTITION B FBB_D[63..0] M5D A 5 FBB_CMD[31..0] FBB_CMD[31..0] [15] 4 ㎃MT20022zs3 㕁 6-15-20023-7b0 D D [15,16,18,19,20,21,22,23,28,64] GND FBVDDQ ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title K4G80325FB-HC25 VRAM=K4G80325FB-HC03, HC28 Size A3 INS16519622 Date: 1 B - 18 Frame Buffer Partition B 2 3 4 5 6 [17] Frame Buffer Partition B Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 17 8 of 77 Schematic Diagrams Frame Buffer Partition A_B 1 2 3 4 5 6 7 8 FRAME BUFFER PARTITION A/B DECOUPLING FBVDDQ DECOUPLING AROUND FBA MEMORIES (DQ0-DQ31) PLACE Under MEM DECOUPLING AROUND FBA MEMORIES (DQ32-DQ63) SPARE *1u_6.3V_X5R_04 *1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 C150 1u_6.3V_X5R_04 C123 C166 C47 *1u_6.3V_X5R_04 C128 C78 A GND 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 1u x 10 10u x 6 22u x 5 Sheet 18 of 77 Frame Buffer Partition A_B GND INS16526066 FBVDDQ B Mirrored J1 J1 SOE*/MF_VDD add 1k to VDD C C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ FBVDDQ Normal Mirrored J1 MF_VSS/SOE* add 1k to VSS add 1k to VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ K4G80325FB-HC25 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A1 A12 A14 A3 C1 C11 C12 C14 C3 C4 E1 E12 E14 E3 F10 F5 H13 H2 K13 K2 M10 M5 N1 N12 N14 N3 R1 R11 R12 R14 R3 R4 V1 V12 V14 V3 A1 VSSQ A12 VSSQ A14 VSSQ A3 VSSQ C1 VSSQ C11 VSSQ C12 VSSQ C14 VSSQ C3 VSSQ C4 VSSQ E1 VSSQ E12 VSSQ E14 K4G80325FB-HC25 VSSQ E3 VSSQ F10 VSSQ F5 VSSQ H13 VSSQ H2 VSSQ K13 VSSQ K2 VSSQ M10 VSSQ M5 VSSQ N1 VSSQ N12 VSSQ N14 VSSQ N3 VSSQ R1 VSSQ R11 VSSQ R12 VSSQ R14 VSSQ R3 VSSQ R4 VSSQ V1 VSSQ V12 VSSQ V14 VSSQ V3 VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ B Normal J1 SOE*/MF_VDD MF_VSS/SOE* add 1k to VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ K4G80325FB-HC25 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A1 A12 A14 A3 C1 C11 C12 C14 C3 C4 E1 E12 E14 E3 F10 F5 H13 H2 K13 K2 M10 M5 N1 N12 N14 N3 R1 R11 R12 R14 R3 R4 V1 V12 V14 V3 A1 VSSQ A12 VSSQ A14 VSSQ A3 VSSQ C1 VSSQ C11 VSSQ C12 VSSQ C14 VSSQ C3 VSSQ C4 VSSQ E1 VSSQ E12 VSSQ E14 K4G80325FB-HC25 VSSQ E3 VSSQ F10 VSSQ F5 VSSQ H13 VSSQ H2 VSSQ K13 VSSQ K2 VSSQ M10 VSSQ M5 VSSQ N1 VSSQ N12 VSSQ N14 VSSQ N3 VSSQ R1 VSSQ R11 VSSQ R12 VSSQ R14 VSSQ R3 VSSQ R4 VSSQ V1 VSSQ V12 VSSQ V14 VSSQ V3 VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 C D D GND GND GND GND [15,16,17,19,20,21,22,23,28,64] ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ FBVDDQ Title Size A3 Date: 1 2 3 4 5 6 [18] Frame Buffer Partition A_B Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 18 of 77 8 Frame Buffer Partition A_B B - 19 B.Schematic Diagrams M4C GND INS16524034 C703 C690 C694 M5C FBVDDQ INS16523208 10u_6.3V_X5R_06 10u_6.3V_X5R_06 *10u_6.3V_X5R_06 10u_6.3V_X5R_06 M2C 10u_6.3V_X5R_06 1u x 10 10u x 6 22u x 5 C695 C696 C702 C676 C130 C131 C668 10u_6.3V_X5R_06 GND INS16524960 C4 FBVDDQ C666 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 *10u_6.3V_X5R_06 10u_6.3V_X5R_06 GND M3C FBVDDQ GND C665 C681 C664 C683 FBVDDQ C674 C682 C675 C667 C685 C7 22u_6.3V_X5R_06 1u_6.3V_X5R_04 C48 1u_6.3V_X5R_04 C99 1u_6.3V_X5R_04 C85 *1u_6.3V_X5R_04 C97 *1u_6.3V_X5R_04 C688 C670 1u_6.3V_X5R_04 C6 1u_6.3V_X5R_04 A PLACE Under MEM SPARE C672 C669 C671 C687 C689 C686 C5 22u_6.3V_X5R_06 FBVDDQ Schematic Diagrams GPU Frame Buffer Partition 1 2 3 4 U22D INS16529121 B.Schematic Diagrams A Sheet 19 of 77 GPU Frame Buffer Partition B C A5 C8 J18 F12 D29 E27 F20 E26 FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7 D5 D8 E17 E12 E30 B29 G21 E24 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 GND GND GND GND GND GND GND GND D FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CMD31 FBC_CMD32 FBC_CMD33 FBC_CMD34 FBC_CMD35 FBC_DBG_RFU1 FBC_DBG_RFU2 J14 J23 FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CMD31 FBC_D[63..0] R60 10K_04 R30 10K_04 FBC_CMD1 FBC_CMD17 FBC_CMD2 FBC_CMD18 R31 10K_04 R58 10K_04 GND R53 R39 *60.4_1%_04 *60.4_1%_04 G15 F15 H21 J21 FBC_CLK0 FBC_CLK0* FBC_CLK1 FBC_CLK1* FBC_WCK01 FBC_WCK01 FBC_WCKB01 FBC_WCKB01 FBC_WCK23 FBC_WCK23 FBC_WCKB23 FBC_WCKB23 FBC_WCK45 FBC_WCK45 FBC_WCKB45 FBC_WCKB45 FBC_WCK67 FBC_WCK67 FBC_WCKB67 FBC_WCKB67 F8 G8 G9 F9 H12 G12 G14 H14 J27 H27 E29 F29 G23 H23 H24 J24 FBC_W CK01 FBC_W CK01* DP_FBC_CLK0 FB_CLK DP_FBC_CLK0 FB_CLK DP_FBC_CLK1 FB_CLK DP_FBC_CLK1 FB_CLK FBC_WCK01 FB_WCK FBC_WCK01 FB_WCK FBC_W CK23 FBC_W CK23* FBC_WCK23 FB_WCK FBC_WCK23 FB_WCK FBC_W CK45 FBC_W CK45* FBC_WCK45 FB_WCK FBC_WCK45 FB_WCK FBC_W CK67 FBC_W CK67* L17 FBC_WCK67 FB_WCK FBC_WCK67 FB_WCK FB_PLL_AVDD [21] FBC_CLK0 [20] FBC_CLK0* [20] FBC_CLK1 [20] FBC_CLK1* [20] FBC_W CK01 [20] FBC_W CK01* [20] FBC_W CK23 [20] FBC_W CK23* [20] FBC_W CK45 [20] FBC_W CK45* [20] FBC_W CK67 [20] FBC_W CK67* [20] FBD_DBI0 FBD_DBI1 FBD_DBI2 FBD_DBI3 FBD_DBI4 FBD_DBI5 FBD_DBI6 FBD_DBI7 AK8 AK4 AK2 AK3 AK5 AK6 AK9 AK7 AG4 AF9 AG6 AG7 AJ4 AJ5 AJ6 AG5 Y6 Y5 V5 Y4 AA6 AA5 AC5 AC4 AD7 AC6 AF6 AD6 AF7 AF8 AF2 AF3 F4 E1 F3 F5 D2 D1 C3 C2 J5 J4 L8 J2 F1 F2 H4 H5 V7 V8 V6 V9 U4 R5 R6 U8 P6 R9 P4 P5 L7 L6 L4 L5 AJ1 AG1 AA7 AD5 D3 H3 U5 M9 FBD_EDC0 AJ3 FBD_EDC1 AG2 FBD_EDC2 AA9 FBD_EDC3 AF4 FBD_EDC4 E3 FBD_EDC5 H2 FBD_EDC6 U6 FBD_EDC7 M5 [15,19] Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y9 0.1u_10V_X7R_04 GND GND [15,19] FB_PLL_AVDD [15,16,17,18,20,21,22,23,28,64] FBVDDQ FBD_D0 FBD_D1 FBD_D2 FBD_D3 FBD_D4 FBD_D5 FBD_D6 FBD_D7 FBD_D8 FBD_D9 FBD_D10 FBD_D11 FBD_D12 FBD_D13 FBD_D14 FBD_D15 FBD_D16 FBD_D17 FBD_D18 FBD_D19 FBD_D20 FBD_D21 FBD_D22 FBD_D23 FBD_D24 FBD_D25 FBD_D26 FBD_D27 FBD_D28 FBD_D29 FBD_D30 FBD_D31 FBD_D32 FBD_D33 FBD_D34 FBD_D35 FBD_D36 FBD_D37 FBD_D38 FBD_D39 FBD_D40 FBD_D41 FBD_D42 FBD_D43 FBD_D44 FBD_D45 FBD_D46 FBD_D47 FBD_D48 FBD_D49 FBD_D50 FBD_D51 FBD_D52 FBD_D53 FBD_D54 FBD_D55 FBD_D56 FBD_D57 FBD_D58 FBD_D59 FBD_D60 FBD_D61 FBD_D62 FBD_D63 FBD_CMD0 FBD_CMD1 FBD_CMD2 FBD_CMD3 FBD_CMD4 FBD_CMD5 FBD_CMD6 FBD_CMD7 FBD_CMD8 FBD_CMD9 FBD_CMD10 FBD_CMD11 FBD_CMD12 FBD_CMD13 FBD_CMD14 FBD_CMD15 FBD_CMD16 FBD_CMD17 FBD_CMD18 FBD_CMD19 FBD_CMD20 FBD_CMD21 FBD_CMD22 FBD_CMD23 FBD_CMD24 FBD_CMD25 FBD_CMD26 FBD_CMD27 FBD_CMD28 FBD_CMD29 FBD_CMD30 FBD_CMD31 FBD_CMD32 FBD_CMD33 FBD_CMD34 FBD_CMD35 AD2 AD1 AD4 AC1 AC2 AC3 AA3 AA2 AA1 AA4 Y1 Y2 Y3 V3 V2 V1 L3 L2 L1 M4 M1 M2 M3 P3 P2 P1 R4 R1 R2 R3 U3 U2 U1 V4 AD3 J3 FBD_DBG_RFU1 FBD_DBG_RFU2 AC9 P9 FBD_CLK0 FBD_CLK0 FBD_CLK1 FBD_CLK1 FBD_DQM0 FBD_DQM1 FBD_DQM2 FBD_DQM3 FBD_DQM4 FBD_DQM5 FBD_DQM6 FBD_DQM7 FBD_DQS_WP0 FBD_DQS_WP1 FBD_DQS_WP2 FBD_DQS_WP3 FBD_DQS_WP4 FBD_DQS_WP5 FBD_DQS_WP6 FBD_DQS_WP7 FBD_CMD0 FBD_CMD1 FBD_CMD2 FBD_CMD3 FBD_CMD4 FBD_CMD5 FBD_CMD6 FBD_CMD7 FBD_CMD8 FBD_CMD9 FBD_CMD10 FBD_CMD11 FBD_CMD12 FBD_CMD13 FBD_CMD14 FBD_CMD15 FBD_CMD16 FBD_CMD17 FBD_CMD18 FBD_CMD19 FBD_CMD20 FBD_CMD21 FBD_CMD22 FBD_CMD23 FBD_CMD24 FBD_CMD25 FBD_CMD26 FBD_CMD27 FBD_CMD28 FBD_CMD29 FBD_CMD30 FBD_CMD31 B - 20 GPU Frame Buffer Partition 4 R168 10K_04 10K_04 A FBD_CMD2 FBD_CMD18 R165 10K_04 R501 10K_04 GND FBVDDQ R64 *60.4_1%_04 R72 *60.4_1%_04 B Y8 Y7 R8 R7 FBD_CLK0 [21] FBD_CLK0* [21] FBD_CLK1 [21] FBD_CLK1* [21] FBD_WCK01 FBD_WCK01 FBD_WCKB01 FBD_WCKB01 FBD_WCK23 FBD_WCK23 FBD_WCKB23 FBD_WCKB23 FBD_WCK45 FBD_WCK45 FBD_WCKB45 FBD_WCKB45 FBD_WCK67 FBD_WCK67 FBD_WCKB67 FBD_WCKB67 AJ8 AJ7 AG8 AG9 AD8 AD9 AC7 AC8 J6 J7 H7 H6 P8 P7 M7 M8 FBD_PLL_AVDD V11 FBD_W CK01 [21] FBD_W CK01* [21] FBD_W CK23 [21] FBD_W CK23* [21] C FBD_W CK45 [21] FBD_W CK45* [21] FBD_W CK67 [21] FBD_W CK67* [21] FB_PLL_AVDD [15,19] C229 GND GND GND GND GND GND GND GND 0.1u_10V_X7R_04 D GND GP104 FBD 5 R512 FBD_CMD1 FBD_CMD17 FBD_DEBUG0 FBD_DEBUG1 GP106 UNUSED ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 3 [21] [21] FBVDDQ FBD_D0 FBD_D1 FBD_D2 FBD_D3 FBD_D4 FBD_D5 FBD_D6 FBD_D7 FBD_D8 FBD_D9 FBD_D10 FBD_D11 FBD_D12 FBD_D13 FBD_D14 FBD_D15 FBD_D16 FBD_D17 FBD_D18 FBD_D19 FBD_D20 FBD_D21 FBD_D22 FBD_D23 FBD_D24 FBD_D25 FBD_D26 FBD_D27 FBD_D28 FBD_D29 FBD_D30 FBD_D31 FBD_D32 FBD_D33 FBD_D34 FBD_D35 FBD_D36 FBD_D37 FBD_D38 FBD_D39 FBD_D40 FBD_D41 FBD_D42 FBD_D43 FBD_D44 FBD_D45 FBD_D46 FBD_D47 FBD_D48 FBD_D49 FBD_D50 FBD_D51 FBD_D52 FBD_D53 FBD_D54 FBD_D55 FBD_D56 FBD_D57 FBD_D58 FBD_D59 FBD_D60 FBD_D61 FBD_D62 FBD_D63 C242 2 FBD_D[63..0] ɈɈONLY G1 ᶵᶲẞ U22E INS16530501 GND 1 FBD_CMD[31..0] FBD_D[63..0] 5/23 FBD FBVDDQ FBVDDQ FBD_EDC[7..0] 8 FBD_CMD[31..0] [21] [20] [20] FBC_DEBUG0 FBC_DEBUG1 FBC_CLK0 FBC_CLK0 FBC_CLK1 FBC_CLK1 FBC_PLL_AVDD [20] FBC_CMD[31..0] FBC_D[63..0] C11 B11 A11 D11 A12 B12 C12 C14 B14 A14 D14 A15 B15 C15 C17 B17 B24 A24 D23 A23 B23 C23 C21 B21 A21 D20 A20 B20 C20 C18 B18 A18 D17 A17 A9 C24 7 FBD_DBI[7..0] FBD_EDC[7..0] [20] FBC_EDC[7..0] FBC_CMD[31..0] FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBC_DBI0 FBC_DBI1 FBC_DBI2 FBC_DBI3 FBC_DBI4 FBC_DBI5 FBC_DBI6 FBC_DBI7 FBC_DBI[7..0] FBC_EDC[7..0] 4/23 FBC C6 D6 A6 B6 B4 A4 B3 C4 D9 C9 E9 B9 B8 A8 F6 E6 F18 G18 E18 H18 D15 E15 G17 H17 J15 H15 E14 F14 H11 G11 F11 E11 J29 F30 H29 G30 B30 A30 H30 C30 D27 J26 F27 G27 C27 B27 A27 G29 H20 D18 G20 E20 F23 E21 D21 E23 G24 H26 F24 G26 F26 D26 B26 C26 6 FBD_DBI[7..0] GPU FRAME BUFFER PARTITION C/D FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 5 FBC_DBI[7..0] 6 [19] GPU Frame Buffer Partition Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 19 8 of 77 Schematic Diagrams Frame Buffer Partition C 1 [19] 2 3 4 FBC_CMD[31..0] [19] [19] [19] [19] [19] [19] [19] [19] FBC_D[63..0] [19] FBC_D[63..0] [19] FBC_DBI[7..0] [19] FBC_EDC[7..0] FBC_DBI[7..0] FBC_EDC[7..0] FBC_WCK01 FBC_WCK01* FBC_WCK23 FBC_WCK23* FBC_WCK45 FBC_WCK45* FBC_WCK67 FBC_WCK67* FBC_W CK01 FBC_W CK01* FBC_W CK23 FBC_W CK23* FBC_W CK45 FBC_W CK45* FBC_W CK67 FBC_W CK67* 5 INS16533781 MIRRORED x32 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC FBC_EDC0 FBC_DBI0 R2 P2 EDC0 DBI0 NC NC NC NC FBC_CMD7 NC NC R13 P13 EDC1 DBI1 P4 P5 J4 FBC_CMD5 FBC_CMD4 FBC_CMD13 FBC_CMD14 FBC_CMD12 FBC_CMD11 FBC_CMD8 FBC_CMD9 FBC_CMD6 NC NC NC V10 VREFD FBC_EDC1 FBC_DBI1 L3 G3 G12 L12 K4 K5 K11 K10 H11 H10 H5 H4 J5 FBC_CMD2 FBC_CMD1 [19] [19] J2 J3 J12 J11 FBC_CLK0 FBC_CLK0* WCK01 WCK01 RAS CAS WE CS ABI FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 A4 A2 B4 B2 E4 E2 F4 F2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 FBC_EDC4 FBC_DBI4 C2 D2 EDC0 DBI0 VREFD A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 x32 RESET CKE A11 A13 B11 B13 E11 E13 F11 F13 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC FBC_EDC5 FBC_DBI5 C13 D13 EDC1 DBI1 GND FBC_W CK45 D4 FBC_W CK45* D5 R52 40.2_1%_04 x16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A5 V5 C260 FBVDDQ MIRRORED x32 C13 D13 0.01u_50V_X7R_04 NC NC R427 549_1%_04 NC NC GND NC H4 H5 H11 H10 K11 K10 K5 K4 J5 ABI A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 NC NC NC NC NC FBC_CMD18 FBC_CMD17 NC NC [19] [19] WCK01 WCK01 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 V11 V13 T11 T13 N11 N13 M11 M13 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 FBC_EDC6 FBC_DBI6 R13 P13 EDC2 DBI2 J2 J3 J12 J11 FBC_CLK1 FBC_CLK1* R49 40.2_1%_04 RESET CKE CLK CLK B R47 40.2_1%_04 K4G80325FB-HC25 NC EDC2 DBI2 FBC_VREFC GND FBC_ZQ0 NC VREFD Sheet 20 of 77 Frame Buffer Partition C DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 FBC_EDC3 FBC_DBI3 C2 D2 EDC3 DBI3 FBC_W CK23 FBC_W CK23* D4 D5 WCK23 WCK23 A10 C706 R431 1.33K_1%_04 820p_50V_X7R_04 GND GND J14 VREFC GND FBC_VREFC J13 ZQ x32 V4 V2 T4 T2 N4 N2 M4 M2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NC FBC_EDC7 FBC_DBI7 R2 P2 EDC3 DBI3 NC FBC_W CK67 FBC_W CK67* P4 P5 SEN GND J14 VREFC J13 ZQ J10 SEN C709 NC 820p_50V_X7R_04 NC NC R45 121_1%_04 NC NC C NC NC GND GND GND NC WCK23 WCK23 K4G80325FB-HC25 D 0.300 FBC_VREF_L R429 931_1%_04 FBC_VREFC D Q32 MTN2002ZS3 G GPIO10_ALT_MEM_VREF S [16,17,21,26] ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ GND Title K4G80325FB-HC25 VRAM=K4G80325FB-HC03, HC28 INS16534491 0.300 FBC_ZQ2 V10 x16 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 R55 121_1%_04 GND NC_RFU_A5 NC_RFU_V5 0.01u_50V_X7R_04 0.300 D A4 A2 B4 B2 E4 E2 F4 F2 A5 V5 C253 VREFD NC FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 1 J4 FBC_CMD21 FBC_CMD20 FBC_CMD29 FBC_CMD30 FBC_CMD28 FBC_CMD27 FBC_CMD24 FBC_CMD25 FBC_CMD22 NORMAL NC_RFU_A5 NC_RFU_V5 NC J10 C FBC_CMD23 A RAS CAS WE CS INS16534713 M15A FBC_EDC2 FBC_DBI2 NC K4G80325FB-HC25 K4G80325FB-HC25 A11 A13 B11 B13 E11 E13 F11 F13 x16 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 CLK CLK A10 G3 L3 L12 G12 M6A R51 40.2_1%_04 K4G80325FB-HC25 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_CMD19 FBC_CMD16 FBC_CMD26 FBC_CMD31 [15,16,17,18,19,21,22,23,28,64] FBVDDQ Size A3 Date: 2 3 4 5 6 [20] Frame Buffer Partition C Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 20 of 77 8 Frame Buffer Partition C B - 21 B.Schematic Diagrams V4 V2 T4 T2 N4 N2 M4 M2 FBC_W CK01 FBC_W CK01* FBC_CMD3 FBC_CMD0 FBC_CMD10 FBC_CMD15 x16 FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 M6B NORMAL M15B INS16534979 V11 V13 T11 T13 N11 N13 M11 M13 8 INS16534265 INS16534063 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 7 M6D M15D A B 6 FRAME BUFFER PARTITION C FBC_CMD[31..0] Schematic Diagrams Frame Buffer Partition D 1 [19] 2 FBD_D[63..0] FBD_D[63..0] FBD_DBI[7..0] [19] FBD_DBI[7..0] [19] FBD_EDC[7..0] FBDEDC[7..0] A [19] [19] [19] [19] [19] [19] [19] [19] FBD_W CK01 FBD_W CK01* FBD_W CK23 FBD_W CK23* FBD_W CK45 FBD_W CK45* FBD_W CK67 FBD_W CK67* FBD_WCK01 FBD_WCK01* FBD_WCK23 FBD_WCK23* FBD_WCK45 FBD_WCK45* FBD_WCK67 FBD_WCK67* INS16537233 NORMAL M7B INS16537773 INS16536547 MIRRORED B FBD_EDC0 FBD_DBI0 R2 P2 NC NC DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 FBD_EDC1 FBD_DBI1 R13 P13 EDC1 DBI1 P4 P5 L3 G3 G12 L12 FBD_CMD7 NC NC NC NC NC NC V10 A4 A2 B4 B2 E4 E2 F4 F2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 FBD_EDC4 FBD_DBI4 C2 D2 EDC0 DBI0 A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 INS16537483 FBD_CMD19 FBD_CMD16 FBD_CMD26 FBD_CMD31 x32 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC FBD_EDC5 FBD_DBI5 C13 D13 EDC1 DBI1 GND R158 40.2_1%_04 INS16536829 G2 A5 V5 NC_RFU_A5 NC_RFU_V5 0.01u_50V_X7R_04 NC G2 FBD_EDC2 FBD_DBI2 C13 D13 EDC2 DBI2 GND R510 549_1%_04 NC NC FBD_EDC6 FBD_DBI6 GND V11 V13 T11 T13 N11 N13 M11 M13 R13 P13 FBD_VREFC NC NC FBD_ZQ0 J14 FBD_D56 FBD_D57 FBD_D58 FBD_D59 FBD_D60 FBD_D61 FBD_D62 FBD_D63 VREFC J13 ZQ J10 SEN C801 C VREFD A10 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 R511 1.33K_1%_04 820p_50V_X7R_04 R507 121_1%_04 G2 G2 G2 GND GND G2 GND GND D K4G80325FB-HC25 G2 GPIO10_ALT_MEM_VREF H4 H5 H11 H10 K11 K10 K5 K4 J5 FBD_CMD18 FBD_CMD17 ABI A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 RFU_A12 J2 J3 B RESET CKE J12 J11 FBD_CLK1 FBD_CLK1* R160 40.2_1%_04 G2 CLK CLK V4 V2 T4 T2 N4 N2 M4 M2 FBD_VREF_L 0.300 Q37 MTN2002ZS3 G K4G80325FB-HC25 G2 A5 V5 C387 NC_RFU_A5 NC_RFU_V5 0.01u_50V_X7R_04 FBD_EDC7 FBD_DBI7 R2 P2 EDC3 DBI3 FBD_W CK67 FBD_W CK67* P4 P5 WCK23 WCK23 V10 GND x16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 R509 R151 40.2_1%_04 G2 NC NC FBD_VREFC NC NC 0.300 FBD_ZQ2 NC NC J14 VREFC J13 ZQ J10 NC NC C804 NC R508 121_1%_04 820p_50V_X7R_04 NC C SEN G2 G2 G2 GND [16,17,20,26] J4 FBD_CMD21 FBD_CMD20 FBD_CMD29 FBD_CMD30 FBD_CMD28 FBD_CMD27 FBD_CMD24 FBD_CMD25 FBD_CMD22 NC x32 0.300 NC WCK23 WCK23 NC VREFD G2 NC EDC3 DBI3 NC EDC2 DBI2 NC D4 D5 NC DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 NC FBD_W CK23 FBD_W CK23* NC NORMAL FBD_D48 FBD_D49 FBD_D50 FBD_D51 FBD_D52 FBD_D53 FBD_D54 FBD_D55 G2 C385 x16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 FBD_CMD23 M8A K4G80325FB-HC25 MIRRORED A11 A13 B11 B13 E11 E13 F11 F13 C2 D2 NC WCK01 WCK01 R150 40.2_1%_04 FBVDDQ FBD_D16 FBD_D17 FBD_D18 FBD_D19 FBD_D20 FBD_D21 FBD_D22 FBD_D23 FBD_EDC3 FBD_DBI3 NC [19] [19] M7A A4 A2 B4 B2 E4 E2 F4 F2 NC K4G80325FB-HC25 G2 CLK CLK RAS CAS WE CS x16 A11 A13 B11 B13 E11 E13 F11 F13 D4 D5 G3 L3 L12 G12 A10 FBD_D40 FBD_D41 FBD_D42 FBD_D43 FBD_D44 FBD_D45 FBD_D46 FBD_D47 FBD_W CK45 FBD_W CK45* RESET CKE J12 J11 WCK01 WCK01 FBD_D24 FBD_D25 FBD_D26 FBD_D27 FBD_D28 FBD_D29 FBD_D30 FBD_D31 A M8B VREFD J2 J3 FBD_CLK0 FBD_CLK0* K4G80325FB-HC25 G2 x32 ABI K4 K5 K11 K10 H11 H10 H5 H4 J5 FBD_CMD2 FBD_CMD1 [19] [19] RAS CAS WE CS J4 FBD_CMD5 FBD_CMD4 FBD_CMD13 FBD_CMD14 FBD_CMD12 FBD_CMD11 FBD_CMD8 FBD_CMD9 FBD_CMD6 NC VREFD V11 V13 T11 T13 N11 N13 M11 M13 FBD_W CK01 FBD_W CK01* NC EDC0 DBI0 FBD_D8 FBD_D9 FBD_D10 FBD_D11 FBD_D12 FBD_D13 FBD_D14 FBD_D15 FBD_CMD3 FBD_CMD0 FBD_CMD10 FBD_CMD15 x16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 FBD_D32 FBD_D33 FBD_D34 FBD_D35 FBD_D36 FBD_D37 FBD_D38 FBD_D39 931_1%_04 GND GND FBD_VREFC G2 S B.Schematic Diagrams Sheet 21 of 77 Frame Buffer Partition D V4 V2 T4 T2 N4 N2 M4 M2 5 M8D M7D x32 FBD_D0 FBD_D1 FBD_D2 FBD_D3 FBD_D4 FBD_D5 FBD_D6 FBD_D7 4 㔜枩ᶵᶲẞ) FRAME BUFFER PARTITION D ɈONLY G1 ᶵᶲẞ (㔜 FBD_CMD[31..0] FBD_CMD[31..0] [19] 3 G2 GND D D [15,16,17,18,19,20,22,23,28,64] ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ K4G80325FB-HC25 Title VRAM=K4G80325FB-HC03, HC28 INS16537031 G2 Size A3 Date: 1 B - 22 Frame Buffer Partition D 2 3 FBVDDQ 4 [21] Frame Buffer Partition D Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 5 21 of 77 Schematic Diagrams Frame Buffer Partition C_D 1 2 3 4 5 6 7 FBVDDQ PLACE Under MEM DECOUPLING AROUND FBC MEMORIES (DQ32-DQ63) FBVDDQ PLACE Under MEM DECOUPLING AROUND FBC MEMORIES (DQ0-DQ31) 8 ɈONLY G1 ᶵᶲẞ FRAME BUFFER PARTITION C/D DECOUPLING C396 C350 C413 C395 C411 C408 C372 C376 C405 C393 C289 C269 C707 C293 C716 C212 C263 C261 C175 C255 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 G2 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 A A G2 GND GND FBVDDQ 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 GND GND GND M6C INS16541048 FBVDDQ B add 1k to VDD C VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ FBVDDQ Normal J1 SOE*/MF_VDD C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 M8C INS16544046 INS16542800 INS16541934 Mirrored J1 GND M7C M15C J1 B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ K4G80325FB-HC25 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A1 A12 A14 A3 C1 C11 C12 C14 C3 C4 E1 E12 E14 E3 F10 F5 H13 H2 K13 K2 M10 M5 N1 N12 N14 N3 R1 R11 R12 R14 R3 R4 V1 V12 V14 V3 A1 VSSQ A12 VSSQ A14 VSSQ A3 VSSQ C1 VSSQ C11 VSSQ C12 VSSQ C14 VSSQ C3 VSSQ C4 VSSQ E1 VSSQ E12 VSSQ E14 K4G80325FB-HC25 VSSQ E3 VSSQ F10 VSSQ F5 VSSQ H13 VSSQ H2 VSSQ K13 VSSQ K2 VSSQ M10 VSSQ M5 VSSQ N1 VSSQ N12 VSSQ N14 VSSQ N3 VSSQ R1 VSSQ R11 VSSQ R12 VSSQ R14 VSSQ R3 VSSQ R4 VSSQ V1 VSSQ V12 VSSQ V14 VSSQ V3 VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Normal J1 SOE*/MF_VDD add 1k to VDD add 1k to VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Mirrored FBVDDQ MF_VSS/SOE* VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ B FBVDDQ MF_VSS/SOE* add 1k to VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 B10 B5 D10 G10 G5 H1 H14 K1 K14 L10 L5 P10 T10 T5 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ K4G80325FB-HC25 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A1 A12 A14 A3 C1 C11 C12 C14 C3 C4 E1 E12 E14 E3 F10 F5 H13 H2 K13 K2 M10 M5 N1 N12 N14 N3 R1 R11 R12 R14 R3 R4 V1 V12 V14 V3 A1 VSSQ A12 VSSQ A14 VSSQ A3 VSSQ C1 VSSQ C11 VSSQ C12 VSSQ C14 VSSQ C3 VSSQ C4 VSSQ E1 VSSQ E12 VSSQ E14 K4G80325FB-HC25 VSSQ E3 VSSQ F10 VSSQ F5 VSSQ H13 VSSQ H2 VSSQ K13 VSSQ K2 VSSQ M10 VSSQ M5 VSSQ N1 VSSQ N12 VSSQ N14 VSSQ N3 VSSQ R1 VSSQ R11 VSSQ R12 VSSQ R14 VSSQ R3 VSSQ R4 VSSQ V1 VSSQ V12 VSSQ V14 VSSQ V3 VSSQ G2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3 Sheet 22 of 77 Frame Buffer Partition C_D C G2 GND D D GND GND ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [15,16,17,18,19,20,21,23,28,64] FBVDDQ Size A3 Date: 1 2 3 4 5 6 [22] Frame Buffer Partition C_D Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 22 of 77 8 Frame Buffer Partition C_D B - 23 B.Schematic Diagrams G2 1u x 10 10u x 6 22u x 5 22u_6.3V_X5R_06 22u_6.3V_X5R_06 G2 C808 G2 22u_6.3V_X5R_06 G2 C823 G2 22u_6.3V_X5R_06 G2 22u_6.3V_X5R_06 G2 10u_4V_X6S_06G2 G2 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 *10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 1u x 10 10u x 6 22u x 5 C797 C404 C409 C776 C784 C380 C351 C807 C811 C746 C708 C713 C181 C715 C266 C251 C262 C209 C747 C714 FBVDDQ 22u_4V_X6S_06 22u_6.3V_X6S_08 10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 *10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 47u_2.5V_X6S_08 10u_4V_X6S_06 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 *1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 *1u_6.3V_X6S_04 *1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 NVVDDS 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 *1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 NVVDDS 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 C245 C248 C234 C233 C238 C232 4.7u_6.3V_X6S_06 4.7u_6.3V_X6S_06 4.7u_6.3V_X6S_06 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 4.7u_6.3V_X6S_06 1u_6.3V_X6S_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 22u_6.3V_X6S_08 22u_6.3V_X6S_08 22u_6.3V_X6S_08 22u_6.3V_X6S_08 22u_6.3V_X6S_08 22u_6.3V_X6S_08 22u_6.3V_X6S_08 22u_6.3V_X6S_08 *22u_6.3V_X6S_08 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 77 of 23 4.7u_6.3V_X6S_06 1u_6.3V_X6S_04 C259 C116 4.7u_6.3V_X6S_06 + 47u_2.5V_X6S_08 *330U_2V_D2_D 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 10u_4V_X6S_06 C244 8 7 Sheet W ednesday, July 05, 2017 Date: 10u_4V_X6S_06 47u_2.5V_X6S_08 GND Rev D02A GND 6 5 6-71-PA700-D02A Document Number SCHEMATIC1 Size A3 [23] GPU Decoupling Title FBVDDQ 1V8_AON 1V8_RUN NVVDDS NVVDD [15,16,17,18,19,20,21,22,28,64] [3,24,26,27,28,31,52,53,61,62,64] [14,15,24,28,52] [28,61] [28,62,63] GND *22u_6.3V_X6S_08 1u_6.3V_X6S_04 10u_4V_X6S_06 10u_4V_X6S_06 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 C29 C247 PLACE Near GPU C246 x9 22uF X6S 0805 B 10u_4V_X6S_06 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1V8_RUN GND 22u_6.3V_X6S_08 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 1u_6.3V_X6S_04 1u_6.3V_X6S_04 C 1u_6.3V_X6S_04 C59 GND 1u_6.3V_X6S_04 C110 1u_6.3V_X6S_04 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 C222 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ C80 D C60 1u_6.3V_X6S_04 10u_4V_X6S_06 10u_4V_X6S_06 GND 10u_4V_X6S_06 GND GND C34 GND C44 1u_6.3V_X6S_04 1u_6.3V_X6S_04 1u_6.3V_X6S_04 *10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 C93 C239 MID-FREQ CERAMICS 1u_6.3V_X6S_04 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 *10u_4V_X6S_06 10u_4V_X6S_06 C194 C281 FBVDDQ 4 3 2 1 C153 C280 FBVDDQ C231 GND GND Near GPU C221 PLACE Under GPU C125 C225 C184 C185 C186 C187 C190 C180 C188 C132 x1 330uF x1 47uF X5R 0805 x2 4.7UF 0603 X6S C241 C135 C151 C32 C118 C235 C148 C156 C74 C207 C55 C81 C56 C216 C170 C72 C228 C197 C54 C214 C169 C41 C86 C79 GND x2 10uF, x6 1uF Partition D C117 C113 C114 C115 C127 C227 C223 C189 C191 C196 GND C96 C100 C103 C236 C108 C64 10u_4V_X6S_06 C15 C17 C210 C16 10u_4V_X6S_06 C19 C57 10u_4V_X6S_06 C149 C31 C13 10u_4V_X6S_06 B - 24 GPU Decoupling C12 GND NVVDD GND C733 x4 10uF C199 D C109 C256 C205 C252 PLACE Under GPU NVVDDS NVVDDS Total : x24 1uF x8 10uF C C200 C26 C145 GND C27 C192 C684 x2 10uF, x6 1uF Partition C C63 C14 C224 C195 C52 C65 C178 C215 C208 C171 C137 C158 C147 C112 C139 C160 C124 Sheet 23 of 77 GPU Decoupling GND B C101 C76 C53 C154 C126 C120 C75 C73 C138 C157 C204 C140 C77 C50 C49 C141 C159 C146 C51 C177 C173 C164 x49 1uF X6S 0402 C174 C45 C201 C28 C249 C213 C18 C33 C240 C25 C58 C243 C62 C46 x2 10uF, x6 1uF Partition B C8 C42 C254 GND x12 10uF 0603 X6S A C30 C83 8 7 6 5 x11 10uF X6S 0603 NVVDD NVVDD x4 22uF X5R 0805 x2 47uF X5R 0805 NVVDD x2 10uF, x6 1uF C9 C40 C84 C250 C134 C143 C87 C105 C102 C95 C98 C36 A PLACE Near GPU NVVDD NVVDD Partition A x9 4.7uF 0603 X6S GPU DECOUPLING PLACE Under GPU FBVDDQ FBVDDQ 4 3 2 1 C61 B.Schematic Diagrams Schematic Diagrams GPU Decoupling x16 1uF X6S 0402 x4 10uF X6S 0603 1V8_AON Schematic Diagrams Straps and XTAL 1 2 [25] 3 4 30ohm ESR 10mohm bead GPU_PLLVDD 14/23 XTAL/PLL L17 1V8_RUN . 40mil HCB1608KF-300T60 R71 C729 嶇P950COST_12/27 GPU_PLLVDD Near to GPU 20mil 0_06 0.1u_10V_X7R_04 GND ROM_SI 0 0 1 1 0 0 1 1 Strap 4 ROM_SCLK 0 1 0 1 0 1 1 M Strap 3 SOR_EXPOSED[3:0] 1111 1= DEVID_SEL Rebrand 1110 0= DEVID_SEL Orignal 1101 2016/7/15 Update 1= PCIE_CFG Low Power 1100 0= PCIE_CFG High Power 1011 1010 1= VGA_DEVICE Enable 1000 0= VGA_DEVICE Disable 0000 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE A GPU near 40mil U42 GPCPLL_AVDD0 AF11 GPCPLL_AVDD1 BB24 XS_PLLVDD 1V8_AON C279 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 R66 XTALSSIN BJ6 GND XTALSSIN BL6 10K_04 XTALIN BM6 XTALOUTBUFF Sheet 24 of 77 Straps and XTAL R65 10K_04 GND GCLK_27M_NV R437 0_04 GND XTALIN C726 4 1 XTALOUT 3 2 GND *10p_50V_NPO_04 B C737 *U83-076_27MHZ fsx3m GND *12p_50V_NPO_04 XTAL 6-22-27R00-1BG 6-22-27R00-1BH GND GND 1 = HIGH : Tied to 1.8V M = Middle : Tied to 0.9V 0 = Low : Tied to 0V MULTI-LEVEL STRAPS 1:Enable 0:Disable SOR 0/1/2/3 ENABLE 1V8_AON STRAP[0:2] Setting RAM type VGA_ROM_SCLK R68 100K_1%_04 R69 100K_1%_04 recommend 2 R443 R444 R445 R447 R446 L Strap5 non-Gsync = L Gsync = H DG P.65 recommend strap resistor 5% or better , voltage use 1V8_AON GND DG P.73 STRAP5 C R442 100K_04 R67 *100K_1%_04 STRAP4 R449 100K_04 [26] STRAP3 [26,34] 100K_04 VGA_ROM_SO [26] *100K_04 [26] STRAP2 [26] *100K_04 VGA_ROM_SI STRAP1 [26] 100K_04 aduio playback strapping [26] [26] R453 100K_04 R88 *100K_1%_04 R454 100K_04 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R87 *100K_1%_04 STRAP0 R452 *100K_04 0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 R86 100K_1%_04 [26] R451 100K_04 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1V8_AON R450 *100K_04 1= SMB_ALT_ADDR Enable 0= SMB_ALT_ADDR Disable GND Pull down resistor 100k [11,12,13,14,26,46,52,53,61,62] NV3V3 [14,15,23,28,52] 1V8_RUN [3,23,26,27,28,31,52,53,61,62,64] 1V8_AON D Setting RAM type default Samsung K4G80325FB-HC25 Micron MT51J256M32HF-80:A Hynix H5GQ8H24MJR-R4C Strap B-die 0 X 0 A-die 0 X 1 M-die 0 X 2 4000MHz 256Mx32 4000MHz 256Mx32 4000MHz 256Mx32 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 1 BK6 XTALOUT X3 GPU under [31] XTALOUTBUFF *100K_04 GSYNC ID 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C193 1/26 NV CHECK 0.1u_10V_X7R_04 eDP ID C257 0 1 0 1 0 1 0 1 1 M 0 1 M 0 1 0 1 VID_PLLVDD R84 *100K_04 0.1u_10V_X7R_04 0 0 1 1 0 0 1 1 1 0 M M 1 0 0 1 1 C283 GND C273 0 0 0 0 1 1 1 1 1 0 0 0 0 M M M M SP_PLLVDD BC12 3 4 [24] STRAPS and XTAL Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 24 of 77 5 Straps and XTAL B - 25 B.Schematic Diagrams ROM_SO 0 0 0 0 1 1 1 1 Strap 5 C276 GPU under Default 0.1u_10V_X7R_04 D RAMCFG[4:0] 0 (0x0000) 1/26 1 (0x0001) 2 (0x0002) 3 (0x0003) 4 (0x0004) 5 (0x0005) 6 (0x0006) 7 (0x0007) 8 (0x0008) 9 (0x0009) 10 (0x000A) 11 (0x000B) 12 (0x000C) 13 (0x000D) 14 (0x000E) 15 (0x000F) 16 (0x0010) 17 (0x0011) 18 (0x0012) 19 (0x0013) 20 (0x0014) 21 (0x0015) 22 (0x0016) 23 (0x0017) 24 (0x0018) 25 (0x0019) 26 (0x001A) RAMCFG[4:0] 00000 00010 00011 00110 00111 C237 C Strap 0 0 1 0 1 0 1 0 1 M 0 1 M 0 1 0 1 M 0 1 M M M 0 1 M M M Strap 0 0 0 1 0 1 C278 B Strap 1 0 0 1 1 0 0 1 1 0 M M 1 0 0 1 1 0 M M 1 M 0 M M 1 M M Strap 1 0 1 1 1 1 C258 10u_6.3V_X5R_06 C104 22u_6.3V_X6S_08 4.7u_6.3V_X6S_06 0.1u_10V_X7R_04 22u_4V_X6S_06 Strap 2 0 0 0 0 1 1 1 1 0 0 0 0 M M M M 1 1 1 1 0 M M M M 1 M Strap 2 0 0 0 1 1 BD12 C734 A NV CHECK 5 XTAL U22S INS16552674 DG P.114 Note: PLL power rails trace rounting to GPU BGA ball must be 12~16 mil wide. Schematic Diagrams IFP I/O Interface 1 2 3 IFP I/O INTERFACE 4 U22V INS16555158 U22N INS16554934 U22U INS16554410 11/23 MIOA 12/23 MIOB 7/23 IFPAB DL-DVI DVI/HDMI MIOAD0 MIOAD1 MIOAD2 MIOAD3 MIOAD4 MIOAD5 MIOAD6 MIOAD7 MIOAD8 MIOAD9 MIOAD10 MIOAD11 DP SDA SCL SDA SCL IFPA_AUX IFPA_AUX TXC TXC TXC TXC IFPA_L3 IFPA_L3 BH11 BG11 BF21 BG21 A BD23 B.Schematic Diagrams BD21 IFPAB_RSET AM5 MIOACAL_PD_VDDQ TXD0 TXD0 TXD0 TXD0 IFPA_L2 IFPA_L2 BG23 BH23 AM6 MIOACAL_PU_GND TXD1 TXD1 TXD1 TXD1 IFPA_L1 IFPA_L1 BF23 BE23 AM7 MIOA_VREF TXD2 TXD2 TXD2 TXD2 IFPA_L0 IFPA_L0 BF24 BG24 Sheet 25 of 77 IFP I/O Interface AN9 AM2 AN7 AN6 AR1 AR6 AR5 AM8 AN3 AR8 AR3 AR2 AV7 MIOBCAL_PD_VDDQ AV8 MIOBCAL_PU_GND BB17 BB15 IFP_IOVDD IFP_IOVDD BB18 BB20 IFP_IOVDD IFP_IOVDD B SDA SCL IFPB_AUX IFPB_AUX BG12 BH12 TXC TXC IFPB_L3 IFPB_L3 BL18 BK18 TXD3 TXD3 TXD0 TXD0 IFPB_L2 IFPB_L2 BK20 BL20 TXD4 TXD4 TXD1 TXD1 IFPB_L1 IFPB_L1 BM20 BM21 TXD5 TXD5 TXD2 TXD2 IFPB_L0 IFPB_L0 BL21 BK21 AW9 MIOA_CTL3 MIOA_HSYNC MIOA_VSYNC MIOA_DE AT7 AM1 AR7 AN1 MIOA_CLKOUT AN2 MIOA_CLKIN AM3 AT3 AV6 AT2 AT1 AW6 AV2 AV1 AV3 AW3 BA8 AW7 BB8 MIOB_CTL3 MIOB_HSYNC MIOB_VSYNC MIOB_DE BB7 AV5 BA7 AW2 MIOB_CLKOUT AW1 A MIOB_VREF GP104 GP106 MIOB B DG P.245 requires IFPx_RSET Pull down 1K_1% resistor 1K_1%_04 BD20 R43 GND HDMI 8/23 IFPC IFPCD_RSET DVI/HDMI 40 mil GND KAI_12/1 U22P INS16554122 DG P.245 requires IFPx_RSET Pull down 1K_1% resistor R40 1K_1%_04 BD17 DP+TYPE C R434 20 mil BD15 IFPEF_PLLVDD C218 TXC TXC IFPE_L3 IFPE_L3 BG14 BH14 MDP_E#3 MDP_E3 IFPE GND BD18 TXD0 TXD0 IFPE_L2 IFPE_L2 BF14 BE14 MDP_E#2 MDP_E2 TXD1 TXD1 IFPE_L1 IFPE_L1 BF15 BG15 MDP_E#1 MDP_E1 TXD2 TXD2 IFPE_L0 IFPE_L0 BG17 BH17 MDP_E#0 MDP_E0 GND IFPC MDP_E_AUX#_SDA [11,46] MDP_E_AUX_SCL [11,46] PEX_VDD MDP_E#2 [46] MDP_E2 [46] IF_IOVDD R46 R44 PLACE Under GPU PLACE Near GPU 20 mil IF_IOVDD 0_06 0_06 C217 MDP_E#1 [46] MDP_E1 [46] BB21 BB23 C182 4.7u_6.3V_X6S_06 C198 1u_6.3V_X6S_04 BL9 BK9 SDA SCL IFPC_AUX IFPC_AUX TXC TXC IFPC_L3 IFPC_L3 BF17 BE17 TXD0 TXD0 IFPC_L2 IFPC_L2 BF18 BG18 TXD1 TXD1 IFPC_L1 IFPC_L1 BG20 BH20 TXD2 TXD2 IFPC_L0 IFPC_L0 BF20 BE20 HDMI_CTRLDATA HDMI_CTRLCLK HDMI_CLOCKN HDMI_CLOCKP [13] [13] [13] [13] HDMI_DATA0N HDMI_DATA0P [13] [13] HDMI_DATA1N HDMI_DATA1P [13] [13] HDMI_DATA2N HDMI_DATA2P [13] [13] IFP_IOVDD IFP_IOVDD C 0.1u_10V_X7R_04 MDP_E#0 [46] MDP_E0 [46] GND BC18 BC20 IFPCD_PLLVDD 0.1u_10V_X7R_04 MDP_E#3 [46] MDP_E3 [46] ʼnŅŎŊ DP PLACE AT BALLS IF_PLLVDD . HCB1608KF-300T60 ŮŪůŪġġŅőŠņ MDP_E_AUX#_SDA MDP_E_AUX_SCL BL8 BK8 IFPE_AUX IFPE_AUX 0.1u_10V_X7R_04 C L1 100K_04 DP SDA SCL PLACE AT BALLS IF_PLLVDD GPU_PLLVDD R435 100K_04 DVI/HDMI [24] C219 10/23 IFPE IFPEF_RSET AT6 MIOB_CLKIN UNUSED U22R INS16554806 IFPAB GND MIOBD0 MIOBD1 MIOBD2 MIOBD3 MIOBD4 MIOBD5 MIOBD6 MIOBD7 MIOBD8 MIOBD9 MIOBD10 MIOBD11 IFPAB_PLLVDD IF_IOVDD IF_IOVDD 5 GND IFP_IOVDD IFP_IOVDD GND U22Q INS16554634 eDP GND U22O INS16554010 9/23 IFPD DP R50 R428 6/23 IFPF DVI/HDMI PLACE Near GPU PLACE Under GPU 20 mil IF_IOVDD C226 4.7u_6.3V_X6S_06 GND C203 C206 0.1u_10V_X7R_04 0.1u_10V_X7R_04 BC21 BC23 IFP_IOVDD IFP_IOVDD 100K_04 DP IFPF BM9 BM8 SDA SCL IFPF_AUX IFPF_AUX TXC TXC IFPF_L3 IFPF_L3 BK11 BL11 TXD0 TXD0 IFPF_L2 IFPF_L2 BM11 BM12 TXD1 TXD1 IFPF_L1 IFPF_L1 BL12 BK12 TXD2 TXD2 IFPF_L0 IFPF_L0 BK14 BL14 MDP_F_AUX#_SDA MDP_F_AUX_SCL [12] [12] MDP_F#3 [12] MDP_F3 [12] IFPD MDP_F#2 [12] MDP_F2 [12] MDP_F#1 [12] MDP_F1 [12] PLACE Under GPU MDP_F#0 [12] MDP_F0 [12] IF_IOVDD 20 mil C183 1u_6.3V_X6S_04 GND 100K_04 DP 100K_04 ŮŪůŪġġŅőŠŇ GND D DVI/HDMI R430 SDA SCL IFPD_AUX IFPD_AUX BF11 BE11 TXC TXC IFPD_L3 IFPD_L3 BM14 BM15 TXD0 TXD0 IFPD_L2 IFPD_L2 BL15 BK15 TXD1 TXD1 IFPD_L1 IFPD_L1 BK17 BL17 TXD2 TXD2 IFPD_L0 IFPD_L0 BM17 BM18 B - 26 IFP I/O Interface DEDP_D#3 DEDP_D3 [3] [3] DEDP_D#2 DEDP_D2 [3] [3] DEDP_D#1 DEDP_D1 [3] [3] DEDP_D#0 DEDP_D0 [3] [3] [3] [3] C211 0.1u_10V_X7R_04 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ GND PEX_VDD 4 [25] IFP I/O Interface Size Document Number Custom SCHEMATIC1 Date: 3 DEDP_D_AUX#_SDA DEDP_D_AUX_SCL IFP_IOVDD IFP_IOVDD [14,53] 2 ŦŅőŠŅ 100K_04 D BC15 BC17 Title 1 R48 Rev D02A 6-71-PA700-D02A Sheet Wednesday, July 05, 2017 5 25 of 77 Schematic Diagrams Misc - GPIO, I2C and ROM 2 3 4 MISC: GPIO, I2C, and ROM 15/23 MISC 2 ROM_SI ROM_SO ROM_SCLK BK2 BK4 BK3 VGA_ROM_SI R466 VGA_ROM_SO R462 VGA_ROM_SCLK R464 33_04 0_04 33_04 5 SMD_VGA_THERM [35,36,44] 1V8_AON R470 10K_04 HDMI IVGA_ROM_CS# GPIO27_IFPC_HPD_R R110 100K_04 D [53] [53] FROM HDMI CONN B Q34 BTN3904 M-SOT23-CBE DVGA_ROM_CS# R480 100K_04 HDMI_HPD [13,32] R472 6 C769 1 C773 Q7B MTDK3S6R 4.7K_04 SMC_VGA_THERM 4.7K_04 SMD_VGA_THERM R109 R93 GPIO27_IFPC_HPD_R 3 Q10B MTDK3S6R MTDK3S6R Q10A VGA_ROM_CS# 3 10K_04 OVERT# VDD3 3.3VS [35,36,44] *10K_04 GPIO23_GPU_PEX_RST_HOLD# R90 Q9 2 G NVJTAG_SEL C S 枸䔁 1V8_AON 12 C742 VGA_ROM_CS# VCC 1 3 9 VGA_ROM_SO 0B0 1B0 A0 GND S0 VCC 4 6 0B1 1B1 A1 GND S1 2 11 IVGA_ROM_CS# DVGA_ROM_CS# L :PORT1 (INTEL) H: PORT2 (NV) 10 5 8 R121 IVGA_ROM_SO_R DVGA_ROM_SO_R 7 1V8_AON FROM 8330B_RE C 100K_04 MDP_F_HPD R469 10K_04 DP_E GPIO12_AC_DETECT_R GPIO18_IFPE_HPD_R D51 C FROM 8330B_RE B A D 3 4 S *MTDK3S6R VGA_BKLPW M 2G 1 D SMTDK3S6R [10] [35] VBATT_BOOST# SMTDK3S6R D Q8B 5G 4 D Q3A SMTDK3S6R GPIO12_AC_DETECT_R [3,8,9,10,11,12,13,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS SMTDK3S6R [11,12,13,14,46,52,53,61,62] NV3V3 [5,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [14,15,23,24,28,52] 1V8_RUN WEY_11/24 [3,23,24,27,28,31,52,53,61,62,64] 1V8_AON Title Size A3 Date: 1 2 3 4 5 6 D ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ wey_12/1 GPIO7_BL_PW M_GPU 5G SMTDK3S6R [11,32,46] D SMTDK3S6R Q3B Q6B GPIO13_BLEN 5G MDP_E_HPD Q8A 1 3 R62 100K_04 3 10K_04 100K_04 100K_04 [10] 4 R70 R75 R438 VGA_BKLTEN Q6A 1 GPIO8_MEM_VDD_CTL GPIO10_ALT_MEM_VREF GPIO21_RASTER_SYNC0 10K_04 AC/BATL#5G AC/BATL# 2G D 2G 3 100K_04 100K_04 100K_04 4 R77 R441 R439 6 R106 100K_04 D 100K_04 Q61B [60] 10K_04 10K_04 wey_11/22 GPIO7_BL_PW M_GPU GPIO11_PPEN GPIO13_BLEN 3.3VS R59 6 3.3VS R105 6 470p_50V_X7R_04 470p_50V_X7R_04 VGA_BKLPWM 3.3VS 3.3VS 100K_04 1V8_AON 220p_50V_NPO_04 RB751S-40H VDD3 R473 *220p_50V_NPO_04 Q33 BTN3904 M-SOT23-CBE R482 AC_IN# GPIO18_IFPE_HPD_R [12,32] C770 100K_04 D C270 C268 VGA_BKLTEN 2.2K_04 I2CC_SCL 2.2K_04 I2CC_SDA [3,10,26,32,48] śɥ śɨ C775 *220p_50V_NPO_04 220p_50V_NPO_04 DG P.261 use 2.2k pull-up on both I2C_SDA/SCL kai_12/6 PS8331_SW R127 *12K_04 R104 R80 R82 *0_04 *PI5A3158BZAE P/N = 6-03-53158-0J1 PR425 100K_04 NV3V3 B U3 *0.1u_16V_Y5V_04 GPIO24_IFPF_HPD_R R468 GND 10K_04 C767 R41 10K_04 R440 10K_04 GPIO0_NVVDD_PW M_VID [62] BD6 CHECK EC PIN76 BB5 GC6_FB_EN [27] GPIO2_GPU_EVENT# BD1 BE4 C D20 A GPIO3_PS_NVVDDS_VID [61] GPU_EVENT# [32] BE1 RB751S-40H GPIO4_1V8_MAIN_EN [27] BG2 GPIO5_FRAME_LOCK# [10] BD2 GPIO6_NVVDD_PSI# [61,62] BD7 GPIO7_BL_PW M_GPU 1V8_AON BH4 GPIO8_MEM_VDD_CTL [64] BJ3 GPIO9_THERM_ALERT# BD3 GPIO10_ALT_MEM_VREF [16,17,20,21] BH3 GPIO11_PPEN [10] BE6 R471 GPIO12_AC_DETECT_R BB1 10K_04 GPIO13_BLEN DP_F BG4 BG1 GPIO24_IFPF_HPD_R BE2 GPIO16_SYS_PEX_RST_MON# T58 BH1 GPIO17_IFPD_HPD_R [3] BE3 GPIO18_IFPE_HPD_R BD4 GPIO20_NVVDDS_PSI [61] BE5 B R475 BA5 GPIO21_RASTER_SYNC0 Q35 BB6 BTN3904 BG3 GPIO23_GPU_PEX_RST_HOLD# M-SOT23-CBE T57 GPIO24_IFPF_HPD_R BD5 BB2 BE7 GPIO27_IFPC_HPD_R BA4 BB4 GPIO28_OC_W ARN# [53] BA3 GPIO29_NVVDD_PH1 [62] [35,60] BB3 BA2 BA1 C765 GND R455 DG P.290 recommend C NVJTAG_SELBK23 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST 2SK3018S3 E BK24 BL23 BM23 BM24 BL24 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31_RFU GPIO32_RFU G PS8331_SW C THERMDP E BJ2 [3,10,26,32,48] 1V8_AON 1V8_AON 100K_04 R42 10K_04 THERMDN 2K_04 2K_04 *220p_50V_NPO_04 T117 T118 T119 T120 JTAG_TRST* BJ1 R95 R96 220p_50V_NPO_04 B Sheet 26 of 77 Misc - GPIO, I2C and ROM [26] Misc-GPIO_I2C_ROM Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 26 of 77 8 Misc - GPIO, I2C and ROM B - 27 B.Schematic Diagrams 5 4 GND D BG8 BF8 C741 A SI SO SCK W 25Q80EW SNIG PCB Footprint = M-SO8 M WIN:6-04-02580-A71 S MX:6-04-25803-A70 S I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA SMC_VGA_THERM 10K_04 GPIO4_1V8_MAIN_EN 10K_04 GPIO5_FRAME_LOCK# *10K_04 GPIO16_SYS_PEX_RST_MON# 10K_04 GPIO9_THERM_ALERT# R801 D 4 8 VCC IVGA_DVGA ROM SWITCH 6 D BG9 BH9 DVGA_ROM_SI 5 DVGA_ROM_SO_R2 DVGA_ROM_SCLK6 S BJ8 SMC_VGA_THERM1 BH8 SMD_VGA_THERM1 I2CC_SCL I2CC_SDA 33_04 0_04 33_04 4 1 2.2K_04 2.2K_04 S TS_VREF 33_04 VGA_ROM_SI R467 VGA_ROM_SO R463 VGA_ROM_SCLK R465 D I2CS_SCL I2CS_SDA DVGA_ROM_CS# R458 HOLD WP CS G 10K_04 R94 R108 NV3V3 OVERT 4 GND C740 7 3 DVGA_ROM_CS#_R 1 10K_04 0.1u_10V_X7R_04 Q7A MTDK3S6R R115 NV3V3 SI SO SCK G BF12 IVGA_ROM_SI 5 IVGA_ROM_SO_R 2 IVGA_ROM_SCLK 6 8 VCC W 25Q40EW 1.8V PCB Footprint = M-SO8 M WIN:6-04-02540-A71 S GD:6-04-02540-491 S T8 IVGA_ROM_CS# R461 U26 HOLD WP CS G TS_VREF U25 10K_04 GPIO12 ℵ䡢娵㗗pull hi 10K or 100K , DG is 100K R448 R89 R802 R85 R457 R456 7 3 33_04 IVGA_ROM_CS#_R1 C299 GND 13/23 MISC 1 BG5 OVERT# VGA_ROM_SI [24] VGA_ROM_SO [24] VGA_ROM_SCLK [24] BF9 GPU_BUFRST* U22W INS16557386 [27,35] 1V8_AON 1V8_AON BUFRST ɰɭ 8 VBIOS ROM 8M (DGPU) 1V8_AON 1V8_AON VGA_ROM_CS# 2 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5 7 0.1u_10V_X7R_04 BL3 BL4 BM4 BM5 BK5 BJ5 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5 BJ4 6 0.1u_10V_X7R_04 [24] [24] [24] [24] A [24] [24,34] 1V8_AON ROM_CS 5 VBIOS ROM 4M (OPTIMUS) C U22T INS16557882 E 1 Schematic Diagrams NVIDIA Power Sequence 1 2 3 1 [35] [26,35] [52] [61] 3 OVERT# 4 1V8_AON_PG NVVDDS_PW RGD NVVDDS_PW RGD [26] [10,32,35] [32] GC6_FB_EN_PCH GC6_FB_EN_PCH 7 8 PLT_RST# DGPU_RST#_PCH DGPU_RST#_PCH [14] 5 6 GC6_FB_EN [30,34] B.Schematic Diagrams 2 NV_EN_DOW N GPU_PEX_RST# GPU_PEX_RST# 5 6 7 8 U6 3.3V A 4 9 10 VDD VIN_DOWN OVERT# 1V8_AON_PG NVVDDS_PWRGD GC6_FB_EN GC6_FB_EN_PCH PLT_RST# dGPU_RST#_PCH GPU_PEX_RST# FBVDDQ_EN PEX_VDD_EN NVVDDS_EN NVVDD_EN 3V3_SYS_EN 1V8_MAIN_EN 1V8_AON_EN GPIO4_1V8_MAIN_EN dGPU_PWR_EN GND 20 19 18 17 NV_FBVDDQ_EN [64] NV_PEXVDD_EN [53] NV_NVVDDS_EN [61] NV_NVVDD_EN 16 NV_3V3_EN 15 14 [62,63] [52] NV_1V8RUN_EN [52] NV_1V8AON_EN [52] 13 A GPIO4_1V8_MAIN_EN DGPU_PW R_EN 12 DGPU_PW R_EN [26] [32,35] 11 SLG4U41681 Sheet 27 of 77 NVIDIA Power Sequence [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V B B D4 [14,62] NVVDD_PW RGD A NVVDDS_PW RGD C RB751S-40H 1V8_AON GPU_PEX_RST# R141 10K_04 DGPU_PW R_EN R145 10K_04 GC6_FB_EN_PCH R490 *10K_04 DGPU_RST#_PCH R138 *10K_04 C C D D [3,23,24,26,28,31,52,53,61,62,64] [2,10,27,38,43,45,48,50,51,52,55,56] ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ 1V8_AON 3.3V Title Size A3 Date: 1 B - 28 NVIDIA Power Sequence 2 3 4 5 6 [27] NVIDIA POWER SEQUENCE Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 27 of 8 77 Schematic Diagrams GPU NVVDD, FBVDDQ 1 NVVDD U22F INS16565366 2 NVVDD NVVDD 18/21 VDD_1/2 A C D AG22 AG23 AG40 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AH35 AH36 AH37 AH38 AH39 AK19 AK20 AK21 AK22 AK23 AK30 AK31 AK32 AK33 AK34 AL13 AL40 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 AP19 AP20 BK52 BL46 BL47 BL48 BL49 BL50 BL51 BL52 BM47 BM48 BM49 BM50 BM51 N14 N18 N22 N26 N27 N31 N35 N39 P13 P40 R19 R20 R21 R22 R23 R30 R31 R32 R33 R34 U14 U15 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD FBVDDQ 20/23 FBVDDQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD BB45 BB46 BB47 BB48 BC38 BC39 BC40 BC41 BC45 BC47 BC49 BD39 BD41 BD46 BD47 BD48 BD49 BD50 BD51 BE41 BE42 BE43 BE46 BE47 BE48 BE49 BE50 BE51 BE52 BF42 BF44 BF45 BF47 BF49 BF51 BG43 BG44 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U38 U39 V13 V40 W19 W20 W21 W22 W23 W30 W31 W32 W33 W34 NVVDD_SENSE GND_SENSE BK45 BL45 AA10 AA11 AA42 AA43 AC10 AC11 AC42 AC43 AD10 AD11 AD42 AD43 AF10 AF43 AG10 AG11 AG42 AG43 AJ10 AJ11 AJ42 AJ43 AK10 AK11 AK42 AK43 AM42 AM43 AN43 AR42 AR43 R42 R43 U10 U11 U43 V10 V42 V43 Y10 Y11 Y42 Y43 FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ_SENSE AT43 K12 K14 K15 K17 K18 K20 K21 K23 K24 K26 K27 K29 K30 K32 K33 K35 K36 K38 K39 K41 L14 L15 L18 L20 L21 L23 L24 L26 L27 L30 L32 L33 L35 L36 L39 M10 M43 P10 P11 P42 P43 R10 R11 AT9 BA6 BA9 BD14 BE12 BG6 BH6 BJ11 BJ9 BK44 NC NC NC NC NC NC NC NC NC NC E52 FBVDDQ_SENSE_R49R416 GND 6 R417 FB_VREF_PROBE 8 U22J INS16567134 NVVDDS 23/23 VDDS 1V8_AON AP27 AP28 AP29 AP35 AP36 AP37 AP38 AP39 AV14 1V8_RUN AV15 AV16 AV17 VDD18 AM10 AV18 VDD18 AM11 AV24 AN10 VDD18 AV25 VDD18 AN11 AV26 VDD18 AR10 AV27 VDD18 AR11 AV28 VDD18 AT10 AV29 VDD18 AT11 AV35 AV10 VDD18 AV36 VDD18 AV11 AV37 VDD18 AW10 AV38 VDD18 AW11 AV39 R14 R15 R16 R17 R18 R24 R25 R26 R27 R28 R29 R35 R36 R37 R38 R39 W14 W15 W16 PLACE WEST EDGE OF FBD W17 W18 R15 *2.2_04 W24 FBVDDQ W25 W26 W27 2.2_04 FBVDDQ_SENSE W28 FBVDDQ_SENSE [53,64] W29 FBVDDQ_SENSE_RTN *2.2_04 FBVDDQ_SENSE_RTN [53,64] W35 W36 PLACE NEAR U1 PIN E52 W37 W38 W39 1V8_AON 1V8_AON 1V8_AON BA10 BB14 BC14 FB_VREF P45 FB_CAL_PD_VDDQ R44 FB_CAL_PD_VDDQ R25 40.2_1%_04 FB_CAL_PU_GND P44 FB_CAL_PU_GND R21 40.2_1%_04 FB_CALTERM_GND R45 FB_CAL_TERM_GNDR20 60.4_1%_04 FBVDDQ VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS AC14 AC15 AC16 AC17 AC18 AC24 AC25 AC26 AC27 AC28 AC29 AC35 AC36 AC37 AC38 AC39 AF14 AF15 AF16 AF17 AF18 AF24 AF25 AF26 AG27 AG28 AG29 AG35 AG36 AG37 AG38 AG39 AK14 AK15 AK16 AK17 AK18 AK24 AK25 AK26 AK27 AK28 AK29 AK35 AK36 AK37 AK38 AK39 AP14 AP15 AP16 AP17 AP18 AP24 AP25 AP26 VDDS_SENSE GNDS_SENSE BM45 BM44 VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS A B GPU_VDDS_SENSE GPU_GNDS_SENSE Sheet 28 of 77 GPU NVVDD, FBVDDQ [61] [61] C GND GPU_NVVDD_SENSE [53,62] GPU_GND_SENSE [53,62] 㓦军NV側朊 NVVDD D G2ㇵ ㇵᶲẞ C152 C202 + + [3,23,24,26,27,31,52,53,61,62,64] [14,15,23,24,52] [15,16,17,18,19,20,21,22,23,64] [23,62,63] [23,61] GND 6-11-2271C-VB1 1 7 NVVDDS U22I INS16563942 21/23 NC/1V8 19/23 VDD_2/2 AP21 AP22 AP23 AP30 AP31 AP32 AP33 AP34 AR13 AR40 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT42 AU43 AV19 AV20 AV21 AV22 AV23 AV30 AV31 AV32 AV33 AV34 AV42 AV43 AV44 AW13 AW40 AW42 AW43 AW44 AW45 AY14 AY18 AY22 AY26 AY27 AY31 AY35 AY39 AY43 AY45 BA43 BA44 BA45 BA46 BA47 BB38 BB39 5 U22H INS16563190 220u_2V_SMD-V VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 4 FBVDDQ 220u_2V_SMD-V VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NVVDD U22G INS16564158 2 3 4 1V8_AON 1V8_RUN FBVDDQ NVVDD NVVDDS ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 5 6 [28] GPU NVVDD, FBVDDQ Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 28 of 77 8 GPU NVVDD, FBVDDQ B - 29 B.Schematic Diagrams B AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AA39 AB13 AB40 AC19 AC20 AC21 AC22 AC23 AC30 AC31 AC32 AC33 AC34 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AE35 AE36 AE37 AE38 AE39 AF13 AF30 AF31 AF32 AF33 AF34 AF40 AG13 AG19 AG20 AG21 BG45 BG46 BG47 BG48 BG49 BG50 BG51 BG52 BH44 BH45 BH47 BH48 BH49 BH50 BH51 BH52 BJ44 BJ45 BJ46 BJ47 BJ48 BJ49 BJ50 BJ51 BJ52 BK47 BK48 BK49 BK50 BK51 3 GPU NVVDD, FBVDDQ Schematic Diagrams GPU GND 1 2 GPU GND 4 Sheet 29 of 77 GPU GND B C D GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5 6 U22L INS16575970 16/23 GND_1/3 A2 A26 A29 A3 A32 A50 A51 AA49 AA8 AB10 AB14 AB15 AB16 AB17 AB18 AB19 AB2 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB4 AB43 AB45 AB47 AB49 AB51 AB6 AB8 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD44 AE10 AE2 AE4 AE43 AE45 AE47 AE49 AE51 AE6 AE8 AF1 AF19 AF20 AF21 AF22 AF23 AF27 AF28 AF29 AF35 AF36 AF37 AF38 AF39 AF45 AF5 AG14 AG15 AG16 AG17 AG18 AG24 AG25 AG26 AG3 AG30 AG31 AG32 AG33 AG34 AG44 AH10 AH2 AH4 AH43 AH45 AH47 AH49 AH51 A B.Schematic Diagrams 3 U22K INS16572314 17/23 GND_2/3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AH6 AH8 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ2 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ9 AK1 AK44 AK47 AL10 AL14 AL15 AL16 AL17 AL18 AL19 AL2 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AL37 AL38 AL39 AL4 AL43 AL45 AL47 AL49 AL51 AL6 AL8 AM4 AM9 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN4 AN5 AN8 AP10 AP2 AP4 AP43 AP45 AP47 AP49 AP51 AP6 AP8 AR14 AR15 AR16 AR17 AR18 AR19 BL37 BD24 BC24 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39 AR4 AR52 AR9 AT4 AT5 AT51 AT52 AT8 AU10 AU14 AU15 AU16 AU17 AU18 AU19 AU2 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 AU4 AU45 AU47 AU49 AU51 AU6 AU8 AV4 AV45 AV9 AW14 AW15 AW16 AW17 AW18 AW19 AW20 AW21 AW22 AW23 AW24 AW25 AW26 AW27 AW28 AW29 AW30 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AW39 AW4 AW46 AW5 AW52 AW8 AY10 AY2 AY4 AY47 AY49 AY51 AY6 AY8 B1 B10 B13 B16 B19 B2 B22 B25 B28 B31 B34 B37 B40 B43 B46 B48 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 7 22/23 GND_3/3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B52 B7 BA48 BB49 BC13 BC16 BC19 BC2 BC22 BC25 BC28 BC31 BC34 BC37 BC4 BC51 BC6 BC8 BD26 BD29 BD32 BD35 BD38 BD52 BE10 BE13 BE15 BE16 BE18 BE19 BE21 BE22 BE24 BE25 BE27 BE28 BE30 BE31 BE33 BE34 BE36 BE37 BE39 BE40 BF2 BF4 BF41 BF6 BG10 BG13 BG16 BG19 BG22 BG25 BG28 BG31 BG34 BG37 BG40 BG42 BG7 BH15 BH18 BH2 BH21 BH24 BH27 BH30 BH33 BH36 BH39 BH42 BH5 BJ10 BJ12 BJ13 BJ14 BJ15 BJ16 BJ17 BJ18 BJ19 BJ20 BJ21 BJ22 BJ23 BJ24 BJ25 BJ26 BJ27 BJ28 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BJ37 BJ38 BJ39 BJ40 BJ41 BJ42 BJ43 BJ7 BK1 BL1 BL10 BL13 BL16 BL19 BL2 BL22 BL25 BL28 BL31 BL34 B5 B51 BL43 BL5 BL7 BM2 BM3 C1 C29 C33 C5 C51 C52 D10 D12 D13 D16 D19 D22 D24 D25 D28 D30 D31 D34 D37 D4 D40 D43 D46 D49 D7 E2 E4 E48 E5 E51 E8 F10 F13 F16 F17 F19 F21 F22 F25 F28 F31 F34 F35 F37 F40 F43 F44 F46 F52 F7 G2 G38 G4 G47 G49 G51 G6 H1 H10 H13 H16 H19 H22 H25 H28 H31 H34 H37 H40 H43 J1 J12 J17 J20 J38 J49 J52 K13 K16 K19 K2 K22 K25 K28 K31 K34 K37 K4 K40 K45 K47 K49 K51 K6 K8 M52 M6 N10 N2 N4 N43 N45 N47 N49 N51 BL40 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND N6 N8 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P51 R49 R52 T10 T14 T15 T16 T17 T18 T19 T2 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T4 T43 T45 T47 T49 T51 T6 T8 U7 U9 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 V39 V49 V52 W10 W2 W4 W43 W45 A B C GND D GND ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title GND GND GND GND [29] GPU GND Size Document Number Custom SCHEMATIC1 Date: 1 B - 30 GPU GND 2 3 4 8 U22M INS16574250 5 6 7 Rev D02A 6-71-PA700-D02A Wednesday, July 05, 2017 Sheet 29 8 of 77 Schematic Diagrams PCH 1/5 5 BOOT HALT ENABLE:LOW (INTERNAL WEAK PD) 4 JTAG ODT DISABLE:LOW (INTERNAL WEAK PU) SPI_SI_R SPI_SO_R R542 R545 *4.7K_04 *4.7K_04 3 2 1 ESPI FLASH SHARING MODE MASTER ATTACHED FLASH SHARING:LOW SLAVE ATTACEHD FLASH SHARING:HIGH (INTERNAL WEAK PD) 3.3VA GPP_G_14_GSXDIN: DMI AC COUPLING FULL VOLTAGE MODE WHEN SAMPLED LOW R552 *4.7K_04 GPP_H_12 U30A D CONSENT STRAP ENABLE:LOW (INTERNAL WEAK PU) PESONALITY STRAP ENABLE:LOW (INTERNAL WEAK PU) SPI_IO2 SPI_IO3 R206 R215 *4.7K_04 *1K_04 [32,35,38,42,48] LAN_W AKEUP# AR19 AN17 VDD3 R535 R548 R231 33_04 33_04 *2.2K_04 SPI_SI_R SPI_SO_R SPI_CS_0# SPI_SCLK_R BB29 BE30 BD31 BC31 AW31 SPI_IO2 SPI_IO3 SPI_CS2# BC29 BD30 AT31 AN36 AL39 AN41 AN38 AH43 AG44 TBTA_ACE_GPIO2 TBTA_ACE_GPIO3 TBTA_ACE_GPIO0 TBTA_MRESET TBTA_ACE_GPIO7 [44] TBTA_ACE_GPIO2 [44] TBTA_ACE_GPIO3 [44] TBTA_ACE_GPIO0 [44] TBTA_MRESET [44] TBTA_ACE_GPIO7 GPP_A11/PME# GPP_B13/PLTRST# RSVD RSVD RSVD RSVD GPP_G16/GSXCLK GPP_G12/GSXDOUT GPP_G13/GSXSLOAD GPP_G14/GSXDIN GPP_G15/GSXSRESET# TP2 TP1 GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1# GPP_H18/SML4ALERT# GPP_H17/SML4DATA GPP_H16/SML4CLK GPP_H15/SML3ALERT# GPP_H14/SML3DATA GPP_H13/SML3CLK GPP_H12/SML2ALERT# GPP_H11/SML2DATA GPP_H10/SML2CLK SPI0_IO2 SPI0_IO3 SPI0_CS2# GPP_D1/SPI1_CLK GPP_D0/SPI1_CS# GPP_D3/SPI1_MOSI GPP_D2/SPI1_MISO GPP_D22/SPI1_IO3 GPP_D21/SPI1_IO2 INTRUDER# D BB27 PLT_RST# TBT_FRC_PW R TBCIO_PLUG_EVENT P43 R39 R36 R42 R41 [27,34] TBT_FRC_PW R [42] TBCIO_PLUG_EVENT [42] GPP_G_14_GSXDIN 3.3VS EXTTS_SNI_DRV0_PCH R235 TCH_PNL_INTR_N R559 BT_RF_KILL_R_N EXTTS_SNI_DRV1_PCH R529 AF41 AE44 BC23 BD24 BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34 SML4ALERT# SML4DATA SML4CLK SML3ALERT# SML3DATA SML3CLK GPP_H_12 SML2DATA SML2CLK BE11 R157 330K_04 *8.2K_04 *10K_04 *8.2K_04 Sheet 30 of 77 PCH 1/5 VCC_RTC HM175 C C SPI_* = 1"~6.5" SPT-H_PCH U30B RTC Wake UP VDD3 [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] BIOS + ME ROM 8MB U31 8 VDD SI SO C829 0.1u_10V_X7R_04 R538 3.3K_1%_04 SPI_W P# R532 3.3K_1%_04 SPI_HOLD#7 3 WP# CE# SCK HOLD# VSS 5 SPI_SI_M R543 33_04 SPI_SI_R 2 SPI_SO_M R531 33_04 SPI_SO_R 1 SPI_CS0# R526 0_04 SPI_CS_0# 6 SPI_SCLK_M R539 33_04 SPI_SCLK_R 4 GD25B64CSIGR DMI_MT_IR_0_DN DMI_MT_IR_0_DP DMI_IT_MR_0_DN DMI_IT_MR_0_DP DMI_MT_IR_1_DN DMI_MT_IR_1_DP DMI_IT_MR_1_DN DMI_IT_MR_1_DP DMI_MT_IR_2_DN DMI_MT_IR_2_DP DMI_IT_MR_2_DN DMI_IT_MR_2_DP DMI_MT_IR_3_DN DMI_MT_IR_3_DP DMI_IT_MR_3_DN DMI_IT_MR_3_DP R191 64M GD:6-04-02564-A75 MXIC:6-04-25647-490 WINBOND: 6-04-02564-470 B TBT GLAN SD4.0 PCIE_RXN1_TBT PCIE_RXP1_TBT PCIE_TXN1_TBT PCIE_TXP1_TBT PCIE_TXN2_TBT PCIE_TXP2_TBT PCIE_RXN2_TBT PCIE_RXP2_TBT PCIE_RXN3_TBT PCIE_RXP3_TBT PCIE_TXN3_TBT PCIE_TXP3_TBT PCIE_RXN4_TBT PCIE_RXP4_TBT PCIE_TXN4_TBT PCIE_TXP4_TBT [48] PCIE_RXN5_GLAN [48] PCIE_RXP5_GLAN [48] PCIE_TXN5_GLAN [48] PCIE_TXP5_GLAN [48] PCIE_RXN6_SD40 [48] PCIE_RXP6_SD40 [48] PCIE_TXN6_SD40 [48] PCIE_TXP6_SD40 WLAN WiGig [38] [38] [38] [38] [38] [38] [38] [38] 100_1%_04 PCIECOMP_N PCIECOMP_P B18 C17 H15 G15 C810 0.22u_10V_X5R_04 PCIETXN1 A16 C812 0.22u_10V_X5R_04 PCIETXP1 B16 C817 0.22u_10V_X5R_04 PCIETXN2 B19 C822 0.22u_10V_X5R_04 PCIETXP2 C19 E17 G17 L17 K17 C824 0.22u_10V_X5R_04 PCIETXN3 B20 C827 0.22u_10V_X5R_04 PCIETXP3 C20 E20 G19 C831 0.22u_10V_X5R_04 PCIETXN4 B21 C833 0.22u_10V_X5R_04 PCIETXP4 A21 K19 L19 C835 0.1u_10V_X7R_04 PCIETXN5 D22 C838 0.1u_10V_X7R_04 PCIETXP5 C22 G22 E22 C841 0.1u_10V_X7R_04 PCIETXN6 B22 C845 0.1u_10V_X7R_04 PCIETXP6 A23 L22 PCIE_RXN7_W LAN K22 PCIE_RXP7_W LAN C23 PCIE_TXN7_W LAN B23 PCIE_TXP7_W LAN K24 PCIE_RXN8_W IGIG L24 PCIE_RXP8_W IGIG C24 PCIE_TXN8_W IGIG B24 PCIE_TXP8_W IGIG DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9 USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14 DMI USB 2.0 PCIE_RCOMPN PCIE_RCOMPP PCIE1_RXN/USB3_7_RXN PCIE1_RXP/USB3_7_RXP PCIE1_TXN/USB3_7_TXN PCIE1_TXP/USB3_7_TXP PCIE2_TXN/USB3_8_TXN PCIE2_TXP/USB3_8_TXP PCIE2_RXN/USB3_8_RXN PCIE2_RXP/USB3_8_RXP PCIE3_RXN/USB3_9_RXN PCIE3_RXP/USB3_9_RXP PCIE3_TXN/USB3_9_TXN PCIE3_TXP/USB3_9_TXP PCIE4_RXN/USB3_10_RXN PCIE4_RXP/USB3_10_RXP PCIE4_TXN/USB3_10_TXN PCIE4_TXP/USB3_10_TXP PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP PCIE7_RXN PCIE7_RXP PCIE7_TXN PCIE7_TXP PCIE8_RXN PCIE8_RXP PCIE8_TXN PCIE8_TXP PCIe/USB 3 [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] [42] L27 N27 C27 B27 E24 G24 B28 A28 G27 E26 B29 C29 L29 K29 B30 A30 GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3# GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7 USB2_COMP USB2_VBUSSENSE RSVD_AB13 USB2_ID GPD7/RSVD AF5 AG7 AD5 AD7 AG8 AG10 AE1 AE2 AC2 AC3 AF2 AF3 AB3 AB2 AL8 AL7 AA1 AA2 AJ8 AJ7 W2 W3 AD3 AD2 V2 V1 AJ11 AJ13 AD43 AD42 AD39 AC44 Y43 Y41 W44 W43 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB_PN7 USB_PP7 USB_PN8 USB_PP8 USB_PN9 USB_PP9 [48] [48] [45] [45] [38] [38] [48] [48] [48] [48] [48] [48] [48] [48] [38] [38] [47] [47] USB3 PORT1 to USB board TYPE C (W/O TBT) 3G USB3 PORT4 to LAN board USB3 PORT5 to USB board USB3 PORT6 to LAN board FINGER NGFF WIGIG/WLAN +BT CCD B USB_OC0# USB_OC1# USB_OC2# VISACH2_D3 USB_OC4# USB_OC5# USB_OC6# USB_OC7# DESIGN NOTE: USB2 COMP RES: PLACE WITHIN 1 INCH AG3 USB2_COMP AD10 USB2_VBUSSENSE AB13 AG2 USB2_ID R148 R175 113_1%_04 1K_04 R161 1K_04 BD14 A A HM175 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [5,31,32,33,34,50] 3.3VA [31,32,33] VCC_RTC [3,8,9,10,11,12,13,26,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [5,26,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 Size A3 Date: 5 4 3 2 [30] PCH 1/5-SPI/DMI/PCIE/USB2 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 30 of 77 1 PCH 1/5 B - 31 B.Schematic Diagrams SPI_W P# SPI_HOLD# SPI_SI_R SPI_SO_R SPI_SCLK_R SPI_CS_0# SPI_SI_R SPI_SO_R SPI_SCLK_R SPI_CS_0# BD17 *0_04 AG15 AG14 AF17 AE17 For ITE IT8587B Test [35] [35] [35] [35] R528 SPT-H_PCH Schematic Diagrams PCH 2/5 5 BIOS RECOVERY ENABLE :LOW 4 3 PCH_RSVD 3.3VS BIOS SET GPIO pin NV power on/off timing 3.3VS R224 [38] [38] [38] R234 10K_04 CL_CLK1 AV2 CL_DATA1 AV3 CL_RST#1 AW2 CL_CLK1 CL_DATA1 CL_RST#1 R44 R43 U39 N42 10K_04 BIOS_REC PCH_RSVD [35] [46] MFG_MODE D52 C SCI# PS8338B_SW [35] SW I# C A RB751S-40H D53 3.3VS 3.3VS SSD_1 R563 B33 C33 K31 L31 [37] PCIE_TXP11_SSD [37] PCIE_TXN11_SSD [37] PCIE_RXP11_SSD [37] PCIE_RXN11_SSD R562 BIOS_REC PCH_RSVD GP39_GFX_CRB_DETECT MFG_MODE *10K_04 *10K_04 Sheet 31 of 77 PCH 2/5 MFG_MODE GP39_GFX_CRB_DETECT R575 10K_04 [49] [49] [49] [49] main HDD AB33 AB35 AA44 AA45 SATA1B_TXN_R SATA1B_TXP_R SATA1B_RXN_R SATA1B_RXP_R SATA1B_TXN_R SATA1B_TXP_R SATA1B_RXN_R SATA1B_RXP_R B38 C38 D39 E37 C36 B36 G35 E35 R207 *100K_04 TBT_CLKREQ# 3/17 㓡ᶵᶲẞ C (妋TBT䔞㨇⓷柴) [37] [37] [37] [37] SSD_1 PCI-E CLK Usage 5 6 8 9 14 A35 B35 H33 G33 PCIE_TXP12_SSD PCIE_TXN12_SSD PCIE_RXP12_SSD PCIE_RXN12_SSD J45 K44 N38 N39 H44 H43 L39 L37 GLAN WLAN PEG(NV) SSD (X 4 LANE) SSD (X 2 LANE) PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN PCIE9_TXP/SATA0A_TXP CLINK GPP_G8/FAN_PWM_0 GPP_G9/FAN_PWM_1 GPP_G10/FAN_PWM_2 GPP_G11/FAN_PWM_3 PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP FAN GPP_G0/FAN_TACH_0 GPP_G1/FAN_TACH_1 GPP_G2/FAN_TACH_2 GPP_G3/FAN_TACH_3 GPP_G4/FAN_TACH_4 GPP_G5/FAN_TACH_5 GPP_G6/FAN_TACH_6 GPP_G7/FAN_TACH_7 PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP PCIE11_TXP PCIE11_TXN PCIE11_RXP PCIE11_RXN PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP GPP_F10/SCLOCK GPP_F11/SLOAD GPP_F13/SDATAOUT0 GPP_F12/SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP PCIE14_TXN/SATA1B_TXN PCIE14_TXP/SATA1B_TXP PCIE14_RXN/SATA1B_RXN PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED# GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7 PCIE13_TXN/SATA0B_TXN PCIE13_TXP/SATA0B_TXP PCIE13_RXN/SATA0B_RXN PCIE13_RXP/SATA0B_RXP PCIE12_TXP PCIE12_TXN PCIE12_RXP PCIE12_RXN GPP_F21/EDP_BKLTCTL GPP_F20/EDP_BKLTEN GPP_F19/EDP_VDDEN PCIE20_TXP/SATA7_TXP PCIE20_TXN/SATA7_TXN PCIE20_RXP/SATA7_RXP PCIE20_RXN/SATA7_RXN PCIE19_TXP/SATA6_TXP PCIE19_TXN/SATA6_TXN PCIE19_RXP/SATA6_RXP PCIE19_RXN/SATA6_RXN HOST THERMTRIP# PECI PM_SYNC PLTRST_PROC# PM_DOWN 24 MHz 32.768 KHz F41 E41 B39 A39 X4 C791 2 1 B 3.3VS 3 4 *10M_04 *1TJS125DJ4A420P_32.768KHz CM200S RTC_X2 [42] C310 C311 C390 12p_50V_NPO_04 6-22-24R00-1BA 6-22-24R00-1B9 C330 XTAL_IN XTAL_OUT GND GND GND PAD 4 7 13 17 W 76-147_24MHZ fsx3m X1 1 16 4 1 A C329 VDDIO_25M VDDIO_24M VOUT VDDIO_27M 2.7K_1%_04 XCLK_RBIAS R513 0_04 PCH_SATAHDD_LED# AG36 AG35 AG39 AD35 AD31 AD38 AC43 AB44 SATAGP0 SATAGP1 SATAGP2 SATAGP3 SATAGP4 25M 24M 32.768K 27M V3.3A VDD VRTC 6 5 9 12 *10p_50V_NPO_04 *10p_50V_NPO_04 *10p_50V_NPO_04 R135 R136 R153 R155 R204 TBT_CLKREQ#_N VDD3 A5 A6 E1 BC9 BD10 TBT_CLKREQ# BC24 AW24 AT24 BD25 BB24 BE25 AT33 AR31 BD32 BC32 BB31 BC33 BA33 AW33 BB33 BD33 C381 W IGIG_CLKREQ# LAN_CLKREQ# W LAN_CLKREQ# SD40_CLKREQ# PEG_CLKREQ# SSD_CLKREQ# SSD2_CLKREQ# W IGIG_CLKREQ# LAN_CLKREQ# W LAN_CLKREQ# SD40_CLKREQ# PEG_CLKREQ# SSD_CLKREQ# SSD2_CLKREQ# GCLK_25M_GLAN [48] GCLK_24M_PCH [31] GCLK_32K [31] GCLK_27M_NV [24] VDD3 330_04 R183 *1.5K_1%_04 R179 *45.3K_1%_04 R13 R11 D6 *33_04 0_04 0_04 22_04 15 2 10 VRTC R154 0_04 20mils 20mils 2 *1K_04 RTC_VBAT_1 20mils W7 Y5 A 䘮暨ᶲẞ 1 2 3 P1 R2 C423 *BAT54CW H RTC_VBAT U2 *1u_6.3V_X5R_04 U3 P/N = 6-20-43130-102 PCB Footprint = 85204-02R 15p_50V_NPO_04 B - 32 PCH 2/5 SATAGP0 EDP_BRIGHTNESS BLON [10] NB_ENAVDD [10] PCH_THERMTRIP#_R R488 PCH_PECI H_PM_SYNC_R R497 [37] [10] 3 SATAGP1 SATAGP3 SATAGP4 43K_04 43K_04 43K_04 R580 R560 10K_04 10K_04 SW I# R557 10K_04 [48] R478 *1K_04 R485 *1K_04 PCH_THERMTRIP# 30.1_1%_04 H_PM_SYNC CLKOUT_CPUBCLK_P CLKOUT_CPUBCLK CLKOUT_ITPXDP CLKOUT_ITPXDP_P CLKOUT_CPUPCIBCLK CLKOUT_CPUPCIBCLK_P CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 XTAL24_OUT XTAL24_IN CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 XCLK_BIASREF RTCX1 RTCX2 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B5/SRCCLKREQ0# GPP_B6/SRCCLKREQ1# GPP_B7/SRCCLKREQ2# GPP_B8/SRCCLKREQ3# GPP_B9/SRCCLKREQ4# GPP_B10/SRCCLKREQ5# GPP_H0/SRCCLKREQ6# GPP_H1/SRCCLKREQ7# GPP_H2/SRCCLKREQ8# GPP_H3/SRCCLKREQ9# GPP_H4/SRCCLKREQ10# GPP_H5/SRCCLKREQ11# GPP_H6/SRCCLKREQ12# GPP_H7/SRCCLKREQ13# GPP_H8/SRCCLKREQ14# GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 CLKOUT_PCIE_N6 CLKOUT_PCIE_P6 CLKOUT_PCIE_N7 CLKOUT_PCIE_P7 CLKOUT_PCIE_N8 CLKOUT_PCIE_P8 CLKOUT_PCIE_N15 CLKOUT_PCIE_P15 CLKOUT_PCIE_N14 CLKOUT_PCIE_P14 CLKOUT_PCIE_N13 CLKOUT_PCIE_P13 CLKOUT_PCIE_N12 CLKOUT_PCIE_P12 2 [9] CLKOUT_PCIE_N9 CLKOUT_PCIE_P9 CLKOUT_PCIE_N10 CLKOUT_PCIE_P10 CLKOUT_PCIE_N11 CLKOUT_PCIE_P11 1K_04 1.0V_VCCST PCH_THERMTRIP# PCH_PECI [5] GPP_A16/CLKOUT_48 CLKOUT_CPUNSSC_P CLKOUT_CPUNSSC [8] DIMM0_CHB_EVENT# [5] [5] 暞ẞ㔠:8 pcs SPT-H_PCH C DIMM0_CHA_EVENT# R484 604_1%_04 R487 *10K_04 PCH_XDP_CLK_DN PCH_XDP_CLK_DP L1 L2 J1 J2 PCH_CPU_PCIBCLK_R_DN PCH_CPU_PCIBCLK_R_DP N7 N8 TBT_REFCLK_100_N TBT_REFCLK_100_P [5] [5] [42] [42] L7 L5 D3 F2 B E5 G4 D5 E6 CLK_PCIE_W IGIG# CLK_PCIE_W IGIG D8 D7 [38] [38] CLK_PCIE_GLAN# [48] CLK_PCIE_GLAN [48] R8 R7 CLK_PCIE_W LAN# [38] CLK_PCIE_W LAN [38] U5 U7 CLK_PCIE_SD40# [48] CLK_PCIE_SD40 [48] W10 W11 N3 N2 VGA_PEXCLK# [14] VGA_PEXCLK [14] CLK_PCIE_SSD# [37] CLK_PCIE_SSD [37] P3 P2 CLK_PCIE_SSD2# [37] CLK_PCIE_SSD2 [37] R3 R4 A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 4 R228 R220 R832 PCH_SATAHDD_LED# SCI# SATAGP 0,2 L: SATA H: PCIe [37] PLTRST_CPU_N [5] H_PM_DOW N [5] XTAL 24MHz 20ppm CL<=12pF 5 PCH_SATAHDD_LED# SATAGP2 HM175 [30,32,33] VCC_RTC [33,51,56] VDD1.0 [5,26,30,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [5,30,32,33,34,50] 3.3VA [3,8,9,10,11,12,13,26,30,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [10,11,12,13,36,39,40,41,47,48,49,50,61,62,63,64] 5VS [5,6,32,56,57] 1.0V_VCCST [39,44,45,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V [3,23,24,26,27,28,52,53,61,62,64] 1V8_AON 6-86-2B002-005 50271-0020N-001 SLG3NB3470VTR PCB Footprint = TQFN16-2X3MM 6-02-33454-EQ0 VCC_RTC A C R182 J_CBAT1 RTC_VBAT 22u_6.3V_X5R_06 1 SSD_2 [37] [37] [37] [37] PLACE CLOSE TO PCH W36 W35 W42 RTC_X1 RTC_X2 SKL䘬VCCRTC天㯪⮷㕤3.2Vẍᶳ (Skarkbay⎗3.3V) ẍPDG⺢嬘㍉䓐ẍᶳ暣嶗(1.5K,45.3K)℞ῤ⎗婧㔜 U7 8 3 14 11 0_04 R499 [38] [48] [38] [48] [14] [37] [37] RESERVED FOR EMI 0_04 R483 VDD1.0 GCLK_32K 10K_04 TBT_CLKREQ#_N W IGIG_CLKREQ# 10K_04 SD40_CLKREQ# 10K_04 R305 R194 R218 0.1u_10V_X7R_04 0.1u_10V_X7R_04 2.2u_6.3V_X5R_04 0.1u_10V_X7R_04 R166 GCLK_24M_PCH LAN_CLKREQ# PEG_CLKREQ# SSD2_CLKREQ# SSD_CLKREQ# CLOCK GENERATOR VDD3 VDD1.0 VCC_RTC 1V8_AON PCH_CPU_BCLK_R_DP PCH_CPU_BCLK_R_DN 3.3VS 3.3VA AD44 AJ3 AL3 AJ4 AK2 AH2 D SSD_2 K37 G37 G45 G44 G2 H2 XTAL24_OUT XTAL24_IN [31] XTAL24_IN RN1 10K_8P4R_04 1 8 2 7 3 6 4 5 PCIE_RXN16_SSD2 PCIE_RXP16_SSD2 PCIE_TXN16_SSD2 PCIE_TXP16_SSD2 H42 H40 E45 F45 *12p_50V_NPO_04 R506 32.768Khz暨SOC or PCH ⎴ᶨ朊ᶵ⎗ㇻVIA , XTALᶳ㕡ᶵ⎗㚱POWER or ᾉ嘇 2015/10/08 C348 C318 C379 C377 [31] 2 3 RTC_X1 24MHZ 6-22-24R00-1B9 *1M_04 6-22-24R00-1BA SSD_1 PCIE_RXN15_SATA2_RXN_SSD2 [37] PCIE_RXP15_SATA2_RXP_SSD2 [37] PCIE_TXN15_SATA2_TXN_SSD2 [37] PCIE_TXP15_SATA2_TXP_SSD2 [37] D43 E42 A41 A40 G1 F1 CPU_24MHZ_R_DP CPU_24MHZ_R_DN R502 C798 *15p_50V_NPO_04 C799 *15p_50V_NPO_04 [5] [5] 1 4 RTC (10 MOHM RES): DO NOT CHANGE TO 0402 X5 [5] [5] SSD_1 PCIE_RXN10_SSD [37] PCIE_RXP10_SSD [37] PCIE_TXN10_SSD [37] PCIE_TXP10_SSD [37] U30G *W 76-147_24MHZ XTAL24_OUT fsx3m C792 *12p_50V_NPO_04 PCIE_RXN9_SATA0A_RXN_SSD [37] PCIE_RXP9_SATA0A_RXP_SSD [37] PCIE_TXN9_SATA0A_TXN_SSD [37] PCIE_TXP9_SATA0A_TXP_SSD [37] G29 E29 C32 B32 AR17 32.768KHZ 6-22-32R76-0B2 6-22-32R76-0BJ 1 G31 H31 C31 B31 HM175 3 2 B.Schematic Diagrams A RB751S-40H CL_CLK CL_DATA CL_RST# PCIe/SATA U43 U42 U41 M44 U36 P44 T45 T44 D GFX SELECT TABLE NORMAL GFX:LOW CUSTOMER GFX:HIGH 2 SPT-H_PCH U30C [31] PCH 2/5-PCIE/SATA/HOST/CLK Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 31 of 77 Schematic Diagrams PCH 3/5 5 4 3 ESPI/LPC SELECT STARP LPC : LOW (DEFAULT) eSPI: HIGH (INTERNAL WEAK PD) 3.3VA BA9 BD8 BE7 BC8 [39] HDA_BITCLK [39] HDA_RST# [39] HDA_SDIN0 R232 VCC_RTC GPP_C5 HDA_SDOUT [32,39] HDA_SDOUT [39] HDA_SYNC *4.7K_04 BB7 BD9 BD1 BE2 D CLOSE TO PCH [3] TOP SWAP OVERRIDE STRAP SWAP ENABLE: HIGH SWAP DISABLE(DEFAULT): LOW (INTERNAL WEAK PD) R180 20K_1%_04 [3] [3] R164 20K_1%_04 R486 AUD_AZACPU_SDO_R AUD_AZACPU_SDI AUD_AZACPU_SCLK R494 30.1_1%_04 AUD_AZACPU_SDO AM1 AN2 30.1_1%_04 AUD_AZACPU_SCLK_R AM2 1 R534 C391 150K_1%_04 1u_6.3V_X6S_04 JOPEN1 *OPEN_10mil-1MM HDA_BCLK HDA_RST# HDA_SDI0 HDA_SDI1 RTC_RST# SRTC_RST# EXI BOOT STALL BYPASS ENABLE:HIGH (INTERNAL WEAK PD) [34] C400 1u_6.3V_X6S_04 3.3VA PM_PCH_PW ROK [35] RSMRST# RSMRST# R181 BC10 BB10 AW11 BA11 RSMRST# HDA_SDO HDA_SYNC *4.7K_04 PCH_HOT_GNSS_DISABLE 3.3VS [35] SMC_CPU_THERM AV13 GPD9/SLP_WLAN# BC14 BD23 AL27 AR27 N44 AN24 AY1 DRAM_RESET# GPP_B2/VRALERT# GPP_B1 GPP_B0 GPP_G17/ADR_COMPLETE GPP_B11 SYS_PWROK RSVD_BD1 RSVD_BE2 AUDIO DISPA_SDO DISPA_SDI DISPA_BCLK BC13 BC15 AV15 BC26 AW15 BD15 BA13 WAKE# GPD6/SLP_A# SLP_LAN# GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5# GPP_D8/I2S0_SCLK GPP_D7/I2S0_RXD GPP_D6/I2S0_TXD GPP_D5/I2S0_SFRM GPP_D20/DMIC_DATA0 GPP_D19/DMIC_CLK0 GPP_D18/DMIC_DATA1 GPP_D17/DMIC_CLK1 AN15 BD13 BB19 BD19 GPD8/SUSCLK GPD0/BATLOW# GPP_A15/SUSACK# GPP_A13/SUSWARN#/SUSPWRDNACK RTCRST# SRTCRST# PCH_PWROK RSMRST# DSW_PWROK GPP_C2/SMBALERT# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C5/SML0ALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPD2/LAN_WAKE# GPD1/ACPRESENT SLP_SUS# GPD3/PWRBTN# SYS_RESET# GPP_B14/SPKR PROCPWRGD ITP_PMODE JTAGX JTAG_TMS JTAG_TDO JTAG_TDI JTAG_TCK JTAG ISH_GP_6_R AR15 GPD11/LANPHYPC SMBUS PCH_DPW ROK AV11 *0402_short SKIN_THRM_SNSR_ALERT_N BB41 SMB_CLK AW44 SMB_DATA BB43 GPP_C5 BA40 SML0_CLK AY44 SML0_DATA BB39 PCH_HOT_GNSS_DISABLE AT27 SMC_CPU_THERM_R AW42 R577 *0_04 SMD_CPU_THERM AW45 [39,47,55] SMB_CLK [39,47,55] SMB_DATA R210 BB17 AW22 GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# GPP_A8/CLKRUN# 2 PCH_SPKR 1 忂䞍BIOS姕⭂PIN 1.35V DESIGN NOTE: '0' '1' 1.2V DDR4_DRAMRST# DDR_VOL_SEL D [55] 㓡冯P870DMᶨ㧋䓐GPP_B0 SYS_PW ROK [34] LAN_W AKEUP# SLP_A# PM_SLP_LAN# SUSB# SUSC# SUS_CLK PM_BATLOW # SUS_PW R_ACK# R199 SUSW ARN# R524 SUS_CLK BD11 BB15 BB13 AT13 AW1 BD26 AM3 LAN_W AKE# AT2 AR3 AR2 AP1 AP2 AN3 ITP_PMODE PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_TDO R498 PCH_JTAG_TDI PCH_JTAG_TCK R489 SLP_SUS#_R R187 [30,35,38,42,48] [10,34,35,41,42,50,56] [35,51,55,56] [38] *0_04 SUS_PW R_ACK#_EC 0_04 AC_PRESENT *0_04 PW R_BTN# SYS_RESET# PCH_SPKR H_PW RGD [35] EC_SLP_SUS# C 1.0V_VCCST 51_04 51_04 1K_04 4 SPT-H_PCH Q41B 3 SMB_CLK 2 D S SMB_CLK_R G MTDK3S6R 1 Q41A 6 SMB_DATA AW4 AY2 AV4 BA4 [12,26] MDP_F_HPD [13,26] HDMI_HPD [11,26,46] MDP_E_HPD D SMB_DATA_R S [3,8,9,44] U30E FROM DP G MTDK3S6R [3,8,9,44] SMC_CPU_THERM_R SMD_CPU_THERM SMB_CLK SMB_DATA FROM DP REDRIVER 5 1K_04 R589 GPP_I7/DDPC_CTRLCLK GPP_I8/DDPC_CTRLDATA GPP_I5/DDPB_CTRLCLK GPP_I6/DDPB_CTRLDATA GPP_I9/DDPD_CTRLCLK GPP_I10/DDPD_CTRLDATA GPP_I0/DDPB_HPD0 GPP_I1/DDPC_HPD1 GPP_I2/DDPD_HPD2 GPP_I3/DDPE_HPD3 VDDQ DRAM_RST# R521 470_04 [3] BD7 SB_IEDP_HPD GPP_F14 GPP_F23 GPP_F22 GPP_I4/EDP_HPD GPP_G23 GPP_G22 GPP_G21 GPP_G20 GPP_H23 R169 *100K_04 DDR4_DRAMRST# DDR4_DRAMRST# [8,9] B C820 *0.1u_10V_X7R_04 HM175 R230 *4.7K_04 SKIN_THRM_SNSR_ALERT_N 4G LTE Flash Descriptor Security Overide Low = Disabled-(Default) High = Enabled 1K_04 ME_W E USB3 PORT6 to LAN board [35] D24 A C HDA_SDOUT [32,39] USB3 PORT5 to USB board RB751S-40H TYPE C (W/O TBT) A [38] [38] [38] [38] USB3_TXN2 USB3_TXP2 USB3_RXN2 USB3_RXP2 [48] [48] [48] [48] USB3_TXN6 USB3_TXP6 USB3_RXN6 USB3_RXP6 [48] [48] [48] [48] USB3_TXN5 USB3_TXP5 USB3_RXN5 USB3_RXP5 [45] [45] [45] [45] USB3_TXP3 USB3_TXN3 USB3_RXP3 USB3_RXN3 [48] [48] [48] [48] USB3_TXP4 USB3_TXN4 USB3_RXP4 USB3_RXN4 C11 B11 B7 A7 B12 A12 C8 B8 B15 C15 K15 K13 B14 C14 G13 H13 D13 C13 A9 B10 B13 A14 G11 E11 USB3_1_TXN USB3_1_TXP USB3_1_RXN USB3_1_RXP USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_6_TXN USB3_6_TXP USB3_6_RXN USB3_6_RXP GPP_A5/LFRAME#/ESPI_CS0# GPP_A6/SERIRQ/ESPI_CS1# GPP_A7/PIRQA#/ESPI_ALERT0# GPP_A0/RCIN#/ESPI_ALERT1# GPP_A14/SUS_STAT#/ESPI_RESET# GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 USB3_5_TXN USB3_5_TXP USB3_5_RXN USB3_5_RXP GPP_G19/SMI# GPP_G18/NMI# USB3_3_TXP/SSIC_2_TXP USB3_3_TXN/SSIC_2_TXN USB3_3_RXP/SSIC_2_RXP USB3_3_RXN/SSIC_2_RXN USB3_4_TXP USB3_4_TXN USB3_4_RXP USB3_4_RXN DGPU_PRSNT# DGPU_PW RGD_R R570 DGPU_SELECT# R236 SML0_DATA R554 499_1%_04 SUSW ARN# R523 1K_04 499_1%_04 VDD3 DGPU_PW R_EN L43 L44 U35 R35 BD36 SML0_CLK [5] DGPU_RST#_PCH 3.3VA [27] [27,35] LAN_W AKEUP# R197 check EC *0_04 DGPU_PW RGD GC6_FB_EN_PCH [10,27,35] GPU_EVENT# [26] 1K_04 AC_PRESENT R519 [64] 10K_04 PM_BATLOW # R162 8.2K_04 3.3VS B DGPU_SELECT# R553 *10K_04 DGPU_PRSNT# *10K_04 R561 3.3VS GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3 SATA USB3 PORT4 to LAN board USB3_TXN1 USB3_TXP1 USB3_RXN1 USB3_RXP1 USB R500 [48] [48] [48] [48] LPC/eSPI 3.3VA USB3 PORT1 to USB board H_SKTOCC_N RN3 1K_8P4R_04 1 8 2 7 3 6 4 5 SPT-H_PCH U30F TLS CONFIDENTITALITY ENABLE: HIGH (INTERNAL WEAK PD) BB3 BD6 BA5 BC4 BE5 BE6 Y44 V44 W39 [35,50,56] [35] [39] [5] HM175 R565 Sheet 32 of 77 PCH 3/5 [35] SUS_PW R_ACK# AT22 AV22 AT19 BD16 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 BE16 BA17 AW17 AT17 BC18 SERIRQ LPC_PIRQA# SB_KBCRST# BC17 AV19 CLK_PCI_KBC_R CLK_PCI_TPM_R [35,47] [35,47] [35,47] [35,47] SYS_RESET# R493 LPC_FRAME# [35,47] SERIRQ [35,47] SB_KBCRST# R518 R196 R177 10K_04 SUS_CLK R189 *1.5K_04 3.3VS 22_04 22_04 PCH_MUTE# RSMRST# KW>>sZ E> /^> t, E^DW> >Kt [35] M45 N43 AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41 10K_04 [41] PCLK_KBC PCLK_TPM [35] [47] 24 Mhz SERIRQ R193 SB_KBCRST# R192 10K_04 10K_04 [5,26,30,31,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [3,8,9,10,11,12,13,26,30,31,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [5,30,31,33,34,50] 3.3VA [5,6,31,56,57] 1.0V_VCCST [30,31,33] VCC_RTC [6,8,9,51,55] VDDQ [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V PS8331_SW [3,10,26,48] [3,23,24,26,27,28,31,52,53,61,62,64] 1V8_AON [14,15,23,24,28,52] 1V8_RUN :PORT1 (INTEL) (DEFAULT) [10,11,12,13,36,39,40,41,47,48,49,50,61,62,63,64] 5VS A L H: PORT2 (NV) ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ HM175 Title R805 1K_04 KBLED_DET [36] [32] PCH 3/5-HDA/SMBUS/RTC//ESP Size Document Number 6-71-PA700-D02A A3 SCHEMATIC1 Date: 5 4 3 2 W ednesday, July 05, 2017 Sheet 32 Rev D02A of 77 1 PCH 3/5 B - 33 B.Schematic Diagrams AL42 AN42 AM43 AJ33 AH44 AJ35 AJ38 AJ42 3.3VS C 2 SPT-H_PCH U30D Schematic Diagrams PCH 4/5 5 4 SPT-H_PCH U30I 3 2 1 U30L VDD1.0 SPT-H_PCH B.Schematic Diagrams C42 D10 D12 D15 D16 D17 D19 D21 D24 D25 D27 D29 D30 D31 D33 D35 D36 E13 E15 E31 E33 F44 F8 G42 G9 H17 H19 H22 H24 H27 H29 H3 H35 J10 J11 J3 J39 J5 T42 U10 U11 U14 U17 U18 U28 U29 U31 U32 U33 U38 U4 U8 V18 V20 V21 V23 V25 V29 V3 V45 W14 W31 W32 W33 W38 W4 W8 Y17 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB11 AB7 AB14 AB31 AB32 AB38 AB4 AB5 AC1 AC20 AC21 AC25 AC29 AC45 AB8 AD11 AD14 AB15 AD32 AD33 AD36 AD4 AD8 AE18 AE20 AE21 AE25 AE28 AL10 AL11 AL13 AL17 AL19 AL24 AL29 AL32 AL33 AL38 AM15 AM17 AM19 AM22 AM24 AM27 AM29 AM45 AN11 AN22 AN27 AN31 AN39 AN7 AN8 AP11 AP4 AR33 AR34 AR42 AR9 AT10 AT15 AT36 AT9 AU1 AU35 AU36 AU39 AU45 C4 VDD3 VDD1.0 U30H AA23 AA26 AA28 AC23 CLOSE TO PCH AC26 (3-5 mm) AC28 R201 *0_04 AE23 C427 AE26 Y23 1u_6.3V_X5R_04 Y25 +VCCDSW _1P0 0.0454A BA29 2.899A 0.021A 0.05A 0.024A 0.137A VDD1.0 L4 . HCB1608KF-121T30 CLOSE TO PCH +VCCF24_1P0_L 0.006A C373 *22u_6.3V_X5R_06 CLOSE TO PCH (3-5 mm) VDD1.0 C382 . HCB1608KF-121T30 C856 3.53A +VCCMPHY_1P0 +VCCAMPHYPLL_1P0 0.11A C426 22u_6.3V_X5R_06 L20 C384 1u_6.3V_X5R_04 1u_6.3V_X5R_04 CLOSE TO PCH (3-5 mm) C855 N17 R19 U20 V17 R17 K2 K3 U21 U23 U25 U26 V26 A43 B43 C44 C45 0.030A V28 0.533A AC17 0.012A AJ5 AL5 C854 0.033A AN19 *22u_6.3V_X5R_06 *22u_6.3V_X5R_06 1u_6.3V_X5R_04 0.075A BA15 3.3VA CLOSE TO PCH (3-5 mm) VDD3 VDD1.0 C416 C421 1u_6.3V_X5R_04 C415 +VCCAAZPLL_1P0 VDD1.0 W15 L3 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 DCPDSW_1P0 eSPI:1.8V LPC:3.3V SPT-H_PCH 3.3VA VCCPRIM_1P0 VCCDSW_3P3 VCCCLK1 VCCCLK3 VCCCLK4 VCCCLK2 VCCCLK2 VCCPGPPA VCCPGPPBCH VCCPGPPBCH VCCPGPPEF VCCPGPPEF VCCPGPPG VCCPRIM_3P3 VCCPRIM_1P0 VCCATS VCCRTCPRIM_3P3 VCCRTC DCPRTC VCCCLK5 VCCCLK5 㺷暣 AL22 0.0908A 3.3VA C863 3.3VA BA24 0.403A 0.1u_10V_X7R_04 BA31 0.082A BC42 BD40 AJ41 AL41 AD41 AN5 0.229A AD15 AD13 BA20 BA22 BA26 0.0061A 0.007A 0.0002A 0.0002A VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHYPLL_1P0 VCCMPHYPLL_1P0 VCCPCIE3PLL_1P0 VCCPCIE3PLL_1P0 VCCAPLLEBB_1P0 VCCPRIM_1P0 VCCUSB2PLL_1P0 VCCUSB2PLL_1P0 VCCHDAPLL_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCSPI VCCSPI VCCSPI VCCPGPPD VCCPGPPD VCCPGPPD VCCPGPPD VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3 VCCHDA VCCDSW_3P3 C793 3.3VA CLOSE TO PCH (1-3 mm) 0.1u_10V_X7R_04 0.1u_10V_X7R_04 CLOSE TO PCH (1-3 mm) 0.065A 0.2875A 3.3VA VDD1.0 3.3VS C412 1u_6.3V_X5R_04 CLOSE TO PCH (3-5 mm) +VCC_RTCEXT_CAP AJ20 AJ21 AJ23 AJ25 0.029A BC44 BA45 BC45 BB45 0.078A BD3 BE3 BE4 0.0811A C858 0.1u_10V_X7R_04 CLOSE TO PCH (1-3 mm) 3.3VA C786 1u_6.3V_X5R_04 CLOSE TO PCH (3-5 mm) VDD1.0 BE41 BE43 BE42 D C795 CLOSE TO PCH (1-3 mm) 0.114A C424 USB B AR5 AR7 U15 AL4 AE29 AE4 AE42 AF18 AF20 AF21 AF23 AF25 AF26 AF28 AF29 AG11 AG13 AG31 AG32 AG33 AG38 AG4 AH1 AH17 AH18 AH20 AH21 AH23 AH25 AH26 AH28 AH29 AH45 AJ10 AJ14 AJ15 AJ17 AJ18 AJ26 AJ28 AJ29 AJ31 AJ32 AJ36 AK4 AK42 AU7 AV17 AV24 AV27 AV31 AV33 AV6 AW13 AW19 AW29 AW37 AW9 AY38 AY45 B25 B3 B37 B40 B6 BA1 BB11 BB16 BB21 BB25 BB30 BB34 BC2 BD43 VCCGPIO C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MPHY Sheet 33 of 77 PCH 4/5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CORE D AC18 AN4 AN10 BE14 BE18 BE23 BE28 BE32 BE37 BE40 BE9 C10 C2 C28 C37 J7 K10 K27 K33 K36 K4 K42 K43 L12 L13 L15 L4 L41 L8 M35 M42 N10 N15 N19 N22 N24 N35 N36 N4 N41 N5 P17 P19 P22 P45 R10 R14 R22 R29 R33 R38 R5 T1 T2 T4 Y18 Y20 Y21 Y26 Y28 Y29 A18 A25 A32 A37 AA17 AA18 AA20 AA21 AA25 AA29 AA4 AA42 AB10 VDD3 C862 1u_6.3V_X5R_04 0.1u_10V_X7R_04 CLOSE TO PCH (1-3 mm) C383 +V3.3A_V1.8A_VCCPGPPD VCC_RTC C422 1u_6.3V_X5R_04 0.1u_10V_X7R_04 2 PJ41 1 3.3VA *1mm DEFAULE ᶲ C 3.3VA HM175 1u_6.3V_X5R_04 CLOSE TO PCH (3-5 mm) 0.1u_10V_X7R_04 . HCB1608KF-121T30 CLOSE TO PCH (3-5 mm) C388 cost down_1216 0.1u_10V_X7R_04 B HM175 HM175 A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ [31,51,56] VDD1.0 [5,26,30,31,32,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [3,8,9,10,11,12,13,26,30,31,32,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [30,31,32] VCC_RTC [5,30,31,32,34,50] 3.3VA Title Size A3 Date: 5 B - 34 PCH 4/5 4 3 2 [33] PCH 4/5-POWER/VSS Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 33 of 77 Schematic Diagrams PCH 5/5 5 NO REBOOT STARP ENABLE: HIGH (INTERNAL WEAK PD) 4 3 2 1 SPT-H_PCH U30J 3.3VS BD2 BD45 BD44 BE44 D45 A42 B45 B44 A4 A3 B2 A2 B1 BB1 BC1 A44 R540 *4.7K_04 LPSS_GSPI0_MOSI D BOOT STARP ENABLE:LPC IS SELECT (INTERNAL WEAK PD) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C1 D1 3.3VA RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PREQ# PRDY# CPU_TRST# PCH_TRIGOUT PCH_TRIGIN RSVD RSVD AR22 W13 U13 RSVD22 P31 N31 P27 R27 N29 P29 AN29 R24 P24 PA5x: 00 ID2 ID1 AT3 PCH_XDP_PREQ#_R AT4 PCH_XDP_PRDY#_R AY5 H_TRST#_R AL2 PCH_2_CPU_TRIGGER_R AK1 R491 R495 R185 R496 *0_04 *0_04 *0_04 30.1_1%_04 H_PREQ# [5] H_PRDY# [5] H_TRST# [5] PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER H R586 NC L R582 10K_04 [6] [6] *4.7K_04 LPSS_GSPI1_MOSI SPT-H_PCH U30K [35] LPSS_GSPI1_MOSI AT29 AR29 AV29 BC27 LPSS_GSPI0_MOSI BD28 BD27 AW27 AR24 SMI# SMI# 䓙GPP_G19䦣军 GPP_B20 , BIOS天㯪 GPP_B16 GPP_B15 C GPP_B22/GSPI1_MOSI GPP_B21/GSPI1_MISO GPP_B20/GSPI1_CLK GPP_B19/GSPI1_CS# GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_B16/GSPI0_CLK GPP_B15/GSPI0_CS# AV44 BA41 AU44 AV43 R566 R567 3.3VS UART2_CTS# UART2_RTS# *49.9K_1%_06 UART2_TXD *49.9K_1%_06 UART2_RXD AN43 AN44 AR39 AR45 PCH_SCL_ESS PCH_SDA_ESS AR41 AR44 AR38 AT42 KAI_12/1 GPP_D16/ISH_UART0_CTS# GPP_D15/ISH_UART0_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA H H GSYNC L H NVSR-GSYNC L L AJ43 AL43 AK44 AK45 TPM_DET BOARD_ID3 BOARD_ID4 EDP: H GSYNC: L L R582 NC GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA GPP_C23/UART2_CTS# GPP_C22/UART2_RTS# GPP_C21/UART2_TXD GPP_C20/UART2_RXD D02_0222_kai R581 100K_04 W /O GSYNC PA70Rx 暨ᶲẞ R586 10K_04 PA50Rx 暨ᶲẞ R582 10K_04 Sheet 34 of 77 PCH 5/5 R585 *10K_04 R583 10K_04 C R572 100K_04 GSYNC D02_0308_KAI BOARD_ID4 TBT: W/ TBT R571 STUFF R564 NOT STUFF W/O TBT R564 STUFF R571 NOT STUFF G sync⇌ ⇌㕟 GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7 GPP_C19/I2C1_SCL GPP_C18/I2C1_SDA GPP_C17/I2C0_SCL GPP_C16/I2C0_SDA GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL BOTZONE_DET PS8338B_PCH SATA_PW R_EN FROM PCH SB_BLON R571 TBT 2/1 NV recommend add GSYNC_ID BC22 BD18 BE21 BD22 BD21 BB22 BC19 3.3VS [24,26] BC38 BB38 BD38 BE39 R583 10K_04 3.3VS 3.3VS GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA D 3.3VS [47] STRAP5 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C12/UART1_RXD/ISH_UART1_RXD AM44 AJ44 3.3VS BOARD_ID1 BOARD_ID2 GSYNC_DET AL44 AL36 AL35 AJ39 GPP_C9/UART0_TXD GPP_C8/UART0_RXD GPP_C11/UART0_CTS# GPP_C10/UART0_RTS# AU41 AT44 AT43 AU43 KAI_12/02 GPP_D9 GPP_D10 GPP_D11 GPP_D12 EDP R583 10K_04 R585 NC [36] SMI# R576 10K_04 BOTZONE_DET R188 10K_04 10K_04 W /O TBT [46] SATA_PW R_EN FROM PCH SB_BLON [10] R564 SB_BLON R209 SATA_PW R_EN FROM PCH *10K_04 3.3VS R514 *10K_04 R574 10K_04 VDD3 [49] R584 BOARD_ID3 BOARD_ID4 3.3VS 10K_04 D02A_0522_KAI *10K_04 HM175 D02_0218 B 14 U11B 74LVC08APW 4 6 BUF_PLT_RST# 5 [35,37,38,42,47,48] VDD3 7 R546 14 *100K_04 wey_12/21 [57] VDD3 VCORE_PG VCORE_PG PM_PW ROK U11C 74LVC08APW 12 8 13 U11D 74LVC08APW 11 SYS_PW ROK_R 9 R202 1K_04 SYS_PW ROK [32] 10 7 ALL_SYS_PW RGD VDD3 EC DELAY ALL_SYS_PWRGD 200ms =PM_PWROK [35] 14 PLT_RST# 7 [27,30] B BUF_PLT_RST# VDD3 R172 14 *10K_04 [56,59] VCCIO_PW RGD SUSB# 3 ALL_SYS_PW RGD 2 ALL_SYS_PW RGD PM_PCH_PW ROK [5,10,35,57] [32] TO VR_ON & EC 7 [10,32,35,41,42,50,56] U11A 74LVC08APW 1 A ON R537 C428 *10K_04 *0.1u_10V_X7R_04 A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [5,30,31,32,33,50] [5,26,30,31,32,33,35,37,38,48,49,50,51,52,53,54,56,59,60] [3,8,9,10,11,12,13,26,30,31,32,33,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VA VDD3 3.3VS Size A3 Date: 5 4 3 2 [34] PCH 5/5-UART/I2C/GPIO Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 34 of 77 1 PCH 5/5 B - 35 B.Schematic Diagrams GSYNC_DET GSYNC_ID HM175 H R586 10K_04 BOARD_ID[2:1] PA50Rx:00 PA70Rx:10 BIOS setting R216 PA7x: 10 ID2 ID1 R585 NC Schematic Diagrams KBC IT8587 5 4 3 . C955 C1013 C1056 10u_6.3V_X5R_06 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C914 0.1u_10V_X7R_04 C999 VGA Chipset N17E-G1 RB (PL) R636 10K N17E-G2 10K N17E-G3 x 10K_04 RB R636 10K_04 MEDION 10K 10K RB (PL) R636 10K VGA Chipset N17E-G1 RA (PH) R637 X RA (PH) R637 56K KBC_AGND 0.1u_10V_X7R_04 . 100K_04 KBC_W RESET# 0.1u_10V_X7R_04 R662 C980 VDD3 [26,60] AC_IN# [48] LED_ACIN [32] AC_PRESENT R648 W/O USB CHARGE R652 USB CHARGE R648 VDD3 [41] *10K_04 KBC_MUTE# [49] R652 CPU_FAN [34] [31] SMI# SCI# BAT_DET MODEL_ID [32] R711 R712 SMC_BAT SMD_BAT R713 R714 SMC_CPU_THERM [5] H_PECI C1063 23 15 10K_04 [60] BAT_VOLT [2] THERM_VOLT [60] TOTAL_CUR [35,60] [35,60] 126 4 16 20 77 CPU_FAN *0.1u_10V_X7R_04 C975 14 79 GPB5/GA20 GPB6/KBRST# GPC7/PWUREQ#/BBO/SMCLK2ALT GPE7/L80LLAT/5VT GPD3/ECSCI#/5VT GPD4/ECSMI# DAC IT8587 GPJ3/DAC3/TACH1B ADC 66 67 69 70 73 110 111 *0_04 EC_PECI 43_1%_04 117 5VT/CTX1/SOUT1/DAT3/ID2/GPH2 B [50,54] 85 87 86 88 USB_CHARGE_EN [38] BT_EN [47] TP_CLK [47] TP_DATA 89 90 KB-SI0 KB-SI1 KB-SI2 KB-SI3 KB-SI4 KB-SI5 KB-SI6 KB-SI7 4 5 6 8 11 12 14 15 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 KB-SO0 KB-SO1 KB-SO2 KB-SO3 KB-SO4 KB-SO5 KB-SO6 KB-SO7 KB-SO8 KB-SO9 KB-SO10 KB-SO11 KB-SO12 KB-SO13 KB-SO14 KB-SO15 1 2 3 7 9 10 13 16 17 18 19 20 21 22 23 24 KB-SO10 KB-SO11 KB-SO12 KB-SO13 KB-SO14 KB-SO15 [26] [26,36,44] [26,36,44] CCD_EN 78 68 24 EC_SSD_LED# [48] 76 80 81 115 116 118 SMC_VGA_THERM SMD_VGA_THERM [10,27,32] GC6_FB_EN_PCH [48] *100K_04 28 29 30 LED_SCROLL# [48] LED_NUM# [48] LED_CAP# DD_ON 125 107 3G_EN GPF6/SMCLK2/PECI TACH0A/GPD6 GPA1/PWM1/5VT GPA5/PWM5/5VT GPA6/PWM6/SSCK/5VT GPA7/PWM7/RIG1#/5VT TMRI0/GPC4 TMRI1/GPC6 BKL_EN GPJ2/DAC2//TACH0B GPI2/ADC2 PW R_SW # LID_SW # 18 21 GPF0/PS2CLK0/TMB0/CEC/5VT GPF2/PS2CLK1/DTR0#/5VT 5VT/L80HLAT/BAO/GPE0 GPF1/PS2DAT0/TMB1/5VT GPF3/PS2DAT1/RTS0#/5VT 5VT/RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 19 112 PW R_BTN# 33 [36] [5] EC_CTRL_EN# H_PROCHOT_EC 5VT/ID3/GPH3 5VT/ID4/GPH4 5VT/ID5/GPH5 5VT/ID6/GPH6 GPC1/SMCLK1/5VT GPC2/SMDAT1/5VT GPF7/SMDAT2/PECIRQT# 5VT/EGAD/GPE1 5VT/EGCS#/GPE2 5VT/EGCLK/GPE3 GPA0/PWM0/5VT GPA2/PWM2/5VT GPA3/PWM3/5VT GPA4/PWM4/5VT TACH1/TMA1/GPD7 5VT/CRX0/GPC0 56 57 KB-SO16 KB-SO17 VDD3 [36] [36] CK32KE/GPJ7 CK32K/GPJ6 93 94 SUSB# [10,32,34,41,42,50,56] SUSC# [32,51,55,56] CHG_JAP 96 97 98 99 W LAN_EN [38] W IGIG_PW R_EN 82 83 R806 84 [38] OVERT# [26,27] 1K_04 KB-DET [36] DGPU_PW R_EN [27,32] 48 119 2 128 3G_PW R_EN [38] EC_SLP_SUS#_R 4/1 del 枸䔁pull hi暣旣 [38] EC_SLP_SUS# DEFAULT㓡 㓡ᶲẞ, (⤪ ⤪㰺㚱ᶲẞ, RTC便 便暣忶⣏) [10] 10K_04 SB_KBCRST# R715 VDD3 VBATT_BOOST# R632 [49] LOT6_CHG PM_PW ROK [32,50,56] 10K_04 [32] CPU_FANSEN DEBUG PORT [34] LAN_W AKEUP# SW I# [30,32,38,42,48] 1 2 3 4 VDD3 C [31] [35,60] 80CLK 3IN1 SMC_BAT 80CLK [37] 3IN1 [37] VDD3 AC D41 BAV99 RECTIFIER A C [35,60] SMD_BAT [60] BAT_DET 85204-04001 PCB Footprint = 85205-0400M PMOSFET_CONTROL# 10K_04 AC D40 BAV99 RECTIFIER R339 R338 R626 R665 R634 1.5K_04 1.5K_04 20K_1%_04 100K_04 10K_04 B A C AC D42 BAV99 RECTIFIER SMC_BAT SMD_BAT BAT_DET KB-DET VGASEN_SEL BAT_VOLT C920 1u_6.3V_X5R_04 A VDD3 5VT/FSCE#/GPG3 5VT/FMOSI/GPG4 5VT/FMISO/GPG5 5VT/FSCK/GPG7 GPD5/GINT/CTS0#/5VT GPB0/RXD/SIN0/5VT GPB1/TXD/SOUT0/5VT 5VT/DSR0#/GPG6 101 102 103 105 104 ALSPI_CE# R704 ALSPI_MSI R705 ALSPI_MSO R706 ALSPI_SCLKR707 0_04 0_04 0_04 0_04 SPI_CS_0# [30] SPI_SI_R [30] SPI_SO_R [30] SPI_SCLK_R [30] VDD3 VDD3 R619 47K_04 AIRPLAN_LED# [48] D29 C A ZD5231BS2 R615 90.9K_1%_04 B C913 R614 C987 *0.1u_10V_X7R_04 R642 *20mil_Short-p E 75 VIN 4 EC_RSMRST# 2 Q45 2SK3018S3 RSMRST# [32] S G NV_EN_DOW N C [27] U38 74AHC1G08GW 1 R622 AVSS VSS1 VSS3 VSS4 VSS5 VSS6 VSS7 1 27 49 91 113 122 VCORE 12 IT8587E/FX Q46 BTN3904 M-SOT23-CBE A 20K_1%_04 0.1u_10V_X7R_04 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ KBC_AGND Title [5,26,30,31,32,33,34,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [3,8,9,10,11,12,13,26,30,31,32,33,34,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [10,39,50,53,54,55,56,57,58,59,60] VIN Size A3 Date: 5 B - 36 KBC IT8587 C VGA_FANSEN [49] ALL_SYS_PW RGD [5,10,34,57] GPE4/PWRSW 47K_04 A 10K_04 IT8587 GPD0/RI1# GPD1/RI2#/5VT UART 108 109 R703 EC_RSMRST# 35 17 47 123 100 [47] GPF4/PS2CLK2/5VT GPF5/PS2DAT2/5VT GP INTERRUPT [32] KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5 GPI5/ADC5/DCD1# 5VT/CLKRUN#/ID0/GPH0 GPI6/ADC6/DSR1# 5VT/CRX1/SIN1/SMCLK3/ID1/GPH1 WAKE UP [50] [10,49] 5VT/SSCE0#/GPG2 J_80DEBUG1 CTX0/TMA0/GPB2 6.8K AUTO_LOAD_MODE GPJ0/TACH2 GPJ4/DAC4/DCD0# GPJ5/DAC5/RIG0# RSMRST# PCH & EC ⎒暨PULL DOWNᶨ ᶨ怲,㑯 㑯1 95 120 124 10K OPTION (⎗ẍ嬲≽ὅEC㍸ὃ䘬EXECL堐) 㛒⛐EXECL堐ᷕ䘬≇傥⎗ẍ冒埴␥⎵ U44B *0_04 VBATT_BOOST# 71 72 PA50 VBATT_BOOST# [49] VGASEN_SEL [45,48,50,54] 106 R618 PS/2 80CLK 3IN1 58 59 60 61 62 63 64 65 D N17E-G2 R661 IT8587E/FX 5VT/( PD )DTR1#/SBUSY/ID7/GPG1 GPB3/SMCLK0/5VT GPB4/SMDAT0/5VT 5VT/RTS1#/GPE5 5VT/LPCPD#/GPE6 25 31 32 34 J_KB2 85208-24051 GPI7/ADC7/CTS1# *5p_50V_NPO_04 [39] KBC_BEEP LED_BAT_CHG LED_BAT_FULL [48] LED_PW R KSO0/PD0 KSO1/PD1 KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15 5VT/SSCE1#/VCEN/TM/GPG0 PWM [48] [48] KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7 GPI0/ADC0 GPI1/ADC1 GPI3/ADC3 GPI4/ADC4 SMBUS 47_04 SMC_BAT_EC 47_04 SMD_BAT_EC 24 74 3 VBAT K/B MATRIX WRST# GPJ1 AVCC VSTBY1 VSTBY2 VSTBY3 VSTBY4 VSTBY5 VSTBY6 GPM0/LAD0 GPM1/LAD1 GPM2/LAD2 GPM3/LAD3 GPM4/LPCCLK LPC GPM5/LFRAME# GPM6/SERIRQ GPD2/LPCRST#/5VT J_KB1 1 2 3 7 [36] KBLIGHT_ADJ 9 10 13 [44] TBTA_HRESET 16 DSx 17 R644 SUS_PW R_ACK#_EC 18 [49] VGA_FAN2 19 [49] VGA_FAN1 20 21 22 23 [32] ME_W E 24 5 Sheet 35 of 77 KBC IT8587 10 9 8 7 13 6 5 22 VCC U44A [32,47] LPC_AD0 [32,47] LPC_AD1 [32,47] LPC_AD2 [32,47] LPC_AD3 [32] PCLK_KBC [32,47] LPC_FRAME# [32,47] SERIRQ [34,37,38,42,47,48] BUF_PLT_RST# 26 50 92 114 121 127 1 11 EMI Solution KB-SO0 KB-SO1 KB-SO2 KB-SO3 KB-SO4 KB-SO5 KB-SO6 KB-SO7 KB-SO8 [32] KB-SO9 PA70 3 HCB1005KF-121T20 D L35 3.3VS B.Schematic Diagrams 4 5 6 8 11 12 14 15 KB-SI0 KB-SI1 KB-SI2 KB-SI3 KB-SI4 KB-SI5 KB-SI6 KB-SI7 VDD3 C944 D C 1 RA R637 MODEL_ID L26 HCB1005KF-121T20 . VDD3 J_KB1 85208-24051 PA50 KBC_AVDD L47 HCB1005KF-121T20 2 VDD3 IT8587(Follow IT8991 PIN Define) 4 3 2 [35] KBC 8587 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 35 of 77 Schematic Diagrams RGB and White KB LED 5 4 3 KEYBOARD RGB LED 2 1 RBG FOR PA5 ᶵἧ䓐⢾悐RESET, TLC59116F RESET# pin天pull high. 3.3VS U36 27 VCC OUT0 OUT1 OUT2 C884 24 25 26 [26,35,44] SMC_VGA_THERM [26,35,44] SMD_VGA_THERM R610 EC_CTRL_EN# *0_04 C906 OUT6 OUT7 OUT8 RESET# SCL OUT9 SDA OUT10 OUT11 NC3 NC4 OUT12 GND OUT13 GND1 OUT14 GND2 OUT15 TLC59116FIRHBR 1000p_50V_X7R_04 6 8 9 KBZONE2_B KBZONE2_R KBZONE2_G 10 11 14 KBZONE3_B KBZONE3_R KBZONE3_G J_KBLED2 2A 5VS C908 4.7u_25V_X5R_08 J_KB1_1 PA50 15 16 17 BOTZONE_R BOTTOM_G BOTTOM_B 19 20 21 22 BOTZONE1_R BOTZONE1_G BOTZONE1_B [35] [35] KB-SO16 KB-SO17 [35] KB-DET KB-SO16 KB-SO17 1 2 3 4 KB-DET NC1 NC2 1 2 3 4 5 6 NC2 7 NC1 8 9 10 11 12 D FP225H-012S10M PA50 M:6-20-94K50-012 S:6-20-94K60-012 FP215H-004S1BM PCB Footprint = 85201-0405R LOW :RGB 婳冒埴䡢娵暣㳩(冒埴婧㔜),㭷ᶨ忂忻ᶵ天OVER 100mA KBZONE1_R KBZONE1_G KBZONE1_B KBZONE2_R KBZONE2_G KBZONE2_B KBZONE3_R KBZONE3_G KBZONE3_B RGB FOR PA7 TLC59116FIRHBR FP225H-012S10M 2A 5VS C296 4.7u_25V_X5R_08 C J_KB2_1 KB-SO16 1 KB-SO17 2 NC1 3 NC2 KB-DET 4 FPC1004-4AW -S PCB Footprint = fp226h-004xxxm_l 6-20-94A30-004 HIGH: White PA5枸 枸䔁 KBZONE1_R KBZONE1_G KBZONE1_B KBZONE2_R KBZONE2_G KBZONE2_B KBZONE3_R KBZONE3_G KBZONE3_B BOTTOM LIGHT 1 12 11 10 9 8 7 NC1 6 NC2 5 4 3 2 1 J_KBLED1 M:6-20-94K50-012 S:6-20-94K60-012 C Sheet 36 of 77 RGB and White KB LED BOTTOM LIGHT J_BL2 1 2 3 4 5 6 7 8 9 10 B 5VS B BOTZONE_DET BOTZONE_R BOTTOM_G BOTTOM_B [34] FP225H-010S10M FP225H-010-xxxM KEYBOARD WHITE LED 5VS 3.3VS R233 10K_04 L25 . *HCB1608KF-121T30 5VS A KBLED_DET KB_W HLED_PW R C940 10u_6.3V_X5R_06 GPIO H: W /O KB_LED L: W/KB_LED [32] KB_W HLED_PW R C924 0.1u_10V_X7R_04 WHITE FOR PA7 WHITE FOR PA5 JACK_12/23 U37 FON-KB 1 2 3 4 FON VIN VOUT VSET GND GND GND GND 8 7 6 5 J_LEDKB2 6 5 4 3 2 1 NCT3940S-A KBLIGHT_ADJ [35] J_LEDKB1 KB_W HLED_PW R KBLED_DET 50501-0060N-001 PA50 6 5 4 3 2 1 KB_W HLED_PW R Title 6-20-94K30-106 Size A3 Date: 5 4 3 VIN 5VS 3.3V VDD3 3.3VS A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ KBLED_DET FP225H-006S10M 6-20-94K30-106 [10,35,39,50,53,54,55,56,57,58,59,60] [10,11,12,13,39,40,41,47,48,49,50,61,62,63,64] [2,10,27,38,43,45,48,50,51,52,55,56] [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] [3,8,9,10,11,12,13,26,30,31,32,33,34,35,37,38,39,41,43,46,47,48,49,50,57,64] 2 [36] RGB AND WHITE KB LED Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 36 of 77 1 RGB and White KB LED B - 37 B.Schematic Diagrams [35] 29 30 7 18 23 OUT3 OUT4 OUT5 E_PAD 10K_04 R609 A0 A1 A2 A3 NC NC1 NC2 KBZONE1_B KBZONE1_R KBZONE1_G 33 0.1u_10V_X7R_04 D 31 32 1 2 12 13 28 3 4 5 Schematic Diagrams M.2 PCIE4X SSD 5 4 3 2 NGFF_M (M2) SSD_1 (PCIE 4X) R804 SATAGP0 1K_04 R225 3.3VS J_SSD1 3.3VS [31] 1 >120 mil 75 73 71 69 67 SATAGP0 H: PCIe L: SATA 43K_04 GND13 GND12 GND11 PEDET(NC-PCIe/GND-SATA) NC18 3.3V8 3.3V7 3.3V6 SUSCLK(32Khz)(O) 74 72 70 68 FOR OPTANE SUPPORT C918 C923 C916 0.1u_10V_X7R_04 0.1u_10V_X7R_04 22u_6.3V_X5R_08 GND GND GND M KEY D [31] CLK_PCIE_SSD [31] CLK_PCIE_SSD# [31] [31] [31] [31] PCIE_TXP9_SATA0A_TXP_SSD PCIE_TXN9_SATA0A_TXN_SSD C905 C902 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PCIE_TXP9_SATA0A_TXP_SSD_R PCIE_TXN9_SATA0A_TXN_SSD_R C891 C887 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PCIE_TXP10_SSD_R PCIE_TXN10_SSD_R PCIE_RXN9_SATA0A_RXN_SSD PCIE_RXP9_SATA0A_RXP_SSD [31] [31] PCIE_TXP10_SSD PCIE_TXN10_SSD B.Schematic Diagrams [31] PCIE_RXP10_SSD [31] PCIE_RXN10_SSD [31] [31] Sheet 37 of 77 M.2 PCIE4X SSD C879 C874 PCIE_TXP11_SSD PCIE_TXN11_SSD [31] [31] PCIE_RXP11_SSD PCIE_RXN11_SSD [31] [31] PCIE_TXP12_SSD PCIE_TXN12_SSD C870 C866 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PCIE_TXP11_SSD_R PCIE_TXN11_SSD_R PCIE_TXP12_SSD_R PCIE_TXN12_SSD_R [31] PCIE_RXP12_SSD [31] PCIE_RXN12_SSD close to J_SSD2 conn C 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND10 REFCLKP REFCLKN GND9 PETp0/SATA-A+ PETn0/SATA-AGND8 PERp0/SATA-BPERn0/SATA-B+ GND7 PETp1 PETn1 GND6 PERp1 PERn1 GND5 PETp2 PETn2 GND4 PERp2 PERn2 GND3 PETp3 PETn3 GND2 PERp3 PERn3 GND1 GND0 NC17 NC16 PEWake#(IO) CLKREQ#(IO) PERST#(O) NC15 NC14 NC13 NC12 NC11 DEVSLP(O) NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 3.3V5 3.3V4 3.3V3 3.3V2 DAS/DSS#(I)(OD) NC1 NC0 3.3V1 3.3V0 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 D SSD_CLKREQ# BUF_PLT_RST# R807 R808 R809 VDD3 3IN1 80CLK 3IN1 [35,37] 80CLK [35,37] >120 mil 3.3VS FOR OPTANE SUPPORT C869 C873 C875 0.1u_10V_X7R_04 0.1u_10V_X7R_04 22u_6.3V_X5R_08 GND GND GND M2M_SSD_LED#R [48] 80 mils 3.3VS C C861 0.1u_10V_X7R_04 NFSM0-S6701-TP64 GND 0_04 0_04 0_04 [31] [34,35,37,38,42,47,48] PCB Footprint = NXSM0-S67XX-XX40 PCB Footprint婳 婳䡢娵㨇㥳ἧ䓐䘬Connector GND NGFF_M (M2) SSD_2 (PCIE 2X) 3.3VS >120 mil SATAGP_SSD2 L: SATA H: PCIE R354 43K_04 [31] SATAGP2 R357 75 73 71 69 67 SATAGP_SSD2 1K_04 B [31] CLK_PCIE_SSD2 [31] CLK_PCIE_SSD2# [31] [31] PCIE_TXP15_SATA2_TXP_SSD2 PCIE_TXN15_SATA2_TXN_SSD2 [31] [31] PCIE_RXN15_SATA2_RXN_SSD2 PCIE_RXP15_SATA2_RXP_SSD2 [31] [31] PCIE_TXP16_SSD2 PCIE_TXN16_SSD2 3.3VS J_SSD2 GND13 GND12 GND11 PEDET(NC-PCIe/GND-SATA) NC18 3.3V8 3.3V7 3.3V6 SUSCLK(32Khz)(O) 74 72 70 68 C1113 C1103 C1101 0.1u_10V_X7R_04 0.1u_10V_X7R_04 10u_6.3V_X5R_06 GND C1092 C1084 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PCIE_TXP15_SATA2_TXP_SSD2_R PCIE_TXN15_SATA2_TXN_SSD2_R C1075 C1069 0.22u_10V_X5R_04 0.22u_10V_X5R_04 PCIE_TXP16_SSD2_R PCIE_TXN16_SSD2_R close to J_SSD2 conn [31] PCIE_RXP16_SSD2 [31] PCIE_RXN16_SSD2 A 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND10 REFCLKP REFCLKN GND9 PETp0/SATA-A+ PETn0/SATA-AGND8 PERp0/SATA-BPERn0/SATA-B+ GND7 PETp1 PETn1 GND6 PERp1 PERn1 GND5 PETp2 PETn2 GND4 PERp2 PERn2 GND3 PETp3 PETn3 GND2 PERp3 PERn3 GND1 GND0 NC17 NC16 PEWake#(IO) CLKREQ#(IO) PERST#(O) NC15 NC14 NC13 NC12 NC11 DEVSLP(O) NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 3.3V5 3.3V4 3.3V3 3.3V2 DAS/DSS#(I)(OD) NC1 NC0 3.3V1 3.3V0 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 B SSD2_CLKREQ# [31] BUF_PLT_RST# [34,35,37,38,42,47,48] R810 R812 R811 0_04 0_04 0_04 3.3VS C1036 C1046 0.1u_10V_X7R_04 0.1u_10V_X7R_04 10u_6.3V_X5R_06 GND GND [48] 3.3VS A C1012 0.1u_10V_X7R_04 PCB Footprint婳 婳䡢娵㨇㥳ἧ䓐䘬Connector ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ GND 3.3VS Size A3 Date: B - 38 M.2 PCIE4X SSD GND M2M_SSD_LED#R2 80 mils PCB Footprint = NXSM0-S67XX-XX40 [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3 3IN1 [35,37] 80CLK [35,37] C1028 Title 4 VDD3 3IN1 80CLK >120 mil NFSM0-S6701-TP64 GND 5 GND GND M KEY PCH= HM170,cap Stuff Default close to J_SSD2 conn 2 [37] M.2 PCIE4X SSD_1/ 2X SSD_2 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 37 of 77 Schematic Diagrams M.2 3G/LTE/WIGIG/WLAN+BT 5 4 3 2 1 CURRENT2A㗪,DON'T DROP BELOW 3.135V PA5枸 枸䔁 3G POWER >120 mil 4 3.3V S2 Windows 8 3G_POWEREN Always hi. GQ2A MTS3572G6 3G GC2 0.1u_10V_X7R_04 5 GC3 3G 3G_3.3V GC6 0.1u_10V_X7R_04 3G GR4 100K_04 3G 6 G GQ2B MTS3572G6 3G GQ1 2SK3018S3 3G [32] USB3_TXP2 [32] USB3_TXN2 3G GC12 3G GC13 2 S1 G1 Close to J_3G1 0.1u_10V_X7R_04 1 GL3 4G LTE Default ᶵᶲẞ 普ᷕ㷔溆 BOT 3G_PW R_EN [32] USB3_RXP2 [32] USB3_RXN2 2 BODYSAR_N 3G_W AKE# 4/8 follow common del CONFIG_2 GND10 GND9 CONFIG_1 Reset#(O)1.8V ANTCTL3(I)1.8V ANTCTL2(I)1.8V ANTCTL1(I)1.8V ANTCTL0(I)1.8V GND8 REFCLKP REFCLKN GND7 PETp0/SATA-A+ PETn0/SATA-AGND6 PERp0/SATA-BPERn0/SATA-B+ GND5 PETp1/USB3.0-Tx+/SSIC-TxP PETn1/USB3.0-Tx-/SSIC-TxN GND4 PERp1/USB3.0-Rx+/SSIC-RxP PERn1/USB3.0-Rx-/SSIC-RxN GND3 GPIO_12(IO)1.8V GPIO_11(IO)1.8V CONFIG_0 BODYSAR⎒䓐㕤⸛㜧 3G_WAKE#枸䔁ᶵᶲ,Ữ⚈䁢EC㰺Pinẍ㓡䁢ᶵ㍍ GPS_DISABLE# GR1 *100_06 1 GL2 USB3_RXP2_R USB3_RXN2_R 4 3 *W CM2012F2S-SHORT 3G_EN C USB3_TXP2_R USB3_TXN2_R 2 3 0.1u_10V_X7R_04 4 *W CM2012F2S-SHORT 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 3G_PW R_EN 3G_3.3V PW R_ON_OFF [30] USB_PN3 [30] USB_PP3 1 GL1 4 3.3V4 3.3V3 3.3V2 SUSCLK(32Khz)(O) SIM Detect(O) COEX1(I/O)1.8V COEX2(I/O)1.8V COEX3(I/O)1.8V NC1 NC0 PEWake#(IO) CLKREQ#(IO) PERST#(O) GPIO_4(IO)1.8V GPIO_3(IO)1.8V GPIO_2(IO)1.8V GPIO_1(IO)1.8V GPIO_0(IO)1.8V DEVSLP(O) UIM_PWR(I) UIM_DATA(IO) UIM_CLK(I) UIM_RESET(I) GPIO_8(IO)1.8V GPIO_10(IO)1.8V GPIO_7(IO)1.8V GPIO_6(IO)1.8V GPIO_5(IO)1.8V 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 GC16 47u_6.3V_X5R_08 GC15 47u_6.3V_X5R_08 GC14 47u_6.3V_X5R_08 3G GC7 0.1u_10V_X7R_04 3G GC5 0.1u_10V_X7R_04 11 9 7 5 3 1 2 4/8 follow common del GR2 *12K_06 GND2 USB_DUSB_D+ GND1 GND0 CONFIG_3 470p_50V_X7R_04 3G M.2 3G/4G-LTE module SIM Detect Pin 66炻ℏ悐䁢1.8V with Pull-up暣旣 GND GR6 *10K_04 3.3V 4/8 RF⺢嬘枸䔁 UIM_PW R UIM_DATA UIM_CLK UIM_RST UIM_PW R UIM_DATA [48] UIM_CLK [48] UIM_RST [48] GPS_DISABLE# GR7 [48] GC9 0.1u_10V_X7R_04 3G 0_04 3G GND GND HUAWEI MU736 ⎗㍍⍿3.3V GPIO_9/DAS/DSS#(I)(OD) W_DISABLE#1(O) Full_Card_Power_Off#(O)1.8V 3.3V1 3.3V0 10 8 6 4 2 M2B_3GSSD_LED#R PW R_ON_OFF C GR8 3G 3G_EN 10K_04 80 mils + GC8 GC4 EEFCX0J221YR10u_6.3V_X5R_06 NFSB0-S6701-TP64 GND [48] GC11 B KEY 3 *W CM2012F2S-SHORT GND D SIM_DET PCB Footprint = NXSB0-S67XX-XX40 PCB Footprint婳 婳䡢娵㨇㥳ἧ䓐䘬Connector 3G 3G_3.3V GC10 0.1u_10V_X7R_04 3G 3G 3G [35] Sheet 38 of 77 M.2 3G/LTE/WIGIG/ WLAN+BT GND GND GND J_W LAN1 [31] CLK_PCIE_W IGIG# [31] CLK_PCIE_W IGIG WLAN+BT/WIGIG WiGig Ʉ Wi-Fi: PCIe v2.1 Gen1 Ʉ BT: USB 2.0 Ʉ WiGig IO: PCIe v2.1 Gen2[30,32,35,38,42,48] B [31] [30] [30] PCIE_RXN8_W IGIG PCIE_RXP8_W IGIG [30] [30] PCIE_TXN8_W IGIG PCIE_TXP8_W IGIG C840 C836 R530 LAN_W AKEUP# W LAN_CLKREQ# [31] [31] CAP CLOSE TO M.2 CONN 3.3VS CLK_PCIE_W LAN# CLK_PCIE_W LAN R525 0.1u_10V_X7R_04 PETN1 0.1u_10V_X7R_04 PETP1 *0_04 W LAN_CLKREQ# 10K_04 CAP CLOSE TO M.2 CONN WLAN [30] [30] PCIE_RXN7_W LAN PCIE_RXP7_W LAN [30] [30] PCIE_TXN7_W LAN PCIE_TXP7_W LAN C818 C814 0.1u_10V_X7R_04 PETN0 0.1u_10V_X7R_04 PETP0 D02A_0317_ℙ䓐䶂嶗 U28 5 4 C802 3 1u_6.3V_X5R_04 VIN VOUT 1 VIN/SS EN W IGIG_3.3V >120 mil R522 *10K_04 W LAN_CLKREQ# [35] W IGIG_PW R_EN ㍍⇘EC ,枰冯EC䡢娵 40 mil 2 *0_04 R211 C433 LAN_W AKEUP# [30,32,35,38,42,48] W IGIG_CLKREQ# [31] 0.1u_10V_X7R_04 *10K_04 3.3V R205 R198 10K_04 10K_04 W IGIG_3.3V B W LAN_EN [35] BT_EN [35] BUF_PLT_RST# [34,35,37,42,47,48] SUS_CLK [32] R795 R796 R797 0_04 0_04 0_04 CL_CLK1 CL_DATA1 CL_RST#1 W IGIG_3.3V CL_CLK1 [31] CL_DATA1 [31] CL_RST#1 [31] C848 C849 普ᷕ㷔溆 BOT W LAN_EN BT_EN W IGIG_PW R_EN W IGIG_3.3V A KEY 0.1u_10V_X7R_04 [30] [30] M: NCT3522U -- 6-02-03522-9C0 S: G5243A ---- 6-02-05243-9C0 AP2821KTR-G1 6-02-02821-9C0 W IGIG_3.3V 4/29 follow common, change net R214 C805 GND UP7553PMA5-25 A 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 22u_6.3V_X5R_08 W IGIG_3.3V >120 mil GND14 3.3V3 Reserved/REFCLKN1 3.3V2 Reserved/REFCLKP1 PEWake1#(IO)(0/3.3V) GND13 CLKREQ1#(IO)(0/3.3V) Reserved/PERn1 PERST1#(IO)(0/3.3V) Reserved/PERp1 Reserved1 GND12 ALERT#(O)(0/3.3V) Reserved/PETn1 I2C CLK(I)(0/3.3V) Reserved/PETp1 I2C DATA(IO)(0/3.3V) GND11 W_DISABLE#1(I)(0/3.3V) PEWake0#(IO) Reserved/W_DISABLE#2(I)(0/3.3V) CLKREQ0#(IO) PERST0#(I)(0/3.3V) GND10 SUSCLK(32Khz)(I)(0/3.3V) REFCLKN0 COEX1(I/O)1.8V REFCLKP0 COEX2(I/O)1.8V GND9 COEX3(I/O)1.8V PERn0 VENDOR DEFINED2 PERp0 VENDOR DEFINED1 GND8 VENDOR DEFINED0 PETn0 GND6 PETp0 DP_ML0p GND7 DP_ML0n DP_HPD(IO)(0/3.3V) GND6 GND5 DP_ML1p DP_ML2p DP_ML1n DP_ML2n GND4 GND3 DP_AUXp DP_ML3p DP_AUXn DP_ML3n GND2 DP_MLDIR GND (In)/3.3V (Out)/NC LED#2(I)(OD) 22u_6.3V_X5R_08 VDD3 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 7 5 3 1 USB_PN8 USB_PP8 GND1 USB_DUSB_D+ GND0 LED#1(O)(OD) 3.3V1 3.3V0 6 4 2 close the M2 connect 40 mil W IGIG_3.3V 4/29 follow common design A NFSA0-S6701-AP64 PCB Footprint = NXSA0-S67XX-XX40 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ PCB Footprint婳 婳䡢娵㨇㥳ἧ䓐䘬Connector [5,26,30,31,32,33,34,35,37,48,49,50,51,52,53,54,56,59,60] VDD3 [10,11,12,13,36,39,40,41,47,48,49,50,61,62,63,64] 5VS [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,39,41,43,46,47,48,49,50,57,64] 3.3VS [39,44,45,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V [2,10,27,43,45,48,50,51,52,55,56] 3.3V Title Size A3 Date: 5 4 3 2 [38] M.2 3G/LTE/ WIGIG/WLAN+BT Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 38 of 77 1 M.2 3G/LTE/WIGIG/WLAN+BT B - 39 B.Schematic Diagrams 3G_PW R_EN 1 3G_PW R_EN S 330K_04 D1 GR3 3G GR5 10_06 3G D 1u_6.3V_X5R_04 3G [35] 3G_3.3V 80 mils GJ_3G1 >120 mil 3 D2 G2 D 3G /LTE CARD USB3.0 Schematic Diagrams Audio 5 4 3 2 1 C1062 0.1u_10V_X7R_04 C616 0.1u_10V_X7R_04 C611 0.1u_10V_X7R_04 Layout Note: U43 pin 1 ~ pin 11 and pin 47 and pin 48 are Digital signals. The others are Analog signals. 898: ᶲẞ 892: ᶵᶲẞ reltek check 3.3VS_AUD 3.3VS Layout Note: D L22 (1)MIC1-L (U13.21) (3)LINE-L (U13.23) (2)MIC1-R (U13.22) (4)LINE-R (U13.24) ␐⚵⽭枰⊭央 AUDG, ᶼ⃀慷性嶐崲 +5VS & +VIN plane. 5VS_AUD 40mil HCB1005KF-121T20 C886 C901 C903 0.1u_10V_X7R_04 10u_6.3V_X5R_06 0.1u_10V_X7R_04 0.1u_10V_X7R_04 L28 C571 C963 1u_6.3V_X5R_04 10u_6.3V_X5R_06 C880 47p_50V_NPO_04 C885 L21 HDA_BITCLK FCM1005MF-300T03 [32] HDA_SDIN0 [32] HDA_SYNC [32] HDA_RST# Sheet 39 of 77 Audio PC BEEP [35] KBC_BEEP [32] PCH_SPKR [41] D28 1 A 22_04 HDA_SDOUT_R 5 6 22_04 22_04 HDA_SDIN0_R 8 22_04 HDA_SYNC_R 10 22_04 HDA_RST#_R 11 Max: 0.5inch EAPD_MODE SPDIFO 3 BEEPR597 R593 C883 47K_04 4.7K_04 *0.1u_10V_X5R_04 [48] [48] L30 HCB1005KF-121T20 C889 JD_SENSEA JD_SENSEB 5VS_AUD R629 C *ZD5231BS2 R277 C912 C917 *1K_04 INT_MIC_R 13 34 *0_04 T93 INT_MIC_OUT 12 1u_6.3V_X5R_04 898: ᶲẞ0R 892: ᶵᶲẞ reltek check 37 29 LDO_IN 5V ALC889 ᶵᶲẞ. *4.7u_6.3V_X5R_06 *4.7u_6.3V_X5R_06 MIC2_L MIC2_R C965 22u_6.3V_X5R_08 AUDG [48] MIC1_L_M [48] MIC1_R_M AUDG Connect standby power(for pop noise) 47 48 BAT54CS3 D34 16 17 18 19 20 MIC1_L_M R281 MIC1_R_M R289 75_04 75_04 C919 C927 7 1 9 DVSS *22p_50V_NPO_04 R596 R595 R594 R250 R251 EAPD_MODE [48] C 2 A C 10u_6.3V_X5R_06 C1144 HDA_SDOUT 4.7u_6.3V_X5R_06 MIC1_L_M_R 21 4.7u_6.3V_X5R_06 MIC1_R_M_R 22 GPIO0/DMIC-CLK/SPDIFO_2* GPIO1/DMIC_DAT REGREF SDATA-OUT BIT-CLK SDATA-IN SYNC RESET# VREF DIGITAL SRUW$ SURR-L SURR-R VREFO-F VREFO-E SPDIF-OUT FRONT-OUT-L SRUW' FRONT-OUT-R PCBEEP SRUW( MIC2-L MIC2-R ANALOG SRUW* LINE2-L LINE2-R CENTER LFE SIDE-L SRUW+ SIDE-R SRUW) GPIO2 CD-L CD-GND CD-R MIC1-L MIC1-R FCM1005KF-601T03 D AUDG JDREF SRUW% ALC892 27 MIC1-VREFO-L *2.2K_04 C957 1u_6.3V_X5R_04 C573 *10u_6.3V_X5R_06 R288 ⤪㚱3D AMP㯋枛 C957ᶵᶲẞ炻C573ᶲẞ INT_MIC_OUT 2.2K_04 C544 SPDIFI/EAPD VRP LDO-IN *HCB1005KF-121T20 0_04 R287 MIC1-VREFO-L VREFO-B(2) Sense A Sense B *0.1u_10V_X7R_04 R342 LINE1-L SRUW& LINE1-R 28 32 MIC1-VREFO-L MIC1-VREFO-R 39 41 30 31 FRONT_L FRONT_R [40,41] [40,41] MIC1-VREFO-R R286 C 2.2K_04 43 44 40 AUDG HEADPHONE_L HEADPHONE_R 14 15 45 46 *680p_50V_X7R_04 AUDG D02_0313_KAI T94 35 36 33 *330p_50V_X7R_04 C545 T137 T138 MIC2-VREFO MIC1_L_M AUDG C915 C909 10u_6.3V_X5R_06 10u_6.3V_X5R_06 SIDE-L_R SIDE-R_R INTERNAL PU 50K JDREF 23 24 R630 C928 75_1%_04 75_1%_04 C569 *0.1u_10V_X7R_04 C572 *10u_6.3V_X5R_06 20K_1%_04 R631 R617 R612 AUDG SIDE_L SIDE_R MIC1_R_M [48] [48] C543 *680p_50V_X7R_04 AUDG AUDG *5.1K_1%_04 *100p_50V_NPO_04 26 42 [32] [32] 2 4 3 5VS MIC2-VREFO AUDG LDO_OUT1 LDO_OUT2 47p_50V_NPO_04 AVSS1 AVSS2 C881 DVDD1 DVDD-IO MIC_CLK MIC_DATA MIC_CLK MIC_DATA A * ALC892:Pin2->GPIO0/DMIC_CLK/SPDIFO_2;Pin3->REGREF;Pin4->GPIO1/DMIC_DATA;Pin29->LDOVDD * ALC898:Pin2->GPIO0/DMIC_CLK/SPDIFO_2;Pin3->REGREF;Pin4->GPIO1/DMIC_DATA;Pin29->LDOVDD AUDG HEADPHONE-L 暞ẞ㔠:31 pcs [48] 3D AMP B 5V HP_JSGND HP_JSGND [48] C596 C593 C1006 2.2u_6.3V_X5R_04 0.1u_10V_X7R_04 22u_6.3V_X5R_08 HP_JSGND VIN B R690 0616 + C964 15_1%_04 EEFCX0J221YR HEADPHONE_R_CR701 470_04 HDPHONE_R C1052 1u_16V_X7R_06 C1051 INL VREF REXT INR C1049 6-07-1052D-3GD 2200p_50V_X7R_04 2200p_50V_X7R_04 D 1M_04 HP_JSGND_EN C2_3DL C1_3DL PGND C1_3DR TH PAD SV3H612V 6-02-03612-1Q0 12 11 10 9 C2_3DL C990 C1_3DL C991 HP_PGND C1_3DR C992 0.01u_50V_X7R_04 0.01u_50V_X7R_04 C2_3DR 0.01u_50V_X7R_04 JDETECT㚫 㚫㓡䁢MUTE#≇ ≇傥 (LOW MUTE) SV3H612 PIN14 AUDG 0.01u_50V_X7R_04 HP_JSGND G QA R742 1M_04 0701 RC AUDG C1050 AUDG A ⤪㚱ᶵᶲAMP暨 暨㯪,⎗ ⎗⡆≈ᶳ↿暣旣枸䔁 HEADPHONE_L R695 *0_04 HEADPHONE-L HEADPHONE_R R699 *0_04 HEADPHONE-R HP_SCL HP_SDA 1u_6.3V_X5R_04 R689 R693 C1032 C1010 22_1%_04 22_1%_04 10p_50V_NPO_04 10p_50V_NPO_04 AUDG 䶂嶗ᷕ⤪䴻㚱 ⎗䚩䔍 SMB_CLK [32,47,55] SMB_DATA [32,47,55] R340 AUDG HEADPHONE-R A [48] 婧㔜IC Pin2忋㍍ᷳRefrence 暣⭡军2.2uFẍᶲ, ⛐塓≽俛㨇倥ᶵ⇘㉱拲倚 Noise ⺈⓮㚨㕘⮵䫾 VREF㓡⚆1u_6,3V_X5R_04, REXT暣旣ᶵᶲẞ Title [39] audio 892 Size A3 Date: B - 40 Audio 0_04 AUDG [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,41,43,46,47,48,49,50,57,64] 3.3VS [44,45,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V [10,11,12,13,36,40,41,47,48,49,50,61,62,63,64] 5VS [10,35,50,53,54,55,56,57,58,59,60] VIN 5 0701 QB Q56 UK3018 17 C1004 Q55 UK3018 G S HEADPHONE_R 1 2 3 4 D HDPHONE_L HP_VREF S 470_04 OUTL VDD JDETECT SGND C1045 1u_16V_X7R_06 HEADPHONE_L_C R700 AUDG OUTR SDA SCL C2_3DR HEADPHONE_L R743 RB 16 15 14 13 U46 6-07-1052D-3GD 5 6 7 8 B.Schematic Diagrams [47] [47] *HCB1005KF-121T20 25 38 AUDG U40 C993 C592 40mil C512 898: ᶲẞ0R 892: ᶲẞHCB1005KF-121T20 reltek check 2 L24 HCB1005KF-121T20 1 2 L23 HCB1005KF-121T20 1 898: ᶲẞ 892: ᶵᶲẞ realtek check 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 1 39 of 77 Schematic Diagrams Audio Subwoofer 5 4 3 SR27 2.2_04 SC23 2200p_50V_X7R_04 2 1 GND SAMP_PW R SAMP_PW R cost down 12/16 SD1 4 5 11 SR22 18K_1%_06 SC14 0.1u_10V_X7R_04 6 SC15 0.1u_10V_X7R_04 7 2CH_SUBW OOFER_RC SC12 0.1u_10V_X7R_04 4 SC11 0.1u_10V_X7R_04 3 AUDG_2 GND GND SR20 100K_04 2 SC22 10p_50V_NPO_04 SR18 18K_1%_04 SC10 0.1u_10V_X7R_04 GND SR14 SR15 SR39 *10K_04 *10K_04 120K_04 AUDG_2 10 16 26 32 1 ROUTP1 ROUTP2 RINP RGND LINN PFLAG GAIN1 GAIN0 DRC1 DRC0 LOUTP2 LOUTP1 LGND 3V3LDO PMAX SR19 10K_04 AUDG_2 ROUTN1 ROUTN2 APA2607QBI LINP LOUTN1 LOUTN2 13 14 15 31 30 SJ_SUBW OOF1 40 mil SUBW OOFER+ SL1 HCB1005KF-121T20 SUBW OOFER- SL2 HCB1005KF-121T20 88266-02001 40 mil 27 28 SAMP_PW R SC33 4.7u_25V_X5R_08 + SC34 *220u_25V_V_B SC32 4.7u_25V_X5R_08 AUDG_2 *0402_short SR28 4.32K_1%_04 FILTER SUB_L 8 SR3 30K_1%_04 SC4 0.1u_10V_X7R_04 SR21 100K_04 5 + OUT 6 A - AUDG_2 3 2 SC29 0.01u_50V_X7R_04 7 SU3B LM358G 0.01u_50V_X7R_04 SAMP_PW R + - SINPUT2+ SR9 *4.3K_1%_04 SC7 *0.1u_10V_X7R_04 SU4A LM358G 1 OUT SC31 0.01u_50V_X7R_04 5 6 + - SUB Woofer out 7 OUT SU4B LM358G 2CH_SUBW OOFER_RC SR32 0_04 AUDG_2 SR31 0_04 AUDG_2 AUDG_2 SAMP_PW R 8 SR33 4.32K_1%_04 SC30 SR8 *0.1u_10V_X5R_04 *4.3K_1%_04 V+ FRONT_L 4 [39,41] SAMP_PW R 100K_04 V- SR24 SAMP_PW R SR29 4.32K_1%_04 SOUTPUT1 V+ AUDG_2 AUDG_2 0.01u_50V_X7R_04 SR7 3.32K_1%_04 4 SC25 SR6 3.32K_1%_04 8 4 - SC28 FC: 300Hz SUB_R V- 2 B V+ SU3A LM358G 1 OUT V- + SEMC1 *1000p_50V_X7R_04 AUDG_2 4 3 V+ 8 30K_1%_04 SR4 SC6 0.1u_10V_X7R_04 SR23 100K_04 0.1u_10V_X7R_04 FRONT_R 0.1u_10V_X7R_04 [39,41] SAMP_PW R 100K_04 SC2 SR25 SAMP_PW R 1000p_50V_X7R_04 0.1u_10V_X7R_04 B SC27 GND AUDG_2 SC1 SC35 AUDG_2 Sheet 40 of 77 Audio Subwoofer 6-20-63120-102 SR36 SR37 SR17 10K_04 10K_04 *120K_04 AUDG_2 C AUDG_2 AUDG_2 AUDG_2 Speaker: ℙ䓐6-23-5P15E-0W3 4ȍ, typ=2.5W max=4W AUDG_2 AUDG_2 SR10 AUDG_2 6-20-63120-102 6-20-43130-104 AUDG_2 SR35 *10K_04 2 1 29 SC13 0.1u_10V_X7R_04 SGAIN1_R SGAIN0_R SDRC1_R SDRC0_R SPFLAG SR11 *10K_04 D 11 12 V- SR13 10K_04 9 SPMAX RINN SC5 SR12 10K_04 18 25 24 23 22 SPFLAG SGAIN1_R SGAIN0_R SDRC1_R SDRC0_R SAMP_3V3LDO SAMP_3V3LDO 婧㔜GAINῤ *1000p_50V_X7R_04 GND SR38 *10K_04 1000p_50V_X7R_04 1000p_50V_X7R_04 C SOSCIN SC3 SC21 330p_50V_X7R_04 21 20 AUDG_2 SAMP_PW R SAMP_PW R SC24 0.1u_10V_X7R_04 AUDG_2 AUDG_2 AUDG_2 SINPUT2- SR34 *100K_04 SC26 0.1u_10V_X7R_04 AUDG_2 A SR30 *100K_04 AUDG_2 AUDG_2 AUDG_2 AUDG_2 Title [40] audio 892 SUBW OOFER [10,11,12,13,36,39,41,47,48,49,50,61,62,63,64] 5VS Size A3 Date: 5 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 40 of 77 1 Audio Subwoofer B - 41 B.Schematic Diagrams GND GND OSCIN OSOC AUDG_2 SEMC2 SC16 0.1u_10V_X7R_04 AUDG_2 AUDG_2 G5110 SD MUTE Case_GND 1 COMP 17 19 SR40 0_04 AGND SS AMP_EN LVDDN LVPPD [41] SR26 130K_1%_06 SHDN SC20 15000p_50V_X7R_06 2 FB SC8 0.1u_10V_X7R_04 SC9 0.1u_10V_X7R_04 AUDG_2 33 GND GND GND_Thermal GND 6 7 LX1 LX2 FREQ VLDO IN RVDDP RVDDN 8 *0402_short SAMPPW R_FREQ9 SR2 10_04SAMPPW R_EN 3 10 SU1 SC17 0.1u_10V_X7R_04 SR16 10K_04 C FMS3004-AS-H SR1 SC19 10u_6.3V_X5R_06 A SU2 VREF . SC18 10u_6.3V_X5R_06 SAMPPW R_SW 2.2uH_4*4*2.0 8 SL3 5VS 5 D Schematic Diagrams Audio Port 1 5 4 3 2 1 AMP_5VS L5 HCB1608KF-121T30 TPA2008D2 P2P BA20550 (TSSOP24) The volume control.the gain range is from -80db(Vvolume=5V) to +20db(Vvolume=0V) with 64 steps precise control. 5VS C945 C967 C951 0.1u_10V_X7R_04 0.1u_10V_X7R_04 22u_6.3V_X5R_08 U15 R290 0.1u_10V_X7R_04 [39,40] AUDG 枛慷婧㔜䓐 R834 AUDG 20 Mil FRONT_L FRONT_L 5VS On 6 7 *100K_1%_04 1 AUDG 6.98K_1%_04 14 R301 10K_1%_04 15 PGNDL1 PGNDR1 PGNDL2 PGNDR2 PVDDL1 VOLUME PVDDL2 VDD 17 ROUTN L9 16 FCM1005KF-121T03 ROUT- 19 20 Mil 5 LOUTP L6 LOUTN L8 FCM1005KF-121T03 LOUT+ 9 4 13 20 Mil 8 FCM1005KF-121T03 LOUT- 12 ROUT+ ROUTLOUT+ LOUT- 2/16 add 1000p_50V_X7R_04 1000p_50V_X7R_04 1000p_50V_X7R_04 TPA2008D2 120K_04 AUDG AUDG AUDG 1 2 3 4 J_SPK1 20 Mil 18 C565 AGND PCB Footprint = 88266-04_L 88266-04001 C575 25 LOUTN D AUDG AUDG FCM1005KF-121T03 ROUT+ 20 Mil 1000p_50V_X7R_04 ROSC R304 220p_50V_NPO_04 LOUTP LINP COSC 11 C PVDDR2 NC 10 C581 ROUTN RINP LINN 2 R300 PVDDR1 RINN L7 C564 Sheet 41 of 77 Audio Port 1 23 C557 R282 4.7K_1%_04 0.1u_10V_X7R_04 C938 0.1u_10V_X7R_04 AUDG BYPASS 24 0_04 *100K_1%_04 0.1u_10V_X7R_04 AUDG ROUTP 20 21 C574 AUDG C 3.3VS Speaker wire length less than 8000mils , It don't need LC Filter. C523 SPKOUTR+,R-,L+,L- Trace width *0.1u_10V_X5R_04 Speaker 4 ohm------> 30mils, Via hole----->C40D20. R266 100K_04 [10,32,34,35,42,50,56] PCH_MUTE# D13 C RB751S-40H A D11 C *RB751S-40H A AUDIO AMP Enable 5 [32] SUSB# [39] B [35] R267 EAPD_MODE 0_04 U13 74AHC1G08GW 1 AMP_EN 4 2 KBC_MUTE# 3/31 枸䔁(⚈898㚫㉱low) C533 1000p_50V_X7R_04 AMP_EN C518 3 B.Schematic Diagrams for R833 C937 ROUTP Thermal_Pad C561 AUDG 22 2.2u_6.3V_X5R_04 . 20 Mil FRONT_R FRONT_R SHUTDOWN . C941 AUDG [39,40] 3 . AMP_EN . D [40] [10,11,12,13,36,39,40,47,48,49,50,61,62,63,64] [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,43,46,47,48,49,50,57,64] 5VS 3.3VS B *0.1u_10V_X7R_04 C548 0.1u_10V_X7R_04 EMI AUDG/DGND⋨↮ AUDG A A Title [41] audio 892 PORT1 Size A3 Date: 5 B - 42 Audio Port 1 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 1 41 of 77 Schematic Diagrams AR_TBT 5 4 3 TBT_XTAL_25_OUT XTAL X2 R735 WP# CE# SO TBT_EE_W P_N 3 SCK TBT_HOLD_N 7 HOLD# VSS 2 TBT_EE_DO 1 TBT_EE_CS_N 6 TBT_EE_CLK 3.3K_1%_04 SI TBT_EE_DI 3.3K_1%_04 3.3K_1%_04 3.3K_1%_04 VDD 5 OUT2_D1p OUT2_D1n [46] [46] OUT2_D2p OUT2_D2n [46] [46] OUT2_D3p OUT2_D3n [46] [46] OUT2_AUXp_SCL OUT2_AUXn_SDA 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 DPSNK1_ML0_P DPSNK1_ML0_N AB7 AC7 C587 C586 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 DPSNK1_ML1_P DPSNK1_ML1_N AB9 AC9 C585 C584 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 DPSNK1_ML2_P AB11 DPSNK1_ML2_N AC11 C583 C582 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 DPSNK1_ML3_P AB13 DPSNK1_ML3_N AC13 C978 C979 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 DPSNK1_AUX_P Y11 DPSNK1_AUX_N W11 AA2 [46] OUT2_HPD R667 100K_04 TBT_SNK0_DDC_CLK TBT_SNK0_DDC_DATA R692 100K_04 4 W 25Q80DV Y5 R4 AB15 AC15 C VCC3V3_S0_SYS TBT_HDMI_DDC_DATA TBT_HDMI_DDC_CLK R302 R299 *2.2K_04 *2.2K_04 TBT_SNK0_DDC_CLK TBT_SNK0_DDC_DATA RTD3_CIO_PW R_EN R664 R694 R325 *2.2K_04 *2.2K_04 *10K_04 AB17 AC17 VCC3V3_SX_SYS AB19 AC19 *0.1u_10V_X7R_04 5 C568 1 AB21 AC21 BUF_PLT_RST#_AR 4 VCC3V3_SX_SYS TBT_I2C_SDA R311 TBT_I2C_SCL R312 TBT_PCIe_W AKE_N R309 TBT_CIO_PLUG_EVENT_N R308 TBT_SLP_S3_N R331 TBT_BATLOW _N R326 TBTA_I2C_INT R745 TBTB_I2C_INT R328 RTD3_USB_PW R_EN RTD3_CIO_PW R_EN TBT_TMU_CLK_OUT TBT_FORCE_PW R OUT2_HPD TBTA_LSRX TBTA_LSTX TBTA_HPD TBT_SNK1_DDC_CLK SINK0_CFG1 TBTB_LSTX TBTB_LSRX TBTB_HPD DPSNK1_HPD R738 R327 R310 R728 R307 R348 R740 R698 R672 R686 R347 R741 R322 R669 100K_04 100K_04 100K_04 100K_04 100K_04 1M_04 1M_04 100K_04 100K_04 100K_04 1M_04 1M_04 100K_04 100K_04 TBT_TDI TBT_TMS TBT_TCK TBT_TDO R670 R684 R688 R680 *10K_04 *10K_04 *10K_04 *10K_04 [34,35,37,38,47,48] Y12 W12 3 R294 DPSNK1_HPD Y6 TBT_SNK1_DDC_CLK SINK0_CFG1 0_04 R687 14K_1%_04 Y8 N4 DPSNK_RBIAS Y18 TBT_TDI Y4 TBT_TMS V4 TBT_TCK T4 TBT_TDO W4 R721 4.75K_0.5%_04 +/-0.5% [45] [45] VCC3V3_LC D02A_0321_ℙ䓐 TBTA_HD2CA_1_P TBTA_HD2CA_1_N [45] [45] TBTA_HD2CA_0_P TBTA_HD2CA_0_N [45] [45] TBTA_CA2HD_0_P TBTA_CA2HD_0_N TBTA_DPSRC_AUX_P TBTA_DPSRC_AUX_N H6 J6 A15 B15 TBTA_CA2HD_1_P TBTA_CA2HD_1_N [45] [45] [44] [44] TBT_RBIAS TBT_RSENSE C1097 0.22u_10V_X5R_02 C1098 0.22u_10V_X5R_02 TBTA_TX1_P TBTA_TX1_N A17 B17 C629 C628 TBTA_TX0_P TBTA_TX0_N A19 B19 0.22u_10V_X5R_02 0.22u_10V_X5R_02 B21 A21 C1005 C998 0.1u_10V_X7R_04 0.1u_10V_X7R_04 TBTA_AUX_P Y15 TBTA_AUX_N W15 PERST_N PCIE_RBIAS DPSNK0_ML0_P DPSNK0_ML0_N DPSRC_ML0_P DPSRC_ML0_N DPSNK0_ML1_P DPSNK0_ML1_N DPSRC_ML1_P DPSRC_ML1_N DPSNK0_ML2_P DPSNK0_ML2_N DPSNK0_ML3_P DPSNK0_ML3_N DPSNK0_AUX_P DPSNK0_AUX_N DPSRC_ML2_P DPSRC_ML2_N DPSRC_ML3_P DPSRC_ML3_N DPSRC_AUX_P DPSRC_AUX_N DPSNK0_HPD DPSRC_HPD DPSNK0_DDC_CLK DPSNK0_DDC_DATA DPSRC_RBIAS DPSNK1_ML0_P DPSNK1_ML0_N DPSNK1_ML1_P DPSNK1_ML1_N DPSNK1_ML2_P DPSNK1_ML2_N DPSNK1_ML3_P DPSNK1_ML3_N DPSNK1_AUX_P DPSNK1_AUX_N DPSNK1_HPD DPSNK1_DDC_CLK DPSNK1_DDC_DATA GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6 TEST_EN TEST_PWR_GOOD DPSNK_RBIAS RESET_N TDI TMS TCK TDO XTAL_25_IN XTAL_25_OUT MISC EE_DI EE_DO EE_CS_N EE_CLK RBIAS RSENSE PA_RX1_P PA_RX1_N PB_RX1_P PB_RX1_N PA_TX1_P PA_TX1_N PB_TX1_P PB_TX1_N PA_TX0_P PA_TX0_N PB_TX0_P PB_TX0_N PA_RX0_P PA_RX0_N PA_DPSRC_AUX_P PA_DPSRC_AUX_N PB_RX0_P PB_RX0_N PB_DPSRC_AUX_P PB_DPSRC_AUX_N PB_USB2_D_P PB_USB2_D_N PB_LSTX PB_LSRX PB_DPSRC_HPD PB_USB2_RBIAS MONDC_SVR ATEST_P ATEST_N DEBUG USB2_ATEST 5 IF SOME OF GPIOs ARE NOT IN USE FOLLOW TABLE BELOW: E20 [44] TBTA_USB2_D_P GPIO | TERMINATION | Power Rail D20 PA_USB2_D_P [44] TBTA_USB2_D_N PA_USB2_D_N ---------------------------------------------------GPIO_0 | 10K PU | VCC3V3_LC TBTA_LSTX A5 [44] TBTA_LSTX TBTA_LSRX GPIO_1 | 10K PU | VCC3V3_LC A4 PA_LSTX [44] TBTA_LSRX TBTA_HPD M4 PA_LSRX GPIO_2 | 100K PD | [44] TBTA_HPD PA_DPSRC_HPD GPIO_3 | 100k PD | PA_USB2_RBIAS H19 R725 499_1%_04 GPIO_4 | 10K PU | VCC3V3_LC PA_USB2_RBIAS GPIO_5 | 10K PU | VCC3V3_LC AC23 GPIO_6 | 100K PD | DEBUG PINs: AB23 THERMDA GPIO_7 | 100K PD | THERMDA GPIO_8 | 100K PD | PIN | TERMINATION VCC3V3_SX_SYS V18 PCIE_ATEST POC_GPIO_0 | 10K PU | VCC3V3_TBT_SX ------------------------------POC_GPIO_1 | 10K PU | VCC3V3_TBT_SX MONDC_SVR | GND AC1 C1094 *0.1u_10V_X7R_04 TEST_EDM POC_GPIO_2 | 100K PD | MONDC_DPSNK_0 | GND POC_GPIO_3 | 100K PD | L15 MONDC_DPSNK_1 | GND FUSE_VQPS_64 1 N15 POC_GPIO_4 | 10K PU | VCC3V3_TBT_SX MONDC_DPSRC | GND FUSE_VQPS_128 TBT_SLP_S3_N 4 POC_GPIO_5 | 10K PU | VCC3V3_TBT_SX MONDC_CIO_0 | GND 2 C23 POC_GPIO_6 | 100K PD | MONDC_CIO_1 | GND C22 MONDC_CIO_0 TEST_EDM | GND MONDC_CIO_1 FUSE_VQPS_64 | GND FUSE_VQPS_128 | GND U54 ATEST_P/N | FLOATING U74AHC1G08G-AL5-R SUSB# [10,32,34,35,41,42,50,56] USB2_ATEST | FLOATING PCIE_ATEST | FLOATING 3 A BUF_PLT_RST# U14 *U74AHC1G08G-AL5-R TBT USB TYPE C B 2 2.2K_1%_04 2.2K_1%_04 10K_04 10K_04 10K_04 10K_04 10K_04 10K_04 PCIE_REFCLK_100_IN_P PCIE_REFCLK_100_IN_N PCIE_CLKREQ_N 5 4 3 MONDC_DPSNK_0 MONDC_DPSNK_1 MONDC_DPSRC U16A JHL6340 Y 0.22u_10V_X5R_02 0.22u_10V_X5R_02 K23 K22 PET2_P PET2_N C607 C610 0.22u_10V_X5R_02 0.22u_10V_X5R_02 F23 F22 PET3_P PET3_N C614 C615 0.22u_10V_X5R_02 0.22u_10V_X5R_02 L4 BUF_PLT_RST#_AR N16 PCIe_RBIAS R691 [30] [30] PCIE_RXP2_TBT PCIE_RXN2_TBT [30] [30] PCIE_RXP3_TBT PCIE_RXN3_TBT [30] [30] PCIE_RXP4_TBT PCIE_RXN4_TBT [30] [30] D 3.01K_1%_04 R2 R1 VCC3V3_SX_SYS N2 N1 TBT_PCIe_W AKE_N L2 L1 S D LAN_W AKEUP# [30,32,35,38,48] Q52 *2SK3018S3 J2 J1 Sheet 42 of 77 AR_TBT W19 Y19 G1 TBT_SRC_HPD N6 DPSRC_RBIAS U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1 TBT_I2C_SDA TBT_I2C_SDA [44] TBT_I2C_SCL TBT_I2C_SCL [44] TBT_EE_W P_N TBT_TMU_CLK_OUT TBT_PCIe_W AKE_N TBT_CIO_PLUG_EVENT_N R303 0_04 TBCIO_PLUG_EVENT [30] TBT_HDMI_DDC_DATA TBT_HDMI_DDC_CLK TBT_SRC_CFG1 TBTA_I2C_INT TBTA_I2C_INT [44] TBTB_I2C_INT RTD3_USB_PW R_EN TBT_FORCE_PW R R720 0_04 TBT_FRC_PW R [30] TBT_BATLOW _N TBT_SLP_S3_N R333 *0_04 SUSB# [10,32,34,35,41,42,50,56] RTD3_CIO_PW R_EN E1 TBT_TEST_EN R332 AB5 TBT_TEST_PW G R298 R717 F4 D22 D23 14K_1%_04 100_04 TBT_RESET_N AB3 AC4 AC3 AB4 C 100_04 TBT_XTAL_25_IN TBT_XTAL_25_OUT [44] NOTE: ASSEMBLE R1305, R1368 if DPSRC NOT IN USE TBT_EE_DI TBT_EE_DO TBT_EE_CS_N TBT_EE_CLK [44] [44] [44] [44] TBT_SRC_CFG1 TBT_SRC_HPD R306 R321 1M_04 1M_04 B B7 A7 A9 B9 A11 B11 A13 B13 Y16 W16 E19 D19 B4 B5 G2 F19 TBTB_LSTX TBTB_LSRX TBTB_HPD PB_USB2_RBIAS R730 499_1%_04 D6 A23 B23 [44] [43] [43,44] [43] E18 W13 A VCC3V3_FLASH VCC3V3_LC VCC3V3_SX_SYS VCC3V3_S0_SYS W18 AB2 Title [42] AR_TBT Size A3 Date: 2 PCIE_RXP1_TBT PCIE_RXN1_TBT CPU PCIE RX 0.22u_10V_X5R_02 0.22u_10V_X5R_02 C599 C602 CPU / Policy Manager R736 0.1u_10V_X7R_04 U51 8 [46] [46] TBT_CLKREQ#_N C589 C588 C597 C594 PET1_P PET1_N TBT USB TYPE C R733 DDI(MUX) R734 OUT2_D0p OUT2_D0n PCIE_TX3_P PCIE_TX3_N PET0_P PET0_N P23 P22 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 42 of 77 1 AR_TBT B - 43 B.Schematic Diagrams C1076 [46] [46] PCIE_RX3_P PCIE_RX3_N PCIE_TX2_P PCIE_TX2_N V23 V22 G [31] TBT_REFCLK_100_P [31] TBT_REFCLK_100_N [31] TBT_CLKREQ#_N VCC3V3_FLASH V19 T19 AC5 PCIE_RX2_P PCIE_RX2_N POC H23 H22 PCIE_TX1_P PCIE_TX1_N PCIe GEN3 PCIE_TXP4_TBT PCIE_TXN4_TBT PCIE_TX0_P PCIE_TX0_N PCIE_RX1_P PCIE_RX1_N SINK PORT 0 [30] [30] M23 M22 PCIE_RX0_P PCIE_RX0_N SOURCE PORT 0 PCIE_TXP3_TBT PCIE_TXN3_TBT T23 T22 LC GPIO [30] [30] Y23 Y22 SINK PORT 1 D PCIE_TXP2_TBT PCIE_TXN2_TBT POC GPIO 6p_50V_NPO_04 PCIE_TXP1_TBT PCIE_TXN1_TBT [30] [30] Misc 6p_50V_NPO_04 [30] [30] PORT B C625 FSX3L 25MHZ AR/PPS COMMON FLASH 1 TBT_XTAL_25_IN Port A 4 TBT PORTS 3 POC 1 CPU PCIE TX C624 2 2 NOTE: SNK0_DDC_data/clk ?connect to 2k PU only if SRC0 is connected and support HDMI (a.i HDMI or DP++ connector). Otherwise can be 100k PD. SNK1_DDC_data ?connect to 100k PD. If SRC0 support HDMI, connect as SNK0_CFG1 to GPU and/or appropriate AUX/DDC demux control SNK1_DDC_clk ?connect to 100k PD. Schematic Diagrams AR Power 5 4 3 VCC3V3_LC 2 1 VCC3V3_SX_SYS VCC3V3_S0_SYS VCC0V9_DP VCC3V3_S0 C1026 L8 L11 L12 M8 T11 T12 L6 M6 V11 V12 V13 D VCC0V9_PCIE C1042 C1030 C1034 C1041 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 B.Schematic Diagrams VCC0V9_USB C1029 C1039 1u_6.3V_X5R_04 1u_6.3V_X5R_04 M13 M15 M16 L19 N19 L18 M18 N18 R15 R16 VCC0V9_CIO Sheet 43 of 77 AR Power R8 R9 R11 R12 C1033 C1035 C1037 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 VCC3V3_ANA_PCIE VCC3V3_ANA_USB2 C1058 C C1066 1u_6.3V_X5R_04 1u_6.3V_X5R_04 PA70HS NOT SUPPORT TBT WAKE UP FOR MEDION R749 and R750 NOT STUFF. R293 and R291 STUFF. FOR ᷕ⿏ Q52 NOT STUFF. VCC3V3_SX_SYS >120 mil 3.3V R749 R750 0_06 0_06 R293 R291 *0_06 *0_06 R297 0_06 >120 mil 3.3VS VCC3V3_S0 >120 mil VCC3V3_S0_SYS L12 CPI160809UF-1R0M . B C634 C635 C638 1u_6.3V_X5R_04 47u_6.3V_X5R_08 47u_6.3V_X5R_08 A L16 J16 A6 A8 A10 A12 A14 A16 A18 A20 A22 B6 B8 B10 B12 B14 B16 B18 B20 B22 D8 D9 D11 D12 D13 D15 D16 D18 E8 E9 E11 E15 E16 E22 E23 F9 F16 F20 G22 G23 H1 H2 H12 H13 H15 H16 H20 J5 J18 J19 J20 J22 J23 K1 K2 L5 L20 L22 L23 M1 M2 M5 M19 M20 N5 N20 N22 N23 VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK VCC0P9_PCIE VCC0P9_PCIE VCC0P9_PCIE VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 VCC0P9_USB VCC0P9_USB VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR SVR_IND SVR_IND SVR_IND SVR_VSS SVR_VSS SVR_VSS C636 C637 C632 A2 A3 B3 D VCC0V9_SVR L9 M9 E12 E13 F11 F12 F13 F15 J9 C1083 C1079 C1054 C1040 C1090 C1091 C1078 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 TBT_SVR_IND C1 C2 D1 L10 XFL4012-601MEC PCB Footprint = XFL4012-2 C639 A1 B1 B2 C631 47u_6.3V_X5R_08 C626 47u_6.3V_X5R_08 47u_6.3V_X5R_08 SVR_VSS_GND VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F18 H18 J11 H11 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M11 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 C1086 C1085 10u_6.3V_X5R_04 10u_6.3V_X5R_04 C1088 B - 44 AR Power 4 3 C1064 1u_6.3V_X5R_04 1u_6.3V_X5R_04 C SVR_VSS_GND B [42] VCC3V3_LC [42,44] VCC3V3_SX_SYS [42] VCC3V3_S0_SYS [2,10,27,38,45,48,50,51,52,55,56] 3.3V [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,46,47,48,49,50,57,64] 3.3VS A Title [43] AR POW ER Size A3 Date: 5 C633 VCC0V9_LVR_OUT VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR_SENSE VCC3P3_ANA_PCIE VCC3P3_ANA_USB2 U16B JHL6340 Y C567 *1u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04 VCC0P9_SVR VCC0P9_SVR VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_SENSE VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA C1070 1u_6.3V_X5R_04 H9 1u_6.3V_X5R_04 VCC3P3A 1u_6.3V_X5R_04 F8 1u_6.3V_X5R_04 R13 1u_6.3V_X5R_04 VCC3P3_S0 1u_6.3V_X5R_04 C1071 1u_6.3V_X5R_04 1u_6.3V_X5R_04 VCC3P3_SX C1060 VCC C1055 GND C1014 R6 1u_6.3V_X5R_04 C1025 VCC3P3_LC 1u_6.3V_X5R_04 C1044 VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA C985 P1 P2 R5 R18 R19 R20 R22 R23 T1 T2 T5 T20 U22 U23 C986 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 1 43 of 77 Schematic Diagrams TPS65982ABZQZ 5 4 3 2 1 TBTA_VBUS VCC5V0_SYS C661 22u_6.3V_X5R_08 C1138 C657 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06 VCC1V8D_TBTA_LDO VCC1V8A_TBTA_LDO TBT TBT L13 HCB2012KF-800T80 TBT TBT D45 C658 0.1u_10V_X7R_04 TBT C1134 ACE_I2C_SDA2 R816 0_04 ACE_I2C_SCL2 R817 0_04 TBTA_I2C_IRQ2Z R820TBT *0_04 TBT TBTA_GPIO0 R771 *0_04 TBTA_ACE_GPIO0 SMD_VGA_THERM SMC_VGA_THERM A5 B5 B6 SMB_CLK_R TBTA_ACE_GPIO2 TBTA_ACE_GPIO3 [30] TBTA_ACE_GPIO7 TO AP SPI ROM [42] [42] [42] [42] [42] [42] R769 E2 F2 1M_04 A9 HV_GATE2 B9 A10 SENSEN B10 SENSEP A6 A7 A8 B7 H10 A11 B11 C11 D11 PP_5V0 PP_5V0 PP_5V0 PP_5V0 PP_CABLE A2 E1 LDO_BMC K1 LDO_1V8A LDO_1V8D H1 B1 VDDIO VIN_3V3 [45] [45] 3A 3A GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 Primary TBTA_MRESET TBTA_HRESET B TBTA_DPSRC_AUX_P TBTA_DPSRC_AUX_N VCC3V3_FLASH R390 R385 TBT R380 TBT R376 R766 TBT TBT TBT R767 R784 TBT TBT VCC3V3_SX_SYS 5V L4 K4 100K_04 TBTA_DIG_AUD_P L3 100K_04 TBTA_DIG_AUD_N K3 100K_04 TBTA_DEBUG1 100K_04 TBTA_DEBUG2 100K_04 L2 K2 J1 J2 100K_04 100K_04 F10 TBTA_ROSC R775 15K_0.1%_04 R774 *10K_04 TBTA_GPIO0 R786 *10K_04 TBTA_GPIO7 E11 D6 0.1% G2 A5 [45] TBTA_CC1_J [45] [45] TBTA_USB2_TP_J TBTA_USB2_TN_J A6 A7 A8 TBTA_SBU1_J A9 C1130 1u_10V_X5R_02 A10 A11 TBTA_CA2HD_1_N_R TBTA_CA2HD_1_P_R A12 C645 1u_6.3V_X5R_04 GND GND TX0_P TX0_N RX0_P RX0_N VBUS VBUS CC1 SBU2 USB2_P_T USB2_N_T CC2 VBUS VBUS RX1_N RX1_P TX1_N TX1_P GND B11 B10 TBTA_CA2HD_0_P_R TBTA_CA2HD_0_N_R B9 C1129 1u_10V_X5R_02 B8 TBTA_SBU2_J B7 B6 TBTA_USB2_BN_J TBTA_USB2_BP_J B5 B4 TBTA_CC2_J [45] [45] [45] [45] C1131 1u_10V_X5R_02 B3 B2 [45] [45] EMI_GND EMI_GND TBTA_HD2CA_1_N_R TBTA_HD2CA_1_P_R [45] [45] B1 VCC3V3_FLASH C Sheet 44 of 77 TPS65982ABZQZ TBT EMR2 EMR1 C1127 USB_RP_P USB_RP_N GND B12 G1 C_USB_TP C_USB_TN SPI_CLK SPI_MOSI SPI_MISO SPI_SS_Z USB2_N_B USB2_P_B SBU1 H2 VOUT_3V3 LDO_3V3 C_USB_BP C_USB_BN K6 TBTA_USB2_P_T L6 TBTA_USB2_N_T TBTA_USB2_P_T TBTA_USB2_N_T [45] [45] 10u_6.3V_X5R_04 TBT K7 TBTA_USB2_P_B L7 TBTA_USB2_N_B TBTA_USB2_P_B TBTA_USB2_N_B [45] [45] 0_04 0_04 EMI_GND UART_TX UART_RX F4 G4 SWD_DAT SWD_CLK R404 100K_04 R790 *0_04 R779TBT *0_04 R780 100K_04 TBT [42] TBTA_LSTX [42] TBTA_LSRX [45] [45] H11 J10 J11 K11 VBUS VBUS VBUS VBUS A4 C1128 1u_10V_X5R_02 EMI_GND I2C_SDA2 I2C_SCL2 I2C_IRQ2Z A2 A3 TBTA_HD2CA_0_P_R TBTA_HD2CA_0_N_R [45] M_RESET HRESET RPD_G1 RPD_G2 DEBUG3 DEBUG4 C_SBU1 DEBUG1 DEBUG2 C_SBU2 TBT VCC3V3_FLASH E4 D5 TBTA_DBG_CTL1 TBTA_DBG_CTL2 K8 TBTA_SBU1 L8 TBTA_SBU2 F11 R402 RESETZ BUSPOWERZ R_OSC U18 TPS65982ABZQZ Y TBT [45] 220p_50V_NPO_04 WHEN CONNECT BUSPOWERZ TO GND, 220p_50V_NPO_04 CONNECT ALSO RPD_Gn to C_CCn TBT R791 AUX_P AUX_N TBTA_CC1 C654 C655 K9 K10 DEBUG_CTL1 DEBUG_CTL2 LSX_R2P LSX_P2R TBTA_CC1 TBTA_CC2 L9 L10 C_CC1 C_CC2 嶇biosec天pin [42] [42] L5 K5 TBTA_USB2_D_P TBTA_USB2_D_N TBT [30] [35] A3 B4 A4 B3 TBT_EE_CLK TBT_EE_DI TBT_EE_DO TBT_EE_CS_N TBT A1 TBT TBT EMI_GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND [30] [30] C R789 *0_04 R403 *0_04 [42] TBTA_HPD TBTA_ACE_GPIO6 R782 *0_04 B2 C2 D10 G11 C10 E10 G10 TBTA_GPIO7 D7 H6 I2C_SDA1 I2C_SCL1 I2C_IRQ1Z 1u_25V_X5R_06 TBT H7 SS 0_04 TBTA_CC2 [45] R773 10K_04 R783 10K_04 TBT TBT B TBTA_SBU1 [45] TBTA_SBU2 [45] *3.3K_04 NOTE: PAY ATTENTION SYMBOL OF TPS65982 BASED ON DS R0.92 AND MIGHT BE FUTURE CHANGES. VCC3V3_SX_SYS TBT_RESET_N [42] TBT TBTA_SS C1132 0.22u_10V_X5R_04 D8 E5 E6 E7 E8 F5 F6 F7 F8 G5 G6 G7 G8 H4 H5 H8 L1 [30] I2C_ADDR GND GND [26,35,36] [26,35,36] [3,8,9,32] R819 SMB_DATA_R 1u_6.3V_X5R_04 A1 B8 [3,8,9,32] D1 D2 C1 TBT_I2C_SDA TBT TBT_I2C_SCL TBTA_I2C_INT [42] [42] *0_04 [42] 10u_6.3V_X5R_04 TBT C644 D J_TYPEC1 DX07S024JJ2 PCB Footprint = DX07S024JJ2 P/N = 6-21-B4K20-024 TBT TBT VCC5V0_SYS 3A A A [45] TBTA_VBUS [42] VCC3V3_FLASH [42,43] VCC3V3_SX_SYS [39,45,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V Title [44] TPS65982ABZQZ TYPEC Size A3 Date: 5 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 44 of 77 1 TPS65982ABZQZ B - 45 B.Schematic Diagrams VCC3V3_SX_SYS R384 *3.3K_1%_04 ACE_I2C_SDA2 R379 *3.3K_1%_04 ACE_I2C_SCL2 R389 *10K_04 TBTA_I2C_IRQ2Z C653 R401 10K_04 TBTA_ACE_GPIO6 10u_6.3V_X5R_04 TBT TBT R371 0_04 F1 PP_HV PP_HV PP_HV PP_HV VCC3V3_SX_SYS R396 TBT A close to pin,1/14 C656 TBT HV_GATE1 2.2u_6.3V_X5R_04 R392 C649 2.2u_6.3V_X5R_04 TBT 0_04 C650 2.2u_6.3V_X5R_04 TBT VCC_HV_SYS C648 D C 0_04 TBT 22u_6.3V_X5R_08 80Ohm, 0.01Ohm DCR, 8A Idc CGND CGND CGND CGND C1137 GND1 GND2 GND3 GND4 TBTA_LDO_BMC C1135 CSOD140SH C1136 Schematic Diagrams USB 3.0 Type C 5 4 3 2 1 Colay Near J_TYPEC1 Near J_TYPEC1 USB3.0 From ASM 1543 TBTA_HD2CA_0_N_R TBTA_HD2CA_0_P_R 0_1%_02 TBT 0_1%_02 TBT [42] [42] R768 R770 TBTA_HD2CA_1_N TBTA_HD2CA_1_P 0_1%_02 TBT 0_1%_02 TBT TBTA_CA2HD_1_N_R TBTA_CA2HD_1_P_R 0_1%_02 TBT 0_1%_02 TBT TBTA_HD2CA_1_N_R TBTA_HD2CA_1_P_R 2 R393 R397 TBTA_CA2HD_1_N TBTA_CA2HD_1_P 1 D50 TVUDF1004AD0 TBTA_SBU2_R TBTA_SBU1_R 1 D46 CPDZC5V0SPC-HF [42] [42] D44 CPDZC5V0SPC-HF RX1 C 2 TBTA_HD2CA_1_N_R TBTA_HD2CA_1_P_R TX0 CC 0_04 W /O TBT TBTA_CC2_R 0_04 W /O TBT TBTA_CC1_R TBTA_CC2 TBTA_CC1 R394 R391 0_04 TBT 0_04 TBT TBTA_CC2_R TBTA_CC1_R R400 R399 0_04 TBT 0_04 TBT TBTA_SBU2_R TBTA_SBU1_R [44] [44] TBTA_SBU2 TBTA_SBU1 [44] [44] USB_PN2 [30] USB_PP2 USB2.0 From PCH [44] [44] L45 0_04 W /O TBT TBTA_USB2_TN_R 0_04 W /O TBT TBTA_USB2_TP_R 1 [44] [44] TBTA_SBU2_J TBTA_SBU1_J TBTA_CC2_J TBTA_CC1_J [44] [44] [44] [44] Colay R776 1 2 R772 *W CM2012F2S-161T03-short 4 L46 3 2 4 3 *W CM2012F2S-161T03-short CHECK ⊭墅 D 1 2 3 4 5 Near J_TYPEC1 USB2.0 [30] 10 9 8 7 6 TBTA_CC2_R TBTA_CC1_R From TBT USB2.0 D49 TVUDF1004AD0 R781 0_04 W /O TBT TBTA_USB2_BN_R R785 0_04 W /O TBT TBTA_USB2_BP_R TBTA_USB2_BP_R TBTA_USB2_BN_R 1 R373 R370 TBTA_HD2CA_0_N TBTA_HD2CA_0_P Colay R788 R787 ASM1543_CC2 ASM1543_CC1 From ASM1543 [44] [44] TBTA_CA2HD_0_N_R TBTA_CA2HD_0_P_R 2 [42] [42] [45] [45] CHECK ⊭墅 TBTA_CA2HD_0_N_R TBTA_CA2HD_0_P_R 0_1%_02 TBT 0_1%_02 TBT D47 CPDZC5V0SPC-HF Sheet 45 of 77 USB 3.0 Typce C R764 R761 TBTA_CA2HD_0_N TBTA_CA2HD_0_P 1 [42] [42] CC 6-24-40001-010 ESD DIODE 15KV/0.2PF CPDZC5V0SPC-HF SMD0201 From TBT RX0 1 USB3.1 D48 CPDZC5V0SPC-HF TBTA_USB2_N_T TBTA_USB2_P_T TBTA_USB2_TN_R TBTA_USB2_TP_R R378 R375 0_04 TBT 0_04 TBT TBTA_USB2_TN_R TBTA_USB2_TP_R R383 R388 0_04 TBT 0_04 TBT TBTA_USB2_BN_R TBTA_USB2_BP_R 10 9 8 7 6 1 2 3 4 5 TBTA_USB2_BP_J TBTA_USB2_BN_J [44] [44] TBTA_USB2_TN_J TBTA_USB2_TP_J [44] [44] C USB2.0 From TBT [44] TBTA_USB2_N_B [44] TBTA_USB2_P_B TX1 kai_0103 OPTION USB3.1㗪 㗪ᶵᶲẞ PORT1 close to connector 3.3V_MUX 5V TBTA_VBUS U19 ASM1543_VCONN_EN ASM1543_PW R_EN ASM1543_MODE_SEL 2 CC_RDY# MC_RDY# HC_RDY# 3 C660 VIN1 VIN2 VOUT1 VOUT2 VOUT3 6 7 8 100 MIL C659 0.1u_10V_X7R_04 33 32 31 30 29 28 27 26 25 10u_6.3V_X5R_06 B USB3.0 From PCH [32] [32] USB3_RXN3 USB3_RXP3 [32] [32] USB3_TXN3 USB3_TXP3 ASM1543_I_SEL0 USB3_RXN3 USB3_RXP3 3.3V_MUX ASM1543_I_SEL1 1 2 3 4 5 6 7 8 I_SEL0/MUX_EN# DA_a DA_b GNDA1 VCC1 DB_a DB_b I_SEL1/MUX_SEL pin1 ASM1543 W /O TBT pin33 REXT DFP_CC2 CC2 VCONN CC1 DFP_CC1 ROLE_SEL GNDA2 GND MODE_SEL PWR_EN VCONN_EN VCC2 CC_RDY# MC_RDY# HC_RDY# GNDA3 U17 GND 4 To TYPE-C CON DA_a1 DA_b1 DB_a1 DB_b1 DA_a2 DA_b2 DB_a2 DB_b2 24 23 22 21 20 19 18 17 A_URXN_SW 1 A_URXP_SW 1 A_UTXN_SW 1 A_UTXP_SW 1 A_URXN_SW 2 A_URXP_SW 2 A_UTXN_SW 2 A_UTXP_SW 2 3.3V_MUX A_URXN_SW 1 [45] A_URXP_SW 1 [45] A_UTXN_SW 1 [45] A_UTXP_SW 1 [45] A_URXN_SW 2 [45] A_URXP_SW 2 [45] A_UTXN_SW 2 [45] A_UTXP_SW 2 [45] R793 4.7K_04 W /O TBT [35,48,50,54] DD_ON R794 ASM1543_REXT ASM1543_ROLE_SEL 5V_MUX To TYPE-C CON ASM1543_CC1 ASM1543_CC2 3.3V_MUX R356 C647 0.1u_10V_X7R_04 pin#5 C652 0.1u_10V_X7R_04 pin#29 C651 1u_6.3V_X5R_04 C641 1u_6.3V_X5R_04 pin#12 C640 10u_6.3V_X5R_06 pin#12 [45] [45] 2.2K_04 2.2K_04 2.2K_04 10K_04 10K_04 R777 R778 R367 R386 R362 R361 *2.2K_04 *2.2K_04 *2.2K_04 *10K_04 *10K_04 12.1K_1%_04 W /O TBT R372 R368 R377 R374 *1M_04 *1M_04 *1M_04 *1M_04 W /O TBT W /O TBT W /O TBT W /O TBT W /O TBT B - 46 USB 3.0 Type C USB3_TXN3 USB3_TXP3 USB3_RXN3 USB3_RXP3 A 0_06 5V 0_06 3 2 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [45] USB3.0 co-lay TYPE C Size A3 Document Number Date: 4 ASM1543_VCONN_EN ASM1543_MODE_SEL ASM1543_ROLE_SEL ASM1543_I_SEL0 ASM1543_I_SEL1 ASM1543_REXT Near to IC [44] TBTA_VBUS [39,44,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V [2,10,27,38,43,48,50,51,52,55,56] 3.3V 5 B ASM1543_VCONN_EN ASM1543_MODE_SEL ASM1543_ROLE_SEL ASM1543_I_SEL0 ASM1543_I_SEL1 R382 R387 R363 R381 R364 3.3V 5V_MUX R405 5 *0_04 5V_MUX 3.3V_MUX OC# 3.3V_MUX Thermal and GND via hole A EN 1 uP7549PRA8-25 3.3A W /O TBT ASM1543_PW R_EN 9 10 11 12 13 14 15 16 B.Schematic Diagrams TX1 2 1 TBTA_HD2CA_1_N_R TBTA_HD2CA_1_P_R 0.1u_6.3V_X5R_02 W /O TBT 0.1u_6.3V_X5R_02 W /O TBT D18 CPDZC5V0SPC-HF C1125 C1126 A_UTXN_SW 2 A_UTXP_SW 2 TBTA_CA2HD_1_N_R TBTA_CA2HD_1_P_R 0_1%_02 W /O TBT 0_1%_02 W /O TBT D19 CPDZC5V0SPC-HF R395 R398 A_URXN_SW 2 A_URXP_SW 2 D17 CPDZC5V0SPC-HF [45] [45] TBTA_HD2CA_0_N_R TBTA_HD2CA_0_P_R [44] [44] D16 CPDZC5V0SPC-HF TX0 RX1 [45] [45] 0.1u_6.3V_X5R_02 W /O TBT 0.1u_6.3V_X5R_02 W /O TBT TBTA_HD2CA_0_N_R TBTA_HD2CA_0_P_R 1 C646 C643 A_UTXN_SW 1 A_UTXP_SW 1 [44] [44] 2 [45] [45] TBTA_CA2HD_1_N_R TBTA_CA2HD_1_P_R 1 D TBTA_CA2HD_0_N_R TBTA_CA2HD_0_P_R 2 0_1%_02 W /O TBT 0_1%_02 W /O TBT 2 A_URXN_SW 1 A_URXP_SW 1 2 D12 R765 R762 RX0 [45] [45] Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 45 of 77 Schematic Diagrams PS8338B 5 4 3 Levels Input: L: Low H: High M: VDD33/2, connect both pull-up and pull-down resistors 3.3VS 3.3VS PSPEQ R245 R246 *4.7K_04 *4.7K_04 PI0 R604 *4.7K_04 3 2 PC10 R608 PC20 Automatic EQ disable; Internal pull down at ~150K ohm, 3.3V IO L: Automatic EQ enable (default) H: Automatic EQ disable PI1 D PC11 Auto test enable; Internal pull down at ~150K ohm, 3.3V I/O. L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable *4.7K_04 R253 R600 Chip operational mode configuration; Internal pull down at ~150K ohm, 3.3V I/O. L: Control switching mode (default) H: Automatic switching mode *4.7K_04 *4.7K_04 R272 R613 3.3VS 3.3VS PSCFG0 1 3.3VS Programmable input equalization levels; Internal pull down at ~150K㫉, 3.3V I/O. L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2 PC21 AUX interception disable for Port y (y = 1, 2). Internal pull down at ~150K㫉, 9,2 L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mV and 0dB M: AUX interception disable, driver output with fixed 400mV and 0dB *4.7K_04 *4.7K_04 R280 *4.7K_04 R621 *4.7K_04 R276 *4.7K_04 R616 *4.7K_04 R284 *4.7K_04 R624 *4.7K_04 Output swing adjustment for Port y (y = 1, 2). Internal pull down at ~150K㫉, 9,2 L: default H: +20% M: -16.7% D 3.3VS *4.7K_04 60 59 58 57 56 55 54 53 52 51 EPAD wey_0411 CO-LAY W/ TBT ᶲẞ MDP_E0 MDP_E#0 R254 R255 0_04 0_04 MDP_E1 MDP_E#1 R256 R257 0_04 0_04 MDP_E2 MDP_E#2 R258 R259 0_04 0_04 MDP_E3 MDP_E#3 R260 R261 0_04 0_04 MDP_E0_R [11] MDP_E#0_R [11] MDP_E1_R [11] MDP_E#1_R [11] MDP_E2_R [11] MDP_E#2_R [11] MDP_E3_R [11] MDP_E#3_R [11] [25] MDP_E0 [25] MDP_E#0 [25] MDP_E1 [25] MDP_E#1 [25] [25] MDP_E2 MDP_E#2 [25] [25] [31] MDP_E3 MDP_E#3 IN_CA_DET C500 0.1u_10V_X7R_04 C900 0.1u_10V_X7R_04 C899 0.1u_10V_X7R_04 C898 C897 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C896 C895 0.1u_10V_X7R_04 0.1u_10V_X7R_04 C894 C893 0.1u_10V_X7R_04 0.1u_10V_X7R_04 PS8338B_SW C892 PS8338B OUT1_D0p OUT1_D0n OUT1_HPD OUT1_D1p OUT1_D1n OUT1_D2p OUT1_D2n OUT1_CA_DET OUT1_D3p OUT1_D3n OUT2_D0p OUT2_D0n OUT2_HPD OUT2_D1p OUT2_D1n OUT2_D2p OUT2_D2n OUT2_CA_DET OUT2_D3p OUT2_D3n R607 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 21 22 23 24 25 26 27 28 29 30 2.2u_6.3V_X5R_04 PI1/SCL_CTL I2C_CTL_EN IN_HPD IN_CA_DET VDD33 IN_D0p IN_D0n PEQ IN_D1p IN_D1n GND IN_D2p IN_D2n PD IN_D3p IN_D3n CEXT SW GND REXT VDD33 IN_DDC_SCL IN_DDC_SDA IN_AUXp IN_AUXn OUT1_AUXp_SCL OUT1_AUXn_SDA OUT2_AUXp_SCL OUT2_AUXn_SDA VDD33 1 2 3 4 5 3.3VS IN_D0p 6 IN_D0n 7 8 PSPEQ IN_D1p 9 IN_D1n 10 11 IN_D2p 12 IN_D2n 13 14 8338PD IN_D3p 15 IN_D3n 16 17 PS8338B_SW 18 19 20 PI1 [11,26,32] MDP_E_HPD [11] IN_CA_DET C925 0.1u_10V_X7R_04 [34] PS8338B_PCH PS8338B_PCH R599 *0_04 3.3VS 8338PD C520 0.1u_10V_X7R_04 NV3V3 NV3V3 NV3V3 CO-LAY NV TO DP ㇵᶲẞ OUT2_D3p OUT2_D3n C921 R623 0.01u_50V_X7R_04 100K_04 OUT2_AUXn_SDA OUT2_AUXp_SCL R830 [42] [42] 100K_04 0_04 C522 0.1u_10V_X7R_04 IN_AUXp 0_04 C538 0.1u_10V_X7R_04 IN_AUXn R823 4.7K_04 R821 4.7K_04 R822 4.7K_04 B D MDP_E_AUX#_SDA B TBT [42] [42] S TBT Hybrid DDC/AUX G AO3415 DEFAULT:LOW Q66 2SK3018S3 G IN_CA_DET G Q65 OUT1_AUXn_SDA OUT1_AUXp_SCL [11] [11] D MUX_AUXP MUX_AUXN GND D Q44 AO3415 S [11,25] R831 TO TBT Sheet 46 of 77 PS8338B R620 S MDP_E_AUX_SCL C 3.3VS 冯R828嶇R839 CO-LAY [11,25] TO DP 3.3VS MUX_AUXP MUX_AUXN IN_AUXp IN_AUXn 4.99K_1%_04 PD PIN: L:Normal operation(default) H:Chip power dow OUT1_D0p [11] OUT1_D0n [11] OUT1_HPD [11] OUT1_D1p [11] OUT1_D1n [11] OUT1_D2p [11] OUT1_D2n [11] OUT1_CA_DET [11] OUT1_D3p [11] OUT1_D3n [11] OUT2_D0p [42] OUT2_D0n [42] OUT2_HPD [42] OUT2_D1p [42] OUT2_D1n [42] OUT2_D2p [42] OUT2_D2n [42] DESIGN NOTE:CFG1 Configuration pin for auto test and input offset cancellation,3.3V IO, internal pull up at 150K H: default, auto test disable and input offset cancellation enable L: auto test enable and input offset cancellation enable M: auto test disable and input offset cancellation disable A DESIGN NOTE:CFG0 DESIGN NOTE:PEQ Configuration pin for automatic EQ and Aux interception; Internal pull down at 150Kohm,3.3V I/O A Programmalbe input equalization levels;internal pull down at 150k ,3.3v I/O L: default, LEQ, compensate channel loss up to 12dB at HBR2 L: default, automatic EQ enable and Aux interception enable H: HEQ, compensate channel loss up to 15dB at HBR2 H: automatic EQ disable and AUX interception enable M:LLEQ, compensate channel loss up to 5dB at HBR2 Title [46] TBT_DP(PS8338B) [11,12,13,14,26,52,53,61,62] [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,47,48,49,50,57,64] M: automatic EQ disable and AUX interception disable,no pre-emphasis, 600mVpp swing 5 NV3V3 3.3VS Size A3 Date: 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 46 of 77 1 PS8338B B - 47 B.Schematic Diagrams Port switching control or priority configuration; Internal pull down at ~150K ohm, 3.3V I/O. L: Port1 is selected or with higher priority (default) H: Port2 is selected or with higher priority C 61 U39 PC10 PC11 PC20 PC21 PI0 PSCFG0 C907 0.01u_50V_X7R_04 *4.7K_04 R818 PI0/SDA_CTL CFG0 CFG1 VDD33 PC10 PC11 PC20 PC21 GND VDD33 PS8338B_SW R603 3.3VS 3.3VS 3.3VS Schematic Diagrams TPM, CCD, TP 5 3 2 GPIO H: W / TPM (ᶲ R222 ) L: W/O TPM (ᶲ R221) TPM_DET R724 0_04 R710 C1114 㲐シPCLK_TPM⤪㚱ᷚ暣旣㚱ᶲTPM㗪暨⺢BOM PCLK_TPM [32,35] LPC_FRAME# [34,35,37,38,42,48] BUF_PLT_RST# [32,35] 21 BUF_PLT_RST# LRESET# SERIRQ C1115 C1073 C1074 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 PIN10 PP GPIO PIN19 1u_6.3V_X5R_04 C1059 0.1u_10V_X7R_04 TP_DATA TP_CLK TP_DATA [35] TP_CLK [35] TP_SMB_DAT TP_SMB_CLK R709 C1053 10K_04 10K_04 *10u_6.3V_X5R_06 C1067 C1068 47p_50V_NPO_04 47p_50V_NPO_04 D 3.3VS FPC0502-6AW -S-HF fp225h-006xxxm_R 6-20-94K30-106 PIN24 TPM_GPIO 6 R352 R346 2.2K_04 2.2K_04 Q27A MTDK3S6R 1 TP_SMB_CLK 6 Q27B MTDK3S6R 4 TP_SMB_DAT SMB_CLK [32,39,55] S BUF_PLT_RST# R758 *0_04 SMBUS address: 0x2C 3 D 4 11 18 25 G GND_1 GND_2 GND_3 GND_4 SLB9665TT_5.51 SMB_DATA [32,39,55] M9 *M-MARK LRESET# H35 *H7_0B6_0D3_7 5/23 ᾖ㓡TPM FW䇰㛔炻冲㕁嘇DISABLE 6-03-09655-0H1 C C1065 R708 TP_CLK TP_DATA D NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 1 2 3 4 5 6 3.3VS LFRAME# LRESET#_1 LRESET#_2 SERIRQ 7 J_TP1 PIN5 5VS S Sheet 47 of 77 TPM, CCD, TP 5 10 19 24 TPM LCLK 22 16 9 27 1 2 3 8 12 13 14 15 28 4.7K_04 VDD1 VDD2 VDD3 VDD4 3.3VS G B.Schematic Diagrams TPM_PP R757 LAD0 LAD1 LAD2 LAD3 *0_04 5 [32] 26 23 20 17 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 3.3VS 0.1u_10V_X7R_04 U52 [32,35] [32,35] [32,35] [32,35] TP_VCC TP_VCC [34] R221 100K_04 W /O TPM D 1 FOR TP 2 R222 100K_04 TPM 4 SLB9665TT(SLB9660 䚠⎴)& NPCT650 COLAY 3.3VS M10 *M-MARK M11 *M-MARK M12 *M-MARK M14 *M-MARK M16 *M-MARK M1 *M-MARK H13 H27 H12 H23 H19 H5 H4 H3 H26 *H8_0D3_7 *H8_0D2_8 *H8_0D2_8 *H8_0D2_8 *H8_0D2_8 *H8_0D2_8 *H8_0D2_8 *H8_0D2_8 *u12_0x10_2b10_0d6_7 C LPC_SIRQ & PM_CLKRUN# 䡢娵PCH䪗 䪗暨PULL HIGH M13 *M-MARK H10 H20 H42 H30 *H8_0D3_7 *H8_0D3_7 *H6_0D2_8 *H6_0D2_8 CCD H36 H34 H24 *H7_0B6_0D3_7 *H7_0B6_0D3_7 *H8_0D2_8 ⬠溆 1A 3.3VS CCD_PW R U20 4 5 C663 VIN VIN VOUT EN GND 1 H28 H2 H29 H1 *C111D111N *C111D111N *C111D111N *C111D111N 48 mil 1A H6 H8 H7 H17 H22 H21 H16 H9 *H6_3D4_4 *H6_3D4_4 *H6_3D4_4 *H6_3D4_4 *H6_3D4_4 *H6_3D4_4 *H6_3D4_4 *H6_3D4_4 C662 1u_6.3V_X5R_04 CCD_EN3 2 2.2u_6.3V_X5R_04 UP7553PMA5-25 kai_1214 M-SOT23-5 [35] CCD_EN From KBC default HI Port 9 B [30] USB_PN9 [30] USB_PP9 C1139 L14 1 MIC_DATA MIC_CLK B 2 4 3 *W CM2012F2S-SHORT C1140 [39] [39] H18 H14 H15 H11 *H9_5D6_0 *H9_5D6_0 *H9_5D6_0 *H9_5D6_0 47p_50V_NPO_04 L15 HCB1005KF-121T20 1 2 1 2 C673 HCB1005KF-121T20 L16 C677 J_CCD1 47p_50V_NPO_04 47p_50V_NPO_04 MIC_DATA_L MIC_CLK_L 3.3VS 47p_50V_NPO_04 1 2 3 4 5 6 7 8 H33 *H8_0D2_8 H38 H40 H39 *H7_0B6_0D3_7 *H7_0B6_0D3_7 *H7_0B6_0D3_7 H31 *H7_0B6_0D3_2 H25 *H9_8D2_8 85204-08001 H43 H44 *H7_0B6_0D3_7 *H7_0B6_0D3_7 BEAD & CAP FOR EMI MAIN: 6-20-44A00-108 2ND: 6-21-C3A00-108 [10,11,12,13,36,39,40,41,48,49,50,61,62,63,64] [2,10,27,38,43,45,48,50,51,52,55,56] [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,48,49,50,57,64] [39,44,45,48,49,50,51,52,53,54,55,56,57,58,59,63] A 5VS 3.3V 3.3VS 5V A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [47] TPM, CCD, TP Size Document Number SCHEMATIC1 A3 Date: 5 B - 48 4 3 2 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 47 of 77 Schematic Diagrams Connectors 5 4 LED BOARD D *0.01u_16V_X7R_04 LED_ACIN [35] LED_PW R [35] LED_BAT_CHG [35] LED_BAT_FULL [35] LED_NUM# [35] LED_CAP# [35] LED_SCROLL# [35] AIRPLAN_LED# [35] 2 J_LAN1 3.3VS [31] J_LAN2 FP238BH- 024S10M 0.1u_10V_X7R_04 [3,10,26,32] 3.3VS VDD3 3.3VS 3.3VS 5 婳EC PIN24復↢ầSSD LED≽ἄ䘬㊯䣢炻德忶AP忂䞍BIOS ⛐⏲䞍EC VDD3 1 EC_SSD_LED# 4 2 [35] PCH_SATAHDD_LED# U47 74AHC1G08GW [30] [30] C537 [31] USB_PN6 USB_PP6 USB_PN4 USB_PP4 0.1u_10V_X7R_04 D36 2 M2M_SSD_LED#R C 3 [30] [30] ↢≽ἄ 3 A 1 M2M_SSD_LED#R2 [35,45,50,54] [31] [31] [30,32,35,38,42] [34,35,37,38,42,47] [37] [37] C BAT54AN3 DD_ON LAN_CLKREQ# SD40_CLKREQ# LAN_W AKEUP# BUF_PLT_RST# [50,55] DD_ON# [31] CLK_PCIE_GLAN# [31] CLK_PCIE_GLAN [30] [30] [30] [30] PCIE_TXN5_GLAN PCIE_TXP5_GLAN PCIE_RXN5_GLAN PCIE_RXP5_GLAN [31] CLK_PCIE_SD40# [31] CLK_PCIE_SD40 [30] [30] PCIE_TXN6_SD40 PCIE_TXP6_SD40 [30] [30] PCIE_RXN6_SD40 PCIE_RXP6_SD40 26 25 [32] [32] USB3_TXN6 USB3_TXP6 [32] [32] USB3_RXN6 USB3_RXP6 [32] [32] USB3_TXN4 USB3_TXP4 [32] [32] USB3_RXN4 USB3_RXP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D GND5 GND4 GND3 GND2 GND1 GND5 GND4 GND3 GND2 GND1 LVDFH-03008-TP00+ PCB Footprint = lvdfh-030xx-tx00 current = 0.3A C USB BOARD CONN C Sheet 48 of 77 Connectors 5V J_USB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AUDIO BOARD CONN 3.3V FPC0502-16AW -S-HF 月役conn㒢㓦 5VS DD_ON# USB_PP1 USB_PN1 USB3_RXN1 USB3_RXP1 USB_PP1 USB_PN1 [32] [32] USB3_TXN1 USB3_TXP1 [32] [32] USB_PN5 USB_PP5 USB3_RXP5 USB3_RXN5 USB3_TXN5 USB3_TXP5 [30] [30] USB3_RXN1 USB3_RXP1 USB3_TXN1 USB3_TXP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 USB_PN5 USB_PP5 [30] [30] USB3_RXP5 USB3_RXN5 [32] [32] USB3_TXN5 USB3_TXP5 [32] [32] L48 MIC1_R_M [39] MIC1_L_M [39] JD_SENSEA [39] JD_SENSEB [39] SIDE_R [39] SIDE_L .FCM1005KF-121T03 SPDIFO [39] EMC1 100p_50V_NPO_04 GND alway ᶲẞ,close to J_AUDIO2 [39] HEADPHONE-R [39] HP_JSGND [39] HEADPHONE-L [39] B J_AUDIO1 AUDG FP225H-030S10M PCB Footprint = fp225h-030gxxm GND FP POWER BTN BOARD CONN 3.3VS J_FP1 3.3VS J_BTN1 SIM BOARD CONN [50] M_BTN# J_SIM1 UIM_PW R SIM_DET UIM_RST UIM_CLK UIM_DATA J_BTN1 1 NC1 NC2 4 [38] 30mil .FCM1005KF-121T03 USB_PN7 USB_PP7 [30] [30] A MAIN: 6-20-94A40-004 2ND: 6-20-94A60-004 SIM_DET [38] UIM_RST [38] UIM_CLK [38] UIM_DATA [38] [11,12,13,14,26,46,52,53,61,62] [39,44,45,49,50,51,52,53,54,55,56,57,58,59,63] [2,10,27,38,43,45,50,51,52,55,56] [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,49,50,57,64] [39,44,45,49,50,51,52,53,54,55,56,57,58,59,63] [10,11,12,13,36,39,40,41,47,49,50,61,62,63,64] [5,26,30,31,32,33,34,35,37,38,49,50,51,52,53,54,56,59,60] [10,35,39,50,53,54,55,56,57,58,59,60] FP225H-008S11M fp225h-008gxxxm_r NV3V3 VDD5 3.3V 3.3VS 5V 5VS VDD3 VIN ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 5 L40 FPC0502-6AW -S-HF fp225h-006xxxm_R FPC1004-4AW -S PCB Footprint = FP226H-004XXXM_L A 1 2 3 4 5 6 7 8 1 2 3 4 30mil 1 2 3 4 5 6 4 3 2 [48] CONNECTOR Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 48 of 77 1 Connectors B - 49 B.Schematic Diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD5 PS8331_SW GND LED_HDD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GCLK_25M_GLAN C505 LED_HDD# MAIN: 6-20-94K50-012 2ND: 6-20-94K60-012 1 (⏓ ⏓USB3.0x2, PHONE JACK) C1133 FP225H-012S10M 12 11 10 9 8 NC1 7 NC2 6 5 4 3 2 1 J_LED1 3 LAN BOARD 3.3VS Schematic Diagrams Fan, LID, SATA HDD 5 4 3 VGA FAN CONTROL-Selector WEY_11/22 Q39 2SK3018S3 D [35,49] VGA_FANSEN LID BOARD CONN CPU FAN CONTROL 5VS G VGASEN_SEL U24 [35,49] 1 2 3 4 FON1# S D26 BAT54CW H A 1 3 C A 2 1 D VGA_FAN2SEN 2 VGA_FAN1SEN A D25 C750 C745 1u_6.3V_X5R_04 *4.7u_6.3V_X5R_06 FON VIN VOUT VSET GND GND GND GND 8 7 6 5 VDD3 J_LID1 NCT3940S-A C RB751S-40H CPU_FAN CPU_FAN [35] [10,35] 1 2 3 4 LID_SW # LID_SW # 5VS_CPU_FAN J_FAN1 FPC1004-4AW -S PCB Footprint = fp226h-004xxxm_l 1 2 3 C721 10u_6.3V_X5R_06 D NC1 NC2 GND 85204-03001 [35,49] 0B1 1B1 7 VGASEN_SEL A0 GND S0 5 8 VCC A1 GND S1 12 C402 *0.1u_10V_X7R_04 J_FAN1 3 R92 3.3VS 4.7K_04 1 1 3 9 4 6 VGA_FANSEN FOR SUPPORT OPTANE㨇 㨇䧖,SATA HDD≈ ≈POWER GATEING暣 暣嶗 [35,49] 5VS *PI5A3158BZAE SATA_5VS śɥ śɨ C J1 1 2.5A U32 C846 1u_6.3V_X5R_04 *4.7u_6.3V_X5R_06 1 2 3 4 FON VIN VOUT VSET GND GND GND GND 8 7 6 5 [35] VGA_FAN1 VOUT VOUT VOUT 7 6 5 M5938BRD1U C973 C972 10u_6.3V_X5R_06 2 SATA_5VS EN VBIAS 4 5V Q50 *2SK3018S3 *10K_04 A C952 D32 C *RB0540S2 J_FAN1 3 1 㑯ᶨᶲẞ R647&D32 OR C974 4.7K_04 BY ἧ䓐䘬廠↢暣⡻ 婧㔜, ὅ≇䌯( 旣ῤ &⊭墅⣏⮷ ) R647 ON 85204-03001 6-20-23120-003 VGA_FAN1SEN 2 *OPEN_4mil PJ48 C4 1 2 3 C821 GATE GND 3 [11,12,13,50,55] SUSB SUSB G B 1 㓦暣徜嶗 枸䔁ᶵᶲ C974 VGA FAN2 CONTROL 5VS C *220_06 1 SATA_PW R_EN FROM PCH J_VFAN1 R520 SATA_5VS 2.5A 8 R646 [34] 5VS_VGA_FAN1 3.3VS VOUT ㈦ bios天 天 pin NCT3940S-A VGA_FAN1 B *OPEN-3mm D VFAN1ON# C844 VIN 10u_6.3V_X5R_06 VGA FAN1 CONTROL 9 C943 10u_6.3V_X5R_06 C939 5VS 2 U42 S 10 VGA_FAN2SEN VGA_FAN1SEN VCC 10u_6.3V_X5R_06 0B0 1B0 CPU_FANSEN 10u_6.3V_X5R_06 2 11 Sheet 49 of 77 Fan, LID, SATA HDD [35] U10 1u_6.3V_X5R_04 *100p_50V_NPO_04 U29 *4.7u_6.3V_X5R_06 FON VIN VOUT VSET GND GND GND GND 8 7 6 5 J_HDD1 NCT3940S-A VGA_FAN2 [35] VGA_FAN2 5VS_VGA_FAN2 J_VFAN2 1 2 3 C828 10u_6.3V_X5R_06 1 2 3 4 5 6 7 8 9 10 SATA1B_TXP SATA1B_TXN C933 C934 0.01u_50V_X7R_04 0.01u_50V_X7R_04 SATA1B_RXN SATA1B_RXP C935 C936 0.01u_50V_X7R_04 0.01u_50V_X7R_04 C931 FP225H-010S10M 88266-03001 A VGA_FAN2SEN J_FAN1 3 3.3VS R170 SATA1B_TXP_R SATA1B_TXN_R SATA1B_RXN_R SATA1B_RXP_R SATA1B_TXP_R [31] SATA1B_TXN_R [31] SATA1B_RXN_R SATA1B_RXP_R 4.7K_04 1 C932 C929 C930 A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ main HDD VDD3 [5,26,30,31,32,33,34,35,37,38,48,50,51,52,53,54,56,59,60] VIN [10,35,39,50,53,54,55,56,57,58,59,60] 3.3VS [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,50,57,64] 3.3V [2,10,27,38,43,45,48,50,51,52,55,56] 5VS [10,11,12,13,36,39,40,41,47,48,50,61,62,63,64] 5V [39,44,45,48,50,51,52,53,54,55,56,57,58,59,63] [31] [31] SATA_5VS 22u_6.3V_X5R_08 1u_6.3V_X5R_04 1 2 3 4 22u_6.3V_X5R_08 C815 0.1u_10V_X7R_04 VFAN2ON# C816 1u_6.3V_X5R_04 B.Schematic Diagrams 5VS 枸䔁 Title [49] FAN, LID, SATA HDD Size A3 Date: 5 B - 50 Fan, LID, SATA HDD 4 3 2 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 49 of 77 Schematic Diagrams 5V, 5VS, 3.3V, 3.3VS, 3.3VA 1 2 3 4 5 VIN1 VIN VA C704 0.1u_50V_Y5V_06 U21 VIN1 C701 VA VIN C698 0.1u_50V_Y5V_06 0.1u_50V_Y5V_06 Clost to P2808B0 [48] R422 10K_04 1 R426 1_1%_06 2 M_BTN# USB_CHARGE_EN R424 10K_04 3 R425 *100K_04 4 R423 VA VIN1 VIN DD_ON_LATCH M_BTN# PWR_SW# INSTANT-ON GND DD_ON 8 R24 7 R420 *100K_04 6 R22 10K_04 5 R23 1K_1%_04 100K_04 USB_CHARGE_EN [35,54] VDD3 PW R_SW # [35] P2808B0 1K_1%_04 A A VDD3 VDD3 PR346 PR358 10K_04 10K_04 SUSB D [48,55] 2SK3018S3 PC215 [10,32,34,35,41,42,56] G SUSB# SUSB 2SK3018S3 *0.1u_10V_X7R_04 PR337 PR352 100K_04 100K_04 [11,12,13,49,55] PQ39 PC228 S D G DD_ON S [35,45,48,54] DD_ON# *0.1u_10V_X7R_04 B B VDD5 5V 6A VDD3 3 6 C996 220p_50V_NPO_04 D Q54A CT2 0.1u_10V_X7R_04 5VS 6A 5VS C994 10 C995 470p_50V_X7R_04 R640 10K_04 VDD3 2 EMI VIN 4 EMI C VIN [32,35,56] SMTDK3S6R VDD3_R VDD3 R678 10K_04 G DEFAULT SHORT SUSB#_EN 2 1 Q53 2SK3018S3 SUSB SUSB# 3.3VA_ON EC_SLP_SUS# C948 1u_6.3V_X5R_04 C949 VDD3 VIN R635 10K_04 S D SMTDK3S6R Q54B 5G 1 PJ45*CV-40mil 1 3 2G 3.3VA_ON R676 100_04 0.1u_10V_X7R_04 D 100_04 R639 100K_04 CT1 8 9 EN2 0.1u_10V_X7R_04 VBIAS 12 R677 OUT2 OUT2 C946 6 7 5 C997 OUT1 OUT1 GND VDD3 13 14 IN2 IN2 4 3A 3.3VA IN1 IN1 GND 1 2 0.1u_10V_X7R_04 G5016 EN1 3.3VA U43 11 C950 15 VDD5 Sheet 50 of 77 5V, 5VS, 3.3V, 3.3VS, 3.3VA R679 C947 PJ44 *1mm *0.1u_10V_X7R_04 *10K_04 C *0.1u_10V_X7R_04 VIN SUSB#_EN [51] ON C88 VDD3 U12 CT1 3 CT2 R556 10K_04 1 DD_ON_EN 8 9 0.1u_10V_X7R_04 3.3VS 6A 3.3VS C490 10 0.1u_10V_X7R_04 EN2 C492 220p_50V_NPO_04 OUT2 OUT2 VBIAS 12 0.1u_10V_X7R_04 OUT1 OUT1 C470 6 7 C491 330p_50V_NPO_04 5 13 14 C493 IN2 IN2 4 6A 3.3V G5016 IN1 IN1 GND 3.3V 1 2 11 0.1u_10V_X7R_04 GND 0.01u_50V_X7R_04 0.01u_50V_X7R_04 1000p_50V_X7R_04 1000p_50V_X7R_04 VDD3 C467 EN1 C91 15 C89 C90 DEFAULT SHORT DD_ON 2 PJ37 *1mm VDD3 C451 C450 1u_6.3V_X5R_04 *0.1u_10V_X7R_04 D VDD3 1 10K_04 SUSB#_EN C449 *0.1u_10V_X7R_04 D [39,44,45,48,49,51,52,53,54,55,56,57,58,59,63] VDD5 [54] VIN1 [60] VA [5,30,31,32,33,34] 3.3VA [10,35,39,53,54,55,56,57,58,59,60] VIN [5,26,30,31,32,33,34,35,37,38,48,49,51,52,53,54,56,59,60] VDD3 [39,44,45,48,49,51,52,53,54,55,56,57,58,59,63] 5V [10,11,12,13,36,39,40,41,47,48,49,61,62,63,64] 5VS [2,10,27,38,43,45,48,51,52,55,56] 3.3V [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,57,64] 3.3VS PJ53*CV-40mil 2 R569 R800 10K_04 2 1 3.3VS_ON 3 4 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: [50] 5V,5VS,3.3V,3.3VS,3.3VA Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 50 of 77 5 5V, 5VS, 3.3V, 3.3VS, 3.3VA B - 51 B.Schematic Diagrams DD_ON# PQ37 Schematic Diagrams 1.0DX_VCCSTG/VCCSFR_OC/2.5V 4 VCCIO_EN [50] SUSB#_EN R591 R590 VOUT VOUT VOUT 1A 8 1A 9 C888 C1080 C1089 7 6 5 M5938BRD1U DEFAULT SHORT 1 U53 10u_6.3V_X5R_06 VOUT VDDQ 10u_6.3V_X5R_06 10u_6.3V_X5R_06 VIN 1 VCCSFR_OC 1.0DX_VCCSTG *1mm 10u_6.3V_X5R_06 C871 10u_6.3V_X5R_06 9 C867 2 PJ43 PJ52 VIN 8 VOUT VCCSTG_EN 2 EN VBIAS 4 SUSB#_EN 5V R751 0_04 VCCSFR_OC C1102 7 VOUT 6 VOUT 5 VOUT M5938BRD1U VCCSFROC_EN C876 D 2 EN 4 VBIAS 5V R746 R592 10K_04 R1 0.1u_10V_X7R_04 R1 *10K_04 C872 C882 GATE GND 3 A D37 D1 *RB0540S2 C A C D27 RB0540S2 1 C1093 1u_6.3V_X5R_04 D1 Sheet 51 of 77 1.0DX_VCCSTG/ VCCSFR_OC/2.5V 2 *1mm 1A 10K_04 *4.7K_04 1u_6.3V_X5R_04 1 6-15-59381-7B0 GATE 3 GND 6-15-59381-7B0 C1108 C1 *0.01u_16V_X7R_04 C1 *0.01u_16V_X7R_04 C *1 R1 *2 C1 VOUT rising time can be speed up if adding & D1 network between EN and GATE VOUT rising time can be slow down if adding between GATE and GND *1 R1 *2 C1 C VOUT rising time can be speed up if adding & D1 network between EN and GATE VOUT rising time can be slow down if adding between GATE and GND 2.5V_LDO 3.3V 3A 2.5V/3A VREG5 PC182 PC180 0.1u_10V_X7R_04 PR289 *47K_04 3 2.5V_PG B PJ31 [32,35,55,56] 1 SUSC# 1 VIN VCNTL POK VOUT PR294 2 *OPEN_4mil 2 8 9 0_04 DEFAULT 1u_6.3V_X5R_04 天䦣月役PIN6儛 PU13 G9661-25ADJF11U NC VFB 3A 6 B PR292 7 Ra PC177 PR290 100K_04 2 *CV-40mil PC176 21.5K_1%_04 PR291 PJ30 1 VDD3 *0.1u_10V_X7R_04 2.5V 3A 5 EN GND GND V2.5_LDO 4 Rb 10K_1%_04 PC178 22u_6.3V_X5R_08 PC181 10u_6.3V_X5R_06 82p_50V_NPO_04 B.Schematic Diagrams [56,59] 1 U35 1A 2 DEFAULT SHORT 1.0DX_VCCSTG VDD1.0 D 3 10u_6.3V_X5R_06 5 NOTE: 1.0DX_VCCSTG TURN-ON need <65us M5938 TURN-ON TIME=60us PC179 *10u_6.3V_X5R_06 For CV test Vout = 0.8V ( 1 + Ra / Rb ) NB671_SIGNAL_GND2 A A [54,56] VREG5 [2,10,27,38,43,45,48,50,52,55,56] 3.3V [10,35,39,50,53,54,55,56,57,58,59,60] VIN [8,9] 2.5V [6,8,9,32,55] VDDQ [6] VCCSFR_OC [39,44,45,48,49,50,52,53,54,55,56,57,58,59,63] 5V [5,6] 1.0DX_VCCSTG [31,33,56] VDD1.0 [5,26,30,31,32,33,34,35,37,38,48,49,50,52,53,54,56,59,60] VDD3 5 B - 52 1.0DX_VCCSTG/VCCSFR_OC/2.5V 4 3 2 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [51] 1.0DX_VCCSTG/VCCSFR_OC/2.5 Size A3 Date: Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 51 of 77 Schematic Diagrams 1V8_RUN/AON, NV3V3 2 3 4 5 6 Open VREG Type 0 5V 1V8_AON PC167 22u_6.3V_X5R_08 PR276 10_06 PR279 10K_04 EM5841BVT [27] PR281 NV_1V8AON_EN 9 1V8_AON_PG PGOOD VIN 2.6Amps @ 1.8V PR277 10K_1%_04 PR278 *160K_04 3 1V8_AON A OpenVReg NV_1V8AON_EN_R 0_04 8 1V8_AON PC165 0.1u_10V_X7R_04 PU11 GND [27] A 7 1V8_AON GND 1 10 PC168 *0.01u_16V_X7R_04 EN/FS BOOT/NC 1 FB SW SW GND GND THERM *0.22u_10V_X5R_04 PC169 1u_6.3V_X5R_04 8 3A 1 2 2.2uH_4*4*2.0 6 7 4 5 11 PR283 PC173 M:6-02-05841-CD0 S:6-02-08071-CD0 4/20 ㍉岤天㯪⮶ℍ2ND 0_04 PR280 0_04 3300p_50V_X7R_04 PC171 PC166 PC170 0.1u_10V_X7R_04 VCC 22u_6.3V_X5R_08 2 PL12 22u_6.3V_X5R_08 PC172 4A GND Rt PR282 20K_1%_04 Rb PR284 10K_1%_04 1.8V= 0.6 * (1+(20K/10K)) 1V8_AON 3A C758 10u_6.3V_X5R_06 9 C771 10u_6.3V_X5R_06 B 1V8_RUN PU10 VIN 3A 8 VOUT 7 VOUT 6 VOUT B VDD3 5 VOUT R128 10_06 M5938BRD1U Sheet 52 of 77 1V8_RUN/AON, NV3V3 6 D 1 R119 100K_04 S MTDK3S6R Q12A R481 0_04 NV_1V8RUN_EN_R 2 EN 4 VBIAS 2G 5V 3 NV_1V8RUN_EN D 4 [27] S MTDK3S6R R474 Q12B R1 NV_1V8RUN_EN_R 5G A C781 1u_6.3V_X5R_04 *0.1u_10V_X7R_04 *10K_04 D22 D1 *RB0540S2 C C780 1 C779 C1 GATE 3 GND 6-15-59381-7B0 100p_50V_NPO_04 C C NV3V3 3.3V NV3V3 U27 10u_6.3V_X5R_06 VOUT VOUT 1A 8 C762 7 6 5 M5938BRD1U 2 EN VBIAS 4 VDD3 R125 10_06 R130 100K_04 Q13A 2G MTDK3S6R 5V Q13B 6 10u_6.3V_X5R_06 VOUT NV_3V3_EN_R 0_04 VOUT 1 R504 NV_3V3_EN VIN 3 [27] 9 C331 10u_6.3V_X5R_06 1A C338 D S D NV_3V3_EN_R *0.1u_10V_X7R_04 R1 R503 *10K_04 C790 A 1u_6.3V_X5R_04 D D23 *RB0540S2 *0.01u_16V_X7R_04 C788 C D1 1 GATE GND 3 C1 6-15-59381-7B0 5G MTDK3S6R 4 C789 S D [5,26,30,31,32,33,34,35,37,38,48,49,50,51,53,54,56,59,60] [14,25,53] [39,44,45,48,49,50,51,53,54,55,56,57,58,59,63] [3,23,24,26,27,28,31,53,61,62,64] [14,15,23,24,28] [2,10,27,38,43,45,48,50,51,55,56] [11,12,13,14,26,46,53,61,62] [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] VDD3 PEX_VDD 5V 1V8_AON 1V8_RUN 3.3V NV3V3 3.3VS ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [52] 1V8_RUN, 1V8_AON , NV3V3 Size A3 Date: 1 2 3 4 5 6 Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 52 of 77 8 1V8_RUN/AON, NV3V3 B - 53 B.Schematic Diagrams Vout= Vref * (1+(Rt/Rb)) 1V8_RUN Schematic Diagrams PEX_VDD 1 2 3 4 5 Open VREG Type 0 5V PC160 0.1u_10V_X7R_04 PU9 7 8 2.6Amps @ 1.0V PC161 PR269 10_06 22u_6.3V_X5R_08 6 PEX_VDD PR75 10K_1%_04 EM5841BVT PEX_VDD GND VIN *160K_04 3 1 BOOT/NC 2 PC159 2.4A PEX_VDD_R PR272 PC158 GND 0_04 PR270 PC155 0_04 3300p_50V_X7R_04 A PEX_VDD_R PC154 0.1u_10V_X7R_04 FB GND PJ28 *3mm 22u_6.3V_X5R_08 1 1 2 2.2uH_4*4*2.0 6 7 4 5 11 22u_6.3V_X5R_08 SW SW GND GND THERM PC57 0.1u_10V_X7R_04 8 PL11 PC156 VCC *0.1u_10V_X7R_04 2 1.1V 4A 0.400 PC157 *0.01u_16V_X7R_04 EN/FS VDD3 R103 10_06 R83 100K_04 GND [27] Rt PR274 6.8K_1%_04 Rb PR273 10K_1%_04 Q5A MTDK5S6R 6 PGOOD OpenVReg 10 A NV_PEXVDD_EN PR76 GND 9 PEXVDD_EN 0_04 GND 0.200 PR271 D 2G PS6_FB_RR_PEXVDD PS6_FB_MARGIN_PEXVDD *10_1%_04 PEXVDD_EN S D 5G 4 PR275 Q5B MTDK5S6R 3 1.050V= 0.6 * (1+(7.5K/10K)) 1 GND GND B.Schematic Diagrams Vout= Vref * (1+(Rt/Rb)) S Cold boot/Optimus: 1V8_AONĺ1V8_RUNĺNVVDDĺNVVDDS ĺPEX_VDDĺFBVDDQ GC6 2.1 Exit: 1V8_RUNĺNVVDD_LĺNVVDD_SĺPEX_VDD or 1V8_RUNĺNVVDD_LĺNVVDD_S & PEX_VDD Sheet 53 of 77 PEX_VDD PWR_SRC_NV_FB GC6_FB_EN VIN 0.400 PRS2 10A 4 3 NVVDDS PEX&1.05V FBVDD/Q VR Complex NV3V3 INS16638818 10A 1 PWR_SRC_VINP_R 2 RL1632T4F-B-R005-FNH GND 1V8_MAIN_EN NV3V3 PU1 1V8_AON 1V8_MAIN NVVDD B PR31 10_1%_04 PWR_SRC_VINP PR33 665K_1%_04 PC36 10u_6.3V_X5R_06 VIN1P 11 PWR_SRC_VINN_R PR29 10_1%_04 PWR_SRC_VINN B PC42 12 VIN1N VS 4 SCL SDA 6 7 I2CC_SCL I2CC_SDA A0 5 PWR_SRC_IMON_A0 0.01u_50V_X7R_04 PR39 *10K_04 GND I2CC_SCL I2CC_SDA [26,53] [26,53] PR37 10K_04 Place resistors close to IC [62] PWR_SRC_NV_VINP_R PR36 10_1%_04 PR38 665K_1%_04 VIN2P 15 VIN2P 14 VIN2N 2 VIN3P 1 VIN3N 8 WARN GND GND NVVDD GPU_PWR_EN [62] GPU_EVENT# GPU GPU_RST# PLATFORM_RST# SYS_PEX_RST_MON# EC/PCH [61] PR35 PWR_SRC_NV_VINN_R 10_1%_04 PR41 PWR_SRC_NVS_VINNP_R GND PR40 [61] PWR_SRC_NVS_VINN_R PR42 GC6 2.1 Control Signals 1.1V8_MAIN_EN 2.GC6_FB_EN 3.GPU_EVENT# 4.GPU_PEX_RST_HOLD# 5.SYS_PEX_RST_MON# C GPU_PEX_RST# EN PGOOD SNN_VIN3P PC43 10u_6.3V_X5R_06 1V8_AON 10 PWR_SRC_VALID 13 SNN_TC 16 SNN_VPU GND PAD 3 17 [62,63] [61,62,64] [3,23,24,26,27,28,31,52,61,62,64] PWR_SRC_NV PWR_SRC_NV_FB 1V8_AON [14,25] PEX_VDD [10,35,39,50,54,55,56,57,58,59,60] VIN [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [39,44,45,48,49,50,51,52,54,55,56,57,58,59,63] 5V [14,15,23,24,28,52] 1V8_RUN [11,12,13,14,26,46,52,61,62] NV3V3 [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,54,56,59,60] VDD3 SNN_VIN3N 10_1%_04 9 1V8_AON CRIT INA3221AIRGV GND PR32 10K_04 PWR_SRC_WARN* PR34 0_04 PR30 10K_04 PWR_SRC_CRTCAL* PR28 0_04 DG P.93 N17E PGOOD EN 1V8_MAIN_EN PV TC VPU GPIO28_OC_WARN# [26] POWER RAIL GC6 2.1 - VR Complex 1. GPU_PWR_EN 2. 1V8_MAIN_EN 3. GC6_FB_EN 1V8_AON GPU VIN2N 10_1%_04 665K_1%_04 NVVDDS GPU_PEX_RST_HOLD# GPU_PWR_EN (SYSTEM) PC37 10u_6.3V_X5R_06 EN PGOOD note: t1(from 1V8_RUN_EN to PEX_VDD/NVVDD_PG) must NOT exceed 4ms. POWER ON SEQUENCE POWER OFF SEQUENCE 1V8_AON ON 1V8_MAIN OFF PEX&1.05V OFF NVVDD OFF NVVDDS OFF FBVDD/Q ON net PCH_GPIO Voltage DGPU_PWR_EN (GPP_F23) (1V8_AON) PEX&1.05V EN D PGOOD [28,62] [28,62] GPPG9_PCH_NV3V3_EN (GPP_G9) (NV3V3) [28,64] NVVDD [28,64] GPPG10_PCH_NVVDD_EN (GPP_G10) (NVVDD) [64] GPPG11_PCH_NVVDDS_EN (GPP_G11) (NVVDDS) EN I2CC_SCL [26,53] I2CC_SDA I2CC_SCL Title FBVDDQ 3 4 GPU_NVVDD_SENSE GPU_NVVDD_SENSE D FBVDDQ_SENSE FBVDDQ_SENSE FBVDDQ_SENSE_RTN FBVDDQ_SENSE_RTN PS2_FBVDDQ_FB PS2_FBVDDQ_FB [53] PEX_VDD Size Document Number Custom SCHEMATIC1 Date: 2 GPU_GND_SENSE GPU_GND_SENSE ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ GPPG0_PCH_PEXVDD_EN (GPP_G0) (PEX_VDD) PGOOD FBVDD/Q GC6_FB_EN B - 54 PEX_VDD [26,53] I2CC_SDA 1V8_MAIN GPPG8_PCH_1V8RUN_EN (GPP_G8) (1V8_MAIN) 1 C State in GC6 5 6 7 Rev D02A 6-71-PA700-D02A Wednesday, July 05, 2017 Sheet 53 8 of 77 Schematic Diagrams VDD3, VDD5 5 4 3 2 1 VREF PR356 *0_04 PR359 0_04 PC221 1u_10V_Y5V_06 PR137 PR349 EN_3V D EN_5V D PC216 1 UGATE1 21 PQ35 0.1u_10V_X7R_04 MDU1516 ULTRASO-8 PR348 VCLK C890 *1000p_50V_X7R_04 S G PR343 PR335 PR339 0_04 PR340 *0_04 PR338 *0_04 0_04 *0_04 2.2_06 VREF VREG5 PC211 PD2 VIN C PC209 A 1 1 2 PJ46 for EMI R606 *5.1_06 PC225 VDD5 2 Sheet 54 of 77 VDD3, VDD5 *5mm R1 DEFAULT SHORT PR354 30.1K_1%_06 + R2 PR351 19.1K_1%_06 PC234 PC222 C 0.1u_10V_X7R_04 Vout=2.01*(1+R1/R2) =2.01*(1+30.1K/19.1K) =5.178 VREG5 VIN1 SYS5V 1 18 LDO5 GND PAD GND VIN 17 13 A PL16 BCIH1040-2R2M *680K_1%_04 =2.01*(1+13.7K/18.7K) =3.482 R1 PR355 13K 19 PR342 2 G PQ34 MDU1531 ULTRASO-8 EN_ALL Vout=2.01*(1+R1/R2) R2 PR348 18.7K 20 PR341 18.7K_1%_04 MEDION LGATE1 16 EN0 3 2 1 CSOD140SH 25 15 LGATE2 4 SKIPSEL 12 PD17 PHASE1 14 5 5 5 5 C PQ33 QM3006M3 PHASE2 VDD5 12A 220u_6.3V_6.3*4.4 R2 *100p_50V_NPO_04 220u_6.3V_6.3*4.4 0.1u_10V_X7R_04 PR355 13.7K_1%_04 R555 *5.1_06 R1 for EMI PC192 PC223 + 6-02-51125-CQ1 11 + + *1000p_50V_X7R_04 UGATE2 PC213 0.1u_50V_Y5V_06 SYS5V C PD18 10 22 *10K_04 A CSOD140SH 4 BOOT1 TPS51125ARGER PR345 D BOOT2 PC79 0.1u_10V_X7R_04 23 S 5 5 5 5 9 POK D LDO3 1u_10V_X7R_06 PC196 4.7u_25V_X5R_08 EN1 4 2 VFB1 VREF TONSEL VFB2 EN2 8 *5mm DEFAULT SHORT PC187 PC203 PC214 PQ36 QM3004M3 PL15 BCIHP0730-4R7M C853 2 1 *1000p_50V_X7R_04 1 C EE 4.7u_25V_X5R_08 0.1u_50V_Y5V_06 4.7u_25V_X5R_08 4.7u_25V_X5R_08 SYS3V PJ33 2 24 3 2 1 VDD3 PC202 VO1 1u_10V_X7R_06 4.7u_25V_X5R_08 RB751S-40H VREG5 B Qpxfs!po!WEE40WEE6 QXN B EN_5V PR361 6 D 10K_04 PQ41A DD_ON_EN_VDD USB_CHARGE_EN S MTDK3S6R D MTDK3S6R [35,50] 2 G 3 1 1 PQ41B 5 G PR362 PJ23 *CV-40mil S 100K_04 D 2 4 DD_ON G PQ40 2SK3018S3 S D02_0313_KAI [35,45,48,50] A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ [51,56] VREG5 [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,56,59,60] VDD3 [39,44,45,48,49,50,51,52,53,55,56,57,58,59,63] VDD5 [50] VIN1 [10,35,39,50,53,55,56,57,58,59,60] VIN Title Size A3 Date: 5 4 3 2 [54] VDD3,VDD5(Power) Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 54 of 77 1 VDD3, VDD5 B - 55 B.Schematic Diagrams 8A VO2 *EEEFZ1E101P VDD3 7 PC205 PC207 *EEEFZ1E101P PC206 VIN PC194 VIN PC218 1000p_50V_X7R_04 PU16 PC282 VREG3 5 6 60.4K_1%_04 3 130K_1%_04 1000p_50V_X7R_04 Schematic Diagrams DDR 1.2V / 0.6VS 3 DDR4 1.2V/0.6VS PD24 5V PU17 G5616BRZ1U *2mm PC260 PC261 20 1 PR379 *15mil_short *10u_6.3V_X5R_06 VTT_SNS 2 11/17 VTT_TON 9 VTT_REF 4 VBST VTT DRVH VTTGND LL VTTSNS DRVL GND PGND TON CS PVCC5 VCC5 VTTREF 18 17 VDDQ_DRVH 16 VDDQ_L 15 VDDQ_DRVL PQ43 MDU1531 ULTRASO-8 14 PR373 4.12K_1%_06 13 VDDQ_CS 12 11 VDDQ_VCC5 VDDQSET 6 VDDQSNS S5 VDDQSET S3 G PR365 2_06 1 C1072 + *2200p_50V_X7R_04 R732 *2.2_1%_06 2 VDDQ *8mm PC240 PC250 VDDQ_S5 8 7 3.3V PR388 *15mil_short PR370 *47K_04 PR369 *0_04 VDDQ_PW RGD C [56] 21 C PJ49 10 GND 5 5V D 13A DEFAULT SHORT PL20 BCIHP0730-1R0M 1 2 PCB Footprint = BCIHP0735A 1u_6.3V_X5R_04 PGOOD VDDQ_SNS 1.2V VDDQ_R PC252 8.06K_1%_04 R345 68K_1%_04 G B C1106 D G S SUSC# 2SK3018S3 PQ51 BTN3904 M-SOT23-CBE D *100p_50V_NPO_04 C981 *0.22u_10V_X5R_04 G PJ25 *CV-40mil *2SK3018S3 3.3V CV Test 3.3V [48,50] PR364 DD_ON# 100K_04 CV Test VDDQ_PW RGD PR406 100K_04 PQ50 0.01u_50V_X7R_04 G ON C PR403 100_04 B PQ52 E VDDQ_R B 2SK3018S3 S B [32,35,51,56] Q23 D 1K_04 2SK3018S3 ⮔⹎≈⣏䁢8mil Q26 PJ51 *CV-40mil 2 PR405 DDR_VTT_PG_CTRL E [5] *0.1u_10V_X7R_04 S 10K_04 G 100K_04 1 PR398 C 5V VTTEN_R *0_04 PR402 SUSB PC278 Q24 2SK3018S3 S D R344 C1000 Q25 [11,12,13,49,50] PR397 4.75K_1%_04 VTTEN S 10K_04 D 5V R666 5V 1 PR372 2 Sheet 55 of 77 DDR 1.2V / 0.6VS 4.7u_25V_X5R_08 PR391 0_04 1u_6.3V_X5R_04 BTN3904 M-SOT23-CBE 1.↯㎃䶂嶗ㇵ暨⮶ℍ ,╖ᶨ暣㸸䓐⍇㛔IC PG 5V VDDQSET_R R697 10_04 3.3V R702 10K_04 R1 UP1804AMA8 8 7 6 5 R675 SMB_CLK 0_04 [32,39,47] R723 *0_04 PR148 *100K_04 B - 56 DDR 1.2V / 0.6VS PJ24 *CV-40mil PQ10 [32] DDR_VOL_SEL PR146 G *0_04 *2SK3018S3 LOW 1.2V HIGH 1.35V A PR147 SMB_DATA ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ *10K_04 0_04 R2 Title [55] DDR 1.2V/0.6VS(Power) [39,44,45,48,49,50,51,52,53,54,56,57,58,59,63] 5V [10,35,39,50,53,54,56,57,58,59,60] VIN [6,8,9,32,51] VDDQ [2,10,27,38,43,45,48,50,51,52,56] 3.3V [8,9] VTT_MEM 5 DDR Vout VDDQSET 0_04 C984 *1u_6.3V_X5R_04 R696 [32,39,47] GPIO *22K_1%_04 R682 0_04 R719 暣⡻ὅTABLE VDDQSET 1 OUT NC NC SCL *0_04 2 C1048 1u_6.3V_X5R_04 A VCC BUS_SEL GND SDA D U48 1 2 3 4 PR374 PR149 S B.Schematic Diagrams 0.1u_10V_X7R_04 4.7u_25V_X5R_08 0.1u_10V_X7R_04 PC249 0.1u_50V_Y5V_06 0.1u_10V_X7R_04 330uF_2V_5*5*4.2 560K_1%_04 VLDOIN PC255 VDDQ_VBST PD25 CSOD140SH 3 PR371 VIN PC247 PC242 22u_6.3V_X5R_08 G PC248 C PJ50 VTT_MEM_R VIN PC267 A 19 10u_6.3V_X5R_06 2A 1 *RB0540S2 2A S PC268 2 PQ46 MDU1516 ULTRASO-8 C VDDQ_R DEFAULT SHORT VTT_MEM A 1 S VTT_MEM(0.675V) D 2 D 4 D 5 4 3 2 Size A3 Date: Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 55 of 77 Schematic Diagrams Power 1.0V, VCCIO 1 2 3 4 5 VIN For CV test 1 PJ38 100K_04 2 *CV-40mil PR316 VDD1.0 820K_1%_06 PC199 PC197 PC198 4.7u_25V_X5R_08 PR324 VDD3 4.7u_25V_X5R_08 EE VDD1.0_EN PQ32 PC201 PR321 0_06 *0.01u_16V_X7R_04 G5602_5V 16 PR317 VTT VR Output Voltages 1.1 V 1.05 V BST TON QM3004M3 1 2.2_04 PL14 BCIHP0730-3R3M 2 1 VOUT 11 LX ILIM VFB VDD PR307 6.19K_1%_04 PQ31 QM3006M3 C857 *1000p_50V_X7R_04 4 3 9 G5602_5V + for EMI PGOOD 8 DL G5602R41U 5 VDD1.0_PW RGD 7 17 1u_6.3V_X5R_04 NC 10K_04 NC PR303 PGND PGND R568 *5.1_06 Sheet 56 of 77 Power 1.0V, VCCIO 14 VDD3 AGND A CSOD140SH M-SOD123 PC190 6 2 *6mm B B VREG5 G5602_5V PR305 DEFAULT SHORT 20mil VDD5 20mil 2 PJ34 20mil 1 *1mm 2 PJ35 20mil 36K_1%_04 PC191 3.3V *15p_50V_NPO_04 PR310 3.3V 1 *1mm R588 10K_04 100K_1%_04 0.75*(1+36K/100K)=1.02 D G 100K_04 C398 C397 0.1u_10V_X7R_04 C407 220p_50V_NPO_04 1 S E VCCIO PJ14 *3mm VDD3 R149 *100_04 D R152 100K_04 S VCCIO_EN SUSC# VCCIO R159 *100K_04 Q16A G2 *MTDK5S6R D C367 S C375 VDD3 D C796 1u_6.3V_X5R_04 VCCIO_EN 0.1u_10V_X7R_04 [51,59] VDD3 S 6 12 2 6 C399 *22u_6.3V_X5R_08 1 1 3 DEFAULT SHORT 1 3 SUSC# C 0.1u_10V_X7R_04 6A Q15A VCCIO_EN G2 *MTDK5S6R 0.1u_10V_X7R_04 S 0.1u_10V_X7R_04 DEFAULT SHORT VDD1.0_PW RGD 1 2 1 PJ11 *CV-40mil PJ10 2 1 4 2 For CV test *1mm 3 D C386 5 4 5G SUSC# *MTDK5S6R CT1 13 14 R505 10K_1%_04 D [32,35,51,55] 4 Q16B Q15B CT2 5 *100_04 OUT1 OUT1 *22u_6.3V_X5R_08 C406 220p_50V_NPO_04 R147 *100K_04 5G *MTDK5S6R PJ42 *CV-40mil C803 1 2 EN1 10 R176 OUT2 OUT2 GND C401 0.1u_10V_X7R_04 VDD3 IN1 IN1 3 8 9 U9 IN2 IN2 GND 1A G5016 15 PJ12 6 7 0.1u_10V_X7R_04 11 *1mm 1.0V VBIAS 2 1.0V_VCCST C800 1 PJ13 1 BTN3904 M-SOT23-CBE 0.022u_16V_X7R_04 4 2 *1mm 2SK3018S3 VDD1.0 EN2 DEFAULT SHORT 1.0V_VCCSFR C865 Q43 2 B C [34,59] *0.01u_16V_X7R_04 C R578 VDD1.0 VCCIO_PW RGD C868 Q42 VCCIO NOTE: 1.0V_VCCST Ton need <10ms G5016 TURN-ON TIME=1.21ms ON VCCIO_PW RGD R587 10K_04 VDDQ_PW RGD SUSB# [55] D [10,32,34,35,41,42,50] U8 74AHC1G08GW [51,54] VREG5 [31,33,51] VDD1.0 [2,3,6] VCCIO [6] 1.0V_VCCSFR [39,44,45,48,49,50,51,52,53,54,55,57,58,59,63] VDD5 [5,6,31,32,57] 1.0V_VCCST [10,35,39,50,53,54,55,57,58,59,60] VIN [39,44,45,48,49,50,51,52,53,54,55,57,58,59,63] 5V [2,10,27,38,43,45,48,50,51,52,55] 3.3V [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,59,60] VDD3 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [56] POWER 1.0V,VCCIO(Power) Size A3 Date: 1 2 3 4 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 56 of 77 5 Power 1.0V, VCCIO B - 57 B.Schematic Diagrams PD16 4 1 PJ40 OCP 12A 10 PC193 1u_6.3V_X5R_04 DEFAULT SHORT VDD1.0 330uF_2V_5*5*4.2 VCC V1.0A PC183 2 A 10A 4 12 DH 1 2 3 VTT_SELECT low high (V1.1S_VTT) EN_PSV PC200 0.1u_10V_X7R_04 13 C A 15 5 5 5 5 2 *1mm 5 5 5 5 1 PJ39 EC_SLP_SUS# 1 2 3 [32,35,50] 0.1u_50V_Y5V_06 PU14 Schematic Diagrams VCC_Core 8 7 6 5 4 3 2 1 ,QWHO6. 0_04 PR252 up1666QQKF FS/OC PC39 4.7u_25V_X7R_08 G2 PC142 4.7u_25V_X7R_08 G2 PC40 4.7u_25V_X7R_08 G2 4.7u_25V_X7R_08 G2 0.1u_25V_X7R_06 G2 PR262 12 LGATE1 2200p_50V_X7R_04 PC143 GPU_VDDS_SENSE PC51 *33p_50V_NPO_04 VREF PC139 PC134 11 PR261 *0_04 [28] 10 *62K_1%_04 330uF_2V_5*5*4.2 100_04 9 UP1666_FBDRTN PQ24 SM7320ESQG 20 LX1_UPI_1666 19 + 330U_2V_D2_D GPU_GNDS_SENSE PR255 PHASE1 PC135 PR64 PR68 45.3K_1%_04 [28] REFADJ + 330uF_2V_5*5*4.2 0_04 8 PC140 0_04 PR65 6 NVVDDS_VREF + PC141 PR63 UP1666_REFADJ 2.2_1%_06 0.1u_10V_X7R_04 *499K_1%_1/16W _04 75K_1%_04 *0.01u_50V_X7R_04 PR249 PC138 NVVDDS_VREF PR59 PC53 PD1 CSOD140SH PW R_SRC_NVVDDS PR67 PC144 8 30A B C B PU2 NVVDDS PL8 CMME063T-R24MS1R197 1 2 9 15R ⎒㚱06㰺㚱08size PR251 2.2_1%_06 G2 5VS PC145 2200p_50V_X7R_04 G2 G2 Phase 㬌⋨➇䶂嶗ᶲẞ PR22 PR24 PR26 PR25 15_1%_06 15_1%_06 15_1%_06 15_1%_06 PR23 5 5 5 5 PR264 PC41 2K_04 PQ2 QM3006M3 [27,61] NV_NVVDDS_EN PR27 D 1 2 3 4 PQ3 2SK3018S3 0_04 G PC35 *10u_6.3V_X5R_06 S B.Schematic Diagrams NVVDDS_VREF D D [53,62,64] PW R_SRC_NV_FB [62,63] PW R_SRC_NV [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [10,11,12,13,36,39,40,41,47,48,49,50,62,63,64] 5VS [3,23,24,26,27,28,31,52,53,62,64] 1V8_AON [23,28] NVVDDS [11,12,13,14,26,46,52,53,62] NV3V3 P650RS/P670RS = G2 Phase P670RP6 = G1 Phase ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 1 B - 62 NVVDDS 2 3 4 5 6 [61] NVVDDS(Power) Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 61 of 8 77 Schematic Diagrams NVVDD 1 1 2 3 4 5 6 7 8 CO-LAY PW R_SRC_NV_FB PW R_SRC_NV PR18 PRS1 1 2 10A [53] *10K_1%_04 PW R_SRC_NV_VINN_R 4 3 RL1632T4F-B-R005-FNH PW R_SRC_NV_VINP_R [53] A *0_04 PR187 *0_04 PR185 0_04 GPIO0_NVVDD_PW M_VID 0_04 PC17 *0.1u_10V_X7R_04 NV_NVVDD_EN layout 1pcs B2 慵䔲2PCS 0805 size G1ᶵᶲ [27,63] place at MOSFET side 5 G2 *0.01u_50V_X7R_04 0_04 PL7 1 S2 B NVVDD 0.6V~1.2V Sheet 62 of 77 NVVDD 1 ”NP-A”㗗NO PASTEMASK PD12 9 30A 2 CMME104T-R22MS PR247 5 G2 9 S2 4700p_50V_X7R_04 NV_VDD_L 2.2_1%_06 CO-LAY PC131 PC20 309_1%_04 PC6 4 6 8 7 PQ22 CSD87350Q5D CSOD140SH PC4 D2 2200p_50V_X7R_04 B PH1_UPI_9509 PR17 15K_1%_04 *20K_1%_04 5VS PH2_UPI_9509 UGATE2 PGOOD BOOT2 18 17 UGATE2_UPI_9509 16 1u_16V_X7R_06 D1 499_1%_04 PR197 2_1%_04 NV3V3 PR169 PR201 PC112 0_04 0.1u_25V_X7R_06 *100K_1%_04 PR194 PR199 [14,27] + 1 2 C INS16666644 S1 5 G2 DCR 0.6m ohm PL6 CMME104T-R22MS 1 2 S1 4 6 D2 8 7 PQ18 CSD87350Q5D place at MOSFET side PC98 3 G1 4 6 D2 8 7 PQ19 CSD87350Q5D PD10 5 G2 9 S2 9 NVVDD 30A PR188 10K_04 S2 0_04 D1 INS16664900 100K_1%_04 499_1%_04 PR191 1 2 3 G1 PC99 2.2_1%_06 CSOD140SH 4/26 power 妋restart⓷柴 ,PR75 51K change to 15K 19 PR173 PR15 *0_04 PR189 PC115 A PR174 *4700p_50V_X7R_04 PH2_UPI_9509 layout 1pcs B2 慵䔲2PCS 0805 size PC88 20 UGATE2_UPI_9509 PR212 0_04 1000p_50V_X7R_04 PC5 PW R_SRC_NV 5VCC C BOOST1 1 2 3 EN PSI ISEN1 PH3_UPI_9509 *10K_1%_04 2.2_06 21 4.7u_25V_X7R_08 25 PHASE2 PR209 5VS 4.7u_25V_X7R_08 [63] LGATE2 [63] PR20 4.7u_25V_X7R_08 PR183 499_1%_04 PC102 PVCC PW M3_1 5VCC 22 4.7u_25V_X7R_08 G1ᶵ ᶵᶲẞ/G 2 ᶲ ẞ PR175 *0_04 C UGATE1 5 7 COMP 100_04 PR181 1K_04 VID FB 15 0_04 NVVDD PR170 up9509PQAG FBDRTN 24 PH1_UPI_9509 23 EEEFZ1E101P 12 PWM3 PC93 PR180 GPU_NVVDD_SENSE PC101 *33p_50V_NPO_04 PHASE1 LGATE1 TON PC86 11 PR171 *0_04 [28,53] 10 VREF ISEN2 UP9509_FBDRTN REFADJ PC11 100_04 9 PC12 PR16 8 1u_25V_X7R_06 0_04 6 UP9509_VREF 1u_25V_X7R_06 PR12 UP9509_REFADJ *51K_1%_04 ISEN3 *0_04 PR10 GND PR14 14 GPU_GND_SENSE *0.1u_16V_X7R_04 13 [28,53] *82K_1%_04 PC103 REFIN 300K_1%_04 PR176 *25TQC15MYFB PR172 PW R_SRC_NV 4/26 power 妋restart⓷柴 ,PC63ᶵᶲẞ UP9509_VREF PU7 4 + UP9509_FBDRTN NVVDD_PW RGD PC100 2200p_50V_X7R_04 1V8_AON NV reserve G1ᶵᶲ PR21 15K_1%_04 PR202 PH1_UPI_9509 *10K_04 PR211 *0_04 䓐㕤婧㗪⸷ GPIO29_NVVDD_PH1 D [26] D PR203 *30.1K_1%_04 D PQ21 *MTN2002ZS3 [63] PW R_SRC_NV [23,28,63] NVVDD [53,61,64] PW R_SRC_NV_FB [11,12,13,14,26,46,52,53,61] NV3V3 [10,11,12,13,36,39,40,41,47,48,49,50,61,63,64] 5VS [39,44,45,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [3,23,24,26,27,28,31,52,53,61,64] 1V8_AON [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS S G PR204 *10K_04 1 2 3 4 5 6 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [62] NVVDD PHASE 1~2 Size A3 Date: Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 62 of 77 8 NVVDD 1 B - 63 B.Schematic Diagrams 16.5K_1%_04 PR210 PR11 S1 4 6 8 7 PQ23 CSD87350Q5D + EEEFZ1E101P 0_04 PC29 4.7u_25V_X7R_08 PR177 0.1u_25V_X7R_06 PC123 PC24 4.7u_25V_X7R_08 D2 100K_1%_04 PR200 4.32K_1%_04 PC116 INS16665736 3 G1 S1 PR198 PR178 4.7u_25V_X7R_08 3 G1 2_1%_04 PC30 1 2 D1 INS16665418 PR195 PC25 4.7u_25V_X7R_08 UP9509_REFADJ 1 2 D1 PC10 20.5K_1%_04 0.1u_10V_X7R_04 PC28 1u_25V_X7R_06 PR13 PR179 6.19K_1%_04 PC26 1u_25V_X7R_06 PC7 4700p_50V_X7R_04 A PW R_SRC_NV PR19 UP9509_VREF UP9509_FBDRTN + C [26] PR186 A 1V8_AON + *25TQC15MYFB 0.400 10K_04 0_04 PC22 PR190 PR193 *25TQC15MYFB GPIO6_NVVDD_PSI# PC21 1V8_AON [26,61] Schematic Diagrams NVVDD 2 4 3 G 1 ᶵ ᶲ ẞ/G 2 ᶲ ẞ PC299 PC297 PC298 PC295 PC296 PC294 5 D2 place at MOSFET side G1ㇵ ㇵᶲẞ S1 4 6 8 7 PQ16 CSD87350Q5D D2 4 6 8 7 PQ17 CSD87350Q5D DCR 0.6m ohm PL5 CMME104T-R22MS 1 2 5 G2 S2 9 S2 9 0.6V~1.2V C692 *22u_6.3V_X5R_08 C700 C39 NVVDD C68 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 22u_6.3V_X5R_08 30A PC132 330uF_2V_5*5*4.2 PD9 C20 + 3 G1 S1 PR168 100K_1%_04 C37 *22u_6.3V_X5R_08 22u_6.3V_X6S_08 PC122 330uF_2V_5*5*4.2 C69 C693 C70 *22u_6.3V_X5R_08 PR196 2.2_1%_06 *22u_6.3V_X5R_08 22u_6.3V_X5R_08 + 3 G1 2_1%_04 D NVVDD PC110 330uF_2V_5*5*4.2 C691 C71 PC133 330uF_2V_5*5*4.2 PC113 *22u_6.3V_X5R_08 C10 *22u_6.3V_X5R_08 22u_6.3V_X6S_08 2200p_50V_X7R_04 + PH3_UPI_9509 85A G2 INS16669230 C PR165 5 G2 Sheet 63 of 77 NVVDD 2 1 2 A DRVL 1 8 9 PGND GND SW D1 INS16668508 GPU DECOUPLING NVVDD G2ᶲ6柮 G1ᶲ4柮 2 CSOD140SH C699 C38 PC129 330uF_2V_5*5*4.2 22u_6.3V_X5R_08 C C21 P650RS/P670RS = G2 Phase P670RP6 = G1 Phase PC130 330uF_2V_5*5*4.2 22u_6.3V_X5R_08 22u_6.3V_X5R_08 C35 + PR155 *0_04 22u_6.3V_X5R_08 C66 + C *22u_6.3V_X5R_08 C11 22u_6.3V_X6S_08 NVVDD NVVDDS G1 => 2 + 1 G2 => 3 + 2 (default) + PC18 *220u_2V_SMD-V C22 *22u_6.3V_X5R_08 C23 22u_6.3V_X5R_08 + PC23 330U_2V_D2_D C24 PC19 *220u_2V_SMD-V B C67 PR153 PR163 PR158 PR160 *15_1%_06 *15_1%_06 *15_1%_06 *15_1%_06 G1ᶵ ᶵᶲẞ/G2ᶲ ᶲẞ PC27 *220u_2V_SMD-V *22u_6.3V_X5R_08 + 㓦暣䶂嶗 5VS *22u_6.3V_X5R_08 + NVVDD B 22u_6.3V_X6S_08 390u_2.5V_0S-CON PQ12 *QM3006M3 x x 28 pcs 10 pcs 5 5 5 5 PR157 *2K_04 [27,62] D 1 2 3 4 PQ13 *2SK3018S3 G NV_NVVDD_EN S B.Schematic Diagrams DRVH PWM 1 2 EEEFZ1E101P 4 PR156 0_04 EN D1 4.7u_25V_X7R_08 3 PW M3_1 PR166 0_04 BST 4.7u_25V_X7R_08 7 [62] VCC [62] 4.7u_25V_X7R_08 PU6 G2 UP1909PDN8 6 PH3_UPI_9509 + 4.7u_25V_X7R_08 PR161 1K_1%_04 0.1u_25V_X7R_06 ”NP-A”㗗NO PASTEMASK 3/7 co-layᶵᶲẞ ,ẍᾖ㬋footprint䁢PASTEMASK PC89 PC14 1u_25V_X7R_06 PC83 2.2u_16V_X5R_06 PC92 PC13 PC8 PC16 PC9 1u_25V_X7R_06 PC15 1000p_50V_X7R_04 1000p_50V_X7R_04 1000p_50V_X7R_04 1000p_50V_X7R_04 C 1000p_50V_X7R_04 1000p_50V_X7R_04 PD7 MDL914S2 A D 1 PW R_SRC_NV 5V PR154 2.2_06 2 layout 1pcs B2 慵䔲2PCS 0805 size + 5 PC87 *10u_6.3V_X5R_06 A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ [62] PW R_SRC_NV [23,28,62] NVVDD [10,11,12,13,36,39,40,41,47,48,49,50,61,62,64] 5VS [39,44,45,48,49,50,51,52,53,54,55,56,57,58,59] 5V [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57,64] 3.3VS [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 5 B - 64 NVVDD 2 4 3 2 Title Size A3 Date: [63] NVVDD PHASE 3~4 Document Number SCHEMATIC1 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 1 63 of 77 Schematic Diagrams FBVDDQ 1 2 3 4 5 6 7 8 1V8_AON FBVDDQ FOR N17_VGA PR231 *0_04 PR232 *0_04 PR225 0_04 NV_FBVDDQ_EN FB_ON PR241 [27] PC121 *10K_04 A A *0.1u_10V_X7R_04 4/7 power change ᶵᶲẞ UP1666_VREF 3/14 1K_04 EMI FBVDDQ_REFIN PR222 2_1%_04 9/6 2 3 4 UGATE1 PR246 PC125 PC126 1.1mm H, 7/26 PR221 FBVDDQ 1 12.1K_1%_04 *0.01u_50V_X7R_04 2200p_50V_X7R_04 PR218 100K_04 PC117 PR215 0_04 9 1 2 PCMB062D-R22MS PR229 0_04 5 6 7 1 BOOST1 3 2 EN 5 4 VID REFIN UGATE1 BOOT2 PR206 2.2_04 17 PC111 16 1u_6.3V_X5R_04 UGATE2 2 3 4 [53] 7/29 PR208 0_04 PC119 *4700p_50V_X7R_04 1000p_50V_X7R_04 C PR184 100K_04 PR220 PL4 1 2 PCMB062D-R22MS 13A 9 C 8 PR213 PC114 0_04 0.1u_25V_X7R_06 PR192 PR8 PR9 PR162 PR164 5.1_06 15_1%_06 15_1%_06 15_1%_06 15_1%_06 *75K_1%_04 PR216 51K_1%_04 *10K_04 5 6 7 *15.8K_1%_04 1 3.3VS PR219 *0_04 2A EMI PC118 PR217 PW R_SRC_NV_FB PR182 2_1%_04 PR223 *0_04 PS2_FBVDDQ_FB PR224 5VS 15 UGATE2 LGATE2 PHASE2 PVCC B + 4.7u_25V_X7R_08 qfn20-3x3mm-rt8816 PR226 1K_1%_04 2 *CV-40mil PSI 7 COMP 220p_50V_NPO_04 18 4.7u_25V_X7R_08 1 PJ26 FBVDDQ REX_0106 FB PGOOD 100_04 12 PVCC 14 PR233 11 PC120 *33p_50V_NPO_04 FBDRTN + PC105 0_04 *0_04 19 up1666QQKF FS/OC 4.7u_25V_X7R_08 100_04 PR243 LGATE1 PC90 PC108 PR239 VREF + 5.1_06 PQ15 SM7320ESQG LX1 0.1u_50V_Y5V_06 FBVDDQ_SENSE 10 FBDRTN PR230 *0_04 [28,53] 9 20 PC104 0_04 8 PR205 PHASE1 PC107 PR240 UP1666_VREF 45.3K_1%_04 13 0_04 PR237 GND *0.01u_50V_X7R_04 PR236 21 FBVDDQ_SENSE_RTN PC128 REFADJ Sheet 64 of 77 FBVDDQ 330U_2V_D2_D [28,53] UP1666_VREFADJ6 330U_2V_D2_D UP1666_VREF *499K_1%_1/16W _04 88.7K_1%_04 PC2 PR245 0.1u_10V_X7R_04 PR238 PW R_SRC_NV_FB 330U_2V_D2_D PU8 B PC85 PR167 PC84 8 0.1u_25V_X7R_06 1.35V 26A PC94 0_04 PL3 13A PR207 PQ20 SM7320ESQG PC109 *0_04 PR214 DGPU_PW RGD 220p_50V_NPO_04 [32] 5VS 0_04 FBVDDQ_REFIN PR6 PR5 from NV NV_FBVDDQ_EN 6 D 10K_04 PQ1A PR4 D 3/14 ADD follow NV ℔⚾ 5 G PQ1B MTDK3S6R 0_04 *10K_1%_04 PC1 2 5 5 5 5 D [3,8,9,10,11,12,13,26,30,31,32,33,34,35,36,37,38,39,41,43,46,47,48,49,50,57] 3.3VS [5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,53,54,56,59,60] VDD3 [53,61,62] PW R_SRC_NV_FB [10,11,12,13,36,39,40,41,47,48,49,50,61,62,63] 5VS [10,35,39,50,53,54,55,56,57,58,59,60] VIN [2,10,27,38,43,45,48,50,51,52,55,56] 3.3V [39,44,45,48,49,50,51,52,53,54,55,56,57,58,59,63] 5V [15,16,17,18,19,20,21,22,23,28] FBVDDQ [3,23,24,26,27,28,31,52,53,61,62] 1V8_AON [14,15,23,24,28,52] 1V8_RUN *0.01u_50V_X7R_04 1 PC82 *10u_6.3V_X5R_06 1 PR1 S 4 G PQ11 2SK3018S3 PC3 *0.01u_50V_X7R_04 S MTDK3S6R 3 H = 1.55V L = 1.35V PQ14 QM3006M3 4 78.7K_1%_04 0_04 2 G GPIO8_MEM_VDD_CTL 40.2k change to 78.8k (power change) PR3 PR2 *0_04 D [26] PR159 2K_04 3/14 S *1K_1%_04 PR7 Vout = Vref * (1 + Rtop / Rbot) 1.55V = 0.704V * (1 + (24.3K/20K)) 1.35V = 0.6096V * (1 + 24.3k/20K) 1 2 3 1V8_AON D 1V8_AON 3 4 5 6 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: [64] FBVDDQ(Power) Document Number SCHEMATIC1 7 Rev D02A 6-71-PA700-D02A W ednesday, July 05, 2017 Sheet 64 of 77 8 FBVDDQ B - 65 B.Schematic Diagrams 40.2K_1%_04 2 phase ᶵᶲẞ (power check) 3/18 10K_04 PR244 4.7u_25V_X7R_08 1u_6.3V_X5R_04 PC97 0.1u_50V_Y5V_06 *0_04 PC127 PR234 4.7u_25V_X7R_08 4.99K_1%_04 PR242 *3.92K_1%_04 PC96 PR228 4.7u_25V_X7R_08 1V8_AON PR235 PC95 UP1666_VREFADJ 2A PR227 PC124 *4700p_50V_X7R_04 power modify PC106 3/28 PW R_SRC_NV_FB 19.6k change to 4.99k (power change) Schematic Diagrams LED Board 5 4 3 2 1 FP225H-012S10M MLED_ACIN MLED_PW R MLED_BAT_CHG MLED_BAT_FULL MLED_NUM# MLED_CAP# MLED_SCROLL# M_W LAN_AIRPLANE# M_dGPU_LED MSATA_LED# 12 11 10 9 8 NC1 7 NC2 6 5 4 3 2 1 MJ_LED1 D MLED_GND M_3.3VS *0_04 4MR1 2MR1 *0_04 5MR1 *0_04 3MR1 *0_04 6MR1 *0_04 M_3.3VS MR10 220_04 220_04 MD7 㬋䄏 MD6 A MR11 220_04 A MR9 220_04 A MR8 220_04 MD8 MD5 MD4 RY-SP190YG34-5M RY-SP190YG34-5M RY-SP190YG34-5M NUM LOCK LED AIRPLANE LED HDD LED MR6 *0_04 C MLED_SCROLL# MLED_CAP# MLED_NUM# C C RY-SP190YG34-5M CAPS LOCK LED C RY-SP190YG34-5M SCROLL LOCK LED C RY-SP190YG34-5M dGPU LED C C *0_04 MR7 A MD9 C Sheet 65 of 77 LED Board A 220_04 1MR1 A MR5 M_W LAN_AIRPLANE# MSATA_LED# B M_dGPU_LED E B.Schematic Diagrams M:6-20-94K50-012 S:6-20-94K60-012 C D MQ1 DTC114EUA MLED_GND MD2 MLED_ACIN_R MR4 680_04 1 MR3 330_04 3 Oragne MLED_PW R_R 月LED䪗 䪗㒢㓦 Green MD1 *TVUDF1004AD0 MLED_ACIN MLED_PW R 1 2 3 MLED_BAT_CHG 4 MLED_BAT_FULL 5 UYG 4 RY-SP195UHYUYG4 B MLED_GND 2 UHY B AC IN/POWER ON LED 㬋䄏 10 9 8 7 6 MLED_GND MLED_GND MD3 MLED_BAT_CHG_R MR2 680_04 1 Oragne MLED_BAT_FULL_R Green 2 UHY MR1 330_04 3 UYG 4 RY-SP195UHYUYG4 BAT CHARGE/FULL LED 㬋䄏 MLED_GND MH1 *H4_0D2_2 A MH2 *H4_0D2_2 MH3 MH4 2 A 2 5 3 1 5 3 4 *MTH7_0D2_3 1 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ 4 *MTH7_0D2_3 Title MLED_GND MLED_GND MLED_GND Size A3 Date: 5 B - 66 LED Board 4 3 2 [65] PA7 LED BOARD_M Document Number SCHEMATIC1 Rev D02A 6-71-PA704-D02A W ednesday, July 05, 2017 Sheet 1 65 of 77 Schematic Diagrams LID Board 5 4 3 2 1 LID SWITCH IC D D VVDD3 PCB Footprint = FP226H-004XXXM_R FPC1004-4AW -S VR1 100K_04 VU1 VCC VC2 V_LID_SW # 2 VC1 AH9249NTR-G1 VD1 *100p_50V_NPO_04 2 *V15AVLC0402 VGND VGND VGND VGND 6-02-09249-LC0 PSU1, PSU2 3 1 2 C C VH1 VH3 *H4_0D2_2 *H4_0D2_2 1VR1 *0_04 VH4 VH2 2 2 5 4VR1 *0_04 3 1 5 1 3 4 2VR1 *0_04 5VR1 *0_04 3VR1 *0_04 6VR1 *0_04 *MTH7_0D2_3 VGND VGND 4 *MTH7_0D2_3 VGND B B A A Title Size A3 Date: 5 4 3 Sheet 66 of 77 LID Board 2 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ [66] LID BOARD_V Document Number Rev D02A 6-71-PA706-D02A W ednesday, July 05, 2017 Sheet 66 of 77 1 LID Board B - 67 B.Schematic Diagrams 0.1u_10V_X7R_04 OUT 1 1 GND VVDD3 VGND 4 NC2 3 NC1 2 1 VJ_LID1 3 V_LID_SW # Schematic Diagrams DC Board 1 2 3 4 5 6 7 8 DJ_DC_JACK1 A 1DR1 *0_04 A 4DR1 *0_04 1 2 3 4 5 6 7 8 DJ_DC_JACK2 2DR1 *0_04 5DR1 *0_04 3DR1 *0_04 6DR1 *0_04 1 GND3 2 GND1 GND2 GND4 B.Schematic Diagrams 207B07BHB0A PCB Footprint = 2DC-G213-B48 50299-00801-004 DGND Sheet 67 of 77 DC Board DH1 DH2 *H7_0D2_3 *H7_0D2_3 B B DGND DGND C C D D ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 1 B - 68 DC Board 2 3 4 5 6 [67] DC BOARD_D Document Number SCHEMATIC1 7 Rev D02A 6-71-PA70C-D02A W ednesday, July 05, 2017 Sheet 67 of 8 77 Schematic Diagrams Power Board 5 4 3 2 1 B3.3VS BJ_BTN1 1 2 3 4 BM_BTN# D B3.3VS NC1 NC2 D 20mil FPC1004-4AW -S fp226h-004xxxm_l BR1 220_04 BGND 20mil POWER BUTTON B_SW 1 TJE-532-Q-T/R 1 3 BC2 2 4 *0.1u_10V_X7R_04 6 1 2 BGND D02㓡 㓡䘥 BD1 BC1 A PCB Footprint = tje-53x-q A 1 5 6 BM_BTN# BD3 0.1u_50V_Y5V_06 BGND BD2 *V15AVLC0402 RY-SP190DBW 71-5A RY-SP190DBW 71-5A C C 2 VARISTOR 6-24-30003-006 BGND P2808A1, 㛔幓㚫䅺㭨, P2808A1 ⮵䫾 D26 mounted VARISTOR. C BGND BGND C Sheet 68 of 77 Power Board 6-53-3050B-B41 100g 1 3 5 6 BH3 2 5 3 1 4BR1 *0_04 5BR1 *0_04 *0_04 3BR1 *0_04 6BR1 *0_04 5 1 3 2 4 4 *MTH7_0D2_3 *0_04 2BR1 BH4 BH1 *H4_0D2_2 *H4_0D2_2 BH2 2 B 1BR1 4 B *MTH7_0D2_3 BGND BGND BGND A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 5 4 3 2 [68] POWER BOARD_B Document Number SCHEMATIC1 Rev D02A 6-71-PA70S-D02A W ednesday, July 05, 2017 Sheet 68 of 77 1 Power Board B - 69 B.Schematic Diagrams 3 4 20mil B_SW1 5 Schematic Diagrams Click Board 5 4 3 TO M/B NC1 NC2 1 2 3 4 TO M/B 1 2 3 4 5 6 T_TP_BTN_R TO T/P 8 PIN T_TP_VCC T_TP_DATA T_TP_CLK T_TP_SMB_DAT T_TP_SMB_CLK FPC0502-6AW -S-HF fp225h-006xxxm M:6-20-94K10-006 S:6-20-94K00-006 B.Schematic Diagrams 1 T_TP_VCC TJ_TP1 T_TP_BTN_L FP226H-004S10M JXT_FP226H-004XXAM TGND M:6-20-94A40-004 S:6-20-94A60-004 TJ_MB1 D 2 W/O FP㗪 㗪 ⎒ᶲ 㬌⋨ 暞 ẞ TJ_CLICK1 TH2 *H7_0D2_3 1 2 3 4 5 6 7 8 T_TP_CLK_J T_TP_DATA_J T_TP_BTN_L T_TP_BTN_R T_TP_SMB_CLK_J T_TP_SMB_DAT_J FP225H-008S11M fp225h-008gxxxm_R TH1 *H7_0D2_3 TGND TD1 *TVUDF1004AD0 6-20-94K30-108 TC1 0.1u_10V_X7R_04 TGND TGND TGND TGND T_TP_CLK_J 10 T_TP_DATA_J 9 8 T_TP_SMB_CLK_J 7 T_TP_SMB_DAT_J 6 D 1 T_TP_CLK 2 T_TP_DATA 3 4 T_TP_SMB_CLK 5 T_TP_SMB_DAT TGND CLICK B'D Sheet 69 of 77 Click Board C C B B jack_12/13 1TR1 *0_04 4TR1 *0_04 2TR1 *0_04 5TR1 *0_04 3TR1 *0_04 6TR1 *0_04 A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 5 B - 70 Click Board 4 3 2 [69] PA7 CLICK BOARD_T Document Number SCHEMATIC1 Rev D02A 6-71-PA702-D02A W ednesday, July 05, 2017 Sheet 1 69 of 77 Schematic Diagrams Audio Board 5 4 3 2 1 E_AUDG EJ_SPDIF1 ESIDE_R ESIDE_L FPC0502-16AW -S-HF EL2 EL1 E_5VS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D ESIDE_SENSE E_5VS 100p_50V_NPO_04 100p_50V_NPO_04 EC1 E_AUDG ESPDIFO 6 1 4 7 5 FCM1005KF-121T03 FCM1005KF-121T03 EC4 A B C ESPDIFO EGND EMIC1_R EMIC1_L EJD_SENSEA EJD_SENSEB ESIDE_R DRIVE IC TX 2SJ3011-003111F EC3 D *0.1u_10V_X7R_04 ESIDE_L EC2 *100p_50V_NPO_04 EJD_SENSEA ER11 EJD_SENSEB ER12 39.2K_1%_04 EHP_SENSE ER13 5.1K_1%_04 ESIDE_SENSE EHEADPHONE-R EHP_AUDG EHEADPHONE-L EMIC_SENSE 20K_1%_04 EGND EGND EJ_AUDIO1 EJ_MIC1 EMIC1_R EMIC1_L EL4 EL3 EC9 EMIC_SENSE EC10 100p_50V_NPO_04 Sheet 70 of 77 Audio Board 1 2 3 4 5 FCM1005KF-121T03 FCM1005KF-121T03 100p_50V_NPO_04 2SJ3006-008311F C C E_AUDG E_AUDG E_AUDG EHP_SENSE EQ1 2SK3018S3 ED54 C G S Resistor 68_04 meet WLK Test B D D02A_0329_WEY RB751S-40H A ER10 47K_04 B EJ_HP1 1 2 3 4 5 E_AUDG EHEADPHONE-R EHEADPHONE-L ER8 ER7 68_04 68_04 EPHONE_R EPHONE_L EL6 EL5 FCM1005KF-121T03 FCM1005KF-121T03 EC8 ER5 EC7 D01A_0214 ER6 *100p_50V_NPO_04 *100p_50V_NPO_04 22K_04 22K_04 2SJ3006-008311F E_AUDG E_AUDG E_AUDG E_AUDG EHP_AUDG D02A_0418_WEY *0_04 ER14 EC5 0.1u_10V_X7R_04 EC12 0.1u_10V_X7R_04 EC11 0.1u_10V_X7R_04 EC6 0.1u_10V_X7R_04 A A E_AUDG ER9 1ER1 *0_04 4ER1 *0_04 2ER1 *0_04 5ER1 *0_04 3ER1 *0_04 6ER1 *0_04 EH3 *H4_2D2_2 EH2 *H4_2D2_2 EH4 *H8_0D2_8 EH1 *H8_0D2_8 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ 0_04 EGND E_AUDG Title EGND EGND EGND Size A3 EGND Date: 5 4 3 2 [70] AUDIO BOARD_E Document Number SCHEMATIC1 Rev D02A 6-71-PA708-D02A W ednesday, July 05, 2017 Sheet 70 of 77 1 Audio Board B - 71 B.Schematic Diagrams E_AUDG Schematic Diagrams USB Board USB3.0 PORT1 W USB_PN1 W USB_PP1 W GND W L2 4 4 5 W D2 10 9 8 W GND W USB_PN1_CON 7 W USB_PP1_CON 6 3 1 2 *W CM2012F2S-161T03-short W 5V 1 2 3 4 5 W USBVCC_CH KAI_12/07 W U1 W GND W USB_PN1_J W USB_PP1_J 5 W C4 VIN VOUT 1 W C10 10u_6.3V_X5R_06 GND W DD_ON# W GND 4 EN# OC# 3 uP7549UMA5-20 PCB Footprint = M-SOT23-5 A + W C3 2 TVUDF1004AD0 W GND W GND W D3 W C11 W C12 W GND 10 9 8 7 6 W RXN1_J W RXP1_J 1 2 3 4 5 W C8 22u_6.3V_X5R_08 W J_USB3_1 377AH09FZT S4NVCB W GND PCB Footprint = 317AH09FZTS4T4CX W TXP1_J W USB3_RXN1 W USB3_RXP1 W USB3_TXN1 0.1u_10V_X7R_04 W USB3_TXP1 0.1u_10V_X7R_04 W C6 22u_6.3V_X5R_08 *EEFCX0J221YR 9 1 8 2 4 3 6 7 5 W TXN1_J W USB_PN1_J W GND W TXN1_J W TXP1_J W USB_PP1_J W RXP1_J TVUDF1004AD0 W RXN1_J USB3.0 Max Trace length Follow Design Guide SSTX+ VBUS SSTXDGND D+ SSRX+ GND_D SSRX- SHIELD SHIELD Standard-A Sheet 71 of 77 USB Board PCB Footprint = FP225H-030GXXM FP225H-030S10M W USB3_TXP5 30 30 29 W USB3_TXN5 29 28 28 27 W USB3_RXN5 27 26 W USB3_RXP5 26 25 25 24 W USB_PP5 24 23 W USB_PN5 23 22 22 21 W USB3_TXP1 21 20 W USB3_TXN1 20 19 19 18 W USB3_RXP1 18 17 W USB3_RXN1 17 16 16 15 W USB_PN1 15 14 W USB_PP1 14 13 W DD_ON# 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 W 5V 2 1 1 3 SHIELD SHIELD GND1 GND3 GND4 GND2 W GND W GND W J_USB1 B B USB3.0 PORT5 W USBVCC3.0_6 3/18 ㍉岤⺢嬘ἧ䓐20KV ESD W U2 5 W 5V VIN VOUT 100 MIL 1 W C9 W C1 10u_6.3V_X5R_06 W D1 *W CM2012F2S-161T03-short 4 3 W USB_PN5 W USB_PP5 1 2 W USB_PN5_CON W USB_PP5_CON W L1 W GND 10 9 8 7 6 C GND 4 W GND OC# 0.1u_10V_X7R_04 W GND 2A/90mohm W GND W DD_ON# W R1 *0402_short W C7 W C5 W USBVCC3.0_6 CLOSE TO CONNECTOR W TXP5_J ⚈⍾㴰co-lay, ⎴㬍⍾㴰暣⭡ 9 1 8 2 4 3 6 7 5 W TXN5_J W USB_PN5_J TVUDF1004AD0 W C14 W C13 W GND W USB3_RXP5 W USB3_RXN5 6 7 8 9 10 5 4 3 2 1 W USB_PP5_J W RXP5_J W TXP5_J W TXN5_J W RXN5_J W GND W RXP5_J W RXN5_J USB3.0 Max Trace length Follow Design Guide W D4 ⍾㴰co-lay, ⚈䃉layout䨢 䨢攻 4W R1 *0_04 GND1 GND3 GND4 GND2 W GND USB3.0 connect 㓡䓐UBS3.1 connect䓐㕁 (ME change) 2W R1 *0_04 5W R1 *0_04 3W R1 *0_04 6W R1 *0_04 D ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title W GND W GND [71] USB3.0 BOARD_W W GND Size A3 Date: B - 72 USB Board SSTX+ SHIELD VBUS SHIELD SSTXDGND D+ SSRX+ GND_D SHIELD SSRX- SHIELD W H1 W H4 W H2 W H3 *H8_0D2_8 *H8_0D2_8 *H5_0D2_2*H5_0D2_2 1W R1 *0_04 W GND 1 22u_6.3V_X5R_08 W GND W J_USB3_2 377AH09FZT S4NVCB PCB Footprint = 317AH09FZTS4T4CX W GND 3/15 3/22 lay swap D 22u_6.3V_X5R_08 C TVUDF1004AD0 W USB3_TXP5 0.1u_10V_X7R_04 W USB3_TXN5 0.1u_10V_X7R_04 *EEFCX0J221YR 3 uP7549UMA5-20 PCB Footprint = M-SOT23-5 W USB_PN5_J W USB_PP5_J 1 2 3 4 5 EN# + W C2 2 Standard-A B.Schematic Diagrams A 2 0.1u_10V_X7R_04 1 2 3 4 Document Number Rev D02A 6-71-PA703-D12A W ednesday, July 05, 2017 Sheet 5 71 of 77 Schematic Diagrams USB 3.0 Board 1 3 4 5 㷔娎䓐,MPᶵ ᶵ⮶ℍ. USB3.0 PORT1 ZR8 *0_04 ZR11 2K_1%_04 *4.7K_04 *4.7K_04 Z5V ZGND ZUSBVCC_CH ZU1 5 ZC1 VIN VOUT ZC5 10u_6.3V_X5R_06 *0_04 ZR1 *0_04 4 5 6 GND DE_A SW_A EN_RXD VCC TX2TX2+ 13 Reserverd DE_B SW_B 14 RX2+ ZJ_USB1 ZR5 3 RX2- 15 19 EQ_B 20 ZC19 GND ZC18 0.1u_10V_X7R_04 CHIP_EN# ZI2C_SCK_P1 ZC16 9 ZR7 *4.7K_04 ZC15 ZGND ZGND Z3.3V 9 1 8 2 4 3 6 7 5 ZTXN1_J ZUSB_PN1_J 11 ZC14 0.1u_10V_X7R_04 ZUSB3_RXN1 ZC12 ZC11 12 ZC13 0.1u_10V_X7R_04 ZUSB3_RXP1 0.01u_50V_X7R_04 0.1u_10V_X7R_04 ZC17 ZUSB_PP1_J ZRXP1_J 1u_6.3V_X5R_04 ZRXN1_J ASM1464 PCB Footprint = QFN24-4X4MM ZR4 ZR3 ZR2 USB3.0 Max Trace length Follow Design Guide ZGND *4.7K_04 *4.7K_04 *4.7K_04 SSTX+ VBUS SSTXDGND D+ SSRX+ GND_D SSRX- ZGND ZUSB_PN1_CON ZUSB_PP1_CON ZL1 ZUSB_PP1 1 2 *W CM2012F2S-161T03-short 4 3 USB3.0 PORT5 10 9 8 7 6 1 2 3 4 5 ZGND 10 9 8 7 6 ZRXN1 ZRXP1 ZGND ZUSB_PN1_J ZUSB_PP1_J ZTXN1 ZTXP1 ZGND TVUDF1004AD0 ZC30 2K_1%_04 VIN 100 MIL 1 VOUT ZC7 ZC6 10u_6.3V_X5R_06 EN# + ZC10 2 GND 0.1u_10V_X7R_04 OC# ZRXP5 0.1u_10V_X7R_04 ZC39 19 ZC29 ZC35 4 5 6 GND DE_A SW_A 2 3 1 VCC TX1+ RX+ TYPE_IND# CHIP_EN# RX2RX2+ *0_04 TX2TX2+ 7 ZSCK_P4 ZC26 0.1u_10V_X7R_04 ZUSB3_TXN5 9 ZC25 0.1u_10V_X7R_04 ZUSB3_TXP5 10 *4.7K_04 C 0.1u_10V_X7R_04 ZUSB3_RXN5 12 ZC23 0.1u_10V_X7R_04 ZUSB3_RXP5 ZTXP5_J ZUSB_PN5_J ZUSB_PP5_J ZRXP5_J Z3.3V *4.7K_04 *4.7K_04 *4.7K_04 ZRXN5_J USB3.0 Max Trace length Follow Design Guide ZC38 ZC22 ZC40 0.01u_50V_X7R_04 0.1u_10V_X7R_04 1u_6.3V_X5R_04 *0_04 4 3 ZL2 ZUSB_PN5 1 2 *W CM2012F2S-161T03-short ⍾㴰co-lay, ⚈䃉layout䨢 䨢攻 1ZR1 *0_04 4ZR1 *0_04 2ZR1 *0_04 5ZR1 *0_04 3ZR1 *0_04 6ZR1 *0_04 ZUSB_PP5_CON 10 ZUSB_PN5_CON 9 8 ZGND 7 6 ZH4 ZH1 ZH3 ZH2 *H8_0D2_8 *H8_0D2_8 *H5_0D2_2 *H5_0D2_2 GND4 GND2 ZGND TVUDF1004AD03/18 ㍉岤⺢嬘ἧ䓐20KV ESD 1 2 3 4 5 ZUSB_PP5_J ZUSB_PN5_J ZTXP5 ZTXN5 ZGND ZRXP5 ZRXN5 ZGND 6 7 8 9 10 5 4 3 2 1 ZTXP5_J ZTXN5_J ZGND ZRXP5_J ZRXN5_J D TVUDF1004AD0 ZD4 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title ZGND ZGND ZGND Size A3 ZGND Date: 2 GND1 GND3 USB3.0 connect 㓡䓐UBS3.1 connect䓐㕁 (ME change) ZD2 ZUSB_PP5 SSTX+ SHIELD VBUS SHIELD SSTXDGND D+ SSRX+ GND_D SHIELD SSRX- SHIELD ZGND 3/15 ZGND 1 9 1 8 2 4 3 6 7 5 ⚈⍾㴰co-lay, ⎴㬍⍾㴰暣⭡ Z3.3V ZC28 ZC31 ZC33 22u_6.3V_X5R_08 ZGND ZJ_USB3_2 377AH09FZT S4NVCB PCB Footprint = 317AH09FZTS4T4CX CLOSE TO CONNECTOR From PCH ZC24 ZC8 ZUSBVCC3.0_6 ZGND 11 ASM1464 PCB Footprint = QFN24-4X4MM 22u_6.3V_X5R_08 ZGND ZGND D *0402_short ZC9 8 ZC27 ZR12 Standard-A 20 VCC ZC37 18 0.1u_10V_X7R_04 RX1- 13 21 To Conn. ZRXN5 EN_RXD 22 ZDD_ON# SMB_SCK Reserverd ZC43 SW_B 0.1u_10V_X7R_04 DE_B ZTXP5 TX1- 14 23 15 ZC42 EQ_A ZSDA_P4 EQ_B *4.7K_04 0.1u_10V_X7R_04 GND ZC41 ZTXN5 16 ZGND 17 C ZGND 2A/90mohm ZGND *EEFCX0J221YR 3 uP7549UMA5-20 PCB Footprint = M-SOT23-5 GND SMB_DATA ZGND ZTXN1_J ZTXP1_J ZUSBVCC3.0_6 ZU2 5 Z5V *0_04 ZGND 25 24 B ZRXN1_J ZRXP1_J 1 2 3 4 5 Sheet 72 of 77 USB 3.0 Board TVUDF1004AD0 4 ZU4 GND4 GND2 SHIELD SHIELD ZD3 3/18 ㍉岤⺢嬘ἧ䓐20KV ESD ZC36 *4.7K_04 *4.7K_04 ZGND GND1 GND3 SHIELD SHIELD ZGND ZD1 ZUSB_PN1 ZC4 22u_6.3V_X5R_08 ZJ_USB3_1 377AH09FZT S4NVCB ZGND PCB Footprint = 317AH09FZTS4T4CX ZTXP1_J ZGND ZGND ZC34 ZC32 OC# Z3.3V B Z3.3V EN# ZC3 22u_6.3V_X5R_08 *EEFCX0J221YR ZUSB3_TXP1 0.1u_10V_X7R_04 10 ZGND ZUSB3_TXN1 0.1u_10V_X7R_04 3 A + ZC2 2 3 4 [72] USB3.0 BOARD(W/REDRIVER)_Z Document Number Rev D02A 6-71-PA703-D02A W ednesday, July 05, 2017 Sheet 72 of 77 5 USB 3.0 Board B - 73 B.Schematic Diagrams 0.1u_10V_X7R_04 ZRXP1 RX+ TYPE_IND# 7 8 4 uP7549UMA5-20 PCB Footprint = M-SOT23-5 ZGND RX1- TX1+ 21 ZRXN1 2 VCC 22 ZC21 To Conn. ZDD_ON# ZGND SMB_SCK TX1- 16 0.1u_10V_X7R_04 GND SMB_DATA 23 ZC20 17 ZTXP1 0.1u_10V_X7R_04 EQ_A ZU3 ZTXN1 25 24 *4.7K_04 ZI2C_SDA_P1 ZR6 ZGND 1 GND ZGND 1 Standard-A ZR9 ZR10 0.1u_10V_X7R_04 Z3.3V 18 A 2 PCB Footprint = FP225H-030GXXM FP225H-030S10M ZUSB3_TXP5 30 30 29 ZUSB3_TXN5 29 28 28 27 ZUSB3_RXN5 27 26 ZUSB3_RXP5 26 25 25 24 ZUSB_PP5 24 23 ZUSB_PN5 23 22 22 21 ZUSB3_TXP1 21 20 ZUSB3_TXN1 20 19 19 18 ZUSB3_RXP1 18 17 ZUSB3_RXN1 17 16 16 15 ZUSB_PN1 15 14 ZUSB_PP1 14 13 ZDD_ON# 13 12 12 11 Z3.3V 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 Z5V 2 1 1 Schematic Diagrams PA7 Card Reader Board 1/4 1 2 3 4 5 6 7 8 LAN Board GIGA LAN LAN (RTL8111G) NXTAL2 NXTAL1 NVDD10 NVDD10 NC5 NC1 NC9 NVDD10 NGND NVDD10 NVDD10 NLED1/GPO NC8 NR11 NC6 NGND NLAN_MDIP0 NLAN_MDIN0 NLAN_MDIP1 NLAN_MDIN1 NLAN_MDIP2 NLAN_MDIN2 Sheet 73 of 77 PA7 Card Reader Board 1/4 32 31 30 29 28 27 26 25 RTL8111G QFN32 REG_OUT VDDREG DVDD10 LANWAKEB ISOLATEB PERSTB HSON HSOP 24 23 22 21 20 19 18 17 NC11 RTL8111G-CG NVDDREG/VDD33 NR8 NR7 1K_04 N3.3VS 15K_1%_04 NGND NBUF_PLT_RST# NPCIE_RXN5_GLAN NPCIE_RXP5_GLAN *0402_short 0.1u_10V_X7R_04 0.1u_10V_X7R_04 NLAN_MDIN2 NBUF_PLT_RST# [76] NLAN_MDIP2 NPCIE_RXN5_GLAN [76]NLAN_MDIN3 NPCIE_RXP5_GLAN [76]NLAN_MDIP3 6 5 3 2 NLAN_W AKEUP# [76] 40 mil NCLK_PCIE_GLAN# [76] NCLK_PCIE_GLAN [76] NPCIE_TXN5_GLAN NPCIE_TXP5_GLAN NLAN_CLKREQ# NR3 NGND PIN32 NGND 10p_50V_NPO_04 1 2 4 3 NX1 FSX3L 25MHZ NGND +3V_LAN_IO Rising time (10%~90%)天>0.5mS and <100mS. NREGOUT NGND 4 NR5 NC7 Cc MX4MX4+ MX3MX3+ TD2TD2+ TD1TD1+ MX2MX2+ MX1MX1+ TCT4 TCT3 TCT2 TCT1 MCT4 MCT3 MCT2 MCT1 13 14 16 17 NLMX1NLMX1+ NLMX2NLMX2+ 19 20 22 23 NLMX3NLMX3+ NLMX4NLMX4+ 15 18 21 24 NNMCT_4 NNMCT_3 NNMCT_2 NNMCT_1 4 Ra NVDD10 *15mil_short (>60mil) 0.1u_10V_X7R_04 A Lawrence_0105 NGND NEML4 3 NDLMX1- 1 2 NDLMX1+ *W CM2012F2S-SHORT TD4TD4+ TD3TD3+ 10 7 4 1 NC49 NEML3 3 1 2 *W CM2012F2S-SHORT NJ_RJ1 NDLMX2NDLMX2+ 4 NEML2 3 NDLMX3- 1 2 NDLMX3+ *W CM2012F2S-SHORT 4 3 NEML1 NDLMX4- NDLMX1+ NDLMX1NDLMX2+ NDLMX2- 1 2 3 6 NDLMX3+ NDLMX3NDLMX4+ NDLMX4- 4 5 7 8 DA+ DADB+ DB- shield shield GND1 GND2 C10202-10839-L 75_1%_04 75_1%_04 75_1%_04 75_1%_04 NNMCT_R NC15 100PF 2KV 1206 NGND NGND DC+ DCDD+ DD- 1 2 NDLMX4+ *W CM2012F2S-SHORT NR15 NR14 NR13 NR12 NS892402 0.01u_16V_X7R_04 1M_04 NGND NC3 [76] N3.3VS *10K_04 [76] [76] NXTAL1 NC52 NGND NXTAL2 NLAN_CLKREQ# NR10 NLAN_W AKEUP# 12 11 9 8 meet realtek Freq tolerance 50ppm NPCIE_TXN5_GLAN NPCIE_TXP5_GLAN NAVDD33 NGND PIN11 GIGA LAN NLAN_MDIN0 NLAN_MDIP0 NLAN_MDIN1 NLAN_MDIP1 capacitors must be close to pin side. NCLK_PCIE_GLAN# NCLK_PCIE_GLAN NLAN_MDIP3 NLAN_MDIN3 B NREGOUT NVDDREG/VDD33 NVDD10 *0.1u_10V_X7R_04 NGND NLAN_W AKEUP# NISOLATEB NPERSTB NR9 NRTL8411B_HSON NC12 NRTL8411B_HSOP NC13 MDIP3 MDIN3 AVDD33 CLKREQB HSIP HSIN REFCLK_P REFCLK_N NVDD10 MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 MDIP2 MDIN2 AVDD10 NC51 NL3 NREGOUT W>40mil 9 10 11 12 13 14 15 16 B.Schematic Diagrams NVDD10 1 2 3 4 5 6 7 8 E_PAD AVDD33 RSET AVDD10 CKXTAL2 CKXTAL1 LED0 LED1/GPO LED2 NU1 NC14 NR6 NC4 *1u_6.3V_X5R_04 0.1u_10V_X7R_04 PIN22 PIN30 NGND NGND (W>60mil L<200mil) 60 mil *15mil_short NLED2 33 NAVDD33 LDO Mode NC10 NVDD3 *4.7u_6.3V_X5R_06 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 Pin#32 PIN3 PIN8 PIN22 NGND NGND NGND NGND *4.7u_6.3V_X5R_04 NAVDD33 NAVDD33 *4.7u_6.3V_X5R_04 2.49K_1%_04 *1K_04 [76] 0.1u_10V_X7R_04 NR2 NR4 NGCLK_25M_GLAN 0.1u_10V_X7R_04 A NRSET NLED0 *0_04 *0_04 *15mil_short 3.3VS:50mA NVDD10 VDD3:700mA NR1 NR40 B NC2 NGND 10p_50V_NPO_04 NGND NVDD3 N3.3VS [76] [76] C C D D ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title Size A3 Date: 1 B - 74 2 3 4 5 6 [73] PA7 LAN BOARD_N 1/4 Document Number SCHEMATIC1 7 Rev D02A 6-71-PA70Z-D02A W ednesday, July 05, 2017 Sheet 73 of 8 77 Schematic Diagrams PA7 Card Reader Board 2/4 5 4 3 2 NVDD5 1 USB3.0 PORT6 NVDD5 NEMC3 NEMC4 *100p_50V_NPO_04 *0.1u_10V_X7R_04 (MB⎛ ⎛ᶳ) NUSBVCC3.0_6 NU4 NGND NGND 5 NVDD5 VIN VOUT 100 MIL 1 NC23 D NC24 10u_6.3V_X5R_06 GND 4 EN# NGND OC# D 2 0.1u_10V_X7R_04 3 uP7549UMA5-20 PCB Footprint = M-SOT23-5 NGND 2A/90mohm NDD_ON# NDD_ON# NR22 *0402_short NC26 NGND 9 1 8 2 4 3 6 7 5 NTXN6_J NUSB_PN6_J NUSB_PP6_J NRXP6_J NRXN6_J USB3.0 Max Trace length Follow Design Guide SSTX+ VBUS SSTXDGND D+ SSRX+ GND_D SSRX- GND1 SHIELD GND2 SHIELD GND3 SHIELD GND4 SHIELD C NGND C19009-90905-L NGND Sheet 74 of 77 PA7 Card Reader Board 2/4 ND2 [76] NUSB_PN6 [76] NUSB_PP6 NUSB_PN6 NUSB_PN6_CON10 NUSB_PP6_CON 9 8 NGND 7 6 4 3 NL2 NUSB_PP6 1 2 *W CM2012F2S-161T03-short NUSB_PN6_J NUSB_PP6_J 1 2 3 4 5 NGND TVUDF1004AD0 ND4 [76] [76] NUSB3_TXP6 NUSB3_TXN6 NC56 NC55 [76] [76] B 0.1u_10V_X7R_04 0.1u_10V_X7R_04 NUSB3_RXP6 NUSB3_RXN6 NGND NUSB3_RXP6 NUSB3_RXN6 10 9 8 7 6 3/18 ㍉岤⺢嬘ἧ䓐20KV ESD NTXP6_J NTXN6_J 1 2 3 4 5 NGND NRXP6_J NRXN6_J B TVUDF1004AD0 SLG55593VTR USB Charging PORT A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title [75,76] Size A3 Date: 5 4 3 [74] PA7 USB3.0 N 2/4 NVDD5 2 Document Number Rev D02A 6-71-PA70Z-D021A W ednesday, July 05, 2017 Sheet 74 of 77 1 PA7 Card Reader Board 2/4 B - 75 B.Schematic Diagrams NTXP6_J C 22u_6.3V_X5R_08 NJ_USB3_2 CLOSE TO CONNECTOR ⚈⍾㴰co-lay, ⎴㬍⍾㴰暣⭡ 22u_6.3V_X5R_08 NC25 NUSBVCC3.0_6 Standard-A [75,76] Schematic Diagrams PA7 Card Reader Board 3/4 5 4 3 2 NVDD5 1 USB3.0 PORT4 NVDD5 NEMC2 NEMC1 *100p_50V_NPO_04 *0.1u_10V_X7R_04 (MB⎛ ⎛ᶳ) D02A_0329_CF NUSBVCC3.0_4 NU3 NGND NGND 5 NVDD5 VIN VOUT 100 MIL 1 NC19 NC18 10u_6.3V_X5R_06 D GND 4 EN# NGND OC# 2 D 0.1u_10V_X7R_04 3 uP7549UMA5-20 PCB Footprint = M-SOT23-5 NGND 2A/90mohm *0402_short NC21 NTXP4_J ⚈⍾㴰co-lay, ⎴㬍⍾㴰暣⭡ 22u_6.3V_X5R_08 9 1 8 2 4 3 6 7 5 NTXN4_J NUSB_PN4_J NUSB_PP4_J NRXP4_J NRXN4_J SSTX+ VBUS SSTXDGND D+ SSRX+ GND_D SSRX- GND1 SHIELD GND2 SHIELD GND3 SHIELD GND4 SHIELD C USB3.0 Max Trace length Follow Design Guide NGND NJ_USB3_1 CLOSE TO CONNECTOR Sheet 75 of 77 PA7 Card Reader Board 3/4 22u_6.3V_X5R_08 NC20 Standard-A NR20 NUSBVCC3.0_4 C NGND C19009-90905-L NGND ND1 W/ USB CHARGER NUSB_PN4_R 4 3 NL1 NUSB_PP4_R 1 2 *W CM2012F2S-161T03-short NVDD5 NUSB_PN4_CON10 NUSB_PP4_CON 9 8 NGND 7 6 1 2 3 4 5 NUSB_PN4_J NUSB_PP4_J NGND TVUDF1004AD0 ND3 NR19 10K_04 NU2 NDD_ON [76] NUSB_PN4 [76] NUSB_PP4 B NUSB_PN4 7 NUSB_PP4 6 5 NVDD5 NC17 CB PRE# TDM DM TDP DP VCC SLG55593VTR PCB Footprint = TDFN8-2X2MM GND 8 [76] CDP Default Low 1 NUSB_PP4_R 3 NC54 NC53 NUSB3_TXP4 NUSB3_TXN4 NUSB_DD_ON# [76] [76] NUSB3_RXP4 NUSB3_RXN4 0.1u_10V_X7R_04 10 0.1u_10V_X7R_04 9 8 NGND NUSB3_RXP4 7 NUSB3_RXN4 6 NR16 100K_04 3/18 ㍉岤⺢嬘ἧ䓐20KV ESD 1 2 3 4 5 NTXP4_J NTXN4_J NGND NRXP4_J NRXN4_J B TVUDF1004AD0 4 SLG55593VTR USB Charging PORT NGND 䚖⇵ἧ䓐㬌㕁SLG55593VTR :6-02-55593-9D0 0.1u_10V_X7R_04 [76] [76] NUSB_PN4_R 2 9 B.Schematic Diagrams NUSB_DD_ON# NGND NGND [74,76] NUSB_PN4 NUSB_PP4 NDD_ON# NDD_ON# NR38 NR39 NR21 *0_04 *0_04 *0_04 NUSB_PN4_R NUSB_PP4_R NUSB_DD_ON# A A ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title NVDD5 [74,76] Size A3 Date: 5 B - 76 PA7 Card Reader Board 3/4 4 3 2 [75] PA7 USB3.0/SIM BOARD_N 3/4 Document Number SCHEMATIC1 Rev D02A 6-71-PA70Z-D02A W ednesday, July 05, 2017 Sheet 1 75 of 77 Schematic Diagrams PA7 Card Reader Board 4/4 2 3 4 N3.3VS NR28 D NSD_W P/MS_BS NCR1_LEDN NR32 NSD_CD# NMS_INS# NSD_LN0_P NSD_LN0_M 10K_04 S 10K_04 32 31 30 29 28 27 26 25 100ohm +/- 15% NBUF_PLT_RST# PCH䪗ᶲẞ 1 NR27 *10K_04 NSD40_CLKREQ# 2 NPCIE_TXP6_SD40 3 NPCIE_TXN6_SD40 4 NCLK_PCIE_SD40 5 NCLK_PCIE_SD40# 6 NC30 0.1u_10V_X7R_04 N_RTS5249_HSOP7 NC29 0.1u_10V_X7R_04 N_RTS5249_HSON8 PERST# CLKREQ# HSIP HSIN REFCLKP REFCLKN HSOP HSON 0_04 NC35 4.7u_6.3V_X5R_06 0.1u_10V_X7R_04 | DATA.x - DATA.y | <= 100mils NGND 20 mil 24 23 22 21 20 19 18 17 NSDREG2 NSD_LN1_M NSD_LN1_P100ohm NSP6 NR24 NSP5 NR25 NSP4 NR30 NDV33_18 NSP3 NC46 NSD_D2/MS_CLK NSD_D3/MS_D3 NSD_CMD/MS_D2 NC45 1u_6.3V_X5R_04 0_04 0_04 0_04 20 mil NR36 *5p_50V_NPO_04 9 10 11 12 13 14 15 16 0618 VALUE UPDATE RTS5250-GR NC33 4.7u_6.3V_X5R_06 0.1u_10V_X7R_04 NC39 40 mil NC48 NSD_VDD2 4.7u_6.3V_X5R_06 NGND 1.2A 60 mil NC32 NGND N_CARD_3V3 VIC_0104 NGND NGND 6-21-A4710-120 10u_6.3V_X5R_06 NEAR PIN11 NGND NGND A 21 22 23 24 PSDCT1-20GLBS1NN4H0 NGND 100ohm +/- 15% NC37 20 mil 4.7u_6.3V_X5R_06 NDV12_S NVCC_CARD 0.1u_10V_X7R_04 0.1u_10V_X7R_04 NGND NCARD_3V3 NC42 Near Cardreader CONN NGND NR31 NC34 40 mil 0.2R_5%_06 4.7u_6.3V_X5R_06 B NVCC_CARD NR37 NGND 0.1u_10V_X7R_04 0.1u_10V_X7R_04 NGND NSD_CMD/MS_D2 NSD_LN0_M NSD_D3/MS_D3 NSD_LN0_P NSD_D2/MS_CLK WP DAT1/RCLKDAT0/RCLK+ VSS5 VSS2 D1+ CLK D1VDD1 VDD2 VSS1 CD VSS4 CMD D0CD/DAT3 D0+ GND1 DAT2 GND2 VSS3 GND3 GND GND4 NC36 40 mil NC31 NSD_CD# NC38 NGND NSD_D0/SD_RCLK_P NSD_D1/SD_RCLK_M 0_04 0_04 NSD_LN1_P NSD_CLK/MS_D0 NSD_LN1_M NSD_VDD2 NC47 NGND NSD_CLK/MS_D0 0_04 5/21 update PCB Footprint NR35 NR34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NVCC_CARD +/- 15% NGND B 50ohm +/- 15% NGND NC44 Place Near Conn NC28 NGND N3V3AUX 1u_6.3V_X5R_04 NJ_CARD1 NSD_W P/MS_BS NSD_D1/SD_RCLK_M NSD_D0/SD_RCLK_P | CLK - DATA | <= 100mils CLK NEED DOUBLE SPACE THEN OTHER NSP2 NSP1 20 mil MDIO0~5 攟䞕ⶖ<200 mil LENGTH <2INCH NC40 NRREF L<200mils NR29 SD_CARD SUPPORT UHS-II 40 mil NGND SDREG2 SD_LN1_M SD_LN1_P SP6 SP5 SP4 DV33_18 SP3 8 Near Cardreader CONN *150_06 SD Card Remove Fall time less than 1 ms NGND when SD card remove. Sheet 76 of 77 PA7 Card Reader Board 4/4 NGND LAN BOARD (I/O RJ-45,USB3.0x1,USB3.1X2,CARD READER,SIM ) NJ_LAN1 NJ_LAN2 FP238BH- 024S10M NVDD5 NVDD3 C NC22 NVDD3 0.1u_10V_X7R_04 N3.3VS NGND [74] [74] NUSB_PN6 NUSB_PP6 [75] [75] N3.3VS NUSB_PN4 NUSB_PP4 [75] [73] NDD_ON NLAN_CLKREQ# [73] [73] NLAN_W AKEUP# NBUF_PLT_RST# [74,75] NDD_ON# NSD40_CLKREQ# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 [73] [73] NCLK_PCIE_GLAN# [73] NCLK_PCIE_GLAN [73] [73] [73] [73] NPCIE_TXN5_GLAN NPCIE_TXP5_GLAN NPCIE_RXN5_GLAN NPCIE_RXP5_GLAN NCLK_PCIE_SD40# NCLK_PCIE_SD40 NPCIE_TXN6_SD40 NPCIE_TXP6_SD40 NPCIE_RXN6_SD40 NPCIE_RXP6_SD40 26 25 NC50 0.1u_10V_X7R_04 NGCLK_25M_GLAN KAI_1/9 [74] [74] NUSB3_TXN6 NUSB3_TXP6 [74] [74] NUSB3_RXN6 NUSB3_RXP6 [75] [75] NUSB3_TXN4 NUSB3_TXP4 [75] [75] NUSB3_RXN4 NUSB3_RXP4 NGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C GND5 GND4 GND3 GND2 GND1 GND5 GND4 GND3 GND2 GND1 NH1 *H8_0D2_8 NGND NH3 *H8_0D2_8 NH5 *H8_0D2_8 NH2 *c87d87n NH8 *c87d87n NH7 *H8_0D2_8 NGND NGND LVDFH-03008-TP00+ PCB Footprint = lvdfh-030xx-tx00 current = 0.3A NGND D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NGND NGND NGND 1NR1 *0_04 4NR1 *0_04 2NR1 *0_04 5NR1 *0_04 3NR1 *0_04 6NR1 *0_04 NGND D ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/ Title NVDD5 [74,75] N3.3VS NVDD3 [73] [73] Size A3 Date: 1 2 3 4 5 6 [76] PA7 CARD R/CON BOARD_N 4/4 Document Number SCHEMATIC1 7 Rev D02A 6-71-PA70Z-D02A W ednesday, July 05, 2017 Sheet 76 of 77 8 PA7 Card Reader Board 4/4 B - 77 B.Schematic Diagrams 12 mil 6.2K_1%_04 N_AV12 QFN32 GND NGND NR26 RTS5250 RREF AV12 3V3_IN CARD_3V3 SD_VDD2 DV12_S SP1/SD_RCLK_M SP2/SD_RCLK_P 33 NDV12_S NU5 WAKE# MS_INS# SD_CD# SP7 GPIO 3V3aux SD_LN0_P SD_LN0_M NQ1 *2SK3018S3 7 0.1u_10V_X7R_04 G NLAN_W AKEUP# NPCIE_RXP6_SD40 NPCIE_RXN6_SD40 6 CARD READER N3V3AUX 3.3VS:1575mA A 5 N3V3AUX 0.1u_10V_X7R_04 1 RTS5250 Schematic Diagrams Power Sequence B.Schematic Diagrams 5 Sheet 77 of 77 Power Sequence 4 3 2 1 D D C C B B A A Title [77] SEQUENCE Size A3 Date: 5 B - 78 Power Sequence 4 3 2 Document Number 6-71-PA700-D02A W ednesday, July 05, 2017 Rev D02A Sheet 1 77 of 77 BIOS Update Appendix C:pdating the FLASH ROM BIOS To update the FLASH ROM BIOS, you must: • • • • • • • Download the BIOS 1. Go to www.clevo.com.tw and point to E-Services and click E-Channel. 2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files (the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model (see sidebar for important information on BIOS versions). Unzip the downloaded files to a bootable CD/DVD or USB Flash drive 1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the downloaded files. 2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software). BIOS Version Make sure you download the latest correct version of the BIOS appropriate for the computer model you are working on. You should only download BIOS versions that are V1.0X.XX or higher as appropriate for your computer model. Note that BIOS versions are not backward compatible and therefore you may not downgrade your BIOS to an older version after upgrading to a later version (e.g if you upgrade a BIOS to ver 1.0X.05, you MAY NOT then go back and flash the BIOS to ver 1.0X.04). Set the computer to boot from the external drive 1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the computer and press F2 (in most cases) to enter the BIOS. 2. Use the arrow keys to highlight the Boot menu. 3. Use the “+” and “-” keys to move boot devices up and down the priority order. 4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS. 5. Press F4 to save any changes you have made and exit the BIOS to restart the computer. C - 1 C:BIOS Update Download the BIOS update from the web site. Unzip the files onto a bootable CD/DVD/USB Flash Drive. Reboot your computer from an external CD/DVD/USB Flash Drive. Use the flash tools to update the flash BIOS using the commands indicated below. Restart the computer booting from the HDD and press F2 at startup enter the BIOS. Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer. After rebooting the computer you may restart the computer again and make any required changes to the default BIOS settings. BIOS Update Use the flash tools to update the BIOS 1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you see the message “EFI Shell”. You will then be prompted to give “Y” or “N” responses to the programs being loaded by EFI Shell. Choose “N” for any memory management programs. 2. You should now see DISK fsX:\> (X is the designated drive number for the CD/DVD drive/USB flash drive). 3. Type the following command: C:BIOS Update fsX:\> Flash.nsh 4. The utility will then proceed to flash the BIOS. 5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer restarts. Restart the computer (booting from the HDD) 1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from the HDD. 2. Press F2 as the computer restarts to enter the BIOS. 3. Use the arrow keys to highlight the Exit menu. 4. Select Load Setup Defaults (or press F3) and select “Yes” to confirm the selection. 5. Press F4 to save any changes you have made and exit the BIOS to restart the computer. Your computer is now running normally with the updated BIOS You may now enter the BIOS and make any changes you require to the default settings. C-2
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Tagged PDF : Yes XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:08:04 Create Date : 2017:07:21 12:06:54Z Creator Tool : FrameMaker 9.0 Modify Date : 2017:07:21 14:06:02+08:00 Metadata Date : 2017:07:21 14:06:02+08:00 Producer : Acrobat Distiller 9.0.0 (Windows) Format : application/pdf Title : untitled Document ID : uuid:756aeae7-82b5-444f-81ba-bd7cad4036a2 Instance ID : uuid:c4af0aff-7865-486f-b2d7-e8aec00c5d21 Page Mode : UseOutlines Page Count : 136 Creator : FrameMaker 9.0EXIF Metadata provided by EXIF.tools