TMS320C6000 Chip Support Library API Reference Guide (Rev. I) CSL
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TMS320C6000
Chip Support Library
API Reference Guide
Literature Number SPRU401I
May 2004
Printed on Recycled Paper
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Preface
Read This First
About This Manual
The TMS320C6000 Chip Support Library (CSL) is a set of application programming interfaces (APIs) used to configure and control all on-chip peripherals. It is intended to make it easier for developers by eliminating much of the
tedious work usually needed to get algorithms up and running in a real system.
Some of the advantages offered by the CSL include: peripheral ease of use,
a level of compatibility between devices, shortened development time, portability, and standardization. A version of the CSL is available for all
TMS320C6000 devices.
This document is organized as follows:
Introduction − a high level overview of the CSL
27 CSL API module chapters
HAL macro chapter
Using CSL APIs Without DSP/BIOS
Register description
How to Use the CSL
Cache register comparison
Glossary
-
How to Use This Manual
The information in this document describes the contents of the
TMS320C6000 chip support library (CSL) as follows:
- Chapter 1 provides an overview of the CSL, includes a table showing CSL
API module support for various C6000 devices, and lists the API modules.
Read This First
iii
Notational Conventions
- Each additional chapter discusses an individual CSL API module and
provides:
J
A description of the API module
J
A table showing the APIs within the module and a page reference for
more specific information
J
A table showing the macros within the module and a page reference
for more specific information
J
A module API Reference section in alphabetical order listing the CSL
API functions, enumerations, type definitions, structures, constants,
and global variables. Examples are given to show how these elements
are used.
- Chapter 28 describes the hardware abstraction layer (HAL) and provides
a HAL macro reference section.
- Appendix A provides an example of using CSL independently of
DSP/BIOS.
- Appendix B provides a list of the registers associated with current
TMS320C6000 DSP devices.
- Appendix C provides a comparison of the old and new CACHE register
names, as they have recently been changed.
- Appendix D provides a glossary.
Notational Conventions
This document uses the following conventions:
- Program listings, program examples, and interactive displays are shown
in a special typeface.
- In syntax descriptions, the function or macro appears in a bold typeface
and the parameters appear in plainface within parentheses. Portions of a
syntax that are in bold should be entered as shown; portions of a syntax
that are within parentheses describe the type of information that should be
entered.
- Macro names are written in uppercase text; function names are written in
lowercase.
- TMS320C6000 devices are referred to throughout this reference guide as
C6201, C6202, etc.
iv
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
The following books describe the TMS320C6000 devices and related support
tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477−8924. When ordering, please
identify the book by its title and literature number. Many of these documents
can be found on the Internet at http://www.ti.com.
TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an
introduction to the C62x/C67x digital signal processors, development
tools, and third-party support.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000 CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6x C Source Debugger User’s Guide (literature number
SPRU188) tells you how to invoke the TMS320C6x simulator and
emulator versions of the C source debugger interface. This book
discusses various aspects of the debugger, including command entry,
code execution, data management, breakpoints, profiling, and analysis.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature
number SPRU190) describes the peripherals available on the C6000
platform of devices.
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000 DSPs and includes application program examples.
TMS320C6000 Assembly Language Tools User’s Guide (literature number
SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the TMS320C6000 generation of devices.
TMS320C6000 Optimizing Compiler User’s Guide (literature number
SPRU187) describes the TMS320C6000 C compiler and the assembly
optimizer. This C compiler accepts ANSI standard C source code and
produces assembly language source code for the TMS320C6000 generation of devices. The assembly optimizer helps you optimize your
assembly code.
TMS320C62x DSP Library (literature number SPRU402) describes the 32
high-level, C-callable, optimized DSP functions for general signal processing, math, and vector operations.
Read This First
v
Related Documentation From Texas Instruments
TMS320C64x Technical Overview (SPRU395) The TMS320C64x technical
overview gives an introduction to the TMS320C64x digital signal processor, and discusses the application areas that are enhanced by the
TMS320C64x VelociTI.
TMS320C62x Image/Video Processing Library (literature number
SPRU400) describes the optimized image/video processing functions
including many C-callable, assembly-optimized, general-purpose
image/video processing routines.
TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide
(literature number SPRU266) describes the operation of the external
memory interface (EMIF) in the digital signal processors of the
TMS320C6000 DSP family.
TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller
Reference Guide (literature number SPRU234) describes the operation
of the EDMA controller in the digital signal processors of the
TMS320C6000 DSP family. This document also describes the quick
DMA (QDMA) used for fast data requests by the CPU.
TMS320C6000 DSP EMAC/MDIO Module Reference Guide (literature
number SPRU628) describes the EMAC and MDIO module in the digital
signal processors of the TMS320C6000 DSP family.
TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference
Guide (literature number SPRU584) describes the general-purpose
input/output (GPIO) peripheral in the digital signal processors (DSPs) of
the TMS320C6000 DSP family.
TMS320C6000 DSP Host Port Interface (HPI) Reference Guide (literature
number SPRU578) describes the host−port interface (HPI) in the digital
signal processors (DSPs) of the TMS320C6000 DSP family that external
processors use to access the memory space.
TMS320C6000 DSP Interrupt Selector Reference Guide (literature number
SPRU646) describes the interrupt selector, interrupt selector registers,
and the available interrupts in the digital signal processors (DSPs) of the
TMS320C6000 DSP family.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference
Guide (literature number SPRU175) describes the I2C module that provides an interface between a TMS320C6000 digital signal processor
(DSP) and any I2C-bus-compatible device that connects by way of an
I2C bus.
TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference
Guide (literature number SPRU041) describes the multichannel audio
serial port (McASP) in the digital signal processors (DSPs) of the
TMS320C6000 DSP family.
vi
Related Documentation From Texas Instruments
TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU580) describes the operation of the
multichannel buffered serial port (McBSP) in the digital signal processors
(DSPs) of the TMS320C6000 DSP family.
TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference
Guide (literature number SPRU581) describes the peripheral component interconnect (PCI) port in the digital signal processors (DSPs) of the
TMS320C6000 DSP family. The PCI port supports connection of the
DSP to a PCI host via the integrated PCI master/slave bus interface.
TMS320C6000 DSP Software Programmable Phase-Locked Loop (PLL)
Controller RG (literature number SPRU233) describes the operation of
the software-programmable phase-locked loop (PLL) controller in the
digital signal processors (DSPs) of the TMS320C6000 DSP family.
TMS320C6000 DSP 32-Bit Timer Reference Guide (literature number
SPRU582) describes the 32-bit timer in the TMS320C6000 DSP family.
TMS320C64x DSP Turbo-Decoder Coprocessor (TCP) Reference Guide
(literature number SPRU534) describes the operation and programming
of the turbo decoder coprocessor (TCP) embedded in the
TMS320C6416 digital signal processor (DSP) of the TMS320C6000
DSP family.
TMS320C64x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide
(literature number SPRU533) describes the operation and programming
of the Viterbi-decoder coprocessor (VCP) embedded in the
TMS320C6416 digital signal processor (DSP) of the TMS320C6000
DSP family.
TMS320C64x DSP Video Port/ /VCXO Interpolated Control (VIC) Port
Reference Guide (literature number SPRU629) describes the video port
and VCXO interpolated control (VIC) port in the TMS320C64x digital
signal processors (DSPs) of the TMS320C6000 DSP family.
TMS320C64x DSP Universal Test and Operations Interface for ATM
(UTOPIA) Reference Guide (literature number SPRU583) describes
the universal test and operations PHY interface for asynchronous transfer mode (UTOPIA) in the TMS320C64x digital signal processors (DSPs)
of the TMS320C6000 DSP family.
TMS320C62x DSP Expansion Bus (XBUS) Reference Guide (literature
number SPRU579) describes the expansion bus (XBUS) used by the
CPU to access off-chip peripherals, FIFOs, and peripheral component
interconnect (PCI) interface devices in the TMS320C62x digital signal
processors (DSPs) of the TMS320C6000 DSP family.
Read This First
vii
Trademarks
TMS320C620x/C670x DSP Program and Data Memory Controller/DMA
Controller Reference Guide (literature number SPRU577) describes
the program memory modes, program and data memory organizations,
and the program and data memory controller in the
TMS320C620x/C670x digital signal processors (DSPs) of the
TMS320C6000 DSP family.
Trademarks
The Texas Instruments logo and Texas Instruments are registered trademarks
of Texas Instruments. Trademarks of Texas Instruments include: TI, Code
Composer Studio, DSP/BIOS, and TMS320C6000.
All other brand or product names are trademarks or registered trademarks of
their respective companies or organizations.
viii
Contents
Contents
1
CSL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Provides an overview of the chip support library (CSL), shows which TMS320C6000 devices
support the various APIs, and lists each of the API modules.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2
CACHE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the CACHE module, gives a description of the two CACHE architectures, lists the
functions and macros within the module, and provides a CACHE API reference section.
2.1
2.2
2.3
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
CHIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the CHIP module, lists the API functions and macros within the CHIP module, and
provides a CHIP API reference section.
3.1
3.2
3.3
4
CSL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1 Benefits of the CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.2 CSL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.3 Interdependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
CSL Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
CSL Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
CSL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.1 Peripheral Initialization via Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
CSL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
CSL Symbolic Constant Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.7.1 Using CSL Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
CSL API Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.8.1 CSL Endianess/Device Support Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
CSL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Describes the CSL module, shows the single API function within the module, and provides a
CSL API reference section.
4.1
4.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
ix
Contents
5
DAT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the DAT module, lists the API functions within the module, discusses how the module
manages the DMA/EDMA peripheral, and provides a DAT API reference section.
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 DAT Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 DAT Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 DMA/EDMA Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Devices With DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5 Devices With EDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2
5-2
5-3
5-3
5-3
5-3
5-4
6
DMA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Describes the DMA module, lists the API functions and macros within the module, and provides
a DMA API reference section.
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.1 Using a DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3
Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4.2 DMA Global Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.4.3 DMA Auxiliary Functions, Constants, and Macros . . . . . . . . . . . . . . . . . . . . . . . 6-23
7
EDMA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Describes the EDMA module, lists the API functions and macros within the module, discusses
how to use an EDMA channel, and provides an EDMA reference section.
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.1.1 Using an EDMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.3
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.4.1 EDMA Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.4.2 EDMA Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
8
EMAC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Describes the EMAC module, lists the API functions and macros within the module, and provides an EMAC reference section.
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
9
EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the EMIF module, lists the API functions and macros within the module, and provides
an EMIF API reference section.
9.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
9-1
9-2
9-3
9-5
9-6
Contents
10 EMIFA/EMIFB Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Describes the EMIFA and EMIFB modules, lists the API functions and macros within the
modules, and provides an API reference section.
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
11 GPIO Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Describes the GPIO module, lists the API functions and macros within the module, and
provides an GPIO API reference section.
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.1 Using GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.4.1 Primary GPIO Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.4.2 Auxiliary GPIO Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
12 HPI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Describes the HPI module, lists the API functions and macros within the module, and provides
an HPI API reference section.
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
13 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Describes the I2C module, lists the API functions and macros within the module, and provides
an I2C API reference section.
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.1 Using an I2C Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.2 Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.3 Auxiliary Functions Defined for C6410 and C6413 . . . . . . . . . . . . . . . . . . . . . 13-22
14 IRQ Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Describes the IRQ module, lists the API functions and macros within the module, and provides
an IRQ API reference section.
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.4.1 Primary IRQ Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.4.2 Auxiliary IRQ Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Contents
xi
Contents
15 McASP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Describes the McASP module, lists the API functions and macros within the module, discusses
using a McASP device, and provides a McASP API reference section.
15.1
15.2
15.3
15.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.1 Using a McASP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.4.2 Parameters and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.4.3 Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.4.4 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30
16 McBSP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Describes the McBSP module, lists the API functions and macros within the module, and
provides a McBSP API reference section.
16.1
16.2
16.3
16.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.1.1 Using a McBSP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.4.2 Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.4.3 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
17 MDIO Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
Describes the MDIO module, lists the API functions and macros within the module, and
provides an MDIO reference section.
17.1
17.2
17.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
18 PCI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Describes the PCI module, lists the API functions and macros within the module, discusses the
three application domains, and provides a PCI API reference section.
18.1
18.2
18.3
18.4
xii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-2
18-4
18-6
18-7
Contents
19 PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
Describes the PLL module, lists the API functions and macros within the module, discusses the
three application domains, and provides a PLL API reference section.
19.1
19.2
19.3
19.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.1 Using the PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19-2
19-3
19-4
19-6
19-7
20 PWR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
Describes the PWR module, lists the API functions and macros within the module, and provides
a PWR API reference section.
20.1
20.2
20.3
20.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-2
20-3
20-5
20-6
21 TCP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
Describes the TCP module, lists the API functions and macros within the module, discusses
how to use the TPC, and provides a TCP API reference section.
21.1
21.2
21.3
21.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.1.1 Using the TCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
22 TIMER Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
Describes the TIMER module, lists the API functions and macros within the module, discusses
how to use a TIMER device, and provides a TIMER API reference section.
22.1
22.2
22.3
22.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.1.1 Using a TIMER Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.4.2 Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
23 UTOPIA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
Describes the UTOPIA module, lists the API functions and macros within the module, discusses
how to use the UTOPIA interface, and provides a UTOP API reference section.
23.1
23.2
23.3
23.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.1.1 Using UTOPIA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
23-2
23-3
23-4
23-6
23-7
xiii
Contents
24 VCP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
Describes the VCP module, lists the API functions and macros within the module, discusses
how to use the VCP, and provides a VCP API reference section.
24.1
24.2
24.3
24.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.1.1 Using the VCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
25 VIC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
Describes the VIC module, lists the API functions and macros within the module, and provides
a VIC reference section.
25.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
26 VP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
Describes the VP module, lists the API functions and macros within the module, and provides
a VP reference section.
26.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2 Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.3 Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9
27 XBUS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
Describes the XBUS module, lists the API functions and macros within the module, discusses
how to use the XBUS device, and provides an XBUS API reference section.
27.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
27.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
28 Using the HAL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
Describes the hardware abstraction layer (HAL), gives a summary of the HAL macros, discusses RMK macros and macro token pasting, and provides a HAL macro reference section.
28.1
28.2
28.3
28.4
xiv
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.1.1 HAL Macro Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.1.2 HAL Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.1.3 HAL Macro Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
Generic Macro Notation and Table of Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4
General Comments Regarding HAL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.3.1 Right-Justified Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.3.2 _OF Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
28.3.3 RMK Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.4 Macro Token Pasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11
28.3.5 Peripheral Register Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11
HAL Macro Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12
Contents
A
Using CSL APIs Without DSP/BIOS ConfigTool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Provides an example of using CSL independently of the DSP/BIOS configuration tool.
A.1
A.2
B
Using CSL APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.1 Using DMA_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.2 Using DMA_configArgs() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling and Linking With CSL Using Code Composer Studio IDE . . . . . . . . . . . . . . .
A.2.1 CSL Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.2 Using the Code Composer Studio Project Environment . . . . . . . . . . . . . . . . . . .
A-2
A-2
A-5
A-7
A-7
A-7
TMS320C6000 CSL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Shows the registers associated with current TMS320C6000 DSPs.
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
B.9
B.10
B.11
B.12
B.13
B.14
B.15
B.16
B.17
B.18
B.19
B.20
B.21
B.22
B.23
B.24
B.25
B.26
Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Direct Memory Access (DMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
Enhanced DMA (EDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-31
EMAC Control Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
EMAC Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
External Memory Interface (EMIF) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-122
General-Purpose Input/Output (GPIO) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-149
Host Port Interface (HPI) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-159
Inter-Integrated Circuit (I2C) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-168
Interrupt Request (IRQ) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-203
Multichannel Audio Serial Port (McASP) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-207
Multichannel Buffered Serial Port (McBSP) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . B-284
MDIO Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-311
Peripheral Component Interconnect (PCI) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . B-328
Phase-Locked Loop (PLL) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-353
Power-Down Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-359
TCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-360
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-382
UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-386
VCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-396
VIC Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-409
Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-413
Video Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-427
Video Display Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-462
Video Port GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-504
Expansion Bus (XBUS) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-529
C
Old and New CACHE APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Describes how the CACHE APIs have changed.
D
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
Explains terms, abbreviations, and acronyms used throughout this book.
Contents
xv
Figures
Figures
1−1
5−1
A−1
B−1
B−2
B−3
B−4
B−5
B−6
B−7
B−8
B−9
B−10
B−11
B−12
B−13
B−14
B−15
B−16
B−17
B−18
B−19
B−20
B−21
B−22
B−23
B−24
B−25
B−26
B−27
B−28
B−29
B−30
B−31
B−32
B−33
xvi
API Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2D Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Defining the Target Device in the Build Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . A-8
Cache Configuration Register (CCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
L2 EDMA Access Control Register (EDMAWEIGHT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
L2 Writeback Base Address Register (L2WBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
L2 Writeback Word Count Register (L2WWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
L2 Writeback−Invalidate Base Address Register (L2WIBAR) . . . . . . . . . . . . . . . . . . . . . . . . B-6
L2 Writeback−Invalidate Word Count Register (L2WIWC) . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
L2 Invalidate Base Address Register (L2IBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
L2 Writeback−Invalidate Word Count Register (L2IWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
L2 Allocation Registers (L2ALLOC0−L2ALLOC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
L1P Invalidate Base Address Register (L1PIBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
L1P Invalidate Word Count Register (L1PIWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
L1D Writeback−Invalidate Base Address Register (L1DWIBAR) . . . . . . . . . . . . . . . . . . . . B-10
L1D Writeback−Invalidate Word Count Register (L1DWIWC) . . . . . . . . . . . . . . . . . . . . . . B-10
L1P Invalidate Base Address Register (L1PIBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11
L1D Invalidate Word Count Register (L1DIWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11
L2 Writeback All Register (L2WB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12
L2 Writeback−Invalidate All Register (L2WBINV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
L2 Memory Attribute Registers (MAR0−MAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14
L2 Memory Attribute Registers (MAR96−MAR111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
L2 Memory Attribute Registers (MAR128−MAR191) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16
DMA Auxiliary Control Register (AUXCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
DMA Channel Primary Control Register (PRICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19
DMA Channel Secondary Control Register (SECCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24
DMA Channel Source Address Register (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28
DMA Channel Destination Address Register (DST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28
DMA Channel Transfer Counter Register (XFRCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29
DMA Global Count Reload Register (GBLCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29
DMA Global Index Register (GBLIDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30
DMA Global Address Reload Register (GBLADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30
EDMA Channel Options Register (OPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-32
EDMA Channel Source Address Register (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-36
EDMA Channel Transfer Count Register (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
EDMA Channel Destination Address Register (DST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Figures
B−34
B−35
B−36
B−37
B−38
B−39
B−40
B−41
B−42
B−43
B−44
B−45
B−46
B−47
B−48
B−49
B−50
B−51
B−52
B−53
B−54
B−55
B−56
B−57
B−58
B−59
B−60
B−61
B−62
B−63
B−64
B−65
B−66
B−67
B−68
B−69
B−70
B−71
B−72
B−73
B−74
B−75
B−76
EDMA Channel Index Register (IDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Count Reload/Link Register (RLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Selector Register 0 (ESEL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Selector Register 1 (ESEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Selector Register 3 (ESEL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue Allocation Register (PQAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue Status Register (PQSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue Status Register (PQSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Pending Register (CIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Pending Low Register (CIPRL) . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Pending High Register (CIPRH) . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Enable Register (CIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Enable Low Register (CIERL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Enable High Register (CIERH) . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Chain Enable Register (CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Chain Enable Low Register (CCERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Chain Enable High Register (CCERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Register (ER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1EDMA Event High Register (ERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Enable Register (EER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Enable Low Register (EERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Enable High Register (EERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Clear Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Clear Low Register (ECRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Clear High Register (ECRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Set Register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Set Low Register (ESRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Set High Register (ESRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Polarity Low Register (EPRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Polarity High Register (EPRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMAC Control Module Transfer Control Register (EWTRCTRL) . . . . . . . . . . . . . . . . . . . .
EMAC Control Module Interrupt Control Register (EWCTL) . . . . . . . . . . . . . . . . . . . . . . . .
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) . . . . . . . . . . . . . . .
Transmit Identification and Version Register (TXIDVER) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Control Register (TXCONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Teardown Register (TXTEARDOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Identification and Version Register (RXIDVER) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Control Register (RXCONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Teardown Register (RXTEARDOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
(RXMBPENABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Unicast Set Register (RXUNICASTSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Unicast Clear Register (RXUNICASTCLEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Maximum Length Register (RXMAXLEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
B-38
B-38
B-39
B-40
B-41
B-42
B-43
B-43
B-44
B-45
B-45
B-46
B-47
B-47
B-48
B-49
B-49
B-50
B-51
B-52
B-53
B-53
B-54
B-55
B-55
B-56
B-57
B-57
B-58
B-59
B-60
B-62
B-63
B-67
B-68
B-69
B-70
B-71
B-72
B-73
B-78
B-80
B-82
xvii
Figures
B−77
B−78
B−79
B−80
B−81
B−82
B−83
B−84
B−85
B−86
B−87
B−88
B−89
B−90
B−91
B−92
B−93
B−94
B−95
B−96
B−97
B−98
B−99
B−100
B−101
B−102
B−103
B−104
B−105
B−106
B−107
B−108
B−109
B−110
B−111
B−112
B−113
B−114
B−115
B−116
B−117
B−118
B−119
B−120
xviii
Receive Buffer Offset Register (RXBUFFEROFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-83
Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH) . . . B-84
Receive Channel n Flow Control Threshold Registers (RXnFLOWTHRESH) . . . . . . . . . B-85
Receive Channel n Free Buffer Count Registers (RXnFREEBUFFER) . . . . . . . . . . . . . . B-86
MAC Control Register (MACCONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-87
MAC Status Register (MACSTATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-89
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) . . . . . . . . . . . . . . . . . B-93
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) . . . . . . . . . . . . . . . . B-94
Transmit Interrupt Mask Set Register (TXINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . . B-95
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . B-97
MAC Input Vector Register (MACINVECTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-99
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) . . . . . . . . . . . . . . . . . B-100
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) . . . . . . . . . . . . . . . B-101
Receive Interrupt Mask Set Register (RXINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . B-102
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . B-104
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) . . . . . . . . . . . . . . . . . . B-106
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) . . . . . . . . . . . . . . . . B-107
MAC Interrupt Mask Set Register (MACINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . . B-108
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . . B-109
MAC Address Channel n Lower Byte Register (MACADDRLn) . . . . . . . . . . . . . . . . . . . . B-110
MAC Address Middle Byte Register (MACADDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-110
MAC Address High Bytes Register (MACADDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-111
MAC Address Hash 1 Register (MACHASH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-112
MAC Address Hash 2 Register (MACHASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
Backoff Test Register (BOFFTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-114
Transmit Pacing Test Register (TPACETEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-115
Receive Pause Timer Register (RXPAUSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-116
Transmit Pause Timer Register (TXPAUSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-117
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) . . . . . . . . . . . . . B-118
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) . . . . . . . . . . . . . B-118
Transmit Channel n Interrupt Acknowledge Register (TXnINTACK) . . . . . . . . . . . . . . . . B-119
Receive Channel n Interrupt Acknowledge Register (RXnINTACK) . . . . . . . . . . . . . . . . B-120
Statistics Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-121
EMIF Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-123
EMIF Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-126
EMIF Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-128
EMIF CE Space Control Register (CECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-131
EMIF CE Space Control Register (CECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-133
EMIF CE Space Control Register (CECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-135
EMIF CE Space Secondary Control Register (CESEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . B-137
EMIF SDRAM Control Register (SDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-139
EMIF SDRAM Control Register (SDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-141
EMIF SDRAM Control Register (SDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-143
EMIF SDRAM Timing Register (SDTIM) (C620x/C670x) . . . . . . . . . . . . . . . . . . . . . . . . . . B-145
Figures
B−121
B−122
B−123
B−124
B−125
B−126
B−127
B−128
B−129
B−130
B−131
B−132
B−133
B−134
B−135
B−136
B−137
B−138
B−139
B−140
B−141
B−142
B−143
B−144
B−145
B−146
B−147
B−148
B−149
B−150
B−151
B−152
B−153
B−154
B−155
B−156
B−157
B−158
B−159
B−160
B−161
B−162
B−163
B−164
EMIF SDRAM Timing Register (SDTIM) (C621x/C671x/C64x) . . . . . . . . . . . . . . . . . . . .
EMIF SDRAM Extension Register (SDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF Peripheral Device Transfer Control Register (PDTCTL) . . . . . . . . . . . . . . . . . . . . .
GPIO Enable Register (GPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Direction Register (GPDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Value Register (GPVAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Delta High Register (GPDH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO High Mask Register (GPHM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Delta Low Register (GPDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Low Mask Register (GPLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Global Control Register (GPGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupt Polarity Register (GPPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Control Register (HPIC)—C620x/C670x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Control Register (HPIC)—C621x/C671x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Control Register (HPIC)—C64x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Transfer Request Control Register (TRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Own Address Register (I2COAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupt Enable Register (I2CIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Status Register (I2CSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Roles of the Clock Divide-Down Values (ICCL and ICCH) . . . . . . . . . . . . . . . . . . . . . . . .
I2C Clock Low-Time Divider Register (I2CCLKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Clock High-Time Divider Register (I2CCLKH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Count Register (I2CCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Receive Register (I2CDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Slave Address Register (I2CSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Transmit Register (I2CDXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Mode Register (I2CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit . . . . . . . .
I2C Interrupt Source Register (I2CISRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Extended Mode Register (I2CEMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Prescaler Register (I2CPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Peripheral Identification Register 1 (I2CPID1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Peripheral Identification Register 2 (I2CPID2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Function Register (I2CPFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Direction Register (I2CPDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Input Register (I2CPDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Output Register (I2CPDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Set Register (I2CPDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Clear Register (I2CPDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Multiplexer High Register (MUXH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Multiplexer Low Register (MUXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Polarity Register (EXTPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Identification Register (PID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down and Emulation Management Register (PWRDEMU) . . . . . . . . . . . . . . . . .
Contents
B-145
B-146
B-148
B-149
B-150
B-151
B-152
B-153
B-154
B-155
B-156
B-158
B-162
B-163
B-164
B-167
B-169
B-170
B-171
B-177
B-177
B-178
B-179
B-180
B-181
B-182
B-183
B-190
B-191
B-192
B-193
B-194
B-195
B-196
B-197
B-198
B-199
B-201
B-202
B-203
B-205
B-206
B-212
B-213
xix
Figures
B−165
B−166
B−167
B−168
B−169
B−170
B−171
B−172
B−173
B−174
B−175
B−176
B−177
B−178
B−179
B−180
B−181
B−182
B−183
B−184
B−185
B−186
B−187
B−188
B−189
B−190
B−191
B−192
B−193
B−194
B−195
B−196
B−197
B−198
B−199
B−200
B−201
B−202
B−203
B−204
B−205
B−206
B−207
B−208
xx
Pin Function Register (PFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Output Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Input Register (PDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Set Register (PDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDCLR Pin Data Clear Register (PDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Mute Control Register (AMUTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Loopback Control Register (DLBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIT Mode Control Register (DITCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Global Control Register (RGBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Format Unit Bit Mask Register (RMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Bit Stream Format Register (RFMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Frame Sync Control Register (AFSRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Clock Control Register (ACLKRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive High-Frequency Clock Control Register (AHCLKRCTL) . . . . . . . . . . . . . . . . . .
Receive TDM Time Slot Register (RTDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Interrupt Control Register (RINTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Status Register (RSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Receive TDM Time Slot Register (RSLOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Clock Check Control Register (RCLKCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver DMA Event Control Register (REVTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Global Control Register (XGBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Format Unit Bit Mask Register (XMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Bit Stream Format Register (XFMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Frame Sync Control Register (AFSXCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Clock Control Register (ACLKXCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit High Frequency Clock Control Register (AHCLKXCTL) . . . . . . . . . . . . . . . . . .
Transmit TDM Time Slot Register (XTDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Interrupt Control Register (XINTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Status Register (XSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Transmit TDM Time Slot Register (XSLOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Clock Check Control Register (XCLKCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter DMA Event Control Register (XEVTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serializer Control Registers (SRCTLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIT Left Channel Status Registers (DITCSRA0−DITCSRA5) . . . . . . . . . . . . . . . . . . . . . .
DIT Right Channel Status Registers (DITCSRB0−DITCSRB5) . . . . . . . . . . . . . . . . . . . .
DIT Left Channel User Data Registers (DITUDRA0−DITUDRA5) . . . . . . . . . . . . . . . . . .
DIT Right Channel User Data Registers (DITUDRB0−DITUDRB5) . . . . . . . . . . . . . . . . .
Transmit Buffer Registers (XBUFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Buffer Registers (RBUFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Receive Register (DRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transmit Register (DXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-214
B-216
B-219
B-221
B-223
B-225
B-227
B-230
B-234
B-235
B-236
B-238
B-239
B-242
B-243
B-245
B-247
B-248
B-250
B-253
B-254
B-256
B-257
B-260
B-261
B-264
B-265
B-267
B-269
B-270
B-272
B-275
B-276
B-278
B-279
B-281
B-281
B-282
B-282
B-283
B-283
B-284
B-285
B-285
Figures
B−209
B−210
B−211
B−212
B−213
B−214
B−215
B−216
B−217
B−218
B−219
B−220
B−221
B−222
B−223
B−224
B−225
B−226
B−227
B−228
B−229
B−230
B−231
B−232
B−233
B−234
B−235
B−236
B−237
B−238
B−239
B−240
B−241
B−242
B−243
B−244
B−245
B−246
B−247
B−248
B−249
B−250
Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Control Register (XCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Register (SRGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Channel Enable Register (RCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Channel Enable Register (XCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced Receive Channel Enable Registers (RCERE0−3) . . . . . . . . . . . . . . . . . . . . . .
Enhanced Transmit Channel Enable Registers (XCERE0−3) . . . . . . . . . . . . . . . . . . . . . .
MDIO Version Register (VERSION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Control Register (CONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO PHY Alive Indication Register (ALIVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO PHY Link Status Register (LINK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Link Status Change Interrupt Register (LINKINTRAW) . . . . . . . . . . . . . . . . . . . . .
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) . . . . . . . . .
MDIO User Command Complete Interrupt Register (USERINTRAW) . . . . . . . . . . . . . . .
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) . .
MDIO User Command Complete Interrupt Mask Set Register
(USERINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Command Complete Interrupt Mask Clear Register
(USERINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Access Register 0 (USERACCESS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Access Register 1 (USERACCESS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User PHY Select Register 0 (USERPHYSEL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User PHY Select Register 1 (USERPHYSEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Reset Source/Status Register (RSTSRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management DSP Control/Status Register (PMDCSR) . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Source Register (PCIIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Enable Register (PCIIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Master Address Register (DSPMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Master Address Register (PCIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Master Control Register (PCIMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current DSP Address (CDSPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current PCI Address Register (CPCIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Byte Count Register (CCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Address Register (EEADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Data Register (EEDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Control Register (EECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Transfer Halt Register (HALT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Transfer Request Control Register (TRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Controller Peripheral Identification Register (PLLPID) . . . . . . . . . . . . . . . . . . . . . . . .
PLL Control/Status Register (PLLCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Multiplier Control Register (PLLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Controller Divider Register (PLLDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
B-290
B-293
B-296
B-299
B-301
B-305
B-306
B-307
B-309
B-312
B-313
B-315
B-316
B-317
B-318
B-319
B-320
B-321
B-322
B-323
B-324
B-326
B-327
B-329
B-332
B-335
B-338
B-341
B-342
B-343
B-344
B-344
B-345
B-346
B-347
B-348
B-350
B-351
B-353
B-354
B-356
B-357
xxi
Figures
B−251
B−252
B−253
B−254
B−255
B−256
B−257
B−258
B−259
B−260
B−261
B−262
B−263
B−264
B−265
B−266
B−267
B−268
B−269
B−270
B−271
B−272
B−273
B−274
B−275
B−276
B−277
B−278
B−279
B−280
B−281
B−282
B−283
B−284
B−285
B−286
B−287
B−288
B−289
B−290
B−291
B−292
B−293
B−294
xxii
Oscillator Divider 1 Register (OSCDIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Control Register (PDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 0 (TCPIC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 1 (TCPIC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 2 (TCPIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 3 (TCPIC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 4 (TCPIC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 5 (TCPIC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 6 (TCPIC6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 7 (TCPIC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 8 (TCPIC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 9 (TCPIC9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 10 (TCPIC10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 11 (TCPIC11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Output Parameter Register (TCPOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Execution Register (TCPEXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Endian Register (TCPEND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Error Register (TCPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Status Register (TCPSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register (CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Period Register (PRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Count Register (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Control Register (UCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Interrupt Enable Register (UIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Interrupt Pending Register (UIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Detect Register (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Enable Registers (EIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Pending Register (EIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 0 (VCPIC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 1 (VCPIC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 2 (VCPIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 3 (VCPIC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 4 (VCPIC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 5 (VCPIC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Output Register 0 (VCPOUT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Output Register 1 (VCPOUT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Execution Register (VCPEXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Endian Mode Register (VCPEND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Status Register 0 (VCPSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Status Register 1 (VCPSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Error Register (VCPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Control Register (VICCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Input Register (VICIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Clock Divider Register (VICDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-358
B-359
B-361
B-363
B-364
B-365
B-366
B-367
B-369
B-370
B-371
B-372
B-373
B-374
B-375
B-376
B-377
B-378
B-380
B-382
B-385
B-385
B-386
B-389
B-390
B-391
B-392
B-394
B-397
B-398
B-399
B-399
B-400
B-401
B-402
B-403
B-404
B-405
B-406
B-407
B-408
B-409
B-411
B-412
Figures
B−295
B−296
B−297
B−298
B−299
B−300
B−301
B−302
B−303
B−304
B−305
B−306
B−307
B−308
B−309
B−310
B−311
B−312
B−313
B−314
B−315
B−316
B−317
B−318
B−319
B−320
B−321
B−322
B−323
B−324
B−325
B−326
B−327
B−328
B−329
B−330
B−331
B−332
B−333
B−334
B−335
B−336
B−337
B−338
Video Port Control Register (VPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Status Register (VPSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Interrupt Enable Register (VPIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Interrupt Status Register (VPIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Capture Channel x Status Register (VCASTAT, VCBSTAT) . . . . . . . . . . . . . . . . . .
Video Capture Channel A Control Register (VCACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) . . . . . . . . .
Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) . . . . . . . . .
Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) . . . . . . . . .
Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) . . . . . . . . .
Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) . . . . . . . . .
Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) . . . . . . . . . . .
Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) . . . . . . . . .
Video Capture Channel B Control Register (VCBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI Capture Control Register (TSICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI Clock Initialization LSB Register (TSICLKINITL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI Clock Initialization MSB Register (TSICLKINITM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI System Time Clock LSB Register (TSISTCLKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI System Time Clock MSB Register (TSISTCLKM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI System Time Clock Compare LSB Register (TSISTCMPL) . . . . . . . . . . . . . . . . . . . .
TSI System Time Clock Compare MSB Register (TSISTCMPM) . . . . . . . . . . . . . . . . . . .
TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) . . . . . . . . . . . . . .
TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) . . . . . . . . . . . . .
TSI System Time Clock Ticks Interrupt Register (TSITICKS) . . . . . . . . . . . . . . . . . . . . . .
Video Display Status Register (VDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Control Register (VDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Frame Size Register (VDFRMSZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Horizontal Blanking Register (VDHBLNK) . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) . . . . . . . . . . . . . . . .
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . . . . . . . . .
Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . . . . . . . . . .
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . . . . . . . . . . . . . .
Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Image Offset Register (VDIMGOFF2) . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Image Size Register (VDIMGSZ2) . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Timing Register (VDFLDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Timing Register (VDFLDT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Threshold Register (VDTHRLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Horizontal Synchronization Register (VDHSYNC) . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) . . . . . . . . .
Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) . . . . . . . . .
Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) . . . . . . . . .
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) . . . . . . . . .
Contents
B-414
B-417
B-418
B-421
B-429
B-431
B-436
B-438
B-439
B-440
B-441
B-444
B-445
B-446
B-451
B-453
B-454
B-455
B-456
B-457
B-458
B-459
B-460
B-461
B-463
B-465
B-470
B-471
B-473
B-474
B-476
B-477
B-479
B-480
B-481
B-483
B-484
B-485
B-486
B-488
B-489
B-490
B-491
B-492
xxiii
Figures
B−339
B−340
B−341
B−342
B−343
B−344
B−345
B−346
B−347
B−348
B−349
B−350
B−351
B−352
B−353
B−354
B−355
B−356
B−357
B−358
B−359
B−360
B−361
B−362
B−363
B−364
B−365
B−366
xxiv
Video Display Counter Reload Register (VDRELOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Display Event Register (VDDISPEVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Clipping Register (VDCLIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Default Display Value Register (VDDEFVAL) . . . . . . . . . . . . . . . . . . . . . . .
Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode . . . . . .
Video Display Vertical Interrupt Register (VDVINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field Bit Register (VDFBIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) . . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) . . . . . . . . . . . . . . . . . . . .
Video Port Peripheral Identification Register (VPPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Peripheral Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Function Register (PFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Data Input Register (PDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Data Output Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Data Set Register (PDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Data Clear Register (PDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Interrupt Enable Register (PIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Interrupt Polarity Register (PIPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Interrupt Status Register (PISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Pin Interrupt Clear Register (PICLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus Global Control Register (XBGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus XCE Space Control Register (XCECTL) . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus Host Port Interface Control Register (XBHC) . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus Internal Master Address Register (XBIMA) . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus External Address Register (XBEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus Data Register (XBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Bus Internal Slave Address Register (XBISA) . . . . . . . . . . . . . . . . . . . . . . . . .
B-493
B-494
B-495
B-496
B-497
B-498
B-499
B-501
B-502
B-505
B-506
B-508
B-510
B-513
B-515
B-517
B-519
B-521
B-523
B-525
B-527
B-529
B-531
B-533
B-535
B-535
B-536
B-536
Tables
Tables
1−1
1−2
1−3
1−4
1−5
1−6
1−7
1−8
1−9
1−10
2−1
2−2
2−3
3−1
3−2
3−3
4−1
5−1
6−1
6−2
6−3
6−4
7−1
7−2
7−3
7−4
8−1
8−2
8−3
8−4
9−1
9−2
9−3
9−4
10−1
10−2
10−3
10−4
CSL Modules and Include Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
CSL Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
CSL Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Generic CSL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Generic CSL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Generic CSL Handle-Based Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Generic CSL Symbolic Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
CSL API Module Support for TMS320C6000 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
CSL API Module Support for TMS320C641x and DM642 Devices . . . . . . . . . . . . . . . . . . 1-16
CSL Device Support Library Name and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . 1-17
CACHE APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
CACHE Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
CACHE Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
CHIP APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
CHIP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
CHIP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
CSL API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
DAT APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
DMA Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
DMA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
DMA Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
DMA Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
EDMA Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
EDMA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
EDMA Macros That Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
EDMA Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
EMAC Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
EMAC APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
EMAC Macros That Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
EMAC Macros that Construct Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
EMIF Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
EMIF APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
EMIF Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
EMIF Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
EMIFA/EMIFB Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
EMIFA/EMIFB APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
EMIFA/EMIFB Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
EMIFA/EMIFB Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . 10-4
Contents
xxv
Tables
11−1
11−2
11−3
11−4
12−1
12−2
12−3
13−1
13−2
13−3
13−4
14−1
14−2
14−3
14−4
15−1
15−2
15−3
15−4
16−1
16−2
16−3
16−4
17−1
17−2
17−3
18−1
18−2
18−3
18−4
19−1
19−2
19−3
19−4
20−1
20−2
20−3
20−4
21−1
21−2
21−3
21−4
22−1
22−2
22−3
22−4
xxvi
GPIO Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McASP Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McASP APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McASP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McASP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Macros That Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWR Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWR APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWR Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWR Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMER Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMER APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMER Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMER Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2
11-2
11-5
11-6
12-2
12-3
12-4
13-2
13-2
13-5
13-6
14-2
14-2
14-4
14-5
15-2
15-2
15-5
15-6
16-2
16-2
16-5
16-6
17-2
17-3
17-3
18-2
18-2
18-4
18-5
19-2
19-2
19-4
19-5
20-2
20-2
20-3
20-4
21-2
21-2
21-7
21-7
22-2
22-2
22-4
22-5
Tables
23−1
23−2
23−3
23−4
24−1
24−2
24−3
24−4
25−1
25−2
25−3
26−1
26−2
27−1
27−2
27−3
27−4
28−1
A−1
B−1
B−2
B−3
B−4
B−5
B−6
B−7
B−8
B−9
B−10
B−11
B−12
B−13
B−14
B−15
B−16
B−17
B−18
B−19
B−20
B−21
B−22
B−23
B−24
B−25
UTOPIA Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
UTOPIA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
UTOP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
UTOP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
VCP Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
VCP APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
VCP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
VCP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
VIC Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
VIC Macros That Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
VIC Macros That Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
Configuration Structures (Macros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
VP APIs and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
XBUS Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
XBUS APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
XBUS Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
XBUS Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
CSL HAL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
CSL Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Cache Configuration Register (CCFG) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
L2 EDMA Access Control Register (EDMAWEIGHT) Field Values . . . . . . . . . . . . . . . . . . . B-5
L2 Writeback Base Address Register (L2WBAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-5
L2 Writeback Word Count Register (L2WWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . B-6
L2 Writeback−Invalidate Base Address Register (L2WIBAR) Field Values . . . . . . . . . . . . B-6
L2 Writeback−Invalidate Word Count Register (L2WIWC) Field Values . . . . . . . . . . . . . . . B-7
L2 Invalidate Base Address Register (L2IBAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-7
L2 Invalidate Word Count Register (L2IWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
L2 Allocation Registers (L2ALLOC0−L2ALLOC3) Field Values . . . . . . . . . . . . . . . . . . . . . . B-8
L1P Invalidate Base Address Register (L1PIBAR) Field Values . . . . . . . . . . . . . . . . . . . . . . B-9
L1P Invalidate Word Count Register (L1PIWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-9
L1D Writeback−Invalidate Base Address Register (L1DWIBAR) Field Values . . . . . . . . B-10
L1D Writeback−Invalidate Word Count Register (L1DWIWC) Field Values . . . . . . . . . . . B-10
L1D Invalidate Base Address Register (L1DIBAR) Field Values . . . . . . . . . . . . . . . . . . . . B-11
L1D Invalidate Word Count Register (L1DIWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-11
L2 Writeback All Register (L2WB) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12
L2 Writeback−Invalidate All Register (L2WBINV) Field Values . . . . . . . . . . . . . . . . . . . . . . B-13
L2 Memory Attribute Registers (MAR0−MAR15) Field Values . . . . . . . . . . . . . . . . . . . . . . B-14
L2 Memory Attribute Registers (MAR96−MAR111) Field Values . . . . . . . . . . . . . . . . . . . . B-15
L2 Memory Attribute Registers (MAR128−MAR191) Field Values . . . . . . . . . . . . . . . . . . . B-16
DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
DMA Auxiliary Control Register (AUXCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
DMA Channel Primary Control Register (PRICTL) Field Values . . . . . . . . . . . . . . . . . . . . B-19
DMA Channel Secondary Control Register (SECCTL) Field Values . . . . . . . . . . . . . . . . . B-24
Contents
xxvii
Tables
B−26
B−27
B−28
B−29
B−30
B−31
B−32
B−33
B−34
B−35
B−36
B−37
B−38
B−39
B−40
B−41
B−42
B−43
B−44
B−45
B−46
B−47
B−48
B−49
B−50
B−51
B−52
B−53
B−54
B−55
B−56
B−57
B−58
B−59
B−60
B−61
B−62
B−63
B−64
B−65
B−66
B−67
B−68
B−69
xxviii
DMA Channel Source Address Register (SRC) Field Values . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Destination Address Register (DST) Field Values . . . . . . . . . . . . . . . . . . . .
DMA Channel Transfer Counter Register (XFRCNT) Field Values . . . . . . . . . . . . . . . . . .
DMA Global Count Reload Register (GBLCNT) Field Values . . . . . . . . . . . . . . . . . . . . . . .
DMA Global Index Register (GBLIDX) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Global Address Reload Register (GBLADDR) Field Values . . . . . . . . . . . . . . . . . . .
EDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Options Register (OPT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Source Address Register (SRC) Field Values . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Transfer Count Register (CNT) Field Values . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Destination Address Register (DST) Field Values . . . . . . . . . . . . . . . . . .
EDMA Channel Index Register (IDX) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Count Reload/Link Register (RLD) Field Values . . . . . . . . . . . . . . . . . . . .
EDMA Event Selector Register 0 (ESEL0) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Selector Register 0 (ESEL1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Selector Register 0 (ESEL3) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue Allocation Register (PQAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue Status Register (PQSR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue Status Register (PQSR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Pending Register (CIPR) Field Values . . . . . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Pending Low Register (CIPRL) Field Values . . . . . . . . . . . . . . .
EDMA Channel Interrupt Pending High Register (CIPRH) Field Values . . . . . . . . . . . . . .
C621x/C671x: Channel Interrupt Enable Register (CIER) Field Values . . . . . . . . . . . . . .
EDMA Channel Interrupt Enable Low Register (CIERL) Field Values . . . . . . . . . . . . . . . .
EDMA Channel Interrupt Enable High Register (CIERH) Field Values . . . . . . . . . . . . . . .
EDMA Channel Chain Enable Register (CCER) Field Values . . . . . . . . . . . . . . . . . . . . . .
EDMA Channel Chain Enable Low Register (CCERL) Field Values . . . . . . . . . . . . . . . . .
EDMA Channel Chain Enable High Register (CCERH) Field Values . . . . . . . . . . . . . . . .
EDMA Event Register (ER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Low Register (ERL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event High Register (ERH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Enable Register (EER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Low Register (EERL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Enable High Register (EERH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Clear Register (ERC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Clear Low Register (ERCL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Clear High Register (ECRH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Set Register (ESR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Set Low Register (ESRL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Set High Register (ESRH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Polarity Low Register (EPRL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Event Polarity High Register (EPRH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
EMAC Control Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMAC Control Module Transfer Control Register (EWTRCTRL) Field Values . . . . . . . .
B-28
B-28
B-29
B-29
B-30
B-30
B-31
B-33
B-36
B-37
B-37
B-38
B-38
B-39
B-40
B-41
B-42
B-43
B-43
B-44
B-45
B-45
B-46
B-47
B-47
B-48
B-49
B-49
B-50
B-51
B-51
B-52
B-53
B-53
B-54
B-55
B-55
B-56
B-57
B-57
B-58
B-59
B-60
B-61
Tables
B−70
B−71
B−72
B−73
B−74
B−75
B−76
B−77
B−78
B−79
B−80
B−81
B−82
B−83
B−84
B−85
B−86
B−87
B−88
B−89
B−90
B−91
B−92
B−93
B−94
B−95
B−96
B−97
B−98
B−99
B−100
B−101
B−102
B−103
B−104
B−105
B−106
B−107
B−108
B−109
B−110
EMAC Control Module Interrupt Control Register (EWCTL) Field Values . . . . . . . . . . . . . B-62
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Values . . . B-63
EMAC Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
Transmit Identification and Version Register (TXIDVER) Field Values . . . . . . . . . . . . . . . B-67
Transmit Control Register (TXCONTROL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
Transmit Teardown Register (TXTEARDOWN) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-69
Receive Identification and Version Register (RXIDVER) Field Values . . . . . . . . . . . . . . . B-70
Receive Control Register (RXCONTROL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-71
Receive Teardown Register (RXTEARDOWN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-72
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
Receive Unicast Set Register (RXUNICASTSET) Field Values . . . . . . . . . . . . . . . . . . . . . B-78
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Values . . . . . . . . . . . . . . . . B-80
Receive Maximum Length Register (RXMAXLEN) Field Values . . . . . . . . . . . . . . . . . . . . B-82
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Values . . . . . . . . . . . . . . . . . B-83
Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-84
Receive Channel n Flow Control Threshold Registers (RXnFLOWTHRESH)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-85
Receive Channel n Free Buffer Count Registers (RXnFREEBUFFER) Field Values . . . B-86
MAC Control Register (MACCONTROL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-87
MAC Status Register (MACSTATUS) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-90
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Values . . . . . . B-93
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Values . . . . . B-94
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Values . . . . . . . . . . . . . . B-95
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Values . . . . . . . . . . B-97
MAC Input Vector Register (MACINVECTOR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-99
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Values . . . . . B-100
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Values . . . . B-101
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Values . . . . . . . . . . . . . . B-102
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Values . . . . . . . . . B-104
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Values . . . . . . B-106
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Values . . . . . B-107
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Values . . . . . . . . . . . . . . . B-108
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Values . . . . . . . . . . B-109
MAC Address Channel n Lower Byte Register (MACADDRLn) Field Values . . . . . . . . . B-110
MAC Address Middle Byte Register (MACADDRM) Field Values . . . . . . . . . . . . . . . . . . B-110
MAC Address High Bytes Register (MACADDRH) Field Values . . . . . . . . . . . . . . . . . . . B-111
MAC Address Hash 1 Register (MACHASH1) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-112
MAC Address Hash 2 Register (MACHASH2) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-113
Backoff Test Register (BOFFTEST) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-114
Transmit Pacing Test Register (TPACETEST) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-115
Receive Pause Timer Register (RXPAUSE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . B-116
Transmit Pause Timer Register (TXPAUSE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . B-117
Contents
xxix
Tables
B−111 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−112 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−113 Transmit Channel n Interrupt Acknowledge Register (TXnINTACK) Field Values . . . . .
B−114 Receive Channel n Interrupt Acknowledge Register (RXnINTACK) Field Values . . . . .
B−115 EMIF Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−116 EMIF Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−117 EMIF Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−118 EMIF Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−119 EMIF CE Space Control Register (CECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
B−120 EMIF CE Space Control Register (CECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
B−121 EMIF CE Space Control Register (CECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
B−122 EMIF CE Space Secondary Control Register (CESEC) Field Values . . . . . . . . . . . . . . .
B−123 EMIF SDRAM Control Register (SDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−124 EMIF SDRAM Control Register (SDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−125 EMIF SDRAM Control Register (SDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−126 EMIF SDRAM Timing Register (SDTIM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−127 EMIF SDRAM Extension Register (SDEXT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
B−128 EMIF Peripheral Device Transfer Control Register (PDTCTL) Field Values . . . . . . . . . .
B−129 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−130 GPIO Enable Register (GPEN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−131 GPIO Direction Register (GPDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−132 GPIO Value Register (GPVAL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−133 GPIO Delta High Register (GPDH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−134 GPIO High Mask Register (GPHM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−135 GPIO Delta Low Register (GPDL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−136 GPIO Low Mask Register (GPLM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−137 GPIO Global Control Register (GPGC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−138 GPIO Interrupt Polarity Register (GPPOL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
B−139 HPI Registers for C62x/C67x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−140 HPI Registers for C64x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−141 HPI Control Register (HPIC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−142 HPI Transfer Request Control Register (TRCTL) Field Values . . . . . . . . . . . . . . . . . . . . .
B−143 I2C Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−144 I2C Own Address Register (I2COAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−145 I2C Interrupt Enable Register (I2CIER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−146 I2C Status Register (I2CSTR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−147 I2C Clock Low-Time Divider Register (I2CCLKL) Field Values . . . . . . . . . . . . . . . . . . . . .
B−148 I2C Clock High-Time Divider Register (I2CCLKH) Field Values . . . . . . . . . . . . . . . . . . . .
B−149 I2C Data Count Register (I2CCNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−150 I2C Data Receive Register (I2CDRR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−151 I2C Slave Address Register (I2CSAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−152 I2C Data Transmit Register (I2CDXR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxx
B-118
B-118
B-119
B-120
B-122
B-123
B-126
B-128
B-131
B-133
B-135
B-137
B-139
B-141
B-143
B-145
B-146
B-148
B-149
B-150
B-150
B-151
B-152
B-153
B-154
B-155
B-156
B-158
B-159
B-159
B-165
B-167
B-168
B-169
B-170
B-172
B-178
B-178
B-179
B-180
B-181
B-182
Tables
B−153
B−154
B−155
B−156
B−157
B−158
B−159
B−160
B−161
B−162
B−163
B−164
B−165
B−166
B−167
B−168
B−169
B−170
B−171
B−172
B−173
B−174
B−175
B−176
B−177
B−178
B−179
B−180
B−181
B−182
B−183
B−184
B−185
B−186
B−187
B−188
B−189
B−190
B−191
B−192
B−193
B−194
B−195
B−196
I2C Mode Register (I2CMDR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits . . . . . . .
How the MST and FDF Bits Affect the Role of TRX Bit . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupt Source Register (I2CISRC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Extended Mode Register (I2CEMDR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Prescaler Register (I2CPSC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Peripheral Identification Register 1 (I2CPID1) Field Values . . . . . . . . . . . . . . . . . . . .
I2C Peripheral Identification Register 2 (I2CPID2) Field Values . . . . . . . . . . . . . . . . . . . .
I2C Pin Function Register (I2CPFUNC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Direction Register (I2CPDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Input Register (I2CPDIN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Output Register (I2CPDOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Set Register (I2CPDSET) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Pin Data Clear Register (I2CPDCLR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Multiplexer High Register (MUXH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Multiplexer Low Register (MUXL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Polarity Register (EXTPOL) Field Values . . . . . . . . . . . . . . . . . . . . . . .
McASP Registers Accessed Through Configuration Bus . . . . . . . . . . . . . . . . . . . . . . . . .
McASP Registers Accessed Through Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Identification Register (PID) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down and Emulation Management Register (PWRDEMU) Field Values . . . . . .
Pin Function Register (PFUNC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Direction Register (PDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Output Register (PDOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Input Register (PDIN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Set Register (PDSET) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Data Clear Register (PDCLR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Mute Control Register (AMUTE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Loopback Control Register (DLBCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . .
DIT Mode Control Register (DITCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Global Control Register (RGBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . .
Receive Format Unit Bit Mask Register (RMASK) Field Values . . . . . . . . . . . . . . . . . . . .
Receive Bit Stream Format Register (RFMT) Field Values . . . . . . . . . . . . . . . . . . . . . . . .
Receive Frame Sync Control Register (AFSRCTL) Field Values . . . . . . . . . . . . . . . . . . .
Receive Clock Control Register (ACLKRCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . .
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Values . . . . . . .
Receive TDM Time Slot Register (RTDM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Interrupt Control Register (RINTCTL) Field Values . . . . . . . . . . . . . . . . . . . . . .
Receiver Status Register (RSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Receive TDM Time Slot Register (RSLOT) Field Values . . . . . . . . . . . . . . . . . .
Receive Clock Check Control Register (RCLKCHK) Field Values . . . . . . . . . . . . . . . . . .
Receiver DMA Event Control Register (REVTCTL) Field Values . . . . . . . . . . . . . . . . . . .
Contents
B-183
B-189
B-189
B-191
B-192
B-193
B-194
B-195
B-196
B-197
B-198
B-200
B-201
B-202
B-203
B-204
B-205
B-206
B-207
B-211
B-212
B-213
B-215
B-217
B-220
B-222
B-224
B-226
B-228
B-231
B-234
B-235
B-236
B-238
B-239
B-242
B-244
B-245
B-247
B-248
B-250
B-253
B-254
B-256
xxxi
Tables
B−197
B−198
B−199
B−200
B−201
B−202
B−203
B−204
B−205
B−206
B−207
B−208
B−209
B−210
B−211
B−212
B−213
B−214
B−215
B−216
B−217
B−218
B−219
B−220
B−221
B−222
B−223
B−224
B−225
B−226
B−227
B−228
B−229
B−230
B−231
B−232
B−233
B−234
B−235
B−236
B−237
xxxii
Transmitter Global Control Register (XGBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . .
Transmit Format Unit Bit Mask Register (XMASK) Field Values . . . . . . . . . . . . . . . . . . . .
Transmit Bit Stream Format Register (XFMT) Field Values . . . . . . . . . . . . . . . . . . . . . . .
Transmit Frame Sync Control Register (AFSXCTL) Field Values . . . . . . . . . . . . . . . . . .
Transmit Clock Control Register (ACLKXCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . .
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Values . . . . . . .
Transmit TDM Time Slot Register (XTDM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Interrupt Control Register (XINTCTL) Field Values . . . . . . . . . . . . . . . . . . . .
Transmitter Status Register (XSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Transmit TDM Time Slot Register (XSLOT) Field Values . . . . . . . . . . . . . . . . . .
Transmit Clock Check Control Register (XCLKCHK) Field Values . . . . . . . . . . . . . . . . . .
Transmitter DMA Event Control Register (XEVTCTL) Field Values . . . . . . . . . . . . . . . . .
Serializer Control Registers (SRCTLn) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Receive Register (DRR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transmit Register (DXR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Control Register (SPCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Control Register (PCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Control Register (RCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Control Register (XCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Register (SRGR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Control Register (MCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Channel Enable Register (RCER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Channel Enable Register (XCER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced Receive Channel Enable Registers (RCERE0−3) Field Values . . . . . . . . . . .
Channel Enable Bits in RCEREn for a 128-Channel Data Stream . . . . . . . . . . . . . . . . . .
Enhanced Transmit Channel Enable Registers (XCERE0−3) Field Values . . . . . . . . . .
Channel Enable Bits in XCEREn for a 128-Channel Data Stream . . . . . . . . . . . . . . . . . .
MDIO Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Version Register (VERSION) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Control Register (CONTROL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO PHY Alive Indication Register (ALIVE) Field Values . . . . . . . . . . . . . . . . . . . . . . . .
MDIO PHY Link Status Register (LINK) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Link Status Change Interrupt Register (LINKINTRAW) Field Values . . . . . . . . . .
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Command Complete Interrupt Register (USERINTRAW) Field Values . . .
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Command Complete Interrupt Mask Clear Register
(USERINTMASKCLEAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO User Access Register 0 (USERACCESS0) Field Values . . . . . . . . . . . . . . . . . . . .
MDIO User Access Register 1 (USERACCESS1) Field Values . . . . . . . . . . . . . . . . . . . .
B-257
B-260
B-261
B-264
B-266
B-267
B-269
B-270
B-273
B-275
B-276
B-278
B-279
B-284
B-284
B-285
B-286
B-290
B-294
B-296
B-299
B-301
B-305
B-306
B-307
B-308
B-309
B-310
B-311
B-312
B-313
B-315
B-316
B-317
B-318
B-319
B-320
B-321
B-322
B-323
B-325
Tables
B−238
B−239
B−240
B−241
B−242
B−243
B−244
B−245
B−246
B−247
B−248
B−249
B−250
B−251
B−252
B−253
B−254
B−255
B−256
B−257
B−258
B−259
B−260
B−261
B−262
B−263
B−264
B−265
B−266
B−267
B−268
B−269
B−270
B−271
B−272
B−273
B−274
B−275
B−276
B−277
B−278
B−279
B−280
B−281
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Values . . . . . . . . . . . . . . . .
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Values . . . . . . . . . . . . . . . .
PCI Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Reset Source/Status Register (RSTSRC) Field Values . . . . . . . . . . . . . . . . . . . . . .
Power Management DSP Control/Status Register (PMDCSR) Field Values . . . . . . . . .
PCI Interrupt Source Register (PCIIS) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Enable Register (PCIIEN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Master Address Register (DSPMA) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Master Address Register (PCIMA) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Master Control Register (PCIMC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current DSP Address (CDSPA) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current PCI Address Register (CPCIA) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Byte Count Register (CCNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Address Register (EEADD) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Data Register (EEDAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Control Register (EECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Transfer Halt Register (HALT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Transfer Request Control Register (TRCTL) Field Values . . . . . . . . . . . . . . . . . . . . .
PLL Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Controller Peripheral Identification Register (PLLPID) Field Values . . . . . . . . . . . .
PLL Control/Status Register (PLLCSR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Multiplier Control Register (PLLM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Controller Divider Register (PLLDIV) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Divider 1 Register (OSCDIV1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Control Register (PDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 0 (TCPIC0) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 1 (TCPIC1) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 2 (TCPIC2) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 3 (TCPIC3) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 4 (TCPIC4) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 5 (TCPIC5) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 6 (TCPIC6) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 7 (TCPIC7) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 8 (TCPIC8) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 9 (TCPIC9) Field Values . . . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 10 (TCPIC10) Field Values . . . . . . . . . . . . . . . . . . . . .
TCP Input Configuration Register 11 (TCPIC11) Field Values . . . . . . . . . . . . . . . . . . . . .
TCP Output Parameter Register (TCPOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Execution Register (TCPEXE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Endian Register (TCPEND) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Error Register (TCPERR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP Status Register (TCPSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
B-326
B-327
B-328
B-329
B-332
B-335
B-338
B-341
B-342
B-343
B-344
B-344
B-345
B-346
B-347
B-348
B-350
B-352
B-353
B-354
B-355
B-356
B-357
B-358
B-359
B-360
B-361
B-363
B-364
B-365
B-366
B-367
B-369
B-370
B-371
B-372
B-373
B-374
B-375
B-376
B-377
B-378
B-380
B-382
xxxiii
Tables
B−282
B−283
B−284
B−285
B−286
B−287
B−288
B−289
B−290
B−291
B−292
B−293
B−294
B−295
B−296
B−297
B−298
B−299
B−300
B−301
B−302
B−303
B−304
B−305
B−306
B−307
B−308
B−309
B−310
B−311
B−312
B−313
B−314
B−315
B−316
B−317
B−318
B−319
B−320
B−321
B−322
B−323
B−324
B−325
xxxiv
Timer Control Register (CTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Period Register (PRD) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Count Register (CNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Control Register (UCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Interrupt Enable Register (UIER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Interrupt Pending Register (UIPR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Detect Register (CDR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Enable Register (EIER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Pending Register (EIPR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Bus Accesses Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 0 (VCPIC0) Field Values . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 1 (VCPIC1) Field Values . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 2 (VCPIC2) Field Values . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 3 (VCPIC3) Field Values . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 4 (VCPIC4) Field Values . . . . . . . . . . . . . . . . . . . . . . .
VCP Input Configuration Register 5 (VCPIC5) Field Values . . . . . . . . . . . . . . . . . . . . . . .
VCP Output Register 0 (VCPOUT0) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Output Register 1 (VCPOUT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Execution Register (VCPEXE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Endian Mode Register (VCPEND) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Status Register 0 (VCPSTAT0) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Status Register 1 (VCPSTAT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCP Error Register (VCPERR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Control Register (VICCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Input Register (VICIN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIC Clock Divider Register (VICDIV) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Control Register (VPCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Status Register (VPSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Interrupt Enable Register (VPIE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Interrupt Status Register (VPIS) Field Values . . . . . . . . . . . . . . . . . . . . . . . . .
Video Capture Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Capture Channel x Status Register (VCxSTAT) Field Values . . . . . . . . . . . . . . . .
Video Capture Channel A Control Register (VCACTL) Field Values . . . . . . . . . . . . . . . .
Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Values . . . . . . . . . .
Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Values . . . . . . . . . .
Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Values . . . . . . . . . .
Video Capture Channel x Field 2 Stop Register (VCxSTOP2) Field Values . . . . . . . . . .
Video Capture Channel x Vertical Interrupt Register (VCxVINT) Field Values . . . . . . . .
Video Capture Channel x Threshold Register (VCxTHRLD) Field Values . . . . . . . . . . .
Video Capture Channel x Event Count Register (VCxEVTCT) Field Values . . . . . . . . .
B-383
B-385
B-385
B-386
B-387
B-389
B-390
B-391
B-393
B-394
B-396
B-397
B-398
B-399
B-399
B-400
B-401
B-402
B-403
B-404
B-405
B-406
B-407
B-408
B-409
B-410
B-411
B-412
B-413
B-414
B-416
B-417
B-418
B-421
B-427
B-429
B-431
B-437
B-438
B-439
B-440
B-442
B-444
B-445
Tables
B−326
B−327
B−328
B−329
B−330
B−331
B−332
B−333
B−334
B−335
B−336
B−337
B−338
B−339
B−340
B−341
B−342
B−343
B−344
B−345
B−346
B−347
B−348
B−349
B−350
B−351
B−352
B−353
B−354
B−355
B−356
B−357
B−358
B−359
B−360
B−361
B−362
B−363
B−364
B−365
B−366
Video Capture Channel B Control Register (VCBCTL) Field Values . . . . . . . . . . . . . . . .
TSI Capture Control Register (TSICTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI Clock Initialization LSB Register (TSICLKINITL) Field Values . . . . . . . . . . . . . . . . . .
TSI Clock Initialization MSB Register (TSICLKINITM) Field Values . . . . . . . . . . . . . . . .
TSI System Time Clock LSB Register (TSISTCLKL) Field Values . . . . . . . . . . . . . . . . . .
TSI System Time Clock MSB Register (TSISTCLKM) Field Values . . . . . . . . . . . . . . . . .
TSI System Time Clock Compare LSB Register (TSISTCMPL) Field Values . . . . . . . .
TSI System Time Clock Compare MSB Register (TSISTCMPM) Field Values . . . . . . .
TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) Field Values . . .
TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) Field Values . .
TSI System Time Clock Ticks Interrupt Register (TSITICKS) Field Values . . . . . . . . . .
Video Display Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Status Register (VDSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Control Register (VDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Frame Size Register (VDFRMSZ) Field Values . . . . . . . . . . . . . . . . . . . . .
Video Display Horizontal Blanking Register (VDHBLNK) Field Values . . . . . . . . . . . . . .
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Values . . . .
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Values . . . . .
Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Values . . . .
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Values . . . . .
Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Values . . . . . . . . . . .
Video Display Field 1 Image Size Register (VDIMGSZ1) Field Values . . . . . . . . . . . . . .
Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Values . . . . . . . . . . .
Video Display Field 2 Image Size Register (VDIMGSZ2) Field Values . . . . . . . . . . . . . .
Video Display Field 1 Timing Register (VDFLDT1) Field Values . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Timing Register (VDFLDT2) Field Values . . . . . . . . . . . . . . . . . . .
Video Display Threshold Register (VDTHRLD) Field Values . . . . . . . . . . . . . . . . . . . . . .
Video Display Horizontal Synchronization Register (VDHSYNC) Field Values . . . . . . .
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Counter Reload Register (VDRELOAD) Field Values . . . . . . . . . . . . . . . .
Video Display Display Event Register (VDDISPEVT) Field Values . . . . . . . . . . . . . . . . .
Video Display Clipping Register (VDCLIP) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Default Display Value Register (VDDEFVAL) Field Values . . . . . . . . . . .
Video Display Vertical Interrupt Register (VDVINT) Field Values . . . . . . . . . . . . . . . . . . .
Video Display Field Bit Register (VDFBIT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Values . . . . . . . .
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Values . . . . . . . .
Video Port GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
B-446
B-451
B-453
B-454
B-455
B-456
B-457
B-458
B-459
B-460
B-461
B-462
B-464
B-465
B-470
B-472
B-473
B-475
B-476
B-478
B-479
B-480
B-482
B-483
B-484
B-485
B-487
B-488
B-489
B-490
B-491
B-492
B-493
B-494
B-495
B-497
B-498
B-500
B-501
B-503
B-504
xxxv
Tables
B−367
B−368
B−369
B−370
B−371
B−372
B−373
B−374
B−375
B−376
B−377
B−378
B−379
B−380
B−381
B−382
B−383
B−384
B−385
B−386
C−1
C−2
C−3
C−4
xxxvi
Video Port Peripheral Identification Register (VPPID) Field Values . . . . . . . . . . . . . . . . . B-505
Video Port Peripheral Control Register (PCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . B-507
Video Port Pin Function Register (PFUNC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . B-508
Video Port Pin Direction Register (PDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-510
Video Port Pin Data Input Register (PDIN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . B-514
Video Port Pin Data Out Register (PDOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . B-516
Video Port Pin Data Set Register (PDSET) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . B-518
Video Port Pin Data Clear Register (PDCLR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-520
Video Port Pin Interrupt Enable Register (PIEN) Field Values . . . . . . . . . . . . . . . . . . . . . B-522
Video Port Pin Interrupt Polarity Register (PIPOL) Field Values . . . . . . . . . . . . . . . . . . . . B-524
Video Port Pin Interrupt Status Register (PISTAT) Field Values . . . . . . . . . . . . . . . . . . . . B-526
Video Port Pin Interrupt Clear Register (PICLR) Field Values . . . . . . . . . . . . . . . . . . . . . B-528
Expansion Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-529
Expansion Bus Global Control Register (XBGC) Field Values . . . . . . . . . . . . . . . . . . . . . B-530
Expansion Bus XCE Space Control Register (XCECTL) Field Values . . . . . . . . . . . . . . B-531
Expansion Bus Host Port Interface Control Register (XBHC) Field Values . . . . . . . . . . B-533
Expansion Bus Internal Master Address Register (XBIMA) Field Values . . . . . . . . . . . . B-535
Expansion Bus External Address Register (XBEA) Field Values . . . . . . . . . . . . . . . . . . . B-535
Expansion Bus Data Register (XBD) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-536
Expansion Bus Internal Slave Address Register (XBISA) Field Values . . . . . . . . . . . . . . B-536
CSL APIs for L2 Cache Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
CSL APIs for L1 Cache Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Mapping of Old L2 Register Names to New L2 Register Names . . . . . . . . . . . . . . . . . . . . . C-2
Mapping of New L2ALLOCx Bit Field Names to Old Bit Field Names (C64x only) . . . . . . C-3
Chapter 1
CSL Overview
This chapter provides an overview of the chip support library (CSL), shows
which TMS320C6000 devices support the various application programming
interfaces (APIs), and lists each of the API modules.
Topic
Page
1.1
CSL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2
CSL Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3
CSL Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4
CSL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.5
CSL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6
CSL Symbolic Constant Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.7
Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.8
CSL API Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1-1
CSL Introduction
1.1 CSL Introduction
The chip support library (CSL) provides a C-language interface for configuring
and controlling on-chip peripherals. It consists of discrete modules that are
built and archived into a library file. Each module relates to a single peripheral
with the exception of several modules that provide general programming
support, such as the interrupt request (IRQ) module which contains APIs for
interrupt management, and the CHIP module which allows the global setting
of the chip.
1.1.1
Benefits of the CSL
The benefits of the CSL include peripheral ease of use, shortened
development time, portability, hardware abstraction, and a level of
standardization and compatibility among devices. Specifically, the CSL offers:
- Standard Protocol-to-Program Peripherals
The CSL provides a standard protocol for programming the on-chip
peripherals. This includes data types and macros to define a peripheral’s
configuration, and functions to implement the various operations of each
peripheral.
- Basic Resource Management
Basic resource management is provided through the use of Open and
Close functions for many of the peripherals. This is especially helpful for
peripherals that support multiple channels.
- Symbolic Peripheral Descriptions
As a side benefit to the creation of the CSL, a complete symbolic
description of all peripheral registers and register fields has been created.
You will find it advantageous to use the higher−level protocols described in
the first two benefits, because these are less device−specific, thus making
it easier to migrate your code to newer versions of TI DSPs.
The symbolic constants used to program any peripheral are listed in its
peripheral reference guide among the register descriptions.
1.1.2
CSL Architecture
The CSL granularity is designed such that each peripheral is covered by a
single API module. Hence, there is a direct memory access (DMA) API module
for the DMA peripheral, a multichannel buffered serial port (McBSP) API
module for the McBSP peripheral, and so on.
1-2
CSL Introduction
Figure 1−1 illustrates some of the individual API modules (see section 1.8 for
a complete list). This architecture allows for future expansion of the CSL
because new API modules can be added as new peripheral devices emerge.
Figure 1−1. API Module Architecture
CACHE
CHIP
CSL
DAT
DMA
...
MCBSP TIMER
...
It is important to note that not all devices support all API modules. This
depends on if the device actually has the peripheral to which an API relates.
For example, the enhanced direct memory access (EDMA) API module is not
supported on a C6201 because this device does not have an EDMA
peripheral. Other modules such as the interrupt request (IRQ) module,
however, are supported on all devices.
Table 1−1 lists general and peripheral modules with their associated include
file and the module support symbol. These components must be included in
your application.
Table 1−1. CSL Modules and Include Files
Peripheral
Module (PER)
Description
Include File
Module Support
Symbol†
CACHE
Cache module
csl_cache.h
CACHE_SUPPORT
CHIP
Chip-specific module
csl_chip.h
CHIP_SUPPORT
CSL
Top-level module
csl.h
NA
DAT
Device independent data copy/fill module
csl_dat.h
DAT_SUPPORT
DMA
Direct memory access module
csl_dma.h
DMA_SUPPORT
EMAC
Ethernet media access controller module
csl_emac.h
EMAC_SUPPORT
EDMA
Enhanced direct memory access module
csl_edma.h
EDMA_SUPPORT
EMIF
External memory interface module
csl_emif.h
EMIF_SUPPORT
EMIFA
External memory interface A module
csl_emifa.h
EMIFA_SUPPORT
EMIFB
External memory interface B module
csl_emifb.h
EMIFB_SUPPORT
GPIO
General-Purpose input/output module
csl_gpio.h
GPIO_SUPPORT
CSL Overview
1-3
CSL Introduction
Peripheral
Module (PER)
Description
Include File
Module Support
Symbol†
HPI
Host port interface module
csl_hpi.h
HPI_SUPPORT
I2C
Inter−Integrated circuit module
csl_i2c.h
I2C_SUPPORT
IRQ
Interrupt controller module
csl_irq.h
IRQ_SUPPORT
McASP
Multichannel audio serial port module
csl_mcasp.h
MCASP_SUPPORT
McBSP
Multichannel buffered serial port module
csl_mcbsp.h
MCBSP_SUPPORT
MDIO
Management data I/O module
csl_mdio.h
MDIO_SUPPORT
PCI
Peripheral component interconnect interface
module
csl_pci.h
PCI_SUPPORT
PWR
Power-down module
csl_pwr.h
PWR_SUPPORT
TCP
Turbo decoder coprocessor module
csl_tcp.h
TCP_SUPPORT
TIMER
Timer module
csl_timer.h
TIMER_SUPPORT
UTOP
Utopia interface module
csl_utop.h
UTOP_SUPPORT
VCP
Viterbi decoder coprocessor module
csl_vcp.h
VCP_SUPPORT
VIC
VCXO interpolated control
csl_vic.h
VIC_SUPPORT
VP
Video port module
csl_vp.h
VP_SUPPORT
XBUS
Expansion bus module
csl_xbus.h
XBUS_SUPPORT
† See definition in the related CSL module.
1.1.3
Interdependencies
Although each API module is unique, there exists some interdependency
between the modules. For example, the DMA module depends on the IRQ
module. This comes into play when linking code because if you use the DMA
module, the IRQ module automatically gets linked also.
1-4
CSL Naming Conventions
1.2 CSL Naming Conventions
Table 1−2 shows the conventions used when naming CSL functions, macros,
and data types.
Table 1−2. CSL Naming Conventions
Object Type
Naming Convention
Function
PER_funcName()†
Variable
PER_varName†
Macro
PER_MACRO_NAME†
Typedef
PER_Typename†
Function Argument
funcArg
Structure Member
memberName
† PER is the placeholder for the module name.
- All functions, variables, macros, and data types start with PER_ (where
PER is the module/peripheral name) in caps (uppercase letters)
- Function names follow the peripheral name and use all small (lower-case)
letters. Capital letters are used only if the function name consists of two
separate words, such as PER_getConfig()
- Macro names follow the peripheral name and use all caps, for example,
DMA_PRICTL_RMK
- Data types start with uppercase letters followed by lowercase letters, such
as DMA_Handle
Note: CSL Macro and Function Names
The CSL macro and constant names are defined for each register and each
field in CSL include files. Therefore, you will need to be careful not to redefine
macros using similar names.
Because many CSL functions are predefined in CSL libraries, you will need
to name your own functions carefully.
CSL Overview
1-5
CSL Data Types
1.3 CSL Data Types
The CSL provides its own set of data types. Table 1−3 lists the CSL data types
as defined in the stdinc.h file.
Table 1−3. CSL Data Types
Data Type
Description
Uint8
unsigned char
Uint16
unsigned short
Uint32
unsigned int
Uint40
unsigned long
Int8
char
Int16
short
Int32
int
Int40
long
These data types are available to all CSL modules. Additional data types are
defined within each module and are described by each module’s chapter.
1-6
CSL Functions
1.4 CSL Functions
Table 1−4 provides a generic description of the most common CSL functions
where PER indicates a peripheral as listed in Table 1−1. Because not all of the
functions are available for all the modules, specific descriptions and functions
are listed in each module chapter.
The following conventions are used and are shown in Table 1−4.
- Italics indicate variable names.
- Brackets [...] indicate optional parameters.
J
[handle] is required only for the handle-based peripherals: DAT, DMA,
EDMA, GPIO, McBSP, and TIMER. See section 1.7.1.
J
[priority] is required only for the DAT peripheral module.
Table 1−4. Generic CSL Functions
Function
Description
handle = PER_open(
channelNumber,
[priority]
flags
Opens a peripheral channel and then performs the operation indicated by flags;
must be called before using a channel. The return value is a unique device handle
to use in subsequent API calls.
The priority parameter applies only to the DAT module.
)
PER_config(
[handle,]
*configStructure
)
Writes the values of the configuration structure to the peripheral registers. You can
initialize the configuration structure with:
- Integer constants
- Integer variables
- CSL symbolic constants, PER_REG_DEFAULT (See Section 1.6 CSL Symbolic Constant Values)
- Merged field values created with the PER_REG_RMK macro
PER_configArgs(
[handle,]
regval_1,
.
.
.
Writes the individual values (regval_n) to the peripheral registers. These values
can be any of the following:
- Integer constants
- Integer variables
- CSL symbolic constants, PER_REG_DEFAULT
- Merged field values created with the PER_REG_RMK macro
regval_n
)
PER_reset(
[handle]
)
Resets the peripheral to its power-on default values.
PER_close(
handle
)
Closes a peripheral channel previously opened with PER_open(). The registers
for the channel are set to their power-on defaults, and any pending interrupt is
cleared.
CSL Overview
1-7
CSL Functions
1.4.1
Peripheral Initialization via Registers
The CSL provides two types of functions for initializing the registers of a
peripheral: PER_config() and PER_configArgs() (where PER is the
peripheral as listed in Table 1−1).
- PER_config() initializes the control registers of the PER peripheral,
where PER is one of the CSL modules. This function requires an address
as its one parameter. The address specifies the location of a structure that
represents the peripherals register values. The configuration structure
data type is defined for each peripheral module that contains the
PER_config() function. Example 1−1 shows an example of this method.
Example 1−1. Using PER_config() with the configuration structure PER_Config
PER_Config MyConfig = {
reg0,
reg1,
…
};
…
PER_config(&MyConfig);
- PER_configArgs() allows you to pass the individual register values as
arguments to the function, which then writes those individual values to the
register. Example 1−2 shows an example of this method.
You can use these two initialization functions interchangeably but you still
need to generate the register values. To simplify the process of defining the
values to write to the peripheral registers, the CSL provides the PER_REG_RMK
(make) macros, which form merged values from a list of field arguments.
Macros are discussed in Section 1.5, CSL Macros.
Example 1−2. Using PER_configArgs
PER_configArgs(reg0, reg1, …);
1-8
CSL Macros
1.5 CSL Macros
Table 1−5 provides a generic description of the most common CSL macros,
where:
- PER indicates a peripheral. (e.g., DMA)
- REG indicates, if applicable, a register name (e.g., PRICTL0, AUXCTL)
- FIELD indicates a field in a register (e.g., ESIZE)
- regval indicates an integer constant, an integer variable, a symbolic
constant (PER_REG_DEFAULT), or a merged field value created with the
peripheral field make macro, PER_FMK().
- fieldval indicates an integer constant, integer variable, or symbolic
constant (PER_REG_FIELD_SYMVAL) as explained in section 1.6); all
field values are right justified
- x indicates an integer constant, integer variable.
- sym indicates a symbolic constant
- CSL also offers equivalent macros to those listed in Table 1−5, but instead
of using REG to identify which channel the register belongs to, it uses the
handle value. The handle value is returned by the PER_open() function
(see section 1.7). These macros are shown in Table 1−6.
Each API chapter provides specific descriptions of the macros within that
module. Page references to the macros in the hardware abstraction layer
(Chapter 28, Using the HAL Macros), are provided for additional information.
CSL Overview
1-9
CSL Macros
Table 1−5. Generic CSL Macros
Macro
Description
PER_REG_RMK(
fieldval_n,
.
.
.
fieldval_0
)
Creates a value to store in the peripheral register; _RMK macros make it easier
to construct register values based on field values.
PER_RGET(REG
)
Returns the value in the peripheral register.
PER_RSET(REG,
regval
)
Writes the value to the peripheral register.
PER_FMK (REG,
FIELD,
fieldval
)
Creates a shifted version of fieldval that you could OR with the result of other
_FMK macros to initialize register REG. This allows the user to initialize few fields
in REG as an alternative to the _RMK macro, which requires that ALL register
fields be initialized.
PER_FGET(REG,
FIELD
)
Returns the value of the specified FIELD in the peripheral register.
PER_FSET(REG,
FIELD,
fieldval
)
Writes fieldval to the specified FIELD in the peripheral register.
PER_REG_ADDR(REG
)
If applicable, gets the memory address (or subaddress) of the peripheral register
REG.
PER_FSETS (REG,
FIELD,
sym
)
Writes the symbol value to the specified field in the peripheral.
PER_FMKS (REG,
FIELD,
sym
)
Creates a shifted version of the symbol value that you can OR with the result of
other _FMK/_FMKS macros to initialize register REG. (See also PER_FMK()
macro.)
1-10
The following rules apply to the _RMK macros:
- Include only fields that are writable.
- Specify field arguments as most-significant bit first.
- Whether or not they are used, all writable field values must be included.
- If you pass a field value exceeding the number of bits allowed for that
particular field, the _RMK macro truncates that field value.
CSL Macros
Table 1−6. Generic CSL Handle-Based Macros
Macro
Description
PER_ADDRH (h,
REG
)
Returns the address of a memory-mapped register for a given handle.
PER_RGETH (h,
REG
)
Returns the value of a register for a given handle.
PER_RSETH (h,
REG,
x
)
Sets the register value to x for a given handle.
PER_FGETH (h,
REG,
FIELD
)
Returns the value of the field for a given handle.
PER_FSETH (h,
REG,
FIELD,
x
)
Sets the field value to x for a given handle.
PER_FSETSH (h,
REG,
FIELD,
SYM
)
Sets the field value to the symbol value for a given handle.
Handle-based CSL macros are applicable to the following peripherals:
-
DMA
EDMA
GPIO
McBSP
TIMER
I2C
McASP
VP
CSL Overview
1-11
CSL Symbolic Constant Values
1.6 CSL Symbolic Constant Values
To facilitate initialization of values in your application code, the CSL provides
symbolic constants for registers and writable field values as described in
Table 1−7, where:
- PER indicates a peripheral
- REG indicates a peripheral register
- FIELD indicates a field in the register
- SYMVAL indicates the symbolic value of a register field
Each API chapter provides specific descriptions of the symbolic constants
within that module. Page references to the constants in the hardware
abstraction layer (Chapter 28, Using the HAL Macros), are provided for
additional information.
Table 1−7. Generic CSL Symbolic Constants
(a) Constant Values for Registers
Constant
Description
PER_REG_DEFAULT
Default value for a register; corresponds to the register value after a
reset or to 0 if a reset has no effect.
(b) Constant Values for Fields
Constant
Description
PER_REG_FIELD_SYMVAL
Symbolic constant to specify values for individual fields in the specified
peripheral register. See the CSL Registers in Appendix B for the symbolic
values.
PER_REG_FIELD_DEFAULT
Default value for a field; corresponds to the field value after a reset or to
0 if a reset has no effect.
1-12
Resource Management
1.7 Resource Management
CSL provides a limited set of functions that enable resource management for
applications which may support multiple algorithms, such as two McBSP or
two TIMERs, and may reuse the same type of peripheral device.
Resource management in CSL is achieved through API calls to the
PER_open() and PER_close() functions. The PER_open() function
normally takes a device number and a reset flag as the primary arguments and
returns a pointer to a handle structure that contains information about which
channel (DMA) or port (McBSP) was opened, then set “Allocate” flag defined
in the handle structure to 1, meaning the channel or port is in use. When given
a specific device number, the open function checks a global “allocate” flag to
determine its availability. If the device/channel is available, then it returns a
pointer to a predefined handle structure for this device. If the device has
already been opened by another process, then an invalid handle is returned
whose value is equal to the CSL symbolic constant, INV. Note that CSL does
nothing other than return an invalid handle from PER_open(). You must use
this to insure that no resource-usage conflicts occur. It is left to the user to
check the value returned from the PER_open() function to guarantee that the
resource has been allocated.
A device/channel may be freed for use by other processes by a call to
PER_close(). PER_close() clears the allocate flag defined under the
handle structure object and resets the device/channel.
All CSL modules that support multiple devices or channels, such as McBSP
and DMA, require a device handle as a primary argument to most API
functions. For these APIs, the definition of a PER_Handle object is required.
1.7.1
Using CSL Handles
Handles are required only for peripherals that have multiple channels or ports,
such as DMA, EDMA, GPIO, McBSP, TIMER, I2C, and VP.
You obtain a handle by calling the PER_open() function. When you no longer
need a particular channel, free those resources by calling the PER_close()
function. The PER_open() and PER_close() functions ensure that you do
not initialize the same channel more than once.
CSL handle objects are used to uniquely identify an open peripheral
channel/port or device. Handle objects must be declared in the C source, and
initialized by a call to a PER_open() function before calling any other API
functions that require a handle object as an argument. PER_open() returns
a value of “INV” if the resource is already allocated.
CSL Overview
1-13
Resource Management
DMA_Handle myDma;
/* Defines a DMA_Handle object, myDma */
Once defined, the CSL handle object is initialized by a call to PER_open.
•
•
myDma = DMA_open (DMA_CHA0, DMA_OPEN_RESET);
/* Open DMA channel 0 */
The call to DMA_open initializes the handle, myDma. This handle can then be
used in calls to other API functions.
if(myDma != INV) {
DMA_start (myDma);
/* Begin transfer */
•
•
DMA_close (myDma); }
1-14
/* Free DMA channel */
CSL API Module Support
1.8 CSL API Module Support
Not all CSL API modules are supported on all devices. For example, the EDMA
API module is not supported on the C6201 because the C6201 does not have
EDMA hardware. When an API module is not supported, all of its header file
information is conditionally compiled out, meaning the declarations will not
exist. Because of this, calling an EDMA API function on devices not supporting
EDMA will result in a compiler and/or linker error.
Note:
To build the program with the right library, the device support symbol must
be set in the compiler option window. For example, if using C6201, the compiler option set in the preprocessor tab would be −dCHIP_6201.
Table 1−8 and Table 1−9 show which devices support the API modules.
Table 1−8. CSL API Module Support for TMS320C6000 Devices
Module
6201
6202
6203
6204
6205
6211
6701
6711
6712
6713
DA610
CACHE
X
X
X
X
X
X
X
X
X
X
X
CHIP
X
X
X
X
X
X
X
X
X
X
X
DAT
X
X
X
X
X
X
X
X
X
X
X
DMA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EDMA
EMIF
X
X
X
X
X
X
X
X
X
GPIO
HPI
X
X
X
X
I2C
IRQ
X
X
X
X
X
X
X
X
X
McASP
McBSP
X
X
X
X
PCI
X
X
X
X
X
X
PLL
PWR
X
X
X
X
X
X
X
X
X
X
X
TIMER
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XBUS
CSL Overview
1-15
CSL API Module Support
Table 1−9. CSL API Module Support for TMS320C641x and DM642 Devices
Module
6414
6415
6416
6410
6413
DM642
CACHE
X
X
X
X
X
X
CHIP
X
X
X
X
X
X
DAT
X
X
X
X
X
X
X
X
X
X
X
X
DMA
EDMA
EMAC
X
EMIFA
X
X
X
X
X
EMIFB
X
X
X
X
X
EMU
X
GPIO
X
X
X
X
X
X
HPI
X
X
X
X
X
X
IRQ
X
X
X
X
X
X
X
X
X
X
X
X
McASP
McBSP
X
X
X
MDIO
X
PCI
PWR
X
X
X
X
X
TCP
TIMER
UTOP
VCP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VIC
X
VP
X
XBUS
1-16
CSL API Module Support
1.8.1
CSL Endianess/Device Support Library
Table 1−10. CSL Device Support Library Name and Symbol Conventions
Device
Little Endian
Library
Big Endian
Library
Device Support
Symbol
C6201
csl6201.lib
csl6201e.lib
CHIP_6201
C6202
csl6202.lib
csl6202e.lib
CHIP_6202
C6203
csl6203.lib
csl6203e.lib
CHIP_6203
C6204
csl6204.lib
csl6204e.lib
CHIP_6204
C6205
csl6205.lib
csl6205e.lib
CHIP_6205
C6211
csl6211.lib
csl6211e.lib
CHIP_6211
C6701
csl6701.lib
csl6701e.lib
CHIP_6701
C6711
csl6711.lib
csl6711e.lib
CHIP_6711
C6712
csl6712.lib
csl6712e.lib
CHIP_6712
C6713
csl6713.lib
csl6713e.lib
CHIP_6713
C6414
csl6414.lib
csl6414e.lib
CHIP_6414
C6415
csl6415.lib
csl6415e.lib
CHIP_6415
C6416
csl6416.lib
csl6416e.lib
CHIP_6416
DA610
cslDA610.lib
cslDA610e.lib
CHIP_DA610
DM642
cslDM642.lib
cslDM642e.lib
CHIP_DM642
C6410
csl6410.lib
csl6410.lib
CHIP_6410
C6413
csl6413.lib
csl6413.lib
CHIP_6413
CSL Overview
1-17
Chapter 2
CACHE Module
This chapter describes the CACHE module, gives a description of the two
CACHE architectures, lists the functions and macros within the module, and
provides a CACHE API reference section.
Topic
Page
2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-1
Overview
2.1 Overview
The CACHE module functions are used for managing data and program
cache.
Currently, TMS320C6x devices use three cache architectures. The first type,
as seen on the C620x device, provides program cache by disabling on-chip
program RAM and turning it into cache. The second and third types, seen on
C621x/C671x and C64x devices respectively, are the two−level (L2) cache
architectures. For the differences between C621x/C671x and C64x cache
architectures, refer to SPRU610 TMS320C64x DSP Two Level Internal
Memory Reference Guide.
The CACHE module has APIs that are specific for the L2 cache and specific
for the older program cache architecture. However, the API functions are
callable on both types of platforms to make application code portable. On
devices without L2, the L2-specific cache API calls do nothing but return
immediately.
Table 2−1 shows the API functions within the CACHE module.
Table 2−1. CACHE APIs
Syntax
Type Description
See page ...
CACHE_clean{
F
Cleans a specific cache region
2-6
CACHE_enableCaching
F
Enables caching for a specified block of address
space
2-7
CACHE_flush{
F
Flushes a region of cache
2-9
CACHE_getL2Mode
F
Gets the L2 cache mode
2-19
CACHE_getL2SramSize
F
Returns current L2 size configured as SRAM
2-10
CACHE_invalidate{
F
Invalidates a region of cache
2-10
CACHE_invAllL1p
F
L1P invalidate all
2-11
CACHE_invL1d
F
L1D block invalidate (C64x only)
2-11
CACHE_invL1p
F
L1P block invalidate
2-12
CACHE_invL2
F
L2 block invalidate (C64x only)
2-13
CACHE_L1D_LINESIZE
C
A compile time constant whose value is the L1D line
size.
2-14
Note: F = Function; C = Constant; M = Macro
† This API function is provided for backward compatibility. Users should use the new APIs.
‡ Only for C6414, C6415, C6416 devices
2-2
Overview
Table 2−1. CACHE APIs (Continued)
Syntax
Type Description
See page ...
CACHE_L1P_LINESIZE
C
A compile time constant whose value is the L1P line
size.
2-14
CACHE_L2_LINESIZE
C
A compile time constant whose value is the L2 line
size.
2-15
CACHE_reset
F
Resets cache to power-on default
2-15
CACHE_resetEMIFA
F
Resets the MAR registers dedicated to the EMIFA
2-15
CACHE_resetEMIFB‡
F
Resets the MAR registers dedicated to the EMIFB
2-15
CACHE_resetL2Queue
F
Resets the queue length of a given queue to default
value
2-16
CACHE_ROUND_TO_LINESIZE
(CACHE,ELCNT,ELSIZE)
M
Rounds to cache line size
2-16
CACHE_setL2Mode
F
Sets L2 cache mode
2-17
CACHE_setL2Queue
F
Sets the queue length of a given L2 queue
2-20
CACHE_setPriL2Req
F
Sets the L2 requestor priority level
2-20
CACHE_setPccMode
F
Sets program cache mode
2-21
CACHE_SUPPORT
C
A compile time constant whose value is 1 if the
device supports the CACHE module
2-21
CACHE_wait
F
Waits for completion of the last cache operation
2-21
CACHE_wbAllL2
F
L2 writeback all
2-22
CACHE_wbInvL1d
F
L1D block writeback and invalidate
2-23
CACHE_wbInvAllL2
F
L2 writeback and invalidate all
2-24
CACHE_wbInvL2
F
L2 block writeback and invalidate
2-25
CACHE_wbL2
F
L2 block writeback
2-26
Note: F = Function; C = Constant; M = Macro
† This API function is provided for backward compatibility. Users should use the new APIs.
‡ Only for C6414, C6415, C6416 devices
CACHE Module
2-3
Macros
2.2 Macros
There are two types of CACHE macros: those that access registers and fields,
and those that construct register and field values.
Table 2−2 lists the CACHE macros that access registers and fields, and
Table 2−3 lists the CACHE macros that construct register and field values. The
macros themselves are found in Chapter 28, Using the HAL Macros.
CACHE macros are not handle-based.
Table 2−2. CACHE Macros that Access Registers and Fields
Macro
Description/Purpose
CACHE_ADDR()
Register address
28-12
CACHE_RGET()
Returns the value in the peripheral register
28-18
CACHE_RSET(,x)
Register set
28-20
CACHE_FGET(,)
Returns the value of the specified field in the
peripheral register
28-13
CACHE_FSET(,,fieldval)
Writes fieldval to the specified field in the
peripheral register
28-15
CACHE_FSETS(,,)
Writes the symbol value to the specified field in
the peripheral
28-17
CACHE_RGETA(addr,)
Gets register for a given address
28-19
CACHE_RSETA(addr,,x)
Sets register for a given address
28-20
CACHE_FGETA(addr,,)
Gets field for a given address
28-13
CACHE_FSETA(addr,,,
fieldval)
Sets field for a given address
28-16
CACHE_FSETSA(addr,,,
)
Sets field symbolically for a given address
28-17
2-4
See page...
Macros
Table 2−3. CACHE Macros that Construct Register and Field Values
Macro
Description/Purpose
See page ...
CACHE__DEFAULT
Register default value
28-21
CACHE__RMK()
Register make
28-23
CACHE__OF()
Register value of ...
28-22
CACHE___DEFAULT
Field default value
28-24
CACHE_FMK()
Field make
28-14
CACHE_FMKS()
Field make symbolically
28-15
CACHE___OF()
Field value of ...
28-24
CACHE___
Field symbolic value
28-24
CACHE Module
2-5
CACHE_clean
2.3 Functions
CACHE_clean
Cleans a range of L2 cache
Note:
This function is provided for backward compatibility only. The user is strongly
advised to use the new functions as shown in Appendix D.
Function
void CACHE_clean(
CACHE_Region region,
void *addr,
Uint32 wordCnt
);
Arguments
region
Specifies which cache region to clean; must be one of the
following:
- CACHE_L2
- CACHE_L2ALL
addr
Beginning address of range to clean; word aligned
wordCnt
Number of 32-bit words to clean. IMPORTANT: Maximum allowed
wordCnt is 65535.
Return Value
none
Description
Cleans a range of L2 cache. All lines within the range defined by addr and
wordCnt are cleaned out of L2. If CACHE_L2ALL is specified, then all of L2
is cleaned, addr and wordCnt are ignored. A clean operation involves writing
back all dirty cache lines and then invalidating those lines. This routine waits
until the operation completes before returning.
Note: This function does nothing on devices without L2 cache.
Example
If you want to clean a 4K-byte range that starts at 0x80000000 out of L2, use:
CACHE_clean(CACHE_L2,(void*)0x80000000,0x00000400);
If you want to clean all lines out of L2 use:
CACHE_clean(CACHE_L2ALL,(void*)0x00000000,0x00000000);
2-6
CACHE_enableCaching
CACHE_enableCaching
Specifies block of ext. memory for caching
Function
void CACHE_enableCaching(
Uint32 block
);
Arguments
block
Specifies a block of external memory to enable caching for; must
be one of the following:
For devices other than C64x−
- CACHE_CE33 −(0xB3000000 to 0xB3FFFFFF)
- CACHE_CE32 −(0xB2000000 to 0xB2FFFFFF)
- CACHE_CE31 −(0xB1000000 to 0xB1FFFFFF)
- CACHE_CE30 −(0xB0000000 to 0xB0FFFFFF)
- CACHE_CE23 −(0xA3000000 to 0xA3FFFFFF)
- CACHE_CE22 −(0xA2000000 to 0xA2FFFFFF)
- CACHE_CE21 −(0xA1000000 to 0xA1FFFFFF)
- CACHE_CE20 −(0xA0000000 to 0xA0FFFFFF)
- CACHE_CE13 −(0x93000000 to 0x93FFFFFF)
- CACHE_CE12 −(0x92000000 to 0x92FFFFFF)
- CACHE_CE11 −(0x91000000 to 0x91FFFFFF)
- CACHE_CE10 −(0x90000000 to 0x90FFFFFF)
- CACHE_CE03 −(0x83000000 to 0x83FFFFFF)
- CACHE_CE02 −(0x82000000 to 0x82FFFFFF)
- CACHE_CE01 −(0x81000000 to 0x81FFFFFF)
- CACHE_CE00 −(0x80000000 to 0x80FFFFFF)
For C6414, C6415, and C6416 EMIFB
- CACHE_EMIFB_CE00 −(60000000h to 60FFFFFFh)
- CACHE_EMIFB_CE01 −(61000000h to 61FFFFFFh)
- CACHE_EMIFB_CE02 −(62000000h to 62FFFFFFh)
- CACHE_EMIFB_CE03 −(63000000h to 63FFFFFFh)
- CACHE_EMIFB_CE010 −(64000000h to 64FFFFFFh)
- CACHE_EMIFB_CE011 −(65000000h to 65FFFFFFh)
- CACHE_EMIFB_CE012 −(66000000h to 66FFFFFFh)
- CACHE_EMIFB_CE013 −(67000000h to 67FFFFFFh)
- CACHE_EMIFB_CE020 −(68000000h to 68FFFFFFh)
- CACHE_EMIFB_CE021 −(69000000h to 69FFFFFFh)
- CACHE_EMIFB_CE022 −(6A000000h to 6AFFFFFFh)
- CACHE_EMIFB_CE023 −(6B000000h to 6BFFFFFFh)
- CACHE_EMIFB_CE030 −(6C000000h to 6CFFFFFFh)
- CACHE_EMIFB_CE031 −(6D000000h to 6DFFFFFFh)
- CACHE_EMIFB_CE032 −(6E000000h to 6EFFFFFFh)
- CACHE_EMIFB_CE033 −(6F000000h to 6FFFFFFFh)
CACHE Module
2-7
CACHE_enableCaching
For EMIFA CE0−
- CACHE_EMIFA_CE00 −(80000000h to 80FFFFFFh)
- CACHE_EMIFA_CE01 −(81000000h to 81FFFFFFh)
- CACHE_EMIFA_CE02 −(82000000h to 82FFFFFFh)
- CACHE_EMIFA_CE03 −(83000000h to 83FFFFFFh)
- CACHE_EMIFA_CE04 −(84000000h to 84FFFFFFh)
- CACHE_EMIFA_CE05 −(85000000h to 85FFFFFFh)
- CACHE_EMIFA_CE06 −(86000000h to 86FFFFFFh)
- CACHE_EMIFA_CE07 −(87000000h to 87FFFFFFh)
- CACHE_EMIFA_CE08 −(88000000h to 88FFFFFFh)
- CACHE_EMIFA_CE09 −(89000000h to 89FFFFFFh)
- CACHE_EMIFA_CE010 −(8A000000h to 8AFFFFFFh)
- CACHE_EMIFA_CE011 −(8B000000h to 8BFFFFFFh)
- CACHE_EMIFA_CE012 −(8C000000h to 8CFFFFFFh)
- CACHE_EMIFA_CE013 −(8D000000h to 8DFFFFFFh)
- CACHE_EMIFA_CE014 −(8E000000h to 8EFFFFFFh)
- CACHE_EMIFA_CE015 −(8F000000h to 8FFFFFFFh)
For CACHE_EMIFA_CE1, CACHE_EMIFA_CE2, and CACHE_EMIFA_CE3
the symbols are the same as CACHE_EMIFA_CE0, with start addresses
90000000h, A0000000h, and B0000000h, respectively.
Return Value
none
Description
Enables caching for the specified block of memory. This is accomplished by
setting the CE bit in the appropriate memory attribute register (MAR). By
default, caching is disabled for all memory spaces.
Note: This function does nothing on devices without L2 cache.
Example
To enable caching for the range of memory from 0x80000000 to 0x80FFFFFF
use:
For C64x −
CACHE_enableCaching(CACHE_EMIFA_CE00);
For other devices −
CACHE_enableCaching(CACHE_CE00);
2-8
CACHE_flush
CACHE_flush
Flushes region of cache (obsolete)
Note:
This function is provided for backward compatibility only. The user is strongly
advised to use the new functions as shown in Appendix D.
Function
void CACHE_flush(
CACHE_Region region,
void *addr,
Uint32 wordCnt
);
Arguments
region
Specifies which cache region to flush from; must be one of the
following:
- CACHE_L2
- CACHE_L2ALL
- CACHE_L1D
addr
Beginning address of range to flush; word aligned
wordCnt
Number of 32-bit words to flush. IMPORTANT: Maximum allowed
wordCnt is 65535.
Return Value
none
Description
Flushes a range of L2 cache. All lines within the range defined by addr and
wordCnt are flushed out of L2. If CACHE_L2ALL is specified, then all of L2 is
flushed; addr and wordCnt are ignored. A flush operation involves writing
back all dirty cache lines, but the lines are not invalidated. This routine waits
until the operation completes before returning.
Note: This function does nothing on devices without L2 cache.
Example
If you want to flush a 4K-byte range that starts at 0x80000000 out of L2, use:
CACHE_flush(CACHE_L2,(void*)0x80000000,0x00000400);
If you want to flush all lines out of L2, use:
CACHE_flush(CACHE_L2ALL,(void*)0x00000000,0x00000000);
CACHE Module
2-9
CACHE_getL2SramSize
CACHE_getL2SramSize Returns current size of L2 that is configured as SRAM
Function
Uint32 CACHE_getL2SramSize();
Arguments
none
Return Value
size
Description
This function returns the current size of L2 that is configured as SRAM.
Returns number of bytes of on-chip SRAM
Note: This function does nothing on devices without L2 cache.
Example
SramSize = CACHE_getL2SramSize();
CACHE_invalidate Invalidates a region of cache (obsolete)
Note:
This function is provided for backward compatibility only. The user is strongly
advised to use the new functions as shown in Appendix D.
Function
void CACHE_invalidate(
CACHE_Region region,
void *addr,
Uint32 wordCnt
);
Arguments
region
Specifies which cache region to invalidate; must be one of the
following:
- CACHE_L1P Invalidate L1P
- CACHE_L1PALL
Invalidate all of L1P
- CACHE_L1DALL Invalidate all of L1D
addr
Beginning address of range to invalidate; word aligned
wordCnt
Number of 32-bit words to invalidate. IMPORTANT: Maximum
allowed wordCnt is 65535.
Return Value
none
Description
Invalidates a range from cache. All lines within the range defined by addr and
wordCnt are invalidated from region. If CACHE_L1PALL is specified, then
all of L1P is invalidated; addr and wordCnt are ignored. Likewise, if
CACHE_L1DALL is specified, then all of L1D is invalidated; addr and
wordCnt are ignored. This routine waits until the operation completes before
returning.
2-10
CACHE_invAllL1p
Note: This function does nothing on devices without L2 cache.
Example
If you want to invalidate a 4K-byte range that starts at 0x80000000 from L1P,
use:
CACHE_invalidate(CACHE_L1P,(void*)0x80000000,0x00000400);
If you want to invalidate all lines from L1D, use:
CACHE_invalidate(CACHE_L1DALL,(void*)0x00000000,0x00000000);
CACHE_invAllL1p L1P invalidates all
Function
void CACHE_invAllL1p();
Arguments
none
Return Value
none
Description
This function issues an L1P invalidate all command to the cache controller.
Please see the TMS320C621x/C671x DSP Two Level Internal Memory
Reference Guide (literature number SPRU609) and the TMS320C64x DSP
Two Level Internal Memory Reference Guide (literature number SPRU610) for
details of this operation.
Example
CACHE_invAllL1p();
CACHE_invL1d
L1D block invalidate (C64x only)
Function
void CACHE_invL1d(
void
*blockPtr,
Uint32
byteCnt,
int
wait
);
Arguments
blockPtr
Pointer to the beginning of the block
byteCnt
Number of bytes in the block. This value must be a multiple of four.
The largest size this can be in 65535*4.
wait
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
Return Value
none
CACHE Module
2-11
CACHE_invL1p
Description
This function issues an L1D block invalidate command to the cache controller.
Please see the TMS320C64x DSP Two Level Internal Memory Reference
Guide (literature number SPRU610) for details of this operation. If a previous
cache operation is still active, the function waits for its completion before
initiating the new operation, in order to prevent lockout of interrupts.
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Although the block size can be specified in number of bytes, the cache
controller operates on whole cache lines only.
This function is only supported on C64x devices.
Example
CACHE_invL1p
char buffer[1024];
/* call with wait flag set */
CACHE_invL1d(buffer, 1024, CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_invL1d(buffer, 1024, CACHE_NOWAIT);
...
...
CACHE_wait();
L1P block invalidate
Function
void CACHE_invL1p(
void
*blockPtr,
Uint32
byteCnt,
int
wait
);
Arguments
blockPtr
Pointer to the beginning of the block
byteCnt
Number of bytes in the block. This value must be a multiple of four.
The largest size this can be in 65535*4.
wait
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
Return Value
2-12
none
CACHE_invL2
Description
This function issues an L1P block invalidate command to the cache controller.
Please see the TMS320C621x/C671x DSP Two Level Internal Memory
Reference Guide (literature number SPRU609) and the TMS320C64x DSP
Two Level Internal Memory Reference Guide (literature number SPRU610) for
details of this operation. If a previous cache operation is still active, the function
waits for its completion before initiating the new operation, in order to prevent
lockout of interrupts.
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Although the block size can be specified in number of bytes, the cache
controller operates on whole cache lines only.
Example
CACHE_invL2
char buffer[1024];
/* call with wait flag set */
CACHE_invL1p(buffer, 1024, CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_invL1p(buffer, 1024, CACHE_NOWAIT);
...
...
CACHE_wait();
L2 block invalidate (C64x devices only)
Function
void CACHE_invL2(
void
*blockPtr,
Uint32
byteCnt,
int
wait
);
Arguments
blockPtr
Pointer to the beginning of the block
byteCnt
Number of bytes in the block. This value must be a multiple of four.
The largest size this can be in 65535*4.
wait
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
Return Value
none
CACHE Module
2-13
CACHE_L1D_LINESIZE
Description
This function issues an L2 block invalidate command to the cache controller.
Please see the TMS320C64x DSP Two Level Internal Memory Reference
Guide (literature number SPRU610) for details of this operation. If a previous
cache operation is still active, the function waits for its completion before
initiating the new operation, in order to prevent lockout of interrupts.
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Although the block size can be specified in number of bytes, the cache
controller operates on whole cache lines only. To prevent unintended behavior,
blockPtr and byteCnt should be multiples of the cache line size.
This function is supported on C64x devices only.
Example
char buffer[1024];
/* call with wait flag set */
CACHE_invL2(buffer, 1024, CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_invL2(buffer, 1024, CACHE_NOWAIT);
...
...
CACHE_wait();
CACHE_L1D_LINESIZE L1D line size
Constant
CACHE_L1D_LINESIZE
Description
Compile-time constant that is set equal to the L1D cache line size of the device.
Example
#pragma DATA_ALIGN(array, CACHE_L1D_LINESIZE)
CACHE_L1P_LINESIZE L1P line size
Constant
CACHE_L1P_LINESIZE
Description
Compile-time constant that is set equal to the L1P cache line size of the device.
Example
#pragma DATA_ALIGN(array, CACHE_L1P_LINESIZE)
2-14
CACHE_L2_LINESIZE
CACHE_L2_LINESIZE L2 line size
Constant
CACHE_L2_LINESIZE
Description
Compile-time constant that is set equal to the L2 cache line size of the device.
Example
#pragma DATA_ALIGN(array, CACHE_L2_LINESIZE)
CACHE_reset
Resets cache to power-on default
Function
void CACHE_reset();
Arguments
none
Return Value
none
Description
Resets cache to power-on default.
Devices with L2 Cache: All MAR bits are cleared
Devices without L2 Cache: PCC field of CSR set to zero (mapped)
Note: If you reset the cache, any dirty data will be lost. If you want to preserve
this data, flush it out first.
Example
CACHE_reset();
CACHE_resetEMIFA Resets the MAR registers dedicated to the EMIFA CE spaces
Function
void CACHE_resetEMIFA();
Arguments
none
Return Value
none
Description
This function resets the MAR registers dedicated to the EMIFA CE spaces.
Example
CACHE_enableCaching(CACHE_EMIFA_CE00);
CACHE_enableCaching(CACHE_EMIFA_CE13);
CACHE_resetEMIFA();
CACHE_resetEMIFB Resets the MAR registers dedicated to the EMIFB CE spaces
Function
void CACHE_resetEMIFB();
Arguments
none
Return Value
none
Description
This function resets all the MAR registers dedicated to the EMIFB CE spaces.
This is defined only for C6414, C6415 and C6416 devices.
Example
CACHE_enableCaching(CACHE_EMIFB_CE00);
CACHE_enableCaching(CACHE_EMIFB_CE13);
CACHE_resetEMIFB();
CACHE Module
2-15
CACHE_resetL2Queue
CACHE_resetL2Queue
Resets the queue length of the L2 queue to its default value
Function
void CACHE_resetL2Queue(
Uint32 queueNum
);
Arguments
queueNum Queue number to be reset to the default length: The following
constants may be used for L2 queue number:
- CACHE_L2Q0
- CACHE_L2Q1
- CACHE_L2Q2
- CACHE_L2Q3
Return Value
none
Description
This functions allows the user to reset the queue length of the given L2 queue
to its default value. See the CACHE_setL2Queue() function.
Example
EDMA_setL2Queue(CACHE_L2Q2,4);
EDMA_resetL2Queue(CACHE_L2Q2);
CACHE_ROUND_TO_LINESIZE Rounds to cache line size
Macro
CACHE_ROUND_TO_LINESIZE(
CACHE,
ELCNT,
ELSIZE
);
Arguments
CACHE
Cache type: L1D, L1P, or L2
ELCNT
Element count
ELSIZE
Element size
Return Value
Rounded up element count
Description
This macro rounds an element up to make an array size a multiple number of
cache lines.
Arrays located in external memory that require user-controlled coherence
maintenance must be aligned at a cache line boundary and be a multiple of
cache lines large to prevent incoherency problems. Please see the
TMS320C6000 DSP Cache User’s Guide (literature number SPRU656) for
details.
2-16
CACHE_setL2Mode
Example
CACHE_setL2Mode
/* assume an L2 line size of 128 bytes */
/* align arrays y and x at the cache line border */
#pragma DATA_ALIGN(y, CACHE_L2_LINESIZE)
#pragma DATA_ALIGN(x, CACHE_L2_LINESIZE)
/* array y spans 7 full lines and 104 bytes of the next line*/
short y[500];
/* the array element count is increased such that the array x
spans a multiple number of cache lines, i.e. 8 lines */
short x[CACHE_ROUNT_TO_LINESIZE(L2, 500, sizeof(short))]
Sets L2 cache mode
Function
CACHE_L2Mode CACHE_setL2Mode(
CACHE_L2Mode newMode
);
Arguments
newMode
New L2 cache mode; must be one of the following:
(For C6711/C6211)
- CACHE_64KSRAM
- CACHE_0KCACHE
- CACHE_48KSRAM
- CACHE_16KCACHE
- CACHE_32KSRAM
- CACHE_32KCACHE
- CACHE_16KSRAM
- CACHE_48KCACHE
- CACHE_0KSRAM
- CACHE_64KCACHE
(For C6713 and DA610)
- CACHE_256KSRAM
- CACHE_0KCACHE
- CACHE_240KSRAM
- CACHE_16KCACHE
- CACHE_224KSRAM
- CACHE_32KCACHE
- CACHE_208KSRAM
- CACHE_48KCACHE
- CACHE_192KSRAM
- CACHE_64KCACHE
CACHE Module
2-17
CACHE_setL2Mode
(For C6414/C6415/C6416)
- CACHE_1024KSRAM
- CACHE_0KCACHE
- CACHE_992KSRAM
- CACHE_32KCACHE
- CACHE_960KSRAM
- CACHE_64KCACHE
- CACHE_896KSRAM
- CACHE_128KCACHE
- CACHE_768KSRAM
- CACHE_256KCACHE
(For C6410)
- CACHE_128KSRAM
- CACHE_0KCACHE
- CACHE_96KSRAM
- CACHE_32KCACHE
- CACHE_64KSRAM
- CACHE_64KCACHE
- CACHE_128KCACHE
(For C6413)
- CACHE_256KSRAM
- CACHE_0KCACHE
- CACHE_224KSRAM
- CACHE_32KCACHE
- CACHE_192KSRAM
- CACHE_64KSRAM
- CACHE_128KSRAM
- CACHE_128KCACHE
- CACHE_256KCACHE
(For DM642)
- CACHE_256KSRAM
- CACHE_0KCACHE
- CACHE_224KSRAM
- CACHE_32KCACHE
- CACHE_192KSRAM
- CACHE_64KCACHE
- CACHE_128KSRAM
- CACHE_128KCACHE
- CACHE_0KSRAM
2-18
CACHE_getL2Mode
- CACHE_256KCACHE
Return Value
oldMode
Returns old cache mode, one of those listed above.
Description
This function sets the mode of the L2 cache. There are three conditions that
may occur as a result of changing cache modes:
1. A decrease in cache size
2. An increase in cache size
3. No change in cache size
If the cache size decreases, all of L2 is writeback-invalidated, then the mode
is changed. If the cache size increases, the part of SRAM that is about to be
turned into cache is writeback-invalidated from L1D and all of L2 is
writeback-invalidated; then the mode is changed. Nothing happens when
there is no change.
Increasing cache size means that some of the SRAM is lost. If there is data
in the SRAM that should not be lost, it must be preserved before changing
cache modes. Some of the cache modes are identical. For example, on the
C6211, there are 64KBytes of L2; hence, CACHE_16KSRAM is equivalent to
CACHE_48KCACHE. However, if the L2 size changes on a future device, this
will not be the case. Note: This function does nothing on devices without L2
cache.
Example
CACHE_L2Mode OldMode;
OldMode = CACHE_setL2Mode(CACHE_32KCACHE);
CACHE_getL2Mode Returns Level 2 Cache mode
Function
voide CACHE_getL2Mode();
Arguments
None
Return Value
Leve 2 Cache mode (listed under CACHE_setL2Mode function explanation)
Description
This retuns the current L2 cache mode. If L2 cache is not supported, it returns
CACHE_0KCACHE.
Example
CACHE_L2Mode oldMode:
OldMode = CACHE_getL2Mode();
CACHE Module
2-19
CACHE_setL2Queue
CACHE_setL2Queue
Sets the queue length of the L2 queue
Function
void CACHE_setL2Queue(
Uint32 queueNum;
Uint32 length
);
Arguments
queueNum
Queue number to be set. The following constants may be
used for L2 queue number:
- CACHE_L2Q0
- CACHE_L2Q1
- CACHE_L2Q2
- CACHE_L2Q3
length
Queue length to be set
Return Value
none
Description
This function allows the user to set the queue length of a specified L2 also
CACHE_resetL2Queue() function.
Example
CACHE_setL2Queue(CACHE_L2Q1,5);
CACHE_setPriL2Req
Sets the L2 priority level “P” of the CCFG register
Function
void CACHE_setPriL2Req(
Uint32 priority
);
Arguments
priority
Return Value
none
Description
This function allows the user to set the L2 priority level “P” of the CCFG
register.
Example
CACHE_setPriL2Req(CACHE_L2PRIHIGH);
2-20
Priority request level to be set. The following constants may be
used:
- CACHE_L2PRIURG
(0)
- CACHE_L2PRIHIGH
(1)
- CACHE_L2PRIMED
(2)
- CACHE_L2PRILOW
(3)
CACHE_setPccMode
CACHE_setPccMode Sets program cache mode
Function
CACHE_Pcc CACHE_setPccMode(
CACHE_Pcc newMode
);
Arguments
newMode
New program cache mode; must be one of the following:
- CACHE_PCC_MAPPED
- CACHE_PCC_ENABLE
Return Value
OldMode
Returns the old program cache mode; will be one of the following:
- CACHE_PCC_MAPPED
- CACHE_PCC_ENABLE
Description
This function sets the program cache mode for devices that do not have an L2
cache. For devices that do have an L2 cache such as the C6211, this function
does nothing. See the TMS320C6000 Peripherals Reference Guide
(SPRU190) for the meaning of the cache modes.
Example
To enable the program cache in normal mode, use:
CACHE_Pcc OldMode;
OldMode = CACHE_setPccMode(CACHE_PCC_ENABLE);
CACHE_SUPPORT Compile time constant
Constant
CACHE_SUPPORT
Description
Compile time constant that has a value of 1 if the device supports the CACHE
module and 0 otherwise. You are not required to use this constant.
Currently, all devices support this module.
Example
CACHE_wait
#if (CACHE_SUPPORT)
/* user cache configuration */
#endif
Waits for completion of the last cache operation
Function
int CACHE_wait();
Arguments
none
Return Value
none
CACHE Module
2-21
CACHE_wbAllL2
Description
This function waits for the completion of the last cache operation.
This function ONLY works in conjunction with the following operations:
-
Example
CACHE_wbAllL2
CACHE_wbL2()
CACHE_invL2()
CACHE_wbInvL2()
CACHE_wbAllL2()
CACHE_wbInvAllL2()
CACHE_invL1d()
CACHE_wbInvL1d()
CACHE_invL1p()
CACHE_wbInvAllL2(CACHE_NOWAIT);
...
...
CACHE_wait();
L2 writeback all
Function
void CACHE_wbAllL2(
int
wait
);
Arguments
wait
Return Value
none
Description
This function issues an L2 writeback all command to the cache controller.
Please see the TMS320C621x/C671x DSP Two Level Internal Memory
Reference Guide (literature number SPRU609) and the TMS320C64x DSP
Two Level Internal Memory Reference Guide (literature number SPRU610) for
details of this operation.
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Example
2-22
/* call with wait flag set */
CACHE_wbAllL2(CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_wbAllL2(CACHE_NOWAIT);
...
CACHE_wait();
CACHE_wbInvL1d
CACHE_wbInvL1d L1D block writeback and invalidate
Function
void CACHE_wbInvL1d(
void
*blockPtr,
Uint32
byteCnt,
int
wait
);
Arguments
blockPtr
Pointer to the beginning of the block
byteCnt
Number of bytes in the block. This value must be a multiple of four.
The largest size this can be in 65535*4.
wait
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
Return Value
none
Description
This function issues an L1D block writeback and invalidate command to the
cache controller. Please see the TMS320C621x/C671x DSP Two Level
Internal Memory Reference Guide (literature number SPRU609) and the
TMS320C64x DSP Two Level Internal Memory Reference Guide (literature
number SPRU610) for details of this operation. If a previous cache operation
is still active, the function waits for its completion before initiating the new
operation, in order to prevent lockout of interrupts.
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Although the block size can be specified in number of bytes, the cache
controller operates on whole cache lines only.
Example
char buffer[1024];
/* call with wait flag set */
CACHE_wbInvL1d(buffer, 1024, CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_wbInvL1d(buffer, 1024, CACHE_NOWAIT);
...
...
CACHE_wait();
CACHE Module
2-23
CACHE_wbInvAllL2
CACHE_wbInvAllL2 L2 writeback and invalidate all
Function
void CACHE_wbInvAllL2(
int
wait
);
Arguments
wait
Return Value
none
Description
This function issues an L2 writeback and invalidate all command to the cache
controller. Please see the TMS320C621x/C671x DSP Two Level Internal
Memory Reference Guide (literature number SPRU609) and the
TMS320C64x DSP Two Level Internal Memory Reference Guide (literature
number SPRU610) for details of this operation.
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Example
2-24
/* call with wait flag set */
CACHE_wbInvAllL2(CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_wbInvAllL2(CACHE_NOWAIT);
...
...
CACHE_wait();
CACHE_wbInvL2
CACHE_wbInvL2
L2 block writeback and invalidate
Function
void CACHE_wbInvL2(
void
*blockPtr,
Uint32
byteCnt,
int
wait
);
Arguments
blockPtr
Pointer to the beginning of the block
byteCnt
Number of bytes in the block. This value must be a multiple of four.
The largest size this can be in 65535*4.
wait
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
Return Value
none
Description
This function issues an L2 block writeback and invalidate command to the
cache controller. Please see the TMS320C621x/C671x DSP Two Level
Internal Memory Reference Guide (literature number SPRU609) and the
TMS320C64x DSP Two Level Internal Memory Reference Guide (literature
number SPRU610) for details of this operation. If a previous cache operation
is still active, the function waits for its completion before initiating the new
operation, in order to prevent lockout of interrupts.
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Although the block size can be specified in number of bytes, the cache
controller operates on whole cache lines only. To prevent unintended behavior,
blockPtr and byteCnt should be multiples of the cache line size.
Example
char buffer[1024];
/* call with wait flag set */
CACHE_wbInvL2(buffer, 1024, CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_wbInvL2(buffer, 1024, CACHE_NOWAIT);
...
...
CACHE_wait();
CACHE Module
2-25
CACHE_wbL2
CACHE_wbL2
L2 block writeback
Function
void CACHE_wbL2(
void
*blockPtr,
Uint32
byteCnt,
int
wait
);
Arguments
blockPtr
Pointer to the beginning of the block
byteCnt
Number of bytes in the block. This value must be a multiple of four.
The largest size this can be in 65535*4.
wait
Wait flag:
- CACHE_NOWAIT − return immediately
- CACHE_WAIT − wait until the operation completes
Return Value
none
Description
This function issues an L2 block writeback command to the cache controller.
Please see the TMS320C621x/C671x DSP Two Level Internal Memory
Reference Guide (literature number SPRU609) and the TMS320C64x DSP
Two Level Internal Memory Reference Guide (literature number SPRU610) for
details of this operation for details of this operation. If a previous cache
operation is still active, the function waits for its completion before initiating the
new operation, in order to prevent lockout of interrupts.
If the user specifies CACHE_NOWAIT, then the function returns immediately,
regardless of whether the operation has completed. The user can call
CACHE_wait() afterwards to wait for the operation to complete.
Although the block size can be specified in number of bytes, the cache
controller operates on whole cache lines only. To prevent unintended behavior,
blockPtr and byteCnt should be multiples of the cache line size.
Example
2-26
char buffer[1024];
/* call with wait flag set */
CACHE_wbL2(buffer, 1024, CACHE_WAIT);
...
/* call without the wait flag set */
CACHE_wbL2(buffer, 1024, CACHE_NOWAIT);
...
...
CACHE_wait();
Chapter 3
CHIP Module
This chapter describes the CHIP module, lists the API functions and macros
within the module, and provides a CHIP API reference section.
Topic
Page
3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-1
Overview
3.1 Overview
The CHIP module is where chip-specific and chip-related code resides. This
module has the potential to grow in the future as more devices are placed on
the market. Currently, CHIP has some API functions for obtaining device
endianess, memory map mode if applicable, and CPU and REV IDs. The
CHIP_Config structure contains a single field which holds the unsigned device
configuration value.
Table 3−1 shows the API functions within the CHIP module.
Table 3−1. CHIP APIs
Syntax
Type Description
See page ...
CHIP_6XXX
C
Current device identification symbols
3-4
CHIP_getCpuId
F
Returns the CPU ID field of the CSR register
3-5
CHIP_getEndian
F
Returns the current endian mode of the device
3-5
CHIP_getMapMode
F
Returns the current map mode of the device
3-6
CHIP_getRevId
F
Returns the CPU revision ID
3-6
CHIP_SUPPORT
C
A compile time constant whose value is 1 if the device
supports the CHIP module
3-6
CHIP_config†
F
Set device configuration
3-7
CHIP_getConfig†
F
Get device configuration
3-7
CHIP_configArgs†
F
Set device configuration
3-7
Note: F = Function; C = Constant
† Only for C6713, DA610, C6412, C6711C, C6712C, DM642, C6410, and C6413 devices.
3-2
Macros
3.2 Macros
There are two types of CHIP macros: those that access registers and fields,
and those that construct register and field values.
Table 3−2 lists the CHIP macros that access registers and fields, and
Table 3−3 lists the CHIP macros that construct register and field values. The
macros themselves are found in Chapter 28, Using the HAL Macros.
CHIP macros are not handle-based.
Table 3−2. CHIP Macros that Access Registers and Fields
Macro
Description/Purpose
See page...
CHIP_CRGET()
Gets the value of CPU register
28-12
CHIP_CRSET(,x)
Sets the value of CPU register
28-13
CHIP_RGET()
Returns the value in the memory-mapped
register
28-18
CHIP_RSET(,x)
Writes the value to the memory-mapped register
28-20
CHIP_FGET(,)
Returns the value of the specified field in the
register
28-13
CHIP_FSET(,,fieldval)
Writes fieldval to the specified field of the register
28-15
CHIP_FSETS(,,)
Writes the symbol value to the specified field in
the peripheral
28-17
Table 3−3. CHIP Macros that Construct Register and Field Values
Macro
Description/Purpose
See page...
CHIP__DEFAULT
Register default value
28-21
CHIP__RMK()
Register make
28-23
CHIP__OF()
Register value of ...
28-22
CHIP___DEFAULT
Field default value
28-24
CHIP_FMK()
Field make
28-14
CHIP_FMKS()
Field make symbolically
28-15
CHIP___OF()
Field value of ...
28-24
CHIP___
Field symbolic value
28-24
CHIP Module
3-3
CHIP_6XXX
3.3 Functions
CHIP_6XXX
Current chip identification symbols
Constant
CHIP_6201
CHIP_6202
CHIP_6203
CHIP_6204
CHIP_6205
CHIP_6211
CHIP_6414
CHIP_6415
CHIP_6416
CHIP_6701
CHIP_6711
CHIP_6712
CHIP_6713
CHIP_DA610
CHIP_6410
CHIP_6413
CHIP_DM642
Description
These are the current chip identification symbols. They are used throughout
the CSL code to make compile-time decisions. When using the CSL, you have
to select the right chip type under Global Setting module. The chip type will
generate the associated macro CHIP_6XXX.
You may also use these symbols to perform conditional compilation; for
example:
#if (CHIP_6201)
/* user CHIP configuration for 6201 /
#elif (CHIP_6211)
/ user CHIP configuration for 6211 */
#endif
3-4
CHIP_getCpuId
CHIP_getCpuId
Returns CPU ID field of CSR register
Function
Uint32 CHIP_getCpuId();
Arguments
none
Return Value
CPU ID
Description
This function returns the CPU ID field of the CSR register.
Example
Uint32 CpuId;
CpuId = CHIP_getCpuId();
CHIP_getEndian
Returns the CPU ID
Returns current endian mode of device
Function
int CHIP_getEndian();
Arguments
none
Return Value
endian mode
Description
Returns the current endian mode of the device as determined by the EN bit of
the CSR register.
Example
Uint32 Endian;
0
Endian = CHIP_getEndian();
if (Endian == CHIP_ENDIAN_BIG) {
/* user big endian configuration /
} else {
/ user little endian configuration */
}
Returns the current endian mode of the device; will be one of
the following:
- CHIP_ENDIAN_BIG
- CHIP_ENDIAN_LITTLE
CHIP Module
3-5
CHIP_getMapMode
CHIP_getMapMode
Returns current map mode of device
Function
int CHIP_getMapMode();
Arguments
none
Return Value
map mode
Description
Returns the current MAP mode of the device as determined by the MAP bit of
the EMIF global control register.
Example
Uint32 MapMode;
0
MapMode = CHIP_getMapMode();
if (MapMode == CHIP_MAP_0) {
/* user map 0 configuration /
} else {
/ user map 1 configuration */
}
CHIP_getRevId
Returns current device MAP mode; will be one of the
following:
- CHIP_MAP_0
- CHIP_MAP_1
Returns CPU revision ID
Function
Uint32 CHIP_getRevId();
Arguments
none
Return Value
revision ID
Description
This function returns the CPU revision ID as determined by the Revision ID
field of the CSR register.
Example
Uint32 RevId;
RevId = CHIP_getRevId();
CHIP_SUPPORT
Returns CPU revision ID
Compile-time constant
Constant
CHIP_SUPPORT
Description
Compile-time constant that has a value of 1 if the device supports the CHIP
module and 0 otherwise. You are not required to use this constant.
Currently, all devices support this module.
Example
3-6
#if (CHIP_SUPPORT)
/* user CHIP configuration */
#endif
CHIP_SUPPORT
CHIP_config
Set device configuration
Function
void CHIP_config(
CHIP_Config *config
);
Arguments
Address of config structure
Return Value
None
Description
Writes the device configuration value held in the config structure to config
address
CHIP_getConfig
Gets the device configuration
Function
void CHIP_getConfig(
CHIP_Config *config
);
Arguments
Address of config structure
Return Value
None
Description
Gets the device configuration value stored in the config structure to
configuration address. This value is written to the devcfg field of the structure.
CHIP_configArgs
Sets the device configuration
Function
void CHIP_configArgs(
unit32 devcfg
);
Arguments
devcfg
Return Value
None
Description
Writes the devcfg value to the device configuration address.
CHIP Module
3-7
Chapter 4
CSL Module
This chapter describes the CSL module, shows the single API function within
the module, and provides a CSL API reference section.
Topic
Page
4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-1
Overview
4.1 Overview
The CSL module is the top-level API module whose primary purpose is to
initialize the library.
The CSL_init() function must be called once at the beginning of your program
before calling any other CSL API functions.
Table 4−1 shows the only function exported by the CSL module.
Table 4−1. CSL API
Syntax
CSL_init
Note:
4-2
F = Function
Type Description
F
Initializes the CSL library
See page ...
4-3
CSL_init
4.2 Functions
CSL_init
Calls initialization function of all CSL API modules
Function
void CSL_init();
Arguments
none
Return Value
none
Description
The CSL module is the top-level API module whose primary purpose is to
initialize the library. Only one function is exported:
CSL_init()
The CSL_init() function must be called once at the beginning of your program
before calling any other CSL API functions.
Example
CSL_init();
CSL Module
4-3
Chapter 5
DAT Module
This chapter describes the DAT module, lists the API functions within the DAT
module, discusses how the DAT module manages the DMA/EDMA peripheral,
and provides a DAT API reference section.
Topic
Page
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5-1
Overview
5.1 Overview
The data module (DAT) is used to move data around by means of DMA/EDMA
hardware. This module serves as a level of abstraction such that it works the
same for devices that have the DMA peripheral as for devices that have the
EDMA peripheral. Therefore, application code that uses the DAT module is
compatible across all current devices regardless of which type of DMA
controller it has.
Table 5−1 shows the API functions within the DAT module.
Table 5−1. DAT APIs
Syntax
Type Description
See page ...
DAT_busy
F
Checks to see if a previous transfer has completed
5-4
DAT_close
F
Closes the DAT module
5-4
DAT_copy
F
Copies a linear block of data from Src to Dst using DMA
or EDMA hardware
5-5
DAT_copy2d
F
Performs a 2-dimensional data copy using DMA or
EDMA hardware.
5-6
DAT_fill
F
Fills a linear block of memory with the specified fill value
using DMA or EDMA hardware
5-8
DAT_open
F
Opens the DAT module
5-10
DAT_setPriority
F
Sets the priority CPU vs DMA/EDMA
5-11
DAT_SUPPORT
C
A compile time constant whose value is 1 if the device
supports the DAT module
5-12
DAT_wait
F
Waits for a previous transfer to complete
5-13
Note:
5.1.1
F = Function; C = Constant
DAT Routines
The DAT module has been intentionally kept simple. There are routines to
copy data from one location to another and routines to fill a region of memory.
These operations occur in the background on dedicated DMA hardware
independent of the CPU. Because of this asynchronous nature, there is API
support that enables waiting until a given copy/fill operation completes. It
works like this: call one of the copy/fill functions and get an ID number as a
return value. Then use this ID number later on to wait for the operation to
complete. This allows the operation to be submitted and performed in the
background while the CPU performs other tasks in the foreground. Then as
needed, the CPU can block on completion of the operation before moving on.
5-2
Overview
5.1.2
DAT Macros
There are no register and field access macros dedicated to the DAT module.
The only macros used by DAT are equivalent to the DMA or EDMA macros.
5.1.3
DMA/EDMA Management
Since the DAT module uses the DMA/EDMA peripheral, it must do so in a
managed way. In other words, it must not use a DMA channel that is already
allocated by the application. To ensure that this does not happen, the DAT
module must be opened before use, this is accomplished using the
DAT_open() API function. Opening the DAT module allocates a DMA
channel for exclusive use. If the module is no longer needed, the DMA
resource may be freed up by closing the DAT module with DAT_close().
Note:
For devices that have EDMA, the DAT module uses the quick DMA feature.
This means that the module does not have to internally allocate a DMA channel. However, you are still required to open the DAT module before use.
5.1.4
Devices With DMA
On devices that have the DMA peripheral, such as the 6201, only one request
may be active at once since only one DMA channel is used. If you submit two
requests one after the other, the first one will be programmed into the DMA
hardware immediately but the second one will have to wait until the first
completes. The APIs will block (spin) if called while a request is still busy by
polling the transfer complete interrupt flag. The completion interrupt is not
actually enabled to eliminate the overhead of taking an interrupt, but the
interrupt flag is still active.
5.1.5
Devices With EDMA
On devices with EDMA, it is possible to have multiple requests pending
because of hardware request queues. Each call into the DAT_copy() or
DAT_fill() function returns a unique transfer ID number. This ID number
is then used by the user so that the transfer can be completed. The ID number
allows the library to distinguish between multiple pending transfers. As with the
DMA, transfer completion is determined by monitoring EDMA transfer
complete codes (interrupt flags).
DAT Module
5-3
DAT_busy
5.2 Functions
DAT_busy
Checks to see if a previous transfer has completed
Function
Uint32 DAT_busy(
Uint32 id);
Arguments
id
Transfer identifier, returned by one of the DAT copy or DAT fill routines.
Return Value
busy
Returns non-zero if transfer is still busy, zero otherwise.
Description
Checks to see if a previous transfer has completed or not, identified by the
transfer ID.
Example
DAT_open(DAT_CHAANY, DAT_PRI_LOW, 0);
...
transferId = DAT_copy(src,dst,len);
...
while (DAT_busy(transferId));
DAT_close
Closes DAT module
Function
void DAT_close();
Arguments
none
Return Value
none
Description
Closes the DAT module. First, any pending requests are allowed to complete;
then if applicable, any DMA channels used by the DAT module are closed.
Example
DAT_close();
5-4
DAT_copy
DAT_copy
Copies linear block of data from Src to Dst using DMA or EDMA hardware
Function
Uint32 DAT_copy(
void *src,
void *dst,
Uint16 byteCnt
);
Arguments
src
Pointer to source data
dst
Pointer to destination location
byteCnt
Number of bytes to copy
Return Value
xfrId
Transfer ID
Description
Copies a linear block of data from Src to Dst using DMA or EDMA hardware,
depending on the device. The arguments are checked for alignment and the
DMA is submitted accordingly. For best performance in devices other than
C64x devices, you should ensure that the source and destination addresses
are aligned on a 4-byte boundary and the transfer length is a multiple of four.
A maximum of 65,535 bytes may be copied. A byteCnt of zero has
unpredictable results.
For C64x devices, the EDMA uses a 64-bit bus (8 bytes) to L2 SRAM. For best
efficiency, the source and destination addresses should be aligned on an
8-byte boundary, with the transfer rate a multiple of eight.
If the DMA channel is busy with one or more previous requests, the function
will block and wait for completion before submitting this request.
The DAT module must be opened before calling this function. See
DAT_open().
The return value is a transfer identifier that may be used later on to wait for
completion. See DAT_wait().
Example
#define DATA_SIZE 256
Uint32 BuffA[DATA_SIZE/sizeof(Uint32)];
Uint32 BuffB[DATA_SIZE/sizeof(Uint32)];
…
DAT_open(DAT_CHAANY,DAT_PRI_LOW,0);
DAT_copy(BuffA,BuffB,DATA_SIZE);
…
DAT Module
5-5
DAT_copy2d
DAT_copy2d
Performs 2-dimensional data copy
Function
Uint32 DAT_copy2d(
Uint32 type,
void *src,
void *dst,
Uint16 lineLen,
Uint16 lineCnt,
Uint16 linePitch
);
Arguments
type
Transfer type:
- DAT_1D2D
- DAT_2D1D
- DAT_2D2D
src
dst
lineLen
lineCnt
linePitch
Pointer to source data
Pointer to destination location
Number of bytes per line
Number of lines
Number of bytes between start of one line to start of next line
Return Value
xfrId
Transfer ID
Description
Performs a 2-dimensional data copy using DMA or EDMA hardware,
depending on the device. The arguments are checked for alignment and the
hardware configured accordingly. For best performance on devices other than
C64x devices, you should ensure that the source address and destination
address are aligned on a 4-byte boundary and that the lineLen and
linePitch are multiples of 4-bytes.
For C64x devices, the EDMA uses a 64-bit bus (8 bytes) to L2 SRAM. For best
efficiency, the source and destination addresses should be aligned on an
8-byte boundary with the transfer rate a multiple of eight.
If the channel is busy with previous requests, this function will block (spin) and
wait until it frees up before submitting this request.
Note: The DAT module must be opened with the DAT_OPEN_2D flag before
calling this function. See DAT_open().
There are three ways to submit a 2D transfer: 1D to 2D, 2D to 1D, and 2D to
2D. This is specified using the type argument. In all cases, the number of bytes
copied is lineLen × lineCnt. The 1D part of the transfer is just a linear block
of data. The 2D part is illustrated in Figure 5−1.
5-6
DAT_copy2d
Figure 5−1. 2D Transfer
LineLen
LineLen = 5
LineCnt = 6
LinePitch = 8
LineCnt
LinePitch
If a 2D to 2D transfer is specified, both the source and destination have the
same lineLen, lineCnt, and linePitch.
The return value is a transfer identifier that may be used later on to wait for
completion. See DAT_wait().
Example
DAT_copy2d (DAT_1D2D, buffA, buffB, 16, 8, 32);
DAT Module
5-7
DAT_fill
DAT_fill
Fills linear block of memory with specified fill value using DMA hardware
Function
Uint32 DAT_fill(
void *dst,
Uint16 byteCnt,
Uint32 *fillValue
);
Arguments
dst
Pointer to destination location
byteCnt
Number of bytes to fill
fillValue
Pointer to fill value
Return Value
xfrId
Transfer ID
Description
Fills a linear block of memory with the specified fill value using DMA hardware.
The arguments are checked for alignment and the DMA is submitted
accordingly. For best performance, you should ensure that the destination
address is aligned on a 4-byte boundary and the transfer length is a multiple
of 4. A maximum of 65,535 bytes may be filled.
For devices other than C64x devices, the fill value is 8-bits in size but must be
contained in a 32-bit word. This is due to the way the DMA hardware works.
If the arguments are 32-bit aligned, then the DMA transfer element size is set
to 32-bits to maximize performance. This means that the source of the transfer,
the fill value, must be 32-bits in size. So, the 8-bit fill value must be repeated
to fill the 32-bit value. For example, if you want to fill a region of memory with
the value 0xA5, the fill value should contain 0xA5A5A5A5 before calling this
function. If the arguments are 16-bit aligned, a 16-bit element size is used.
Finally, if any of the arguments are 8-bit aligned, an 8-bit element size is used.
It is a good idea to always fill in the entire 32-bit fill value to eliminate any endian
issues.
For C64x devices, the fill count must be a multiple of 8 bytes. The EDMA uses
a 64-bit bus to store data in L2 SRAM. A pointer of 64-bit value must be passed
to the “fillvalue” parameter (a set of 8 consecutive bytes, aligned). The EDMA
transfer element size is set to 64-bits. If you want to fill the memory region with
a value of 0x1234, the pointer should point to two consecutive 32-bit words set
to 0x12341234 value .
If the DMA channel is busy with a previous request, the function will block and
wait for completion before submitting this request.
The DAT module must be opened before calling this function. See
DAT_open().
5-8
DAT_fill
The return value is a transfer identifier that may be used later on to wait for
completion. See DAT_wait().
Note:
You should be aware that if the fill value is in cache, the DMA always uses
the external address and not the value that is in cache. It is up to you to ensure that the fill value is flushed before calling this function. Also, since the
user specifies a pointer to the fill value, it is important not to write to it while
the fill is in progress.
Example
Uint32 BUFF_SIZE 256;
Uint32 buff[BUFF_SIZE/sizeof(Uint32)];
Uint32 fillValue = 0xA5A5A5A5;
…
DAT_open(DAT_CHAANY,DAT_PRI_LOW,0);
DAT_fill(buff,BUFF_SIZE,&fillValue);
For 64x devices:
Uint32 BUFF_SIZE 256; /* 8 * 8bytes */
Uint32 buff[BUFF_SIZE/sizeof(Uint32)];
Uint32 fillValue[2] = {0x12341234,0x12341234};
Uint32 *fillValuePtr = fillValue;
…
DAT_open(DAT_CHAANY,DAT_PRI_LOW,0);
DAT_fill(buff,BUFF_SIZE,&fillValue);
DAT Module
5-9
DAT_open
DAT_open
Opens DAT module
Function
Uint32 DAT_open(
int chaNum,
int priority,
Uint32 flags
);
Arguments
chaNum
Specifies which DMA channel to allocate; must be one of the
following:
- DAT_CHAANY
- DAT_CHA0
- DAT_CHA1
- DAT_CHA2
- DAT_CHA3
priority
Specifies the priority of the DMA channel; must be one of the
following:
- DAT_PRI_LOW
- DAT_PRI_HIGH
flags
Miscellaneous open flags
- DAT_OPEN_2D
success
for failure are:
Returns zero on failure and non-zero if successful. Reasons
Return Value
- The DAT module is already open.
- Required resources could not be allocated.
Description
This function opens up the DAT module and must be called before calling any
of the other DAT API functions. The ChaNum argument specifies which DMA
channel to open for exclusive use by the DAT module. For devices with EDMA,
the ChaNum argument is ignored because the quick DMA is used which does
not have a channel associated with it.
For DMA Devices:
- ChaNum specifies which DMA channel to use
- DAT_PRI_LOW sets the DMA channel up for CPU priority
- DAT_PRI_HIGH sets the DMA channel up for DMA priority
For EDMA Devices:
- ChaNum is ignored
5-10
DAT_setPriority
- DAT_PRI_LOW sets LOW priority
- DAT_PRI_HIGH sets HIGH priority
Once the DAT module is opened, any resources allocated, such as DMA
channels, remain allocated. You can call DAT_close() to free these
resources.
If 2D transfers are planned via DAT_copy2d, the DAT_OPEN_2D flag must
be specified. Specifying this flag for devices with the DMA peripheral will cause
allocation of one global count reload register and one global index register.
These global registers are freed when DAT_close() is called.
Note:
For devices with EDMA, the DAT module uses the EDMA registers to submit
transfer requests. Also used is the channel interrupt pending register (CIPR).
Interrupts are not enabled but the completion flags in CIPR are used. The
DAT module uses interrupt completion codes 1 through 4 which amounts to
a mask of 0x00000001E in the CIPR register. If you use the DAT module on
devices with EDMA, you must avoid using transfer completion codes 1
through 4.
Example
To open the DAT module using any available DMA channel, use:
DAT_open(DAT_CHAANY,DAT_PRI_LOW,0);
To open the DAT module using DMA channel 2 in high-priority mode, use:
DAT_open(DAT_CHA2,DAT_PRI_HIGH,0);
To open the DAT module for 2D copies, use:
DAT_open (DAT_CHAANY, DAT_PRI_HIGH, DAT_OPEN_2D);
DAT_setPriority
Sets the priority of DMA or EDMA channel
Function
void DAT_setPriority(
int priority
);
Arguments
priority
Return Value
none
Description
Sets the priority bit value PRI of PRICTL register for devices supporting DMA,
and the PRI of OPT register for devices supporting EDMA. See also
DAT_open() function. The priority value can be set by using the following
predefined constants:
Priority bit value
DAT Module
5-11
DAT_SUPPORT
- DAT_PRI_LOW
- DAT_PRI_HIGH
Example
DAT_SUPPORT
/* Open DAT channel with priority Low */
DAT_open(DMA_CHAANY,DAT_PRI_LOW,0)
/* Set transfer with priority high */
DAT_setPriority(DAT_PRI_HI);
Compile-time constant
Constant
DAT_SUPPORT
Description
Compile-time constant that has a value of 1 if the device supports the DAT
module and 0 otherwise. You are not required to use this constant.
Note: The DAT module is supported by all devices that have an EDMA or DMA
peripheral.
Example
5-12
#if (DAT_SUPPORT)
/* user DAT configuration */
#endif
DAT_wait
DAT_wait
Waits for previous transfer to complete identification by transfer ID
Function
void DAT_wait(
Uint32 id
);
Arguments
id
Return Value
none
Description
This function waits for a previous transfer to complete, identified by the transfer
ID. If the transfer has already completed, this function returns immediately.
Interrupts are not disabled during the wait.
Example
Uint32 transferId;
…
DAT_open(DAT_CHAANY, DAT_PRI_LOW, 0);
…
transferId = DAT_copy(src,dst,len);
/* user DAT configuration */
DAT_wait(transferId);
Transfer identifier, returned by one of the DAT copy or DAT fill routines.
Two predefined transfer IDs may be used:
- DAT_XFRID_WAITALL
- DAT_XFRID_WAITNONE
Using DAT_XFRID_WAITALL means wait until all transfers have
completed. Using DAT_XFRID_WAITNONE means do not wait for any
transfers to complete. This can be useful as the first operation in a
pipelined copy sequence.
DAT Module
5-13
Chapter 6
DMA Module
This chapter describes the DMA module, lists the API functions and macros
within the module, discusses how to use a DMA channel, and provides a DMA
API reference section.
Topic
Page
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3
Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6-1
Overview
6.1 Overview
Currently, the are two DMA architectures used on TMS320C6x devices are:
DMA and EDMA (enhanced DMA). Devices such as the C6201 have the
DMA peripheral, whereas the C6211 has the EDMA peripheral. The two
architectures are different enough to warrant a separate API module for each.
Table 6−1 lists the configuration structures for use with the DMA functions.
Table 6−2 lists the functions and constants available in the CSL DMA module.
Table 6−1. DMA Configuration Structures
Structure
Purpose
See page ...
DMA_Config
DMA structure that contains all local registers required to set up
a specific DMA channel
6-7
DMA_GlobalConfig
Global DMA structure that contains all global registers that you
may need to initialize a DMA channel
6-8
Table 6−2. DMA APIs
(a) DMA Primary Functions
Syntax
Type Description
See page ...
DMA_close
F
Closes a DMA channel opened via DMA_open()
6-9
DMA_config
F
Sets up the DMA channel using the configuration
structure
6-9
DMA_configArgs
F
Sets up the DMA channel using the register values
passed in
6-10
DMA_open
F
Opens a DMA channel for use
6-11
DMA_pause
F
Pauses the DMA channel by setting the START bits in
the primary control register appropriately
6-12
DMA_reset
F
Resets the DMA channel by setting its registers to
power-on defaults
6-12
DMA_start
F
Starts a DMA channel running without auto−initialization
6-13
DMA_stop
F
Stops a DMA channel by setting the START bits in the
primary control register appropriately
6-13
Note:
6-2
F = Function; C = Constant; M = Macro
Overview
Table 6−2. DMA APIs (Continued)
(b) DMA Global Register Functions
Syntax
Type Description
See page ...
DMA_allocGlobalReg
F
Provides resource management for the DMA global
registers
6-14
DMA_freeGlobalReg
F
Frees a global DMA register previously allocated by
calling DMA_AllocGlobalReg()
6-16
DMA_getGlobalReg
F
Reads a global DMA register that was previously
allocated by calling DMA_AllocGlobalReg()
6-16
DMA_getGlobalRegAddr
F
Gets DMA global register address
6-17
DMA_globalAlloc
F
Allocates DMA global registers
6-18
DMA_globalConfig
F
Configures entry for DMA configuration structure
6-19
DMA_globalConfigArgs
F
Configures entry for DMA registers
6-20
DMA_globalFree
F
Frees Allocated DMA global register
6-22
DMA_globalGetConfig
F
Returns the entry for the DMA configuration structure
6-22
DMA_setGlobalReg
F
Sets value of a global DMA register previously allocated
by calling DMA_AllocGlobalReg()
6-23
(c) DMA Auxiliary Functions, Constants, and Macros
Syntax
Type Description
See page ...
DMA_autoStart
F
Starts a DMA channel with auto−initialization
6-23
DMA_CHA_CNT
C
Number of DMA channels for the current device
6-24
DMA_CLEAR_CONDITION
M
Clears condition flag
6-24
DMA_GBLADDRA
C
DMA global address register A mask
6-24
DMA_GBLADDRB
C
DMA global address register B mask
6-24
DMA_GBLADDRC
C
DMA global address register C mask
6-25
DMA_GBLADDRD
C
DMA global address register D mask
6-25
DMA_GBLCNTA
C
DMA global count reload register A mask
6-25
DMA_GBLCNTB
C
DMA global count reload register B mask
6-25
DMA_GBLIDXA
C
DMA global index register A mask
6-25
Note:
F = Function; C = Constant; M = Macro
DMA Module
6-3
Overview
Table 6−2. DMA APIs (Continued)
DMA_GBLIDXB
C
DMA global index register B mask
6-26
DMA_GET_CONDITION
M
Gets condition flag
6-26
DMA_getConfig
F
Reads the current DMA configuration structure
6-26
DMA_getEventId
F
Returns the IRQ event ID for the DMA completion
interrupt
6-27
DMA_getStatus
F
Reads the status bits of the DMA channel
6-27
DMA_restoreStatus
F
Restores the status from DMA_getStatus() by setting
the START bit of the PRICTL primary control register
6-27
DMA_setAuxCtl
F
Sets the DMA AUXCTL register
6-28
DMA_SUPPORT
C
A compile time constant whose value is 1 if the device
supports the DMA module
6-28
DMA_wait
F
Enters a spin loop that polls the DMA status bits until
the DMA completes
6-29
Note:
6.1.1
F = Function; C = Constant; M = Macro
Using a DMA Channel
To use a DMA channel, you must first open it and obtain a device handle using
DMA_open(). Once opened, you use the device handle to call the other API
functions. The channel may be configured by passing a DMA_Config
structure to DMA_config() or by passing register values to the
DMA_configArgs() function. To assist in creating register values, there are
DMA_RMK (make) macros that construct register values based on field
values. In addition, there are symbol constants that may be used for the field
values.
There are functions for managing shared global DMA registers,
DMA_allocGlobalReg(),
DMA_freeGlobalReg(),
DMA_setGlobalReg(), and DMA_getGlobalReg().
6-4
Macros
6.2 Macros
There are two types of DMA macros: those that access registers and fields,
and those that construct register and field values.
Table 6−3 lists the DMA macros that access registers and fields, and
Table 6−4 lists the DMA macros that construct register and field values. The
macros themselves are found in Chapter 28, Using the HAL Macros.
The DMA module includes handle-based macros.
Table 6−3. DMA Macros that Access Registers and Fields
Macro
Description/Purpose
See page ...
DMA_ADDR()
Register address
28-12
DMA_RGET()
Returns the value in the peripheral register
28-18
DMA_RSET(,x)
Register set
28-20
DMA_FGET(,)
Returns the value of the specified field in the
peripheral register
28-13
DMA_FSET(,,fieldval)
Writes fieldval to the specified field in the
peripheral register
28-15
DMA_FSETS(,,)
Writes the symbol value to the specified field
in the peripheral
28-17
DMA_RGETA(addr,)
Gets register for a given address
28-19
DMA_RSETA(addr,,x)
Sets register for a given address
28-20
DMA_FGETA(addr,,)
Gets field for a given address
28-13
DMA_FSETA(addr,,,fieldval)
Sets field for a given address
28-16
DMA_FSETSA(addr,,,
)
Sets field symbolically for a given address
28-17
DMA_ADDRH(h,)
Returns the address of a memory-mapped
register for a given handle
28-12
DMA_RGETH(h,)
Returns the value of a register for a given
handle
28-19
DMA_RSETH(h,,x)
Sets the register value to x for a given handle
28-21
DMA_FGETH(h,,)
Returns the value of the field for a given
handle
28-14
DMA_FSETH(h,,,fieldval)
Sets the field value to x for a given handle
28-16
DMA Module
6-5
Macros
Table 6−4. DMA Macros that Construct Register and Field Values
Macro
Description/Purpose
See page ...
DMA__DEFAULT
Register default value
28-21
DMA__RMK()
Register make
28-23
DMA__OF()
Register value of ...
28-22
DMA___DEFAULT
Field default value
28-24
DMA_FMK()
Field make
28-14
DMA_FMKS()
Field make symbolically
28-15
DMA___OF()
Field value of ...
28-24
DMA___
Field symbolic value
28-24
6-6
DMA_Config
6.3 Configuration Structures
Because the DMA has both local and global registers for each channel, the
CSL DMA module has two configuration structures:
- DMA_Config (channel configuration structure) contains all the local
registers required to set up a specific DMA channel.
- DMA_GlobalConfig (global configuration structure) contains all the
global registers needed to initialize a DMA channel. These global registers
are resources shared across the different DMA channels, and include
element/frame indexes and reload registers, as well as src/dst page
registers.
You can use literal values or the _RMK macros to create the structure member
values.
DMA_Config
DMA configuration structure used to set up DMA channel
Structure
DMA_Config
Members
Uint32 prictl
Uint32 secctl
Uint32 src
Uint32 dst
Uint32 xfrcnt
Description
This DMA configuration structure is used to set up a DMA channel. You create
and initialize this structure and then pass its address to the DMA_config()
function. You can use literal values or the _RMK macros to create the structure
member values.
Example
DMA_Config MyConfig = {
0x00000050, /* prictl */
0x00000080, /* secctl */
0x80000000, /* src
*/
0x80010000, /* dst
*/
0x00200040 /* xfrcnt */
};
…
DMA_config(hDma,&MyConfig);
DMA primary control register value
DMA secondary control register value
DMA source address register value
DMA destination address register value
DMA transfer count register value
DMA Module
6-7
DMA_GlobalConfig
DMA_GlobalConfig DMA global register configuration structure
Structure
typedef struct {
Uint32 addrA;
Uint32 addrB;
Uint32 addrC;
Uint32 addrD;
Uint32 idxA;
Uint32 idxB;
Uint32 cntA;
Uint32 cntB;
} DMA_GlobalConfig;
Members
addrA
addrB
addrC
addrD
idxA
idxB
cntA
cntB
Description
This is the DMA global register configuration structure used to set up a DMA
global register configuration. You create and initialize this structure, then pass
its address to the DMA_globalConfig() function.
Example
Uint32 dmaGblRegMsk;
Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC;
DMA_GlobalConfig dmaGblCfg = {
0x00000000, /* Global Address Register A */
0x80001000, /* Global Address Register B */
0x80002000, /* Global Address Register C */
0x00000000, /* Global Address Register D */
0x00000000, /* Global Index Register A
*/
0x00000000, /* Global Index Register B */
0x00000000, /* Global Count Reload Register A */
0x00000000 /* Global Count Reload Register B */
};
dmaGblRegMsk = DMA_globalAlloc(dmaGblRegId);
DMA_globalConfig(dmaGblRegMsk, &dmaGblCfg);
6-8
Global address register A value.
Global address register B value.
Global address register C value.
Global address register D value.
Global index register A value.
Global index register B value.
Global count reload register A value.
Global count reload register B value.
DMA_close
6.4 Functions
6.4.1
Primary Functions
DMA_close
Closes DMA channel opened via DMA_open()
Function
void DMA_close(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
This function closes a DMA channel previously opened via DMA_open(). The
registers for the DMA channel are set to their power-on defaults and the
completion interrupt is disabled and cleared.
Example
DMA_close(hDma);
DMA_config
Handle to DMA channel, see DMA_open()
Sets up DMA channel using configuration structure
Function
void DMA_config(
DMA_Handle hDma,
DMA_Config *Config
);
Arguments
hDma
Handle to DMA channel. See DMA_open()
Config
Pointer to an initialized configuration structure
Return Value
none
Description
Sets up the DMA channel using the configuration structure. The values of the
structure are written to the DMA registers. The primary control register (prictl)
is written last. See also DMA_configArgs() and DMA_Config.
Example
DMA_Config MyConfig = {
0x00000050, /* prictl */
0x00000080, /* secctl */
0x80000000, /* src
*/
0x80010000, /* dst
*/
0x00200040 /* xfrcnt */
};
…
DMA_config(hDma,&MyConfig);
DMA Module
6-9
DMA_configArgs
DMA_configArgs
Sets up DMA channel using register values passed in
Function
void DMA_configArgs(
DMA_Handle hDma,
Uint32 prictl,
Uint32 secctl,
Uint32 src,
Uint32 dst,
Uint32 xfrcnt
);
Arguments
hDma
Handle to DMA channel. See DMA_open()
prictl
Primary control register value
secctl
Secondary control register value
src
Source address register value
dst
Destination address register value
xfrcnt
Transfer count register value
Return Value
none
Description
Sets up the DMA channel using the register values passed in. The register
values are written to the DMA registers. The primary control register (prictl) is
written last. See also DMA_config().
You may use literal values for the arguments or for readability. You may use
the _RMK macros to create the register values based on field values.
Example
6-10
DMA_configArgs(hDma,
0x00000050, /* prictl
0x00000080, /* secctl
0x80000000, /* src
0x80010000, /* dst
0x00200040 /* xfrcnt
);
*/
*/
*/
*/
*/
DMA_open
DMA_open
Opens DMA channel for use
Function
DMA_Handle DMA_open(
int chaNum,
Uint32 flags
);
Arguments
chaNum
DMA channel to open:
- DMA_CHAANY
- DMA_CHA0
- DMA_CHA1
- DMA_CHA2
- DMA_CHA3
flags
Open flags (logical OR of DMA_OPEN_RESET)
Return Value
Device Handle Handle to newly opened device
Description
Before a DMA channel can be used, it must first be opened by this function.
Once opened, it cannot be opened again until closed. See DMA_close(). You
have the option of either specifying exactly which physical channel to open or
you can let the library pick an unused one for you by specifying DMA_CHAANY.
The return value is a unique device handle that you use in subsequent DMA
API calls. If the open fails, INV is returned.
If the DMA_OPEN_RESET is specified, the DMA channel registers are set to
their power-on defaults and the channel interrupt is disabled and cleared.
Example
DMA_Handle hDma;
…
hDma = DMA_open(DMA_CHAANY,DMA_OPEN_RESET);
DMA Module
6-11
DMA_pause
DMA_pause
Pauses DMA channel by setting START bits in primary control register
Function
void DMA_pause(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
This function pauses the DMA channel by setting the START bits in the primary
control register accordingly. See also DMA_start(), DMA_stop(), and
DMA_autoStart().
Example
DMA_pause(hDma);
DMA_reset
Handle to DMA channel. See DMA_open()
Resets DMA channel by setting its registers to power-on defaults
Function
void DMA_reset(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
Resets the DMA channel by setting its registers to power-on defaults and
disabling and clearing the channel interrupt. You may use INV as the device
handle to reset all channels.
Example
/* reset an open DMA channel /
DMA_reset(hDma);
Handle to DMA channel. See DMA_open()
/ reset all DMA channels */
DMA_reset(INV);
6-12
DMA_start
DMA_start
Starts DMA channel running without auto−initialization
Function
void DMA_start(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
Starts a DMA channel running without auto−initialization by setting the START
bits in the primary control register accordingly. See also DMA_pause(),
DMA_stop(), and DMA_autoStart().
Example
DMA_start(hDma);
DMA_stop
Handle to DMA channel, see DMA_open()
Stops DMA channel by setting START bits in primary control register
Function
void DMA_stop(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
Stops a DMA channel by setting the START bits in the primary control register
accordingly.
See
also
DMA_pause(),
DMA_start(),
and
DMA_autoStart().
Example
DMA_stop(hDma);
Handle to DMA channel. See DMA_open()
DMA Module
6-13
DMA_allocGlobalReg
6.4.2
DMA Global Register Functions
DMA_allocGlobalReg
Allocates global DMA register
Function
Uint32 DMA_allocGlobalReg(
DMA_Gbl regType,
Uint32 initVal
);
Arguments
regType
Global register type; must be one of the following:
- DMA_GBL_ADDRRLD
- DMA_GBL_INDEX
- DMA_GBL_CNTRLD
- DMA_GBL_SPLIT
initVal
Value to initialize the register to
Return Value
Global Register ID Unique ID number for the global register
Description
Since the DMA global registers are shared, they must be controlled using
resource management. This is done using DMA_allocGlobalReg() and
DMA_freeGlobalReg() functions. Allocating a register ensures that it will
not be reallocated until it is freed. The register ID may then be used to get or
set the register value by calling DMA_getGlobalReg() and
DMA_setGlobalReg() respectively. If the register cannot be allocated, a
register ID of 0 is returned.
The register ID may directly be used with the DMA_PRICTL_RMK macro.
- DMA_GBL_ADDRRLD
Allocate global address register for use as DMA DST RELOAD or DMA
SRC RELOAD. Will allocate one of the following DMA registers:
J
Global Address Register B
J
Global Address Register C
J
Global Address Register D
- DMA_GBL_INDEX
Allocate global index register for use as DMA INDEX. Will allocate one of
the following DMA registers:
6-14
J
Global Index Register A
J
Global Index Register B
DMA_allocGlobalReg
- DMA_GBL_CNTRLD
Allocate global count reload register for use as DMA CNT RELOAD. Will
allocate one of the following DMA registers:
J
Global Count Reload Register A
J
Global Count Reload Register B
- DMA_GBL_SPLIT
Allocate global address register for use as DMA SPLIT. Will allocated one
of the following DMA registers:
Example
J
Global Address Register A
J
Global Address Register B
J
Global Address Register C
Uint32 RegId;
…
/* allocate global index register and initialize it */
RegId = DMA_allocGlobalReg(DMA_GBL_
INDEX,0x00200040);
DMA Module
6-15
DMA_freeGlobalReg
DMA_freeGlobalReg Frees global DMA register that was previously allocated
Function
void DMA_freeGlobalReg(
Uint32 regId
);
Arguments
regId
Return Value
none
Description
This function frees a global DMA register that was previously allocated by
calling DMA_allocGlobalReg(). Once freed, the register is available for
reallocation.
Example
Uint32 RegId;
…
/* allocate global index register and initialize it */
RegId = DMA_allocGlobalReg(DMA_GBL_INDEX,0x00200040);
…
/* some time later on when you’re done with it */
DMA_freeGlobalReg(RegId);
DMA_getGlobalReg
Global register ID obtained from DMA_allocGlobalReg().
Reads global DMA register that was previously allocated
Function
Uint32 DMA_getGlobalReg(
Uint32 regId
);
Arguments
regId
Return Value
Register Value Value read from register
Description
This function returns the register value of the global DMA register that was
previously allocated by calling DMA_allocGlobalReg().
Global register ID obtained from DMA_allocGlobalReg().
If you prefer not to use the alloc/free paradigm for the global register
management, the predefined register IDs may be used. You should be aware
that use of predefined register IDs precludes the use of alloc/free. The list of
predefined IDs are shown below:
6-16
DMA_getGlobalRegAddr
-
DMA_GBL_ADDRRLDB
DMA_GBL_ADDRRLDC
DMA_GBL_ADDRRLDD
DMA_GBL_INDEXA
DMA_GBL_INDEXB
DMA_GBL_CNTRLDA
DMA_GBL_CNTRLDB
DMA_GBL_SPLITA
DMA_GBL_SPLITB
DMA_GBL_SPLITC
Note:
DMA_GBL_ADDRRLDB denotes the same physical register as
DMA_GBL_SPLITB and DMA_GBL_ADDRRLDC denotes the same physical
register as DMA_GBL_SPLITC.
Example
Uint32 RegId;
Uint32 RegValue;
…
/* allocate global index register and initialize it /
RegId = DMA_allocGlobalReg(DMA_GBL_
INDEX,0x00200040);
…
RegValue = DMA_getGlobalReg(RegId);
DMA_getGlobalRegAddr Gets DMA global register address
Function
Uint32 DMA_getGlobalRegAddr(
Uint32 regId
);
Arguments
regId
DMA global registers ID
Return Value
Uint32
DMA global register address corresponding to regId
Description
Get DMA global register address and return the address value.
Example
Uint32 regId = DMA_GBL_ADDRRLDB;
Uint32 regAddr;
regAddr = DMA_getGlobalRegAddr(regId);
DMA Module
6-17
DMA_globalAlloc
DMA_globalAlloc
Allocates DMA global registers
Function
Uint32 DMA_globalAlloc(
Uint32 regs
);
Arguments
regs
DMA global registers ID
Return Value
Uint32
Allocated DMA global registers mask
Description
Allocates DMA global registers and returns a mask of allocated DMA global
registers. Mask depends on DMA global register ID and the availability of the
register.
Example
Uint32 dmaGblRegMsk;
Uint32 regs = DMA_GBLADDRB | DMA_GBLADDRC;
DmaGblRegMsk = DMA_globalAlloc(regs);
6-18
DMA_globalConfig
DMA_globalConfig Sets up the DMA global registers using the configuration structure
Function
void DMA_globalConfig(
Uint32 regs,
DMA_GlobalConfig *cfg
);
Arguments
regs
DMA global register mask
cfg
Pointer to an initialized configuration structure.
Return Value
none
Description
Sets up the DMA global registers using the configuration structure. The values
of the structure that are written to the DMA global registers depend on the DMA
global register mask.
Example
Uint32 dmaGblRegMsk;
Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC;
DMA_GlobalConfig dmaGblCfg = {
0x00000000, /* Global Address Register A */
0x80001000, /* Global Address Register B */
0x80002000, /* Global Address Register C */
0x00000000, /* Global Address Register D */
0x00000000, /* Global Index Register A
*/
0x00000000, /* Global Index Register B
*/
0x00000000, /* Global Count Reload Register A */
0x00000000 /* Global Count Reload Register B */
};
dmaGblRegMsk = DMA_globalAlloc(dmaGblRegId);
DMA_globalConfig(dmaGblRegMsk, &dmaGblCfg);
DMA Module
6-19
DMA_globalConfigArgs
DMA_globalConfigArgs
Establishes DMA global register value
Function
void DMA_globalConfigArgs(
Uint32 regs,
Uint32 addrA,
Uint32 addrB,
Uint32 addrC,
Uint32 addrD,
Uint32 idxA,
Uint32 idxB,
Uint32 cntA,
Uint32 cntB
);
Arguments
regs
addrA
addrB
addrC
addrD
idxA
idxB
cntA
cntB
Return Value
none
Description
Sets up the DMA global registers using the register values passed in. The
register values that are written to the DMA global registers depend on the DMA
global register mask.
6-20
DMA global register mask value.
Global address register A value.
Global address register B value.
Global address register C value.
Global address register D value.
Global index register A value.
Global index register B value.
Global count reload register A value.
Global count reload register B value.
DMA_globalConfigArgs
Example
Uint32 dmaGblRegMsk;
Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC;
Uint32 addrA = 0x00000000;
Uint32 addrB = 0x80001000;
Uint32 addrC = 0x80002000;
Uint32 addrD = 0x00000000;
Uint32 idxA = 0x00000000;
Uint32 idxB = 0x00000000;
Uint32 cntA = 0x00000000;
Uint32 cntB = 0x00000000;
dmaGblRegMsk = DMA_globalAlloc(dmaGblRegId);
DMA_globalConfigArgs(
dmaGblRegMsk,
addrA,
addrB,
addrC,
addrD,
idxA,
idxB,
cntA,
cntB
);
DMA Module
6-21
DMA_globalFree
DMA_globalFree
Frees allocated DMA global registers
Function
Void DMA_globalFree(
Uint32 regs
);
Arguments
regs
Return Value
none
Description
Frees previously allocated DMA global registers; depends on regs.
Example
Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC;
DMA_globalFree(dmaGblRegId);
DMA_globalGetConfig
DMA global registers ID
Gets current DMA global register configuration value
Function
void DMA_globalGetConfig(
Uint32 regs,
DMA_GlobalConfig *cfg
);
Arguments
regs
DMA global register ID
cfg
Pointer to an initialized configuration structure.
Return Value
none
Description
Gets DMA global registers current configuration value depending on DMA
global register ID.
Example
Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC;
DMA_GlobalConfig dmaGblCfg;
DMA_globalGetConfig(dmaGblRegId, &dmaGblCfg);
6-22
DMA_setGlobalReg
DMA_setGlobalReg
Sets value of global DMA register that was previously allocated
Function
void DMA_setGlobalReg(
Uint32 regId,
Uint32 val
);
Arguments
regId
Global register ID obtained from DMA_allocGlobalReg().
val
Value to set register to
Return Value
none
Description
This function sets the value of a global DMA register that was previously
allocated by calling DMA_allocGlobalReg().
Example
Uint32 RegId;
…
/* allocate global index register and initialize it /
RegId = DMA_allocGlobalReg(DMA_GBL_INDEX,0x00200040);
…
DMA_setGlobalReg(RegId,0x12345678);
6.4.3
DMA Auxiliary Functions, Constants, and Macros
DMA_autoStart
Starts DMA channel with autoinitialization
Function
void DMA_autoStart(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
Starts a DMA channel running with autoinitialization by setting the START bits
in the primary control register accordingly. See also DMA_pause(),
DMA_stop(), and DMA_start().
Example
DMA_autoStart(hDma);
Handle to DMA channel, see DMA_open()
DMA Module
6-23
DMA_CHA_CNT
DMA_CHA_CNT
Number of DMA channels for current device
Constant
DMA_CHA_CNT
Description
This constant holds the number of physical DMA channels for the current
device.
DMA_CLEAR_CONDITION
Clears one of the condition flags in DMA secondary control register
Macro
DMA_CLEAR_CONDITION(
hDma,
COND
);
Arguments
hDma
Handle to DMA channel, see DMA_open()
COND
Condition to clear, must be one of the following:
- DMA_SECCTL_SXCOND
- DMA_SECCTL_FRAMECOND
- DMA_SECCTL_LASTCOND
- DMA_SECCTL_BLOCKCOND
- DMA_SECCTL_RDROPCOND
- DMA_SECCTL_WDROPCOND
Return Value
none
Description
This macro clears one of the condition flags in the DMA secondary control
register. See the TMS320C6000 Peripherals Reference Guide (SPRU190) for
a description of the condition flags.
Example
DMA_CLEAR_CONDITION(hDma,DMA_SECCTL_BLOCKCOND);
DMA_GBLADDRA DMA global address register A mask
Constant
DMA_GBLADDRA
Description
This constant allows selection of the global address register A. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMA_globalConfigArgs() functions.
DMA_GBLADDRB DMA global address register B mask
Constant
DMA_GBLADDRB
Description
This constant allows selection of the global address register B. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMA_globalConfigArgs() functions.
6-24
DMA_GBLADDRC
DMA_GBLADDRC DMA global address register C mask
Constant
DMA_GBLADDRC
Description
This constant allows selection of the global address register C. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMA_globalConfigArgs() functions.
DMA_GBLADDRD DMA global address register D mask
Constant
DMA_GBLADDRD
Description
This constant allows selection of the global address register D. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMS_globalConfigArgs() functions.
DMA_GBLCNTA
DMA global count reload register A mask
Constant
DMA_GBLCNTA
Description
This constant allows selection of the global count reload register A. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMA_globalConfigArgs() functions.
DMA_GBLCNTB
DMA global count reload register B mask
Constant
DMA_GBLCNTB
Description
This constant allows selection of the global count reload register B. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMA_globalConfigArgs() functions.
DMA_GBLIDXA
DMA global index register A mask
Constant
DMA_GBLIDXA
Description
This constant allows selection of the global index register A. See
DMA_globalAlloc(), DMA_globalConfigArgs(), and
DMA_globalConfig() functions.
DMA Module
6-25
DMA_GBLIDXB
DMA_GBLIDXB
DMA global index register B mask
Constant
DMA_GBLIDXB
Description
This constant allows selection of the global index register B. See
DMA_globalAlloc(), DMA_globalConfig(), and
DMA_globalConfigArgs() functions.
DMA_GET_CONDITION
Gets one of the condition flags in DMA secondary control register
Macro
DMA_GET_CONDITION(
hDma,
COND
);
Arguments
hDma
Handle to DMA channel. See DMA_open()
COND
Condition to get; must be one of the following:
- DMA_SECCTL_SXCOND
- DMA_SECCTL_FRAMECOND
- DMA_SECCTL_LASTCOND
- DMA_SECCTL_BLOCKCOND
- DMA_SECCTL_RDROPCOND
- DMA_SECCTL_WDROPCOND
Return Value
Condition
Condition, 0 if clear, 1 if set
Description
This macro gets one of the condition flags in the DMA secondary control
register. See the TMS320C6000 Peripherals Reference Guide (SPRU190) for
a description of the condition flags.
Example
if (DMA_GET_CONDITION(hDma,DMA_SECCTL_BLOCKCOND)) {
/* user DMA configuration */
}
DMA_getConfig
Reads the current DMA configuration values
Function
void DMA_getConfig(
DMA_Handle hDma,
DMA_Config *config
);
Arguments
hDma
config
6-26
DMA handle. See DMA_open()
Pointer to a configuration structure
DMA_getEventId
Return Value
none
Description
Get DMA current configuration value
Example
DMA_config dmaCfg;
DMA_getConfig(hDma, &dmaCfg);
DMA_getEventId
Returns IRQ event ID for DMA completion interrupt
Function
Uint32 DMA_getEventId(
DMA_Handle hDma
);
Arguments
hDma
Handle to DMA channel. See DMA_open()
Return Value
Event ID
IRQ Event ID for DMA Channel
Description
Returns the IRQ Event ID for the DMA completion interrupt. Use this ID to
manage the event using the IRQ module.
Example
EventId = DMA_getEventId(hDma);
IRQ_enable(EventId);
DMA_getStatus
Reads status bits of DMA channel
Function
Uint32 DMA_getStatus(
DMA_Handle hDma
);
Arguments
hDma
Return Value
Status Value
Handle to DMA channel, see DMA_open()
Current DMA channel status:
DMA_STATUS_STOPPED
DMA_STATUS_RUNNING
DMA_STATUS_PAUSED
DMA_STATUS_AUTORUNNING
-
Description
This function reads the STATUS bits of the DMA channel.
Example
while (DMA_getStatus(hDma)==DMA_STATUS_RUNNING);
DMA_restoreStatus Restores the status from DMA_getStatus()
Function
void DMA_restoreStatus(
Uint32 hDma,
Uint32 status
);
Arguments
hDma
status
Handle to DMA channel. See DMA_open()
Status from DMA_getStatus() function
DMA Module
6-27
DMA_setAuxCtl
Return Value
none
Description
Restores the status from DMA_getStatus() by setting the START bit of the
PRICTL primary control register.
Example
status = DMA_getStatus(hDma);
...
DMA_restoreStatus(hDma, status);
DMA_setAuxCtl
Sets DMA AUXCTL register
Function
void DMA_setAuxCtl(
Uint32 auxCtl
);
Arguments
auxCtl
Return Value
none
Description
This function sets the DMA AUXCTL register. You may use the
DMA_AUXCTL_RMK macro to construct the register value based on field
values. The default value for this register is DMA_AUXCTL_DEFAULT.
Example
DMA_setAuxCtl(0x00000000);
DMA_SUPPORT
Value to set AUXCTL register to
Compile time constant
Constant
DMA_SUPPORT
Description
Compile time constant that has a value of 1 if the device supports the DMA
module and 0 otherwise. You are not required to use this constant.
Note:
The DMA module is not supported on devices that do not have the DMA peripheral. In these cases, the EDMA module is supported instead.
Example
6-28
#if (DMA_SUPPORT)
/* user DMA configuration /
#elif (EDMA_SUPPORT)
/ user EDMA configuration */
#endif
DMA_wait
DMA_wait
Enters spin loop that polls DMA status bits until DMA completes
Function
void DMA_wait(
DMA_Handle hDma
);
Arguments
hDma
Return Value
none
Description
This function enters a spin loop that polls the DMA status bits until the DMA
completes. Interrupts are not disabled during this loop. This function is
equivalent to the following line of code:
Handle to DMA channel. See DMA_open()
while (DMA_getStatus(hDma)&DMA_STATUS_RUNNING);
Example
DMA_wait(hDma);
DMA Module
6-29
Chapter 7
EDMA Module
This chapter describes the EDMA module, lists the API functions and macros
within the module, discusses how to use an EDMA channel, and provides an
EDMA API reference section.
Topic
Page
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.3
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7-1
Overview
7.1 Overview
Currently, there are two DMA architectures used on C6x devices: DMA and
EDMA (Enhanced DMA). Devices such as the C6201 have the DMA
peripheral whereas C6211 devices have the EDMA peripheral. The two
architectures are different enough to warrant a separate API module for each.
Table 7−1 lists the configuration structures for use with the EDMA functions.
Table 7−2 lists the functions and constants available in the CSL EDMA
module.
Table 7−1. EDMA Configuration Structure
Structure
Purpose
EDMA_Config
The EDMA configuration structure used to set up an EDMA
channel
See page ...
7-7
Table 7−2. EDMA APIs
(a) EDMA Primary Functions
Syntax
Type Description
See page ...
EDMA_close
F
Closes a previously opened EDMA channel
7-8
EDMA_config
F
Sets up the EDMA channel using the configuration
structure
7-8
EDMA_configArgs
F
Sets up the EDMA channel using the EDMA parameter
arguments
7-9
EDMA_open
F
Opens an EDMA channel
7-10
EDMA_reset
F
Resets the given EDMA channel
7-15
(b) EDMA Auxiliary Functions and Constants
Syntax
Type Description
See page ...
EDMA_allocTable
F
Allocates a parameter RAM table from PRAM
7-16
EDMA_allocTableEx
F
Allocates set of parameter RAM tables from PRAM
7-17
EDMA_CHA_CNT
C
Number of EDMA channels
7-17
EDMA_chain
F
Sets the TCC,TCINT fields of the parent EDMA handle
7-18
EDMA_clearChannel
F
Clears the EDMA event flag in the EDMA channel event
register
7-19
EDMA_clearPram
F
Clears the EDMA parameter RAM (PRAM)
7-20
Note:
7-2
F = Function; C = Constant
Overview
Table 7−2. EDMA APIs (Continued)
Syntax
Type Description
See page ...
EDMA_disableChaining
F
Disables EDMA chaining
7-20
EDMA_enableChaining
F
Enables EDMA chaining
7-20
EDMA_disableChannel
F
Disables an EDMA channel
7-21
EDMA_enableChannel
F
Enables an EDMA channel
7-21
EDMA_freeTable
F
Frees up a PRAM table previously allocated
7-22
EDMA_freeTableEx
F
Frees a previously allocated set of parameter RAM
tables
7-22
EDMA_getChannel
F
Returns the current state of the channel event
7-23
EDMA_getConfig
F
Reads the current EDMA configuration values
7-23
EDMA_getPriQStatus
F
Returns the value of the priority queue status register
(PQSR)
7-24
EDMA_getScratchAddr
F
Returns the starting address of the EDMA PRAM used
as non-cacheable on-chip SRAM (scratch area)
7-24
EDMA_getScratchSize
F
Returns the size (in bytes) of the EDMA PRAM used as
non-cacheable on-chip SRAM (scratch area)
7-24
EDMA_getTableAddress
F
Returns the 32-bit absolute address of the table
7-25
EDMA_intAlloc
F
Allocates a transfer complete code
7-25
EDMA_intClear
F
Clears EDMA transfer completion interrupt pending flag
7-25
EDMA_intDefaultHandler
F
Default function called by EDMA_intDispatcher()
7-26
EDMA_intDisable
F
Disables EDMA transfer completion interrupt
7-26
EDMA_intDispatcher
F
Calls an ISR when CIER[x] and CIPR[x] are
both set
7-26
EDMA_intEnable
F
Enables EDMA transfer completion interrupt
7-27
EDMA_intFree
F
Frees a transfer complete code previously allocated
7-27
EDMA_intHook
F
Hooks to an ISR channel which is called by
EDMA_intDispatcher()
7-28
EDMA_intTest
F
Tests EDMA transfer completion interrupt pending flag
7-29
EDMA_link
F
Links two EDMA transfers together
7-29
EDMA_qdmaConfig
F
Sets up QDMA registers using configuration structure
7-30
EDMA_qdmaConfigArgs
F
Sets up QDMA registers using arguments
7-31
Note:
F = Function; C = Constant
EDMA Module
7-3
Overview
Table 7−2. EDMA APIs (Continued)
Syntax
Type Description
See page ...
EDMA_resetAll
F
Resets all EDMA channels supported by the chip device
7-32
EDMA_resetPriQLength
F
Resets the Priority queue length to the default value
7-32
EDMA_setChannel
F
Triggers an EDMA channel by writing to the appropriate
bit in the event set register (ESR)
7-32
EDMA_setEvtPolarity
F
Sets the polarity of the event associated with the EDMA
handle.
7-33
EDMA_setPriQLength
F
Sets the length of a given priority queue allocation
register
7-33
EDMA_SUPPORT
C
A compile-time constant whose value is 1 if the device
supports the EDMA module
7-34
EDMA_TABLE_CNT
C
A compile-time constant that holds the total number of
parameter table entries in the EDMA PRAM
7-34
Note:
7.1.1
F = Function; C = Constant
Using an EDMA Channel
To use an EDMA channel, you must first open it and obtain a device handle
using EDMA_open(). Once opened, use the device handle to call the other
API functions. The channel may be configured by passing an EDMA_Config
structure to EDMA_config() or by passing register values to the
EDMA_configArgs() function. To assist in creating register values, the
_RMK (make) macros construct register values based on field values. In
addition, the symbol constants may be used for the field values.
Two functions manage the parameter RAM
EDMA_allocTable() and EDMA_freeTable().
7-4
(PRAM)
tables:
Macros
7.2 Macros
There are two types of EDMA macros: those that access registers and fields,
and those that construct register and field values.
Table 7−3 lists the EDMA macros that access registers and fields, and
Table 7−4 lists the EDMA macros that construct register and field values. The
macros themselves are found in Chapter 28, Using the HAL Macros.
The EDMA module includes handle-based macros.
Table 7−3. EDMA Macros That Access Registers and Fields
Macro
Description/Purpose
See page...
EDMA_ADDR()
Register address
28-12
EDMA_RGET()
Returns the current value of a register
28-18
EDMA_RSET(,x)
Register set
28-20
EDMA_FGET(,)
Returns the value of the specified field in a
register
28-13
EDMA_FSET(,,x)
Writes fieldval to the specified field in a register
28-15
EDMA_FSETS(,,)
Writes the symbol value to the specified field in
the peripheral
28-17
EDMA_RGETA(addr,)
Gets register value for a given address
28-19
EDMA_RSETA(addr,,x)
Sets register for a given address
28-20
EDMA_FGETA(addr,,)
Gets field for a given address
28-13
EDMA_FSETA(addr,,,x)
Sets field for a given address
28-16
EDMA_FSETSA(addr,,,
)
Sets field symbolically for a given address
28-17
EDMA_ADDRH(h,)
Returns the address of a memory-mapped
register for a given handle
28-12
EDMA_RGETH(h,)
Returns the value of a register for a given handle
28-19
EDMA_RSETH(h,,x)
Sets the register value to x for a given handle
28-21
EDMA_FGETH(h,,)
Returns the value of the field for a given handle
28-14
EDMA_FSETH(h,,,x)
Sets the field value to x for a given handle
28-16
EDMA_FSETSH(h,,,
)
Sets the field symbolically for a given handle
28-18
EDMA Module
7-5
Macros
Table 7−4. EDMA Macros that Construct Register and Field Values
Macro
Description/Purpose
See page...
EDMA__DEFAULT
Register default value
28-21
EDMA__RMK()
Register make
28-23
EDMA__OF()
Register value of ...
28-22
EDMA___DEFAULT
Field default value
28-24
EDMA_FMK()
Field make
28-14
EDMA_FMKS()
Field make symbolically
28-15
EDMA___OF()
Field value of ...
28-24
EDMA___
Field symbolic value
28-24
7-6
EDMA_Config
7.3 Configuration Structure
EDMA_Config
EDMA configuration structure used to set up EDMA channel
Structure
EDMA_Config
Members
Uint32 opt
Options
Uint32 src
Source address
Uint32 cnt
Transfer count
Uint32 dst
Destination address
Uint32 idx
Index
Uint32 rld
Element count reload and link address
Description
This is the EDMA configuration structure used to set up an EDMA channel. You
create and initialize this structure and then pass its address to the
EDMA_config() function.
Example
EDMA_Config myConfig = {
0x41200000, /* opt */
0x80000000, /* src */
0x00000040, /* cnt */
0x80010000, /* dst */
0x00000004, /* idx */
0x00000000 /* rld */
};
…
EDMA_config(hEdma,&myConfig);
EDMA Module
7-7
EDMA_close
7.4 Functions
7.4.1
EDMA Primary Functions
EDMA_close
Closes previously opened EDMA channel
Function
void EDMA_close(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
Closes a previously opened EDMA channel.
Device handle. See EDMA_open().
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_config
EDMA_close(hEdma);
Sets up EDMA channel using configuration structure
Function
void EDMA_config(
EDMA_Handle hEdma,
EDMA_Config *config
);
Arguments
hEdma
Device handle. See EDMA_open() and EDMA_allocTable().
config
Pointer to an initialized configuration structure
Return Value
none
Description
Sets up the EDMA channel using the configuration structure. The values of the
structure are written to the EDMA PRAM entries. The options value (opt) is
written last. See also EDMA_configArgs() and EDMA_Config.
This function accepts the following device handles:
- From EDMA_open()
- From EDMA_allocTable()
7-8
EDMA_configArgs
Example
EDMA_Config myConfig = {
0x41200000, /* opt */
0x80000000, /* src */
0x00000040, /* cnt */
0x80010000, /* dst */
0x00000004, /* idx */
0x00000000 /* rld */
};
…
EDMA_config(hEdma,&myConfig);
EDMA_configArgs Sets up EDMA channel using EDMA parameter arguments
Function
void EDMA_configArgs(
EDMA_Handle hEdma,
Uint32 opt,
Uint32 src,
Uint32 cnt,
Uint32 dst,
Uint32 idx,
Uint32 rld
);
Arguments
hEdma
Device handle. See EDMA_open() and EDMA_allocTable().
opt
Options
src
Source address
cnt
Transfer count
dst
Destination address
idx
Index
rld
Element count reload and link address
Return Value
none
Description
Sets up the EDMA channel using the EDMA parameter arguments. The values
of the arguments are written to the EDMA PRAM entries. The options value
(opt) is written last. See also EDMA_config().
This function accepts the following device handles:
EDMA Module
7-9
EDMA_open
- From EDMA_open()
- From EDMA_allocTable()
Example
EDMA_open
EDMA_configArgs(hEdma,
0x41200000, /* opt */
0x80000000, /* src */
0x00000040, /* cnt */
0x80010000, /* dst */
0x00000004, /* idx */
0x00000000 /* rld */
);
Opens EDMA channel
Function
EDMA_Handle EDMA_open(
int chaNum,
Uint32 flags
);
Arguments
chaNum
EDMA channel to open:
(For C6201, C6202, C6203, C6204, C6205, C6701, C6211, C6711, C6711C,
C6712 and C6712C)
- EDMA_CHA_ANY
- EDMA_CHA_DSPINT
- EDMA_CHA_TINT0
- EDMA_CHA_TINT1
- EDMA_CHA_SDINT
- EDMA_CHA_EXTINT4
- EDMA_CHA_EXTINT5
- EDMA_CHA_EXTINT6
- EDMA_CHA_EXTINT7
- EDMA_CHA_TCC8
- EDMA_CHA_TCC9
- EDMA_CHA_TCC10
- EDMA_CHA_TCC11
- EDMA_CHA_XEVT0
- EDMA_CHA_REVT0
- EDMA_CHA_XEVT1
- EDMA_CHA_REVT1
- EDMA_CHA_ANY
- EDMA_CHA_DSPINT
- EDMA_CHA_TINT0
7-10
EDMA_open
-
EDMA_CHA_TINT1
EDMA_CHA_SDINT
EDMA_CHA_EXTINT4
EDMA_CHA_EXTINT5
EDMA_CHA_EXTINT6
EDMA_CHA_EXTINT7
EDMA_CHA_TCC8
EDMA_CHA_TCC9
EDMA_CHA_TCC10
EDMA_CHA_TCC11
EDMA_CHA_XEVT0
EDMA_CHA_REVT0
EDMA_CHA_XEVT1
EDMA_CHA_REVT1
(In addition, for C6711C and C6712C)
- EDMA_CHA_GPINT4
- EDMA_CHA_GPINT5
- EDMA_CHA_GPINT6
- EDMA_CHA_GPINT7
- EDMA_CHA_GPINT2
(For C6713, DA610, C6414, C6415, C6416, DM642, C6412, and C6413)
- EDMA_CHA_ANY
- EDMA_CHA_DSPINT
- EDMA_CHA_TINT0
- EDMA_CHA_TINT1
- EDMA_CHA_SDINT
- EDMA_CHA_EXTINT4
- EDMA_CHA_GPINT4
- EDMA_CHA_EXTINT5
- EDMA_CHA_GPINT5
- EDMA_CHA_EXTINT6
- EDMA_CHA_GPINT6
- EDMA_CHA_EXTINT7
- EDMA_CHA_GPINT7
- EDMA_CHA_TCC8
- EDMA_CHA_GPINT0
- EDMA_CHA_TCC9
- EDMA_CHA_GPINT1
- EDMA_CHA_TCC10
- EDMA_CHA_GPINT2
- EDMA_CHA_TCC11
EDMA Module
7-11
EDMA_open
-
EDMA_CHA_GPINT3
EDMA_CHA_XEVT0
EDMA_CHA_REVT0
EDMA_CHA_XEVT1
EDMA_CHA_REVT1
EDMA_CHA_GPINT8
EDMA_CHA_GPINT9
EDMA_CHA_GPINT10
EDMA_CHA_GPINT11
EDMA_CHA_GPINT12
EDMA_CHA_GPINT13
EDMA_CHA_GPINT14
EDMA_CHA_GPINT15
(In addition, for C6713 and DA610)
- EDMA_CHA_AXEVTE0
- EDMA_CHA_AXEVTO0
- EDMA_CHA_AXEVT0
- EDMA_CHA_AREVTE0
- EDMA_CHA_AREVTO0
- EDMA_CHA_AREVT0
- EDMA_CHA_AXEVTE1
- EDMA_CHA_AXEVTO1
- EDMA_CHA_AXEVT1
- EDMA_CHA_AREVTE1
- EDMA_CHA_AREVTO1
- EDMA_CHA_AREVT1
- EDMA_CHA_ICREVT0
- EDMA_CHA_ICXEVT0
- EDMA_CHA_ICREVT1
- EDMA_CHA_ICXEVT1
(In addition, for C6410, and C6413)
- EDMA_CHA_TINT2
- EDMA_CHA_VCPREVT0
- EDMA_CHA_VCPXEVT0
- EDMA_CHA_AXEVTE0
- EDMA_CHA_AXEVTO0
- EDMA_CHA_AXEVT0
- EDMA_CHA_AREVTE0
- EDMA_CHA_AREVTO0
- EDMA_CHA_AREVT0
- EDMA_CHA_AXEVTE1
7-12
EDMA_open
-
EDMA_CHA_AXEVTO1
EDMA_CHA_AXEVT1
EDMA_CHA_AXEVTE1
EDMA_CHA_AXEVTO1
EDMA_CHA_AXEVT1
EDMA_CHA_ICREVT0
EDMA_CHA_ICXEVT0
EDMA_CHA_ICREVT1
EDMA_CHA_ICXEVT1
(In addition, for DM642)
-
EDMA_CHA_VP0EVTYA
EDMA_CHA_VP0EVTUA
EDMA_CHA_VP0EVTVA
EDMA_CHA_TINT2
EDMA_CHA_PCI
EDMA_CHA_MACEVT
EDMA_CHA_ICREVT0
EDMA_CHA_ICXEVT0
EDMA_CHA_VP0EVTYB
EDMA_CHA_VP0EVTUB
EDMA_CHA_VP0EVTVB
EDMA_CHA_AXEVTE0
EDMA_CHA_AXEVTO0
EDMA_CHA_AXEVT0
EDMA_CHA_AREVTE0
EDMA_CHA_AREVTO0
EDMA_CHA_AREVT0
EDMA_CHA_VP1EVTYB
EDMA_CHA_VP1EVTUB
EDMA_CHA_VP1EVTVB
EDMA_CHA_VP2EVTYB
EDMA_CHA_VP2EVTUB
EDMA_CHA_VP2EVTVB
EDMA_CHA_VP1EVTYA
EDMA_CHA_VP1EVTUA
EDMA_CHA_VP1EVTVA
EDMA_CHA_VP2EVTYA
EDMA_CHA_VP2EVTUA
EDMA_CHA_VP2EVTVA
EDMA Module
7-13
EDMA_open
(In addition, for C6414, C6415 and C6416)
- EDMA_CHA_XEVT2
- EDMA_CHA_REVT2
- EDMA_CHA_TINT2
- EDMA_CHA_SDINTB
- EDMA_CHA_PCI
- EDMA_CHA_VCPREVT
- EDMA_CHA_VCPXEVT
- EDMA_CHA_TCPREVT
- EDMA_CHA_TCPXEVT
- EDMA_CHA_UREVT
- EDMA_CHA_UREVT0
- EDMA_CHA_UREVT1
- EDMA_CHA_UREVT2
- EDMA_CHA_UREVT3
- EDMA_CHA_UREVT4
- EDMA_CHA_UREVT5
- EDMA_CHA_UREVT6
- EDMA_CHA_UREVT7
- EDMA_CHA_UXEVT
- EDMA_CHA_UXEVT0
- EDMA_CHA_UXEVT1
- EDMA_CHA_UXEVT2
- EDMA_CHA_UXEVT3
- EDMA_CHA_UXEVT4
- EDMA_CHA_UXEVT5
- EDMA_CHA_UXEVT6
- EDMA_CHA_UXEVT7
(In addition, for C6412)
- EDMA_CHA_TINT2
- EDMA_CHA_PCI
- EDMA_CHA_MACEVT
- EDMA_CHA_ICREVT0
- EDMA_CHA_ICXEVT0
flags
Return Value
7-14
Open flags, logical OR of any of the following:
- EDMA_OPEN_RESET
- EDMA_OPEN_ENABLE
Device Handle Device handle to be used by other EDMA API function calls.
EDMA_reset
Description
Before an EDMA channel can be used, it must first be opened by this function.
Once opened, it cannot be opened again until closed. See EDMA_close().
You have the option of either specifying exactly which physical channel to open
or you can let the library pick an unused one for you by specifying
EDMA_CHA_ANY. The return value is a unique device handle that you use in
subsequent EDMA API calls. If the open fails, INV is returned.
If the EDMA_OPEN_RESET is specified, the EDMA channel is reset and the
channel interrupt is disabled and cleared. If the EDMA_OPEN_ENABLE flag is
specified, the channel will be enabled.
If the channel cannot be opened, INV is returned.
Note: If the DAT module is open [see DAT_open()], then EDMA transfer
completion interrupts 1 through 4 are reserved.
Refer to the TMS320C6000 Peripherals Reference Guide (SPRU190) for
details regarding the EDMA channels.
Example
EDMA_reset
EDMA_Handle hEdma;
...
hEdma = EDMA_open(EDMA_CHA_TINT0,EDMA_OPEN_RESET);
...
Resets given EDMA channel
Function
void EDMA_reset(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
Resets the given EDMA channel.
Device handle obtained by EDMA_open().
The following steps are taken:
- The channel is disabled
- The channel event flag is cleared
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_reset(hEdma);
EDMA Module
7-15
EDMA_allocTable
7.4.2
EDMA Auxiliary Functions and Constants
EDMA_allocTable
Allocates a parameter RAM table from PRAM
Function
EDMA_Handle EDMA_allocTable(
int tableNum
);
Arguments
tableNum
Return Value
Device Handle Returns a device handle
Description
This function allocates the PRAM tables dedicated to the Reload/Link
parameters. You use the Reload/Link PRAM tables for linking transfers
together. You can either specify a table number or specify –1 and the function
will pick an unused one for you. The return value is a device handle and may
be used for APIs that require a device handle. If the table could not be
allocated, then INV is returned.
Table number to allocate. Valid values are 0 to
EDMA_TABLE_CNT–1; –1 for any.
If you finish with the table and wish to free it up again, call
EDMA_freeTable().
For TMS320C621x/C671x, the first two tables located at 0x01A00180 and
0x01A00198, respectively, are reserved. The first parameter table is initialized
to zero, and the second table is reserved for CSL code. The first available table
for the user starts at address 0x01A001B0. There are 67 available tables, with
table numbers from 0 to 66.
For TMS320C64xx, the first two tables located at 0x01A00600 and
0x01A00618 are reserved. The first parameter table is initialized to zero, and
the second table is reserved for CSL code. The first available table for the user
starts at address 0x01A00630. There are 19 available tables, with table
numbers from 0 to 18.
hEdmaTable=EDMA_allocTable(0);
will allocate the Reload/Link parameter table located at:
- 0x01A001B0 for C621x/C671x devices
- 0x01A00630 for C64xx devices
Example
7-16
EDMA_Handle hEdmaTable;
...
hEdmaTable = EDMA_allocTable(–1);
EDMA_allocTableEx
EDMA_allocTableEx Allocates set of parameter RAM tables from PRAM
Function
int EDMA_allocTableEx(
int cnt,
EDMA_Handle *array
);
Arguments
cnt
Number of tables to allocate
array
An array to hold the table handles for each table allocated
Return Value
numAllocated
cnt or 0.
Returns the actual number of tables allocated. It will either be
Description
This function allocates a set of parameter RAM tables from PRAM. The tables
are not guaranteed to be contiguous in memory. You use PRAM tables for
linking transfers together. The array passed in is filled with table handles and
each one may be used for APIs that require a device handle.
If you finish with the tables and wish to free them up again, call
EDMA_freeTableEx().
Example
EDMA_CHA_CNT
EDMA_Handle hEdmaTableArray[16];
...
if (EDMA_allocTableEx(16,hEdmaTableArray)) {
...
}
Number of EDMA channels
Constant
EDMA_CHA_CNT
Description
Compile time constant that holds the number of EDMA channels.
EDMA Module
7-17
EDMA_chain
EDMA_chain
Sets the TCC, TCINT fields of the parent EDMA handle
Function
void EDMA_chain(
EDMA_Handle parent,
EDMA_Handle nextChannel,
int flag_tcc,
int flag_atcc
);
Arguments
parent
EDMA handle following the chainable transfer.
nextChannel
EDMA handle associated with the channel to be chained.
flag_tcc
Flag for TCC,TCINT setting (and TCCM for C64x devices).
The following constants must be used:
- 0
- EDMA_TCC_SET or 1
flag_atcc
Flag for ATCC, ATCINT setting (C64x devices only).
The following constants must be used:
- 0
- EDMA_ATCC_SET or 1
Return Value
none
Description
Sets the TCC,TCINT fields (and TCCM field for C64x devices) of the “parent”
EDMA handle based on the “nextChannel” EDMA handle.
For C621x/C671x, only channels from 8 to 11 are chainable.
7-18
EDMA_clearChannel
Example
EDMA_Handle hEdmaChain,hEdmaPar;
Unit32 Tcc;
/*Open and Configure parent Channel*/
hEdmaPar=EDMA_open(EDMA_CHA_TINT1,EDMA_OPEN_RESET);
EDMA_config(hEdmaPar,&myConfig);
/*Allocate a transfer complete code*/
Tcc=intAlloc(–1);
/*Open the Channel for the next transfer with TCC value*/
hEdmaChain=EDMA_open(Tcc,EDMA_OPEN_RESET);
/*Update the TCC, TCINT, (TCCM) fields of the parent channel
configuration*/
EDMA_chain(hEdmaPar,hEdmaChain,EDMA_TCC_SET,0)
/*Enable chaining: CCER (CCERL/CCERH) setting*/
);
EDMA_enableChaining(hEdmaChain);
EDMA_clearChannel Clears EDMA event flag in EDMA channel event register
Function
void EDMA_clearChannel(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
This function clears the EDMA event flag in the EDMA channel event register
by writing to the appropriate bit in the EDMA event clear register (ECR).
Device handle, see EDMA_open().
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_clearChannel(hEdma);
EDMA Module
7-19
EDMA_clearPram
EDMA_clearPram
Clears the EDMA parameter RAM (PRAM)
Function
void EDMA_clearPram(
Uint32 val
);
Arguments
val
Return Value
none
Description
This function clears all of the EDMA parameter RAM with the value specified.
This function should not be called if EDMA channels are active.
Example
EDMA_clearPram(0);
EDMA_disableChaining
Value to clear the PRAM with
Disables EDMA chaining
Function
void EDMA_disableChaining(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
Disables the CCE bit in the Channel Chaining Enable Register associated with
the EDMA handle. See also EDMA_enableChaining().
EDMA handle to be chained
For C621x/C671x, only channels from 8 to 11 are chainable.
Example
EDMA_enableChaining(hEdmaCha8);
EDMA_disableChaining(hEdmaCha8);
EDMA_enableChaining Enables EDMA chaining
Function
void EDMA_enableChaining(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
Enables the CCE bit in the Channel Chaining Enable Register associated with
the EDMA handle.
7-20
EDMA handle to be chained
EDMA_disableChannel
For C621x/C671x, only channels from 8 to 11 are chainable.
Example
EDMA _Handle hEdmaCha8
Uint32 Tcc;
/*Allocate the transfer complete code*/
Tcc=EDMA_intAlloc(8);
/*Open the channel related to the TCC*/
hEdmaCha8=EDMA_open(Tcc,EDMA_OPEN_RESET);
/*Enable chaining*/
EDMA_enableChaining(hEdmaCha8);
EDMA_disableChannel Disables EDMA channel
Function
void EDMA_disableChannel(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
Disables an EDMA channel by clearing the corresponding bit in the EDMA
event enable register. See also EDMA_enableChannel().
Device handle, see EDMA_open().
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_disableChannel(hEdma);
EDMA_enableChannel
Enables EDMA channel
Function
void EDMA_enableChannel(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
Enables an EDMA channel by setting the corresponding bit in the EDMA event
enable register. See also EDMA_disableChannel(). When you open an
EDMA channel it is disabled, so you must enable it explicitly.
Device handle, see EDMA_open().
EDMA Module
7-21
EDMA_freeTable
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_freeTable
EDMA_enableChannel(hEdma);
Frees up PRAM table previously allocated
Function
void EDMA_freeTable(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
none
Description
This function frees up
EDMA_allocTable().
Device handle. See EDMA_allocTable().
a
PRAM
table
previously
allocated
via
This function accepts the following device handle:
From EDMA_allocTable()
Example
EDMA_freeTableEx
EDMA_freeTable(hEdmaTable);
Frees a previously allocated set of parameter RAM tables
Function
void EDMA_freeTableEx(
int cnt,
EDMA_Handle *array
);
Arguments
cnt
Number of table handles in array to free
array
An array containing table handles for each table to be freed
Return Value
none
Description
This function frees a set of parameter RAM tables that were previously
allocated. You use PRAM tables for linking transfers together. The array that
is passed in must contain the table handles for each one to be freed.
Example
EDMA_Handle hEdmaTableArray[16];
...
if (EDMA_allocTableEx(16,hEdmaTableArray)) {
...
}
...
EDMA_freeTableEx(16,hEdmaTableArray);
7-22
EDMA_getChannel
EDMA_getChannel
Returns current state of channel event
Function
Uint32 EDMA_getChannel(
EDMA_Handle hEdma
);
Arguments
hEdma
Device handle. See EDMA_open().
Return Value
Channel Flag
Channel event flag:
- 0 – event not detected
- 1 – event detected
Description
Returns the current state of the channel event by reading the event flag from
the EDMA channel event register (ER).
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_getConfig
flag = EDMA_getChannel(hEdma);
Reads the current EDMA configuration values
Function
void EDMA_getConfig(
EDMA_Handle hEdma,
EDMA_Config *config
);
Arguments
hEdma
Device handle. See EDMA_open().
config
Pointer to a configuration structure.
Return Value
none
Description
Get EDMA current configuration value
Example
EDMA_Config edmaCfg;
EDMA_getConfig(hEdma,&edmaCfg);
EDMA Module
7-23
EDMA_getPriQStatus
EDMA_getPriQStatus Returns value of priority queue status register (PQSR)
Function
Uint32 EDMA_getPriQStatus();
Arguments
none
Return Value
Status
Description
Returns the value of the priority queue status register (PQSR). May be the
logical OR of any of the following:
Returns status of the priority queue
- 0x00000001– PQ0
- 0x00000002– PQ1
- 0x00000004 – PQ2
Example
pqStat = EDMA_getPriQStatus();
EDMA_getScratchAddr Returns starting address of EDMA PRAM scratch area
Function
Uint32 EDMA_getScratchAddr();
Arguments
none
Return Value
Scratch Address
Description
There is a small portion of the EDMA PRAM that is not used for parameter
tables and is free for use as non-cacheable on-chip SRAM. This function
returns the starting address of this scratch area. See also
EDMA_getScratchSize().
Example
Uint32 *scratchWord;
scratchWord = (Uint32*)EDMA_getScratchAddr();
32-bit starting address of PRAM scratch area
EDMA_getScratchSize Returns size (in bytes) of EDMA PRAM scratch area
Function
Uint32 EDMA_getScratchSize();
Arguments
none
Return Value
Scratch Size
Description
There is a small portion of the EDMA PRAM that is not used for parameter
tables and is free for use as non-cacheable on-chip SRAM. This function
returns the size of this scratch area in bytes. See also
EDMA_getScratchAddr().
Example
scratchSize = EDMA_getScratchSize();
7-24
Size of PRAM scratch area in bytes
EDMA_getTableAddress
EDMA_getTableAddress Returns 32-bit absolute address of table
Function
Uint32 EDMA_getTableAddress(
EDMA_Handle hEdma
);
Arguments
hEdma
Return Value
Table Address 32-bit address of table
Description
Given a device handle obtained from EDMA_allocTable(), this function
returns the 32-bit absolute address of the table.
Device handle obtained by EDMA_allocTable().
This function accepts the following device handle:
From EDMA_allocTable()
Example
EDMA_intAlloc
addr = EDMA_getTableAddress(hEdmaTable);
Allocates a transfer complete code
Function
int EDMA_intAlloc(
int tcc
);
Arguments
tcc
Transfer-complete code number or −1
Return Value
tccReturn
Transfer-complete code number or –1
Description
This function allocates the transfer-complete code passed in and returns the
same TCC number if successful, or –1 otherwise. If −1 is used as an argument,
the first available TCC number is allocated.
Example
EDMA_intAlloc(5);
EDMA_intAlloc(43);
tcc=EDMA_intAlloc(−1);;
EDMA_intClear
Clears EDMA transfer-completion interrupt-pending flag
Function
void EDMA_intClear(
Uint32 intNum
);
Arguments
intNum
Transfer-completion interrupt number [0..31].
EDMA Module
7-25
EDMA_intDefaultHandler
Return Value
none
Description
This function clears a transfer-completion interrupt flag by modifying the CIPR
register appropriately.
Note: If the DAT module is open [see DAT_open()], then EDMA
transfer-completion interrupts 1 through 4 are reserved.
Example
EDMA_intDefaultHandler
EDMA_intClear(12);
Default function called by EDMA_intDispatcher()
Function
void EDMA_intDefaultHandler(
int tccNum
);
Arguments
tccNum
Return Value
none
Description
This is the default function that is called by EDMA_intDispatcher(). It does
nothing, it just returns. See also EDMA_intDispatcher() and
EDMA_intHook().
EDMA_intDisable
Channel completion number
Disables EDMA transfer-completion interrupt
Function
void EDMA_intDisable(
Uint32 intNum
);
Arguments
intNum
Return Value
none
Description
This function disables a transfer-completion interrupt by modifying the CIER
register appropriately.
Transfer-completion interrupt number [0..31].
Note: If the DAT module is open [see DAT_open()], then EDMA
transfer-completion interrupts 1 through 4 are reserved.
Example
EDMA_intDisable(12);
EDMA_intDispatcher Calls an ISR when CIER[x] and CIPR[x] are both set
Function
void EDMA_intDispatcher(
void
);
Arguments
none
7-26
EDMA_intEnable
Return Value
none
Description
This function checks for CIER and CIPR for all those bits which are set in both
the registers and calls the corresponding ISR. For example, if CIER[14] = 1
and CIPR[14] =1 then it calls the ISR corresponding to channel 14. By default,
this ISR is EDMA_intHandler(), however, this can be changed by
EDMA_intHook(). See also EDMA_intDefaultHandler() and
EDMA_intHook().
Example
EDMA_intDispatcher();
EDMA_intEnable
Enables the EDMA transfer-completion interrupt
Function
void EDMA_intEnable(
Uint32 intNum
);
Arguments
intNum
Return Value
none
Description
This function enables a transfer completion interrupt by modifying the CIER
register appropriately.
Transfer-completion interrupt number [0..31].
Note: If the DAT module is open [see DAT_open()], then EDMA
transfer-completion interrupts 1 through 4 are reserved.
Example
EDMA_intFree
EDMA_intEnable(12);
Frees the transfer-complete code number
Function
void EDMA_intFree(
int tcc
);
Arguments
tcc
Return Value
none
Description
This function frees a transfer-complete code number previously allocated.
Example
EDMA_intAlloc(17);
...
EDMA_intFree(17);
Transfer-complete code number to be free
EDMA Module
7-27
EDMA_intHook
EDMA_intHook
Hooks an isr to a channel, which is called by EDMA_intDsipatcher()
Function
EDMA_IntHandler EDMA_intHook(
int
tccNum
EDMA_IntHandler
funcAddr
);
Arguments
tccNum
Channel to which the ISR is to be hooked
funcAddr
ISR name
Return Value
IntHandler Returns the old ISR address
Description
This function hooks an ISR to the specified channel.
When the tcint is ’1’ and tccNum is specified in the EDMA options, the EDMA
controller sets the corresponding bit in the CIPR register. If the corresponding
bit in the CIER register is also set, then calling EDMA_intDispatcher()
would call the ISR corresponding the the tccNum, which by default is nothing.
To change this default ISR to a different one, use EDMA_intHook(). Only
when an ISR is hooked this way would it be called. See also
EDMA_intDefaultHandler() and EDMA_intDispatcher().
Example
EDMA_intReset
void complete();
EDMA_intHook(13,
channel 13
complete);
//Hooks
complete
function
to
Resets a specified interrupt
Function
void EDMA_intReset(
Uint32 tccIntNum
);
Arguments
tccIntNum Interrupt mask of interrupt to be reset
Return Value
None
Description
A single interrupt can be turned off using this function. This function turns off
the corresponding bit for the interrupt number in the CIERL or CIERH in case
of C64xx devices and int the CIER in case of others.
Example
EDMA_intReset(0x1);
//turn off interrupt related to bit 1 of CIER (or CIERL in
case of C64xx devices)
7-28
EDMA_intResetAll
EDMA_intResetAll Resets all interrupts for the device
Function
void EDMA_intResetAll();
Arguments
None
Return Value
None
Description
This function resets the CIER register (CIERL and CIERH in case of C64xx
devices) so that all interrupts are disabled. It also sets all the bits of the CIPR
register (CIPRL and CIPRH in case of C64xx devices).
EDMA_intTest
Tests EDMA transfer-completion interrupt-pending flag
Function
Uint32 EDMA_intTest(
Uint32 intNum
);
Arguments
intNum
Transfer-completion interrupt number [0..31].
Return Value
Uint32
Result:
0 = flag was clear
1 = flag was set
Description
This function tests a transfer-completion interrupt flag by reading the CIPR
register appropriately.
Note: If the DAT module is open [see DAT_open()], then EDMA
transfer-completion interrupts 1 through 4 are reserved.
Example
EDMA_link
if (EDMA_intTest(12)) {
...
}
Links two EDMA transfers together
Function
void EDMA_link(
EDMA_Handle parent,
EDMA_Handle child
);
Arguments
parent
Handle of the parent (link from parent)
child
Handle of the child (link to child)
EDMA Module
7-29
EDMA_map
Return Value
none
Description
This function links two EDMA transfers together by setting the LINK field of the
parent’s RLD parameter appropriately. Both parent and child handles may be
from EDMA_open(), EDMA_allocTable(), or a combination of both.
parent–>child
Note: This function does not attempt to set the LINK field of the OPT
parameter; this is still up to the user.
Example
EDMA_map
EDMA_Handle hEdma;
EDMA_Handle hEdmaTable;
...
hEdma = EDMA_open(EDMA_CHA_TINT1,0);
hEdmaTable = EDMA_allocTable(–1);
EDMA_link(hEdma,hEdmaTable);
EDMA_link(hEdmaTable,hEdmaTable);
Maps EDMA event to a channel
Function
void EDMA_map(
int eventNum,
int chNum
Arguments
eventNum EDMA event to be mapped to channel
chNum Channel to which event is to be mapped
Return Value
int Returns channel selected for mapping
Description
This function maps the given EDMA event to specified channel
Example
EDMA_map(12, 3); //Maps event 12 to channel 3
EDMA_qdmaConfig
Sets up QDMA registers using configuration structure
Function
void EDMA_qdmaConfig(
EDMA_Config *config
);
Arguments
config
Return Value
none
Description
Sets up the QDMA registers using the configuration structure. The src, cnt, dst,
and idx values are written to the normal QDMA registers, then the opt value
is written to the pseudo-OPT register which initiates the transfer. The rld
member of the structure is ignored, since the QDMA does not support reloads
or linking. See also EDMA_qdmaConfigArgs() and EDMA_Config.
7-30
Pointer to an initialized configuration structure
EDMA_qdmaConfigArgs
Example
EDMA_Config myConfig = {
0x41200000, /* opt */
0x80000000, /* src */
0x00000040, /* cnt */
0x80010000, /* dst */
0x00000004, /* idx */
0x00000000 /* rld will be ignored */
};
…
EDMA_qdmaConfig(&myConfig);
EDMA_qdmaConfigArgs Sets up QDMA registers using arguments
Function
void EDMA_qdmaConfigArgs(
Uint32 opt,
Uint32 src,
Uint32 cnt,
Uint32 dst,
Uint32 idx
);
Arguments
opt
Options
src
Source address
cnt
Transfer count
dst
Destination address
idx
Index
Return Value
none
Description
Sets up the QDMA registers using the arguments passed in. The src, cnt, dst,
and idx values are written to the normal QDMA registers, then the opt value
is written to the pseudo-OPT register which initiates the transfer. See also
EDMA_qdmaConfig() and EDMA_Config.
Example
EDMA_qdmaConfigArgs(
0x41200000, /* opt
0x80000000, /* src
0x00000040, /* cnt
0x80010000, /* dst
0x00000004 /* idx
);
*/
*/
*/
*/
*/
EDMA Module
7-31
EDMA_resetAll
EDMA_resetAll
Resets all EDMA channels supported by the chip device
Function
void EDMA_resetAll();
Arguments
none
Return Value
none
Description
This function resets all EDMA channels supported by the device by disabling
EDMA enable bits, disabling and clearing the channel interrupt registers, and
clearing the PRAM tables associated to the EDMA events.
Example
EDMA_resetAll();
EDMA_resetPriQLength
Resets the priority queue length (C64x devices only)
Function
void EDMA_resetPriQLength(
Uint32 priNum
)
Arguments
priNum
Return Value
none
Description
Resets the queue length of the associated priority queue allocation register to
the default value. See also EDMA_setPriQLength() function
Example
/* Sets the queue length of the PQAR0 register */
EDMA_setPriQLength(EDMA_Q0,4);
/* Resets the queue length of the PQAR0 */
EDMA_resetPriQLength(EDMA_Q0);
Queue Number [0–3] associated to the following constants:
- EDMA_Q0
- EDMA_Q1
- EDMA_Q2
- EDMA_Q3
EDMA_setChannel Triggers EDMA channel by writing to appropriate bit in ESR
Function
void EDMA_setChannel(
EDMA_Handle hEdma
);
Arguments
hEdma
7-32
Device handle obtained by EDMA_open().
EDMA_setEvtPolarity
Return Value
none
Description
Software triggers an EDMA channel by writing to the appropriate bit in the
EDMA event set register (ESR).
This function accepts the following device handle:
From EDMA_open()
Example
EDMA_setChannel(hEdma);
EDMA_setEvtPolarity Sets the event polarity associated with an EDMA channel
Function
void EDMA_setEvtPolarity(
EDMA_handle hEdma,
int polarity
);
Arguments
hEdma
Device handle associated with the EDMA channel obtained by
EDMA_open()
polarity
Event polarity (0 or 1)
- EDMA_EVT_LOWHIGH (0)
- EDMA_EVT_HIGHLOW (1)
Return Value
none
Description
Sets the polarity of the event associated with the EDMA channel.
Example
/* Sets the polarity of the event to
transition*/
hEdma=EDMA_open(EDMA_CHA_TINT1,0);
EDMA_setEvtPolarity(hEdma,EDMA_EVT_HIGHLOW);
falling-edge
of
EDMA_setPriQLength Sets the priority queue length (C64x devices only)
Function
EDMA_setPriQLength(
Uint32 priNum,
Uint32 length
);
Arguments
priNum
Queue Number [0–3] associated to the following constants:
- EDMA_Q0
- EDMA_Q1
- EDMA_Q2
- EDMA_Q3
length
length of the queue
EDMA Module
7-33
EDMA_SUPPORT
Return Value
none
Description
Sets the queue length of the associated priority queue allocation register (See
EDMA_resetPriQLength() function.)
Example
/* Sets the queue length of the PQAR1 register to 4 */
EDMA_setPriQLength(EDMA_Q1,4);
EDMA_resetPriQLength(EDMA_Q1);
EDMA_SUPPORT
Compile-time constant
Constant
EDMA_SUPPORT
Description
Compile-time constant that has a value of 1 if the device supports the EDMA
module and 0 otherwise. You are not required to use this constant.
Note: The EDMA module is not supported on devices that do not have the
EDMA peripheral. In these cases, the DMA module is supported instead.
Example
EDMA_TABLE_CNT
#if (EDMA_SUPPORT)
/* user EDMA configuration /
#elif (DMA_SUPPORT)
/ user DMA configuration */
#endif
Compile-time constant
Constant
EDMA_TABLE_CNT
Description
Compile-time constant that holds the total number of reload/link
parameter-table entries in the EDMA PRAM.
7-34
Chapter 8
EMAC Module
This chapter describes the EMAC module, lists the API functions and macros
within the module, and provides an EMAC reference section.
Topic
Page
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3
Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8-1
Overview
8.1 Overview
The ethernet media access controller (EMAC) module provides an efficient
interface between the DSP core processor and the networked community. The
EMAC supports both 10Base-T (10Mbits/sec) and 100BaseTX
(100Mbits/sec), in either half or full duplex, with hardware flow control and
quality-of-service (QOS) support.
Note: When used in a multitasking environment, no EMAC function may be
called while another EMAC function is operating on the same device handle
in another thread. It is the responsibility of the application to assure adherence
to this restriction.
Table 8−1 lists the configuration structures for use with the EMAC functions.
Table 8−2 lists the functions and constants available in the CSL EMAC
module.
Table 8−1. EMAC Configuration Structure
Structure
Purpose
See page
EMAC_Config
The config structure defines how the EMAC device should operate
8-6
EMAC_Pkt
The packet structure defines the basic unit of memory used to hold
data packets for the EMAC device
8-8
EMAC_Status
The status structure contains information about the MAC’s run-time
status
8-10
EMAC_Statistics
The statistics structure is used to retreive the current count of
various packet events in the system
8-11
Table 8−2. EMAC APIs
Syntax
Type Description
See page
EMAC_close
F
Closes the EMAC peripheral indicated by the supplied
instance handle
8-13
EMAC_enumerate
F
Enumerates the EMAC peripherals installed in the system
and returns an integer count
8-13
EMAC_getReceiveFilter
F
Called to get the current packet filter setting for received
packets.
8-14
EMAC_getStatistics
F
Called to get the current device statistics
8-15
EMAC_getStatus
F
Called to get the current device status
8-16
EMAC_open
F
Opens the EMAC peripheral at the given physical index
8-17
EMAC_setReceiveFilter
F
Called to set the packet filter for received packets
8-18
8-2
Overview
Table 8−2. EMAC APIs (Continued)
Syntax
Type Description
See page
EMAC_setMulticast
F
Called to install a list of multicast addresses for use in
multicast address filtering
8-19
EMAC_sendPacket
F
Sends a Ethernet data packet out the EMAC device
8-20
EMAC_serviceCheck
F
This function should be called every time there is an
EMAC device interrupt
8-21
EMAC_SUPPORT
C
A compile-time constant whose value is 1 if the device
supports the EMAC module
8-22
EMAC_timerTick
F
This function should be called for each device in the
system on a periodic basis of 100 mS
8-22
EMAC Module
8-3
Macros
8.2 Macros
There are two types of EMAC macros: those that access registers and fields,
and those that construct register and field values. Table 8−3 lists the EMAC
macros that access registers and fields, and Table 8−3 lists the EMAC macros
that construct register and field values. The macros themselves are found in
Chapter 28, Using the HAL Macros.
Table 8−3. EMAC Macros That Access Registers and Fields
Macro
Description/Purpose
EMAC_ADDR()
Register address
28-12
EMAC_RGET()
Returns the value in the peripheral register
28-18
EMAC_RGETI(,)
Returns the value of register at position IDX from
REGBASE
EMAC_RSET(,x)
Register set
EMAC_RSETI(,,x)
Sets the value of register at position IDX from
REGBASE
EMAC_FGET(,)
Returns the value of the specified field in the
peripheral register
EMAC_FGETI(,,
)
Returns the value of field of register at position
IDX from REGBASE
EMAC_FSET(,,fieldval)
Writes fieldval to the specified field in the
peripheral register
EMAC_FSETI(,,
,x)
Sets the value of field of register at position IDX
from REGBASE
EMAC_FSETS(,,)
Writes the symbol value to the specified field in
the peripheral
EMAC_FSETSI(,,
,)
Writes the symbol value to field of register at
position IDX from REGBASE
8-4
See page
28-20
28-13
28-15
28-17
Macros
Table 8−4. EMAC Macros that Construct Registers and Fields
Macro
Description/Purpose
See page
EMAC__DEFAULT
Register default value
28-21
EMAC__RMK()
Register make
28-23
EMAC__OF()
Register value of
28-22
EMAC___DEFAULT
Field default value
28-24
EMAC_FMK()
Field make
28-14
EMAC_FMKS()
Field make symbolically
28-15
EMAC___OF()
Field value of
28-24
EMAC___
Field symbolic value
28-24
EMAC Module
8-5
EMAC_Config
8.3 Configuration Structure
EMAC_Config
Members
EMAC configuration defines how the EMAC device should operate
Uint ModeFlags:
/* Configuation Mode Flags */
Uint MdioModeFlags;
/* csl_mdio Mode Flags (see csl_mdio.h) */
Uint TxChannels;
/* Number of Tx Channels to use (1−8) */
Uint8 MacAddr[6];
/* Mac Address */
Uint RxMaxPktPool;
/* Max Rx packet buffers to get from pool */
EMACPkt EMAC_Pkt * (*pfcbGetPacket)(Handle hApplication);
/* Callback function */
void (*pfcbFreePacket)(Handle hApplication, EMAC_Pkt *pPacket);
/* Callback function */
EMAC_Pkt *(*pfcbRxPacket)(Handle hApplication, EMAC_Pkt *pPacket);
/*Callback function */
void (*pfcbStatus)(Handle hApplication);
/* Callback function */
void (*pfcbStatistics)(Handle hApplication);
/* Callback function */
Description
The config structure defines how the EMAC device should operate. It is passed
to the device when the device is opened, and remains in effect until the device
is closed.
A list of callback functions is used to register callback functions with a particular
instance of the EMAC peripheral. Callback functions are used by EMAC to
communicate with the application. These functions are REQUIRED for
operation. The same callback table can be used for multiple driver instances.
The callback functions can be used by EMAC during any EMAC function, but
mostly occur during calls to EMAC_statusIsr() and EMAC_statusPoll().
8-6
EMAC_Config
- * pfcbGetPacket
Called by EMAC to get a free packet buffer from the application layer for
receive data. This function should return NULL is no free packets are
available. The size of the packet buffer must be large enough to
accommodate a full sized packet (1514 or 1518 depending on the
EMAC_CONFIG_MODEFLG_RXCRC flag), plus any application buffer
padding (DataOffset).
- * pfcbFreePacket
Called by EMAC to give a free packet buffer back to the application layer.
This function is used to return transmit packets. Note that at the time of the
call, structure fields other than pDataBuffer and BufferLen are in an
undefined state.
- * pfcbRxPacket
Called to give a received data packet to the application layer. The
applicaiton must accept the packet. When the application is finished with
the packet, it can return it to its own free queue. This function also returns a
pointer to a free packet to replace the received packet on the EMAC free
list. It returns NULL when no free packets are available. The return packet
is the same as would be returned by pfcbGetPacket. Therefore, if a newly
received packet is not desired, it can simply be returned to EMAC via the
return value.
- * pfcbStatus
Called to indicate to the application that it should call EMAC_getStatus() to
read the current device status. This call is made when device status
changes.
- * pfcbStatistics
Called to indicate to the application that it should call EMAC_getStatistics()
to read the current Ethernet statistics. Called when the statistic counters
are to the point of overflow. The hApplication calling calling argument is the
application’s handle as supplied to the EMAC device in the EMAC_open()
function.
EMAC Module
8-7
EMAC_Pkt
EMAC_Pkt
Members
Defines the basic unit of memory used to hold data packets for the
EMAC
Uint32 AppPrivate;
struct _EMAC_Pkt *pPrev;
struct _EMAC_Pkt *pNext;
Uint8 *pDataBuffer;
Uint32 BufferLen;
Uint32 Flags;
Uint32 ValidLen;
Uint32 DataOffset;
Uint32 PktChannel;
Uint32 PktLength;
Uint32 PktFrags;
Description
/*For use by the application
/*Previous record */
/*Next record */
/*Pointer to Data Buffer (read only) */
/*Physical Length of buffer (read only) */
/*Packet Flags */
/*Length of valid data in buffer */
/*Byte offset to valid data */
/*Tx/Rx Channel/Priority 0−7 (SOP only) */
/*Length of Packet (SOP only) */
/*(same as ValidLen on single frag Pkt) */
/*Number of frags in packet (SOP only) */
/*(frag is EMAC_Pkt record − normally 1)*/
The packet structure defines the basic unit of memory used to hold data
packets for the EMAC device.
A packet is comprised of one or more packet buffers. Each packet buffer
contains a packet buffer header, and a pointer to the buffer data. The
EMAC_Pkt structure defines the packet buffer header.
The pDataBuffer field points to the packet data. This is set when the buffer is
allocated, and is not altered.
BufferLen holds the the total length of the data buffer that is used to store the
packet (or packet fragment). This size is set by the entity that originally
allocates the buffer, and is not altered.
The Flags field contains additional information about the packet.
ValidLen holds the length of the valid data currently contained in the data
buffer.
DataOffset is the byte offset from the start of the data buffer to the first byte of
valid data. Therefore, (ValidLen+DataOffet)<=BufferLen.
Note that for receive buffer packets, the DataOffset field may be assigned
before there is any valid data in the packet buffer. This allows the application
to reserve space at the top of data buffer for private use. In all instances, the
8-8
EMAC_Pkt
DataOffset field must be valid for all packets handled by EMAC.
The data portion of the packet buffer represents a packet or a fragment of a
larger packet. This is determined by the Flags parameter. At the start of every
packet, the SOP bit is set in Flags. If the EOP bit is also set, then the packet
is not fragmented. Otherwise; the next packet structure pointed to by the pNext
field will contain the next fragment in the packet. On either type of buffer, when
the SOP bit is set in Flags, then the PktChannel, PktLength, and PktFrags
fields must also be valid. These fields contain additional information about the
packet.
The PktChannel field detetmines what channel the packet has arrived on, or
what channel it should be transmitted on. The EMAC library supports only a
single receive channel, but allows for up to eight transmit channels. Transmit
channels can be treated as round−robin or priority queues.
The PktLength field holds the size of the entire packet. On single frag packets
(both SOP and EOP set in BufFlags), PktLength and ValidLen will be equal.
The PktFrags field holds the number of fragments (EMAC_Pkt records) usedto
describe the packet. If more than 1 frag is present, the first recordmust have
EMAC_PKT_FLAGS_SOP flag set, with corresponding fields validated.Each
frag/record must be linked list using the pNext field, and the finalfrag/record
must have EMAC_PKT_FLAGS_EOP flag set and pNext=0.
In systems where the packet resides in cacheable memory, the data buffer
must start on a cache line boundary and be an even multiple of cache lines in
size. The EMAC_Pkt header must not appear in the same cache line as the
data portion of the packet. On multi-fragment packets, some packet fragments
may reside in cacheable memory where others do not.
Note: It is up to the caller to assure that all packet buffers residing in cacheable
memory are not currently stored in L1 or L2 cache when passed to any EMAC
function.
Some of the packet Flags can only be set if the device is in the proper
configuration to receive the corresponding frames. In order to enable these
flags, the following modes must be set:
RxCrc Flag : RXCRC Mode in EMAC_Config
RxErr Flags : PASSERROR Mode in EMAC_Config
RxCtl Flags : PASSCONTROL Mode in EMAC_Config
RxPrm Flag : EMAC_RXFILTER_ALL in EMAC_setReceiveFilter()
EMAC Module
8-9
EMAC_Status
EMAC_Status
Contains Information about the MAC’s run-time status
Members
uint
uint
uint
uint
uint
dioLinkStatus;
PhyDev;
RxPktHeld;
TxPktHeld;
FatalError;
/* csl_mdio Link status (see csl_mdio.h) */
/* Current PHY device in use (0−31) */
/* Number of packets held for Rx */
/* Number of packets held for Tx */
/* Fatal Error when non-zero */
Description
The status structure contains information about the MAC’s run-time status.
The following is a short description of the configuration fields:
- MdioLinkStatus
-
8-10
Current link status (non-zero on link) (see csl_mdio.h)
PhyDev
Current PHY device in use (0−31)
RxPktHeld
Current number of Rx packets held by the EMAC device
TxPktHeld
Current number of Tx packets held by the EMAC device
FatalError
Fatal Error Code
EMAC_Statistics
EMAC_Statistics
Members
Retreives the current count of various packet events in the system
Uint32 RxGoodFrames;
Uint32 RxBCastFrames;
Uint32 RxMCastFrames;
Uint32 RxPauseFrames;
Uint32 RxCRCErrors;
Uint32 RxAlignCodeErrors;
Uint32 RxOversized;
Uint32 RxJabber;
Uint32 RxUndersized;
Uint32 RxFragments;
Uint32 RxFiltered;
Uint32 RxQOSFiltered;
Uint32 RxOctets;
Uint32 TxGoodFrames;
Uint32 TxBCastFrames;
Uint32 TxMCastFrames;
Uint32 TxPauseFrames;
Uint32 TxDeferred;
Uint32 TxCollision;
Uint32 TxSingleColl;
Uint32 TxMultiColl;
Uint32 TxExcessiveColl;
Uint32 TxLateColl;
Uint32 TxUnderrun;
Uint32 TxCarrierSLoss;
Uint32 TxOctets;
Uint32 Frame64;
Uint32 Frame65t127;
Uint32 Frame128t255;
/* Good Frames Received */
/* Good Broadcast Frames Received */
/* Good Multicast Frames Received */
/* PauseRx Frames Received */
/* Frames Received with CRC Errors */
/* Frames Received with Alignment/Code
Errors */
/* Oversized Frames Received */
/* Jabber Frames Received */
/* Undersized Frames Received */
/* Rx Frame Fragments Received */
/* Rx Frames Filtered Based on Address */
/* Rx Frames Filtered Based on QoS
Filtering */
/* Total Received Bytes in Good Frames */
/* Good Frames Sent */
* Good Broadcast Frames Sent */
/* Good Multicast Frames Sent */
/* PauseTx Frames Sent */
/* Frames Where Transmission was
Deferred */
/* Total Frames Sent With Collision */
/* Frames Sent with Exactly One Collision*/
/* Frames Sent with Multiple Colisions */
/* Tx Frames Lost Due to Excessive
Collisions */
/* Tx Frames Lost Due to a Late Collision*/
/* Tx Frames Lost with Transmit Underrun
Error */
/* Tx Frames Lost Due to Carrier Sense
Loss */
/* Total Transmitted Bytes in Good
Frames*/
/* Total Tx&Rx with Octet Size of 64 */
/* Total Tx&Rx with Octet Size of 65 to
127 */
/* Total Tx&Rx with Octet Size of 128 to
EMAC Module
8-11
EMAC_Statistics
Uint32 Frame256t511;
Uint32 Frame512t1023;
Uint32 Frame1024tUp;
Uint32 NetOctets;
Uint32 RxSOFOverruns;
Uint32 RxMOFOverruns;
Uint32 RxDMAOverruns;
Description
255 */
/* Total Tx&Rx with Octet Size of 256 to
511 */
/* Total Tx&Rx with Octet Size of 512 to
1023 */
/* Total Tx&Rx with Octet Size of
>=1024 */
/* Sum of all Octets Tx or Rx on the
Network */
/* Total Rx Start of Frame Overruns */
/* Total Rx Middle of Frame Overruns */
/* Total Rx DMA Overruns */
The statistics structure is the used to retrieve the current count of various
packet events in the system. These values represent the delta values from the
last time the statistics were read.
Note: The application is charged with verifying that only one of the following
API calls may only be executing at a given time across all threads and all
interrupt functions.
8-12
EMAC_close
8.4 Functions
In the function descriptions, uint is defined as unsigned int and Handle as void*
EMAC_close
Closes the EMAC peripheral indicated by the supplied instance
handle
Function
uint EMAC_close(
Handle hEMAC
);
Arguments
Handle hEMAC
Return Value
uint
Description
When called, the EMAC device will shutdown both send and receive
operations, and free all pending transmit and receive packets. See
EMAC_open for more details.
The function returns zero on success, or an error code on failure.
Possible error codes include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
Handle hEMAC;
uint retStat;
...
retStat = EMAC_close(hEMAC);
EMAC_enumerate Enumerates the peripherals installed in the system and returns an
integer count
Function
uint EMAC_enumerate();
Arguments
None
Return Value
uint
Description
Enumerates the EMAC peripherals installed in the system and returns an
integer count. The EMAC devices are enumerated in a consistent fashion so
that each device can be later referenced by its physical index value ranging
from ”1” to ”n” where ”n” is the count returned by this function.
Example
uint numOfEmac;
...
numOfEmac = EMAC_enumerate();
EMAC Module
8-13
EMAC_getReceiveFilter
EMAC_getReceiveFilter Called to get the current packet filter setting for received
packets
Function
uint EMAC_getReceiveFilter(
Handle hEMAC,
uint *pReceiveFilter
);
Arguments
Handle hEMAC
uint *pReceiveFilter
Return Value
uint
Description
Called to get the current packet filter setting for received packets. The filter
values are the same as those used in EMAC_setReceiveFilter(). The current
filter value is written to the pointer supplied in pReceiveFilter. The function
returns zero on success, or an error code on failure.
Possible error code include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
8-14
Handle hEMAC;
uint *pReceiveFilter;
uint retStat;
...
retStat = EMAC_getReceiveFilter(hEMAC, pReceiveFilter);
EMAC_getStatistics
EMAC_getStatistics Called to get the current device statistics
Function
uint EMAC_getStatistics(
Handle hEMAC,
EMAC_Statistics *pStatistics
);
Arguments
Handle hEMAC
EMAC_Statistics *pStatistics
Return Value
uint
Description
Called to get the current device statistics. The statistics structure contains a
collection of event counts for various packet sent and receive properties.
Reading the statistics also clears the current statistic counters, so the values
read represent a delta from the last call. The statistics information is copied into
the structure pointed to by the pStatistics argument. The function returns zero
on success, or an error code on failure.
Possible error code include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
uint retVal;
Handle hEMAC;
EMAC_Statistics *pStatistics;
...
retVal = EMAC_getStatistics(hEMAC, pStatistics);
EMAC Module
8-15
EMAC_getStatus
EMAC_getStatus
Called to get the current device status
Function
uint EMAC_getStatus(
Handle hEMAC,
EMAC_Status *pStatus
);
Arguments
Handle hEMAC
EMAC_Status *pStatus
Return Value
uint
Description
Called to get the current status of the device. The device status is copied into
the supplied data structure. The function returns zero on success, or an error
code on failure.
Possible error code include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
8-16
uint retVal;
Handle hEMAC;
EMAC_Status *pStatus;
...
retVal = EMAC_getStatus(hEMAC, pStatus);
EMAC_open
EMAC_open
Opens the EMAC peripheral at the given physical index
Function
uint EMAC_open(
int physicalIndex,
Handle hApplication,
EMAC_Config *pEMACConfig,
Handle *phEMAC
);
Arguments
int physicalIndex
Handle hApplication
EMAC_Config *pEMACConfig
Handle *phEMAC
Return Value
uint
Description
Opens the EMAC peripheral at the given physical index and initializes it to an
embryonic state. The calling application must supply a operating configuration
that includes a callback function table. Data from this config structure is copied
into the device’s internal instance structure so the structure may be discarded
after EMAC_open() returns. In order to change an item in the configuration,
the the EMAC device must be closed and then re-opened with the new
configuration. The application layer may pass in an hApplication callback
handle, that will be supplied by the EMAC device when making calls to the
application callback functions. An EMAC device handle is written to phEMAC.
This handle must be saved by the caller and then passed to other EMAC
device functions.
The default receive filter prevents normal packets from being received until the
receive filter is specified by calling EMAC_receiveFilter(). A device reset is
achieved by calling EMAC_close() followed by EMAC_open(). The function
returns zero on success, or an error code on failure.
Possible error codes include:
EMAC_ERROR_ALREADY − The device is already open
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
uint retVal;
Handle hApplication;
EMAC_Config *pEMACConfig;
Handle *phEMAC;
...
retVal = EMAC_open(1, hApplication, pEMACConfig, phEMAC);
EMAC Module
8-17
EMAC_setReceiveFilter
EMAC_setReceiveFilter Called to set the packet filter for received packets
Function
uint EMAC_setReceiveFilter(
Handle hEMAC,
uint ReceiveFilter
);
Arguments
Handle hEMAC
uint ReceiveFilter
Return Value
uint
Description
Called to set the packet filter for received packets. The filtering level is
inclusive, so BROADCAST would include both BROADCAST and DIRECTED
(UNICAST) packets.
Available filtering modes include the following:
EMAC_RXFILTER_NOTHING − Receive nothing
EMAC_RXFILTER_DIRECT − Receive only Unicast to local MAC addr
EMAC_RXFILTER_BROADCAST − Receive direct and broadcast
EMAC_RXFILTER_MULTICAST − Receive above plus multicast in mcast list
EMAC_RXFILTER_ALLMULTICAST − Receive above plus all multicast
EMAC_RXFILTER_ALL − Receive all packets
Note that if error frames and control frames are desired, reception of these
must be specified in the device configuration.
Possible error code include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
8-18
uint retVal;
Handle hEMAC;
...
retVal = EMAC_setReceiveFilter(hEMAC, EMAC_RXFILTER_DIRECT);
EMAC_setMulticast
EMAC_setMulticast Called to install a list of multicast addresses for use in multicast
address filtering
Function
uint EMAC_setMulticast(
Handle hEMAC,
uint AddrCnt,
Uint8 *pMCastList
);
Arguments
Handle hEMAC
uint AddrCnt
Uint8 *pMCastList
Return Value
uint
Description
This function is called to install a list of multicast addresses for use in multicast
address filtering. Each time this function is called, any current multicast
configuration is discarded in favor of the new list. Therefore, a set with a list
size of zero removes all multicast addresses from the device.
Note that the multicast list configuration is stateless in that the list of multicast
addresses used to build the configuration is not retained. Therefore, it is
impossible to examine a list of currently installed addresses.
The addresses to install are pointed to by pMCastList. The length of this list
in bytes is 6 times the value of AddrCnt. When AddrCnt is zero, the pMCastList
parameter can be NULL.. The function returns zero on success, or an error
code on failure. The multicast list settings are not altered in the event of a
failure code.
Possible error code include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
uint retVal;
Handle hEMAC;
Uint8 *pMCastList;
...
retVal = EMAC_setMulticast(hEMAC, 0, NULL);
EMAC Module
8-19
EMAC_sendPacket
EMAC_sendPacket Sends a Ethernet data packet out the EMAC device
Function
uint EMAC_sendPacket(
Handle hEMAC,
EMAC_Pkt *pPacket
);
Arguments
Handle hEMAC
EMAC_Pkt *pPacket
Return Value
uint
Description
Sends a Ethernet data packet out the EMAC device. On a non-error return, the
EMAC device takes ownership of the packet. The packet is returned to the
application’s free pool once it has been transmitted.
The function returns zero on success, or an error code on failure. When an
error code is returned, the EMAC device has not taken ownership of the
packet.
Possible error codes include:
EMAC_ERROR_INVALID − A calling parameter is invalid
EMAC_ERROR_BADPACKET − The packet structure is invalid
Example
8-20
uint retVal;
Handle hEMAC;
EMAC_Pkt *pPacket;
...
retVal = EMAC_sendPacket(hEMAC, pPacket);
EMAC_serviceCheck
EMAC_serviceCheck Called every time there is an EMAC device interrupt
Function
uint EMAC_serviceCheck(
Handle hEMAC
);
Arguments
Handle hEMAC
Return Value
uint
Description
This function should be called every time there is an EMAC device interrupt.
It maintains the status the EMAC.
Note that the application has the responsibility for mapping the physical device
index to the correct EMAC_serviceCheck() function. If more than one EMAC
device is on the same interrupt, the function must be called for each device.
Possible error codes include:
EMAC_ERROR_INVALID − A calling parameter is invalid
EMAC_ERROR_MACFATAL − Fatal error in the MAC − Call EMAC_close()
Example
uint retVal;
Handle hEMAC;
...
retVal = EMAC_serviceCheck(hEMAC);
EMAC Module
8-21
EMAC_SUPPORT
EMAC_SUPPORT
Description
EMAC_timerTICK
Compile-time constant
Compile-time constant that has a value of 1 if the device supports the EMAC
module and 0 otherwise. You are not required to use this constant.
Called for each device in the system on a periodic basis of 100 ms
Function
uint EMAC_timerTick(
Handle hEMAC
);
Arguments
Handle hEMAC
Return Value
uint
Description
This function should be called for each device in the system on a periodic basis
of 100 mS (10 times a second). It is used to check the status of the EMAC and
MDIO device, and to potentially recover from low Rx buffer conditions. Strict
timing is not required, but the application should make a reasonable attempt
to adhere to the 100 mS mark. A missed call should not be ”made up” by
making mulitple sequential calls A ”polling” driver (one that calls
EMAC_serviceCheck() in a tight loop), must also adhere to the 100 mS timing
on this function.
Possible error codes include:
EMAC_ERROR_INVALID − A calling parameter is invalid
Example
8-22
uint retVal;
Handle hEMAC;
retVal = EMAC_timerTick(hEMAC);
Chapter 9
EMIF Module
This chapter describes the EMIF module, lists the API functions and macros
within the module, and provides an EMIF API reference section.
Note: This module has not been updated for C64x devices.
Topic
Page
9.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3
Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9-1
Overview
9.1 Overview
The EMIF module has a simple API for configuring the EMIF registers.
The EMIF may be configured by passing an EMIF_Config() structure to
EMIF_config() or by passing register values to the EMIF_configArgs()
function. To assist in creating register values, there are EMIF_MK (make)
macros that construct register values based on field values. In addition, there
are symbol constants that may be used for the field values.
Table 9−1 lists the configuration structure for use with the EMIF functions.
Table 9−2 lists the functions and constants available in the CSL EMIF module.
Table 9−1. EMIF Configuration Structure
Structure
Purpose
EMIF_Config
Structure used to set up the EMIF peripheral
See page ...
9-5
Table 9−2. EMIF APIs
Syntax
Type Description
See page ...
EMIF_config
F
Sets up the EMIF using the configuration structure
9-6
EMIF_configArgs
F
Sets up the EMIF using the register value arguments
9-6
EMIF_getConfig
F
Reads the current EMIF configuration values
9-8
EMIF_SUPPORT
C
A compile time constant that has a value of 1 if the
device supports the EMIF module
9-8
Note:
9-2
F = Function; C = Constant
Macros
9.2 Macros
There are two types of EMIF macros: those that access registers and fields,
and those that construct register and field values.
Table 9−3 lists the EMIF macros that access registers and fields, and
Table 9−4 lists the EMIF macros that construct register and field values. The
macros themselves are found in Chapter 28, Using the HAL Macros.
EMIF macros are not handle based.
Table 9−3. EMIF Macros that Access Registers and Fields
Macro
Description/Purpose
See page ...
EMIF_ADDR()
Register address
28-12
EMIF_RGET()
Returns the value in the peripheral register
28-18
EMIF_RSET(,x)
Register set
28-20
EMIF_FGET(,)
Returns the value of the specified field in the
peripheral register
28-13
EMIF_FSET(,,fieldval)
Writes fieldval to the specified field in the
peripheral register
28-15
EMIF_FSETS(,,)
Writes the symbol value to the specified field
in the peripheral
28-17
EMIF_RGETA(addr,)
Gets register for a given address
28-19
EMIF_RSETA(addr,,x)
Sets register for a given address
28-20
EMIF_FGETA(addr,,)
Gets field for a given address
28-13
EMIF_FSETA(addr,,,fieldval)
Sets field for a given address
28-16
EMIF_FSETSA(addr,,,) Sets field symbolically for a given address
EMIF Module
28-17
9-3
Macros
Table 9−4. EMIF Macros that Construct Register and Field Values
Macro
Description/Purpose
See page ...
EMIF__DEFAULT
Register default value
28-21
EMIF__RMK()
Register make
28-23
EMIF__OF()
Register value of ...
28-22
EMIF___DEFAULT
Field default value
28-24
EMIF_FMK()
Field make
28-14
EMIF_FMKS()
Field make symbolically
28-15
EMIF___OF()
Field value of ...
28-24
EMIF___
Field symbolic value
28-24
9-4
EMIF_Config
9.3 Configuration Structure
EMIF_Config
Structure used to set up EMIF peripheral
Structure
EMIF_Config
Members
Uint32 gblctl
EMIF global control register value
Uint32 cectl0
CE0 space control register value
Uint32 cectl1
CE1 space control register value
Uint32 cectl2
CE2 space control register value
Uint32 sdctl3
CE3 space control register value
Uint32 cectl
SDRAM control register value
Uint32 sdtim
SDRAM timing register value
Uint32 sdext
SDRAM extension register value
(for 6211/6711 only)
Description
This is the EMIF configuration structure used to set up the EMIF peripheral.
You create and initialize this structure and then pass its address to the
EMIF_config() function. You can use literal values or the EMIF_MK macros
to create the structure member values.
Example
EMIF_Config MyConfig = { /* example for 6211/6711 */
0x00003060, /* gblctl */
0x00000040, /* cectl0 */
0x404F0323, /* cectl1 */
0x00000030, /* cectl2 */
0x00000030, /* cectl3 */
0x72270000, /* sdctl */
0x00000410, /* sdtim */
0x00000000 /* sdext */
};
…
EMIF_config(&MyConfig);
EMIF Module
9-5
EMIF_config
9.4 Functions
EMIF_config
Sets up EMIF using configuration structure
Function
void EMIF_config(
EMIF_Config *config
);
Arguments
config
Return Value
none
Description
Sets up the EMIF using the configuration structure. The values of the structure
are written to the EMIF registers. See also EMIF_configArgs() and
EMIF_Config.
Example
EMIF_Config MyConfig = { /* example for 6211/6711 */
0x00003060, /* gblctl */
0x00000040, /* cectl0 */
0x404F0323, /* cectl1 */
0x00000030, /* cectl2 */
0x00000030, /* cectl3 */
0x72270000, /* sdctl */
0x00000410, /* sdtim */
0x00000000 /* sdext */
};
…
EMIF_config(&MyConfig);
EMIF_configArgs
Function
9-6
Pointer to an initialized configuration structure
Sets up EMIF using register value arguments
/* for 6211/6711 only*/
void EMIF_configArgs(
Uint32 gblctl,
Uint32 cectl0,
Uint32 cectl1,
Uint32 cectl2,
Uint32 cectl3,
Uint32 sdctl,
Uint32 sdtim,
Uint32 sdext
EMIF_configArgs
);
/* for all other devices*/
void EMIF_configArgs(
Uint32 gblctl,
Uint32 cectl0,
Uint32 cectl1,
Uint32 cectl2,
Uint32 cectl3,
Uint32 sdctl,
Uint32 sdtim
);
Arguments
gblctl
EMIF global control register value
cectl0
CE0 space control register value
cectl1
CE1 space control register value
cectl2
CE2 space control register value
cectl3
CE3 space control register value
sdctl
SDRAM control register value
sdtim
SDRAM timing register value
sdext
SDRAM extension register value
(optional − reserved for 6211/6711 only)
Return Value
none
Description
Sets up the EMIF using the register value arguments. The arguments are
written to the EMIF registers. See also EMIF_config().
Example
EMIF_configArgs(
0x00003060, /*
0x00000040, /*
0x404F0323, /*
0x00000030, /*
0x00000030, /*
0x72270000, /*
0x00000410 /*
);
/* devices other than 6211/6711 */
gblctl */
cectl0 */
cectl1 */
cectl2 */
cectl3 */
sdctl */
sdtim */
EMIF Module
9-7
EMIF_getConfig
EMIF_getConfig
Reads the current EMIF configuration values
Function
void EMIF_getConfig(
EMIF_Config *config
);
Arguments
config
Return Value
none
Description
Get EMIF current configuration value
Example
EMIF_config emifCfg;
EMIF_getConfig(&emifCfg);
EMIF_SUPPORT
Pointer to a configuration structure.
Compile time constant
Constant
EMIF_SUPPORT
Description
Compile time constant that has a value of 1 if the device supports the EMIF
module and 0 otherwise. You are not required to use this constant.
Currently, all devices support this module.
Example
9-8
#if (EMIF_SUPPORT)
/* user EMIF configuration /
#endif
Chapter 10
EMIFA/EMIFB Modules
This chapter describes the EMIFA and EMIFB modules, lists the API functions
and macros within the modules, and provides an API reference section.
Topic
Page
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10-1
Overview
10.1 Overview
The EMIFA and EMIFB modules have simple APIs for configuring the EMIFA
and EMIFB registers respectively.
The EMIFA and EMIFB may be configured by passing a configuration
structure to EMIFA_config() and EMIFB_config() or by passing register
values to the EMIFA_configArgs() and EMIFB_configArgs()
functions. To assist in creating register values, the EMIFA__RMK() and
EMIFB__RMK() (make) macros construct register values based on
field values. In addition, the symbol constants may be used for the field values.
Table 10−1 lists the configuration structure for use with the EMIFA/EMIFB
functions.
Table 10−2 lists the functions and constants available in the CSL
EMIFA/EMIFB modules.
Table 10−1. EMIFA/EMIFB Configuration Structure
Syntax
Type Description
EMIFA_Config
EMIFB_Config
S
Structure used to set up the EMIFA(B) peripheral
See page ...
10-5
Table 10−2. EMIFA/EMIFB APIs
Syntax
Type Description
See page ...
EMIFA_config
EMIFB_config
F
Sets up the EMIFA(B) using the configuration structure
10-7
EMIFA_configArgs
EMIFB_configArgs
F
Sets up the EMIFA(B) using the register value
arguments
10-9
EMIFA_getConfig
EMIFB_getConfig
F
Reads the current EMIFA(B) configuration values
10-11
EMIFA_SUPPORT
EMIFB_SUPPORT
C
A compile time constant that has a value of 1 if the
device supports the EMIFA and/or EMIFB modules
10-11
Note:
10-2
F = Function; C = Constant
Macros
10.2 Macros
There are two types of macros: those that access registers and fields, and
those that construct register and field values.
Table 10−3 lists the EMIFA and EMIFB macros that access registers and
fields, and Table 10−4 lists the EMIFA and EMIFB macros that construct
register and field values. The macros themselves are found in Chapter 28,
Using the HAL Macros.
EMIFA and EMIFB macros are not handle-based.
Table 10−3. EMIFA/EMIFB Macros that Access Registers and Fields
Macro
Description/Purpose
See page ...
EMIFA_ADDR()
EMIFB_ADDR()
Register address
28-12
EMIFA_RGET()
EMIFB_RGET()
Return the value in the peripheral register
28-18
EMIFA_RSET(,x)
EMIFB_RSET(,x)
Register set
28-20
EMIFA_FGET(,)
EMIFB_FGET(,)
Return the value of the specified field in the
peripheral register
28-13
EMIFA_FSET(,,fieldval)
EMIFB_FSET(,,fieldval)
Write fieldval to the specified field in the
peripheral register
28-13
EMIFA_FSETS(,,)
EMIFB_FSETS(,,)
Write the symbol value to the specified field in
the peripheral
28-17
EMIFA_RGETA(addr,)
EMIFB_RGETA(addr,)
Get register for a given address
28-19
EMIFA_RSETA(addr,,x)
EMIFB_RSETA(addr,,x)
Set register for a given address
28-20
EMIFA_FGETA(addr,,)
EMIFB_FGETA(addr,,)
Get field for a given address
28-13
EMIFA_FSETA(addr,,,x)
EMIFB_FSETA(addr,,,x)
Set field for a given address
28-16
EMIFA_FSETSA(addr,,,
)
EMIFB_FSETSA(addr,,,
)
Set field symbolically for a given address
28-12
EMIFA/EMIFB Modules
10-3
Macros
Table 10−4. EMIFA/EMIFB Macros that Construct Register and Field Values
Macro
Description/Purpose
See page ...
EMIFA__DEFAULT
EMIFB__DEFAULT
Register default value
28-21
EMIFA__RMK()
EMIFB__RMK()
Register make
28-23
EMIFA__OF()
EMIFB__OF()
Register value of ...
28-22
EMIFA___DEFAULT
EMIFB___DEFAULT
Field default value
28-24
EMIFA_FMK()
EMIFB_FMK()
Field make
28-14
EMIFA_FMKS()
EMIFB_FMKS()
Field make symbolically
28-15
EMIFA___OF()
EMIFB___OF()
Field value of ...
28-24
EMIFA___
EMIFB___
Field symbolic value
28-24
10-4
EMIFA_Config EMIFB_Config
10.3 Configuration Structure
EMIFA_Config
EMIFB_Config
Structures used to set up EMIFA and EMIFB peripherals
Structure
EMIFA_Config
EMIFB_Config
Members
Uint32 gblctl
Uint32 cectl0
Uint32 cectl1
Uint32 cectl2
Uint32 cectl3
Uint32 sdctl
Uint32 sdtim
Uint32 sdext
Uint32 cesec0
Uint32 cesec1
Uint32 cesec2
Uint32 cesec3
Description
These are the EMIFA and EMIFB configuration structures used to set up the
EMIFA and EMIFB peripherals, respectively. You create and initialize these
structures and then pass their addresses to the EMIFA_config() and
EMIFB_config() functions. You can use literal values or the
EMIFA__RMK and EMIFB__RMK macros to create the
structure member values.
EMIFA(B)global control register value
CE0 space control register value
CE1 space control register value
CE2 space control register value
CE3 space control register value
SDRAM control register value
SDRAM timing register value
SDRAM extension register value
CE0 space secondary control register value
CE1 space secondary control register value
CE2 space secondary control register value
CE3 space secondary control register value
EMIFA/B Modules
10-5
EMIFA_Config EMIFB_Config
Example
EMIFA_Config MyConfigA = {
0x00003060, /* gblctl */
0x00000040, /* cectl0 */
0x404F0323, /* cectl1 */
0x00000030, /* cectl2 */
0x00000030, /* cectl3 */
0x07117000, /* sdctl */
0x00000610, /* sdtim */
0x00000000, /* sdext */
0x00000000, /* cesec0 */
0x00000000, /* cesec1 */
0x00000000, /* cesec2 */
0x00000000 /* cesec3 */
};
EMIFB_Config MyConfigB = {
0x00003060, /* gblctl */
0x00000040, /* cectl0 */
0x404F0323, /* cectl1 */
0x00000030, /* cectl2 */
0x00000030, /* cectl3 */
0x07117000, /* sdctl */
0x00000610, /* sdtim */
0x00000000, /* sdext */
0x00000000, /* cesec0 */
0x00000000, /* cesec1 */
0x00000000, /* cesec2 */
0x00000000 /* cesec3 */
};
…
EMIFA_config(&MyConfigA);
EMIFB_config(&MyConfigB);
10-6
EMIFA_config EMIFB_config
10.4 Functions
EMIFA_config
EMIFB_config
Function
Sets up EMIFA and EMIFB using configuration structures
void EMIFA_config(
EMIFA_Config *config
);
void EMIFB_config(
EMIFB_Config *config
);
Arguments
config
Pointer to an initialized configuration structure
Return Value
none
Description
Sets up the EMIFA and/or EMIFB using the configuration respective
structures. The values of the structures are written to the EMIFA and EMIFB
registers respectively.
EMIFA/B Modules
10-7
EMIFA_config EMIFB_config
Example
EMIFA_Config MyConfigA = {
0x00003060, /* gblctl */
0x00000040, /* cectl0 */
0x404F0323, /* cectl1 */
0x00000030, /* cectl2 */
0x00000030, /* cectl3 */
0x07117000, /* sdctl */
0x00000610, /* sdtim */
0x00000000, /* sdext */
0x00000000, /* cesec0 */
0x00000000, /* cesec1 */
0x00000000, /* cesec2 */
0x00000000. /* cesec3 */
};
EMIFB_Config MyConfigB = {
0x00003060, /* gblctl */
0x00000040, /* cectl0 */
0x404F0323, /* cectl1 */
0x00000030, /* cectl2 */
0x00000030, /* cectl3 */
0x07117000, /* sdctl */
0x00000610, /* sdtim */
0x00000000, /* sdext */
0x00000000, /* cesec0 */
0x00000000, /* cesec1 */
0x00000000, /* cesec2 */
0x00000000 /* cesec3 */
};
…
EMIFA_config(&MyConfigA);
EMIFB_config(&MyConfigB);
10-8
EMIFA_configArgs EMIFB_configArgs
EMIFA_configArgs
EMIFB_configArgs Sets up EMIFA and EMIFB using register value arguments
Function
void EMIFA_configArgs(
Uint32 gblctl,
Uint32 cectl0,
Uint32 cectl1,
Uint32 cectl2,
Uint32 cectl3,
Uint32 sdctl,
Uint32 sdtim,
Uint32 sdext,
Uint32 cesec0,
Uint32 cesec1,
Uint32 cesec2,
Uint32 cesec3
);
void EMIFB_configArgs(
Uint32 gblctl,
Uint32 cectl0,
Uint32 cectl1,
Uint32 cectl2,
Uint32 cectl3,
Uint32 sdctl,
Uint32 sdtim,
Uint32 sdext,
Uint32 cesec0,
Uint32 cesec1,
Uint32 cesec2,
Uint32 cesec3
);
Arguments
gblctl
cectl0
cectl1
cectl2
cectl3
sdctl
sdtim
sdext
cesec0
cesec1
EMIFA(B) global control register value
CE0 space control register value
CE1 space control register value
CE2 space control register value
CE3 space control register value
SDRAM control register value
SDRAM timing register value
SDRAM extension register value
CE0 space secondary register value
CE1 space secondary register value
EMIFA/B Modules
10-9
EMIFA_configArgs EMIFB_configArgs
cesec2
cesec3
CE2 space secondary register value
CE3 space secondary register value
Return Value
none
Description
Set up the EMIFA and EMIFB using the register value arguments. The
arguments are written to the EMIFA and EMIFB registers respectively. See
also EMIFA_config(),EMIFB_config() functions.
Example
EMIFA_configArgs(
0x00003060, /* gblctl
0x00000040, /* cectl0
0x404F0323, /* cectl1
0x00000030, /* cectl2
0x00000030, /* cectl3
0x07117000, /* sdctl
0x00000610, /* sdtim
0x00000000, /* sdext
0x00000000, /* cesec0
0x00000000, /* cesec1
0x00000000, /* cesec2
0x00000000 /* cesec3
);
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
EMIFB_configArgs(
0x00003060, /* gblctl
0x00000040, /* cectl0
0x404F0323, /* cectl1
0x00000030, /* cectl2
0x00000030, /* cectl3
0x07117000, /* sdctl
0x00000610, /* sdtim
0x00000000, /* sdext
0x00000000, /* cesec0
0x00000000, /* cesec1
0x00000000, /* cesec2
0x00000000 /* cesec3
);
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
10-10
EMIFA_getConfig EMIFB_getConfig
EMIFA_getConfig
EMIFB_getConfig
Function
Reads the current EMIFA and EMIFB configuration values
void EMIFA_getConfig(
EMIFA_Config *config
);
void EMIFB_getConfig(
EMIFB_Config *config
);
Arguments
config
Pointer to a configuration structure.
Return Value
none
Description
Get EMIFA and EMIFB current configuration values.
Example
EMIFA_config emifCfgA;
EMIFB_config emifCfgB;
EMIFA_getConfig(&emifCfgA);
EMIFB_getConfig(&emifCfgB);
EMIFA_SUPPORT
EMIFB_SUPPORT Compile-time constants
Constant
EMIFA_SUPPORT
EMIFB_SUPPORT
Description
Compile time constants that have a value of 1 if the device supports the EMIFA
and EMIFB modules respectively, and 0 otherwise. You are not required to use
this constant.
Currently, all devices support this module.
Example
#if (EMIFA_SUPPORT)
/* user EMIFA configuration /
#endif
EMIFA/B Modules
10-11
Chapter 11
GPIO Module
This chapter describes the GPIO module, lists the GPIO functions and macros
within the module, and provides a GPIO API reference section.
Topic
Page
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11-1
Overview
11.1 Overview
For TMS320C64x devices, the GPIO peripheral provides 16 dedicated
general-purpose pins that can be configured as either inputs or outputs. Each
GPx pin configured as an input can directly trigger a CPU interrupt or a GPIO
event. The properties and functionalities of the GPx pins are covered by a set
of CSL APIs.
Table 11−1 lists the configuration structure for use with the GPIO functions.
Table 11−2 lists the functions and constants available in the CSL GPIO
module.
Table 11−1. GPIO Configuration Structure
Syntax
GPIO_Config
Type Description
S
The GPIO configuration structure used to set the GPIO
Global control register
See page ...
11-7
Table 11−2. GPIO APIs
(a) Primary GPIO Functions
Syntax
Type Description
See page ...
GPIO_close
F
Closes a GPIO port previously opened via
GPIO_open()
11-8
GPIO_config
F
Sets up the GPIO global control register using the
configuration structure
11-8
GPIO_configArgs
F
Sets up the GPIO global control register using the
register values passed in
11-9
GPIO_open
F
Opens a GPIO port for use
11-10
GPIO_reset
C
Resets the given GPIO channel
11-10
(b) Auxiliary GPIO Functions
Syntax
Type Description
See page ...
GPIO_clear
F
Clears the GPIO Delta registers
11-11
GPIO_deltaLowClear
F
Clears bits of given input pins in Delta Low register
11-11
GPIO_deltaLowGet
F
Indicates if a given input pin has undergone a
high-to-low transition. Returns 0 if the transition is not
detected.
11-12
11-2
Overview
Syntax
Type Description
See page ...
GPIO_deltaHighClear
F
Clears the bit of a given input pin in Delta High register
11-12
GPIO_deltaHighGet
F
Indicates if a given input pin has undergone a
low-to-high transition. Returns 0 if the transition is not
detected.
11-13
GPIO_getConfig
F
Reads the current GPIO configuration structure
11-13
GPIO_GPINTx
C
Constants dedicated to GPIO interrupt/event signals:
GPIO_GPINT0, GPIO_GPINT4, GPIO_GPINT5,
GPIO_GPINT6, GPIO_GPINT7
11-14
GPIO_intPolarity
F
Sets the polarity of the GPINTx interrupt/event signals
when configured in Pass Through mode
11-14
GPIO_maskLowClear
F
Clears the bits of given input pins in Mask Low register
11-15
GPIO_maskLowSet
F
Enables given pins to cause a CPU interrupt or EDMA
event based on corresponding GPxDL or inverted
GPxVAL by setting the associated mask bit.
11-15
GPIO_maskHighClear
F
Clears the bits of input pins in Mask High register
11-16
GPIO_maskHighSet
F
Enables given pins to cause a CPU interrupt or EGPIO
event based on corresponding GPxDH or GPxVAL by
setting the associated mask bit.
11-16
GPIO_pinDisable
F
Disables given pins under the Global Enable register
11-17
GPIO_pinDirection
F
Sets the direction of the given pins. Applies only if the
corresponding pins are enabled.
11-17
GPIO_pinEnable
F
Enables the given pins under the Global Enable register
11-18
GPIO_pinRead
F
Reads the detected values of pins configured as inputs
and the values to be driven on given output pins.
11-18
GPIO_pinWrite
F
Writes the values to be driven on given output pins.
11-19
GPIO_PINx
C
Constants dedicated to GPIO pins: GPIO_PIN0
–GPIO_PIN15.
11-19
GPIO_read
C
Reads data from a set of pins.
11-20
GPIO_SUPPORT
C
A compile time constant whose value is 1 if the device
supports the GPIO module.
11-20
GPIO_write
C
Writes the value to the specified set of GPIO pins.
11-20
Note:
F = Function; C = Constant
GPIO Module
11-3
Overview
11.1.1 Using GPIO
To use the GPIO pins, you must first allocate a device using GPIO_open(),
and then configure the Global Control register to determine the peripheral
mode by using the configuration structure to GPIO_config() or by passing
register value to the GPIO_configArgs() function. To assist in creating
register values, there are GPIO_