TMS570LC43x 16/32 RISC Flash Microcontroller Technical Reference Manual (Rev. A)
spnu563a_tech_reference_manual
User Manual:
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- Table of Contents
- Preface
- 1 Introduction
- 2 Architecture
- 2.1 Introduction
- 2.2 Memory Organization
- 2.3 Exceptions
- 2.4 Clocks
- 2.5 System and Peripheral Control Registers
- 2.5.1 Primary System Control Registers (SYS)
- 2.5.1.1 SYS Pin Control Register 1 (SYSPC1)
- 2.5.1.2 SYS Pin Control Register 2 (SYSPC2)
- 2.5.1.3 SYS Pin Control Register 3 (SYSPC3)
- 2.5.1.4 SYS Pin Control Register 4 (SYSPC4)
- 2.5.1.5 SYS Pin Control Register 5 (SYSPC5)
- 2.5.1.6 SYS Pin Control Register 6 (SYSPC6)
- 2.5.1.7 SYS Pin Control Register 7 (SYSPC7)
- 2.5.1.8 SYS Pin Control Register 8 (SYSPC8)
- 2.5.1.9 SYS Pin Control Register 9 (SYSPC9)
- 2.5.1.10 Clock Source Disable Register (CSDIS)
- 2.5.1.11 Clock Source Disable Set Register (CSDISSET)
- 2.5.1.12 Clock Source Disable Clear Register (CSDISCLR)
- 2.5.1.13 Clock Domain Disable Register (CDDIS)
- 2.5.1.14 Clock Domain Disable Set Register (CDDISSET)
- 2.5.1.15 Clock Domain Disable Clear Register (CDDISCLR)
- 2.5.1.16 GCLK1, HCLK, VCLK, and VCLK2 Source Register (GHVSRC)
- 2.5.1.17 Peripheral Asynchronous Clock Source Register (VCLKASRC)
- 2.5.1.18 RTI Clock Source Register (RCLKSRC)
- 2.5.1.19 Clock Source Valid Status Register (CSVSTAT)
- 2.5.1.20 Memory Self-Test Global Control Register (MSTGCR)
- 2.5.1.21 Memory Hardware Initialization Global Control Register (MINITGCR)
- 2.5.1.22 MBIST Controller/ Memory Initialization Enable Register (MSINENA)
- 2.5.1.23 MSTC Global Status Register (MSTCGSTAT)
- 2.5.1.24 Memory Hardware Initialization Status Register (MINISTAT)
- 2.5.1.25 PLL Control Register 1 (PLLCTL1)
- 2.5.1.26 PLL Control Register 2 (PLLCTL2)
- 2.5.1.27 SYS Pin Control Register 10 (SYSPC10)
- 2.5.1.28 Die Identification Register Lower Word (DIEIDL)
- 2.5.1.29 Die Identification Register Upper Word (DIEIDH)
- 2.5.1.30 LPO/Clock Monitor Control Register (LPOMONCTL)
- 2.5.1.31 Clock Test Register (CLKTEST)
- 2.5.1.32 DFT Control Register (DFTCTRLREG)
- 2.5.1.33 DFT Control Register 2 (DFTCTRLREG2)
- 2.5.1.34 General Purpose Register (GPREG1)
- 2.5.1.35 System Software Interrupt Request 1 Register (SSIR1)
- 2.5.1.36 System Software Interrupt Request 2 Register (SSIR2)
- 2.5.1.37 System Software Interrupt Request 3 Register (SSIR3)
- 2.5.1.38 System Software Interrupt Request 4 Register (SSIR4)
- 2.5.1.39 RAM Control Register (RAMGCR)
- 2.5.1.40 Bus Matrix Module Control Register 1 (BMMCR1)
- 2.5.1.41 CPU Reset Control Register (CPURSTCR)
- 2.5.1.42 Clock Control Register (CLKCNTL)
- 2.5.1.43 ECP Control Register (ECPCNTL)
- 2.5.1.44 DEV Parity Control Register 1 (DEVCR1)
- 2.5.1.45 System Exception Control Register (SYSECR)
- 2.5.1.46 System Exception Status Register (SYSESR)
- 2.5.1.47 System Test Abort Status Register (SYSTASR)
- 2.5.1.48 Global Status Register (GLBSTAT)
- 2.5.1.49 Device Identification Register (DEVID)
- 2.5.1.50 Software Interrupt Vector Register (SSIVEC)
- 2.5.1.51 System Software Interrupt Flag Register (SSIF)
- 2.5.2 Secondary System Control Registers (SYS2)
- 2.5.2.1 PLL Control Register 3 (PLLCTL3)
- 2.5.2.2 CPU Logic Bist Clock Divider (STCLKDIV)
- 2.5.2.3 ECP Control Register 1 (ECPCNTL1)
- 2.5.2.4 Clock 2 Control Register (CLK2CNTRL)
- 2.5.2.5 Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
- 2.5.2.6 HCLK Control Register (HCLKCNTL)
- 2.5.2.7 Clock Slip Control Register (CLKSLIP)
- 2.5.2.8 IP ECC Error Enable Register (IP1ECCERREN)
- 2.5.2.9 EFUSE Controller Control Register (EFC_CTLREG)
- 2.5.2.10 Die Identification Register Lower Word (DIEIDL_REG0)
- 2.5.2.11 Die Identification Register Upper Word (DIEIDH_REG1)
- 2.5.2.12 Die Identification Register Lower Word (DIEIDL_REG2)
- 2.5.2.13 Die Identification Register Upper Word (DIEIDH_REG3)
- 2.5.3 Peripheral Central Resource (PCR) Control Registers
- 2.5.3.1 Peripheral Memory Protection Set Register 0 (PMPROTSET0)
- 2.5.3.2 Peripheral Memory Protection Set Register 1 (PMPROTSET1)
- 2.5.3.3 Peripheral Memory Protection Clear Register 0 (PMPROTCLR0)
- 2.5.3.4 Peripheral Memory Protection Clear Register 1 (PMPROTCLR1)
- 2.5.3.5 Peripheral Protection Set Register 0 (PPROTSET0)
- 2.5.3.6 Peripheral Protection Set Register 1 (PPROTSET1)
- 2.5.3.7 Peripheral Protection Set Register 2 (PPROTSET2)
- 2.5.3.8 Peripheral Protection Set Register 3 (PPROTSET3)
- 2.5.3.9 Peripheral Protection Clear Register 0 (PPROTCLR0)
- 2.5.3.10 Peripheral Protection Clear Register 1 (PPROTCLR1)
- 2.5.3.11 Peripheral Protection Clear Register 2 (PPROTCLR2)
- 2.5.3.12 Peripheral Protection Clear Register 3 (PPROTCLR3)
- 2.5.3.13 Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0)
- 2.5.3.14 Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1)
- 2.5.3.15 Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0)
- 2.5.3.16 Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1)
- 2.5.3.17 Peripheral Power-Down Set Register 0 (PSPWRDWNSET0)
- 2.5.3.18 Peripheral Power-Down Set Register 1 (PSPWRDWNSET1)
- 2.5.3.19 Peripheral Power-Down Set Register 2 (PSPWRDWNSET2)
- 2.5.3.20 Peripheral Power-Down Set Register 3 (PSPWRDWNSET3)
- 2.5.3.21 Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0)
- 2.5.3.22 Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1)
- 2.5.3.23 Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2)
- 2.5.3.24 Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3)
- 2.5.3.25 Debug Frame Powerdown Set Register (PDPWRDWNSET)
- 2.5.3.26 Debug Frame Powerdown Clear Register (PDPWRDWNCLR)
- 2.5.3.27 MasterID Protection Write Enable Register (MSTIDWRENA)
- 2.5.3.28 MasterID Enable Register (MSTIDENA)
- 2.5.3.29 MasterID Diagnostic Control Register (MSTIDDIAGCTRL)
- 2.5.3.30 Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L)
- 2.5.3.31 Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H)
- 2.5.3.32 Peripheral Frame n MasterID Protection Register_L/H (PS[1-31]MSTID_L/H)
- 2.5.3.33 Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L)
- 2.5.3.34 Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H)
- 2.5.3.35 Privileged Peripheral Frame n MasterID Protection Register_L/H (PPS[1-7]MSTID_L/H)
- 2.5.3.36 Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L)
- 2.5.3.37 Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H)
- 2.5.3.38 Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSE[1-31]MSTID_L/H)
- 2.5.3.39 Peripheral Memory Frame MasterID Protection Register (PCS[0-31]MSTID)
- 2.5.3.40 Privileged Peripheral Memory Frame MasterID Protection Register (PPCS[0-7]MSTID)
- 2.5.1 Primary System Control Registers (SYS)
- 3 SCR Control Module (SCM)
- 3.1 Overview
- 3.2 Module Operation
- 3.3 How to Use SCM
- 3.4 SCM Registers
- 3.4.1 SCM REVID Register (SCMREVID)
- 3.4.2 SCM Control Register (SCMCNTRL)
- 3.4.3 SCM Compare Threshold Counter Register (SCMTHRESHOLD)
- 3.4.4 SCM Initiator Error0 Status Register (SCMIAERR0STAT)
- 3.4.5 SCM Initiator Error1 Status Register (SCMIAERR1STAT)
- 3.4.6 SCM Initiator Active Status Register (SCMIASTAT)
- 3.4.7 SCM Target Active Status Register (SCMTASTAT)
- 4 Interconnect
- 4.1 Overview
- 4.2 Peripheral Interconnect Subsystem
- 4.3 CPU Interconnect Subsystem
- 4.4 SDC MMR Registers
- 4.4.1 SDC Status Register (SDC_STATUS)
- 4.4.2 SDC Control Register (SDC_CONTROL)
- 4.4.3 Error Generic Parity Register (ERR_GENERIC_PARITY)
- 4.4.4 Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS)
- 4.4.5 Error Transaction ID Register (ERR_TRANS_ID)
- 4.4.6 Error Transaction Signature Register (ERR_TRANS_SIGNATURE)
- 4.4.7 Error Transaction Type Register (ERR_TRANS_TYPE)
- 4.4.8 Error User Parity Register (ERR_USER_PARITY)
- 4.4.9 Slave Error Unexpected Master ID Register (SERR_UNEXPECTED_MID)
- 4.4.10 Slave Error Address Decode Register (SERR_ADDR_DECODE)
- 4.4.11 Slave Error User Parity Register (SERR_USER_PARITY)
- 5 Power Management Module (PMM)
- 5.1 Overview
- 5.2 Power Domains
- 5.3 PMM Operation
- 5.4 PMM Registers
- 5.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0)
- 5.4.2 Logic Power Domain Control Register (LOGICPDPWRCTRL1)
- 5.4.3 Power Domain Clock Disable Register (PDCLKDISREG)
- 5.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG)
- 5.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)
- 5.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)
- 5.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)
- 5.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)
- 5.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)
- 5.4.10 Logic Power Domain PD6 Power Status Register (LOGICPDPWRSTAT4)
- 5.4.11 Global Control Register 1 (GLOBALCTRL1)
- 5.4.12 Global Status Register (GLOBALSTAT)
- 5.4.13 PSCON Diagnostic Compare Key Register (PRCKEYREG)
- 5.4.14 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)
- 5.4.15 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)
- 5.4.16 Isolation Diagnostic Status Register (ISODIAGSTAT)
- 6 I/O Multiplexing and Control Module (IOMM)
- 6.1 Overview
- 6.2 Main Features of I/O Multiplexing Module (IOMM)
- 6.3 Control of Multiplexed Outputs
- 6.4 Control of Multiplexed Inputs
- 6.5 Control of Special Multiplexed Options
- 6.5.1 Control of SDRAM Clock (EMIF_CLK)
- 6.5.2 Control for other EMIF Outputs
- 6.5.3 Control of Ethernet Controller Mode
- 6.5.4 Control of ADC Trigger Events
- 6.5.5 Control for ADC Event Trigger Signal Generation from ePWMx Modules
- 6.5.6 Control for Generating Interrupt Upon External Fault Indication to N2HETx
- 6.5.7 Control for Synchronizing Time Bases for All ePWMx Modules
- 6.5.8 Control for Synchronizing all ePWMx Modules to N2HET1 Module Time-Base
- 6.5.9 Control for Input Connections to ePWMx Modules
- 6.5.10 Control for Input Connections to eCAPx Modules
- 6.5.11 Control for Input Connections to eQEPx Modules
- 6.5.12 Selecting GIO Port for External DMA Request
- 6.5.13 Temperature Sensor Selection
- 6.6 Safety Features
- 6.7 IOMM Registers
- 6.7.1 REVISION_REG: Revision Register
- 6.7.2 BOOT_REG: Boot Mode Register
- 6.7.3 KICK_REG0: Kicker Register 0
- 6.7.4 KICK_REG1: Kicker Register 1
- 6.7.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register
- 6.7.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register
- 6.7.7 ERR_ENABLE_REG: Error Signaling Enable Register
- 6.7.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register
- 6.7.9 FAULT_ADDRESS_REG: Fault Address Register
- 6.7.10 FAULT_STATUS_REG: Fault Status Register
- 6.7.11 FAULT_CLEAR_REG: Fault Clear Register
- 6.7.12 PINMMRnn: Output Pin Multiplexing Control Registers
- 6.7.13 PINMMRnn: Input Pin Multiplexing Control Registers
- 6.7.14 PINMMRnn: Special Functionality Multiplexing Control Registers
- 7 F021 Level 2 Flash Module Controller (L2FMC)
- 7.1 Overview
- 7.2 Default Flash Configuration
- 7.3 EEPROM Emulation Support
- 7.4 SECDED
- 7.5 Memory Map
- 7.6 Power On, Power Off Considerations
- 7.7 Emulation and SIL3 Diagnostic Modes
- 7.8 Parameter Overlay Module (POM)
- 7.9 Summary of L2FMC Errors
- 7.10 Flash Control Registers
- 7.10.1 Flash Read Control Register (FRDCNTL)
- 7.10.2 Read Margin Control Register (FSPRD)
- 7.10.3 EEPROM Error Correction Control Register (EE_FEDACCTRL1)
- 7.10.4 Flash Port A Error and Status Register (FEDAC_PASTATUS)
- 7.10.5 Flash Port B Error and Status Register (FEDAC_PBSTATUS)
- 7.10.6 Flash Global Error and Status Register (FEDAC_GBLSTATUS)
- 7.10.7 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
- 7.10.8 Primary Address Tag Register (FPRIM_ADD_TAG)
- 7.10.9 Duplicate Address Tag Register (FDUP_ADD_TAG)
- 7.10.10 Flash Bank Protection Register (FBPROT)
- 7.10.11 Flash Bank Sector Enable Register (FBSE)
- 7.10.12 Flash Bank Busy Register (FBBUSY)
- 7.10.13 Flash Bank Access Control Register (FBAC)
- 7.10.14 Flash Bank Power Mode Register (FBPWRMODE)
- 7.10.15 Flash Bank/Pump Ready Register (FBPRDY)
- 7.10.16 Flash Pump Access Control Register 1 (FPAC1)
- 7.10.17 Flash Module Access Control Register (FMAC)
- 7.10.18 Flash Module Status Register (FMSTAT)
- 7.10.19 EEPROM Emulation Data MSW Register (FEMU_DMSW)
- 7.10.20 EEPROM Emulation Data LSW Register (FEMU_DLSW)
- 7.10.21 EEPROM Emulation ECC Register (FEMU_ECC)
- 7.10.22 Flash Lock Register (FLOCK)
- 7.10.23 Diagnostic Control Register (FDIAGCTRL)
- 7.10.24 Raw Address Register (FRAW_ADDR)
- 7.10.25 Parity Override Register (FPAR_OVR)
- 7.10.26 Reset Configuration Valid Register (RCR_VALID)
- 7.10.27 Crossbar Access Time Threshold Register (ACC_THRESHOLD)
- 7.10.28 Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2)
- 7.10.29 Lower Word of Reset Configuration Read Register (RCR_VALUE0)
- 7.10.30 Upper Word of Reset Configuration Read Register (RCR_VALUE1)
- 7.10.31 FSM Register Write Enable Register (FSM_WR_ENA)
- 7.10.32 EEPROM Emulation Configuration Register (EEPROM_CONFIG)
- 7.10.33 FSM Sector Register 1 (FSM_SECTOR1)
- 7.10.34 FSM Sector Register 2 (FSM_SECTOR2)
- 7.10.35 Flash Bank Configuration Register (FCFG_BANK)
- 7.11 POM Control Registers
- 8 Level 2 RAM (L2RAMW) Module
- 8.1 Overview
- 8.2 Module Operation
- 8.3 Control and Status Registers
- 8.3.1 L2RAMW Module Control Register (RAMCTRL)
- 8.3.2 L2RAMW Error Status Register (RAMERRSTATUS)
- 8.3.3 L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H)
- 8.3.4 L2RAMW Diagnostic Data Vector Low Register (DIAG_DATA_VECTOR_L)
- 8.3.5 L2RAMW Diagnostic ECC Vector Register (DIAG_ECC)
- 8.3.6 L2RAMW RAM Test Mode Control Register (RAMTEST)
- 8.3.7 L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT)
- 8.3.8 L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN)
- 8.3.9 L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0)
- 8.3.10 L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1)
- 9 Programmable Built-In Self-Test (PBIST) Module
- 9.1 Overview
- 9.2 RAM Grouping and Algorithm
- 9.3 PBIST Flow
- 9.4 Memory Test Algorithms on the On-chip ROM
- 9.5 PBIST Control Registers
- 9.5.1 RAM Configuration Register (RAMT)
- 9.5.2 Datalogger Register (DLR)
- 9.5.3 PBIST Activate/Clock Enable Register (PACT)
- 9.5.4 PBIST ID Register
- 9.5.5 Override Register (OVER)
- 9.5.6 Fail Status Fail Register (FSRF0)
- 9.5.7 Fail Status Count Registers (FSRC0 and FSRC1)
- 9.5.8 Fail Status Address Registers (FSRA0 and FSRA1)
- 9.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1)
- 9.5.10 ROM Mask Register (ROM)
- 9.5.11 ROM Algorithm Mask Register (ALGO)
- 9.5.12 RAM Info Mask Lower Register (RINFOL)
- 9.5.13 RAM Info Mask Upper Register (RINFOU)
- 9.6 PBIST Configuration Example
- 10 Self-Test Controller (STC) Module
- 10.1 General Description
- 10.2 STC Module Assignments
- 10.3 STC Programmers Flow
- 10.4 Application Self-Test Flow
- 10.5 STC1 Segment 0 (CPU) Test Coverage and Duration
- 10.6 STC1 Segment 1 (µSCU) Test Coverage and Duration
- 10.7 STC2 (nHET) Test Coverage and Duration
- 10.8 STC Control Registers
- 10.8.1 STC Global Control Register 0 (STCGCR0)
- 10.8.2 STC Global Control Register 1 (STCGCR1)
- 10.8.3 Self-Test Run Timeout Counter Preload Register (STCTPR)
- 10.8.4 STC Current ROM Address Register - CORE1 (STCCADDR1)
- 10.8.5 STC Current Interval Count Register (STCCICR)
- 10.8.6 Self-Test Global Status Register (STCGSTAT)
- 10.8.7 Self-Test Fail Status Register (STCFSTAT)
- 10.8.8 CORE1 Current MISR Registers (CORE1_CURMISR[3:0])
- 10.8.9 CORE2 Current MISR Registers (CORE2_CURMISR[3:0])
- 10.8.10 Signature Compare Self-Check Register (STCSCSCR)
- 10.8.11 STC Current ROM Address Register - CORE2 (STCCADDR2)
- 10.8.12 STC Clock Prescalar Register (STCCLKDIV)
- 10.8.13 Segment Interval Preload Register (STCSEGPLR)
- 10.9 STC Configuration Example
- 10.10 Self-Test Controller Diagnostics
- 11 System Memory Protection Unit (NMPU)
- 11.1 Overview
- 11.2 Module Operation
- 11.3 How to Use NMPU
- 11.4 NMPU Registers
- 11.4.1 MPU Revision ID Register (MPUREV)
- 11.4.2 MPU Lock Register (MPULOCK)
- 11.4.3 MPU Diagnostics Control Register (MPUDIAGCTRL)
- 11.4.4 MPU Diagnostic Address Register (MPUDIAGADDR)
- 11.4.5 MPU Error Status Register (MPUERRSTAT)
- 11.4.6 MPU Error Address Register (MPUERRADDR)
- 11.4.7 MPU Control Register 1 (MPUCTRL1)
- 11.4.8 MPU Control Register 2 (MPUCTRL2)
- 11.4.9 MPU Type Register (MPUTYPE)
- 11.4.10 MPU Region Base Address Register (MPUREGBASE)
- 11.4.11 MPU Region Size and Enable Register (MPUREGSENA)
- 11.4.12 MPU Region Access Control Register (MPUREGACR)
- 11.4.13 MPU Region Number Register (MPUREGNUM)
- 12 Error Profiling Controller (EPC)
- 12.1 Overview
- 12.2 Module Operation
- 12.3 How to Use EPC
- 12.4 EPC Control Registers
- 12.4.1 EPC REVID Register (EPCREVID)
- 12.4.2 EPC Control Register (EPCCNTRL)
- 12.4.3 Uncorrectable Error Status Register (UERRSTAT)
- 12.4.4 EPC Error Status Register (EPCERRSTAT)
- 12.4.5 FIFO Full Status Register (FIFOFULLSTAT)
- 12.4.6 IP Interface FIFO Overflow Status Register (OVRFLWSTAT)
- 12.4.7 CAM Index Available Status Register (CAMAVAILSTAT)
- 12.4.8 Uncorrectable Error Address Register n (UERR_ADDR)
- 12.4.9 CAM Content Update Register n (CAM_CONTENT)
- 12.4.10 CAM Index Registers (CAM_INDEX[0-7])
- 13 CPU Compare Module for Cortex-R5F (CCM-R5F)
- 13.1 Overview
- 13.2 Module Operation
- 13.3 Control Registers
- 13.3.1 CCM-R5F Status Register 1 (CCMSR1)
- 13.3.2 CCM-R5F Key Register 1 (CCMKEYR1)
- 13.3.3 CCM-R5F Status Register 2 (CCMSR2)
- 13.3.4 CCM-R5F Key Register 2 (CCMKEYR2)
- 13.3.5 CCM-R5F Status Register 3 (CCMSR3)
- 13.3.6 CCM-R5F Key Register 3 (CCMKEYR3)
- 13.3.7 CCM-R5F Polarity Control Register (CCMPOLCNTRL)
- 13.3.8 CCM-R5F Status Register 4 (CCMSR4)
- 13.3.9 CCM-R5F Key Register 4 (CCMKEYR4)
- 13.3.10 CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0)
- 14 Oscillator and PLL
- 14.1 Introduction
- 14.2 Quick Start
- 14.3 Oscillator
- 14.4 Low Power Oscillator and Clock Detect (LPOCLKDET)
- 14.5 PLL
- 14.6 PLL Control Registers
- 14.7 Phase-Locked Loop Theory of Operation
- 14.8 Programming Example
- 15 Dual-Clock Comparator (DCC) Module
- 15.1 Introduction
- 15.2 Module Operation
- 15.3 Clock Source Selection for Counter0 and Counter1
- 15.4 DCC Control Registers
- 15.4.1 DCC Global Control Register (DCCGCTRL)
- 15.4.2 DCC Revision Id Register (DCCREV)
- 15.4.3 DCC Counter0 Seed Register (DCCCNT0SEED)
- 15.4.4 DCC Valid0 Seed Register (DCCVALID0SEED)
- 15.4.5 DCC Counter1 Seed Register (DCCCNT1SEED)
- 15.4.6 DCC Status Register (DCCSTAT)
- 15.4.7 DCC Counter0 Value Register (DCCCNT0)
- 15.4.8 DCC Valid0 Value Register (DCCVALID0)
- 15.4.9 DCC Counter1 Value Register (DCCCNT1)
- 15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC)
- 15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
- 16 Error Signaling Module (ESM)
- 16.1 Overview
- 16.2 Module Operation
- 16.3 Recommended Programming Procedure
- 16.4 ESM Control Registers
- 16.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
- 16.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
- 16.4.3 ESM Interrupt Enable Set/Status Register 1 (ESMIESR1)
- 16.4.4 ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1)
- 16.4.5 ESM Interrupt Level Set/Status Register 1 (ESMILSR1)
- 16.4.6 ESM Interrupt Level Clear/Status Register 1 (ESMILCR1)
- 16.4.7 ESM Status Register 1 (ESMSR1)
- 16.4.8 ESM Status Register 2 (ESMSR2)
- 16.4.9 ESM Status Register 3 (ESMSR3)
- 16.4.10 ESM ERROR Pin Status Register (ESMEPSR)
- 16.4.11 ESM Interrupt Offset High Register (ESMIOFFHR)
- 16.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR)
- 16.4.13 ESM Low-Time Counter Register (ESMLTCR)
- 16.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)
- 16.4.15 ESM Error Key Register (ESMEKR)
- 16.4.16 ESM Status Shadow Register 2 (ESMSSR2)
- 16.4.17 ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4)
- 16.4.18 ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4)
- 16.4.19 ESM Interrupt Enable Set/Status Register 4 (ESMIESR4)
- 16.4.20 ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4)
- 16.4.21 ESM Interrupt Level Set/Status Register 4 (ESMILSR4)
- 16.4.22 ESM Interrupt Level Clear/Status Register 4 (ESMILCR4)
- 16.4.23 ESM Status Register 4 (ESMSR4)
- 16.4.24 ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7)
- 16.4.25 ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7)
- 16.4.26 ESM Interrupt Enable Set/Status Register 7 (ESMIESR7)
- 16.4.27 ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7)
- 16.4.28 ESM Interrupt Level Set/Status Register 7 (ESMILSR7)
- 16.4.29 ESM Interrupt Level Clear/Status Register 7 (ESMILCR7)
- 16.4.30 ESM Status Register 7 (ESMSR7)
- 17 Real-Time Interrupt (RTI) Module
- 17.1 Overview
- 17.2 Module Operation
- 17.3 RTI Control Registers
- 17.3.1 RTI Global Control Register (RTIGCTRL)
- 17.3.2 RTI Timebase Control Register (RTITBCTRL)
- 17.3.3 RTI Capture Control Register (RTICAPCTRL)
- 17.3.4 RTI Compare Control Register (RTICOMPCTRL)
- 17.3.5 RTI Free Running Counter 0 Register (RTIFRC0)
- 17.3.6 RTI Up Counter 0 Register (RTIUC0)
- 17.3.7 RTI Compare Up Counter 0 Register (RTICPUC0)
- 17.3.8 RTI Capture Free Running Counter 0 Register (RTICAFRC0)
- 17.3.9 RTI Capture Up Counter 0 Register (RTICAUC0)
- 17.3.10 RTI Free Running Counter 1 Register (RTIFRC1)
- 17.3.11 RTI Up Counter 1 Register (RTIUC1)
- 17.3.12 RTI Compare Up Counter 1 Register (RTICPUC1)
- 17.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1)
- 17.3.14 RTI Capture Up Counter 1 Register (RTICAUC1)
- 17.3.15 RTI Compare 0 Register (RTICOMP0)
- 17.3.16 RTI Update Compare 0 Register (RTIUDCP0)
- 17.3.17 RTI Compare 1 Register (RTICOMP1)
- 17.3.18 RTI Update Compare 1 Register (RTIUDCP1)
- 17.3.19 RTI Compare 2 Register (RTICOMP2)
- 17.3.20 RTI Update Compare 2 Register (RTIUDCP2)
- 17.3.21 RTI Compare 3 Register (RTICOMP3)
- 17.3.22 RTI Update Compare 3 Register (RTIUDCP3)
- 17.3.23 RTI Timebase Low Compare Register (RTITBLCOMP)
- 17.3.24 RTI Timebase High Compare Register (RTITBHCOMP)
- 17.3.25 RTI Set Interrupt Enable Register (RTISETINTENA)
- 17.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA)
- 17.3.27 RTI Interrupt Flag Register (RTIINTFLAG)
- 17.3.28 Digital Watchdog Control Register (RTIDWDCTRL)
- 17.3.29 Digital Watchdog Preload Register (RTIDWDPRLD)
- 17.3.30 Watchdog Status Register (RTIWDSTATUS)
- 17.3.31 RTI Watchdog Key Register (RTIWDKEY)
- 17.3.32 RTI Digital Watchdog Down Counter (RTIDWDCNTR)
- 17.3.33 Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL)
- 17.3.34 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)
- 17.3.35 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)
- 17.3.36 RTI Compare 0 Clear Register (RTICMP0CLR)
- 17.3.37 RTI Compare 1 Clear Register (RTICMP1CLR)
- 17.3.38 RTI Compare 2 Clear Register (RTICMP2CLR)
- 17.3.39 RTI Compare 3 Clear Register (RTICMP3CLR)
- 18 Cyclic Redundancy Check (CRC) Controller Module
- 18.1 Overview
- 18.2 Module Operation
- 18.2.1 General Operation
- 18.2.2 CRC Modes of Operation
- 18.2.3 PSA Signature Register
- 18.2.4 PSA Sector Signature Register
- 18.2.5 CRC Value Register
- 18.2.6 Raw Data Register
- 18.2.7 Example DMA Controller Setup
- 18.2.8 Pattern Count Register
- 18.2.9 Sector Count Register/Current Sector Register
- 18.2.10 Interrupt
- 18.2.11 Power Down Mode
- 18.2.12 Emulation
- 18.2.13 Peripheral Bus Interface
- 18.3 Example
- 18.4 CRC Control Registers
- 18.4.1 CRC Global Control Register 0 (CRC_CTRL0)
- 18.4.2 CRC Global Control Register (CRC_CTRL1)
- 18.4.3 CRC Global Control Register 2 (CRC_CTRL2)
- 18.4.4 CRC Interrupt Enable Set Register (CRC_INTS)
- 18.4.5 CRC Interrupt Enable Reset Register (CRC_INTR)
- 18.4.6 CRC Interrupt Status Register (CRC_STATUS)
- 18.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG)
- 18.4.8 CRC Busy Register (CRC_BUSY)
- 18.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)
- 18.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1)
- 18.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1)
- 18.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)
- 18.4.13 CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1)
- 18.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1)
- 18.4.15 Channel 1 PSA Signature High Register (PSA_SIGREGH1)
- 18.4.16 Channel 1 CRC Value Low Register (CRC_REGL1)
- 18.4.17 Channel 1 CRC Value High Register (CRC_REGH1)
- 18.4.18 Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1)
- 18.4.19 Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)
- 18.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1)
- 18.4.21 Channel 1 Raw Data High Register (RAW_DATAREGH1)
- 18.4.22 CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2)
- 18.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2)
- 18.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2)
- 18.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
- 18.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
- 18.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2)
- 18.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2)
- 18.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)
- 18.4.30 Channel 2 CRC Value High Register (CRC_REGH2)
- 18.4.31 Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2)
- 18.4.32 Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)
- 18.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)
- 18.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2)
- 19 Vectored Interrupt Manager (VIM) Module
- 19.1 Overview
- 19.2 Dual VIM for Safety
- 19.3 Device Level Interrupt Management
- 19.4 Interrupt Handling Inside VIM
- 19.5 Interrupt Vector Table (VIM RAM)
- 19.6 VIM Wakeup Interrupt
- 19.7 Capture Event Sources
- 19.8 Examples
- 19.9 VIM Control Registers
- 19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT)
- 19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL)
- 19.9.3 Uncorrectable Error Address Register (UERRADDR)
- 19.9.4 Fallback Vector Address Register (FBVECADDR)
- 19.9.5 Single-Bit Error Address Register (SBERRADDR)
- 19.9.6 VIM Offset Vector Registers
- 19.9.7 IRQ Index Offset Vector Register (IRQINDEX)
- 19.9.8 FIQ Index Offset Vector Registers (FIQINDEX)
- 19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3])
- 19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3])
- 19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])
- 19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3])
- 19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])
- 19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3])
- 19.9.15 IRQ Interrupt Vector Register (IRQVECREG)
- 19.9.16 FIQ Interrupt Vector Register (FIQVECREG)
- 19.9.17 Capture Event Register (CAPEVT)
- 19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31])
- 20 Direct Memory Access Controller (DMA) Module
- 20.1 Overview
- 20.2 Module Operation
- 20.2.1 Memory Space
- 20.2.2 DMA Data Access
- 20.2.3 Addressing Modes
- 20.2.4 DMA Channel Control Packets
- 20.2.5 Priority Queue
- 20.2.6 Data Packing and Unpacking
- 20.2.7 DMA Request
- 20.2.8 Auto-Initiation
- 20.2.9 Interrupts
- 20.2.10 Debugging
- 20.2.11 Power Management
- 20.2.12 FIFO Buffer
- 20.2.13 Channel Chaining
- 20.2.14 Request Polarity
- 20.2.15 Memory Protection
- 20.2.16 ECC Checking
- 20.2.17 ECC Testing
- 20.2.18 Initializing RAM with ECC
- 20.2.19 Transaction Errors
- 20.3 Control Registers and Control Packets
- 20.3.1 Global Configuration Registers
- 20.3.1.1 Global Control Register (GCTRL)
- 20.3.1.2 Channel Pending Register (PEND)
- 20.3.1.3 DMA Status Register (DMASTAT)
- 20.3.1.4 DMA Revision ID Register (DMAREVID)
- 20.3.1.5 HW Channel Enable Set and Status Register (HWCHENAS)
- 20.3.1.6 HW Channel Enable Reset and Status Register (HWCHENAR)
- 20.3.1.7 SW Channel Enable Set and Status Register (SWCHENAS)
- 20.3.1.8 SW Channel Enable Reset and Status Register (SWCHENAR)
- 20.3.1.9 Channel Priority Set Register (CHPRIOS)
- 20.3.1.10 Channel Priority Reset Register (CHPRIOR)
- 20.3.1.11 Global Channel Interrupt Enable Set Register (GCHIENAS)
- 20.3.1.12 Global Channel Interrupt Enable Reset Register (GCHIENAR)
- 20.3.1.13 DMA Request Assignment Register 0 (DREQASI0)
- 20.3.1.14 DMA Request Assignment Register 1 (DREQASI1)
- 20.3.1.15 DMA Request Assignment Register 2 (DREQASI2)
- 20.3.1.16 DMA Request Assignment Register 3 (DREQASI3)
- 20.3.1.17 DMA Request Assignment Register 4 (DREQASI4)
- 20.3.1.18 DMA Request Assignment Register 5 (DREQASI5)
- 20.3.1.19 DMA Request Assignment Register 6 (DREQASI6)
- 20.3.1.20 DMA Request Assignment Register 7 (DREQASI7)
- 20.3.1.21 Port Assignment Register 0 (PAR0)
- 20.3.1.22 Port Assignment Register 1 (PAR1)
- 20.3.1.23 Port Assignment Register 2 (PAR2)
- 20.3.1.24 Port Assignment Register 3 (PAR3)
- 20.3.1.25 FTC Interrupt Mapping Register (FTCMAP)
- 20.3.1.26 LFS Interrupt Mapping Register (LFSMAP)
- 20.3.1.27 HBC Interrupt Mapping Register (HBCMAP)
- 20.3.1.28 BTC Interrupt Mapping Register (BTCMAP)
- 20.3.1.29 FTC Interrupt Enable Set Register (FTCINTENAS)
- 20.3.1.30 FTC Interrupt Enable Reset Register (FTCINTENAR)
- 20.3.1.31 LFS Interrupt Enable Set Register (LFSINTENAS)
- 20.3.1.32 LFS Interrupt Enable Reset Register (LFSINTENAR)
- 20.3.1.33 HBC Interrupt Enable Set Register (HBCINTENAS)
- 20.3.1.34 HBC Interrupt Enable Reset Register (HBCINTENAR)
- 20.3.1.35 BTC Interrupt Enable Set Register (BTCINTENAS)
- 20.3.1.36 BTC Interrupt Enable Reset Register (BTCINTENAR)
- 20.3.1.37 Global Interrupt Flag Register (GINTFLAG)
- 20.3.1.38 FTC Interrupt Flag Register (FTCFLAG)
- 20.3.1.39 LFS Interrupt Flag Register (LFSFLAG)
- 20.3.1.40 HBC Interrupt Flag Register (HBCFLAG)
- 20.3.1.41 BTC Interrupt Flag Register (BTCFLAG)
- 20.3.1.42 BER Interrupt Flag Register (BERFLAG)
- 20.3.1.43 FTCA Interrupt Channel Offset Register (FTCAOFFSET)
- 20.3.1.44 LFSA Interrupt Channel Offset Register (LFSAOFFSET)
- 20.3.1.45 HBCA Interrupt Channel Offset Register (HBCAOFFSET)
- 20.3.1.46 BTCA Interrupt Channel Offset Register (BTCAOFFSET)
- 20.3.1.47 FTCB Interrupt Channel Offset Register (FTCBOFFSET)
- 20.3.1.48 LFSB Interrupt Channel Offset Register (LFSBOFFSET)
- 20.3.1.49 HBCB Interrupt Channel Offset Register (HBCBOFFSET)
- 20.3.1.50 BTCB Interrupt Channel Offset Register (BTCBOFFSET)
- 20.3.1.51 Port Control Register (PTCRL)
- 20.3.1.52 RAM Test Control Register (RTCTRL)
- 20.3.1.53 Debug Control Register (DCTRL)
- 20.3.1.54 Watch Point Register (WPR)
- 20.3.1.55 Watch Mask Register (WMR)
- 20.3.1.56 FIFO A Active Channel Source Address Register (FAACSADDR)
- 20.3.1.57 FIFO A Active Channel Destination Address Register (FAACDADDR)
- 20.3.1.58 FIFO A Active Channel Transfer Count Register (FAACTC)
- 20.3.1.59 FIFO B Active Channel Source Address Register (FBACSADDR)
- 20.3.1.60 FIFO B Active Channel Destination Address Register (FBACDADDR)
- 20.3.1.61 FIFO B Active Channel Transfer Count Register (FBACTC)
- 20.3.1.62 ECC Control Register (DMAPECR)
- 20.3.1.63 DMA ECC Error Address Register (DMAPAR)
- 20.3.1.64 DMA Memory Protection Control Register 1 (DMAMPCTRL1)
- 20.3.1.65 DMA Memory Protection Status Register 1 (DMAMPST1)
- 20.3.1.66 DMA Memory Protection Region 0 Start Address Register (DMAMPR0S)
- 20.3.1.67 DMA Memory Protection Region 0 End Address Register (DMAMPR0E)
- 20.3.1.68 DMA Memory Protection Region 1 Start Address Register (DMAMPR1S)
- 20.3.1.69 DMA Memory Protection Region 1 End Address Register (DMAMPR1E)
- 20.3.1.70 DMA Memory Protection Region 2 Start Address Register (DMAMPR2S)
- 20.3.1.71 DMA Memory Protection Region 2 End Address Register (DMAMPR2E)
- 20.3.1.72 DMA Memory Protection Region 3 Start Address Register (DMAMPR3S)
- 20.3.1.73 DMA Memory Protection Region 3 End Address Register (DMAMPR3E)
- 20.3.1.74 DMA Memory Protection Control Register 2 (DMAMPCTRL2)
- 20.3.1.75 DMA Memory Protection Status Register 2 (DMAMPST2)
- 20.3.1.76 DMA Memory Protection Region 4 Start Address Register (DMAMPR4S)
- 20.3.1.77 DMA Memory Protection Region 4 End Address Register (DMAMPR4E)
- 20.3.1.78 DMA Memory Protection Region 5 Start Address Register (DMAMPR5S)
- 20.3.1.79 DMA Memory Protection Region 5 End Address Register (DMAMPR5E)
- 20.3.1.80 DMA Memory Protection Region 6 Start Address Register (DMAMPR6S)
- 20.3.1.81 DMA Memory Protection Region 6 End Address Register (DMAMPR6E)
- 20.3.1.82 DMA Memory Protection Region 7 Start Address Register (DMAMPR7S)
- 20.3.1.83 DMA Memory Protection Region 7 End Address Register (DMAMPR7E)
- 20.3.1.84 DMA Single-Bit ECC Control Register (DMASECCCTRL)
- 20.3.1.85 DMA ECC Single-Bit Error Address Register (DMAECCSBE)
- 20.3.1.86 FIFO A Status Register (FIFOASTAT)
- 20.3.1.87 FIFO B Status Register (FIFOBSTAT)
- 20.3.1.88 DMA Request Polarity Select Register 1 (DMAREQPS1)
- 20.3.1.89 DMA Request Polarity Select Register 0 (DMAREQPS0)
- 20.3.1.90 Transaction Parity Error Event Control Register (TERECTRL)
- 20.3.1.91 TER Event Flag Register (TERFLAG)
- 20.3.1.92 TER Event Channel Offset Register (TERROFFSET)
- 20.3.2 Channel Configuration
- 20.3.2.1 Initial Source Address Register (ISADDR)
- 20.3.2.2 Initial Destination Address Register (IDADDR)
- 20.3.2.3 Initial Transfer Count Register (ITCOUNT)
- 20.3.2.4 Channel Control Register (CHCTRL)
- 20.3.2.5 Element Index Offset Register (EIOFF)
- 20.3.2.6 Frame Index Offset Register (FIOFF)
- 20.3.2.7 Current Source Address Register (CSADDR)
- 20.3.2.8 Current Destination Address Register (CDADDR)
- 20.3.2.9 Current Transfer Count Register (CTCOUNT)
- 20.3.1 Global Configuration Registers
- 21 External Memory Interface (EMIF)
- 21.1 Introduction
- 21.2 EMIF Module Architecture
- 21.2.1 EMIF Clock Control
- 21.2.2 EMIF Requests
- 21.2.3 EMIF Signal Descriptions
- 21.2.4 EMIF Signal Multiplexing Control
- 21.2.5 SDRAM Controller and Interface
- 21.2.5.1 SDRAM Commands
- 21.2.5.2 Interfacing to SDRAM
- 21.2.5.3 SDRAM Configuration Registers
- 21.2.5.4 SDRAM Auto-Initialization Sequence
- 21.2.5.5 SDRAM Configuration Procedure
- 21.2.5.6 EMIF Refresh Controller
- 21.2.5.7 Self-Refresh Mode
- 21.2.5.8 Power Down Mode
- 21.2.5.9 SDRAM Read Operation
- 21.2.5.10 SDRAM Write Operations
- 21.2.5.11 Mapping from Logical Address to EMIF Pins
- 21.2.6 Asynchronous Controller and Interface
- 21.2.6.1 Interfacing to Asynchronous Memory
- 21.2.6.2 Accessing Larger Asynchronous Memories
- 21.2.6.3 Configuring the EMIF for Asynchronous Accesses
- 21.2.6.4 Read and Write Operations in Normal Mode
- 21.2.6.5 Read and Write Operation in Select Strobe Mode
- 21.2.6.6 Extended Wait Mode and the EMIF_nWAIT Pin
- 21.2.6.7 NOR Flash Page Mode
- 21.2.7 Data Bus Parking
- 21.2.8 Reset and Initialization Considerations
- 21.2.9 Interrupt Support
- 21.2.10 DMA Event Support
- 21.2.11 EMIF Signal Multiplexing
- 21.2.12 Memory Map
- 21.2.13 Priority and Arbitration
- 21.2.14 System Considerations
- 21.2.15 Power Management
- 21.2.16 Emulation Considerations
- 21.3 EMIF Registers
- 21.3.1 Module ID Register (MIDR)
- 21.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)
- 21.3.3 SDRAM Configuration Register (SDCR)
- 21.3.4 SDRAM Refresh Control Register (SDRCR)
- 21.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG)
- 21.3.6 SDRAM Timing Register (SDTIMR)
- 21.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR)
- 21.3.8 EMIF Interrupt Raw Register (INTRAW)
- 21.3.9 EMIF Interrupt Masked Register (INTMSK)
- 21.3.10 EMIF Interrupt Mask Set Register (INTMSKSET)
- 21.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR)
- 21.3.12 Page Mode Control Register (PMCR)
- 21.4 Example Configuration
- 21.4.1 Hardware Interface
- 21.4.2 Software Configuration
- 21.4.2.1 Configuring the SDRAM Interface
- 21.4.2.1.1 PLL Programming for the EMIF to K4S641632H-TC(L)70 Interface
- 21.4.2.1.2 SDRAM Timing Register (SDTIMR) Settings for the EMIF to K4S641632H-TC(L)70 Interface
- 21.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDSRETR) Settings for the EMIF to K4S641632H-TC(L)70 Interface
- 21.4.2.1.4 SDRAM Refresh Control Register (SDRCR) Settings for the EMIF to K4S641632H-TC(L)70 Interface
- 21.4.2.1.5 SDRAM Configuration Register (SDCR) Settings for the EMIF to K4S641632H-TC(L)70 Interface
- 21.4.2.2 Configuring the Flash Interface
- 21.4.2.1 Configuring the SDRAM Interface
- 22 Analog To Digital Converter (ADC) Module
- 22.1 Overview
- 22.2 Basic Operation
- 22.2.1 Basic Features and Usage of the ADC
- 22.2.1.1 How to Select Between 12-bit and 10-bit Resolutions
- 22.2.1.2 How to Set Up the ADCLK Speed
- 22.2.1.3 How to Set Up the Input Channel Acquisition Time
- 22.2.1.4 How to Select an Input Channel for Conversion
- 22.2.1.5 How to Select Between Single Conversion Sequence or Continuous Conversions
- 22.2.1.6 How to Start a Conversion
- 22.2.1.7 How to Know When the Group Conversion is Completed
- 22.2.1.8 How Results are Stored in the Results’ Memory
- 22.2.1.9 How to Read the Results from the Results’ Memory
- 22.2.1.10 How to Stop a Conversion
- 22.2.1.11 Example Sequence for Basic Configuration of ADC Module
- 22.2.2 Advanced Conversion Group Configuration Options
- 22.2.2.1 Group Trigger Options
- 22.2.2.2 Analog Input Channel Selection Mode Options
- 22.2.2.3 Single or Continuous Conversion Modes
- 22.2.2.4 Conversion Group Freeze Capability
- 22.2.2.5 Conversion Group Memory Overrun Option
- 22.2.2.6 Response on Writing Non-Zero Value to Conversion Group’s Channel Select Register
- 22.2.2.7 Conversion Result Size on Reading: 8-bit, 10-bit, or 12-bit
- 22.2.2.8 Option to Read Group Channel ID Along With Conversion Result
- 22.2.3 ADC Module Basic Interrupts
- 22.2.4 ADC Module DMA Requests
- 22.2.5 ADC Magnitude Threshold Interrupts
- 22.2.6 ADC Special Modes
- 22.2.7 ADC Results’ RAM Special Features
- 22.2.8 ADEVT Pin General Purpose I/O Functionality
- 22.2.1 Basic Features and Usage of the ADC
- 22.3 ADC Registers
- 22.3.1 ADC Reset Control Register (ADRSTCR)
- 22.3.2 ADC Operating Mode Control Register (ADOPMODECR)
- 22.3.3 ADC Clock Control Register (ADCLOCKCR)
- 22.3.4 ADC Calibration Mode Control Register (ADCALCR)
- 22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR)
- 22.3.6 ADC Group1 Operating Mode Control Register (ADG1MODECR)
- 22.3.7 ADC Group2 Operating Mode Control Register (ADG2MODECR)
- 22.3.8 ADC Event Group Trigger Source Select Register (ADEVSRC)
- 22.3.9 ADC Group1 Trigger Source Select Register (ADG1SRC)
- 22.3.10 ADC Group2 Trigger Source Select Register (ADG2SRC)
- 22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)
- 22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)
- 22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)
- 22.3.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG)
- 22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG)
- 22.3.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG)
- 22.3.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)
- 22.3.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR)
- 22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
- 22.3.20 ADC Event Group DMA Control Register (ADEVDMACR)
- 22.3.21 ADC Group1 DMA Control Register (ADG1DMACR)
- 22.3.22 ADC Group2 DMA Control Register (ADG2DMACR)
- 22.3.23 ADC Results Memory Configuration Register (ADBNDCR)
- 22.3.24 ADC Results Memory Size Configuration Register (ADBNDEND)
- 22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)
- 22.3.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP)
- 22.3.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP)
- 22.3.28 ADC Event Group Status Register (ADEVSR)
- 22.3.29 ADC Group1 Status Register (ADG1SR)
- 22.3.30 ADC Group2 Status Register (ADG2SR)
- 22.3.31 ADC Event Group Channel Select Register (ADEVSEL)
- 22.3.32 ADC Group1 Channel Select Register (ADG1SEL)
- 22.3.33 ADC Group2 Channel Select Register (ADG2SEL)
- 22.3.34 ADC Calibration and Error Offset Correction Register (ADCALR)
- 22.3.35 ADC State Machine Status Register (ADSMSTATE)
- 22.3.36 ADC Channel Last Conversion Value Register (ADLASTCONV)
- 22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER)
- 22.3.38 ADC Group1 Results FIFO Register (ADG1BUFFER)
- 22.3.39 ADC Group2 Results FIFO Register (ADG2BUFFER)
- 22.3.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
- 22.3.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)
- 22.3.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)
- 22.3.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR)
- 22.3.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT)
- 22.3.45 ADC ADEVT Pin Input Value Register (ADEVTIN)
- 22.3.46 ADC ADEVT Pin Set Register (ADEVTSET)
- 22.3.47 ADC ADEVT Pin Clear Register (ADEVTCLR)
- 22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR)
- 22.3.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS)
- 22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL)
- 22.3.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
- 22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)
- 22.3.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)
- 22.3.54 ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR)
- 22.3.55 ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK)
- 22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
- 22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
- 22.3.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG)
- 22.3.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)
- 22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)
- 22.3.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR)
- 22.3.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR)
- 22.3.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)
- 22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR)
- 22.3.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR)
- 22.3.66 ADC Parity Control Register (ADPARCR)
- 22.3.67 ADC Parity Error Address Register (ADPARADDR)
- 22.3.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL)
- 22.3.69 ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL)
- 22.3.70 ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL)
- 22.3.71 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL)
- 22.3.72 ADC Event Group Current Count Register (ADEVCURRCOUNT)
- 22.3.73 ADC Event Group Maximum Count Register (ADEVMAXCOUNT)
- 22.3.74 ADC Group1 Current Count Register (ADG1CURRCOUNT)
- 22.3.75 ADC Group1 Maximum Count Register (ADG1MAXCOUNT)
- 22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT)
- 22.3.77 ADC Group2 Maximum Count Register (ADG2MAXCOUNT)
- 23 High-End Timer (N2HET) Module
- 23.1 Overview
- 23.2 N2HET Functional Description
- 23.2.1 Specialized Timer Micromachine
- 23.2.2 N2HET RAM Organization
- 23.2.3 Time Base
- 23.2.4 Host Interface
- 23.2.5 I/O Control
- 23.2.5.1 Using General-Purpose I/O Data Set and Clear Registers
- 23.2.5.2 Loop Resolution Structure
- 23.2.5.3 High Resolution Structure
- 23.2.5.4 HR Block Diagram
- 23.2.5.5 HR Structures Sharing (Input)
- 23.2.5.6 AND / XOR-shared HR Structure (Output)
- 23.2.5.7 Loop Back Mode
- 23.2.5.8 Edge Detection Input Timing
- 23.2.5.9 PWM Generation Example 1 (in HR Mode)
- 23.2.5.10 PWM Generation Example 2 (in HR Mode)
- 23.2.5.11 Pulse Generation Example (in HR Mode)
- 23.2.5.12 Pulse Measurement Example (in HR Mode)
- 23.2.5.13 WCAP Execution Example (in HR Mode)
- 23.2.5.14 I/O Pull Control Feature
- 23.2.5.15 Open-Drain Feature
- 23.2.5.16 N2HET Pin Disable Feature
- 23.2.6 Suppression Filters
- 23.2.7 Interrupts and Exceptions
- 23.2.8 Hardware Priority Scheme
- 23.2.9 N2HET Requests to DMA and HTU
- 23.3 Angle Functions
- 23.4 N2HET Control Registers
- 23.4.1 Global Configuration Register (HETGCR)
- 23.4.2 Prescale Factor Register (HETPFR)
- 23.4.3 N2HET Current Address Register (HETADDR)
- 23.4.4 Offset Index Priority Level 1 Register (HETOFF1)
- 23.4.5 Offset Index Priority Level 2 Register (HETOFF2)
- 23.4.6 Interrupt Enable Set Register (HETINTENAS)
- 23.4.7 Interrupt Enable Clear Register (HETINTENAC)
- 23.4.8 Exception Control Register 1 (HETEXC1)
- 23.4.9 Exception Control Register 2 (HETEXC2)
- 23.4.10 Interrupt Priority Register (HETPRY)
- 23.4.11 Interrupt Flag Register (HETFLG)
- 23.4.12 AND Share Control Register (HETAND)
- 23.4.13 HR Share Control Register (HETHRSH)
- 23.4.14 XOR Share Control Register (HETXOR)
- 23.4.15 Request Enable Set Register (HETREQENS)
- 23.4.16 Request Enable Clear Register (HETREQENC)
- 23.4.17 Request Destination Select Register (HETREQDS)
- 23.4.18 NHET Direction Register (HETDIR)
- 23.4.19 N2HET Data Input Register (HETDIN)
- 23.4.20 N2HET Data Output Register (HETDOUT)
- 23.4.21 NHET Data Set Register (HETDSET)
- 23.4.22 N2HET Data Clear Register (HETDCLR)
- 23.4.23 N2HET Open Drain Register (HETPDR)
- 23.4.24 N2HET Pull Disable Register (HETPULDIS)
- 23.4.25 N2HET Pull Select Register (HETPSL)
- 23.4.26 Parity Control Register (HETPCR)
- 23.4.27 Parity Address Register (HETPAR)
- 23.4.28 Parity Pin Register (HETPPR)
- 23.4.29 Suppression Filter Preload Register (HETSFPRLD)
- 23.4.30 Suppression Filter Enable Register (HETSFENA)
- 23.4.31 Loop Back Pair Select Register (HETLBPSEL)
- 23.4.32 Loop Back Pair Direction Register (HETLBPDIR)
- 23.4.33 N2HET Pin Disable Register (HETPINDIS)
- 23.5 HWAG Registers
- 23.5.1 HWAG Pin Select Register (HWAPINSEL)
- 23.5.2 HWAG Global Control Register 0 (HWAGCR0)
- 23.5.3 HWAG Global Control Register 1 (HWAGCR1)
- 23.5.4 HWAG Global Control Register 2 (HWAGCR2)
- 23.5.5 HWAG Interrupt Enable Set Register (HWAENASET)
- 23.5.6 HWAG Interrupt Enable Clear Register (HWAENACLR)
- 23.5.7 HWAG Interrupt Level Set Register (HWALVLSET)
- 23.5.8 HWAG Interrupt Level Clear Register (HWALVLCLR)
- 23.5.9 HWAG Interrupt Flag Register (HWAFLG)
- 23.5.10 HWAG Interrupt Offset Register 0 (HWAOFF0)
- 23.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1)
- 23.5.12 HWAG Angle Value Register (HWAACNT)
- 23.5.13 HWAG Previous Tooth Period Value Register (HWAPCNT1)
- 23.5.14 HWAG Current Tooth Period Value Register (HWAPCNT)
- 23.5.15 HWAG Step Width Register (HWASTWD)
- 23.5.16 HWAG Teeth Number Register (HWATHNB)
- 23.5.17 HWAG Current Teeth Number Register (HWATHVL)
- 23.5.18 HWAG Filter Register (HWAFIL)
- 23.5.19 HWAG Filter Register 2 (HWAFIL2)
- 23.5.20 HWAG Angle Increment Register (HWAANGI)
- 23.6 Instruction Set
- 23.6.1 Instruction Summary
- 23.6.2 Abbreviations, Encoding Formats and Bits
- 23.6.3 Instruction Description
- 23.6.3.1 ACMP (Angle Compare)
- 23.6.3.2 ACNT (Angle Count)
- 23.6.3.3 ADCNST (Add Constant)
- 23.6.3.4 ADC, ADD, AND, OR, SBB, SUB, XOR
- 23.6.3.5 ADM32 (Add Move 32)
- 23.6.3.6 APCNT (Angle Period Count)
- 23.6.3.7 BR (Branch)
- 23.6.3.8 CNT (Count)
- 23.6.3.9 DADM64 (Data Add Move 64)
- 23.6.3.10 DJZ (Decrement and Jump if Zero)
- 23.6.3.11 ECMP (Equality Compare)
- 23.6.3.12 ECNT (Event Count)
- 23.6.3.13 MCMP (Magnitude Compare)
- 23.6.3.14 MOV32 (Data Move 32)
- 23.6.3.15 MOV64 (Data Move 64)
- 23.6.3.16 PCNT (Period/Pulse Count)
- 23.6.3.17 PWCNT (Pulse Width Count)
- 23.6.3.18 RADM64 (Register Add Move 64)
- 23.6.3.19 RCNT (Ratio Count)
- 23.6.3.20 SCMP (Sequence Compare)
- 23.6.3.21 SCNT (Step Count)
- 23.6.3.22 SHFT (Shift)
- 23.6.3.23 WCAP (Software Capture Word)
- 23.6.3.24 WCAPE (Software Capture Word and Event Count)
- 24 High-End Timer Transfer Unit (HTU) Module
- 24.1 Overview
- 24.2 Module Operation
- 24.3 Use Cases
- 24.4 HTU Control Registers
- 24.4.1 Global Control Register (HTU GC)
- 24.4.2 Control Packet Enable Register (HTU CPENA)
- 24.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0)
- 24.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1)
- 24.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2)
- 24.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3)
- 24.4.7 Active Control Packet and Error Register (HTU ACPE)
- 24.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)
- 24.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS)
- 24.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC)
- 24.4.11 Interrupt Mapping Register (HTU INTMAP)
- 24.4.12 Interrupt Offset Register 0 (HTU INTOFF0)
- 24.4.13 Interrupt Offset Register 1 (HTU INTOFF1)
- 24.4.14 Buffer Initialization Mode Register (HTU BIM)
- 24.4.15 Request Lost Flag Register (HTU RLOSTFL)
- 24.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL)
- 24.4.17 BER Interrupt Flag Register (HTU BERINTFL)
- 24.4.18 Memory Protection 1 Start Address Register (HTU MP1S)
- 24.4.19 Memory Protection 1 End Address Register (HTU MP1E)
- 24.4.20 Debug Control Register (HTU DCTRL)
- 24.4.21 Watch Point Register (HTU WPR)
- 24.4.22 Watch Mask Register (HTU WMR)
- 24.4.23 Module Identification Register (HTU ID)
- 24.4.24 Parity Control Register (HTU PCR)
- 24.4.25 Parity Address Register (HTU PAR)
- 24.4.26 Memory Protection Control and Status Register (HTU MPCS)
- 24.4.27 Memory Protection Start Address Register 0 (HTU MP0S)
- 24.4.28 Memory Protection End Address Register (HTU MP0E)
- 24.5 Double Control Packet Configuration Memory
- 24.5.1 Initial Full Address A Register (HTU IFADDRA)
- 24.5.2 Initial Full Address B Register (HTU IFADDRB)
- 24.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT)
- 24.5.4 Initial Transfer Count Register (HTU ITCOUNT)
- 24.5.5 Current Full Address A Register (HTU CFADDRA)
- 24.5.6 Current Full Address B Register (HTU CFADDRB)
- 24.5.7 Current Frame Count Register (HTU CFCOUNT)
- 24.6 Examples
- 25 General-Purpose Input/Output (GIO) Module
- 25.1 Overview
- 25.2 Quick Start Guide
- 25.3 Functional Description of GIO Module
- 25.4 Device Modes of Operation
- 25.5 GIO Control Registers
- 25.5.1 GIO Global Control Register (GIOGCR0)
- 25.5.2 GIO Interrupt Detect Register (GIOINTDET)
- 25.5.3 GIO Interrupt Polarity Register (GIOPOL)
- 25.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)
- 25.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)
- 25.5.6 GIO Interrupt Flag Register (GIOFLG)
- 25.5.7 GIO Offset Register 1 (GIOOFF1)
- 25.5.8 GIO Offset B Register (GIOOFF2)
- 25.5.9 GIO Emulation A Register (GIOEMU1)
- 25.5.10 GIO Emulation B Register (GIOEMU2)
- 25.5.11 GIO Data Direction Registers (GIODIR[A-B])
- 25.5.12 GIO Data Input Registers (GIODIN[A-B])
- 25.5.13 GIO Data Output Registers (GIODOUT[A-B])
- 25.5.14 GIO Data Set Registers (GIODSET[A-B])
- 25.5.15 GIO Data Clear Registers (GIODCLR[A-B])
- 25.5.16 GIO Open Drain Registers (GIOPDR[A-B])
- 25.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B])
- 25.5.18 GIO Pull Select Registers (GIOPSL[A-B])
- 25.6 I/O Control Summary
- 26 FlexRay Module
- 26.1 Overview
- 26.2 Module Operation
- 26.2.1 Transfer Unit
- 26.2.2 Communication Cycle
- 26.2.3 Communication Modes
- 26.2.4 Clock Synchronization
- 26.2.5 Error Handling
- 26.2.6 Communication Controller States
- 26.2.7 Network Management
- 26.2.8 Filtering and Masking
- 26.2.9 Transmit Process
- 26.2.10 Receive Process
- 26.2.11 FIFO Function
- 26.2.12 Message Handling
- 26.2.13 Module RAMs
- 26.2.14 Interrupts
- 26.2.15 Minimum Peripheral Clock Frequency
- 26.2.16 Assignment of FlexRay Configuration Parameters
- 26.2.17 Emulation/Debug Support
- 26.3 FlexRay Module Registers
- 26.3.1 Transfer Unit Registers
- 26.3.1.1 Global Static Number 0 (GSN0)
- 26.3.1.2 Global Static Number 1 (GSN1)
- 26.3.1.3 Global Control Set/Reset (GCS/GCR)
- 26.3.1.4 Transfer Status Current Buffer (TSCB)
- 26.3.1.5 Last Transferred Buffer to Communication Controller (LTBCC)
- 26.3.1.6 Last Transferred Buffer to System Memory (LTBSM)
- 26.3.1.7 Transfer Base Address (TBA)
- 26.3.1.8 Next Transfer Base Address (NTBA)
- 26.3.1.9 Base Address of Mirrored Status (BAMS)
- 26.3.1.10 Start Address of Memory Protection (SAMP)
- 26.3.1.11 End Address of Memory Protection (EAMP)
- 26.3.1.12 Transfer to System Memory Occurred (TSMO[1-4])
- 26.3.1.13 Transfer to Communication Controller Occurred (TCCO[1-4])
- 26.3.1.14 Transfer Occurred Offset (TOOFF)
- 26.3.1.15 TCR Single-Bit Error Status (TSBESTAT)
- 26.3.1.16 ECC Error Address (PEADR)
- 26.3.1.17 Transfer Error Interrupt Flag (TEIF)
- 26.3.1.18 Transfer Error Interrupt Enable Set/Reset (TEIRES/TEIRER)
- 26.3.1.19 Trigger Transfer to System Memory Set/Reset (TTSMS[1-4]/TTSMR[1-4])
- 26.3.1.20 Trigger Transfer to Communication Controller Set/Reset (TTCCS[1-4]/TTCCR[1-4])
- 26.3.1.21 Enable Transfer on Event to System Memory Set/Reset (ETESMS[1-4]/ETESMR[1-4])
- 26.3.1.22 Clear on Event to System Memory Set/Reset (CESMS[1-4]/CESMR[1-4])
- 26.3.1.23 Transfer to System Memory Interrupt Enable Set/Reset (TSMIES[1-4]/TSMIER[1-4])
- 26.3.1.24 Transfer to Communication Controller Interrupt Enable Set/Reset (TCCIES[1-4]/TCCIER[1-4])
- 26.3.1.25 Transfer Configuration RAM (TCR)
- 26.3.1.26 TCR ECC Test Mode
- 26.3.2 Communication Controller Registers
- 26.3.2.1 Special Registers
- 26.3.2.2 Interrupt Registers
- 26.3.2.2.1 Error Interrupt Register (EIR)
- 26.3.2.2.2 Status Interrupt Register (SIR)
- 26.3.2.2.3 Error Interrupt Line Select (EILS)
- 26.3.2.2.4 Status Interrupt Line Select (SILS)
- 26.3.2.2.5 Error Interrupt Enable Set / Reset (EIES/EIER)
- 26.3.2.2.6 Status Interrupt Enable Set / Reset Register (SIES/SIER)
- 26.3.2.2.7 Interrupt Line Enable Register (ILE)
- 26.3.2.2.8 Timer 0 Configuration Register (T0C)
- 26.3.2.2.9 Timer 1 Configuration Register (T1C)
- 26.3.2.2.10 Stop Watch Register 1 Register (STPW1)
- 26.3.2.2.11 Stop Watch Register 2 Register (STPW2)
- 26.3.2.3 Control Registers
- 26.3.2.3.1 SUC Configuration Register 1 (SUCC1)
- 26.3.2.3.2 SUC Configuration Register 2 (SUCC2)
- 26.3.2.3.3 SUC Configuration Register 3 (SUCC3)
- 26.3.2.3.4 NEM Configuration Register (NEMC)
- 26.3.2.3.5 PRT Configuration Register 1 (PRTC1)
- 26.3.2.3.6 PRT Configuration Register 2 (PRTC2)
- 26.3.2.3.7 MHD Configuration Register (MHDC)
- 26.3.2.3.8 GTU Configuration Register 1 (GTUC1)
- 26.3.2.3.9 GTU Configuration Register 2 (GTUC2)
- 26.3.2.3.10 GTU Configuration Register 3 (GTUC3)
- 26.3.2.3.11 GTU Configuration Register 4 (GTUC4)
- 26.3.2.3.12 GTU Configuration Register 5 (GTUC5)
- 26.3.2.3.13 GTU Configuration Register 6 (GTUC6)
- 26.3.2.3.14 GTU Configuration Register 7 (GTUC7)
- 26.3.2.3.15 GTU Configuration Register 8 (GTUC8)
- 26.3.2.3.16 GTU Configuration Register 9 (GTUC9)
- 26.3.2.3.17 GTU Configuration Register 10 (GTUC10)
- 26.3.2.3.18 GTU Configuration Register 11 (GTUC11)
- 26.3.2.4 Status Registers
- 26.3.2.4.1 Communication Controller Status Vector (CCSV)
- 26.3.2.4.2 Communication Controller Error Vector (CCEV)
- 26.3.2.4.3 Slot Counter Value (SCV)
- 26.3.2.4.4 Macrotick and Cycle Counter Value (MTCCV)
- 26.3.2.4.5 Rate Correction Value (RCV)
- 26.3.2.4.6 Offset Correction Value (OCV)
- 26.3.2.4.7 Sync Frame Status (SFS)
- 26.3.2.4.8 Symbol Window and NIT Status (SWNIT)
- 26.3.2.4.9 Aggregated Channel Status (ACS)
- 26.3.2.4.10 Even Sync ID Registers (ESID[1-15])
- 26.3.2.4.11 Odd Sync ID Registers (OSID[1-15])
- 26.3.2.4.12 Network Management Vector Registers (NMV[1-3])
- 26.3.2.5 Message Buffer Control Registers
- 26.3.2.6 Message Buffer Status Registers
- 26.3.2.6.1 Message Handler Status (MHDS)
- 26.3.2.6.2 Last Dynamic Transmit Slot (LDTS)
- 26.3.2.6.3 FIFO Status Register (FSR)
- 26.3.2.6.4 Message Handler Constraints Flags (MHDF)
- 26.3.2.6.5 Transmission Request Registers (TXRQ[1-4])
- 26.3.2.6.6 New Data Registers (NDAT[1-4])
- 26.3.2.6.7 Message Buffer Status Changed Registers (MBSC[1-4])
- 26.3.2.7 Identification Registers
- 26.3.2.8 Input Buffer
- 26.3.2.8.1 Write Data Section Registers (WRDS[1-64])
- 26.3.2.8.2 Write Header Section Register 1 (WRHS1)
- 26.3.2.8.3 Write Header Section Register 2 (WRHS2)
- 26.3.2.8.4 Write Header Section Register 3 (WRHS3)
- 26.3.2.8.5 Input Buffer Command Mask Register (IBCM)
- 26.3.2.8.6 Input Buffer Command Request Register (IBCR)
- 26.3.2.9 Output Buffer
- 26.3.2.9.1 Read Data Section Registers (RDDS[1-64])
- 26.3.2.9.2 Read Header Section Register 1 (RDHS1)
- 26.3.2.9.3 Read Header Section Register 2 (RDHS2)
- 26.3.2.9.4 Read Header Section Register 3 (RDHS3)
- 26.3.2.9.5 Message Buffer Status Register (MBS)
- 26.3.2.9.6 Output Buffer Command Mask Register (OBCM)
- 26.3.2.9.7 Output Buffer Command Request Register (OBCR)
- 26.3.1 Transfer Unit Registers
- 27 Controller Area Network (DCAN) Module
- 27.1 Overview
- 27.2 CAN Blocks
- 27.3 CAN Bit Timing
- 27.4 CAN Module Configuration
- 27.5 Message RAM
- 27.6 Message Interface Register Sets
- 27.7 Message Object Configurations
- 27.7.1 Configuration of a Transmit Object for Data Frames
- 27.7.2 Configuration of a Transmit Object for Remote Frames
- 27.7.3 Configuration of a Single Receive Object for Data Frames
- 27.7.4 Configuration of a Single Receive Object for Remote Frames
- 27.7.5 Configuration of a FIFO Buffer
- 27.7.6 Reconfiguration of Message Objects for the Reception of Frames
- 27.7.7 Reconfiguration of Message Objects for the Transmission of Frames
- 27.8 Message Handling
- 27.8.1 Message Handler Overview
- 27.8.2 Receive/Transmit Priority
- 27.8.3 Transmission of Messages in Event Driven CAN Communication
- 27.8.4 Updating a Transmit Object
- 27.8.5 Changing a Transmit Object
- 27.8.6 Acceptance Filtering of Received Messages
- 27.8.7 Reception of Data Frames
- 27.8.8 Reception of Remote Frames
- 27.8.9 Reading Received Messages
- 27.8.10 Requesting New Data for a Receive Object
- 27.8.11 Storing Received Messages in FIFO Buffers
- 27.8.12 Reading from a FIFO Buffer
- 27.9 CAN Message Transfer
- 27.10 Interrupt Functionality
- 27.11 Global Power Down Mode
- 27.12 Local Power Down Mode
- 27.13 GIO Support
- 27.14 Test Modes
- 27.15 SECDED Mechanism
- 27.16 Debug/Suspend Mode
- 27.17 DCAN Control Registers
- 27.17.1 CAN Control Register (DCAN CTL)
- 27.17.2 Error and Status Register (DCAN ES)
- 27.17.3 Error Counter Register (DCAN ERRC)
- 27.17.4 Bit Timing Register (DCAN BTR)
- 27.17.5 Interrupt Register (DCAN INT)
- 27.17.6 Test Register (DCAN TEST)
- 27.17.7 Parity Error Code Register (DCAN PERR)
- 27.17.8 Core Release Register (DCAN REL)
- 27.17.9 ECC Diagnostic Register (DCAN ECCDIAG)
- 27.17.10 ECC Diagnostic Status Register (DCAN ECCDIAG STAT)
- 27.17.11 ECC Control and Status Register (DCAN ECC CS)
- 27.17.12 ECC Single-Bit Error Code Register (DCAN ECC SERR)
- 27.17.13 Auto-Bus-On Time Register (DCAN ABOTR)
- 27.17.14 Transmission Request X Register (DCAN TXRQ X)
- 27.17.15 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78)
- 27.17.16 New Data X Register (DCAN NWDAT X)
- 27.17.17 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78)
- 27.17.18 Interrupt Pending X Register (DCAN INTPND X)
- 27.17.19 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78)
- 27.17.20 Message Valid X Register (DCAN MSGVAL X)
- 27.17.21 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78)
- 27.17.22 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78)
- 27.17.23 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)
- 27.17.24 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK)
- 27.17.25 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)
- 27.17.26 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL)
- 27.17.27 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB)
- 27.17.28 IF3 Observation Register (DCAN IF3OBS)
- 27.17.29 IF3 Mask Register (DCAN IF3MSK)
- 27.17.30 IF3 Arbitration Register (DCAN IF3ARB)
- 27.17.31 IF3 Message Control Register (DCAN IF3MCTL)
- 27.17.32 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB)
- 27.17.33 IF3 Update Enable Registers (DCAN IF3UPD12 to DCAN IF3UPD78)
- 27.17.34 CAN TX IO Control Register (DCAN TIOC)
- 27.17.35 CAN RX IO Control Register (DCAN RIOC)
- 28 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP)
- 28.1 Overview
- 28.2 Basic Operation
- 28.2.1 SPI Mode
- 28.2.2 MibSPI Mode
- 28.2.3 DMA Requests
- 28.2.4 Interrupts
- 28.2.5 Physical Interface
- 28.2.6 Advanced Module Configuration Options
- 28.2.6.1 Data Formats
- 28.2.6.2 Clocking Modes
- 28.2.6.3 Decoded and Encoded Chip Select (Master Only)
- 28.2.6.4 Chip Select Timing Control
- 28.2.6.5 Multiple Transfers to Same Slave and Variable Chip Select Setup and Hold Timing
- 28.2.6.6 Parallel Mode (Multiple SIMO/SOMI Support, not available on all devices)
- 28.2.6.6.1 Parallel Mode Block Diagram
- 28.2.6.6.2 Parallel Mode Pin Mapping, MSB First
- 28.2.6.6.3 Parallel Mode Pin Mapping, MSB-First, LSB-First
- 28.2.6.6.4 2-Data Line Mode (MSB First, Phase 0, Polarity 0)
- 28.2.6.6.5 4-Data Line Mode (MSB First, Phase 0, Polarity 0)
- 28.2.6.6.6 8-Data Line Mode (MSB First, Phase 0, Polarity 0)
- 28.2.6.7 MibSPI Slave in Multi-buffer Configuration
- 28.2.6.8 Transfer Groups
- 28.2.7 General-Purpose I/O
- 28.2.8 Low-Power Mode
- 28.2.9 Safety Features
- 28.2.10 Test Features
- 28.2.11 Module Configuration
- 28.3 Control Registers
- 28.3.1 SPI Global Control Register 0 (SPIGCR0)
- 28.3.2 SPI Global Control Register 1 (SPIGCR1)
- 28.3.3 SPI Interrupt Register (SPIINT0)
- 28.3.4 SPI Interrupt Level Register (SPILVL)
- 28.3.5 SPI Flag Register (SPIFLG)
- 28.3.6 SPI Pin Control Register 0 (SPIPC0)
- 28.3.7 SPI Pin Control Register 1 (SPIPC1)
- 28.3.8 SPI Pin Control Register 2 (SPIPC2)
- 28.3.9 SPI Pin Control Register 3 (SPIPC3)
- 28.3.10 SPI Pin Control Register 4 (SPIPC4)
- 28.3.11 SPI Pin Control Register 5 (SPIPC5)
- 28.3.12 SPI Pin Control Register 6 (SPIPC6)
- 28.3.13 SPI Pin Control Register 7 (SPIPC7)
- 28.3.14 SPI Pin Control Register 8 (SPIPC8)
- 28.3.15 SPI Transmit Data Register 0 (SPIDAT0)
- 28.3.16 SPI Transmit Data Register 1 (SPIDAT1)
- 28.3.17 SPI Receive Buffer Register (SPIBUF)
- 28.3.18 SPI Emulation Register (SPIEMU)
- 28.3.19 SPI Delay Register (SPIDELAY)
- 28.3.20 SPI Default Chip Select Register (SPIDEF)
- 28.3.21 SPI Data Format Registers (SPIFMT[3:0])
- 28.3.22 Interrupt Vector 0 (INTVECT0)
- 28.3.23 Interrupt Vector 1 (INTVECT1)
- 28.3.24 SPI Pin Control Register 9 (SPIPC9)
- 28.3.25 Parallel/Modulo Mode Control Register (SPIPMCTRL)
- 28.3.26 Multi-buffer Mode Enable Register (MIBSPIE)
- 28.3.27 TG Interrupt Enable Set Register (TGITENST)
- 28.3.28 TG Interrupt Enable Clear Register (TGITENCR)
- 28.3.29 Transfer Group Interrupt Level Set Register (TGITLVST)
- 28.3.30 Transfer Group Interrupt Level Clear Register (TGITLVCR)
- 28.3.31 Transfer Group Interrupt Flag Register (TGINTFLAG)
- 28.3.32 Tick Count Register (TICKCNT)
- 28.3.33 Last TG End Pointer (LTGPEND)
- 28.3.34 TGx Control Registers (TGxCTRL)
- 28.3.35 DMA Channel Control Register (DMAxCTRL)
- 28.3.36 DMAxCOUNT Register (ICOUNT)
- 28.3.37 DMA Large Count (DMACNTLEN)
- 28.3.38 Parity/ECC Control Register (PAR_ECC_CTRL)
- 28.3.39 Parity/ECC Status Register (PAR_ECC_STAT)
- 28.3.40 Uncorrectable Parity or Double-Bit ECC Error Address Register - RXRAM (UERRADDR1)
- 28.3.41 Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM (UERRADDR0)
- 28.3.42 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR)
- 28.3.43 I/O-Loopback Test Control Register (IOLPBKTSTCR)
- 28.3.44 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1)
- 28.3.45 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3)
- 28.3.46 ECC Diagnostic Control Register (ECCDIAG_CTRL)
- 28.3.47 ECC Diagnostic Status Register (ECCDIAG_STAT)
- 28.3.48 Single-Bit Error Address Register - RXRAM (SBERRADDR1)
- 28.3.49 Single-Bit Error Address Register - TXRAM (SBERRADDR0)
- 28.4 Multi-buffer RAM
- 28.5 Parity\ECC Memory
- 28.6 MibSPI Pin Timing Parameters
- 29 Serial Communication Interface (SCI)/ Local Interconnect Network (LIN) Module
- 29.1 Introduction and Features
- 29.2 SCI
- 29.3 LIN
- 29.3.1 LIN Communication Formats
- 29.3.2 LIN Interrupts
- 29.3.3 LIN DMA Interface
- 29.3.4 LIN Configurations
- 29.4 Low-Power Mode
- 29.5 Emulation Mode
- 29.6 GPIO Functionality
- 29.7 SCI/LIN Control Registers
- 29.7.1 SCI Global Control Register 0 (SCIGCR0)
- 29.7.2 SCI Global Control Register 1 (SCIGCR1)
- 29.7.3 SCI Global Control Register 2 (SCIGCR2)
- 29.7.4 SCI Set Interrupt Register (SCISETINT)
- 29.7.5 SCI Clear Interrupt Register (SCICLEARINT)
- 29.7.6 SCI Set Interrupt Level Register (SCISETINTLVL)
- 29.7.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL)
- 29.7.8 SCI Flags Register (SCIFLR)
- 29.7.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0)
- 29.7.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1)
- 29.7.11 SCI Format Control Register (SCIFORMAT)
- 29.7.12 Baud Rate Selection Register (BRS)
- 29.7.13 SCI Data Buffers (SCIED, SCIRD, SCITD)
- 29.7.14 SCI Pin I/O Control Register 0 (SCIPIO0)
- 29.7.15 SCI Pin I/O Control Register 1 (SCIPIO1)
- 29.7.16 SCI Pin I/O Control Register 2 (SCIPIO2)
- 29.7.17 SCI Pin I/O Control Register 3 (SCIPIO3)
- 29.7.18 SCI Pin I/O Control Register 4 (SCIPIO4)
- 29.7.19 SCI Pin I/O Control Register 5 (SCIPIO5)
- 29.7.20 SCI Pin I/O Control Register 6 (SCIPIO6)
- 29.7.21 SCI Pin I/O Control Register 7 (SCIPIO7)
- 29.7.22 SCI Pin I/O Control Register 8 (SCIPIO8)
- 29.7.23 LIN Compare Register (LINCOMPARE)
- 29.7.24 LIN Receive Buffer 0 Register (LINRD0)
- 29.7.25 LIN Receive Buffer 1 Register (LINRD1)
- 29.7.26 LIN Mask Register (LINMASK)
- 29.7.27 LIN Identification Register (LINID)
- 29.7.28 LIN Transmit Buffer 0 Register (LINTD0)
- 29.7.29 LIN Transmit Buffer 1 Register (LINTD1)
- 29.7.30 Maximum Baud Rate Selection Register (MBRS)
- 29.7.31 Input/Output Error Enable (IODFTCTRL) Register
- 30 Serial Communication Interface (SCI) Module
- 30.1 Introduction
- 30.2 SCI Communication Formats
- 30.3 SCI Interrupts
- 30.4 SCI DMA Interface
- 30.5 SCI Configurations
- 30.6 SCI Low-Power Mode
- 30.7 SCI Control Registers
- 30.7.1 SCI Global Control Register 0 (SCIGCR0)
- 30.7.2 SCI Global Control Register 1 (SCIGCR1)
- 30.7.3 SCI Set Interrupt Register (SCISETINT)
- 30.7.4 SCI Clear Interrupt Register (SCICLEARINT)
- 30.7.5 SCI Set Interrupt Level Register (SCISETINTLVL)
- 30.7.6 SCI Clear Interrupt Level Register (SCICLEARINTLVL)
- 30.7.7 SCI Flags Register (SCIFLR)
- 30.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0)
- 30.7.9 SCI Interrupt Vector Offset 1 (SCIINTVECT1)
- 30.7.10 SCI Format Control Register (SCIFORMAT)
- 30.7.11 Baud Rate Selection Register (BRS)
- 30.7.12 SCI Data Buffers (SCIED, SCIRD, SCITD)
- 30.7.13 SCI Pin I/O Control Register 0 (SCIPIO0)
- 30.7.14 SCI Pin I/O Control Register 1 (SCIPIO1)
- 30.7.15 SCI Pin I/O Control Register 2 (SCIPIO2)
- 30.7.16 SCI Pin I/O Control Register 3 (SCIPIO3)
- 30.7.17 SCI Pin I/O Control Register 4 (SCIPIO4)
- 30.7.18 SCI Pin I/O Control Register 5 (SCIPIO5)
- 30.7.19 SCI Pin I/O Control Register 6 (SCIPIO6)
- 30.7.20 SCI Pin I/O Control Register 7 (SCIPIO7)
- 30.7.21 SCI Pin I/O Control Register 8 (SCIPIO8)
- 30.7.22 Input/Output Error Enable (IODFTCTRL) Register
- 30.8 GPIO Functionality
- 31 Inter-Integrated Circuit (I2C) Module
- 31.1 Overview
- 31.2 I2C Module Operation
- 31.3 I2C Operation Modes
- 31.4 I2C Module Integrity
- 31.5 Operational Information
- 31.6 I2C Control Registers
- 31.6.1 I2C Own Address Manager (I2COAR)
- 31.6.2 I2C Interrupt Mask Register (I2CIMR)
- 31.6.3 I2C Status Register (I2CSTR)
- 31.6.4 I2C Clock Divider Low Register (I2CCKL)
- 31.6.5 I2C Clock Control High Register (I2CCKH)
- 31.6.6 I2C Data Count Register (I2CCNT)
- 31.6.7 I2C Data Receive Register (I2CDRR)
- 31.6.8 I2C Slave Address Register (I2CSAR)
- 31.6.9 I2C Data Transmit Register (I2CDXR)
- 31.6.10 I2C Mode Register (I2CMDR)
- 31.6.11 I2C Interrupt Vector Register (I2CIVR)
- 31.6.12 I2C Extended Mode Register (I2CEMDR)
- 31.6.13 I2C Prescale Register (I2CPSC)
- 31.6.14 I2C Peripheral ID Register 1 (I2CPID1)
- 31.6.15 I2C Peripheral ID Register 2 (I2CPID2)
- 31.6.16 I2C DMA Control Register (I2CDMACR)
- 31.6.17 I2C Pin Function Register (I2CPFNC)
- 31.6.18 I2C Pin Direction Register (I2CPDIR)
- 31.6.19 I2C Data Input Register (I2CDIN)
- 31.6.20 I2C Data Output Register (I2CDOUT)
- 31.6.21 I2C Data Set Register (I2CDSET)
- 31.6.22 I2C Data Clear Register (I2CDCLR)
- 31.6.23 I2C Pin Open Drain Register (I2CPDR)
- 31.6.24 I2C Pull Disable Register (I2CPDIS)
- 31.6.25 I2C Pull Select Register (I2CPSEL)
- 31.6.26 I2C Pins Slew Rate Select Register (I2CSRS)
- 31.7 Sample Waveforms
- 32 EMAC/MDIO Module
- 32.1 Introduction
- 32.2 Architecture
- 32.2.1 Clock Control
- 32.2.2 Memory Map
- 32.2.3 Signal Descriptions
- 32.2.4 MII / RMII Signal Multiplexing Control
- 32.2.5 Ethernet Protocol Overview
- 32.2.6 Programming Interface
- 32.2.6.1 Packet Buffer Descriptors
- 32.2.6.2 Transmit and Receive Descriptor Queues
- 32.2.6.3 Transmit and Receive EMAC Interrupts
- 32.2.6.4 Transmit Buffer Descriptor Format
- 32.2.6.4.1 Next Descriptor Pointer
- 32.2.6.4.2 Buffer Pointer
- 32.2.6.4.3 Buffer Offset
- 32.2.6.4.4 Buffer Length
- 32.2.6.4.5 Packet Length
- 32.2.6.4.6 Start of Packet (SOP) Flag
- 32.2.6.4.7 End of Packet (EOP) Flag
- 32.2.6.4.8 Ownership (OWNER) Flag
- 32.2.6.4.9 End of Queue (EOQ) Flag
- 32.2.6.4.10 Teardown Complete (TDOWNCMPLT) Flag
- 32.2.6.4.11 Pass CRC (PASSCRC) Flag
- 32.2.6.5 Receive Buffer Descriptor Format
- 32.2.6.5.1 Next Descriptor Pointer
- 32.2.6.5.2 Buffer Pointer
- 32.2.6.5.3 Buffer Offset
- 32.2.6.5.4 Buffer Length
- 32.2.6.5.5 Packet Length
- 32.2.6.5.6 Start of Packet (SOP) Flag
- 32.2.6.5.7 End of Packet (EOP) Flag
- 32.2.6.5.8 Ownership (OWNER) Flag
- 32.2.6.5.9 End of Queue (EOQ) Flag
- 32.2.6.5.10 Teardown Complete (TDOWNCMPLT) Flag
- 32.2.6.5.11 Pass CRC (PASSCRC) Flag
- 32.2.6.5.12 Jabber Flag
- 32.2.6.5.13 Oversize Flag
- 32.2.6.5.14 Fragment Flag
- 32.2.6.5.15 Undersized Flag
- 32.2.6.5.16 Control Flag
- 32.2.6.5.17 Overrun Flag
- 32.2.6.5.18 Code Error (CODEERROR) Flag
- 32.2.6.5.19 Alignment Error (ALIGNERROR) Flag
- 32.2.6.5.20 CRC Error (CRCERROR) Flag
- 32.2.6.5.21 No Match (NOMATCH) Flag
- 32.2.7 EMAC Control Module
- 32.2.8 MDIO Module
- 32.2.9 EMAC Module
- 32.2.9.1 EMAC Module Components
- 32.2.9.1.1 Receive DMA Engine
- 32.2.9.1.2 Receive FIFO
- 32.2.9.1.3 MAC Receiver
- 32.2.9.1.4 Transmit DMA Engine
- 32.2.9.1.5 Transmit FIFO
- 32.2.9.1.6 MAC Transmitter
- 32.2.9.1.7 Statistics Logic
- 32.2.9.1.8 State RAM
- 32.2.9.1.9 EMAC Interrupt Controller
- 32.2.9.1.10 Control Registers and Logic
- 32.2.9.1.11 Clock and Reset Logic
- 32.2.9.2 EMAC Module Operational Overview
- 32.2.9.1 EMAC Module Components
- 32.2.10 MAC Interface
- 32.2.11 Packet Receive Operation
- 32.2.11.1 Receive DMA Host Configuration
- 32.2.11.2 Receive Channel Enabling
- 32.2.11.3 Receive Address Matching
- 32.2.11.4 Hardware Receive QOS Support
- 32.2.11.5 Host Free Buffer Tracking
- 32.2.11.6 Receive Channel Teardown
- 32.2.11.7 Receive Frame Classification
- 32.2.11.8 Promiscuous Receive Mode
- 32.2.11.9 Receive Overrun
- 32.2.12 Packet Transmit Operation
- 32.2.13 Receive and Transmit Latency
- 32.2.14 Transfer Node Priority
- 32.2.15 Reset Considerations
- 32.2.16 Initialization
- 32.2.17 Interrupt Support
- 32.2.18 Power Management
- 32.2.19 Emulation Considerations
- 32.3 EMAC Control Module Registers
- 32.3.1 EMAC Control Module Revision ID Register (REVID)
- 32.3.2 EMAC Control Module Software Reset Register (SOFTRESET)
- 32.3.3 EMAC Control Module Interrupt Control Register (INTCONTROL)
- 32.3.4 EMAC Control Module Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN)
- 32.3.5 EMAC Control Module Receive Interrupt Enable Registers (C0RXEN)
- 32.3.6 EMAC Control Module Transmit Interrupt Enable Registers (C0TXEN)
- 32.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN)
- 32.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT)
- 32.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT)
- 32.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT)
- 32.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT)
- 32.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX)
- 32.3.13 EMAC Control Module Transmit Interrupts Per Millisecond Registers (C0TXIMAX)
- 32.4 MDIO Registers
- 32.4.1 MDIO Revision ID Register (REVID)
- 32.4.2 MDIO Control Register (CONTROL)
- 32.4.3 PHY Acknowledge Status Register (ALIVE)
- 32.4.4 PHY Link Status Register (LINK)
- 32.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
- 32.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
- 32.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
- 32.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
- 32.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
- 32.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
- 32.4.11 MDIO User Access Register 0 (USERACCESS0)
- 32.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)
- 32.4.13 MDIO User Access Register 1 (USERACCESS1)
- 32.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)
- 32.5 EMAC Module Registers
- 32.5.1 Transmit Revision ID Register (TXREVID)
- 32.5.2 Transmit Control Register (TXCONTROL)
- 32.5.3 Transmit Teardown Register (TXTEARDOWN)
- 32.5.4 Receive Revision ID Register (RXREVID)
- 32.5.5 Receive Control Register (RXCONTROL)
- 32.5.6 Receive Teardown Register (RXTEARDOWN)
- 32.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
- 32.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
- 32.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)
- 32.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
- 32.5.11 MAC Input Vector Register (MACINVECTOR)
- 32.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)
- 32.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
- 32.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
- 32.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
- 32.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
- 32.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
- 32.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
- 32.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
- 32.5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
- 32.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
- 32.5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
- 32.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
- 32.5.24 Receive Maximum Length Register (RXMAXLEN)
- 32.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)
- 32.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
- 32.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH)
- 32.5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER)
- 32.5.29 MAC Control Register (MACCONTROL)
- 32.5.30 MAC Status Register (MACSTATUS)
- 32.5.31 Emulation Control Register (EMCONTROL)
- 32.5.32 FIFO Control Register (FIFOCONTROL)
- 32.5.33 MAC Configuration Register (MACCONFIG)
- 32.5.34 Soft Reset Register (SOFTRESET)
- 32.5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)
- 32.5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)
- 32.5.37 MAC Hash Address Register 1 (MACHASH1)
- 32.5.38 MAC Hash Address Register 2 (MACHASH2)
- 32.5.39 Back Off Test Register (BOFFTEST)
- 32.5.40 Transmit Pacing Algorithm Test Register (TPACETEST)
- 32.5.41 Receive Pause Timer Register (RXPAUSE)
- 32.5.42 Transmit Pause Timer Register (TXPAUSE)
- 32.5.43 MAC Address Low Bytes Register (MACADDRLO)
- 32.5.44 MAC Address High Bytes Register (MACADDRHI)
- 32.5.45 MAC Index Register (MACINDEX)
- 32.5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP)
- 32.5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP)
- 32.5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)
- 32.5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP)
- 32.5.50 Network Statistics Registers
- 32.5.50.1 Good Receive Frames Register (RXGOODFRAMES) (offset = 200h)
- 32.5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) (offset = 204h)
- 32.5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) (offset = 208h)
- 32.5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) (offset = 20Ch)
- 32.5.50.5 Receive CRC Errors Register (RXCRCERRORS) (offset = 210h)
- 32.5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS) (offset = 214h)
- 32.5.50.7 Receive Oversized Frames Register (RXOVERSIZED) (offset = 218h)
- 32.5.50.8 Receive Jabber Frames Register (RXJABBER) (offset = 21Ch)
- 32.5.50.9 Receive Undersized Frames Register (RXUNDERSIZED) (offset = 220h)
- 32.5.50.10 Receive Frame Fragments Register (RXFRAGMENTS) (offset = 224h)
- 32.5.50.11 Filtered Receive Frames Register (RXFILTERED) (offset = 228h)
- 32.5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) (offset = 22Ch)
- 32.5.50.13 Receive Octet Frames Register (RXOCTETS) (offset = 230h)
- 32.5.50.14 Good Transmit Frames Register (TXGOODFRAMES) (offset = 234h)
- 32.5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) (offset = 238h)
- 32.5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) (offset = 23Ch)
- 32.5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) (offset = 240h)
- 32.5.50.18 Deferred Transmit Frames Register (TXDEFERRED) (offset = 244h)
- 32.5.50.19 Transmit Collision Frames Register (TXCOLLISION) (offset = 248h)
- 32.5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) (offset = 24Ch)
- 32.5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) (offset = 250h)
- 32.5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) (offset = 254h)
- 32.5.50.23 Transmit Late Collision Frames Register (TXLATECOLL) (offset = 258h)
- 32.5.50.24 Transmit Underrun Error Register (TXUNDERRUN) (offset = 25Ch)
- 32.5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) (offset = 260h)
- 32.5.50.26 Transmit Octet Frames Register (TXOCTETS) (offset = 264h)
- 32.5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) (offset = 268h)
- 32.5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) (offset = 26Ch)
- 32.5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255) (offset = 270h)
- 32.5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) (offset = 274h)
- 32.5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) (offset = 278h)
- 32.5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) (offset = 27Ch)
- 32.5.50.33 Network Octet Frames Register (NETOCTETS) (offset = 280h)
- 32.5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) (offset = 284h)
- 32.5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) (offset = 288h)
- 32.5.50.36 Receive DMA Overruns Register (RXDMAOVERRUNS) (offset = 28Ch)
- 33 Enhanced Capture (eCAP) Module
- 33.1 Introduction
- 33.2 Basic Operation
- 33.3 Application of the ECAP Module
- 33.3.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger
- 33.3.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger
- 33.3.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger
- 33.3.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
- 33.4 Application of the APWM Mode
- 33.5 eCAP Registers
- 33.5.1 Time-Stamp Counter Register (TSCTR)
- 33.5.2 Counter Phase Control Register (CTRPHS)
- 33.5.3 Capture-1 Register (CAP1)
- 33.5.4 Capture-2 Register (CAP2)
- 33.5.5 Capture-3 Register (CAP3)
- 33.5.6 Capture-4 Register (CAP4)
- 33.5.7 ECAP Control Register 2 (ECCTL2)
- 33.5.8 ECAP Control Regiser 1 (ECCTL1)
- 33.5.9 ECAP Interrupt Flag Register (ECFLG)
- 33.5.10 ECAP Interrupt Enable Register (ECEINT)
- 33.5.11 ECAP Interrupt Forcing Register (ECFRC)
- 33.5.12 ECAP Interrupt Clear Register (ECCLR)
- 34 Enhanced Quadrature Encoder Pulse (eQEP) Module
- 34.1 Introduction
- 34.2 Basic Operation
- 34.3 eQEP Registers
- 34.3.1 eQEP Position Counter Register (QPOSCNT)
- 34.3.2 eQEP Position Counter Initialization Register (QPOSINIT)
- 34.3.3 eQEP Maximum Position Count Register (QPOSMAX)
- 34.3.4 eQEP Position-Compare Register (QPOSCMP)
- 34.3.5 eQEP Index Position Latch Register (QPOSILAT)
- 34.3.6 eQEP Strobe Position Latch Register (QPOSSLAT)
- 34.3.7 eQEP Position Counter Latch Register (QPOSLAT)
- 34.3.8 eQEP Unit Timer Register (QUTMR)
- 34.3.9 eQEP Unit Period Register (QUPRD)
- 34.3.10 eQEP Watchdog Period Register (QWDPRD)
- 34.3.11 eQEP Watchdog Timer Register (QWDTMR)
- 34.3.12 eQEP Control Register (QEPCTL)
- 34.3.13 eQEP Decoder Control Register (QDECCTL)
- 34.3.14 eQEP Position-Compare Control Register (QPOSCTL)
- 34.3.15 eQEP Capture Control Register (QCAPCTL)
- 34.3.16 eQEP Interrupt Flag Register (QFLG)
- 34.3.17 eQEP Interrupt Enable Register (QEINT)
- 34.3.18 eQEP Interrupt Force Register (QFRC)
- 34.3.19 eQEP Interrupt Clear Register (QCLR)
- 34.3.20 eQEP Capture Timer Register (QCTMR)
- 34.3.21 eQEP Status Register (QEPSTS)
- 34.3.22 eQEP Capture Timer Latch Register (QCTMRLAT)
- 34.3.23 eQEP Capture Period Register (QCPRD)
- 34.3.24 eQEP Capture Period Latch Register (QCPRDLAT)
- 35 Enhanced Pulse Width Modulator (ePWM) Module
- 35.1 Introduction
- 35.2 ePWM Submodules
- 35.2.1 Overview
- 35.2.2 Time-Base (TB) Submodule
- 35.2.3 Counter-Compare (CC) Submodule
- 35.2.4 Action-Qualifier (AQ) Submodule
- 35.2.5 Dead-Band Generator (DB) Submodule
- 35.2.6 PWM-Chopper (PC) Submodule
- 35.2.7 Trip-Zone (TZ) Submodule
- 35.2.8 Event-Trigger (ET) Submodule
- 35.2.9 Digital Compare (DC) Submodule
- 35.2.10 Proper Interrupt Initialization Procedure
- 35.3 Application Examples
- 35.3.1 Overview of Multiple Modules
- 35.3.2 Key Configuration Capabilities
- 35.3.3 Controlling Multiple Buck Converters With Independent Frequencies
- 35.3.4 Controlling Multiple Buck Converters With Same Frequencies
- 35.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
- 35.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
- 35.3.7 Practical Applications Using Phase Control Between PWM Modules
- 35.4 ePWM Registers
- 35.4.1 Time-Base Submodule Registers
- 35.4.2 Counter-Compare Submodule Registers
- 35.4.3 Action-Qualifier Submodule Registers
- 35.4.4 Dead-Band Submodule Registers
- 35.4.5 Trip-Zone Submodule Registers
- 35.4.5.1 Trip-Zone Digital Compare Event Select Register (TZDCSEL)
- 35.4.5.2 Trip-Zone Select Register (TZSEL)
- 35.4.5.3 Trip-Zone Enable Interrupt Register (TZEINT)
- 35.4.5.4 Trip-Zone Control Register (TZCTL)
- 35.4.5.5 Trip-Zone Clear Register (TZCLR)
- 35.4.5.6 Trip-Zone Flag Register (TZFLG)
- 35.4.5.7 Trip-Zone Force Register (TZFRC)
- 35.4.6 Event-Trigger Submodule Registers
- 35.4.7 PWM-Chopper Submodule Register
- 35.4.8 Digital Compare Submodule Registers
- 35.4.8.1 Digital Compare A Control Register (DCACTL)
- 35.4.8.2 Digital Compare Trip Select (DCTRIPSEL)
- 35.4.8.3 Digital Compare Filter Control Register (DCFCTL)
- 35.4.8.4 Digital Compare B Control Register (DCBCTL)
- 35.4.8.5 Digital Compare Filter Offset Register (DCFOFFSET)
- 35.4.8.6 Digital Compare Capture Control Register (DCCAPCTL)
- 35.4.8.7 Digital Compare Filter Window Register (DCFWINDOW)
- 35.4.8.8 Digital Compare Filter Offset Counter Register (DCFOFFSETCNT)
- 35.4.8.9 Digital Compare Counter Capture Register (DCCAP)
- 35.4.8.10 Digital Compare Filter Window Counter Register (DCFWINDOWCNT)
- 36 Data Modification Module (DMM)
- 36.1 Overview
- 36.2 Module Operation
- 36.3 Control Registers
- 36.3.1 DMM Global Control Register (DMMGLBCTRL)
- 36.3.2 DMM Interrupt Set Register (DMMINTSET)
- 36.3.3 DMM Interrupt Clear Register (DMMINTCLR)
- 36.3.4 DMM Interrupt Level Register (DMMINTLVL)
- 36.3.5 DMM Interrupt Flag Register (DMMINTFLG)
- 36.3.6 DMM Interrupt Offset 1 Register (DMMOFF1)
- 36.3.7 DMM Interrupt Offset 2 Register (DMMOFF2)
- 36.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST)
- 36.3.9 DMM Direct Data Mode Blocksize Register (DMMDDMBL)
- 36.3.10 DMM Direct Data Mode Pointer Register (DMMDDMPT)
- 36.3.11 DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT)
- 36.3.12 DMM Destination x Region 1 (DMMDESTxREG1)
- 36.3.13 DMM Destination x Blocksize 1 (DMMDESTxBL1)
- 36.3.14 DMM Destination x Region 2 (DMMDESTxREG2)
- 36.3.15 DMM Destination x Blocksize 2 (DMMDESTxBL2)
- 36.3.16 DMM Pin Control 0 (DMMPC0)
- 36.3.17 DMM Pin Control 1 (DMMPC1)
- 36.3.18 DMM Pin Control 2 (DMMPC2)
- 36.3.19 DMM Pin Control 3 (DMMPC3)
- 36.3.20 DMM Pin Control 4 (DMMPC4)
- 36.3.21 DMM Pin Control 5 (DMMPC5)
- 36.3.22 DMM Pin Control 6 (DMMPC6)
- 36.3.23 DMM Pin Control 7 (DMMPC7)
- 36.3.24 DMM Pin Control 8 (DMMPC8)
- 37 RAM Trace Port (RTP)
- 37.1 Overview
- 37.2 Module Operation
- 37.3 RTP Control Registers
- 37.3.1 RTP Global Control Register (RTPGLBCTRL)
- 37.3.2 RTP Trace Enable Register (RTPTRENA)
- 37.3.3 RTP Global Status Register (RTPGSR)
- 37.3.4 RTP RAM 1 Trace Region Registers (RTPRAM1REG[1:2])
- 37.3.5 RTP RAM 2 Trace Region Registers (RTPRAM2REG[1:2])
- 37.3.6 RTP RAM 3 Trace Region Registers (RTPRAM3REG[1:2])
- 37.3.7 RTP Peripheral Trace Region Registers (RTPPERREG[1:2])
- 37.3.8 RTP Direct Data Mode Write Register (RTPDDMW)
- 37.3.9 RTP Pin Control 0 Register (RTPPC0)
- 37.3.10 RTP Pin Control 1 Register (RTPPC1)
- 37.3.11 RTP Pin Control 2 Register (RTPPC2)
- 37.3.12 RTP Pin Control 3 Register (RTPPC3)
- 37.3.13 RTP Pin Control 4 Register (RTPPC4)
- 37.3.14 RTP Pin Control 5 Register (RTPPC5)
- 37.3.15 RTP Pin Control 6 Register (RTPPC6)
- 37.3.16 RTP Pin Control 7 Register (RTPPC7)
- 37.3.17 RTP Pin Control 8 Register (RTPPC8)
- 38 eFuse Controller
- Revision History
- Important Notice