TN1176 LatticeECP3 SERDES/PCS Usage Guide Lattice ECP3 SERDES PCS
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- LatticeECP3 SERDES/PCS Usage Guide
- Introduction
- Features
- Using This Technical Note
- Standards Supported
- Architecture Overview
- SERDES/PCS Functional Description
- SERDES
- Equalizer
- Pre-Emphasis
- Reference Clocks
- SERDES Clock Architecture
- Rate Modes
- Reference Clock from an FPGA Core
- Full Data, Div 2 and Div 11 Data Rates
- Dynamic Switching Between Full Rate and Half Rate (DIV2)
- Reference Clock Sources
- Spread Spectrum Clocking (SSC) Support
- Loss of Signal
- Loss Of Lock
- TX Lane-to-Lane Skew
- SERDES PCS Configuration Setup
- Auto-Configuration File
- Transmit Data
- Receive Data
- 8b10b Decoder
- External Link State Machine Option
- Idle Insert for Gigabit Ethernet Mode
- Clock Tolerance Compensation
- Calculating Minimum Interpacket Gap
- PCS Module Generation in IPexpress
- 8-Bit and 10-Bit SERDES-Only Modes
- Generic 8b10b Mode
- LatticeECP3 PCS in Gigabit Ethernet and SGMII Modes
- XAUI Mode
- LatticeECP3 PCS in PCI Express Revision 1.1 (2.5Gpbs) Mode
- PCI Express Beacon Support
- SDI (SMPTE) Mode
- Serial RapidIO (SRIO) Mode
- Serial Digital Video and Out-Of-Band Low Speed SERDES Operation
- Open Base Station Architecture Initiative (OBSAI)
- Common Public Radio Interface (CPRI)
- SONET/SDH
- FPGA Interface Clocks
- Case I_a: 8/10-Bit, CTC FIFO and RX/TX FIFOs Not Bypassed
- Case I_b: 8/10-Bit, CTC FIFO Bypassed
- Case I_c: 8/10-Bit, RX/TX FIFO Bypassed
- Case I_d: 8/10-Bit, CTC FIFO and RX/TX FIFOs Bypassed
- Case II_a: 16/20-bit, CTC FIFO and RX/TX FIFOs NOT Bypassed
- Case II_b: 16/20-bit, CTC FIFO Bypassed
- SERDES/PCS Block Latency
- SERDES Debug Capabilities
- SERDES/PCS RESET
- References
- Technical Support Assistance
- Revision History
- Appendix A. Configuration Registers
- Quad Registers Overview
- Per Quad PCS Control Registers Details
- Per Quad PCS Control Registers Details
- Per Quad Reset and Clock Control Registers Details
- Per Quad PCS Status Registers Details
- Per Quad SERDES Status Registers Details
- Channel Registers Overview
- Per Channel PCS Control Registers Details
- Per Channel SERDES Control Registers Details
- Per Channel Reset and Clock Control Registers Details
- Per Channel PCS Status Registers Details
- Per Channel SERDES Status Registers Details
- Appendix B. Register Settings for Various Standards
- Appendix C. Attribute Cross Reference Table
- Appendix D. Lattice Diamond Overview