TN FC 35: E·MMC PCB Design Guide TNFC35 E MMC
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TN-FC-35: e·MMC PCB Design Guide Introduction Technical Note e·MMC PCB Design Guide Introduction This document is intended as guide for PCB designers using Micron e·MMC devices and will discuss the primary issues affecting design and layout. Figure 1: e·MMC 4.5 and 5.0 Package Compatibility 1 2 3 A NC NC DAT0 B NC C 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A NC NC DAT0 DAT1 DAT2 VSS RFU NC NC NC NC NC NC NC A B NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC B C NC VDDI NC VSSQ NC VCCQ NC NC NC NC NC NC NC NC C D NC NC NC NC NC NC NC D E NC NC NC RFU RFU NC NC NC E NC F NC NC NC VCC RFU NC NC NC F NC NC G NC NC NC VSS RFU NC NC NC G NC NC NC H NC NC NC DS VSS NC NC NC H VCC NC NC NC J NC NC NC VSS VCC NC NC NC J RFU NC NC NC K NC NC NC RST_n RFU NC NC NC K NC NC NC L NC NC NC NC NC NC L NC NC NC NC M NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC M NC NC NC NC NC N NC NC NC NC NC NC NC NC N NC NC VSSQ NC NC VCCQ NC NC VSSQ NC RFU P NC NC VCCQ VSSQ VCCQ VSSQ NC NC NC RFU NC NC NC NC P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 7 8 9 10 11 12 13 14 RFU RFU NC NC NC NC NC NC NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC NC VDDIM NC VSSQ VCCQ NC NC NC NC NC NC NC NC D NC NC NC NC NC NC NC E NC NC NC RFU RFU NC NC NC F NC NC NC VCC RFU NC NC G NC NC RFU VSS RFU NC H NC NC NC RFU VSS J NC NC NC RFU K NC NC NC RST_n L NC NC NC M NC NC NC VCCQ CMD CLK NC NC NC NC N NC VSSQ NC VCCQ VSSQ NC NC NC NC P NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC DAT1 DAT2 RFU VCC RFU VSS RFU RFU VSS PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN RFU VCC VCC RFU VSS RFU RFU VSS RFU VCC Ball e·MMC 4.51 e·MMC 5.0 H5 RFU DS DS can be floating if HS400 is not used. A6, J5 RFU VSS VSS can be floating if HS400 is not used. C5 RFU NC Used for routing in this technical note only because it is NC internally, and JEDEC redefined it as NC for e·MMC 5.0. 1 Comment Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All information discussed herein is provided on an "as is" basis, without warranties of any kind. TN-FC-35: e·MMC PCB Design Guide Introduction Figure 2: Host to Micron e·MMC 5.0 Connection VCCQ R_CMD R_DAT R_DAT R_DAT R_DAT R_DAT R_DAT R_DAT R_DAT R_RST_n C2 U1 e·MMC CLK CMD VCCQ CLK CMD SR_DS DS VDDiM VCC C5 C6 GND VDDiM U2 Host controller SR_CLK VCCQ DS DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 RST_n DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 RST_n C3 GND C1 VCC R_DS C4 VCC PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. TN-FC-35: e·MMC PCB Design Guide Signal and Capacitor Placement Signal and Capacitor Placement SR_CLK should be close to the host device, and SR_DS should be close to the e·MMC device. e·MMC signals can be fanned out through NC pins. No internal connection is present for NC pins. Micron recommends that e·MMC signals not be fanned out through RFU pins. The recommended decoupling capacitors should be placed on the bottom side of the PCB across the BGA escape vias in order to minimize the connection inductance seen by the capacitor. The capacitor pad should be connected to the power and ground plane with a larger via to minimize the inductance in decoupling capacitors and allow for maximum current flow. The recommended capacitor values are shown in Table 1 (page 4). Wide, short traces between the via and capacitor pads should be used, or the via placed adjacent to the capacitor pad. Figure 4 (page 4) shows how to connect capacitor pads to the power and ground plane. Method 1 is not recommended, while the others are recommended. Figure 3: Capacitor Placement and Signal PCB Layout D0 D1 D2 VSS D3 D4 D5 D6 D7 VDDi VSSQ VCCQ VCC VSS DS RST_n CMD CLK PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. TN-FC-35: e·MMC PCB Design Guide Signal and Capacitor Placement Table 1: Component Parameter Values Parameter Symbol Min Max Recommended Unit Pull-up resistance for CMD R_CMD 4.7 50 10 KΩ To prevent bus floating Pull-up resistance for DAT[7:0] Comments R_DAT 10 50 50 KΩ To prevent bus floating R_RST_n 4.7 50 50 KΩ It is not necessary to put pull-up resistance on RST_n line if the host does not use H/W reset. R_DS 4.7 50 50 KΩ Impedance of CLK/CMD/DS/ DAT[7:0] – 45 55 50 Ω Impedance match Serial resistance on CLK line SR_CLK 0 47 22 Ω To stabilize CLK signal Serial resistance on DS line SR_DS 0 47 22 Ω To stabilize DS signal VCCQ capacitor value C1, C2 2.2 + 0.1 4.7 + 0.22 2.2 + 0.1 µF Decoupling capacitor should be connected with VCCQ and VSSQ as closely as possible. VCC capacitor value (≤8GB) C3, C4 2.2 + 0.1 4.7 + 0.22 2.2 + 0.1 µF 4.7 + 0.22 µF Decoupling capacitor should be connected to VCC and VSS as closely as possible. 1 + 0.1 µF Pull-up resistance for RST_n Pull-down resistance for R_DS VCC capacitor value (>8GB) VDDIM capacitor value C5, C6 1 + 0.1 4.7 + 0.1 Decoupling capacitor should be connected to VDDIM and VSSQ as closely as possible. Figure 4: Connecting Capacitor Pads Absolutely not! 1 Even better 3 PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN Better 2 Better still 4 4 The best! Solid via within pad 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. TN-FC-35: e·MMC PCB Design Guide PCB Topology and Layout PCB Topology and Layout The PCB board must have at least four layers. CLK, CMD, DQ and DS signals should be treated as transmission lines with controlled impedance from 45Ω to 55Ω. The skew of propagation time of these signals should be minimized and the PCB trace length difference kept within ±50 mil. The following figure shows two commonly used PCB transmission line topologies. Figure 5: Transmission Line Topologies PCB Trace Ground Plane Dielectric Microstrip Stripline The e·MMC signals' trace length should be as short as possible; it is best kept to less than 2000 mil. The transmission line should be designed so that the conductor is as close to the ground plane as possible. This technique will couple the transmission line tightly to the ground plane and help decouple it from adjacent signals. It's best to widen spacing between signal lines as much as routing restrictions will allow, trying not to bring traces closer than three times the trace width. Figure 6: Trace Width Example W Arc-shaped traces should be used instead of right-angle bends. Figure 7: Trace Shape Not recommended Recommended Recommended There should be NO breaks or voids in the ground plane under or over the high speed signals. PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. TN-FC-35: e·MMC PCB Design Guide PCB Topology and Layout Figure 8: Avoiding Breaks and Voids Return current Return current Slot in image plane Slot in image plane Bad Better The best signaling is obtained when a constant reference plane is maintained. If a reference plane transition cannot be avoided, we recommend using the following techniques. • If the signal reference plane changes from ground plane to power plane, adding capacitors near the via transition site will help support a good return path. • If the signal reference plane changes from ground plane to another ground plane, ground vias should surround all high-speed signals (two ground vias per clock via; one ground via per high speed signal via). PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. TN-FC-35: e·MMC PCB Design Guide PCB Topology and Layout Figure 9: Additional Capacitor for Return Current MLCC Trace Ground plane Power plane Trace Stubs should be kept short to avoid reflections. Stub propagation delay should be kept to <20% of the rise time of the signal. Figure 10: Typical Stub Case Branch PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. TN-FC-35: e·MMC PCB Design Guide Revision History Revision History Rev. B – 01/15 • Updated the Host to Micron e·MMC 5.0 Connection figure Rev. A – 08/14 • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef85c3dc13 tnfc35_eMMC_pcb_design_guide.pdf - Rev. B 01/15 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.
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