The Design Warrior's Guide To FPGAs Warriors

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Cover
Title Page
Copyright Page
Dedication
What's on the CD-ROM?
Contents (hyperlinked)
Preface
Acknowledgments
Chapter 1: Introduction
- What are FPGAs?
- Why are FPGAs of interest?
- What can FPGAs be used for?
- What’s in this book?
- What’s not in this book?
- Who’s this book for?
Chapter 2: Fundamental Concepts
- The key thing about FPGAs
- A simple programmable function
- Fusible link technologies
- Antifuse technologies
- Mask-programmed devices
- PROMs
- EPROM-based technologies
- EEPROM-based technologies
- FLASH-based technologies
- SRAM-based technologies
- Summary
Chapter 3: The Origin of FPGAs
- Related technologies
- Transistors
- Integrated circuits
- SRAMs, DRAMs, and microprocessors
- SPLDs and CPLDs
- ASICs (gate arrays, etc.)
- FPGAs
Chapter 4: Alternative FPGA Architectures
- A word of warning
- A little background information
- Antifuse versus SRAM versus …
- Fine-, medium-, and coarse-grained architectures
- MUX- versus LUT-based logic blocks
- CLBs versus LABs versus slices
- Fast carry chains
- Embedded RAMs
- Embedded multipliers, adders, MACs, etc.
- Embedded processor cores (hard and soft)
- Clock trees and clock managers
- General-purpose I/O
- Gigabit transceivers
- Hard IP, soft IP, and firm IP
- System gates versus real gates
- FPGA years
Chapter 5: Programming (Configuring) an FPGA
- Weasel words
- Configuration files, etc.
- Configuration cells
- Antifuse-based FPGAs
- SRAM-based FPGAs
- Using the configuration port
- Using the JTAG port
- Using an embedded processor
Chapter 6: Who Are All the Players?
- Introduction
- FPGA and FPAA vendors
- FPNA vendors
- Full-line EDA vendors
- FPGA-specialist and independent EDA vendors
- FPGA design consultants with special tools
- Open-source, free, and low-cost design tools
Chapter 7: FPGA Versus ASIC Design Styles
- Introduction
- Coding styles
- Pipelining and levels of logic
- Asynchronous design practices
- Clock considerations
- Register and latch considerations
- Resource sharing (time-division multiplexing)
- State machine encoding
- Test methodologies
Chapter 8: Schematic-Based Design Flows
- In the days of yore
- The early days of EDA
- A simple (early) schematic-driven ASIC flow
- A simple (early) schematic-driven FPGA flow
- Flat versus hierarchical schematics
- Schematic-driven FPGA design flows today
Chapter 9: HDL-Based Design Flows
- Schematic-based flows grind to a halt
- The advent of HDL-based flows
- Graphical design entry lives on
- A positive plethora of HDLs
- Points to ponder
Chapter 10: Silicon Virtual Prototyping for FPGAs
- Just what is an SVP?
- ASIC-based SVP approaches
- FPGA-based SVPs
Chapter 11: C/C++ etc.–Based Design Flows
- Problems with traditional HDL-based flows
- C versus C++ and concurrent versus sequential
- SystemC-based flows
- Augmented C/C++-based flows
- Pure C/C++-based flows
- Different levels of synthesis abstraction
- Mixed-language design and verification environments
Chapter 12: DSP-Based Design Flows
- Introducing DSP
- Alternative DSP implementations
- FPGA-centric design flows for DSPs
- Mixed DSP and VHDL/Verilog etc. environments
Chapter 13: Embedded Processor-Based Design Flows
- Introduction
- Hard versus soft cores
- Partitioning a design into its hardware and software components
- Hardware versus software views of the world
- Using an FPGA as its own development environment
- Improving visibility in the design
- A few coverification alternatives
- A rather cunning design environment
Chapter 14: Modular and Incremental Design
- Handling things as one big chunk
- Partitioning things into smaller chunks
- There’s always another way
Chapter 15: High-Speed Design and Other PCB Considerations
- Before we start
- We were all so much younger then
- The times they are a-changing
- Other things to think about
Chapter 16: Observing Internal Nodes in an FPGA
- Lack of visibility
- Multiplexing as a solution
- Special debugging circuitry
- Virtual logic analyzers
- VirtualWires
Chapter 17: Intellectual Property
- Sources of IP
- Handcrafted IP
- IP core generators
- Miscellaneous stuff
Chapter 18: Migrating ASIC Designs to FPGAs and Vice Versa
- Alternative design scenarios
Chapter 19: Simulation, Synthesis, Verification, etc. Design Tools
- Introduction
- Simulation (cycle-based, event-driven, etc.)
- Synthesis (logic/HDL versus physically aware)
- Timing analysis (static versus dynamic)
- Verification in general
- Formal verification
- Miscellaneous
Chapter 20: Choosing the Right Device
- So many choices
- If only there were a tool
- Technology
- Basic resources and packaging
- General-purpose I/O interfaces
- Embedded multipliers, RAMs, etc.
- Embedded processor cores
- Gigabit I/O capabilities
- IP availability
- Speed grades
- On a happier note
Chapter 21: Gigabit Transceivers
- Introduction
- Differential pairs
- Multiple standards
- 8-bit/10-bit encoding, etc.
- Delving into the transceiver blocks
- Ganging multiple transceiver blocks together
- Configurable stuff
- Clock recovery, jitter, and eye diagrams
Chapter 22: Reconfigurable Computing
- Dynamically reconfigurable logic
- Dynamically reconfigurable interconnect
- Reconfigurable computing
Chapter 23: Field-Programmable Node Arrays
- Introduction
- Algorithmic evaluation
- picoChip’s picoArray technology
- QuickSilver’s ACM technology
- It’s silicon, Jim, but not as we know it!
Chapter 24: Independent Design Tools
- Introduction
- ParaCore Architect
- The Confluence system design language
- Do you have a tool?
Chapter 25: Creating an Open-Source-Based Design Flow
- How to start an FPGA design shop for next to nothing
- The development platform: Linux
- The verification environment
- Formal verification
- Access to common IP components
- Synthesis and implementation tools
- FPGA development boards
- Miscellaneous stuff
Chapter 26: Future FPGA Developments
- Be afraid, be very afraid
- Next-generation architectures and technologies
- Don’t forget the design tools
- Expect the unexpected
Appendix A: Signal Integrity 101
- Before we start
- Capacitive and inductive coupling (crosstalk)
- Chip-level effects
- Board-level effects
Appendix B: Deep-Submicron Delay Effects 101
- Introduction
- The evolution of delay specifications
- A potpourri of definitions
- Alternative interconnect models
- DSM delay effects
- Summary
Appendix C: Linear Feedback Shift Registers 101
- The Ouroboras
- Many-to-one implementations
- More taps than you know what to do with
- Seeding an LFSR
- FIFO applications
- Modifying LFSRs to sequence 2n values
- Accessing the previous value
- Encryption and decryption applications
- Cyclic redundancy check applications
- Data compression applications
- Built-in self-test applications
- Pseudorandom-number-generation applications
- Last but not least
Glossary
About the Author
Index

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