UM10204 I2C Bus Specification And User Manual SPEC
UM10204%20I2C-bus%20specification%20and%20user%20manual
UserManual_i2c
User Manual:
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Page Count: 64
- 1. Introduction
- 2. I2C-bus features
- 3. The I2C-bus protocol
- 3.1 Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols
- 3.1.1 SDA and SCL signals
- 3.1.2 SDA and SCL logic levels
- 3.1.3 Data validity
- 3.1.4 START and STOP conditions
- 3.1.5 Byte format
- 3.1.6 Acknowledge (ACK) and Not Acknowledge (NACK)
- 3.1.7 Clock synchronization
- 3.1.8 Arbitration
- 3.1.9 Clock stretching
- 3.1.10 The slave address and R/W bit
- 3.1.11 10-bit addressing
- 3.1.12 Reserved addresses
- 3.1.13 General call address
- 3.1.14 Software reset
- 3.1.15 START byte
- 3.1.16 Bus clear
- 3.1.17 Device ID
- 3.2 Ultra Fast-mode I2C-bus protocol
- 3.2.1 USDA and USCL signals
- 3.2.2 USDA and USCL logic levels
- 3.2.3 Data validity
- 3.2.4 START and STOP conditions
- 3.2.5 Byte format
- 3.2.6 Acknowledge (ACK) and Not Acknowledge (NACK)
- 3.2.7 The slave address and R/W bit
- 3.2.8 10-bit addressing
- 3.2.9 Reserved addresses in UFm
- 3.2.10 General call address
- 3.2.11 Software reset
- 3.2.12 START byte
- 3.2.13 Unresponsive slave reset
- 3.2.14 Device ID
- 3.1 Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols
- 4. Other uses of the I2C-bus communications protocol
- 5. Bus speeds
- 5.1 Fast-mode
- 5.2 Fast-mode Plus
- 5.3 Hs-mode
- 5.3.1 High speed transfer
- 5.3.2 Serial data format in Hs-mode
- 5.3.3 Switching from F/S-mode to Hs-mode and back
- 5.3.4 Hs-mode devices at lower speed modes
- 5.3.5 Mixed speed modes on one serial bus system
- 5.3.6 Standard, Fast-mode and Fast-mode Plus transfer in a mixed-speed bus system
- 5.3.7 Hs-mode transfer in a mixed-speed bus system
- 5.3.8 Timing requirements for the bridge in a mixed-speed bus system
- 5.4 Ultra Fast-mode
- 6. Electrical specifications and timing for I/O stages and bus lines
- 7. Electrical connections of I2C-bus devices to the bus lines
- 8. Abbreviations
- 9. Legal information
- 10. Contents