V1751/VX1751 UM3356 V1751 User Manual Rev16
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User Manual UM3350 V1751/VX1751 4/8 Channels 10bit 2/1 GS/s Digitizer Rev. 16 - June 12th , 2017 Purpose of this Manual This document contains the full hardware descrip on of the V1751 and VX1751 CAEN digi zers and their principle of opera ng as Waveform Recording Digi zer (basing on the herea er called ”waveform recording firmware”). The reference firmware revision is: 4.14_0.7. For any reference to registers in this user manual, please refer to document [RD1] on the digi zer web page. For any reference to DPP firmware in this user manual, please refer to documents [RD2] and [RD3] present on the firmware web page. Change Document Record Date Revision - 00-15 June 12th , 2017 16 Changes Old manuals are available on request (see Chap. Technical Support). Revised layout and improved text. Symbols, Abbreviated Terms and Notation ADC AMC DAQ DAC DC LVDS PLL ROC TTT USB Analog-to-Digital Converter ADC & Memory Controller Data Acquisi on Digital-to-Analog Converter Direct Current Low-Voltage Differen al Signal Phase-Locked Loop ReadOut Controller Trigger Time Tag Universal Serial Bus Reference Documents [RD1] UM6009 – 751 Registers Descrip on. [RD2] UM2088 – DPP-PSD User Manual. [RD3] UM2764 – DPP-ZLEplus User Manual. [RD4] UM1935 – CAENDigi zer User & Reference Manual. [RD5] UM2091 – CAEN WaveDump User Manual. [RD6] GD2817 – How to make coincidences with CAEN digi zers. [RD7] AN2086 – Synchroniza on of a mul -board acquisi on systems with CAEN digi zers. [RD8] AN2472 – CONET1 to CONET2 migra on. [RD9] GD2512 – CAENUpgrader QuickStart Guide. [RD10] GD2484 – CAENScope Quick Start Guide. [RD11] UM5960 – CoMPASS User Manual. All CAEN documents can be downloaded at: h p://www.caen.it/csite/LibrarySearch.jsp CAEN S.pA. Via Vetraia, 11 55049 Viareggio (LU) - ITALY Tel. +39.0584.388.398 Fax +39.0584.388.959 info@caen.it www.caen.it ©CAEN SpA – 2017 Disclaimer No part of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or otherwise, without the prior wri en permission of CAEN SpA. The informa on contained herein has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifica ons without giving any no ce; for up to date informa on please visit www.caen.it. MADE IN ITALY: We remark that all our boards have been designed and assembled in Italy. In a challenging environment where a compe ve edge is o en obtained at the cost of lower wages and declining working condi ons, we proudly acknowledge that all those who par cipated in the produc on and distribu on process of our devices were reasonably paid and worked in a safe environment (this is true for the boards marked ”MADE IN ITALY”, while we cannot guarantee for third-party manufactures). UM3350 - V1751/VX1751 User Manual rev. 16 3 Index Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change document record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Symbols, abbreviated terms and nota on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Safety No ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 Introduc on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Technical Specifica ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Packaging and Compliancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Temperature Protec on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC chips temperature readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC chips over temperature protec on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 7 Panels Descrip on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 22 8 Func onal Descrip on . . . . . . . . . . . . . . . . Analog Input Stage . . . . . . . . . . . . . . . . DC Offset Individual Se ng . . . . . . . . Clock Distribu on . . . . . . . . . . . . . . . . PLL Mode . . . . . . . . . . . . . . . . . . . . Reducing the Sampling Frequency . . . . . . . Trigger Clock . . . . . . . . . . . . . . . . . . . Output Clock . . . . . . . . . . . . . . . . . . . DES Mode . . . . . . . . . . . . . . . . . . . . Acquisi on Modes . . . . . . . . . . . . . . . . Channel Calibra on . . . . . . . . . . . . Acquisi on Run/Stop . . . . . . . . . . . . Acquisi on Triggering: Samples and Events Mul -Event Memory Organiza on . . . . . Custom size events . . . . . . . . . . Event structure . . . . . . . . . . . . . . . Header . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . Event Format Examples . . . . . . . . Acquisi on Synchroniza on . . . . . . . . Trigger Management . . . . . . . . . . . . . . So ware Trigger . . . . . . . . . . . . . . External Trigger . . . . . . . . . . . . . . . Self-Trigger . . . . . . . . . . . . . . . . . LVDS I/O Trigger . . . . . . . . . . . . . . Trigger coincidence level . . . . . . . . . . 23 23 23 24 25 25 25 25 26 26 26 29 29 31 31 32 32 33 33 34 35 35 35 36 36 37 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UM3350 - V1751/VX1751 User Manual rev. 16 TRG-IN as Gate . . . . . . . . . . . . . . . Trigger distribu on . . . . . . . . . . . . . Example . . . . . . . . . . . . . . . . Mul -board Synchroniza on . . . . . . . . . . Front Panel LVDS I/Os . . . . . . . . . . . . . . Mode 0: REGISTER . . . . . . . . . . . . . Mode 1: TRIGGER . . . . . . . . . . . . . Mode 2: nBUSY/nVETO . . . . . . . . . . . Mode 3: LEGACY . . . . . . . . . . . . . . Analog Monitor . . . . . . . . . . . . . . . . . Trigger Majority Mode . . . . . . . . . . . Test Mode . . . . . . . . . . . . . . . . . Buffer Occupancy Mode . . . . . . . . . . Voltage Level Mode . . . . . . . . . . . . Test Pa ern Generator . . . . . . . . . . . . . . Reset, Clear and Default Configura on . . . . . Global Reset . . . . . . . . . . . . . . . . Memory Reset . . . . . . . . . . . . . . . Timer Reset . . . . . . . . . . . . . . . . . VMEBus Interface . . . . . . . . . . . . . . . . Addressing Capabili es . . . . . . . . . . . Address Reloca on . . . . . . . . . . . . . Data Transfer Capabili es and Events Readout . Block Transfer D32/D64, 2eVME, and 2eSST Chained Block Transfer D32/D64 . . . . . . Single D32 Transfer . . . . . . . . . . . . . Op cal Link Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 41 42 43 45 45 45 46 47 47 48 48 48 49 50 50 50 50 51 51 52 53 53 54 54 55 9 Drivers & Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 56 56 10 So ware Tools . . . . . . . . . . CAENUpgrader . . . . . . . . CAENComm Demo . . . . . . DPP-ZLEplus Control So ware CAEN WaveDump . . . . . . CAEN Scope . . . . . . . . . DPP-PSD Control So ware . . CoMPASS . . . . . . . . . . . . . . . . . . . 58 58 59 60 61 62 63 64 11 HW Installa on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 66 66 12 Firmware and Upgrades . . . . . . Firmware Upgrade . . . . . . . Firmware File Descrip on Troubleshoo ng . . . . . . . . . . . . 67 67 68 68 13 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Returns and Repairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 69 69 . . . . . . . . . . . . . . . . . . . . UM3350 - V1751/VX1751 User Manual rev. 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Figures 6 Fig. 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Fig. 4.1 V1751 model view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Fig. 7.1 Front panel view of V1751 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Fig. 7.2 Rotary and dip switches loca on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fig. 8.1 Analog input diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fig. 8.2 Clock distribu on diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fig. 8.3 Diagram of the ADCcalibra on flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Fig. 8.4 Automa c calibra on at WaveDump first run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Fig. 8.5 Temperature monitoring with manual calibra on in WaveDump so ware . . . . . . . . . . . . . 28 Fig. 8.6 Channel calibra on in DPP-PSD Control So ware . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Fig. 8.7 Trigger Overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fig. 8.8 Event Format in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Fig. 8.9 Block diagram of Trigger management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Fig. 8.10 Self-trigger genera on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Fig. 8.11 Self-trigger rela onship with Majority level = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Fig. 8.12 Self-trigger rela onship with Majority level = 1 and TTVAW ̸= 0. . . . . . . . . . . . . . . . . . . . 38 Fig. 8.13 Self-trigger rela onship with Majority level = 1 and TTVAW = 0. . . . . . . . . . . . . . . . . . . . 39 Fig. 8.14 Trigger configura on of TRG-OUT front panel connector. . . . . . . . . . . . . . . . . . . . . . . . 40 Fig. 8.15 Majority logic (2 channels over-threshold; bit[6]=0 register address 0x8000). . . . . . . . . . . . . 47 Fig. 8.16 FPGA Test Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Fig. 8.17 A24 addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Fig. 8.18 A32 addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Fig. 8.19 CR/CSR addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Fig. 8.20 So ware reloca on of base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Fig. 8.21 Example of BLT readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Fig. 9.1 Drivers and so ware layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Fig. 10.1 CAENUpgrader Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Fig. 10.2 CAENComm Demo Java and LabVIEW graphical interface . . . . . . . . . . . . . . . . . . . . . . 59 Fig. 10.3 Screen-shots of DPP-ZLEplus Control So ware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Fig. 10.4 CAEN WaveDump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Fig. 10.5 CAENScope main frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Fig. 10.6 CAEN DPP-PSD Control So ware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Fig. 10.7 CoMPASS so ware tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Fig. 11.1 Front panel LEDs status at power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 UM3350 - V1751/VX1751 User Manual rev. 16 List of Tables Tab. 1.1 Table of models and related items. Note that the memory size is expressed as MS/ch, where M = 1000 · 1000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tab. 3.1 Specifica on table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Tab. 5.1 Power requirements table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Tab. 8.1 Buffer organiza on of 751 family series. For each value of buffer size it is reported the memory size and the number of samples of one buffer, where k = 1024 and M = 1024 · 1024. . . . . . . . . Tab. 8.2 Pa ern/Trg Op ons configura on table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tab. 8.3 Front Panel LVDS I/Os default se ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tab. 8.4 Features descrip on when LVDS group is configured as INPUT . . . . . . . . . . . . . . . . . . . . Tab. 8.5 Features descrip on when LVDS group is configured as OUTPUT . . . . . . . . . . . . . . . . . . 31 32 43 44 44 UM3350 - V1751/VX1751 User Manual rev. 16 7 Safety No ces CAUTION: this product needs proper cooling. USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING THE BOARD MAY DEGRADE ITS PERFORMANCES! CAUTION: this product needs proper handling. V1751/VX1751 DO NOT SUPPORT LIVE INSERTION (HOT SWAP)! REMOVE OR INSERT THE BOARD WHEN THE VME CRATE IS POWERED OFF! ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE! 8 UM3350 - V1751/VX1751 User Manual rev. 16 1 Introduc on The V1751 is a 1-unit wide VME 6U module housing a 8 Channel 10 bit 1 GS/s Flash ADC Waveform Digizer with 1 Vpp input dynamic range on single ended MCX coaxial connectors (see Tab. 1.1). Versions with 200 mVpp single ended customiza on is also available (see Tab. 1.1). The DC offset is adjustable via a 16-bit DAC on each channel in the ±0.5 V (@1 Vpp ), ±100 mV (@200 mVpp ) range. The digi zer can work in Dual Edge Sampling (DES mode) at 2 GS/s. In this mode only half of the channels are enabled for acquisi on. Considering the sampling frequency and bit number, these 751 digi zer family is well suited for fast signals as the ones coming from fast organic, inorganic and liquid scin llators coupled with PMTs or Silicon Photomul plier, Diamond detectors and others. A common acquisi on trigger signal (common to all the channels) can be fed externally via the front panel TRG-IN input connector or via so ware. Alterna vely, each channel is able to generate a self-trigger when the input signal goes under/over a programmable threshold. The trigger from one board can be propagated out of the board through the front panel TRG-OUT connector. During the acquisi on, data stream is con nuously wri en in a circular memory buffer. When the trigger occurs, the digi zer writes addi onal samples for the post trigger and freezes the buffer that can be read by one of the provided readout links. Each channel has a SRAM digital memory (see Tab. 1.1 for the available memory size op ons) divided into buffers of programmable size (1 ÷ 1024). The size of the memory doubles when working in DES mode. The readout (from VMEbus or Op cal link) of a frozen buffer is independent from the write opera ons in the ac ve circular buffer (ADC data storage). V1751 features front panel CLK-IN connector as well as an internal PLL for clock synthesis from internal/external references. Mul -board synchroniza on is supported, so all V1751 can be synchronized to a common clock source ensuring Trigger Time Stamps alignment. Once synchronized, all data will be aligned and coherent across mul ple V1751 boards. CLK-IN / CLK-OUT connectors allow for a Daisy-chained clock distribu on. 16 general purpose LVDS I/Os FPGA-controlled can be programmed for Busy, Data Ready, Memory Full, or Individual Trig-Out management. An Input Pa ern (external signal) can be provided on the LVDS I/Os to be latched to each trigger as an event marker (see Sec. Front Panel LVDS I/Os). An analog output (MON/Σ) from internal 12-bit 125-MHz DAC, controlled by the FPGA, allows the user to reproduce four types of outgoing informa on: Trigger Majority, Test Pulses, Memory Occupancy, Voltage Level (see Sec. Analog Monitor). V1751 is equipped with a VME64 interface (VM64X in case of VX1751) where the data readout can be performed in Single Data Transfer (D32), 32/64-bit Block Transfer (BLT, MBLT, 2eVME. 2eSST) and 32/64-bit Chained Block Transfer (CBLT). The module houses Op cal Link interface (CAEN proprietary CONET protocol) suppor ng transfer rate up to 80 MB/s and offers daisy chain capability. Therefore, it is possible to connect up to 8 ADC modules to a single A2818 Op cal Link Controller, or up to 32 using a 4-link A3818 version (Mod. A2818/A3818, see Tab. 1.1). VME and Op cal Link accesses take place on independent paths and are handled by the on-board controller, therefore when accessed through Op cal Link the board can be operated outside the VME Crate. In addi on to the waveform recording firmware, CAEN provides for this digi zer two types of Digital Pulse Processing firmware (DPP): • Pulse Shape Discrimina on (DPP-PSD) [RD2], which combines the func onali es of a digital QDC (charge integra on) and discriminator of different shapes for par cle iden fica on. • Zero Length Encoding (DPP-ZLEplus) [RD3], for the Zero suppression and data reduc on. These special firmware make the digi zer an enhanced system for Physics Applica ons. UM3350 - V1751/VX1751 User Manual rev. 16 9 Board Model V1751 V1751C WPERS0175102 DPP Firmware DDP-PSD 8ch DDP-ZLE 8ch Related Products A2818 A3818A A3818B A3818C V1718 V1718LC VX1718 VX1718LC V2718 V2718LC VX2718 VX2718LC V2718LC KIT V2718 KIT V2718 KIT-B VX2718LC KIT VX2718 KIT VX2718 KIT-B Accessories A317 A318 A654 A654 KIT4 A654 KIT8 A659 A659 KIT4 A659 KIT8 AI2730 AI2720 AI2705 AI2703 AY2730 AY2720 AY2705 Descrip on 4/8 Ch. 10 bit 2/1 GS/s Digi zer: 3.6/1.8MS/ch, EP3C16, SE 4/8 Ch. 10 bit 2/1 GS/s Digi zer: 28.8/14.4MS/ch, EP3C16, SE x751 Customiza on - 200mVpp Input Range, SE Descrip on DDP-PSD Digital Pulse Processing for Pulse Shape Discrimina on (8ch x751) Digital Pulse Processing Zero Length Encoding for (8ch x 751) Descrip on A2818 – PCI Op cal Link (Rhos compliant) A3818A – PCIe 1 Op cal Link A3818B – PCIe 2 Op cal Link A3818C – PCIe 4 Op cal Link V1718 - VME-USB 2.0 Bridge V1718LC - VME-USB 2.0 Bridge (Rohs Compliant) VX1718 - VME-USB 2.0 Bridge VX1718LC - VME-USB 2.0 Bridge (Rohs Compliant) V2718 - VME-PCI Bridge V2718LC - VME-PCI Bridge (Rohs compliant) VX2718 - VME-PCI Bridge VX2718LC - VME-PCI Bridge V2718KITLC - VME-PCI Bridge (V2718)+PCI Op cal Link (A2818)+Op cal Fibre 5m duplex (AY2705) (Rohs) V2718KIT - VME-PCI Bridge (V2718) + PCI Op calLink (A2818) + Op cal Fibre 5m duplex (AY2705) V2718KITB - VME-PCI Bridge (V2718) + PCIe Op cal Link (A3818A) + Op cal Fibre 5m duplex (AY2705) VX2718KITLC - VME-PCI Bridge (VX2718)+PCI Op cal Link (A2818)+Op cal Fibre 5m duplex (AY2705) (Rohs) VX2718KIT - VME-PCI Bridge (VX2718) + PCI Op calLink (A2818) + Op cal Fibre 5m duplex (AY2705) VX2718KITB - VME-PCI Bridge (VX2718) + PCIe Op cal Link (A3818A) + Op cal Fibre 5m duplex (AY2705) Descrip on Clock Distribu on Cable SE to Differen al Clock Adapter Single Channel MCX to LEMO Cable Adapter 4 MCX TO LEMO Cable Adapter 8 MCX TO LEMO Cable Adapter Single Channel MCX to BNC Cable Adapter 4 MCX TO BNC Cable Adapter 8 MCX TO BNC Cable Adapter Op cal Fibre 30 m simplex Op cal Fibre 20 m simplex Op cal Fibre 5 m simplex Op cal Fibre 30 cm simplex Op cal Fibre 30 m duplex Op cal Fibre 20 m duplex Op cal Fibre 5 m duplex Tab. 1.1: Table of models and related items. Note that the memory size is expressed as MS/ch, where M = 1000 · 1000. 10 UM3350 - V1751/VX1751 User Manual rev. 16 2 Block Diagram FRONT PANEL x8 (8 channels) DAC AMC [FPGA] ADC & MEMORY CONTROLLER CLK IN CLK OUT MUX OSC CLOCK MANAGER (AD9510) VCXO 1GHz LOCAL BUS BUFFERS VME ADC TRIGGERS & SYNC INPUTS TRG IN TRG OUT S IN MON DAC DIGITAL I/Os ROC [FPGA] - Readout control - VME interface control - Optical link control - Trigger control - External interface control OPTICAL LINK Fig. 2.1: Block Diagram UM3350 - V1751/VX1751 User Manual rev. 16 11 3 Technical Specifica ons GENERAL Form Factor 1-unit wide, 6U VME64 (V1751) and VME64X (VX1751) Channels Connector 8 channels MCX Single ended Weight 535 g Bandwidth 500 MHz Note: EVEN channels must be disconnected in DES mode ANALOG INPUT DIGITAL CONVERSION ADC SAMPLING CLOCK GENERATION DIGITAL I/O MEMORY TRIGGER 12 Impedance (Zin ) 50 Ω Full Scale Range (FSR) 1 Vpp or customizable to 200 mVpp Offset Programmable DAC for DC offset adjustment on each channel in the full range Abs Max Ra ng @1Vpp : 3 Vpp (with Vrail max +3 V or –3 V for any DAC offset value) @200 mVpp : 2 Vpp (with Vrail max +2 V or –2 V for any DAC offset value) Sampling Rate Resolu on 1 GS/s (2 GS/s DES mode) simultaneously on each channel 10 bits Clock source: internal/external On-board programmable PLL provides genera on of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference. CLK-IN (AMP Modu II) CLK-OUT (AMP Modu IV) S-IN (LEMO) AC coupled differen al DC coupled differen al SYNC/START input clock LVDS clock output locked front panel digital input LVDS, ECL, PECL, LVPECL, to ADC sampling clock, NIM/TTL, Zin = 50 Ω CML, Zdiff = 100 Ω Zdiff = 100 Ω TRG-IN (LEMO) TRG-OUT (LEMO) External trigger digital Trigger digital output input NIM/TTL, Rt = 50 Ω NIM/TTL, Zin = 50 Ω 1.835 MS/ch (3.6 MS/ch in DES mode) or 14.4 MS/ch (28.8 MS/ch in DES mode) (see Tab. 1.1) Mul Event Buffer divisible into 1 ÷ 1024 Independent read and write access Programmable event size and pre/post trigger Trigger Propaga on Trigger Source TRG-OUT programmable digital output - Self-trigger: channel over/under-threshold for common (waveform recording firmware) or Trigger Time Stamp individual (DPP firmware only) trigger Waveform recording FW/DPP-ZLEplus: genera on 31-bit counter – 16 ns resolu on - 17 s - External-trigger: common trigger by TRG IN range; 48 bit fw extension connector or individual by LVDS connector DPP-PSD: 32-bit counter – 1 ns (DPP firmware only) resolu on (1 ps fine me stamp - So ware-trigger: common trigger by resolu on with dCFD) - 4 s range; 48 so ware command bit fw extension; 64 bit sw extension UM3350 - V1751/VX1751 User Manual rev. 16 SYNCHRONIZATION ADC & MEMORY CONTR. COMMUNICATION INTERFACE ANALOG MONITOR LVDS I/O SUPPORTED DPP FIRMWARE FIRMWARE UPGRADE Clock Propaga on Daisy chain: through CLK-IN/CLK-OUT connectors One-to-many: clock distribu on from an external clock source on CLK-IN connector Clock Cable delay compensa on Acquisi on Synchroniza on Sync, Start/Stop through digital I/O (S-IN or TRG-IN input / TRG-OUT output) Trigger Time Stamps Alignment By S-IN input connector Altera Cyclone EP1C20 (one FPGA serves 1 channel) Op cal Link VME CAEN CONET proprietary protocol VME 64X compliant Up to 80 MB/s transfer rate Data transfer mode: BLT32, MBLT64 Daisy-chain: it is possible to connect up to 8 or (70 MB/s using CAEN Bridge), 32 ADC modules to a single Op cal Link CBLT32/64, 2eVME, 2eSST (up to 200 Controller (respec vely A2818 or A3818) MB/s) 12-bit / 125 MHz DAC FPGA controlled; four opera ng modes: - Test pulses: 1 Vpp ramp generator - Majority signal: propor onal to the nr. Of channels under/over threshold (steps of 125 mV) - Memory Occupancy signal: propor onal to the Mul Event Buffer Occupancy (1 buffer 1mV) - Voltage level: programmable output voltage level 16 general purpose LVDS I/O controlled by the FPGA: Busy, Data Ready, Memory full, Individual Trig-Out and other func ons can be programmed An Input Pa ern from the LVDS I/O can be associated to each trigger as an event marker DPP-PSD for the Pulse Shape Discrimina on DPP-ZLEplus for the Zero Length Encoding Firmware can be upgraded via VMEbus/Op cal Link SOFTWARE General purpose C libraries, configura on tools, readout so ware (Windows® and Linux® support). LabVIEW™ VIs and demos for Windows® only POWER CONSUMPTIONS 6.5 A @ +5V; 200 mA @ +12V, 300 mA @ -12V Tab. 3.1: Specifica on table UM3350 - V1751/VX1751 User Manual rev. 16 13 4 Packaging and Compliancy V1751/VX1751 modules are 1-unit wide, 6U VME64/VME64X boards. Fig. 4.1: V1751 model view 14 UM3350 - V1751/VX1751 User Manual rev. 16 CAUTION: to manage the product, consult the opera ng instruc ons provided. A POTENTIAL RISK EXISTS IF THE OPERATING INSTRUCTIONS ARE NOT FOLLOWED! CAUTION: this product needs proper cooling. USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING THE BOARD MAY DEGRADE ITS PERFORMANCES! CAUTION: this product needs proper handling. V1751/VX1751 DO NOT SUPPORT LIVE INSERTION (HOT SWAP)! REMOVE OR INSERT THE BOARD WHEN THE VME CRATE IS POWERED OFF! ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE! CAEN provides the specific document “Precau ons for Handling, Storage and Installaon”, available in the documenta on tab of the product’s web page, that is mandatory to read before operating with CAEN equipment. UM3350 - V1751/VX1751 User Manual rev. 16 15 5 Power Requirements The table below resumes the V1751/VX1751 power consump ons per relevant power supply rail. MODULE V1751/VX1751 +5 V 6.5 A SUPPLY VOLTAGE +12 V 200 mA -12 V 300 mA Tab. 5.1: Power requirements table 16 UM3350 - V1751/VX1751 User Manual rev. 16 6 Temperature Protec on ADC chips temperature readout The V1751 features an internal ADC temperature monitoring system, useful in order to es mate the steady thermal state of the ADCs and to perform the calibra on procedure (see Sec. Channel Calibra on). Since each ADC manages two channels (0-1, 2-3. 4-5, 6-7) iden cal temperature values will be found for couples of channels; such values can be readout using register 0x1nA8. ADC chips over temperature protection Each ADC will be automa cally powered off whenever the core temperature reaches 90°C. The relevant channels will not therefore par cipate any more to data event, and bit[7] and bit[8] of register 0x1n88 will set to 1 (channel power down and over-temperature flags respec vely). When the ADC core temperature decreases under 65°C, the bit[8] will return to 0, and the relevant channels can be restored to normal opera on following these steps: • Wait un l bit 8 of 0x1n88 register returns to 0 • Set bit[0] = 0 of 0x1n9C; bit[7] of 0x1n88 will return to 0. • Perform a calibra on procedure on the restored channels (see Sec. Channel Calibra on) ´ UM3350 - V1751/VX1751 User Manual rev. 16 17 7 Panels Descrip on Fig. 7.1: Front panel view of V1751 18 UM3350 - V1751/VX1751 User Manual rev. 16 Front Panel ANALOG INPUT FUNCTION Input connectors from CH0 to CH7 receive the input analog signals. ELECTRICAL SPECS Input dynamics: 1 Vpp Input impedance (Zin ): 50 Ω. Absolute max analog input voltage: @1 Vpp : 3 Vpp (with Vrail max +3 V or -3 V) @200 mVpp : 2 Vpp (with Vrail max +2 V or –2 V) for any DAC offset value. MECHANICAL SPECS Series: MCX connectors. Type: CS 85MCX-50-0-16. Manufacturer: SUHNER Suggested plug: MCX-50-2-16 type. Suggested cable: RG174 type. Note: 200 (50 Ω) mVpp input range is available by ordering op on (see Tab. 1.1). CLOCK IN/CLOCK OUT FUNCTION Input and output connectors for the external clock. ELECTRICAL SPECS Sign. type: differen al (LVDS, ECL, PECL, LVPECL, CML). CAEN provides single ended-to-differen al A318 cable adapter (see Tab. 1.1) for CLK-IN. Coupling: AC (CLK-IN); DC (CLK-OUT). Zdiff : 100 Ω. MECHANICAL SPECS Series: AMPMODU connectors. Type: 3-102203-4 (3-pin). Manufacturer: AMP Inc. PINOUT CLK IN LED (GREEN): indicates the external clock is enabled. TRG-IN / TRG-OUT / S-IN FUNCTION • TRG-OUT: digital output connector to propagate: - probes from the mezzanines; - S-IN signal. • TRG-IN: digital input connector for the external trigger. • S-IN: SYNC/START/STOP digital input connector configurable as reset of the me stamp (see Sec. Reset, Clear and Default Configura on) or to start/stop the acquisi on (see Sec. Acquisi on Run/Stop). MECHANICAL SPECS Series: 101 A 004 connectors. Type: DLP 101 A 004-28. Manufacturer: FISCHER. Alterna vely: Type: EPL 00 250 NTN. Manufacturer: LEMO. ELECTRICAL SPECS Signal level: NIM or TTL. TRG-IN/S-IN Input impedance (Zin ): 50 Ω TRG-OUT requires 50 Ω termina on. TTL (GREEN), NIM (GREEN): indicate the standard TTL or NIM set for TRG-OUT, TRG-IN, and S-IN. UM3350 - V1751/VX1751 User Manual rev. 16 19 OPTICAL LINK PORT FUNCTION Op cal LINK connector for data readout and flow control. Daisy chainable. Compliant with Mul mode 62.5/125 μm cable featuring LC connectors on both sides. MECHANICAL SPECS Series: SFF Transceivers. Type: FTLF8519F-2KNL (LC connectors). Manufacturer: FINISAR. ELECTRICAL SPECS Transfer rate: up to 80 MB/s. PINOUT LINK LEDs (GREEN/YELOW): right LED (GREEN) indicates the network presence, while le LED (YELLOW) signals the data transfer ac vity. MON / Σ FUNCTION Analog Monitor output connector with 4 programmable modes (see Sec. Analog Monitor): - Trigger Majority - Test Pulses - Memory Occupancy - Voltage Level MECHANICAL SPECS Series: 101 A 004 connectors. Type: DLP 101 A 004-28. Manufacturer: FISCHER. Alterna vely: Type: EPL 00 250 NTN. Manufacturer: LEMO. ELECTRICAL SPECS 12-bit (125 MHz) DAC output. 1 Vpp on Rt = 50 Ω DIAGNOSTICS LEDs DTACK (GREEN): indicates there is a VME read/write access to the board; PLL LOCK (GREEN): indicates the PLL is locked to the reference clock; PLL BYPS (GREEN): not used; RUN (GREEN): indicates the acquisi on is running (data taking). See Sec. Acquisi on Run/Stop; TRG (GREEN): indicates the trigger is accepted; DRDY (GREEN): indicates the event/data is present in the Output Buffer; BUSY (RED): indicates all the buffers are full for at least one channel. 20 UM3350 - V1751/VX1751 User Manual rev. 16 LVDS I/Os CONNECTOR FUNCTION 16-pin connector with programmable general purpose LVDS I/O signals organized in 4 independent signal groups: 0÷3; 4÷7; 8÷11; 12÷15. In/Out direc on is so ware controlled. Different selectable modes (see Sec. Front Panel LVDS I/Os): - Register - Trigger - nBusy/nVeto - Legacy MECHANICAL SPECS Series : TE - AMPMODU Mod II Series Type: 5-826634-0 34 pin (lead spacing: 2.54 mm; row pitch: 2.54 mm) Manufacturer: AMP Inc. ELECTRICAL SPECS Level: differen al LVDS Zdiff : 100 Ω LVDS I/O LEDs (GREEN): Each LED close to a 4-pin group lights on if the pins are set as outputs. LABELS Two blue labels on each inser on/extrac on handle on the VME front panel report: - Manufacturer name and board’s model - Brief func onal descrip on of the module A li le silver label on the bo om of the VME board’s front panel reports: - 4-digit Serial Number (S/N) UM3350 - V1751/VX1751 User Manual rev. 16 21 Internal Components B C A Fig. 7.2: Rotary and dip switches loca on 22 A SW3,4,5,6: ”Base Address [31:16]” Type: Rotary Switches B SW2: “CLOCK SOURCE” INT/EXT Type: Dip Switch C SW7: ”FW” BKP/STD Type: Dip Switch Func on: Set the VME Base Address of the module Func on: Selects the clock source (External or Internal) Func on: Selects ”Standard” (STD) or ”Backup” (BKP) FLASH page as first to be read at power-on to load the FW on the FPGAs (default posi on is STD); see Sec. Firmware Upgrade UM3350 - V1751/VX1751 User Manual rev. 16 8 Func onal Descrip on Analog Input Stage Input dynamic is 1 Vpp ; 200 mVpp version is available upon request (see Tab. 1.1). In order to preserve the full dynamic range with unipolar input signal, posi ve or nega ve, it is possible to add a DC offset by means of a 16 bit DAC, which is up to ± 0.5 V @ 1 Vpp and ± 0.1 V @ 200 mVpp Ṫhe input bandwidth ranges from DC to 500 MHz (with 2nd order linear phase an -aliasing low pass filter). Input Dynamic Range: 1 Vpp Input MCX 50 OpAmp ADC FPGA Vref DAC +1.00 10 bit 16 bit Positive Unipolar DAC = FSR +0.50 0 -0.50 -1.00 Negative Unipolar DAC = 0 Bipolar DAC = FSR/2 Fig. 8.1: Analog input diagram DC Offset Individual Setting Se ng the DC offset for channel n requires a write access at register addresses 0x1n98. Wri ng at 0x8098, the DC offset will apply to all channels at once. Refer to [RD1] for more details. UM3350 - V1751/VX1751 User Manual rev. 16 23 Clock Distribution 1 GHz VCXO-CLK CLK Source DIP-SW EXT Feedback loop VCXO INT AD9510 MUX CLK-IN MEZZANINES (x4) REF-CLK REFIN Rdiv CLK2 Phase Detector Ndiv Charge Pump SCLK MUX CLK1 INTCLK SAMP-CLK0 Sdiv Sdiv SPI CTRL DFF Ldiv Ldel Odiv Odel TRG IN Trigger & Sync Logic TRG OUT Optical Link/ VME Interface VME Optical Link FPGA (ROC) Local Bus Interface CH1 ADC RAMCLK DATA SYNC SRAM TRIGGER SELF-TRGs SYNC S IN CLKOUT Acquisition & Memory Control Logic TRG-CLK SyncB DATA SAMP-CLK3 OUT-CLK CLK-OUT CH0 ADC SCLK SAMP-CLK2 Sdiv OSC CLKOUT SAMP-CLK1 Sdiv SYNCB 50MHz DATA FANOUT 8 LOCAL BUS FIFO Local Bus Interface FPGA (AMC) OSC-CLK Fig. 8.2: Clock distribu on diagram The clock distribu on of the module takes place on two domains: OSC-CLK and REF-CLK. OSC-CLK is a fixed 50-MHz clock coming from a local oscillator which handles VMEbus, Op cal Link and Local Bus, that takes care of the communica on between motherboard and mezzanines (see red traces in Fig. 8.2). REF-CLK handles ADC sampling, trigger logic, and acquisi on logic (samples storage into RAM, buffer freezing on trigger) through a clock chain. REF-CLK can be either an external (via the front panel CLK-IN connector) or an internal (via the 50-MHz local oscillator) source. In the la er mode, OSC-CLK and REF-CLK will be synchronous (the opera on mode remains the same). REF-CLK clock source selec on can be done by an on-board dedicated dip switch (see Fig. 7.2) between the following modes: • INT mode (default) means REF-CLK is the 50 MHz of the local oscillator (REF-CLK = OSC-CLK); • EXT mode means REF-CLK source is the external frequency fed on CLK-IN connector. The external clock signal must be differen al (LVDS, ECL, PECL, LVPECL, CML) with a ji er lower than 100 ppm (see Chap. Technical Specifica ons). CAEN provides the A318 cable to adapt single ended signals coming from an external clock unit into the differen al CLK-IN connector (see Tab. 1.1). The V1751 is equipped with a phase-locked-loop (PLL) and clock distribu on device, AD9510. It receives the REF-CLK and generates the sampling clock for ADCs and the mezzanine FPGA (SAMP-CLK0 up to SAMPCLK3), as well as the trigger logic synchroniza on clock (TRG-CLK) and the output clock (CLK-OUT). AD9510 configura on can be changed and stored into non-vola le memory. Changing the AD9510 configura on is primarily intended to be used for external PLL reference clock frequency change (see Sec. PLL Mode). The V1751 locks to an external 50 MHz reference clock with default AD9510 configura on. Refer to the AD9510 datasheet for more details: h p://www.analog.com/UploadedFiles/Data_Sheets/AD9510.pdf (in case the ac ve link above does not work, copy and paste it on the internet browser) 24 UM3350 - V1751/VX1751 User Manual rev. 16 PLL Mode The Phase Detector within the AD9510 device allows to couple REF-CLK with an external VCXO, which provides the nominal ADCs frequency (1 GS/s). As introduced in Sec. Clock Distribu on, the source of the REF-CLK signal (see Fig. 8.2) can be external on CLK-IN front panel connector or internal from the 50 MHz local oscillator. Programming the REF-CLK source internal or external can be performed by ac ng on the on-board dip switch SW2 (see Sec. Internal Components). The following op ons are allowed: 1. 50 MHz internal clock source - this is the standard opera on mode: the AD9510 dividers do not require to be reprogrammed (the digi zer works in the AD9510 default configura on). The clock source selec on dip switch SW2 is in default INT mode. REF-CLK = OSC-CLK. 2. 50 MHz external clock source - in this case, the clock source is taken from an external device; the AD9510 dividers do not need to be reprogrammed as the external frequency is the same as the default one. The clock source selec on dip switch must be set in EXT mode. CLK-IN = REF-CLK = OSC-CLK. 3. External clock source different from 50 MHz - the clock source is externally provided as in point 2, but the AD9510 dividers must now be reprogrammed to lock the the VCXO to the new REF-CLK in order to provide out the nominal sampling frequency at 1 GS/s. The clock source selec on dip switch must be set in EXT mode. CLK-IN = REF-CLK ̸= OSC-CLK. If the digi zer is locked, the PLL-LOCK front panel LED must be on. Note: the user can configure the clock parameters, generate the PLL programming file and load it on the board by using the CAENUpgrader so ware tool (see Chap. So ware Tools). Reducing the Sampling Frequency In case the board is required to work at a sampling frequency (SAMP-CLK) lower than the nominal, it can be achieved by reprogramming the AD9510 dividers. REF-CLK can be configured as in Sec. PLL Mode. Not all the frequencies are admi ed and a lower frequency limit must be considered, due to the internal electronics. Please contact CAEN (see Sec. Technical Support) to check the feasibility. Trigger Clock The TRG-CLK logic works at 125 MHz, equal to 1/8 of the sampling frequency: TRG-CLK = 1/8· SAMPL-CLK. Eight samples of trigger “uncertainty” occurs over the acquisi on window (16 samples uncertainty in DES mode). Output Clock The AD9510 output can be available on the front panel CLK-OUT connector (see Fig. 8.2). This op on is par cularly useful in case of mul -board synchroniza on to propagate the clock reference source in Daisy Chain. This op on can be enabled by the user while configuring the PLL programming file in the CAENUpgrader so ware. UM3350 - V1751/VX1751 User Manual rev. 16 25 DES Mode The board can be programmed to operate in Dual Edge Sampling (DES) mode, at 2 GS/s. DES Mode is configurable by se ng bit[12] = 1 of register 0x8000 (see [RD1]). Note: Only even channels are managed when opera ng the digi zer in DES mode. Acquisition Modes Channel Calibration The module performs a self-calibra on of the ADCs at its power-on. Anyway, in order to achieve the best performance, the calibra on procedure is recommended to be executed by the user, on command, a er the ADCs have stabilized their opera ng temperature. The calibra on will not need to be repeated at each run unless the opera ng temperature changes significantly, or clock se ngs are modified (e.g. switching from internal to external clock). The diagram below synthesises the flow for a proper calibra on: POWER-ON BOARD CONFIGURATION TEMPERATURE STABILIZATION LOOP CALIBRATE START RUN Temperature or Clock variation Acquisition sessions (n cycles) STOP RUN Fig. 8.3: Diagram of the ADCcalibra on flow. • At low level, the ADCs temperature can be read at the register address 0x1nA8 [RD1], while the calibra on must be performed through register address 0x809C. The following steps are required: – set bit[1] = 0 of register 0x809C; 26 UM3350 - V1751/VX1751 User Manual rev. 16 – set bit[1] = 1 of register 0x809C. The self calibra on process will start simultaneously on each channel of the board and bit[6] of register 0x1n88 will be set to 0; – poll bit[6] of register 0x1n88 un l it returns to 1 (few milliseconds); – set again bit[1] = 0 of register 0x809C. Steps in case of DES mode are: – – – – – make sure that EVEN channels are disconnected; disable EVEN channels; enable DES mode by se ng bit[12] = 1 of register 0x8000; set bit[1] = 0 of register 0x809C; set bit[1] = 1 of register 0x809C. The self calibra on process will start simultaneously on each channel of the board and bit[6] of register 0x1n88 will be set to 0; – poll bit[6] of register 0x1n88 un l it returns to 1 (few milliseconds); – set again bit[1] = 0 of register 0x809C. Note: Whenever switching from Normal mode to DES mode and vice-versa, the ADC calibra on must be repeated. Note: It is normally not required to calibrate a er a board reset but, if a Reset command is intenonally issued to the digi zer (write access at register address 0xEF24) to be directly followed by a calibra on procedure, it is recommended to wait for the board to reach stable condi ons (indicavely 100 ms) before star ng the calibra on. Note: At power-on, a Sync command is also issued by the firmware to the ADCs to synchronize all of them to the board’s clock. In the standard opera ng, this command is not required to be repeated by the user. If a Sync command is inten onally issued (write access at register address 0x813C), the user must consider that a new calibra on procedure is needed for a correct board opera ng. • At the library level, developers can exploit the CAENDigi zer library (see Sec. Libraries) dedicated rou nes which are ReadTemperature() func on for temperature readings and the Calibrate() func on which executes the channel calibra on steps above described. Note: Star ng from CAENDigi zer release 2.6.1, the Reset() func on has been modified so that it no longer includes the channel calibra on rou ne implemented in the code. This calibra on must be performed on command by the dedicated Calibrate() func on. Please, see the Library user manual for reference ([RD4]). • At so ware level, CAEN manages the command channel calibra on in different readout so ware (please, refer the relevant so ware User Manual for details). ♢ WaveDump 1. Lauch WaveDump. This so ware performs an automa c ADC calibra on and displays a message when it is completed (see Fig. 8.4). This allows the user to start using the program sure Fig. 8.4: Automa c calibra on at WaveDump first run that the digi zer has been calibrated at least once. UM3350 - V1751/VX1751 User Manual rev. 16 27 NOTE THAT: If SKIP_STARTUP_CALIBRATION parameter is set to YES in WaveDump configura on file, the automa c start-up calibra on is not performed and no message is displayed 2. At any me, the user can check the channel temperatures (with the acquisi on not running) by issuing mul ple “m” commands from the keyboard. 3. In case of significant varia ons, issuing a “c” command provokes a manual channel calibra on to be executed (see Fig. 8.5). Fig. 8.5: Temperature monitoring with manual calibra on in WaveDump so ware 4. A new acquisi on can start. Please, refer to WaveDump User Manual for complete so ware descrip on ([RD5]). ♢ DPP-PSD Control So ware 1. Launch DPP-PSD Control So ware 2. Connect to the digi zer 3. Before to start the acquisi on, go to the “Stats” tab and monitor the channel temperatures displayed in the relevant column un l you see they don’t vary significantly 4. Go to the “General” tab and press the “Calibrate” bu on 5. Start the acquisi on Fig. 8.6: Channel calibra on in DPP-PSD Control So ware 28 UM3350 - V1751/VX1751 User Manual rev. 16 Acquisition Run/Stop The acquisi on can be started and stopped in different ways, according to bits[2:0] of register 0x8100 [RD1]: - SW CONTROLLED (bits[1:0] = 00): Start and Stop take place by so ware command. Bit[2] = 0 means stopped, while bit[2] = 1 means running. - S-IN CONTROLLED (bits[1:0] = 01): bit[2] = 1 arms the acquisi on and the Start is issued as the S-IN signal is set high and the Stop occurs when it is set low. If bit[2] = 0 (disarmed), the acquisi on is always off. - FIRST TRIGGER CONTROLLED (bits[1:0] = 10): bit[2] = 1 arms the acquisi on and the Start is issued on the first trigger pulse (rising edge) on the TRG-IN connector. This pulse is not used as a trigger; actual triggers start from the second pulse on TRG-IN. The Stop acquisi on must be SW controlled (i.e. reset of bit[2]). - LVDS I/Os CONTROLLED: this mode acts like the S-IN CONTROLLED (bits[1:0] = 01), but using the configurable features of the signals on the LVDS I/Os connector (see Sec. Front Panel LVDS I/Os). Acquisition Triggering: Samples and Events When the acquisi on is running, a trigger signal allows to: - store a 31-bit counter value of the Trigger Time Tag (TTT). The counter (represen ng a me reference), like the Trigger Logic Unit (see Fig. 8.2), operates at a frequency of 125 MHz (i.e. 8 ns, that is to say 8 ADC clock cycles). Due to the way acquired data is wri en into the board internal memory (i.e. in 4-sample bunches), the TTT counter is read every 2 trigger logic clock cycles, which means the trigger me stamp resolu on results in 16 ns (i.e. 62.5 MHz). Basing on that, the LSB of the TTT is always “0”; - increment the EVENT COUNTER; - fill the ac ve buffer with the pre/post-trigger samples, whose number is programmable via register address 0x8114 [RD1]; the acquisi on window width (also referred to as record length) is determined via register addresses 0x800C and 0x8020; then, the buffer is frozen for readout purposes, while the acquisi on con nues on another buffer. An event is therefore composed by the trigger me tag, pre- and post-trigger samples and the event counter. Overlap between “acquisi on windows” may occur (a new trigger occurs while the board is s ll storing the samples related to the previous trigger); this overlap can be either rejected or accepted (programmable via so ware). If the board is programmed to accept the overlapping triggers (by wri ng at register address 0x8000 [RD1]), as the overlapping trigger arrives, the current ac ve buffer is filled up, then the samples storage con nues on the subsequent one. In this case, not all events will have the same size (see Fig. 8.7). A trigger can be refused for the following causes: - Acquisi on is not ac ve. - Memory is FULL and therefore there are no available buffers. - The required number of samples for building the event pre-trigger is not reached yet; this happens typically as the trigger occurs too early either with respect to the RUN Acquisi on command (see Sec. Acquisi on Run/Stop) or with respect to a buffer emptying a er a Memory FULL status (see Sec. Acquisi on Synchroniza on). - The trigger overlaps the previous one and the board is not enabled for accep ng overlapped triggers. As a trigger is refused, the current buffer is not frozen and the acquisi on con nues wri ng on it. The EVENT COUNTER can be programmed in order to be either incremented or not. If this func on is enabled, UM3350 - V1751/VX1751 User Manual rev. 16 29 EVENT n EVENT n+1 EVENT n+2 Recorded TRIGGER Not Recorded PRE POST ACQUISITION WINDOW Overlapping Triggers Fig. 8.7: Trigger Overlap the EVENT COUNTER value iden fies the trigger number sent (but the event number sequence is lost); if the func on is not enabled, the EVENT COUNTER value coincides with the sequence of buffers saved and readout. 30 UM3350 - V1751/VX1751 User Manual rev. 16 Multi-Event Memory Organization Each channel of the V1751 features a SRAM memory to store the acquired events. The memory size in the standard event storage mode is 1.75 MS or 13.73 MS1 , where M = 1024 · 1024, according to the board version (see Tab . 1.1). The channel memory can be divided in a programmable number of buffers, Nb (Nb from 1 up to 1024), by the register address 0x800C [RD1], as described in Tab. 8.1. Note: in case of DES mode, values must be mul plied by 2. Register Value Number of Buffers BUFFER_CODE (Nb ) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 1 2 4 8 16 32 64 128 256 512 1024 Size of one Buffer SRAM 2.33 MB/ch SRAM 18.3 MB/ch (1.75 MS) (13.73 MS) 2.333 MB/ch (1.75 MS) 18.3 MB/ch (13.73 MS) 1.167 MB/ch (896 kS) 9.1 MB/ch (6.8 MS) 597.2 kB/ch (448 kS) 4.6 MB (3.4 MS) 298.6 kB/ch (224 kS) 2.3 MB/ch (1.7 MS) 149.3 kB/ch (112 kS) 1.1 MB/ch (878.7 kS) 74.6 kB/ch (56 kS) 586.2 kB/ch (439.3 kS) 37.3 kB/ch (28 kS) 293.1 kB/ch (219.7 kS) 18.7 kB/ch (14 kS) 146.6 kB/ch (109.8 kS) 9.3 kB/ch (7 kS) 73.3 kB/ch (54.9 kS) 4.7 kB/ch (3.5 kS) 36.6 kB/ch (27.4 kS) 2.3 kB/ch (1.75 kS) 18.3 kB/ch (13.7 kS) Tab. 8.1: Buffer organiza on of 751 family series. For each value of buffer size it is reported the memory size and the number of samples of one buffer, where k = 1024 and M = 1024 · 1024. Having 1.75 MS memory size as reference, this means that each buffer contains Nb = 1024 means 1.75k samples in each buffer). 1.75M/Nb samples (e.g. Custom size events In case an event size less than the buffer size is needed, the user can set the N_LOC value at register address 0x8020 [RD1], where N_LOC is the number of memory loca ons. The size of the event is so forced to be according to the formula: 1 · N_LOC = 7 · NSample (normal mode) 1 · N_LOC = 14 · NSample (DES mode) When N_LOC = 0 the custom size is disabled. Note: The value of N_LOC must be set in order that the relevant number of samples does not exceed the buffer size and it must not be modified while the acquisi on is running. Even using the custom size se ng, the number of buffers and the buffer size are not affected by N_LOC, but they are s ll determined by Nb . The concepts of buffer organiza on and custom size directly affect the width of the acquisi on window (i.e. number of the digi zed waveform samples per event). The Record Length parameter defined in CAEN so ware (such as WaveDump and CAENScope introduced in Chap. So ware Tools) and the Set/GetRecordLength() func ons of the CAENDigi zer library (see Sec. Libraries) rely on these concepts. 1 Memory size is 1.8 MS and 14.4 MS in case of M = 1000 · 1000 UM3350 - V1751/VX1751 User Manual rev. 16 31 Event structure The event can be readout via VMEbus or Op cal Link; data format is 32-bit long word (see Fig. 8.8). An event is structured as: • Header (four 32-bit words) • Data (variable size and format) Header The Header consists of four words including the following informa on: • EVENT SIZE (bits[27:0] of 1st header word) is the total size of the event, i.e. the number of 32-bit long words to be read. • BOARD ID (bits[31:27] of 2nd header word) is the GEO address, meaningful for VME64X modules. • BOARD FAIL FLAG (bit[26] of 2nd header word) implemented from ROC FPGA firmware revision 4.5 on (reserved otherwise), it is set to “1” in consequence of a hardware problem (e.g. PLL unlocking). The user can collect more informa on about the cause by reading at register address 0x8104 and contact CAEN Support Service if necessary (see Chap. Technical Support). • PATTERN (bits[23:8] of 2nd header word) is the 16-bit PATTERN latched on the LVDS I/Os as the trigger arrives. Note: Star ng from revision 4.6 of the ROC FPGA firmware, these 16 bits can be programmed to provide trigger informa on according to the se ng of the bits[22:21] at register address 0x811C (see Tab 8.2). REGISTER 0x811C Bits[22:21] 00 (default) FUNCTIONAL DESCRIPTION PATTERN 01 Event Trigger Source 10 Extended Trigger Time Tag (ETTT) 11 Not used PATTERN /TRG OPTIONS INFORMATION (16 bits in the 2nd header word) Pa ern of the 16 LVDS signals . Indicates the trigger source causing the event acquisi on: Bits[23:19] = 00000 Bit[18] = So ware Trigger Bit[17] = External Trigger Bit[16] = Trigger from LVDS connector Bits[15:8] = Channel self-trigger (refer to Sec. Self-Trigger). A 48-bit Trigger Time Tag (ETTT) informaon is configured, where Bits[23:8] contributes as the 16 most significant bits together to the 32-bit TTT field (4th header word). Note: in the ETTT op on, the overflow bit is not provided. If configured, it acts like “00” se ng. Tab. 8.2: Pa ern/Trg Op ons configura on table. • CHANNEL MASK (bits[7:0] of 2nd header word) is the mask of the channels par cipa ng in the event (e.g. CH5 and CH7 par cipa ng → Channel Mask = 0xA). This informa on must be used by the so ware to acknowledge from which channel the samples are coming (the first event contains the samples from the channel with the lowest number). 32 UM3350 - V1751/VX1751 User Manual rev. 16 Note: in DES mode even channels are automa cally disabled. • EVENT COUNTER (bits[23:0] of 3rd header word) is the trigger counter; it can count either accepted triggers only, or all triggers (bit[3] of register address 0x8100). • TRIGGER TIME TAG (bits[31:0] of 4th header word) is the 31-bit Trigger Time Tag (TTT) informa on (31 bit counter and 32nd bit as roll-over flag), which is the trigger me reference. If the ETTT op on is enabled, then this field becomes the 32 less significant bits of the 48-bit Extended Trigger Time Tag informa on in addi on to the 16 bits (MSB) of the TRG OPTIONS field (2nd event word). Note that, in the ETTT case, the roll-over flag is no more provided. The trigger me tag is reset either at the start of acquisi on, or via front panel signal on S-IN or LVDS I/O connectors, and increments with 250 MHz frequency (i.e. every 8 ADC clock cycles). The TTT value is read at half the frequency (i.e. 125 MHz) so that the specifica ons are 16 ns resolu on and 17 s range (8 ns × (231 – 1)), which can be extended to 625 h (8 ns × (248 – 1)) if ETTT is enabled. Data Data are the stored samples. Data from masked channels are not read. When opera ng in DES mode the EVEN channels are automa cally disabled. Bits[31:30] of the data words iden fies how many samples are stored in the corresponding word. The example in Sec. Event Format Examples shows the case of two samples in the last word. Event Format Examples The event format is shown in the following figure (case of 8 channels enabled): 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 1 0 BOARD ID 7 6 5 4 3 2 EVENT SIZE BF RES 1 PATTERN/TRG OPTIONS RESERVED CHANNEL MASK EVENT COUNTER TRIGGER TIME TAG 1 SAMPLE [2] - CH[0] SAMPLE [1] - CH[0] SAMPLE [0] - CH[0] 1 1 SAMPLE [5] - CH[0] SAMPLE [4] - CH[0] SAMPLE [3] - CH[0] ….. 0 SAMPLE [N-1] - CH[0] SAMPLE [N-2] - CH[0] 1 1 SAMPLE [2] - CH[1] SAMPLE [1] - CH[1] SAMPLE [0] - CH[1] 1 1 SAMPLE [5] - CH[1] SAMPLE [4] - CH[1] SAMPLE [3] - CH[1] ….. 0 SAMPLE [N-1] - CH[1] SAMPLE [N-2] - CH[1] ….. 1 ….. 1 SAMPLE [2] - CH[7] SAMPLE [1] - CH[7] SAMPLE [0] - CH[7] 1 1 SAMPLE [5] - CH[7] SAMPLE [4] - CH[7] SAMPLE [3] - CH[7] ….. 0 SAMPLE [N-1] - CH[7] SAMPLE [N-2] - CH[7] DATA CH7 1 1 DATA CH1 1 0 DATA CH0 1 1 HEADER 1 8 Fig. 8.8: Event Format in Normal Mode UM3350 - V1751/VX1751 User Manual rev. 16 33 Acquisition Synchronization Each channel of the digi zer is provided with a SRAM memory that can be organized in a programmable number Nb of circular buffers (Nb = [1 : 1024], see Tab. 8.1). When the trigger occurs, the FPGA writes further a programmable number of samples for the post-trigger and freezes the buffer, so that the stored data can be read via VME or Op cal Link. The acquisi on can con nue in a new buffer. When all buffers are filled, the board is considered FULL: no trigger is accepted and the acquisi on stops (i.e. the samples coming from the ADC are not wri en into the memory, so they are lost). As soon as one buffer is read out and freed, the board exits the FULL condi on and acquisi on restarts. IMPORTANT: When the acquisi on restarts, no trigger is accepted un l at least the en re buffer is wri en. This means that the dead me is extended for a certain me (depending on the size of the acquisi on window) a er the board exits the FULL condi on. A way to eliminate this extra dead me is by se ng bit[5] = 1 at register address 0x8100 [RD1]. The board is so programmed to enter the FULL condi on when Nb – 1 buffers are filled: no trigger is then accepted, but samples wri ng con nues in the last available buffer. As soon as one buffer is read out and becomes free, the boards exits the FULL condi on and can immediately accept a new trigger. This way, the FULL reflects the BUSY condi on of the board (i.e. inability to accept triggers). Note: when bit[5] = 1, the minimum number of circular buffers to be programmed is Nb = 2. In some cases, the BUSY propaga on from the digi zer to other parts of the system has some latency and it can happen that one or more triggers occur while the digi zer is already FULL and unable to accept those triggers. This condi on causes event loss and it is par cularly unsuitable when there are mul ple digi zers running synchronously, because the triggers accepted by one board and not by other boards cause event misalignment. In these cases, it is possible to program the BUSY signal to be asserted when the digi zer is close to FULL condi on, but it has s ll some free buffers (Almost FULL condi on). In this mode, the digi zer remains able to accept some more triggers even a er the BUSY asser on and the system can tolerate a delay in the inhibit of the trigger genera on. When the Almost FULL condi on is enabled by se ng the Almost FULL level to “X” (register address 0x816C [RD1]), the BUSY signal is asserted as soon as X buffers are filled, although the board s ll goes FULL (and rejects triggers) when the number of filled buffers is Nb or Nb – 1, depending on bit[5] at register address 0x8100 as above described. It is possible to provide the BUSY signal on the digi zer front panel TRG-OUT output (bit[20], bits[19:18] and bits[17:16] at register address 0x811C are involved [RD1]). In case of mul -board setup, the BUSY signal can be propagated among boards through the front panel LVDS I/O connector (see Sec. Front Panel LVDS I/Os). 34 UM3350 - V1751/VX1751 User Manual rev. 16 Trigger Management When opera ng the waveform recording firmware, all board channels share the same trigger (board common trigger), so they acquire an event simultaneously and in the same way (determined number of samples according to buffer organiza on and custom size se ngs, as well as posi on with respect to the trigger defined by the post-trigger). x4 mezzanines Mother Board x2 channels Memory Buffers TRG OUT TRG IN D 8 x8 Q Acquisition Logic TRIGGER ADC SCLK LOCAL TRG 8 Enable Mask 8 Digital Thresholds SW TRG VME Interface Local Bus Interface Fig. 8.9: Block diagram of Trigger management. • So ware Trigger • External Trigger • Self-trigger • Coincidences • TRG-IN as Gate • LVDS I/O Trigger Software Trigger So ware triggers are internally produced via so ware command (write access at register address 0x8108) through VMEbus or Op cal Link. External Trigger A TTL or NIM external signal can be provided to the front panel TRG-IN connector (configurable at register address 0x811C). If the external trigger is not synchronized with the internal clock, a 1-clock period ji er occurs. UM3350 - V1751/VX1751 User Manual rev. 16 35 Self-Trigger Each channel can generate a self-trigger signal (SELF-TRG) when the digi zed input pulse exceeds a configurable threshold set through the register address 0x1n80 [RD1]. The individual self-triggers from all channels are propagated to the central trigger logic on the motherboard (see Fig. 8.9) where they par cipate in logic OR to produce the board common trigger, which is finally distributed back to all channels on the mezzanines causing the event acquisi on (see Sec. Trigger distribu on). THRESHOLD CH0 IN Local Trigger CH0 (Channel Configuration register <6> =0) Local Trigger CH0 (Channel Configuration register <6> =1) Fig. 8.10: Self-trigger genera on. Bits[7:0] of register 0x810C allows the user to program which channel par cipates to the global trigger genera on. LVDS I/O Trigger LVDS I/O specific pins on the front panel dedicated connector can be programmed as trigger inputs and enabled to par cipate in the common trigger genera on with other trigger sources. Refer to Sec. Front Panel LVDS I/Os for details. 36 UM3350 - V1751/VX1751 User Manual rev. 16 Trigger coincidence level Opera ng the waveform recording firmware, the acquisi on trigger is common to the whole board. This common trigger allows the coincidence acquisi on mode to be performed through the Majority opera on. Enabling the coincidences is possible by wri ng at register address 0x810C : • Bits[7:0] enable a specific channel self-trigger to par cipate in the coincidence; • Bits[23:20] set the coincidence window (TTVAW ) linearly in steps of the Trigger clock (8 ns); • Bits[26:24] set the Majority (i.e. Coincidence) level; the coincidence takes place when: Number of enabled channels > Majority level Supposing that bits[7:0] = FF (i.e. all channels are enabled) and bits[26:24] = 01 (i.e. Majority level = 1), a common trigger is issued whenever at least two of the enabled self-triggers are in coincidence within the programmed TTVAW . The Majority level must be smaller than the number of channels enabled via bits[7:0] mask. By default, bits[26:24] = 00 (i.e. Majority level = 0), which means the coincidence acquisi on mode is disabled and the TTVAW is meaningless. In this case, the common trigger is simple OR of the enabled channel self-triggers. Note: in order not to overload the plots but preserve the clearness of concept, only CH0 and CH1 are supposed to be fed with input pulses in the following figures. Fig. 8.11 shows the trigger management in case the coincidences are disabled. CH0 THRESHOLD CH0(enabled) IN SELF-TRG[CH0] CH1 THRESHOLD CH1(enabled) IN SELF-TRG[CH0] OR signal TRIGGER (Maj.lev = 0) Fig. 8.11: Self-trigger rela onship with Majority level = 0. Fig. 8.12 shows the trigger management in case the coincidences are enabled with Majority level = 1 and TTVAW is a value different from 0. Note: with respect to the posi on where the common trigger is generated, the por on of input signal stored depends on the programmed length of the acquisi on window and on the post trigger se ng. UM3350 - V1751/VX1751 User Manual rev. 16 37 CH0 THRESHOLD CH0(enabled) IN SELF-TRG[CH0] CH1 THRESHOLD CH1(enabled) IN SELF-TRG[CH1] OR signal TTVAW TRIGGER (Maj.lev = 1) Fig. 8.12: Self-trigger rela onship with Majority level = 1 and TTVAW ̸= 0. Fig. 8.13 shows the trigger management in case the coincidences are enabled with Majority level = 1 and TTVAW = 0 (i.e. 1 clock cycle). Note: CAEN provides a guide to coincidences including a prac cal example of making coincidences with the waveform recording firmware [RD6]. 38 UM3350 - V1751/VX1751 User Manual rev. 16 CH0 THRESHOLD CH0(enabled) IN SELF-TRG[CH0] CH1 THRESHOLD CH1(enabled) IN SELF-TRG[CH1] OR signal TTVAW TRIGGER (Maj.lev = 1) Fig. 8.13: Self-trigger rela onship with Majority level = 1 and TTVAW = 0. UM3350 - V1751/VX1751 User Manual rev. 16 39 TRG-IN as Gate It is possible to configure TRG-IN as a gate for trigger an -veto func on. The common acquisi on trigger is then issued upon the AND between the external signal on TRG-IN and the other trigger sources but the so ware trigger (i.e. the so ware trigger cannot par cipate in the Trigger as Gate mode). This mode is enabled by se ng bit[27] = 1 of register 0x810C and bit[10] = 1 of register 0x811C . The trigger sources par cipa ng in AND with TRG-IN are configurable through register 0x810C as well. Trigger distribution As described in Sec. Trigger Management, the OR of all the enabled trigger sources, synchronized with the internal clock, becomes the common trigger of the board that is fed in parallel to all channels, consequently causing the capture of an event. By default, only the So ware Trigger and the External Trigger par cipate in the common acquisi on trigger (refer to the red path on top of Fig. 8.14). 0x810C Bits[7:0] 8 8 MASK 1 SW TRG EXT TRG LVDS I/O COMMON ACQUISITON TRIGGER TO THE CHANNELS OR 0x810C Bits[31:29] MASK 2 SW TRG EXT TRG SW TRG LVDS I/O EXT TRG MASK 3 LVDS I/O 8 00 TRG SOURCES SELF-TRG[7:0] 8 0x8110 Bits[31:29] 01 OR 10 PB PROBES OR 11 0x8110 Bits[7:0] 8 MASK 4 TRG-OUT MB PROBES S-IN 00 8 8 0x811C Bits[17:16] 01 AND 10 0x8110 Bits[9:8] 8 MAJORITY 0x8110 Bits[12:10] Fig. 8.14: Trigger configura on of TRG-OUT front panel connector. A Trigger Out signal is also generated on the relevant front panel TRG-OUT connector (NIM or TTL), and allows to extend the trigger signal to other boards. Thanks to its configurability, TRG-OUT can propagate out: - the OR of all the enabled trigger sources (only the So ware Trigger is provided by default, as in the red path of Fig. 8.14); - the OR, AND or MAJORITY exclusively of the channel self-triggers. The registers involved in the TRG-OUT programming are: - Register address 0x8110; - Register address 0x811C. 40 UM3350 - V1751/VX1751 User Manual rev. 16 Example It could be required to start the acquisi on on all the channels of a mul -board system as soon as one of the board channels (board “n”) crosses its threshold. Trigger Out signal is then fed to an external Fan Out logic unit (e.g. CAEN V2495 board); the obtained signal has then to be provided to the external trigger input TRG-IN of all the boards in the system (including the board which generated the Trigger Out signal). In this case, the programming steps to perform are therea er described. 1. Register 0x8110 on board “n”: - Enable the desired self-trigger as Trigger Out signal on board “n” (by bits[7:0] mask). - Disable So ware Trigger, External Trigger and LVDS I/O Trigger as Trigger Out signal on board “n” (bits[31:29] = 000). - Set Trigger Out signal as the OR of the enabled self-trigger on board “n” (bits[9:8] = 00). 2. Register 0x811C on board “n”: - Configure the digi zer to propagates on TRG-OUT the internal trigger sources according to the 0x8110 se ngs (i.e. the enabled self-trigger, in the specific case) on board “n” (bits[17:16] = 00). 3. Register 0x810C on all the boards in the system (including board “n”): - Enable External Trigger to par cipate in the board common acquisi on trigger, disable So ware Trigger , LVDS I/O Trigger and the channel self-triggers (bits[31:29] = 010; bits[7:0] = 00000000) UM3350 - V1751/VX1751 User Manual rev. 16 41 Multi-board Synchronization When mul -board systems are involved in an experiment, it is necessary to synchronize different boards. In this way, the user can acquire from N boards with Y channel each, like if they were just one board with (N x Y) channels. The main issue synchronizing a mul -board system is to propagate the sampling clock among the boards. This is made through input/output daisy chain connec ons among the digi zers. One board must be chosen to be the “master” board that propagates its own clock to the others. A programmable phase shi can adjust possible delays in the clock propaga on. This allows to have both the ADC sampling clock and the me reference in common for all boards. Having the same me reference means that the acquisi on starts/stops at the same me, and that the me stamps of different boards are aligned to the same absolute me. There are several ways to implement the trigger logic. The synchroniza on tool allows to propagate the trigger to all boards and acquire the events accordingly. Moreover, in case of busy state of one or more boards, the acquisi on is inhibited for all boards. As a detailed guide to mul -board synchroniza on, CAEN provides a dedicated Applica on Note [RD7]. 42 UM3350 - V1751/VX1751 User Manual rev. 16 Front Panel LVDS I/Os The V1751 is provided with 16 general purpose programmable LVDS I/O signals (see Chap. Panels Descripon). From the ROC FPGA firmware revision 3.8 on, a more flexible configura on management has been introduced, which allows these signals to be programmed in terms of direc on (INPUT/OUTPUT) and funconality by groups of 4. THE USER MUST SET BIT[8] = 1 AT 0x811C IN ORDER TO ENABLE THE NEW LVDS I/Os CONFIGURATION MODES NOTE ABOUT LVDS I/Os CONFIGURATIONS IMPLEMENTED IN ROC FW RELEASES <3.8 THE WAVEFORM RECORDING FIRMWARE MAKES ALSO AVAILABLE THE OLD CONFIGURATIONS (bit[8] = 0). USERS WHOSE SOFTWARE BASES ON THE OLD LVDS I/Os CONFIGURATION MANAGEMENT CAN REFER TO THE USER MANUAL OF THE RELEVANT DIGITIZER OR CAN CONTACT CAEN FOR INFORMATION (see Chap. Technical Support). SINCE THIS COULD BE NO LONGER GUARANTEED IN THE FUTURE, THE USER IS HEARTLY RECOMMENDED TO TAKE THE NEW CONFIGURATION MANAGEMENT AS REFERENCE! The direc on of the signals are set by the bits[5:2] at register address 0x811C: Bit[2] → LVDS I/O[3:0] Bit[3] → LVDS I/O[7:4] Bit[4] → LVDS I/O[11:8] Bit[5] → LVDS I/O[15:12] Where se ng the bit to 0 enables the relevant signals in the group as INPUT, while 1 enables them as OUTPUT. By default, the new modes are disabled (i.e. bit[8] = 0) and the status of the LVDS I/O signals is congruent with the old Programmed I/O mode (see Tab. 8.3). Nr. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Direc on out out out out out out out out out out out out in in - Func on Ch 0 self-trigger Ch 1 self-trigger Ch 2 self-trigger Ch 3 self-trigger Ch 4 self-trigger Ch 5 self-trigger Ch 6 self-trigger Ch 7 self-trigger Memory Full Event Data Ready Channels Trigger RUN Status Trigger Time Tag Reset (ac ve low) Memory Clear (ac ve low) reserved reserved Descrip on The over-threshold informa on from the relevant channel Memory full flag Board event data ready flag OR of the new event to be read signal Board run flag Reset of the trigger me tag counter Clear command of all channel memories N.A. N.A. Tab. 8.3: Front Panel LVDS I/Os default se ngs. UM3350 - V1751/VX1751 User Manual rev. 16 43 When enabled (i.e. bit[8] = 1), the new management allows each group of 4 signals of the LVDS I/O 16-pin connector to be configured in one of the 4 following modes (according to bits[15:0] at register address 0x81A0): - Mode 0 (bits[n+3:n] = 0000): REGISTER - Mode 1 (bits[n+3:n] = 0001): TRIGGER - Mode 2 (bits[n+3:n] = 0010): nBUSY/nVETO - Mode 3 (bits[n+3:n] = 0011): LEGACY where n = 0, 4, 8, 12. Note: Whatever op on is set, the LVDS I/Os are always latched with the trigger and the relevant status of the 16 signals is always wri en into the header Pa ern field (see Sec. Event structure); the user can then choose to read it out or not. REGISTER TRIGGER LVDS IN [15:12] Reg[15:12] Not available LVDS IN [11:8] Reg[11:8] Not available LVDS IN [7:4] Reg[7:4] Not available LVDS IN [3:0] Reg[3:0] Not available nBUSY/nVETO 15: nRunIn 14: nTriggerIn 13: nVetoIn 12: nBusyIn 11: nRunIn 10: nTriggerIn 9: nVetoIn 8: nBusyIn 7: nRunIn 6: nTriggerIn 5: nVetoIn 4: nBusyIn 3: nRunIn 2: nTriggerIn 1: nVetoIn 0: nBusyIn LEGACY 15: reserved 14: reserved 13: reserved 12: nClear_TTT 11: reserved 10: reserved 9: reserved 8: nClear_TTT 7: reserved 6: reserved 5: reserved 4: nClear_TTT 3: reserved 2: reserved 1: reserved 0: nClear_TTT nBUSY/nVETO 15: nRun 14: nTrigger 13: nVeto 12: nBusy 11: nRun 10: nTrigger 9: nVeto 8: nBusy 7: nRun 6: nTrigger 5: nVeto 4: nBusy 3: nRun 2: nTrigger 3: nVeto 0: nBusy LEGACY 15: Run 14: Trigger 13: DataReady 12: Busy 11: Run 10: Trigger 9: DataReady 8: Busy 7: Run 6: Trigger 5: DataReady 4: Busy 3: Run 2: Trigger 1: DataReady 0: Busy Tab. 8.4: Features descrip on when LVDS group is configured as INPUT REGISTER TRIGGER LVDS OUT [15:12] Reg[15:12] TrigOut_Ch[7:4] LVDS OUT [11:8] Reg[11:8] TrigOut_Ch[3:0] LVDS OUT [7:4] Reg[7:4] TrigOut_Ch[7:4] LVDS OUT [3:0] Reg[3:0] TrigOut_Ch[3:0] Tab. 8.5: Features descrip on when LVDS group is configured as OUTPUT 44 UM3350 - V1751/VX1751 User Manual rev. 16 Mode 0: REGISTER Direc on is INPUT: the logic level of the LVDS I/O signals can be read at register address 0x8118. Direc on is OUTPUT: the logic level of the LVDS I/O signals can be wri en at register address 0x8118. Mode 1: TRIGGER Direc on is INPUT: Not available. Direc on is OUTPUT: the TrgOut_Ch[(n + 3) : n] signals (n = 0, 4) consist of the channel self-triggers coming directly from the mezzanines. Mode 2: nBUSY/nVETO nBusy Signal nBusyIn (INPUT) is an ac ve low signal which, if enabled, is used to generate the nBusy signal (OUTPUT) as below. The Busy signal (fed out on LVDS I/Os or TRG-OUT LEMO connector) is: Almost_Full OR (LVDS_BusyIn AND BusyIn_enable) where - Almost_Full indicates the filling of the Buffer Memory up to a programmable level (12-bit range) set at register address 0x816C; - LVDS_BusyIn is available in nBUSY/nVETO configura on (see Tab. 8.5); - BusyIn_enable is set at register address 0x8100, bit[8]. nVETO Signal Direc on is INPUT: nVETOIn is an ac ve low signal which, if enabled (register address 0x8100, bit[9] = 1), is used to veto the genera on of the common trigger propagated to the channels for the event acquisi on. Direc on is OUTPUT: the nVETO signal is the copy of nVETOIn. nTrigger Signal Direc on is INPUT: nTriggerIn is an ac ve low signal which, if enabled, is a real trigger able to cause the event acquisi on. It can be propagated to TRG-OUT LEMO connector or to the individual triggers. Direc on is OUTPUT: nTrigger signal is the copy of the trigger signal propagated to the TRG-OUT LEMO connector or copy of the acquisi on common trigger. This is selected by bit[16] of the 0x81A0 register. nRun Signal Direc on is INPUT: nRunIn is an ac ve low signal which can be used as Start for the digi zer (register address 0x8100, bits[1:0] = 11). It is possible to program the Start on the level or on the edge of the nRunIn signal (register address 0x8100, bit[11]). Direc on is OUTPUT: nRun signal is the inverse of the internal Run of the board. UM3350 - V1751/VX1751 User Manual rev. 16 45 Mode 3: LEGACY Legacy Mode has been introduced in order the LVDS connector (properly programmed) to be able to feature the same I/O signals available in the ROC FPGA firmware revisions lower than 3.8. nClear_TTT Signal It is the only signal available as INPUT. It is the Trigger Time Tag (TTT) reset, like in the old configura on. Busy Signal The Busy signal is ac ve high and it is exactly the inverse of the nBusy signal (see Sec. Mode 2: nBUSY/nVETO). In case register address 0x816C is set to 0x0 and the BusyIn signal is disabled, the Busy is the FULL signal present in the old configura on. DataReady Signal The DataReady is an ac ve high signal indica ng that the board has data available for readout (the same as the DataReady front panel LED does). Trigger Signal The ac ve high Trigger signal is the copy of the acquisi on trigger (common trigger) sent from the motherboard to the mezzanines (it is neither the signal provided out on the TRG-OUT LEMO connector nor the inverse of the signal sent to the LVDS connector). Run Signal The Run signal is ac ve high and represents the inverse of the nRun signal (see Sec. Mode 2: nBUSY/nVETO). 46 UM3350 - V1751/VX1751 User Manual rev. 16 Analog Monitor The board houses a 12bit (125 MHz) DAC with 0 ÷ 1 V dynamics on a 50 Ω load (see Fig. 2.1), whose input is controlled by the ROC FPGA and the signal output (driving 50 Ω) is available on the MON/Σ output connector. MON output of more boards can be summed by an external Linear Fan In. The DAC control logic implements four opera ng modes according to the value of bits[2:0] at register address 0x8144: - Trigger Majority Mode (0x8144 = 0x0) - Test Mode (0x8144 = 0x1) - Buffer Occupancy Mode (0x8144 = 0x3) - Voltage Level Mode (0x8144 = 0x4) Trigger Majority Mode It is possible to generate a Majority signal with the DAC: a voltage signal whose amplitude is propor onal to the number of channels under/over threshold (1 step = 125 mV); this allows, via an external discriminator, to produce a common trigger signal, as the number of triggering channels has exceeded a par cular threshold. THRESHOLD CH0 IN THRESHOLD CH1 IN 250mV 125mV MAJORITY Fig. 8.15: Majority logic (2 channels over-threshold; bit[6]=0 register address 0x8000). In the example depicted in Fig. 8.15, the MON output provides a signal whose amplitude is propor onal to the number of channels over the trigger threshold. UM3350 - V1751/VX1751 User Manual rev. 16 47 Test Mode In this mode the MON output provides a sawtooth signal with 1 V amplitude and 30.52 kHz frequency. Buffer Occupancy Mode In this mode, MON output connector provides a voltage value increasing, propor onally with the number of buffers filled with events, in fixed steps of 0.976 mV given by: Vmax Nbmax where Vmax ≈ 1 V and Nbmax = 1024 is the Maximum_Number_of_Buffers (i.e. the value of the register address 0x800C, as introduced in Sec. Mul -Event Memory Organiza on). Example: if 0x800C = 0x4 (i.e. 16 buffers), the maximum Buffer Occupancy output voltage level is given by 0.976 mV × 16. This mode allows to test the readout efficiency: in fact, if the average event readout throughput is as fast as trigger rate, then MON out value remains constant; otherwise if MON out value grows in me, this means that readout rate is slower than trigger rate. Star ng from revision 4.9 of the ROC FPGA (motherboard) firmware, it is possible to apply a digital gain to the fixed step, par cularly when the memory is organized in a small number of buffers. The gain can be set as powers of two ranging between 20 = 1 (no gain, which is the default se ng) and 2A , where the exponent is the value to write at register address 0x81B4. Voltage Level Mode In this mode, MON out provides a voltage value programmable via the 12-bit ’N’ parameter wri en in the 0x8138 register, with: Vmon = 1/4096 × N (Volt). 48 UM3350 - V1751/VX1751 User Manual rev. 16 Test Pattern Generator The FPGA AMC can emulate the ADC and write into memory a sawtooth signal for test purposes. It can be enabled via register 0x8000. Fig. 8.16 shows the test ramps for even and odd channels respec vely. Even channel test wave 1200 1023 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 Even channel ramp down zoom 1023 1000 800 600 400 255 200 -0 1021 63 1022 1023 1024 1025 15 1026 3 1027 0 1028 1029 1030 Odd channel test wave 1200 1023 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 Odd channel ramp up zoom 960 1000 1008 1020 1023 768 800 600 400 200 -0 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 Fig. 8.16: FPGA Test Waveform. UM3350 - V1751/VX1751 User Manual rev. 16 49 Reset, Clear and Default Configuration Global Reset Global Reset is performed at power-on of the module or via so ware by write access at register address 0xEF24 . It allows to clear the data off the Output Buffer, the event counter and performs a FPGAs global reset, which restores the FPGAs to the default configura on. It ini alizes all counters to their ini al state and clears all detected error condi ons. Memory Reset The Memory Reset clears the data off the Output Buffer. The Memory Reset can be forwarded via a write access at register address 0xEF28 . In the old LVDS I/O configura on (ROC FPGA revision before 3.8), it is also possible to perform a memory clear by sending a pulse to the front panel dedicated Memory Clear input (see Tab. 8.3). Timer Reset The Timer Reset allows to ini alize the mer which tags an event. The Timer Reset can be forwarded with a pulse sent either to the LVDS I/O dedicated input (see Tab. 8.3 and Sec. Mode 3: LEGACY) or to the S-IN input (leading edge sensi ve). 50 UM3350 - V1751/VX1751 User Manual rev. 16 VMEBus Interface The module is provided with a fully compliant VME64/VME64X interface, whose main features are: • EUROCARD 9U Format • J1/P1 and J2/P2 with either 160 pins (5 rows) or 96 (3 rows) connectors • A24, A32 and CR-CSR address modes • D32, BLT/MBLT, 2eVME, 2eSST data modes • MCST write capability • CBLT data transfers • RORA interrupter • Configura on ROM Addressing Capabilities • Base address: the module works in A24/A32 mode The Base Address of the module is selected through four rotary switches (see Fig. 7.2), then it is validated only with either a power-ON cycle or a System Reset (see Sec. Reset, Clear and Default Configura on). ADDRESS MODE A24 31 ADDRESS RANGE [0x000000:0xFF0000] 16 15 24 23 NOTES SW2 and SW3 ignored 0 OFFSET 3 45 2 0 F 1 E F 2 BC D BC D 0 78 9 6 A A 3 45 SW5 78 9 E SW4 6 1 Fig. 8.17: A24 addressing. ADDRESS MODE A32 31 ADDRESS RANGE [0x00000000:0xFFFF0000] 16 15 24 23 NOTES 0 OFFSET F 3 45 3 45 1 E F 3 45 E 2 2 1 2 78 9 BC D 0 6 A 1 E F 3 45 SW5 78 9 BC D 0 6 A BC D BC D 2 SW4 78 9 A A 0 6 0 F SW3 78 9 E SW2 6 1 Fig. 8.18: A32 addressing. • CR/CSR address: the addressing is based on the slot number taken from the relevant backplane lines. The recognised Address Modifier for this cycle is 2F. This feature is implemented only on versions with 160-pin connectors. 31 24 23 19 18 16 15 GEO 0 OFFSET Fig. 8.19: CR/CSR addressing. UM3350 - V1751/VX1751 User Manual rev. 16 51 Address Relocation The bit[15:0] of register address 0xEF10 allow to set via so ware the board Base Address (valid values ≠ 0). Such register allows to overwrite the rotary switches se ngs; its se ng is enabled via bit[6] of the register address 0xEF00. The used addresses are: 31 24 23 16 15 0 A32 OFFSET ADER H 24 23 16 15 0 OFFSET A24 31 software relocation ADER L ADER L software relocation Fig. 8.20: So ware reloca on of base address 52 UM3350 - V1751/VX1751 User Manual rev. 16 Data Transfer Capabilities and Events Readout The board features a Mul -Event digital memory per channel, configurable by the user to be divided into 1 up to 1024 buffers, as detailed in Sec. Mul -Event Memory Organiza on. Once they are wri en in the memory, the events become available for readout via VMEbus or Op cal Link. During the memory readout, the board can store other events (independently from the readout) on the available free buffers. The events are read out sequen ally and completely, star ng from the Header of the first available event, followed by the samples of the enabled channels (from 0 to 7) as reported in . Once an event is completed, the relevant memory buffer becomes free and ready to be wri en again (old data are lost). A er the last word in an event, the first word (Header) of the subsequent event is readout. It is not possible to read out an event par ally. The size of an event (EVENT SIZE) is configurable and depends on register addresses 0x8020 and 0x800C , as well as on the number of enabled channels. The board supports D32 single data readout, Block Transfer BLT32 and MBLT64, 2eVME and 2eSST cycles. Sustained readout rate is up to 60 MB/s with MBLT64, up to 100 MB/s with 2eVME and up to 160 MB/s with 2eSST. Block Transfer D32/D64, 2eVME, and 2eSST The Block Transfer readout mode allows to read N complete events sequen ally, where N is set at register address 0xEF1C , or by using the SetMaxNumEventsBLT func on of the CAENDigi zer library [RD4]. When developing programs, the readout process can be implemented on different basis : • Using Interrupts: as soon as the programmed number of events is available for readout, the board sends an interrupt to the PC over the op cal communica on link (not supported by USB). • Using Polling (interrupts disabled): by performing periodic read accesses to a specific register of the board it is possible to know the number of events present in the board and perform a BLT read of the specific size to read them out. • Using Con nuous Read (interrupts disabled): con nuous data read of the maximum allowed size (e.g. total memory size) is performed by the so ware without polling the board. The actual size of the block read is determined by the board that terminates the BLT access at the end of the data, according to the configura on of register address 0xEF1C, or the library func on SetMaxNumEventsBLT men oned above. If the board is empty, the BLT access is immediately terminated and the “Read Block” func on will return 0 bytes (it is the ReadData func on in the CAENDigi zer Library). The event is configurable as indicated in the introduc on of the paragraph, namely: [Event Size] = [8*(Buffer Size)] + [16 bytes] Then, it is necessary to perform as many cycles as required in order to readout the programmed number of events. It is suggested to enable BERR signal during BLT32 cycles, in order to end the cycle avoiding filler readout. The last BLT32 cycle will not be completed, it will be ended by BERR a er the #N event in memory is transferred (see example in the figure below). Since some 64-bit CPU cut off the last 32- bit word of a transferred block, if the number of words composing such block is odd, it is necessary to add a dummy word (which has then to be removed via so ware) in order to avoid data loss. This can be achieved by se ng the ALIGN64 bit (bit[5]) at register address 0xEF00. MBLT64 cycle is similar to the BLT32 cycle, except that the address and data lines are mul plexed to form 64 bit address and data buses. The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals (DS and DTACK) to complete a data cycle UM3350 - V1751/VX1751 User Manual rev. 16 53 Fig. 8.21: Example of BLT readout Chained Block Transfer D32/D64 The V1751 allows to readout events from more daisy chained boards (Chained Block Transfer mode). The technique which handles the CBLT is based on the passing of a token between the boards; it is necessary to verify that the used VME crate supports such cycles. Several con guous boards, in order to be Daisy chained, must be configured as “first”, “intermediate” or “last” via register address 0xEF0C. A common Base Address is then defined via the same register; when a BLT cycle is executed at the address CBLT_Base + 0x0000 ÷ 0x0FFC, the “first” board starts to transfer its data, driving DTACK properly; once the transfer is completed, the token is passed to the second board via the IACKIN-IACKOUT lines of the crate, and so on un l the “last” board, which completes the data transfer and asserts BERR (which has to be enabled): the Master then ends the cycle and the slave boards are rearmed for a new acquisi on. If the size of the BLT cycle is smaller than the events size, the board which has the token waits for another BLT cycle to begin (from the point where the previous cycle has ended). Single D32 Transfer This mode allows the user to readout a word per me, from the header (actually 4 words) of the first available event, followed by all the words un l the end of the event, then the second event is transferred. The exact sequence of the transferred words is shown in Sec. Event structure. It is suggested, a er the 1st word is transferred, to check the EVENT SIZE informa on and then do as many cycles as necessary (actually EVENT SIZE -1) in order to read completely the event. 54 UM3350 - V1751/VX1751 User Manual rev. 16 Optical Link Access The board houses a daisy chainable Op cal Link (communica on path which uses op cal fiber cables as physical transmission line) able to transfer data at 80 MB/s, therefore it is possible to connect up to eight V1751 to a single Op cal Link Controller by using the A2818 PCI card or up to thirty-two V1751 with the A3818 PCIe card. Detailed informa on on CAEN PCI/PCIe Controllers can be find at www.caen.it: Home / Products / Modular Pulse Processing Electronics / PCI/PCIe / Op cal Controller The parameters for read/write accesses via Op cal Link are the same used by VME cycles (Address Modifier, Base Address, data Width, etc); wrong parameter se ngs cause Bus Error. Bit[3] at register address 0xEF00 enables the module to broadcast an interrupt request on the Op cal Link; the enabled Op cal Link Controllers propagate the interrupt on the PCI bus when a request from the Op cal Link is sensed. Interrupts can also be managed at the CAENDigi zer library level (see “Interrupt Configura on” [RD4]). VME and Op cal Link accesses take place on independent paths and are handled by board internal controller, with VME having higher priority; anyway it is be er to avoid accessing the board via VME and Op cal Link simultaneously. Note: CONET2 is CAEN proprietary serial protocol developed to allow the op cal link communica on between the host PC, equipped with a A2818 or a A3818 Controller, and a CAEN CONET slave. CONET2 is 50% more efficient in the data rate transfer than the previous CONET1 version. The two protocol versions are not compliant to eachother and before to migrate from CONET1 to CONET2 it is recommended to read the instruc ons provided by CAEN in the dedicated Applica on Note [RD8]. UM3350 - V1751/VX1751 User Manual rev. 16 55 9 Drivers & Libraries Drivers In order to interface with the board, CAEN provides the drivers for the supported physical communica on channels and compliant with Windows® and Linux® OS: • CONET Op cal Link, managed by the A2818 PCI card or the A3818 PCIe card. The driver installa on package is available on CAEN website in the “So ware/Firmware” tab at the A2818 or A3818 page (login required). Note: For the installa on of the Op cal Link driver, refer to the User Manual of the specific card. • USB 2.0 Drivers are managed by the V1718 USB-to-VME Bridge. The driver installa on package is available on CAEN website in the “So ware/Firmware” area at the V1718 page (login required). Note: For the installa on of the USB driver, refer to the User Manual of the V1718 Bridge. Libraries CAEN libraries are a set of middleware so ware required by CAEN so ware tools for a correct func oning. These libraries, including also demo and example programs, represent a powerful base for users who want to develop customized applica ons for the digi zer control (communica on, configura on, readout, etc.): • CAENDigi zer is a library of func ons designed specifically for the Digi zer families suppor ng both waveform recording firmware and DPP firmware. The CAENDigi zer library is based on the CAENComm library. For this reason, the CAENComm libraries must be already installed on the host PC before installing the CAENDigi zer. The CAENDigi zer installa on package and relevant documenta on [RD4] are available on CAEN website in the ”Download” tab at the CAENDigi zer Library page. • CAENComm library manages the communica on at low level (read and write access). The purpose of the CAENComm is to implement a common interface to the higher so ware layers, masking the details of the physical channel and its protocol, thus making the libraries and applica ons that rely on the CAENComm independent from the physical layer. Moreover, the CAENComm requires the CAENVMELib library (access to the VME bus) even in the cases where the VME is not used. This is the reason why CAENVMELib has to be already installed on your PC before installing the CAENComm. The CAENComm installa on package, the relevant documenta on and the link to the required CAENVMELib, are available on CAEN website in the ”Download” tab at the CAENComm Library page. CAENComm (and other libraries here described) supports the following communica on channels (Fig. 9.1): PC → USB (V1718) → VMEbus → V1751(VX1751) PC → PCI/PCIe (A2818/A3818) → CONET → V1751(VX1751) PC → PCI/PCIe (A2818/A3818) → CONET (V2718) → VMEbus → V1751(VX1751) 56 UM3350 - V1751/VX1751 User Manual rev. 16 WHEN TO INSTALL CAEN LIBRARIES: WINDOWS® compliant CAEN so ware = NOT. CAEN so ware for Windows® OS are stand-alone, which means the program locally installs the DLL files of the required libraries. LINUX® compliant CAEN so ware = YES. CAEN so ware for Linux® OS is not stand-alone. The user must install the required libraries apart to run the so ware. WINDOWS® and LINUX® compliant customized so ware = YES. The user must install the required libraries apart in case of custom so ware development. CAEN SW Tools User’s custom software CAENDigitizer Library CAENComm Library V1718 USB driver A3818 driver PCIe PCI A2818 driver USB 2.0 VME64/VME64X Digitizers A2818 A3818 V1718 VMEbus V2718 CONET2 (Optical Link) Fig. 9.1: Drivers and so ware layers. UM3350 - V1751/VX1751 User Manual rev. 16 57 10 So ware Tools CAEN provides so ware tools to interface the 751 digi zer family, which are available for free download at www.caen.it following the path: Home / Products / Firmware/So ware / Digi zer So ware CAENUpgrader CAENUpgrader is free so ware composed of command line tools together with a Java Graphical User Interface. CAENUpgrader, for the V1751 , allows in few easy steps to: • Upload different FPGA firmware versions on the digi zer • Read the firmware release of the digi zer and the bridge (when included in the communica on chain) • Manage the firmware license, in case of DPP firmware • Generate a programming file to configure the internal PLL • Upgrade the internal PLL • Get the Board Info file, useful in case of support The so ware relies on the CAENComm and CAENVMELib libraries (see Chap. Drivers & Libraries) and requires third-party Java™ SE 8 update 40 (or later) to be installed. Fig. 10.1: CAENUpgrader Graphical User Interface CAENUpgrader installa on package can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / Configura on Tools / CAENUpgrader CAEN provides a guide to the so ware features and usage [RD9], free downloadable at the web page above. Note: CAENUpgrader is available for Windows® pla orms (32 and 64-bit) as stand-alone version (all the required CAEN libraries are installed locally with the program). Only the drivers for the specific communica on link must be installed apart by the user. The CAENUpgrader version for Linux® pla orm is not stand-alone, so it needs the required libraries to be installed apart by the user. 58 UM3350 - V1751/VX1751 User Manual rev. 16 CAENComm Demo CAENComm Demo is simple so ware developed in C/C++ source code and provided both with Java™ and LabVIEW™ GUI interface. The demo mainly allows for a full board configura on at low level by direct read/write access to the registers and may be used as a debug instrument. Fig. 10.2: CAENComm Demo Java and LabVIEW graphical interface The Demo is included in the CAENComm library installa on Windows package, which can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / So ware Libraries / CAENComm Library CAEN provides the Demo descrip on in the CAENComm library User Manual, free downloadable at the web page above. Note: CAENComm Demo is available for Windows® pla orms (32 and 64-bit) and requires CAENComm and CAENVMELib as addi onal so ware to be installed by the user (see Chap. Drivers & Libraries). UM3350 - V1751/VX1751 User Manual rev. 16 59 DPP-ZLEplus Control Software DPP-ZLEplus Control So ware is a demo applica on introducing the user to understand the principle of opera on of the Digital Pulse Processing for the Zero Length Encoding (DPP-ZLEplus). The user can make an en re acquisi on through this so ware, as well use the source code to develop his/her customized readout program. Indeed, the package includes the C source files and the Visual Studio project (compliant with Visual Studio Professional 2010). The DPP-ZLEplus Control So ware is a C-based applica on that programs the Digi zer according to a set of parameters in the configura on text file, starts/stops the acquisi on and manages the data readout. The waveforms elaborated by the DPP-ZLEplus algorithm are plo ed using gnuplot, an external plo ng tool, or saved to output text files. Fig. 10.3: Screen-shots of DPP-ZLEplus Control So ware. The installa on package can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / Readout So ware / DPP-ZLEplus Control So ware CAEN provides the so ware User Manual [RD3], free downloadable at the web page above. DPP-ZLEplus Control So ware does not work with waveform recording firmware. 60 UM3350 - V1751/VX1751 User Manual rev. 16 CAEN WaveDump WaveDump is a basic console applica on, with no graphics, suppor ng only CAEN digi zers running the waveform recording firmware. It allows the user to program a single board (according to a text configura on file containing a list of parameters and instruc ons), to start/stop the acquisi on, read the data, display the readout and trigger rate, apply some post-processing (e.g. FFT and amplitude histogram), save data to a file and also plot the waveforms using Gnuplot (third-party graphing u lity: www.gnuplot.info). WaveDump is a very helpful example of C code demonstra ng the use of libraries and methods for an efficient readout and data analysis. Thanks to the included source files and the VS project, star ng with this demo is strongly recommended to all those users willing to write the so ware on their own. Fig. 10.4: CAEN WaveDump The installa on packages can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / Readout So ware / CAEN WaveDump CAEN provides the so ware User Manual [RD5] and a guide for ge ng started with it, free downloadable at the web page above. Note: CAEN WaveDump can operate with Windows® and Linux® pla orms (32 and 64 bits); the so ware relies on the CAENDigi zer, CAENComm and CAENVMELib libraries (see Chap. Drivers & Libraries). Windows® versions of WaveDump are stand-alone (all required libraries are present within the so ware package), while the Linux® versions need the required libraries to be previously installed by the user. Moreover Linux® users are required to install the third-party Gnuplot. CAEN WaveDump does not work with digi zers running DPP firmware. UM3350 - V1751/VX1751 User Manual rev. 16 61 CAEN Scope In a brand new framework, CAENScope so ware allows to manage the CAEN digi zers running the waveform recording firmware. CAENScope user friendly interface presents different sec ons to easily manage the digi zer configura on and plot the waveforms. Once connected, the program retrieves the digi zer informa on. Different parameters can be set for the channels, trigger and trace visualiza on (up to 12 traces) can be simultaneously plo ed. Signals can be recorded to files in two different formats: Binary (SQLite db) and Text (XML). It is also possible to save and restore the program se ngs. Fig. 10.5: CAENScope main frame. CAENScope installa on packages can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / Readout So ware / CAENSCOPE CAEN provides the so ware User Manual [RD10], free downloadable at the web page above. Note: Windows® and Linux® versions are stand-alone. The so ware downloads the required CAENDigi zer, CAENComm and CAENVMELib libraries. Linux users are required to install the following packages: - sharu ls; - libX ; - libXss (specifically for Debian derived distribu ons, e.g. Debian, Ubuntu, etc.); - libXScrnSaver (specifically for RedHat derived distribu ons, e.g. RHEL, Fedora, Centos, etc.). CAENScope does not work with digi zers running DPP firmware. 62 UM3350 - V1751/VX1751 User Manual rev. 16 DPP-PSD Control Software DPP-PSD Control So ware is a demo applica on introducing the user to understand the principle of opera on of the Digital Pulse Processing for the Pulse Shape Discrimina on (DPP-PSD). It can manage singleboard communica on and acquisi on of CAEN 720, 725, 730, and 751 Digi zer series running DPP-PSD firmware and the DT5790 Digital Pulse Analyzer. DPP-PSD Control So ware is based on a Java Graphical User Interface for the parameters se ng (connecon, DPP algorithm, acquisi on, etc.), a C console applica on working as an acquisi on engine (DPPRunner) and a third-party graphing u lity (Gnuplot: www.gnuplot.info). The GUI directly handles the acquisi on engine through run me commands and generates also a textual configura on file that contains all the selected parameters values. This file is read by DPPRunner, which programs the Digi zer according to the parameters, starts the acquisi on and manages the data readout. The so ware can operate in the Oscilloscope mode, where digi zed input waveforms and digital signals from the internal filters are monitored in order to be er tune the DPP parameters, and in the Histogram mode, where energy (i.e. charge) and me histograms (built by the so ware) can be monitored. According to the opera ng mode, raw data like waveforms or charges, PSD and me stamp lists, as well as energy or me histograms can be saved to output files for off-line analysis. Fig. 10.6: CAEN DPP-PSD Control So ware. The installa on package can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / Readout So ware / DPP-PSD Control So ware CAEN provides the so ware User Manual [RD2], free downloadable at the web page above. CAEN DPP-PSD Control So ware does not work with waveform recording firmware. UM3350 - V1751/VX1751 User Manual rev. 16 63 CoMPASS CoMPASS (CAEN Mul -PArameter Spectroscopy So ware) is the new so ware from CAEN able to implement a Mul -parametric DAQ for Physics Applica ons, where the detectors can be connected directly to the digi zers inputs and the so ware acquires energy, ming, and PSD spectra. CoMPASS so ware has been designed as a user-friendly interface to manage the acquisi on with all the CAEN DPP algorithm. CoMPASS can manage mul ple boards, even in synchronized mode, and the event correla on between different channels (hardware and/or so ware), apply energy and PSD cuts, calculate and show the sta s cs (trigger rates, data throughput, etc...), save the output data files (raw data, lists, waveforms, spectra) and use the saved files to run off-line with different processing parameters. CoMPASS So ware supports CAEN x720, x724, x725, x730, x740D, x751 digi zer families running the DPPPSD, DPP-PHA and DPP-QDC firmware, and the x781 MCA family. Fig. 10.7: CoMPASS so ware tool. The installa on package can be downloaded on CAEN web site (login required) at: Home / Products / Firmware/So ware / Digi zer So ware / Readout So ware / CoMPASS CAEN provides the so ware User Manual [RD11], free downloadable at the web page above. CoMPASS does not work with waveform recording firmware. 64 UM3350 - V1751/VX1751 User Manual rev. 16 11 HW Installa on • The V1751 fits into 6U VME crates. • VX1751 versions require VME64X compliant crates • Use only crates with forced cooling air flow • Turn the crate OFF before board inser on/removal • Remove all cables connected to the front panel before board inser on/removal CAUTION: this product needs proper cooling. USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING THE BOARD MAY DEGRADE ITS PERFORMANCES! CAUTION: this product needs proper handling. V1751/VX1751 DO NOT SUPPORT LIVE INSERTION (HOT SWAP)! REMOVE OR INSERT THE BOARD WHEN THE VME CRATE IS POWERED OFF! ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE! UM3350 - V1751/VX1751 User Manual rev. 16 65 Power-on Sequence To power on the board, perform the following steps: 1. Insert the V1751 into the crate; 2. power up the crate. Power-on Status At power-on, the module is in the following status: • the Output Buffer is cleared; • registers are set to their default configura on A er the power-on, only the NIM and PLL LOCK LEDs must stay ON (see Fig. 11.1). Fig. 11.1: Front panel LEDs status at power-on. 66 UM3350 - V1751/VX1751 User Manual rev. 16 12 Firmware and Upgrades The board hosts one FPGA on the mainboard and two FPGAs per mezzanine (i.e. one FPGA per channel). The channel FPGAs firmware is iden cal. A unique file is provided that will update all the FPGAs at the same me. ROC FPGA MAINBOARD FPGA (Readout Controller + VME interface): FPGA Altera Cyclone EP1C20 AMC FPGA MEZZANINE FPGA (ADC readout/Memory Controller): FPGA Altera Cyclone EP1C20 The firmware is stored onto the on-board FLASH memory. Two copies of the firmware are stored in two different pages of the FLASH, referred to as Standard (STD) and Backup (BKP). In case of waveform recording firmware, the board is delivered equipped with the same firmware version on both pages. At power-on, a micro-controller reads the FLASH memory and programs the module automa cally loading the first working firmware copy, that is the STD one in normal opera ng. The on-board dedicated SW7 dip switch, set on STD posi on by default, allows to select the first FLASH page to be read at power-on (see Sec. Internal Components). It is possible to upgrade the board firmware via VMEbus or Op cal Link by wri ng the FLASH with the CAENUpgrader so ware (see Chap. So ware Tools). IT IS STRONGLY SUGGESTED TO OPERATE THE DIGITIZER UPON THE STD COPY OF THE FIRMWARE. UPGRADES ARE SO RECOMMENDED ONLY ON THE STD PAGE OF THE FLASH. THE BKP COPY IS TO BE INTENDED ONLY FOR RECOVERY USAGE. IF BOTH PAGES RESULT CORRUPTED, THE USER WILL NO LONGER BE ABLE TO UPLOAD THE FIRMWARE VIA VMEbus OR OPTICAL LINK AGAIN AND THE BOARD NEEDS TO BE SENT TO CAEN FOR REPAIR! Firmware Upgrade All firmware updates are available for download on CAEN website www.caen.it (login required) at the following path: Home / Products / Modular Pulse Processing Electronics / VME / Digi zers / V1751 Different firmware are available for the 751 family: • The waveform recording firmware; • The special DPP firmware for Physics Applica ons: – DPP-PSD firmware to use the digi zer as a digital replacement Dual Gate QDC, Discriminator and Gate Generator. – DPP-ZLEplus firmware to transfer the waveform in a compact format performing an advanced Zero Suppression algorithm. DPP firmware updates can also be found at the relevant DPP firmware web page: Home /Products / Firmware/So ware / DPP Firmware/So ware Tools (Digi zer) / DPP Firmware /UM3350 - V1751/VX1751 User Manual rev. 16 67 Firmware File Description The programming file has the extension .CFA (CAEN Firmware Archive). It is an archiving file format that aggregates all the programming files of the same firmware kind which are compa ble with the same digi zer family. The CFA naming conven on follows this general scheme: • x751_rev_X.Y_W.Z.CFA for the waveform recording firmware where x751 are all the supported boards (the 751 family includes DT5751, N6751, V1751, VX1751), X.Y is the major/minor revision number of the mainboard FPGA, and W.Z is the major/minor revision number of the channel FPGA. The major revision number of the channel FPGA is a fixed number specific for each DPP and digi zer family, and it can be equal or grater than 128 (for example, ). The waveform recording firmware major revision number is not fixed and it is less than 128. Note: DPP special firmware is a pay firmware requiring a license to be purchased. If not licensed, the firmware can be loaded but it will run fully func onal with a me limita on per power cycle (30 minutes). Details on the license ordering procedure are included in the CAENUpgrader guide [RD9]. Troubleshooting In case of upgrade failure (e.g. STD FLASH page is corrupted), the user can try to reboot the board: a er a power cycle, the system programs the board automa cally from the alterna ve FLASH page (e.g. BKP FLASH page), if this is not corrupted as well. The user can so perform a further upgrade a empt on the STD page to restore the firmware copy. BECAUSE OF AN UPGRADE FAILURE, THE SW7 DIP SWITCH POSITION MAY NOT CORRESPOND TO THE FLASH PAGE FIRMWARE COPY LOADED ON THE BOARD FPGAs. Note: old versions of the digi zer motherboard have a slightly different FLASH management. Use CAENUpgrader 1.6.0 or later to get the BoardInfoFile (using the ”Get Informa on” func on) and check that the FLASH_TYPE=0. Alterna vely, use a so ware u lity like CAENComm Demo to read at register address 0xF050 and check that bit[7]=0. In this case, at power-on, the micro-controller loads exactly the firmware copy from the FLASH page selected through the SW7 dip switch (e.g. STD by default) . When a failure occurs during the upgrade of the STD page of the FLASH, which compromises the communica on with the V1751 , the user can perform the following recovering procedure as first a empt: - force the board to reboot loading the copy of the firmware stored on the BKP page of the FLASH. For this purpose, power off the crate, switch the dedicated SW1 switch to BKP posi on and power on the crate . - use CAENUpgrader to read the firmware revision (in this case the one of the BKP copy). If this succeeds, it is so possible to communicate again with the board; - use CAENUpgrader to load the proper firmware file on the STD page, then power off the crate, switch SW7 back to STD posi on and power on the crate. If neither of the procedures here described succeeds, it is recommended to send the board back to CAEN in repair (see Chap. Technical Support). 68 UM3350 - V1751/VX1751 User Manual rev. 16 13 Technical Support CAEN support services are available for the user by accessing the Support & Services area on CAEN website at h p://www.caen.it. Returns and Repairs Users who need for product(s) return and repair have to fill and send the Product Return Form (PRF) in the Returns and Repairs area at Home / Support & Services, describing the specific failure. A printed copy of the PRF must also be included in the package to be shipped. Contacts for shipping are reported on the website at Home / Contacts. Technical Support Service CAEN experts can provide technical support at the e-mail addresses below: support.nuclear@caen.it (for ques ons about the hardware) support.compu ng@caen.it (for ques ons about so ware and libraries) UM3350 - V1751/VX1751 User Manual rev. 16 69 UM3350 - V1751/VX1751 User Manual rev. 16- June 12th , 2017 00000-00-02827-GXXX Copyright ©CAEN SpA. All rights reserved. Informa on in this publica on supersedes all earlier versions. Specifica ons subject to change without no ce.
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