UltraScale FPGA Product Tables And Selection Guide Ultra Scale FPGAs
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© Copyright 2013–2016 Xilinx . Kintex® UltraScale™ FPGAs Logic Resources Memory Resources Clock Resources I/O Resources Integrated IP Resources Speed Grades Footprint Compatible with Virtex® UltraScale Devices Device Name System Logic Cells (K) CLB Flip-Flops CLB LUTs Maximum Distributed RAM (Kb) Block RAM/FIFO w/ECC (36Kb each) Block RAM/FIFO (18Kb each) Total Block RAM (Mb) CMT (1 MMCM, 2 PLLs) I/O DLL Maximum Single-Ended HP I/Os Maximum Differential HP I/O Pairs Maximum Single-Ended HR I/Os Maximum Differential HR I/O Pairs DSP Slices System Monitor PCIe® Gen1/2/3 Interlaken 100G Ethernet 16.3Gb/s Transceivers (GTH/GTY) Commercial Extended Industrial Package Package Dimensions Footprint(3, 4, 5, 6) (mm) A784(7) 23x23(8) A676(7) 27x27 A900(7) 31x31 A1156 35x35 A1517 40x40 C1517 40x40 D1517 40x40 B1760 42.5x42.5 A2104 47.5x47.5 B2104 47.5x47.5 D1924 45x45 F1924 45x45 KU025(1) 318 290,880 145,440 4,230 360 720 12.7 6 24 208 96 104 48 1,152 1 1 0 0 12 -1 -2 -1 -2 KU035 444 406,256 203,128 5,908 540 1,080 19.0 10 40 416 192 104 48 1,700 1 2 0 0 16 -1 -2 -3 -1 -1L -2 KU040 530 484,800 242,400 7,050 600 1,200 21.1 10 40 416 192 104 48 1,920 1 3 0 0 20 -1 -2 -3 -1 -1L -2 KU060 726 663,360 331,680 9,180 1,080 2,160 38.0 12 48 520 240 104 48 2,760 1 3 0 0 32 -1 -2 -3 -1 -1L -2 KU085 1,088 995,040 497,520 13,770 1,620 3,240 56.9 22 56 572 264 104 56 4,100 2 4 0 0 56 -1 -2 -3 -1 -1L -2 KU095 1,176 1,075,200 537,600 4,800 1,680 3,360 59.1 16 64 650 288 52 24 768 1 4 2 2 64(2) -1 -2 -1 -2 HR I/O, HP I/O, GTH/GTY 104, 208, 12 104, 364, 8 104, 208, 16 104, 364, 16 104, 416, 16 104, 364, 8 104, 208, 16 104, 364, 16 104, 416, 20 104, 416, 28 104, 520, 32 52, 468, 28 104, 520, 48 104, 520, 48 52, 468, 40 104, 572, 44 52, 650, 48 52, 650, 64 104, 520, 56 Notes: 1. Certain advanced configuration features are not supported in the KU025. Refer to the Configuring FPGAs section in DS890, UltraScale Architecture and Product Overview. 2. GTY transceivers in KU095 devices support data rates up to 16.3Gb/s. 3. Packages with the same package footprint designator, e.g., A2104, are footprint compatible with all other UltraScale devices with the same sequence. See the migration table for details on inter-family migration. 4. Maximum achievable performance is device and package dependent; consult the associated data sheet for details. 5. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 6. See UG575, UltraScale Architecture Packaging and Pinouts User Guide for more information. 7. GTH transceivers in A784, A676, and A900 packages support data rates up to 12.5Gb/s. 8. 0.8mm ball pitch. All other packages listed 1mm ball pitch. Page 2 KU115 1,451 1,326,720 663,360 18,360 2,160 4,320 75.9 24 64 676 312 156 72 5,520 2 6 0 0 64 -1 -2 -3 -1 -1L -2 © Copyright 2013–2016 Xilinx . 104, 234, 64 104, 598, 52 156, 676, 52 104, 598, 64 156, 676, 52 104, 624, 64 Virtex® UltraScale™ FPGAs Logic Resources Memory Resources Clock Resources I/O Resources Integrated IP Resources Speed Grades Footprint Compatible with Kintex® UltraScale Devices Device Name System Logic Cells (K) CLB Flip-Flops CLB LUTs Maximum Distributed RAM (Kb) Block RAM/FIFO w/ECC (36Kb each) Block RAM/FIFO (18Kb each) Total Block RAM (Mb) CMT (1 MMCM, 2 PLLs) I/O DLL Transceiver Fractional PLL Maximum Single-Ended HP I/Os Maximum Differential HP I/O Pairs Maximum Single-Ended HR I/Os Maximum Differential HR I/O Pairs DSP Slices System Monitor PCIe® Gen1/2/3 Interlaken 100G Ethernet GTH 16.3Gb/s Transceivers GTY 30.5Gb/s Transceivers Commercial Extended Industrial Package Package Dimensions Footprint(1, 2, 3) (mm) C1517 D1517 B1760 A2104 B2104 C2104 B2377 A2577 A2892 40x40 40x40 42.5x42.5 47.5x47.5 47.5x47.5 47.5x47.5 50x50 52.5x52.5 55x55 XCVU065 783 716,160 358,080 4,830 1,260 2,520 44.3 10 40 5 468 216 52 24 600 1 2 3 3 20 20 – -1H -2 -3 -1 -2 XCVU080 975 891,424 445,712 3,980 1,421 2,842 50.0 16 64 8 780 360 52 24 672 1 4 6 4 32 32 – -1H -2 -3 -1 -2 XCVU095 1,176 1,075,200 537,600 4,800 1,728 3,456 60.8 16 64 8 780 360 52 24 768 1 4 6 4 32 32 – -1H -2 -3 -1 -2 XCVU125 1,567 1,432,320 716,160 9,660 2,520 5,040 88.6 20 80 10 780 360 52 24 1,200 2 4 6 6 40 40 – -1H -2 -3 -1 -2 XCVU160 2,027 1,852,800 926,400 12,690 3,276 6,552 115.2 28 120 13 650 300 52 24 1,560 3 4 8 9 52 52 – -1H -2 -3 -1 -2 XCVU190 2,350 2,148,480 1,074,240 14,490 3,780 7,560 132.9 30 120 15 650 300 52 24 1,800 3 6 9 9 60 60 – -1H -2 -3 -1 -2 HR I/O, HP I/O, GTH 16.3Gb/s, GTY 30.5Gb/s 52, 468, 20, 20 52, 468, 20, 20 52, 286, 32, 32 52, 650, 32, 16 52, 780, 28, 24 52, 650, 32, 32 52, 468, 20, 20 52, 286, 32, 32 52, 650, 32, 16 52, 780, 28, 24 52, 650, 32, 32 52, 364, 32, 32 52, 286, 40, 32 52, 650, 36, 16 52, 780, 28, 24 52, 650, 40, 36 52, 364, 40, 40 52, 650, 40, 36 52, 364, 52, 52 52, 650, 40, 36 52, 364, 52, 52 52, 1248, 36, 0 0, 448, 60, 60 52, 1404, 48, 0 Notes: 1. Packages with the same package footprint designator, e.g., A2104, are footprint compatible with all other UltraScale devices with the same sequence. See the migration table for details on inter-family migration. 2. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 3. See UG575, Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinouts User Guide for more information. Page 3 XCVU440 5,541 5,065,920 2,532,960 28,710 2,520 5,040 88.6 30 120 0 1,404 648 52 24 2,880 3 6 0 3 48 0 -1 -2 -3 -1 -2 © Copyright 2013–2016 Xilinx . UltraScale Device Ordering Information Footprint XC V U ### Xilinx Commercial V: Virtex UltraScale K: Kintex Value Index -1 Speed Grade -1 = Slowest -L1 = Low Power (Kintex only) -H1 = Slowest or Mid F L V A #### C F: Flip-Chip F: Lid V: RoHS 6/6 Package (1.0mm) L: Lid SSI G: RoHS 6/6 Designator S: Flip-Chip B: Lidless w/exemption 15 (0.8mm) Package Pin Count Temperature Grade (C, E, I) (Virtex only) -2 = Mid -3 = Fastest C = Commercial (Tj = 0°C to +85°C) E = Extended (Tj = 0°C to +100°C) I = Industrial (Tj = –40°C to +100°C) For valid part/package combinations, go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os Tables Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 4 © Copyright 2013–2016 Xilinx . UltraScale™ Device Footprint Compatibility HR I/O, HP I/O, GTH 16.3Gb/s; GTY 30.5Gb/s Package Dimensions (mm) 23x23 27x27 31x31 35x35 Package Footprint A784 A676 A900 A1156 XCKU025 23mm–42.5mm 40x40 A1517 C1517 42.5x42.5 D1517 B1760 104, 208, 12, 0 XCKU035 104, 364, 8, 0 104, 208, 16, 0 104, 364, 16, 0 104, 416, 16, 0 XCKU040 104, 364, 8, 0 104, 208,16, 0 104, 364, 16, 0 104, 416, 20, 0 XCKU060 104, 416, 28, 0 104, 520, 32, 0 XCKU085 N/A 104, 520, 48, 0 XCKU095 52, 468, 20, 8(1) N/A 52, 468, 20, 20(1) 104, 520, 48, 0 N/A XCKU115 XCVU065 XCVU080 104, 572, 44, 0 52, 468, 20, 20 52, 650, 32, 16(1) 104, 234, 64, 0 104, 598, 52, 0 N/A N/A 52, 468, 20, 20 52, 286, 32, 32 52, 650, 32, 16 Footprint compatibility is indicated by shading per column. XCVU095 52, 468, 20, 20 52, 286, 32, 32 52, 650, 32, 16 XCVU125 52, 286, 40, 32 52, 650, 36, 16 Notes: 1. GTY transceivers in KU095 devices support data rates up to 16.3Gb/s. Refer to data sheet for details. Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 5 © Copyright 2013–2016 Xilinx . UltraScale™ Device Footprint Compatibility 45mm–55mm HR I/O, HP I/O, GTH 16.3Gb/s; GTY 30.5Gb/s Package Dimensions (mm) Package Footprint 45x45 D1924 47.5x47.5 F1924 A2104 B2104 C2104 50x50 52.5x52.5 55x55 B2377 A2577 A2892 XCKU035 XCKU040 XCKU060 XCKU085 104, 520, 56, 0 XCKU095 N/A XCKU115 156, 676, 52, 0 104, 624, 64, 0 52, 650, 32, 32(1) 156, 676, 52, 0 104, 598, 64, 0 XCVU065 N/A N/A XCVU080 52, 780, 28, 24 52, 650, 32, 32 XCVU095 52, 780, 28, 24 52, 650, 32, 32 52, 364, 32, 32 XCVU125 52, 780, 28, 24 52, 650, 40, 36 52, 364, 40, 40 52, 650, 40, 36 52, 364, 52, 52 52, 650, 40, 36 52, 364, 52, 52 XCVU160 XCVU190 Footprint compatibility is indicated by shading per column. XCVU440 0, 448, 60, 60 52, 1248, 36, 0 52, 1404, 48, 0 Notes: Important: Verify all data in this document with the device data sheets found at www.xilinx.com 1. GTY transceivers in KU095 devices support data rates up to 16.3Gb/s. Refer to data sheet for details. Page 6 © Copyright 2013–2016 Xilinx . UltraScale Architecture Migration Table UltraScale and UltraScale+ families provide footprint compatibility to enable users to migrate designs from one device or family to another. Any two packages with the same footprint identifier code are footprint compatible. Kintex® UltraScale™ Pkg Kintex UltraScale+™ Virtex® UltraScale Virtex UltraScale+ mm KU025 KU035 KU040 KU060 KU085 KU095 KU115 KU3P KU5P KU9P KU11P KU13P KU15P VU065 VU080 VU095 VU125 VU160 VU190 VU440 VU3P VU5P VU7P VU9P VU11P VU13P A784 23 B784 23 A676 27 B676 27 A900 31 D900 31 E900 31 A1156 35 A1517 40 C1517 40 D1517 40 E1517 40 A1760 42.5 B1760 42.5 E1760 42.5 D1924 45 F1924 45 A2104 47.5(1) B2104 47.5(1) C2104 47.5(1) B2377 50 A2577 52.5 A2892 55 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes: 1. The body size of the VU13P device in the A2104, B2104, and C2104 packages is 52.5mm. These packages are footprint compatible with the corresponding 47.5mm body size packages. See UG583, UltraScale Architecture PCB Design User Guide for important migration details. Legend Device Migration Path Page 7 © Copyright 2013–2016 Xilinx . Digital Signal Processing Metrics UltraScale architecture further enhances the Xilinx DSP48 slice with features designed to allow users to do more calculations in fewer DSP resources, enhancing both device utilization and performance. Examples include wider multipliers for floating point calculations, wide XOR functions for ECC, CRC, and EFEC, and pre-adder squaring for rounding algorithms. DSP Slice Count XCKU025 XCKU035 XCKU040 XCKU060 XCKU085 XCKU095 XCKU115 XCVU065 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU440 1152 1700 1920 2760 4100 768 5520 600 672 768 1200 1560 1800 Speed grade FMAX [MHz] Max GMAC/s 2880 -1 594 6558 -2 661 7297 For more information, refer to: UG579, UltraScale Architecture DSP Slice User Guide Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 8 © Copyright 2013–2016 Xilinx . -3 741 8181 Block RAM Metrics UltraScale architecture block RAM adds new features to increase performance, device utilization, and power efficiency. These new features are designed to provide highly efficient solutions for applications in the Wireless, Wired, Video, and Signal Processing markets by offering hardened memory cascade to reduce fabric use and increase performance, and flexible hard FIFO and user accessible dynamic power control to reduce power. XCKU025 XCKU035 XCKU040 XCKU060 XCKU085 XCKU095 XCKU115 XCVU065 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU440 Block RAM Capacity (Mb) 13 19 21 38 57 59 76 44 50 61 89 115 133 89 Speed grade -1 -2 -3 True dual-port Block RAM FMAX [MHz] 525 585 660 For more information, refer to: UG573, UltraScale Architecture Memory Resources User Guide Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 9 © Copyright 2013–2016 Xilinx . High-Speed Serial Transceivers For high bandwidth applications, including 500Gb/s, 400Gb/s, and 100Gb/s line cards, serial data transmission across backplanes and longer distances is becoming increasingly important. UltraScale architecture serial transceivers include the proven on-chip circuits required to provide optimal signal integrity in real world environments, at data rates up to 16.3Gb/s (GTH) and 30.5Gb/s (GTY). Total Transceiver Count XCKU025 XCKU035 XCKU040 GTH = 16.3Gb/s GTY = 30.5Gb/s 12 16 GTY 20 XCKU060 32 XCKU085 56 XCKU095 32(1) 64 32 XCKU115 XCVU065 GTH 20 20 XCVU080 32 32 XCVU095 XCVU125 32 32 40 40 XCVU160 52 60 XCVU190 XCVU440 52 60 48 For more information, refer to UG576, UltraScale Architecture GTH Transceivers User Guide and UG578, UltraScale Architecture GTY Transceivers User Guide Notes: 1. GTY up to 16.3Gb/s. Refer to data sheet for details. Page 10 Important: Verify all data in this document with the device data sheets found at www.xilinx.com © Copyright 2013–2016 Xilinx . Transceiver Aggregate Bandwidth For high bandwidth applications, including 500Gb/s, 400Gb/s, and 100Gb/s line cards, serial data transmission across backplanes and longer distances is becoming increasingly important. UltraScale architecture serial transceivers include the proven on-chip circuits required to provide optimal signal integrity in real world environments, at data rates up to 16.3Gb/s (GTH) and 30.5Gb/s (GTY). Transceiver Aggregate Bandwidth (Gb/s) XCKU025 391 XCKU035 522 XCKU040 652 XCKU060 GTY 1826 1043(1) 1043 2086 XCKU115 XCVU065 GTH 1043 XCKU085 XCKU095 GTH = 16.3Gb/s GTY = 30.5Gb/s 652 1220 XCVU080 1043 1952 XCVU095 XCVU125 1043 1304 1952 XCVU160 XCVU190 XCVU440 2440 1695 1956 3172 3660 1565 Transceiver Aggregate Bandwidth (Gb/s) = # of Transceivers x Maximum Line Rate x 2 (Full Duplex) For more information, refer to UG576, UltraScale Architecture GTH Transceivers User Guide and UG578, UltraScale Architecture GTY Transceivers User Guide Notes: 1. GTY up to 16.3Gb/s. Refer to data sheet for details. Page 11 Important: Verify all data in this document with the device data sheets found at www.xilinx.com © Copyright 2013–2016 Xilinx . References DS890, UltraScale Architecture and Product Overview DS892, Kintex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics DS893, Virtex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics UG570, UltraScale Architecture Configuration User Guide UG571, UltraScale Architecture SelectIO Resources User Guide UG572, UltraScale Architecture Clocking Resources User Guide UG573, UltraScale Architecture Memory Resources User Guide UG574, UltraScale Architecture Configurable Logic Block User Guide UG575, Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinout User Guide UG576, UltraScale Architecture GTH Transceivers User Guide UG578, UltraScale Architecture GTY Transceivers User Guide UG579, UltraScale Architecture DSP Slice User Guide UG580, UltraScale Architecture System Monitor User Guide UG583, UltraScale Architecture PCB and Pin Planning User Guide PG150, LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 12 © Copyright 2013–2016 Xilinx . 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