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COM Express™ conga-TC87
4th Generation Intel® Core™ i7, i5, i3 and Mobile Intel® Celeron Single Chip Ultra Low TDP Processors

User’s Guide
Revision 0.1 (Preliminary)
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Revision History
Revision

Date (yyyy.mm.dd)

Author

Changes

0.1

2013.11.14

AEM

•

Preliminary release

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Preface
This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-TC87. It is
one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should
be used include the following:
COM Express™ Design Guide
COM Express™ Specification
The links to these documents can be found on the congatec AG website at www.congatec.com

Disclaimer
The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice.
congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims
any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes
no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for
discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or
exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information
contained herein or the use thereof.

Intended Audience
This user’s guide is intended for technically qualified personnel. It is not intended for general audiences.

Lead-Free Designs (RoHS)
All congatec AG designs are created from lead‑free components and are completely RoHS compliant.

Electrostatic Sensitive Device
All congatec AG products are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a congatec AG product
except at an electrostatic‑free workstation. Additionally, do not ship or store congatec AG products near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the congatec AG Limited Warranty.
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Symbols
The following symbols are used in this user’s guide:

Warning
Warnings indicate conditions that, if not observed, can cause personal injury.

Caution
Cautions warn the user about how to prevent damage to hardware or loss of data.

Note
Notes call attention to important information that should be observed.

Terminology
Term

Description

GB
GHz
kB
MB
Mbit
kHz
MHz
TDP
PCIe
SATA
PEG
PCH
eDP
T.O.M.
HDA
N.C.
N.A.
MCP
TBD

Gigabyte (1,073,741,824 bytes)
Gigahertz (one billion hertz)
Kilobyte (1024 bytes)
Megabyte (1,048,576 bytes)
Megabit (1,048,576 bits)
Kilohertz (one thousand hertz)
Megahertz (one million hertz)
Thermal Design Power
PCI Express
Serial ATA
PCI Express Graphics
Platform Controller Hub
Embedded DisplayPort
Top of memory = max. DRAM installed
High Definition Audio
Not connected
Not available
MCP
To be determined

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Trademarks
Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property
of their respective trademark holders. These trademark holders are not affiliated with congatec AG, our products, or our website.

Warranty
congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited
warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and
conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and
from time to time.
The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license
agreements, which are available at www.congatec.com and/or upon request.
Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the
products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or
due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec’s option and expense.
Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight
prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.
Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged
or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to
congatec’s direct customer only and is not assignable or transferable.
Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either
express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of
fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.
congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be
liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive
remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the
product only.

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ISO 9001

Certification
congatec AG is certified to DIN EN ISO 9001 standard.
C

ER

T I F I C AT I O

N

TM

Technical Support
congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products
can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities and
drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support
department by email at support@congatec.com

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Contents
1

INTRODUCTION...................................................................... 10

2

Specifications............................................................................ 12

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.6
2.6.1
2.7

Feature List............................................................................... 12
Supported Operating Systems.................................................. 13
Mechanical Dimensions............................................................ 13
Supply Voltage Standard Power............................................... 14
Electrical Characteristics........................................................... 14
Rise Time.................................................................................. 14
Power Consumption.................................................................. 15
Intel® Core™ i7-4650U 1.7 GHz Dual Core™ 4MB Cache ...... 16
Intel® Core™ i5-4300U 1.9 GHz Dual Core™ 3MB Cache ...... 16
Intel® Core™ i3-4010U 1.7 GHz Dual Core™ 3MB Cache ...... 17
Intel® Celeron® 2980U 1.6 GHz Dual Core™ 2MB Cache ....... 17
Supply Voltage Battery Power.................................................. 17
CMOS Battery Power Consumption......................................... 17
Environmental Specifications.................................................... 18

3

Block Diagram........................................................................... 19

4

Heatspreader............................................................................ 20

4.1

Heatspreader Dimensions........................................................ 21

5

Connector Subsystems Rows A, B, C, D.................................. 22

5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1.12

Primary Connector Rows A and B............................................. 23
Serial ATA™ (SATA).................................................................. 23
USB 2.0..................................................................................... 23
High Definition Audio (HDA) Interface....................................... 23
Gigabit Ethernet ....................................................................... 23
LPC Bus.................................................................................... 24
I²C Bus Fast Mode.................................................................... 24
PCI Express™.......................................................................... 24
ExpressCard™.......................................................................... 24
Graphics Output (VGA/CRT).................................................... 24
LCD (LVDS/eDP)...................................................................... 25
General Purpose Serial Interface.............................................. 25
Power Control........................................................................... 26

5.1.13
5.2
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.4

Power Management.................................................................. 29
Secondary Connector Rows C and D....................................... 30
PCI Express™.......................................................................... 30
PCI Express Graphics (PEG).................................................... 30
Digital Display Interface............................................................ 30
HDMI......................................................................................... 31
DVI............................................................................................ 31
DisplayPort (DP)....................................................................... 31
USB 3.0..................................................................................... 32

6

Additional Features................................................................... 33

6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.7
6.8

congatec Board Controller (cBC).............................................. 33
Board Information..................................................................... 33
Watchdog.................................................................................. 33
I2C Bus...................................................................................... 33
Power Loss Control................................................................... 33
Embedded BIOS....................................................................... 34
CMOS Backup in Non Volatile Memory.................................... 34
OEM CMOS Default Settings and OEM BIOS Logo................. 34
OEM BIOS Code....................................................................... 34
congatec Battery Management Interface.................................. 35
API Support (CGOS/EAPI)....................................................... 35
Security Features...................................................................... 36
Suspend to Ram....................................................................... 36

7

conga Tech Notes..................................................................... 37

7.1
7.1.1
7.1.1.1
7.1.1.2
7.1.1.3
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4

Intel® PCH-LP Features............................................................ 37
Intel® Rapid Storage Technology ............................................. 37
AHCI......................................................................................... 37
RAID......................................................................................... 37
Intel® Smart Response Technology .......................................... 37
Intel® Rapid Start Technology................................................... 38
Intel® Processor Features......................................................... 38
Intel® Turbo Boost Technology.................................................. 38
Thermal Monitor and Catastrophic Thermal Protection............ 39
Processor Performance Control................................................ 39
Intel® 64 Architecture................................................................. 40

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7.2.5
7.2.6
7.3
7.4
7.5

Intel® Virtualization Technology................................................. 41
Thermal Management............................................................... 41
ACPI Suspend Modes and Resume Events............................. 42
Low Voltage Memory (DDR3L)................................................. 42
USB 2.0 EHCI Host Controller Support.................................... 43

8

Signal Descriptions and Pinout Tables...................................... 44

8.1
8.2
8.3
8.4
8.5

A-B Connector Signal Descriptions........................................... 45
A-B Connector Pinout............................................................... 54
C-D Connector Signal Descriptions.......................................... 56
C-D Connector Pinout............................................................... 65
Boot Strap Signals.................................................................... 67

9

System Resources.................................................................... 68

9.1
9.1.1
9.2
9.3
9.4
9.5

I/O Address Assignment............................................................ 68
LPC Bus.................................................................................... 68
PCI Configuration Space Map.................................................. 69
PCI Interrupt Routing Map........................................................ 70
I²C Bus...................................................................................... 70
SM Bus..................................................................................... 70

10

BIOS Setup Description............................................................ 71

11

Industry Specifications.............................................................. 72

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List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32

Feature Summary..................................................................... 12
Display Combination (U-processor line)................................... 30
Signal Tables Terminology Descriptions................................... 44
Intel® High Definition Audio Link Signals Descriptions.............. 45
Gigabit Ethernet Signal Descriptions........................................ 45
Serial ATA Signal Descriptions.................................................. 46
PCI Express Signal Descriptions (general purpose)................. 47
ExpressCard Support Pins Signal Descriptions........................ 47
LPC Signal Descriptions........................................................... 48
USB Signal Descriptions........................................................... 48
CRT Signal Descriptions........................................................... 49
LVDS Signal Descriptions......................................................... 49
Embedded DisplayPort Signal Descriptions............................. 50
SPI BIOS Flash Interface Signal Descriptions.......................... 50
Miscellaneous Signal Descriptions........................................... 51
General Purpose I/O Signal Descriptions................................. 51
Power and System Management Signal Descriptions.............. 52
General Purpose Serial Interface Signal Descriptions.............. 52
Power and GND Signal Descriptions........................................ 53
Connector A-B Pinout............................................................... 54
PCI Express Signal Descriptions (general purpose)................. 56
USB 3.0 Signal Descriptions..................................................... 56
PCI Express Signal Descriptions (x16 Graphics)...................... 57
DDI Signal Description.............................................................. 59
HDMI Signal Descriptions......................................................... 61
DisplayPort (DP) Signal Descriptions....................................... 62
Module Type Definition Signal Description............................... 64
Power and GND Signal Descriptions........................................ 64
Connector C-D Pinout............................................................... 65
Boot Strap Signal Descriptions................................................. 67
PCI Configuration Space Map.................................................. 69
PCI Interrupt Routing Map........................................................ 70

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1

INTRODUCTION

COM Express™ Concept
COM Express™ is an open industry standard defined specifically for COMs (computer on modules). Its creation provides the ability to make a
smooth transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form
factors:
• Compact
• Basic		
• Extended

95mm x 95mm
125mm x 95mm
155mm x 110mm

The COM Express™ specification 2.1 defines seven different pinout types.
Types

Connector Rows

PCI Express Lanes

Type 1

A-B

Up to 6

PCI

IDE Channels

LAN ports

Type 2
Type 3

A-B C-D
A-B C-D

Up to 22
Up to 22

Type 4

A-B C-D

Up to 32

Type 5

A-B C-D

Up to 32

3

Type 6

A-B C-D

Up to 24

1

Type 10

A-B

Up to 4

1

1
32 bit
32 bit

1

1
3

1

1

The conga-TC87 modules use the Type 6 pinout definition. They are equipped with two high performance connectors that ensure stable data
throughput.
The COM (computer on module) integrates all the core components and is mounted onto an application specific carrier board. COM modules
are legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These
functions include, but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial ATA,
USB 2.0, and Gigabit Ethernet. The Type 6 pinout provides the ability to offer PCI Express, Serial ATA, and LPC options thereby expanding
the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is
perfectly suited for all applications.
Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all
the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a
dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™
modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use
of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary.
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conga-TC87 Options Information
The conga-TC87 is currently available in four variants. This user’s guide describes all of these variants. The table below show the different
configurations available. Check for the Part No. that applies to your product. This will tell you what options described in this user’s guide are
available on your particular module.
conga-TC87
Part-No.

046901

046902

046903

046904

Processor

Intel® Core™ i7-4650U 1.7
GHz Dual Core™
4 MByte
3.3 GHz
Intel® HD graphics 5000 (GT3)
1.1 GHz
No
Yes
Yes
Yes
15 W

Intel® Core™ i5-4300U 1.9 GHz
Dual Core™
3 MByte
2.9 GHz
Intel® HD graphics 4400 (GT2)
1.1 GHz
No
Yes
Yes
Yes
15 W

Intel® Core™ i3-4010U 1.7 GHz
Dual Core™
3 MByte
n/a
Intel® HD graphics 4400 (GT2)
1.0 GHz
No
Yes
Yes
Yes
15 W

Intel® Celeron® 2980U
1.6 GHz Dual Core™
2 MByte
n/a
Intel® HD graphics (GT2)
1.0 GHz
No
Yes
Yes
Yes
15 W

Intel® Smart Cache
Max. Turbo Frequency
Processor Graphics
Graphics Max. Dynamic Freq
PEG
LVDS
DisplayPort (DP)
HDMI
Processor TDP (Max)

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2

Specifications

2.1

Feature List
Table 1

Feature Summary

Form Factor
Processor

Memory
congatec Board
Controller
Chipset
Audio
Ethernet
Graphics Options

Based on COM Express™ standard pinout Type 6 Rev. 2.1 (Compact size 95 x 95 mm).
Intel® Core™ i7-4650U 1.7 GHz Dual Core™ with 4-MByte Intel® Smart Cache
Intel® Core™ i5-4300U 1.9 GHz Dual Core™ with 3-MByte Intel® Smart Cache
Intel® Core™ i3-4010U 1.7 GHz Dual Core™ with 3-MByte Intel® Smart Cache
Intel® Celeron® 2980U 1.6 GHz Dual Core™ with 2-MByte Intel® Smart Cache
2 sockets: SO-DIMM DDR3L (Low voltage @ 1.35V) up to 1600MT/s, with 16GB maximum capacity. Sockets located top and bottom side of module.
Multi-stage watchdog, non-volatile user data storage, manufacturing and board information, board statistics, BIOS setup data backup, I2C bus, Power
loss control.

Intel® 8 Series PCH-LP integrated in the Multi-Chip Package (MCP).
High Definition Audio (HDA)/digital audio interface with support for multiple codecs
Gigabit Ethernet support via the onboard Intel® l218LM GbE Phy. Also offers AMT 9.5 support.
Next Generation Intel® HD Graphics (4400/5000) with support for Intel® Clear Video Technology (HD encode/transcode, Blu-ray playback), DirectX
Video Acceleration (full AVC/VC1/MPEG2 hardware decode), OpenGL 4.0 and DirectX11.1. Up to 3 independent displays supported (Must be two DDI’s
(DP, HDMI/DVI) plus one eDP/LVDS)
• LVDS (Integrated flat panel interface with 25-112MHz single/dual-channel • DisplayPort 1.1 (DP): 2x DisplayPorts ports on digital ports B, C.
LVDS Transmitter). Supports:
Multiplexed with HDMI/DVI ports. Hot‑Plug detect support.
• Single-channel LVDS interface: 1 x 18 bpp or 1 x 24 bpp.
• HDMI 1.4: 2x HDMI ports on digital ports B, C. Multiplexed with
• Dual channel LVDS interface: 2 x 18 bpp or 2 x 24 bpp panel.
DisplayPort (DP)/DVI. Hot-plug detect support.
• VESA LVDS color mappings
• DVI: 2x DVI ports on digital ports B, C. Multiplexed with HDMI/DP
• Automatic Panel Detection via Embedded Panel Interface based on
ports. Hot‑Plug detect support.
VESA EDID™ 1.3.
• Optional VGA interface
• Resolution up to 1920x1200 in dual LVDS bus mode.
(NOTE: This option is offered on digital port C and supported only on rev.
• Optional eDP interface
C.x. and later. The display combination for revisions with VGA support is
(NOTE: Either eDP or LVDS signals supported. Both not supported).
1x DDI, 1x VGA and 1x eDP).
• 4x Serial ATA® 6Gb/s with RAID support 0/1/5/10 (Celeron variant
• 2x Serial Interface (UART0/1)
Peripheral
supports only 2x SATA 6Gb/s)
• LPC Bus
Interfaces
• 4 PCI Express® Lanes. Support for full 5 Gb/s bandwidth in each direction • I²C Bus, Fast Mode, multi-master
per x1 links. (can be configured via special/customized BIOS firmware to • SM Bus
support four x1 and one x4 links.
• SPI
• 8x USB 2.0 (EHCI)
• GPIOs
• 2x USB 3.0 (XHCI)
AMI Aptio® UEFI 2.x firmware, 8/16 MByte serial SPI with congatec Embedded BIOS features.
BIOS
Power Management • ACPI 4.0 compliant with battery support. Also supports Suspend to RAM (S3) and Intel AMT 9.5.
• Configurable TDP
• Ultra low standby power consumption, Deep Sx.
Optional discrete Trusted Platform Module “TPM”, new AES Instructions for faster and better encryption.
Security
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Note
Some of the features mentioned in the above feature summary are optional. Check the article number of your module and compare it to the
option information list on page 11 of this user’s guide to determine what options are available on your particular module.

2.2

Supported Operating Systems
The conga-TC87 supports the following operating systems.
• Microsoft® Windows® 8
• Microsoft® Windows® 7
• Microsoft® Windows® Embedded Standard
• Linux

2.3

Mechanical Dimensions
• 95.0 mm x 95.0 mm (3.74” x 3.74”)
• Height approximately 18 or 21mm (including heatspreader) depending on the carrier board connector that is used. If the 5mm
(height) carrier board connector is used, then approximate overall height is 18mm. If the 8mm (height) carrier board connector is
used, then approximate overall height is 21mm.

Heatspreader
Module PCB
4.00
13.00

7.00
5.00

18.00

2.00
4.50
Carrier Board PCB

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2.4

Supply Voltage Standard Power
• 12V DC ± 5%
The dynamic range shall not exceed the static range.
12.60V

Absolute Maximum

Dynamic Range
12.10V
12V

Nominal

Static Range

11.90V

11.40V

2.4.1

Absolute Minimum

Electrical Characteristics
Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for
pinout Type 6 (dual connector, 440 pins).
Power Rail

2.4.2

Module Pin Current Nominal Input Input Range Derated Input Max. Input Ripple Max. Module Input Power Assumed
Max. Load
Capability (Amps) (Volts)
(Volts)
(Volts)
(10Hz to 20MHz) (w. derated input)
Conversion Power
(mV)
(Watts)
Efficiency (Watts)

VCC_12V
12
VCC_5V-SBY 2

12
5

11.4-12.6
4.75-5.25

VCC_RTC

3

2.0-3.3

0.5

11.4
4.75

+/- 100
+/- 50

137
9

85%

116

+/- 20

Rise Time
The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during
the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

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2.5

Power Consumption
The power consumption values listed in this document were measured under a controlled environment. The hardware used for testing includes
a conga‑TC87 module, conga-TEVAL carrier board, hdmi-equipped LCD monitor, SATA SSD drive, and USB keyboard/mouse. The SATA drive
was powered externally by an ATX power supply so that it does not influence the power consumption value that is measured for the module.
To ensure that only the power consumption of the CPU module is measured, the conga-TEVAL power consumption was determined before the
measurement and subtracted from the overall power consumption value measured.
The USB keyboard/mouse were detached once the module was configured within the OS. All recorded values were averaged over a 30
second time period. Cooling of the module was done by the module specific heatspreader and a fan cooled heatsink to measure the power
consumption under normal thermal conditions.
Each module was measured while running Windows 7 Professional 64Bit, Hyper Threading enabled, Speed Step enabled, CPU Turbo Mode
enabled and Power Plan set to “Power Saver”. This setting ensures that Core™ processors run in LFM (lowest frequency mode) with minimal
core voltage during desktop idle. Each module was tested while using two 2GB memory modules. Using different sizes of RAM, as well as one
or two memory modules, will cause slight variances in the measured results.
To measure the worst case power consumption the cooling solution was removed and the CPU core temperature was allowed to run up to
between 90° and 95°C while running 100% workload with the Power Plan set to “Balanced”. The peak current value was then recorded. This
value should be taken into consideration when designing the system’s power supply to ensure that the power supply is sufficient during worst
case scenarios.
Power consumption values were recorded during the following stages:
Windows 7 (64 bit)
• Desktop Idle (power plan = Power Saver)
• 100% CPU workload (see note below, power plan = Power Saver)
• 100% CPU workload at approximately 100°C peak power consumption (power plan = Balanced)
• Suspend to RAM. Supply power for S3 mode is 5V.

Note
A software tool was used to stress the CPU to Max Turbo Frequency.

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Processor Information
The tables below provide additional information about the power consumption data for each of the conga-TC87 variants offered. The values
are recorded at various operating mode.

2.5.1

Intel® Core™ i7-4650U 1.7 GHz Dual Core™ 4MB Cache
Intel® Core™ i7-4650U 1.7 GHz 2 Core™ 4MB Intel® Smart Cache
22nm
Layout Rev. TU87LB1 /BIOS Rev. TU87R005

conga-TC87 Art. No. 046901
(GT3 Graphics)
Max Turbo Frequency
Memory Size
Operating System
Power State

3.3 GHz
4GB
Windows 7 (64 bit)

Desktop Idle

100% workload

100% workload in
Turbo mode (peak)

Power consumption (measured in Amperes/Watts) 0.23 A/2.8 W (12V) 1.38 A/16.6 W (12V) 2.41 A/28.9 W (12V)

2.5.2

Suspend to Ram (S3) 5V Input
Power
0.06 A/0.3 W (5V)

Intel® Core™ i5-4300U 1.9 GHz Dual Core™ 3MB Cache
Intel® Core™ i5-4300U 1.9 GHz 2 Core™ 3MB Intel® Smart Cache
22nm
Layout Rev. TU87LB1 /BIOS Rev. TU87R005

conga-TC87 Art. No. 046902
(GT2 Graphics)
Max Turbo Frequency
Memory Size
Operating System
Power State

2.9 GHz
4GB
Windows 7 (64 bit)

Desktop Idle

100% workload

100% workload in
Turbo mode (peak)

Power consumption (measured in Amperes/Watts) 0.28 A/3.4 W (12V) 1.38 A/16.6 W (12V) 1.95 A/23.4 W (12V)

Suspend to Ram (S3) 5V Input
Power
0.06 A/0.3 W (5V)

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2.5.3

Intel® Core™ i3-4010U 1.7 GHz Dual Core™ 3MB Cache
Intel® Core™ i3-4010U 1.7 GHz 2 Core™ 3MB Intel® Smart Cache
22nm
Layout Rev. TU87LB1 /BIOS Rev. TU87R005

conga-TC87 Art. No. 046903
(GT2 Graphics)
Max Turbo Frequency
Memory Size
Operating System
Power State

N/A
4GB
Windows 7 (64 bit)

Desktop Idle

100% workload

100% workload approx. Suspend to Ram (S3) 5V Input
100% CPU temp (peak) Power

Power consumption (measured in Amperes/Watts) 0.23 A/2.8 W (12V) 0.99 A/11.9 W (12V) 1.67 A/20.0 W (12V)

2.5.4

Intel® Celeron® 2980U 1.6 GHz Dual Core™ 2MB Cache
Intel® Celeron® 2980U 1.6 GHz 2 Core™ 2MB Intel® Smart Cache
22nm
Layout Rev. TU87LB1 /BIOS Rev. TU87R005

conga-TC87 Art. No. 046904
(GT2 Graphics)
Max Turbo Frequency
Memory Size
Operating System
Power State

N/A
4GB
Windows 7 (64 bit)

Desktop Idle

Power consumption (measured in Amperes/Watts) TBD

2.6

0.06 A/0.3 W (5V)

100% workload

100% workload approx. Suspend to Ram (S3) 5V Input
100% CPU temp (peak) Power

TBD

TBD

TBD

Supply Voltage Battery Power
• 2.0V-3.5V DC
• Typical 3V DC

2.6.1

CMOS Battery Power Consumption
RTC @ 20ºC

Voltage

Current

Integrated in the Intel® 8 Series PCH-LP

3V DC

9 µA

The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime. You should measure the
CMOS battery power consumption in your customer specific application in worst case conditions, for example during high temperature and high
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battery voltage. The self-discharge of the battery must also be considered when determining CMOS battery lifetime. For more information about
calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_Lifetime.pdf on congatec AG website at www.congatec.com.

2.7

Environmental Specifications
Temperature		

Operation: 0° to 60°C		

Storage: -20° to +80°C

Humidity			

Operation: 10% to 90%

Storage: 5% to 95%

Caution
The above operating temperatures must be strictly adhered to at all times. When using a heatspreader, the maximum operating temperature
refers to any measurable spot on the heatspreader’s surface.
congatec AG strongly recommends that you use the appropriate congatec module heatspreader as a thermal interface between the module
and your application specific cooling solution.
If for some reason it is not possible to use the appropriate congatec module heatspreader, then it is the responsibility of the operator to ensure
that all components found on the module operate within the component manufacturer’s specified temperature range.
For more information about operating a congatec module without heatspreader, contact congatec technical support.
Humidity specifications are for non-condensing conditions.

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3

Block Diagram
COM Express
Type 6

COM Express
Type 6
Intel® ULT SOC (CPU + PCH)

A-B Connector
CRT

Turbo Boost 2.0 Technology

PCIe Port 5
PCIe Port 4
PCIe Port 3
PCIe Port 2
PCIe Port 1
PCIe Port 0
CRT

LVDS/eDP

HT Technology

Ethernet 10/100/1000
Intel I218LM

Ethernet

PCIe5-L3

X PCIe5-L2
PCIe5-L1
X
X PCIe5-L0

X
X

PCIe3
PCIe2
PCIe1
PCIe0

X
LVDS/eDP

A-B Connector

4th Generation Intel® Core™ Processor

VGA supported only on rev. C.x and later

eDP to LVDS
Bridge

eDP

TXT

AVX2

VT

Optional DP to VGA

(Only on rev. C.x and later)

AES-NI

64 Architecture
SSE4.2

TSX

Digital Display Interfaces
DisplayPort 1.2
HDMI 1.4 (3D, 4k)
Hardware Graphics Accelerators
Vector Graphics
3D
2D
DXVA
Video Codecs
MPEG-2

APIs
OpenCL 1.2

H.264

OpenGL 4.0

WMV9

DirectX 11.1

Intel® 8 Series PCH-LP

UART0/1

SER0/1

USB 2.0

USB Port 0..7

SPI Flash
0

SPI Flash
1

SPI

Digital Display Signals

DDC

SATA0 - SATA3
LPC

AUX CH

XDP

X
X

USB 3.0 Port 0
USB 3.0 Port 1
USB 3.0 Port 2
USB 3.0 Port 3

X
X

PCIe Port 7
PCIe Port 6

2x SO-DIMM (X1/X2)
Dual Channel DDR3L

SM Bus

HUB

MGMNT
PECI

I/O Interfaces
PCIe

LPC Bus

GPIOs

SATA

USB 2.0

USB 3.0

congatec System
Management
Controller

TPM
SM Bus
I2C Bus
GPIOs
LID#/SLEEP#
FAN control

X

DP/HDMI Port C
DP/HDMI Port B
DP/HDMI Port D

Hot Plug Detect

High Definition Audio
ASRC

SPI
SATA Port 0
SATA Port 1
SATA Port 2
SATA Port 3
LPC Bus

PEG x16

Integrated Intel HD Graphics

Low Power Interconnect

HDA I/F

X

(TX BC)
congatec custom

I2C

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4

Heatspreader
An important factor for each system integration is the thermal design. The heatspreader acts as a thermal coupling device to the module and
its aluminum plate is 4mm thick. The heatspreader is thermally coupled to the CPU and other heat generating components via a heat pipe.
Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated, it is not to be considered
as a heatsink. It has been designed to be used as a thermal interface between the module and the application specific thermal solution. The
application specific thermal solution may use heatsinks with fans, and/or heat pipes, which can be attached to the heatspreader. Some thermal
solutions may also require that the heatspreader is attached directly to the systems chassis thereby using the whole chassis as a heat dissipater.
For additional information about the conga‑TC87 heatspreader, refer to section 4.1 of this document.

Caution
There are mounting holes on the heatspreader designed to attach the heatspreader to the module. These mounting holes must be used
to ensure that all components that are required to make contact with heatspreader do so. Failure to use these mounting holes will result in
improper contact between these components and heatspreader thereby reducing heat dissipation efficiency.
Attention must be given to the mounting solution used to mount the heatspreader and module into the system chassis. Do not use a threaded
heatspreader together with threaded carrier board standoffs. The combination of the two threads may be staggered, which could lead to
stripping or cross-threading of the threads in either the standoffs of the heatspreader or carrier board.

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4.1

Heatspreader Dimensions

Note
All measurements are in millimeters. Torque specification for heatspreader screws is 0.3 Nm. Mechanical system assembly mounting shall
follow the valid DIN/IS0 specifications.
Caution
When using the heatspreader in a high shock and/or vibration environment, congatec recommends the use of a thread-locking fluid on the
heatspreader screws to ensure the above mentioned torque specification is maintained.
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5

Connector Subsystems Rows A, B, C, D
The conga-TC87 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout) for a total of 440 pins connectivity.
These connectors are broken down into four rows. The primary connector consists of rows A and B while the secondary connector consists of
rows C and D.
In this view the connectors are seen “through” the module.

A-B
4 PCI Express Lanes
4x Serial ATA
8x USB 2.0
High Definition Audio I/F
Gigabit Ethernet

(connected via a x1 PCI Express Lane)

LPC Bus
2x Serial Interface (UART)
I²C Bus Fast Mode
LVDS/eDP
SM Bus
SPI
GPIOs
Power Control
Power Management
Fan Control

C-D
2x USB 3.0
2x HDMI

(Routed to DDI interface at
connector)

2x DVI

(Routed to DDI interface at
connector)

2x DisplayPort (DP)

(Routed to DDI interface at
connector)

1x VGA (optional)

(supported only on rev. C.x and
later)

C-D
A-B

top view
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5.1

Primary Connector Rows A and B
The following subsystems can be found on the primary connector rows A and B.

5.1.1

Serial ATA™ (SATA)
The conga-TC87 provides 4 SATA interfaces (SATA 0-3) externally via the Intel® 8 Series PCH-LP integrated in the MCP. The SATA ports are
based on Serial ATA Specification, Revision 3.0 and support up to 6.0 Gb/s data transfer rates.
The Intel® 8 Series PCH-LP featured on the conga-TC87 has one integrated SATA host controller. This controller does not support legacy mode
using I/O space, rather it supports only one mode of operation - AHCI mode using memory space. Hot-plug is also supported when operating
in non-native IDE mode. For more information, refer to section 10 “BIOS Setup Description”.
Note
The conga-TC87 Celeron variants support up to 2 SATA interfaces only.

5.1.2

USB 2.0
The conga-TC87 offers 8 USB 2.0 interfaces on the A-B connector. The EHCI host controller in the PCH supports these interfaces with highspeed, full-speed and low-speed USB signalling. The controller complies with USB standard 1.1 and 2.0. For more information about how the
USB host controllers are routed, see section 7.5.

5.1.3

High Definition Audio (HDA) Interface
The conga-TC87 provides an interface that supports the connection of HDA audio codecs.

5.1.4

Gigabit Ethernet
The conga-TC87 is equipped with a Gigabit Ethernet Controller that is integrated within the Intel® 8 Series PCH-LP. This controller is routed
to the onboard Intel® l218-LM Phy through the use of the fifth PCI Express lane. The Ethernet interface consists of 4 pairs of low voltage
differential pair signals designated from GBE0_MD0± to GBE0_MD3± plus control signals for link activity indicators. These signals can be used
to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board.
Note
The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection. It is not active during a 10Mbit connection. This is a limitation

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of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the
GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TC87 module.

5.1.5

LPC Bus
conga-TC87 offers the LPC (Low Pin Count) bus through the Intel® 8 Series PCH-LP. There are many devices available for this Intel® defined
bus. The LPC bus corresponds approximately to a serialized ISA bus yet with a significantly reduced number of signals. Due to the software
compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application specific baseboard
using this bus. See section 9.1.1 for more information about the LPC Bus.

5.1.6

I²C Bus Fast Mode
The I²C bus is implemented through the congatec board controller (TI Stellaris® LM4FS11H5BB) and accessed through the congatec CGOS
driver and API. The controller provides a Fast Mode multi-master I²C Bus that has maximum I²C bandwidth.

5.1.7

PCI Express™
The conga-TC87 offers 5 PCI Express™ lanes via the Intel® 8 Series PCH-LP. Four of these lanes are offered externally on the A-B connector.
The remaining lane is used by the onboard Gigabit Ethernet interface. The lanes are Gen 2 compliant and offer support for full 5 Gb/s bandwidth
in each direction per x1 link.
Default configuration for the lanes on the AB connector is 4x1 link. A 1x4 and 2x2 link configuration is also possible but requires a special/
customized BIOS firmware. Contact congatec technical support for more information about this subject.
The PCI Express interface is based on the PCI Express Specification 2.0 with Gen 1 (2.5Gb/s) and Gen 2 (5 Gb/s) speed.

5.1.8

ExpressCard™
The conga-TC87 supports the implementation of ExpressCards, which requires the dedication of one USB 2.0 port or a x1 PCI Express link
for each ExpressCard used.

5.1.9

Graphics Output (VGA/CRT)
The Intel® ULT SoC does not support VGA interface. However on the conga-TC87 rev C.x and later, an optional VGA interface is supported on
the DDI digital port C via NXP PTN3392BS Displayport to VGA controller.

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5.1.10

LCD (LVDS/eDP)
The conga-TC87 offers an LVDS/eDP interface on the AB connector. The LVDS/eDP interface is by default configured to provide LVDS signals.
The interface can optionally be switched via the BIOS setup menu to support eDP signals.
The single/dual channel LVDS interface is provided through an onboard eDP to LVDS bridge device. The eDP to LVDS bridge processes
incoming DisplayPort stream and converts the DP protocol to LVDS, before transmitting the processed stream in LVDS format. The bridge
supports single and dual channel signalling with color depths of 18 bits or 24 bits per pixel and pixel clock frequency up to 112 MHz.

Note
The LVDS/eDP interface supports either LVDS or eDP signals. Both signals are not supported simultaneously.

5.1.11

General Purpose Serial Interface
Two TTL compatible two wire ports are available on Type 6 COM Express modules. These pins are designated SER0_TX, SER0_RX, SER1_TX
and SER1_RX. Data out of the module is on the _TX pins. Hardware handshaking and hardware flow control are not supported. The module
asynchronous serial ports are intended for general purpose use and for use with debugging software that make use of the “console redirect”
features available in many operating systems.
The conga-TC87 offers two UART interfaces via two UART controllers integrated in the congatec Board Controller. These controllers support
up to 1MBit/s and can operate in low-speed, full-speed and high-speed modes. The UART interfaces are routed to the AB connector and
require congatec driver to function..

Note
The UART interfaces do not support legacy COM port emulation.

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5.1.12

Power Control
PWR_OK
Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module can
start its onboard power sequencing.
Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low
at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier
board power rails are up, to ensure a stable system.
A sample screenshot is shown below:

Note
The module is kept in reset as long as the PWR_OK is driven by carrier board hardware.
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The conga-TC87 PWR_OK input circuitry is implemented as shown below:

+V12.0_S0

R4
R1%100kS02

R1
R1%47k5S02
R13
R1%1k00S02
PWR_OK
R2
R1%20k0S02

TB
TBC847

To Module Power Logic

R5
R1%47k5S02

The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also allows for carrier board designs that are not driving
PWR_OK. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier
board hardware drives the signal low until it is safe to let the module boot-up.
When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be
only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specification but this
can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when
the carrier board hardware is ready to boot.
The three typical usage scenarios for a carrier board design are:
• Connect PWR_OK to the “power good” signal of an ATX type power supply.
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• Connect PWR_OK to the last voltage regulator in the chain on the carrier board.
• Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.
With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.
The conga-TC87 provides support for controlling ATX-style power supplies. When not using an ATX power supply then the conga-TC87’s pins
SUS_S3/PS_ON, 5V_SB, and PWRBTN# should be left unconnected.
SUS_S3#/PS_ON#
The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an ATXstyle power supply. In order to accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and
is located on the carrier board.
PWRBTN#
When using ATX-style power supplies PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary‑contact, active-low
debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to
3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this
signal from the system may vary as a result of modifications made in BIOS settings or by system software.

Power Supply Implementation Guidelines
12 volt input power is the sole operational power source for the conga-TC87. The remaining necessary voltages are internally generated on
the module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing
a power supply for a conga-TC87 application:
• It has also been noticed that on some occasions, problems occur when using a 12V power supply that produces non monotonic voltage
when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals
when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming
confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply
applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use
of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. This should be done during the power supply
qualification phase therefore ensuring that the above mentioned problem doesn’t arise in the application. For more information about this
issue visit www.formfactors.org and view page 25 figure 7 of the document “ATX12V Power Supply Design Guide V2.2”.

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5.1.13

Power Management
ACPI
The conga-TC87 supports Advanced Configuration and Power Interface (ACPI) specification, revision 4.0a. It also supports Suspend to RAM
(S3). For more information, see section 7.3 “ACPI Suspend Modes and Resume Events”.
DEEP Sx
The Deep Sx is a lower power state employed to minimize the power consumption while in S3/S4/S5. In the Deep Sx state, the system entry
condition determines if the system context is maintained or not. All power is shut off except for minimal logic which supports limited set of wake
events for Deep Sx. The Deep Sx on resumption, puts system back into the state it is entered from. In other words, if Deep Sx state was entered
from S3 state, then the resume path will place system back into S3.

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5.2

Secondary Connector Rows C and D
The following subsystems can be found on the secondary connector rows C and D.

5.2.1

PCI Express™
The conga-TC87 does not offer PCI Express lanes on the CD connector. For more information on supported PCI Express lanes, see section
5.1.7.

5.2.2

PCI Express Graphics (PEG)
The Intel® ULT SoC does not support PEG interface.

5.2.3

Digital Display Interface
The conga-TC87 supports two Digital Display Interfaces. These interfaces can be configured as DisplayPort, HDMI/DVI. On conga-TC87 rev
C.x and later, the DDI digital port C is used for optional VGA support.
The processor on the conga-TC87 supports High-bandwidth Digital Content Protection (HDCP) for playing high definition content over digital
interfaces. Integrated in the processor is a dedicated Mini HD audio controller which drives audio on integrated digital display interfaces such
as HDMI and DisplayPort.
The conga-TC87 offers the Digital Display Interface on the CD connector and supports up to three independent displays. The display combination
must be 2 DDI and 1 eDP. For revisions equipped with optional VGA, the combination must be 1x DDI (Port B), 1x VGA (via Port C) and 1x
eDP. The table below shows the conga-TC87 display combination and is not applicable to revisions equipped with optional VGA interface.
Table 2

Display Combination (U-processor line)

Display 1
(DDI Port B)

Display 2
(DDI Port C)

Display 3

Display 1
Max. Resolution

Display 2
Max. Resolution

Display 3
Max. Resolution

HDMI
DP
HDMI

HDMI
DP
DP

eDP
eDP
eDP

4096x2304 @24Hz
3200x2000 @60Hz
4096x2304 @24Hz

4096x2304 @24Hz
3200x2000 @60Hz
3200x2000 @60Hz

3200x2000 @60Hz
3200x2000 @60Hz
3200x2000 @60Hz

Note
The DP and eDP resolutions in the table above are supported for 4 lanes with link data rate HBR2 at 24 bits per pixel and single stream mode
of operation. The DisplayPort Aux CH, DDC channel, panel power sequencing and HPD are supported through the PCH.
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5.2.3.1

HDMI
The conga-TC87 offers two HDMI ports on the CD connector via the Digital Display Interfaces supported by the processor. The HDMI interfaces
are based on HDMI 1.4 specification with support for 3D, 4K, Deep Color and x.v Color. These interfaces are multiplexed onto the Digital
Display Interface of the COM Express connector.
Supported audio formats are AC-3 Dolby Digital, Dolby Digital Plus, DTS-HD, LPCM, 192 KHz/24 bit, 8 channel, Dolby TrueHD, DTS-HD
Master Audio (Lossless Blu-Ray Disc Audio Format).

Note
The conga-TC87 supports a maximum of 2 independent HDMI displays. Revisions equipped with optional VGA interface support only 1 HDMI
interface. See table 2 above for possible display combinations. Consumer electronics control (CEC) is not supported.

5.2.3.2

DVI
The conga-TC87 offers two DVI ports on the CD connector. The DVI interfaces are multiplexed onto the Digital Display Interface of the COM
Express connector.

Note
The conga-TC87 supports a maximum of 2 independent DVI displays. Revisions equipped with optional VGA interface support only 1 DVI
interface. See table 2 above for possible display combinations.

5.2.3.3

DisplayPort (DP)
The conga-TC87 offers two DP ports, each capable of supporting data rate of 1.62 GT/s, 2.97 GT/s and 5.4 GT/s on 1, 2 or 4 data lanes. The
DP is multiplexed onto the Digital Display Interface (DDI) of the COM Express connector and can support up to 3200x2000 resolutions at 60Hz.
The DisplayPort specification is a VESA standard aimed at consolidating internal and external connection methods to reduce device complexity,
supporting key cross industry applications, and providing performance scalability to enable the next generation of displays. See section 8.5 of
this document for more information about enabling DisplayPort peripherals.

Note
The conga-TC87 supports a maximum of 2 independent DisplayPort displays. Revisions equipped with optional VGA interface support only 1
DP interface. See table 2 above for possible display combinations.

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5.2.4

USB 3.0
The conga-TC87 offers two SuperSpeed USB 3.0 ports on the CD connector. These ports are controlled by an xHCI host controller provided
by the Intel® 8 Series PCH-LP integrated in the MCP. The host controller allows data transfers of up to 5 Gb/s and supports SuperSpeed, highspeed, full-speed and low-speed traffic.

Note
The xHCI controller supports USB 3.0 debugging.

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6

Additional Features

6.1

congatec Board Controller (cBC)
The conga-TC87 is equipped with Texas Instruments Tiva™ TM4E1231H6ZRB microcontroller. This onboard microcontroller plays an important
role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features such as system monitoring
or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86
processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all congatec modules.

6.2

Board Information
The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and firmware
revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

6.3

Watchdog
The conga-TC87 is equipped with a multi stage watchdog solution that is triggered by software. The COM Express™ Specification does not
provide support for external hardware triggering of the Watchdog, which means the conga-TC87 does not support external hardware triggering.
For more information about the Watchdog feature, see the BIOS setup description in section 10.4.2 of this document and application note
AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.

Note
The conga-TC87 module does not support the watchdog NMI mode. COM Express type 6 modules do not support the PCI bus, therefore the
PCI_SERR# signal is not available. There is no way to drive an NMI to the processor without the presence of the PCI_SERR# PCI bus signal.

6.4

I2C Bus
The conga-TC87 supports I2C bus. Thanks to the I2C host controller in the cBC, the I2C bus is multi-master capable and runs at fast mode.

6.5

Power Loss Control
The cBC has full control of the power-up of the module and therefore can be used to specify the behavior of the system after an AC power loss
condition. Supported modes are “Always On”, “Remain Off” and “Last State”.

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6.6

Embedded BIOS
The conga-TC87 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI firmware. These are
the most important embedded PC features:

6.6.1

CMOS Backup in Non Volatile Memory
A copy of the CMOS memory (SRAM) is stored in the BIOS flash device. This prevents the system from booting up with the wrong system
configuration if the backup battery (RTC battery) fails. Additionally, it provides the ability to create systems that do not require a CMOS backup
battery.

6.6.2

OEM CMOS Default Settings and OEM BIOS Logo
This feature allows system designers to create and store their own CMOS default configuration and BIOS logo (splash screen) within the BIOS
flash device. Customized BIOS development by congatec for these changes is no longer necessary because customers can easily do these
changes by themselves using the congatec system utility CGUITL.

6.6.3

OEM BIOS Code
With the congatec embedded BIOS it is even possible for system designers to add their own code to the BIOS POST process. Except for
custom specific code, this feature can also be used to support Win XP SLP installation, Window 7 SLIC table, verb tables for HDA codecs, rare
graphic modes and Super I/O controllers.
For more information about customizing the congatec embedded BIOS refer to the congatec System Utility user’s guide, which is called
CGUTLm1x.pdf and can be found on the congatec AG website at www.congatec.com or contact congatec technical support.

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6.6.4

congatec Battery Management Interface
In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec AG defined an interface for
the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according
to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable
operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...), without the need
for additional modifications to the system BIOS.
The conga-TC87 BIOS fully supports this interface. For more information about this subject visit the congatec website and view the following
documents:
• congatec Battery Management Interface Specification
• Battery System Design Guide
• conga-SBM3 User’s Guide

6.6.5

API Support (CGOS/EAPI)
In order to benefit from the above mentioned non-industry standard feature set, congatec provides an API that allows application software
developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming
Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux.
The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules.
All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software
developers guide, which is available on the congatec website .
Other COM (Computer on Modules) vendors offer similar driver solutions for these kind of embedded PC features, which are by nature
proprietary. All the API solutions that can be found on the market are not compatible to each other. As a result, writing application software that
can run on more than one vendor’s COM is not so easy. Customers have to change their application software when switching to another COM
vendor. EAPI (Embedded Application Programming Interface) is a programming interface defined by the PICMG that addresses this problem.
With this unified API it is now possible to run the same application on all vendor’s COMs that offer EAPI driver support. Contact congatec
technical support for more information about EAPI.

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6.7

Security Features
The conga-TC87 can be equipped optionally with a “Trusted Platform Module“ (TPM 1.2). This TPM 1.2 includes coprocessors to calculate
efficient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive applications
like gaming and e-commerce will benefit also with improved authentication, integrity and confidence levels.

6.8

Suspend to Ram
The Suspend to RAM feature is available on the conga-TC87.

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7

conga Tech Notes
The conga-TC87 has some technological features that require additional explanation. The following section will give the reader a better
understanding of some of these features. This information will also help to gain a better understanding of the information found in the System
Resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.

7.1

Intel® PCH-LP Features

7.1.1

Intel® Rapid Storage Technology
The Intel® 8 Series PCH-LP provides support for Intel® Rapid Storage Technology, allowing AHCI functionality and RAID 0/1/5/10 support.

7.1.1.1

AHCI
The Intel® 8 Series PCH-LP provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface
for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as port independent DMA engines
(each device is treated as a master) and hardware-assisted native command queuing. AHCI also provides usability enhancements such as
Hot-Plug and advanced power management.

7.1.1.2

RAID
The industry-leading RAID capability provides high performance RAID 0, 1, 5, and 10 functionality on the 4 SATA ports of Intel® 8 Series
PCH-LP. Software components include an Option ROM for pre‑boot configuration and boot functionality, a Microsoft* Windows* compatible
driver, and a user interface for configuration and management of the RAID capability of the Intel® 8 Series PCH-LP.

7.1.1.3

Intel® Smart Response Technology
Intel® Smart Response Technology is a disk caching solution that can provide improved computer system performance with improved
power savings. It allows configuration of a computer systems with the advantage of having HDDs for maximum storage capacity with system
performance at or near SSD performance levels.

Note
This feature requires an Intel® Core Processor

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7.1.2

Intel® Rapid Start Technology
Intel® Rapid Start Technology enables systems to quickly resume from deep sleep. With this feature enabled, the system resumes smoothly
and faster than with fresh Start Up or Resume from Hibernate, while maintaining the previous activity of the user.

Note
This feature requires an Intel® Core Processor

7.2

Intel® Processor Features

7.2.1

Intel® Turbo Boost Technology
Intel® Turbo Boost Technology allows processor cores to run faster than the base operating frequency if it’s operating below power, current, and
temperature specification limits. Intel® Turbo Boost Technology is activated when the Operating System (OS) requests the highest processor
performance state. The maximum frequency of Intel® Turbo Boost Technology is dependent on the number of active cores. The amount of time
the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment. Any of the following
can set the upper limit of Intel® Turbo Boost Technology on a given workload:
• Number of active cores
• Estimated current consumption
• Estimated power consumption
• Processor temperature
When the processor is operating below these limits and the user’s workload demands additional performance, the processor frequency will
dynamically increase by 100 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of
active cores is reached. For more information about Intel® Turbo Boost 2 Technology visit the Intel® website.

Note
Only conga-TC87 module variants that feature the Core™ i7 and i5 processors support Intel® Turbo Boost 2 Technology. Refer to the power
consumption tables in section 2.5 of this document for information about the maximum turbo frequency available for each variant of the
conga-TC87.

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7.2.2

Thermal Monitor and Catastrophic Thermal Protection
Intel® Core™ i7/i5/i3 and Celeron® processors have a thermal monitor feature that helps to control the processor temperature. The integrated
TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation temperature that
the Intel® Thermal Monitor uses to activate the TCC can be slightly modified via TCC Activation Offset in BIOS setup submenu “CPU submenu”.
The Thermal Monitor can control the processor temperature through the use of two different methods defined as TM1 and TM2. TM1 method
consists of the modulation (starting and stopping) of the processor clocks at a 50% duty cycle. The TM2 method initiates an Enhanced Intel
Speedstep transition to the lowest performance state once the processor silicon reaches the maximum operating temperature.

Note
The maximum operating temperature for Intel® Core™ i7/i5/i3 and Celeron® processors is 100°C.
To ensure that the TCC is active for only short periods of time, thus reducing the impact on processor performance to a minimum, it is necessary
to have a properly designed thermal solution. The Intel® Core™ i7/i5/i3 and Celeron® processor’s respective datasheet can provide you with
more information about this subject.
THERMTRIP# signal is used by Intel®’s Core™ i7/i5/i3 and Celeron® processors for catastrophic thermal protection. If the processor’s silicon
reaches a temperature of approximately 125°C then the processor signal THERMTRIP# will go active and the system will automatically shut
down to prevent any damage to the processor as a result of overheating. The THERMTRIP# signal activation is completely independent from
processor activity and therefore does not produce any bus cycles.

Note
In order for THERMTRIP# to be able to automatically switch off the system, it is necessary to use an ATX style power supply.

7.2.3

Processor Performance Control
Intel® Core™ i7/i5/i3 and Celeron® processors found on the conga-TC87 run at different voltage/frequency states (performance states), which
is referred to as Enhanced Intel® SpeedStep® technology (EIST). Operating systems that support performance control take advantage of
microprocessors that use several different performance states in order to efficiently operate the processor when it’s not being fully used.
The operating system will determine the necessary performance state that the processor should run at so that the optimal balance between
performance and power consumption can be achieved during runtime.
The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that the
power scheme setting you choose has the ability to support Enhanced Intel® SpeedStep® technology.

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7.2.4

Intel® 64 Architecture
The formerly known Intel® Extended Memory 64 Technology is an enhancement to Intel®’s IA-32 architecture. Intel® 64 is only available on
Intel® Core™ i7/i5/i3 and Celeron® processors and is designed to run with newly written 64-bit code and access more than 4GB of memory.
Processors with Intel® 64 architecture support 64-bit-capable operating systems from Microsoft, Red Hat and SuSE. Processors running in
legacy mode remain fully compatible with today’s existing 32-bit applications and operating systems
Platforms with Intel® 64 can be run in three basic ways :
1. Legacy Mode: 32-bit operating system and 32-bit applications. In this mode no software changes are required, however the benefits of
Intel® 64 are not utilized.
2. Compatibility Mode: 64-bit operating system and 32-bit applications. This mode requires all device drivers to be 64-bit. The operating
system will see the 64-bit extensions but the 32-bit application will not. Existing 32-bit applications do not need to be recompiled and may
or may not benefit from the 64-bit extensions. The application will likely need to be re-certified by the vendor to run on the new 64-bit
extended operating system.
3. 64-bit Mode: 64-bit operating system and 64-bit applications. This usage requires 64-bit device drivers. It also requires applications to be
modified for 64‑bit operation and then recompiled and validated.
Intel® 64 supports:
• 64-bit flat virtual address space
• 64-bit pointers
• 64-bit wide general purpose registers
• 64-bit integer support
• Up to one Terabyte (TB) of platform address space
You can find more information about Intel® 64 Technology at: http://developer.intel.com/technology/intel64/index.htm

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7.2.5

Intel® Virtualization Technology
Virtualization solutions enhanced by Intel® VT will allow a Core™ i7/i5/i3 platform to run multiple operating systems and applications in
independent partitions. When using virtualization capabilities, one computer system can function as multiple “virtual” systems. With processor
and I/O enhancements to Intel®’s various platforms, Intel® Virtualization Technology can improve the performance and robustness of today’s
software-only virtual machine solutions.
Intel® VT is a multi-generational series of extensions to Intel® processor and platform architecture that provides a new hardware foundation for
virtualization, establishing a common infrastructure for all classes of Intel® based systems. The broad availability of Intel® VT makes it possible
to create entirely new applications for virtualization in servers, clients as well as embedded systems thus providing new ways to improve
system reliability, manageability, security, and real-time quality of service.
The success of any new hardware architecture is highly dependent on the system software that puts its new features to use. In the case of
virtualization technology, that support comes from the virtual machine monitor (VMM), a layer of software that controls the underlying physical
platform resources sharing them between multiple “guest” operating systems. Intel® VT is already incorporated into most commercial and opensource VMMs including those from VMware, Microsoft, XenSource, Parallels, Virtual Iron, Jaluna and TenAsys.
You can find more information about Intel® Virtualization Technology at: http://developer.intel.com/technology/virtualization/index.htm

Note
congatec does not offer virtual machine monitor (VMM) software. All VMM software support questions and queries should be directed to the
VMM software vendor and not congatec technical support.

7.2.6

Thermal Management
ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the
operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands
put on the CPU by the application.
The conga-TC87 supports Critical Trip Point. This cooling policy ensures that the operating system shuts down properly if the temperature in
the thermal zone reaches a critical point, in order to prevent damage to the system as a result of high temperatures. Use the “critical trip point”
setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system.

Note
The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the
appropriate trip points.

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7.3

ACPI Suspend Modes and Resume Events
conga-TC87 supports S3 (STR= Suspend to RAM). For more information about S3 wake events, see section 10.4.5 “ACPI Configuration
Submenu”.
S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by the following operating systems (S4_OS= Hibernate):
• Windows 8, Windows 7, Windows Vista, Linux.
This table lists the “Wake Events” that resume the system from S3 unless otherwise stated in the “Conditions/Remarks” column:
Wake Event

Conditions/Remarks

Power Button
Onboard LAN Event
SMBALERT#
PCI Express WAKE#
PME#

Wakes unconditionally from S3-S5.
Device driver must be configured for Wake On LAN support.
Wakes unconditionally from S3-S5.
Wakes unconditionally from S3-S5.
Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On
PME# to Enabled in the Power setup menu.
USB Mouse/Keyboard Event
When Standby mode is set to S3, USB hardware must be powered by standby power source.
Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program).
In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer
out of standby’.
RTC Alarm
Activate and configure Resume On RTC Alarm in the Power setup menu. Only available in S5.
Watchdog Power Button Event Wakes unconditionally from S3-S5.

7.4

Low Voltage Memory (DDR3L)
The Haswell ULT processor featured on the conga-TC87 supports low voltage system memory interface. The memory interface I/O voltage
is 1.35V and supports non-ECC, unbuffered DDR3L SO-DIMMs. With this low voltage system memory interface on the processor, the congaTC87 offers a system optimized for lowest possible power consumption. The reduction in power consumption due to lower voltage subsequently
reduces the heat generated.

Caution
The usage of DDR3@1.5V SO-DIMM modules may affect the stability or boot-up of the conga-TC87. Therefore use only non-ECC, unbuffered
DDR3L SO-DIMM memory modules up to 1600 MT/s on the conga-TC87.

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7.5

USB 2.0 EHCI Host Controller Support
The 8 available USB ports are provided by a USB 2.0 Rate Matching Hub (RMH) integrated within the Intel® 8 Series PCH-LP . The EHCI
controller is connected to the hub as shown below. The Hub convert low and full-speed traffic into high-speed traffic. When the RMHs are
enabled, they will appear to software like an external hub is connected to Port 0 of the EHCI controller. In addition, port 1 of the RMH is
multiplexed with Port 1 of the EHCI controller and is able to bypass the RMH for use as the Debug Port. The hub operates like any USB 2.0
Discrete Hub and will consume one tier of hubs allowed by the USB 2.0 Spec. A maximum of four additional non-root hubs can be supported
on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 8000h.
Routing Diagram

EHCI #1
USB 2.0 Rate Matching Hub

Internal Port:

Port 0

Ports swapped on revision C.x and later
to support Debug Port on COM Express Port 0

COM Express Port:

{

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

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8

Signal Descriptions and Pinout Tables
The following section describes the signals found on COM Express™ Type VI connectors used for congatec AG modules. The pinout of the
modules complies with COM Express Type 6 Rev. 2.1.
Table 3 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express™
module pull-up or pull-down resistor has been used. If the field entry area in this column for the signal is empty, then no pull-up or pull-down
resistor has been implemented by congatec.
The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When
“#” is not present, the signal is asserted when at a high voltage level.
Note
The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented
by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip’s
datasheet.
Table 3

Signal Tables Terminology Descriptions

Term

Description

PU
PD
I/O 3.3V
I/O 5V
I 3.3V
I 5V
I/O 3.3VSB
O 3.3V
O 5V
OD
P
DDC
PCIE
PEG
SATA
REF
PDS

congatec implemented pull-up resistor
congatec implemented pull-down resistor
Bi-directional signal 3.3V tolerant
Bi-directional signal 5V tolerant
Input 3.3V tolerant
Input 5V tolerant
Input 3.3V tolerant active in standby state
Output 3.3V signal level
Output 5V signal level
Open drain output
Power Input/Output
Display Data Channel
In compliance with PCI Express Base Specification, Revision 2.0
PCI Express Graphics
In compliance with Serial ATA specification Revision 2.6 and 3.0.
Reference voltage output. May be sourced from a module power plane.
Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal
module capabilities (pinout type) to the Carrier Board.

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8.1

A-B Connector Signal Descriptions
Table 4

Intel® High Definition Audio Link Signals Descriptions

Signal

Pin #

Description

I/O

Intel® High Definition Audio Reset: This signal is the master hardware reset
to external codec(s).
AC/HDA_SYNC
A29
Intel® High Definition Audio Sync: This signal is a 48 kHz fixed rate sample
sync to the codec(s). It is also used to encode the stream number.
AC/HDA_BITCLK
A32
Intel® High Definition Audio Bit Clock Output: This signal is a 24.000MHz
serial data clock generated by the Intel® High Definition Audio controller.
AC/HDA_SDOUT
A33
Intel® High Definition Audio Serial Data Out: This signal is the serial TDM
data output to the codec(s). This serial output is double-pumped for a bit rate
of 48 Mb/s for Intel® High Definition Audio.
AC/HDA_SDIN[2:0] B28-B30 Intel® High Definition Audio Serial Data In [0]: These signals are serial TDM
data inputs from the three codecs. The serial input is single-pumped for a bit
rate of 24 Mb/s for Intel® High Definition Audio.

AC/HDA_RST#

A30

PU/PD Comment

O 3.3VSB

AC’97 codecs are not supported.

O 3.3VSB

AC’97 codecs are not supported.

O 3.3VSB

AC’97 codecs are not supported.

O 3.3VSB

I 3.3VSB

PU 1K
3.3VSB

AC’97 codecs are not supported.
AC/HDA_SDOUT is a boot strap signal
(see note below)
AC’97 codecs are not supported.

Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.
For more information refer to section 8.5 of this user’s guide.

Table 5

Gigabit Ethernet Signal Descriptions

Gigabit Ethernet Pin # Description

I/O

GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3-

A13
A12
A10
A9
A7
A6
A3
A2

I/O Analog

GBE0_ACT#
GBE0_LINK#
GBE0_LINK100#
GBE0_LINK1000#

B2
A8
A4
A5

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate
in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:
1000
100
10
MDI[0]+/B1_DA+/TX+/MDI[1]+/B1_DB+/RX+/MDI[2]+/B1_DC+/MDI[3]+/B1_DD+/Gigabit Ethernet Controller 0 activity indicator, active low.
Gigabit Ethernet Controller 0 link indicator, active low.
Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.
Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.

TX+/RX+/-

PU/PD Comment
Twisted pair
signals for
external
transformer.

O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB

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Gigabit Ethernet Pin # Description
GBE0_CTREF

A14

I/O

Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is
determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the module. In the case in which the reference is shorted
to ground, the current shall be limited to 250mA or less.

PU/PD Comment
Not connected

Note
The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection, it is not active during a 10Mbit connection. This is a limitation
of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the
GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TC87 module.

Table 6

Serial ATA Signal Descriptions

Signal

Pin # Description

I/O

SATA0_RX+
SATA0_RXSATA0_TX+
SATA0_TXSATA1_RX+
SATA1_RXSATA1_TX+
SATA1_TXSATA2_RX+
SATA2_RXSATA2_TX+
SATA2_TXSATA3_RX+
SATA3_RXSATA3_TX+
SATA3_TX(S)ATA_ACT#

A19
A20
A16
A17
B19
B20
B16
B17
A25
A26
A22
A23
B25
B26
B22
B23
A28

Serial ATA channel 0, Receive Input differential pair.

I SATA

PU/PD

Comment
Supports Serial ATA specification, Revision 3.0

Serial ATA channel 0, Transmit Output differential pair.

O SATA

Supports Serial ATA specification, Revision 3.0

Serial ATA channel 1, Receive Input differential pair.

I SATA

Supports Serial ATA specification, Revision 3.0

Serial ATA channel 1, Transmit Output differential pair.

O SATA

Supports Serial ATA specification, Revision 3.0

Serial ATA channel 2, Receive Input differential pair.

I SATA

Supports Serial ATA specification, Revision 3.0

Serial ATA channel 2, Transmit Output differential pair.

O SATA

Supports Serial ATA specification, Revision 3.0

Serial ATA channel 3, Receive Input differential pair.

I SATA

Supports Serial ATA specification, Revision 3.0

Serial ATA channel 3, Transmit Output differential pair.

O SATA

Supports Serial ATA specification, Revision 3.0

ATA (parallel and serial) or SAS activity indicator, active low. I/O 3.3v

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Table 7

PCI Express Signal Descriptions (general purpose)

Signal

Pin # Description

I/O

PCIE_RX0+
PCIE_RX0PCIE_TX0+
PCIE_TX0PCIE_RX1+
PCIE_RX1PCIE_TX1+
PCIE_TX1PCIE_RX2+
PCIE_RX2PCIE_TX2+
PCIE_TX2PCIE_RX3+
PCIE_RX3PCIE_TX3+
PCIE_TX3PCIE_RX4+
PCIE_RX4PCIE_TX4+
PCIE_TX4PCIE_RX5+
PCIE_RX5PCIE_TX5+
PCIE_TX5PCIE_CLK_REF+
PCIE_CLK_REF-

B68
B69
A68
A69
B64
B65
A64
A65
B61
B62
A61
A62
B58
B59
A58
A59
B55
B56
A55
A56
B52
B53
A52
A53
A88
A89

PCI Express channel 0, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 0, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 1, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 1, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 2, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 2, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 3, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 3, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 2.0

PCI Express channel 4, Receive Input differential pair.

I PCIE

Not supported

PCI Express channel 4, Transmit Output differential pair.

O PCIE

Not supported

PCI Express channel 5, Receive Input differential pair.

I PCIE

Not supported

PCI Express channel 5, Transmit Output differential pair.

O PCIE

Not supported

PCI Express Reference Clock output for all PCI Express
and PCI Express Graphics Lanes.

O PCIE

A PCI Express Gen2/3 compliant clock buffer chip must be used
on the carrier board if more than one PCI Express device is
designed in.

Table 8

PU/PD

Comment

ExpressCard Support Pins Signal Descriptions

Signal

Pin #

Description

I/O

PU/PD

EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#

A49
B48
A48
B47

ExpressCard capable card request.

I 3.3V

PU 10k 3.3V

ExpressCard Reset

O 3.3V

PU 10k 3.3V

Comment

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Table 9

LPC Signal Descriptions

Signal

Pin #

Description

I/O

LPC_AD[0:3]
LPC_FRAME#
LPC_DRQ[0:1]#
LPC_SERIRQ
LPC_CLK

B4-B7
B3
B8-B9
A50
B10

LPC multiplexed address, command and data bus
LPC frame indicates the start of an LPC cycle
LPC serial DMA request
LPC serial interrupt
LPC clock output - 24 MHz nominal

I/O 3.3V
O 3.3V
I 3.3V
PU 10k 3.3V
I/O OD 3.3V PU 10k 3.3V
O 3.3V

Table 10

PU/PD

Comment

USB Signal Descriptions

Signal

Pin # Description

I/O

USB0+
USB0USB1+
USB1USB2+
USB2USB3+
USB3USB4+
USB4USB5+
USB5USB6+
USB6USB7+
USB7USB_0_1_OC#

A46
A45
B46
B45
A43
A42
B43
B42
A40
A39
B40
B39
A37
A36
B37
B36
B44

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PU 10k
3.3VSB 3.3VSB

USB_2_3_OC#

A44

USB_4_5_OC#

B38

USB_6_7_OC#

A38

USB Port 0, data + or D+
USB Port 0, data - or DUSB Port 1, data + or D+
USB Port 1, data - or DUSB Port 2, data + or D+
USB Port 2, data - or DUSB Port 3, data + or D+
USB Port 3, data - or DUSB Port 4, data + or D+
USB Port 4, data - or DUSB Port 5, data + or D+
USB Port 5, data - or DUSB Port 6, data + or D+
USB Port 6, data - or DUSB Port 7, data + or D+
USB Port 7, data - or DUSB over-current sense, USB ports 0 and 1. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low.
USB over-current sense, USB ports 2 and 3. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low. .
USB over-current sense, USB ports 4 and 5. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low.
USB over-current sense, USB ports 6 and 7. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low.

PU/PD Comment
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
Do not pull this line high on the carrier board.

I
PU 10k Do not pull this line high on the carrier board.
3.3VSB 3.3VSB
I
PU 10k Do not pull this line high on the carrier board.
3.3VSB 3.3VSB
I
PU 10k Do not pull this line high on the carrier board.
3.3VSB 3.3VSB

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Table 11

CRT Signal Descriptions

Signal

Pin # Description

I/O

PU/PD

VGA_RED
VGA_GRN
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT

B89
B91
B92
B93
B94
B95
B96

O Analog
O Analog
O Analog
O 3.3V
O 3.3V
I/O OD 5V
I/O OD 5V

PD 150R
PD 150R
PD 150R

Table 12

Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
Horizontal sync output to VGA monitor
Vertical sync output to VGA monitor
DDC clock line (I²C port dedicated to identify VGA monitor capabilities)
DDC data line.

Comment

Optional on rev. C.x and later
Optional on rev. C.x and later
Optional on rev. C.x and later
Optional on rev. C.x and later
Optional on rev. C.x and later
PU 1k2 3.3V Optional on rev. C.x and later
PU 1k2 3.3V Optional on rev. C.x and later

LVDS Signal Descriptions

Signal

Pin #

Description

I/O

LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_A3+
LVDS_A3LVDS_A_CK+
LVDS_A_CKLVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_B_CK+
LVDS_B_CKLVDS_VDD_EN
LVDS_BKLT_EN
LVDS_BKLT_CTRL
LVDS_I2C_CK
LVDS_I2C_DAT

A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
A77
B79
B83
A83
A84

LVDS Channel A differential pairs

O LVDS

LVDS Channel A differential clock

O LVDS

LVDS Channel B differential pairs

O LVDS

LVDS Channel B differential clock

O LVDS

LVDS panel power enable
LVDS panel backlight enable
LVDS panel backlight brightness control
DDC lines used for flat panel detection and control.
DDC lines used for flat panel detection and control.

O 3.3V
O 3.3V
O 3.3V
O 3.3V
I/O 3.3V

PU/PD

Comment

PD 10k
PD 10k
PU 2k2 3.3V
PU 2k2 3.3V

.

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Table 13

Embedded DisplayPort Signal Descriptions

Signal

Pin # Description

I/O

eDP_TX3+
eDP_TX3eDP_TX2+
eDP_TX2eDP_TX1+
eDP_TX1eDP_TX0+
eDP_TX0eDP_VDD_EN
eDP_BKLT_EN
eDP_BKLT_CTRL
eDP_AUX+

A81
A82
A71
A72
A73
A74
A75
A76
A77
B79
B83
A83

eDP differential pairs.

AC coupled off
module.

eDP power enable.
eDP backlight enable.
eDP backlight brightness control.
eDP AUX+.

eDP_AUX-

A84

eDP AUX-.

eDP_HPD

A87

Detection of Hot Plug / Unplug and notification of the link layer.

O 3.3V
O 3.3V
O 3.3V
AC coupled off
module.
AC coupled off
module.
I 3.3V

Table 14

PU/PD

Comment
eDP_TX2 and eDP_TX3 pairs are not supported on
conga-TC87.

PD 10k
PD 10k

SPI BIOS Flash Interface Signal Descriptions

Signal

Pin # Description

I/O

SPI_CS#

B97

Chip select for Carrier Board SPI BIOS Flash.

O 3.3VSB

SPI_MISO
SPI_MOSI
SPI_CLK
SPI_POWER

A92
A95
A94
A91

I 3.3VSB
O 3.3VSB
O 3.3VSB
+ 3.3VSB

BIOS_DIS0# A34

Data in to module from carrier board SPI BIOS flash.
Data out from module to carrier board SPI BIOS flash.
Clock from module to carrier board SPI BIOS flash.
Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to power
SPI BIOS flash on the carrier only.
Selection strap to determine the BIOS boot device.

I 3.3VSB

BIOS_DIS1# B88

Selection strap to determine the BIOS boot device.

I 3.3VSB

PU/PD

Comment
Carrier shall pull to SPI_POWER when
external SPI provided but not used.

PU 10K
3.3VSB
PU 10K
3.3VSB

Carrier shall be left as no-connect.
Carrier shall be left as no-connect

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Table 15

Miscellaneous Signal Descriptions

Signal

Pin # Description

I/O

PU/PD

I2C_CK
I2C_DAT
SPKR

B33
B34
B32

General purpose I²C port clock output/input
General purpose I²C port data I/O line
Output for audio enunciator, the “speaker” in PC-AT systems

I/O 3.3V
I/O 3.3V
O 3.3V

PU 2K2 3.3VSB
PU 2K2 3.3VSB

WDT
FAN_PWNOUT

B27
B101
B102

O 3.3V
O OD
3.3V
I OD

PD 10K
PU 10K 3.3V

FAN_TACHIN

Output indicating that a watchdog time-out event has occurred.
Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control
the fan’s RPM.
Fan tachometer input.

TPM_PP

A96

Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip
has an internal pull‑down. This signal is used to indicate Physical Presence to the
TPM.

I 3.3V

Comment

SPEAKER is a boot strap signal
(see note below)

PU 10K 3.3V

Requires a fan with a two pulse
output.
Trusted Platform Module chip is
optional.

Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 8.5 of this user’s guide.

Table 16

General Purpose I/O Signal Descriptions

Signal

Pin # Description

I/O

GPO0

A93

O 3.3V

SDIO interface is not supported on the conga-TC87

GPO1

B54

O 3.3V

SDIO interface is not supported on the conga-TC87

GPO2

B57

O 3.3V

SDIO interface is not supported on the conga-TC87

GPO3

B63

O 3.3V

SDIO interface is not supported on the conga-TC87

GPI0

A54

GPI1

A63

GPI2

A67

GPI3

A85

General purpose output pins.
Shared with SD_CLK. Output from COM Express, input to SD
General purpose output pins.
Shared with SD_CMD. Output from COM Express, input to SD
General purpose output pins.
Shared with SD_WP. Output from COM Express, input to SD
General purpose output pins.
Shared with SD_CD. Output from COM Express, input to SD
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA0. Bidirectional signal
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA1. Bidirectional signal
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA2. Bidirectional signal
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA3. Bidirectional signal.

PU/PD

Comment

I 3.3V

PU 10K 3.3V

SDIO interface is not supported on the conga-TC87

I 3.3V

PU 10K 3.3V

SDIO interface is not supported on the conga-TC87

I 3.3V

PU 10K 3.3V

SDIO interface is not supported on the conga-TC87

I 3.3V

PU 10K 3.3V

SDIO interface is not supported on the conga-TC87

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Table 17

Power and System Management Signal Descriptions

Signal

Pin # Description

I/O

PU/PD

PWRBTN#
SYS_RESET#

B12
B49

I 3.3VSB
I 3.3VSB

PU 10k 3.3VSB
PU 10k 3.3VSB

CB_RESET#

B50

O 3.3V

PD 100k

PWR_OK

B24

SUS_STAT#
SUS_S3#

B18
A15

SUS_S4#
SUS_S5#
WAKE0#
WAKE1#

A18
A24
B66
B67

BATLOW#

A27

THRM#
THERMTRIP#
SMB_CK
SMB_DAT#

B35
A35
B13
B14

SMB_ALERT#

B15

LID#
SLEEP

A103
B103

Table 18

Power button to bring system out of S5 (soft off), active on rising edge.
Reset button input. Active low input. Edge triggered.
System will not be held in hardware reset while this input is kept low.
Reset output from module to Carrier Board. Active low. Issued by module chipset and may result
from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below
the minimum specification, a watchdog timeout, or may be initiated by the module software.
Power OK from main power supply. A high value indicates that the power is good.
Indicates imminent suspend operation; used to notify LPC devices.
Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3#
on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on
a typical ATX power supply.
Indicates system is in Suspend to Disk state. Active low output.
Indicates system is in Soft Off state.
PCI Express wake up signal.
General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or
mouse activity.
Battery low input. This signal may be driven low by external circuitry to signal that the system
battery is low, or may be used to signal some other external power-management event.
Input from off-module temp sensor indicating an over-temp situation.
Active low output indicating that the CPU has entered thermal shutdown.
System Management Bus bidirectional clock line.
System Management Bus bidirectional data line.

Comment

I 3.3V

Set by resistor divider
to accept 3.3V.

O 3.3VSB
O 3.3VSB

PU 10k 3.3VSB

O 3.3VSB
O 3.3VSB
I 3.3VSB
I 3.3VSB

PU 1k 3.3VSB
PU 10k 3.3VSB

I 3.3VSB

PU 10k 3.3VSB

I 3.3V
O 3.3V
I/O 3.3VSB
I/O OD
3.3VSB
I 3.3VSB

PU 10k 3.3V
PU 10k 3.3V
PU 2k2 3.3VSB
PU 2k2 3.3VSB

System Management Bus Alert – active low input can be used to generate an SMI# (System
Management Interrupt) or to wake the system.
Lid button. Used by the ACPI operating system for a LID switch.
I OD 3.3V
Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake it I OD 3.3V
up again.

Not supported

PU 10k 3.3VSB
PU 10k 3.3VSB
PU 10k 3.3VSB

General Purpose Serial Interface Signal Descriptions

Signal

Pin #

Description

I/O

PU/PD

SER0_TX
SER1_TX
SER0_RX
SER1_RX

A98
A101
A99
A102

General purpose serial port transmitter
General purpose serial port transmitter
General purpose serial port receiver
General purpose serial port receiver

O 3.3V
O 3.3V
I 3.3V
I 3.3V

PU 50k 3.3V
PU 50k 3.3V

Copyright © 2013 congatec AG 							TU87m01 							

Comment

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Table 19

Power and GND Signal Descriptions

Signal

Pin #

Description

I/O

VCC_12V

A104-A109
B104-B109
B84-B87

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s)
shall be used.
Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY
pins on the connector(s) shall be used. Only used for standby and suspend functions.
May be left unconnected if these functions are not used in the system design.
Real-time clock circuit-power input. Nominally +3.0V.
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier Board GND plane.

P

VCC_5V_SBY

VCC_RTC
GND

A47
A1, A11, A21, A31, A41,
A51, A57, A60, A66,
A70, A80, A90, A100,
A110, B1, B11, B21,
B31, B41, B51, B60,
B70, B80, B90, B100,
B110

PU/PD

Comment

P

P
P

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8.2

A-B Connector Pinout
Table 20

Connector A-B Pinout

Pin

Row A

Pin

Row B

Pin

Row A

Pin

Row B

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37

GND (FIXED)
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND (FIXED)
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF (*)
SUS_S3#
SATA0_TX+
SATA0_TXSUS_S4#
SATA0_RX+
SATA0_RXGND (FIXED)
SATA2_TX+
SATA2_TXSUS_S5#
SATA2_RX+
SATA2_RXBATLOW#
(S)ATA_ACT#
AC/HDA_SYNC
AC/HDA_RST#
GND (FIXED)
AC/HDA_BITCLK
AC/HDA_SDOUT
BIOS_DIS0#
THRMTRIP#
USB6USB6+

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37

GND (FIXED)
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND (FIXED)
PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TXSUS_STAT#
SATA1_RX+
SATA1_RXGND (FIXED)
SATA3_TX+
SATA3_TXPWR_OK
SATA3_RX+
SATA3_RXWDT
AC/HDA_SDIN2
AC/HDA_SDIN1
AC/HDA_SDIN0
GND (FIXED)
SPKR
I2C_CK
I2C_DAT
THRM#
USB7USB7+

A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92

PCIE_TX4- (*)
GND
PCIE_TX3+
PCIE_TX3GND (FIXED)
PCIE_TX2+
PCIE_TX2GPI1
PCIE_TX1+
PCIE_TX1GND
GPI2
PCIE_TX0+
PCIE_TX0GND (FIXED)
eDP_TX2+/LVDS_A0+
eDP_TX2-/LVDS_A0eDP_TX1+/LVDS_A1+
eDP_TX1-/LVDS_A1eDP_TX0+/LVDS_A2+
eDP_TX0-/LVDS_A2eDP/LVDS_VDD_EN
LVDS_A3+
LVDS_A3GND (FIXED)
eDP_TX3+/LVDS_A_CK+
eDP_TX3-/LVDS_A_CKeDP_AUX+/LVDS_I2C_CK
eDP_AUX-/LVDS_I2C_DAT
GPI3
RSVD
eDP_HPD
PCIE0_CK_REF+
PCIE0_CK_REFGND (FIXED)
SPI_POWER
SPI_MISO

B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92

PCIE_RX4- (*)
GPO2
PCIE_RX3+
PCIE_RX3GND (FIXED)
PCIE_RX2+
PCIE_RX2GPO3
PCIE_RX1+
PCIE_RX1WAKE0#
WAKE1#
PCIE_RX0+
PCIE_RX0GND (FIXED)
LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3eDP/LVDS_BKLT_EN
GND (FIXED)
LVDS_B_CK+
LVDS_B_CKeDP/LVDS_BKLT_CTRL
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
BIOS_DIS1#
VGA_RED (*)
GND (FIXED)
VGA_GRN (*)
VGA_BLU (*)

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Pin

Row A

Pin

Row B

Pin

Row A

Pin

Row B

A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55

USB_6_7_OC#
USB4USB4+
GND (FIXED)
USB2USB2+
USB_2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
GND (FIXED)
PCIE_TX5+ (*)
PCIE_TX5- (*)
GPI0
PCIE_TX4+ (*)

B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55

USB_4_5_OC#
USB5USB5+
GND (FIXED)
USB3USB3+
USB_0_1_OC#
USB1USB1+
EXCD1_PERST#
EXCD1_CPPE#
SYS_RESET#
CB_RESET#
GND (FIXED)
PCIE_RX5+ (*)
PCIE_RX5- (*)
GPO1
PCIE_RX4+ (*)

A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110

GPO0
SPI_CLK
SPI_MOSI
TPM_PP
TYPE10#
SER0_TX
SER0_RX
GND (FIXED)
SER1_TX
SER1_RX
LID#
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)

B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110

VGA_HSYNC (*)
VGA_VSYNC (*)
VGA_I2C_CK (*)
VGA_I2C_DAT (*)
SPI_CS#
RSVD
RSVD
GND (FIXED)
FAN_PWMOUT
FAN_TACHIN
SLEEP#
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)

Note
The signals marked with asterisk symbol (*) are not supported on the conga TC87.

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8.3

C-D Connector Signal Descriptions
Table 21

PCI Express Signal Descriptions (general purpose)

Signal

Pin # Description

I/O

PCIE_RX6+
PCIE_RX6PCIE_TX6+
PCIE_TX6PCIE_RX7+
PCIE_RX7PCIE_TX7+
PCIE_TX7-

C19
C20
D19
D20
C22
C23
D22
D23

PCI Express channel 6, Receive Input differential pair.

I PCIE

Not supported

PCI Express channel 6, Transmit Output differential pair.

O PCIE

Not supported

PCI Express channel 7, Receive Input differential pair.

I PCIE

Not supported

PCI Express channel 7, Transmit Output differential pair.

O PCIE

Not supported

Table 22

PU/PD

Comment

USB 3.0 Signal Descriptions

Signal

Pin # Description

I/O

USB_SSRX0+
USB_SSRX0USB_SSTX0+
USB_SSTX0USB_SSRX1+
USB_SSRX1USB_SSTX1+
USB_SSTX1USB_SSRX2+
USB_SSRX2USB_SSTX2+
USB_SSTX2USB_SSRX3+
USB_SSRX3USB_SSTX3+
USB_SSTX3-

C4
C3
D4
D3
C7
C6
D7
D6
C10
C9
D10
D9
C13
C12
D13
D12

I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O

Additional receive signal differential pairs for the Superspeed USB data path
Additional transmit signal differential pairs for the Superspeed USB data path
Additional receive signal differential pairs for the Superspeed USB data path
Additional transmit signal differential pairs for the Superspeed USB data path
Additional receive signal differential pairs for the Superspeed USB data path
Additional transmit signal differential pairs for the Superspeed USB data path
Additional receive signal differential pairs for the Superspeed USB data path
Additional transmit signal differential pairs for the Superspeed USB data path

PU/PD Comment

Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.

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Table 23

PCI Express Signal Descriptions (x16 Graphics)

Signal

Pin # Description

PEG_RX0+
PEG_RX0PEG_RX1+
PEG_RX1PEG_RX2+
PEG_RX2PEG_RX3+
PEG_RX3PEG_RX4+
PEG_RX4PEG_RX5+
PEG_RX5PEG_RX6+
PEG_RX6PEG_RX7+
PEG_RX7PEG_RX8+
PEG_RX8PEG_RX9+
PEG_RX9PEG_RX10+
PEG_RX10PEG_RX11+
PEG_RX11PEG_RX12+
PEG_RX12PEG_RX13+
PEG_RX13PEG_RX14+
PEG_RX14PEG_RX15+
PEG_RX15-

C52
C53
C55
C56
C58
C59
C61
C62
C65
C66
C68
C69
C71
C72
C74
C75
C78
C79
C81
C82
C85
C86
C88
C89
C91
C92
C94
C95
C98
C99
C101
C102

I/O

I PCIE
PCI Express Graphics Receive Input differential pairs.
Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known
as PCIE_RX[16-31] + and -.

PU/PD

Comment
Not supported.

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Signal

Pin # Description

I/O

PEG_TX0+
PEG_TX0PEG_TX1+
PEG_TX1PEG_TX2+
PEG_TX2PEG_TX3+
PEG_TX3PEG_TX4+
PEG_TX4PEG_TX5+
PEG_TX5PEG_TX6+
PEG_TX6PEG_TX7+
PEG_TX7PEG_TX8+
PEG_TX8PEG_TX9+
PEG_TX9PEG_TX10+
PEG_TX10PEG_TX11+
PEG_TX11PEG_TX12+
PEG_TX12PEG_TX13+
PEG_TX13PEG_TX14+
PEG_TX14PEG_TX15+
PEG_TX15PEG_LANE_RV#

D52
D53
D55
D56
D58
D59
D61
D62
D65
D66
D68
D69
D71
D72
D74
D75
D78
D79
D81
D82
D85
D86
D88
D89
D91
D92
D94
D95
D98
D99
D101
D102
D54

O PCIE

PCI Express Graphics Transmit Output differential pairs.
Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31
known as PCIE_TX[16-31] + and -.

PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane I
order.

PU/PD

Comment
Not supported.

PU 10k 3.3V Not supported.

Note
The PCI Express Graphics interface is not supported on the conga-TC87.

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Table 24

DDI Signal Description

Signal

Pin # Description

I/O

DDI1_PAIR0+
DDI1_PAIR0DDI1_PAIR1+
DDI1_PAIR1DDI1_PAIR2+
DDI1_PAIR2DDI1_PAIR3+
DDI1_PAIR3DDI1_PAIR4+
DDI1_PAIR4DDI1_PAIR5+
DDI1_PAIR5DDI1_PAIR6+
DDI1_PAIR6DDI1_HPD
DDI1_CTRLCLK_AUX+

D26
D27
D29
D30
D32
D33
D36
D37
C25
C26
C29
C30
C15
C16
C24
D15

O PCIE

DDI1_CTRLDATA_AUX- D16

DDI1_DDC_AUX_SEL

D34

DDI2_PAIR0+
DDI2_PAIR0DDI2_PAIR1+
DDI2_PAIR1DDI2_PAIR2+
DDI2_PAIR2DDI2_PAIR3+
DDI2_PAIR3DDI2_HPD
DDI2_CTRLCLK_AUX+

D39
D40
D42
D43
D46
D47
D49
D50
D44
C32

DDI2_CTRLDATA_AUX- C33

Multiplexed with DP1_LANE0+ and TMDS1_DATA2+.
Multiplexed with DP1_LANE0- and TMDS1_DATA2-.
Multiplexed with DP1_LANE1+ and TMDS1_DATA1+.
Multiplexed with DP1_LANE1- and TMDS1_DATA1-.
Multiplexed with DP1_LANE2+ and TMDS1_DATA0+.
Multiplexed with DP1_LANE2- and TMDS1_DATA0-.
Multiplexed with DP1_LANE3+ and TMDS1_CLK+.
Multiplexed with DP1_LANE3- and TMDS1_CLK-.
Multiplexed with SDVO1_INT+.
Multiplexed with SDVO1_INT-.
Multiplexed with SDVO1_TVCLKIN+.
Multiplexed with SDVO1_TVCLKIN-.
Multiplexed with SDVO1_FLDSTALL+.
Multiplexed with SDVO1_FLDSTALL-.
Multiplexed with DP1_HPD and HDMI1_HPD.
Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK.
DP AUX+ function if DDI1_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high
Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.
DP AUX- function if DDI1_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high
Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-.
This pin shall have a IM pull-down to logic ground on the module. If this input
is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the
AUX pair contains the CTRLCLK and CTRLDATA signals.
Multiplexed with DP2_LANE0+ and TMDS2_DATA2+.
Multiplexed with DP2_LANE0- and TMDS2_DATA2-.
Multiplexed with DP2_LANE1+ and TMDS2_DATA1+.
Multiplexed with DP2_LANE1- and TMDS2_DATA1-.
Multiplexed with DP2_LANE2+ and TMDS2_DATA0+.
Multiplexed with DP2_LANE2- and TMDS2_DATA0-.
Multiplexed with DP2_LANE3+ and TMDS2_CLK+.
Multiplexed with DP2_LANE3- and TMDS2_CLK-.
Multiplexed with DP2_HPD and HDMI2_HPD.
Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK.
DP AUX+ function if DDI2_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high
Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.
DP AUX- function if DDI2_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high.

PU/PD Comment

O PCIE
O PCIE
O PCIE
Not supported
Not supported
Not supported
I 3.3V

PD 1M
PD100k

I/O PCIE
I/O OD 3.3V
PU 100k DDI1_CTRLDATA_AUX- is a boot
I/O PCIE
3.3V
strap signal (see not below).
I/O OD 3.3V
DDI enable strap already populated.
I 3.3V
PD 1M

O PCIE
O PCIE
O PCIE
O PCIE
I 3.3V

PD 1M
PD 100k

I/O PCIE
I/O OD 3.3V
PU 100k DDI2_CTRLCLK_AUX- is a boot strap
I/O PCIE
3.3V
signal (see note below).
I/O OD 3.3V
DDI enable strap already populated.

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Signal

Pin # Description

I/O

DDI2_DDC_AUX_SEL

C34

I 3.3V

DDI3_PAIR0+
DDI3_PAIR0DDI3_PAIR1+
DDI3_PAIR1DDI3_PAIR2+
DDI3_PAIR2DDI3_PAIR3+
DDI3_PAIR3DDI3_HPD
DDI3_CTRLCLK_AUX+

C39
C40
C42
C43
C46
C47
C49
C50
C44
C36

DDI3_CTRLDATA_AUX- C37

DDI3_DDC_AUX_SEL

C38

Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-.
This pin shall have a IM pull-down to logic ground on the module. If this input
is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the
AUX pair contains the CTRLCLK and CTRLDATA signals
Multiplexed with DP3_LANE0+ and TMDS3_DATA2+.
Multiplexed with DP3_LANE0- and TMDS3_DATA2-.
Multiplexed with DP3_LANE1+ and TMDS3_DATA1+.
Multiplexed with DP3_LANE1- and TMDS3_DATA1-.
Multiplexed with DP3_LANE2+ and TMDS3_DATA0+.
Multiplexed with DP3_LANE2- and TMDS3_DATA0-.
Multiplexed with DP3_LANE3+ and TMDS3_CLK+.
Multiplexed with DP3_LANE3- and TMDS3_CLK-.
Multiplexed with DP3_HPD and HDMI3_HPD.
Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK.
DP AUX+ function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high
Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.
DP AUX- function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.
Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-.
This pin shall have a IM pull-down to logic ground on the module. If this input
is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the
AUX pair contains the CTRLCLK and CTRLDATA signals

PU/PD Comment

O PCIE

Not supported

O PCIE

Not supported

O PCIE

Not supported

O PCIE

Not supported

I 3.3V

Not supported
Not supported

I/O PCIE
I/O OD 3.3V
Not supported
I/O PCIE
I/O OD 3.3V
I 3.3V

Not supported

Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 8.5 of this user’s guide.
The Digital Display Interface (DDI) signals are multiplexed with HDMI and DisplayPort (DP). The signals for these interfaces are routed to the
DDI interface of the COM Express connector. Refer to the HDMI and DisplayPort signal description tables in this section for information about
the signals routed to the DDI interface of the COM Express connector.

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Table 25

HDMI Signal Descriptions

Signal

Pin # Description

I/O

TMDS1_CLK +
TMDS1_CLK TMDS1_DATA0+
TMDS1_DATA0TMDS1_DATA1+
TMDS1_DATA1TMDS1_DATA2+
TMDS1_DATA2HDMI1_HPD

D36
D37
D32
D33
D29
D30
D26
D27
C24

O PCIE

HDMI1_CTRLCLK

D15

HDMI1_CTRLDATA

D16

TMDS2_CLK +
TMDS2_CLK TMDS2_DATA0+
TMDS2_DATA0TMDS2_DATA1+
TMDS2_DATA1TMDS2_DATA2+
TMDS2_DATA2HDMI2_HPD

D49
D50
D46
D47
D42
D43
D39
D40
D44

HDMI2_CTRLCLK

C32

HDM12_CTRLDATA

C33

TMDS3_CLK +
TMDS3_CLK TMDS3_DATA0+
TMDS3_DATA0TMDS3_DATA1+
TMDS3_DATA1TMDS3_DATA2+
TMDS3_DATA2HDMI3_HPD

C49
C50
C46
C47
C42
C43
C39
C40
C44

HDMI3_CTRLCLK

C36

HDMI/DVI TMDS Clock output differential pair.
Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-..
HDMI/DVI TMDS differential pair.
Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
HDMI/DVI Hot-plug detect.
Multiplexed with DDI1_HPD.
HDMI/DVI I2C Control Clock
Multiplexed with DDI1_CTRLCLK_AUX+
HDMI/DVI I2C Control Data
Multiplexed with DDI1_CTRLDATA_AUXHDMI/DVI TMDS Clock output differential pair..
Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-..
HDMI/DVI Hot-plug detect.
Multiplexed with DDI2_HPD
HDMI/DVI I2C Control Clock
Multiplexed with DDI2_CTRLCLK_AUX+
HDMI/DVI I2C Control Data
Multiplexed with DDI2_CTRLDATA_AUXHDMI/DVI TMDS Clock output differential pair..
Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.
HDMI/DVI TMDS differential pair.
Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-..
HDMI/DVI TMDS differential pair.
Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.
HDMI/DVI Hot-plug detect.
Multiplexed with DDI3_HPD.
HDMI/DVI I2C Control Clock
Multiplexed with DDI3_CTRLCLK_AUX+

PU/PD

Comment

O PCIE
O PCIE
O PCIE
I PCIE

PD 1M

I/O OD 3.3V PD 100k
I/O OD 3.3V PU 100k HDMI1_CTRLDATA is a boot strap signal (see note below).
3.3V
HDMI enable strap already populated
O PCIE
O PCIE
O PCIE
O PCIE
I PCIE

PD 1M

I/O OD 3.3V PD 100k
I/O OD 3.3V PU 100k HDMI2_CTRLDATA is a boot strap signal (see note below).
3.3V
HDMI enable strap is already populated.
O PCIE
Not supported
O PCIE

Not supported

O PCIE

Not supported

O PCIE

Not supported

I PCIE

Not supported

I/O OD 3.3V

Not supported

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Signal

Pin # Description

HDMI3_CTRLDATA

C37

HDMI/DVI I2C Control Data
Multiplexed with DDI3_CTRLDATA_AUX-

I/O

PU/PD

I/O OD 3.3V

Comment
Not supported

Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 8.5 of this user’s guide.

Table 26

DisplayPort (DP) Signal Descriptions

Signal

Pin # Description

I/O

DP1_LANE3+
DP1_LANE3-

D36
D37

O PCIE

DP1_LANE2+
DP1_LANE2-

D32
D33

DP1_LANE1+
DP1_LANE1-

D29
D30

DP1_LANE0+
DP1_LANE0-

D26
D27

DP1_HPD

C24

DP1_AUX+

D15

DP1_AUX-

D16

DP2_LANE3+
DP2_LANE3-

D49
D50

DP2_LANE2+
DP2_LANE2-

D46
D47

DP2_LANE1+
DP2_LANE1-

D42
D43

DP2_LANE0+
DP2_LANE0-

D39
D40

Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI1_HPD.
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access.
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0-

PU/PD

Comment

O PCIE

O PCIE

O PCIE

I 3.3V

PD 1M

I/O PCIE PD 100k
I/O PCIE PU 100k
3.3V
O PCIE

DP1_AUX- is a boot strap signal (see note below).
DP enable strap is already populated.

O PCIE

O PCIE

O PCIE

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Signal

Pin # Description

DP2_HPD

D44

DP2_AUX+

C32

DP2_AUX-

C33

DP3_LANE3+
DP3_LANE3-

C49
C50

DP3_LANE2+
DP3_LANE2-

C46
C47

DP3_LANE1+
DP3_LANE1-

C42
C43

DP3_LANE0+
DP3_LANE0-

C39
C40

DP3_HPD

C44

DP3_AUX+

C36

DP3_AUX-

C37

Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI2_HPD.
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access.
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-.
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.
Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI3_HPD.
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access.
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access.

I/O

PU/PD

I 3.3V

PD 1M

Comment

I/O PCIE PD 100k
I/O PCIE PU 100k
3.3V
O PCIE

DP2_AUX- is a boot strap signal (see note below).
DP enable strap already populated.
Not supported

O PCIE

Not supported

O PCIE

Not supported

O PCIE

Not supported

I 3.3V

Not supported

I/O PCIE

Not supported

I/O PCIE

Not supported

Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 8.5 of this user’s guide.

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Table 27

Module Type Definition Signal Description

Signal

Pin #

Description

I/O

Comment

TYPE0#
TYPE1#
TYPE2#

C54
C57
D57

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on
the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X).
TYPE2#
TYPE1#
TYPE0#

PDS

TYPE[0:2]# signals are
available on all modules
following the Type 2-6
Pinout standard.
The conga-TC87 is based
on the COM Express Type
6 pinout therefore the pins
0 and 1 are not connected
and pin 2 is connected to
GND.

X
NC
NC
NC
NC
GND

X
NC
NC
GND
GND
NC

X
NC
GND
NC
GND
NC

Pinout Type 1
Pinout Type 2
Pinout Type 3 (no IDE)
Pinout Type 4 (no PCI)
Pinout Type 5 (no IDE, no PCI)
Pinout Type 6 (no IDE, no PCI)

The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off
(e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The
Carrier Board logic may also implement a fault indicator such as an LED.
TYPE10# A97

Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev. 1.0/2.0 PDS
module is installed.

Not connected to indicate
“Pinout R2.0”.

TYPE10#
NC
PD
12V

Pinout R2.0
Pinout Type 10 pull down to ground with 4.7k resistor
Pinout R1.0
This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin
is defined as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0
module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor.

Table 28

Power and GND Signal Descriptions

Signal

Pin #

VCC_12V

C104-C109
Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used. P
D104-D109
P
C1, C2, C5, C8, C11, Ground - DC power and signal and AC signal return path.
C14, C21, C31, C41, All available GND connector pins shall be used and tied to carrier board GND plane.
C51, C60, C70,C73,
C76, C80, C84, C87,
C90, C93, C96, C100,
C103, C110, D1, D2,
D5, D8, D11, D14,
D21, D31, D41, D51,
D60, D67, D70, D73,
D76, D80, D84, D87,
D90, D93, D96, D100,
D103, D110

GND

Description

I/O

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PU/PD Comment

64/72

8.4

C-D Connector Pinout
Table 29

Connector C-D Pinout

Pin

Row C

Pin

Row D

Pin

Row C

Pin

Row D

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37

GND (FIXED)
GND
USB_SSRX0USB_SSRX0+
GND
USB_SSRX1USB_SSRX1+
GND
USB_SSRX2- (*)
USB_SSRX2+ (*)
GND (FIXED)
USB_SSRX3- (*)
USB_SSRX3+ (*)
GND
DDI1_PAIR6+ (*)
DDI1_PAIR6- (*)
RSVD
RSVD
PCIE_RX6+ (*)
PCIE_RX6- (*)
GND (FIXED)
PCIE_RX7+ (*)
PCIE_RX7- (*)
DDI1_HPD
DDI1_PAIR4+ (*)
DDI1_PAIR4- (*)
RSVD
RSVD
DDI1_PAIR5+ (*)
DDI1_PAIR5- (*)
GND (FIXED)
DDI2_CTRLCLK_AUX+
DDI2_CTRLDATA_AUXDDI2_DDC_AUX_SEL
RSVD
DDI3_CTRLCLK_AUX+ (*)
DDI3_CTRLDATA_AUX- (*)

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37

GND (FIXED)
GND
USB_SSTX0USB_SSTX0+
GND
USB_SSTX1USB_SSTX1+
GND
USB_SSTX2- (*)
USB_SSTX2+ (*)
GND (FIXED)
USB_SSTX3- (*)
USB_SSTX3+ (*)
GND
DDI1_CTRLCLK_AUX+
DDI1_CTRLDATA_AUXRSVD
RSVD
PCIE_TX6+ (*)
PCIE_TX6- (*)
GND (FIXED)
PCIE_TX7+ (*)
PCIE_TX7- (*)
RSVD
RSVD
DDI1_PAIR0+
DDI1_PAIR0RSVD
DDI1_PAIR1+
DDI1_PAIR1GND (FIXED)
DDI1_PAIR2+
DDI1_PAIR2DDI1_DDC_AUX_SEL
RSVD
DDI1_PAIR3+
DDI1_PAIR3-

C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92

PEG_RX1- (*)
TYPE1#
PEG_RX2+ (*)
PEG_RX2- (*)
GND (FIXED)
PEG_RX3+ (*)
PEG_RX3- (*)
RSVD
RSVD
PEG_RX4+ (*)
PEG_RX4- (*)
RSVD
PEG_RX5+ (*)
PEG_RX5- (*)
GND (FIXED)
PEG_RX6+ (*)
PEG_RX6- (*)
GND
PEG_RX7+ (*)
PEG_RX7- (*)
GND
RSVD
PEG_RX8+ (*)
PEG_RX8- (*)
GND (FIXED)
PEG_RX9+ (*)
PEG_RX9- (*)
RSVD
GND
PEG_RX10+ (*)
PEG_RX10- (*)
GND
PEG_RX11+ (*)
PEG_RX11- (*)
GND (FIXED)
PEG_RX12+ (*)
PEG_RX12- (*)

D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92

PEG_TX1- (*)
TYPE2#
PEG_TX2+ (*)
PEG_TX2- (*)
GND (FIXED)
PEG_TX3+ (*)
PEG_TX3- (*)
DDPC_CTRLCLK
DDPC_CTRLDATA
PEG_TX4+ (*)
PEG_TX4- (*)
GND
PEG_TX5+ (*)
PEG_TX5- (*)
GND (FIXED)
PEG_TX6+ (*)
PEG_TX6- (*)
GND
PEG_TX7+ (*)
PEG_TX7- (*)
GND
RSVD
PEG_TX8+ (*)
PEG_TX8- (*)
GND (FIXED)
PEG_TX9+ (*)
PEG_TX9- (*)
RSVD
GND
PEG_TX10+ (*)
PEG_TX10- (*)
GND
PEG_TX11+ (*)
PEG_TX11- (*)
GND (FIXED)
PEG_TX12+ (*)
PEG_TX12- (*)

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Pin

Row C

Pin

Row D

Pin

Row C

Pin

Row D

C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55

DDI3_DDC_AUX_SEL (*)
DDI3_PAIR0+ (*)
DDI3_PAIR0- (*)
GND (FIXED)
DDI3_PAIR1+ (*)
DDI3_PAIR1- (*)
DDI3_HPD
RSVD
DDI3_PAIR2+ (*)
DDI3_PAIR2- (*)
RSVD
DDI3_PAIR3+ (*)
DDI3_PAIR3- (*)
GND (FIXED)
PEG_RX0+ (*)
PEG_RX0- (*)
TYPE0#
PEG_RX1+ (*)

D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55

RSVD
DDI2_PAIR0+
DDI2_PAIR0GND (FIXED)
DDI2_PAIR1+
DDI2_PAIR1DDI2_HPD
RSVD
DDI2_PAIR2+
DDI2_PAIR2RSVD
DDI2_PAIR3+
DDI2_PAIR3GND (FIXED)
PEG_TX0+ (*)
PEG_TX0- (*)
PEG_LANE_RV# (*)
PEG_TX1+ (*)

C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110

GND
PEG_RX13+ (*)
PEG_RX13- (*)
GND
RVSD
PEG_RX14+ (*)
PEG_RX14- (*)
GND (FIXED)
PEG_RX15+ (*)
PEG_RX15- (*)
GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)

D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110

GND
PEG_TX13+ (*)
PEG_TX13- (*)
GND
RSVD
PEG_TX14+ (*)
PEG_TX14- (*)
GND (FIXED)
PEG_TX15+ (*)
PEG_TX15- (*)
GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)

Note
The signals marked with an asterisk symbol (*) are not supported on the conga-TC87.

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8.5

Boot Strap Signals
Table 30

Boot Strap Signal Descriptions

Signal

Pin # Description of Boot Strap Signal

AC/HDA_SDOUT

A33

SPKR

B32

DDI1_CTRLDATA_AUX- D16
DP1_AUXHDMI_CTRLDATA
DDI2_CTRLDATA_AUX- C33
DP2_AUXHDM2_CTRLDATA

High Definition Audio Serial Data Out: This signal is the serial TDM data
output to the codec(s). This serial output is double-pumped for a bit rate of 48
Mb/s for High Definition Audio.
Output for audio enunciator, the “speaker” in PC-AT systems
Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.
DP AUX- function if DDI1_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high.
Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.
DP AUX- function if DDI2_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high.

I/O

PU/PD Comment

O 3.3VSB

PU 1K AC/HDA_SDOUT is a boot strap
3.3VSB signal (see caution statement below)

O 3.3V

SPKR is a boot strap signal (see
caution statement below)
PU100k DDI1_CTRLDATA_AUX- is a boot
3.3V
strap signal (see not below).

I/O PCIE
I/O OD 3.3V

PU100k DDI2_CTRLDATA_AUX- is a boot
I/O PCIE
3.3V
strap signal (see not below).
I/O OD 3.3V

Caution
The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are
inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors
that are located on the module. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals
listed in the above table. External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or
cause irreparable damage to the module.

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9

System Resources

9.1

I/O Address Assignment
The I/O address assignment of the conga-TC87 module is functionally identical with a standard PC/AT.

Note
The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not
consume I/O resources in that area.

9.1.1

LPC Bus
On the conga-TC87, the PCI Express Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to
the internal PCI Bus not the LPC Bus. Only specified I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS, the following
I/O address ranges are sent to the LPC Bus:
2Eh – 2Fh
4Eh – 4Fh
60h, 64h
A00h – BFFh
C00h – CFFh (always used internally)
Parts of these ranges are not available if a Super I/O is used on the carrier board. If a Super I/O is not implemented on the carrier board,
then these ranges are available for customer use. If you require additional LPC Bus resources other than those mentioned above, or more
information about this subject, contact congatec technical support for assistance.

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9.2

PCI Configuration Space Map
Table 31

PCI Configuration Space Map

Bus Number (hex) Device Number (hex) Function Number (hex) Description
00h
00h
00h
00h
00h( Note1)
00h( Note1)
00h( Note1)
00h( Note1)
00h
00h (Note2)
00h (Note2)
00h (Note2)
00h (Note2)
00h
00h
00h
00h
00h
01h (Note3)
02h (Note3)
03h (Note3)
04h (Note3)

00h
02h
03h
14h
16h
16h
16h
16h
19h
1Ch
1Ch
1Ch
1Ch
1Dh
1Fh
1Fh
1Fh
1Fh
00h
00h
00h
00h

00h
00h
00h
00h
00h
01h
02h
03h
00h
00h
01h
02h
03h
00h
00h
02h
03h
06h
00h
00h
00h
00h

Host Bridge
Graphics
Intel High Definition Audio controller
XHCI Host Controller
Management Engine (ME) Interface 1
Intel ME Interface 2
ME IDE Redirection (IDE-R) Interface
ME KT (Remote Keyboard and Text)
Onboard Gigabit LAN Controller
PCI Express Root Port 0
PCI Express Root Port 1
PCI Express Root Port 2
PCI Express Root Port 3
EHCI Host Controller
PCI to LPC Bridge
Serial ATA Controller
SMBus Host Controller
Thermal Subsystem
PCI Express Port 0
PCI Express Port 1
PCI Express Port 2
PCI Express Port 3

Note
1. In the standard configuration, the Intel Management Engine (ME) related devices are partly present or not present at all.
2. The PCI Express Ports are visible only if a device is attached behind them to the PCI Express Slot on the carrier board.
3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus
numbers will change based on actual hardware configuration.

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9.3

PCI Interrupt Routing Map
Table 32

PCI Interrupt Routing Map

PIRQ PCI BUS APIC
Graphic HDA
INT Line ¹ Mode IRQ

XHCI EHCI

A
B
C
D
E
F
G
H

x

INTA
INTB
INTC
INTD

16
17
18
19
20
21
22
23

x

x

SM Bus + LAN SATA
Thermal

PCI-EX
Root Port
0

PCI-EX
PCI-EX
PCI-EX
Root Port Root Port 2 Root
1
Port 3

x
x
x

x
x

x

PCI-EX
Port 0

PCI-EX
Port 1

PCI-EX
Port 2

PCI-EX
Port 3

x2
x3
x4
x5

x5
x2
x3
x4

x4
x5
x²
x³

x3
x4
x5
x2

x

x

Note

9.4

1

These interrupt lines are virtual (message based).

2

Interrupt used by single function PCI Express devices (INTA).

3

Interrupt used by multifunction PCI Express devices (INTB).

4

Interrupt used by multifunction PCI Express devices (INTC).

5

Interrupt used by multifunction PCI Express devices (INTD).

I²C Bus
There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

9.5

SM Bus
System Management (SM) bus signals are connected to the Intel® 8 Series PCH-LP and the SM bus is not intended to be used by off-board
non-system management devices. For more information about this subject, contact congatec technical support.

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10

BIOS Setup Description
TBD

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11

Industry Specifications
The list below provides links to industry specifications that apply to congatec AG modules.
Specification

Low Pin Count Interface Specification, Revision 1.0 (LPC)
Universal Serial Bus (USB) Specification, Revision 2.0
PCI Specification, Revision 2.3
Serial ATA Specification, Revision 3.0
PICMG® COM Express Module™ Base Specification
PCI Express Base Specification, Revision 2.0

Link
http://developer.intel.com/design/chipsets/industry/lpc.htm
http://www.usb.org/home
http://www.pcisig.com/specifications
http://www.serialata.org
http://www.picmg.org/
http://www.pcisig.com/specifications

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Subject                         : conga-TU87, Type 6, Intel 4th Generation i7 Core, Intel i5 Core, Intel i3 Core COM Express, Intel Celeron processor, Hasswell ULT, Ultra low TDP, Deep Sx, cTDP, Compact, SATA, Serial ATA, USB 3.0, PCI Express, PCI Express Gen 3.0, LPC, I²C, COM, Computer on Module, System on Module, Intel, Core, Celeron, AEM
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