Conga TU87 User's Guide User

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1 INTRODUCTION
2 Specifications
- 2.1 Feature List
- 2.2 Supported Operating Systems
- 2.3 Mechanical Dimensions
- 2.4 Supply Voltage Standard Power
  - 2.4.1 Electrical Characteristics
  - 2.4.2 Rise Time
- 2.5 Power Consumption
- 2.6 Supply Voltage Battery Power
  - 2.6.1 CMOS Battery Power Consumption
- 2.7 Environmental Specifications
3 Block Diagram
4 Heatspreader
- 4.1 Heatspreader Dimensions
5 Connector Subsystems Rows A, B, C, D
- 5.1 Primary Connector Rows A and B
- 5.2 Secondary Connector Rows C and D
6 Additional Features
- 6.1 congatec Board Controller (cBC)
- 6.2 Board Information
- 6.3 Watchdog
- 6.4 I2C Bus
- 6.5 Power Loss Control
- 6.6 Embedded BIOS
- 6.7 Security Features
- 6.8 Suspend to Ram
7 conga Tech Notes
- 7.1 Intel® PCH-LP Features
  - 7.1.1 Intel® Rapid Storage Technology
  - 7.1.2 Intel® Rapid Start Technology
- 7.2 Intel® Processor Features
- 7.3 ACPI Suspend Modes and Resume Events
- 7.4 Low Voltage Memory (DDR3L)
- 7.5 USB 2.0 EHCI Host Controller Support
8 Signal Descriptions and Pinout Tables
- 8.1 A-B Connector Signal Descriptions
- 8.2 A-B Connector Pinout
- 8.3 C-D Connector Signal Descriptions
- 8.4 C-D Connector Pinout
- 8.5 Boot Strap Signals
9 System Resources
- 9.1 I/O Address Assignment
  - 9.1.1 LPC Bus
- 9.2 PCI Configuration Space Map
- 9.3 PCI Interrupt Routing Map
- 9.4 I²C Bus
- 9.5 SM Bus
10 BIOS Setup Description
11 Industry Specifications
Table 1 Feature Summary
Table 2 Display Combination (U-processor line)
Table 3 Signal Tables Terminology Descriptions
Table 4 Intel® High Definition Audio Link Signals Descriptions
Table 5 Gigabit Ethernet Signal Descriptions
Table 6 Serial ATA Signal Descriptions
Table 7 PCI Express Signal Descriptions (general purpose)
Table 8 ExpressCard Support Pins Signal Descriptions
Table 9 LPC Signal Descriptions
Table 10 USB Signal Descriptions
Table 11 CRT Signal Descriptions
Table 12 LVDS Signal Descriptions
Table 13 Embedded DisplayPort Signal Descriptions
Table 14 SPI BIOS Flash Interface Signal Descriptions
Table 15 Miscellaneous Signal Descriptions
Table 16 General Purpose I/O Signal Descriptions
Table 17 Power and System Management Signal Descriptions
Table 18 General Purpose Serial Interface Signal Descriptions
Table 19 Power and GND Signal Descriptions
Table 20 Connector A-B Pinout
Table 21 PCI Express Signal Descriptions (general purpose)
Table 22 USB 3.0 Signal Descriptions
Table 23 PCI Express Signal Descriptions (x16 Graphics)
Table 24 DDI Signal Description
Table 25 HDMI Signal Descriptions
Table 26 DisplayPort (DP) Signal Descriptions
Table 27 Module Type Definition Signal Description
Table 28 Power and GND Signal Descriptions
Table 29 Connector C-D Pinout
Table 30 Boot Strap Signal Descriptions
Table 31 PCI Configuration Space Map
Table 32 PCI Interrupt Routing Map

COM Express™ conga-TC87

4th Generation Intel® Core™ i7, i5, i3 and Mobile Intel® Celeron Single Chip Ultra Low TDP Processors

User’s Guide

Revision 0.1 (Preliminary)

Revision History

Revision Date (yyyy.mm.dd) Author Changes

0.1 2013.11.14 AEM • Preliminary release

Preface

This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-TC87. It is

one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should

be used include the following:

COM Express™ Design Guide

COM Express™ Specication

The links to these documents can be found on the congatec AG website at www.congatec.com

Disclaimer

The information contained within this user’s guide, including but not limited to any product specication, is subject to change without notice.

congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims

any implied warranties of merchantability or tness for any particular purpose with regard to any of the foregoing. congatec AG assumes

no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for

discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or

exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information

contained herein or the use thereof.

Intended Audience

This user’s guide is intended for technically qualied personnel. It is not intended for general audiences.

Lead-Free Designs (RoHS)

All congatec AG designs are created from lead-free components and are completely RoHS compliant.

Electrostatic Sensitive Device

All congatec AG products are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a congatec AG product

except at an electrostatic-free workstation. Additionally, do not ship or store congatec AG products near strong electrostatic, electromagnetic,

magnetic, or radioactive elds unless the device is contained within its original manufacturer’s packaging. Be aware that failure to comply with

these guidelines will void the congatec AG Limited Warranty.

Symbols

The following symbols are used in this user’s guide:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note

Notes call attention to important information that should be observed.

Terminology

Term Description

GB Gigabyte (1,073,741,824 bytes)

GHz Gigahertz (one billion hertz)

kB Kilobyte (1024 bytes)

MB Megabyte (1,048,576 bytes)

Mbit Megabit (1,048,576 bits)

kHz Kilohertz (one thousand hertz)

MHz Megahertz (one million hertz)

TDP Thermal Design Power

PCIe PCI Express

SATA Serial ATA

PEG PCI Express Graphics

PCH Platform Controller Hub

eDP Embedded DisplayPort

T.O.M. Top of memory = max. DRAM installed

HDA High Denition Audio

N.C. Not connected

N.A. Not available

MCP MCP

TBD To be determined

Trademarks

Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property

of their respective trademark holders. These trademark holders are not afliated with congatec AG, our products, or our website.

Warranty

congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited

warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and

conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and

from time to time.

The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license

agreements, which are available at www.congatec.com and/or upon request.

Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the

products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or

due to non conformance to the agreed upon specications, will be repaired or exchanged, at congatec’s option and expense.

Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight

prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.

Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged

or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to

congatec’s direct customer only and is not assignable or transferable.

Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either

express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of

tness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.

congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be

liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive

remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the

product only.

Certication

congatec AG is certied to DIN EN ISO 9001 standard.

Technical Support

congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products

can be easily used and implemented. We request that you rst visit our website at www.congatec.com for the latest documentation, utilities and

drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support

department by email at support@congatec.com

Contents

1 INTRODUCTION .....................................................................10

2 Specications ...........................................................................12

2.1 Feature List .............................................................................. 12

2.2 Supported Operating Systems ................................................. 13

2.3 Mechanical Dimensions ...........................................................13

2.4 Supply Voltage Standard Power .............................................. 14

2.4.1 Electrical Characteristics ..........................................................14

2.4.2 Rise Time ................................................................................. 14

2.5 Power Consumption .................................................................15

2.5.1 Intel® Core™ i7-4650U 1.7 GHz Dual Core™ 4MB Cache ..... 16

2.5.2 Intel® Core™ i5-4300U 1.9 GHz Dual Core™ 3MB Cache ..... 16

2.5.3 Intel® Core™ i3-4010U 1.7 GHz Dual Core™ 3MB Cache ..... 17

2.5.4 Intel® Celeron® 2980U 1.6 GHz Dual Core™ 2MB Cache ...... 17

2.6 Supply Voltage Battery Power ................................................. 17

2.6.1 CMOS Battery Power Consumption ........................................ 17

2.7 Environmental Specications ................................................... 18

3 Block Diagram ..........................................................................19

4 Heatspreader ...........................................................................20

4.1 Heatspreader Dimensions ....................................................... 21

5 Connector Subsystems Rows A, B, C, D ................................. 22

5.1 Primary Connector Rows A and B ............................................ 23

5.1.1 Serial ATA™ (SATA) ................................................................. 23

5.1.2 USB 2.0 ....................................................................................23

5.1.3 High Denition Audio (HDA) Interface ...................................... 23

5.1.4 Gigabit Ethernet ......................................................................23

5.1.5 LPC Bus ...................................................................................24

5.1.6 I²C Bus Fast Mode ...................................................................24

5.1.7 PCI Express™ .........................................................................24

5.1.8 ExpressCard™ .........................................................................24

5.1.9 Graphics Output (VGA/CRT) ...................................................24

5.1.10 LCD (LVDS/eDP) ..................................................................... 25

5.1.11 General Purpose Serial Interface ............................................. 25

5.1.12 Power Control ..........................................................................26

5.1.13 Power Management .................................................................29

5.2 Secondary Connector Rows C and D ...................................... 30

5.2.1 PCI Express™ .........................................................................30

5.2.2 PCI Express Graphics (PEG) ...................................................30

5.2.3 Digital Display Interface ...........................................................30

5.2.3.1 HDMI ........................................................................................31

5.2.3.2 DVI ........................................................................................... 31

5.2.3.3 DisplayPort (DP) ......................................................................31

5.2.4 USB 3.0 ....................................................................................32

6 Additional Features ..................................................................33

6.1 congatec Board Controller (cBC) ............................................. 33

6.2 Board Information ....................................................................33

6.3 Watchdog ................................................................................. 33

6.4 I2C Bus ..................................................................................... 33

6.5 Power Loss Control ..................................................................33

6.6 Embedded BIOS ......................................................................34

6.6.1 CMOS Backup in Non Volatile Memory ................................... 34

6.6.2 OEM CMOS Default Settings and OEM BIOS Logo ................ 34

6.6.3 OEM BIOS Code ......................................................................34

6.6.4 congatec Battery Management Interface ................................. 35

6.6.5 API Support (CGOS/EAPI) ......................................................35

6.7 Security Features .....................................................................36

6.8 Suspend to Ram ......................................................................36

7 conga Tech Notes .................................................................... 37

7.1 Intel® PCH-LP Features ...........................................................37

7.1.1 Intel® Rapid Storage Technology ............................................37

7.1.1.1 AHCI ........................................................................................37

7.1.1.2 RAID ........................................................................................37

7.1.1.3 Intel® Smart Response Technology .........................................37

7.1.2 Intel® Rapid Start Technology ..................................................38

7.2 Intel® Processor Features ........................................................38

7.2.1 Intel® Turbo Boost Technology ................................................. 38

7.2.2 Thermal Monitor and Catastrophic Thermal Protection ...........39

7.2.3 Processor Performance Control ............................................... 39

7.2.4 Intel® 64 Architecture ................................................................40

7.2.5 Intel® Virtualization Technology ................................................ 41

7.2.6 Thermal Management ..............................................................41

7.3 ACPI Suspend Modes and Resume Events ............................ 42

7.4 Low Voltage Memory (DDR3L) ................................................ 42

7.5 USB 2.0 EHCI Host Controller Support ................................... 43

8 Signal Descriptions and Pinout Tables .....................................44

8.1 A-B Connector Signal Descriptions .......................................... 45

8.2 A-B Connector Pinout ..............................................................54

8.3 C-D Connector Signal Descriptions ......................................... 56

8.4 C-D Connector Pinout ..............................................................65

8.5 Boot Strap Signals ...................................................................67

9 System Resources ...................................................................68

9.1 I/O Address Assignment ........................................................... 68

9.1.1 LPC Bus ...................................................................................68

9.2 PCI Conguration Space Map ................................................. 69

9.3 PCI Interrupt Routing Map .......................................................70

9.4 I²C Bus ..................................................................................... 70

9.5 SM Bus ....................................................................................70

10 BIOS Setup Description ...........................................................71

11 Industry Specications .............................................................72

List of Tables

Table 1 Feature Summary ....................................................................12

Table 2 Display Combination (U-processor line) .................................. 30

Table 3 Signal Tables Terminology Descriptions .................................. 44

Table 4 Intel® High Denition Audio Link Signals Descriptions ............. 45

Table 5 Gigabit Ethernet Signal Descriptions ....................................... 45

Table 6 Serial ATA Signal Descriptions ................................................. 46

Table 7 PCI Express Signal Descriptions (general purpose) ................ 47

Table 8 ExpressCard Support Pins Signal Descriptions ....................... 47

Table 9 LPC Signal Descriptions ..........................................................48

Table 10 USB Signal Descriptions ..........................................................48

Table 11 CRT Signal Descriptions ..........................................................49

Table 12 LVDS Signal Descriptions ........................................................ 49

Table 13 Embedded DisplayPort Signal Descriptions ............................ 50

Table 14 SPI BIOS Flash Interface Signal Descriptions ......................... 50

Table 15 Miscellaneous Signal Descriptions .......................................... 51

Table 16 General Purpose I/O Signal Descriptions ................................ 51

Table 17 Power and System Management Signal Descriptions ............. 52

Table 18 General Purpose Serial Interface Signal Descriptions ............. 52

Table 19 Power and GND Signal Descriptions ....................................... 53

Table 20 Connector A-B Pinout .............................................................. 54

Table 21 PCI Express Signal Descriptions (general purpose) ................ 56

Table 22 USB 3.0 Signal Descriptions .................................................... 56

Table 23 PCI Express Signal Descriptions (x16 Graphics) ..................... 57

Table 24 DDI Signal Description .............................................................59

Table 25 HDMI Signal Descriptions ........................................................61

Table 26 DisplayPort (DP) Signal Descriptions ...................................... 62

Table 27 Module Type Denition Signal Description .............................. 64

Table 28 Power and GND Signal Descriptions ....................................... 64

Table 29 Connector C-D Pinout ..............................................................65

Table 30 Boot Strap Signal Descriptions ................................................ 67

Table 31 PCI Conguration Space Map ................................................. 69

Table 32 PCI Interrupt Routing Map .......................................................70

1 INTRODUCTION

COM Express™ Concept

COM Express™ is an open industry standard dened specically for COMs (computer on modules). Its creation provides the ability to make a

smooth transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form

factors:

• Compact 95mm x 95mm

• Basic 125mm x 95mm

• Extended 155mm x 110mm

The COM Express™ specication 2.1 denes seven different pinout types.

Types Connector Rows PCI Express Lanes PCI IDE Channels LAN ports

Type 1 A-B Up to 6 1

Type 2 A-B C-D Up to 22 32 bit 1 1

Type 3 A-B C-D Up to 22 32 bit 3

Type 4 A-B C-D Up to 32 1 1

Type 5 A-B C-D Up to 32 3

Type 6 A-B C-D Up to 24 1

Type 10 A-B Up to 4 1

The conga-TC87 modules use the Type 6 pinout denition. They are equipped with two high performance connectors that ensure stable data

throughput.

The COM (computer on module) integrates all the core components and is mounted onto an application specic carrier board. COM modules

are legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These

functions include, but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial ATA,

USB 2.0, and Gigabit Ethernet. The Type 6 pinout provides the ability to offer PCI Express, Serial ATA, and LPC options thereby expanding

the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is

perfectly suited for all applications.

Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all

the interface connectors required to attach the system to the application specic peripherals. This versatility allows the designer to create a

dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™

modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use

of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary.

conga-TC87 Options Information

The conga-TC87 is currently available in four variants. This user’s guide describes all of these variants. The table below show the different

congurations available. Check for the Part No. that applies to your product. This will tell you what options described in this user’s guide are

available on your particular module.

conga-TC87

Part-No. 046901 046902 046903 046904

Processor Intel® Core™ i7-4650U 1.7

GHz Dual Core™ Intel® Core™ i5-4300U 1.9 GHz

Dual Core™ Intel® Core™ i3-4010U 1.7 GHz

Dual Core™ Intel® Celeron® 2980U

1.6 GHz Dual Core™

Intel® Smart Cache 4 MByte 3 MByte 3 MByte 2 MByte

Max. Turbo Frequency 3.3 GHz 2.9 GHz n/a n/a

Processor Graphics Intel® HD graphics 5000 (GT3) Intel® HD graphics 4400 (GT2) Intel® HD graphics 4400 (GT2) Intel® HD graphics (GT2)

Graphics Max. Dynamic Freq 1.1 GHz 1.1 GHz 1.0 GHz 1.0 GHz

PEG No No No No

LVDS Yes Yes Yes Yes

DisplayPort (DP) Yes Yes Yes Yes

HDMI Yes Yes Yes Yes

Processor TDP (Max) 15 W 15 W 15 W 15 W

2 Specications

2.1 Feature List

Table 1 Feature Summary

Form Factor Based on COM Express™ standard pinout Type 6 Rev. 2.1 (Compact size 95 x 95 mm).

Processor Intel® Core™ i7-4650U 1.7 GHz Dual Core™ with 4-MByte Intel® Smart Cache

Intel® Core™ i5-4300U 1.9 GHz Dual Core™ with 3-MByte Intel® Smart Cache

Intel® Core™ i3-4010U 1.7 GHz Dual Core™ with 3-MByte Intel® Smart Cache

Intel® Celeron® 2980U 1.6 GHz Dual Core™ with 2-MByte Intel® Smart Cache

Memory 2 sockets: SO-DIMM DDR3L (Low voltage @ 1.35V) up to 1600MT/s, with 16GB maximum capacity. Sockets located top and bottom side of module.

congatec Board

Controller Multi-stage watchdog, non-volatile user data storage, manufacturing and board information, board statistics, BIOS setup data backup, I2C bus, Power

loss control.

Chipset Intel® 8 Series PCH-LP integrated in the Multi-Chip Package (MCP).

Audio High Denition Audio (HDA)/digital audio interface with support for multiple codecs

Ethernet Gigabit Ethernet support via the onboard Intel® l218LM GbE Phy. Also offers AMT 9.5 support.

Graphics Options Next Generation Intel® HD Graphics (4400/5000) with support for Intel® Clear Video Technology (HD encode/transcode, Blu-ray playback), DirectX

Video Acceleration (full AVC/VC1/MPEG2 hardware decode), OpenGL 4.0 and DirectX11.1. Up to 3 independent displays supported (Must be two DDI’s

(DP, HDMI/DVI) plus one eDP/LVDS)

• LVDS (Integrated at panel interface with 25-112MHz single/dual-channel

LVDS Transmitter). Supports:

• Single-channel LVDS interface: 1 x 18 bpp or 1 x 24 bpp.

• Dual channel LVDS interface: 2 x 18 bpp or 2 x 24 bpp panel.

• VESA LVDS color mappings

• Automatic Panel Detection via Embedded Panel Interface based on

VESA EDID™ 1.3.

• Resolution up to 1920x1200 in dual LVDS bus mode.

• Optional eDP interface

(NOTE: Either eDP or LVDS signals supported. Both not supported).

• DisplayPort 1.1 (DP): 2x DisplayPorts ports on digital ports B, C.

Multiplexed with HDMI/DVI ports. Hot-Plug detect support.

• HDMI 1.4: 2x HDMI ports on digital ports B, C. Multiplexed with

DisplayPort (DP)/DVI. Hot-plug detect support.

• DVI: 2x DVI ports on digital ports B, C. Multiplexed with HDMI/DP

ports. Hot-Plug detect support.

• Optional VGA interface

(NOTE: This option is offered on digital port C and supported only on rev.

C.x. and later. The display combination for revisions with VGA support is

1x DDI, 1x VGA and 1x eDP).

Peripheral

Interfaces • 4x Serial ATA® 6Gb/s with RAID support 0/1/5/10 (Celeron variant

supports only 2x SATA 6Gb/s)

• 4 PCI Express® Lanes. Support for full 5 Gb/s bandwidth in each direction

per x1 links. (can be congured via special/customized BIOS rmware to

support four x1 and one x4 links.

• 8x USB 2.0 (EHCI)

• 2x USB 3.0 (XHCI)

• 2x Serial Interface (UART0/1)

• LPC Bus

• I²C Bus, Fast Mode, multi-master

• SM Bus

• SPI

• GPIOs

BIOS AMI Aptio® UEFI 2.x rmware, 8/16 MByte serial SPI with congatec Embedded BIOS features.

Power Management • ACPI 4.0 compliant with battery support. Also supports Suspend to RAM (S3) and Intel AMT 9.5.

• Congurable TDP

• Ultra low standby power consumption, Deep Sx.

Security Optional discrete Trusted Platform Module “TPM”, new AES Instructions for faster and better encryption.

Note

Some of the features mentioned in the above feature summary are optional. Check the article number of your module and compare it to the

option information list on page 11 of this user’s guide to determine what options are available on your particular module.

2.2 Supported Operating Systems

The conga-TC87 supports the following operating systems.

• Microsoft® Windows® 8

• Microsoft® Windows® 7

• Microsoft® Windows® Embedded Standard

• Linux

2.3 Mechanical Dimensions

• 95.0 mm x 95.0 mm (3.74” x 3.74”)

• Height approximately 18 or 21mm (including heatspreader) depending on the carrier board connector that is used. If the 5mm

(height) carrier board connector is used, then approximate overall height is 18mm. If the 8mm (height) carrier board connector is

used, then approximate overall height is 21mm.

4.00

Heatspreader

Module PCB

Carrier Board PCB

7.00

5.00 2.00

4.50

13.0018.00

2.4 Supply Voltage Standard Power

• 12V DC ± 5%

The dynamic range shall not exceed the static range.

2.4.1 Electrical Characteristics

Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for

pinout Type 6 (dual connector, 440 pins).

Power Rail Module Pin Current

Capability (Amps) Nominal Input

(Volts) Input Range

(Volts) Derated Input

(Volts) Max. Input Ripple

(10Hz to 20MHz)

(mV)

Max. Module Input Power

(w. derated input)

(Watts)

Assumed

Conversion

Efciency

Max. Load

Power

(Watts)

VCC_12V 12 12 11.4-12.6 11.4 +/- 100 137 85% 116

VCC_5V-SBY 2 5 4.75-5.25 4.75 +/- 50 9

VCC_RTC 0.5 3 2.0-3.3 +/- 20

2.4.2 Rise Time

The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during

the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

Nominal Static Range

Dynamic Range

Absolute Minimum

Absolute Maximum12.60V

11.40V

12V

12.10V

11.90V

2.5 Power Consumption

The power consumption values listed in this document were measured under a controlled environment. The hardware used for testing includes

a conga-TC87 module, conga-TEVAL carrier board, hdmi-equipped LCD monitor, SATA SSD drive, and USB keyboard/mouse. The SATA drive

was powered externally by an ATX power supply so that it does not inuence the power consumption value that is measured for the module.

To ensure that only the power consumption of the CPU module is measured, the conga-TEVAL power consumption was determined before the

measurement and subtracted from the overall power consumption value measured.

The USB keyboard/mouse were detached once the module was congured within the OS. All recorded values were averaged over a 30

second time period. Cooling of the module was done by the module specic heatspreader and a fan cooled heatsink to measure the power

consumption under normal thermal conditions.

Each module was measured while running Windows 7 Professional 64Bit, Hyper Threading enabled, Speed Step enabled, CPU Turbo Mode

enabled and Power Plan set to “Power Saver”. This setting ensures that Core™ processors run in LFM (lowest frequency mode) with minimal

core voltage during desktop idle. Each module was tested while using two 2GB memory modules. Using different sizes of RAM, as well as one

or two memory modules, will cause slight variances in the measured results.

To measure the worst case power consumption the cooling solution was removed and the CPU core temperature was allowed to run up to

between 90° and 95°C while running 100% workload with the Power Plan set to “Balanced”. The peak current value was then recorded. This

value should be taken into consideration when designing the system’s power supply to ensure that the power supply is sufcient during worst

case scenarios.

Power consumption values were recorded during the following stages:

Windows 7 (64 bit)

• Desktop Idle (power plan = Power Saver)

• 100% CPU workload (see note below, power plan = Power Saver)

• 100% CPU workload at approximately 100°C peak power consumption (power plan = Balanced)

• Suspend to RAM. Supply power for S3 mode is 5V.

Note

A software tool was used to stress the CPU to Max Turbo Frequency.

Processor Information

The tables below provide additional information about the power consumption data for each of the conga-TC87 variants offered. The values

are recorded at various operating mode.

2.5.1 Intel® Core™ i7-4650U 1.7 GHz Dual Core™ 4MB Cache

conga-TC87 Art. No. 046901

(GT3 Graphics) Intel® Core™ i7-4650U 1.7 GHz 2 Core™ 4MB Intel® Smart Cache

22nm

Layout Rev. TU87LB1 /BIOS Rev. TU87R005

Max Turbo Frequency 3.3 GHz

Memory Size 4GB

Operating System Windows 7 (64 bit)

Power State Desktop Idle 100% workload 100% workload in

Turbo mode (peak) Suspend to Ram (S3) 5V Input

Power

Power consumption (measured in Amperes/Watts) 0.23 A/2.8 W (12V) 1.38 A/16.6 W (12V) 2.41 A/28.9 W (12V) 0.06 A/0.3 W (5V)

2.5.2 Intel® Core™ i5-4300U 1.9 GHz Dual Core™ 3MB Cache

conga-TC87 Art. No. 046902

(GT2 Graphics) Intel® Core™ i5-4300U 1.9 GHz 2 Core™ 3MB Intel® Smart Cache

22nm

Layout Rev. TU87LB1 /BIOS Rev. TU87R005

Max Turbo Frequency 2.9 GHz

Memory Size 4GB

Operating System Windows 7 (64 bit)

Power State Desktop Idle 100% workload 100% workload in

Turbo mode (peak) Suspend to Ram (S3) 5V Input

Power

Power consumption (measured in Amperes/Watts) 0.28 A/3.4 W (12V) 1.38 A/16.6 W (12V) 1.95 A/23.4 W (12V) 0.06 A/0.3 W (5V)

2.5.3 Intel® Core™ i3-4010U 1.7 GHz Dual Core™ 3MB Cache

conga-TC87 Art. No. 046903

(GT2 Graphics) Intel® Core™ i3-4010U 1.7 GHz 2 Core™ 3MB Intel® Smart Cache

22nm

Layout Rev. TU87LB1 /BIOS Rev. TU87R005

Max Turbo Frequency N/A

Memory Size 4GB

Operating System Windows 7 (64 bit)

Power State Desktop Idle 100% workload 100% workload approx.

100% CPU temp (peak) Suspend to Ram (S3) 5V Input

Power

Power consumption (measured in Amperes/Watts) 0.23 A/2.8 W (12V) 0.99 A/11.9 W (12V) 1.67 A/20.0 W (12V) 0.06 A/0.3 W (5V)

2.5.4 Intel® Celeron® 2980U 1.6 GHz Dual Core™ 2MB Cache

conga-TC87 Art. No. 046904

(GT2 Graphics) Intel® Celeron® 2980U 1.6 GHz 2 Core™ 2MB Intel® Smart Cache

22nm

Layout Rev. TU87LB1 /BIOS Rev. TU87R005

Max Turbo Frequency N/A

Memory Size 4GB

Operating System Windows 7 (64 bit)

Power State Desktop Idle 100% workload 100% workload approx.

100% CPU temp (peak) Suspend to Ram (S3) 5V Input

Power

Power consumption (measured in Amperes/Watts) TBD TBD TBD TBD

2.6 Supply Voltage Battery Power

• 2.0V-3.5V DC

• Typical 3V DC

2.6.1 CMOS Battery Power Consumption

RTC @ 20ºC Voltage Current

Integrated in the Intel® 8 Series PCH-LP 3V DC 9 µA

The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime. You should measure the

CMOS battery power consumption in your customer specic application in worst case conditions, for example during high temperature and high

battery voltage. The self-discharge of the battery must also be considered when determining CMOS battery lifetime. For more information about

calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_Lifetime.pdf on congatec AG website at www.congatec.com.

2.7 Environmental Specications

Temperature Operation: 0° to 60°C Storage: -20° to +80°C

Humidity Operation: 10% to 90% Storage: 5% to 95%

Caution

The above operating temperatures must be strictly adhered to at all times. When using a heatspreader, the maximum operating temperature

refers to any measurable spot on the heatspreader’s surface.

congatec AG strongly recommends that you use the appropriate congatec module heatspreader as a thermal interface between the module

and your application specic cooling solution.

If for some reason it is not possible to use the appropriate congatec module heatspreader, then it is the responsibility of the operator to ensure

that all components found on the module operate within the component manufacturer’s specied temperature range.

For more information about operating a congatec module without heatspreader, contact congatec technical support.

Humidity specications are for non-condensing conditions.

3 Block Diagram

Intel® ULT SOC (CPU + PCH)

Integrated Intel HD Graphics

Vector Graphics

Turbo Boost 2.0 Technology

HT Technology

AVX2

AES-NI

SSE4.2 TSX

64 Architecture

TXT

2D DXVA

MPEG-2

Video Codecs APIs

Hardware Graphics Accelerators

DisplayPort 1.2 HDMI 1.4 (3D, 4k)

Digital Display Interfaces

4th Generaon Intel® Core™ Processor

WMV9

H.264

OpenCL 1.2

DirectX 11.1

OpenGL 4.0

Intel® 8 Series PCH-LP

Digital Display Signals

High Deﬁnion Audio

ASRC

DDC AUX CH Hot Plug Detect

SATA USB 2.0

LPC BusPCIe

I/O Interfaces

GPIOs

USB 3.0

MGMNT

PECI

Dual Channel DDR3L

eDP

Low Power Interconnect

PCIe0

PCIe1

PCIe2

PCIe3

PCIe5-L0

PCIe5-L1

PCIe5-L2

eDP to LVDS

Bridge

HUB

congatec System

Management

Controller

PCIe5-L3

2x SO-DIMM (X1/X2)

SPI Flash

LVDS/eDP

VGA supported only on rev. C.x and later

Ethernet 10/100/1000

Intel I218LM

Oponal DP to VGA

(Only on rev. C.x and later)

TPM

XDP

LPC

I2C

SATA0 - SATA3

USB 2.0

SM Bus

UART0/1

Ethernet

CRT

LVDS/eDP

COM Express

Type 6

A-B Connector

LPC Bus

HDA I/F

SER0/1

USB Port 0..7

SATA Port 0

SATA Port 1

SATA Port 2

SATA Port 3

GPIOs

I2C Bus

SM Bus

SPI

LID#/SLEEP#

FAN control

CRT

PCIe Port 0

PCIe Port 1

PCIe Port 2

PCIe Port 3

PCIe Port 4

PCIe Port 5

USB 3.0 Port 0

USB 3.0 Port 1

USB 3.0 Port 2

USB 3.0 Port 3

(TX BC)

congatec custom

PCIe Port 6

PCIe Port 7

COM Express

Type 6

A-B Connector

PEG x16

DP/HDMI Port C

DP/HDMI Port B

DP/HDMI Port D

4 Heatspreader

An important factor for each system integration is the thermal design. The heatspreader acts as a thermal coupling device to the module and

its aluminum plate is 4mm thick. The heatspreader is thermally coupled to the CPU and other heat generating components via a heat pipe.

Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated, it is not to be considered

as a heatsink. It has been designed to be used as a thermal interface between the module and the application specic thermal solution. The

application specic thermal solution may use heatsinks with fans, and/or heat pipes, which can be attached to the heatspreader. Some thermal

solutions may also require that the heatspreader is attached directly to the systems chassis thereby using the whole chassis as a heat dissipater.

For additional information about the conga-TC87 heatspreader, refer to section 4.1 of this document.

Caution

There are mounting holes on the heatspreader designed to attach the heatspreader to the module. These mounting holes must be used

to ensure that all components that are required to make contact with heatspreader do so. Failure to use these mounting holes will result in

improper contact between these components and heatspreader thereby reducing heat dissipation efciency.

Attention must be given to the mounting solution used to mount the heatspreader and module into the system chassis. Do not use a threaded

heatspreader together with threaded carrier board standoffs. The combination of the two threads may be staggered, which could lead to

stripping or cross-threading of the threads in either the standoffs of the heatspreader or carrier board.

4.1 Heatspreader Dimensions

Note

All measurements are in millimeters. Torque specication for heatspreader screws is 0.3 Nm. Mechanical system assembly mounting shall

follow the valid DIN/IS0 specications.

Caution

When using the heatspreader in a high shock and/or vibration environment, congatec recommends the use of a thread-locking uid on the

heatspreader screws to ensure the above mentioned torque specication is maintained.

5 Connector Subsystems Rows A, B, C, D

The conga-TC87 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout) for a total of 440 pins connectivity.

These connectors are broken down into four rows. The primary connector consists of rows A and B while the secondary connector consists of

rows C and D.

In this view the connectors are seen “through” the module.

top view

C-D

A-B

4 PCI Express Lanes

4x Serial ATA

8x USB 2.0

High Definition Audio I/F

Gigabit Ethernet

(connected via a x1 PCI Express Lane)

LPC Bus

2x Serial Interface (UART)

I²C Bus Fast Mode

LVDS/eDP

SM Bus

SPI

GPIOs

Power Control

Power Management

Fan Control

C-D

2x USB 3.0

2x HDMI

(Routed to DDI interface at

connector)

2x DVI

(Routed to DDI interface at

connector)

2x DisplayPort (DP)

(Routed to DDI interface at

connector)

1x VGA (optional)

(supported only on rev. C.x and

later)

5.1 Primary Connector Rows A and B

The following subsystems can be found on the primary connector rows A and B.

5.1.1 Serial ATA™ (SATA)

The conga-TC87 provides 4 SATA interfaces (SATA 0-3) externally via the Intel® 8 Series PCH-LP integrated in the MCP. The SATA ports are

based on Serial ATA Specication, Revision 3.0 and support up to 6.0 Gb/s data transfer rates.

The Intel® 8 Series PCH-LP featured on the conga-TC87 has one integrated SATA host controller. This controller does not support legacy mode

using I/O space, rather it supports only one mode of operation - AHCI mode using memory space. Hot-plug is also supported when operating

in non-native IDE mode. For more information, refer to section 10 “BIOS Setup Description”.

Note

The conga-TC87 Celeron variants support up to 2 SATA interfaces only.

5.1.2 USB 2.0

The conga-TC87 offers 8 USB 2.0 interfaces on the A-B connector. The EHCI host controller in the PCH supports these interfaces with high-

speed, full-speed and low-speed USB signalling. The controller complies with USB standard 1.1 and 2.0. For more information about how the

USB host controllers are routed, see section 7.5.

5.1.3 High Denition Audio (HDA) Interface

The conga-TC87 provides an interface that supports the connection of HDA audio codecs.

5.1.4 Gigabit Ethernet

The conga-TC87 is equipped with a Gigabit Ethernet Controller that is integrated within the Intel® 8 Series PCH-LP. This controller is routed

to the onboard Intel® l218-LM Phy through the use of the fth PCI Express lane. The Ethernet interface consists of 4 pairs of low voltage

differential pair signals designated from GBE0_MD0± to GBE0_MD3± plus control signals for link activity indicators. These signals can be used

to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board.

Note

The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection. It is not active during a 10Mbit connection. This is a limitation

of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the

GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TC87 module.

5.1.5 LPC Bus

conga-TC87 offers the LPC (Low Pin Count) bus through the Intel® 8 Series PCH-LP. There are many devices available for this Intel® dened

bus. The LPC bus corresponds approximately to a serialized ISA bus yet with a signicantly reduced number of signals. Due to the software

compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application specic baseboard

using this bus. See section 9.1.1 for more information about the LPC Bus.

5.1.6 I²C Bus Fast Mode

The I²C bus is implemented through the congatec board controller (TI Stellaris® LM4FS11H5BB) and accessed through the congatec CGOS

driver and API. The controller provides a Fast Mode multi-master I²C Bus that has maximum I²C bandwidth.

5.1.7 PCI Express™

The conga-TC87 offers 5 PCI Express™ lanes via the Intel® 8 Series PCH-LP. Four of these lanes are offered externally on the A-B connector.

The remaining lane is used by the onboard Gigabit Ethernet interface. The lanes are Gen 2 compliant and offer support for full 5 Gb/s bandwidth

in each direction per x1 link.

Default conguration for the lanes on the AB connector is 4x1 link. A 1x4 and 2x2 link conguration is also possible but requires a special/

customized BIOS rmware. Contact congatec technical support for more information about this subject.

The PCI Express interface is based on the PCI Express Specication 2.0 with Gen 1 (2.5Gb/s) and Gen 2 (5 Gb/s) speed.

5.1.8 ExpressCard™

The conga-TC87 supports the implementation of ExpressCards, which requires the dedication of one USB 2.0 port or a x1 PCI Express link

for each ExpressCard used.

5.1.9 Graphics Output (VGA/CRT)

The Intel® ULT SoC does not support VGA interface. However on the conga-TC87 rev C.x and later, an optional VGA interface is supported on

the DDI digital port C via NXP PTN3392BS Displayport to VGA controller.

5.1.10 LCD (LVDS/eDP)

The conga-TC87 offers an LVDS/eDP interface on the AB connector. The LVDS/eDP interface is by default congured to provide LVDS signals.

The interface can optionally be switched via the BIOS setup menu to support eDP signals.

The single/dual channel LVDS interface is provided through an onboard eDP to LVDS bridge device. The eDP to LVDS bridge processes

incoming DisplayPort stream and converts the DP protocol to LVDS, before transmitting the processed stream in LVDS format. The bridge

supports single and dual channel signalling with color depths of 18 bits or 24 bits per pixel and pixel clock frequency up to 112 MHz.

Note

The LVDS/eDP interface supports either LVDS or eDP signals. Both signals are not supported simultaneously.

5.1.11 General Purpose Serial Interface

Two TTL compatible two wire ports are available on Type 6 COM Express modules. These pins are designated SER0_TX, SER0_RX, SER1_TX

and SER1_RX. Data out of the module is on the _TX pins. Hardware handshaking and hardware ow control are not supported. The module

asynchronous serial ports are intended for general purpose use and for use with debugging software that make use of the “console redirect”

features available in many operating systems.

The conga-TC87 offers two UART interfaces via two UART controllers integrated in the congatec Board Controller. These controllers support

up to 1MBit/s and can operate in low-speed, full-speed and high-speed modes. The UART interfaces are routed to the AB connector and

require congatec driver to function..

Note

The UART interfaces do not support legacy COM port emulation.

5.1.12 Power Control

PWR_OK

Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module can

start its onboard power sequencing.

Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low

at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier

board power rails are up, to ensure a stable system.

A sample screenshot is shown below:

Note

The module is kept in reset as long as the PWR_OK is driven by carrier board hardware.

The conga-TC87 PWR_OK input circuitry is implemented as shown below:

The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also allows for carrier board designs that are not driving

PWR_OK. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier

board hardware drives the signal low until it is safe to let the module boot-up.

When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be

only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specication but this

can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when

the carrier board hardware is ready to boot.

The three typical usage scenarios for a carrier board design are:

• Connect PWR_OK to the “power good” signal of an ATX type power supply.

To Module Power Logic

PWR_OK

R1%47k5S02

TBC847

R1%100kS02

+V12.0_S0

R13

R1%1k00S02

R1%47k5S02

R1%20k0S02

• Connect PWR_OK to the last voltage regulator in the chain on the carrier board.

• Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.

With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.

The conga-TC87 provides support for controlling ATX-style power supplies. When not using an ATX power supply then the conga-TC87’s pins

SUS_S3/PS_ON, 5V_SB, and PWRBTN# should be left unconnected.

SUS_S3#/PS_ON#

The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an ATX-

style power supply. In order to accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and

is located on the carrier board.

PWRBTN#

When using ATX-style power supplies PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary-contact, active-low

debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to

3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this

signal from the system may vary as a result of modications made in BIOS settings or by system software.

Power Supply Implementation Guidelines

12 volt input power is the sole operational power source for the conga-TC87. The remaining necessary voltages are internally generated on

the module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing

a power supply for a conga-TC87 application:

• It has also been noticed that on some occasions, problems occur when using a 12V power supply that produces non monotonic voltage

when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals

when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming

confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply

applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use

of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. This should be done during the power supply

qualication phase therefore ensuring that the above mentioned problem doesn’t arise in the application. For more information about this

issue visit www.formfactors.org and view page 25 gure 7 of the document “ATX12V Power Supply Design Guide V2.2”.

5.1.13 Power Management

ACPI

The conga-TC87 supports Advanced Conguration and Power Interface (ACPI) specication, revision 4.0a. It also supports Suspend to RAM

(S3). For more information, see section 7.3 “ACPI Suspend Modes and Resume Events”.

DEEP Sx

The Deep Sx is a lower power state employed to minimize the power consumption while in S3/S4/S5. In the Deep Sx state, the system entry

condition determines if the system context is maintained or not. All power is shut off except for minimal logic which supports limited set of wake

events for Deep Sx. The Deep Sx on resumption, puts system back into the state it is entered from. In other words, if Deep Sx state was entered

from S3 state, then the resume path will place system back into S3.

5.2 Secondary Connector Rows C and D

The following subsystems can be found on the secondary connector rows C and D.

5.2.1 PCI Express™

The conga-TC87 does not offer PCI Express lanes on the CD connector. For more information on supported PCI Express lanes, see section

5.1.7.

5.2.2 PCI Express Graphics (PEG)

The Intel® ULT SoC does not support PEG interface.

5.2.3 Digital Display Interface

The conga-TC87 supports two Digital Display Interfaces. These interfaces can be congured as DisplayPort, HDMI/DVI. On conga-TC87 rev

C.x and later, the DDI digital port C is used for optional VGA support.

The processor on the conga-TC87 supports High-bandwidth Digital Content Protection (HDCP) for playing high denition content over digital

interfaces. Integrated in the processor is a dedicated Mini HD audio controller which drives audio on integrated digital display interfaces such

as HDMI and DisplayPort.

The conga-TC87 offers the Digital Display Interface on the CD connector and supports up to three independent displays. The display combination

must be 2 DDI and 1 eDP. For revisions equipped with optional VGA, the combination must be 1x DDI (Port B), 1x VGA (via Port C) and 1x

eDP. The table below shows the conga-TC87 display combination and is not applicable to revisions equipped with optional VGA interface.

Table 2 Display Combination (U-processor line)

Display 1

(DDI Port B) Display 2

(DDI Port C) Display 3 Display 1

Max. Resolution Display 2

Max. Resolution Display 3

Max. Resolution

HDMI HDMI eDP 4096x2304 @24Hz 4096x2304 @24Hz 3200x2000 @60Hz

DP DP eDP 3200x2000 @60Hz 3200x2000 @60Hz 3200x2000 @60Hz

HDMI DP eDP 4096x2304 @24Hz 3200x2000 @60Hz 3200x2000 @60Hz

Note

The DP and eDP resolutions in the table above are supported for 4 lanes with link data rate HBR2 at 24 bits per pixel and single stream mode

of operation. The DisplayPort Aux CH, DDC channel, panel power sequencing and HPD are supported through the PCH.

5.2.3.1 HDMI

The conga-TC87 offers two HDMI ports on the CD connector via the Digital Display Interfaces supported by the processor. The HDMI interfaces

are based on HDMI 1.4 specication with support for 3D, 4K, Deep Color and x.v Color. These interfaces are multiplexed onto the Digital

Display Interface of the COM Express connector.

Supported audio formats are AC-3 Dolby Digital, Dolby Digital Plus, DTS-HD, LPCM, 192 KHz/24 bit, 8 channel, Dolby TrueHD, DTS-HD

Master Audio (Lossless Blu-Ray Disc Audio Format).

Note

The conga-TC87 supports a maximum of 2 independent HDMI displays. Revisions equipped with optional VGA interface support only 1 HDMI

interface. See table 2 above for possible display combinations. Consumer electronics control (CEC) is not supported.

5.2.3.2 DVI

The conga-TC87 offers two DVI ports on the CD connector. The DVI interfaces are multiplexed onto the Digital Display Interface of the COM

Express connector.

Note

The conga-TC87 supports a maximum of 2 independent DVI displays. Revisions equipped with optional VGA interface support only 1 DVI

interface. See table 2 above for possible display combinations.

5.2.3.3 DisplayPort (DP)

The conga-TC87 offers two DP ports, each capable of supporting data rate of 1.62 GT/s, 2.97 GT/s and 5.4 GT/s on 1, 2 or 4 data lanes. The

DP is multiplexed onto the Digital Display Interface (DDI) of the COM Express connector and can support up to 3200x2000 resolutions at 60Hz.

The DisplayPort specication is a VESA standard aimed at consolidating internal and external connection methods to reduce device complexity,

supporting key cross industry applications, and providing performance scalability to enable the next generation of displays. See section 8.5 of

this document for more information about enabling DisplayPort peripherals.

Note

The conga-TC87 supports a maximum of 2 independent DisplayPort displays. Revisions equipped with optional VGA interface support only 1

DP interface. See table 2 above for possible display combinations.

5.2.4 USB 3.0

The conga-TC87 offers two SuperSpeed USB 3.0 ports on the CD connector. These ports are controlled by an xHCI host controller provided

by the Intel® 8 Series PCH-LP integrated in the MCP. The host controller allows data transfers of up to 5 Gb/s and supports SuperSpeed, high-

speed, full-speed and low-speed trafc.

Note

The xHCI controller supports USB 3.0 debugging.

6 Additional Features

6.1 congatec Board Controller (cBC)

The conga-TC87 is equipped with Texas Instruments Tiva™ TM4E1231H6ZRB microcontroller. This onboard microcontroller plays an important

role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features such as system monitoring

or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86

processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all congatec modules.

6.2 Board Information

The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and rmware

revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

6.3 Watchdog

The conga-TC87 is equipped with a multi stage watchdog solution that is triggered by software. The COM Express™ Specication does not

provide support for external hardware triggering of the Watchdog, which means the conga-TC87 does not support external hardware triggering.

For more information about the Watchdog feature, see the BIOS setup description in section 10.4.2 of this document and application note

AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.

Note

The conga-TC87 module does not support the watchdog NMI mode. COM Express type 6 modules do not support the PCI bus, therefore the

PCI_SERR# signal is not available. There is no way to drive an NMI to the processor without the presence of the PCI_SERR# PCI bus signal.

6.4 I2C Bus

The conga-TC87 supports I2C bus. Thanks to the I2C host controller in the cBC, the I2C bus is multi-master capable and runs at fast mode.

6.5 Power Loss Control

The cBC has full control of the power-up of the module and therefore can be used to specify the behavior of the system after an AC power loss

condition. Supported modes are “Always On”, “Remain Off” and “Last State”.

6.6 Embedded BIOS

The conga-TC87 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI rmware. These are

the most important embedded PC features:

6.6.1 CMOS Backup in Non Volatile Memory

A copy of the CMOS memory (SRAM) is stored in the BIOS ash device. This prevents the system from booting up with the wrong system

conguration if the backup battery (RTC battery) fails. Additionally, it provides the ability to create systems that do not require a CMOS backup

battery.

6.6.2 OEM CMOS Default Settings and OEM BIOS Logo

This feature allows system designers to create and store their own CMOS default conguration and BIOS logo (splash screen) within the BIOS

ash device. Customized BIOS development by congatec for these changes is no longer necessary because customers can easily do these

changes by themselves using the congatec system utility CGUITL.

6.6.3 OEM BIOS Code

With the congatec embedded BIOS it is even possible for system designers to add their own code to the BIOS POST process. Except for

custom specic code, this feature can also be used to support Win XP SLP installation, Window 7 SLIC table, verb tables for HDA codecs, rare

graphic modes and Super I/O controllers.

For more information about customizing the congatec embedded BIOS refer to the congatec System Utility user’s guide, which is called

CGUTLm1x.pdf and can be found on the congatec AG website at www.congatec.com or contact congatec technical support.

6.6.4 congatec Battery Management Interface

In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec AG dened an interface for

the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according

to the congatec Battery Management Interface Specication can provide the battery management functions supported by an ACPI capable

operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...), without the need

for additional modications to the system BIOS.

The conga-TC87 BIOS fully supports this interface. For more information about this subject visit the congatec website and view the following

documents:

• congatec Battery Management Interface Specication

• Battery System Design Guide

• conga-SBM3 User’s Guide

6.6.5 API Support (CGOS/EAPI)

In order to benet from the above mentioned non-industry standard feature set, congatec provides an API that allows application software

developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming

Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux.

The architecture of the CGOS API driver provides the ability to write application software that runs unmodied on all congatec CPU modules.

All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software

developers guide, which is available on the congatec website .

Other COM (Computer on Modules) vendors offer similar driver solutions for these kind of embedded PC features, which are by nature

proprietary. All the API solutions that can be found on the market are not compatible to each other. As a result, writing application software that

can run on more than one vendor’s COM is not so easy. Customers have to change their application software when switching to another COM

vendor. EAPI (Embedded Application Programming Interface) is a programming interface dened by the PICMG that addresses this problem.

With this unied API it is now possible to run the same application on all vendor’s COMs that offer EAPI driver support. Contact congatec

technical support for more information about EAPI.

6.7 Security Features

The conga-TC87 can be equipped optionally with a “Trusted Platform Module“ (TPM 1.2). This TPM 1.2 includes coprocessors to calculate

efcient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive applications

like gaming and e-commerce will benet also with improved authentication, integrity and condence levels.

6.8 Suspend to Ram

The Suspend to RAM feature is available on the conga-TC87.

7 conga Tech Notes

The conga-TC87 has some technological features that require additional explanation. The following section will give the reader a better

understanding of some of these features. This information will also help to gain a better understanding of the information found in the System

Resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.

7.1 Intel® PCH-LP Features

7.1.1 Intel® Rapid Storage Technology

The Intel® 8 Series PCH-LP provides support for Intel® Rapid Storage Technology, allowing AHCI functionality and RAID 0/1/5/10 support.

7.1.1.1 AHCI

The Intel® 8 Series PCH-LP provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface

for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as port independent DMA engines

(each device is treated as a master) and hardware-assisted native command queuing. AHCI also provides usability enhancements such as

Hot-Plug and advanced power management.

7.1.1.2 RAID

The industry-leading RAID capability provides high performance RAID 0, 1, 5, and 10 functionality on the 4 SATA ports of Intel® 8 Series

PCH-LP. Software components include an Option ROM for pre-boot conguration and boot functionality, a Microsoft* Windows* compatible

driver, and a user interface for conguration and management of the RAID capability of the Intel® 8 Series PCH-LP.

7.1.1.3 Intel® Smart Response Technology

Intel® Smart Response Technology is a disk caching solution that can provide improved computer system performance with improved

power savings. It allows conguration of a computer systems with the advantage of having HDDs for maximum storage capacity with system

performance at or near SSD performance levels.

Note

This feature requires an Intel® Core Processor

7.1.2 Intel® Rapid Start Technology

Intel® Rapid Start Technology enables systems to quickly resume from deep sleep. With this feature enabled, the system resumes smoothly

and faster than with fresh Start Up or Resume from Hibernate, while maintaining the previous activity of the user.

Note

This feature requires an Intel® Core Processor

7.2 Intel® Processor Features

7.2.1 Intel® Turbo Boost Technology

Intel® Turbo Boost Technology allows processor cores to run faster than the base operating frequency if it’s operating below power, current, and

temperature specication limits. Intel® Turbo Boost Technology is activated when the Operating System (OS) requests the highest processor

performance state. The maximum frequency of Intel® Turbo Boost Technology is dependent on the number of active cores. The amount of time

the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment. Any of the following

can set the upper limit of Intel® Turbo Boost Technology on a given workload:

• Number of active cores

• Estimated current consumption

• Estimated power consumption

• Processor temperature

When the processor is operating below these limits and the user’s workload demands additional performance, the processor frequency will

dynamically increase by 100 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of

active cores is reached. For more information about Intel® Turbo Boost 2 Technology visit the Intel® website.

Note

Only conga-TC87 module variants that feature the Core™ i7 and i5 processors support Intel® Turbo Boost 2 Technology. Refer to the power

consumption tables in section 2.5 of this document for information about the maximum turbo frequency available for each variant of the

conga-TC87.

7.2.2 Thermal Monitor and Catastrophic Thermal Protection

Intel® Core™ i7/i5/i3 and Celeron® processors have a thermal monitor feature that helps to control the processor temperature. The integrated

TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation temperature that

the Intel® Thermal Monitor uses to activate the TCC can be slightly modied via TCC Activation Offset in BIOS setup submenu “CPU submenu”.

The Thermal Monitor can control the processor temperature through the use of two different methods dened as TM1 and TM2. TM1 method

consists of the modulation (starting and stopping) of the processor clocks at a 50% duty cycle. The TM2 method initiates an Enhanced Intel

Speedstep transition to the lowest performance state once the processor silicon reaches the maximum operating temperature.

Note

The maximum operating temperature for Intel® Core™ i7/i5/i3 and Celeron® processors is 100°C.

To ensure that the TCC is active for only short periods of time, thus reducing the impact on processor performance to a minimum, it is necessary

to have a properly designed thermal solution. The Intel® Core™ i7/i5/i3 and Celeron® processor’s respective datasheet can provide you with

more information about this subject.

THERMTRIP# signal is used by Intel®’s Core™ i7/i5/i3 and Celeron® processors for catastrophic thermal protection. If the processor’s silicon

reaches a temperature of approximately 125°C then the processor signal THERMTRIP# will go active and the system will automatically shut

down to prevent any damage to the processor as a result of overheating. The THERMTRIP# signal activation is completely independent from

processor activity and therefore does not produce any bus cycles.

Note

In order for THERMTRIP# to be able to automatically switch off the system, it is necessary to use an ATX style power supply.

7.2.3 Processor Performance Control

Intel® Core™ i7/i5/i3 and Celeron® processors found on the conga-TC87 run at different voltage/frequency states (performance states), which

is referred to as Enhanced Intel® SpeedStep® technology (EIST). Operating systems that support performance control take advantage of

microprocessors that use several different performance states in order to efciently operate the processor when it’s not being fully used.

The operating system will determine the necessary performance state that the processor should run at so that the optimal balance between

performance and power consumption can be achieved during runtime.

The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that the

power scheme setting you choose has the ability to support Enhanced Intel® SpeedStep® technology.

7.2.4 Intel® 64 Architecture

The formerly known Intel® Extended Memory 64 Technology is an enhancement to Intel®’s IA-32 architecture. Intel® 64 is only available on

Intel® Core™ i7/i5/i3 and Celeron® processors and is designed to run with newly written 64-bit code and access more than 4GB of memory.

Processors with Intel® 64 architecture support 64-bit-capable operating systems from Microsoft, Red Hat and SuSE. Processors running in

legacy mode remain fully compatible with today’s existing 32-bit applications and operating systems

Platforms with Intel® 64 can be run in three basic ways :

1. Legacy Mode: 32-bit operating system and 32-bit applications. In this mode no software changes are required, however the benets of

Intel® 64 are not utilized.

2. Compatibility Mode: 64-bit operating system and 32-bit applications. This mode requires all device drivers to be 64-bit. The operating

system will see the 64-bit extensions but the 32-bit application will not. Existing 32-bit applications do not need to be recompiled and may

or may not benet from the 64-bit extensions. The application will likely need to be re-certied by the vendor to run on the new 64-bit

extended operating system.

3. 64-bit Mode: 64-bit operating system and 64-bit applications. This usage requires 64-bit device drivers. It also requires applications to be

modied for 64-bit operation and then recompiled and validated.

Intel® 64 supports:

• 64-bit at virtual address space

• 64-bit pointers

• 64-bit wide general purpose registers

• 64-bit integer support

• Up to one Terabyte (TB) of platform address space

You can nd more information about Intel® 64 Technology at: http://developer.intel.com/technology/intel64/index.htm

7.2.5 Intel® Virtualization Technology

Virtualization solutions enhanced by Intel® VT will allow a Core™ i7/i5/i3 platform to run multiple operating systems and applications in

independent partitions. When using virtualization capabilities, one computer system can function as multiple “virtual” systems. With processor

and I/O enhancements to Intel®’s various platforms, Intel® Virtualization Technology can improve the performance and robustness of today’s

software-only virtual machine solutions.

Intel® VT is a multi-generational series of extensions to Intel® processor and platform architecture that provides a new hardware foundation for

virtualization, establishing a common infrastructure for all classes of Intel® based systems. The broad availability of Intel® VT makes it possible

to create entirely new applications for virtualization in servers, clients as well as embedded systems thus providing new ways to improve

system reliability, manageability, security, and real-time quality of service.

The success of any new hardware architecture is highly dependent on the system software that puts its new features to use. In the case of

virtualization technology, that support comes from the virtual machine monitor (VMM), a layer of software that controls the underlying physical

platform resources sharing them between multiple “guest” operating systems. Intel® VT is already incorporated into most commercial and open-

source VMMs including those from VMware, Microsoft, XenSource, Parallels, Virtual Iron, Jaluna and TenAsys.

You can nd more information about Intel® Virtualization Technology at: http://developer.intel.com/technology/virtualization/index.htm

Note

congatec does not offer virtual machine monitor (VMM) software. All VMM software support questions and queries should be directed to the

VMM software vendor and not congatec technical support.

7.2.6 Thermal Management

ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the

operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands

put on the CPU by the application.

The conga-TC87 supports Critical Trip Point. This cooling policy ensures that the operating system shuts down properly if the temperature in

the thermal zone reaches a critical point, in order to prevent damage to the system as a result of high temperatures. Use the “critical trip point”

setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system.

Note

The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the

appropriate trip points.

7.3 ACPI Suspend Modes and Resume Events

conga-TC87 supports S3 (STR= Suspend to RAM). For more information about S3 wake events, see section 10.4.5 “ACPI Conguration

Submenu”.

S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by the following operating systems (S4_OS= Hibernate):

• Windows 8, Windows 7, Windows Vista, Linux.

This table lists the “Wake Events” that resume the system from S3 unless otherwise stated in the “Conditions/Remarks” column:

Wake Event Conditions/Remarks

Power Button Wakes unconditionally from S3-S5.

Onboard LAN Event Device driver must be congured for Wake On LAN support.

SMBALERT# Wakes unconditionally from S3-S5.

PCI Express WAKE# Wakes unconditionally from S3-S5.

PME# Activate the wake up capabilities of a PCI device using Windows Device Manager conguration options for this device OR set Resume On

PME# to Enabled in the Power setup menu.

USB Mouse/Keyboard Event When Standby mode is set to S3, USB hardware must be powered by standby power source.

Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program).

In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer

out of standby’.

RTC Alarm Activate and congure Resume On RTC Alarm in the Power setup menu. Only available in S5.

Watchdog Power Button Event Wakes unconditionally from S3-S5.

7.4 Low Voltage Memory (DDR3L)

The Haswell ULT processor featured on the conga-TC87 supports low voltage system memory interface. The memory interface I/O voltage

is 1.35V and supports non-ECC, unbuffered DDR3L SO-DIMMs. With this low voltage system memory interface on the processor, the conga-

TC87 offers a system optimized for lowest possible power consumption. The reduction in power consumption due to lower voltage subsequently

reduces the heat generated.

Caution

The usage of DDR3@1.5V SO-DIMM modules may affect the stability or boot-up of the conga-TC87. Therefore use only non-ECC, unbuffered

DDR3L SO-DIMM memory modules up to 1600 MT/s on the conga-TC87.

7.5 USB 2.0 EHCI Host Controller Support

The 8 available USB ports are provided by a USB 2.0 Rate Matching Hub (RMH) integrated within the Intel® 8 Series PCH-LP . The EHCI

controller is connected to the hub as shown below. The Hub convert low and full-speed trafc into high-speed trafc. When the RMHs are

enabled, they will appear to software like an external hub is connected to Port 0 of the EHCI controller. In addition, port 1 of the RMH is

multiplexed with Port 1 of the EHCI controller and is able to bypass the RMH for use as the Debug Port. The hub operates like any USB 2.0

Discrete Hub and will consume one tier of hubs allowed by the USB 2.0 Spec. A maximum of four additional non-root hubs can be supported

on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 8000h.

Routing Diagram

EHCI #1EHCI #1

Port 5Port 4Port 3Port 2Port 1Port 0Internal Port: Port 7

Port 7

Port 6

Port 5 Port 6Port 4Port 3Port 2Port 1Port 0COM Express Port:

Ports swapped on revision C.x and later

to support Debug Port on COM Express Port 0

USB 2.0 Rate Matching Hub

EHCI #1

{

8 Signal Descriptions and Pinout Tables

The following section describes the signals found on COM Express™ Type VI connectors used for congatec AG modules. The pinout of the

modules complies with COM Express Type 6 Rev. 2.1.

Table 3 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express™

module pull-up or pull-down resistor has been used. If the eld entry area in this column for the signal is empty, then no pull-up or pull-down

resistor has been implemented by congatec.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When

“#” is not present, the signal is asserted when at a high voltage level.

Note

The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented

by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip’s

datasheet.

Table 3 Signal Tables Terminology Descriptions

Term Description

PU congatec implemented pull-up resistor

PD congatec implemented pull-down resistor

I/O 3.3V Bi-directional signal 3.3V tolerant

I/O 5V Bi-directional signal 5V tolerant

I 3.3V Input 3.3V tolerant

I 5V Input 5V tolerant

I/O 3.3VSB Input 3.3V tolerant active in standby state

O 3.3V Output 3.3V signal level

O 5V Output 5V signal level

OD Open drain output

P Power Input/Output

DDC Display Data Channel

PCIE In compliance with PCI Express Base Specication, Revision 2.0

PEG PCI Express Graphics

SATA In compliance with Serial ATA specication Revision 2.6 and 3.0.

REF Reference voltage output. May be sourced from a module power plane.

PDS Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal

module capabilities (pinout type) to the Carrier Board.

8.1 A-B Connector Signal Descriptions

Table 4 Intel® High Denition Audio Link Signals Descriptions

Signal Pin # Description I/O PU/PD Comment

AC/HDA_RST# A30 Intel® High Denition Audio Reset: This signal is the master hardware reset

to external codec(s). O 3.3VSB AC’97 codecs are not supported.

AC/HDA_SYNC A29 Intel® High Denition Audio Sync: This signal is a 48 kHz xed rate sample

sync to the codec(s). It is also used to encode the stream number. O 3.3VSB AC’97 codecs are not supported.

AC/HDA_BITCLK A32 Intel® High Denition Audio Bit Clock Output: This signal is a 24.000MHz

serial data clock generated by the Intel® High Denition Audio controller.

O 3.3VSB AC’97 codecs are not supported.

AC/HDA_SDOUT A33 Intel® High Denition Audio Serial Data Out: This signal is the serial TDM

data output to the codec(s). This serial output is double-pumped for a bit rate

of 48 Mb/s for Intel® High Denition Audio.

O 3.3VSB PU 1K

3.3VSB

AC’97 codecs are not supported.

AC/HDA_SDOUT is a boot strap signal

(see note below)

AC/HDA_SDIN[2:0] B28-B30 Intel® High Denition Audio Serial Data In [0]: These signals are serial TDM

data inputs from the three codecs. The serial input is single-pumped for a bit

rate of 24 Mb/s for Intel® High Denition Audio.

I 3.3VSB AC’97 codecs are not supported.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.

For more information refer to section 8.5 of this user’s guide.

Table 5 Gigabit Ethernet Signal Descriptions

Gigabit Ethernet Pin # Description I/O PU/PD Comment

GBE0_MDI0+

GBE0_MDI0-

GBE0_MDI1+

GBE0_MDI1-

GBE0_MDI2+

GBE0_MDI2-

GBE0_MDI3+

GBE0_MDI3-

A13

A12

A10

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate

in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following: I/O Analog Twisted pair

signals for

external

transformer.

1000 100 10

MDI[0]+/- B1_DA+/- TX+/- TX+/-

MDI[1]+/- B1_DB+/- RX+/- RX+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB

GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB

GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB

GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB

Gigabit Ethernet Pin # Description I/O PU/PD Comment

GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is

determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The

reference voltage output shall be current limited on the module. In the case in which the reference is shorted

to ground, the current shall be limited to 250mA or less.

Not connected

Note

The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection, it is not active during a 10Mbit connection. This is a limitation

of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the

GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TC87 module.

Table 6 Serial ATA Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SATA0_RX+

SATA0_RX-

A19

A20 Serial ATA channel 0, Receive Input differential pair. I SATA Supports Serial ATA specication, Revision 3.0

SATA0_TX+

SATA0_TX- A16

A17 Serial ATA channel 0, Transmit Output differential pair. O SATA Supports Serial ATA specication, Revision 3.0

SATA1_RX+

SATA1_RX-

B19

B20 Serial ATA channel 1, Receive Input differential pair. I SATA Supports Serial ATA specication, Revision 3.0

SATA1_TX+

SATA1_TX- B16

B17 Serial ATA channel 1, Transmit Output differential pair. O SATA Supports Serial ATA specication, Revision 3.0

SATA2_RX+

SATA2_RX- A25

A26 Serial ATA channel 2, Receive Input differential pair. I SATA Supports Serial ATA specication, Revision 3.0

SATA2_TX+

SATA2_TX- A22

A23 Serial ATA channel 2, Transmit Output differential pair. O SATA Supports Serial ATA specication, Revision 3.0

SATA3_RX+

SATA3_RX- B25

B26 Serial ATA channel 3, Receive Input differential pair. I SATA Supports Serial ATA specication, Revision 3.0

SATA3_TX+

SATA3_TX- B22

B23 Serial ATA channel 3, Transmit Output differential pair. O SATA Supports Serial ATA specication, Revision 3.0

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. I/O 3.3v

Table 7 PCI Express Signal Descriptions (general purpose)

Signal Pin # Description I/O PU/PD Comment

PCIE_RX0+

PCIE_RX0- B68

B69

PCI Express channel 0, Receive Input differential pair. I PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_TX0+

PCIE_TX0- A68

A69

PCI Express channel 0, Transmit Output differential pair. O PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_RX1+

PCIE_RX1- B64

B65 PCI Express channel 1, Receive Input differential pair. I PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_TX1+

PCIE_TX1- A64

A65 PCI Express channel 1, Transmit Output differential pair. O PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_RX2+

PCIE_RX2- B61

B62 PCI Express channel 2, Receive Input differential pair. I PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_TX2+

PCIE_TX2- A61

A62 PCI Express channel 2, Transmit Output differential pair. O PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_RX3+

PCIE_RX3- B58

B59

PCI Express channel 3, Receive Input differential pair. I PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_TX3+

PCIE_TX3- A58

A59

PCI Express channel 3, Transmit Output differential pair. O PCIE Supports PCI Express Base Specication, Revision 2.0

PCIE_RX4+

PCIE_RX4- B55

B56 PCI Express channel 4, Receive Input differential pair. I PCIE Not supported

PCIE_TX4+

PCIE_TX4- A55

A56 PCI Express channel 4, Transmit Output differential pair. O PCIE Not supported

PCIE_RX5+

PCIE_RX5- B52

B53 PCI Express channel 5, Receive Input differential pair. I PCIE Not supported

PCIE_TX5+

PCIE_TX5- A52

A53 PCI Express channel 5, Transmit Output differential pair. O PCIE Not supported

PCIE_CLK_REF+

PCIE_CLK_REF- A88

A89

PCI Express Reference Clock output for all PCI Express

and PCI Express Graphics Lanes. O PCIE A PCI Express Gen2/3 compliant clock buffer chip must be used

on the carrier board if more than one PCI Express device is

designed in.

Table 8 ExpressCard Support Pins Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

EXCD0_CPPE#

EXCD1_CPPE#

A49

B48 ExpressCard capable card request. I 3.3V PU 10k 3.3V

EXCD0_PERST#

EXCD1_PERST# A48

B47 ExpressCard Reset O 3.3V PU 10k 3.3V

Table 9 LPC Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V

LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V

LPC_DRQ[0:1]# B8-B9 LPC serial DMA request I 3.3V PU 10k 3.3V

LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 10k 3.3V

LPC_CLK B10 LPC clock output - 24 MHz nominal O 3.3V

Table 10 USB Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

USB0+ A46 USB Port 0, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB0- A45 USB Port 0, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB1+ B46 USB Port 1, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB1- B45 USB Port 1, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB2+ A43 USB Port 2, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB2- A42 USB Port 2, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB3+ B43 USB Port 3, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB3- B42 USB Port 3, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB4+ A40 USB Port 4, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB4- A39 USB Port 4, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB5+ B40 USB Port 5, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB5- B39 USB Port 5, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB6+ A37 USB Port 6, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB6- A36 USB Port 6, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB7+ B37 USB Port 7, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB7- B36 USB Port 7, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall

be present on the module. An open drain driver from a USB current

monitor on the carrier board may drive this line low.

3.3VSB PU 10k

3.3VSB Do not pull this line high on the carrier board.

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall

be present on the module. An open drain driver from a USB current

monitor on the carrier board may drive this line low. .

3.3VSB PU 10k

3.3VSB Do not pull this line high on the carrier board.

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall

be present on the module. An open drain driver from a USB current

monitor on the carrier board may drive this line low.

3.3VSB PU 10k

3.3VSB Do not pull this line high on the carrier board.

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall

be present on the module. An open drain driver from a USB current

monitor on the carrier board may drive this line low.

3.3VSB PU 10k

3.3VSB Do not pull this line high on the carrier board.

Table 11 CRT Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VGA_RED B89 Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load. O Analog PD 150R Optional on rev. C.x and later

VGA_GRN B91 Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load. O Analog PD 150R Optional on rev. C.x and later

VGA_BLU B92 Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load. O Analog PD 150R Optional on rev. C.x and later

VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V Optional on rev. C.x and later

VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V Optional on rev. C.x and later

VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify VGA monitor capabilities) I/O OD 5V PU 1k2 3.3V Optional on rev. C.x and later

VGA_I2C_DAT B96 DDC data line. I/O OD 5V PU 1k2 3.3V Optional on rev. C.x and later

Table 12 LVDS Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

LVDS_A0+

LVDS_A0-

LVDS_A1+

LVDS_A1-

LVDS_A2+

LVDS_A2-

LVDS_A3+

LVDS_A3-

A71

A72

A73

A74

A75

A76

A78

A79

LVDS Channel A differential pairs O LVDS

LVDS_A_CK+

LVDS_A_CK- A81

A82 LVDS Channel A differential clock O LVDS

LVDS_B0+

LVDS_B0-

LVDS_B1+

LVDS_B1-

LVDS_B2+

LVDS_B2-

LVDS_B3+

LVDS_B3-

B71

B72

B73

B74

B75

B76

B77

B78

LVDS Channel B differential pairs O LVDS

LVDS_B_CK+

LVDS_B_CK- B81

B82 LVDS Channel B differential clock O LVDS

LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 10k

LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V PD 10k

LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V

LVDS_I2C_CK A83 DDC lines used for at panel detection and control. O 3.3V PU 2k2 3.3V

LVDS_I2C_DAT A84 DDC lines used for at panel detection and control. I/O 3.3V PU 2k2 3.3V .

Table 13 Embedded DisplayPort Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

eDP_TX3+

eDP_TX3-

eDP_TX2+

eDP_TX2-

eDP_TX1+

eDP_TX1-

eDP_TX0+

eDP_TX0-

A81

A82

A71

A72

A73

A74

A75

A76

eDP differential pairs. AC coupled off

module. eDP_TX2 and eDP_TX3 pairs are not supported on

conga-TC87.

eDP_VDD_EN A77 eDP power enable. O 3.3V PD 10k

eDP_BKLT_EN B79 eDP backlight enable. O 3.3V PD 10k

eDP_BKLT_CTRL B83 eDP backlight brightness control. O 3.3V

eDP_AUX+ A83 eDP AUX+. AC coupled off

module.

eDP_AUX- A84 eDP AUX-. AC coupled off

module.

eDP_HPD A87 Detection of Hot Plug / Unplug and notication of the link layer. I 3.3V

Table 14 SPI BIOS Flash Interface Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Carrier shall pull to SPI_POWER when

external SPI provided but not used.

SPI_MISO A92 Data in to module from carrier board SPI BIOS ash. I 3.3VSB

SPI_MOSI A95 Data out from module to carrier board SPI BIOS ash. O 3.3VSB

SPI_CLK A94 Clock from module to carrier board SPI BIOS ash. O 3.3VSB

SPI_POWER A91 Power source for carrier board SPI BIOS ash. SPI_POWER shall be used to power

SPI BIOS ash on the carrier only.

+ 3.3VSB

BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K

3.3VSB Carrier shall be left as no-connect.

BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K

3.3VSB Carrier shall be left as no-connect

Table 15 Miscellaneous Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

I2C_CK B33 General purpose I²C port clock output/input I/O 3.3V PU 2K2 3.3VSB

I2C_DAT B34 General purpose I²C port data I/O line I/O 3.3V PU 2K2 3.3VSB

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPEAKER is a boot strap signal

(see note below)

WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V PD 10K

FAN_PWNOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control

the fan’s RPM. O OD

3.3V PU 10K 3.3V

FAN_TACHIN B102 Fan tachometer input. I OD PU 10K 3.3V Requires a fan with a two pulse

output.

TPM_PP A96 Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip

has an internal pull-down. This signal is used to indicate Physical Presence to the

TPM.

I 3.3V Trusted Platform Module chip is

optional.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more

information refer to section 8.5 of this user’s guide.

Table 16 General Purpose I/O Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

GPO0 A93 General purpose output pins.

Shared with SD_CLK. Output from COM Express, input to SD O 3.3V SDIO interface is not supported on the conga-TC87

GPO1 B54 General purpose output pins.

Shared with SD_CMD. Output from COM Express, input to SD O 3.3V SDIO interface is not supported on the conga-TC87

GPO2 B57 General purpose output pins.

Shared with SD_WP. Output from COM Express, input to SD O 3.3V SDIO interface is not supported on the conga-TC87

GPO3 B63 General purpose output pins.

Shared with SD_CD. Output from COM Express, input to SD O 3.3V SDIO interface is not supported on the conga-TC87

GPI0 A54 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA0. Bidirectional signal I 3.3V PU 10K 3.3V SDIO interface is not supported on the conga-TC87

GPI1 A63 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA1. Bidirectional signal I 3.3V PU 10K 3.3V SDIO interface is not supported on the conga-TC87

GPI2 A67 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA2. Bidirectional signal I 3.3V PU 10K 3.3V SDIO interface is not supported on the conga-TC87

GPI3 A85 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA3. Bidirectional signal. I 3.3V PU 10K 3.3V SDIO interface is not supported on the conga-TC87

Table 17 Power and System Management Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

PWRBTN# B12 Power button to bring system out of S5 (soft off), active on rising edge. I 3.3VSB PU 10k 3.3VSB

SYS_RESET# B49 Reset button input. Active low input. Edge triggered.

System will not be held in hardware reset while this input is kept low. I 3.3VSB PU 10k 3.3VSB

CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module chipset and may result

from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below

the minimum specication, a watchdog timeout, or may be initiated by the module software.

O 3.3V PD 100k

PWR_OK B24 Power OK from main power supply. A high value indicates that the power is good. I 3.3V Set by resistor divider

to accept 3.3V.

SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB PU 10k 3.3VSB

SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3#

on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on

a typical ATX power supply.

O 3.3VSB

SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB Not supported

SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB

WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 1k 3.3VSB

WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or

mouse activity. I 3.3VSB PU 10k 3.3VSB

BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that the system

battery is low, or may be used to signal some other external power-management event. I 3.3VSB PU 10k 3.3VSB

THRM# B35 Input from off-module temp sensor indicating an over-temp situation. I 3.3V PU 10k 3.3V

THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V PU 10k 3.3V

SMB_CK B13 System Management Bus bidirectional clock line. I/O 3.3VSB PU 2k2 3.3VSB

SMB_DAT# B14 System Management Bus bidirectional data line. I/O OD

3.3VSB PU 2k2 3.3VSB

SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System

Management Interrupt) or to wake the system. I 3.3VSB PU 10k 3.3VSB

LID# A103 Lid button. Used by the ACPI operating system for a LID switch. I OD 3.3V PU 10k 3.3VSB

SLEEP B103 Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake it

up again. I OD 3.3V PU 10k 3.3VSB

Table 18 General Purpose Serial Interface Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SER0_TX A98 General purpose serial port transmitter O 3.3V

SER1_TX A101 General purpose serial port transmitter O 3.3V

SER0_RX A99 General purpose serial port receiver I 3.3V PU 50k 3.3V

SER1_RX A102 General purpose serial port receiver I 3.3V PU 50k 3.3V

Table 19 Power and GND Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VCC_12V A104-A109

B104-B109

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s)

shall be used. P

VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY

pins on the connector(s) shall be used. Only used for standby and suspend functions.

May be left unconnected if these functions are not used in the system design.

VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P

GND A1, A11, A21, A31, A41,

A51, A57, A60, A66,

A70, A80, A90, A100,

A110, B1, B11, B21,

B31, B41, B51, B60,

B70, B80, B90, B100,

B110

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to Carrier Board GND plane. P

8.2 A-B Connector Pinout

Table 20 Connector A-B Pinout

Pin Row A Pin Row B Pin Row A Pin Row B

A1 GND (FIXED) B1 GND (FIXED) A56 PCIE_TX4- (*) B56 PCIE_RX4- (*)

A2 GBE0_MDI3- B2 GBE0_ACT# A57 GND B57 GPO2

A3 GBE0_MDI3+ B3 LPC_FRAME# A58 PCIE_TX3+ B58 PCIE_RX3+

A4 GBE0_LINK100# B4 LPC_AD0 A59 PCIE_TX3- B59 PCIE_RX3-

A5 GBE0_LINK1000# B5 LPC_AD1 A60 GND (FIXED) B60 GND (FIXED)

A6 GBE0_MDI2- B6 LPC_AD2 A61 PCIE_TX2+ B61 PCIE_RX2+

A7 GBE0_MDI2+ B7 LPC_AD3 A62 PCIE_TX2- B62 PCIE_RX2-

A8 GBE0_LINK# B8 LPC_DRQ0# A63 GPI1 B63 GPO3

A9 GBE0_MDI1- B9 LPC_DRQ1# A64 PCIE_TX1+ B64 PCIE_RX1+

A10 GBE0_MDI1+ B10 LPC_CLK A65 PCIE_TX1- B65 PCIE_RX1-

A11 GND (FIXED) B11 GND (FIXED) A66 GND B66 WAKE0#

A12 GBE0_MDI0- B12 PWRBTN# A67 GPI2 B67 WAKE1#

A13 GBE0_MDI0+ B13 SMB_CK A68 PCIE_TX0+ B68 PCIE_RX0+

A14 GBE0_CTREF (*) B14 SMB_DAT A69 PCIE_TX0- B69 PCIE_RX0-

A15 SUS_S3# B15 SMB_ALERT# A70 GND (FIXED) B70 GND (FIXED)

A16 SATA0_TX+ B16 SATA1_TX+ A71 eDP_TX2+/LVDS_A0+ B71 LVDS_B0+

A17 SATA0_TX- B17 SATA1_TX- A72 eDP_TX2-/LVDS_A0- B72 LVDS_B0-

A18 SUS_S4# B18 SUS_STAT# A73 eDP_TX1+/LVDS_A1+ B73 LVDS_B1+

A19 SATA0_RX+ B19 SATA1_RX+ A74 eDP_TX1-/LVDS_A1- B74 LVDS_B1-

A20 SATA0_RX- B20 SATA1_RX- A75 eDP_TX0+/LVDS_A2+ B75 LVDS_B2+

A21 GND (FIXED) B21 GND (FIXED) A76 eDP_TX0-/LVDS_A2- B76 LVDS_B2-

A22 SATA2_TX+ B22 SATA3_TX+ A77 eDP/LVDS_VDD_EN B77 LVDS_B3+

A23 SATA2_TX- B23 SATA3_TX- A78 LVDS_A3+ B78 LVDS_B3-

A24 SUS_S5# B24 PWR_OK A79 LVDS_A3- B79 eDP/LVDS_BKLT_EN

A25 SATA2_RX+ B25 SATA3_RX+ A80 GND (FIXED) B80 GND (FIXED)

A26 SATA2_RX- B26 SATA3_RX- A81 eDP_TX3+/LVDS_A_CK+ B81 LVDS_B_CK+

A27 BATLOW# B27 WDT A82 eDP_TX3-/LVDS_A_CK- B82 LVDS_B_CK-

A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 A83 eDP_AUX+/LVDS_I2C_CK B83 eDP/LVDS_BKLT_CTRL

A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 A84 eDP_AUX-/LVDS_I2C_DAT B84 VCC_5V_SBY

A30 AC/HDA_RST# B30 AC/HDA_SDIN0 A85 GPI3 B85 VCC_5V_SBY

A31 GND (FIXED) B31 GND (FIXED) A86 RSVD B86 VCC_5V_SBY

A32 AC/HDA_BITCLK B32 SPKR A87 eDP_HPD B87 VCC_5V_SBY

A33 AC/HDA_SDOUT B33 I2C_CK A88 PCIE0_CK_REF+ B88 BIOS_DIS1#

A34 BIOS_DIS0# B34 I2C_DAT A89 PCIE0_CK_REF- B89 VGA_RED (*)

A35 THRMTRIP# B35 THRM# A90 GND (FIXED) B90 GND (FIXED)

A36 USB6- B36 USB7- A91 SPI_POWER B91 VGA_GRN (*)

A37 USB6+ B37 USB7+ A92 SPI_MISO B92 VGA_BLU (*)

Pin Row A Pin Row B Pin Row A Pin Row B

A38 USB_6_7_OC# B38 USB_4_5_OC# A93 GPO0 B93 VGA_HSYNC (*)

A39 USB4- B39 USB5- A94 SPI_CLK B94 VGA_VSYNC (*)

A40 USB4+ B40 USB5+ A95 SPI_MOSI B95 VGA_I2C_CK (*)

A41 GND (FIXED) B41 GND (FIXED) A96 TPM_PP B96 VGA_I2C_DAT (*)

A42 USB2- B42 USB3- A97 TYPE10# B97 SPI_CS#

A43 USB2+ B43 USB3+ A98 SER0_TX B98 RSVD

A44 USB_2_3_OC# B44 USB_0_1_OC# A99 SER0_RX B99 RSVD

A45 USB0- B45 USB1- A100 GND (FIXED) B100 GND (FIXED)

A46 USB0+ B46 USB1+ A101 SER1_TX B101 FAN_PWMOUT

A47 VCC_RTC B47 EXCD1_PERST# A102 SER1_RX B102 FAN_TACHIN

A48 EXCD0_PERST# B48 EXCD1_CPPE# A103 LID# B103 SLEEP#

A49 EXCD0_CPPE# B49 SYS_RESET# A104 VCC_12V B104 VCC_12V

A50 LPC_SERIRQ B50 CB_RESET# A105 VCC_12V B105 VCC_12V

A51 GND (FIXED) B51 GND (FIXED) A106 VCC_12V B106 VCC_12V

A52 PCIE_TX5+ (*) B52 PCIE_RX5+ (*) A107 VCC_12V B107 VCC_12V

A53 PCIE_TX5- (*) B53 PCIE_RX5- (*) A108 VCC_12V B108 VCC_12V

A54 GPI0 B54 GPO1 A109 VCC_12V B109 VCC_12V

A55 PCIE_TX4+ (*) B55 PCIE_RX4+ (*) A110 GND (FIXED) B110 GND (FIXED)

Note

The signals marked with asterisk symbol (*) are not supported on the conga TC87.

8.3 C-D Connector Signal Descriptions

Table 21 PCI Express Signal Descriptions (general purpose)

Signal Pin # Description I/O PU/PD Comment

PCIE_RX6+

PCIE_RX6-

C19

C20 PCI Express channel 6, Receive Input differential pair. I PCIE Not supported

PCIE_TX6+

PCIE_TX6-

D19

D20 PCI Express channel 6, Transmit Output differential pair. O PCIE Not supported

PCIE_RX7+

PCIE_RX7- C22

C23 PCI Express channel 7, Receive Input differential pair. I PCIE Not supported

PCIE_TX7+

PCIE_TX7- D22

D23 PCI Express channel 7, Transmit Output differential pair. O PCIE Not supported

Table 22 USB 3.0 Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

USB_SSRX0+ C4 Additional receive signal differential pairs for the Superspeed USB data path I

USB_SSRX0- C3 I

USB_SSTX0+ D4 Additional transmit signal differential pairs for the Superspeed USB data path O

USB_SSTX0- D3 O

USB_SSRX1+ C7 Additional receive signal differential pairs for the Superspeed USB data path I

USB_SSRX1- C6 I

USB_SSTX1+ D7 Additional transmit signal differential pairs for the Superspeed USB data path O

USB_SSTX1- D6 O

USB_SSRX2+ C10 Additional receive signal differential pairs for the Superspeed USB data path I Not supported.

USB_SSRX2- C9 I Not supported.

USB_SSTX2+ D10 Additional transmit signal differential pairs for the Superspeed USB data path O Not supported.

USB_SSTX2- D9 O Not supported.

USB_SSRX3+ C13 Additional receive signal differential pairs for the Superspeed USB data path I Not supported.

USB_SSRX3- C12 I Not supported.

USB_SSTX3+ D13 Additional transmit signal differential pairs for the Superspeed USB data path O Not supported.

USB_SSTX3- D12 O Not supported.

Table 23 PCI Express Signal Descriptions (x16 Graphics)

Signal Pin # Description I/O PU/PD Comment

PEG_RX0+

PEG_RX0-

PEG_RX1+

PEG_RX1-

PEG_RX2+

PEG_RX2-

PEG_RX3+

PEG_RX3-

PEG_RX4+

PEG_RX4-

PEG_RX5+

PEG_RX5-

PEG_RX6+

PEG_RX6-

PEG_RX7+

PEG_RX7-

PEG_RX8+

PEG_RX8-

PEG_RX9+

PEG_RX9-

PEG_RX10+

PEG_RX10-

PEG_RX11+

PEG_RX11-

PEG_RX12+

PEG_RX12-

PEG_RX13+

PEG_RX13-

PEG_RX14+

PEG_RX14-

PEG_RX15+

PEG_RX15-

C52

C53

C55

C56

C58

C59

C61

C62

C65

C66

C68

C69

C71

C72

C74

C75

C78

C79

C81

C82

C85

C86

C88

C89

C91

C92

C94

C95

C98

C99

C101

C102

PCI Express Graphics Receive Input differential pairs.

Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known

as PCIE_RX[16-31] + and -.

I PCIE Not supported.

Signal Pin # Description I/O PU/PD Comment

PEG_TX0+

PEG_TX0-

PEG_TX1+

PEG_TX1-

PEG_TX2+

PEG_TX2-

PEG_TX3+

PEG_TX3-

PEG_TX4+

PEG_TX4-

PEG_TX5+

PEG_TX5-

PEG_TX6+

PEG_TX6-

PEG_TX7+

PEG_TX7-

PEG_TX8+

PEG_TX8-

PEG_TX9+

PEG_TX9-

PEG_TX10+

PEG_TX10-

PEG_TX11+

PEG_TX11-

PEG_TX12+

PEG_TX12-

PEG_TX13+

PEG_TX13-

PEG_TX14+

PEG_TX14-

PEG_TX15+

PEG_TX15-

D52

D53

D55

D56

D58

D59

D61

D62

D65

D66

D68

D69

D71

D72

D74

D75

D78

D79

D81

D82

D85

D86

D88

D89

D91

D92

D94

D95

D98

D99

D101

D102

PCI Express Graphics Transmit Output differential pairs.

Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31

known as PCIE_TX[16-31] + and -.

O PCIE Not supported.

PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane

order. I PU 10k 3.3V Not supported.

Note

The PCI Express Graphics interface is not supported on the conga-TC87.

Table 24 DDI Signal Description

Signal Pin # Description I/O PU/PD Comment

DDI1_PAIR0+

DDI1_PAIR0- D26

D27 Multiplexed with DP1_LANE0+ and TMDS1_DATA2+.

Multiplexed with DP1_LANE0- and TMDS1_DATA2-. O PCIE

DDI1_PAIR1+

DDI1_PAIR1-

D29

D30 Multiplexed with DP1_LANE1+ and TMDS1_DATA1+.

Multiplexed with DP1_LANE1- and TMDS1_DATA1-. O PCIE

DDI1_PAIR2+

DDI1_PAIR2- D32

D33 Multiplexed with DP1_LANE2+ and TMDS1_DATA0+.

Multiplexed with DP1_LANE2- and TMDS1_DATA0-. O PCIE

DDI1_PAIR3+

DDI1_PAIR3- D36

D37 Multiplexed with DP1_LANE3+ and TMDS1_CLK+.

Multiplexed with DP1_LANE3- and TMDS1_CLK-. O PCIE

DDI1_PAIR4+

DDI1_PAIR4- C25

C26 Multiplexed with SDVO1_INT+.

Multiplexed with SDVO1_INT-. Not supported

DDI1_PAIR5+

DDI1_PAIR5-

C29

C30 Multiplexed with SDVO1_TVCLKIN+.

Multiplexed with SDVO1_TVCLKIN-. Not supported

DDI1_PAIR6+

DDI1_PAIR6- C15

C16 Multiplexed with SDVO1_FLDSTALL+.

Multiplexed with SDVO1_FLDSTALL-. Not supported

DDI1_HPD C24 Multiplexed with DP1_HPD and HDMI1_HPD. I 3.3V PD 1M

DDI1_CTRLCLK_AUX+ D15 Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK.

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high I/O PCIE

I/O OD 3.3V

PD100k

DDI1_CTRLDATA_AUX- D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.

DP AUX- function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I/O PCIE

I/O OD 3.3V

PU 100k

3.3V DDI1_CTRLDATA_AUX- is a boot

strap signal (see not below).

DDI enable strap already populated.

DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-.

This pin shall have a IM pull-down to logic ground on the module. If this input

is oating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the

AUX pair contains the CTRLCLK and CTRLDATA signals.

I 3.3V PD 1M

DDI2_PAIR0+

DDI2_PAIR0-

D39

D40 Multiplexed with DP2_LANE0+ and TMDS2_DATA2+.

Multiplexed with DP2_LANE0- and TMDS2_DATA2-. O PCIE

DDI2_PAIR1+

DDI2_PAIR1- D42

D43 Multiplexed with DP2_LANE1+ and TMDS2_DATA1+.

Multiplexed with DP2_LANE1- and TMDS2_DATA1-. O PCIE

DDI2_PAIR2+

DDI2_PAIR2- D46

D47 Multiplexed with DP2_LANE2+ and TMDS2_DATA0+.

Multiplexed with DP2_LANE2- and TMDS2_DATA0-. O PCIE

DDI2_PAIR3+

DDI2_PAIR3-

D49

D50 Multiplexed with DP2_LANE3+ and TMDS2_CLK+.

Multiplexed with DP2_LANE3- and TMDS2_CLK-. O PCIE

DDI2_HPD D44 Multiplexed with DP2_HPD and HDMI2_HPD. I 3.3V PD 1M

DDI2_CTRLCLK_AUX+ C32 Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK.

DP AUX+ function if DDI2_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high I/O PCIE

I/O OD 3.3V

PD 100k

DDI2_CTRLDATA_AUX- C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.

DP AUX- function if DDI2_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high. I/O PCIE

I/O OD 3.3V

PU 100k

3.3V DDI2_CTRLCLK_AUX- is a boot strap

signal (see note below).

DDI enable strap already populated.

Signal Pin # Description I/O PU/PD Comment

DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-.

This pin shall have a IM pull-down to logic ground on the module. If this input

is oating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the

AUX pair contains the CTRLCLK and CTRLDATA signals

I 3.3V

DDI3_PAIR0+

DDI3_PAIR0-

C39

C40 Multiplexed with DP3_LANE0+ and TMDS3_DATA2+.

Multiplexed with DP3_LANE0- and TMDS3_DATA2-. O PCIE Not supported

DDI3_PAIR1+

DDI3_PAIR1- C42

C43 Multiplexed with DP3_LANE1+ and TMDS3_DATA1+.

Multiplexed with DP3_LANE1- and TMDS3_DATA1-. O PCIE Not supported

DDI3_PAIR2+

DDI3_PAIR2- C46

C47 Multiplexed with DP3_LANE2+ and TMDS3_DATA0+.

Multiplexed with DP3_LANE2- and TMDS3_DATA0-. O PCIE Not supported

DDI3_PAIR3+

DDI3_PAIR3-

C49

C50 Multiplexed with DP3_LANE3+ and TMDS3_CLK+.

Multiplexed with DP3_LANE3- and TMDS3_CLK-. O PCIE Not supported

DDI3_HPD C44 Multiplexed with DP3_HPD and HDMI3_HPD. I 3.3V Not supported

DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK.

DP AUX+ function if DDI3_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I/O PCIE

I/O OD 3.3V

Not supported

DDI3_CTRLDATA_AUX- C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.

DP AUX- function if DDI3_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high. I/O PCIE

I/O OD 3.3V

Not supported

DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-.

This pin shall have a IM pull-down to logic ground on the module. If this input

is oating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the

AUX pair contains the CTRLCLK and CTRLDATA signals

I 3.3V Not supported

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more

information refer to section 8.5 of this user’s guide.

The Digital Display Interface (DDI) signals are multiplexed with HDMI and DisplayPort (DP). The signals for these interfaces are routed to the

DDI interface of the COM Express connector. Refer to the HDMI and DisplayPort signal description tables in this section for information about

the signals routed to the DDI interface of the COM Express connector.

Table 25 HDMI Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

TMDS1_CLK +

TMDS1_CLK - D36

D37 HDMI/DVI TMDS Clock output differential pair.

Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-. O PCIE

TMDS1_DATA0+

TMDS1_DATA0- D32

D33 HDMI/DVI TMDS differential pair.

Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-. O PCIE

TMDS1_DATA1+

TMDS1_DATA1-

D29

D30 HDMI/DVI TMDS differential pair.

Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.. O PCIE

TMDS1_DATA2+

TMDS1_DATA2- D26

D27 HDMI/DVI TMDS differential pair.

Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-. O PCIE

HDMI1_HPD C24 HDMI/DVI Hot-plug detect.

Multiplexed with DDI1_HPD. I PCIE PD 1M

HDMI1_CTRLCLK D15 HDMI/DVI I2C Control Clock

Multiplexed with DDI1_CTRLCLK_AUX+ I/O OD 3.3V PD 100k

HDMI1_CTRLDATA D16 HDMI/DVI I2C Control Data

Multiplexed with DDI1_CTRLDATA_AUX- I/O OD 3.3V PU 100k

3.3V HDMI1_CTRLDATA is a boot strap signal (see note below).

HDMI enable strap already populated

TMDS2_CLK +

TMDS2_CLK -

D49

D50 HDMI/DVI TMDS Clock output differential pair..

Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-. O PCIE

TMDS2_DATA0+

TMDS2_DATA0- D46

D47 HDMI/DVI TMDS differential pair.

Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-. O PCIE

TMDS2_DATA1+

TMDS2_DATA1- D42

D43 HDMI/DVI TMDS differential pair.

Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-. O PCIE

TMDS2_DATA2+

TMDS2_DATA2-

D39

D40 HDMI/DVI TMDS differential pair.

Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-.. O PCIE

HDMI2_HPD D44 HDMI/DVI Hot-plug detect.

Multiplexed with DDI2_HPD I PCIE PD 1M

HDMI2_CTRLCLK C32 HDMI/DVI I2C Control Clock

Multiplexed with DDI2_CTRLCLK_AUX+ I/O OD 3.3V PD 100k

HDM12_CTRLDATA C33 HDMI/DVI I2C Control Data

Multiplexed with DDI2_CTRLDATA_AUX- I/O OD 3.3V PU 100k

3.3V HDMI2_CTRLDATA is a boot strap signal (see note below).

HDMI enable strap is already populated.

TMDS3_CLK +

TMDS3_CLK -

C49

C50 HDMI/DVI TMDS Clock output differential pair..

Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-. O PCIE Not supported

TMDS3_DATA0+

TMDS3_DATA0- C46

C47 HDMI/DVI TMDS differential pair.

Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-. O PCIE Not supported

TMDS3_DATA1+

TMDS3_DATA1- C42

C43 HDMI/DVI TMDS differential pair.

Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-.. O PCIE Not supported

TMDS3_DATA2+

TMDS3_DATA2-

C39

C40 HDMI/DVI TMDS differential pair.

Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-. O PCIE Not supported

HDMI3_HPD C44 HDMI/DVI Hot-plug detect.

Multiplexed with DDI3_HPD. I PCIE Not supported

HDMI3_CTRLCLK C36 HDMI/DVI I2C Control Clock

Multiplexed with DDI3_CTRLCLK_AUX+ I/O OD 3.3V Not supported

Signal Pin # Description I/O PU/PD Comment

HDMI3_CTRLDATA C37 HDMI/DVI I2C Control Data

Multiplexed with DDI3_CTRLDATA_AUX- I/O OD 3.3V Not supported

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more

information refer to section 8.5 of this user’s guide.

Table 26 DisplayPort (DP) Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

DP1_LANE3+

DP1_LANE3- D36

D37 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.

O PCIE

DP1_LANE2+

DP1_LANE2- D32

D33 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.

O PCIE

DP1_LANE1+

DP1_LANE1-

D29

D30 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.

O PCIE

DP1_LANE0+

DP1_LANE0- D26

D27 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.

O PCIE

DP1_HPD C24 Detection of Hot Plug / Unplug and notication of the link layer.

Multiplexed with DDI1_HPD. I 3.3V PD 1M

DP1_AUX+ D15 Half-duplex bi-directional AUX channel for services such as link

conguration or maintenance and EDID access.

I/O PCIE PD 100k

DP1_AUX- D16 Half-duplex bi-directional AUX channel for services such as link

conguration or maintenance and EDID access.

I/O PCIE PU 100k

3.3V DP1_AUX- is a boot strap signal (see note below).

DP enable strap is already populated.

DP2_LANE3+

DP2_LANE3-

D49

D50 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-

O PCIE

DP2_LANE2+

DP2_LANE2- D46

D47 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-

O PCIE

DP2_LANE1+

DP2_LANE1- D42

D43 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-

O PCIE

DP2_LANE0+

DP2_LANE0-

D39

D40 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0-

O PCIE

Signal Pin # Description I/O PU/PD Comment

DP2_HPD D44 Detection of Hot Plug / Unplug and notication of the link layer.

Multiplexed with DDI2_HPD. I 3.3V PD 1M

DP2_AUX+ C32 Half-duplex bi-directional AUX channel for services such as link

conguration or maintenance and EDID access.

I/O PCIE PD 100k

DP2_AUX- C33 Half-duplex bi-directional AUX channel for services such as link

conguration or maintenance and EDID access.

I/O PCIE PU 100k

3.3V DP2_AUX- is a boot strap signal (see note below).

DP enable strap already populated.

DP3_LANE3+

DP3_LANE3-

C49

C50 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.

O PCIE Not supported

DP3_LANE2+

DP3_LANE2- C46

C47 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.

O PCIE Not supported

DP3_LANE1+

DP3_LANE1- C42

C43 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-.

O PCIE Not supported

DP3_LANE0+

DP3_LANE0-

C39

C40 Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.

O PCIE Not supported

DP3_HPD C44 Detection of Hot Plug / Unplug and notication of the link layer.

Multiplexed with DDI3_HPD. I 3.3V Not supported

DP3_AUX+ C36 Half-duplex bi-directional AUX channel for services such as link

conguration or maintenance and EDID access.

I/O PCIE Not supported

DP3_AUX- C37 Half-duplex bi-directional AUX channel for services such as link

conguration or maintenance and EDID access.

I/O PCIE Not supported

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more

information refer to section 8.5 of this user’s guide.

Table 27 Module Type Denition Signal Description

Signal Pin # Description I/O Comment

TYPE0#

TYPE1#

TYPE2#

C54

C57

D57

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on

the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X). PDS TYPE[0:2]# signals are

available on all modules

following the Type 2-6

Pinout standard.

The conga-TC87 is based

on the COM Express Type

6 pinout therefore the pins

0 and 1 are not connected

and pin 2 is connected to

GND.

TYPE2# TYPE1# TYPE0#

GND

Pinout Type 1

Pinout Type 2

Pinout Type 3 (no IDE)

Pinout Type 4 (no PCI)

Pinout Type 5 (no IDE, no PCI)

Pinout Type 6 (no IDE, no PCI)

The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off

(e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The

Carrier Board logic may also implement a fault indicator such as an LED.

TYPE10# A97 Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev. 1.0/2.0

module is installed. PDS Not connected to indicate

“Pinout R2.0”.

TYPE10#

12V

Pinout R2.0

Pinout Type 10 pull down to ground with 4.7k resistor

Pinout R1.0

This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin

is dened as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0

module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor.

Table 28 Power and GND Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VCC_12V C104-C109

D104-D109

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used. P

GND C1, C2, C5, C8, C11,

C14, C21, C31, C41,

C51, C60, C70,C73,

C76, C80, C84, C87,

C90, C93, C96, C100,

C103, C110, D1, D2,

D5, D8, D11, D14,

D21, D31, D41, D51,

D60, D67, D70, D73,

D76, D80, D84, D87,

D90, D93, D96, D100,

D103, D110

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to carrier board GND plane. P

8.4 C-D Connector Pinout

Table 29 Connector C-D Pinout

Pin Row C Pin Row D Pin Row C Pin Row D

C1 GND (FIXED) D1 GND (FIXED) C56 PEG_RX1- (*) D56 PEG_TX1- (*)

C2 GND D2 GND C57 TYPE1# D57 TYPE2#

C3 USB_SSRX0- D3 USB_SSTX0- C58 PEG_RX2+ (*) D58 PEG_TX2+ (*)

C4 USB_SSRX0+ D4 USB_SSTX0+ C59 PEG_RX2- (*) D59 PEG_TX2- (*)

C5 GND D5 GND C60 GND (FIXED) D60 GND (FIXED)

C6 USB_SSRX1- D6 USB_SSTX1- C61 PEG_RX3+ (*) D61 PEG_TX3+ (*)

C7 USB_SSRX1+ D7 USB_SSTX1+ C62 PEG_RX3- (*) D62 PEG_TX3- (*)

C8 GND D8 GND C63 RSVD D63 DDPC_CTRLCLK

C9 USB_SSRX2- (*) D9 USB_SSTX2- (*) C64 RSVD D64 DDPC_CTRLDATA

C10 USB_SSRX2+ (*) D10 USB_SSTX2+ (*) C65 PEG_RX4+ (*) D65 PEG_TX4+ (*)

C11 GND (FIXED) D11 GND (FIXED) C66 PEG_RX4- (*) D66 PEG_TX4- (*)

C12 USB_SSRX3- (*) D12 USB_SSTX3- (*) C67 RSVD D67 GND

C13 USB_SSRX3+ (*) D13 USB_SSTX3+ (*) C68 PEG_RX5+ (*) D68 PEG_TX5+ (*)

C14 GND D14 GND C69 PEG_RX5- (*) D69 PEG_TX5- (*)

C15 DDI1_PAIR6+ (*) D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED) D70 GND (FIXED)

C16 DDI1_PAIR6- (*) D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+ (*) D71 PEG_TX6+ (*)

C17 RSVD D17 RSVD C72 PEG_RX6- (*) D72 PEG_TX6- (*)

C18 RSVD D18 RSVD C73 GND D73 GND

C19 PCIE_RX6+ (*) D19 PCIE_TX6+ (*) C74 PEG_RX7+ (*) D74 PEG_TX7+ (*)

C20 PCIE_RX6- (*) D20 PCIE_TX6- (*) C75 PEG_RX7- (*) D75 PEG_TX7- (*)

C21 GND (FIXED) D21 GND (FIXED) C76 GND D76 GND

C22 PCIE_RX7+ (*) D22 PCIE_TX7+ (*) C77 RSVD D77 RSVD

C23 PCIE_RX7- (*) D23 PCIE_TX7- (*) C78 PEG_RX8+ (*) D78 PEG_TX8+ (*)

C24 DDI1_HPD D24 RSVD C79 PEG_RX8- (*) D79 PEG_TX8- (*)

C25 DDI1_PAIR4+ (*) D25 RSVD C80 GND (FIXED) D80 GND (FIXED)

C26 DDI1_PAIR4- (*) D26 DDI1_PAIR0+ C81 PEG_RX9+ (*) D81 PEG_TX9+ (*)

C27 RSVD D27 DDI1_PAIR0- C82 PEG_RX9- (*) D82 PEG_TX9- (*)

C28 RSVD D28 RSVD C83 RSVD D83 RSVD

C29 DDI1_PAIR5+ (*) D29 DDI1_PAIR1+ C84 GND D84 GND

C30 DDI1_PAIR5- (*) D30 DDI1_PAIR1- C85 PEG_RX10+ (*) D85 PEG_TX10+ (*)

C31 GND (FIXED) D31 GND (FIXED) C86 PEG_RX10- (*) D86 PEG_TX10- (*)

C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+ C87 GND D87 GND

C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2- C88 PEG_RX11+ (*) D88 PEG_TX11+ (*)

C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL C89 PEG_RX11- (*) D89 PEG_TX11- (*)

C35 RSVD D35 RSVD C90 GND (FIXED) D90 GND (FIXED)

C36 DDI3_CTRLCLK_AUX+ (*) D36 DDI1_PAIR3+ C91 PEG_RX12+ (*) D91 PEG_TX12+ (*)

C37 DDI3_CTRLDATA_AUX- (*) D37 DDI1_PAIR3- C92 PEG_RX12- (*) D92 PEG_TX12- (*)

Pin Row C Pin Row D Pin Row C Pin Row D

C38 DDI3_DDC_AUX_SEL (*) D38 RSVD C93 GND D93 GND

C39 DDI3_PAIR0+ (*) D39 DDI2_PAIR0+ C94 PEG_RX13+ (*) D94 PEG_TX13+ (*)

C40 DDI3_PAIR0- (*) D40 DDI2_PAIR0- C95 PEG_RX13- (*) D95 PEG_TX13- (*)

C41 GND (FIXED) D41 GND (FIXED) C96 GND D96 GND

C42 DDI3_PAIR1+ (*) D42 DDI2_PAIR1+ C97 RVSD D97 RSVD

C43 DDI3_PAIR1- (*) D43 DDI2_PAIR1- C98 PEG_RX14+ (*) D98 PEG_TX14+ (*)

C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14- (*) D99 PEG_TX14- (*)

C45 RSVD D45 RSVD C100 GND (FIXED) D100 GND (FIXED)

C46 DDI3_PAIR2+ (*) D46 DDI2_PAIR2+ C101 PEG_RX15+ (*) D101 PEG_TX15+ (*)

C47 DDI3_PAIR2- (*) D47 DDI2_PAIR2- C102 PEG_RX15- (*) D102 PEG_TX15- (*)

C48 RSVD D48 RSVD C103 GND D103 GND

C49 DDI3_PAIR3+ (*) D49 DDI2_PAIR3+ C104 VCC_12V D104 VCC_12V

C50 DDI3_PAIR3- (*) D50 DDI2_PAIR3- C105 VCC_12V D105 VCC_12V

C51 GND (FIXED) D51 GND (FIXED) C106 VCC_12V D106 VCC_12V

C52 PEG_RX0+ (*) D52 PEG_TX0+ (*) C107 VCC_12V D107 VCC_12V

C53 PEG_RX0- (*) D53 PEG_TX0- (*) C108 VCC_12V D108 VCC_12V

C54 TYPE0# D54 PEG_LANE_RV# (*) C109 VCC_12V D109 VCC_12V

C55 PEG_RX1+ (*) D55 PEG_TX1+ (*) C110 GND (FIXED) D110 GND (FIXED)

Note

The signals marked with an asterisk symbol (*) are not supported on the conga-TC87.

8.5 Boot Strap Signals

Table 30 Boot Strap Signal Descriptions

Signal Pin # Description of Boot Strap Signal I/O PU/PD Comment

AC/HDA_SDOUT A33 High Denition Audio Serial Data Out: This signal is the serial TDM data

output to the codec(s). This serial output is double-pumped for a bit rate of 48

Mb/s for High Denition Audio.

O 3.3VSB PU 1K

3.3VSB AC/HDA_SDOUT is a boot strap

signal (see caution statement below)

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPKR is a boot strap signal (see

caution statement below)

DDI1_CTRLDATA_AUX-

DP1_AUX-

HDMI_CTRLDATA

D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.

DP AUX- function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high. I/O PCIE

I/O OD 3.3V

PU100k

3.3V DDI1_CTRLDATA_AUX- is a boot

strap signal (see not below).

DDI2_CTRLDATA_AUX-

DP2_AUX-

HDM2_CTRLDATA

C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.

DP AUX- function if DDI2_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high. I/O PCIE

I/O OD 3.3V

PU100k

3.3V DDI2_CTRLDATA_AUX- is a boot

strap signal (see not below).

Caution

The signals listed in the table above are used as chipset conguration straps during system reset. In this condition (during reset), they are

inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors

that are located on the module. No external DC loads or external pull-up or pull-down resistors should change the conguration of the signals

listed in the above table. External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or

cause irreparable damage to the module.

9 System Resources

9.1 I/O Address Assignment

The I/O address assignment of the conga-TC87 module is functionally identical with a standard PC/AT.

Note

The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not

consume I/O resources in that area.

9.1.1 LPC Bus

On the conga-TC87, the PCI Express Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to

the internal PCI Bus not the LPC Bus. Only specied I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS, the following

I/O address ranges are sent to the LPC Bus:

2Eh – 2Fh

4Eh – 4Fh

60h, 64h

A00h – BFFh

C00h – CFFh (always used internally)

Parts of these ranges are not available if a Super I/O is used on the carrier board. If a Super I/O is not implemented on the carrier board,

then these ranges are available for customer use. If you require additional LPC Bus resources other than those mentioned above, or more

information about this subject, contact congatec technical support for assistance.

9.2 PCI Conguration Space Map

Table 31 PCI Conguration Space Map

Bus Number (hex) Device Number (hex) Function Number (hex) Description

00h 00h 00h Host Bridge

00h 02h 00h Graphics

00h 03h 00h Intel High Denition Audio controller

00h 14h 00h XHCI Host Controller

00h( Note1) 16h 00h Management Engine (ME) Interface 1

00h( Note1) 16h 01h Intel ME Interface 2

00h( Note1) 16h 02h ME IDE Redirection (IDE-R) Interface

00h( Note1) 16h 03h ME KT (Remote Keyboard and Text)

00h 19h 00h Onboard Gigabit LAN Controller

00h (Note2) 1Ch 00h PCI Express Root Port 0

00h (Note2) 1Ch 01h PCI Express Root Port 1

00h (Note2) 1Ch 02h PCI Express Root Port 2

00h (Note2) 1Ch 03h PCI Express Root Port 3

00h 1Dh 00h EHCI Host Controller

00h 1Fh 00h PCI to LPC Bridge

00h 1Fh 02h Serial ATA Controller

00h 1Fh 03h SMBus Host Controller

00h 1Fh 06h Thermal Subsystem

01h (Note3) 00h 00h PCI Express Port 0

02h (Note3) 00h 00h PCI Express Port 1

03h (Note3) 00h 00h PCI Express Port 2

04h (Note3) 00h 00h PCI Express Port 3

Note

1. In the standard conguration, the Intel Management Engine (ME) related devices are partly present or not present at all.

2. The PCI Express Ports are visible only if a device is attached behind them to the PCI Express Slot on the carrier board.

3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus

numbers will change based on actual hardware conguration.

9.3 PCI Interrupt Routing Map

Table 32 PCI Interrupt Routing Map

PIRQ PCI BUS

INT Line ¹ APIC

Mode IRQ Graphic HDA XHCI EHCI SM Bus +

Thermal LAN SATA PCI-EX

Root Port

PCI-EX

Root Port

PCI-EX

Root Port 2 PCI-EX

Root

Port 3

PCI-EX

Port 0 PCI-EX

Port 1 PCI-EX

Port 2 PCI-EX

Port 3

A INTA 16 x x x x x 2x 5x 4x 3

B INTB 17 x x 3x 2x 5x 4

C INTC 18 x x x 4x 3x ² x 5

D INTD 19 x x x 5x 4x ³ x 2

E 20 x

F 21

G 22

H 23 x

Note

1 These interrupt lines are virtual (message based).

2 Interrupt used by single function PCI Express devices (INTA).

3 Interrupt used by multifunction PCI Express devices (INTB).

4 Interrupt used by multifunction PCI Express devices (INTC).

5 Interrupt used by multifunction PCI Express devices (INTD).

9.4 I²C Bus

There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

9.5 SM Bus

System Management (SM) bus signals are connected to the Intel® 8 Series PCH-LP and the SM bus is not intended to be used by off-board

non-system management devices. For more information about this subject, contact congatec technical support.

10 BIOS Setup Description

TBD

11 Industry Specications

The list below provides links to industry specications that apply to congatec AG modules.

Specication Link

Low Pin Count Interface Specication, Revision 1.0 (LPC) http://developer.intel.com/design/chipsets/industry/lpc.htm

Universal Serial Bus (USB) Specication, Revision 2.0 http://www.usb.org/home

PCI Specication, Revision 2.3 http://www.pcisig.com/specications

Serial ATA Specication, Revision 3.0 http://www.serialata.org

PICMG® COM Express Module™ Base Specication http://www.picmg.org/

PCI Express Base Specication, Revision 2.0 http://www.pcisig.com/specications

Conga TU87 User's Guide User

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