ATmega48A, ATmega48PA, ATmega88A, ATmega88PA, ATmega168A, ATmega1688PA, ATmega328, ATmega328P Datasheet YMFC 3D ATmega328 Manual

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Atmel 8-bit Microcontroller with 4/8/16/32KBytes
In-System Programmable Flash
ATmega48A; ATmega48PA; ATmega88A; ATmega88PA;
ATmega168A; ATmega168PA; ATmega328; ATmega328P

Features
•
•

•

•

•

•

•
•
•
•
•

High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
– 4/8/16/32KBytes of In-System Self-Programmable Flash program memory
– 256/512/512/1KBytes EEPROM
– 512/1K/1K/2KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/100 years at 25C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
Atmel® QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix® acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V
Temperature Range:
– -40C to 85C
Speed Grade:
– 0 - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25C
– Active Mode: 0.2mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.75µA (Including 32kHz RTC)

8271G–AVR–02/2013

1. Pin Configurations
Figure 1-1.

Pinout ATmega48A/PA/88A/PA/168A/PA/328/P
28 PDIP

PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)

32 TQFP Top View

32
31
30
29
28
27
26
25

(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0

24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8

PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)

(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4

9
10
11
12
13
14
15
16

PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
32
31
30
29
28
27
26
25

PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7

PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)

Table 1-1.

(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4

NOTE: Bottom pad should be soldered to ground.

24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8

PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)

9
10
11
12
13
14
15
16

8
9
10
11
12
13
14

1
2
3
4
5
6
7

PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)

32 MLF Top View

28 MLF Top View

(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5

28
27
26
25
24
23
22
21
20
19
18
17
16
15

NOTE: Bottom pad should be soldered to ground.

(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4

(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7

1
2
3
4
5
6
7
8
9
10
11
12
13
14

32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA
1

2

3

4

5

6

A

PD2

PD1

PC6

PC4

PC2

PC1

B

PD3

PD4

PD0

PC5

PC3

PC0

C

GND

GND

ADC7

GND

D

VDD

VDD

AREF

ADC6

E

PB6

PD6

PB0

PB2

AVDD

PB5

F

PB7

PD5

PD7

PB1

PB3

PB4

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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1.1

Pin Descriptions

1.1.1

VCC
Digital supply voltage.

1.1.2

GND
Ground.

1.1.3

Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and
input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as TOSC2...1 input for the
Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 83 and ”System
Clock and Clock Options” on page 26.

1.1.4

Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a
reset condition becomes active, even if the clock is not running.

1.1.5

PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the
minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in
Table 29-16 on page 312. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 86.|

1.1.6

Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 89.

1.1.7

AVCC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that
PC6...4 use digital supply voltage, VCC.

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1.1.8

AREF
AREF is the analog reference pin for the A/D Converter.

1.1.9

ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered
from the analog supply and serve as 10-bit ADC channels.

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2. Overview
The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.

Block Diagram
VCC

Block Diagram
GND

Figure 2-1.

Watchdog
Timer
Watchdog
Oscillator

Oscillator
Circuits /
Clock
Generation

Power
Supervision
POR / BOD &
RESET

debugWIRE

Flash

SRAM

PROGRAM
LOGIC

CPU
EEPROM
AVCC
AREF
GND

DATABUS

2.1

8bit T/C 0

16bit T/C 1

A/D Conv.

8bit T/C 2

Analog
Comp.

Internal
Bandgap

USART 0

SPI

TWI

PORT D (8)

PORT B (8)

PORT C (7)

2

6

RESET
XTAL[1..2]
PD[0..7]

PB[0..7]

PC[0..6]

ADC[6..7]

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.

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The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes SRAM,
23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an
SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog
Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.
Atmel® offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into
AVR® microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for unambiguous
detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your
own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use
any interface to download the application program in the Application Flash memory. Software in the Boot Flash
section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega48A/PA/88A/PA/168A/PA/328/P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and
Evaluation kits.

2.2

Comparison Between Processors
The ATmega48A/PA/88A/PA/168A/PA/328/P differ only in memory sizes, boot loader support, and interrupt vector
sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the devices.
Table 2-1.

Memory Size Summary

Device

Flash

EEPROM

RAM

Interrupt Vector Size

ATmega48A

4KBytes

256Bytes

512Bytes

1 instruction word/vector

ATmega48PA

4KBytes

256Bytes

512Bytes

1 instruction word/vector

ATmega88A

8KBytes

512Bytes

1KBytes

1 instruction word/vector

ATmega88PA

8KBytes

512Bytes

1KBytes

1 instruction word/vector

ATmega168A

16KBytes

512Bytes

1KBytes

2 instruction words/vector

ATmega168PA

16KBytes

512Bytes

1KBytes

2 instruction words/vector

ATmega328

32KBytes

1KBytes

2KBytes

2 instruction words/vector

ATmega328P

32KBytes

1KBytes

2KBytes

2 instruction words/vector

ATmega48A/PA/88A/PA/168A/PA/328/P support a real Read-While-Write Self-Programming mechanism. There is
a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega 48A/48PA there
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is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the
entire Flash

3. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note:

1.

4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.

5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.

6. Capacitive Touch Sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR® microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel QMatrix® acquisition
methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library
User Guide - also available for download from Atmel website.

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7. AVR CPU Core
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
Figure 7-1.

Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash
Program
Memory

Program
Counter

Status
and Control

32 x 8
General
Purpose
Registrers

Instruction
Decoder

Control Lines

Indirect Addressing

Instruction
Register

Direct Addressing

7.1

Interrupt
Unit
SPI
Unit
Watchdog
Timer

ALU

Analog
Comparator

I/O Module1

Data
SRAM

I/O Module 2

I/O Module n
EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper-

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ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P has Extended I/O space from 0x60
- 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

7.2

ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

7.3

Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.

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7.3.1

SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
Bit

7

6

5

4

3

2

1

0

0x3F (0x5F)

I

T

H

S

V

N

Z

C

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

SREG

• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic.
See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.

7.4

General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input

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• One 16-bit output operand and one 16-bit result input
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7-2.

AVR CPU General Purpose Working Registers
7

0

Addr.

R0

0x00

R1

0x01

R2

0x02

…
R13

0x0D

General

R14

0x0E

Purpose

R15

0x0F

Working

R16

0x10

Registers

R17

0x11

…
R26

0x1A

X-register Low Byte

R27

0x1B

X-register High Byte

R28

0x1C

Y-register Low Byte

R29

0x1D

Y-register High Byte

R30

0x1E

Z-register Low Byte

R31

0x1F

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
7.4.1

The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 7-3.
Figure 7-3.

The X-, Y-, and Z-registers
15

X-register

XH

7

XL
0

R27 (0x1B)

15
Y-register

YH

7

YL
0

0

7

0

R28 (0x1C)

15

ZH

7

0

R31 (0x1F)

0

R26 (0x1A)

R29 (0x1D)

Z-register

0

7

ZL
7

0
0

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

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7.5

Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory
locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data
SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease
the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be
set to point above start of the SRAM, see Table 8-3 on page 18.
See Table 7-1 for Stack Pointer details.
Table 7-1.

Stack Pointer instructions

Instruction

Stack pointer

Description

PUSH

Decremented by 1

Data is pushed onto the stack

CALL
ICALL
RCALL

Decremented by 2

Return address is pushed onto the stack with a subroutine call or
interrupt

POP

Incremented by 1

Data is popped from the stack

RET
RETI

Incremented by 2

Return address is popped from the stack with return from
subroutine or return from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
7.5.1

SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit

15

14

13

12

11

10

9

8

0x3E (0x5E)

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPH

0x3D (0x5D)

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

7

6

5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

RAMEND

Read/Write

Initial Value

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7.6

Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 7-4.

The Parallel Instruction Fetches and Instruction Executions
T1

T2

T3

T4

clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch

Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-5.

Single Cycle ALU Operation
T1

T2

T3

T4

clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back

7.7

Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits
BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory Programming” on page 285 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in ”Interrupts” on page 57. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 57 for more
information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 269.

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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG
cli

; store SREG value

; disable interrupts during timed sequence

sbi EECR, EEMPE

; start EEPROM write

sbi EECR, EEPE
out SREG, r16

; restore SREG value (I-bit)

C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<
...

...

; Set Stack Pointer to top of RAM

xxx

...

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12.2

Interrupt Vectors in ATmega88A and ATmega88PA

Table 12-2.

Reset and Interrupt Vectors in ATmega88A and ATmega88PA

Vector No.

Program
Address(2)

Source

Interrupt Definition

1

0x000(1)

RESET

External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2

0x001

INT0

External Interrupt Request 0

3

0x002

INT1

External Interrupt Request 1

4

0x003

PCINT0

Pin Change Interrupt Request 0

5

0x004

PCINT1

Pin Change Interrupt Request 1

6

0x005

PCINT2

Pin Change Interrupt Request 2

7

0x006

WDT

Watchdog Time-out Interrupt

8

0x007

TIMER2 COMPA

Timer/Counter2 Compare Match A

9

0x008

TIMER2 COMPB

Timer/Counter2 Compare Match B

10

0x009

TIMER2 OVF

Timer/Counter2 Overflow

11

0x00A

TIMER1 CAPT

Timer/Counter1 Capture Event

12

0x00B

TIMER1 COMPA

Timer/Counter1 Compare Match A

13

0x00C

TIMER1 COMPB

Timer/Coutner1 Compare Match B

14

0x00D

TIMER1 OVF

Timer/Counter1 Overflow

15

0x00E

TIMER0 COMPA

Timer/Counter0 Compare Match A

16

0x00F

TIMER0 COMPB

Timer/Counter0 Compare Match B

17

0x010

TIMER0 OVF

Timer/Counter0 Overflow

18

0x011

SPI, STC

SPI Serial Transfer Complete

19

0x012

USART, RX

USART Rx Complete

20

0x013

USART, UDRE

USART, Data Register Empty

21

0x014

USART, TX

USART, Tx Complete

22

0x015

ADC

ADC Conversion Complete

23

0x016

EE READY

EEPROM Ready

24

0x017

ANALOG COMP

Analog Comparator

25

0x018

TWI

2-wire Serial Interface

26

0x019

SPM READY

Store Program Memory Ready

Notes:

1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 269.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of
each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 12-3 on page 60 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application
section while the Interrupt Vectors are in the Boot section or vice versa.

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Table 12-3.

Reset and Interrupt Vectors Placement in ATmega88A and ATmega88PA(1)

BOOTRST

IVSEL

1

Note:

Reset Address

Interrupt Vectors Start Address

0

0x000

0x001

1

1

0x000

Boot Reset Address + 0x001

0

0

Boot Reset Address

0x001

0

1

Boot Reset Address

Boot Reset Address + 0x001

1. The Boot Reset Address is shown in Table 27-7 on page 280. For the BOOTRST Fuse “1” means unprogrammed
while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is:
Address Labels Code

Comments

0x000

rjmp

RESET

; Reset Handler

0x001

rjmp

EXT_INT0

; IRQ0 Handler

0x002

rjmp

EXT_INT1

; IRQ1 Handler

0x003

rjmp

PCINT0

; PCINT0 Handler

0x004

rjmp

PCINT1

; PCINT1 Handler

0x005

rjmp

PCINT2

; PCINT2 Handler

0x006

rjmp

WDT

; Watchdog Timer Handler

0x007

rjmp

TIM2_COMPA

; Timer2 Compare A Handler

0X008

rjmp

TIM2_COMPB

; Timer2 Compare B Handler

0x009

rjmp

TIM2_OVF

; Timer2 Overflow Handler

0x00A

rjmp

TIM1_CAPT

; Timer1 Capture Handler

0x00B

rjmp

TIM1_COMPA

; Timer1 Compare A Handler

0x00C

rjmp

TIM1_COMPB

; Timer1 Compare B Handler

0x00D

rjmp

TIM1_OVF

; Timer1 Overflow Handler

0x00E

rjmp

TIM0_COMPA

; Timer0 Compare A Handler

0x00F

rjmp

TIM0_COMPB

; Timer0 Compare B Handler

0x010

rjmp

TIM0_OVF

; Timer0 Overflow Handler

0x011

rjmp

SPI_STC

; SPI Transfer Complete Handler

0x012

rjmp

USART_RXC

; USART, RX Complete Handler

0x013

rjmp

USART_UDRE

; USART, UDR Empty Handler

0x014

rjmp

USART_TXC

; USART, TX Complete Handler

0x015

rjmp

ADC

; ADC Conversion Complete Handler

0x016

rjmp

EE_RDY

; EEPROM Ready Handler

0x017

rjmp

ANA_COMP

; Analog Comparator Handler

0x018

rjmp

TWI

; 2-wire Serial Interface Handler

0x019

rjmp

SPM_RDY

; Store Program Memory Ready Handler

0x01ARESET:

ldi

r16, high(RAMEND); Main program start

0x01B

out

SPH,r16

0x01C

ldi

r16, low(RAMEND)

0x01D
0x01E

out
sei

SPL,r16

0x01F



;
; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega88A/88PA is:
Address Labels Code

Comments

0x000

RESET: ldi

0x001

out

SPH,r16

r16,high(RAMEND); Main program start

0x002

ldi

r16,low(RAMEND)

0x003
0x004

out
sei

SPL,r16

0x005



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

;
.org 0xC01
0xC01

rjmp

EXT_INT0

; IRQ0 Handler

0xC02

rjmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0xC19

rjmp

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is:
Address Labels Code

Comments

.org 0x001
0x001

rjmp

EXT_INT0

; IRQ0 Handler

0x002

rjmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0x019

rjmp

SPM_RDY

; Store Program Memory Ready Handler

;
.org 0xC00
0xC00
RESET: ldi

r16,high(RAMEND); Main program start

0xC01

out

SPH,r16

0xC02

ldi

r16,low(RAMEND)

0xC03
0xC04

out
sei

SPL,r16

0xC05



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses in ATmega88A/88PA is:
Address Labels Code

Comments

;
.org 0xC00
0xC00

rjmp

RESET

; Reset handler

0xC01

rjmp

EXT_INT0

; IRQ0 Handler

0xC02

rjmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0xC19

rjmp

SPM_RDY

; Store Program Memory Ready Handler

;
0xC1A

RESET: ldi

0xC1B

out

SPH,r16

r16,high(RAMEND); Main program start

0xC1C

ldi

r16,low(RAMEND)

; Set Stack Pointer to top of RAM

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12.3

0xC1D
0xC1E

out
sei

SPL,r16

0xC1F



; Enable interrupts
xxx

Interrupt Vectors in ATmega168A and ATmega168PA

Table 12-4.
VectorNo.
1

Reset and Interrupt Vectors in ATmega168A and ATmega168PA
Program
Address(2)
(1)

0x0000

Source

Interrupt Definition

RESET

External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2

0x0002

INT0

External Interrupt Request 0

3

0x0004

INT1

External Interrupt Request 1

4

0x0006

PCINT0

Pin Change Interrupt Request 0

5

0x0008

PCINT1

Pin Change Interrupt Request 1

6

0x000A

PCINT2

Pin Change Interrupt Request 2

7

0x000C

WDT

Watchdog Time-out Interrupt

8

0x000E

TIMER2 COMPA

Timer/Counter2 Compare Match A

9

0x0010

TIMER2 COMPB

Timer/Counter2 Compare Match B

10

0x0012

TIMER2 OVF

Timer/Counter2 Overflow

11

0x0014

TIMER1 CAPT

Timer/Counter1 Capture Event

12

0x0016

TIMER1 COMPA

Timer/Counter1 Compare Match A

13

0x0018

TIMER1 COMPB

Timer/Coutner1 Compare Match B

14

0x001A

TIMER1 OVF

Timer/Counter1 Overflow

15

0x001C

TIMER0 COMPA

Timer/Counter0 Compare Match A

16

0x001E

TIMER0 COMPB

Timer/Counter0 Compare Match B

17

0x0020

TIMER0 OVF

Timer/Counter0 Overflow

18

0x0022

SPI, STC

SPI Serial Transfer Complete

19

0x0024

USART, RX

USART Rx Complete

20

0x0026

USART, UDRE

USART, Data Register Empty

21

0x0028

USART, TX

USART, Tx Complete

22

0x002A

ADC

ADC Conversion Complete

23

0x002C

EE READY

EEPROM Ready

24

0x002E

ANALOG COMP

Analog Comparator

25

0x0030

TWI

2-wire Serial Interface

26

0x0032

SPM READY

Store Program Memory Ready

Notes:

1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 269.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of
each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 12-5 on page 63 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and reg-

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ular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application
section while the Interrupt Vectors are in the Boot section or vice versa.
Table 12-5.

Reset and Interrupt Vectors Placement in ATmega168A and ATmega168PA(1)

BOOTRST

IVSEL

1

Note:

Reset Address

Interrupt Vectors Start Address

0

0x000

0x002

1

1

0x000

Boot Reset Address + 0x0002

0

0

Boot Reset Address

0x002

0

1

Boot Reset Address

Boot Reset Address + 0x0002

1. The Boot Reset Address is shown in Table 27-7 on page 280. For the BOOTRST Fuse “1” means unprogrammed
while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA
is:
Address Labels Code

Comments

0x0000

jmp

RESET

; Reset Handler

0x0002

jmp

EXT_INT0

; IRQ0 Handler

0x0004

jmp

EXT_INT1

; IRQ1 Handler

0x0006

jmp

PCINT0

; PCINT0 Handler

0x0008

jmp

PCINT1

; PCINT1 Handler

0x000A

jmp

PCINT2

; PCINT2 Handler

0x000C

jmp

WDT

; Watchdog Timer Handler

0x000E

jmp

TIM2_COMPA

; Timer2 Compare A Handler

0x0010

jmp

TIM2_COMPB

; Timer2 Compare B Handler

0x0012

jmp

TIM2_OVF

; Timer2 Overflow Handler

0x0014

jmp

TIM1_CAPT

; Timer1 Capture Handler

0x0016

jmp

TIM1_COMPA

; Timer1 Compare A Handler

0x0018

jmp

TIM1_COMPB

; Timer1 Compare B Handler

0x001A

jmp

TIM1_OVF

; Timer1 Overflow Handler

0x001C

jmp

TIM0_COMPA

; Timer0 Compare A Handler

0x001E

jmp

TIM0_COMPB

; Timer0 Compare B Handler

0x0020

jmp

TIM0_OVF

; Timer0 Overflow Handler

0x0022

jmp

SPI_STC

; SPI Transfer Complete Handler

0x0024

jmp

USART_RXC

; USART, RX Complete Handler

0x0026

jmp

USART_UDRE

; USART, UDR Empty Handler

0x0028

jmp

USART_TXC

; USART, TX Complete Handler

0x002A

jmp

ADC

; ADC Conversion Complete Handler

0x002C

jmp

EE_RDY

; EEPROM Ready Handler

0x002E

jmp

ANA_COMP

; Analog Comparator Handler

0x0030

jmp

TWI

; 2-wire Serial Interface Handler

0x0032

jmp

SPM_RDY

; Store Program Memory Ready Handler

;
0x0033RESET:

ldi

r16, high(RAMEND); Main program start

0x0034

out

SPH,r16

0x0035

ldi

r16, low(RAMEND)

0x0036

out

SPL,r16

0x0037

sei

; Set Stack Pointer to top of RAM

; Enable interrupts

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0x0038
...


...

...

xxx

...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega168A/168PA is:
Address Labels Code

Comments

0x0000

RESET: ldi

0x0001

out

SPH,r16

r16,high(RAMEND); Main program start

0x0002

ldi

r16,low(RAMEND)

0x0003
0x0004

out
sei

SPL,r16

0x0005



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

;
.org 0x1C02
0x1C02

jmp

EXT_INT0

; IRQ0 Handler

0x1C04

jmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0x1C32

jmp

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA is:

Address Labels Code

Comments

.org 0x0002
0x0002

jmp

EXT_INT0

; IRQ0 Handler

0x0004

jmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0x0032

jmp

SPM_RDY

; Store Program Memory Ready Handler

;
.org 0x1C00
0x1C00 RESET: ldi

r16,high(RAMEND); Main program start

0x1C01

out

SPH,r16

0x1C02

ldi

r16,low(RAMEND)

0x1C03
0x1C04

out
sei

SPL,r16

0x1C05



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses in ATmega168A/168PA is:
Address Labels Code

Comments

;
.org 0x1C00
0x1C00

jmp

RESET

; Reset handler

0x1C02

jmp

EXT_INT0

; IRQ0 Handler

0x1C04

jmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0x1C32

jmp

SPM_RDY

; Store Program Memory Ready Handler

;

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12.4

0x1C33

RESET: ldi

r16,high(RAMEND); Main program start

0x1C34

out

SPH,r16

0x1C35

ldi

r16,low(RAMEND)

0x1C36
0x1C37

out
sei

SPL,r16

0x1C38



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

Interrupt Vectors in ATmega328 and ATmega328P

Table 12-6.

Reset and Interrupt Vectors in ATmega328 and ATmega328P

VectorNo.

Program
Address(2)

Source

Interrupt Definition

1

0x0000(1)

RESET

External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2

0x0002

INT0

External Interrupt Request 0

3

0x0004

INT1

External Interrupt Request 1

4

0x0006

PCINT0

Pin Change Interrupt Request 0

5

0x0008

PCINT1

Pin Change Interrupt Request 1

6

0x000A

PCINT2

Pin Change Interrupt Request 2

7

0x000C

WDT

Watchdog Time-out Interrupt

8

0x000E

TIMER2 COMPA

Timer/Counter2 Compare Match A

9

0x0010

TIMER2 COMPB

Timer/Counter2 Compare Match B

10

0x0012

TIMER2 OVF

Timer/Counter2 Overflow

11

0x0014

TIMER1 CAPT

Timer/Counter1 Capture Event

12

0x0016

TIMER1 COMPA

Timer/Counter1 Compare Match A

13

0x0018

TIMER1 COMPB

Timer/Coutner1 Compare Match B

14

0x001A

TIMER1 OVF

Timer/Counter1 Overflow

15

0x001C

TIMER0 COMPA

Timer/Counter0 Compare Match A

16

0x001E

TIMER0 COMPB

Timer/Counter0 Compare Match B

17

0x0020

TIMER0 OVF

Timer/Counter0 Overflow

18

0x0022

SPI, STC

SPI Serial Transfer Complete

19

0x0024

USART, RX

USART Rx Complete

20

0x0026

USART, UDRE

USART, Data Register Empty

21

0x0028

USART, TX

USART, Tx Complete

22

0x002A

ADC

ADC Conversion Complete

23

0x002C

EE READY

EEPROM Ready

24

0x002E

ANALOG COMP

Analog Comparator

25

0x0030

TWI

2-wire Serial Interface

26

0x0032

SPM READY

Store Program Memory Ready

Notes:

1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 269.

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2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of
each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 12-7 on page 66 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application
section while the Interrupt Vectors are in the Boot section or vice versa.
Table 12-7.

Reset and Interrupt Vectors Placement in ATmega328 and ATmega328P(1)

BOOTRST

IVSEL

1

Note:

Reset Address

Interrupt Vectors Start Address

0

0x000

0x002

1

1

0x000

Boot Reset Address + 0x0002

0

0

Boot Reset Address

0x002

0

1

Boot Reset Address

Boot Reset Address + 0x0002

1. The Boot Reset Address is shown in Table 27-7 on page 280. For the BOOTRST Fuse “1” means unprogrammed
while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P is:
Address Labels Code

Comments

0x0000

jmp

RESET

; Reset Handler

0x0002

jmp

EXT_INT0

; IRQ0 Handler

0x0004

jmp

EXT_INT1

; IRQ1 Handler

0x0006

jmp

PCINT0

; PCINT0 Handler

0x0008

jmp

PCINT1

; PCINT1 Handler

0x000A

jmp

PCINT2

; PCINT2 Handler

0x000C

jmp

WDT

; Watchdog Timer Handler

0x000E

jmp

TIM2_COMPA

; Timer2 Compare A Handler

0x0010

jmp

TIM2_COMPB

; Timer2 Compare B Handler

0x0012

jmp

TIM2_OVF

; Timer2 Overflow Handler

0x0014

jmp

TIM1_CAPT

; Timer1 Capture Handler

0x0016

jmp

TIM1_COMPA

; Timer1 Compare A Handler

0x0018

jmp

TIM1_COMPB

; Timer1 Compare B Handler

0x001A

jmp

TIM1_OVF

; Timer1 Overflow Handler

0x001C

jmp

TIM0_COMPA

; Timer0 Compare A Handler

0x001E

jmp

TIM0_COMPB

; Timer0 Compare B Handler

0x0020

jmp

TIM0_OVF

; Timer0 Overflow Handler

0x0022

jmp

SPI_STC

; SPI Transfer Complete Handler

0x0024

jmp

USART_RXC

; USART, RX Complete Handler

0x0026

jmp

USART_UDRE

; USART, UDR Empty Handler

0x0028

jmp

USART_TXC

; USART, TX Complete Handler

0x002A

jmp

ADC

; ADC Conversion Complete Handler

0x002C

jmp

EE_RDY

; EEPROM Ready Handler

0x002E

jmp

ANA_COMP

; Analog Comparator Handler

0x0030

jmp

TWI

; 2-wire Serial Interface Handler

0x0032

jmp

SPM_RDY

; Store Program Memory Ready Handler

;
0x0033RESET:

ldi

r16, high(RAMEND); Main program start

0x0034

out

SPH,r16

; Set Stack Pointer to top of RAM

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0x0035

ldi

r16, low(RAMEND)

0x0036

out

SPL,r16

0x0037

sei

0x0038
...

; Enable interrupts


...

...

xxx

...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega328/328P is:
Address Labels Code

Comments

0x0000

RESET: ldi

r16,high(RAMEND); Main program start

0x0001

out

SPH,r16

0x0002

ldi

r16,low(RAMEND)

0x0003
0x0004

out
sei

SPL,r16

0x0005



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

;
.org 0x3C02
0x3C02

jmp

EXT_INT0

; IRQ0 Handler

0x3C04

jmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0x3C32

jmp

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P is:
Address Labels Code

Comments

.org 0x0002
0x0002

jmp

EXT_INT0

; IRQ0 Handler

0x0004

jmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

0x0032

jmp

SPM_RDY

; Store Program Memory Ready Handler

;
.org 0x3C00
0x3C00 RESET: ldi

r16,high(RAMEND); Main program start

0x3C01

out

SPH,r16

0x3C02

ldi

r16,low(RAMEND)

0x3C03
0x3C04

out
sei

SPL,r16

0x3C05



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses in ATmega328/328P is:
Address Labels Code

Comments

;
.org 0x3C00
0x3C00

jmp

RESET

; Reset handler

0x3C02

jmp

EXT_INT0

; IRQ0 Handler

0x3C04

jmp

EXT_INT1

; IRQ1 Handler

...

...

...

;

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0x3C32

jmp

SPM_RDY

; Store Program Memory Ready Handler

;
0x3C33

RESET: ldi

r16,high(RAMEND); Main program start

0x3C34

out

SPH,r16

0x3C35

ldi

r16,low(RAMEND)

0x3C36
0x3C37

out
sei

SPL,r16

0x3C38



; Set Stack Pointer to top of RAM

; Enable interrupts
xxx

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12.5

Register Description

12.5.1

Moving Interrupts Between Application and Boot Space, ATmega88A/88PA, ATmega168A/168PA and
ATmega328/328P
The MCU Control Register controls the placement of the Interrupt Vector table.
MCUCR – MCU Control Register
Bit

7

6

5

4

3

2

1

0

0x35 (0x55)

–

BODS(1)

BODSE(1)

PUD

–

–

IVSEL

IVCE

Read/Write

R

R/W

R/W

R/W

R

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Note:

MCUCR

1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P

• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this
bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual
address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section ”Boot
Loader Support – Read-While-Write Self-Programming” on page 269 for details. To avoid unintentional changes of
Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b.

Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE
is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot
Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section ”Boot Loader Support – Read-While-Write Self-Programming” on page 269 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four
cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the
IVSEL description above. See Code Example below.

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Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1< CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.

17.3

External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin
is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is
then passed through the edge detector. Figure 17-1 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.
Figure 17-1. T1/T0 Pin Sampling

Tn

D

Q

D

Q

D

Tn_sync
(To Clock
Select Logic)

Q

LE
clk I/O
Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2)

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given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1(1)
clk I/O

Clear

PSRSYNC

T0

Synchronization
T1

Synchronization

clkT1

Note:

clkT0

1. The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1.

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17.4
17.4.1

Register Description
GTCCR – General Timer/Counter Control Register
Bit

7

6

5

4

3

2

1

0

0x23 (0x43)

TSM

–

–

–

–

–

PSRASY

PSRSYNC

Read/Write

R/W

R

R

R

R

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

GTCCR

• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted.
This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without
the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and
PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the
same prescaler and a reset of this prescaler will affect both timers.

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18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1

Features
•
•
•
•
•
•
•

18.2

Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock

Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of
the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to ”Pinout
ATmega48A/PA/88A/PA/168A/PA/328/P” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins,
are shown in bold. The device-specific I/O Register and bit locations are listed in the ”Register Description” on
page 155.
The PRTIM2 bit in ”Minimizing Power Consumption” on page 41 must be written to zero to enable Timer/Counter2
module.
Figure 18-1. 8-bit Timer/Counter Block Diagram
Count
Clear
Direction

TOVn
(Int.Req.)
Control Logic

clkTn

Clock Select
Edge
Detector

TOP

Tn

BOTTOM
( From Prescaler )

Timer/Counter
TCNTn

=

=0
OCnA
(Int.Req.)
Waveform
Generation

=

OCnA

DATA BUS

OCRnA
Fixed
TOP
Value

Waveform
Generation

=

OCnB

OCRnB

TCCRnA

18.2.1

OCnB
(Int.Req.)

TCCRnB

Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt
request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are

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individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See ”Output Compare Unit” on page 144 for
details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request.
18.2.2

Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in Table 18-1 are also used extensively throughout the section.
Table 18-1.
BOTTOM

18.3

Definitions
The counter reaches the BOTTOM when it becomes zero (0x00).

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation.

Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to
logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see ”ASSR – Asynchronous Status Register” on page 160. For details on clock
sources and prescaler, see ”Timer/Counter Prescaler” on page 154.

18.4

Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 on page 143
shows a block diagram of the counter and its surrounding environment.
Figure 18-2. Counter Unit Block Diagram
TOVn
(Int.Req.)

DATA BUS

TOSC1
count
TCNTn

clear

clk Tn

Control Logic

Prescaler

T/C
Oscillator

direction

bottom

TOSC2

top

clkI/O

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Signal description (internal signals):
count

Increment or decrement TCNT2 by 1.

direction

Selects between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clkTn

Timer/Counter clock, referred to as clkT2 in the following.

top

Signalizes that TCNT2 has reached maximum value.

bottom

Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be
accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter
Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform
generation, see ”Modes of Operation” on page 147.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits.
TOV2 can be used for generating a CPU interrupt.

18.5

Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B).
Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output
Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when
the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals
are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page 147).
Figure 18-3 shows a block diagram of the Output Compare unit.

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Figure 18-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )
OCFnx (Int.Req.)

top
bottom

Waveform Generator

OCnx

FOCn

WGMn1:0

COMnX1:0

The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x
directly.
18.5.1

Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the
timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings
define whether the OC2x pin is set, cleared or toggled).

18.5.2

Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2
without triggering an interrupt when the Timer/Counter clock is enabled.

18.5.3

Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the
Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM
when the counter is downcounting.
The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal
mode. The OC2x Register keeps its value even when changing between Waveform Generation modes.

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Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the
COM2x1:0 bits will take effect immediately.

18.6

Compare Match Output Unit
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0
bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the
OC2x pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port
Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x
state, the reference is for the internal OC2x Register, not the OC2x pin.
Figure 18-4. Compare Match Output Unit, Schematic

COMnx1
COMnx0
FOCnx

Waveform
Generator

D

Q
1

OCnx

DATA BUS

D

0

OCnx
Pin

Q

PORT
D

Q

DDR
clk I/O

The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either
of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as
output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled.
Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on
page 155
18.6.1

Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes,
setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 18-5 on page 156. For
fast PWM mode, refer to Table 18-6 on page 156, and for phase correct PWM refer to Table 18-7 on page 157.
A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits.

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18.7

Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a
compare match (See ”Compare Match Output Unit” on page 146).
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 151.

18.7.1

Normal Mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

18.7.2

Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The
OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the
compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 18-5. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared.
Figure 18-5. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set

TCNTn

OCnx
(Toggle)
Period

(COMnx1:0 = 1)

1

2

3

4

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower
than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will

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not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by
the following equation:
f clk_I/O
f OCnx = ------------------------------------------------2  N   1 + OCRnx 
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
18.7.3

Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and
OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the
compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of
the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This
high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications.
High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total
system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The
TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent
compare matches between OCR2x and TCNT2.
Figure 18-6. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set

OCRnx Update and
TOVn Interrupt Flag Set

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

1

2

3

4

5

6

7

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting

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the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. (See Table
18-3 on page 155). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match
between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------N  256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM2A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle
its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency
of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the
double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
18.7.4

Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly
from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A
when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In
inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation
frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes,
these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between
OCR2x and TCNT2.

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Figure 18-7. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

1

2

3

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 18-4
on page 155). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between
OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match
between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase
correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = ----------------N  510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 18-7 OCnx has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
• OCR2A changes its value from MAX, like in Figure 18-7. When the OCR2A value is MAX the OCn pin value is the
same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at
MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.

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18.8

Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown
as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock.
The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than
phase correct PWM mode.
Figure 18-8. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn

(clkI/O /1)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 18-9 shows the same timing data, but with the prescaler enabled.
Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn

(clkI/O /8)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 18-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)
clkI/O
clkTn

(clkI/O /8)

TCNTn

OCRnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCFnx

Figure 18-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

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Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn

(clkI/O /8)

TCNTn
(CTC)
OCRnx

TOP - 1

TOP

BOTTOM

BOTTOM + 1

TOP

OCFnx

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18.9

Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
b.

Select clock source by setting AS2 as appropriate.

c.

Write new values to TCNT2, OCR2x, and TCCR2x.

d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.
e. Clear the Timer/Counter2 Interrupt Flags.
f.

Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.
• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register,
and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the
temporary register have been transferred to its destination. Each of the five mentioned registers have their
individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in
progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register
– ASSR has been implemented.
• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x,
the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device.
Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of
the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled
during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the
corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the
MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions
must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode within the TOSC1
cycle, the interrupt will immediately occur and the device wake up again. The result is multiple interrupts and
wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt whether the time before reentering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure
that one TOSC1 cycle has elapsed:
a. Write a value to TCCR2x, TCNT2, or OCR2x.
b.

Wait until the corresponding Update Busy Flag in ASSR returns to zero.

c.

Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running,
except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby
mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The
user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from
Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a
wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the
Oscillator is in use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the
timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from
the instruction following SLEEP.

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• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since
TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register
synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When
waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the
previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after
waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b.

Wait for the corresponding Update Busy Flag to be cleared.

c.

Read TCNT2.

During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes
3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can
read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer
clock and is not synchronized to the processor clock.

18.10 Timer/Counter Prescaler
Figure 18-12. Prescaler for Timer/Counter2

PSRASY

clkT2S/1024

clkT2S/256

clkT2S/128

AS2

clkT2S/64

10-BIT T/C PRESCALER

Clear

clkT2S/32

TOSC1

clkT2S
clkT2S/8

clkI/O

0

CS20
CS21
CS22

TIMER/COUNTER2 CLOCK SOURCE
clkT2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock
clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This
enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an
independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and
clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the
prescaler. This allows the user to operate with a predictable prescaler.

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18.11 Register Description
18.11.1

TCCR2A – Timer/Counter Control Register A
Bit

7

6

5

4

3

2

1

0

COM2A1

COM2A0

COM2B1

COM2B0

–

–

WGM21

WGM20

Read/Write

R/W

R/W

R/W

R/W

R

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

(0xB0)

TCCR2A

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the
OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting.
Table 18-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (nonPWM).
Table 18-2.

Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

0

0

Normal port operation, OC0A disconnected.

0

1

Toggle OC2A on Compare Match

1

0

Clear OC2A on Compare Match

1

1

Set OC2A on Compare Match

Table 18-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Table 18-3.

Compare Output Mode, Fast PWM Mode(1)

COM2A1

COM2A0

0

0

Normal port operation, OC2A disconnected.

0

1

WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.

1

0

Clear OC2A on Compare Match, set OC2A at BOTTOM,
(non-inverting mode).

1

1

Set OC2A on Compare Match, clear OC2A at BOTTOM,
(inverting mode).

Note:

Description

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on page 148 for more details.

Table 18-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode.
Table 18-4.

Compare Output Mode, Phase Correct PWM Mode(1)

COM2A1

COM2A0

0

0

Description
Normal port operation, OC2A disconnected.

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Table 18-4.

Compare Output Mode, Phase Correct PWM Mode(1)

COM2A1

COM2A0

0

1

WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.

1

0

Clear OC2A on Compare Match when up-counting. Set OC2A on
Compare Match when down-counting.

1

1

Set OC2A on Compare Match when up-counting. Clear OC2A on
Compare Match when down-counting.

Note:

Description

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 149 for more details.

• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the
OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting.
Table 18-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (nonPWM).
Table 18-5.

Compare Output Mode, non-PWM Mode

COM2B1

COM2B0

Description

0

0

Normal port operation, OC2B disconnected.

0

1

Toggle OC2B on Compare Match

1

0

Clear OC2B on Compare Match

1

1

Set OC2B on Compare Match

Table 18-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode.
Table 18-6.

Compare Output Mode, Fast PWM Mode(1)

COM2B1

COM2B0

0

0

Normal port operation, OC2B disconnected.

0

1

Reserved

1

0

Clear OC2B on Compare Match, set OC2B at BOTTOM,
(non-inverting mode).

1

1

Set OC2B on Compare Match, clear OC2B at BOTTOM,
(inverting mode).

Note:

Description

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See ”Phase Correct PWM Mode” on page 149 for more details.

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Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode.
Compare Output Mode, Phase Correct PWM Mode(1)

Table 18-7.
COM2B1

COM2B0

0

0

Normal port operation, OC2B disconnected.

0

1

Reserved

1

0

Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.

1

1

Set OC2B on Compare Match when up-counting. Clear OC2B on
Compare Match when down-counting.

Note:

Description

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 149 for more details.

• Bits 3:2 – Reserved
These bits are reserved in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 18-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see ”Modes of Operation”
on page 147).
Table 18-8.

Waveform Generation Mode Bit Description
Timer/Counter
Mode of
Operation

TOP

Update of
OCRx at

TOV Flag
Set on(1)(2)

Mode

WGM22

WGM21

WGM20

0

0

0

0

Normal

0xFF

Immediate

MAX

1

0

0

1

PWM, Phase
Correct

0xFF

TOP

BOTTOM

2

0

1

0

CTC

OCRA

Immediate

MAX

3

0

1

1

Fast PWM

0xFF

BOTTOM

MAX

4

1

0

0

Reserved

–

–

–

5

1

0

1

PWM, Phase
Correct

OCRA

TOP

BOTTOM

6

1

1

0

Reserved

–

–

–

7

1

1

1

Fast PWM

OCRA

BOTTOM

TOP

Notes:

1. MAX= 0xFF
2. BOTTOM= 0x00

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18.11.2

TCCR2B – Timer/Counter Control Register B
Bit

7

6

5

4

3

2

1

0

FOC2A

FOC2B

–

–

WGM22

CS22

CS21

CS20

Read/Write

W

W

R

R

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

(0xB1)

TCCR2B

• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the
FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the
effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when
operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the
FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the
effect of the forced compare.
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Reserved
These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bit 3 – WGM22: Waveform Generation Mode
See the description in the ”TCCR2A – Timer/Counter Control Register A” on page 155.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 18-9 on page 158.
Table 18-9.

Clock Select Bit Description

CS22

CS21

CS20

Description

0

0

0

No clock source (Timer/Counter stopped).

0

0

1

clkT2S/(No prescaling)

0

1

0

clkT2S/8 (From prescaler)

0

1

1

clkT2S/32 (From prescaler)

1

0

0

clkT2S/64 (From prescaler)

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Table 18-9.

Clock Select Bit Description

CS22

CS21

CS20

Description

1

0

1

clkT2S/128 (From prescaler)

1

1

0

clkT2S/256 (From prescaler)

1

1

1

clkT2S/1024 (From prescaler)

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
18.11.3

TCNT2 – Timer/Counter Register
Bit

7

6

5

4

(0xB2)

3

2

1

0

TCNT2[7:0]

TCNT2

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between
TCNT2 and the OCR2x Registers.
18.11.4

OCR2A – Output Compare Register A
Bit

7

6

5

4

(0xB3)

3

2

1

0

OCR2A[7:0]

OCR2A

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2A pin.
18.11.5

OCR2B – Output Compare Register B
Bit

7

6

5

4

(0xB4)

3

2

1

0

OCR2B[7:0]

OCR2B

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2B pin.
18.11.6

TIMSK2 – Timer/Counter2 Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

(0x70)

–

–

–

–

–

OCIE2B

OCIE2A

TOIE2

Read/Write

R

R

R

R

R

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

TIMSK2

• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2
occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.

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• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2
occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the
TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.
18.11.7

TIFR2 – Timer/Counter2 Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

0x17 (0x37)

–

–

–

–

–

OCF2B

OCF2A

TOV2

Read/Write

R

R

R

R

R

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

TIFR2

• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B –
Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B
(Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A –
Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
18.11.8

ASSR – Asynchronous Status Register
Bit

7

6

5

4

3

2

1

0

(0xB6)

–

EXCLK

AS2

TCN2UB

OCR2AUB

OCR2BUB

TCR2AUB

TCR2BUB

Read/Write

R

R/W

R/W

R

R

R

R

R

Initial Value

0

0

0

0

0

0

0

0

ASSR

• Bit 7 – Reserved
This bit is reserved and will always read as zero.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and
an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK
should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this
bit is zero.

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• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one,
Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the
value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that OCR2A is ready to be updated with a new value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2A is ready to be updated with a new value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2B is ready to be updated with a new value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated
value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading
TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the
temporary storage register is read.
18.11.9

GTCCR – General Timer/Counter Control Register
Bit

7

6

5

4

3

2

1

0

0x23 (0x43)

TSM

–

–

–

–

–

PSRASY

PSRSYNC

Read/Write

R/W

R

R

R

R

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

GTCCR

• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the
prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of
the ”Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 141 for a description of the Timer/Counter Synchronization mode.

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19. SPI – Serial Peripheral Interface
19.1

Features
•
•
•
•
•
•
•
•

Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega48A/PA/88A/PA/168A/PA/328/P and peripheral devices or between several AVR devices.
The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 199. The PRSPI bit in ”Minimizing Power Consumption” on page 41 must be written to zero to enable SPI module.
Figure 19-1. SPI Block Diagram(1)

DIVIDER
/2/4/8/16/32/64/128

SPI2X

SPI2X

19.2

Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode

Note:

1. Refer to Figure 1-1 on page 2, and Table 14-3 on page 83 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 163. The system
consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle

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when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in
their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange
data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by
pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by
user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the
SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer
Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is
driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not
be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR
Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 19-2. SPI Master-slave Interconnection

SHIFT
ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direction. This means that
bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When
receiving data, however, a received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of
the clock signal, the minimum low and high periods should be:
Low periods: Longer than 2 CPU clock cycles.
High periods: Longer than 2 CPU clock cycles.

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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 19-1 on page 164. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page
81.
Table 19-1.
Pin

SPI Pin Overrides(Note:)
Direction, Master SPI

Direction, Slave SPI

MOSI

User Defined

Input

MISO

Input

User Defined

SCK

User Defined

Input

SS

User Defined

Input

Note:

See ”Alternate Functions of Port B” on page 83 for a detailed description of how to define the direction of the user
defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins.
DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI
is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.

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Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi

r17,(1<>8);
UBRR0L = (unsigned char)ubrr;
Enable receiver and transmitter */
UCSR0B = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}
Note:

1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.

The receive function example reads all the I/O Registers into the Register File before any computation is done.
This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early
as possible.

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20.7.3

Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one
when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any
unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the
RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt
will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interruptdriven data reception is used, the receive complete routine must read the received data from UDRn in order to
clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates.

20.7.4

Receiver Error Flags
The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn).
All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer
together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read
location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag
location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future
USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive
buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the
stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions
and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver
ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs
when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last
read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to
zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If
Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set
this bit to zero when writing to UCSRnA. For more details see ”Parity Bit Calculation” on page 177 and ”Parity
Checker” on page 184.

20.7.5

Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the
data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can
then be read by software to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is
read.

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20.7.6

Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function
of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in
the buffer will be lost

20.7.7

Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error
condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to
flush the receive buffer.
Assembly Code Example(1)
USART_Flush:
in r16, UCSRnA
sbrs r16, RXCn
ret
in

r16, UDRn

rjmp USART_Flush

C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck  12MHz
High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck  12MHz
28.8.1

Serial Programming Pin Mapping

Table 28-17. Pin Mapping Serial Programming

28.8.2

Symbol

Pins

I/O

Description

MOSI

PB3

I

Serial Data in

MISO

PB4

O

Serial Data out

SCK

PB5

I

Serial Clock

Serial Programming Algorithm
When writing serial data to the ATmega48A/PA/88A/PA/168A/PA/328/P, data is clocked on the rising edge of SCK.

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When reading data from the ATmega48A/PA/88A/PA/168A/PA/328/P, data is clocked on the falling edge of SCK.
See Figure 28-9 for timing details.
To program and verify the ATmega48A/PA/88A/PA/168A/PA/328/P in the serial programming mode, the following
sequence is recommended (See Serial Programming Instruction set in Table 28-19 on page 301):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive
pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction
to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did
not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying
the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is applied for a given
address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with
the 7 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before
issuing the next page (See Table 28-18). Accessing the serial programming interface before the Flash write
operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with
the appropriate Write instruction. An EEPROM memory location is first automatically erased before new
data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the
next byte (See Table 28-18). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time
by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction.
The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 7
MSB of the address. When using EEPROM page access only byte locations loaded with the Load
EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling
(RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table 2818). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected
address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.

Table 28-18. Typical Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol

Minimum Wait Delay

tWD_FLASH

4.5ms

tWD_EEPROM

3.6ms

tWD_ERASE

9.0ms

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28.8.3

Serial Programming Instruction set
Table 28-19 on page 301 and Figure 28-8 on page 302 describes the Instruction set.

Table 28-19. Serial Programming Instruction Set (Hexadecimal values)
Instruction Format
Instruction/Operation

Byte 1

Byte 2

Byte 3

Byte4

Programming Enable

$AC

$53

$00

$00

Chip Erase (Program Memory/EEPROM)

$AC

$80

$00

$00

Poll RDY/BSY

$F0

$00

$00

data byte out

Load Extended Address byte(1)

$4D

$00

Extended adr

$00

Load Program Memory Page, High byte

$48

$00

adr LSB

high data byte in

Load Program Memory Page, Low byte

$40

$00

adr LSB

low data byte in

Load EEPROM Memory Page (page access)

$C1

$00

0000 000aa

data byte in

Read Program Memory, High byte

$28

adr MSB

adr LSB

high data byte out

Read Program Memory, Low byte

$20

adr MSB

adr LSB

low data byte out

Read EEPROM Memory

$A0

0000 00aa

aaaa aaaa

data byte out

Read Lock bits

$58

$00

$00

data byte out

Read Signature Byte

$30

$00

0000 000aa

data byte out

Read Fuse bits

$50

$00

$00

data byte out

Read Fuse High bits

$58

$08

$00

data byte out

Read Extended Fuse Bits

$50

$08

$00

data byte out

Read Calibration Byte

$38

$00

$00

data byte out

Write Program Memory Page

$4C

adr MSB(8)

adr LSB(8)

$00

Write EEPROM Memory

$C0

0000 00aa

aaaa aaaa

data byte in

Write EEPROM Memory Page (page access)

$C2

0000 00aa

aaaa aa00

$00

Write Lock bits

$AC

$E0

$00

data byte in

Write Fuse bits

$AC

$A0

$00

data byte in

Write Fuse High bits

$AC

$A8

$00

data byte in

Write Extended Fuse Bits

$AC

$A4

$00

data byte in

Load Instructions

Read Instructions

Write Instructions(6)

Notes:

1.
2.
3.
4.
5.
6.
7.
8.

Not all instructions are applicable for all parts.
a = address.
Bits are programmed ‘0’, unprogrammed ‘1’.
To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
Instructions accessing program memory use a word address. This address may be random within the page range.
See http://www.atmel.com/avr for Application Notes regarding programming and programmers.
WORDS

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’
before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.

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After data is loaded to the page buffer, program the EEPROM page, see Figure 28-8 on page 302.
Figure 28-8. Serial Programming Instruction example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)

Byte 1

Byte 2
Adr MSB
A

Byte 3

Write Program Memory Page/
Write EEPROM Memory Page

Byte 1

Byte 4

Byte 2

Adr LSB

Bit 15 B

Adr MSB

Byte 3

Byte 4

Adrr LSB
B

Bit 15 B

0

0

Page Buffer
Page Offset

Page 0

Page 1

Page 2
Page Number

Page N-1

Program Memory/
EEPROM Memory

28.8.4

SPI Serial Programming Characteristics
Figure 28-9. Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)

MSB

LSB

SERIAL DATA OUTPUT
(MISO)

MSB

LSB

SERIAL CLOCK INPUT
(SCK)
SAMPLE

For characteristics of the SPI module see “SPI Timing Characteristics” on page 313.

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29. Electrical Characteristics – (TA = -40°C to 85°C)
29.1

Absolute Maximum Ratings*
*NOTICE:

Operating Temperature.................................. -55C to +125C
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V

Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ................................................ 40.0mA
DC Current VCC and GND Pins................................. 200.0mA

29.2

DC Characteristics

Table 29-1.
Symbol

Common DC characteristics TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Condition

Min.

Typ.

Max.

Units

(1)

VIL

Input Low Voltage, except
XTAL1 and RESET pin

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

-0.5
-0.5

0.2VCC
0.3VCC(1)

V

VIH

Input High Voltage, except
XTAL1 and RESET pins

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

0.7VCC(2)
0.6VCC(2)

VCC + 0.5
VCC + 0.5

V

VIL1

Input Low Voltage,
XTAL1 pin

VCC = 1.8V - 5.5V

-0.5

0.1VCC(1)

V

VIH1

Input High Voltage,
XTAL1 pin

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

0.8VCC(2)
0.7VCC(2)

VCC + 0.5
VCC + 0.5

V

VIL2

Input Low Voltage,
RESET pin

VCC = 1.8V - 5.5V

-0.5

0.1VCC(1)

V

VIH2

Input High Voltage,
RESET pin

VCC = 1.8V - 5.5V

0.9VCC(2)

VCC + 0.5

V

VIL3

Input Low Voltage,
RESET pin as I/O

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

-0.5
-0.5

0.2VCC(1)
0.3VCC(1)

V

VIH3

Input High Voltage,
RESET pin as I/O

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

0.7VCC(2)
0.6VCC(2)

VCC + 0.5
VCC + 0.5

V

VOL

Output Low Voltage(4)
except RESET pin

IOL = 20mA, VCC = 5V

IOL = 10mA, VCC = 3V

VOH

Output High Voltage(3)
except Reset pin

TA=85C

0.9

TA=105C

1.0

TA=85C

0.6

TA=105C

0.7

IOH = -20mA, VCC =
5V

TA=85C

4.2

TA=105C

4.1

IOH = -10mA, VCC =
3V

TA=85C

2.3

TA=105C

2.1

V

V

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Table 29-1.

Common DC characteristics TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol

Parameter

Condition

IIL

Input Leakage
Current I/O Pin

IIH

Input Leakage
Current I/O Pin

RRST

Reset Pull-up Resistor

RPU

I/O Pin Pull-up Resistor

VACIO

Analog Comparator
Input Offset Voltage

VCC = 5V
Vin = VCC/2

IACLK

Analog Comparator
Input Leakage Current

VCC = 5V
Vin = VCC/2

tACID

Analog Comparator
Propagation Delay

VCC = 2.7V
VCC = 4.0V

Notes:

Typ.

Max.

Units

VCC = 5.5V, pin low
(absolute value)

1

µA

VCC = 5.5V, pin high
(absolute value)

1

µA

30

60

k

20

50

k

40

mV

50

nA

<10
-50
750
500

ns

1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min.” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega48A/PA/88A/PA/168A/PA/328/P:
1] The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150mA.
2] The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150mA.
If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
4. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega48A/PA/88A/PA/168A/PA/328/P:
1] The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100mA.
2] The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA.
3] The sum of all IOL, for ports D0 - D4, RESET should not exceed 100mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.

29.2.1

ATmega48A DC Characteristics

Table 29-2.
Symbol

ATmega48A DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode(3)
Notes:

Min.

Typ.(2)

Max.

Units

Active 1MHz, VCC = 2V

0.2

0.55

mA

Active 4MHz, VCC = 3V

1.2

3.5

mA

Active 8MHz, VCC = 5V

4.0

12

mA

Idle 1MHz, VCC = 2V

0.03

0.5

mA

Idle 4MHz, VCC = 3V

0.21

1.5

mA

Idle 8MHz, VCC = 5V

0.9

5.5

mA

32kHz TOSC enabled, VCC = 1.8V

0.75

µA

32kHz TOSC enabled, VCC = 3V

0.9

µA

WDT enabled, VCC = 3V

3.9

15

µA

WDT disabled, VCC = 3V

0.1

2

µA

Condition

Min.

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C.

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3. The current consumption values include input leakage current.

29.2.2

ATmega48PA DC Characteristics – Current Consumption

Table 29-3.
Symbol

ATmega48PA DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

(3)

Power-down mode

Table 29-4.
Symbol

Max.

Active 1MHz, VCC = 2V

0.2

0.5

Active 4MHz, VCC = 3V

1.2

2.5

Active 8MHz, VCC = 5V

4.0

9

Idle 1MHz, VCC = 2V

0.03

0.15

Idle 4MHz, VCC = 3V

0.21

0.7

Idle 8MHz, VCC = 5V

0.9

2.7

32kHz TOSC enabled, VCC = 1.8V

0.75

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

3.9

8

WDT disabled, VCC = 3V

0.1

2

Min.

Units

mA

µA

ATmega48PA DC characteristics - TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode(3)
Notes:

Typ.(2)

Condition

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.22

0.55

Active 4MHz, VCC = 3V

1.15

2.65

Active 8MHz, VCC = 5V

4.1

9.5

Idle 1MHz, VCC = 2V

0.024

0.16

Idle 4MHz, VCC = 3V

0.2

0.75

Idle 8MHz, VCC = 5V

0.78

2.8

32kHz TOSC enabled, VCC= 1.8V

0.75

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

3.9

10

WDT disabled, VCC = 3V

0.1

5

Condition

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

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29.2.3

ATmega88A DC Characteristics

Table 29-5.
Symbol

ATmega88A DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode(3)
Notes:

Max.

Active 1MHz, VCC = 2V

0.2

0.55

Active 4MHz, VCC = 3V

1.2

3.5

Active 8MHz, VCC = 5V

4.1

12

Idle 1MHz, VCC = 2V

0.03

0.5

Idle 4MHz, VCC = 3V

0.18

1.5

Idle 8MHz, VCC = 5V

0.8

5.5

32kHz TOSC enabled, VCC = 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

3.9

15

WDT disabled, VCC = 3V

0.1

2

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

29.2.4

ATmega88PA DC Characteristics

Table 29-6.
Symbol

ATmega88PA DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.2

0.5

Active 4MHz, VCC = 3V

1.2

2.5

Active 8MHz, VCC = 5V

4.1

9

Idle 1MHz, VCC = 2V

0.03

0.15

Idle 4MHz, VCC = 3V

0.18

0.7

Idle 8MHz, VCC = 5V

0.8

2.7

32kHz TOSC enabled, VCC = 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

3.9

8

WDT disabled, VCC = 3V

0.1

2

Condition

Power Supply Current(1)

ICC
Power-save mode(3)

(3)

Power-down mode
Notes:

Typ.(2)

Condition

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

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Table 29-7.
Symbol

ATmega88PA DC characteristics - TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

(3)

Power-down mode
Notes:

Max.

Active 1MHz, VCC = 2V

0.2

0.6

Active 4MHz, VCC = 3V

1.2

2.75

Active 8MHz, VCC = 5V

4.1

10

Idle 1MHz, VCC = 2V

0.03

0.17

Idle 4MHz, VCC = 3V

0.18

0.8

Idle 8MHz, VCC = 5V

0.8

3

32kHz TOSC enabled, VCC= 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

3.9

10

WDT disabled, VCC = 3V

0.1

5

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

29.2.5

ATmega168A DC Characteristics

Table 29-8.
Symbol

ATmega168A DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode(3)
Notes:

Typ.(2)

Condition

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.2

0.55

Active 4MHz, VCC = 3V

1.2

3.5

Active 8MHz, VCC = 5V

4.2

12

Idle 1MHz, VCC = 2V

0.03

0.5

Idle 4MHz, VCC = 3V

0.2

1.5

Idle 8MHz, VCC = 5V

0.9

5.5

32kHz TOSC enabled, VCC = 1.8V

0.75

32kHz TOSC enabled, VCC = 3V

0.83

WDT enabled, VCC = 3V

4.1

15

WDT disabled, VCC = 3V

0.1

2

Condition

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

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29.2.6

ATmega168PA DC Characteristics

Table 29-9.
Symbol

ATmega168PA DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode
Notes:

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.2

0.5

Active 4MHz, VCC = 3V

1.2

2.5

Active 8MHz, VCC = 5V

4.2

9

Idle 1MHz, VCC = 2V

0.03

0.15

Idle 4MHz, VCC = 3V

0.2

0.7

Idle 8MHz, VCC = 5V

0.9

2.7

32kHz TOSC enabled, VCC = 1.8V

0.75

32kHz TOSC enabled, VCC = 3V

0.83

WDT enabled, VCC = 3V

4.1

8

WDT disabled, VCC = 3V

0.1

2

Condition

(3)

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

Table 29-10. ATmega168PA DC characteristics - TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Symbol

Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode
Notes:

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.3

0.6

Active 4MHz, VCC = 3V

1.8

2.75

Active 8MHz, VCC = 5V

6.7

10

Idle 1MHz, VCC = 2V

0.06

0.2

Idle 4MHz, VCC = 3V

0.4

0.8

Idle 8MHz, VCC = 5V

1.7

3

32kHz TOSC enabled, VCC = 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

4.6

10

WDT disabled, VCC = 3V

0.1

5

Condition

(3)

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

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29.2.7

ATmega328 DC Characteristics

Table 29-11. ATmega328 DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Symbol

Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode(3)
Notes:

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.3

0.55

Active 4MHz, VCC = 3V

1.7

3.5

Active 8MHz, VCC = 5V

5.2

12

Idle 1MHz, VCC = 2V

0.04

0.5

Idle 4MHz, VCC = 3V

0.3

1.5

Idle 8MHz, VCC = 5V

1.2

5.5

32kHz TOSC enabled, VCC = 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

4.2

15

WDT disabled, VCC = 3V

0.1

2

Condition

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

29.2.8

ATmega328P DC Characteristics

Table 29-12. ATmega328P DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)
Symbol

Parameter

Power Supply Current(1)

ICC
Power-save mode(3)

Power-down mode(3)
Notes:

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.3

0.5

Active 4MHz, VCC = 3V

1.7

2.5

Active 8MHz, VCC = 5V

5.2

9

Idle 1MHz, VCC = 2V

0.04

0.15

Idle 4MHz, VCC = 3V

0.3

0.7

Idle 8MHz, VCC = 5V

1.2

2.7

32kHz TOSC enabled, VCC = 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

4.2

8

WDT disabled, VCC = 3V

0.1

2

Condition

Min.

Units

mA

µA

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

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Table 29-13. ATmega328P DC characteristics - TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Symbol

Parameter

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.3

0.5

Active 4MHz, VCC = 3V

1.7

2.5

Active 8MHz, VCC = 5V

5.2

9.0

Idle 1MHz, VCC = 2V

0.04

0.15

Idle 4MHz, VCC = 3V

0.3

0.7

Idle 8MHz, VCC = 5V

1.2

2.7

32kHz TOSC enabled, VCC = 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

4.2

10

WDT disabled, VCC = 3V

0.1

5

Condition

Power Supply Current(1)

ICC
Power-save mode(3)

(3)

Power-down mode

Min.

Units

mA

Notes:

1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

29.3

Speed Grades

µA

Maximum frequency is dependent on VCC. As shown in Figure 29-1, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.
Figure 29-1. Maximum Frequency vs. VCC

20 MHz

10 MHz

Safe Operating Area
4 MHz

1.8V

2.7V

4.5V

5.5V

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29.4

Clock Characteristics

29.4.1

Calibrated Internal RC Oscillator Accuracy

Table 29-14. Calibration Accuracy of Internal RC Oscillator
Frequency

VCC

Temperature

Calibration Accuracy

Factory
Calibration

8.0MHz

3V

25C

±10%

User
Calibration

7.3 - 8.1MHz

1.8V - 5.5V

-40C - 85C

±1%

29.4.2

External Clock Drive Waveforms
Figure 29-2. External Clock Drive Waveforms

V IH1
V IL1

29.4.3

External Clock Drive

Table 29-15. External Clock Drive
VCC= 1.8 - 5.5V

VCC= 2.7 - 5.5V

VCC= 4.5 - 5.5V

Min.

Max.

Min.

Max.

Min.

Max.

Units

0

4

0

10

0

20

MHz

Symbol

Parameter

1/tCLCL

Oscillator Frequency

tCLCL

Clock Period

250

100

50

ns

tCHCX

High Time

100

40

20

ns

tCLCX

Low Time

100

40

20

ns

tCLCH

Rise Time

2.0

1.6

0.5

s

tCHCL

Fall Time

2.0

1.6

0.5

s

tCLCL

Change in period from
one clock cycle to the
next

2

2

2

%

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29.5

System and Reset Characteristics

Table 29-16. Reset, Brown-out and Internal Voltage Characteristics(1)
Symbol

Parameter
Power-on Reset Threshold Voltage (rising)

VPOT

Power-on Reset Threshold Voltage (falling)

SRON

Power-on Slope Rate

VRST

RESET Pin Threshold Voltage

tRST

Minimum pulse width on RESET Pin

(2)

Min.

Typ

Max

Units

1.1

1.4

1.6

V

0.6

1.3

1.6

V

0.01

10

V/ms

0.2 VCC

0.9 VCC

V

2.5

µs

Brown-out Detector Hysteresis

50

mV

tBOD

Min. Pulse Width on Brown-out Reset

2

µs

VBG

Bandgap reference voltage

VCC=2.7
TA=25°C

tBG

Bandgap reference start-up time

IBG

Bandgap reference current consumption

VHYST

Notes:

1.0

1.1

1.2

V

VCC=2.7
TA=25°C

40

70

µs

VCC=2.7
TA=25°C

10

µA

1. Values are guidelines only.
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

Table 29-17. BODLEVEL Fuse Coding(1)(2)
BODLEVEL 2:0 Fuses

Min. VBOT

111

Typ VBOT

Max VBOT

Units

BOD Disabled

110

1.7

1.8

2.0

101

2.5

2.7

2.9

100

4.1

4.3

4.5

V

011
010
Reserved
001
000
Notes:

1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is
tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to
a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 110, 101 and 100.
2. VBOT tested at 25C and 85C in production

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29.6

SPI Timing Characteristics
See Figure 29-3 and Figure 29-4 for details.
Table 29-18. SPI Timing Parameters
Description

Mode

1

SCK period

Master

See Table 19-5

2

SCK high/low

Master

50% duty cycle

3

Rise/Fall time

Master

3.6

4

Setup

Master

10

5

Hold

Master

10

6

Out to SCK

Master

0.5 • tsck

7

SCK to out

Master

10

8

SCK to out high

Master

10

9

SS low to out

Slave

15

10

SCK period

Slave

4 • tck

11

SCK high/low(1)

Slave

2 • tck

12

Rise/Fall time

Slave

13

Setup

Slave

10

14

Hold

Slave

tck

15

SCK to out

Slave

16

SCK to SS high

Slave

17

SS high to tri-state

Slave

18

SS low to SCK

Slave

Note:

Min.

Typ

Max

ns

1600

15
20
10
20

1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12MHz
- 3 tCLCL for fCK > 12MHz

Figure 29-3. SPI Interface Timing Requirements (Master Mode)
SS
6

1

SCK
(CPOL = 0)
2

2

SCK
(CPOL = 1)
4

MISO
(Data Input)

5

3

MSB

...

LSB
8

7

MOSI
(Data Output)

MSB

...

LSB

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Figure 29-4. SPI Interface Timing Requirements (Slave Mode)
SS
10

9

16

SCK
(CPOL = 0)
11

11

SCK
(CPOL = 1)
13

MOSI
(Data Input)

14

12

MSB

...

LSB

15

MISO
(Data Output)

MSB

17

...

LSB

X

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29.7

Two-wire Serial Interface Characteristics

Table 29-19 describes the requirements for devices connected to the 2-wire Serial Bus. The
ATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface meets or exceeds these requirements under the noted
conditions.
Timing symbols refer to Figure 29-5.
Table 29-19. Two-wire Serial Bus Requirements
Symbol

Parameter

VIL

Min.

Max

Units

Input Low-voltage

-0.5

0.3 VCC

V

VIH

Input High-voltage

0.7 VCC

VCC + 0.5

V

Vhys(1)

Hysteresis of Schmitt Trigger Inputs

0.05 VCC(2)

–

V

VOL(1)

Output Low-voltage

0

tr(1)

Output Fall Time from VIHmin to VILmax

tSP(1)

Spikes Suppressed by Input Filter

Ii

Input Current each I/O Pin

Ci(1)

Capacitance for each I/O Pin

Rp

SCL Clock Frequency

0.4

V

20 + 0.1Cb

(3)(2)

300

ns

20 + 0.1Cb

(3)(2)

250

ns

0

50(2)

ns

-10

10

µA

–

10

pF

0

400

kHz

fSCL  100kHz

V CC – 0,4V
--------------------------3mA

1000ns
----------------Cb



fSCL > 100kHz

V CC – 0,4V
--------------------------3mA

300ns
-------------Cb



fSCL  100kHz

4.0

–

µs

fSCL > 100kHz

0.6

–

µs

fSCL  100kHz

4.7

–

µs

fSCL > 100kHz

1.3

–

µs

fSCL  100kHz

4.0

–

µs

fSCL > 100kHz

0.6

–

µs

fSCL  100kHz

4.7

–

µs

fSCL > 100kHz

0.6

–

µs

fSCL  100kHz

0

3.45

µs

fSCL > 100kHz

0

0.9

µs

fSCL  100kHz

250

–

ns

fSCL > 100kHz

100

–

ns

fSCL  100kHz

4.0

–

µs

fSCL > 100kHz

0.6

–

µs

fSCL  100kHz

4.7

–

µs

fSCL > 100kHz

1.3

–

µs

(3)

10pF < Cb < 400pF

0.1VCC < Vi < 0.9VCC
fCK(4)

(5)

> max(16fSCL, 250kHz)

Value of Pull-up resistor

tHD;STA

Hold Time (repeated) START Condition

tLOW

Low Period of the SCL Clock

tHIGH

High period of the SCL clock

tSU;STA

Set-up time for a repeated START condition

tHD;DAT

Data hold time

tSU;DAT

Data setup time

tSU;STO

Setup time for STOP condition

tBUF

Bus free time between a STOP and START
condition

Notes:

3mA sink current

Rise Time for both SDA and SCL

tof(1)

fSCL

Condition

1. In ATmega48A/PA/88A/PA/168A/PA/328/P, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100kHz.

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3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement.

Figure 29-5. Two-wire Serial Bus Timing
tof

tHIGH

tLOW

tr
tLOW

SCL
tSU;STA
SDA

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

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29.8

ADC Characteristics

Table 29-20. ADC Characteristics
Symbol

Parameter

Condition

Min.

Resolution

VIN

Units
Bits

VREF = 4V, VCC = 4V,
ADC clock = 200kHz

2

LSB

VREF = 4V, VCC = 4V,
ADC clock = 1MHz

4.5

LSB

VREF = 4V, VCC = 4V,
ADC clock = 200kHz
Noise Reduction Mode

2

LSB

VREF = 4V, VCC = 4V,
ADC clock = 1MHz
Noise Reduction Mode

4.5

LSB

Integral Non-Linearity (INL)

VREF = 4V, VCC = 4V,
ADC clock = 200kHz

0.5

LSB

Differential Non-Linearity
(DNL)

VREF = 4V, VCC = 4V,
ADC clock = 200kHz

0.25

LSB

Gain Error

VREF = 4V, VCC = 4V,
ADC clock = 200kHz

2

LSB

Offset Error

VREF = 4V, VCC = 4V,
ADC clock = 200kHz

2

LSB

Conversion Time

Free Running Conversion

Clock Frequency

VREF

Max

10

Absolute accuracy (Including
INL, DNL, quantization error,
gain and offset error)

AVCC(1)

Typ

Analog Supply Voltage
Reference Voltage
Input Voltage

13

260

µs

50

1000

kHz

VCC - 0.3

VCC + 0.3

V

1.0

AVCC

V

GND

VREF

V

Input Bandwidth

38.5

VINT

Internal Voltage Reference

RREF

Reference Input Resistance

32

k

RAIN

Analog Input Resistance

100

M

Note:

1.0

1.1

kHz
1.2

V

1. AVCC absolute min./max: 1.8V/5.5V

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29.9

Parallel Programming Characteristics
Table 29-21. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol

Parameter

Min.

VPP

Programming Enable Voltage

11.5

IPP

Programming Enable Current

tDVXH

Data and Control Valid before XTAL1 High

67

ns

tXLXH

XTAL1 Low to XTAL1 High

200

ns

tXHXL

XTAL1 Pulse Width High

150

ns

tXLDX

Data and Control Hold after XTAL1 Low

67

ns

tXLWL

XTAL1 Low to WR Low

0

ns

tXLPH

XTAL1 Low to PAGEL high

0

ns

tPLXH

PAGEL low to XTAL1 high

150

ns

tBVPH

BS1 Valid before PAGEL High

67

ns

tPHPL

PAGEL Pulse Width High

150

ns

tPLBX

BS1 Hold after PAGEL Low

67

ns

tWLBX

BS2/1 Hold after WR Low

67

ns

tPLWL

PAGEL Low to WR Low

67

ns

tBVWL

BS1 Valid to WR Low

67

ns

tWLWH

WR Pulse Width Low

150

ns

tWLRL

WR Low to RDY/BSY Low
(1)

WR Low to RDY/BSY High

tWLRH

(2)

Units

12.5

V

250

A

1

s

3.7

4.5

ms

7.5

9

ms

WR Low to RDY/BSY High for Chip Erase

tXLOL

XTAL1 Low to OE Low

0

tBVDV

BS1 Valid to DATA valid

0

tOLDV
tOHDZ
1.
2.

Max

0

tWLRH_CE

Notes:

Typ

ns
250

ns

OE Low to DATA Valid

250

ns

OE High to DATA Tri-stated

250

ns

tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
tWLRH_CE is valid for the Chip Erase command.

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Figure 29-6. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL

XTAL1
tDVXH

tXLDX

Data & Contol
(DATA, XA0/1, BS1, BS2)
tPLBX t BVWL

tBVPH
PAGEL

tWLBX

tPHPL
tWLWH

WR

tPLWL
WLRL

RDY/BSY
tWLRH

Figure 29-7. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)

LOAD DATA LOAD DATA
(HIGH BYTE)

LOAD DATA
(LOW BYTE)

tXLPH

t XLXH

LOAD ADDRESS
(LOW BYTE)

tPLXH

XTAL1

BS1
PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0
XA1

Note:

1. The timing requirements shown in Figure 29-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.

Figure 29-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing
Requirements(1)
LOAD ADDRESS
(LOW BYTE)

READ DATA
(LOW BYTE)

READ DATA
(HIGH BYTE)

LOAD ADDRESS
(LOW BYTE)

tXLOL

XTAL1
tBVDV

BS1
tOLDV

OE

DATA

tOHDZ

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 29-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.

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30.

Electrical Characteristics (TA = -40°C to 105°C)

30.1

Absolute Maximum Ratings*
*NOTICE:

Operating Temperature . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground. . . . . . . . . . -0.5V to VCC+0.5V

Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these
or other conditions beyond those indicated in
the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Voltage on RESET with respect to Ground-0.5V to +13.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . . 6.0V
DC Current per I/O Pin. . . . . . . . . . . . . . . . . . . 40.0mA
DC Current VCC and GND Pins . . . . . . . . . . . 200.0mA

30.2

DC Characteristics

Symbol

Parameter

Condition

Min.

VIL

Input Low Voltage, except
XTAL1 and RESET pin

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

-0.5
-0.5

0.2VCC(1)
0.3VCC(1)

VIH

Input High Voltage, except
XTAL1 and RESET pins

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

0.7VCC(2)
0.6VCC(2)

VCC + 0.5
VCC + 0.5

VIL1

Input Low Voltage,
XTAL1 pin

VCC = 1.8V - 5.5V

-0.5

0.1VCC(1)

VIH1

Input High Voltage,
XTAL1 pin

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

0.8VCC(2)
0.7VCC(2)

VCC + 0.5
VCC + 0.5

VIL2

Input Low Voltage,
RESET pin

VCC = 1.8V - 5.5V

-0.5

0.1VCC(1)

VIH2

Input High Voltage,
RESET pin

VCC = 1.8V - 5.5V

0.9VCC(2)

VCC + 0.5

VIL3

Input Low Voltage,
RESET pin as I/O

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

-0.5
-0.5

0.2VCC(1)
0.3VCC(1)

VIH3

Input High Voltage,
RESET pin as I/O

VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V

0.7VCC(2)
0.6VCC(2)

VCC + 0.5
VCC + 0.5

Output Low Voltage(4)

IOL = 20mA, VCC = 5V
IOL = 10mA, VCC = 3V

VOL

VOH

except RESET pin
Output High Voltage(4)
except Reset pin

Typ.

Max.

Units

V

IOH = -20mA, VCC = 5V
IOH = -10mA, VCC = 3V

0.9
0.6
4.2
2.3

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Symbol

Parameter

Condition

Min.

Typ.

Max.

IIL

Input Leakage
Current I/O Pin

VCC = 5.5V, pin low
(absolute value)

IIH

Input Leakage
Current I/O Pin

VCC = 5.5V, pin high
(absolute value)

RRST

Reset Pull-up Resistor

30

60

RPU

I/O Pin Pull-up Resistor

20

50

VACIO

Analog Comparator
Input Offset Voltage

VCC = 5V
Vin = VCC/2

IACLK

Analog Comparator
Input Leakage Current

VCC = 5V
Vin = VCC/2

tACID

Analog Comparator
Propagation Delay

VCC = 2.7V
VCC = 4.0V

Units

1
µA

Notes:

1.
2.
3.

4.

1

<10
-50

k

40

mV

50

nA

750
500

ns

“Max” means the highest value where the pin is guaranteed to be read as low
“Min.” means the lowest value where the pin is guaranteed to be read as high
Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following
must be observed:
ATmega168P:
1] The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100mA
2] The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA
3] The sum of all IOL, for ports D0 - D4, RESET should not exceed 100mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition
Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
ATmega168P:
1] The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150mA
2] The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150mA
If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition

30.2.1 ATmega48PA DC Characteristics – Current Consumption
Symbol

Parameter

Power Supply Current(1)

ICC

Power-save mode(3)

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.22

0.55

Active 4MHz, VCC = 3V

1.15

2.65

Active 8MHz, VCC = 5V

4.1

9.5

Idle 1MHz, VCC = 2V

0.024

0.16

Idle 4MHz, VCC = 3V

0.2

0.75

Idle 8MHz, VCC = 5V

0.78

2.8

WDT enabled, VCC = 3V

3.9

8.5

WDT disabled, VCC = 3V

0.1

3

Condition

Min.

Units

mA

32kHz TOSC enabled, VCC= 1.8V
32kHz TOSC enabled, VCC = 3V

Power-down mode(3)
Notes:

1.
2.
3.

µA

Values with “Minimizing Power Consumption” enabled (0xFF)
Typical values at 25°C. Maximum values are test limits in production
The current consumption values include input leakage current

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30.2.2 ATmega88PA DC Characteristics – Current Consumption
Symbol

Parameter

Power Supply Current(1)

ICC

Power-save mode(3)

Power-down mode(3)
Notes:

1.
2.
3.

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.2

0.6

Active 4MHz, VCC = 3V

1.2

2.75

Active 8MHz, VCC = 5V

4.1

10

Idle 1MHz, VCC = 2V

0.03

0.17

Idle 4MHz, VCC = 3V

0.18

0.8

Idle 8MHz, VCC = 5V

0.8

3

32kHz TOSC enabled, VCC= 1.8V

0.8

32kHz TOSC enabled, VCC = 3V

0.9

WDT enabled, VCC = 3V

3.9

8.8

WDT disabled, VCC = 3V

0.1

4

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.3

0.6

Active 4MHz, VCC = 3V

1.8

2.75

Active 8MHz, VCC = 5V

6.7

10

Idle 1MHz, VCC = 2V

0.06

0.2

Idle 4MHz, VCC = 3V

0.4

0.8

Idle 8MHz, VCC = 5V

1.7

3

32kHz TOSC enabled, VCC = 1.8V

0.8

2.2

32kHz TOSC enabled, VCC = 3V

0.9

2.9

WDT enabled, VCC = 3V

4.6

8.8

WDT disabled, VCC = 3V

0.1

2.2

Condition

Min.

Units

mA

µA

Values with “Minimizing Power Consumption” enabled (0xFF)
Typical values at 25°C. Maximum values are test limits in production
The current consumption values include input leakage current

30.2.3 ATmega168P DC Characteristics – Current Consumption
Symbol

Parameter

Power Supply Current(1)

ICC

Power-save mode(3)(4)

Power-down mode(3)
Notes:

1.
2.
3.
4.

Condition

Min.

Units

mA

µA

Values with “Minimizing Power Consumption” enabled (0xFF)
Typical values at 25C. Maximum values are test limits in production
The current consumption values include input leakage current
Maximum values are characterized values and not test limits in production

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30.2.4 ATmega328P DC Characteristics – Current Consumption
Symbol

Parameter

Power Supply Current(1)

ICC

Power-save mode(3)(4)

Power-down mode(3)
Notes:

1.
2.
3.
4.

Typ.(2)

Max.

Active 1MHz, VCC = 2V

0.3

0.5

Active 4MHz, VCC = 3V

1.7

2.5

Active 8MHz, VCC = 5V

5.2

9.0

Idle 1MHz, VCC = 2V

0.04

0.15

Idle 4MHz, VCC = 3V

0.3

0.7

Idle 8MHz, VCC = 5V

1.2

2.7

32kHz TOSC enabled, VCC = 1.8V

0.8

1.6

32kHz TOSC enabled, VCC = 3V

0.9

2.6

WDT enabled, VCC = 3V

4.2

8.0

WDT disabled, VCC = 3V

0.1

2.0

Condition

Min.

Units

mA

µA

Values with “Minimizing Power Consumption” enabled (0xFF)
Typical values at 25C. Maximum values are test limits in production
The current consumption values include input leakage current
Maximum values are characterized values and not test limits in production

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31. Typical Characteristics – (TA = -40°C to 85°C)
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
square wave generator with rail-to-rail output is used as clock source.
All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the
corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements.
The ”ATmega88PA: Supply Current of IO Modules” on page 405 and page 455 shows the additional current consumption compared to ICC Active and ICC Idle for every I/O module controlled by the Power Reduction Register.
See ”Power Reduction Register” on page 41 for details.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

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Active Supply Current
Figure 31-1. ATmega48A: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
1

5.5 V
0.8

5.0 V
4.5 V

ICC (mA)

31.1.1

ATmega48A Typical Characteristics

0.6

4.0 V
3.3 V

0.4

2.7 V
0.2

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-2. ATmega48A: Active Supply Current vs. Frequency (1-20MHz
12

5.5V

10

5.0V
8
ICC (mA)

31.1

4.5V

6

4.0V
4

3.3V

2

2.7V
1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

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Figure 31-3. ATmega48A: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.14

85 °C
-40 °C
25 °C

0.12

ICC (mA)

0.1
0.08
0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-4. ATmega48A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.2

85 °C
25 °C
-40 °C

1

ICC (mA)

0.8

0.6

0.4

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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Figure 31-5. ATmega48A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
85 °C
25 °C
-40 °C

5

ICC (mA)

4

3

2

1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-6. ATmega48A: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.16

5.5 V
0.14

ICC (mA)

31.1.2

0.12

5.0 V

0.1

4.5 V

0.08

4.0 V

0.06

3.3 V

0.04

2.7 V
1.8 V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

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Figure 31-7. ATmega48A: Idle Supply Current vs. Frequency (1-20MHz)
3

5.5 V

2.5

5.0 V
ICC (mA)

2

4.5 V

1.5

4.0 V
1

3.3 V

0.5

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-8. ATmega48A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.042

85 °C

0.035

25 °C

ICC (mA)

0.028

-40 °C
0.021

0.014

0.007

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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Figure 31-9. ATmega48A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.35

85 °C
25 °C
-40 °C

0.3

ICC (mA)

0.25
0.2
0.15
0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-10. ATmega48A: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
85 °C
25 °C
-40 °C

1.2

1

ICC (mA)

0.8

0.6

0.4

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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31.1.3

ATmega48A: Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-1.
PRR bit

ATmega48PA: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

2.9uA

20.7µA

97.4µA

PRTWI

6.0µA

44.8µA

219.7µA

PRTIM2

5.0µA

34.5µA

141.3µAµA

PRTIM1

3.6µA

24.4µA

107.7µA

PRTIM0

1.4µA

9.5µA

38.4µA

PRSPI

5.0µA

38.0µA

190.4µA

PRADC

6.1µA

47.4µA

244.7µA

Table 31-2.

ATmega48PA: Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption
compared to Active with external
clock (see Figure 31-48 on page
350 and Figure 31-49 on page
350)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-53 on page
352 and Figure 31-54 on page
353)

PRUSART0

1.8%

11.4%

PRTWI

3.9%

20.6%

PRTIM2

2.9%

15.7%

PRTIM1

2.1%

11.2%

PRTIM0

0.8%

4.2%

PRSPI

3.3%

17.6%

PRADC

4.2%

22.1%

It is possible to calculate the typical current consumption based on the numbers from Table 31-2 on page 330 for
other VCC and frequency settings than listed in Table 31-1 on page 330.
31.1.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-4 on page 355, third column, we see that we need to add 11.2% for the TIMER1, 22.1%
for the ADC, and 17.6% for the SPI module. Reading from Figure 31-53 on page 352, we find that the idle current
consumption is ~0.028 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1,
ADC, and SPI enabled, gives:
I CC total  0.028 mA  (1 + 0.112 + 0.221 + 0.176)  0.042 mA

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Power-down Supply Current
Figure 31-11. ATmega48A: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1.2

85 °C
1

ICC (uA)

0.8

0.6

0.4

-40 °C
25 °C

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-12. ATmega48A: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
8

-40 °C
85 °C
25 °C
6

ICC (uA)

31.1.4

4

2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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31.1.5

Power-save Supply Current
Figure 31-13. ATmega48A: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING
2

85 °C

ICC (uA)

1.6

25 °C

1.2

-40 °C
0.8

0.4

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-14. ATmega48A: Standby Supply Current vs. Vcc (Watchdog Timer Disabled
0.16

6MHz_xtal
6MHz_res

0.14
0.12

4MHz_res
4MHz_xtal

0.1
ICC (mA)

31.1.6

0.08

2MHz_res
2MHz_xtal

0.06

450kHz_res
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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Pin Pull-Up
Figure 31-15. ATmega48A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
50

IOP (uA)

40

30

20

10

25 °C
85 °C
-40 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VOP (V)

Figure 31-16. ATmega48A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
70
60
50
IOP (uA)

31.1.7

40
30
20

25 °C
85 °C
-40 °C

10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

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Figure 31-17. ATmega48A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
140
120

IOP (uA)

100
80
60
40

25 °C
85 °C
-40 °C

20
0
0

1

2

3

4

5

VOP (V)

Figure 31-18. ATmega48A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V))
35
30

IRESET (uA)

25
20
15
10

25 °C
5

-40 °C
85 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

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Figure 31-19. ATmega48A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V)
60

50

IRESET (uA)

40

30

20

25 °C
-40 °C
85 °C

10

0
0

0.5

1

1.5

2

2.5

3

VRESET (V)

Figure 31-20. ATmega48A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (uA)

80

60

40

20

25 °C
-40 °C
85 °C

0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

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Pin Driver Strength
Figure 31-21. ATmega48A: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V)
1

85 °C
0.8

25 °C
0.6
VOL (V)

-40 °C

0.4

0.2

0
0

4

8

12

16

20

IOL (mA)

Figure 31-22. ATmega48A: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V)

VOL (V)

31.1.8

0.6

85 °C

0.5

25 °C

0.4

-40 °C

0.3

0.2

0.1

0
0

4

8

12

16

20

IOL (mA)

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Figure 31-23. ATmega48A: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V)
3.5
3

VOH (V)

2.5

-40 °C
25 °C
85 °C

2
1.5
1
0.5
0
0

4

8

12

16

20

IOH (mA)

Figure 31-24. ATmega48A: I/O Pin Output Voltage vs. Source Current (VCC = 5 V)
5
4.9
4.8

VOH (V)

4.7
4.6

-40 °C

4.5

25 °C
4.4

85 °C

4.3
4.2
0

4

8

12

16

20

IOH (mA)

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Pin Threshold and Hysteresis
Figure 31-25. ATmega48A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3

-40 °C
25 °C
85 °C

2.5

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-26. ATmega48A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

85 °C
25 °C
-40 °C

2

Threshold (V)

31.1.9

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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Figure 31-27. ATmega48A: I/O Pin Input Hysteresis vs. VCC
0.6

25 °C
85 °C
-40 °C

Input Hysteresis (V)

0.5

0.4

0.3

0.2

0.1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-28. ATmega48A: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1)’
-40 °C
25 °C
85 °C

2.5

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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Figure 31-29. )ATmega48A: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

85 °C
25 °C
-40 °C

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-30. ATmega48A: Reset Pin Input Hysteresis vs. VCC
0.7
0.6

Input Hysteresis (V)

0.5
0.4
0.3
0.2

85 °C
25 °C
-40 °C

0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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BOD Threshold
Figure 31-31. ATmega48A: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)
1.85

Rising Vcc
1.84

Threshold (V)

1.83

1.82

Falling Vcc
1.81

1.8

1.79
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-32. ATmega48A: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)
2.76

Rising Vcc
2.74
2.72
Threshold (V)

31.1.10

2.7
2.68

Falling Vcc

2.66
2.64
2.62
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

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Figure 31-33. ATmega48A: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)
4.36

Rising Vcc
4.34

Threshold (V)

4.32

4.3

4.28

Falling Vcc
4.26

4.24
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-34. ATmega48A: Bandgap Voltage vs. VCC
1.104

Bandgap Voltage (V)

1.102

85 °C

1.1

25 °C
1.098
1.096

-40 °C
1.094
1.092
1.09
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

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Internal Oscillator Speed
Figure 31-35. ATmega48A: Watchdog Oscillator Frequency vs. Temperature
116

114

FRC (kHz)

112

110

2.7 V
3.3 V
4.0 V
5.5 V

108

106

104
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-36. ATmega48A: Watchdog Oscillator Frequency vs. VCC
118

116

FRC (kHz)

31.1.11

114

-40 °C

112

25 °C

110

108

85 °C
106
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

343

Figure 31-37. ATmega48A: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.2

85 °C
8.1

FRC (MHz)

8

25 °C
7.9

7.8

-40 °C

7.7

7.6
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-38. ATmega48A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.2

3.3 V
5.5 V
1.8 V

8.1

FRC (MHz)

8

7.9

7.8

7.7

7.6
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

344

Figure 31-39. ATmega48A: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
16

85 °C
25 °C
-40 °C

14

FRC (MHz)

12
10
8
6
4
2
0
0

16

32

48

64

80

96

112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

Current Consumption of Peripheral Units
Figure 31-40. ATmega48A: ADC Current vs. VCC (AREF = AVCC)
350

-40 °C
25 °C
85 °C

300
250
ICC (uA)

31.1.12

200
150
100
50
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

345

Figure 31-41. ATmega48A: Analog Comparator Current vs. VCC
90

-40 °C
25 °C
85 °C

80
70

ICC (uA)

60
50
40
30
20
10
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-42. ATmega48A: AREF External Reference Current vs. VCC
160

85 °C
25 °C
-40 °C

140
120

ICC (uA)

100
80
60
40
20
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

346

Figure 31-43. ATmega48A Brownout Detector Current vs. VCC
40

ICC (uA)

32

85 °C
25 °C
-40 °C

24

16

8

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-44. ATmega48A: Programming Current vs. VCC
6

-40 °C
5

25 °C

ICC (mA)

4

3

85 °C

2

1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

347

Current Consumption in Reset and Reset Pulsewidth
Figure 31-45. ATmega48A: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz)

ICC (mA)

0.14
0.12

5.5 V

0.1

5.0 V

0.08

4.5 V
4.0 V

0.06

3.3 V
0.04

2.7 V

0.02

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-46. ATmega48A: Reset Supply Current vs. Frequency (1 - 20MHz)
2.5

5.5 V
2

5.0 V
4.5 V

ICC (mA)

31.1.13

1.5

4.0 V
1

3.3 V
0.5

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

348

Figure 31-47. ATmega48A: Minimum Reset Pulse width vs. VCC
1600
1400

Pulsewidth (ns)

1200
1000
800
600
400

85 °C
25 °C
-40 °C

200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

349

Active Supply Current
Figure 31-48. ATmega48PA: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
0.16

ICC (mA)

31.2.1

ATmega48PA Typical Characteristics

0.14

5.5V

0.12

5.0V

0.1

4.5V

0.08

4.0V

0.06

3.3V

0.04

2.7V
1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-49. ATmega48PA: Active Supply Current vs. Frequency (1-20MHz)
11

5.5V

10
9

5.0V

8

4.5V

7
ICC (mA)

31.2

6

4.0V

5
4

3.3V

3

2.7V

2
1

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

350

Figure 31-50. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05

105°C

0.045

85°C

0.04

ICC (mA)

0.035
0.03

25°C

0.025

-40°C

0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-51. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
105°C
85°C
25°C
-40°C

1.2
1.1
1

ICC (mA)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

351

Figure 31-52. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
5.5

105°C
85°C
25°C
-40°C

5
4.5

ICC (mA)

4
3.5
3
2.5
2
1.5
1
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-53. ATmega48PA: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.16

ICC (mA)

31.2.2

0.14

5.5V

0.12

5.0V

0.1

4.5V

0.08

4.0V

0.06

3.3V

0.04

2.7V
1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

352

Figure 31-54. ATmega48PA: Idle Supply Current vs. Frequency (1-20MHz)
2.6

5.5V

2.4
2.2

5.0V

2

4.5V

1.8
ICC (mA)

1.6
1.4

4.0V

1.2
1
0.8

3.3V

0.6

2.7V

0.4
0.2

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-55. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05

105°C

0.045

85°C

0.04

ICC (mA)

0.035
0.03

25°C
-40°C

0.025
0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

353

Figure 31-56. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.33

105°C
85°C
25°C
-40°C

ICC (mA)

0.28

0.23

0.18

0.13

0.08
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-57. ATmega48PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
1.3

105°C
85°C
25°C
-40°C

1.2
1.1
1
ICC (mA)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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354

31.2.3

ATmega48PA: Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-3.
PRR bit

ATmega48PA: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

2.9µA

20.7µA

97.4µA

PRTWI

6.0µA

44.8µA

219.7µA

PRTIM2

5.0µA

34.5µA

141.3µA

PRTIM1

3.6µA

24.4µA

107.7µA

PRTIM0

1.4µA

9.5µA

38.4µA

PRSPI

5.0µA

38.0µA

190.4µA

PRADC

6.1µA

47.4µA

244.7µA

Table 31-4.

ATmega48PA: Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption
compared to Active with external
clock (see Figure 31-48 on page
350 and Figure 31-49 on page
350)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-53 on page
352 and Figure 31-54 on page
353)

PRUSART0

1.8%

11.4%

PRTWI

3.9%

20.6%

PRTIM2

2.9%

15.7%

PRTIM1

2.1%

11.2%

PRTIM0

0.8%

4.2%

PRSPI

3.3%

17.6%

PRADC

4.2%

22.1%

It is possible to calculate the typical current consumption based on the numbers from Table 31-4 on page 355 for
other VCC and frequency settings than listed in Table 31-3 on page 355.
31.2.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-4 on page 355, third column, we see that we need to add 11.2% for the TIMER1, 22.1%
for the ADC, and 17.6% for the SPI module. Reading from Figure 31-53 on page 352, we find that the idle current
consumption is ~0.028 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1,
ADC, and SPI enabled, gives:
I CC total  0.028 mA  (1 + 0.112 + 0.221 + 0.176)  0.042 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

355

Power-down Supply Current
Figure 31-58. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
2.7

105°C

2.4
2.1

ICC (µA)

1.8
1.5
1.2
0.9

85°C
-40°C

0.6
0.3

25°C
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-59. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
9

105°C

8.5
8

-40°C
85°C
25°C

7.5
7
6.5
ICC (µA)

31.2.4

6
5.5
5
4.5
4
3.5
3
2.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

356

31.2.5

Power-save Supply Current
Figure 31-60. ATmega48PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
2.5
2.25

105°C

2

Icc [µA]

1.75
1.5

85°C

1.25
1
0.75

25°C

0.5

-40°C

0.25
0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc [V]

Standby Supply Current
Figure 31-61. ATmega48PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
6MHz_xtal
6MHz_res

150
135
120

4MHz_res
4MHz_xtal

105
90
ICC (µA)

31.2.6

2MHz_res
2MHz_xtal

75
60

1MHz_res
450kHz_res

45
30
15
0.0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

357

Pin Pull-Up
Figure 31-62. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
45
40
35

IOP (µA)

30
25
20
15
10

105°C
-40°C
25°C
85°C

5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VOP (V)

Figure 31-63. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
70
60
50

IOP (µA)

31.2.7

40
30
20

25°C
85°C
-40°C
105°C

10
0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

358

Figure 31-64. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

120
105

IOP (µA)

90
75
60
45
30

25°C
85°C
105°C
-40°C

15
0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VOP (V)

Figure 31-65. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
35
30

IRESET (µA)

25
20
15
10

25°C
-40°C
105°C
85°C

5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

359

Figure 31-66. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
52
48
44
40

IRESET (µA)

36
32
28
24
20
16
12

25°C
-40°C
85°C
105°C

8
4
0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VRESET (V)

Figure 31-67. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
110
100
90
80
IRESET (µA)

70
60
50
40
30

85°C
25°C
-40°C
105°C

20
10
0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

360

Pin Driver Strength
Figure 31-68. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1

105°C
85°C

0.9
0.8

25°C

0.7

VOL (V)

0.6

-40°C
0.5
0.4
0.3
0.2
0.1
0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

Figure 31-69. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.65

105°C
85°C

0.6
0.55
0.5

25°C

0.45

-40°C

0.4
VOL (V)

31.2.8

0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

361

Figure 31-70. ATmega48PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V)
3
2.9
2.8
2.7

VOH (V)

2.6
2.5
2.4

-40°C

2.3
2.2

25°C

2.1
2

85°C
105°C

1.9
0

2

4

6

8

10

12

14

16

18

20

IOH (mA)

Figure 31-71. ATmega48PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5
4.9

VOH (V)

4.8
4.7
4.6

-40°C
4.5

25°C
4.4

85°C
105°C

4.3
0

2

4

6

8

10

12

14

16

18

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

362

Pin Threshold and Hysteresis
Figure 31-72. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

105°C
85°C
-40°C
25°C

2.9
2.6

Threshold (V)

2.3
2
1.7
1.4
1.1
0.8
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-73. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

105°C
-40°C
85°C
25°C

2.4
2.1
1.8
Threshold (V)

31.2.9

1.5
1.2
0.9
0.6
0.3
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

363

Figure 31-74. ATmega48PA: I/O Pin Input Hysteresis vs. VCC
0.6

-40 °C

25°C
85°C
105°C
-40°C

Input Hysteresis (mV)

0.55
0.5
0.45

25 °C

0.4

85 °C

0.35
0.3

105 °C

0.25
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-75. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

105°C
85°C
-40°C
25°C

2.45

Threshold (V)

2.2

1.95

1.7

1.45

1.2

-40°C
25°C
85°C

105°C

0.95
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

364

Figure 31-76. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

-40°C
105°C
85°C
25°C

2.4
2.2

Threshold (V)

2
1.8
1.6
1.4
1.2
1
0.8
0.6
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-77. ATmega48PA: Reset Pin Input Hysteresis vs. VCC
0.65
0.6

-40°C

0.55

Input Hysteresis (mV)

0.5
0.45

25°C

0.4
0.35
0.3

85°C

0.25
0.2
0.15

105°C
85°C
105°C
25°C
-40°C

0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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365

BOD Threshold
Figure 31-78. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.825
1.82

Rising Vcc

1.815

Threshold (V)

1.81
1.805
1.8
1.795
1.79

Falling Vcc

1.785
1.78
1.775
1.77
1.765
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 31-79. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.76
2.75

Rising Vcc

2.74
2.73
Threshold (V)

31.2.10

2.72
2.71
2.7
2.69
2.68
Falling Vcc

2.67
2.66
2.65
2.64
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

366

Figure 31-80. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.34
4.32

Rising Vcc

Threshold (V)

4.3
4.28
4.26

Falling Vcc
4.24
4.22
4.2
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

Temperature (°C)

Figure 31-81. ATmega48PA: Bandgap Voltage vs. VCC
1.1325
1.13

Bandgap Voltage [V]

1.1275

105°C
85°C

1.125

25°C

1.1225
1.12
1.1175
1.115

-40°C

1.1125
1.11

1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc [V]

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

367

Internal Oscillator Speed
Figure 31-82. ATmega48PA: Watchdog Oscillator Frequency vs. Temperature
116

114

FRC (kHz)

112

110

108

2.7V
3.3V
4.0V
5.5V

106

104
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

Temperature (°C)

Figure 31-83. ATmega48PA: Watchdog Oscillator Frequency vs. VCC
116

FRC (kHz)

31.2.11

114

-40°C

112

25°C

110

108

85°C
106

105°C

104
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

368

Figure 31-84. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.25
8.2

105°C

8.15

85°C

8.1

FRC (MHz)

8.05
8

25°C

7.95
7.9
7.85
7.8
7.75

-40°C

7.7
7.65
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-85. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature

4.0V
3.0V
5.5V

8.2
8.15

1.8V

8.1
8.05
FRC (MHz)

8
7.95
7.9
7.85
7.8
7.75
7.7
7.65
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

369

Figure 31-86. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value

85°C
25°C
105°C
-40°C

15
14
13
12
FRC (MHz)

11
10
9
8
7
6
5
4
0

16

32

48

64

80

96

112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

Current Consumption of Peripheral Units
Figure 31-87. ATmega48PA: ADC Current vs. VCC (AREF = AVCC)

-40°C
25°C
85°C
105°C

310
290
270
250
ICC (µA)

31.2.12

230
210
190
170
150
130
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

370

Figure 31-88. ATmega48PA: Analog Comparator Current vs. VCC
90

-40°C

85
80

25°C
85°C
105°C

75

ICC (µA)

70
65
60
55
50
45

105°C
85°C
25°C
35 -40°C
40

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-89. ATmega48PA: AREF External Reference Current vs. VCC

105°C
85°C
25°C
-40°C

150
140
130
120

ICC (µA)

110
100
90
80
70
60
50
40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

371

Figure 31-90. ATmega48PA: Brownout Detector Current vs. VCC
26
25

105°C
85°C

24
23

25°C
-40°C

ICC (µA)

22
21
20
19
18
17
16
15
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-91. ATmega48PA: Programming Current vs. VCC
5.5

-40°C

5

25°C

4.5

ICC (mA)

4
3.5
3

85°C
105°C

2.5
2
1.5
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

372

Current Consumption in Reset and Reset Pulsewidth
Figure 31-92. ATmega48PA: Reset Supply Current vs. Low Frequency (0.1MHz- 1.0MHz)
0.13

5.5V

0.12
0.11

5.0V

0.1
0.09

4.5V

ICC (mA)

0.08
0.07

4.0V

0.06
0.05

3.3V

0.04

2.7V

0.03

1.8V

0.02
0.01
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-93. ATmega48PA: Reset Supply Current vs. Frequency (1MHz- 20MHz)
2.4

5.5V

2.2

5.0V

2
1.8

4.5V

1.6
ICC (mA)

31.2.13

1.4

4.0V

1.2
1
0.8

3.3V

0.6

2.7V

0.4
0.2

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

373

Figure 31-94. ATmega48PA: Minimum Reset Pulse width vs. VCC
1600
1500
1400
1300

Pulsewidth (ns)

1200
1100
1000
900
800
700
600
500
400
300
200
1.5

2

2.5

3

3.5

4

4.5

5

105°C
85°C
25°C
-40°C

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

374

Active Supply Current
Figure 31-95. ATmega88A: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
1

5.5 V
0.8

5.0 V
4.5 V

ICC (mA)

31.3.1

ATmega88A Typical Characteristics

0.6

4.0 V
3.3 V

0.4

2.7 V
0.2

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-96. ATmega88A: Active Supply Current vs. Frequency (1 - 20MHz)
12

5.5 V

10

5.0 V
8
ICC (mA)

31.3

4.5 V

6

4.0 V
4

3.3 V
2.7 V

2

1.8 V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

375

Figure 31-97. ATmega88A: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.12

-40 °C
25 °C
85 °C

ICC (mA)

0.09

0.06

0.03

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-98. ATmega88A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.2

85 °C
25 °C

1

-40 °C

ICC (mA)

0.8

0.6

0.4

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

376

Figure 31-99. ATmega88A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
85 °C
25 °C

5

-40 °C

ICC (mA)

4

3

2

1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-100.ATmega88A: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.15

5.5 V
0.12

5.0 V
ICC (mA)

31.3.2

0.09

4.5 V
4.0 V

0.06

3.3 V
2.7 V

0.03

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

377

Figure 31-101.ATmega88A: Idle Supply Current vs. Frequency (1-20MHz)
2.5

5.5 V
2

ICC (mA)

5.0 V
4.5 V

1.5

4.0 V
1

3.3 V
0.5

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-102.ATmega88A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.04

85 °C

ICC (mA)

0.03

25 °C
-40 °C
0.02

0.01

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

378

Figure 31-103.ATmega88A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.35

85 °C
25 °C
-40 °C

0.3

ICC (mA)

0.25
0.2
0.15
0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-104.ATmega88A: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
1.2

85 °C
25 °C
-40 °C

ICC (mA)

0.9

0.6

0.3

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

379

31.3.3

ATmega88A: Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-5.
PRR bit

ATmega88PA: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

3.0µA

21.3µA

97.9µA

PRTWI

6.1µA

45.4µA

219.0µA

PRTIM2

5.2µA

35.2µA

149.5µA

PRTIM1

3.8µA

25.6µA

110.0µA

PRTIM0

1.5µA

9.8µA

39.6µA

PRSPI

5.2µA

40.0µA

199.6µA

PRADC

6.3µA

48.7µA

247.0µA

Table 31-6.

ATmega88PA: Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption
compared to Active with external
clock (see Figure 31-142 on page
399 and Figure 31-143 on page
400)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-147 on page
402 and Figure 31-148 on page
402)

PRUSART0

1.8%

11.4%

PRTWI

3.9%

24.4%

PRTIM2

2.9%

18.6%

PRTIM1

2.1%

13.6%

PRTIM0

0.8%

5.2%

PRSPI

3.5%

21.5%

PRADC

4.2%

26.3%

It is possible to calculate the typical current consumption based on the numbers from Table 31-8 on page 405 for
other VCC and frequency settings than listed in Table 31-7 on page 405.
31.3.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-8 on page 405, third column, we see that we need to add 13.6% for the TIMER1, 26.3%
for the ADC, and 21.5% for the SPI module. Reading from Figure 31-147 on page 402, we find that the idle current
consumption is ~0.027 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1,
ADC, and SPI enabled, gives:
I CC total  0.027 mA  (1 + 0.136 + 0.263 + 0.215)  0.043 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

380

Power-down Supply Current
Figure 31-105.ATmega88A: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1.6

85 °C

1.4
1.2

ICC (uA)

1
0.8
0.6
0.4

25 °C

0.2

-40 °C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-106.ATmega88A: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
8

85 °C
-40 °C
25 °C

6

ICC (uA)

31.3.4

4

2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

381

31.3.5

Power-save Supply Current
Figure 31-107.ATmega88A: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
3

2.5

85 °C

ICC (uA)

2

-40 °C

1.5

25 °C
1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-108.ATmega88A: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.18

6MHz_res
6MHz_xtal

0.16
0.14
0.12
ICC (mA)

31.3.6

4MHz_res
4MHz_xtal

0.1
0.08

2MHz_res
2MHz_xtal

0.06

450kHz_res

0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

382

Pin Pull-Up
Figure 31-109.ATmega88A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
50

IOP (uA)

40

30

20

10

25 °C
-40 °C
85 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VOP (V)

Figure 31-110.ATmega88A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
80
70
60
50
IOP (uA)

31.3.7

40
30
20

25 °C

10

-40 °C
85 °C

0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

383

Figure 31-111.ATmega88A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
140
120

IOP (uA)

100
80
60
40

25 °C
85 °C
-40 °C

20
0
0

1

2

3

4

5

VOP (V)

Figure 31-112.ATmega88A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V)
40
35

IRESET (uA)

30
25
20
15
10

25 °C

5

-40 °C
85 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

384

Figure 31-113.ATmega88A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V)
60

50

IRESET (uA)

40

30

20

25 °C
-40 °C
85 °C

10

0
0

0.5

1

1.5

2

2.5

3

VRESET (V)

Figure 31-114.ATmega88A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V)
120

100

IRESET (uA)

80

60

40

25 °C
-40 °C
85 °C

20

0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

385

Pin Driver Strength
Figure 31-115.ATmega88A: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V)
1

85 °C
0.8

25 °C
VOL (V)

0.6

-40 °C
0.4

0.2

0
0

4

8

12

16

20

IOL (mA)

Figure 31-116.ATmega88A: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V)
0.6

85 °C
0.5

25 °C
0.4
VOL (V)

31.3.8

-40 °C

0.3

0.2

0.1

0
0

4

8

12

16

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

386

Figure 31-117.ATmega88A: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V)
3.5
3

VOH (V)

2.5

-40 °C
25 °C
85 °C

2
1.5
1
0.5
0
0

4

8

12

16

20

IOH (mA)

Figure 31-118.)ATmega88A: I/O Pin Output Voltage vs. Source Current (VCC = 5 V)
5
4.9
4.8

VOH (V)

4.7
4.6

-40 °C
4.5

25 °C

4.4

85 °C

4.3
4.2
0

4

8

12

16

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

387

Pin Threshold and Hysteresis
Figure 31-119.ATmega88A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
85 °C
-40 °C
25 °C

3

2.5

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-120.ATmega88A: I/O Pin Input Threshold
, Voltage vs. VCC (VIL, I/O Pin read as ‘0’
-40 °C
85 °C
25 °C

2.5

2

Threshold (V)

31.3.9

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

388

Figure 31-121.ATmega88A: I/O Pin Input Hysteresis vs. VCC
0.6

25 °C
85 °C
-40 °C

Input Hysteresis (V)

0.5

0.4

0.3

0.2

0.1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-122.ATmega88A: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
-40 °C

1.5

25 °C
85 °C

Threshold (V)

1.2

0.9

0.6

0.3

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

389

Figure 31-123.ATmega88A: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

85 °C
25 °C
-40 °C

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-124.ATmega88A: Reset Pin Input Hysteresis vs. VCC
0.6

Input Hysteresis (V)

0.5

0.4

0.3

0.2

85 °C
25 °C
-40 °C

0.1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

390

BOD Threshold
Figure 31-125.ATmega88A: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)
1.83

Rising Vcc

1.82

Threshold (V)

1.81

1.8

1.79

Falling Vcc
1.78

1.77
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

80

90

Temperature (°C)

Figure 31-126.ATmega88A: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)
2.76

Rising Vcc
2.74

2.72
Threshold (V)

31.3.10

2.7

Falling Vcc

2.68

2.66

2.64
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

391

Figure 31-127.ATmega88A: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)
4.34

Rising Vcc

4.32

Threshold (V)

4.3

4.28

Falling Vcc

4.26

4.24

4.22
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-128.ATmega88A: Bandgap Voltage vs. VCC
1.103

Bandgap Voltage (V)

1.102
1.101
1.1

25 °C
1.099
1.098

-40 °C
85 °C

1.097
1.096
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

392

Internal Oscillator Speed
Figure 31-129.ATmega88A: Watchdog Oscillator Frequency vs. Temperature
114
113
112

FRC (kHz)

111
110
109
108

2.7 V
3.3 V
4.0 V
5.5 V

107
106
105
-40

-20

0

20

40

60

80

100

Temperature (°C)

Figure 31-130.ATmega88A: Watchdog Oscillator Frequency vs. VCC
116

114

-40 °C
112
FRC (kHz)

31.3.11

25 °C

110

108

106

85 °C

104
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

393

Figure 31-131.ATmega88A: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.3

85 °C
8.2

FRC (MHz)

8.1

25 °C

8
7.9

-40 °C
7.8
7.7
7.6
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-132.ATmega88A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.3

5.5 V
4.0 V

8.2

FRC (MHz)

3.0 V
8.1

8

7.9

7.8
-40

-20

0

20

40

60

80

100

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

394

Figure 31-133.ATmega88A: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
14

85 °C
25 °C
-40 °C

12

FRC (MHz)

10
8
6
4
2
0
0

16

32

48

64

80

96

112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

Current Consumption of Peripheral Units
Figure 31-134.ATmega88A: ADC Current vs. VCC (AREF = AVCC)
-40 °C
25 °C
85 °C

300

250

200
ICC (uA)

31.3.12

150

100

50

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

395

Figure 31-135.ATmega88A: Analog Comparator Current vs. VCC
90

-40 °C
25 °C
85 °C

80
70

ICC (uA)

60
50
40
30
20
10
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-136.ATmega88A: AREF External Reference Current vs. VCC
85 °C
25 °C
-40 °C

160
140
120

ICC (uA)

100
80
60
40
20
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

396

Figure 31-137.ATmega88A: Brownout Detector Current vs. VCC
50

ICC (uA)

40

30

85 °C
25 °C
20

-40 °C

10

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-138.ATmega88A: Programming Current vs. VCC
8

-40 °C
25 °C

7
6

85 °C

ICC (mA)

5
4
3
2
1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

397

Current Consumption in Reset and Reset Pulsewidth
Figure 31-139.ATmega88A: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz)
0.12

5.5 V
0.1

5.0 V
ICC (mA)

0.08

4.5 V
4.0 V

0.06

3.3 V
0.04

2.7 V
1.8 V

0.02

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-140.ATmega88A: Reset Supply Current vs. Frequency (1 - 20MHz)
2

5.5 V
5.0 V

1.6

4.5 V
ICC (mA)

31.3.13

1.2

4.0 V
0.8

3.3 V
0.4

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

398

Figure 31-141.ATmega88A: Minimum Reset Pulse width vs. VCC
1600
1400

Pulsewidth (ns)

1200
1000
800
600
400

85 °C
25 °C
-40 °C

200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

31.4.1

ATmega88PA Typical Characteristics
Active Supply Current
Figure 31-142.ATmega88PA: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
0.14

5.5V

0.12

5.0V

0.1

ICC (mA)

31.4

4.5V

0.08

4.0V
0.06

3.3V
2.7V

0.04

1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

399

Figure 31-143.ATmega88PA: Active Supply Current vs. Frequency (1 - 20MHz)
12

5.5V

10

5.0V
ICC (mA)

8

4.5V

6

4.0V
4

3.3V
2.7V

2

1.8V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-144.ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.14

105°C

0.12

-40°C
25°C

0.1

ICC (mA)

85°C
0.08
0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

400

Figure 31-145.ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.4

105°C
85°C
25°C
-40°C

1.2

ICC (mA)

1
0.8
0.6
0.4
0.2
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-146.ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
6

105°C
85°C
25°C
-40°C

5

ICC (mA)

4

3

2

1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

401

Idle Supply Current
Figure 31-147.ATmega88PA: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.15

5.5 V
0.12

ICC (mA)

5.0 V
0.09

4.5 V
4.0 V

0.06

3.3 V
2.7 V

0.03

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-148.ATmega88PA: Idle Supply Current vs. Frequency (1 - 20MHz)
2.5

5.5 V
2

5.0 V
ICC (mA)

31.4.2

4.5 V

1.5

4.0 V
1

3.3 V
0.5

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

402

Figure 31-149.ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05
0.045

105°C

0.04

ICC (mA)

0.035

85°C

0.03

25°C
-40°C

0.025
0.02
0.015
0.01
0.005
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-150.ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.4

105°C

ICC (mA)

0.35
0.3

85°C
25°C

0.25

-40°C

0.2
0.15
0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

403

Figure 31-151.ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
1.2

105°C
85°C
25°C

1

-40°C
ICC (mA)

0.8

0.6

0.4

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

404

31.4.3

ATmega88PA: Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-7.
PRR bit

ATmega88PA: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

3.0µA

21.3µA

97.9µA

PRTWI

6.1µA

45.4µA

219.0µA

PRTIM2

5.2µA

35.2µA

149.5µA

PRTIM1

3.8µA

25.6µA

110.0µA

PRTIM0

1.5µA

9.8µA

39.6µA

PRSPI

5.2µA

40.0µA

199.6µA

PRADC

6.3µA

48.7µA

247.0µA

Table 31-8.

ATmega88PA: Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption
compared to Active with external
clock (see Figure 31-142 on page
399 and Figure 31-143 on page
400)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-147 on page
402 and Figure 31-148 on page
402)

PRUSART0

1.8%

11.4%

PRTWI

3.9%

24.4%

PRTIM2

2.9%

18.6%

PRTIM1

2.1%

13.6%

PRTIM0

0.8%

5.2%

PRSPI

3.5%

21.5%

PRADC

4.2%

26.3%

It is possible to calculate the typical current consumption based on the numbers from Table 31-8 for other VCC and
frequency settings than listed in Table 31-7.
31.4.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-8, third column, we see that we need to add 13.6% for the TIMER1, 26.3% for the ADC,
and 21.5% for the SPI module. Reading from Figure 31-147 on page 402, we find that the idle current consumption
is ~0.027 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI
enabled, gives:
I CC total  0.027 mA  (1 + 0.136 + 0.263 + 0.215)  0.043 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

405

Power-down Supply Current
Figure 31-152.ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
5

105°C

ICC (µA)

4

3

2

85°C
1

25°C
-40°C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-153.ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
12

10

105°C
8

ICC (µA)

31.4.4

-40°C
6

25°C
4

85°C
2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

406

31.4.5

Power-save Supply Current
Figure 31-154.ATmega88PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
6

105°C

ICC (µA)

4

85°C

2

25°C
-40°C
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-155.ATmega88PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.18

6MHz_res
6MHz_xtal

0.16
0.14
0.12
ICC (mA)

31.4.6

4MHz_res
4MHz_xtal

0.1
0.08

2MHz_res
2MHz_xtal

0.06

450kHz_res

0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

407

Pin Pull-Up
Figure 31-156.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
60

50

IOP (µA)

40

30

20

25°C
10

-40°C

0

85°C
105°C
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VOP (V)

Figure 31-157.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60
50

IOP (µA)

31.4.7

40
30

25°C

20

-40°C
85°C
105°C

10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

408

Figure 31-158.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
160
140
120

IOP (µA)

100
80
60

25°C

40

-40°C
85°C
105°C

20
0
0

1

2

3

4

5

6

VOP (V)

Figure 31-159.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
40
35

IRESET (µA)

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

409

Figure 31-160.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
60

50

IRESET (µA)

40

30

20

25°C
-40°C
85°C
105°C

10

0
0

0.5

1

1.5

2

2.5

3

VRESET (V)

Figure 31-161.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (µA)

80

60

40

25°C
-40°C
85°C
105°C

20

0
0

1

2

3

4

5

6

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

410

Pin Driver Strength
Figure 31-162.ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1.2

1

105°C
85°C
VOL (V)

0.8

25°C
0.6

-40°C
0.4

0.2

0
0

5

10

15

20

25

IOL (mA)

Figure 31-163.ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.7
0.6

105°C

85°C

0.5

25°C
VOL (V)

31.4.8

0.4

-40°C

0.3
0.2
0.1
0
0

5

10

15

20

25

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

411

Figure 31-164.ATmega88PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V)
3.5

VOH (V)

3

2.5

-40°C
25°C
85°C
105°C

2

1.5
0

5

10

15

20

25

IOH (mA)

Figure 31-165.ATmega88PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5.2

5

VOH (V)

4.8

4.6

-40°C
25°C

4.4

85°C
105°C

4.2
0

5

10

15

20

25

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

412

Pin Threshold and Hysteresis
Figure 31-166.ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3.5

105°C
85°C
25°C
-40°C

3

Threshold (V)

2.5
2
1.5
1
0.5
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-167.ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

2

Threshold (V)

31.4.9

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

413

Figure 31-168.ATmega88PA: I/O Pin Input Hysteresis vs. VCC
0.7

Input Hysteresis (mV)

0.6

-40°C

0.5

25°C
0.4

85°C
0.3

105°C

0.2
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-169.ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
2.5

Threshold (V)

2

1.5

1

-40°C
25°C
85°C
105°C

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

414

Figure 31-170.ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

4

4.5

5

5.5

VCC (V)

Figure 31-171.ATmega88PA: Reset Pin Input Hysteresis vs. VCC
0.7
0.6

Input Hysteresis (mV)

-40°C
0.5

25°C

0.4
0.3

85°C
0.2

105°C
0.1
0
1.5

2

2.5

3

3.5
VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

415

BOD Threshold
Figure 31-172.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.84
1.83

Rising Vcc
Threshold (V)

1.82
1.81
1.8
1.79
1.78

Falling Vcc

1.77
1.76
-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 31-173.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.8

Rising Vcc

2.78
2.76
2.74

Threshold (V)

31.4.10

2.72
2.7
2.68

Falling Vcc

2.66
2.64
2.62
2.6
-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

416

Figure 31-174.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.5
4.45
4.4

Rising Vcc

Threshold (V)

4.35
4.3
4.25

Falling Vcc

4.2
4.15
4.1
4.05
4
-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 31-175.ATmega88PA: Calibrated Bandgap Voltage vs. Temperature
1.09

1.8V
2.7V
3.3V
4.0V
4.5V
5.5V

1.085

Bandgap Voltage [V]

1.08
1.075
1.07
1.065
1.06
1.055
1.05
1.045

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature [V]

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

417

Figure 31-176.ATmega88PA: Bandgap Voltage vs. VCC
1.09
1.085

105°C
85°C

Bandgap Voltage [V]

1.08
1.075

25°C
1.07
1.065
1.06
1.055

-40°C

1.05
1.045
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc [V]

Internal Oscillator Speed
Figure 31-177.ATmega88PA: Watchdog Oscillator Frequency vs. Temperature
116
114
112

FRC (kHz)

31.4.11

110
108

2.7V
3.3V
4.0V

106
104

5.5V

102
-40

-20

0

20

40

60

80

100

120

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

418

Figure 31-178.ATmega88PA: Watchdog Oscillator Frequency vs. VCC
116
114

-40°C

FRC (kHz)

112

25°C

110
108
106

85°C

104

105°C

102
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-179.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.5

105°C
85°C

FRC (MHz)

8.25

25°C
8

-40°C
7.75

7.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

419

Figure 31-180.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.4

5.5V
4.0V
3.0V

8.3

FRC (MHz)

8.2

1.8V

8.1
8
7.9
7.8
7.7
7.6
-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 31-181.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value

FRC (MHz)

14
12

105°C
85°C

10

25°C
-40°C

8
6
4
2
0
0

16

32

48

64

80

96

112

128

144

160

176

192

208

224

240

256

OSCCAL (X1)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

420

Current Consumption of Peripheral Units
Figure 31-182.ATmega88PA: ADC Current vs. VCC (AREF = AVCC)
350

-40°C
300

25°C
85°C
105°C

ICC (µA)

250
200
150
100
50
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

4

4.5

5

5.5

VCC (V)

Figure 31-183.ATmega88PA: Analog Comparator Current vs. VCC
90
80
70
60

ICC (µA)

31.4.12

105°C

50
40
30

85°C
25°C
-40°C

20
10
0
1.5

2

2.5

3

3.5
VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

421

Figure 31-184.ATmega88PA: AREF External Reference Current vs. VCC
160

105°C
85°C
25°C
-40°C

140
120

ICC (µA)

100
80
60
40
20
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

4

4.5

5

5.5

VCC (V)

Figure 31-185.ATmega88PA: Brownout Detector Current vs. VCC
30

25

ICC (µA)

20

15

105°C
85°C
25°C
-40°C

10

5

0
1.5

2

2.5

3

3.5
VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

422

Figure 31-186.ATmega88PA: Programming Current vs. VCC
10
9
8

-40°C

ICC (mA)

7
6
5

25°C

4

85°C

3

105°C

2
1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Current Consumption in Reset and Reset Pulsewidth
Figure 31-187.ATmega88PA: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.12

5.5V
0.1

5.0V
0.08

ICC (mA)

31.4.13

4.5V
4.0V

0.06

3.3V
0.04

1.8V

0.02

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

423

Figure 31-188.ATmega88PA: Reset Supply Current vs. Frequency (1MHz - 20MHz)
2.5

2

5.5V

ICC (mA)

5.0V
1.5

4.5V
4.0V

1

3.3V
0.5

2.7V
1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-189.ATmega88PA: Minimum Reset Pulse width vs. VCC
1800
1600

Pulsewidth (ns)

1400
1200
1000
800
600

105°C
85°C
25°C
-40°C

400
200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

424

Active Supply Current
Figure 31-190.ATmega168A: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
1

5.5 V
0.8

5.0 V
4.5 V

ICC (mA)

31.5.1

ATmega168A Typical Characteristics

0.6

4.0 V
3.3 V

0.4

2.7 V
0.2

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-191.ATmega168A: Active Supply Current vs. Frequency (1-20MHz)
12

5.5 V

10

5.0 V
8
ICC (mA)

31.5

4.5 V

6

4.0 V
4

3.3 V
2.7 V

2

1.8 V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

425

Figure 31-192.ATmega168A: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.15

-40 °C
85 °C
25 °C

ICC (mA)

0.12

0.09

0.06

0.03

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-193.ATmega168A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.2

85 °C
25 °C
-40 °C

1

ICC (mA)

0.8

0.6

0.4

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

426

Figure 31-194.ATmega168A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
85 °C
25 °C
-40 °C

5

ICC (mA)

4

3

2

1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-195.ATmega168A: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.15

5.5 V
0.12

ICC (mA)

31.5.2

5.0 V
4.5 V

0.09

4.0 V
0.06

3.3 V
2.7 V

0.03

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

427

Figure 31-196.ATmega168A: Idle Supply Current vs. Frequency (1-20MHz)
3

5.5 V

2.5

5.0 V
ICC (mA)

2

4.5 V
1.5

4.0 V

1

3.3 V
0.5

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-197.IATmega168A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.04

85 °C
0.035
0.03

25 °C
-40 °C

ICC (mA)

0.025
0.02
0.015
0.01
0.005
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

428

Figure 31-198.ATmega168A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.3

85 °C
25 °C
-40 °C

0.25

ICC (mA)

0.2

0.15

0.1

0.05

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-199.ATmega168A: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
1.2

85 °C
25 °C
-40 °C

ICC (mA)

0.9

0.6

0.3

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

429

31.5.3

ATmega168A Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-9.
PRR bit

ATmega168A: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

2.86µA

20.3µA

52.2µA

PRTWI

6.00µA

44.1µA

122.0µA

PRTIM2

4.97µA

33.2µA

79.8µA

PRTIM1

3.50µA

23.0µA

55.3µA

PRTIM0

1.43µA

9.2µA

21.4µA

PRSPI

5.01µA

38.6µA

111.4µA

PRADC

6.34µA

45.7µA

123.6µA

Table 31-10. ATmega168A: Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption
compared to Active with external
clock (see Figure 31-237 on page
450 and Figure 31-238 on page
450)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-242 on page
452 and Figure 31-243 on page
453)

PRUSART0

1.5%

8.9%

PRTWI

3.2%

19.5%

PRTIM2

2.4%

14.8%

PRTIM1

1.7%

10.3%

PRTIM0

0.7%

4.1%

PRSPI

2.9%

17.1%

PRADC

3.4%

20.3%

It is possible to calculate the typical current consumption based on the numbers from Table 31-12 on page 455 for
other VCC and frequency settings than listed in Table 31-11 on page 455.
31.5.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-12 on page 455, third column, we see that we need to add 10.3% for the TIMER1,
20.3% for the ADC, and 17.1% for the SPI module. Reading from Figure 31-242 on page 452, we find that the idle
current consumption is ~0.027 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with
TIMER1, ADC, and SPI enabled, gives:
I CC total  0.027 mA  (1 + 0.103 + 0.203 + 0.171)  0.040 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

430

Power-down Supply Current
Figure 31-200.ATmega168A: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1

85 °C

ICC (uA)

0.8

0.6

0.4

0.2

25 °C
-40 °C
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-201.ATmega168A: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
8

-40 °C
85 °C
25 °C

6

ICC (uA)

31.5.4

4

2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

431

31.5.5

Power-save Supply Current
Figure 31-202.ATmega168A: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
2.5

85 °C
2

ICC (uA)

1.5

-40 °C
25 °C

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-203.ATmega168A: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
6MHz_xtal
6MHz_res

0.14
0.12

4MHz_res
4MHz_xtal

0.1
ICC(mA)

31.5.6

0.08

2MHz_res
2MHz_xtal
450kHz_res
1MHz_res

0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

432

Pin Pull-Up
Figure 31-204.ATmega168A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
50

IOP (uA)

40

30

20

10

25 °C
-40 °C
85 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VOP (V)

Figure 31-205.ATmega168A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
80
70
60
50
IOP (uA)

31.5.7

40
30
20

25 °C

10

-40 °C
85 °C

0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

433

Figure 31-206.ATmega168A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
160
140
120

IOP (uA)

100
80
60
40

25 °C

20

-40 °C
85 °C

0
0

1

2

3

4

5

6

VOP (V)

Figure 31-207.ATmega168A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V)
40
35

IRESET (uA)

30
25
20
15
10

25 °C

5

-40 °C
85 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

434

Figure 31-208.ATmega168A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V)
60

50

IRESET (uA)

40

30

20

25 °C
-40 °C
85 °C

10

0
0

0.5

1

1.5

2

2.5

3

VRESET (V)

Figure 31-209.ATmega168A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (uA)

80

60

40

25 °C
-40 °C
85 °C

20

0
0

1

2

3

4

5

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

435

Pin Driver Strength
Figure 31-210.ATmega168A: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V)
1

85 °C
0.8

25 °C
VOL (V)

0.6

-40 °C
0.4

0.2

0
0

4

8

12

16

20

IOL (mA)

Figure 31-211.ATmega168A: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V)
0.6

85 °C
0.5

25 °C
-40 °C

0.4
VOL (V)

31.5.8

0.3

0.2

0.1

0
0

4

8

12

16

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

436

Figure 31-212.ATmega168A: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V)
3.5
3

VOH (V)

2.5

-40 °C
25 °C
85 °C

2
1.5
1
0.5
0
0

4

8

12

16

20

IOH (mA)

Figure 31-213.ATmega168A: I/O Pin Output Voltage vs. Source Current (VCC = 5 V)
5

VOH (V)

4.8

4.6

-40 °C
25 °C
85 °C

4.4

4.2

4
0

4

8

12

16

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

437

Pin Threshold and Hysteresis
Figure 31-214.ATmega168A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3

85 °C
25 °C
-40 °C

2.5

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-215.ATmega168A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
85 °C
25 °C
-40 °C

2.5

2

Threshold (V)

31.5.9

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

438

Figure 31-216.ATmega168A: I/O Pin Input Hysteresis vs. VCC
85 °C
25 °C
-40 °C

0.6

Input Hysteresis (V)

0.5

0.4

0.3

0.2

0.1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-217.ATmega168A: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
85 °C
-40 °C
25 °C

1.5

Threshold (V)

1.2

0.9

0.6

0.3

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

439

Figure 31-218.ATmega168A: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
-40 °C
85 °C
25 °C

2.5

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-219.ATmega168A: Reset Pin Input Hysteresis vs. VCC
0.7
0.6

Input Hysteresis (V)

0.5
0.4
0.3
0.2

85 °C
0.1

25 °C
-40 °C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

440

BOD Threshold
Figure 31-220.ATmega168A: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)
1.86
1.84

Rising Vcc
Threshold (V)

1.82
1.8

Falling Vcc
1.78
1.76
1.74
1.72
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-221.ATmega168A: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)
2.76

Rising Vcc

2.74
2.72
Threshold (V)

31.5.10

2.7
2.68

Falling Vcc
2.66
2.64
2.62
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

441

Figure 31-222.ATmega168A: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)
4.34
4.32

Rising Vcc

Threshold (V)

4.3
4.28
4.26

Falling Vcc

4.24
4.22
4.2
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-223.ATmega168A: Bandgap Voltage vs. VCC
1.135
1.133

Bandgap Voltage (V)

1.131
1.129

85 °C

1.127

25 °C

1.125
1.123
1.121
1.119

-40 °C

1.117
1.115
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

442

Internal Oscillator Speed
Figure 31-224.ATmega168A: Watchdog Oscillator Frequency vs. Temperature
121

FRC (kHz)

119

117

115

2.7 V
113

3.3 V
5.5 V

111
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 31-225.ATmega168A: Watchdog Oscillator Frequency vs. VCC
122

120

-40 °C
118
FRC (kHz)

31.5.11

25 °C

116

114

112

85 °C

110
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

443

Figure 31-226.ATmega168A: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8,4

85 °C
8.2

FRC (MHz)

25 °C
8

7.8

-40 °C

7.6

7.4
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-227.ATmega168A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.3

5.5 V
5.0 V
2.7 V

8.2

FRC (MHz)

8.1

1.8 V

8
7.9
7.8
7.7
7.6
7.5
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

444

Figure 31-228.ATmega168A: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
16

85 °C
25 °C

14

-40 °C

FRC (MHz)

12
10
8
6
4
2
0
0

16

32

48

64

80

96

112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

Current Consumption of Peripheral Units
Figure 31-229.ATmega168A: ADC Current vs. VCC (AREF = AVCC)
350

-40 °C
25 °C
85 °C

300

ICC (uA)

31.5.12

250

200

150

100
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

445

Figure 31-230.ATmega168A: Analog Comparator Current vs. VCC
90

-40 °C
25 °C
85 °C

80

ICC (uA)

70

60

50

40

30
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-231.ATmega168A: AREF External Reference Current vs. VCC
180

25 °C

160

85 °C
-40 °C

140

ICC (uA)

120
100
80
60
40
20
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

446

Figure 31-232.ATmega168A: Brownout Detector Current vs. VCC
26

85 °C

24

25 °C

ICC (uA)

22

-40 °C

20
18
16
14
12
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-233.ATmega168A: Programming Current vs. VCC

ICC (mA)

10

8

-40 °C
25 °C

6

85 °C

4

2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

447

Current Consumption in Reset and Reset Pulsewidth
Figure 31-234.ATmega168A: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz)
0.12

5.5 V
0.1

5.0 V
ICC (mA)

0.08

4.5 V
4.0 V

0.06

3.3 V

0.04

2.7 V
1.8 V

0.02

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-235.ATmega168A: Reset Supply Current vs. Frequency (1 - 20MHz)
2.5

5.5 V

2

5.0 V
ICC (mA)

31.5.13

4.5 V

1.5

4.0 V
1

3.3 V
0.5

2.7 V
1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

448

Figure 31-236.ATmega168A: Minimum Reset Pulse width vs. VCC
1750
1500

Pulsewidth (ns)

1250
1000
750
500

85 °C
25 °C
-40 °C

250
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

449

Active Supply Current
Figure 31-237.ATmega168PA: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
1

5.5V

0.9

ICC (mA)

31.6.1

ATmega168PA Typical Characteristics

0.8

5.0V

0.7

4.5V

0.6

4.0V

0.5
0.4

3.3V

0.3

2.7V

0.2

1.8V

0.1
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-238.ATmega168PA: Active Supply Current vs. Frequency (1-20MHz)
12

5.5V
10

5.0V
8
ICC (mA)

31.6

4.5V

6

4.0V
3.6V

4

2.7V

2

1.8V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

450

Figure 31-239.ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.14

105°C
-40°C
85°C
25°C

0.12

ICC (mA)

0.1

0.08

0.06

0.04

0.02
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-240.ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.2

105°C
85°C
25°C
-40°C

1.1
1

ICC (mA)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

451

Figure 31-241.ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
5.5

105°C
85°C
25°C
-40°C

5
4.5

ICC (mA)

4
3.5
3
2.5
2
1.5
1
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-242.ATmega168PA: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.16

5.5V

0.14

5.0V

0.12

ICC (mA)

31.6.2

0.1

4.5V

0.08

4.0V
3.6V

0.06

2.7V

0.04

1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

452

Figure 31-243.ATmega168PA: Idle Supply Current vs. Frequency (1-20MHz)
12

5.5V
10

5.0V

ICC (mA)

8

4.5V

6

4.0V
3.6V

4

2.7V

2

1.8V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-244.ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.045

105°C

0.04

85°C
0.035

ICC (mA)

0.03

25°C
-40°C

0.025
0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

453

Figure 31-245.ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.3

105°C
85°C
25°C
-40°C

0.27
0.24

ICC (mA)

0.21
0.18
0.15
0.12
0.09
0.06
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-246.ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
1.3

105°C
85°C
25°C
-40°C

1.1

ICC (mA)

0.9

0.7

0.5

0.3

0.1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

454

31.6.3

ATmega168PA Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-11. ATmega168PA: Additional Current Consumption for the different I/O modules (absolute values)
PRR bit

Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

2.86µA

20.3µA

52.2µA

PRTWI

6.00µA

44.1µA

122.0µA

PRTIM2

4.97µA

33.2µA

79.8µA

PRTIM1

3.50µA

23.0µA

55.3µA

PRTIM0

1.43µA

9.2µA

21.4µA

PRSPI

5.01µA

38.6µA

111.4µA

PRADC

6.34µA

45.7µA

123.6µA

Table 31-12. ATmega168PA: Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption
compared to Active with external
clock (see Figure 31-237 on page
450 and Figure 31-238 on page
450)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-242 on page
452 and Figure 31-243 on page
453)

PRUSART0

1.5%

8.9%

PRTWI

3.2%

19.5%

PRTIM2

2.4%

14.8%

PRTIM1

1.7%

10.3%

PRTIM0

0.7%

4.1%

PRSPI

2.9%

17.1%

PRADC

3.4%

20.3%

It is possible to calculate the typical current consumption based on the numbers from Table 31-12 on page 455 for
other VCC and frequency settings than listed in Table 31-11 on page 455.
31.6.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-12 on page 455, third column, we see that we need to add 10.3% for the TIMER1,
20.3% for the ADC, and 17.1% for the SPI module. Reading from Figure 31-242 on page 452, we find that the idle
current consumption is ~0.027 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with
TIMER1, ADC, and SPI enabled, gives:
I CC total  0.02 mA  (1 + 0.103 + 0.203 + 0.171)  0.04 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

455

Power-down Supply Current
Figure 31-247.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
2.4

105°C

2.1
1.8

ICC (µA)

1.5
1.2
0.9

85°C

0.6
0.3

25°C
-40°C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-248.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
9

105°C

8

-40°C
85°C
25°C

7
ICC (µA)

31.6.4

6

5

4

3
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

456

31.6.5

Power-save Supply Current
Figure 31-249.ATmega168PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
4

105°C
3.5

ICC (µA)

3
2.5

85°C
2
1.5

-40°C
25°C

1
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-250.ATmega168PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
6MHz_xtal
6MHz_res

0.14
0.12

4MHz_res
4MHz_xtal

0.1
ICC(mA)

31.6.6

0.08

2MHz_res
2MHz_xtal
450kHz_res
1MHz_res

0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

457

Pin Pull-Up
Figure 31-251.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
50
45
40

IOP (µA)

35
30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VOP (V)

Figure 31-252.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60
50
IOP (µA)

31.6.7

40
30

25°C
85°C
-40°C
105°C

20
10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

458

Figure 31-253.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
140
120

IOP (µA)

100
80
60
40

25°C
85°C
-40°C
105°C

20
0
0

1

2

3

4

5

VOP (V)

Figure 31-254.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 1.8V)
40
35

IRESET (µA)

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

459

Figure 31-255.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 2.7V)
60

50

IRESET (µA)

40

30

20

25°C
-40°C
85°C
105 C

10

0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VRESET (V)

Figure 31-256.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (µA)

80

60

40

25°C
-40°C
85°C
105°C

20

0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

460

Pin Driver Strength
Figure 31-257.ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1

105°C
85°C

0.9
0.8

VOL (V)

0.7

25°C

0.6

-40°C

0.5
0.4
0.3
0.2
0.1
0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

Figure 31-258.ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.6

105°C
85°C

0.5

25°C
-40°C

0.4
VOL (V)

31.6.8

0.3

0.2

0.1

0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

461

Figure 31-259.ATmega168PA: I/O Pin Output Voltage vs. Source Current (VCC = 3V)
3.1
2.9

VOH (V)

2.7
2.5

-40°C

2.3

25°C
2.1

85°C
105°C

1.9
1.7
0

5

10

15

20

IOH (mA)

Figure 31-260.ATmega168PA I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5
4.9

VOH (V)

4.8
4.7
4.6

-40°C
4.5

25°C
85°C
105°C

4.4
4.3
0

5

10

15

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

462

Pin Threshold and Hysteresis
Figure 31-261.ATmega168PA I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3

105°C
85°C
25°C
-40°C

2.8
2.6

Threshold (V)

2.4
2.2
2
1.8
1.6
1.4
1.2
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-262.ATmega168PA I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

105°C
85°C
25°C
-40°C

2.5

2

Threshold (V)

31.6.9

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

463

Figure 31-263.ATmega168PA I/O Pin Input Hysteresis vs. VCC
85°C
105°C

0.6

-40°C

Input Hysteresis (V)

0.55
0.5

25°C

0.45
0.4
0.35
0.3
0.25
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-264.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
1.5

-40°C
25°C
85°C
105°C

1.4

Threshold (V)

1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

464

Figure 31-265.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

2.3
2.1

Threshold (V)

1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-266.ATmega168PA: Reset Pin Input Hysteresis vs. VCC
0.7

-40°C
0.6

Input Hysteresis (V)

0.5

25°C
0.4
0.3

85°C

0.2

105°C
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

465

BOD Threshold
Figure 31-267.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.83
1.82

Rising Vcc

Threshold (V)

1.81
1.8
1.79

Falling Vcc
1.78
1.77
1.76
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 31-268.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.76
2.74

Rising Vcc
2.72
Threshold (V)

31.6.10

2.7
2.68

Falling Vcc
2.66
2.64
2.62
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

466

Figure 31-269.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.32

Rising Vcc

Threshold (V)

4.3

4.28

4.26

4.24

Falling Vcc
4.22

4.2
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 31-270.ATmega168PA: Calibrated Bandgap Voltage vs. Temperature
1.136

1.8V
2.7V
3.3V
4.0V
4.5V

1.134

Bandgap Voltage (V)

1.132
1.13
1.128

5.5V

1.126
1.124
1.122
1.12
1.118
1.116
-50

-30

-10

10

30

50

70

90

110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

467

Figure 31-271.ATmega168PA: Calibrated Bandgap Voltage vs. Vcc
1.136
1.134

Bandgap Voltage (V)

1.132
1.13
1.128

85°C
105°C
25°C

1.126
1.124
1.122
1.12
1.118

-40°C

1.116
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Internal Oscillator Speed
Figure 31-272.ATmega168PA: Watchdog Oscillator Frequency vs. Temperature
122
120
118

FRC (kHz)

31.6.11

116
114

2.7V
3.3V
4.0V
4.5V
5.5V
5.0V

112
110
108
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

468

Figure 31-273.ATmega168PA: Watchdog Oscillator Frequency vs. VCC
122
120

-40°C

FRC (kHz)

118

25°C

116
114
112

85°C

110

105°C
108
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-274.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.5
8.4

105°C
85°C

8.3

FRC (MHz)

8.2
8.1

25°C

8
7.9
7.8

-40°C

7.7
7.6
7.5
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

469

Figure 31-275.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.4

5.5V
4.5V
4.0V
3.3V
1.8V

8.3
8.2

FRC (MHz)

8.1
8
7.9
7.8
7.7
7.6
7.5
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 31-276.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
14

105°C
85°C
25°C
-40°C

12

FRC (MHz)

10

8

6

4

2
0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

470

Current Consumption of Peripheral Units
Figure 31-277.ATmega168PA: ADC Current vs. VCC (AREF = AVCC)
325

-40°C
25°C
85°C
105°C

300
275

ICC (µA)

250
225
200
175
150
125
100
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-278.ATmega168PA: Analog Comparator Current vs. VCC
90

-40°C
105°C
25°C
85°C

80

70
ICC (µA)

31.6.12

60

50

40

30
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

471

Figure 31-279.ATmega168PA: AREF External Reference Current vs. VCC
180

25°C
85°C
105°C
-40°C

160

ICC (µA)

140
120
100
80
60
40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-280.ATmega168PA: Brownout Detector Current vs. VCC

ICC (µA)

28
26

105°C

24

85°C

22

25°C
-40°C

20
18
16
14
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

472

Figure 31-281.ATmega168PA: Programming Current vs. VCC
9

-40°C
25°C

8
7

105°C
85°C

ICC (mA)

6
5
4
3
2
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Current Consumption in Reset and Reset Pulsewidth
Figure 31-282.ATmega168PA: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.12

5.5V
0.1

0.08

ICC (mA)

31.6.13

4.5V
4.0V

0.06

3.3V

0.04

2.7V
1.8V

0.02

0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

473

Figure 31-283.ATmega168PA: Reset Supply Current vs. Frequency (1MHz - 20MHz)
2.4
2.1

5.5V

1.8

5.0V
4.5V

ICC (mA)

1.5
1.2

4.0V
0.9

3.6V

0.6

2.7V

0.3

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-284.ATmega168PA: Minimum Reset Pulse Width vs. Vcc
1800
1600

Pulsewidth (ns)

1400
1200
1000
800
600

105°C
85°C
25°C
-40°C

400
200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

474

Active Supply Current
Figure 31-285.ATmega328: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
1.2

5.5 V
1

5.0 V
0.8
ICC (mA)

31.7.1

ATmega328 Typical Characteristics

4.5 V
4.0 V

0.6

3.3 V
0.4

2.7 V
1.8 V

0.2

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-286.ATmega328: Active Supply Current vs. Frequency (1-20MHz)
14

ICC (mA)

31.7

5.5V

12

5.0V

10

4.5V

8

4.0 V

6

3.3 V
4

2.7 V
2

1.8 V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

475

Figure 31-287.ATmega328: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.16

85 °C
25 °C
-40 °C

ICC (mA)

0.12

0.08

0.04

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-288.ATmega328: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.4

85 °C
25 °C

1.2

-40 °C

ICC (mA)

1
0.8
0.6
0.4
0.2
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

476

Figure 31-289.ATmega328: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
8
7

85 °C

6

25 °C
-40 °C

ICC (mA)

5
4
3
2
1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-290.ATmega328: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.2

5.5 V
0.16

5.0 V

ICC (mA)

31.7.2

4.5 V

0.12

4.0 V
3.3 V

0.08

2.7 V
0.04

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

477

Figure 31-291.ATmega328: Idle Supply Current vs. Frequency (1-20MHz)
4

I CC (mA)

3.5

5.5 V

3

5.0 V

2.5

4.5 V

2

4.0 V

1.5

3.3 V

1

2.7 V

0.5

1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-292.ATmega328: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.06

ICC (mA)

0.05

0.04

85 °C

0.03

25 °C
-40 °C

0.02

0.01

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

478

Figure 31-293.ATmega328: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.4

85 °C

0.35

25 °C

0.3

-40 °C

ICC (mA)

0.25
0.2
0.15
0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-294.ATmega328: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
2

85 °C

1.6

ICC (mA)

25 °C

-40 °C

1.2

0.8

0.4

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

479

31.7.3

ATmega328 Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-13. ATmega328: Additional Current Consumption for the different I/O modules (absolute values)
PRR bit

Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

3.20 µA

22.17 µA

100.25 µA

PRTWI

7.34 µA

46.55 µA

199.25 µA

PRTIM2

7.34 µA

50.79 µA

224.25 µA

PRTIM1

6.19 µA

41.25 µA

176.25 µA

PRTIM0

1.89 µA

14.28 µA

61.13 µA

PRSPI

6.94 µA

43.84 µA

186.50 µA

PRADC

8.66 µA

61.80 µA

295.38 µA

Table 31-14. ATmega328: Additional Current Consumption (percentage) in Active and Idle mode
Additional Current consumption
compared to Active with external
clock (see Figure 31-332 on page
500 and Figure 31-333 on page
500)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-337 on page
502 and Figure 31-338 on page
503)

PRUSART0

1.4%

7.8%

PRTWI

3.0%

16.6%

PRTIM2

3.3%

17.8%

PRTIM1

2.7%

14.5%

PRTIM0

0.9%

4.8%

PRSPI

2.9%

15.7%

PRADC

4.1%

22.1%

PRR bit

It is possible to calculate the typical current consumption based on the numbers from Table 31-13 for other VCC
and frequency settings than listed in Table 31-14.
31.7.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-14, third column, we see that we need to add 14.5% for the TIMER1, 22.1% for the ADC,
and 15.7% for the SPI module. Reading from Figure 31-338 on page 503, we find that the idle current consumption
is ~0.055 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI
enabled, gives:
I CC total  0.045 mA  (1 + 0.145 + 0.221 + 0.157)  0.069 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

480

Power-down Supply Current
Figure 31-295.ATmega328: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1.2

85 °C
1

ICC (uA)

0.8

0.6

0.4

0.2

25 °C
-40 °C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-296.ATmega328: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
10
9

-40 °C
85 °C
25 °C

8
7
6
ICC (uA)

31.7.4

5
4
3
2
1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

481

31.7.5

Power-save Supply Current
Figure 31-297.ATmega328: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
2
1.8
1.6

25 °C

1.4
ICC (uA)

1.2
1
0.8
0.6
0.4
0.2
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-298.ATmega328: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.16

6MHz_res
6MHz_xtal

0.14
0.12

4MHz_res
4MHz_xtal

0.1
ICC (mA)

31.7.6

0.08

2MHz_res
2MHz_xtal

0.06

1MHz_res

0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

482

Pin Pull-Up
Figure 31-299.ATmega328: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
60

50

IOP (uA)

40

30

20

10

25 °C

0

85 °C
-40 °C
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VOP (V)

Figure 31-300.ATmega328: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
90
80
70
60
IOP (uA)

31.7.7

50
40
30
20

25 °C

10

85 °C
-40 °C

0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

483

Figure 31-301.ATmega328: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
160
140
120

IOP (uA)

100
80
60
40

25 °C

20

85 °C
-40 °C

0
0

1

2

3

4

5

6

VOP (V)

Figure 31-302.ATmega328: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V)
40
35
30

IRESET (uA)

25
20
15
10

25 °C

5

85 °C
-40 °C

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VRESET(V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

484

Figure 31-303.ATmega328: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V)
70
60

IRESET (uA)

50
40
30
20

25 °C
10

85 °C
-40 °C

0
0

0.5

1

1.5

2

2.5

3

VRESET(V)

Figure 31-304.ATmega328: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V)
120

100

IRESET(uA)

80

60

40

25 °C
20

85 °C
-40 °C

0
0

1

2

3

4

5

6

VRESET(V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

485

Pin Driver Strength
Figure 31-305.ATmega328: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V)
1

85 °C
0.8

25 °C
V OL (V)

0.6

-40 °C
0.4

0.2

0
0

5

10

15

20

25

IOL (mA)

Figure 31-306.ATmega328: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V)
0.6

85 °C
0.5

25 °C
0.4
V OL (V)

31.7.8

-40 °C

0.3

0.2

0.1

0
0

5

10

15

20

25

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

486

Figure 31-307.ATmega328: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V)
3.5
3

V OH (V)

2.5

-40 °C
25 °C
85 °C

2
1.5
1
0.5
0
0

5

10

15

20

25

IOH (mA)

Figure 31-308.ATmega328: I/O Pin Output Voltage vs. Source Current (VCC = 5 V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V

5.1
5
4.9

V OH (V)

4.8
4.7
4.6

-40 °C
4.5

25 °C

4.4

85 °C

4.3
0

5

10

15

20

25

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

487

Pin Threshold and Hysteresis
Figure 31-309.ATmega328: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
4
3.5

-40 °C
25 °C
85 °C

Threshold (V)

3
2.5
2
1.5
1
0.5
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-310.ATmega328: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'

2.5

85 °C
25 °C
-40 °C

2

Threshold (V)

31.7.9

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

488

Figure 31-311.ATmega328: I/O Pin Input Hysteresis vs. VCC

I/O PIN INPUT HYSTERESIS vs. VCC
0.7

-40 °C
25 °C
85 °C

0.6

Input Hysteresis (V)

0.5
0.4
0.3
0.2
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-312.ATmega328: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
2.5

-40 °C
25 °C

Threshold (V)

2

85 °C

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

489

Figure 31-313.ATmega328: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

85 °C
25 °C

Threshold (V)

2

-40 °C

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-314.ATmega328: Reset Pin Input Hysteresis vs. VCC
0.7
0.6

Input Hysteresis (V)

0.5
0.4
0.3
0.2

-40 °C
0.1

25 °C
85 °C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

490

BOD Threshold
Figure 31-315.ATmega328: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)
1.85

1.83

Threshold (V)

1
1.81

0

1.79

1.77

1.75
-60

-40

-20

0

20

40

60

80

100

Temperature (°C)

Figure 31-316.ATmega328: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)
2.78

2.76

1
2.74
Threshold (V)

31.7.10

2.72

2.7

2.68

0

2.66
-60

-40

-20

0

20

40

60

80

100

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

491

Figure 31-317.ATmega328: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)
4.4

Threshold (V)

4.35

1

4.3

0
4.25
-60

-40

-20

0

20

40

60

80

100

Temperature (°C)

Figure 31-318.ATmega328: Bandgap Voltage vs. VCC
1.138

Bandgap Voltage (V)

1.136
1.134

25 °C

1.132
1.13
1.128

85 °C
-40 °C

1.126
1.124
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

492

Internal Oscillator Speed
Figure 31-319.ATmega328: Watchdog Oscillator Frequency vs. Temperature
119
118
117

F RC (kHz)

116
115
114
113
112

2.7 V

111

3.3 V

110

4.0 V
5.5 V

109
-60

-40

-20

0

20

40

60

80

100

Temperature (°C)

Figure 31-320.ATmega328: Watchdog Oscillator Frequency vs. VCC
120

118

-40 °C
116
F RC (kHz)

31.7.11

25 °C

114

112

110

85 °C

108

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

493

Figure 31-321.ATmega328: Calibrated 8MHz RC Oscillator Frequency vs. VCC

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC
8.4

85 °C
8.2

F RC (MHz)

25 °C
8

-40 °C

7.8

7.6

7.4
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-322.ATmega328: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.4
8.3

5.0 V

8.2

3.0 V

F RC (MHz)

8.1
8
7.9
7.8
7.7
7.6
-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

494

Figure 31-323.ATmega328: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
16
14

85 °C
25 °C

12

-40 °C

F RC (MHz)

10
8
6
4
2
0
0

16

32

48

64

80

96

112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

Current Consumption of Peripheral Units
Figure 31-324.ATmega328: ADC Current vs. VCC (AREF = AVCC)
350

-40 °C
25 °C
85 °C

300
250

ICC (uA)

31.7.12

200
150
100
50
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

495

Figure 31-325.ATmega328: Analog Comparator Current vs. VCC
120

100

-40 °C
25 °C
85 °C

ICC (uA)

80

60

40

20

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-326.ATmega328: AREF External Reference Current vs. VCC
180

85 °C
25 °C
-40 °C

160
140

ICC (uA)

120
100
80
60
40
20
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

496

Figure 31-327.ATmega328: Brownout Detector Current vs. VCC
30

85 °C
25 °C
-40 °C

25

ICC (uA)

20

15

10

5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-328.ATmega328: Programming Current vs. VCC
10
9

25 °C
85 °C
-40 °C

8

ICC (mA)

7
6
5
4
3
2
1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

497

Current Consumption in Reset and Reset Pulsewidth
Figure 31-329.ATmega328: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz)
0.15

5.5 V
5.0 V
4.5 V

0.1
ICC (mA)

4.0 V
3.3 V
2.7 V

0.05

1.8 V

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-330.ATmega328: Reset Supply Current vs. Frequency (1 - 20MHz)
3

5.5 V

2.5

5.0 V
4.5 V

2
ICC (mA)

31.7.13

4.0 V

1.5

1

3.3 V
2.7 V

0.5

1.8 V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

498

Figure 31-331.ATmega328: Minimum Reset Pulse width vs. VCC
1800
1600
1400

Pulsewidth (ns)

1200
1000
800
600
400

85 °C
25 °C
-40 °C

200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

499

Active Supply Current
Figure 31-332.ATmega328P: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
1.2

5.5V
1

5.0V

ICC (mA)

31.8.1

ATmega328P Typical Characteristics

0.8

4.5V

0.6

4.0V
3.6V

0.4

2.7V
1.8V

0.2

0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-333.ATmega328P: Active Supply Current vs. Frequency (1-20MHz)

ICC (mA)

31.8

3.5

5.5V

3

5.0V

2.5

4.5V

2

4.0V
1.5

3.6V

1

2.7V
0.5

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

500

Figure 31-334.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.16

105°C
85°C
-40°C
25°C

0.14
0.12

ICC (mA)

0.1
0.08
0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-335.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.4

105°C
85°C
25°C
-40°C

1.2

ICC (mA)

1

0.8

0.6

0.4

0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

501

Figure 31-336.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
7

105°C
85°C
25°C
-40°C

6

ICC (mA)

5

4

3

2

1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Idle Supply Current
Figure 31-337.ATmega328P: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.2

5.5V

0.18
0.16

5.0V

0.14

ICC (mA)

31.8.2

4.5V

0.12

4.0V
3.6V

0.1
0.08
0.06

2.7V

0.04

1.8V

0.02
0
0

0.2

0.4

0.6

0.8

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

502

ICC (mA)

Figure 31-338.ATmega328P: Idle Supply Current vs. Frequency (1-20MHz)
3.5

5.5V

3

5.0V

2.5

4.5V

2

4.0V
1.5

3.6V

1

2.7V
0.5

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 31-339.ATmega328P: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05

105°C

0.045

85°C

0.04

ICC (mA)

0.035

25°C
-40°C

0.03
0.025
0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

503

Figure 31-340.ATmega328P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.4

105°C
85°C
25°C
-40°C

0.35

ICC (mA)

0.3

0.25

0.2

0.15

0.1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-341.ATmega328P Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
1.8

105°C
85°C
25°C
-40°C

1.6
1.4

ICC (mA)

1.2
1
0.8
0.6
0.4
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

504

31.8.3

ATmega328P Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details.
Table 31-15. ATmega328P: Additional Current Consumption for the different I/O modules (absolute values)
PRR bit

Typical numbers
VCC = 2V, F = 1MHz

VCC = 3V, F = 4MHz

VCC = 5V, F = 8MHz

PRUSART0

3.20 µA

22.17 µA

100.25 µA

PRTWI

7.34 µA

46.55 µA

199.25 µA

PRTIM2

7.34 µA

50.79 µA

224.25 µA

PRTIM1

6.19 µA

41.25 µA

176.25 µA

PRTIM0

1.89 µA

14.28 µA

61.13 µA

PRSPI

6.94 µA

43.84 µA

186.50 µA

PRADC

8.66 µA

61.80 µA

295.38 µA

Table 31-16. ATmega328P: Additional Current Consumption (percentage) in Active and Idle mode
Additional Current consumption
compared to Active with external
clock (see Figure 31-332 on page
500 and Figure 31-333 on page
500)

Additional Current consumption
compared to Idle with external
clock (see Figure 31-337 on page
502 and Figure 31-338 on page
503)

PRUSART0

1.4%

7.8%

PRTWI

3.0%

16.6%

PRTIM2

3.3%

17.8%

PRTIM1

2.7%

14.5%

PRTIM0

0.9%

4.8%

PRSPI

2.9%

15.7%

PRADC

4.1%

22.1%

PRR bit

It is possible to calculate the typical current consumption based on the numbers from Table 31-15 for other VCC
and frequency settings than listed in Table 31-16.
31.8.3.1
Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-16, third column, we see that we need to add 14.5% for the TIMER1, 22.1% for the ADC,
and 15.7% for the SPI module. Reading from Figure 31-338 on page 503, we find that the idle current consumption
is ~0.055 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI
enabled, gives:
I CC total  0.045 mA  (1 + 0.145 + 0.221 + 0.157)  0.069 mA

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

505

Power-down Supply Current
Figure 31-342.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
3

105°C
2.5

ICC (µA)

2

1.5

85°C

1

0.5

25°C
-40°C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-343.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
10

105°C
9

-40°C
85°C
25°C

8
7
ICC (µA)

31.8.4

6
5
4
3
2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

506

31.8.5

Power-save Supply Current
Figure 31-344.ATmega328P: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal
Oscillator Running)
4
3.5

105°C
3

ICC (µA)

2.5
2

85°C

1.5
1

25°C
-40°C

0.5
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Standby Supply Current
Figure 31-345.ATmega328P: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.16

6MHz_res
6MHz_xtal

0.14
0.12

4MHz_res
4MHz_xtal

0.1
ICC (mA)

31.8.6

0.08

2MHz_res
2MHz_xtal

0.06

1MHz_res

0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

507

Pin Pull-Up
Figure 31-346.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
50
45
40

IOP(µA)

35
30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VOP (V)

Figure 31-347.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60
50
IOP (µA)

31.8.7

40
30
20

25°C
85°C
-40°C
105°C

10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

508

Figure 31-348.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
160
140
120

IOP (µA)

100
80
60

25°C
85°C
105°C
-40°C

40
20
0
0

1

2

3

4

5

VOP (V)

Figure 31-349.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
40
35

IRESET (µA)

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

509

Figure 31-350.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
60

50

IRESET (µA)

40

30

20

25°C
-40°C
85°C
105°C

10

0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VRESET (V)

Figure 31-351.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (µA)

80

60

40

25°C
-40°C
85°C
105°C

20

0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

510

Pin Driver Strength
Figure 31-352.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1

105°C
85°C

0.9
0.8

25°C

VOL (V)

0.7
0.6

-40°C

0.5
0.4
0.3
0.2
0.1
0
0

5

10

15

20

IOL (mA)

Figure 31-353.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.7

105°C
85°C

0.6
0.5
VOL (V)

31.8.8

25°C

0.4

-40°C

0.3
0.2
0.1
0
0

5

10

15

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

511

Figure 31-354.ATmega328P: I/O Pin Output Voltage vs. Source Current (Vcc = 3V)
3.1

2.9

VOH (V)

2.7

2.5

-40°C

2.3

25°C
2.1

85°C
105°C

1.9
0

5

10

15

20

IOH (mA)

Figure 31-355.ATmega328P: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5.1
5
4.9

VOH (V)

4.8
4.7
4.6

-40°C
4.5

25°C
85°C
105°C

4.4
4.3
0

5

10

15

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

512

Pin Threshold and Hysteresis
Figure 31-356.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3.1

105°C
85°C
25°C
-40°C

2.8

Threshold (V)

2.5
2.2
1.9
1.6
1.3
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-357.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’
2.6

105°C
2.3

85°C
25°C

2

-40°C
Threshold (V)

31.8.9

1.7
1.4
1.1
0.8
0.5
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

513

Figure 31-358.ATmega328P: I/O Pin Input Hysteresis vs. VCC
0.8

Input Hysteresis (mV)

0.7

-40°C
25°C
85°C
105°C

0.6

0.5

0.4

0.3

0.2
1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

VCC (V)

Figure 31-359.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

Threshold (V)

2.6

-40°C

2.4

25°C

2.2

85°C

2

105°C

1.8
1.6
1.4
1.2
1
0.8
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

514

Figure 31-360.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

2.3
2.1

Threshold (V)

1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-361.ATmega328P: Reset Pin Input Hysteresis vs. VCC
0.7

-40°C
0.6

Input Hysteresis (V)

0.5

25°C
0.4
0.3

85°C

0.2

105°C
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

515

BOD Threshold
Figure 31-362.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.84

Rising Vcc

Threshold (V)

1.83

1.82

1.81

1.8

Falling Vcc
1.79

1.78
-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100 110

Temperature (°C)

Figure 31-363.ATmega328P BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.78
2.77

Rising Vcc

2.76
2.75
Threshold (V)

31.8.10

2.74
2.73
2.72
2.71
2.7

Falling Vcc

2.69
2.68
2.67
2.66
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

516

Figure 31-364.ATmega328P BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.38
4.36

Rising Vcc

Threshold (V)

4.34
4.32
4.3
4.28

Falling Vcc

4.26
4.24
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 31-365.ATmega328P: Calibrated Bandgap Voltage vs. Vcc
1.139

Bandgap Voltage (V)

1.136

25°C

1.133

1.13

1.127

85°C
-40°C

1.124

105°C
1.121
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

517

Internal Oscillator Speed
Figure 31-366.ATmega328P: Watchdog Oscillator Frequency vs. Temperature
120
118

FRC (kHz)

116
114
112
110

2.7V
3.6V
4.0V
5.5V

108
106
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 31-367.ATmega328PC Watchdog Oscillator Frequency vs. VCC
120
118

-40°C
116
FRC (kHz)

31.8.11

25°C

114
112
110

85°C

108

105°C

106
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

518

Figure 31-368.ATmega328P: Calibrated 8 MHz RC Oscillator Frequency vs. VCC
8.6

105°C
85°C

8.4

FRC (MHz)

8.2

25°C
8

-40°C

7.8
7.6
7.4
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-369.ATmega328P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature

5.5V
5.0V
4.5V
4.0V
3.6V
2.7V

8.4
8.3
8.2

FRC (MHz)

8.1

1.8V

8
7.9
7.8
7.7
7.6
7.5
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

519

Figure 31-370.ATmega328P Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
14

105°C
85°C
25°C
-40°C

13
12

FRC (MHz)

11
10
9
8
7
6
5
4
0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)

Current Consumption of Peripheral Units
Figure 31-371.ATmega328P: ADC Current vs. VCC (AREF = AVCC)
160

85°C
105°C
25°C
-40°C

140

120
ICC (µA)

31.8.12

100

80

60

40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

520

Figure 31-372.ATmega328P: Analog Comparator Current vs. VCC

ICC (µA)

100
90

-40°C

80

25°C
85°C
105°C

70
60
50
40
30
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-373.ATmega328P: AREF External Reference Current vs. VCC
180

85°C
105°C
25°C
-40°C

160

ICC (µA)

140
120
100
80
60
40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

521

Figure 31-374.ATmega328P: Brownout Detector Current vs. VCC
30

105°C
85°C

ICC (µA)

25

25°C
-40°C
20

15

10
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 31-375.ATmega328P: Programming Current vs. VCC
10
9

25°C
85°C
105°C
-40°C

8

ICC (mA)

7
6
5
4
3
2
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

522

Current Consumption in Reset and Reset Pulsewidth
Figure 31-376.ATmega328P: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.16

5.5V

ICC (mA)

0.14
0.12

5.0V

0.1

4.5V
4.0V
3.6V

0.08
0.06

2.7V
0.04

1.8V

0.02
0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 31-377.ATmega328P Reset Supply Current vs. Frequency (1MHz - 20MHz)
3

5.5V

2.5

5.0V
4.5V

2
ICC (mA)

31.8.13

4.0V

1.5

3.6V

1

2.7V

0.5

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

523

Figure 31-378.ATmega328P: Minimum Reset Pulse Width vs. Vcc
1800
1600

Pulsewidth (ns)

1400
1200
1000
800
600

105°C
85°C
25°C
-40°C

400
200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

524

32.

ATmega48PA Typical Characteristics – (TA = -40°C to 105°C)
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave
generator with rail-to-rail output is used as clock source.
All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the
corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O
pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage
and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Active Supply Current
Figure 32-1. ATmega48PA: Active Supply Current vs. Low Frequency (0.1MHz -1.0MHz)
1

5.5V

0.9
0.8

5.0V

0.7
ICC (mA)

32.1

4.5V

0.6

4.0V
0.5
0.4

3.6V
3.3V

0.3

2.7V

0.2

1.8V

0.1
0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

525

Figure 32-2. ATmega48PA: Active Supply Current vs. Frequency (1MHz - 20MHz)
11

5.5V

10
9

5.0V

8

4.5V

ICC (mA)

7
6

4.0V

5
4

3.3V

3

2.7V

2
1

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 32-3. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)

105°C
85°C
-40°C
25°C

0.126
0.1158
0.1056

ICC (mA)

0.0954
0.0852
0.075
0.0648
0.0546
0.0444
0.0342
0.024
1.8

2.17

2.54

2.91

3.28

3.65

4.02

4.39

4.76

5.13

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

526

Figure 32-4. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)

105°C
85°C
25°C
-40°C

1.2
1.1
1

ICC (mA)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-5. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
5.5

105°C
85°C
25°C
-40°C

5
4.5

ICC (mA)

4
3.5
3
2.5
2
1.5
1
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

527

Idle Supply Current
Figure 32-6. ATmega48PA: Idle Supply Current vs. Low Frequency (0.1MHz -1.0MHz)

ICC (mA)

0.16
0.14

5.5V

0.12

5.0V

0.1

4.5V

0.08

4.0V

0.06

3.3V

0.04

2.7V
1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 32-7. ATmega48PA: Idle Supply Current vs. Frequency (1MHz - 20MHz)
2.6

5.5V

2.4
2.2

5.0V

2

4.5V

1.8
1.6
ICC (mA)

32.2

1.4

4.0V

1.2
1
0.8

3.3V

0.6

2.7V

0.4
0.2

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

528

Figure 32-8. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05

105°C

0.045

85°C

0.04

ICC (mA)

0.035
0.03

25°C
-40°C

0.025
0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-9. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.33

105°C
85°C
25°C
-40°C

ICC (mA)

0.28

0.23

0.18

0.13

0.08
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

529

Figure 32-10.ATmega48PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
1.3

105°C
85°C
25°C
-40°C

1.2
1.1
1
ICC (mA)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-down Supply Current
Figure 32-11.ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
2.7

105°C

2.4
2.1
1.8
ICC (µA)

32.3

1.5
1.2
0.9

85°C
-40°C

0.6
0.3

25°C
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

530

Figure 32-12.ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
9

105°C

8.5
8

-40°C
85°C
25°C

7.5
7
ICC (µA)

6.5
6
5.5
5
4.5
4
3.5
3
2.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

32.4

Power-save Supply Current
Figure 32-13.ATmega48PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

531

32.5

Standby Supply Current
Figure 32-14.ATmega48PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)

6MHz_xtal
6MHz_res

150
135
120

4MHz_res
4MHz_xtal

105
ICC (µA)

90

2MHz_res
2MHz_xtal

75
60

1MHz_res
450kHz_res

45
30
15
0.0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Pin Pull-Up
Figure 32-15.ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
45
40
35
30
IOP (µA)

32.6

25
20
15
10

105°C
-40°C
25°C
85°C

5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

532

Figure 32-16.ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
70
60

IOP (µA)

50
40
30
20

25°C
85°C
-40°C
105°C

10
0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VOP (V)

Figure 32-17.ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

120
105

IOP (µA)

90
75
60
45
30

25°C
85°C
105°C
-40°C

15
0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

533

Figure 32-18.ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
35
30

IRESET (µA)

25
20
15
10

25°C
-40°C
105°C
85°C

5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

Figure 32-19.ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
52
48
44
40

IRESET (µA)

36
32
28
24
20
16
12

25°C
-40°C
85°C
105°C

8
4
0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

534

Figure 32-20.ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
110
100
90
80
IRESET (µA)

70
60
50
40
30

85°C
25°C
-40°C
105°C

20
10
0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

Pin Driver Strength
Figure 32-21.ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1

105°C
85°C

0.9
0.8

25°C

0.7
0.6

VOL (V)

32.7

-40°C
0.5
0.4
0.3
0.2
0.1
0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

535

Figure 32-22.ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.65

105°C
85°C

0.6
0.55
0.5

25°C

0.45

-40°C

VOL (V)

0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

Figure 32-23.ATmega48PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V)
3
2.9
2.8
2.7

VOH (V)

2.6
2.5
2.4

-40°C

2.3
2.2

25°C

2.1
2

85°C
105°C

1.9
0

2

4

6

8

10

12

14

16

18

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

536

Figure 32-24.ATmega48PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5
4.9

VOH (V)

4.8
4.7
4.6

-40°C
4.5

25°C
4.4

85°C
105°C

4.3
0

2

4

6

8

10

12

14

16

18

20

IOH (mA)

Pin Threshold and Hysteresis
Figure 32-25.ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

105°C
85°C
-40°C
25°C

2.9
2.6
2.3
Threshold (V)

32.8

2
1.7
1.4
1.1
0.8
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

537

Figure 32-26.ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

105°C
-40°C
85°C
25°C

2.4
2.1

Threshold (V)

1.8
1.5
1.2
0.9
0.6
0.3
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-27.ATmega48PA: I/O Pin Input Hysteresis vs. VCC
0.6

-40 °C

25°C
85°C
105°C
-40°C

Input Hysteresis (mV)

0.55
0.5
0.45

25 °C

0.4

85 °C

0.35
0.3

105 °C

0.25
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

538

Figure 32-28.ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

105°C
85°C
-40°C
25°C

2.45

Threshold (V)

2.2

1.95

1.7

1.45

1.2

-40°C
25°C
85°C

105°C

0.95
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-29.ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

-40°C
105°C
85°C
25°C

2.4
2.2

Threshold (V)

2
1.8
1.6
1.4
1.2
1
0.8
0.6
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

539

Figure 32-30.ATmega48PA: Reset Pin Input Hysteresis vs. VCC
0.65

-40°C

0.6
0.55

Input Hysteresis (mV)

0.5
0.45

25°C

0.4
0.35
0.3

85°C

0.25
0.2

105°C

0.15

85°C
105°C
25°C
-40°C

0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

BOD Threshold
Figure 32-31.ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.825
1.82

Rising Vcc

1.815
1.81

Threshold (V)

32.9

1.805
1.8
1.795
1.79

Falling Vcc

1.785
1.78
1.775
1.77
1.765
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

540

Figure 32-32.ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.76
2.75

Rising Vcc

2.74

Threshold (V)

2.73
2.72
2.71
2.7
2.69
2.68
Falling Vcc

2.67
2.66
2.65
2.64
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

90

100

Temperature (°C)

Figure 32-33.ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.34
4.32

Rising Vcc

Threshold (V)

4.3
4.28
4.26

Falling Vcc
4.24
4.22
4.2
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

541

32.10 Internal Oscilllator Speed
Figure 32-34.ATmega48PA: Watchdog Oscillator Frequency vs. Temperature
116

114

FRC (kHz)

112

110

108

2.7V
3.3V
4.0V
5.5V

106

104
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

Temperature (°C)

Figure 32-35.ATmega48PA: Watchdog Oscillator Frequency vs. VCC

FRC (kHz)

116

114

-40°C

112

25°C

110

108

85°C
106

105°C

104
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

542

Figure 32-36.ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.25
8.2

105°C

8.15

85°C

8.1

FRC (MHz)

8.05
8

25°C

7.95
7.9
7.85
7.8
7.75

-40°C

7.7
7.65
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-37.ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature

4.0V
3.0V
5.5V

8.2
8.15

1.8V

8.1
8.05
FRC (MHz)

8
7.95
7.9
7.85
7.8
7.75
7.7
7.65
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

543

Figure 32-38.ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value

85°C
25°C
105°C
-40°C

15
14
13
12
FRC (MHz)

11
10
9
8
7
6
5
4
0

16

32

48

64

80

96

112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

32.11 Current Consumption of Peripheral Units
Figure 32-39.ATmega48PA: ADC Current vs. VCC (AREF = AVCC)

-40°C
25°C
85°C
105°C

310
290
270

ICC (µA)

250
230
210
190
170
150
130
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

544

Figure 32-40.ATmega48PA: Analog Comparator Current vs. VCC
90

-40°C

85
80

25°C
85°C
105°C

75

ICC (µA)

70
65
60
55
50
45

105°C
85°C
25°C
35 -40°C
40

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-41.ATmega48PA: AREF External Reference Current vs. VCC

105°C
85°C
25°C
-40°C

150
140
130
120

ICC (µA)

110
100
90
80
70
60
50
40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

545

Figure 32-42.ATmega48PA: Brownout Detector Current vs. VCC
26
25

105°C
85°C

24
23

25°C
-40°C

ICC (µA)

22
21
20
19
18
17
16
15
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 32-43.ATmega48PA: Programming Current vs. VCC
5.5

-40°C

5

25°C

4.5

ICC (mA)

4
3.5
3

85°C
105°C

2.5
2
1.5
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

546

32.12 Current Consumption in Reset and Reset Pulsewidth
Figure 32-44.ATmega48PA: Reset Supply Current vs. Low Frequency (0.1MHz- 1.0MHz)
0.13

5.5V

0.12
0.11

5.0V

0.1
0.09

4.5V

ICC (mA)

0.08
0.07

4.0V

0.06
0.05

3.3V

0.04

2.7V

0.03

1.8V

0.02
0.01
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 32-45.ATmega48PA: Reset Supply Current vs. Frequency (1MHz- 20MHz)
2.4

5.5V

2.2

5.0V

2
1.8

4.5V

ICC (mA)

1.6
1.4

4.0V

1.2
1
0.8

3.3V

0.6

2.7V

0.4
0.2

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

547

Figure 32-46.ATmega48PA: Minimum Reset Pulse width vs. VCC
1600
1500
1400
1300

Pulsewidth (ns)

1200
1100
1000
900
800
700
600
500
400
300
200
1.5

2

2.5

3

3.5

4

4.5

5

105°C
85°C
25°C
-40°C

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

548

33.

ATmega88PA Typical Characteristics – (TA = -40°C to 105°C)
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave
generator with rail-to-rail output is used as clock source.
All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the
corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O
pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage
and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Active Supply Current
Figure 33-1. ATmega88PA: Active Supply Current vs. Low Frequency (0.1MHz -1.0MHz)
1
0.9

5.5V

0.8

5.0V

0.7

ICC (mA)

33.1

4.5V

0.6

4.0V
0.5
0.4

3.3V

0.3

2.7V

0.2

1.8V

0.1
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

549

Figure 33-2. ATmega88PA: Active Supply Current vs. Frequency (1MHz - 20MHz)
12

5.5V

10

5.0V
ICC (mA)

8

4.5V

6

4.0V
4

3.3V
2.7V

2

1.8V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 33-3. ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.14

105°C

0.12

-40°C
25°C

0.1

ICC (mA)

85°C
0.08
0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

550

Figure 33-4. ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.4

105°C
85°C
25°C
-40°C

1.2

ICC (mA)

1
0.8
0.6
0.4
0.2
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 33-5. ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
6

105°C
85°C
25°C
-40°C

5

ICC (mA)

4

3

2

1

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

551

Idle Supply Current
Figure 33-6. ATmega88PA: Idle Supply Current vs. Low Frequency (0.1MHz -1.0MHz)
0.14

5.5V

0.12

5.0V

ICC (mA)

0.1

4.5V

0.08

4.0V
0.06

3.3V
2.7V

0.04

1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 33-7. ATmega88PA: Idle Supply Current vs. Frequency (1MHz - 20MHz)
2.5

5.5V
2

5.0V
ICC (mA)

33.2

4.5V

1.5

4.0V

1

3.3V
0.5

2.7V
1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

552

Figure 33-8. ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05
0.045

105°C

0.04

ICC (mA)

0.035

85°C

0.03

25°C
-40°C

0.025
0.02
0.015
0.01
0.005
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 33-9. ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.4

105°C

ICC (mA)

0.35
0.3

85°C
25°C

0.25

-40°C

0.2
0.15
0.1
0.05
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

553

Figure 33-10.ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
1.2

105°C
85°C
25°C

1

-40°C
ICC (mA)

0.8

0.6

0.4

0.2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-down Supply Current
Figure 33-11.ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
5

105°C
4

ICC (µA)

33.3

3

2

85°C
1

25°C
-40°C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

554

Figure 33-12.ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
12

10

105°C

ICC (µA)

8

-40°C
6

25°C
4

85°C
2

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-save Supply Current
Figure 33-13.ATmega88PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running)
6

105°C
4

ICC (µA)

33.4

85°C

2

25°C
-40°C
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

555

Pin Pull-Up
Figure 33-14.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
60

50

IOP (µA)

40

30

20

25°C
10

-40°C

0

85°C
105°C
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VOP (V)

Figure 33-15.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60
50

IOP (µA)

33.5

40
30

25°C

20

-40°C
85°C
105°C

10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

556

Figure 33-16.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
160
140
120

IOP (µA)

100
80
60

25°C

40

-40°C
85°C
105°C

20
0
0

1

2

3

4

5

6

VOP (V)

Figure 33-17.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
40
35

IRESET (µA)

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

557

Figure 33-18.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
60

50

IRESET (µA)

40

30

20

25°C
-40°C
85°C
105°C

10

0
0

0.5

1

1.5

2

2.5

3

VRESET (V)

Figure 33-19.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (µA)

80

60

40

25°C
-40°C
85°C
105°C

20

0
0

1

2

3

4

5

6

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

558

Pin Driver Strength
Figure 33-20.ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1.2

1

105°C
85°C
VOL (V)

0.8

25°C
0.6

-40°C
0.4

0.2

0
0

5

10

15

20

25

IOL (mA)

Figure 33-21.ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.7
0.6

105°C

85°C

0.5

25°C
VOL (V)

33.6

0.4

-40°C

0.3
0.2
0.1
0
0

5

10

15

20

25

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

559

Figure 33-22.ATmega88PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V)
3.5

VOH (V)

3

2.5

-40°C
25°C
85°C
105°C

2

1.5
0

5

10

15

20

25

IOH (mA)

Figure 33-23.ATmega88PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5.2

5

VOH (V)

4.8

4.6

-40°C
25°C

4.4

85°C
105°C

4.2
0

5

10

15

20

25

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

560

Pin Threshold and Hysteresis
Figure 33-24.ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3.5

105°C
85°C
25°C
-40°C

3

Threshold (V)

2.5
2
1.5
1
0.5
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 33-25.ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

2

Threshold (V)

33.7

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

561

Figure 33-26.ATmega88PA: I/O Pin Input Hysteresis vs. VCC
0.7

Input Hysteresis (mV)

0.6

-40°C

0.5

25°C
0.4

85°C
0.3

105°C

0.2
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 33-27.ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
2.5

Threshold (V)

2

1.5

1

-40°C
25°C
85°C
105°C

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

562

Figure 33-28.ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

4

4.5

5

5.5

VCC (V)

Figure 33-29.ATmega88PA: Reset Pin Input Hysteresis vs. VCC
0.7
0.6

Input Hysteresis (mV)

-40°C
0.5

25°C

0.4
0.3

85°C
0.2

105°C
0.1
0
1.5

2

2.5

3

3.5
VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

563

BOD Threshold
Figure 33-30.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.84
1.83

Rising Vcc
Threshold (V)

1.82
1.81
1.8
1.79
1.78

Falling Vcc

1.77
1.76
-60

-40

-20

0

20

40

60

80

100

120

100

120

Temperature (°C)

Figure 33-31.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.8

Rising Vcc

2.78
2.76
2.74

Threshold (V)

33.8

2.72
2.7
2.68

Falling Vcc

2.66
2.64
2.62
2.6
-60

-40

-20

0

20

40

60

80

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

564

Figure 33-32.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.5
4.45
4.4

Rising Vcc

Threshold (V)

4.35
4.3
4.25

Falling Vcc

4.2
4.15
4.1
4.05
4
-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Internal Oscilllator Speed
Figure 33-33.ATmega88PA: Watchdog Oscillator Frequency vs. Temperature
116
114
112

FRC (kHz)

33.9

110
108

2.7V
3.3V
4.0V

106
104

5.5V

102
-40

-20

0

20

40

60

80

100

120

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

565

Figure 33-34.ATmega88PA: Watchdog Oscillator Frequency vs. VCC

116
114

-40°C

FRC (kHz)

112

25°C

110
108
106

85°C

104

105°C

102
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 33-35.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.5

105°C
85°C

FRC (MHz)

8.25

25°C
8

-40°C
7.75

7.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

566

Figure 33-36.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.4

5.5V
4.0V
3.0V

8.3

FRC (MHz)

8.2

1.8V

8.1
8
7.9
7.8
7.7
7.6
-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 33-37.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value

FRC (MHz)

14
12

105°C
85°C

10

25°C
-40°C

8
6
4
2
0
0

16

32

48

64

80

96

112

128

144

160

176

192

208

224

240

256

OSCCAL (X1)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

567

33.10 Current Consumption of Peripheral Units
Figure 33-38.ATmega88PA: ADC Current vs. VCC (AREF = AVCC)
350

-40°C
300

25°C
85°C
105°C

ICC (µA)

250
200
150
100
50
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

4

4.5

5

5.5

VCC (V)

Figure 33-39.ATmega88PA: Analog Comparator Current vs. VCC
90
80
70

ICC (µA)

60

105°C

50
40
30

85°C
25°C
-40°C

20
10
0
1.5

2

2.5

3

3.5
VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

568

Figure 33-40.ATmega88PA: AREF External Reference Current vs. VCC
160

105°C
85°C
25°C
-40°C

140
120

ICC (µA)

100
80
60
40
20
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

4

4.5

5

5.5

VCC (V)

Figure 33-41.ATmega88PA: Brownout Detector Current vs. VCC
30

25

ICC (µA)

20

15

105°C
85°C
25°C
-40°C

10

5

0
1.5

2

2.5

3

3.5
VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

569

Figure 33-42.ATmega88PA: Programming Current vs. VCC
10
9
8

-40°C

ICC (mA)

7
6
5

25°C

4

85°C

3

105°C

2
1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

33.11 Current Consumption in Reset and Reset Pulsewidth
Figure 33-43.ATmega88PA: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.12

5.5V
0.1

5.0V
ICC (mA)

0.08

4.5V
4.0V

0.06

3.3V
0.04

1.8V

0.02

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

570

Figure 33-44.ATmega88PA: Reset Supply Current vs. Frequency (1MHz - 20MHz)
2.5

2

5.5V

ICC (mA)

5.0V
1.5

4.5V
4.0V

1

3.3V
0.5

2.7V
1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 33-45.ATmega88PA: Minimum Reset Pulse width vs. VCC
1800
1600

Pulsewidth (ns)

1400
1200
1000
800
600

105°C
85°C
25°C
-40°C

400
200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

571

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

572

34.

ATmega168PA Typical Characteristics – (TA = -40°C to 105°C)
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
sine wave generator with rail-to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Active Supply Current
Figure 34-1. ATmega168PA: Active Supply Current vs. Low Frequency (0.1MHz -1.0MHz)
1

5.5V

0.9

ICC (mA)

34.1

0.8

5.0V

0.7

4.5V

0.6

4.0V

0.5
0.4

3.3V

0.3

2.7V

0.2

1.8V

0.1
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

573

Figure 34-2. ATmega168PA: Active Supply Current vs. Frequency (1MHz - 20MHz)
12

5.5V
10

5.0V

ICC (mA)

8

4.5V

6

4.0V
3.6V

4

2.7V

2

1.8V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 34-3. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.14

105°C
-40°C
85°C
25°C

0.12

ICC (mA)

0.1

0.08

0.06

0.04

0.02
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

574

Figure 34-4. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.2

105°C
85°C
25°C
-40°C

1.1
1

ICC (mA)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-5. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
5.5

105°C
85°C
25°C
-40°C

5
4.5

ICC (mA)

4
3.5
3
2.5
2
1.5
1
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

575

Idle Supply Current
Figure 34-6. ATmega168PA: Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.16

5.5V

0.14

5.0V

ICC (mA)

0.12
0.1

4.5V

0.08

4.0V
3.6V

0.06

2.7V

0.04

1.8V

0.02
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 34-7. ATmega168PA: Idle Supply Current vs. Frequency (1MHz - 20MHz)
2.7

5.5V

2.4

5.0V

2.1

4.5V

1.8
ICC (mA)

34.2

1.5

4.0V
1.2

3.6V

0.9
0.6

2.7V
0.3

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

576

Figure 34-8. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.045

105°C

0.04

85°C
0.035

ICC (mA)

0.03

25°C
-40°C

0.025
0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-9. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.3

105°C
85°C
25°C
-40°C

0.27
0.24

ICC (mA)

0.21
0.18
0.15
0.12
0.09
0.06
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

577

Figure 34-10.ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
1.3

105°C
85°C
25°C
-40°C

1.1

ICC (mA)

0.9

0.7

0.5

0.3

0.1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-down Supply Current
Figure 34-11.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
2.4

105°C

2.1
1.8
1.5
ICC (µA)

34.3

1.2
0.9

85°C

0.6
0.3

25°C
-40°C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

578

Figure 34-12.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
9

105°C

8

-40°C
85°C
25°C

ICC (µA)

7

6

5

4

3
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-save Supply Current
Figure 34-13.ATmega168PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running)
4

105°C
3.5
3
ICC (µA)

34.4

2.5

85°C
2
1.5

-40°C
25°C

1
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

579

34.5

Standby Supply Current
Figure 34-14.ATmega168PA: Standby Supply Current vs. VCC (Watchdog Timer Disabled).
0.15

6 MHz_res
6 MHz_xtal

0.14
0.13
0.12

4 MHz_res
4 MHz_xtal

0.11

ICC (mA)

0.1
0.09

2 MHz_res
2 MHz_xtal

0.08
0.07

1 MHz_res

0.06
0.05
0.04
0.03
0.02
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Pin Pull-Up
Figure 34-15.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
50
45
40
35
IOP (µA)

34.6

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

580

Figure 34-16.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60

IOP (µA)

50
40
30

25°C
85°C
-40°C
105°C

20
10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

Figure 34-17.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
140
120

IOP (µA)

100
80
60
40

25°C
85°C
-40°C
105°C

20
0
0

1

2

3

4

5

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

581

Figure 34-18.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 1.8V)
40
35

IRESET (µA)

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

Figure 34-19.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 2.7V)
60

50

IRESET (µA)

40

30

20

25°C
-40°C
85°C
105 C

10

0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

582

Figure 34-20.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (µA)

80

60

40

25°C
-40°C
85°C
105°C

20

0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

Pin Driver Strength
Figure 34-21.ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1

105°C
85°C

0.9
0.8
0.7
VOL (V)

34.7

25°C

0.6

-40°C

0.5
0.4
0.3
0.2
0.1
0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

583

Figure 34-22.ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.6

105°C
85°C

0.5

25°C
-40°C

VOL (V)

0.4

0.3

0.2

0.1

0
0

2

4

6

8

10

12

14

16

18

20

IOL (mA)

Figure 34-23.ATmega168PA: I/O Pin Output Voltage vs. Source Current (VCC = 3V)
3.1
2.9

VOH (V)

2.7
2.5

-40°C

2.3

25°C
2.1

85°C
105°C

1.9
1.7
0

5

10

15

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

584

Figure 34-24.ATmega168PA I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5
4.9

VOH (V)

4.8
4.7
4.6

-40°C
4.5

25°C
85°C
105°C

4.4
4.3
0

5

10

15

20

IOH (mA)

Pin Threshold and Hysteresis
Figure 34-25.ATmega168PA I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3

105°C
85°C
25°C
-40°C

2.8
2.6
2.4
Threshold (V)

34.8

2.2
2
1.8
1.6
1.4
1.2
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

585

Figure 34-26.ATmega168PA I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)

105°C
85°C
25°C
-40°C

2.5

Threshold (V)

2

1.5

1

0.5

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-27.ATmega168PA I/O Pin Input Hysteresis vs. VCC

85°C
105°C

0.6

-40°C

Input Hysteresis (V)

0.55
0.5

25°C

0.45
0.4
0.35
0.3
0.25
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

586

Figure 34-28.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
1.5

-40°C
25°C
85°C
105°C

1.4

Threshold (V)

1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-29.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

2.3
2.1

Threshold (V)

1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

587

Figure 34-30.ATmega168PA: Reset Pin Input Hysteresis vs. VCC
0.7

-40°C
0.6

Input Hysteresis (V)

0.5

25°C
0.4
0.3

85°C

0.2

105°C
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

BOD Threshold
Figure 34-31.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.83
1.82

Rising Vcc

1.81
Threshold (V)

34.9

1.8
1.79

Falling Vcc
1.78
1.77
1.76
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

588

Figure 34-32.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.76
2.74

Rising Vcc
Threshold (V)

2.72
2.7
2.68

Falling Vcc
2.66
2.64
2.62
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

90

100 110

Temperature (°C)

Figure 34-33.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.32

Rising Vcc

Threshold (V)

4.3

4.28

4.26

4.24

Falling Vcc
4.22

4.2
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

589

Figure 34-34.ATmega168PA: Calibrated Bandgap Voltage vs. Vcc
1.136
1.134

Bandgap Voltage (V)

1.132
1.13
1.128

85°C
105°C
25°C

1.126
1.124
1.122
1.12
1.118

-40°C

1.116
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 34-35.ATmega168PA: Calibrated Bandgap Voltage vs. Temperature
1.136

1.8V
2.7V
3.3V
4.0V
4.5V

1.134

Bandgap Voltage (V)

1.132
1.13
1.128

5.5V

1.126
1.124
1.122
1.12
1.118
1.116
-50

-30

-10

10

30

50

70

90

110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

590

34.10 Internal Oscillator Speed
Figure 34-36.ATmega168PA: Watchdog Oscillator Frequency vs. Temperature
122
120

FRC (kHz)

118
116
114

2.7V
3.3V
4.0V
4.5V
5.5V
5.0V

112
110
108
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature (°C)

Figure 34-37.ATmega168PA: Watchdog Oscillator Frequency vs. VCC
122
120

-40°C

FRC (kHz)

118

25°C

116
114
112

85°C

110

105°C
108
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

591

Figure 34-38.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.5
8.4

105°C
85°C

8.3

FRC (MHz)

8.2
8.1

25°C

8
7.9
7.8

-40°C

7.7
7.6
7.5
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-39.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.4

5.5V
4.5V
4.0V
3.3V
1.8V

8.3
8.2

FRC (MHz)

8.1
8
7.9
7.8
7.7
7.6
7.5
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

592

Figure 34-40.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
14

105°C
85°C
25°C
-40°C

12

FRC (MHz)

10

8

6

4

2
0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

34.11 Current Consumption of Peripheral Units
Figure 34-41.ATmega168PA: ADC Current vs. VCC (AREF = AVCC)
325

-40°C
25°C
85°C
105°C

300
275

ICC (µA)

250
225
200
175
150
125
100
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

593

Figure 34-42.ATmega168PA: Analog Comparator Current vs. VCC
90

-40°C
105°C
25°C
85°C

80

ICC (µA)

70

60

50

40

30
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-43.ATmega168PA: AREF External Reference Current vs. VCC
180

25°C
85°C
105°C
-40°C

160

ICC (µA)

140
120
100
80
60
40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

594

Figure 34-44.ATmega168PA: Brownout Detector Current vs. VCC

ICC (µA)

28
26

105°C

24

85°C

22

25°C
-40°C

20
18
16
14
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 34-45.ATmega168PA: Programming Current vs. VCC
9

-40°C
25°C

8
7

105°C
85°C

ICC (mA)

6
5
4
3
2
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

595

34.12 Current Consumption in Reset and Reset Pulsewidth
Figure 34-46.ATmega168PA: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.12

5.5V
0.1

ICC (mA)

0.08

4.5V
4.0V

0.06

3.3V

0.04

2.7V
1.8V

0.02

0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 34-47.ATmega168PA: Reset Supply Current vs. Frequency (1MHz - 20MHz)
2.4
2.1

5.5V

1.8

5.0V
4.5V

ICC (mA)

1.5
1.2

4.0V
0.9

3.6V

0.6

2.7V

0.3

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

596

Figure 34-48.ATmega168PA: Minimum Reset Pulse Width vs. Vcc
1800
1600

Pulsewidth (ns)

1400
1200
1000
800
600

105°C
85°C
25°C
-40°C

400
200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

597

35.

ATmega328P Typical Characteristics – (TA = -40°C to 105°C)
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
sine wave generator with rail-to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

ATmega328P Active Supply Current
Figure 35-1. ATmega328P: Active Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
1.2

5.5V
1

5.0V

ICC (mA)

35.1

0.8

4.5V

0.6

4.0V
3.6V

0.4

2.7V
1.8V

0.2

0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

598

ICC (mA)

Figure 35-2. ATmega328P: Active Supply Current vs. Frequency (1MHz - 20MHz)
14

5.5V

12

5.0V

10

4.5V

8

4.0V
6

3.6V

4

2.7V
2

1.8V
0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 35-3. ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.16

105°C
85°C
-40°C
25°C

0.14
0.12

ICC (mA)

0.1
0.08
0.06
0.04
0.02
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

599

Figure 35-4. ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.4

105°C
85°C
25°C
-40°C

1.2

ICC (mA)

1

0.8

0.6

0.4

0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-5. ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
7

105°C
85°C
25°C
-40°C

6

ICC (mA)

5

4

3

2

1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

600

Idle Supply Current
Figure 35-6. ATmega328P: Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.2

5.5V

0.18
0.16

5.0V

ICC (mA)

0.14

4.5V

0.12

4.0V
3.6V

0.1
0.08
0.06

2.7V

0.04

1.8V

0.02
0
0

0.2

0.4

0.6

0.8

1

Frequency (MHz)

Figure 35-7. ATmega328P: Idle Supply Current vs. Frequency (1MHz - 20MHz)

ICC (mA)

35.2

3.5

5.5V

3

5.0V

2.5

4.5V

2

4.0V
1.5

3.6V

1

2.7V
0.5

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

601

Figure 35-8. ATmega328P: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.05

105°C

0.045

85°C

0.04

ICC (mA)

0.035

25°C
-40°C

0.03
0.025
0.02
0.015
0.01
0.005
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-9. ATmega328P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.4

105°C
85°C
25°C
-40°C

0.35

ICC (mA)

0.3

0.25

0.2

0.15

0.1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

602

Figure 35-10.ATmega328P Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz)
1.8

105°C
85°C
25°C
-40°C

1.6
1.4

ICC (mA)

1.2
1
0.8
0.6
0.4
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-down Supply Current
Figure 35-11.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
3

105°C
2.5

2
ICC (µA)

35.3

1.5

85°C

1

0.5

25°C
-40°C

0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

603

Figure 35-12.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
10

105°C
9

-40°C
85°C
25°C

8

ICC (µA)

7
6
5
4
3
2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Power-save Supply Current
Figure 35-13.ATmega328P: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running)
4
3.5

105°C
3
2.5

ICC (µA)

35.4

2

85°C

1.5
1

25°C
-40°C

0.5
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

604

35.5

Standby Supply Current
Figure 35-14.ATmega328P: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.15

6 MHz_res
6 MHz_xtal

0.14
0.13
0.12

4 MHz_res
4 MHz_xtal

0.11
ICC (mA)

0.1
0.09

2 MHz_res
2 MHz_xtal

0.08
0.07

1 MHz_res

0.06
0.05
0.04
0.03
0.02
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Pin Pull-Up
Figure 35-15.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
50
45
40
35

IOP(µA)

35.6

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

605

Figure 35-16.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60

IOP (µA)

50
40
30
20

25°C
85°C
-40°C
105°C

10
0
0

0.5

1

1.5

2

2.5

3

VOP (V)

Figure 35-17.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
160
140
120

IOP (µA)

100
80
60

25°C
85°C
105°C
-40°C

40
20
0
0

1

2

3

4

5

VOP (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

606

Figure 35-18.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
40
35

IRESET (µA)

30
25
20
15

25°C
-40°C
85°C
105°C

10
5
0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VRESET (V)

Figure 35-19.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
60

50

IRESET (µA)

40

30

20

25°C
-40°C
85°C
105°C

10

0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

VRESET (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

607

Figure 35-20.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

IRESET (µA)

80

60

40

25°C
-40°C
85°C
105°C

20

0
0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VRESET (V)

Pin Driver Strength
Figure 35-21.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
1

105°C
85°C

0.9
0.8

25°C

0.7

VOL (V)

35.7

0.6

-40°C

0.5
0.4
0.3
0.2
0.1
0
0

5

10

15

20

IOL (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

608

Figure 35-22.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.7

105°C
85°C

0.6

VOL (V)

0.5

25°C

0.4

-40°C

0.3
0.2
0.1
0
0

5

10

15

20

IOL (mA)

Figure 35-23.ATmega328P: I/O Pin Output Voltage vs. Source Current (Vcc = 3V)
3.1

2.9

VOH (V)

2.7

2.5

-40°C

2.3

25°C
2.1

85°C
105°C

1.9
0

5

10

15

20

IOH (mA)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

609

Figure 35-24.ATmega328P: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5.1
5
4.9

VOH (V)

4.8
4.7
4.6

-40°C
4.5

25°C
85°C
105°C

4.4
4.3
0

5

10

15

20

IOH (mA)

Pin Threshold and Hysteresis
Figure 35-25.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3.1

105°C
85°C
25°C
-40°C

2.8
2.5

Threshold (V)

35.8

2.2
1.9
1.6
1.3
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

610

Figure 35-26.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’
2.6

105°C
2.3

85°C

2

25°C

Threshold (V)

-40°C
1.7
1.4
1.1
0.8
0.5
0.2
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-27.ATmega328P: I/O Pin Input Hysteresis vs. VCC
0.8

Input Hysteresis (mV)

0.7

-40°C
25°C
85°C
105°C

0.6

0.5

0.4

0.3

0.2
1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

611

Figure 35-28.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

Threshold (V)

2.6

-40°C

2.4

25°C

2.2

85°C

2

105°C

1.8
1.6
1.4
1.2
1
0.8
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-29.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5

105°C
85°C
25°C
-40°C

2.3
2.1

Threshold (V)

1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

612

Figure 35-30.ATmega328P: Reset Pin Input Hysteresis vs. VCC
0.7

-40°C
0.6

Input Hysteresis (V)

0.5

25°C
0.4
0.3

85°C

0.2

105°C
0.1
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

BOD Threshold
Figure 35-31.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.84

Rising Vcc

1.83

Threshold (V)

35.9

1.82

1.81

1.8

Falling Vcc
1.79

1.78
-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

613

Figure 35-32.ATmega328P BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
2.78
2.77

Rising Vcc

2.76

Threshold (V)

2.75
2.74
2.73
2.72
2.71
2.7

Falling Vcc

2.69
2.68
2.67
2.66
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

90

100 110

Temperature (°C)

Figure 35-33.ATmega328P BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.38
4.36

Rising Vcc

Threshold (V)

4.34
4.32
4.3
4.28

Falling Vcc

4.26
4.24
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

614

Figure 35-34.ATmega328P: Calibrated Bandgap Voltage vs. Vcc
1.139

Bandgap Voltage (V)

1.136

25°C

1.133

1.13

1.127

85°C
-40°C

1.124

105°C
1.121
1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

35.10 Internal Oscillator Speed
Figure 35-35.ATmega328P: Watchdog Oscillator Frequency vs. Temperature
120
118

FRC (kHz)

116
114
112
110

2.7V
3.6V
4.0V
5.5V

108
106
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

615

Figure 35-36.ATmega328PC Watchdog Oscillator Frequency vs. VCC
120
118

-40°C

FRC (kHz)

116

25°C

114
112
110

85°C

108

105°C

106
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-37.ATmega328P: Calibrated 8 MHz RC Oscillator Frequency vs. VCC
8.6

105°C
85°C

8.4

FRC (MHz)

8.2

25°C
8

-40°C

7.8
7.6
7.4
2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

616

Figure 35-38.ATmega328P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature

5.5V
5.0V
4.5V
4.0V
3.6V
2.7V

8.4
8.3
8.2

FRC (MHz)

8.1

1.8V

8
7.9
7.8
7.7
7.6
7.5
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100 110

Temperature (°C)

Figure 35-39.ATmega328P Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
14

105°C
85°C
25°C
-40°C

13
12

FRC (MHz)

11
10
9
8
7
6
5
4
0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

617

35.11 Current Consumption of Peripheral Units
Figure 35-40.ATmega328P: ADC Current vs. VCC (AREF = AVCC)
160

85°C
105°C
25°C
-40°C

140

ICC (µA)

120

100

80

60

40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-41.ATmega328P: Analog Comparator Current vs. VCC

ICC (µA)

100
90

-40°C

80

25°C
85°C
105°C

70
60
50
40
30
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

618

Figure 35-42.ATmega328P: AREF External Reference Current vs. VCC
180

85°C
105°C
25°C
-40°C

160

ICC (µA)

140
120
100
80
60
40
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

Figure 35-43.ATmega328P: Brownout Detector Current vs. VCC
30

105°C
85°C

ICC (µA)

25

25°C
-40°C
20

15

10
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

619

Figure 35-44.ATmega328P: Programming Current vs. VCC
10
9

25°C
85°C
105°C
-40°C

8

ICC (mA)

7
6
5
4
3
2
1
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

35.12 Current Consumption in Reset and Reset Pulsewidth
Figure 35-45.ATmega328P: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
0.16

5.5V

ICC (mA)

0.14
0.12

5.0V

0.1

4.5V
4.0V
3.6V

0.08
0.06

2.7V
0.04

1.8V

0.02
0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

620

Figure 35-46.ATmega328P Reset Supply Current vs. Frequency (1MHz - 20MHz)
3

5.5V

2.5

5.0V
4.5V

ICC (mA)

2

4.0V

1.5

3.6V

1

2.7V

0.5

1.8V

0
0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 35-47.ATmega328P: Minimum Reset Pulse Width vs. Vcc
1800
1600

Pulsewidth (ns)

1400
1200
1000
800
600

105°C
85°C
25°C
-40°C

400
200
0
1.5

2

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

621

36. Register Summary
Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(0xFF)

Reserved

–

–

–

–

–

–

–

–

(0xFE)

Reserved

–

–

–

–

–

–

–

–

(0xFD)

Reserved

–

–

–

–

–

–

–

–

(0xFC)

Reserved

–

–

–

–

–

–

–

–

(0xFB)

Reserved

–

–

–

–

–

–

–

–

(0xFA)

Reserved

–

–

–

–

–

–

–

–

(0xF9)

Reserved

–

–

–

–

–

–

–

–

(0xF8)

Reserved

–

–

–

–

–

–

–

–

(0xF7)

Reserved

–

–

–

–

–

–

–

–

(0xF6)

Reserved

–

–

–

–

–

–

–

–

(0xF5)

Reserved

–

–

–

–

–

–

–

–

(0xF4)

Reserved

–

–

–

–

–

–

–

–

(0xF3)

Reserved

–

–

–

–

–

–

–

–

(0xF2)

Reserved

–

–

–

–

–

–

–

–

(0xF1)

Reserved

–

–

–

–

–

–

–

–

(0xF0)

Reserved

–

–

–

–

–

–

–

–

(0xEF)

Reserved

–

–

–

–

–

–

–

–

(0xEE)

Reserved

–

–

–

–

–

–

–

–

(0xED)

Reserved

–

–

–

–

–

–

–

–

(0xEC)

Reserved

–

–

–

–

–

–

–

–

(0xEB)

Reserved

–

–

–

–

–

–

–

–

(0xEA)

Reserved

–

–

–

–

–

–

–

–

(0xE9)

Reserved

–

–

–

–

–

–

–

–

(0xE8)

Reserved

–

–

–

–

–

–

–

–

(0xE7)

Reserved

–

–

–

–

–

–

–

–

(0xE6)

Reserved

–

–

–

–

–

–

–

–

(0xE5)

Reserved

–

–

–

–

–

–

–

–

(0xE4)

Reserved

–

–

–

–

–

–

–

–

(0xE3)

Reserved

–

–

–

–

–

–

–

–

(0xE2)

Reserved

–

–

–

–

–

–

–

–

(0xE1)

Reserved

–

–

–

–

–

–

–

–

(0xE0)

Reserved

–

–

–

–

–

–

–

–

(0xDF)

Reserved

–

–

–

–

–

–

–

–

(0xDE)

Reserved

–

–

–

–

–

–

–

–

(0xDD)

Reserved

–

–

–

–

–

–

–

–

(0xDC)

Reserved

–

–

–

–

–

–

–

–

(0xDB)

Reserved

–

–

–

–

–

–

–

–

(0xDA)

Reserved

–

–

–

–

–

–

–

–

(0xD9)

Reserved

–

–

–

–

–

–

–

–

(0xD8)

Reserved

–

–

–

–

–

–

–

–

(0xD7)

Reserved

–

–

–

–

–

–

–

–

(0xD6)

Reserved

–

–

–

–

–

–

–

–

(0xD5)

Reserved

–

–

–

–

–

–

–

–

(0xD4)

Reserved

–

–

–

–

–

–

–

–

(0xD3)

Reserved

–

–

–

–

–

–

–

–

(0xD2)

Reserved

–

–

–

–

–

–

–

–

(0xD1)

Reserved

–

–

–

–

–

–

–

–

(0xD0)

Reserved

–

–

–

–

–

–

–

–

(0xCF)

Reserved

–

–

–

–

–

–

–

–

(0xCE)

Reserved

–

–

–

–

–

–

–

–

(0xCD)

Reserved

–

–

–

–

–

–

–

–

(0xCC)

Reserved

–

–

–

–

–

–

–

–

(0xCB)

Reserved

–

–

–

–

–

–

–

–

(0xCA)

Reserved

–

–

–

–

–

–

–

–

(0xC9)

Reserved

–

–

–

–

–

–

–

–

(0xC8)

Reserved

–

–

–

–

–

–

–

–

(0xC7)

Reserved

–

–

–

–

–

–

–

–

(0xC6)

UDR0

(0xC5)

UBRR0H

USART I/O Data Register

194
USART Baud Rate Register High

(0xC4)

UBRR0L

(0xC3)

Reserved

–

–

198

USART Baud Rate Register Low
–

Page

198

–

–

–

–

–

(0xC2)

UCSR0C

UMSEL01

UMSEL00

UPM01

UPM00

USBS0

UCSZ01 /UDORD0

UCSZ00 / UCPHA0

UCPOL0

(0xC1)

UCSR0B

RXCIE0

TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

195

(0xC0)

UCSR0A

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

194

(0xBF)

Reserved

–

–

–

–

–

–

–

–

(0xBE)

Reserved

–

–

–

–

–

–

–

–

196/207

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

622

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBD)

TWAMR

TWAM6

TWAM5

TWAM4

TWAM3

TWAM2

TWAM1

TWAM0

–

237

(0xBC)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

235

(0xBB)

TWDR

(0xBA)

TWAR

TWA6

TWA5

TWA4

TWS7

TWS6

TWS5

2-wire Serial Interface Data Register

(0xB9)

TWSR

(0xB8)

TWBR

(0xB7)

Reserved

–

(0xB6)

ASSR

–

(0xB5)

Reserved

–

237

TWA3

TWA2

TWA1

TWA0

TWGCE

237

TWS4

TWS3

–

TWPS1

TWPS0

236

2-wire Serial Interface Bit Rate Register

235

–

–

–

–

–

–

EXCLK

AS2

TCN2UB

OCR2AUB

OCR2BUB

TCR2AUB

TCR2BUB

–

–

–

–

–

–

–

160

(0xB4)

OCR2B

Timer/Counter2 Output Compare Register B

159

(0xB3)

OCR2A

Timer/Counter2 Output Compare Register A

159

(0xB2)

TCNT2

(0xB1)

TCCR2B

FOC2A

FOC2B

–

Timer/Counter2 (8-bit)
–

WGM22

CS22

CS21

CS20

159
158

(0xB0)

TCCR2A

COM2A1

COM2A0

COM2B1

COM2B0

–

–

WGM21

WGM20

155

(0xAF)

Reserved

–

–

–

–

–

–

–

–

(0xAE)

Reserved

–

–

–

–

–

–

–

–

(0xAD)

Reserved

–

–

–

–

–

–

–

–

(0xAC)

Reserved

–

–

–

–

–

–

–

–

(0xAB)

Reserved

–

–

–

–

–

–

–

–

(0xAA)

Reserved

–

–

–

–

–

–

–

–

(0xA9)

Reserved

–

–

–

–

–

–

–

–

(0xA8)

Reserved

–

–

–

–

–

–

–

–

(0xA7)

Reserved

–

–

–

–

–

–

–

–

(0xA6)

Reserved

–

–

–

–

–

–

–

–

(0xA5)

Reserved

–

–

–

–

–

–

–

–

(0xA4)

Reserved

–

–

–

–

–

–

–

–

(0xA3)

Reserved

–

–

–

–

–

–

–

–

(0xA2)

Reserved

–

–

–

–

–

–

–

–

(0xA1)

Reserved

–

–

–

–

–

–

–

–

(0xA0)

Reserved

–

–

–

–

–

–

–

–

(0x9F)

Reserved

–

–

–

–

–

–

–

–

(0x9E)

Reserved

–

–

–

–

–

–

–

–

(0x9D)

Reserved

–

–

–

–

–

–

–

–

(0x9C)

Reserved

–

–

–

–

–

–

–

–

(0x9B)

Reserved

–

–

–

–

–

–

–

–

(0x9A)

Reserved

–

–

–

–

–

–

–

–

(0x99)

Reserved

–

–

–

–

–

–

–

–

(0x98)

Reserved

–

–

–

–

–

–

–

–

(0x97)

Reserved

–

–

–

–

–

–

–

–

(0x96)

Reserved

–

–

–

–

–

–

–

–

(0x95)

Reserved

–

–

–

–

–

–

–

–

(0x94)

Reserved

–

–

–

–

–

–

–

–

(0x93)

Reserved

–

–

–

–

–

–

–

–

(0x92)

Reserved

–

–

–

–

–

–

–

–

(0x91)

Reserved

–

–

–

–

–

–

–

–

(0x90)

Reserved

–

–

–

–

–

–

–

–

(0x8F)

Reserved

–

–

–

–

–

–

–

–

(0x8E)

Reserved

–

–

–

–

–

–

–

–

(0x8D)

Reserved

–

–

–

–

–

–

–

–

(0x8C)

Reserved

–

–

–

–

–

–

–

–

(0x8B)

OCR1BH

Timer/Counter1 - Output Compare Register B High Byte

136

(0x8A)

OCR1BL

Timer/Counter1 - Output Compare Register B Low Byte

136

(0x89)

OCR1AH

Timer/Counter1 - Output Compare Register A High Byte

136

(0x88)

OCR1AL

Timer/Counter1 - Output Compare Register A Low Byte

136

(0x87)

ICR1H

Timer/Counter1 - Input Capture Register High Byte

136

(0x86)

ICR1L

Timer/Counter1 - Input Capture Register Low Byte

136

(0x85)

TCNT1H

Timer/Counter1 - Counter Register High Byte

135

(0x84)

TCNT1L

Timer/Counter1 - Counter Register Low Byte

135

(0x83)

Reserved

–

–

–

–

–

–

–

(0x82)

TCCR1C

FOC1A

FOC1B

–

–

–

–

–

–

(0x81)

TCCR1B

ICNC1

ICES1

–

WGM13

WGM12

CS12

CS11

CS10

134

(0x80)

TCCR1A

COM1A1

COM1A0

COM1B1

COM1B0

–

–

WGM11

WGM10

132

–
135

(0x7F)

DIDR1

–

–

–

–

–

–

AIN1D

AIN0D

241

(0x7E)

DIDR0

–

–

ADC5D

ADC4D

ADC3D

ADC2D

ADC1D

ADC0D

257

(0x7D)

Reserved

–

–

–

–

–

–

–

–

(0x7C)

ADMUX

REFS1

REFS0

ADLAR

–

MUX3

MUX2

MUX1

MUX0

254

(0x7B)

ADCSRB

–

ACME

–

–

–

ADTS2

ADTS1

ADTS0

257

(0x7A)

ADCSRA

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

255

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

623

Address

Name

(0x79)

ADCH

Bit 7

Bit 6

Bit 5

ADC Data Register High byte

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(0x78)

ADCL

ADC Data Register Low byte

(0x77)

Reserved

–

–

–

–

–

–

–

–

(0x76)

Reserved

–

–

–

–

–

–

–

–

(0x75)

Reserved

–

–

–

–

–

–

–

–

(0x74)

Reserved

–

–

–

–

–

–

–

–

(0x73)

Reserved

–

–

–

–

–

–

–

–

(0x72)

Reserved

–

–

–

–

–

–

–

–

(0x71)

Reserved

–

–

–

–

–

–

–

–

(0x70)

TIMSK2

–

–

–

–

–

OCIE2B

OCIE2A

TOIE2

159

(0x6F)

TIMSK1

–

–

ICIE1

–

–

OCIE1B

OCIE1A

TOIE1

136

(0x6E)

TIMSK0

–

–

–

–

–

OCIE0B

OCIE0A

TOIE0

110

(0x6D)

PCMSK2

PCINT23

PCINT22

PCINT21

PCINT20

PCINT19

PCINT18

PCINT17

PCINT16

75

(0x6C)

PCMSK1

–

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

PCINT9

PCINT8

75

(0x6B)

PCMSK0

PCINT7

PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

PCINT1

PCINT0

75

(0x6A)

Reserved

–

–

–

–

–

–

–

–

(0x69)

EICRA

–

–

–

–

ISC11

ISC10

ISC01

ISC00

(0x68)

PCICR

–

–

–

–

–

PCIE2

PCIE1

PCIE0

(0x67)

Reserved

–

–

–

–

–

–

–

–

(0x66)

OSCCAL

(0x65)

Reserved

–

–

–

–

–

–

–

–

(0x64)

PRR

PRTWI

PRTIM2

PRTIM0

–

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

–

–

–

–

–

–

–

–

(0x62)

Reserved

–

–

–

–

–

–

–

–

(0x61)

CLKPR

CLKPCE

–

–

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

36

(0x60)

WDTCSR

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

54

0x3F (0x5F)

SREG

I

T

H

S

V

N

Z

C

9

0x3E (0x5E)

SPH

–

–

–

–

–

(SP10) 5.

SP9

SP8

12

0x3D (0x5D)

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

12

0x3C (0x5C)

Reserved

–

–

–

–

–

–

–

–

0x3B (0x5B)

Reserved

–

–

–

–

–

–

–

–

0x3A (0x5A)

Reserved

–

–

–

–

–

–

–

–

0x39 (0x59)

Reserved

–

–

–

–

–

–

–

–

0x38 (0x58)

Reserved

–

–

–

–

–

–

–

–

0x37 (0x57)

SPMCSR

SPMIE

(RWWSB)5.

SIGRD

(RWWSRE)5.

BLBSET

PGWRT

PGERS

SPMEN

0x36 (0x56)

Reserved

–

–

–

–

–

–

–

–

0x35 (0x55)

MCUCR

–

BODS(6)

BODSE(6)

PUD

–

–

IVSEL

IVCE

0x34 (0x54)

MCUSR

–

–

–

–

WDRF

BORF

EXTRF

PORF

54

0x33 (0x53)

SMCR

–

–

–

–

SM2

SM1

SM0

SE

39

0x32 (0x52)

Reserved

–

–

–

–

–

–

–

–

0x31 (0x51)

Reserved

–

–

–

–

–

–

–

–

0x30 (0x50)

ACSR

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

0x2F (0x4F)

Reserved

–

–

–

–

–

–

–

–

0x2E (0x4E)

SPDR

0x2D (0x4D)

SPSR

SPIF

WCOL

–

–

–

–

–

SPI2X

170

0x2C (0x4C)

SPCR

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

169

0x2B (0x4B)

GPIOR2

General Purpose I/O Register 2

0x2A (0x4A)

GPIOR1

General Purpose I/O Register 1

0x29 (0x49)

Reserved

0x28 (0x48)

OCR0B

Timer/Counter0 Output Compare Register B

0x27 (0x47)

OCR0A

Timer/Counter0 Output Compare Register A

0x26 (0x46)

TCNT0

0x25 (0x45)

TCCR0B

FOC0A

FOC0B

–

–

WGM02

CS02

CS01

CS00

0x24 (0x44)

TCCR0A

COM0A1

COM0A0

COM0B1

COM0B0

–

–

WGM01

WGM00

0x23 (0x43)

GTCCR

TSM

–

–

–

–

–

PSRASY

PSRSYNC

0x22 (0x42)

EEARH

(EEPROM Address Register High Byte) 5.

0x21 (0x41)

EEARL

EEPROM Address Register Low Byte

21

0x20 (0x40)

EEDR

EEPROM Data Register

21

256
256

Oscillator Calibration Register

–

–

–

72

36

SPI Data Register

–

Page

41

283
44/69/92

240
171

25
25

–

–

–

–

Timer/Counter0 (8-bit)

–

–

EEPM1

EEPM0

EERIE

141/161
21

0x1F (0x3F)

EECR

0x1E (0x3E)

GPIOR0

EEMPE

EEPE

EERE

21

0x1D (0x3D)

EIMSK

–

–

–

–

–

–

INT1

INT0

73

0x1C (0x3C)

EIFR

–

–

–

–

–

–

0x1B (0x3B)

PCIFR

–

–

–

–

–

PCIF2

INTF1

INTF0

73

PCIF1

PCIF0

0x1A (0x3A)

Reserved

–

–

–

–

–

–

–

–

0x19 (0x39)

Reserved

–

–

–

–

–

–

–

–

0x18 (0x38)

Reserved

–

–

–

–

–

–

–

–

0x17 (0x37)

TIFR2

–

–

–

–

–

OCF2B

OCF2A

TOV2

160

0x16 (0x36)

TIFR1

–

–

ICF1

–

–

OCF1B

OCF1A

TOV1

137

General Purpose I/O Register 0

25

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

624

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x15 (0x35)

TIFR0

–

–

–

–

–

OCF0B

OCF0A

TOV0

Page

0x14 (0x34)

Reserved

–

–

–

–

–

–

–

–

0x13 (0x33)

Reserved

–

–

–

–

–

–

–

–

0x12 (0x32)

Reserved

–

–

–

–

–

–

–

–

0x11 (0x31)

Reserved

–

–

–

–

–

–

–

–

0x10 (0x30)

Reserved

–

–

–

–

–

–

–

–

0x0F (0x2F)

Reserved

–

–

–

–

–

–

–

–

0x0E (0x2E)

Reserved

–

–

–

–

–

–

–

–

0x0D (0x2D)

Reserved

–

–

–

–

–

–

–

–

0x0C (0x2C)

Reserved

–

–

–

–

–

–

–

–

0x0B (0x2B)

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

93

0x0A (0x2A)

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

93

0x09 (0x29)

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

93

0x08 (0x28)

PORTC

–

PORTC6

PORTC5

PORTC4

PORTC3

PORTC2

PORTC1

PORTC0

92

0x07 (0x27)

DDRC

–

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

92

0x06 (0x26)

PINC

–

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

92

0x05 (0x25)

PORTB

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

92

0x04 (0x24)

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

92

0x03 (0x23)

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

92

0x02 (0x22)

Reserved

–

–

–

–

–

–

–

–

0x01 (0x21)

Reserved

–

–

–

–

–

–

–

–

0x0 (0x20)

Reserved

–

–

–

–

–

–

–

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48A/PA/88A/PA/168A/PA/328/P is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for ATmega88A/88PA/168A/168PA/328/328P.
6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

625

37. Instruction Set Summary
Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS
ADD

Rd, Rr

Add two Registers

Rd  Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry two Registers

Rd  Rd + Rr + C

Z,C,N,V,H

1

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl  Rdh:Rdl + K

Z,C,N,V,S

2

SUB

Rd, Rr

Subtract two Registers

Rd  Rd - Rr

Z,C,N,V,H

1

SUBI

Rd, K

Subtract Constant from Register

Rd  Rd - K

Z,C,N,V,H

1

SBC

Rd, Rr

Subtract with Carry two Registers

Rd  Rd - Rr - C

Z,C,N,V,H

1

SBCI

Rd, K

Subtract with Carry Constant from Reg.

Rd  Rd - K - C

Z,C,N,V,H

1

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl  Rdh:Rdl - K

Z,C,N,V,S

2

AND

Rd, Rr

Logical AND Registers

Rd Rd  Rr

Z,N,V

1

ANDI

Rd, K

Logical AND Register and Constant

Rd  Rd K

Z,N,V

1

OR

Rd, Rr

Logical OR Registers

Rd  Rd v Rr

Z,N,V

1

ORI

Rd, K

Logical OR Register and Constant

Rd Rd v K

Z,N,V

1

EOR

Rd, Rr

Exclusive OR Registers

Rd  Rd  Rr

Z,N,V

1

1

COM

Rd

One’s Complement

Rd  0xFF  Rd

Z,C,N,V

1

NEG

Rd

Two’s Complement

Rd  0x00  Rd

Z,C,N,V,H

1

SBR

Rd,K

Set Bit(s) in Register

Rd  Rd v K

Z,N,V

1

CBR

Rd,K

Clear Bit(s) in Register

Rd  Rd  (0xFF - K)

Z,N,V

1

INC

Rd

Increment

Rd  Rd + 1

Z,N,V

1

DEC

Rd

Decrement

Rd  Rd  1

Z,N,V

1

TST

Rd

Test for Zero or Minus

Rd  Rd  Rd

Z,N,V

1

CLR

Rd

Clear Register

Rd  Rd  Rd

Z,N,V

1

SER

Rd

Set Register

Rd  0xFF

None

1

MUL

Rd, Rr

Multiply Unsigned

R1:R0  Rd x Rr

Z,C

2

MULS

Rd, Rr

Multiply Signed

R1:R0  Rd x Rr

Z,C

2

MULSU

Rd, Rr

Multiply Signed with Unsigned

R1:R0  Rd x Rr

Z,C

2

FMUL

Rd, Rr

Fractional Multiply Unsigned

R1:R0  (Rd x Rr) << 1

Z,C

2

FMULS

Rd, Rr

Fractional Multiply Signed

R1:R0  (Rd x Rr) << 1

Z,C

2

FMULSU

Rd, Rr

Fractional Multiply Signed with Unsigned

R1:R0  (Rd x Rr) << 1

Z,C

2
2

BRANCH INSTRUCTIONS
RJMP

k

IJMP

Relative Jump

PC PC + k + 1

None

Indirect Jump to (Z)

PC  Z

None

2

JMP(1)

k

Direct Jump

PC k

None

3

RCALL

k

Relative Subroutine Call

PC  PC + k + 1

None

3

Indirect Call to (Z)

PC  Z

None

3

Direct Subroutine Call

PC  k

None

4

RET

Subroutine Return

PC  STACK

None

4

RETI

Interrupt Return

PC  STACK

I

4

ICALL
CALL(1)

k

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC PC + 2 or 3

None

CP

Rd,Rr

Compare

Rd  Rr

Z, N,V,C,H

1/2/3
1

CPC

Rd,Rr

Compare with Carry

Rd  Rr  C

Z, N,V,C,H

1

CPI

Rd,K

Compare Register with Immediate

Rd  K

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC  PC + 2 or 3

None

1/2/3

1

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC  PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC  PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC  PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PCPC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PCPC+k + 1

None

1/2

BREQ

k

Branch if Equal

if (Z = 1) then PC  PC + k + 1

None

1/2

BRNE

k

Branch if Not Equal

if (Z = 0) then PC  PC + k + 1

None

1/2

BRCS

k

Branch if Carry Set

if (C = 1) then PC  PC + k + 1

None

1/2

BRCC

k

Branch if Carry Cleared

if (C = 0) then PC  PC + k + 1

None

1/2

BRSH

k

Branch if Same or Higher

if (C = 0) then PC  PC + k + 1

None

1/2

BRLO

k

Branch if Lower

if (C = 1) then PC  PC + k + 1

None

1/2

BRMI

k

Branch if Minus

if (N = 1) then PC  PC + k + 1

None

1/2

BRPL

k

Branch if Plus

if (N = 0) then PC  PC + k + 1

None

1/2

BRGE

k

Branch if Greater or Equal, Signed

if (N  V= 0) then PC  PC + k + 1

None

1/2

BRLT

k

Branch if Less Than Zero, Signed

if (N  V= 1) then PC  PC + k + 1

None

1/2

BRHS

k

Branch if Half Carry Flag Set

if (H = 1) then PC  PC + k + 1

None

1/2

BRHC

k

Branch if Half Carry Flag Cleared

if (H = 0) then PC  PC + k + 1

None

1/2

BRTS

k

Branch if T Flag Set

if (T = 1) then PC  PC + k + 1

None

1/2

BRTC

k

Branch if T Flag Cleared

if (T = 0) then PC  PC + k + 1

None

1/2

BRVS

k

Branch if Overflow Flag is Set

if (V = 1) then PC  PC + k + 1

None

1/2

BRVC

k

Branch if Overflow Flag is Cleared

if (V = 0) then PC  PC + k + 1

None

1/2

BRIE

k

Branch if Interrupt Enabled

if ( I = 1) then PC  PC + k + 1

None

1/2

BRID

k

Branch if Interrupt Disabled

if ( I = 0) then PC  PC + k + 1

None

1/2

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

626

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BIT AND BIT-TEST INSTRUCTIONS
SBI

P,b

Set Bit in I/O Register

I/O(P,b)  1

None

2

CBI

P,b

Clear Bit in I/O Register

I/O(P,b)  0

None

2

LSL

Rd

Logical Shift Left

Rd(n+1)  Rd(n), Rd(0)  0

Z,C,N,V

1

LSR

Rd

Logical Shift Right

Rd(n)  Rd(n+1), Rd(7)  0

Z,C,N,V

1

ROL

Rd

Rotate Left Through Carry

Rd(0)C,Rd(n+1) Rd(n),CRd(7)

Z,C,N,V

1

ROR

Rd

Rotate Right Through Carry

Rd(7)C,Rd(n) Rd(n+1),CRd(0)

Z,C,N,V

1

ASR

Rd

Arithmetic Shift Right

Rd(n)  Rd(n+1), n=0...6

Z,C,N,V

1

SWAP

Rd

Swap Nibbles

Rd(3...0)Rd(7...4),Rd(7...4)Rd(3...0)

None

1

BSET

s

Flag Set

SREG(s)  1

SREG(s)

1

BCLR

s

Flag Clear

SREG(s)  0

SREG(s)

1

BST

Rr, b

Bit Store from Register to T

T  Rr(b)

T

1

BLD

Rd, b

Bit load from T to Register

Rd(b)  T

None

1

SEC

Set Carry

C1

C

1

CLC

Clear Carry

C0

C

1

SEN

Set Negative Flag

N1

N

1

CLN

Clear Negative Flag

N0

N

1

SEZ

Set Zero Flag

Z1

Z

1

CLZ

Clear Zero Flag

Z0

Z

1

SEI

Global Interrupt Enable

I1

I

1

CLI

Global Interrupt Disable

I 0

I

1

SES

Set Signed Test Flag

S1

S

1

CLS

Clear Signed Test Flag

S0

S

1

SEV

Set Twos Complement Overflow.

V1

V

1

CLV

Clear Twos Complement Overflow

V0

V

1

SET

Set T in SREG

T1

T

1

CLT

Clear T in SREG

T0

T

1

SEH

Set Half Carry Flag in SREG

H1

H

1

CLH

Clear Half Carry Flag in SREG

H0

H

1

DATA TRANSFER INSTRUCTIONS
MOV

Rd, Rr

Move Between Registers

Rd  Rr

None

1

MOVW

Rd, Rr

Copy Register Word

Rd+1:Rd  Rr+1:Rr

None

1

LDI

Rd, K

Load Immediate

Rd  K

None

1

LD

Rd, X

Load Indirect

Rd  (X)

None

2

LD

Rd, X+

Load Indirect and Post-Inc.

Rd  (X), X  X + 1

None

2

LD

Rd, - X

Load Indirect and Pre-Dec.

X  X - 1, Rd  (X)

None

2

LD

Rd, Y

Load Indirect

Rd  (Y)

None

2

LD

Rd, Y+

Load Indirect and Post-Inc.

Rd  (Y), Y  Y + 1

None

2

LD

Rd, - Y

Load Indirect and Pre-Dec.

Y  Y - 1, Rd  (Y)

None

2

LDD

Rd,Y+q

Load Indirect with Displacement

Rd  (Y + q)

None

2

LD

Rd, Z

Load Indirect

Rd  (Z)

None

2

LD

Rd, Z+

Load Indirect and Post-Inc.

Rd  (Z), Z  Z+1

None

2

LD

Rd, -Z

Load Indirect and Pre-Dec.

Z  Z - 1, Rd  (Z)

None

2

LDD

Rd, Z+q

Load Indirect with Displacement

Rd  (Z + q)

None

2

LDS

Rd, k

Load Direct from SRAM

Rd  (k)

None

2

ST

X, Rr

Store Indirect

(X) Rr

None

2

ST

X+, Rr

Store Indirect and Post-Inc.

(X) Rr, X  X + 1

None

2

ST

- X, Rr

Store Indirect and Pre-Dec.

X  X - 1, (X)  Rr

None

2

ST

Y, Rr

Store Indirect

(Y)  Rr

None

2

ST

Y+, Rr

Store Indirect and Post-Inc.

(Y)  Rr, Y  Y + 1

None

2

ST

- Y, Rr

Store Indirect and Pre-Dec.

Y  Y - 1, (Y)  Rr

None

2

STD

Y+q,Rr

Store Indirect with Displacement

(Y + q)  Rr

None

2

ST

Z, Rr

Store Indirect

(Z)  Rr

None

2

ST

Z+, Rr

Store Indirect and Post-Inc.

(Z)  Rr, Z  Z + 1

None

2

ST

-Z, Rr

Store Indirect and Pre-Dec.

Z  Z - 1, (Z)  Rr

None

2

STD

Z+q,Rr

Store Indirect with Displacement

(Z + q)  Rr

None

2

STS

k, Rr

Store Direct to SRAM

(k)  Rr

None

2

Load Program Memory

R0  (Z)

None

3

LPM
LPM

Rd, Z

Load Program Memory

Rd  (Z)

None

3

LPM

Rd, Z+

Load Program Memory and Post-Inc

Rd  (Z), Z  Z+1

None

3

Store Program Memory

(Z)  R1:R0

None

-

IN

Rd, P

In Port

Rd  P

None

1

OUT

P, Rr

Out Port

P  Rr

None

1

PUSH

Rr

Push Register on Stack

STACK  Rr

None

2

POP

Rd

Pop Register from Stack

Rd  STACK

None

2

None

1

None

1

SPM

MCU CONTROL INSTRUCTIONS
NOP

No Operation

SLEEP

Sleep

(see specific descr. for Sleep function)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

627

Mnemonics
WDR
BREAK

Note:

Operands

Description
Watchdog Reset
Break

Operation
(see specific descr. for WDR/timer)
For On-chip Debug Only

Flags

#Clocks

None
None

1
N/A

1. These instructions are only available in ATmega168PA and ATmega328P.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

628

38. Ordering Information
38.1

ATmega48A

Speed (MHz)

20(3)

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega48A-AU
ATmega48A-AUR(5)
ATmega48A-CCU
ATmega48A-CCUR(5)
ATmega48A-MMH(4)
ATmega48A-MMHR(4)(5)
ATmega48A-MU
ATmega48A-MUR(5)
ATmega48A-PU

32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3

Operational Range(6)

Industrial
(-40C to 85C)

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. See ”Speed Grades” on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel.
6. Use ”ATmega48PA” on page 630, industrial (-40C to 105C) as the ATmega48A (-40C to 105C) is not presently offered.

Package Type
32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5 mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

629

38.2

ATmega48PA

Speed (MHz)(3)

20

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega48PA-AU
ATmega48PA-AUR(5)
ATmega48PA-CCU
ATmega48PA-CCUR(5)
ATmega48PA-MMH(4)
ATmega48PA-MMHR(4)(5)
ATmega48PA-MU
ATmega48PA-MUR(5)
ATmega48PA-PU

32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3

Industrial
(-40C to 85C)

ATmega48PA-AN
ATmega48PA-ANR(5)
ATmega48PA-MMN(4)
ATmega48PA-MMNR(4)(5)
ATmega48PA-MN
ATmega48PA-MNR(5)
ATmega48PA-PN

32A
32A
28M1
28M1
32M1-A
32M1-A
28P3

Industrial
(-40C to 105C)

Operational Range

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. See ”Speed Grades” on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

630

38.3

ATmega88A

Speed (MHz)

20(3)

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega88A-AU
ATmega88A-AUR(5)
ATmega88A-CCU
ATmega88A-CCUR(5)
ATmega88A-MMH(4)
ATmega88A-MMHR(4)(5)
ATmega88A-MU
ATmega88A-MUR(5)
ATmega88A-PU

32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3

Operational Range(6)

Industrial
(-40C to 85C)

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel.
6. Use ”ATmega88PA” on page 632, industrial (-40C to 105C) as the ATmega48A (-40C to 105C) is not presently offered.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

631

38.4

ATmega88PA

Speed (MHz)(3)

20

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega88PA-AU
ATmega88PA-AUR(5)
ATmega88PA-CCU
ATmega88PA-CCUR(5)
ATmega88PA-MMH(4)
ATmega88PA-MMHR(4)(5)
ATmega88PA-MU
ATmega88PA-MUR(5)
ATmega88PA-PU

32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3

Industrial
(-40C to 85C)

ATmega88PA-AN
ATmega88PA-ANR(5)
ATmega88PA-MMN(4)
ATmega88PA-MMNR(4)(5)
ATmega88PA-MN
ATmega88PA-MNR(5)
ATmega88PA-PN

32A
32A
28M1
28M1
32M1-A
32M1-A
28P3

Industrial
(-40C to 105C)

Operational Range

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5 mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

632

38.5

ATmega168A

Speed (MHz)(3)

20

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega168A-AU
ATmega168A-AUR(5)
ATmega168A-CCU
ATmega168A-CCUR(5)
ATmega168A-MMH(4)
ATmega168A-MMHR(4)(5)
ATmega168A-MU
ATmega168A-MUR(5)
ATmega168A-PU

32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3

Operational Range(6)

Industrial
(-40C to 85C)

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 310
4. NiPdAu Lead Finish.
5. Tape & Reel.
6. Use ”ATmega168PA” on page 634, industrial (-40C to 105C) as the ATmega48A (-40C to 105C) is not presently offered.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

633

38.6

ATmega168PA

Speed (MHz)(3)

20

20

Note:

Ordering Code(2)

Package(1)

1.8 - 5.5

ATmega168PA-AU
ATmega168PA-AUR(5)
ATmega168PA-CCU
ATmega168PA-CCUR(5)
ATmega168PA-MMH(4)
ATmega168PA-MMHR(4)(5)
ATmega168PA-MU
ATmega168PA-MUR(5)
ATmega168PA-PU

32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3

Industrial
(-40C to 85C)

1.8 - 5.5

ATmega168PA-AN
ATmega168PA-ANR(5)
ATmega168PA-MN
ATmega168PA-MNR(5)
ATmega168PA-PN

32A
32A
32M1-A
32M1-A
28P3

Industrial
(-40C to 105C)

Power Supply (V)

Operational Range

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

634

38.7

ATmega328

Speed (MHz)

20(3)

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega328-AU
ATmega328-AUR(5)
ATmega328-MMH(4)
ATmega328-MMHR(4)(5)
ATmega328-MU
ATmega328-MUR(5)
ATmega328-PU

32A
32A
28M1
28M1
32M1-A
32M1-A
28P3

Operational Range(6)

Industrial
(-40C to 85C)

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 29-1 on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel
6. Use ”ATmega328P” on page 636, industrial (-40C to 105C) as the ATmega48A (-40C to 105C) is not presently offered.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

635

38.8

ATmega328P

Speed (MHz)(3)

20

Note:

Power Supply (V)

1.8 - 5.5

Ordering Code(2)

Package(1)

ATmega328P-AU
ATmega328P-AUR(5)
ATmega328P-MMH(4)
ATmega328P-MMHR(4)(5)
ATmega328P-MU
ATmega328P-MUR(5)
ATmega328P-PU

32A
32A
28M1
28M1
32M1-A
32M1-A
28P3

Industrial
(-40C to 85C)

ATmega328P-AN
ATmega328P-ANR(5)
ATmega328P-MN
ATmega328P-MNR(5)
ATmega328P-PN

32A
32A
32M1-A
32M1-A
28P3

Industrial
(-40C to 105C)

Operational Range

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 29-1 on page 310.
4. NiPdAu Lead Finish.
5. Tape & Reel.

Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

636

39. Packaging Information
39.1

32A

PIN 1 IDENTIFIER

PIN 1
e

B
E1

E

D1
D

C

0°~7°
A1

A2

A

L
COMMON DIMENSIONS
(Unit of measure = mm)

Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.

SYMBOL

MIN

NOM

MAX

A

–

–

1.20

A1

0.05

–

0.15

A2

0.95

1.00

1.05

D

8.75

9.00

9.25

D1

6.90

7.00

7.10

E

8.75

9.00

9.25

E1

6.90

7.00

7.10

B

0.30

–

0.45

C

0.09

–

0.20

L

0.45

–

0.75

e

NOTE

Note 2

Note 2

0.80 TYP

2010-10-20
DRAWING NO.

TITLE
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

32A

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

REV.
C

637

39.2

32CC1

1 2

3 4

5

6

0.08

A
B

Pin#1 ID

C
D

SIDE VIEW

D

E
b1

F

A1
E

A
A2

TOP VIEW

E1
e
1 2

3 4

5

32-Øb

6

F

D1

COMMON DIMENSIONS
(Unit of Measure = mm)

E
D
B
A

A1 BALL CORNER

MIN

NOM

MAX

A

–

–

0.60

A1

0.12

–

–

SYMBOL

C
e

BOTTOM VIEW

A2
0.25

b1

0.25

D

3.90

D1

Note1: Dimension “b” is measured at the maximum ball dia. in a plane parallel
to the seating plane.
Note2: Dimension “b1” is the solderable surface defined by the opening of the
solder resist layer.

Package Drawing Contact:
packagedrawings@atmel.com

0.38 REF

b

E

0.30

0.35

1

–

–

2

4.00

4.10

2.50 BSC
3.90

4.00

4.10

E1

2.50 BSC

e

0.50 BSC

TITLE
32CC1, 32-ball (6 x 6 Array), 4 x 4 x 0.6 mm
package, ball pitch 0.50 mm, Ultra Thin,
Fine-Pitch Ball Grid Array (UFBGA)

NOTE

GPC
CAG

DRAWING NO.

07/06/10
REV.

32CC1

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

B

638

39.3

28M1

D
C

1
2

Pin 1 ID

3

E

SIDE VIEW

A1

TOP VIEW
A

y
D2

K

1

0.45

2

R 0.20

3

E2
b

COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL

MIN

NOM

MAX

A

0.80

0.90

1.00

A1

0.00

0.02

0.05

b

0.17

0.22

0.27

C

L
e
0.4 Ref
(4x)

Note:

0.20 REF

D

3.95

4.00

4.05

D2

2.35

2.40

2.45

E

3.95

4.00

4.05

E2

2.35

2.40

2.45

e

BOTTOM VIEW

The terminal #1 ID is a Laser-marked Feature.

NOTE

0.45

L

0.35

0.40

0.45

y

0.00

–

0.08

K

0.20

–

–

10/24/08
Package Drawing Contact:
packagedrawings@atmel.com

TITLE
28M1, 28-pad, 4 x 4 x 1.0mm Body, Lead Pitch 0.45mm,
2.4 x 2.4mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)

GPC
ZBV

DRAWING NO.

REV.

28M1

B

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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639

39.4

32M1-A

D
D1

1
2
3

0

Pin 1 ID
E1

SIDE VIEW

E

TOP VIEW

A3
A2
A1
A

K

0.08 C

P
D2

1
2
3

P
Pin #1 Notch
(0.20 R)

K

e

SYMBOL

MIN

NOM

MAX

A

0.80

0.90

1.00

A1

–

0.02

0.05

A2

–

0.65

1.00

A3
E2

b

COMMON DIMENSIONS
(Unit of Measure = mm)

L

BOTTOM VIEW

0.20 REF

b

0.18

0.23

0.30

D

4.90

5.00

5.10

D1

4.70

4.75

4.80

D2

2.95

3.10

3.25

E

4.90

5.00

5.10

E1

4.70

4.75

4.80

E2

2.95

3.10

3.25

e

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

NOTE

0.50 BSC

L

0.30

0.40

0.50

P

–

–

0

–

–

0.60
12o

K

0.20

–

–

5/25/06

R

2325 Orchard Parkway
San Jose, CA 95131

TITLE
32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm,
3.10mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.
32M1-A

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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REV.
E

640

39.5

28P3

D

PIN
1

E1

A

SEATING PLANE

L

B2
B1

A1

B

(4 PLACES)

0º ~ 15º

REF

e
E

C

COMMON DIMENSIONS
(Unit of Measure = mm)
NOM

MAX

–

4.5724

A1

0.508

–

–

D

34.544

–

34.798

E

7.620

–

8.255

A

eB

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").

MIN
–

SYMBOL

E1

7.112

–

7.493

B

0.381

–

0.533

B1

1.143

–

1.397

B2

0.762

–

1.143

L

3.175

–

3.429

C

0.203

–

0.356

eB

–

–

10.160

e

NOTE

Note 1

Note 1

2.540 TYP

09/28/01

R

2325 Orchard Parkway
San Jose, CA 95131

TITLE
28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP)

DRAWING NO.
28P3

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271G–AVR–02/2013

REV.
B

641

40. Errata
40.1

Errata ATmega48A
The revision letter in this section refers to the revision of the ATmega48A device.

40.1.1

Rev. D
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

40.2

Errata ATmega48PA
The revision letter in this section refers to the revision of the ATmega48PA device.

40.2.1

Rev. D
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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40.3

Errata ATmega88A
The revision letter in this section refers to the revision of the ATmega88A device.

40.3.1

Rev. F
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

40.4

Errata ATmega88PA
The revision letter in this section refers to the revision of the ATmega88PA device.

40.4.1

Rev. F
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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643

40.5

Errata ATmega168A
The revision letter in this section refers to the revision of the ATmega168A device.

40.5.1

Rev. E
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

40.6

Errata ATmega168PA
The revision letter in this section refers to the revision of the ATmega168PA device.

40.6.1

Rev E
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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40.7

Errata ATmega328
The revision letter in this section refers to the revision of the ATmega328 device.

40.7.1

Rev D
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

40.7.2

Rev C
Not sampled.

40.7.3

Rev B
• Analog MUX can be turned off when setting ACME bit
• Unstable 32kHz Oscillator
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. Unstable 32kHz Oscillator
The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is
inaccurate.
Problem Fix/ Workaround
None.

40.7.4

Rev A
• Analog MUX can be turned off when setting ACME bit
• Unstable 32kHz Oscillator
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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2. Unstable 32kHz Oscillator
The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is
inaccurate.
Problem Fix/ Workaround
None.

40.8

Errata ATmega328P
The revision letter in this section refers to the revision of the ATmega328P device.

40.8.1

Rev D
• Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit
after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.

40.8.2

Rev C
Not sampled.

40.8.3

Rev B
• Analog MUX can be turned off when setting ACME bit
• Unstable 32kHz Oscillator
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. Unstable 32kHz Oscillator
The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is
inaccurate.
Problem Fix/ Workaround
None.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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40.8.4

Rev A
• Unstable 32kHz Oscillator
1. Unstable 32kHz Oscillator
The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is
inaccurate.
Problem Fix/ Workaround
None.

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41. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in
this section are referring to the document revision.

41.1

Rev. 8271G – 02/2013

1.
2.
3.
4.
5.

41.2

Rev. 8271F – 08/2012

1.

2.

3.
4.
5.

41.3

Added ”Electrical Characteristics (TA = -40°C to 105°C)” on page 320.
Added ”ATmega48PA Typical Characteristics – (TA = -40°C to 105°C)” on page 525.
Added ”ATmega88PA Typical Characteristics – (TA = -40°C to 105°C)” on page 549.
Added ”ATmega168PA Typical Characteristics – (TA = -40°C to 105°C)” on page 573.
Added ”ATmega328P Typical Characteristics – (TA = -40°C to 105°C)” on page 598.

Added ”DC Characteristics” on page 303. The following tables for DC characteristics - TA = -40C to 105C added:
Table 29-4 on page 305
Table 29-7 on page 307
Table 29-10 on page 308
Table 29-13 on page 310
Replaced the following typical characteristics by the plots that include les characteristics at “TA = -40C to 105C”:
”ATmega48PA Typical Characteristics” on page 350
”ATmega88PA Typical Characteristics” on page 399
”ATmega168PA Typical Characteristics” on page 450
”ATmega328P Typical Characteristics” on page 500
Removed the Power Save (Psave) maximum numbers for all devices throughout ”Electrical Characteristics – (TA =
-40°C to 85°C)” on page 303.
Changed the powerdown maximum numbers from 8.5 and 3µA to 10 and 5µA (ATmega48PA, ATmega88PA,
ATmega168PA and ATmega328P).
Changed the table note “Maximum values are characterized values and not test limits in production” to “Max values
are test limits in production throughout ”Electrical Characteristics – (TA = -40°C to 85°C)” on page 303.

Rev. 8271E – 07/2012

1.
2.
3.
4.
5.
6.
7.
8.
9.

Updated Figure 1-1 on page 2. Overlined “RESET” in 28 MLF top view and in 32 MLF top view.
Added EEAR9 bit to the ”EEARH and EEARL – The EEPROM Address Register” on page 21 and updated the all bit
descriptions accordingly.
Added a footnote “EEAR9 and EEAR8 are unused bits in ATmega48A/48PA and must always be written to zero” to
”EEARH and EEARL – The EEPROM Address Register” on page 21.
Updated Table 18-8 on page 157, “Waveform Generation Mode Bit Description” . WGM2, WGM1 and WGM0
changed to WGM22, WGM21 and WGM20 respectively.
Updated ”TCCR2B – Timer/Counter Control Register B” on page 158. bit 2 (CS22) and bit 3 (WGM22) changed
from R (read only) to R/W (read/write).
Updated the definition of fosc on page 174. fosc is the system clock frequency (not XTAL pin frequency)
Updated ”SPMCSR – Store Program Memory Control and Status Register” on page 267. Bit 0 renamed SPMEN
and added bit 5 “SIGRD”.
Replaced “SELFPRGEN” by “SPMEN” throughout the whole datasheet including in the “code examples”, except in
”Program And Data Memory Lock Bits” on page 285 and in ”Fuse Bits” on page 286.
Updated ”Register Summary” on page 622 to include the bits: SIGRD and SPMEN in the SMPCSR register.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
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10.
11.
12.

41.4

Rev. 8271D – 05/11

1.
2.
3.
4.
5.
6.
7.
8.

41.5

Added Atmel QTouch Sensing Capability Feature
Updated ”Register Description” on page 92 with PINxn as R/W.
Added a footnote to the PINxn, page 92.
Updated “Ordering Information”,”ATmega328” on page 635. Added “ATmega328-MMH” and “ATmega328-MMHR”.
Updated “Ordering Information”,”ATmega328P” on page 636. Added “ATmega328P-MMH” and “ATmega328PMMHR”.
Added “Ordering Information” for ATmega48PA/88PA/168PA/328P @ 105C
Updated ”Errata ATmega328” on page 645 and ”Errata ATmega328P” on page 646
Updated the datasheet according to the Atmel new brand style guide.

Rev. 8271C – 08/10

1.
2.
3.
4.

41.6

Updated the Table 29-1 on page 303. Removed the footnote.
Updated the footnote of the Table 29-18 on page 313. Removed the footnote “Note 2”.
Updated ”Errata” on page 642. Added “Errata” TWI Data setup time can be too short.

Added 32UFBGA Pinout, Table 1-1 on page 2.
Updated the “SRAM Data Memory”, Figure 8-3 on page 18.
Updated ”Ordering Information” on page 629 with CCU and CCUR code related to “32CC1” Package drawing.
“32CC1” Package drawing added ”Packaging Information” on page 637.

Rev. 8271B – 04/10

1.
2.
3.
4.

5.

Updated Table 9-8 with correct value for timer oscillator at xtal2/tos2
Corrected use of SBIS instructions in assembly code examples.
Corrected BOD and BODSE bits to R/W in Section 10.11.2 on page 44, Section 12.5 on page 69 and Section 14.4
on page 92
Figures for bandgap characterization added, Figure 31-34 on page 342, Figure 31-81 on page 367, Figure 31-128
on page 392, Figure 31-176 on page 418, Figure 31-223 on page 442, Figure 31-271 on page 468, Figure 31-318
on page 492 and Figure 31-365 on page 517.
Updated ”Packaging Information” on page 637 by replacing 28M1 with a correct corresponding package.

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41.7

Rev. 8271A – 12/09

1.
2

New datasheet 8271 with merged information for ATmega48PA, ATmega88PA, ATmega168PA and ATmega48A,
ATmega88A andATmega168A. Also included information on ATmega328 and ATmega328P
Changes done:
–
–
–
–
–
–
–
–
–
–

New devices added: ATmega48A/ATmega88A/ATmega168A and ATmega328
Updated Feature Description
Updated Table 2-1 on page 6
Added note for BOD Disable on page 39.
Added note on BOD and BODSE in ”MCUCR – MCU Control Register” on page 92 and ”Register
Description” on page 283
Added limitation informatin for the application ”Boot Loader Support – Read-While-Write SelfProgramming” on page 269
Added limitiation information for ”Program And Data Memory Lock Bits” on page 285
Added specified DC characteristics
Added typical characteristics
Removed exception information in ”Address Match Unit” on page 216.

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Table of Contents
Features ..................................................................................................... 1
1

Pin Configurations ................................................................................... 2
1.1Pin Descriptions .........................................................................................................3

2

Overview ................................................................................................... 5
2.1Block Diagram ...........................................................................................................5
2.2Comparison Between Processors .............................................................................6

3

Resources ................................................................................................. 7

4

Data Retention .......................................................................................... 7

5

About Code Examples ............................................................................. 7

6

Capacitive Touch Sensing ....................................................................... 7

7

AVR CPU Core .......................................................................................... 8
7.1Overview ....................................................................................................................8
7.2ALU – Arithmetic Logic Unit .......................................................................................9
7.3Status Register ..........................................................................................................9
7.4General Purpose Register File ................................................................................10
7.5Stack Pointer ...........................................................................................................12
7.6Instruction Execution Timing ...................................................................................13
7.7Reset and Interrupt Handling ...................................................................................13

8

AVR Memories ........................................................................................ 16
8.1Overview ..................................................................................................................16
8.2In-System Reprogrammable Flash Program Memory .............................................16
8.3SRAM Data Memory ................................................................................................18
8.4EEPROM Data Memory ..........................................................................................19
8.5I/O Memory ..............................................................................................................20
8.6Register Description ................................................................................................21

9

System Clock and Clock Options ......................................................... 26
9.1Clock Systems and their Distribution .......................................................................26
9.2Clock Sources .........................................................................................................27
9.3Low Power Crystal Oscillator ...................................................................................28
9.4Full Swing Crystal Oscillator ....................................................................................29
9.5Low Frequency Crystal Oscillator ............................................................................31
9.6Calibrated Internal RC Oscillator .............................................................................32

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9.7128kHz Internal Oscillator .......................................................................................33
9.8External Clock .........................................................................................................33
9.9Clock Output Buffer .................................................................................................34
9.10Timer/Counter Oscillator ........................................................................................34
9.11System Clock Prescaler ........................................................................................34
9.12Register Description ..............................................................................................36

10 Power Management and Sleep Modes ................................................. 38
10.1Sleep Modes ..........................................................................................................38
10.2BOD Disable(1) .......................................................................................................39
10.3Idle Mode ...............................................................................................................39
10.4ADC Noise Reduction Mode ..................................................................................39
10.5Power-down Mode .................................................................................................39
10.6Power-save Mode ..................................................................................................40
10.7Standby Mode .......................................................................................................40
10.8Extended Standby Mode .......................................................................................41
10.9Power Reduction Register .....................................................................................41
10.10Minimizing Power Consumption ..........................................................................41
10.11Register Description ............................................................................................43

11 System Control and Reset ..................................................................... 46
11.1Resetting the AVR .................................................................................................46
11.2Reset Sources .......................................................................................................46
11.3Power-on Reset .....................................................................................................47
11.4External Reset .......................................................................................................48
11.5Brown-out Detection ..............................................................................................48
11.6Watchdog System Reset .......................................................................................49
11.7Internal Voltage Reference ....................................................................................49
11.8Watchdog Timer ....................................................................................................50
11.9Register Description ..............................................................................................54

12 Interrupts ................................................................................................. 57
12.1Interrupt Vectors in ATmega48A and ATmega48PA .............................................57
12.2Interrupt Vectors in ATmega88A and ATmega88PA .............................................59
12.3Interrupt Vectors in ATmega168A and ATmega168PA .........................................62
12.4Interrupt Vectors in ATmega328 and ATmega328P ..............................................65
12.5Register Description ..............................................................................................69

13 External Interrupts ................................................................................. 71

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13.1Pin Change Interrupt Timing ..................................................................................71
13.2Register Description ..............................................................................................72

14 I/O-Ports .................................................................................................. 76
14.1Overview ................................................................................................................76
14.2Ports as General Digital I/O ...................................................................................77
14.3Alternate Port Functions ........................................................................................81
14.4Register Description ..............................................................................................92

15 8-bit Timer/Counter0 with PWM ............................................................ 94
15.1Features ................................................................................................................94
15.2Overview ................................................................................................................94
15.3Timer/Counter Clock Sources ...............................................................................95
15.4Counter Unit ..........................................................................................................95
15.5Output Compare Unit .............................................................................................96
15.6Compare Match Output Unit ..................................................................................98
15.7Modes of Operation ...............................................................................................99
15.8Timer/Counter Timing Diagrams .........................................................................103
15.9Register Description ............................................................................................105

16 16-bit Timer/Counter1 with PWM ........................................................ 112
16.1Features ..............................................................................................................112
16.2Overview ..............................................................................................................112
16.3Accessing 16-bit Registers ..................................................................................114
16.4Timer/Counter Clock Sources .............................................................................117
16.5Counter Unit ........................................................................................................118
16.6Input Capture Unit ...............................................................................................118
16.7Output Compare Units .........................................................................................120
16.8Compare Match Output Unit ................................................................................122
16.9Modes of Operation .............................................................................................123
16.10Timer/Counter Timing Diagrams .......................................................................130
16.11Register Description ..........................................................................................132

17 Timer/Counter0 and Timer/Counter1 Prescalers ............................... 139
17.1Internal Clock Source ..........................................................................................139
17.2Prescaler Reset ...................................................................................................139
17.3External Clock Source .........................................................................................139
17.4Register Description ............................................................................................141

18 8-bit Timer/Counter2 with PWM and Asynchronous Operation ....... 142

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18.1Features ..............................................................................................................142
18.2Overview ..............................................................................................................142
18.3Timer/Counter Clock Sources .............................................................................143
18.4Counter Unit ........................................................................................................143
18.5Output Compare Unit ...........................................................................................144
18.6Compare Match Output Unit ................................................................................146
18.7Modes of Operation .............................................................................................147
18.8Timer/Counter Timing Diagrams .........................................................................151
18.9Asynchronous Operation of Timer/Counter2 .......................................................153
18.10Timer/Counter Prescaler ...................................................................................154
18.11Register Description ..........................................................................................155

19 SPI – Serial Peripheral Interface ......................................................... 162
19.1Features ..............................................................................................................162
19.2Overview ..............................................................................................................162
19.3SS Pin Functionality ............................................................................................167
19.4Data Modes .........................................................................................................167
19.5Register Description ............................................................................................169

20 USART0 ................................................................................................. 172
20.1Features ..............................................................................................................172
20.2Overview ..............................................................................................................172
20.3Clock Generation .................................................................................................173
20.4Frame Formats ....................................................................................................176
20.5USART Initialization .............................................................................................177
20.6Data Transmission – The USART Transmitter ....................................................179
20.7Data Reception – The USART Receiver .............................................................181
20.8Asynchronous Data Reception ............................................................................185
20.9Multi-processor Communication Mode ................................................................188
20.10Examples of Baud Rate Setting .........................................................................189
20.11Register Description ..........................................................................................194

21 USART in SPI Mode .............................................................................. 199
21.1Features ..............................................................................................................199
21.2Overview ..............................................................................................................199
21.3Clock Generation .................................................................................................199
21.4SPI Data Modes and Timing ................................................................................200
21.5Frame Formats ....................................................................................................200
21.6Data Transfer .......................................................................................................203

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21.7AVR USART MSPIM vs. AVR SPI ......................................................................205
21.8Register Description ............................................................................................206

22 2-wire Serial Interface .......................................................................... 209
22.1Features ..............................................................................................................209
22.22-wire Serial Interface Bus Definition ..................................................................209
22.3Data Transfer and Frame Format ........................................................................210
22.4Multi-master Bus Systems, Arbitration and Synchronization ...............................213
22.5Overview of the TWI Module ...............................................................................215
22.6Using the TWI ......................................................................................................217
22.7Transmission Modes ...........................................................................................220
22.8Multi-master Systems and Arbitration ..................................................................233
22.9Register Description ............................................................................................235

23 Analog Comparator .............................................................................. 239
23.1Overview ..............................................................................................................239
23.2Analog Comparator Multiplexed Input .................................................................239
23.3Register Description ............................................................................................240

24 Analog-to-Digital Converter ................................................................ 242
24.1Features ..............................................................................................................242
24.2Overview ..............................................................................................................242
24.3Starting a Conversion ..........................................................................................244
24.4Prescaling and Conversion Timing ......................................................................245
24.5Changing Channel or Reference Selection .........................................................247
24.6ADC Noise Canceler ...........................................................................................248
24.7ADC Conversion Result .......................................................................................252
24.8Temperature Measurement .................................................................................252
24.9Register Description ............................................................................................254

25 debugWIRE On-chip Debug System ................................................... 259
25.1Features ..............................................................................................................259
25.2Overview ..............................................................................................................259
25.3Physical Interface ................................................................................................259
25.4Software Break Points .........................................................................................260
25.5Limitations of debugWIRE ...................................................................................260
25.6Register Description ............................................................................................260

26 Self-Programming the Flash, ATmega 48A/48PA .............................. 261
26.1Overview ..............................................................................................................261

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26.2Addressing the Flash During Self-Programming .................................................262
26.3Register Description ............................................................................................267

27 Boot Loader Support – Read-While-Write Self-Programming ......... 269
27.1Features ..............................................................................................................269
27.2Overview ..............................................................................................................269
27.3Application and Boot Loader Flash Sections .......................................................269
27.4Read-While-Write and No Read-While-Write Flash Sections ..............................269
27.5Boot Loader Lock Bits .........................................................................................272
27.6Entering the Boot Loader Program ......................................................................273
27.7Addressing the Flash During Self-Programming .................................................274
27.8Self-Programming the Flash ................................................................................275
27.9Register Description ............................................................................................283

28 Memory Programming ......................................................................... 285
28.1Program And Data Memory Lock Bits .................................................................285
28.2Fuse Bits ..............................................................................................................286
28.3Signature Bytes ...................................................................................................289
28.4Calibration Byte ...................................................................................................289
28.5Page Size ............................................................................................................290
28.6Parallel Programming Parameters, Pin Mapping, and Commands .....................290
28.7Parallel Programming ..........................................................................................292
28.8Serial Downloading ..............................................................................................299

29 Electrical Characteristics .................................................................... 303
29.1Absolute Maximum Ratings* ...............................................................................303
29.2DC Characteristics ...............................................................................................303
29.3Speed Grades .....................................................................................................310
29.4Clock Characteristics ...........................................................................................311
29.5System and Reset Characteristics ......................................................................312
29.6SPI Timing Characteristics ..................................................................................313
29.7Two-wire Serial Interface Characteristics ............................................................315
29.8ADC Characteristics ............................................................................................317
29.9Parallel Programming Characteristics .................................................................318

30 Electrical Characteristics (TA = -40°C to 105°C) ............................... 320
30.1Absolute Maximum Ratings* ...............................................................................320
30.2DC Characteristics ...............................................................................................320

31 Typical Characteristics ........................................................................ 324

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31.1ATmega48A Typical Characteristics ...................................................................325
31.2ATmega48PA Typical Characteristics .................................................................350
31.3ATmega88A Typical Characteristics ...................................................................375
31.4ATmega88PA Typical Characteristics .................................................................399
31.5ATmega168A Typical Characteristics .................................................................425
31.6ATmega168PA Typical Characteristics ...............................................................450
31.7ATmega328 Typical Characteristics ....................................................................475
31.8ATmega328P Typical Characteristics .................................................................500

32 ATmega48PA Typical Characteristics – (TA = -40°C to 105°C) ........ 525
32.1Active Supply Current ..........................................................................................525
32.2Idle Supply Current ..............................................................................................528
32.3Power-down Supply Current ................................................................................530
32.4Power-save Supply Current .................................................................................531
32.5Standby Supply Current ......................................................................................532
32.6Pin Pull-Up ...........................................................................................................532
32.7Pin Driver Strength ..............................................................................................535
32.8Pin Threshold and Hysteresis ..............................................................................537
32.9BOD Threshold ....................................................................................................540
32.10Internal Oscilllator Speed ..................................................................................542
32.11Current Consumption of Peripheral Units ..........................................................544
32.12Current Consumption in Reset and Reset Pulsewidth ......................................547

33 ATmega88PA Typical Characteristics – (TA = -40°C to 105°C) ........ 549
33.1Active Supply Current ..........................................................................................549
33.2Idle Supply Current ..............................................................................................552
33.3Power-down Supply Current ................................................................................554
33.4Power-save Supply Current .................................................................................555
33.5Pin Pull-Up ...........................................................................................................556
33.6Pin Driver Strength ..............................................................................................559
33.7Pin Threshold and Hysteresis ..............................................................................561
33.8BOD Threshold ....................................................................................................564
33.9Internal Oscilllator Speed ....................................................................................565
33.10Current Consumption of Peripheral Units ..........................................................568
33.11Current Consumption in Reset and Reset Pulsewidth ......................................570

34 ATmega168PA Typical Characteristics – (TA = -40°C to 105°C) ...... 573
34.1Active Supply Current ..........................................................................................573
34.2Idle Supply Current ..............................................................................................576

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34.3Power-down Supply Current ................................................................................578
34.4Power-save Supply Current .................................................................................579
34.5Standby Supply Current ......................................................................................580
34.6Pin Pull-Up ...........................................................................................................580
34.7Pin Driver Strength ..............................................................................................583
34.8Pin Threshold and Hysteresis ..............................................................................585
34.9BOD Threshold ....................................................................................................588
34.10Internal Oscillator Speed ...................................................................................591
34.11Current Consumption of Peripheral Units ..........................................................593
34.12Current Consumption in Reset and Reset Pulsewidth ......................................596

35 ATmega328P Typical Characteristics – (TA = -40°C to 105°C) ........ 598
35.1ATmega328P Active Supply Current ...................................................................598
35.2Idle Supply Current ..............................................................................................601
35.3Power-down Supply Current ................................................................................603
35.4Power-save Supply Current .................................................................................604
35.5Standby Supply Current ......................................................................................605
35.6Pin Pull-Up ...........................................................................................................605
35.7Pin Driver Strength ..............................................................................................608
35.8Pin Threshold and Hysteresis ..............................................................................610
35.9BOD Threshold ....................................................................................................613
35.10Internal Oscillator Speed ...................................................................................615
35.11Current Consumption of Peripheral Units ..........................................................618
35.12Current Consumption in Reset and Reset Pulsewidth ......................................620

36 Register Summary ................................................................................ 622
37 Instruction Set Summary ..................................................................... 626
38 Ordering Information ........................................................................... 629
38.1ATmega48A ........................................................................................................629
38.2ATmega48PA ......................................................................................................630
38.3ATmega88A .........................................................................................................631
38.4ATmega88PA ......................................................................................................632
38.5ATmega168A .......................................................................................................633
38.6ATmega168PA ...................................................................................................634
38.7ATmega328 ........................................................................................................635
38.8ATmega328P ......................................................................................................636

39 Packaging Information ......................................................................... 637

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39.132A ......................................................................................................................637
39.232CC1 .................................................................................................................638
39.328M1 ....................................................................................................................639
39.432M1-A ................................................................................................................640
39.528P3 ....................................................................................................................641

40 Errata ..................................................................................................... 642
40.1Errata ATmega48A ..............................................................................................642
40.2Errata ATmega48PA ...........................................................................................642
40.3Errata ATmega88A ..............................................................................................643
40.4Errata ATmega88PA ...........................................................................................643
40.5Errata ATmega168A ............................................................................................644
40.6Errata ATmega168PA .........................................................................................644
40.7Errata ATmega328 ..............................................................................................645
40.8Errata ATmega328P ............................................................................................646

41 Datasheet Revision History ................................................................. 648
41.1Rev. 8271G – 02/2013 ........................................................................................648
41.2Rev. 8271F – 08/2012 .........................................................................................648
41.3Rev. 8271E – 07/2012 .........................................................................................648
41.4Rev. 8271D – 05/11 .............................................................................................649
41.5Rev. 8271C – 08/10 .............................................................................................649
41.6Rev. 8271B – 04/10 .............................................................................................649
41.7Rev. 8271A – 12/09 .............................................................................................650

Table of Contents ....................................................................................... i

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Atmel Corporation
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© 2012 Atmel Corporation. All rights reserved. / Rev.: 8271G–AVR–02/2013
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Title                           : ATmega48A, ATmega48PA, ATmega88A, ATmega88PA, ATmega168A, ATmega1688PA, ATmega328, ATmega328P datasheet
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Keywords                        : Atmel 8-bit Microcontroller, ATmega48A; ATmega48PA;  ATmega88A, ATmega88PA, ATmega168A, ATmega168PA, ATmega328, ATmega328P, High performance, low power, advanced RISC Architecture, high endurance, non-volatile memory segment, EEPROM, In-system self-programmable flash, Internal SRAM, Atmel QTouch library support, capacitive touch, 64 sense channels, 8-bit and 16-bit Timer/counter, PWM, 10-bit ADC, USART, SPI, I2C, WDT, AC, POR
Subject                         : Atmel 8-bit Microcontroller with 4/8/16/32Kbytes In-System Programmable Flash

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