Z8601_Z8603_Data_Sheet_Sep82 Z8601 Z8603 Data Sheet Sep82
User Manual: Z8601_Z8603_Data_Sheet_Sep82
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Z8® Family of
Microcomputers
Z8601 • Z8603
~
Zilog
Product
Specification
September 1982
Copyright, 1982 by 2110g, Inc, All rights reserved, No part of
this publication may be reproduced without the written
permission of Zilog Inc.
I
The information in this publication is subject to change
wi thou t notice.
Z8® Family of
Microcomputers
Z8601 • Z8603
Product
Specification
~
Zilog
September 1982
28601 Single-Chip Microcomputer with 2K ROM
28603 Prototyping Device with EPROM Interface
Features
General
Description
• Complete microcomputer, 2K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
62K bytes addressable external space each
for program and data memory.
• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit programmable prescaler.
• Register Pointer so that short, fast instructions can access any of nine working
register groups in I. 5 p.s.
• 144-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.
• On-chip oscillator which accepts crystal or
external clock drive.
• Average instruction execution time of
2.2 p.s, maximum of 4.25 p.s.
• Low-power standby option which retains
contents of general-purpose registers.
• Vectored, priority interrupts for I/O,
counter/timers, and UART.
• Single + 5 V power supply-all pins TTLcompatible.
The 28601 microcomputer introduces a new
level of sophistication to Single-chip architecture. Compared to earlier single-chip microcomputers, the Z8601 offers faster execution;
more efficient use of memory; more sophisticated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8601 can be
tailored to the needs of its user. It can be con-
figured as a stand-alone microcomputer with
2K bytes of internal ROM, a traditional microprocessor that manages up to 124K bytes of
external memory, or a parallel- processing element in a system with other processors and
peripheral controllers linked by the Z-BUS. In
all configurations, a large number of pins
remain available for I/O.
+5V
PORT 2
(BIT PRO·
GRAMMABLE)
110
PORT 0
(NIBBLE
PROGRAMMABLE)
110 OR As-A,.,
P3,
XTAL1
P2,
P3,
P2,
P3,
P2,
REID
P2,
R/Vi
P2,
os
P2,
AS
P2,
P3,
P2,
GND
P3,
P3,
PORT 3
(FOUR INPUT;
PORT 1
FOUR OUTPUT)
(BYTE
PROGRAMMABLE)
SERIAL AND
PARALLEL 110
AND CONTROL
110 OR ADC,-AD)
Figure I. Pin Functions
2037 -00 1, 002
P3,
XTAL2
po,
po,
po,
po,
po,
po,
po,
po,
P3,
PI,
PI,
PI,
PI,
PI,
PI,
PI,
PI,
Figure 2. Pin Assignments
Architecture
Z8601 architecture is charact.erized by a
flexible VO scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O capabilities. The Z8601 fulfills this with
32 pins dedicated to input and output. These
lines are grouped into four ports of eight lines
each and are configurable under software control to provide timing, status signals, serial or
parallel I/O with or without handshake, and an
address/data bus for interfacing external
memory.
Because the multiplexed address/data bus is
merged with the I/O-oriented ports, the Z8601
can assume many different memory and I/O
configurations. These configurations range
from a self-colJ.tained microcomputer to a
Vee
OUTPUT
microprocessor that can address 124K bytes of
external memory.
Three basic address spaces are available to
support this wide range of configurations: program memory (internal and external), data
memory (external) and the register file (Internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
four I/O port registers, and 16 control and
status registers.
To unburden the program from coping with
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware support for the UART is minimized
because one of the on-chip timers supplies the
bit rate.
XTAL
GND
As
!!
uo
(BIT PROGRAMMABLE)
ADDRESS OR I/O
(NIBBLE PROGRAMMABLE)
ADDRESS/DATA OR 110
(BYTE PROGRAMMABLE)
Figure 3. Functional Block Diagram
Pin
Description
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory, transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along with
Ports 0 and 1, Data Strobe and Reacl/Write.
DS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.
PDO.. PO~.Plo-P171 P2o-P~. P30-P37. I/O Port
Lines (inpuVoutputs, TTL-compatible). These
32 lin~s are divided into four 8-bit I/O ports
2
that can be configured under program control
for I/O or external memory interface.
RESET. Reset (input, active Low). RESET initializes the Z8601. When RESET is deactivated,
prograin execution begins from internal program location OOOCH.
R/W. Read/Write (output). R/W is Low when
the Z8601 is writing to external program or
data memory.
XTALI. XTAL2. Crystal], Crystal 2 (time-base
input and output). These pins connect a seriesresonant crystal (8 MHz maximum) or an external single-phase clock (8 MHz maximum) to
the on-chip clock oscillator and buffer.
2037,003
Address
Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 2048 bytes
consist of on-chip mask-programmed ROM. At
addresses 2048 and greater, the Z8601
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond
to the six available interrupts.
Data Memory. The Z8601 can address 62K
bytes of external data memory beginning at
5535
locations 2048 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-RI27) and 16
control and status registers (R240-R255). These
registers are assigned the address locations
shown in Figure 6.
Z8601 instructions can access registers
65535
r----------,
EXTERNAL
ROM OR RAM
2048
2047
,,
ON·CHIP
ROM
Locotlona
Ilrst byte 0
Instruction
I~ ::-------------
executed
allerres8
11
10
IRQS
9
IRQ4
,
Interrup
Veclo
(Lower ByteI
Inl&rrupt
Vector
(Upper ByteI
EXTERNAL
DATA
MEMORY
IRQS
8
IRQ4
7
IRQ3
6
5 ,,_
IRC3
4
lRQ2
IRQ2
3
IRQ1
2
IRQ1
1
IROO
0
IROO
~~:; \ - - - - - - - - - - - 1
NOT ADDRESSABLE
Figure 4. Program Memory Map
LOCATION
IDENTIFIERS
255
STACK POINTER (BITS 7-0)
254
STACK POINTER (BITS 15-8)
253
REGISTER POINTER
.PL
,PH
RP
2S2
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT REQUEST REGISTER
IRQ
249
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
247
PORT 3 MODe
246
PORT 2 MODE
245
244
TIMER/COUNTER
Figure 5. Data Memory Map
___ I
l-f~=:3==::;:=====125S
L "'. '. '. I 0 0 0 0 '253
240
The upper nibble 01 the regislerlile address
;>--- proVided by the register pointer spBcllles
the acllve worklng·rBglster group.
.---------_..,127
P01M
P3M
P2M
TO PRESCALER
PREO
a
TO
243
T1 PRESCALER
242
TIMER/COUNTER 1
T1
241
TIMER MODE
TMR
240
SERIAL 110
SIO
PRE1
NOT
IMPLEMENTED
ThBlower
nibble 01
SPECIFIED WORKING·
REGISTER GROUP
127
--
thBregllter
III. address
proYidedby
Ihelnstructlon
points to IhB
specified
regllter.
GENERAL·PURPOSE
REGISTERS
PORT 3
P3
PORT 2
P2
PORT 1
P1
PORT 0
PO
Figure 6. The Register File
2037 -004, 005, 006, 007
1-----------115
----"OPORTS----- 3
Figure 7. The Register Pointer
3
Address
Spaces
(Continued)
Serial
Input/
Output
Stacks. Either the internal register file or the
directly or indirectly with an 8-bit address
field. The Z8601 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
2048 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within
the 124 general-purpose registers (R4-RI27).
Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second.
The Z8601 automatically adds a start bit and
two stop bits to transmitted data (Figure 8).
Odd parity is also available as an option. Eight
data bits are always transmitted, regardless of
parity selection. If parity is enabled, the eighth
bit is the odd parity bit. An interrupt request
(IRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.
Transmitted Data
Received Data
(No Parity)
(No Parity)
1~1~1~1~1~1~1~1~1~lul
T
I
LSTART BIT
' - - - - - - E I G H T DATA BITS
LSTART BIT
' - - - - - - E I G H T DATA BITS
L.- - - - - - - - O N E STOP BIT
TWO STOP alTS
Transmitted Data
Received Data
(With Parity)
(With Parity)
T' ---
000 PARITY
II
TWO STOP BITS
L.- - - - - - - - - D N E STOP BIT
_LSTARTBIT
' - - - - - - S E V E N DATA 81TS
LSTAAT BIT
' - - - - - S E V E N DATA BITS
L - - - - -_ _ _ PARITy ERROR FLAG
Figure 8. Serial Data Formats
Counter/
Timers
4
The Z8601 contains two 8-bit programmable
counter/timers (To and TIl, each driven by its
own 6-bit programmable prescaler. The TI
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from I to 64. Each prescaler drives its counter,
which decrements the value (I to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQs (TI)-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmedto stop upon reaching zero (single-
pass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for T I is user-definable and
can be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (l MHz maximum),
a trigger input that can be retriggerable or
non-retriggerable, or as a gate input for the
internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of T I. Port 3 line P36 also
serves as a timer output (Tour) through which
To, TI or the internal clock can be output.
2037-009
110 Ports
The 28601 has 32 lines dedicated to input
and output. These lines are grouped into four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to
provide address outputs, timing, status signals,
serial I/O, and parallel I/O with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 1 can be programmed as a byte I/O
port or as an address/data port for interfacing
external memory. When used as an I/O port,
Port I may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls ROY 1
and DAVl (Ready and Data Available).
Memory locations greater than 2048 are
referenced through Port 1. To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If
more than 256 external locations are required,
Port 0 must output the additional lines.
Port I can be placed in the high-impedance
state along with Port 0, AS, DS and RIW, allow-
ing the 2860 I to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33
as a Bus Acknowledge input and P34 as a Bus
Request output.
Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port 0 may be placed under handshake control. In this configuration, Port 3 lines P32 and
P35 are used as the handshake controls DA Vo
and ROYo. Handshake signal assignment is
dictated by the I/O direction of the upper
nibble P04-P07.
For external memory references, Port 0 can
provide address bits As-All (lower nibble) or
As-Al5 (lower and upper nibble) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as
I/O while the lower nibble is used for addressing. When Port 0 nibbles are defined as
address bits, they can be set to the highimpedance state along with Port I and the control signals AS, DS and R/W.
Port 2 bits can be programmed independently as input or output. The port is
always available for I/O operations. In addition, Port 2 can be configured to provide
open-drain outputs.
Like Ports and 1, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P3l and P36 are used as
the handshake controls lines DAV2 and ROY2.
The handshake signal assignment for Port 3
lines P3l and P36 is dictated by the direction
(input or output) assigned to bit 7 of Port 2.
°
Port 3 lines can be configured as I/O or control lines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37). For serial I/O, lines P30
and P37 are programmed as serial in and serial
au t respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, I and 2
(DAVand RDY); four external interrupt
request signals (IRQo-IRQ3); timer input and
output signals (TIN and TOUT) and Data
Memory Select (DM).
PORT 1
(If0 OR ADo-AD1)
HANDSHA~~ CONTROLS
} DAV1 AND RDY1
(P33 AND P3,.)
Figure 9a. Pori 1
I
PORT 0
(1/0 OR Aa-Als)
Figure 9b. Pori 0
PORT 2(110)
!1MiPSHAKE CONTROLS
} DAV2 AND RDY2
(P3, AND P36)
Figure 9c. Pori 2
PORT 3
(110 OR CONTROl)
Figure 9d. Pori 3
5
Interrupts
Clock
Power Down
Standby
Option
6
The Z8601 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter/
timers. These interrupts are both maskable and
:, prior4~zed. The Interrupt Mask register globally or 'individually enables or disables the six
interrupt requests_When more than one interrupt is ~nding, pri-;rffies-are resolved by a
programmable priority encoder that is controlled by the Interrupt Priority register.
All Z8601 interrupts are vectored. When an
interrupt request is granted, an interrupt
machine cycle is entered. This disables all
subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
Polled interrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
The on-chip oscillator has a high-gain,
series-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capaCitors (Cj = 15 pF) from each pin to
ground. The speCifications for the crystal are
as follows:
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input. This
necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended or
due to power failure, must be preceded by a
software routine that stores the appropriate
status into the register file. Figure 10 shows
the recommended circuit for a battery back-up
supply system.
• AT cut, series resonant
• Fundamental type, 8 MHz maximum
• Series resistance, Rs :s 1000
+5V
0----__.---1 VDD
zae01
J
Figure 10. RacommeDCled Driver Circuit
for Power Down Operation
2037-010
Z8603
Protopack
Emulator
The Z8603 MPE (Protopack) is used for
prototype development and preproduction of
mask-programmed applications. The Protopack
is a ROMless version of the standard Z8601,
housed in a pin-compatible 40-pin package
(Figure 11).
To provide pin compatibility and interchangeability with the standard maskprogrammed device, the Protopack carries
(piggy-backs) a 24-pin socket for a direct
interface to program memory (Figure 1). The
24-pin socket is equipped with 11 ROM
address lines, 8 ROM data lines and necessary
control lines for interface to 2716 EPROM for
the first 2K bytes of program memory.
Pin compatibility allows the user to design
the pc board for a final 40-pin maskprogrammed Z8601, and, at the same time,
allows the use of the Protopack to build the
prototype and pilot production units. When the
final program is established, the user can then
switch over to the 40-pin mask-programmed
Z8601 for large volume production. The Protopack is also useful in small volume applications where masked ROM setup time, mask
charges, etc., are prohibitive and program
flexibility is desired.
Compared to the conventional EPROM
versions of the single-chip microcomputers,
the Protopack approach offers two main
advantages:
• Ease of developing various programs during
the prototyping stage. For instance, in
applications where the same hardware
configuration is used with more than one
program, the Z8603 Protopack allows
economical program storage in separate
EPROMs (or PROMs), whereas the use of
separate EPROM-based single-chip
microcomputers is more costly .
Figure 11. The Z8603 Microcomputer Protopack Emulator
Instruction
Set
Notation
Addressing Modes. The folloWing notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
IR
Ir
RR
Indirect register pair or indired working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Flags. Control Register R252 contains the follOWing
six flags:
Indirect-register or indired working-register
c
Z
Indirect working-register address only
S
V
D
H
Register pair or working register pair address
describing the instruction set.
dst
src
Destination location or contents
Source location or contents
cc
SP
Condition code (see list)
Indirect address prefix
Stack pOinter (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)
Interrupt mask register (control register 251)
IMR
2037·012
Assignment of a value is indicated by the symbol
"_". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
address
Symbols. The follOWing symbols are used in
@
• Elimination of long lead time in procuring
EPROM-based microcomputers.
Carry flag
Zero flag
Sign flag
Overflow flag
DeCimal-adjust flag
Half-carry flag
Affected flags are indicated by:
o
Cleared to zero
Set to one
11
Set or cleared according to operation
X
Unaffected
Undefined
7
Condition
Codes
Value
Flags Set
Meaning
Mnemonic
1000
0111
1111
0110
1110
1101
0101
DIDO
1100
0110
1110
IDOl
0001
1010
0010
IIII
0111
lOll
00 II
0000
Always true
C
NC
C
I
C = 0
Carry
No carry
Z
Z
Z
S
S
V
V
Z
Z
(S
(S
Zero
Not zero
Plus
NZ
PL
MI
OV
NOV
EQ
NE
GE
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
LT
GT
LE
UGE
ULT
UGT
ULE
= I
= 0
0
= I
I
0
I
0
XOR V) = 0
XOR V) = I
[Z OR (S XOR V)] = 0
[Z OR (S XOR V)] = I
C=O
C = I
(C = 0 AND Z = 0)
(C OR Z) = I
Never true
Instruction
Formats
ope
CCF, 01, EI, IRET, NOP,
ReF, RET, SCF
."
ope
INCr
One-Byte Instructions
ope
MODE
dst/src
ope
."
I
OR
h 1 1 01 dst/src I
OR
11
1 1
01
eLR, CPL, CA, DEC,
DECW, INC, INeW, POP,
PUSH, RL, Rle, RR,
RRC, SRA, SWAP
ope
MODE
OR
OR
.ot
til 0
1 1 1 0
Ace, ADD, AND, CP,
lO, OR, SSC, SUB,
'"
.ot
TeM, TM, XOR
.ot
Ace, ADD, AND, CP,
LO, OR, sec, sus,
TeM, TM, XOR
JP, CALL (Indirect)
.ot
ope
ope
.ot
MODE
OR
11
1 1
01
VALUE
SRP
VALUE
MODE
ope
.ot
MODe
MODE
ope
dsUsrc
srcldst
dst/src
ope
ope
LD
OR
OR
.ot
1 1 1 0
1 1 1 0
.ot
reM, TM, XOR
srcldst
dst
Ace, ADD, AND,
CP, OR, sec, SUB,
lope
lO, LOE, lOEI,
lDC, lOCI
ope
LD
ADDRESS
OR
l'
LD
1 1
01
,ro
I
ope
JP
DA,
DA,
LD
VALUE
IdstlCCR~ ope
MODE
dstlsrc
ope
DJNZ, JR
CALL
DA,
DA,
Two-Byte Instructions
Three-Byte Instructions
Figure 12. Instruction. Formats
8
2037-013
Instruction
Summary
Opcode Flags Affected
laalruction
and Operation
Addr Mode
ADC dBt,Bre
dBt-dBt+Bre+C
(Note 1)
ADD dBt,Bre
dBt - dBt + Bre
(Note 1)
00
AND dBt,Bre
dBt - dBt AND Bre
(Note 1)
50
- * * 0
D6
------
dBt
arc
Byi.
(Hex)
10
CALL dBt
DA
SP-SP-2
IRR
@SP - PC; PC - dBt
D4
CCF
C - NOTC
EF
·0·
·0·
.- -
- - -
CLR dst
dBt - 0
R
IR
BO
Bl
------
COM dBt
dBt - NOT dBt
R
IR
60
0--
61
CP dst,Bre
dBt - Bre
(Note 1)
DA dBt
dst - DA dBt
R
IR
40
41
DEC dBt
dBt - dBt-l
R
IR
DECW dBt
dBt-dst-l
RR
IR
CZSVDH
r
Irr
Irr
82
------
LDEI dBt,Bre
Ir
Irr
dBt - Bre
r-r+ 1; rr-rr+ 1
Irr
Ir
LDE dBt,Bre
dBt - Bre
FF
------
OR dBt,Bre
dBt - dBt OR Bre
(Note 1)
40
- * * 0
POP dst
dBt - @SP
SP - SP + 1
R
IR
50
------
NOP
PUSH Bre
SP-SP-l; @SP-Bre
00
01
-***--
RLC dBt
80
-***--
RR dst
AO
Al
-----------
R
IR
L:{ri:OOciJ
'
, •
R
IR
11
1E14!::::::::!J.J I~
EO
El
LEHi::3J
R
.' , • IR
CO
Cl
sac
dBt,Brc
dBt - dBt-Bre-C
91
10
(Note 1)
SCF
C-l
• 1
3D
.
1 - - - - -
DO
Dl
* * *0
31
------
20
* * * * 1
SWAPds! ~ R
IR
FO
Fl
X
• *
TeM dst,Bre
(NOT dBt) AND Bre
(Note 1)
60
-
• ·0 - -
TM dBt, Bre
dBt AND Brc
(Note I)
7D
- *
------
XOR dst,Bre
dBt - dBt XOR arc
(Note 1)
BO
Note I
------ * * *- -
-
* * *- -
* * * * * *
cD
e=O-F
30
RA
eB
e=O-F
------
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
------
r
X
r
Ir
R
R
R
IR
IR
X
r
Ir
r
R
IR
1m
1m
R
LDC dBt,Bre
dBt - Bre
r
Irr
Irr
C2
D2
------
LDCI dst,Bre
dBt - Bre
Ir
Irr
Irr
Ir
C3
D3
------
r-r+ 1; rr-rr+ 1
~
DF
DA
1m
R
------
90
RR
IR
r
R
70
71
RL dBt
IRR
LD dst,Bre
dBt - Bre
R
IR
* • * X- -
R
IR
if cc is true,
PC-PC+dBt
Range: + 127, -128
51
------
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR(7) -1
if co is true
------
AF
BF
JP ee,dBt
83
93
RET
PC - @SP; SP - SP + 2
AD
rE
r=O-F
20
21
!RET
92
0-- - - -
9F
INCW dBt
dBt - dBt +
JR ee,dBt
(Hex)
SRA dBt
INC dBt
dBt-dBt+l
Byte
arc
CF
rA
r=O-F
EI
IMR(7) - 1
Opcode Flags Affected
dBt
RRC dBt
*
AddrMode
RCF
C - 0
8F
DJNZ r,dBt
RA
r - r - 1
ifr
0
PC-PC + dBt
Range: + 127, -128
PC - dBt
laalructlon
and Operation
81
DI
IMR (7) - 0
1085-003
CZSVDH
lEl~I~
SRP sre
RP - Brc
1m
SUB dBt,Brc
dBt - dBt - Bre
(Note 1)
.
X - -
* 0 - ·0 - -
These instructions have an identical set of addressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a D in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, to determine the opcode of an ADC
instruction use the addressing modes r (destination) and
Ir (source). The result is 13.
AddrMode
dBt
arc
Lower
Opcode Nibble
~
Ir
lID
ffi
lID
R
R
R
IR
R
1M
[!]
IR
1M
121
9
Registers
R244TO
Counter/Timer 0 Register
(F4H ; Reacl/Write)
R240 810
8erlall/0 Regilter
(F~; Reacl/Write)
L-_ _ _ _
=
INTERNAL CLOCK OUY OIl 11
T MODES
EXTERNAL CLOCK IN~aT = 00
GATE INPUT = 01
(NON.Rg~1:::~::~~) 10
=
LSB)
R241 TMR
Timer Mode Register
(FlH; Reacl/Write)
R245 PREO
Preac:aler 0 Regllter
(F5H; Write Only)
~~O
~L
J
NOT Tour
USEDMODES
_ 00 ~
foOUT
01
T, OUT _ 10
SERIAL DATA (Do
1 =
LOAD
To
- NO
FUNCTION
0 = DISABLE To COUNT
1 ... ENABLE To COUNT
1
=
1 ",,·f0 MODULO·N
RESERVED
0 .. NO FUNCTION
1 = LOAD T1
0 "" DISABLE T, COUNT
•
COUNTMODE
o = To SINGlE·PASS
PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
ENABLE T1 COUNT
01-00 HEX)
TRIGGER INPUT = 11
(RETRIGGERABLE)
R242 TI
Counter Timer 1 Regilter
(F2H; Reacl/Write)
R246 P2M
Port 2 Mode Register
(FElH; Write Only)
R243 PREI
Preac:aler 1 Register
(F~; Write Only)
R247 P3M
Port 3 Mode Register
(F7H; Write Only)
~L
COUNTMODE
o = T1 SINGLE·PASS
1 = T1 MODULO·N
CLOCK SOURCE
1 = T 1 INTERNAL
o=
T1 EXTERNAL TIMING INPUT
[gE
LO
PORT 2 PULLoUPS OPEN DRAIN
1 PORT 2 PULl·UPS ACTIVE
RESERVED
o P32 = INPUT
P35
1 P32 = DAYOIRDYO P35
00 P33
(TIN) MODE
~~} P33
PRESCALER MODULO
(RANGE: 1~64 DECIMAL
01~OO HEX)
1 1 P33
= INPUT
= INPUT
= DAY11RDY1
P34
P34
P34
= OUTPUT
= RDVOIIJAVii
= OUTPUT
= OM
:
= RDY111lm
~ =:~ ~ ~N:yUJ.g~~ ~= ~~~~~)
L-_ _ _ _ _ _ _ ~=: ~ ~N:R~lLIN
=:~ ~ ~~~~~TOUT
L-_ _ _ _ _ _ _ _ ~ ~:=:~ g~F
Figure 13. Control Registers
10
2037-014
Registers
R252 FLAGS
R248 POIM
Port 0 and 1 Mode Register
(F~; Write Only)
(Continued)
~
PO•• PO,MODE:]
OUTPUT
= 00
INPUT - 01
= 1X
~~
L
A12~A1'
Flag Register
(FCH ; Read/Write)
'
1X - A.~A11
STACK SELECTION
0 = EXTERNAL
EXTERNAL MEMORY TIMING
NORMAL - 0
EXTENDED = 1
llI~~
LUSER FLAG Ft
LUSER FLAG F2
Pa.·PO,MODE
00 = OUTPUT
01 "" INPUT
1 ... INTERNAL
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
P10·P17 MODE
00 ... BYTE OUTPUT
01 "" BYTE INPUT
to -
HALF CARRY FLAG
ZERO FLAG
A".AI>,
CARRY FLAG
11 - HIGH·IMPEDANCE ADo-ADJ.
AS, DB, RIW, At-Au. A12-A1&
IF SELECTED
R253 RP
ReglBter Pointer
(F~; Read/Write)
R2491PR
Interrupt Priority Register
(F9H; Write Only)
III ~. ""-~
II>,I~I~I~I~ID,I~I .. I
~:J i [
IRQ3, IRQ5 PRIORITY (GROUP A)
0=IRQ5>IRQ3
1 = IRQ3 > IRQ5
RESERVED = ODD
C > A :> B = 001
A>8>C=010
A > C :> 8 = 011
8>C>A=1oo
C :> B > A = 101
B :> A :> C = 110
RESERVED = 111
IROO, IRQ2 PRIORITY (GROUP 8)
o = IRQ2 > IROO
1 = IROO :> IRQ2
LDON'TCARE
IR01, IRQ4 PRIORITY (GROUP C)
o=
IR01 > IR04
1 "" IRQ4 :> IR01
8254 SPH
Stack Pointer
(FEH ; Read/Write)
R250IRQ
Interrupt Request Register
(FAH ; Read/Write)
RESERVED
II>,I .. I.. I~ID,ID,I~I .. I
~ IRQO -
T
IR01
IRQ2
IRQ3
IRQ4
IRQ5
Po, INPUT (Do _ IRQO)
- P3, INPUT
,.. Pa, INPUT
= P30 INPUT, SERIAL INPUT
• To. SERIAL OUTPUT
- T,
R2511MR
Interrupt Mask Register
(F~; Read/Write)
Il______
8255 SPL
Stack Pointer
(FFH; Read/Write)
II>,I .. I.. I~I~!~I~I .. I
~ CDo
1 ENABLES IRoo-IR05
- IROO)
1
..____
:~~~S~~=~~R LOWER
RESERVED
' - - - - - - - - 1 ENABLES INTERRUPTS
Figure 13. Control aegisters
11
Z8601
Opcode
Map
Lower Nibble (Hex)
o
6,5
o
2
3
•
5
..e..
.!
..Q
:9
6
~
3
4
5
6
7
8
9
A
B
6,5
6,5
10,5
10,5
10,5
10,5
6,5
6,5
LD
12/10,5
12/10,0
DJNZ
12, HI
Il,RA
JR
cc,RA
DEC ADD ADD ADD ADD ADD ADD
Rl
IRl
Il, f2
6,5
6,5
6,5
RLC
RLC
n,lra
6,5
R2,Rl
10,5
7
8
::>
9
A
B
C
D
E
F
Bytes per
Instruction
JR2,Rl
Rl,IM
IRl,iM
10,5
10,5
10,5
R2,Rl
10,5
JR2,Rl
10,5
Rl,IM
Rl
JRl
II, f2
II, 1r2
6,5
6,5
6,5
6,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
Rl
8,0
JRl
6,1
II, f2
Il,Il2
6,5
IR2,Rl
10,5
Rl,IM
10,5
IRl,IM
6,5
R2,Rl
10,5
IP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
1M
II, [2
II1Ir2
6,5
OR
R2,Rl
10,5
OR
R2,Rl
10,5
AND
R2,Rl
10,5
TCM
R2,Rl
IR2,Rl
8,5
DA
JRl
Rl.IM
10,5
OR
Rl,IM
10,5
AND
Rl,iM
10,5
TCM
Rl,iM
IRl,IM
10,5
OR
JRl,IM
10,5
AND
IRl,IM
10,5
TCM
IRl,IM
10,5
TM
Rl,IM
10,5
TM
IRl,iM
JRRl
8,5
DA
Rl
10,5
POP
Rl
6,5
COM
Rl
PUSH
R2
10,5
DECW
RRl
6,5
RL
Rl
10,5
INCW
RRl
6,5
CLR
Rl
6,5
RRC
Rl
6,5
SM
Rl
6,5
RR
Rl
8,5
SWAP
Rl
LD
II,
Hz
C
6,5
LD
rl,iM
D
12/10,0
JP
6,5
INC
cc,DA
fl
Il, [2
6,5
OR
r 1, Ira
10,5
POP
IRl
6,5
AND
6,5
AND
II, [2
Il,IrZ
6,5
COM
IRl
6,5
TCM
6,5
TCM
Il,Irz
II, fa
6,5
6,5
10,5
TM
PUSH
TM
TM
II, fZ
Il,lrz
R2,Rl
JR2
12,0
18,0
10,5
DECW LDE
LOEI
IRl
II, IrI2 Ir 1, !rIa
12,0
18,0
6,5
RL
LDE
LOE!
12, lIn Lu,IrIl
JRl
10,5
6,5
6,5
10,5
INCW
CP
CP
CP
IRl
II, fZ
r 1, Ira
R2,Rl
6,5
6,5
6,5
10,5
CLR
XOR
XOR
XOR
II, f2
II, Ira
R2,Rl
JRl
6,5
12,0
18,0
RRC
LDC
LDCI
(1, !rI2
IrI,IIll
IRl
6,5
SRA
JRl
12,0
LDC
lZ,IrI}
10,5
OR
IR2,Rl
10,5
AND
IR2,Rl
10,5
TCM
IR2,Rl
10,5
TM
IR2,Rl
-
6,5
LD
Il,Irz
8,5
SWAP
IRl
6,5
LD
In,I2
10,5
LD
R2,Rl
JR"IM
10,5
-
-
10,5
-
-
-
-
6,1
DI
6,1
EI
------'--
10,5
CP
JR2,Rl
10,5
CP
Rl,iM
10,5
CP
IRl,IM
10,5
XOR
IR2,Rl
10,5
XOR
Rl,IM
10,5
XOR
JRl,iM
14,0
RET
-
10,5
LD
IR2,Rl
20,0
CALL
DA
10,5
LD
Rl,IM
6,5
RCF
-
10,5
LD
12,
x,
°
16,
IRET
10,5
LO
II, X, Hz
18,0
20,0
LDCI CALL*
Irz, Irn IRRl
6,5
RR
JRl
10,5
-
HI
10,5
LD
IRl,iM
6,5
SCF
6,5
CCF
-
10,5
LD
R2,IRl
6,0
NOP
~~------~~~~-----'~ ~,------~~~------~~ ~'----------~~~---------'~ ~ ~
2
2
3
Lower
Opcode
Nibble
Execution
Cycles
Upper _
Opcode
Nibble
•
•
Pipeline
Cycles
~0'5
A
CP
Mnemonic
Legend:
R = 8~ Bit Address
r = 4· Bit Address
Rl or rt = Dst Address
Hz or [2 = Src Address
R2, R1
Ftr~
Operand
Second
Operand
*2-byte- instruction; fetch cycle appears as a 3-byte instruction
12
F
E
ADC ADC ADC ADC ADC ADC
10/12,1 12/14,1
z;
Ilo
Ilo
6,5
DEC
2
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.
Absolute
Maximum
Ratings
Standard
Test
Conditions
Voltages on all pins
withrespecttoGND .......... -O.3Vto +7.0V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to +150°C
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
+5V
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
D
D
D
+4.75 V S Vee S +5.25 V
GND = 0 V
O°C S TA S +70°C*
.. See Ordering Information section for package
temperature range and product number.
+5V
+5V
+'V
,.,
2.1K
Uk
74LS04
Uk
74LS04
XTAL1
I
Figure 14. Tast Load 1
DC
Character-
istics
8085-0313, 0312
Symbol
Figure 15. Test Load 2
Min
Max
Unit
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock. Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Vee
V
V1L
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
-10
10L
Output Leakage
-10
IJR
Reset Input Current
lee
Vee Supply Current
180
rnA
IMM
VMM Supply Current
10
rnA
VMM
Backup Supply Voltage
3
Condition
V
IoH
= -250 p,A
0.4
V
IoL
=
10
p.A
10
p,A
o Vs
o Vs
-50
p.A
Vee
Vee
V
= 15pF MAX
Figure 16. External Clock Interface Circuit
Parameter
2.4
CL
+2.0 rnA
VIN s
+5.25 V
VIN s +5.25 V
=
+5.25 V, VRL
=0V
Power Down Mode
Power Down
13
External 110
or Memory
Read and
Write Timing
!la-Dr OUT
PORT 1
M
Di
(WRITE)
Figure 17. External I/O or Memory Read/Write
ZB60113
No.
1
2
3
4
Symbol
Parameter
TdA(AS)
TdAS(A)
TdAS(DR)
Address Valid to AS f Delay
AS f to Address Floal Delay
AS f to Read Data Required Valid
TwAS
AS Low Width
TdAz(DS)
Address Float to DS I
5
6-TwDSR
DS (Read) Low Width
7
TwDSW
DS (Write) Low Width
TdDSR(DR)
8
DS I to Read Data Required Valid
ThDR(DS)
9
Read Data to DS f Hold Time
TdDS(A)
10
DS f to Address Active Delay
11
TdDS(AS)
DS f to AS I Delay
12 - TdRlW(AS) - - RIW Valid to AS f Delay
13
TdDS(RIW)
DS f to RlW Not Valid
14
TdDW(DSW)
Write Data Valid to DS (Write) I Delay
TdDS(DW)
15
DS f to Write Data Not Valid Delay
TdA(DR)
Address Valid to Read Data Required Valid
16
17
TdAS(DS)
AS f to DS I Delay
Min
Max
50
70
ZB60113-12
Min
Notes*t
220
1,2,3
1,2,3
1,2,3,4
35
45
360
80
55
0
250
160
0
185
110
1,2,3
200
0
70
70
50
60
50
70
130
0
45
55
30
35
35
45
1,2,3,4
1,2,3,4
1,2,3,4
I
410
80
Max
255
55
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3
NOTES:
I. Test Load I
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.
4. When using extended memory t.irning add 2 TpC.
14
5. All timing references use 2.0 V for a logic 1" and 0.8 V for a logic "0".
* All units in nanoseconds (ns),
t Timings are preliminary and subject to change.
\I
2194-011
Additional
Timing
Table
Figure 18. Additional Timing
ZB601I3
No.
2
3
4
56
Symbol
Parameter
TpC
TrC,TlC
Period
125
Rise And Fall Times
37
Width
Low Width
100
High Width - - - - - - - - - - 3TpC
TpC
Period
8
Timer Input Rise And Fall Times
Interrupt Request Input Low Time
100
Interrupt Request Input High Time
3TpC
Min
Min
Max
1000
25
83
1000
15
Input Clock
Clock Input
Input Clock
TwC
TwTinL
Timer Input
TwTinH - - - Timer Input
TpTin
Timer Input
7
TrTin,TlTin
8
9
TwIL
TwIH
NOTES:
1. Clock timing references uses 3.B V for a logic "1" and 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "1" and O.S V for
a logic "0",
Z8603
Memory Port
Ao-A.O
Timing
Z8601l3-12
Max
100
Notes*t
1
26
70
2
3TpC - - - - - - 2
TpC
2
8
2
100
2,3
70
2,3
3TpC
3. Interrupt request via Port 3.
.. Units in nanoseconds (ns).
t Timings are preliminary and subj ect to change.
~~________________~_A_D_D_RE_~__VA_L_'D__________________~b(
T-~.• ______0___~.1
T~lr_
__
- -_
-_
-J
_
Do-D7
~
DON'T CARE
~
DATA IN VALID
Figure 19. Memory Port Timing
Z8601I3
No.
Symbol
Parameter
2
TdA(DI)
ThDI(A)
Address Valid to Data Input Delay
Data In Hold Time
NOTES:
I. Test Load 2
2. This is a Clock-eyde-Dependent parameter. For clock frequencies other than the maximum, use the following formula:
2860113 = 5 TpC - 165
28601/3·12 = 5 TpC - 95
2194·012 2037·019
Min
Max
Z8601l3
Min
460
o
Max
Notes*
320
1,2
o
.. Units are nanoseconds unless otherwise specified; timings are
preliminary and subject to change.
15
Han4shake
Timing
DA~:~; ____________~
_____~.:::;:~.:
~ ___________
IIDY
(OUTPUT)
Fig\1re 20a. Inp\1t Hgncishake
-:::~ ~~~~~_1=E
___,·__1~~~~~~~;2D_"=T_A~OU~TV~AL;,"~~~.~~-~
1>:-,---,- - - ~
(INPUT)
Fi9l1re 20b. O\1tp\1t Handshake
Z8601l3
No.
Symbol
Parameter
Min
TsDI(DAV)
Data In Setup Time
0
2
ThDI(DAV)
Data In Hold Time
230
3
TwDAV
Data Available Width
175
4
TdDAVIf(RDY) DAV I Input to RDY I Delay
5-TdDAVOf(RDY)-DAV I OutputtoRDY I D e l a y - - - - - - - - 0
6
7
8
9
DAV I Input to RDY I Delay
DAV I Output to RDY I Delay
Data Out to DAV I Delay
Rdy I Input to DAV I Delay
TdDAVIr(RDY)
TdDAVOrRDY)
TdDO(DAV)
TdRDY(DAV)
NOTES:
I. Test load I
2. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "1" and 0.8 V for
a logic "0",
ClockNumber
Cycle-TimeDependent
1
Characterbtics
2
3
4
6
7
8
10
11
12
13
14
15
16
17
Symbol
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdRlW(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DRl
TdAS(l)S)
Max
Max
0
160
120
175
175
0
50
0
Z8601/3-12
Min
200
120
1.2
0 ------1,3
120
1,2
0
1,3
30
1
140
0
1
* Urtits in nanoseconds (ns).
t Timings are preliminary and subject to change.
Z8601l3
Z8601I3-l2
Equation
Equation
TpC-75
TpC-55
4TpC-140*
TpC-45
3TpC-125*
2TpC-90*
3TpC-175*
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215*
TpC-45
TpC-50
TpC-40
4TpC-llO*
TpC-30
3TpC-65*
2TpC-55*
3TpC-120*
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160*
TpC-30
* Add 2l'pC when using extended memory timing
16
2194-0i:
Ordering
Information
Product
Number
Package/
Temp
Speed
Product
Number
Description
Package/
Temp
Speed
Z8601
CE
8.0 MHz
Z8MCU
(2K ROM, 40-pin)
Z8601-12
DS
Z8601
CS
8.0 MHz
Same as above
Z8601-12
Z8601
DE
8.0 MHz
Same as above
Z8601-12
Z8601
DS
8.0 MHz
Same as above
Z8601
Z8601
PE
8.0 MHz
Same as above
Z8601
PS
8.0 MHz
Same as above
Z8601-12
CE
12.0 MHz
Z8MCU
(2K ROM, 40-pin)
Z8601-12
CS
12.0 MHz
Same as above
Z8601-12
DE
12.0 MHz
Same as above
NOTES: C
=
S
~
Package
Dimensions
r
PIN 1
IDENTIFICATION
12.0 MHz
Z8MCU
(2K ROM, 40-pin)
PE
12.0 MHz
Same as above
PS
12.0 MHz
LS
8.0 MHz
Z8601-12
LS
12.0 MHz
Z8603
RS
8.0 MHz
Z8603-12
RS
12.0 MHz
Cera.mic, D = Cerdip, L = Leadless Chip Carrier (LCC) P
GOC to + 7GoC.
= Plastic,
R
Description
= Protopack;
E
= - 40°C to
40
Same as above
Z8MCU
(2K XROM,
44-pin LCC)
Same as above
Z8MCU
(2K XROM,
Prototyping Device,
(40-pin)
Same as above
+ 70 0 85C,
21
~s:~ ~============~
)~
~
20
~o:~
I'
0.040
~~~!E~
m
II
r
0.125
MIN
0.050
1-±.015 BOTH ENDS
0.060
0.020
~
0.100
L±.010TYP
0.018
~L±.003TYP
40-Pin Ceramic Package
NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.
17
Package
DlmensloDs
(Continued)
40-Pln Cerdip Package
~=:g-
:~:
_0.5288Q,_
II- - ::::
II
0.489 SQ. II
*~"a~"
1
0.077
0.054
0.013
0.011
0.020 • 45° REF.
6
~D
II
0.056
0.040 -
II ~I
-
0.050
TYP
_ 0.025
TYP
U-Pin Leadle•• Package
18
0.040 x 45°
TYP. 3 REF.
Package
21
40
Dimensions
T
(Continued)
~~~=nrrrT~n=rrTT"=rrr~~n=rrTT"=rrr~~n=~
20
1r=~
!~
I·-----------------------~~~----------------------~'~I
0.62O~
0.&00
0.009
~
0.lS0
MAX
~,----------------------------------H----------~~O
~~
I~~::~~
J
'O-Pin Plastic Package
40
D
D
L~D
~
~~~
ffiDDDDDDDDDDDD
O.
MAX MAX
m_)
0
0
0
0
0
0
0
0
0
0
F
0
20
1
P IN 1 ..../
IDENTIFICATION
-
2.020 MAX
FOSO±.020
-------1.220 MAX
'I
t
0.300
:~~~Q==~II
r-0.S30 SQ.----j
MAX
MAX
-
0.010
--±.002
TYP
~OR~-----I
_
1+--0.l00±.010TYP
•
TYP
_
LO.04O+.007TYP
-------------------lR~~
-.002
MIN
,
'O-Pin Protopack Package
19
Notes
Zilog
Sales
Offices
West
Midwest
East
United Kingdom
Sales & Technical Center
Zilog, Incorporated
1315 Dell Avenue
Campbell, CA 95008
Phone: (408) 370-8120
TWX: 910-338-7621
Sales & Technical Center
Zilog, Incorporated
951 North Plum Grove Road
Suite F
Schaumburg, IL 60195
Phone: (312) 885-8080
TWX: 910-291-1064
Sales & Technical Center
Zilog, Incorporated
Corporate Place
99 South Bedford SI.
Burlington, MA 01803
Phone: (617) 273-4222
TWX: 710-332-1726
Zilog (U.K.) Limited
Zilog House
43-53 Moorbridge Road
Maidenhead
Berkshire, SL6 8PL England
Phone: 0628-39200
Telex: 848609
Sales & Technical Center
Zilog, Incorporated
28349 Chagrin Blvd.
Suite 109
Woodmere, OH 44122
Phone: (216) 831-7040
FAX: 216-831-2957
Sales & Technical Center
Zilog, Incorporated
240 Cedar Knolls Rd.
Cedar Knolls, NJ 07927
Phone: (201) 540-1671
Sales & Technical Center
Zilog, Incorporated
18023 Sky Park Circle
Suite J
Irvine, CA 92714
Phone: (714) 549-2891
TWX: 910-595-2803
Sales & Technical Center
Zilog, Incorporated
15643 Sherman Way
Suite 430
Van Nuys, CA 91406
Phone: (213) 989-7485
TWX: 910-495-1765
Sales & Technical Center
Zilog, Incorporated
1750 112th Ave. N.E.
Suite Dl61
Bellevue, W A 98004
Phone: (206) 454-5597
Zilog, Inc.
00-2037-03
South
Sales & Technical Center
Zilog, Incorporated
4851 Keller Springs Road,
Suite 211
Dallas, TX 75248
Phone: (214) 931-9090
TWX: 910-860-5850
Zilog, Incorporated
7113 Burnet Rd.
Suite 207
Austin, TX 78757
Phone: (512) 453-3216
1315 Dell Ave., Campbell, California 95008
Technical Center
Zilog, Incorporated
3300 Buckeye Rd.
Suite 401
Atlanta, GA 30341
Phone: (404) 451-8425
Sales & Technical Center
Zilog, Incorporated
1442 U.S. Hwy 19 South
SUlte 135
Clearwater, FL 33516
Phone: (813) 535-5571
Zilog, Inc.
613-B Pit! SI.
Cornwall, Ontario
Canada K6J 3R8
Phone: (613) 938-1121
France
Zilog, Incorporated
Tour Europe
Cedex 7
92080 Paris La Defense
France
Phone: (I) 778-14-33
Telex: 611445F
West Germany
Zilog GmbH
Eschenstrasse 8
D-8028 TAUFKIRCHEN
Munich, West Germany·
Phone: 89-612-6046
Telex: 529110 Zilog d.
Japan
Zilog, Japan K.K.
Konparu Bldg. 5F
2-8 Akasaka 4-Chome
Minato-Ku, Tokyo 107
Japan
Phone: (81) (03) 587-0528
Telex: 2422024 NB: Zilog J
Telephone (408)370-8000
TWX 910-338-7621
Printed in USA
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2011:09:16 17:53:03-08:00 Modify Date : 2011:09:17 01:59:57-07:00 Metadata Date : 2011:09:17 01:59:57-07:00 Producer : Adobe Acrobat 9.45 Paper Capture Plug-in Format : application/pdf Document ID : uuid:ced0d73b-006c-45e9-9a0a-e22249a79a68 Instance ID : uuid:f12c476f-77f0-45a0-8649-c61c10deb548 Page Layout : SinglePage Page Mode : UseNone Page Count : 24EXIF Metadata provided by EXIF.tools