AD622 User's Manual Ad622um
User Manual: ad622um
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AD 622 DATA ACQUISITION CARD USER'S MANUAL © 2014 HUMUSOFT ® © C O PY R IG H T 2014 by H U M U SO FT s.r.o.. A ll rights reserved. N o part of this publication m ay be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, w ithout the prior w ritten consent of H U M U SO FT s.r.o. L im ited W arranty: H U M U SO FT s.r.o. disclaims all liability for any direct or indirect damages caused by use or misuse of the AD 622 device or this documentation. H U M U SO FT is a registered trademark of H U M U SO FT s.r.o. O ther brand and product names are trademarks or registered trademarks of their respective holders. Printed in Czech Republic Table of Contents Table of Contents 1. Introduction 4 1.1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1. A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.2. D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.3. Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.4. Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. Installation 7 2.1. Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2. Driver Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. Programming Guide 10 3.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3. A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4. D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5. Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. I/O Signals 18 4.1. Output Connector Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Introduction Introduction 1. Introduction 1.1. General Description The AD 622 data acquisition card is designed for the need of connecting PC compatible computers to real world signals. The AD 622 contains 8 channel fast 14 bit A/D converter with simultaneous sample/hold circuit, 8 independent 14 bit D/A converters, 8 bit digital input port and 8 bit digital output port. The card is designed for standard data acquisition and control applications and optimized for use with Real Time Toolbox for Simulink®. AD 622 features fully 32 bit architecture for fast throughput. 1.2. Features List The AD 622 offers following features: C 32-bit architecture C 14 bit A/D converter with simultaneous sample & hold circuit C Conversion time 1.6 ìs for single channel or 3.7 ìs for 8 channels C 8 channel single ended fault protected input multiplexer C Input range ±10V C Internal clock & voltage reference C 8 D/A converters with 14 bit resolution and ±10V output range C 8 bit TTL compatible digital input port C 8 bit TTL compatible digital output port 4 Introduction C Interrupt C Requires one PCI 2.3 slot and optional second slot for second connector C Can be used in 5V or 3.3V slot C Power consumption 500 mA@+5V, 150 mA@+12V, 150 mA@-12V C Operating temperature 0°C to +70°C 1.3. Specifications 1.3.1. A/D Converter Resolution: 14 bits Number of channels: 8 single ended Sample/hold circuit: simultaneous sampling of all channels Conversion time: 1.6 ìs single channel 1.9 ìs 2 channels 2.5 ìs 4 channels 3.7 ìs 8 channels FIFO: 8 entries/one conversion cycle Input ranges: ±10V Input protection: ±18V Input impedance: > 1010 Ohm 1.3.2. D/A Converter Resolution: 14 bit Number of channels: 8 Settling time: max. 31 ìs (full scale swing, 1/2 LSB) Slew Rate: 10 V/ìs Output current: min. ±10 mA 5 Introduction Short circuit current: ±15 mA DC output impedance: max. 0.5 Ohm Load capacitance: max. 50 pF Differential nonlinearity: ±1 LSB 1.3.3. Digital Inputs Number of bits: 8 Input signal levels: TTL Logic 0: 0.8 V max. Logic 1: 2.0 V min. 1.3.4. Digital Outputs Number of bits: 8 Output signal levels: TTL Logic 0: 0.5 V max. @ 24 mA (sink) Logic 1: 2.0 V min. @ 15 mA (source) Outputs: TTL 6 Hardware Installation 2. Installation 2.1. Board Installation AD 622 has no switches or jumpers and you can install it in any free PCI expansion slot of your computer. Follow the steps outlined below: C Turn off the power of the computer system and unplug the power cord. C Disconnect all cables connected to the computer system. C Using a screwdriver, remove the cover-mounting screws. These screws are at the rear side of the PC. C Remove the computer system's cover. C Find an empty expansion slot in your computer for AD 622 card. If the slot still has the metal expansion-slot cover attached, remove the cover with a screwdriver. Save the screw to install the AD 622. C Hold the AD 622 firmly at the top of the board, and press the gold edge connector into an empty PCI expansion slot. C Using a screwdriver, screw the retaining bracket tightly against the rear plate of the computer system. C In case of using also quadrature encoder inputs or timer/counters install also the aditional connector with metal slot cover to the neighbouring slot. Otherwise you can disconnect the aditional connector from the board and save it for future use. C Replace the cover of the computer, and plug in the power cord. C Reconnect all cables that were previously attached to the rear of the 7 Hardware Installation computer. 2.2. Driver Installation Once you have installed AD 622 to PCI slot you can install Windows driver. Follow the steps outlined below: Turn on the computer, boot Microsoft Windows. AD 622 is detected by system automatically. In Add Hardware Wizzard window click Next. Insert installation floppy into drive a. In Found New Hardware Wizzard select Install the software automatically and click Next. 8 Hardware Installation When prompted for driver location type a:\ and click Next. Click Finish to complete installation. 9 Programming Guide 3. Programming Guide 3.1. Register Map AD 622 uses PCI Vendor ID 0x186C and Device ID 0x0622. Registers of AD 622 card are located in 3 memory mapped regions: R egion Function BADR0 PC I chipset, interrupts, status bits, (memory mapped) special functions BADR1 A /D , D /A , digital I/O Size W idth (bytes) (bits) 32 32 128 16/32 (memory mapped) Table 1. Base Address Regions PCI chipset (PCI 9030) and counter/timer chip are located in 32-bit regions and should be accessed by 32-bit instructions. BADR1 containing analog I/O has 16-bit architecture and registers are naturally 16-bit wide, but 32-bit access to this area is allowed as well under certain conditions. 32-bit access is broken by PCI chipset into two 16-bit cycles on the AD 622 internal bus. This allows increasing throughput by accessing two consecutive internal 16-bit registers by single PCI cycle. Therefore two D/A channels can be written or two A/D channels can be read at once which increases speed of data transfers almost twice. Do not use 32-bit access to other registers than ADDATA and DA0 - DA7. 10 Programming Guide A ddress R ead W rite B A D R 0+0x4C IN TC SR IN TC SR B A D R 0+0x54 G PIO C G PIO C Table 2. BADR0 Memory Map A ddress R ead W rite B A D R 1+0x00 A D D A T A - A /D data A D CT RL - A /D control B A D R 1+0x02 A D D A T A - A /D data mirror B A D R 1+0x04 A D D A T A - A /D data mirror B A D R 1+0x06 A D D A T A - A /D data mirror B A D R 1+0x08 A D D A T A - A /D data mirror B A D R 1+0x0A A D D A T A - A /D data mirror B A D R 1+0x0C A D D A T A - A /D data mirror B A D R 1+0x0E A D D A T A - A /D data mirror B A D R 1+0x10 D IN - D igital input D O UT - D igital output B A D R 1+0x20 A D ST AR T - A /D SW trigger D A 0 - D /A 0 data B A D R 1+0x22 D A 1 - D /A 1 data B A D R 1+0x24 D A 2 - D /A 2 data B A D R 1+0x26 D A 3 - D /A 3 data B A D R 1+0x28 D A 4 - D /A 4 data B A D R 1+0x2A D A 5 - D /A 5 data B A D R 1+0x2C D A 6 - D /A 6 data B A D R 1+0x2E D A 7 - D /A 7 data Table 3. BADR1 Memory Map 11 Programming Guide 3.2. Register Description INTCSR Bit 0 BADR0+0x4C Interrupt Control/Status Description A D INT E nable. 1 enables A /D interrupt, 0 disables A /D interrupt. R/W Default 0 A D IN T Polarity. 1 active high, 0 active low . Connected to 1 E O L C of A /D converter, should be set to active low for 0 normal operation. 2 5:3 6 7 A D INT Status. 1 indicates interrupt active, 0 indicates interrupt not active. 0 R eserved. 0 PC I Interrupt E nable. 1 enables PC I interrupt. 0 Softw are Interrupt. 1 generates PC I interrupt (IN TA #) if PC I Interrupt Enable bit is set (bit [6]=1). 0 A D INT Select E nable. 1 indicates edge triggered, 0 indicates 8 level triggered interrupt. 0 N ote: O perates only in H igh-Polarity mode (bit [1]= 1) 9 10 31:11 R eserved. A D INT C lear. W riting 1 to this bit clears A D IN T in edge mode. R eserved Table 4. INTCSR - Interrupt Control/Status Register Format 12 0 0 0x000600 Programming Guide GPIOC BADR0+0x54 Genaral Purpose I/O Control R/W Bit Description Default 16:0 R eserved. 0x006C 0 E O L C . Reads EO LC (end of last conversion) bit of A /D 17 converter. A ctive low , 0 w hen all channels converted, 1 0 during A /D conversion. 21:18 R eserved. 0x10 L DA C. Load D /A converters, active low . W riting 0 m akes 23 D /A latches transparent, 1 holds D /A outputs. C an be used for 0 simultaneous update of analog outputs. 25:24 26 31:27 R eserved. 10 D A C E N . 1 enables D /A outputs. 0 forces 0V to all D /A outputs. R eserved. 0 0 Table 5. GPIOC - General Purpose I/O Control Register Format ADCTRL Bit BADR1+0x00 A/D Control Description W Default 0 C H 0 select. 1 enables chanel 0 in channel scan list. 0 1 C H 1 select. 1 enables chanel 1 in channel scan list. 0 2 C H 2 select. 1 enables chanel 2 in channel scan list. 0 3 C H 3 select. 1 enables chanel 3 in channel scan list. 0 4 C H 4 select. 1 enables chanel 4 in channel scan list. 0 5 C H 5 select. 1 enables chanel 5 in channel scan list. 0 6 C H 6 select. 1 enables chanel 6 in channel scan list. 0 7 C H 7 select. 1 enables chanel 7 in channel scan list. 0 15:8 Reserved. 0x00 Table 6. ADCTRL - A/D Control Register Format 13 Programming Guide ADDATA Bit BADR1+0x00 A/D Data Description R Default A /D D ata. R eads data from A /D . Data is valid after EO LC bit 13:0 in G PIO C goes low . D ata from channels selected in A D C TR L N /A register are available in FIFO , low er number channels first. 15:14 R eserved N /A Table 7. ADDATA - A/D DATA Register Format N ote: ADDATA register has 7 mirror registers located from BADR1+0x02 to BADR1+0x0E. This arrangem ent remaps FIFO to linear address space and allow s reading consecutive values from A/D FIFO by 32-bit instructions. DIN BADR1+0x10 Digital Input Bit Description 7:0 D igital input 7:0. R eads digital input port. 15:8 R eserved R Default 1 N /A Table 8. DIN - Digital Input Register Format DOUT BADR1+0x10 Digital Output Bit Description 7:0 D igital output 7:0. W rites to digital output port. 15:8 R eserved W Default 0 N /A Table 9. DOUT - Digital Output Register Format ADSTART Bit 15:0 14 BADR1+0x20 A/D Conversion Start Description A /D C onversion Start. R eading this register triggers A /D conversion for all channels selected in AD CTRL. R Default N /A Programming Guide Table 10. ADSTART - A/D Conversion Start Register Format DA0 BADR1+0x20 D/A Converter 0 W DA1 BADR1+0x22 D/A Converter 1 W DA2 BADR1+0x24 D/A Converter 2 W DA3 BADR1+0x26 D/A Converter 3 W DA4 BADR1+0x28 D/A Converter 4 W DA5 BADR1+0x2A D/A Converter 5 W DA6 BADR1+0x2C D/A Converter 6 W DA7 BADR1+0x2E D/A Converter 7 W Bit Description Default 13:0 D A x. D /A converter channel n data. 0x3FFF 15:14 R eserved. N /A Table 12. DAx - D/A Converter Data Register Format Note: D/A converter outputs are updated only if LDAC bit in GPIOC registrer is set low (bit [23] at BADR0+0x54 =0). Otherwise D/A outputs are keeping old values and data written to DAn registers are kept until LDAC goes low. LDAC bit can be used for simultaneous update of D/A outputs. 3.3. A/D Converter A/D converter is controlled through ADDATA, ADCTRL, ADSTART and GPIOC registers. Before starting a conversion it is necessary to configure channels which will be converted by ADCTRL register. Each A/D channel has one bit in ADCTRL. Setting this bit includes the channel in conversion scan list. Conversion can be initiated by a read operation from ADSTART register. Once the conversion is started, selected channels are simultaneously sampled and converted. When the conversion of all selected channels is complete, EOLC (bit 17 in GPIOC register) is set low which means that converted data is available in output FIFO and can be 15 Programming Guide read from ADDATA register. EOLC remains low until next conversion is started. Starting new conversion resets FIFO. A/D converter has fixed input range ±10V and uses two's complement binary coding. A/D converter zero offset can be adjusted by R23. A/D gain can be adjusted by R25. Digital Value Analog Voltage 0x3FFF -0.0012 V 0x2000 -10.0000 V 0x1FFF 9.9988 V 0x0000 0.0000 V Table 13. A/D Inputs Coding 3.4. D/A Converters D/A converters are accessed through eight data input latch registers DA0 - DA7. D/A converter outputs are initially connected to ground until DACEN (bit 26 in GPIOC register) is set to 1. This bit can be used to disconnecting all analog outputs from D/A converters. Data from D/A input latch registers are passed to D/A converters only if LDAC (bit 23 in GPIOC register) is 0. If this bit is set to 1, data remains just in input latches without being written to D/A converters. Then if LDAC is set to 0, all D/A outputs are updated simultaneously from input latch registers. Output voltage ranges of D/A converters are ±10V and straight binary coding is used. After power-on or hardware reset the output voltage is set to 0V. D/A converter positive range can be adjusted by R5 while negative range can be adjusted by R8. 16 Programming Guide Digital Value Analog Voltage 0x3FFF 9.9988 V 0x2000 0.0000 V 0x1FFF -0.0012 V 0x0000 -10.0000 V Table 14. D/A Outputs Coding 3.5. Digital I/O AD 622 contains one 8-bit digital input port and one 8-bit digital output port. Digital input port can be accessed directly by read from DIN register. Inputs are TTL compatible. Digital output port can be accessed by byte or word write to DOUT register. Outputs are TTL compatible. After power-on or hardware reset digital outputs are set to 0. 17 I/O Signals 4. I/O Signals 4.1. Output Connector Signal Description The AD 622 multifunction I/O card is equipped with an on-board 37 pin D-type female connector X1. For pin assignment refer to Table 15. TB 620 Terminal Board can be connected to X1 connector. AD0-AD7 Analog inputs DA0-DA7 Analog outputs DIN0-DIN7 TTL compatible digital inputs DOUT0-DOUT7 TTL compatible digital outputs +12V +12V power supply -12V -12V power supply +5V +5V power supply AGND Analog ground GND Digital ground 18 I/O Signals AD0 1 AD1 2 AD2 3 AD3 4 AD4 5 AD5 6 AD6 7 AD7 8 AGND 9 DA6 10 DA7 11 DIN0 12 DIN1 13 DIN2 14 DIN3 15 DIN4 16 DIN5 17 DIN6 18 DIN7 19 20 DA0 21 DA1 22 DA2 23 DA3 24 DA4 25 DA5 26 -12V 27 +12V 28 +5V 29 GND 30 DOUT0 31 DOUT1 32 DOUT2 33 DOUT3 34 DOUT4 35 DOUT5 36 DOUT6 37 DOUT7 Table 15. X1 Connector Pin Assignement 19 Contact Address Contact address: HUMUSOFT s.r.o. Pobøežní 20 186 00 Praha 8 Czech Republic tel.: + 420 2 84011730 tel./fax: + 420 2 84011740 E-mail: info@humusoft.com Homepage: http://www.humusoft.com 20
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