Analog_system_lab_pro_manual_v103 Analog System Lab Pro Manual V103

User Manual: analog_system_lab_pro_manual_v103

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MANUAL
MANUAL
K.R.K. Rao and C.P. Ravikumar
Zoran Ristić
Miodrag Veljković
Danijela Krajnović
Aleksandar Nikolić
MikroElektronika Ltd.
www.mikroe.com
MANUAL
Analog
System
Lab Kit PRO
Analog
System
Lab Kit PRO
Authors
Editor in Chief
Assistant Editor
Cover Design
Graphic Design/DTP
Publisher
June 2012.
Special Thanks to
Harmanpreet Singh
for his help in performing the additional experiments
(Experiments 11-14) included in the new release of ASLK Pro.
Analog System Lab Kit PRO
Analog System Lab Kit PRO Manual
ver. 1.03b
0 100000 019382
page 3
Analog System Lab Kit PRO
Table of contents
Introduction 9
Experiment 1:
Experiment 2:
Analog System Lab 10
Organization of the Analog System Lab Course 11
Lab Setup 12
System Lab Kit ASLK PRO - An overview 13
Hardware 13
Software 13
Getting to know ASLK PRO 14
Organization of the Manual 16
1.1 Brief theory and motivation 18
1.1.1 UnityGainAmplier 18
1.1.2 Non-invertingAmplier 19
1.1.3 InvertingAmplier 19
1.2 Exercise Set 1 20
1.3 Measurements to be taken 20
1.4 What should you submit 21
1.5 Other related ICs 21
2.1 Brief theory and motivation 24
Experiment 3:
3.1 Brief theory and motivation 28
3.1.1 Integrators 28
3.1.2 Dierentiators 28
3.2 Specications 28
3.3 Measurements to be taken 28
3.4 What should you submit 29
3.5 Exercise Set 3 - Grounded Capacitor Topologies
ofIntegratorandDierentiator 30
Experiment 4:
4.1 Brief theory and motivation 32
4.2 Specication 33
4.3 Measurements to be taken 33
4.4 What should you submit 33
4.5 Exercise Set 4 34
2.1.1 Inverting Regenerative Comparator 24
2.1.2 Astable Multivibrator 24
2.1.3 Monostable Multivibrator (Timer) 25
2.2 Exercise Set 2 26
17
23
Study the characteristics of negative feedback amplifiers and
design of an instrumentation amplifier
Study the characteristics of regenerative feedback system with
extension to design an astable and monostable multivibrator
27
Study the characteristics of integrators and differentiator circuits
31
Design of Analog Filters
page 4 Analog System Lab Kit PRO
Experiment 6:
6.1 Brief theory and motivation 40
6.2 Specications 40
6.3 Measurements to be taken 40
6.4 What should you submit 41
6.5 Exercise Set 6 41
Experiment 7:
7.1 Brief theory and motivation 44
7.2 Specications 44
7.3 Measurements to be taken 45
7.4 What should you submit 45
7.5 Exercise Set 7 45
Experiment 9:
Experiment 10:
Experiment 8:
8.1 Brief theory and motivation 48
8.2 Specications 48
8.3 Measurements to be taken 48
8.4 What should you submit 48
8.5 Exercise Set 8 49
9.1 Brief theory and motivation 52
9.2 Specication 52
9.3 Measurements to be taken 52
9.3.1 Time response 52
9.3.2 Transfer function 52
9.4 What should you submit 53
9.5 Exercise Set 9 53
10.1 Brief theory and motivation 56
10.2 Specications 56
10.3 Measurements to be taken 56
10.4 What should you submit 57
10.5 Exercise Set 10 57
Experiment 5:
5.1 Brief theory and motivation 36
5.1.1 Multiplier as a Phase Detector 36
5.2 Specication 37
5.3 Measurements to be taken 37
5.3.1 Transient response 37
5.4 What should you submit 37
5.4.1 Exercise Set 5 38
Table of contents
35
39
43
47
51
55
Design of a self-tuned filter
Design a function generator and convert it to Voltage-Controlled
Oscillator/FM Generator
Design of a Phase Lock Loop (PLL)
Automatic Gain Control (AGC) Automatic Volume Control (AVC)
DC-DC Converter
Design a Low Dropout (LDO) regulator
page 5
Analog System Lab Kit PRO
Experiment 11:
Experiment 12:
Experiment 13:
Experiment 14:
11.1 Brief theory and motivation 60
11.2 Specications 60
11.3 Measurements to be taken 60
11.4 What should you submit 61
12.1 Brief theory and motivation 64
12.2 Specications 65
12.3 Measurements to be taken 65
12.4 What should you submit 65
13.1 Brief theory and motivation 68
13.2 Specications 68
13.3 Measurements to be taken 68
13.4 What should you submit 68
13.5 Exercise Set 13 69
14.1 Brief theory and motivation 72
A ICs used in ASLK PRO 75
A.1 TL082:JFET-InputOperationalAmplier 76
A.1.1 Features 76
A.1.2 Applications 76
A.1.3 Description 76
A.1.4 Download Datasheet 76
A.2 MPY634: Wide Bandwidth Analog Precision Multiplier 77
A.2.1 Features 77
A.2.2 Applications 77
A.2.3 Description 77
A.2.4 Download Datasheet 77
A.3 DAC 7821: 12 Bit, Parallel, Multiplying DAC 78
A.3.1 Features 78
A.3.2 Applications 78
A.3.3 Description 78
A.3.4 Download Datasheet 78
A.4 TPS40200: Wide-Input, Non-Synchronous Buck
DC/DC Controller 79
A.4.1 Features 79
A.4.2 Applications 79
A.4.3 Description 79
A.4.4 Download Datasheet 79
Table of contents
14.2 Specications 72
14.3 Measurements to be taken 72
14.4 What should you submit 72
14.5 Exercise Set 14 73
59
63
67
71
To study the parameters of an LDO integrated circuit
To study the parameters of a DC-DC Converter using on-board
Evaluation module
Design of a Digitally Controlled Gain Stage Amplifier
Design of a Digitally Programmable Square and Triangular wave
generator/oscillator
page 6 Analog System Lab Kit PRO
Signal Chain in an Electronic System 10
Analog System Lab Kit PRO 13
Picture of ASLK PRO 15
1.1 An ideal Dual-Input, Single-Output OP-Amp and its I-O
characteristic 18
1.2 A Unity Gain System 18
1.3 Magnitude and Phase response of a Unity Gain System 19
1.4 TimeResponseofanAmplierfor
a step input of size Vp 19
1.5 (a)Non-invertingamplierofgain2,
(b)Invertingamplierofgain2 19
1.6 NegativeFeedbackAmpliers 19
1.7 FrequencyResponseofNegativeFeedbackAmpliers 20
1.8 Outputs VF1 , VF2 and VF3 of Negative Feedback
AmpliersofFigure2.6forSquare-waveInputVG1 20
1.9 InstrumentationAmplierswith(a)threeand(b)two
operationalampliers 20
2.1 Inverting Schmitt-Trigger and
its Hysteresis Characteristic 24
2.2 Symbol for an Inverting Schmitt Trigger 24
2.3 Non-inverting Schmitt Trigger
and its Hysteresis Curve 24
2.4 Astable Multivibrator and its characteristics 25
2.5 Trigger waveform 25
2.6 Monostable Multivibrator and its outputs 25
3.1 Integrator 28
3.2 Dierentiator 28
3.3 FrequencyResponseofintegratoranddierentiator 29
3.4 Outputsofintegratoranddierentiatorfor
square-wave and triangular-wave inputs 30
Listofgures
B Introduction to Macromodels 83
Bibliography 99
C Activity - Convert your
PC/laptop into an Oscilloscope 87
D Analog System Lab Kit PRO
Connection Diagrams 89
B.1 Micromodels 84
B.2 Macromodels 84
C.1 Introduction 88
C.2 Limitations 88
A.5 TLV7250: Micropower Low-Dropout Voltage Regulator 80
A.5.1 Features 80
A.5.2 Applications 80
A.5.3 Description 80
A.5.4 Download Datasheet 80
A.6 Transistors: 2N3906, 2N3904, BS250 81
A.6.1 2N3906 Features, A.6.2 Download Datasheet 81
A.6.3 2N3904 Features, A.6.4 Download Datasheet 81
A.6.5 BS250 Features, A.6.6 Download Datasheet 81
A.7 Diode: 1N4448 Small Signal Diode 82
A.7.1 Features 82
A.7.2 Download Datasheet 82
Table of contents
page 7
Analog System Lab Kit PRO
Listofgures
3.5 Circuits for Exercise 3 30
4.1 A Second-order Universal Active Filter 32
4.2 Magnitude and Phase Response of
LPF,BPF,BSF,andHPFlters 32
5.1 Analog Multiplier 36
5.2 A Self-Tuned Filter based on a Voltage Controlled
Filter or Voltage Controlled Phase Generator 36
5.3 Output of the Self-Tuned Filter
based on simulation 37
6.1 Function Generator 40
6.2 Function Generator Output 40
6.3 Voltage-Controlled Oscillator (VCO) 41
7.1 Phase Locked Loop (PLL) and its characterisitics 44
7.2 Sample output waveform for
the Phase Locked Loop (PLL) Experiment 44
7.3 Block Diagram of Frequency Optimizer 45
8.1 Automatic Gain Control (AGC)/
Automatic Volume Control (AVC) 48
8.2 Input-Output Characteristics of AGC/AVC 48
8.3 AGC circuit and its output 49
9.1 DC-DC Converter and PWM waveform 52
9.2 (a) SMPS Circuit (b) Ouptut Waveforms 53
10.1 Low Dropout Regulator (LDO) 56
10.2 A regulator circuit and its simulated outputs - line
regulation and load regulation 56
11.1 Schematic diagram of on-board evaluation module 60
11.2(a) Line regulation 61
11.2(b) Load regulation 61
12.1 Schematic of the on-board EVM 64
12.2 Simulation waveforms - TP3 is the PWM waveform
and TP4 is the switching waveform 65
13.1 CircuitforDigitalControlledGainStageAmplier 68
13.2 Equivalent Circuit for simulation 69
13.3 Simulation output of digitally controlled Oscillator when
the input pattern for the DAC 69
was selected to be 0x800
14.1 Circuit for Digital Controlled Oscillator 72
14.2 Circuit for Simulation 73
14.3 Simulation Results 73
A.1 TL082-JFET-InputOperationalAmplier 76
A.2 MPY634 - Analog Multiplier 77
A.3 DAC 7821 - Digital to Analog Converter 78
A.4 TPS40200 - DC/DC Controller 79
A.5 TPS7250 -Micropower Low-Dropout Voltage Regulator 80
A.6 2N3906PNPGeneralPurposeAmplier 81
A.7 2N3906NPNGeneralPurposeAmplier 81
A.8 BS250 P-Channel Enh. Mode Vertical DMOS FET 81
A.9 1N4448 Small Signal Diode 82
C.1 BuercircuitneededtointerfaceanAnalogSignalto
Oscilloscope 88
D.1 OP-Amp1AconnectedinInvertingConguration 90
D.2 OP-Amp1Bconnectedininvertingconguration 90
D.3 OP-Amp 2A can be used in both inverting
andnon-invertingconguration 91
D.4 OP-Amp 2B can be used in both inverting
andnon-invertingconguration 91
D.5 OP-Amp3Acanbeusedinunitygainconguration
oranyothercustomconguration 92
page 8 Analog System Lab Kit PRO
introduction
List of tables
Listofgures
1.1 Plot of Peak to Peak amplitude of output
Vpp w.r.t. Input Frequency 21
1.2 Plot of Magnitude and Phase variation
w.r.t. Input Frequency 21
1.3 Plot of DC output voltage and phase variation
w.r.t. DC input voltage 21
2.1 Plot of Hysteresis w.r.t. Regenerative Feedback 25
D.6 OP-Amp3Bcanbeusedinunitygainconguration
oranyothercustomconguration 92
D.7 Connections for analog multiplier MPY634 - SET I 92
D.8 Connections for analog multiplier MPY634 - SET II 93
D.9 Connections for analog multiplier MPY634 - SET III 93
D.10 Connections for A/D converter DAC7821 - DAC I 94
D.11 Connections for A/D converter DAC7821 - DAC II 95
D.12 Connections for TPS40200 Evaluation
step-down DC/DC converter 96
D.13 Connections for TP7250 low-dropout linear voltage reg. 97
D.14 MOSFET socket 97
D.15 Bipolar Junction Transistor socket 97
D.16 Diode sockets 98
D.17 Trimmer-potentiometers 98
D.18 Main power supply 98
D.19 General purpose area (2.54mm / 100mills pad spacing) 98
3.1 Plot of Magnitude and Phase w.r.t. Input Frequency 29
3.2 Plot of Magnitude and Phase w.r.t. Input Frequency 29
3.3 Variation of Peak to Peak value of output
w.r.t. Peak value of Input 29
4.1 Transfer Functions of Active Filters 32
4.2 Frequency Response of a BPF with
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
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=
=
=
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=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
,
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
33
4.3 Frequency Response of a BSF with
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
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~r
yrr
=
=
++
=
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+
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=
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-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
,
33
5.1 Variation of output amplitude with input frequency 37
6.1 Change in frequency as a function of Control Voltage 41
7.1 Output Phase as a function of Input Frequency 45
7.2 Control Voltage as a function of Input Frequency 45
8.1 Transfer characteristic of the AGC circuit 48
9.1 Variation of output voltage with reference voltage
in a DC-DC converter 53
9.2 Variation of duty cycle with reference voltage
in a DC-DC converter 53
10.1 Variation of Load Regulation with Load Current
in an LDO 56
10.2 Variation of Line Regulation with Input Voltage
in an LDO 57
11.1 Line regulation 61
11.2 Load regulation 61
12.1 Variation of the duty cycle of PWM waveform
with input voltage 66
12.2 Line regulation 66
12.3 Load regulation 66
13.1 Variation in output amplitude with bit pattern 68
14.1 Varying the bit pattern input to the DAC 72
B.1 OperationalAmpliersavailablefromTexasInstruments85
page 9
Analog System Lab Kit PRO
Introduction
What you need to know before you get started
page 10 Analog System Lab Kit PRO
introduction
1
2
3
4
5
6
Analog System Lab
Although digital signal processing is the most common form of processing signals,
analog signal processing cannot be completely avoided since the real world is
analog in nature. Consider a typical signal chain (Figure below).
It is evident that analog circuits play a
crucial role in the implementation of an
electronic system.
The goal of the Analog System Lab
Course is to provide students an
exposure to the fascinating world
of analog and mixed-signal signal
processing. The course can be adapted
for an undergraduate or a postgraduate
curriculum. As part of the lab course,
the student will build analog systems
using analog ICs and study their macro
models, characteristics and limitations.
Our philosophy in designing this lab
course has been to focus on system
design rather than circuit design. We
feel that many Analog Design classes
in the colleges focus on the circuit
design aspect, ignoring the issues
encountered in system design. In the
real world, a system designer uses
the analog ICs as building blocks. The
focus of the system designer are to
optimize system-level cost, power, and
performance. IC manufacturers such as
TexasInstrumentsoeralargenumber
of choices of integrated circuits keeping
in mind the diverse requirements
of system designers. As a student,
you must be aware of these diverse
oeringsofsemiconductorsandselect
the right IC for the right application. We
have tried to emphasize this aspect
in designing the experiments in this
manual.
A sensor converts the real-world signal into an analog electrical signal.
This analog signal is often weak and noisy.
Ampliersareneededtostrengthenthesignal.Analoglteringmaybe
necessary to remove noise from the signal. This “front end” processing
improves the signal-to-noise ratio. Three of the most important building
blocks used in this stage are (a) Operational Ampliers, (b) Analog
multipliers and (c) Analog Comparators.
An analog-to-digital converter transforms the analog signal into a
stream of 0s and 1s.
The digital data is processed by a CPU, such as a DSP, a microprocessor,
or a microcontroller. The choice of the processor depends on how
intensive the computation is. A DSP may be necessary when real-
time signal processing is needed and the computations are complex.
Microprocessorsandmicrocontrollersmaysuceinotherapplications.
Digital-to-analog conversion (DAC) is necessary to convert the stream of
0s and 1s back into analog form.
TheoutputoftheDAChastobeampliedbeforetheanalogsignalcan
drive an external actuator.
Figure: Signal Chain in an Electronic System
Typical signal chain
page 11
Analog System Lab Kit PRO
Organization of the Course
In designing the lab course, we have assumed that there are about 12 during a semester. We have designed 14 experiments which can be carried out either individually or
by groups of two students. The experiments in Analog System Lab can be categorized as follows.
At the end of Analog System Lab, we believe you will have the following know-
how about analog system design.
1.YouwilllearnaboutthecharacteristicsandspecicationofanalogICsusedin
electronic systems.
2. You will learn how to develop a macromodel for an IC based on its terminal
characteristics, I/O characteristics, DC-transfer characteristics, frequency
response, stability characteristic and sensitivity characteristic.
3. You will be able to make the right choice for an IC for a given application.
4. You will be able to perform basic fault diagnosis of an electronic system.
In the rst part, the student will be exposed to the
operation of the basic building blocks of analog
systems. Most of the experiments in the Analog
System Lab Course are centered around the following
two components.
The OP-amp TL082, a general purpose JFET-
input operational amplier, made by Texas
Instruments.
Wide-bandwidth, precision analog multiplier
MPY634 from Texas Instruments.
Using these components, the student will build
gain stages, buers, instrumentation ampliers and
voltage regulators. These experiments bring out
several important issues, such as measurement of
gain- bandwidth product, slew-rate, and saturation
limitsoftheoperationalampliers.
Part-II concentrates on building analog systems using the blocks mentioned above.
First, we introduce integrators and dierentiatorswhichareessentialforimplementingltersthatcanband-
limit a signal prior to the sampling process to avoid aliasing errors.
We then introduce the analog comparator, which is a mixed-mode device - its input is analog and output is digital.
Inacomparator,therisetime,falltime,anddelaytimeareimportantapartfrominputoset.
A function generator is also a mixed-mode system that uses an integrator and a regenerative comparator as
building blocks. The function generator is capable of producing a triangular waveform and square waveform as
outputs. It is also useful in Pulse Width Modulation in DC-to-DC converters, switched-mode power supplies, and
Class-Dpowerampliers.
The analog multiplier, which is a voltage or current controlled amplier, nds applications in communication
circuits in the form of mixer, modulator, demodulator and phase detector. We use the multiplier in building Voltage
Controlled Oscillators, Frequency Modulated waveform generators, or Frequency Shift Key waveform generators
in modems, Automatic Gain Controllers, Amplitude Stabilized Oscillators, Self-tuned Filters and Frequency Locked
Loop using voltage controlled phase generators and VCOs and multiplier as phase detector are built and their lock
range and capture range.
In the Analog System Lab, the frequency range of all applications has been restricted to 1-10 kHz, with the
following in mind - (a) The macromodels for the ideal device can be used in simulation, (b) A PC can be used
in place of an oscilloscope. We have also included an experiment that can help the student use a PC as an
oscilloscope. We also suggest an experiment on the development of macromodels for an OP-Amp.
What is our goal?
Part I - Learning the basics Part II - Building analog systems
introduction
page 12 Analog System Lab Kit PRO
introduction
Lab Setup
ASLK PRO and the associated Lab Manual from Texas Instruments India - the
lab kit comes with required connectors. Refer to Chapter 1.4 for an overview of
the kit.
Oscilloscope. We provide an experiment that helps you build a circuit to directly
interface analog outputs to an oscilloscope (See Chapter C).
Dual power supply with the operating voltages of ±10V.
Function generators which can operate in the range on 1 to 10 MHz and capable
of generating sine, square and triangular waves.
A computer with installed circuit simulation software.
When we do not explicitly mention the magnitude and frequency of the input
waveform, please use 0 to 1V as the amplitude of the input and 1 kHz as the
frequency.
Always use sinusoidal input when you plot the frequency response and use
square wave input when you plot the transient response.
Precaution! Please note that TL082 is a dual OP-Amp. This means that the IC
has two OP-Amp circuits. If your experiment requires only one of the two ICs, do
not leave the inputs and output of the other OP- Amp open; instead, place the
second OP-Amp in unity-gain mode and ground the inputs.
Advisory to Students and Instructors. We strongly advise that the student
performs the simulation experiments outside the lab hours. The student must
bring a copy of the simulation results to the class and show it to the instructor at
the beginning of the class. The lab hours must be utilized only for the hardware
experiment and comparing the actual outputs with simulation results.
11
2
3
4
5
2
3
4
In all the experiments of Analog System Lab, please note the following.The setup for the Analog System Lab is very simple and requires the following.
page 13
Analog System Lab Kit PRO
System Lab Kit overview
ASLK PRO has been developed at Texas Instruments India. This kit is designed for
undergraduate engineering students to perform analog lab experiments. The main
ideabehindASLKPROistoprovideacostecientplatformortestbedforstudents
to realize almost any analog system using general purpose ICs such as OP-Amps and
analog multipliers.
ASLKPROcomeswiththreegeneral-purposeoperationalampliers(TL082) and three
wide-bandwidth precision analog multipliers (MPY634) from Texas Instruments. We
have also included two 12-bit parallel-input multiplying digital-to-analog converters
DAC7821, a wide-input non-synchronous buck-type DC/DC controller TPS40200, and
a low dropout regulator TPS7250 from Texas Instruments. A portion of ASLK PRO is
left for general-purpose prototyping which can be used for carrying out mini-projects.
Hardware
The kit has a provision to connect ±10V DC power supply. The kit comes with the
necessary short and long connectors.
This comprehensive user manual included with the kit gives complete insight of how
to use ASLK PRO. The manual covers exercises of analog system design along with
brief theory and simulation results.
Refer to Appendix A for the details of the integrated circuits that are included in ASLK
PRO. Refer to Appendix D for additional details of ASLK PRO.
introduction
The following software is necessary to carry out the experiments suggested in this
manual.
1. TINA or PSpice or any powerful simulator based on the SPICE Simulation Engine
2. FilterPro-Asoftwareprogramfordesigninganaloglters
3. SwitcherPro - A software program for designing power supplies
We will assume that you are familiar with the concept of simulation and are able to
simulate a given circuit.
FilterPro isaprogramfordesigningactivelters.Atthetimeofwritingthismanual,
FilterProVersion3.1isthelatest.Itsupportsthedesignofdierenttypesoflters,
namely Bessel, Butterworth, Chebychev, Gaussian, and linear-phase lters. The
softwarecanbeusedtodesignlow-passlters,high-passlters,band-stoplters,
andband-passlterswithupto10poles.Thesoftwarecanbedownloadedfrom[9].
Software
Analog System Lab Kit PRO
page 14 Analog System Lab Kit PRO
introduction
Getting to know ASLK PRO
The Analog System Lab kit ASLK PRO is divided into many sections. Refer to the photo of ASLK PRO when you read the following description.
There are three TL082 OP-Amp ICs labelled 1, 2, 3 on ASLK PRO. Each of these
ICshastwoampliers,whicharelabelledAandB.Thus1Aand1Barethetwo
OP-AMps on OP-AMP IC 1, etc. The six OP-amps are categorized as below.
1
4
5
6
7
8
9
10
2
3
OP-Amp Type Purpose
1A TYPE I InvertingCongurationonly
1B TYPE I InvertingCongurationonly
2A TYPE II FullConguration
2B TYPE II FullConguration
3A TYPE III BasicConguration
3B TYPE III BasicConguration
Thus, the OP-amps are marked TYPE I, TYPE II and TYPE III on the board. The
OP-AmpsmarkedTYPEIcanbeconnectedintheinvertingcongurationonly.
With the help of connectors, either resistors or capacitors can be used in the
feedback loop of the amplier. There are two such TYPE I ampliers. There
aretwoTYPEIIamplierswhichcanbeconguredtoactasinvertingornon-
inverting.Finally,wehavetwoTYPEIIIamplierswhichcanbeusedasvoltage
buers.
Three analog multipliers are included in the kit. These are wide-bandwidth
precision analog multipliers from Texas Instruments (MPY634). Each
multiplier is a 14-pin IC and operates on internally provided ±10V supply.
There are two digital-to-analog converters (DAC) provided in the
kit, labeled DAC I and DAC II. Both the DACs are DAC7821 from Texas
Instruments. They are 12-bit, parallel-input multiplying DACs which can be
used in place of analog multipliers in circuits like AGC/AVC. Ground and power
supplies are provided internally to the DAC. DAC Logic Supply Jumper can
be used to connect logic power supplies of both DAC I and DAC II to either
LDO or DC/DC converter located on the board. Using Tri-state switches you
can set 12-bits of input data for each DAC to desired value. Click the Latch
Data button to trigger Digital-to-analog conversion.
We have included a wide-input non-synchronous DC/DC buck
converter TPS40200 from Texas Instruments on ASLK PRO. The
converter provides an output of 3.3V over a wide input range
of 5.5-15V at output currents ranging from 0.125A to 2.5A.
Using Vout SEL jumper you can select output voltage to be either 5V or
3.3V. Another jumper allows you to select whether input voltage is provided
from the board (+10V), or externally using screw terminals.
We have included two transistor sockets on the board, which are needed in
designing an LDO regulator (Experiment 10), or custom experiments.
A specialized LDO regulator IC (TPS7250) has been included on the
board, which can provide a constant output voltage for input voltage ranging
from 5.5V to 11V. Ground connection is internally provided to the IC. Using
ON/OFF jumper you can enable or disable LDO IC. Another jumper allows
you to select whether input voltage is provided from the board (+10V), or
externally using screw terminals.
There are two 1kX trimmers (potentiometer) in the kit to enable the designer
to obtain a variable voltage if needed for a circuit. The potentiometers are
labeled P1 and P2. These operate respectively in the range 0V to +10V, and
-10V to 0V.
The kit has a screw terminals to connect ±10V power supply. All the
ICs on the board are internally connected to power supply. Please refer to
Appendix D for schematics of ASLK PRO.
We have included two diode sockets on the board, which can be used as
rectiersincustomlaboratoryexperiments.
The top right portion of the kit is a general-purpose area which can be
used as a proto-board. ± 10V points and GND are provided for this area.
page 15
Analog System Lab Kit PRO
Photo of ASLK PRO
introduction
6
1 11
2
8
10
3
7
4 5
9
page 16 Analog System Lab Kit PRO
The student should have the following skills to pursue Analog System Lab:
introduction
Organization of the Manual
There are 14 experiments in this manual and the next 14 chapters are devoted
to them, We recommend that in the first cycle of experiments, the instructor
introduces the ASLK PRO and ensure that all the students are familiar with a
simulation software. A warm-up exercise can be included, where the students
are asked to use the simulation software. For each of the experiments, we have
clarified the goal of the experiment and provided the theoretical background.
The Analog System Lab can be conducted parallel to a theory course on Analog
Design or as a separate lab that follows a theory course.
1. Basic understanding of electronic circuits
2. Basic computer skills required to run the
simulation tools
3. Ability to use the oscilloscope
4. Concepts of gain, bandwidth, transfer function,
lters,regulatorsandwaveshaping
page 17
Analog System Lab Kit PRO
Experiment 1
Chapter 1
Study the characteristics of negative feedback
amplifiers and design of an instrumentation amplifier
page 18 Analog System Lab Kit PRO
V2
V1
Vo= Ao [V1-V2]
+VSS
-VSS
experiment 1
The goal of this experiment is two-fold. In the rst part, we will understand
the application of negative feedback in designing ampliers. In the second
part, we will build an instrumentation amplier.
An OP-Amp [8]canbeusedinnegativefeedbackmodetobuildunitygainampliers,
non-invertingampliersandinvertingampliers.WhileanidealOP-Ampisassumed
tohaveinniteopen-loopgain and innitebandwidth,realOP-Ampshavenite
numbers for these parameters. Therefore, it is important to understand some
limitationsofrealOP-Amps,suchasniteGain-BandwidthProduct(GB). Similarly,
theslewrateandsaturationlimitsofanoperationalamplierareequallyimportant.
Given an OP-amp, how do we measure these parameters?
1.1 Brief theory and motivation
1.1.1UnityGainAmplier
Figure 1.1: An ideal Dual-Input, Single-Output OP-Amp and its I-O characteristic
Figure 1.2:
A Unity Gain System
(1.1)
(1.2)
(1.3)
(1.4)
(1.5)
(1.6)
(1.7)
Sincethefrequencyandtransientresponseofanamplierareimpactedbythese
parameters, we can measure the parameters if we have the frequency and transient
responseoftheamplier;youcanobtaintheseresponsecharacteristicsbyapplying
sinusoidal and square wave inputs respectively. We invite the reader to view the
recorded lecture [16].
An OP-Amp can be considered as a Voltage Controlled Voltage Source (VCVS) with
the voltage gain tending towards innity. For nite output voltage, the input
voltage is practically zero. This is the basic theory of OP-Amp in the negative
feedbackconguration.Figure1.1showsadierential-input,single-ended-output
OP-Amp which uses dual supply !Vss for biasing.
In the above equations, A0istheopen-loop gain; forrealampliers,A0 is in the
range 105 to 106 and hence V1 c V2 . A unity feedback circuit is shown in the Figure
1.2. It is easy to see that,
In OP-amps, closed loop gain A is frequency
dependent, as shown in the equation below, where
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
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01
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2
2
02
0
0
0
0
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$
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3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
and
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
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0
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2
2
02
0
0
0
0
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$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
are called the dominant poles of the OP-
amp. This transfer function is typical OP-Amp that
has internal frequency compensation. Please view
the recorded lecture [17] to get to know more about
frequency compensation.
WecannowwritethetransferfunctionTforaunity-gainamplieras,
The term
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
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01
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2
2
02
0
0
0
0
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$
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$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
, also known as the gain bandwidth product of the operational
amplier,isoneofthemostimportantparametersinOP-Ampnegativefeedback
circuit. The above transfer function can be rewritten as
VO
VS
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
Goal of the experiment
page 19
Analog System Lab Kit PRO
1.1.2Non-invertingAmplier
1.1.3InvertingAmplier
Figure 1.3: Magnitude and Phase response of a Unity Gain System
Figure 1.5: (a) Non-inverting amplier of gain 2, (b) Inverting amplier of gain 2
Figure 1.6: Negative Feedback Ampliers
where
and
Q is the quality factor and
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
is the damping factor, and
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
is the natural
frequency of the system. When the frequency response is plotted with magnitude
vs
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
and phase vs
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
, it appears as shown in Figure 1.3.
If one applies a step of peak voltage
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
totheunitygainamplier,andif
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
slew
rate, then the output appears as shown in Figure 2.4 if
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
or
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
.
Q is approximately equal to the total number of visible peaks in the step response and
the frequency of ringing is
~~
()
1
1
1
VAVV
VVA
V
V
V
A
A
V
Vas A
Ass
A
TA
AsAsAsA
sGBsAsGB
GB A
GB
TsQs
Q
GB A
GB
GB
Q
Q
V
VGB
Q
Q
dt
dV
V
1
1
1
11
1
1
1
1
1
1
1
1
1
2
1
2
1
114
2
02
2
s
s
dd
dddd
dd
d
d
d
d
p
p
p
0012
12
0
0
0
0
0
0
0
12
0
001022012
02 2
01
20
2
2
02
0
0
0
0
""
$
$
$
$
3
1
2
1
~~~
~~
~
~~
~~
~
~~
p
~
=
=
=+
=++
=
=++ ++
=+
=
=
=
=
=
~~
~
p
-
-
+
++
++
+
-
__
_
_
`
_
ii
i
i
j
i
.
Slew-rate is known as the maximum rate
at which the output of the OP-Amps is
capable of rising; in other words, slew
rate is the maximum value that dVo/dt
can attain. In this experiment, as we go
on increasing the amplitude of the step
input, at some amplitude the rate at
which the output starts rising remains
constant and no longer increases with
the peak voltage of input; this rate is
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
~ ~
( )
1
1
1
V A V V
V V A
V
V
V
A
A
V
Vas A
As s
A
TA
A sA sA sA
sGB sA sGB
GB A
GB
Ts Qs
Q
GB A
GB
GB
Q
Q
V
V GB
Q
Q
dt
dV
V
1
1
1
1 1
1
1
1
1
1
1
1
1
1
2
1
2
1
1 14
2
02
2
s
s
d d
d d d d
d d
d
d
d
d
p
p
p
0 01 2
1 2
0
0
0
0
0
0
0
1 2
0
0 01 0220 1 2
0 2 2
0 1
20
2
2
0 2
0
0
0
0
" "
$
$
$
$
3
1
2
1
~ ~~
~ ~
~
~ ~
~~
~
~~
p
~
=
=
=+
=+ +
=
=+ + + +
=+
=
=
=
=
=
~ ~
~
p
-
-
+
+ +
+ +
+
-
_ _
_
_
`
_
i i
i
i
j
i
VI
R
R
VO
VI
R
2R
VO
Anon-invertingamplierwithagainof2isshowninFigure1.5(a).
Aninvertingamplierwithagainof2isshowninFigure1.5(b).
called slew rate. It can therefore be determined by applying a square wave of Vp at
certain high frequency and increasing the magnitude of the input.
U1U2
R1
R2
VF2
U3
R3
R4
VF3VF1
VG1
+
Unity gain Non-inverting amp Inverting amplifier
Figure 1.4: Time Response of an
Amplier for a step input of size Vp
Figure 1.6 shows all the three negative feedback amplier congurations. Figure
1.7illustratesthefrequencyresponse(magnitude and phase)ofthethreedierent
negativefeedbackampliertopologies.Figure1.8showstheoutputofthethreetypes
ofampliersforasquare-waveinput,illustratingthelimitationsduetoslew-rate.
experiment 1
page 20 Analog System Lab Kit PRO
experiment 1
1.2 Exercise Set 1 1.3 Measurements to be taken
Designthefollowingampliers-(a)aunitygainamplier,(b)anon-inverting
amplierwithagainof2(Figure1.5(a))andaninvertingamplierwiththe
gain of 2.2 (Figure 1.5(b)).
DesignaninstrumentationamplierusingthreeOP-Ampswithacontrollable
dierential-mode gain of 3. Refer to Figure 1.9(a) for the circuit diagram.
Assume that the resistors have 1% tolerance and determine the Common
Mode Rejection Ratio (CMRR) of the setup and estimate its bandwidth. We
invite the reader to view the recorded lecture [18].
DesignaninstrumentationamplierusingtwoOP-Ampswithacontrollable
dierential-modegainof5.RefertoFigure1.9forthecircuitdiagramsofthe
instrumentationampliersanddeterminethevaluesoftheresistors.Assume
that the resistors have 1% tolerance and determine the CMRR of the setup
and estimate its bandwidth.
Figure 1.7: Frequency Response of Negative Feedback Ampliers
Figure 1.8: Outputs VF1, VF2 and VF3 of Negative Feedback
Ampliers of Figure 1.6 for Square-wave Input VG1
Transientresponse-Applyasquarewaveofxedmagnitudeandstudythe
eectofslewrateonunitygain,invertingandnon-invertingampliers.
Frequency Response - Obtain the gain bandwidth product of the unity gain
amplier, the inverting amplier and the non-inverting amplier from the
frequency response.
DC Transfer Characteristics - Study the saturation limits for an OP-Amp.
Determine the second pole of an OP-Amp and develop the macromodel for the
given OP-Amp IC TL082. See Appendix B for an introduction to the topic of
analog macromodels.
1 1
2
3
4
2
3
page 21
Analog System Lab Kit PRO
experiment 1
1.4 What should you submit 1.5 Other related ICs
Figure 1.9: Instrumentation Ampliers with (a) three
and (b) two operational ampliers
Table 1.1: Plot of Peak to Peak amplitude of output Vpp w.r.t. Input frequency
Table 1.2: Plot of Magnitude and Phase variation w.r.t. Input Frequency
Table 1.3: Plot of DC output voltage and phase variation w.r.t. DC input voltage
Submit the simulation results for Transient response, Frequency response and
DC transfer characteristics.
Take the plots of Transient response, Frequency response and DC transfer
characteristics from the oscilloscope and compare it with your simulation
results.
Apply square wave of amplitude 1V at the input. Change the input frequency
and study the peak to peak amplitude of the output. Take the readings in
Table 1.1 and compute the slew-rate.
SpecicICsfromTexasInstrumentswhichcanbeusedasinstrumentationAmpliers
are INA114, INA118 and INA128. Additional ICs from Texas Instruments which can
be used as general purpose OP-Amps are OPA703, OPA357, etc. See CHAPTER 2,
EXPERIMENT 1.
1
2
3
4
5
R
R
nR
V1
V2
R
R
R
R
VO
R
R
V1
R
nR
R
V2
VO
Frequency Response - Apply sine wave input to the system and study the
magnitude and phase response. Take your readings in Table 1.2.
DCtransferCharacteristics-VarytheDCinputvoltageandstudyitseecton
the output voltage. Take your readings in Table 1.3.
S. No. Input Frequency Peak to Peak Amplitude of output (Vpp)
1
2
3
4
S. No. Input Frequency Magnitude Variation Phase Variation
1
2
3
4
S. No. DC Input Voltage DC Output Voltage Phase Variation
1
2
3
4
Datasheets of all these ICs are available at http://www.ti.com.
An excellent reference about operational ampliers is the “Handbook of
Operational Amplier Applications” by Carter and Brown [5].
Further Reading
page 22 Analog System Lab Kit PRO
experiment 1
Notes on Experiment 1:
page 23
Analog System Lab Kit PRO
Experiment 2
Chapter 2
Study the characteristics of regenerative feedback
system with extension to design an astable and
monostable multivibrator
page 24 Analog System Lab Kit PRO
experiment 2
The goal of this experiment is to understand the basics of hysteresis and
the need of hysteresis in the switching circuits.
In the earlier experiment we had discussed the use of only negative feedback. Let
us now introduce the case of regenerative positive feedback as shown in Figure 2.1.
Thereaderwillbenetbylisteningtotherecordedlectureat[20].
2.1 Brief theory and motivation
2.1.1 Inverting Regenerative Comparator
2.1.2 Astable Multivibrator
Figure 2.1: Inverting Schmitt-Trigger and its Hysteresis Characteristic
Figure 2.3: Non-inverting Schmitt Trigger and its Hysteresis Curve
Goal of the experiment
- -
VbV
= =
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
V A
V
VAA
R R
R
A
A
A
V
V
V
V
V
T RC
RC
t
RC
V
R R
R
R
R
R
fTkHz
ms
RC
1
1
1
1 2
1
0
1 2
1
1
i
i
ss
ss
ss
ss
ss
0 0 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$ $
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
- -
VbV
= =
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
V A
V
VAA
R R
R
A
A
A
V
V
V
V
V
T RC
RC
t
RC
V
R R
R
R
R
R
fTkHz
ms
RC
1
1
1
1 2
1
0
1 2
1
1
i
i
ss
ss
ss
ss
ss
0 0 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$ $
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
- -
VbV
= =
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
V A
V
VAA
R R
R
A
A
A
V
V
V
V
V
T RC
RC
t
RC
V
R R
R
R
R
R
fTkHz
ms
RC
1
1
1
1 2
1
0
1 2
1
1
i
i
ss
ss
ss
ss
ss
0 0 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$ $
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
- -
VbV
= =
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
V A
V
VAA
R R
R
A
A
A
V
V
V
V
V
T RC
RC
t
RC
V
R R
R
R
R
R
fTkHz
ms
RC
1
1
1
1 2
1
0
1 2
1
1
i
i
ss
ss
ss
ss
ss
0 0 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$ $
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
(2.1)
(2.4)
(2.2)
(2.3)
+
R2
R1
VI
VO
+VSS
-VSS
However, when
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
, it becomes
unstable as amplier as output satu-
rates. When
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
the region of
operation of this circuit is regenerative
comparator. This is the mixed-mode
circuit. Output is stable only in two
stages
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
and
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. When the input
is large negative value output saturates
at
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
as input in increased output
remain at
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
until input reaches
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
at this point it changes to stable state
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. Now when the input is decreased it
can change state only at
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. Thus hysteresis of
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
is seen around 0. This kind
of comparator is a must while driving a MOSFET as a switch in ON-OFF controllers
SMPS (Switched Mode Power Supply), pulse width modulators and class-D audio
power ampliers. The symbol for this inverting type Schmitt trigger is shown in
Figure 2.2. The non-inverting Schmitt trigger is as shown in Figure 2.3.
R1
R2
VI
VO
+VSS
-VSS
Figure 2.2: Symbol for an Inverting
Schmitt Trigger
An astable multivibrator is shown in Figure 2.4. The square and the triangular
waveformsshowninthegurearebothgeneratedusingtheastablemultivibrator.
We refer to
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
as the regenerative feedback. The time period of the multivibrator is
given by
page 25
Analog System Lab Kit PRO
2.1.3 Monostable Multivibrator (Timer)
Figure 2.4: Astable Multivibrator and its characteristics
Figure 2.6: Monostable Multivibrator and its outputs
- -
VbV
= =
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
V A
V
VAA
R R
R
A
A
A
V
V
V
V
V
T RC
RC
t
RC
V
R R
R
R
R
R
fTkHz
ms
RC
1
1
1
1 2
1
0
1 2
1
1
i
i
ss
ss
ss
ss
ss
0 0 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$ $
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
- -
VbV
= =
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
V A
V
VAA
R R
R
A
A
A
V
V
V
V
V
T RC
RC
t
RC
V
R R
R
R
R
R
fTkHz
ms
RC
1
1
1
1 2
1
0
1 2
1
1
i
i
ss
ss
ss
ss
ss
0 0 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$ $
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
(2.5)
The circuit diagram for a monostable multivibrator is shown in 2.6. The trigger
waveform shown in Figure 2.5 is applied to the monostable. The negative edge
triggers the monostable, which produces the square waveform shown in Figure 2.6.
R2
R1
VC
R
VO
C
+VSS
-VSS
The monostable remains in the “on” state until it is triggered; at this time, the circuit
switches to the “o” state for a period equal to
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. The equation for
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
is shown
below.
After triggering the monostable at time t, the next trigger pulse must be applied
after
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. The formula for
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
is given below.
Table 2.1: Plot of Hysteresis w.r.t. Regenerative Feedback
S. No. Regenerative Feedback Hysteresis
1
2
3
4
R
R
VC
R
C
C
Trigger V
D
+VSS
-VSS
experiment 2
Figure 2.5: Trigger waveform
page 26 Analog System Lab Kit PRO
experiment 2
2.2 Exercise Set 2
Design a regenerative feedback circuit with the hysteresis of
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. Obtain the
DC transfer characteristics of the system. Estimate the hysteresis and see how
it can be controlled by varying the regenerative feedback
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
.
Vary either
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
or
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
in order to vary
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
. Apply the triangular waveform with
the peak voltage of 10V at a given frequency to both circuits and observe the
output waveform.
a) Submit the simulation results for DC transfer characteristics.
b)
Take the plots of DC transfer characteristics from oscilloscope and
compare it with simulation results.
1
23
c) Vary the regenerative feedback and see the variation in the
hysteresis, hysteresis is directly proportional to regenerative
feedback.
Design an astable multivibrator using charging and discharging of capacitor
C through resistance R between input and output of the Schmitt trigger. See
Figure 2.4. Assume that frequency
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
.
Design a monostable multivibrator for
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
and estimate
--
VbV
==
1
1
1
1
1
2
21
1
1
1
1,5
4
ln
ln
ln
VA
V
VAA
RR
R
A
A
A
V
V
V
V
V
TRC
RC
t
RC
V
RR
R
R
R
R
fTkHz
ms
RC
1
1
1
12
1
0
12
1
1
i
i
ss
ss
ss
ss
ss
00 0
0
0
0
0
0
2
$
$
$
$$
$
$
$
$
$$
$
$
!
1
b
b
b
b
b
b
b
b
b
b
b
b
b
x
&
=
=
=
+
=+
=
+
=
+
=
=
x
x
x
=- -
+
-
-
-
+
_
d
d
d
i
n
n
n
using the
formula 2.5.
Notes on Experiment 2:
page 27
Analog System Lab Kit PRO
Experiment 3
Chapter 3
Study the characteristics of integrators and
differentiator circuits
page 28 Analog System Lab Kit PRO
experiment 3
The goal of the experiment is to understand the advantages and
disadvantages of using integrators or dierentiators as a building block in
solving
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
order dierential equations or building an
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
order lter.
Integrators and dierentiators can be used as a building block for lters. Filters
form the essential block in analog signal processing to improve signal to noise
ratio. An OP-Amp can be used to construct an integrator or a dierentiator. This
experiment is to understand the advantage of integrators as building blocks instead
ofdierentiators.Dierentiatorsarerejectedbecauseoftheirpoorhigh-frequency
noise response.
AdierentiatorcircuitthatusesanOP-AmpisshowninFigure3.2.
FixtheRCtimeconstantoftheintegratorordierentiatorsothatthephaseshift
andmagnitudevariationoftheidealblockremainsunaectedbytheactivedevice
parameters.
Transient Response - Apply the step input and square wave input to the
integrator and study the output response. Apply the triangular and square
inputtothedierentiatorandstudytheoutputresponse.
Frequency Response - Apply the sine wave input and study the phase error
andmagnitudeerrorforintegratoranddierentiator.
An integrator circuit that uses an OP-Amp is shown in Figure 3.1.
Assuming
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
,
3.1 Brief theory and motivation
3.1.1 Integrators
3.1.2Dierentiators
3.2Specications
3.3 Measurements to be taken
Goal of the experiment
+ +
N
A GBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
s RC
sRC
Q
s s
sRC
GB
V
V
VRC
V T
T f
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
+ +
=
+ +
=
=
-
-
-
a
b
b
k
l
l
+ +
N
A GBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
s RC
sRC
Q
s s
sRC
GB
V
V
VRC
V T
T f
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
+ +
=
+ +
=
=
-
-
-
a
b
b
k
l
l
C
R
VI
VO = -VI/SCR
Figure 3.1: Integrator
Figure 3.2: Dierentiator
The output goes to saturation in practice. For making it work a high valued resistance
across
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
must be added in order to bring the OP-Amp to the active region where it
can act as an integrator.
(3.1)
(3.2)
Theoutputofthedierentiatorremainsatinputoset(approximately0).However,
any sudden disturbance at the input causes it to ring at natural frequency
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
.
C
R
VI
VO = -SCRVI
1
2
page 29
Analog System Lab Kit PRO
Simulatetheintegratoranddierentiatorandobtainthetransientresponse
and phase response.
Take the plots of transient response and phase response on an oscilloscope
and compare it with simulation results.
3.4 What should you submit
experiment 3
1
2
3
4
Frequency Response - Apply a sine wave to the integrator (similarly to the
dierentiator)andvarytheinputfrequencytoobtainphaseandmagnitude
error. Prepare a Table of the form 3.1. Figure 3.3 shows the typical frequency
responseforintegratorsanddierentiators.Foranintegrator,theplotshows
a phase lag which is proportional to
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
. The magnitude decreases with
increasingfrequency.Forthedierentiator,thephasewillchangerapidlyat
natural frequency in direct proportion to quality factor. The magnitude peaks
at natural frequency and is directly proportional to the quality factor.
Table 3.1: Plot of Magnitude and Phase w.r.t. Input Frequency
Table 3.2: Plot of Magnitude and Phase w.r.t. Input Frequency
Figure 3.3: Frequency Response of integrator and dierentiator
S. No. Input Frequency Magnitude Phase
1
2
3
4
5
S. No. Input Frequency Magnitude Phase
1
2
3
4
5
Transient response - Apply the square wave as an input to integrator, vary
the peak amplitude of the square wave and obtain the peak to peak value
of output wave.
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
is directly proportional to peak voltage of input
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
and is
given by
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
, where
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
,
++
N
AGBs
V
V
GB
s
sCR
C
V
V
GB
s
GB
sRC
sRC
Q
ss
sRC
GB
V
V
VRC
VT
Tf
f
1
1
1
1
1
2
1
th
i
i
pp
p
pp
p
0
0
2
00
2
2
0
GB RC$
$
$
$
~~
~
~
=
=
=
++
=
++
=
=
-
-
-
a
b
b
k
l
l
being the input frequency.
Figure 3.4 shows sample output waveforms obtained through simulation.
Table 3.3: Variation of Peak to Peak value of
output w.r.t. Peak value of Input
S. No. Peak Value of input Vp Peak to Peak value of output
1
2
3
4
page 30 Analog System Lab Kit PRO
Determine the function of the circuits shown in Figure 3.5. What are the advantages
and disadvantages of these circuits when compared to their conventional
counterparts?
3.5 Exercise Set 3 - Grounded
Capacitor Topologies of Integrator
andDierentiator
Figure 3.5: Circuit for Exercise 3
R
VI
VO = 2VI/SCR
R
R
R
C
R
VIVO = sCRVI/2
R
R
R
C
Notes on Experiment 3:
experiment 3
Figure 3.4: Outputs of integrator and dierentiator
for square-wave and triangular-wave inputs
U1
C1
R1
U2
C2
R2
+VF1 VF2
page 31
Analog System Lab Kit PRO
Experiment 4
Chapter 4
Design of Analog Filters
page 32 Analog System Lab Kit PRO
experiment 4
To understand the working of four types of second order lters, namely, Low
Pass, High Pass, Band Pass, and Band Stop lters, and study their frequency
characteristics (phase and magnitude).
Second order lters (or biquard lters) are important since they are the building
blocks in the construction of
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
orderlters,for
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
. When N is odd, the
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
order
ltercanberealizedusing
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
secondorderltersandonerstorderlter.When
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
is even, we need
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
secondorderlters.Pleaselistentotherecordedlecture
at [19]foradetailedexplanationofactivelters.
Secondorderltercanbeusedtoconstructfourdierenttypesoflters.Thetransfer
functionsforthedierentltertypesareshowninTable4.1,where
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
isthelowfrequencygainofthetransferfunction.Thelternamesareoften
abbreviated as LPF (Low-pass Filter), HPF (High-pass Filter), BPF (Band Pass Filter),
and BSF (Band Stop Filter). In this experiment, we will describe a universal active
lter,whichprovidesallthefourlterfunctionalities.Figure4.1showsasecond
orderuniversallterrealizedusingtwointegrators.Notethattherearedierent
outputs of the circuit that realize LPF, HPF, BPF and BSF functions.
4.1 Brief theory and motivation
Goal of the experiment
C
R
C
R
R
R
Q•R
VI
R/H0
R
BPF LPF
BSF
HPF
R
Figure 4.1: A Second-order Universal Active Filter Figure 4.2: Magnitude and Phase response of LPF, BPF, BSF, and HPF lters
Table 4.1: Transfer functions of Active Filters
Low Pass Filter
d
d
2
1
1
1
1
10
10
1
10
2 10 /
10
100 0.1sin sin
N
N
N
N
N
RC
H
V
V
Q
s s
H
V
V
Q
s s
Hs
V
V
Q
s s
Hs
V
V
Q
s s
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
H Q
V
V
rad s
H
t t t
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$ $
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~ ~
~
~
~
~
r
~ r
y r r
=
=
+ +
=
+ +
=
+ +
+
=
=
=
=
=
=
=
=
=
= +
-
=
+ +
+
-
-
-
-
b
bb
b
a
bb
__ _
l
l
l
l
k
l
l
ii i
High Pass Filter
d
d
2
1
1
1
1
10
10
1
10
2 10 /
10
100 0.1sin sin
N
N
N
N
N
RC
H
V
V
Q
s s
H
V
V
Q
s s
Hs
V
V
Q
s s
Hs
V
V
Q
s s
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
H Q
V
V
rad s
H
t t t
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$ $
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~ ~
~
~
~
~
r
~ r
y r r
=
=
+ +
=
+ +
=
+ +
+
=
=
=
=
=
=
=
=
=
= +
-
=
+ +
+
-
-
-
-
b
bb
b
a
bb
__ _
l
l
l
l
k
l
l
ii i
Band Pass Filter
d
d
2
1
1
1
1
10
10
1
10
2 10 /
10
100 0.1sin sin
N
N
N
N
N
RC
H
V
V
Q
s s
H
V
V
Q
s s
Hs
V
V
Q
s s
Hs
V
V
Q
s s
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
H Q
V
V
rad s
H
t t t
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$ $
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~ ~
~
~
~
~
r
~ r
y r r
=
=
+ +
=
+ +
=
+ +
+
=
=
=
=
=
=
=
=
=
= +
-
=
+ +
+
-
-
-
-
b
bb
b
a
bb
__ _
l
l
l
l
k
l
l
ii i
Band Stop Filter
d
d
2
1
1
1
1
10
10
1
10
2 10 /
10
100 0.1sin sin
N
N
N
N
N
RC
H
V
V
Q
s s
H
V
V
Q
s s
Hs
V
V
Q
s s
Hs
V
V
Q
s s
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
H Q
V
V
rad s
H
t t t
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$ $
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~ ~
~
~
~
~
r
~ r
y r r
=
=
+ +
=
+ +
=
+ +
+
=
=
=
=
=
=
=
=
=
= +
-
=
+ +
+
-
-
-
-
b
bb
b
a
bb
__ _
l
l
l
l
k
l
l
ii i
page 33
Analog System Lab Kit PRO
Design a Band Pass and a Band Stop lter. For the BPF, assume
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
. For the BSF, assume
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
.
Steady State Response - Apply a square wave input (Try
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
to both BPF and BSF circuits and observe the outputs.
Band Pass output will output the fundamental frequency of the
square wave multiplied by the gain at the centre frequency. The
amplitude at this frequency is given by
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
, where
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
is the
peak amplitude of the input square wave.
The Band Stop lter’s output will carry all the harmonics of the
square wave, other than fundamental. This illustrates the application
of BSF as a distortion analyzer.
Frequency Response - Apply the sine wave input and obtain the magnitude
and the phase response.
Simulate the circuits and obtain the Steady-State response and Frequency
response.
Take the plots of the Steady-State response and Frequency response from the
oscilloscope and compare it with simulation results.
Frequency Response - Apply a sine wave input and vary its input frequency
to obtain the phase and magnitude error. Use Table 4.2 and 4.3 to note your
readings. The nature of graphs should be as shown above.
The magnitude and phase response of LPF, BPF, BSF, and HPF lters are shown in
Figure4.2.Notethatthelow-passlterfrequencyresponsepeaksat
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and has a value equal to
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
. The phase sensitivity
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
is maximum at
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and is given by
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
. This information about phase variation can be used
to tune the lter to a desired frequency
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
. This is demonstrated in the next
experiment.
Forthebandpasslter,themagnituderesponsepeaksat
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and is given by
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
.Thebandstopltershowsanullmagnituderesponseat
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
.
4.2Specication
4.3 Measurements to be taken
4.4 What you should submit
experiment 4
Table 4-2: Frequency Response of a BPF with
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
,
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
Table 4-3: Frequency Response of a BSF with
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
,
Frequency Response of Filters
1
1
2
3
2
Band Pass Band Stop
S.No. Input Frequency Phase Magnitude Phase Magnitude
1
2
3
4
Band Pass Band Stop
S.No. Input Frequency Phase Magnitude Phase Magnitude
1
2
3
4
page 34 Analog System Lab Kit PRO
experiment 4
4.5 Exercise Set 4
Higher order lters are normally designed by cascading second order lters
and,ifneeded,onerst-orderlter.DesignathirdorderButterworthLowpass
Filter using FilterPro and obtain the frequency response as well as the
transientresponseofthelter.Thespecicationsarebandwidthofthelter
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
and
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
.
Design a notch lter (band-stop lter) to eliminate the 50Hz power
life frequency. In order to test this circuit, synthesize a waveform
d
d
2
1
1
1
1
10
10
1
10
210/
10
1000.1sinsin
N
N
N
N
N
RC
H
V
V
Q
ss
H
V
V
Q
ss
Hs
V
V
Q
ss
Hs
V
V
Q
ss
sH
Q
Q
HQ
Q
HQ
kHz
Q
kHz
Q
f kHz
f kHz
HQ
V
V
rad s
H
ttt
2
1
2
1
1
1
1
12
1
14
1
2
4
200
0
03
2
2
0
01
0
2
2
0
0
0
4
th
i
i
i
i
p
p
0
00
00
2
2
0
2
02
00
2
2
0
0
04
00
2
2
0
2
2
0
0
2
0
0
0
0
0
0
0
$
$
$
$
$$
$
$
2
~
~~
~~
~
~~
~
~~
~
~
~
z
~~
~
~
~
~
r
~r
yrr
=
=
++
=
++
=
++
+
=
=
=
=
=
=
=
=
=
=+
-
=
++
+
-
-
-
-
b
bb
b
a
bb
___
l
l
l
l
k
l
l
iii
Voltsanduseitastheinputtothelter.
What output did you obtain?
1
2
The circuit described in Figure 4.1 is a universal active lter circuit. While
this circuit can be built with OP-Amps, a specialized IC called UAF42 from
Texas Instruments provides the functionality of the Universal Active Filter.
We encourage you to use this circuit and understand its function.
Datasheet of UAF42 is available from http://www.ti.com.
Also refer to the application notes [7], [11], and [12].
Related Circuits
Notes on Experiment 4:
page 35
Analog System Lab Kit PRO
Experiment 5
Chapter 5
Design of a self-tuned filter
page 36 Analog System Lab Kit PRO
experiment 5
The goal of this experiment is to learn the concept of tuning a lter. The idea
is to adjust the RC time constants of the lter so that in phase response of
a lowpass lter, the output phase w.r.t. input is exactly 90ø at the incoming
frequency. This principle is utilized in distortion analyzers and spectrum
analyzers, such self tuned lters are used to lock on to the fundamental
frequency and harmonics of the input.
Inordertodesignself-tunedltersand
other analog systems in subsequent
experiments, we need to introduce
one more building block, the Analog
multiplier. The reader will benet
from viewing the recorded lecture at
[21]. In ASLK PRO, we have used to
MPY634 analog multiplier from Texas
Instruments. Refer to Figure 5.1, which shows the symbol of an analog multiplier.
5.1 Brief theory and motivation
5.1.1 Multiplier as a Phase Detector
Goal of the experiment
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
(5.1)
(5.2)
(5.3)
(5.4)
Figure 5.1: Analog Multiplier
where
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
is a non-linear term in
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
and
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
. For a precision multiplier,
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
and
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
, where
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
is the reference voltage of the multiplier. Hence, for precision
ampliers,
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
.
In Experiment 4, if we replace the integrator with a multiplier followed by integrator,
then the circuit becomes a Voltage Controlled Filter (or a Voltage Controlled Phase
Generator). This forms the basic circuit for self-tuned lter. See Figure 5.2. The
outputoftheself-tunedlterforasquare-waveinput,includingthecontrolvoltage
waveform,is showninFigure5.3.Thegurebringsouttheaspectofautomatic
control and self-tuning.
In the circuit of Figure 5.1, the output of the multiplier is
cos cosVV
VV t
2r
p p
0$z ~z
= +-
l
_ i
8
B
After passing through the low-pass lter, the high frequency component gets
lteredoutandonlytheaveragevalueofoutput
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
remains.
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
is called the sensitivity of the phase detector and is measured in Volts/radians.
For
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
,
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
becomes 0. This information is used to tune the voltage controlled
lter(VCF)automatically.Thevoltage-controlledlter,alongwithphasedetector,is
calledaself-tunedlter.SeeFigure5.2.
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
of the VCF is given by
Therefore,
The sensitivity of VCF is
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
radians/sec/Volts. Now
U1
C2
R1
U1•U2
R2
U2
C1
U1•U2
VF1
R8R6
R3
U3
R9
U4
R7
+
VG1
U5
R5
U1•U2
R4
C3
R11
R10
V3
+
VF3
VF2
Figure 5.2: A Self-Tuned Filter based on a Voltage Controlled Filter
or Voltage Controlled Phase Generator
page 37
Analog System Lab Kit PRO
5.2Specication
5.3 Measurements to be taken
5.4 What should you submit
5.3.1 Transient response
experiment 5
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
2
90
0
1
cos
tan
RC
V V K V K V K V V
V
V
V V
V V
V
V VVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
s s
H
Q
d
dQ
dV
dQV
V
kHz
Q
H QV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset x x y y x y
x
y
r x
y r
r
x yr
r
p p
pd
av
pd
av
r
c
crc
c
c c
i
r
r
c
c
av
i
0 0
0
0
0
0 0
0
0
00
1
0
0
0
# # # #
#
$
$
$ $
p
z
z
~
~
~ ~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
= + + + +
=
=
=
=
=
= =
=
=
=
=
=
=
p
z
+ +
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
Figure 5.3: Output of the Self-Tuned Filter based on simulation
Table 5.1: Variation of output amplitude with input frequency
If we consider the low-pass output, then
then
Hence, sensitivity of VCF(KVCF) is equal to
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
.
For varying input frequency the output phase will always lock to the input phase
with90˚phasedierencebetweenthetwoif
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
.
Simulate the circuits and obtain the transient response of the system.
Take the plots of transient response from oscilloscope and compare it with
simulation results.
Measure the output amplitude of the fundamental (Band Pass output) at
varyinginputfrequencyatxedinputamplitude.
Output amplitude should remain constant for varying input frequency within
the lock range of the system.
Apply a square wave input and observe the amplitude of the Band Pass output for
fundamental and its harmonics.
Assume that the input frequency is
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
and design a high-
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
 Band pass lter
whose centre frequency gets tuned to
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
.
Input voltage =
S.No. Input Frequency Output Amplitude
1
2
3
4
1
2
3
page 38 Analog System Lab Kit PRO
experiment 5
5.4.1 Exercise Set 5
Determinethelockrangeoftheself-tunedlteryoudesigned.Thelockrange
isdenedastherangeofinputfrequencieswheretheamplitudeoftheoutput
voltage remains constant at
2
90
0
1
cos
tan
RC
VV KVKVKVV
V
V
VV
VV
V
VVVV
VV
VV
Kd
dV
K
V
VRC
V
dV
d
VRCV
dV
d
dV
d
d
d
dV
d
V
V
Q
ss
H
Q
d
dQ
dV
dQV
V
kHz
Q
HQV
1
1
1
2
2
0
0
2
2
0
2
0
0
offset xxyy xy
x
y
rx
yr
r
xyr
r
pp
pd
av
pd
av
r
c
crc
c
cc
i
r
r
c
c
av
i
00
0
0
0
00
0
0
00
1
0
0
0
####
#
$
$
$$
p
z
z
~
~
~~
z
z
~
z~
~~
z
~
~
~
~
~
z~
z
#
#
=+ ++ +
=
=
=
=
=
==
=
=
=
=
=
=
p
z
++
+
-
-
-
-
l
c
b
b
d
bl
l
n
l
1
Texas Instruments also manufactures the following related ICs - Voltage-
controlled ampliers (e.g. VCA820) and multiplying DAC (e.g. DAC7821).
Refer to http://www.ti.com for application notes.
Related Circuits
Notes on Experiment 5:
page 39
Analog System Lab Kit PRO
Experiment 6
Chapter 6
Design a function generator and convert it to
Voltage-Controlled Oscillator/FM Generator
page 40 Analog System Lab Kit PRO
experiment 6
To understand a classic mixed mode circuit that uses two-bit A to D Converter
along with an analog integrator block. The architecture of the circuit is similar
to that of a sigma delta converter.
The feedback loop is made up of a two-bit A/D converter (at
1
1
V
fRCRR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
fRCRR
kHz
RC RR
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
21
1
2
1
2
21
ss
r
c
VCO
cr
c
VCO
c
21
!
$
$$$
$
$
$
#
=
== =
=
=
l
l
__
__
_
ii
ii
i
levels), also
called Schmitt trigger, and an integrator. The circuit is also known as a function
generator and is shown in Figure 6.1. The output of the function generator is
shown in Figure 6.2.
The function generator produces a square wave at the Schmitt Trigger output and
a triangular wave at the integrator output with the frequency of oscillation equal
to
1
1
V
fRCRR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
fRCRR
kHz
RC RR
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
21
1
2
1
2
21
ss
r
c
VCO
cr
c
VCO
c
21
!
$
$$$
$
$
$
#
=
== =
=
=
l
l
__
__
_
ii
ii
i
. The function generator circuit can be converted as a linear
VCO by using the multiplier integrator combination as shown in Figure 6.3.
6.1 Brief theory and motivation
6.2Specications
6.3 Measurements to be taken
Goal of the experiment
1
1
V
f RC RR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
f RC RR
kHz
RC R R
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
2 1
1
2
1
2
2 1
ss
r
c
VCO
cr
c
VCO
c
2 1
!
$
$ $$
$
$
$
#
=
= = =
=
=
l
l
_ _
_ _
_
i i
i i
i
1
1
V
f RC RR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
f RC RR
kHz
RC R R
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
2 1
1
2
1
2
2 1
ss
r
c
VCO
cr
c
VCO
c
2 1
!
$
$ $$
$
$
$
#
=
= = =
=
=
l
l
_ _
_ _
_
i i
i i
i
The frequency of oscillation of the VCO becomes
U1U2
R2R1
U1•U2
10
+
VG
VF1
R
C
VF2
Figure 6.1: Function Generator
Sensitivity of the VCO is the important parameter and is given as
1
1
V
fRCRR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
fRCRR
kHz
RC RR
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
21
1
2
1
2
21
ss
r
c
VCO
cr
c
VCO
c
21
!
$
$$$
$
$
$
#
=
== =
=
=
l
l
__
__
_
ii
ii
i
, where it is
given as
(6.1)
where
1
1
V
fRCRR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
fRCRR
kHz
RC RR
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
21
1
2
1
2
21
ss
r
c
VCO
cr
c
VCO
c
21
!
$
$$$
$
$
$
#
=
== =
=
=
l
l
__
__
_
ii
ii
i
VCO is an important analog circuit as it is used in FSK/FM generation and constitutes
the modulator part of the MODEM. As a VCO, it can be used in Phase Locked Loop
(PLL). It is a basic building block forming sigma delta converter. It can also be used
asreferenceoscillatorforaClassDamplier.
Design of a function generator which can generate square and triangular wave for
a frequency of 1 kHz.
Determine the frequency of oscillations of square and triangular wave. Frequency of
oscillation should be equal to
1
1
V
fRCRR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
fRCRR
kHz
RC RR
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
21
1
2
1
2
21
ss
r
c
VCO
cr
c
VCO
c
21
!
$
$$$
$
$
$
#
=
== =
=
=
l
l
__
__
_
ii
ii
i
. Convert the function generator into a
Voltage Controlled Oscillator (VCO) or FM/FSK generator also called “mod of modem.”
Figure 6.2: Function Generator Output
page 41
Analog System Lab Kit PRO
6.5 Exercise Set 6
6.4 What should you submit
experiment 6
Figure 6.3: Voltage-Controlled Oscillator (VCO)
Table 6.1: Change in frequency as a function of Control Voltage
Simulate the circuits and obtain the Transient response of the system.
C
R1
VCR1
R2
1
2
3
Take the plots of time response from oscilloscope and compare it with
simulation results.
VarythecontrolvoltageoftheVCOandseetheeectonthefrequencyof
the output waveform also measure the sensitivity (KVCO) of the VCO which is
nothing but
1
1
V
fRCRR
fRC VR
VR
KdV
df
RC VV
R
Vc
fHz Volts
fRCRR
kHz
RC RR
V
K
dV
df
V
kHz
kHz
14
4
4
14
1
4
1
10
21
1
2
1
2
21
ss
r
c
VCO
cr
c
VCO
c
21
!
$
$$$
$
$
$
#
=
== =
=
=
l
l
__
__
_
ii
ii
i
. Use Table 6.1 to note your readings.
Apply 1V, 1kHz square wave over 2V DC and observe the FSK for a VCO which is
designed for 10kHz frequency.
S.No. Control Voltage (Vc) Change in Frequency
1
2
3
4
Notes on Experiment 6:
page 42 Analog System Lab Kit PRO
experiment 6
Notes on Experiment 6:
page 43
Analog System Lab Kit PRO
Experiment 7
Chapter 7
Design of a Phase Lock Loop (PLL)
page 44 Analog System Lab Kit PRO
experiment 7
The goal of this experiment is to make you aware of the functionality of
the Phase Lock Loop commonly referred to as PLL which is primarily used
for a frequency synthesizer in high frequency stable clock generators. From
a crystal of some kHz range, it is possible to generate waveform of GHz
frequency range using a PLL.
Intheloopofself-tunedlterstudiedinexperimentnumber5ifwereplacethe
Voltage Control Filter (VCF) with Voltage Control Oscillator (VCO) (discussed in
experiment6)thenitbecomesPLLasshowninFigure7.1.Thereaderwillbenet
from viewing the recorded lecture at [22].
The sensitivity of the PLL is given by
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
and is equal to
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
, where
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
,
frequency of oscillation of VCO. Hence
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
, which is nothing but
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
Design a PLL to get locked to frequency of 1 kHz.
7.1 Brief theory and motivation
7.2Specications
Goal of the experiment
K
dV
d
VRC
V
dV
d
VRC
V
V
K V
V
V
V
V
K AK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCO c
Q
CQ
i
ref
pd VCO
$
$
# # #
~
~
r
=
=
=
~
~
~
~
VCO
R
C
Vref=0
VI
VO
Vc Control Voltage
Input Frequency
W(Input)
(Output)
(7.1)
Figure 7.1: Phase Locked Loop (PLL) and its characteristics Figure 7.2: Sample output waveform for the Phase Locked Loop (PLL) Experiment
When no input voltage is applied to the system, the system oscillates at the free
running frequency of the VCO, given by
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
with corresponding control voltage of
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
. If the input is applied to the system with the same frequency as
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
, the PLL
willcontinuetorunatthefreerunningfrequencyandthephasedierencebetween
the two signals
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
and
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
as90˚since
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
is 0 (already explained in Experiment 5
of Chapter 6). As the frequency of input signal is changed, the control voltage will
change correspondingly, so as to lock the output frequency to the input frequency.
Asaresult,thereisachangeofphasedierencebetweenthetwosignalsaway
from90˚.Therangeofinputfrequenciesforwhichoutputfrequenciesgetslocked
totheinputiscalledthelockrangeofthesystem.Thelockrangeis denedas
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
on either side of
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
cr
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
.
-
-
+
+
VG1
+
V2
R1
R4
U3
U4
R5
C1
R2
R3
V1
+
+
VF1
VF3
VF2
10.00
5.00
0.00
-5.00
-10.00
0.00 10.00m 20.00m 30.00m
Time (s)
Output
U2
U1
C2
U
1
C
1
R
1
V
G1
U
2
U
3
R
2
R
3
R
5
U
4
R
4
C
2
V
F3
+
V
F2
V
F1
V
1
+
V
2
+
page 45
Analog System Lab Kit PRO
7.3 Measurements to be taken 7.5 Exercise Set 7
7.4 What you should submit
experiment 7
Table 7.1: Output Phase as a function of Input Frequency
Table 7.2: Control Voltage as a function of Input Frequency
Figure 7.3: Block Diagram of Frequency Optimizer
Measure the lock range of the system and measure the change in the phase of
the output signal as input frequency is varied within the lock range.
Vary the input frequency and obtain the change in the control voltage and plot
the output. A sample output characteristic of the PLL is shown in Figure 7.2.
Design a Frequency Synthesizer to generate a waveform of 1MHz frequency from a
100kHz crystal as shown in Figure 7.3.
Simulate the circuits and obtain the characteristics of the system.
Take the plots of characteristics from oscilloscope and compare it with
simulation results.
Measure the change in the phase of the output signal as input frequency is
varied within the lock range.
Vary the input frequency and obtain the change in the control voltage. Use
Table 7.2 to record your readings.
1
1
2
3
4
2
S.No. Input Frequency Control Voltage
1
2
3
4
S.No. Input Frequency Output Phase
1
2
3
4
Notes on Experiment 7:
page 46 Analog System Lab Kit PRO
experiment 7
Notes on Experiment 7:
page 47
Analog System Lab Kit PRO
Experiment 8
Chapter 8
Automatic Gain Control (AGC) Automatic Volume
Control (AVC)
page 48 Analog System Lab Kit PRO
experiment 8
In the front-end electronics of a system, we may require that the gain of the
amplier be adjustable, since the amplitude of the input keeps varying. Such
a system can be designed using feedback. This experiment demonstrates
one such system.
Thereaderwillbenetfromtherecordedlecturesat[25]. Another useful reference
is the application note on Automatic Level Controller for Speech Signals using PID
Controllers [2].
In the signal chain of an electronic system, the output of the sensor can vary
depending on the strength of the input. To adapt to wide variations in the magnitude
oftheinput,wecandesignanamplierwhosegaincanbeadjusteddynamically.
This is possible when the input signal has a narrow bandwidth and the control
system is called Automatic Gain Control or AGC. Since we may wish to maintain the
outputvoltageoftheamplierataconstantlevel,wealsousethetermAutomatic
Volume Control (AVC). Figure 8.1 shows an AGC circuit. The typical I/O characteristics
of AGC/AVC circuit is shown in Figure 8.2. As shown in Figure 8.2, the output value
of the system remains constant at
VV
VVV
2
2
rref
pi rref
=
beyond input voltage
VV
VVV
2
2
rref
pi rref
=
.
Simulate the circuit of Figure 8.1 and obtain the Transfer Characteristic of the
system. Assume that the input comes from a function generator; use a sine
wave input of a single frequency.
Build the circuit shown on Figure 8.1. Plot/print the transfer characteristic
using the oscilloscope and compare it with simulation results.
Transfer Characteristics - Plot the input versus output characteristics for the AGC/AVC.
Design AGC/AVC system to maintain the peak amplitude of the sine wave at 2V.
8.1 Brief theory and motivation
8.2Specication
8.3 Measurements to be taken
8.4 What you should submit
Goal of the experiment
C
R
Vref=
VC
VI=Vpi•sinωtVpi•sinωt
2VR
VOP
VR
VC
]
]
VR
VC•Vpi
]
]
VR
1
2
2
Figure 8.1: Automatic Gain Control (AGC)/Automatic Volume Control (AVC)
Figure 8.2: Input-Output Characteristics of AGC/AVC
Table 8.1: Transfer characteristic of the AGC circuit
1
2
3Plot the output as a function of input voltage. Enter sucient number of
readings in Table 8.2. Does the output remain constant as the magnitude of
the input is increased? Beyond what value of the input voltage does the gain
begin to stabilize? We have included sample output waveform for the AGC
circuit in Figure 8.3.
S.No. Input Voltage Output Voltage
1
2
3
4
page 49
Analog System Lab Kit PRO
8.5 Exercise Set 8
experiment 8
Figure 8.3: AGC circuit and its output
DeterminethelockrangefortheAGC,whichisdenedastherangeofinputvalues
for which output voltage remains constant.
U1U2
+
R4R3
R1
R2
C1
VF1
VG1
VF2
10
VXVY
10
VXVY
V2
+
V1
+
Notes on Experiment 8:
page 50 Analog System Lab Kit PRO
experiment 8
Notes on Experiment 8:
page 51
Analog System Lab Kit PRO
Experiment 9
Chapter 9
DC-DC Converter
page 52 Analog System Lab Kit PRO
experiment 9
The goal of the experiment is to design a high-ecient DC-DC converter using
a general purpose OP-Amp and a comparator and study its characteristics.
We also aim to study the characteristics of a DC-DC converter IC, and for
this purpose we selected the wide-input non synchronous buck DC/DC
controller TPS40200 from Texas Instruments. This IC is included in ASLK
PRO as evaluation module.
Thereaderwillbenetfromviewingtherecordedlectureat[24]. Also refer to the
applicationnote,DesignConsiderationsforClass-DAudioPowerAmpliers[15].
Function generator is the basic block for DC-DC converter. The triangular output
of the function generator with peak amplitude
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
and frequency
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
is fed to the
comparator whose other input is connected to the reference voltage Vref. The output
of this comparator is the PWM (Pulse width modulation) waveform whose duty cycle
is given by
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
, where T is time period of triangular wave and is
equal to
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
. This duty cycle is directly proportional to reference voltage Vref.
Ifweconnectthelosslesslow-passlter(LClter)attheoutputofthecomparator
as shown in Figure 9.1, it is possible to get stable DC voltage
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
withhigheciency
Design a DC-DC converter which has 10 kHz oscillator whose triangular wave output
with peak amplitude Vp is fed to a comparator whose other input is connected to
Vref (reference voltage).
Obtain the time response of the system and plot
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
versus
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
.
Obtain the
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
versus
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
characteristics.
9.1 Brief theory and motivation
9.2Specications
9.3 Measurements to be taken
Goal of the experiment
L
Vref
Function
Generator
CRL
Vg VOVav
+VSS
-VSS
Figure 9.1: DC-DC Converter and PWM waveform
9.3.1 Time response
9.3.2 Transfer function
between
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
depending upon the value of
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
. Hence circuit becomes SMPS system
where
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
.
IfwereplaceLClterwithMOSFET,andapplyaudioinputas
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
to the comparator
thenatoutputoftheMOSFETampliedaudiooutputisobtained,thisisClassD
PowerAmplieroperation.
page 53
Analog System Lab Kit PRO
9.4 What should you submit
9.5 Exercise Set 9
experiment 9
Simulate the circuits and obtain the time response and transfer characteristics
of the system.
Take the plots of transfer characteristics and time response from oscilloscope
and compare it with simulation results.
Plot the average output voltage
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
as a function of reference voltage
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
and
obtain the plot; the plot will be linear.
Plot the duty cycle
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
as a function of reference voltage
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
and obtain the
plot, the plot will be linear. We have included the typical output waveform of
the SMPS circuit in Figure 9.2
Perform the same experiment with the specialized IC for DC-DC converter from
Texas Instrument TPS40200 and compare the characteristics of both systems.
1
2
3
4
Table 9.1: Variation of output voltage with reference voltage in a DC-DC converter
Table 9.2: Variation of duty cycle with reference voltage in a DC-DC converter
S.No. Reference Voltage Output Voltage
1
2
3
4
S.No. Reference Voltage Duty Cycle
V
f
V
TVV
T
Tf
V
V
VVVV
TV
T
2
11
1
p
ref
refp
av
ss
av refssp
ref
!
$
x
x
x
=
=
=
-
-
_i
1
2
3
4
+
LR1
R2
R4R3C1
VG1
VF1 VF2
V2
+
U1
U2
Figure 9.2: (a) SMPS Circuit (b) Output Waveforms
page 54 Analog System Lab Kit PRO
experiment 9
Notes on Experiment 9:
page 55
Analog System Lab Kit PRO
Experiment 10
Chapter 10
Design a Low Dropout (LDO) regulator
page 56 Analog System Lab Kit PRO
experiment 10
The goal of this experiment is to design a Low Dropout regulator using
general purpose OP-Amp and PMOS and study its characteristics with
extension to study characteristics of TPS7250 IC. We aim to design a
linear voltage regulator with high eciency which is used in low noise high
eciency applications.
LDOisusedtoproduceregulatedvoltageforhigheciencylownoiseapplications.
Please view the recorded lectures at [23] for a detailed description of voltage
regulators. In case of DC-DC converter switching takes place (as shown by PWM
waveform) and switching is a source of noise but in LDO no switching takes place
henceitisusedasvoltageregulatorinlownoisehighecientsystems.Asshown
in the circuit below LDO uses PMOS along with OP-Amp so that power dissipation in
OP-Ampisminimalandeciencyishigh.Theregulatedoutputvoltageisgivenby
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
.
Output Characteristics - Measure the load regulation of the system. Load regulation
is given by
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
when Io is varying from minimum to maximum value.
Transfer Characteristics - Measure the line regulation of the system. Line regulation
is given by
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
when
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
is varying from minimum to maximum value.
Measure the ripple rejection by applying the ripple input voltage and measuring
the output ripple voltage.
Measure the output impedance of the LDO, which is given by
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
. We have shown
the sample output of load regulation and line regulation in Figure 10.2.
Generate 3V output when input voltage is varying from 4V to 5V.
10.1 Brief theory and motivation
10.3 Measurements to be taken
10.2Specications
Goal of the experiment
Figure 10.1: Low Dropout Regulator (LDO)
Table 10.1: Variation of Load Regulation with Load Current in an LDO
Figure 10.2: A regulator circuit and its simulated
outputs - line regulation and load regulation
R2
R1RL
R
+
Vref
VUN
VOR1
R2
= Vref [1+ ]
1
2
3
4
R52k
R10k
R410k
R610k
Z1
D1
R310k
R210k VF1
V1
+
S.No. Reference Voltage Output Voltage
1
2
3
4
page 57
Analog System Lab Kit PRO
Simulate the circuits and compute the output characteristics, transfer
characteristics, and ripple rejection.
Perform the same experiment with the specialized IC for LDO from Texas Instrument
TPS7250 and compare the characteristics of both systems.
10.4 What should you submit 10.5 Exercise Set 10
experiment 10
Figure 10.3: Variation of Line Regulation with Input Voltage in an LDO
1
Input resistance (ohms)
Input voltage (V)
S.No. Input Voltage Line Regulation
1
2
3
4
S.No. Ripple Input Voltage Ripple Output Voltage
1
2
3
4
Take the plots of output characteristics, transfer characteristics and ripple rejection
from the Oscilloscope and compare it with simulation results.
Obtain the Load Regulation - Vary the load such that load current varies and obtain
the output voltage, see the point till where output voltage remains constant.
After that output will fall as the load current increases.
Obtain the Ripple Rejection - Apply the input ripple voltage and see the output
ripple voltage, with the input ripple voltage output ripple voltage will rise.
Obtain the Line Regulation - Vary the input voltage and plot the output voltage as
a function of the input voltage. Until the input reaches a certain value, the output
voltage remains constant; after this point, the output voltage will rise as the input
voltage is increased.
Calculate the output impedance.
2
3
4
5
6
page 58 Analog System Lab Kit PRO
experiment 10
Notes on Experiment 10:
page 59
Analog System Lab Kit PRO
Experiment 11
Chapter 11
To study the parameters of an LDO integrated circuit
page 60 Analog System Lab Kit PRO
experiment 11
The ASLK Pro kit includes an on-board voltage regulator evaluation module
TPS7250. The goal of this experiment is to study the parameters of the
Low Dropout Regulator (LDO) IC TPS7250 from Texas Instruments using
the on-board evaluation module.
TPS7250 evaluation module helps us evaluate the operation and performance of
the TPS7250 family of linear regulators. The linear regulator TPS7250 from Texas
Instrumentsiscapableof200mAoutputcurrentat5Vxedoutputvoltagelevel.
It is a low quiescent current, low noise, high PSRR, fast start-up LDO with excellent
line and transient response. See Figure 11.1 for the schematic diagram of the
evaluation module.
The input supply voltage VIN is fed at screw terminal CN3 and falls in the range
5.5V to 11V. The leads to the input supply must be as short as possible and must
be twisted to reduce EMI transmission. The capacitor C102 improves the transient
response of the regulator. The capacitor C101 helps to reduce the ringing on input
when supply wires are too long.
To study the parameters (Line regulation, Load regulation) of LDO TPS7250 using the
on-board evaluation module.
11.1 Brief theory and motivation 11.2Specications
11.3 Measurements to be taken
Goal of the experiment
Obtain the Line Regulation: Vary the input voltage (from 5.5V to 11V in steps of
0.5V)andplottheoutputvoltageasthefunctionoftheinputvoltageforaxed
output load.
Obtain the Load Regulation: Vary the load (within the permissible limits) such that
loadcurrentvariesandobtaintheoutputvoltageforaxedinputvoltage.Plot
the output voltage as function of the load current.
1
2
Figure 11.1: Schematic diagram of on-board evaluation module
The regulator can be enabled/disabled using the ON/OFF jumper JP7. The “Enable”
pin(EN)mustneverbeleftoating.Connectingashortingjumperwirebetweenpins
1 (GND) and pin 2 (EN) of JP7 enables the regulator. Connecting a jumper wire between
pins 2 (EN) and pin 3 (VIN) disables the regulator. Output voltage is available on screw
terminal CN4, or Vout pin header, and the typical load current is 200mA.
VIN 5.5 -10 V VOUT 5
V
GND
3
IN 5
IN 6
EN
4
OUT 7
OUT 8
SENSE
1
PG
2
TPS7250
SENSE
PG
GND
EN
OUT
OUT
IN
IN
IC1
IN
OUT
ENABLE
REG IN
HD117
VIN
HD118
VOUT
HD116
GND
R4
4K7
OUT
CN3
VIN
CN4
VOUT
JP6
VCC+10
R101
247K
C101
1u F
C102
100nF
C103
10uF
JP7
GND
GND
LD4
@250mA
ON
OFF
page 61
Analog System Lab Kit PRO
11.4 What should you submit?
experiment 11
Table 11.1: Line regulation
Table 11-.2: Load regulation
Simulate the circuit using a simulator such as PSPICE Capture (version 15.7 or
higher) or Cadence 16.0. The typical characteristics will be of the form as shown
in Figure 11-2(a) and Figure 11-2(b).
12
3
Vary the input voltage for constant load and observe the output voltage. Use
Table 11-1 for taking the readings for line regulation.
1.8032V
1.8028V
1.8024V
1.8020V
VOUT
VIN
3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
1.8040V
1.8035V
1.8030V
VOUT
IOUT
21.5mA 30.0mA 40.0mA 50.0mA 60.0mA 70.0mA
S.No. Input voltage (VIN) Output voltage (VOUT)
1
2
3
4
S.No. Load current (IOUT) Output voltage(VOUT)
1
2
3
4
Vary the load so that load current varies; observe the output voltage for
constant input voltage. Use Table 11-2 for taking the readings for load
regulation.
Figure 11.2(a): Line regulation
Figure 11.2(b): Load regulation
page 62 Analog System Lab Kit PRO
experiment 11
Notes on Experiment 11:
page 63
Analog System Lab Kit PRO
Experiment 12
Chapter 12
To study the parameters of a DC-DC Converter using
on-board Evaluation module
page 64 Analog System Lab Kit PRO
experiment 12
The goal of the experiment is to congure the on-board evaluation module
TPS40200 on the ASLK PRO Kit as a switched mode power supply that
can provide a regulated output voltage of 5V or 3.3V for an input whose
range is 6V-15V.
The TPS40200 evaluation module included on ASLK PRO. Kit uses the TPS40200
non synchronous buck converter to provide a resistor-selected, 3.3V or 5V output that
delivers up to 2.5A from up to 16V input bus. See Figure 12-1 for a schematic diagram
of the EVM. The evaluation module operates from a single supply and uses the single
12.1 Brief theory and motivation
Goal of the experiment
Figure 12.1: Schematic of the on-board EVM
P–channel Power FET and Schottky diode to produce a low cost buck converter. The
regulated output of the EVM is resistance-selected and can be adjusted within the
limited range by making the changes in the feedback loop, as shown below.
The feedback factor
0.7
1
VV
VV
RR
R
VVdutycycle
TP
TP
M
R
TP
J
TP
TP
R
C
209207
209
205
207
209
20
201
203
204
201
213
out
ref
ref
out in
8
$
X
=
=
=
=
b
b+
can be changed by changing feedback resistance R209 to
adjust the output. But in ASLK PRO, we do not have the provision of changing R209.
We can therefore achieve this task by connecting an external resistance of suitable
value between the terminals TP8 and the ground.
0.7
1
VV
V V
R R
R
V Vdutycycle
TP
TP
M
R
TP
J
TP
TP
R
C
209 207
209
205
207
209
20
201
203
204
201
213
out
ref
ref
out in
8
$
X
=
=
=
=
b
b+
RC
1
SS
2
COMP
3
FB
4GND5
DRV 6
ISNS 7
VDD 8
TPS40200
RC
SS
COMP
FB
VDD
ISNS
DRV
GND
U4
4
3
6
5
2
1
Q101
FDC5614P
VIN 6 – 15V
VOUT 3.3V or 5V
VIN
VOUT
GATE
SRC
DRAIN
RC
SS
COMP
FB
ISNS
DRV
DC/DC IN
HD143
VOUT
R3
4K7
C202
68pF
C203
220nF
C204
220nF C205
470pF
C206
4.7nF
C207
33pF
C208
100nF
C211
10uF
C212
10uF
C213
470pF
C214
470nF
C201
220uF
C209
330uF
C210
330uF
L201
33uH
R201
100K
R202
0.03
R203
1K
R204
0E
R205
100K
R206
25.5E
R207
100K
R208
49.9
R209
27K4
R210
1M
R211
41K2
HD120
TP2
HD121
TP3
HD122
TP1
HD123
TP8
HD124
TP6
HD125
TP9
HD126
TP4
HD127
TP7
HD128
TP5
LD3
JP9
D201
MBRS340
CN6
VOUT
CN5
VIN
JP8
VCC+10
@ 0.125 – 2.5A
3.3V
5V
HD142
Vin
page 65
Analog System Lab Kit PRO
The unregulated input is connected at screw terminal CN5. Output load is connected
to screw terminal at CN6.The switching waveform can be observed at the terminal
TP4.The evaluation module has a switching frequency of 200 kHz. This frequency
is decided by the combination of R201 and C213. The duty cycle of this waveform
varies linearly with the input voltage for a constant output voltage, as shown
below.
What should be the value of the external resistance to be connected between
TP8 and Ground to congure the evaluation module to generate regulated
output voltage of 5V?
Simulatetheconguredcircuitusingasimulator.Thetypicalwaveformswill
be of the form shown in Figure 12.2.
In this experiment, we wish to study the line and load regulation for the TPS40200
integratedcircuitwhenitisconguredtogeneratea5VDCoutput.
Conguretheonboardevaluationmoduletogenerateconstant5VDCoutputby
making the changes in the feedback path using the available terminals.
12.2Specications
12.3 Measurements to be taken
12.4 What should you submit?
experiment 12
Figure 12.2: Simulation waveforms - TP3 is the PWM waveform
and TP4 is the switching waveform
The output ripple voltage can be measured across terminals TP5 and TP7 by simply
placing the oscilloscope probes. The oscilloscope must be set for
0.7
1
VV
VV
RR
R
VVdutycycle
TP
TP
M
R
TP
J
TP
TP
R
C
209207
209
205
207
209
20
201
203
204
201
213
out
ref
ref
out in
8
$
X
=
=
=
=
b
b+
impedance,
AC coupling. The same terminals can be used for the measurement of the regulated
output DC voltage using a voltmeter.
What should be the value of the external
resistance for the regulated output of 5V?
Obtain the Line Regulation: Vary the input voltage from 10V to 15V in steps
of 0.5V and plot the output voltage as the function of the input voltage for a
constant output load.
Obtain the Load Regulation: Vary the load (within the permissible limits) such
that load current varies and obtain the output voltage for constant input
voltage. Plot the output voltage as a function of the load current.
1
1
3
4
2
2
TP3
TP4
Vin
Vout
1.00
0.00
20.00
-10.00
10.00
10.00
5.01
4.98
10.00m 10.02m 10.05m 10.07m 10.10m
Congure the on board evaluation module to generate a regulated output
voltage of 5V, and observe the waveforms mentioned in Figure 12.2 and
compare with the simulation results.
Vary the input voltage for a regulated output voltage of 5V and observe the
change in the duty cycle of the PWM waveform. Use Table 12.1 to record the
readings. Compare the readings with simulation results and plot the graph
between the input voltage and duty cycle. Is the plot linear?
0.7
1
VV
V V
R R
R
V Vdutycycle
TP
TP
M
R
TP
J
TP
TP
R
C
209 207
209
205
207
209
20
201
203
204
201
213
out
ref
ref
out in
8
$
X
=
=
=
=
b
b+
page 66 Analog System Lab Kit PRO
experiment 12
Varytheinputvoltageforaxedloadandobservetheoutputvoltage.Use
Table 12.2 for taking the readings for line regulation
Vary the load so that load current varies; observe the output voltage for a
xedinputvoltage.UseTable12.3fortakingthereadings.
Table 12.1: Variation of the duty cycle of PWM waveform with input voltage
Table 12.2: Line regulation
Table 12.3: Load regulation
S.No. Input voltage (Vin) Duty cycle
1
2
3
4
S.No. Input voltage (Vin) Output voltage (Vout)
1
2
3
4
S.No. Load current Output voltage (Vout)
1
2
3
4
5
6
Notes on Experiment 12:
page 67
Analog System Lab Kit PRO
Experiment 13
Chapter 13
Design of a Digitally Controlled Gain Stage Amplifier
page 68 Analog System Lab Kit PRO
experiment 13
The goal of the experiment is to design a negative feedback amplier whose
gain is digitally controlled using a multiplying DAC.
More and more, we see the trend of using Digital Signal Processors and/or
Microcontrollers to control the behavior of the front-end signal conditioning circuits
in an instrumentation or RF system. Examples of such systems are Automatic Gain
Control system and Automatic Voltage Control systems. In this experiment, we will
demonstrate the use of a multiplying DAC to control the gain of a programmable gain
amplier;weincludeanexerciseattheendofthischaptertoillustratetheuseofa
microcontrollerforcontrollingthegainofaprogrammablegainamplier.
See Figure 13.1 for the circuit of an inverting amplier; the gain of this amplier
can be digitally controlled by changing the bit pattern presented to the input of the
multiplying DAC, DAC7821.
To study the variation in gain when the bit pattern applied to the input of the DAC is
changed.
Apply a 100 Hz sine wave of 100mV peak amplitude at
...AA A
VV
R
R
A
V
RR
2
4096
11 10 0
1
2
21
out in
nn
in
0
11
$$
=
_i
/
and measure the output
voltage amplitude. Select
...AA A
VV
R
R
A
V
RR
2
4096
11 10 0
1
2
21
out in
nn
in
0
11
$$
=
_i
/
to be 2.2. Vary the input bit pattern
...AA A
VV
R
R
A
V
RR
2
4096
11 10 0
1
2
21
out in
nn
in
0
11
$$
=
_i
/
and
measure the amplitude of the output voltage.
The circuit of Figure 13.1 cannot be directly simulated, since the macro-model for
DAC7821 is not available at the time of writing. For the purpose of simulation,
wewillusethemacromodelofadierent12-bitDAC,theMV95308. Simulate
the circuit schematic shown in Figure 13.2, which is equivalent to the circuit
ofFigure13.1.Observetheoutputwaveformsfordierentbitpatterns.The
typical simulation waveforms are of the form shown in Figure 13.3.
Use the circuit shown in Figure 13.1 for practical implementation of the Digital
programmablegainstageamplier.
Applythesinewaveofxedamplitudeandvarythebitpattern,asshown
in Table 13.1. Note the Peak to Peak amplitude of the output. Compare the
simulation results with the practical results.
13.1 Brief theory and motivation
13.2Specications
13.3 Measurements to be taken
13.4 What should you submit?
Goal of the experiment
C1
R1
R2DAC7821
RFB VDD
GND
VREF
IOUT1
IOUT2
VDD
VOUT
VIN
TL082
TL082
Figure 13.1: Circuit for Digital Controlled Gain Stage Amplier
Table 13.1: Variation in output amplitude with bit pattern
Let the 12-bit input pattern to DAC be given by
...AA A
VV
R
R
A
V
RR
2
4096
11 10 0
1
2
21
out in
nn
in
0
11
$$
=
_i
/
. The expression for the
outputvoltageofthenegativefeedbackamplierisgivenby
1
2
3
S.No. BIT Pattern Peak to Peak Amplitude of the output
1100000000000
2010000000000
3001000000000
4000100000000
...AA A
V V
R
R
A
V
R R
2
4096
11 10 0
1
2
2 1
out in
nn
in
0
11
$ $
=
_ i
/
page 69
Analog System Lab Kit PRO
0
11
E
A
RO
RI
GND
1
2
3
4
5
6
7
8
9
10
MV95308
V1
5V
R2
R1
+
R31k
J1
J2
J2
J1
R41k
VOUT
TL082
TL082
VIN
V2
10V
V3
10V
J1
J2
+
+
+
13.5 Exercise Set 13
experiment 13
Figure 13.3: Simulation output of digitally controlled gain stage amplier
when the input pattern for the DAC was selected to be 0x800
Amplitude(volts)
500.00m
-500.00m
Amplitude(volts)
100.00m
-100.00m
0.00 5.00m 10.00m 15.00m 20.00m
Time(s)
Output
Input
Design a digitally programmable non-inverting amplier whose gain varies
from 6.4 and above.
Notes on Experiment 13:
Figure 13.2: Equivalent Circuit for simulation
page 70 Analog System Lab Kit PRO
experiment 13
Notes on Experiment 13:
page 71
Analog System Lab Kit PRO
Experiment 14
Chapter 14
Design of a Digitally Programmable Square and
Triangular wave generator/oscillator
page 72 Analog System Lab Kit PRO
C1
R1
R 1k DAC7821
RFB VDD
GND
VREF
IOUT1
IOUT2
VDD
VOUT
TL082
TL082
C 1u
TL082
R2
experiment 14
To design a digitally controlled oscillators where the oscillation frequency of
the output square and triangular wave forms is controlled by a binary pattern.
Such systems are useful in digital PLL and in FSK generation in a MODEM.
In Experiment 6, we used an analog multiplier in conjunction with an integrator to
build a VCO. In this experiment, we will use a multiplying DAC7821 (instead of a
multiplier) and an integrator to implement a digitally controlled square and triangular
wave generator. See Figure 14.1 for the circuit schematic of a digitally programmable
square and triangular wave generator. VOUT is the square wave output and the
output of the integrator is the triangular waveform.
Design a Digitally Programmable Oscillator that can generate square and triangular
waveforms with a maximum frequency of 400 Hz.
Implement the Digitally programmable Square and Triangular wave generator using
the circuit as shown in Figure 14.1.Observe the frequency of Oscillations of system
and vary it by varying bit pattern input to the DAC.
Simulate the circuit using any simulator and observe the frequency of oscillation
of the square and triangular waveforms. See Figure 14.2 for the result of
simulation. The typical simulation waveforms are of the form shown in Figure
14.3. For this simulation, we used the macro-model of MV95308 since the
macro-model for the DAC is not available at the time of writing.
VarythebitpatterninputtotheDACinmannerspeciedinTable14.1and
note down the change in the frequency of oscillations and compare the
practical results with the simulation results.
Plot a graph where the x-axis shows the analog equivalent of the bit pattern
and the y-axis shows the frequency of oscillations. Note that the 12-bit input
to the DAC is interpreted as an unsigned number.
14.1 Brief theory and motivation
14.2Specications
14.3 Measurements to be taken
14.4 What Should you Submit
Goal of the experiment
Figure 14.1: Circuit for Digital Controlled Oscillator
Frequency of oscillations of digital programmable oscillator is given by
Table 14.1: Varying the bit pattern input to the DAC
S.No. BIT Pattern Peak to Peak Amplitude of the output
1100000000000
2010000000000
3001000000000
4000100000000
1
2
3
1fRC R
RA
Q
4
1
4096
2
10
nn
1
20
11
$ $
= +
=
b l
/
page 73
Analog System Lab Kit PRO
experiment 13
0
11
E
A
RO
RI
GND
1
2
3
4
5
6
7
8
9
10
MV95308
V1
5V
R1k
R1
R31k
J1
J2
J2
J1
R41k
V squ
TL082
TL082
V tri
V2
10V
V3
10V
J1
J2
C
R2
J2
J1
TL082
1u
+
+
+
3.00
-3.00
V tri
0.00 25.00m 50.00m 75.00m 100.00m
Time(s)
10.00
-10.00
V squ
Notes on Experiment 14:
Figure 14.3: Simulation Results
Figure 14.2: Circuit for Simulation
14.5 Exercise Set 14
Designadigitallyprogrammableband-passlterwith
1fRC R
RA
Q
4
1
4096
2
10
nn
1
20
11
$$
=+
=
bl
/
and gain of 1 at
the centre frequency.
page 74 Analog System Lab Kit PRO
experiment 14
Notes on Experiment 14:
page 75
Analog System Lab Kit PRO
ICs used in
ASLK PRO
Appendix A
Texas Instruments Analog ICs used in ASLK PRO
page 76 Analog System Lab Kit PRO
TheTL08xJFET-inputoperationalamplierfamily
is designed to oer a wider selection than any
previouslydevelopedoperationalamplierfamily.
Each of these JFET-input operational ampliers
incorporates well-matched, high-voltage JFET
and bipolar transistors in a monolithic integrated
circuit. The devices feature high slew rates, low
input bias and oset currents, and low oset
voltagetemperaturecoecient.Osetadjustment
and external compensation options are available
withintheTL08xfamily.TheC-suxdevicesare
characterizedforoperationfrom0˚Cto70˚C.The
I-sux devices are characterized for operation
from -40˚C to 85˚C. The Q-sux devices are
characterizedforoperationfrom-40˚Cto125˚C.
•LowPowerConsumption
•WideCommon-ModeandDierentialVoltageRanges
•InputBiasandOsetCurrents
•OutputShort-CircuitProtection
•LowTotalHarmonicDistortion...0.003%Typ
•HighInputImpedance...JFET-InputStage
•Latch-Up-FreeOperation
•HighSlewRate...13V/μsTyp
•Common-ModeInputVoltageRangeIncludesVCC+
•InputBuer
•High-SpeedIntegrators
•D/AConverters
•SampleAndHoldCircuits
http://www.ti.com/lit/gpn/tl082
JFET-Input Operational Amplier
A.1.1 Features
A.1.3 Description
A.1.4 Download Datasheet
Figure A.1: TL082 - JFET-Input Operational Amplier
A.1.2 Applications
TL082
appendix A
page 77
Analog System Lab Kit PRO
The MPY634 is a wide bandwidth, high accuracy,
four-quadrant analog multiplier. Its accurately
laser-trimmed multiplier characteristics make it
easy to use in a wide variety of applications with
a minimum of external parts, often eliminating
all external trimming. Its dierential X, Y, and Z
inputsallowcongurationasamultiplier,squarer,
divider, square-rooter, and other functions while
maintaining high accuracy. The wide bandwidth
of this new design allows signal processing
at IF, RF, and video frequencies. The internal
output amplier of the MPY634 reduces design
complexity compared to other high frequency
multipliers and balanced modulator circuits.
It is capable of performing frequency mixing,
balanced modulation, and demodulation with
excellent carrier rejection. An accurate internal
voltage reference provides precise setting of
the scale factor. The dierential Z input allows
user-selected scale factors from 0.1 to 10 using
external feedback resistors.
•WideBandwidth:10MHzTyp
•0.5%MaxFour-QuadrantAccuracy
•InternalWide-BandwidthOpAmp
•EasyToUse
•LowCost
•PrecisionAnalogSignalProcessing
•ModulationAndDemodulation
•Voltage-ControlledAmpliers
•VideoSignalProcessing
•Voltage-ControlledFiltersAndOscillators
http://www.ti.com/lit/gpn/mpy634
Wide Bandwidth Analog Precision Multiplier
appendix A
A.2.1 Features
A.2.3 Description
A.2.4 Download Datasheet
Figure A.2: MPY634 - Analog Multiplier
A.2.2 Applications
MPY634
X
1
+V
S
X
2
Out
SF Z
1
Y
1
Z
2
Y
2
–V
S
–15V
+15V
Y Input
±10V FS
±12V PK
X Input
±10V FS
±12V PK
470kΩ
Optional
Summing
Input,
Z, ±10V PK
+ Z
2
(X
1
– X
2
) (Y
1
– Y
2
)
10V
50kΩ
+15V
–15V1kΩ
Optional O ffset
Trim C ircuit
V
OUT
, ±12V PK
=
MPY634
page 78 Analog System Lab Kit PRO
appendix A
The DAC7821 is a CMOS 12-bit current output
digital-to-analog converter (DAC). This device
operates from a single 2.5V to 5.5V power supply,
making it suitable for battery-powered and many
other applications. This DAC operates with a fast
parallel interface. Data read back allows the user
to read the contents of the DAC register via the DB
pins. On power-up, the internal register and latches
are lled with zeroes and the DAC outputs are at
zeroscale.TheDAC7821oersexcellent4-quadrant
multiplication characteristics, with a large signal
multiplying and width of 10MHz. The applied
external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback
resistor (RFB) provides temperature tracking and
full-scale voltage output when combined with an
externalcurrent-to-voltageprecisionamplier.The
DAC7821 is available in a 20-lead TSSOP package.
•2.5Vto5.5Vsupplyoperation
•FastParallelInterface:17nsWriteCycle
•UpdateRateof20.4MSPS
•10MHzMultiplyingBandwidth
•10Vinput
•LowGlitchEnergy:5nV-s
•ExtendedTemperatureRange:-40˚Cto+125˚C
•20-LeadTSSOPPackages
•12-BitMonotonic
•1LSBINL
•ReadbackFunction
•Power-OnResetwithBrownoutDetection
•PortableBattery-PoweredInstruments
•AnalogProcessing
•WaveformGenerators
•ProgrammableAmpliersandAttenuators
•DigitallyControlledCalibration
•ProgrammableFiltersandOscillators
•CompositeVideo
•Ultrasound
http://www.ti.com/lit/gpn/dac7821
12 Bit, Parallel, Multiplying DAC
A.3.1 Features
A.3.3 Description
A.3.4 Download Datasheet
A.3.2 Applications
DAC 7821
•Industry-StandardPinConguration
•4-QuadrantMultiplication
Figure A.3: DAC 7821 - Digital to Analog Converter
page 79
Analog System Lab Kit PRO
The TPS40200 is a exible non-synchronous
controller with a built in 200-mA driver for P-channel
FETs. The circuit operates with inputs up to 52V with
apower-savingfeaturethatturnsodrivercurrent
once the external FET has been fully turned on. This
featureextendstheexibilityofthedevice,allowing
it to operate with an input voltage up to 52V without
dissipating excessive power. The circuit operates
with voltage-mode feedback and has feed-forward
input-voltage compensation that responds instantly
to input voltage change. The internal 700mV
reference is trimmed to 1%, providing the means to
accurately control low voltages. The TPS40200 is
available in an 8-pin SOIC, and supports many of the
features of more complex controllers.
•InputVoltageRange4.5to52V
•OutputVoltage(700mVto90%VIN)
•200mAInternalP-ChannelFETDriver
•VoltageFeed-ForwardCompensation
•UndervoltageLockout
•ProgrammableFixedFrequency(35-500kHz)
Operation
•ProgrammableShortCircuitProtection
•HiccupOvercurrentFaultRecovery
•ProgrammableClosedLoopSoftStart
•IndustrialControl
•DSL/CableModems
•DistributedPowerSystems
•Scanners
•Telecom
http://www.ti.com/lit/gpn/tps40200
Wide-Input, Non-Synchronous Buck DC/DC Controller
appendix A
A.4.1 Features
A.4.3 Description
A.4.4 Download Datasheet
Figure A.4: TPS40200 - DC/DC Controller
A.4.2 Applications
TPS40200
•700mV1%ReferenceVoltage
•ExternalSynchronization
•Small8-PinSOIC(D)andQFN(DRB)Packages
page 80 Analog System Lab Kit PRO
appendix A
The TPS72xx family of low-dropout (LDO) voltage
regulators oers the benets of low-dropout
voltage, micropower operation, and miniaturized
packaging. These regulators feature extremely low
dropout voltages and quiescent currents compared to
conventionalLDOregulators.Oeredinsmall-outline
integrated-circuit (SOIC) packages and 8-terminal
thin shrink small-outline (TSSOP), the TPS72xx
series devices are ideal for cost-sensitive designs
and for designs where board space is at a premium.
A combination of new circuit design and process
innovation has enabled the usual pnp pass transistor
to be replaced by a PMOS device. Because the PMOS
pass element behaves as a ue resistor, the dropout
voltage is very low – maximum of 85 mV at 100 mA
of load current (TPS7250) – and is directly proportional
to the load current. Since the PMOS pass element
is a voltage-driven device, the quiescent current is
very low (300 mA maximum) and is stable over the
entire range of output load current (0 mA to 250 mA).
Intended for use in portable systems such as laptops
and cellular phones, the low-dropout voltage and
micropoweroperationresultinasignicantincrease
in system battery operating life.
•Availablein5-V,4.85-V,3.3-V,3.0-V,and2.5-V
Fixed-Output and Adjustable Versions
•DropoutVoltage<85mVMaxatIO=100mA
(TPS7250)
•LowQuiescentCurrent,IndependentofLoad,180
mA Typ
•8-PinSOICand8-PinTSSOPPackage
•OutputRegulatedto±2%OverFullOperating
Range for Fixed-Output Versions
•ExtremelyLowSleep-StateCurrent,0.5mAMax
•Power-Good(PG)StatusOutput
•WirelessHandsets
•SmartPhones,PDAs
•MP3Players
•ZigBeeTMNetworks
•BluetoothTMDevices
•Li-IonOperatedHandheldProducts
•WLANandOtherPCAdd-onCards
http://www.ti.com/lit/gpn/tps7250
Micropower Low-Dropout (LDO) Voltage Regulator
SENSE
PG
OUT
OUT
6
5
4
IN
IN
EN
GND
3
2
1
7
8
VI
0.1 F
PG
CSR = 1
VO
10 F
+
TPS7250
CO
250 k
A.5.1 Features
A.5.3 Description
A.5.4 Download DatasheetA.5.2 Applications
TPS7250
Figure A.5: TPS7250 -Micropower Low-Dropout (LDO) Voltage Regulator
page 81
Analog System Lab Kit PRO
•
PNP General Purpose Transistor
•
Collector-Emiter Breakdown Voltage:
V(BR)CEO=40V
•
Collector-Base Breakdown Voltage:
V(BR)CBO=40V
•
hFE: 100 @ IC=10mADC,VCE=1VDC
•
TransitionFrequency:f=100MHz@VCE=20VDC,
IC=10mADC
http://61.222.192.61/mccsemi/
up_pdf/2N3906(TO-92).pdf
http://61.222.192.61/mccsemi/
up_pdf/2N3904(TO-92).pdf
http://www.diodes.com/datasheets/BS250P.pdf
A.6.1 2N3906 Features A.6.3 2N3904 Features A.6.5 BS250 Features
A.6.2 Download Datasheet A.6.4 Download Datasheet A.6.6 Download Datasheet
Transistors
Figure A.6: 2N3906
PNP General Purpose Amplier
Figure A.7: 2N3906
NPN General Purpose Amplier
Figure A.8: BS250
P-Channel Enhancement
Mode Vertical DMOS FET
B CE G SDB CE
•
NPN General Purpose Transistor
•
Collector-Emiter Breakdown Voltage:
V(BR)CEO=40V
•
Collector-Base Breakdown Voltage:
V(BR)CBO=60V
•
hFE: 100 @ IC=10mADC,VCE=1VDC
•
TransitionFrequency:f=100MHz@VCE=20VDC,
IC=10mADC
•
P-CHANNEL ENHANCEMENT MODE VERTICAL
DMOS FET
•
Drain-Source Voltage: VDS=-45V
•
Continuous Drain Current ID=-230mA
@ TAMB=25°C
•
Gate-Source Voltage: VGS=±20V
•
Static Drain-Source on-State Resistance:
RDS(ON)=14Ω@VGS=-10V,ID=-200mA
•
Gate-Source Threshold Voltage:
VGS(TH) Min -1V; Max: -3.5V @ ID=-1mA,VDS=VGS
2N3906, 2N3904, BS250
page 82 Analog System Lab Kit PRO
1N4448 Small Signal Diode
DIODE
Figure A.9:
1N4448 Small Signal Diode
•BreakdownVoltage:VR=100V@IR=100μA
•ForwardVoltage:VF=620-720mV@IF=5mA
•ReverseLeakage:IR=25uA@VR=20V
•TotalCapacitance:CT=4pF,VR=0,f=1MHz
•ReverseRecoveryTime:tRR=4nS@IF=10mA,VR=6.0V,RL=100Ω
http://www.fairchildsemi.com/ds/1N/1N914.pdf
A.7.1 Features
A.7.2 Download Datasheet
page 83
Analog System Lab Kit PRO
Introduction to
Macromodels
Appendix B
page 84 Analog System Lab Kit PRO
appendix B
Simulation models are very useful in the design phase of an electronic system.
Before a system is actually built using real components, it is necessary to perform
a‘softwarebreadboarding’exercisethroughsimulationtoverifythefunctionality
of the system and to measure its performance. If the system consists of several
building blocks B1, B2, ..., Bn, the simulator requires a mathematical representation
of each of these building blocks in order to predict the system performance. Let us
consideraverysimpleexampleofapassivecomponentsuchasaresistor.Ohm’slaw
can be used to model the resistor if we intend to use the resistor in a DC circuit. But
if the resistor is used in a high frequency application, we may have to think about
the parasitic inductances and capacitances associated with the resistor. Similarly,
the voltage and current may not have a strict linear relation due to the dependence
oftheresistivityontemperatureofoperation,skineect,andsoon.Thisexample
illustrates that there is no single model for an electronic component. Depending
on the application and the accuracy desired, we may have to use simpler or more
complex mathematical models.
We will use another example to illustrate the above point. The MOS transistor,
which is the building block of most integrated circuits today, is introduced at the
beginning of the course on VLSI design. In a digital circuit, the transistor may be
simplymodeledasanidealswitchthatcanbeturnedonorobycontrollingthe
gatevoltage.This model issucientifweareonlyinterestedinunderstanding
the functionality of the circuit. If we wish to analyze the speed of operation of the
circuit or the power dissipation in the circuit, we will need to model the parasitics
associated with the transistors. If the same transistor is used in an analog circuit,
the model that we use in the analysis would depend on the accuracy which we want
intheanalysis.Wemayperformdierentkindsofanalysisforananalogcircuit-
DC analysis, transient analysis, and steady-state analysis. Simulators such as SPICE
requiretheusertospecifythemodelforthetransistor.Therearemanydierent
models available today for the MOS transistor, depending on the desired accuracy.
The level-1 model captures the dependence of the drain-to-source current on the
gate-to-source and drain-to-source voltages, the mobility of the majority carrier,
the width and length of the channel, and the gate oxide thickness. It also considers
non-idealities such as channel length modulation in the saturation region, and the
dependence of the threshold voltage on the source-to-bulk voltage. More complex
models for the transistor are available, which have more than 50 parameters.
Ifyouhavebuiltanoperationalamplierusingtransistors,astraight-forwardway
to analyze the performance of the OP-Amp is to come up with the micromodel of the
OPAMAP, where each transistor is simply replaced with its corresponding simulation
model. Micromodels will lead to accurate simulation, but will prove computationally
A macromodel is a mathematical convenience that helps to reduce simulation
complexity. The idea is to replace the actual circuit by something that is simpler,
but is nearly equivalent in terms of input characteristics, output characteristics, and
feedforward characteristics. Simulation of a complete system becomes much more
simple when we use macromodels for the blocks. Manufacturers of semiconductors
provide macromodels for their products to help system designers in the process of
systemcongurationselection. The macromodelscanbe loaded intoa simulator.
B.1 Micromodels
B.2 Macromodels
intensive. As the number of nodes in the circuit increases, the memory requirement
will be higher and the convergence of the simulation can take longer.
A macromodel is a way to address the problem of space-time complexity mentioned
above. In today’s electronic systems we make use of analog circuits such as
operationalampliers,dataconverters,PLL,VCO,voltageregulators,andsoon.
The goal of the system designer is not only to get a functionally correct design,
but also to optimize the cost and performance of the system. The system-level
cost and performance depend on the way the building blocks B1, B2,..., Bn have
been implemented. For example, if B1 is an OP-Amp, we may have several choices
ofoperationalampliers.TexasInstrumentsoersalargenumberofoperational
ampliers that a system designer can choose from. Refer to Table B.1. As you
willsee,therearecloseto2000typesofoperationalampliersavailable!These
are categorized into 17 dierent bins to make the selection simpler. However,
you will notice that 240 varieties are available in the category of Standard Linear
amplifers! How does a system designer select from this large collection? To
understandthis,youmustlookatthecharacteristicsofastandardlinearamplier
- these include the number of operational ampliers in a single package, the
GainBandwidth Productoftheamplier,theCMRR,Vs(min),Vs(max),and so
on. See http://tinyurl.com/ti-std-linear. The website allows you to specify these
parameters and narrow your choices.
But how does one specify the parameters for the components? The overall
system performance will depend on the way the parameters for the individual
components have been selected. For example, the gain-bandwidth product of an
operationalamplierB1willinuenceasystem-levelparametersuchasthenoise
immunity or stability. If one has n components in the system, and there are m
choices for each component, there are m·npossiblesystemcongurations.Even
if we are able to narrow the choices through some other considerations, we may
stillhavetoevaluateseveralsystemcongurations.Performingsimulationsusing
micromodels will be a painstaking and non-productive way of selecting system
congurations.
page 85
Analog System Lab Kit PRO
appendix B
As you can guess, there is no single macromodel for an IC. A number of macromodels
can be derived, based on the level of accuracy desired and the computational
complexity that one can aord. A recommended design methodology is to start
with a simple macromodel for the system components and simulate the system. A
stepwiserenementproceduremaybeadoptedandmoreaccuratemodelscanbe
used for selected components when the results are not satisfactory.
Characteristic Number of Varieties
1StandardLinearAmplier 240
2FullyDierentialAmplier 28
3 Voltage Feedback 68
4 Current Feedback 47
5 Rail to Rail 14
6 JFET/CMOS 23
7 DSL/Power Line 19
8PrecisionAmplier 641
9 Low Power 144
10 HighSpeedAmplier(≥50MHz) 182
11 Low Input Bias Current/FET Input 38
12 Low Noise 69
13 Wide Bandwidth 175
14 LowOsetVoltage 121
15 High Voltage 4
16 High Output Current 54
17 LCDGammaBuer 22
Table B.1: Operational Ampliers available from Texas Instruments
Notes on Appendix B:
page 86 Analog System Lab Kit PRO
appendix B
Notes on Appendix B:
page 87
Analog System Lab Kit PRO
Activity
Appendix C
Convert your PC/laptop into
an Oscilloscope
page 88 Analog System Lab Kit PRO
appendix C
In any analog lab, an oscilloscope is required to display
waveforms at dierent points in the circuit under
construction in order to verify circuit operation and, if
necessary, redesign the circuit. High-end oscilloscopes
are needed for measurements and characterization
in labs. Today, solutions are available to students for
converting a PC into an oscilloscope. These solutions
require some additional hardware to route the analog
signals to the PC for observation; they also require
software that provides the graphical user interface to
convert a PC display into an oscilloscope. Since most
students have access to a PC or laptop today, we have
designed the Analog System Lab such that a PC-based
oscilloscope solution can be used along with ASLK
PRO. We believe this will reduce the dependence of
the student on a full-edged lab. In this chapter, we
will review a solution for a PC-based oscilloscope. The
components on the ASLK PRO can be used to build
the interface circuit needed to convert the PC into an
oscilloscope.
Oneofthesolutionsfora“PCoscilloscope”isZelscope
[33] which works on personal computers running
Microsoft Windows XP. The hardware requirements for
the PC are modest (300+ MHz clock, 64+ MB memory).
It uses the sound card in the PC for converting the
analogsignalsintodigitalform.TheZelscopesoftware,
which requires about 1 MB space, is capable of using
the digitized signal to display waveforms as well as
the frequency spectrum of the analog signal. At the
‘line in’ jack of the sound card, the typical voltage
should be about 1 volt AC; hence it is essential to
protect the sound card from over voltages. A buer
ampliercircuitisrequiredtoprotectthesoundcard
from overvoltages. Two copies of such a circuit are
needed to implement a dual-channel oscilloscope. The
buerampliercircuitisshowninFigureC.1andhas
been borrowed from [32].
C.1 Introduction
Limitations
BNC
C1
0.1uF
R1
1M
C2
20pF
R2
47k 1/2W
C3
100pF
D2
1N914
D3
1N914
R3
4.7k
-12V
D1
1N914
+12V
TI082
RS
27k
R4
3k
R6
100k
RCA
IVoutl<12V
Zin=1M
IVinl<150V
S1
•Not possible to display DC voltages (due to input
capacitor of sound card blocks DC)
•Lowfrequencyrange(10Hz-20kHz)
•Measurementisnotveryaccurate
Figure C.1:
Buer circuit
needed to
interface an
Analog Signal
to Oscilloscope
page 89
Analog System Lab Kit PRO
Connection
diagrams
Appendix D
page 90 Analog System Lab Kit PRO
appendix D
Figure D.1: OP-Amp 1A connected in Inverting Conguration Figure D.2: OP-Amp 1B connected in inverting conguration
VCC+10
VCC-10
3
2
1
OPAMP1A
OP1
HD23
OP1A OUT
HD9
GND
HD10
+10V
HD11
OP1A IN-
HD12
-10V
HD13
R11
HD14
C11
HD15
R12
HD16
C12
HD17
R13
HD18
C13
HD19
R14
HD20
C14
HD21
R15
R11
1K
R12
1K
R13
2K2
R14
4K7
R15
10K
C11
0.01uF
C12
0.1uF
C13
0.1uF
C14
1uF
C20
0.1uF
C10
0.1uF
VCC+10
VCC-10
5
6
7
OPAMP1B
OP1
HD26
OP1B OUT
HD22
GND
HD119
+10V
HD24
OP1B IN-
HD181
-10V
HD1
R21
HD2
C21
HD3
R22
HD4
C22
HD5
R23
HD6
C23
HD7
R24
HD8
C24
HD25
R25
R21
1K
R22
1K
R23
2K2
R24
4K7
R25
10K
C21
0.01uF
C22
0.1uF
C23
0.1uF
C24
1uF
VCC+10
VCC-10
3
2
1
OPAMP1A
OP1
HD23
OP1A OUT
HD9
GND
HD10
+10V
HD11
OP1A IN-
HD12
-10V
HD13
R11
HD14
C11
HD15
R12
HD16
C12
HD17
R13
HD18
C13
HD19
R14
HD20
C14
HD21
R15
R11
1K
R12
1K
R13
2K2
R14
4K7
R15
10K
C11
0.01uF
C12
0.1uF
C13
0.1uF
C14
1uF
C20
0.1uF
C10
0.1uF
VCC+10
VCC-10
5
6
7
OPAMP1B
OP1
HD26
OP1B OUT
HD22
GND
HD119
+10V
HD24
OP1B IN-
HD181
-10V
HD1
R21
HD2
C21
HD3
R22
HD4
C22
HD5
R23
HD6
C23
HD7
R24
HD8
C24
HD25
R25
R21
1K
R22
1K
R23
2K2
R24
4K7
R25
10K
C21
0.01uF
C22
0.1uF
C23
0.1uF
C24
1uF
OP AMP TYPE I - A - INVERTING OP AMP TYPE I - B - INVERTING
page 91
Analog System Lab Kit PRO
Figure D.3: OP-Amp 2A can be used in both inverting
and non-inverting conguration
Figure D.4: OP-Amp 2B can be used in both inverting
and non-inverting conguration
VCC+10
VCC-10
3
2
1
OPAMP2A
OP2
HD52
OP2A OUT
HD36
OP2A IN+
HD37
+10V
HD38
OP2A IN-
HD39
-10V
HD40
R31
HD46
C31
HD42
R32
HD47
C32
HD44
R33
HD43
C33
HD45
R34
HD41
R35
R31
1K
R32
4K7
R33
10K
R34
2K2
R35
1K
C31
1uF
C32
0.1uF
C33
0.01uF
C40
0.1uF
C30
0.1uF
HD35
R36
HD33
C34
HD31
R37
HD30
C35
HD32
R38
HD34
C36
R36
1K
R37
10K
R38
2K2
C34
1uF
C35
0.1uF
C36
0.1uF
HD54
GND
VCC+10
VCC-10
5
6
7
OPAMP2B
OP2
HD62
OP2B OUT
HD51
OP2B IN+
HD183
+10V
HD53
OP2B IN-
HD180
-10V
HD55
R41
HD58
C41
HD56
R42
HD66
C42
HD57
R43
HD64
C43
HD65
R44
HD63
R45
R41
1K
R42
4K7
R43
10K
R44
2K2
R45
1K
C41
1uF
C42
0.1uF
C43
0.01uF
HD61
R46
HD60
C44
HD59
R47
HD48
C45
HD49
R48
HD50
C46
R46
1K
R47
10K
R48
2K2
C44
1uF
C45
0.1uF
C46
0.1uF
VCC+10
VCC-10
3
2
1
OPAMP2A
OP2
HD52
OP2A OUT
HD36
OP2A IN+
HD37
+10V
HD38
OP2A IN-
HD39
-10V
HD40
R31
HD46
C31
HD42
R32
HD47
C32
HD44
R33
HD43
C33
HD45
R34
HD41
R35
R31
1K
R32
4K7
R33
10K
R34
2K2
R35
1K
C31
1uF
C32
0.1uF
C33
0.01uF
C40
0.1uF
C30
0.1uF
HD35
R36
HD33
C34
HD31
R37
HD30
C35
HD32
R38
HD34
C36
R36
1K
R37
10K
R38
2K2
C34
1uF
C35
0.1uF
C36
0.1uF
HD54
GND
VCC+10
VCC-10
5
6
7
OPAMP2B
OP2
HD62
OP2B OUT
HD51
OP2B IN+
HD183
+10V
HD53
OP2B IN-
HD180
-10V
HD55
R41
HD58
C41
HD56
R42
HD66
C42
HD57
R43
HD64
C43
HD65
R44
HD63
R45
R41
1K
R42
4K7
R43
10K
R44
2K2
R45
1K
C41
1uF
C42
0.1uF
C43
0.01uF
HD61
R46
HD60
C44
HD59
R47
HD48
C45
HD49
R48
HD50
C46
R46
1K
R47
10K
R48
2K2
C44
1uF
C45
0.1uF
C46
0.1uF
appendix D
OP AMP TYPE II - A - FULL OP AMP TYPE II - B - FULL
page 92 Analog System Lab Kit PRO
appendix D
Figure D.7: Connections for analog multiplier MPY634 - SET I
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U1
HD80
Y2
HD81
Y1
HD82
SF
HD83
X2
HD84
X1
HD87
Z2
HD88
Z1
HD89
OUT
VCC-10
VCC+10VCC+10
VCC-10
C71
100nF
C72
100nF
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U2
HD91
Y2
HD92
Y1
HD94
SF
HD95
X2
HD96
X1
HD100
Z2
HD101
Z1
HD103
OUT
VCC-10
VCC+10VCC+10
VCC-10
C81
100nF
C82
100nF
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U3
HD98
Y2
HD99
Y1
HD102
SF
HD104
X2
HD105
X1
HD109
Z2
HD110
Z1
HD111
OUT
VCC-10
VCC+10VCC+10
VCC-10
C91
100nF
C92
100nF
HD90
+10V
HD106
+10V
HD112
+10V
HD85
-10V
HD97
-10V
HD107
-10V
HD86
GND
HD93
GND
HD108
GND
OP AMP TYPE III - A - BASIC
OP AMP TYPE III - B - BASIC
ANALOG MULTIPLIER - SET I
VCC+10
VCC-10
3
2
1
OPAMP3A
OP3
HD72
OP3A OUT
HD69
OP3A IN+
HD67
+10V
HD70
OP3A IN-
HD68
-10V
C58
0.1uF
C59
0.1uF
VCC+10
VCC-10
5
6
7
OPAMP3B
OP3
HD74
OP3B OUT
HD71
OP3B IN+
HD179
+10V
HD73
OP3B IN-
HD182
-10V
HD75
GND
VCC+10
VCC-10
3
2
1
OPAMP3A
OP3
HD72
OP3A OUT
HD69
OP3A IN+
HD67
+10V
HD70
OP3A IN-
HD68
-10V
C58
0.1uF
C59
0.1uF
VCC+10
VCC-10
5
6
7
OPAMP3B
OP3
HD74
OP3B OUT
HD71
OP3B IN+
HD179
+10V
HD73
OP3B IN-
HD182
-10V
HD75
GND
Figure D.6: OP-Amp 3B can be used in unity gain conguration
or any other custom conguration
Figure D.5: OP-Amp 3A can be used in unity gain conguration
or any other custom conguration
page 93
Analog System Lab Kit PRO
Figure D.8: Connections for analog multiplier MPY634 - SET II Figure D.9: Connections for analog multiplier MPY634 - SET III
appendix D
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U1
HD80
Y2
HD81
Y1
HD82
SF
HD83
X2
HD84
X1
HD87
Z2
HD88
Z1
HD89
OUT
VCC-10
VCC+10VCC+10
VCC-10
C71
100nF
C72
100nF
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U2
HD91
Y2
HD92
Y1
HD94
SF
HD95
X2
HD96
X1
HD100
Z2
HD101
Z1
HD103
OUT
VCC-10
VCC+10VCC+10
VCC-10
C81
100nF
C82
100nF
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U3
HD98
Y2
HD99
Y1
HD102
SF
HD104
X2
HD105
X1
HD109
Z2
HD110
Z1
HD111
OUT
VCC-10
VCC+10VCC+10
VCC-10
C91
100nF
C92
100nF
HD90
+10V
HD106
+10V
HD112
+10V
HD85
-10V
HD97
-10V
HD107
-10V
HD86
GND
HD93
GND
HD108
GND
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U1
HD80
Y2
HD81
Y1
HD82
SF
HD83
X2
HD84
X1
HD87
Z2
HD88
Z1
HD89
OUT
VCC-10
VCC+10VCC+10
VCC-10
C71
100nF
C72
100nF
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U2
HD91
Y2
HD92
Y1
HD94
SF
HD95
X2
HD96
X1
HD100
Z2
HD101
Z1
HD103
OUT
VCC-10
VCC+10VCC+10
VCC-10
C81
100nF
C82
100nF
X1
1
X2
2
NC
3
SF
4
NC
5
Y1
6
Y2
7
+VS 14
NC 13
OUT 12
Z1 11
Z2 10
NC 9
-VS 8
MPY634
X1
X2
NC
Y2
Y1
NC
SF
NC
-VS
+VS
NC
OUT
Z1
Z2
U3
HD98
Y2
HD99
Y1
HD102
SF
HD104
X2
HD105
X1
HD109
Z2
HD110
Z1
HD111
OUT
VCC-10
VCC+10VCC+10
VCC-10
C91
100nF
C92
100nF
HD90
+10V
HD106
+10V
HD112
+10V
HD85
-10V
HD97
-10V
HD107
-10V
HD86
GND
HD93
GND
HD108
GND
ANALOG MULTIPLIER - SET II ANALOG MULTIPLIER - SET III
page 94 Analog System Lab Kit PRO
appendix D
Figure D.10: connections for analog-to-digital converter DAC7821 - DAC I
1
2
3
4
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
12
DAC7821
IOUT1
IOUT2
GND
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB0
DB1
DB2
DB3
DB4
RFB
VREF
VDD
R/W
CS
DA1
1
2
3
4
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
12
DAC7821
IOUT1
IOUT2
GND
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB0
DB1
DB2
DB3
DB4
RFB
VREF
VDD
R/W
CS
DA2
12345678
+
_
9 10 11 12
SW1
DBA0
DBA1
DBA2
DBA3
DBA4DBA5
DBA6
DBA7
DBA8
DBA9
DBA10
DBA11
CS A
CS A
12345678
+
_
9 10 11 12
SW2
CS B
DBB0
DBB1
DBB2
DBB3
DBB4DBB5
DBB6
DBB7
DBB8
DBB9
DBB10
DBB11
T1
R51
10K
VCC+5
HD144 HD145
DBA0
DBA1
DBA2
DBA3
DBA4
DBA5
DBA6
DBA7
DBA8
DBA9
DBA10
DBA11
DBB0
DBB1
DBB2
DBB3
DBB4
DBB5
DBB6
DBB7
DBB8
DBB9
DBB10
DBB11
R53
220R
R52
220R
VCC+5
R63
220R
R62
220R
VCC+5
R54
10k
DBA0
DBA1
DBA2
DBA3
DBA4
DBA5
DBA6
DBA7
DBA8
DBA9
DBA10
DBA11
DBB0
DBB1
DBB2
DBB3
DBB4
DBB5
DBB6
DBB7
DBB8
DBB9
DBB10
DBB11
HD137
CS
C51
100nF
CS B
T2
R61
10K
VCC+5
HD138
CS
C61
100nF
VCC+10
VCC-10
HD176
+10V
HD135
GND
HD175
-10V
VCC+10
VCC-10
HD178
+10V
HD136
GND
HD177
-10V
HD184
R/W
HD151
IOUT2
HD153
IOUT1
HD169
VREF
HD171
RFB
HD152
IOUT2
HD154
IOUT1
HD170
VREF
HD172
RFB
C52
100nF
VCC+5 VCC+5
R64
10k
HD185
R/W
C62
100nF
VCC+5VCC+5
JP3
VCC+5
OUT
VOUT
LDO
DC/DC
DAC I
page 95
Analog System Lab Kit PRO
appendix D
1
2
3
4
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
12
DAC7821
IOUT1
IOUT2
GND
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB0
DB1
DB2
DB3
DB4
RFB
VREF
VDD
R/W
CS
DA1
1
2
3
4
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
12
DAC7821
IOUT1
IOUT2
GND
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB0
DB1
DB2
DB3
DB4
RFB
VREF
VDD
R/W
CS
DA2
12345678
+
_
9 10 11 12
SW1
DBA0
DBA1
DBA2
DBA3
DBA4DBA5
DBA6
DBA7
DBA8
DBA9
DBA10
DBA11
CS A
CS A
12345678
+
_
9 10 11 12
SW2
CS B
DBB0
DBB1
DBB2
DBB3
DBB4DBB5
DBB6
DBB7
DBB8
DBB9
DBB10
DBB11
T1
R51
10K
VCC+5
HD144 HD145
DBA0
DBA1
DBA2
DBA3
DBA4
DBA5
DBA6
DBA7
DBA8
DBA9
DBA10
DBA11
DBB0
DBB1
DBB2
DBB3
DBB4
DBB5
DBB6
DBB7
DBB8
DBB9
DBB10
DBB11
R53
220R
R52
220R
VCC+5
R63
220R
R62
220R
VCC+5
R54
10k
DBA0
DBA1
DBA2
DBA3
DBA4
DBA5
DBA6
DBA7
DBA8
DBA9
DBA10
DBA11
DBB0
DBB1
DBB2
DBB3
DBB4
DBB5
DBB6
DBB7
DBB8
DBB9
DBB10
DBB11
HD137
CS
C51
100nF
CS B
T2
R61
10K
VCC+5
HD138
CS
C61
100nF
VCC+10
VCC-10
HD176
+10V
HD135
GND
HD175
-10V
VCC+10
VCC-10
HD178
+10V
HD136
GND
HD177
-10V
HD184
R/W
HD151
IOUT2
HD153
IOUT1
HD169
VREF
HD171
RFB
HD152
IOUT2
HD154
IOUT1
HD170
VREF
HD172
RFB
C52
100nF
VCC+5 VCC+5
R64
10k
HD185
R/W
C62
100nF
VCC+5VCC+5
JP3
VCC+5
OUT
VOUT
LDO
DC/DC
Figure D.11: connections for analog-to-digital converter DAC7821 - DAC II
DAC II
page 96 Analog System Lab Kit PRO
appendix D
Figure D.12: Connections for TPS40200 Evaluation step-down DC/DC converter
RC
1
SS
2
COMP
3
FB
4GND5
DRV 6
ISNS 7
VDD 8
TPS40200
RC
SS
COMP
FB
VDD
ISNS
DRV
GND
U4
4
3
6
5
2
1
Q101
FDC5614P
VIN 6 – 15V
VOUT 3.3V or 5V
VIN
VOUT
GATE
SRC
DRAIN
RC
SS
COMP
FB
ISNS
DRV
DC/DC IN
HD142
Vin
HD143
VOUT
R3
4K7
C202
68pF
C203
220nF
C204
220nF C205
470pF
C206
4.7nF
C207
33pF
C208
100nF
C211
10uF
C212
10uF
C213
470pF
C214
470nF
C201
220uF
C209
330uF
C210
330uF
L201
33uH
R201
100K
R202
0.03
R203
1K
R204
0E
R205
100K
R206
25.5E
R207
100K
R208
49.9
R209
27K4
R210
1M
R211
41K2
HD120
TP2
HD121
TP3
HD122
TP1
HD123
TP8
HD124
TP6
HD125
TP9
HD126
TP4
HD127
TP7
HD128
TP5
LD3
JP9
D201
MBRS340
CN6
VOUT
CN5
VIN
JP8
VCC+10
@ 0.125 – 2.5A
3.3V
5V
DC/DC CONVERTER
page 97
Analog System Lab Kit PRO
appendix D
Figure D.15: Bipolar Junction Transistor socketFigure D.14: MOSFET socket
VIN 5.5 -10 V VOUT 5
V
GND
3
IN 5
IN 6
EN
4
OUT 7
OUT 8
SENSE
1
PG
2
TPS7250
SENSE
PG
GND
EN
OUT
OUT
IN
IN
IC1
IN
OUT
ENABLE
REG IN
HD117
VIN
HD118
VOUT
HD116
GND
R4
4K7
OUT
CN3
VIN
CN4
VOUT
JP6
VCC+10
R101
247K
C101
1uF
C102
100nF
C103
10uF
JP7
GND
GND
LD4
@250mA
ON
OFF
HD140B
BASE
HD141B
COLLECTOR
HD139B
EMITTER
1
2
3
TRANSISTOR SOCKET
E C
B
HD114B
GATE
HD115B
DRAIN
HD113B
SOURCE
1
2
3
MOSFET SOCKET
S D
G
HD140B
BASE
HD141B
COLLECTOR
HD139B
EMITTER
1
2
3
TRANSISTOR SOCKET
E C
B
HD114B
GATE
HD115B
DRAIN
HD113B
SOURCE
1
2
3
MOSFET SOCKET
S D
G
LDO REGULATOR
Figure D.13: Connections for TP7250 low-dropout linear voltage regulator
TRANSISTOR SOCKET (MOSFET) TRANSISTOR SOCKET (BJT)
page 98 Analog System Lab Kit PRO
appendix D
D1
D2
HD76B
D2A
HD77B
D1A
HD78B
D2K
HD79B
D1K
Figure D.18: Main power supply
Figure D.16: Diode sockets Figure D.17: Trimmer-potentiometers
P1
1K
VCC+10
P2
1K
VCC-10
HD129
GND
HD130
GND
HD131
+10V
HD132
S1
HD133
-10V
HD134
S2
DIODES
POWER SUPPLY
TRIMMERS
GENERAL PURPOSE AREA
HD29
+10V
HD27
-10V
HD28
GND
R1
6K8
R2
6K8
CN1
+10V
CN2
-10V
VCC+10
VCC-10
VCC+10
VCC-10
LD1
LD2
VCC-10
VCC+10
Figure D.19: General purpose area (2.54mm / 100mills pad spacing)
page 99
Analog System Lab Kit PRO
Bibliography
List of references and related articles for
further reading
page 100 Analog System Lab Kit PRO
Bibliography 1 of 2
[01] ADCPro (TM) - Analog to Digital Conversion Evaluation Software. Free. Available from http://focus.ti.com/docs/toolsw/folders/print/adcpro.html
[02] F. Archibald. Automatic Level Controller for Speech Signals Using PID Controllers. Application Notes from Texas Instruments.
Available from http://focus.ti.com/lit/wp/spraaj4/spraaj4.pdf
[03] High-Performance Analog. Available from www.ti.com/analog
[04] Wide Bandwidth Precision Analog Multiplier MPY634, Burr Brown Products from Texas Instruments,
Available from http://focus.ti.com/lit/ds/sbfs017a/sbfs017a.pdf
[05] B.CarterandT.Brown.HandbookOfOperationalAmplierApplications.TexasInstrumentsApplicationReport.2001.
Available from http://focus.ti.com/lit/an/sboa092a/sboa092a.pdf
[06] B.Carter.OpAmpandComparators-Don’tConfuseThem!TexasInstrumentsApplicationReport,2001.
Available from http://tinyurl.com/carteropamp-comp
[07] B. Carter. Filter Design in Thirty Seconds. Application Report from Texas Instruments. Downloadable from http://focus.ti.com/lit/an/sloa093/sloa093.pdf
[08] B. Carter and R. Mancini. OPAMPS For Everyone. Elsevier Science Publishers, 2009.
[09] FilterPro (TM) - Active Filter Design Application. Free software. Available from http://tinyurl.com/lterpro-download
[10] Thomas Kuehl and Faisal Ali. Active Filter Synthesis Made Easy With FilterPro V3.0. Tutorial presented in TI Technology Days 2010 (May), USA.
Available from http://www.ti.com/ww/en/techdays/2010/index.shtml.
[11] J. Molina. DESIGN A 60Hz NOTCH FILTER WITH THE UAF42. Application note from Burr-Brown (Texas Instruments), 2000.
Available from http://focus.ti.com/lit/an/sbfa012/sbfa012.pdf
[12] J. Molina. DIGITALLY PROGRAMMABLE, TIME-CONTINUOUS ACTIVE FILTER, 2000.
Application note from Burr-Brown (Texas Instruments), http://focus.ti.com/lit/an/sbfa005/sbfa005.pdf
[13] George S. Moschytz. From Printed Circuit Boards to Systems-on-a-chip. IEEE Circuits and Systems magazine, Vol 10, Number 2, 2010.
[14] Phase-locked loop. Wikipedia entry. http://en.wikipedia.org/wiki/Phaselocked loop
[15] R.Palmer.DesignConsiderationsforClass-DAudioAmpliers.ApplicationNotefromTexasInstruments.
Available from http://focus.ti.com/lit/an/sloa031/sloa031.pdf
[16] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. OPAmp in Negative Feedback.
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec7 and http://tinyurl.com/krkrao-nptel-lec8
page 101
Analog System Lab Kit PRO
Bibliography 2 of 2
[17] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Frequency Compensation in Negative Feedback.
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec16 and http://tinyurl.com/krkraonptel-lec17
[18] K.R.K.Rao.ElectronicsforAnalogSignalProcessing-PartII.InstrumentationAmplier.
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec11
[19] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Active Filters.
Recorded lecture available through NPTEL. http://tinyurl.com/krkraonptel-lec12
[20] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Positive Feedback (Regenerative).
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec9
[21] K.R.K. Rao. Analog ICs. Self-Tuned Filter. Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-ic-lec23
[22] K.R.K. Rao. Analog ICs. Phase Locked Loop. Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptelic-lec24,
http://tinyurl.com/krkrao-nptel-ic-lec25, http://tinyurl.com/krkraonptel-ic-lec26, and http:// tinyurl.com/krkrao-nptel-ic-lec27
[23] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Voltage Regulators. Recorded lecture available through NPTEL.
http://tinyurl.com/krkrao-nptel-26, http://tinyurl.com/krkrao-nptel-27, and http:// tinyurl.com/krkrao-nptel-28
[24] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Converters. Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-28,
[25] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. AGC/AVC. http://tinyurl.com/krkrao-nptel-33, http://tinyurl.com/krkrao-nptel-34,
http://tinyurl.com/krkrao-nptel-35, http://tinyurl.com/krkrao-nptel-36
[26] K.R.K.Rao. Analog Ics Voltage Controlled Oscillator. Recorded lectures available from links: http://tinyurl.com/krkrao-vco-1, http://tinyurl.com/krkrao-vco-2
[27] Thomas Kugesstadt. Active Filter Design Techniques. Texas Instruments. Available from http://focus.ti.com/lit/ml/sloa088/sloa088.pdf
[28] Oscilloscope Solutions from Texas Instruments - Available from http://focus.ti.com/docs/solution/folders/ print/437.html
[29] PC Based Test and Instrumentation. Available from http://www.pctestinstruments.com/
[30] SwitcherPro (TM) - Switching Power Supply Design Tool. http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html
[31] Texas Intruments Analog eLAB - SPICE Model Resources. Macromodels for TI analog ICs are downloadable from http://tinyurl.com/ti-macromodels
[32] How to use PC as Oscilloscope. Available from http://www.trickswindows.com
[33] Zelscope:OscilloscopeandSpectrumAnalyzer.Availablefromhttp://www.zelscope.com
page 102 Analog System Lab Kit PRO
These materials are for academic and
training usage: for teaching and learning
purposes only. The materials are not
warranted in any way for production use.
Copyright © Texas Instruments 2012.
MANUAL
MANUAL
K.R.K. Rao and C.P. Ravikumar
Zoran Ristić
Miodrag Veljković
Danijela Krajnović
Aleksandar Nikolić
MikroElektronika Ltd.
www.mikroe.com
MANUAL
Analog
System
Lab Kit PRO
Analog
System
Lab Kit PRO
Authors
Editor in Chief
Assistant Editor
Cover Design
Graphic Design/DTP
Publisher
June 2012.
Special Thanks to
Harmanpreet Singh
for his help in performing the additional experiments
(Experiments 11-14) included in the new release of ASLK Pro.
Analog System Lab Kit PRO
Analog System Lab Kit PRO Manual
ver. 1.03b
0 100000 019382

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