ARM Architecture Reference Manual ARMv7 A And R Edition
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- ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
- Contents
- Preface
- Part A: Application Level Architecture
- A1: Introduction to the ARM Architecture
- A2: Application Level Programmers’ Model
- A2.1 About the Application level programmers’ model
- A2.2 ARM core data types and arithmetic
- A2.3 ARM core registers
- A2.4 The Application Program Status Register (APSR)
- A2.5 Execution state registers
- A2.6 Advanced SIMD and Floating-point Extensions
- A2.7 Floating-point data types and arithmetic
- A2.7.1 ARM standard floating-point input and output values
- A2.7.2 Advanced SIMD and Floating-point single-precision format
- A2.7.3 Floating-point double-precision format
- A2.7.4 Advanced SIMD and Floating-point half-precision formats
- A2.7.5 Flush-to-zero
- A2.7.6 NaN handling and the Default NaN
- A2.7.7 Floating-point exceptions
- A2.7.8 Pseudocode details of floating-point operations
- Generation of specific floating-point values
- Floating-point negation and absolute value
- Floating-point value unpacking
- Floating-point exception and NaN handling
- Floating-point rounding
- Selection of ARM standard floating-point arithmetic
- Floating-point comparisons
- Floating-point maximum and minimum
- Floating-point addition and subtraction
- Floating-point multiplication and division
- Floating-point fused multiply-add
- Floating-point reciprocal estimate and step
- Floating-point square root
- Floating-point reciprocal square root estimate and step
- Floating-point conversions
- A2.8 Polynomial arithmetic over {0, 1}
- A2.9 Coprocessor support
- A2.10 Thumb Execution Environment
- A2.11 Jazelle direct bytecode execution support
- A2.12 Exceptions, debug events and checks
- A3: Application Level Memory Model
- A3.1 Address space
- A3.2 Alignment support
- A3.3 Endian support
- A3.4 Synchronization and semaphores
- A3.4.1 Exclusive access instructions and Non-shareable memory regions
- A3.4.2 Exclusive access instructions and Shareable memory regions
- A3.4.3 Tagging and the size of the tagged memory block
- A3.4.4 Context switch support
- A3.4.5 Load-Exclusive and Store-Exclusive usage restrictions
- A3.4.6 Semaphores
- A3.4.7 Synchronization primitives and the memory order model
- A3.4.8 Use of WFE and SEV instructions by spin-locks
- A3.5 Memory types and attributes and the memory order model
- A3.6 Access rights
- A3.7 Virtual and physical addressing
- A3.8 Memory access order
- A3.9 Caches and memory hierarchy
- A4: The Instruction Sets
- A4.1 About the instruction sets
- A4.2 Unified Assembler Language
- A4.3 Branch instructions
- A4.4 Data-processing instructions
- A4.4.1 Standard data-processing instructions
- A4.4.2 Shift instructions
- A4.4.3 Multiply instructions
- A4.4.4 Saturating instructions
- A4.4.5 Saturating addition and subtraction instructions
- A4.4.6 Packing and unpacking instructions
- A4.4.7 Parallel addition and subtraction instructions
- A4.4.8 Divide instructions
- A4.4.9 Miscellaneous data-processing instructions
- A4.5 Status register access instructions
- A4.6 Load/store instructions
- A4.7 Load/store multiple instructions
- A4.8 Miscellaneous instructions
- A4.9 Exception-generating and exception-handling instructions
- A4.10 Coprocessor instructions
- A4.11 Advanced SIMD and Floating-point load/store instructions
- A4.12 Advanced SIMD and Floating-point register transfer instructions
- A4.13 Advanced SIMD data-processing instructions
- A4.13.1 Advanced SIMD parallel addition and subtraction
- A4.13.2 Bitwise Advanced SIMD data-processing instructions
- A4.13.3 Advanced SIMD comparison instructions
- A4.13.4 Advanced SIMD shift instructions
- A4.13.5 Advanced SIMD multiply instructions
- A4.13.6 Miscellaneous Advanced SIMD data-processing instructions
- A4.14 Floating-point data-processing instructions
- A5: ARM Instruction Set Encoding
- A5.1 ARM instruction set encoding
- A5.2 Data-processing and miscellaneous instructions
- A5.2.1 Data-processing (register)
- A5.2.2 Data-processing (register-shifted register)
- A5.2.3 Data-processing (immediate)
- A5.2.4 Modified immediate constants in ARM instructions
- A5.2.5 Multiply and multiply accumulate
- A5.2.6 Saturating addition and subtraction
- A5.2.7 Halfword multiply and multiply accumulate
- A5.2.8 Extra load/store instructions
- A5.2.9 Extra load/store instructions, unprivileged
- A5.2.10 Synchronization primitives
- A5.2.11 MSR (immediate), and hints
- A5.2.12 Miscellaneous instructions
- A5.3 Load/store word and unsigned byte
- A5.4 Media instructions
- A5.5 Branch, branch with link, and block data transfer
- A5.6 Coprocessor instructions, and Supervisor Call
- A5.7 Unconditional instructions
- A6: Thumb Instruction Set Encoding
- A6.1 Thumb instruction set encoding
- A6.2 16-bit Thumb instruction encoding
- A6.3 32-bit Thumb instruction encoding
- A6.3.1 Data-processing (modified immediate)
- A6.3.2 Modified immediate constants in Thumb instructions
- A6.3.3 Data-processing (plain binary immediate)
- A6.3.4 Branches and miscellaneous control
- A6.3.5 Load/store multiple
- A6.3.6 Load/store dual, load/store exclusive, table branch
- A6.3.7 Load word
- A6.3.8 Load halfword, memory hints
- A6.3.9 Load byte, memory hints
- A6.3.10 Store single data item
- A6.3.11 Data-processing (shifted register)
- A6.3.12 Data-processing (register)
- A6.3.13 Parallel addition and subtraction, signed
- A6.3.14 Parallel addition and subtraction, unsigned
- A6.3.15 Miscellaneous operations
- A6.3.16 Multiply, multiply accumulate, and absolute difference
- A6.3.17 Long multiply, long multiply accumulate, and divide
- A6.3.18 Coprocessor, Advanced SIMD, and Floating-point instructions
- A7: Advanced SIMD and Floating-point Instruction Encoding
- A7.1 Overview
- A7.2 Advanced SIMD and Floating-point instruction syntax
- A7.3 Register encoding
- A7.4 Advanced SIMD data-processing instructions
- A7.5 Floating-point data-processing instructions
- A7.6 Extension register load/store instructions
- A7.7 Advanced SIMD element or structure load/store instructions
- A7.8 8, 16, and 32-bit transfer between ARM core and extension registers
- A7.9 64-bit transfers between ARM core and extension registers
- A8: Instruction Details
- A8.1 Format of instruction descriptions
- A8.2 Standard assembler syntax fields
- A8.3 Conditional execution
- A8.4 Shifts applied to a register
- A8.5 Memory accesses
- A8.6 Encoding of lists of ARM core registers
- A8.7 Additional pseudocode support for instruction descriptions
- A8.8 Alphabetical list of instructions
- A8.8.1 ADC (immediate)
- A8.8.2 ADC (register)
- A8.8.3 ADC (register-shifted register)
- A8.8.4 ADD (immediate, Thumb)
- A8.8.5 ADD (immediate, ARM)
- A8.8.6 ADD (register, Thumb)
- A8.8.7 ADD (register, ARM)
- A8.8.8 ADD (register-shifted register)
- A8.8.9 ADD (SP plus immediate)
- A8.8.10 ADD (SP plus register, Thumb)
- A8.8.11 ADD (SP plus register, ARM)
- A8.8.12 ADR
- A8.8.13 AND (immediate)
- A8.8.14 AND (register)
- A8.8.15 AND (register-shifted register)
- A8.8.16 ASR (immediate)
- A8.8.17 ASR (register)
- A8.8.18 B
- A8.8.19 BFC
- A8.8.20 BFI
- A8.8.21 BIC (immediate)
- A8.8.22 BIC (register)
- A8.8.23 BIC (register-shifted register)
- A8.8.24 BKPT
- A8.8.25 BL, BLX (immediate)
- A8.8.26 BLX (register)
- A8.8.27 BX
- A8.8.28 BXJ
- A8.8.29 CBNZ, CBZ
- A8.8.30 CDP, CDP2
- A8.8.31 CHKA
- A8.8.32 CLREX
- A8.8.33 CLZ
- A8.8.34 CMN (immediate)
- A8.8.35 CMN (register)
- A8.8.36 CMN (register-shifted register)
- A8.8.37 CMP (immediate)
- A8.8.38 CMP (register)
- A8.8.39 CMP (register-shifted register)
- A8.8.40 CPS
- A8.8.41 CPY
- A8.8.42 DBG
- A8.8.43 DMB
- A8.8.44 DSB
- A8.8.45 ENTERX
- A8.8.46 EOR (immediate)
- A8.8.47 EOR (register)
- A8.8.48 EOR (register-shifted register)
- A8.8.49 ERET
- A8.8.50 F*, former Floating-point instruction mnemonics
- A8.8.51 HB, HBL, HBLP, HBP
- A8.8.52 HVC
- A8.8.53 ISB
- A8.8.54 IT
- A8.8.55 LDC, LDC2 (immediate)
- A8.8.56 LDC, LDC2 (literal)
- A8.8.57 LDM/LDMIA/LDMFD (Thumb)
- A8.8.58 LDM/LDMIA/LDMFD (ARM)
- A8.8.59 LDMDA/LDMFA
- A8.8.60 LDMDB/LDMEA
- A8.8.61 LDMIB/LDMED
- A8.8.62 LDR (immediate, Thumb)
- A8.8.63 LDR (immediate, ARM)
- A8.8.64 LDR (literal)
- A8.8.65 LDR (register, Thumb)
- A8.8.66 LDR (register, ARM)
- A8.8.67 LDRB (immediate, Thumb)
- A8.8.68 LDRB (immediate, ARM)
- A8.8.69 LDRB (literal)
- A8.8.70 LDRB (register)
- A8.8.71 LDRBT
- A8.8.72 LDRD (immediate)
- A8.8.73 LDRD (literal)
- A8.8.74 LDRD (register)
- A8.8.75 LDREX
- A8.8.76 LDREXB
- A8.8.77 LDREXD
- A8.8.78 LDREXH
- A8.8.79 LDRH (immediate, Thumb)
- A8.8.80 LDRH (immediate, ARM)
- A8.8.81 LDRH (literal)
- A8.8.82 LDRH (register)
- A8.8.83 LDRHT
- A8.8.84 LDRSB (immediate)
- A8.8.85 LDRSB (literal)
- A8.8.86 LDRSB (register)
- A8.8.87 LDRSBT
- A8.8.88 LDRSH (immediate)
- A8.8.89 LDRSH (literal)
- A8.8.90 LDRSH (register)
- A8.8.91 LDRSHT
- A8.8.92 LDRT
- A8.8.93 LEAVEX
- A8.8.94 LSL (immediate)
- A8.8.95 LSL (register)
- A8.8.96 LSR (immediate)
- A8.8.97 LSR (register)
- A8.8.98 MCR, MCR2
- A8.8.99 MCRR, MCRR2
- A8.8.100 MLA
- A8.8.101 MLS
- A8.8.102 MOV (immediate)
- A8.8.103 MOV (register, Thumb)
- A8.8.104 MOV (register, ARM)
- A8.8.105 MOV (shifted register)
- A8.8.106 MOVT
- A8.8.107 MRC, MRC2
- A8.8.108 MRRC, MRRC2
- A8.8.109 MRS
- A8.8.110 MRS (Banked register)
- A8.8.111 MSR (immediate)
- A8.8.112 MSR (register)
- A8.8.113 MSR (Banked register)
- A8.8.114 MUL
- A8.8.115 MVN (immediate)
- A8.8.116 MVN (register)
- A8.8.117 MVN (register-shifted register)
- A8.8.118 NEG
- A8.8.119 NOP
- A8.8.120 ORN (immediate)
- A8.8.121 ORN (register)
- A8.8.122 ORR (immediate)
- A8.8.123 ORR (register)
- A8.8.124 ORR (register-shifted register)
- A8.8.125 PKH
- A8.8.126 PLD, PLDW (immediate)
- A8.8.127 PLD (literal)
- A8.8.128 PLD, PLDW (register)
- A8.8.129 PLI (immediate, literal)
- A8.8.130 PLI (register)
- A8.8.131 POP (Thumb)
- A8.8.132 POP (ARM)
- A8.8.133 PUSH
- A8.8.134 QADD
- A8.8.135 QADD16
- A8.8.136 QADD8
- A8.8.137 QASX
- A8.8.138 QDADD
- A8.8.139 QDSUB
- A8.8.140 QSAX
- A8.8.141 QSUB
- A8.8.142 QSUB16
- A8.8.143 QSUB8
- A8.8.144 RBIT
- A8.8.145 REV
- A8.8.146 REV16
- A8.8.147 REVSH
- A8.8.148 RFE
- A8.8.149 ROR (immediate)
- A8.8.150 ROR (register)
- A8.8.151 RRX
- A8.8.152 RSB (immediate)
- A8.8.153 RSB (register)
- A8.8.154 RSB (register-shifted register)
- A8.8.155 RSC (immediate)
- A8.8.156 RSC (register)
- A8.8.157 RSC (register-shifted register)
- A8.8.158 SADD16
- A8.8.159 SADD8
- A8.8.160 SASX
- A8.8.161 SBC (immediate)
- A8.8.162 SBC (register)
- A8.8.163 SBC (register-shifted register)
- A8.8.164 SBFX
- A8.8.165 SDIV
- A8.8.166 SEL
- A8.8.167 SETEND
- A8.8.168 SEV
- A8.8.169 SHADD16
- A8.8.170 SHADD8
- A8.8.171 SHASX
- A8.8.172 SHSAX
- A8.8.173 SHSUB16
- A8.8.174 SHSUB8
- A8.8.175 SMC (previously SMI)
- A8.8.176 SMLABB, SMLABT, SMLATB, SMLATT
- A8.8.177 SMLAD
- A8.8.178 SMLAL
- A8.8.179 SMLALBB, SMLALBT, SMLALTB, SMLALTT
- A8.8.180 SMLALD
- A8.8.181 SMLAWB, SMLAWT
- A8.8.182 SMLSD
- A8.8.183 SMLSLD
- A8.8.184 SMMLA
- A8.8.185 SMMLS
- A8.8.186 SMMUL
- A8.8.187 SMUAD
- A8.8.188 SMULBB, SMULBT, SMULTB, SMULTT
- A8.8.189 SMULL
- A8.8.190 SMULWB, SMULWT
- A8.8.191 SMUSD
- A8.8.192 SRS
- A8.8.193 SSAT
- A8.8.194 SSAT16
- A8.8.195 SSAX
- A8.8.196 SSUB16
- A8.8.197 SSUB8
- A8.8.198 STC, STC2
- A8.8.199 STM (STMIA, STMEA)
- A8.8.200 STMDA (STMED)
- A8.8.201 STMDB (STMFD)
- A8.8.202 STMIB (STMFA)
- A8.8.203 STR (immediate, Thumb)
- A8.8.204 STR (immediate, ARM)
- A8.8.205 STR (register)
- A8.8.206 STRB (immediate, Thumb)
- A8.8.207 STRB (immediate, ARM)
- A8.8.208 STRB (register)
- A8.8.209 STRBT
- A8.8.210 STRD (immediate)
- A8.8.211 STRD (register)
- A8.8.212 STREX
- A8.8.213 STREXB
- A8.8.214 STREXD
- A8.8.215 STREXH
- A8.8.216 STRH (immediate, Thumb)
- A8.8.217 STRH (immediate, ARM)
- A8.8.218 STRH (register)
- A8.8.219 STRHT
- A8.8.220 STRT
- A8.8.221 SUB (immediate, Thumb)
- A8.8.222 SUB (immediate, ARM)
- A8.8.223 SUB (register)
- A8.8.224 SUB (register-shifted register)
- A8.8.225 SUB (SP minus immediate)
- A8.8.226 SUB (SP minus register)
- A8.8.227 SUBS PC, LR and related instructions
- A8.8.228 SVC (previously SWI)
- A8.8.229 SWP, SWPB
- A8.8.230 SXTAB
- A8.8.231 SXTAB16
- A8.8.232 SXTAH
- A8.8.233 SXTB
- A8.8.234 SXTB16
- A8.8.235 SXTH
- A8.8.236 TBB, TBH
- A8.8.237 TEQ (immediate)
- A8.8.238 TEQ (register)
- A8.8.239 TEQ (register-shifted register)
- A8.8.240 TST (immediate)
- A8.8.241 TST (register)
- A8.8.242 TST (register-shifted register)
- A8.8.243 UADD16
- A8.8.244 UADD8
- A8.8.245 UASX
- A8.8.246 UBFX
- A8.8.247 UDF
- A8.8.248 UDIV
- A8.8.249 UHADD16
- A8.8.250 UHADD8
- A8.8.251 UHASX
- A8.8.252 UHSAX
- A8.8.253 UHSUB16
- A8.8.254 UHSUB8
- A8.8.255 UMAAL
- A8.8.256 UMLAL
- A8.8.257 UMULL
- A8.8.258 UQADD16
- A8.8.259 UQADD8
- A8.8.260 UQASX
- A8.8.261 UQSAX
- A8.8.262 UQSUB16
- A8.8.263 UQSUB8
- A8.8.264 USAD8
- A8.8.265 USADA8
- A8.8.266 USAT
- A8.8.267 USAT16
- A8.8.268 USAX
- A8.8.269 USUB16
- A8.8.270 USUB8
- A8.8.271 UXTAB
- A8.8.272 UXTAB16
- A8.8.273 UXTAH
- A8.8.274 UXTB
- A8.8.275 UXTB16
- A8.8.276 UXTH
- A8.8.277 VABA, VABAL
- A8.8.278 VABD, VABDL (integer)
- A8.8.279 VABD (floating-point)
- A8.8.280 VABS
- A8.8.281 VACGE, VACGT, VACLE, VACLT
- A8.8.282 VADD (integer)
- A8.8.283 VADD (floating-point)
- A8.8.284 VADDHN
- A8.8.285 VADDL, VADDW
- A8.8.286 VAND (immediate)
- A8.8.287 VAND (register)
- A8.8.288 VBIC (immediate)
- A8.8.289 VBIC (register)
- A8.8.290 VBIF, VBIT, VBSL
- A8.8.291 VCEQ (register)
- A8.8.292 VCEQ (immediate #0)
- A8.8.293 VCGE (register)
- A8.8.294 VCGE (immediate #0)
- A8.8.295 VCGT (register)
- A8.8.296 VCGT (immediate #0)
- A8.8.297 VCLE (register)
- A8.8.298 VCLE (immediate #0)
- A8.8.299 VCLS
- A8.8.300 VCLT (register)
- A8.8.301 VCLT (immediate #0)
- A8.8.302 VCLZ
- A8.8.303 VCMP, VCMPE
- A8.8.304 VCNT
- A8.8.305 VCVT (between floating-point and integer, Advanced SIMD)
- A8.8.306 VCVT, VCVTR (between floating-point and integer, Floating-point)
- A8.8.307 VCVT (between floating-point and fixed-point, Advanced SIMD)
- A8.8.308 VCVT (between floating-point and fixed-point, Floating-point)
- A8.8.309 VCVT (between double-precision and single-precision)
- A8.8.310 VCVT (between half-precision and single-precision, Advanced SIMD)
- A8.8.311 VCVTB, VCVTT
- A8.8.312 VDIV
- A8.8.313 VDUP (scalar)
- A8.8.314 VDUP (ARM core register)
- A8.8.315 VEOR
- A8.8.316 VEXT
- A8.8.317 VFMA, VFMS
- A8.8.318 VFNMA, VFNMS
- A8.8.319 VHADD, VHSUB
- A8.8.320 VLD1 (multiple single elements)
- A8.8.321 VLD1 (single element to one lane)
- A8.8.322 VLD1 (single element to all lanes)
- A8.8.323 VLD2 (multiple 2-element structures)
- A8.8.324 VLD2 (single 2-element structure to one lane)
- A8.8.325 VLD2 (single 2-element structure to all lanes)
- A8.8.326 VLD3 (multiple 3-element structures)
- A8.8.327 VLD3 (single 3-element structure to one lane)
- A8.8.328 VLD3 (single 3-element structure to all lanes)
- A8.8.329 VLD4 (multiple 4-element structures)
- A8.8.330 VLD4 (single 4-element structure to one lane)
- A8.8.331 VLD4 (single 4-element structure to all lanes)
- A8.8.332 VLDM
- A8.8.333 VLDR
- A8.8.334 VMAX, VMIN (integer)
- A8.8.335 VMAX, VMIN (floating-point)
- A8.8.336 VMLA, VMLAL, VMLS, VMLSL (integer)
- A8.8.337 VMLA, VMLS (floating-point)
- A8.8.338 VMLA, VMLAL, VMLS, VMLSL (by scalar)
- A8.8.339 VMOV (immediate)
- A8.8.340 VMOV (register)
- A8.8.341 VMOV (ARM core register to scalar)
- A8.8.342 VMOV (scalar to ARM core register)
- A8.8.343 VMOV (between ARM core register and single-precision register)
- A8.8.344 VMOV (between two ARM core registers and two single-precision registers)
- A8.8.345 VMOV (between two ARM core registers and a doubleword extension register)
- A8.8.346 VMOVL
- A8.8.347 VMOVN
- A8.8.348 VMRS
- A8.8.349 VMSR
- A8.8.350 VMUL, VMULL (integer and polynomial)
- A8.8.351 VMUL (floating-point)
- A8.8.352 VMUL, VMULL (by scalar)
- A8.8.353 VMVN (immediate)
- A8.8.354 VMVN (register)
- A8.8.355 VNEG
- A8.8.356 VNMLA, VNMLS, VNMUL
- A8.8.357 VORN (immediate)
- A8.8.358 VORN (register)
- A8.8.359 VORR (immediate)
- A8.8.360 VORR (register)
- A8.8.361 VPADAL
- A8.8.362 VPADD (integer)
- A8.8.363 VPADD (floating-point)
- A8.8.364 VPADDL
- A8.8.365 VPMAX, VPMIN (integer)
- A8.8.366 VPMAX, VPMIN (floating-point)
- A8.8.367 VPOP
- A8.8.368 VPUSH
- A8.8.369 VQABS
- A8.8.370 VQADD
- A8.8.371 VQDMLAL, VQDMLSL
- A8.8.372 VQDMULH
- A8.8.373 VQDMULL
- A8.8.374 VQMOVN, VQMOVUN
- A8.8.375 VQNEG
- A8.8.376 VQRDMULH
- A8.8.377 VQRSHL
- A8.8.378 VQRSHRN, VQRSHRUN
- A8.8.379 VQSHL (register)
- A8.8.380 VQSHL, VQSHLU (immediate)
- A8.8.381 VQSHRN, VQSHRUN
- A8.8.382 VQSUB
- A8.8.383 VRADDHN
- A8.8.384 VRECPE
- A8.8.385 VRECPS
- A8.8.386 VREV16, VREV32, VREV64
- A8.8.387 VRHADD
- A8.8.388 VRSHL
- A8.8.389 VRSHR
- A8.8.390 VRSHRN
- A8.8.391 VRSQRTE
- A8.8.392 VRSQRTS
- A8.8.393 VRSRA
- A8.8.394 VRSUBHN
- A8.8.395 VSHL (immediate)
- A8.8.396 VSHL (register)
- A8.8.397 VSHLL
- A8.8.398 VSHR
- A8.8.399 VSHRN
- A8.8.400 VSLI
- A8.8.401 VSQRT
- A8.8.402 VSRA
- A8.8.403 VSRI
- A8.8.404 VST1 (multiple single elements)
- A8.8.405 VST1 (single element from one lane)
- A8.8.406 VST2 (multiple 2-element structures)
- A8.8.407 VST2 (single 2-element structure from one lane)
- A8.8.408 VST3 (multiple 3-element structures)
- A8.8.409 VST3 (single 3-element structure from one lane)
- A8.8.410 VST4 (multiple 4-element structures)
- A8.8.411 VST4 (single 4-element structure from one lane)
- A8.8.412 VSTM
- A8.8.413 VSTR
- A8.8.414 VSUB (integer)
- A8.8.415 VSUB (floating-point)
- A8.8.416 VSUBHN
- A8.8.417 VSUBL, VSUBW
- A8.8.418 VSWP
- A8.8.419 VTBL, VTBX
- A8.8.420 VTRN
- A8.8.421 VTST
- A8.8.422 VUZP
- A8.8.423 VZIP
- A8.8.424 WFE
- A8.8.425 WFI
- A8.8.426 YIELD
- A9: The ThumbEE Instruction Set
- A9.1 About the ThumbEE instruction set
- A9.2 ThumbEE instruction set encoding
- A9.3 Additional instructions in Thumb and ThumbEE instruction sets
- A9.4 ThumbEE instructions with modified behavior
- A9.5 Additional ThumbEE instructions
- Part B: System Level Architecture
- B1: The System Level Programmers’ Model
- B1.1 About the System level programmers’ model
- B1.2 System level concepts and terminology
- B1.3 ARM processor modes and ARM core registers
- B1.4 Instruction set states
- B1.5 The Security Extensions
- B1.6 The Large Physical Address Extension
- B1.7 The Virtualization Extensions
- B1.8 Exception handling
- B1.8.1 Exception vectors and the exception base address
- B1.8.2 Exception priority order
- B1.8.3 Overview of exception entry
- B1.8.4 Processor mode for taking exceptions
- B1.8.5 Processor state on exception entry
- B1.8.6 Asynchronous exception masking
- B1.8.7 Summaries of asynchronous exception behavior
- B1.8.8 Routing general exceptions to Hyp mode
- B1.8.9 Routing Debug exceptions to Hyp mode
- B1.8.10 Exception return
- B1.8.11 Virtual exceptions in the Virtualization Extensions
- B1.8.12 Low interrupt latency configuration
- B1.8.13 Wait For Event and Send Event
- B1.8.14 Wait For Interrupt
- B1.9 Exception descriptions
- B1.9.1 Reset
- B1.9.2 Undefined Instruction exception
- B1.9.3 Hyp Trap exception
- B1.9.4 Supervisor Call (SVC) exception
- B1.9.5 Secure Monitor Call (SMC) exception
- B1.9.6 Hypervisor Call (HVC) exception
- B1.9.7 Prefetch Abort exception
- B1.9.8 Data Abort exception
- B1.9.9 Virtual Abort exception
- B1.9.10 IRQ exception
- B1.9.11 Virtual IRQ exception
- B1.9.12 FIQ exception
- B1.9.13 Virtual FIQ exception
- B1.9.14 Additional pseudocode functions for exception handling
- B1.10 Coprocessors and system control
- B1.11 Advanced SIMD and floating-point support
- B1.12 Thumb Execution Environment
- B1.13 Jazelle direct bytecode execution
- B1.14 Traps to the hypervisor
- B1.14.1 General information about traps to the hypervisor
- B1.14.2 Trapping ID mechanisms
- B1.14.3 Trapping accesses to lockdown, DMA, and TCM operations
- B1.14.4 Trapping accesses to cache maintenance operations
- B1.14.5 Trapping accesses to TLB maintenance operations
- B1.14.6 Trapping accesses to the Auxiliary Control Register
- B1.14.7 Trapping accesses to the Performance Monitors Extension
- B1.14.8 Trapping use of the SMC instruction
- B1.14.9 Trapping use of the WFI and WFE instructions
- B1.14.10 Trapping accesses to Jazelle functionality
- B1.14.11 Trapping accesses to the ThumbEE configuration registers
- B1.14.12 Trapping accesses to coprocessors
- B1.14.13 Trapping writes to virtual memory control registers
- B1.14.14 Generic trapping of accesses to CP15 system control registers
- B1.14.15 Trapping CP14 accesses to debug registers
- B1.14.16 Trapping CP14 accesses to trace registers
- B1.14.17 Summary of trap controls
- B2: Common Memory System Architecture Features
- B2.1 About the memory system architecture
- B2.2 Caches and branch predictors
- B2.2.1 Cache identification
- B2.2.2 Cache behavior
- B2.2.3 Cache enabling and disabling
- B2.2.4 Branch predictors
- B2.2.5 Multiprocessor considerations for cache and similar maintenance operations
- B2.2.6 About ARMv7 cache and branch predictor maintenance functionality
- B2.2.7 Cache and branch predictor maintenance operations
- B2.2.8 The interaction of cache lockdown with cache maintenance operations
- B2.2.9 Ordering of cache and branch predictor maintenance operations
- B2.2.10 System level caches
- B2.3 IMPLEMENTATION DEFINED memory system features
- B2.4 Pseudocode details of general memory system operations
- B2.4.1 Memory data type definitions
- B2.4.2 Basic memory accesses
- B2.4.3 Interfaces to memory system specific pseudocode
- B2.4.4 Aligned memory accesses
- B2.4.5 Unaligned memory accesses
- B2.4.6 Reverse endianness
- B2.4.7 Exclusive monitors operations
- B2.4.8 Access permission checking
- B2.4.9 Default memory access decode
- B2.4.10 Data Abort exception
- B3: Virtual Memory System Architecture (VMSA)
- B3.1 About the VMSA
- B3.2 The effects of disabling MMUs on VMSA behavior
- B3.3 Translation tables
- B3.4 Secure and Non-secure address spaces
- B3.5 Short-descriptor translation table format
- B3.5.1 Short-descriptor translation table format descriptors
- B3.5.2 Memory attributes in the Short-descriptor translation table format descriptors
- B3.5.3 Control of Secure or Non-secure memory access, Short-descriptor format
- B3.5.4 Selecting between TTBR0 and TTBR1, Short-descriptor translation table format
- B3.5.5 Translation table walks, when using the Short-descriptor translation table format
- B3.6 Long-descriptor translation table format
- B3.6.1 Long-descriptor translation table format descriptors
- B3.6.2 Memory attributes in the Long-descriptor translation table format descriptors
- B3.6.3 Control of Secure or Non-secure memory access, Long-descriptor format
- B3.6.4 Selecting between TTBR0 and TTBR1, Long-descriptor translation table format
- B3.6.5 Long-descriptor translation table format address lookup levels
- B3.6.6 Translation table walks, when using the Long-descriptor translation table format
- B3.7 Memory access control
- B3.8 Memory region attributes
- B3.8.1 Overview of memory region attributes for stage 1 translations
- B3.8.2 Short-descriptor format memory region attributes, without TEX remap
- B3.8.3 Short-descriptor format memory region attributes, with TEX remap
- B3.8.4 Long-descriptor format memory region attributes
- B3.8.5 PL2 control of Non-secure memory region attributes
- B3.9 Translation Lookaside Buffers (TLBs)
- B3.10 TLB maintenance requirements
- B3.10.1 General TLB maintenance requirements
- B3.10.2 Maintenance requirements on changing system control register values
- B3.10.3 Atomicity of register changes on changing virtual machine
- B3.10.4 Synchronization of changes of ASID and TTBR
- B3.10.5 Multiprocessor effects on TLB maintenance operations
- B3.10.6 The scope of TLB maintenance operations
- B3.11 Caches in a VMSA implementation
- B3.12 VMSA memory aborts
- B3.13 Exception reporting in a VMSA implementation
- B3.13.1 About exception reporting
- B3.13.2 Reporting exceptions taken to PL1 modes
- B3.13.3 Fault reporting in PL1 modes
- B3.13.4 Summary of register updates on faults taken to PL1 modes
- B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode
- B3.13.6 Use of the HSR
- B3.13.7 Summary of register updates on exceptions taken to the PL2 mode
- B3.14 Virtual Address to Physical Address translation operations
- B3.15 About the system control registers for VMSA
- B3.15.1 About system control register accesses
- B3.15.2 General behavior of system control registers
- B3.15.3 Classification of system control registers
- B3.15.4 Effect of the LPAE and Virtualization Extensions on the system control registers
- B3.15.5 Synchronization of changes to system control registers
- B3.15.6 Meaning of fixed bit values in register diagrams
- B3.16 Organization of the CP14 registers in a VMSA implementation
- B3.17 Organization of the CP15 registers in a VMSA implementation
- B3.17.1 CP15 register summary by coprocessor register number
- VMSA CP15 c0 register summary, identification registers
- VMSA CP15 c1 register summary, system control registers
- VMSA CP15 c2 and c3 register summary, Memory protection and control registers
- CP15 c4, Not used
- VMSA CP15 c5 and c6 register summary, Memory system fault registers
- VMSA CP15 c7 register summary, Cache maintenance, address translation, and other functions
- VMSA CP15 c8 register summary, TLB maintenance operations
- VMSA CP15 c9 register summary, reserved for cache and TCM control and performance monitors
- VMSA CP15 c10 register summary, memory remapping and TLB control registers
- VMSA CP15 c11 register summary, reserved for TCM DMA registers
- VMSA CP15 c12 register summary, Security Extensions registers
- VMSA CP15 c13 register summary, Process, context and thread ID registers
- VMSA CP15 c14, reserved for Generic Timer Extension
- VMSA CP15 c15 register summary, IMPLEMENTATION DEFINED registers
- B3.17.2 Full list of VMSA CP15 registers, by coprocessor register number
- B3.17.3 Views of the CP15 registers
- B3.17.1 CP15 register summary by coprocessor register number
- B3.18 Functional grouping of VMSAv7 system control registers
- B3.18.1 Identification registers, functional group
- B3.18.2 Virtual memory control registers, functional group
- B3.18.3 PL1 Fault handling registers, functional group
- B3.18.4 Other system control registers, functional group
- B3.18.5 Lockdown, DMA, and TCM features, functional group, VMSA
- B3.18.6 Cache maintenance operations, functional group, VMSA
- B3.18.7 TLB maintenance operations, functional group
- B3.18.8 Address translation operations, functional group
- B3.18.9 Miscellaneous operations, functional group
- B3.18.10 Performance Monitors, functional group
- B3.18.11 Security Extensions registers, functional group
- B3.18.12 Virtualization Extensions registers, functional group
- B3.18.13 Generic Timer Extension registers
- B3.18.14 IMPLEMENTATION DEFINED registers, functional group
- B3.19 Pseudocode details of VMSA memory system operations
- B4: System Control Registers in a VMSA implementation
- B4.1 VMSA System control registers descriptions, in register order
- B4.1.1 ACTLR, IMPLEMENTATION DEFINED Auxiliary Control Register, VMSA
- B4.1.2 ADFSR and AIFSR, Auxiliary Data and Instruction Fault Status Registers, VMSA
- B4.1.3 AIDR, IMPLEMENTATION DEFINED Auxiliary ID Register, VMSA
- B4.1.4 AIFSR, Auxiliary Instruction Fault Status Register, VMSA
- B4.1.5 AMAIR0 and AMAIR1, Auxiliary Memory Attribute Indirection Registers 0 and 1, VMSA
- B4.1.6 ATS12NSOPR, Address Translate Stages 1 and 2 Non-secure PL1 Read, VMSA only
- B4.1.7 ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure PL1 Write, VMSA only
- B4.1.8 ATS12NSOUR, Address Translate Stages 1 and 2 Non-secure Unprivileged Read, VMSA only
- B4.1.9 ATS12NSOUW, Address Translate Stages 1 and 2 Non-secure Unprivileged Write, VMSA only
- B4.1.10 ATS1CPR, Address Translate Stage 1 Current state PL1 Read, VMSA only
- B4.1.11 ATS1CPW, Address Translate Stage 1 Current state PL1 Write, VMSA only
- B4.1.12 ATS1CUR, Address Translate Stage 1 Current state Unprivileged Read, VMSA only
- B4.1.13 ATS1CUW, Address Translate Stage 1 Current state Unprivileged Write, VMSA only
- B4.1.14 ATS1HR, Address Translate Stage 1 Hyp mode Read, VMSA only
- B4.1.15 ATS1HW, Address Translate Stage 1 Hyp mode Write, VMSA only
- B4.1.16 BPIALL, Branch Predictor Invalidate All, VMSA
- B4.1.17 BPIALLIS, Branch Predictor Invalidate All, Inner Shareable, VMSA
- B4.1.18 BPIMVA, Branch Predictor Invalidate by MVA, VMSA
- B4.1.19 CCSIDR, Cache Size ID Registers, VMSA
- B4.1.20 CLIDR, Cache Level ID Register, VMSA
- B4.1.21 CNTFRQ, Counter Frequency register, VMSA
- B4.1.22 CNTHCTL, Timer PL2 Control register, Virtualization Extensions
- B4.1.23 CNTHP_CTL, PL2 Physical Timer Control register, Virtualization Extension
- B4.1.24 CNTHP_CVAL, PL2 Physical Timer CompareValue register, Virtualization Extensions
- B4.1.25 CNTHP_TVAL, PL2 Physical TimerValue register, Virtualization Extensions
- B4.1.26 CNTKCTL, Timer PL1 Control register, VMSA
- B4.1.27 CNTP_CTL, PL1 Physical Timer Control register, VMSA
- B4.1.28 CNTP_CVAL, PL1 Physical Timer CompareValue register, VMSA
- B4.1.29 CNTP_TVAL, PL1 Physical TimerValue register, VMSA
- B4.1.30 CNTPCT, Physical Count register, VMSA
- B4.1.31 CNTV_CTL, Virtual Timer Control register, VMSA
- B4.1.32 CNTV_CVAL, Virtual Timer CompareValue register, VMSA
- B4.1.33 CNTV_TVAL, Virtual TimerValue register, VMSA
- B4.1.34 CNTVCT, Virtual Count register, VMSA
- B4.1.35 CNTVOFF, Virtual Offset register, VMSA
- B4.1.36 CONTEXTIDR, Context ID Register, VMSA
- B4.1.37 CP15DMB, CP15 Data Memory Barrier operation, VMSA
- B4.1.38 CP15DSB, CP15 Data Synchronization Barrier operation, VMSA
- B4.1.39 CP15ISB, CP15 Instruction Synchronization Barrier operation, VMSA
- B4.1.40 CPACR, Coprocessor Access Control Register, VMSA
- B4.1.41 CSSELR, Cache Size Selection Register, VMSA
- B4.1.42 CTR, Cache Type Register, VMSA
- B4.1.43 DACR, Domain Access Control Register, VMSA
- B4.1.44 DCCIMVAC, Data Cache Clean and Invalidate by MVA to PoC, VMSA
- B4.1.45 DCCISW, Data Cache Clean and Invalidate by Set/Way, VMSA
- B4.1.46 DCCMVAC, Data Cache Clean by MVA to PoC, VMSA
- B4.1.47 DCCMVAU, Data Cache Clean by MVA to PoU, VMSA
- B4.1.48 DCCSW, Data Cache Clean by Set/Way, VMSA
- B4.1.49 DCIMVAC, Data Cache Invalidate by MVA to PoC, VMSA
- B4.1.50 DCISW, Data Cache Invalidate by Set/Way, VMSA
- B4.1.51 DFAR, Data Fault Address Register, VMSA
- B4.1.52 DFSR, Data Fault Status Register, VMSA
- B4.1.53 DTLBIALL, Data TLB Invalidate All, VMSA only
- B4.1.54 DTLBIASID, Data TLB Invalidate by ASID, VMSA only
- B4.1.55 DTLBIMVA, Data TLB Invalidate by MVA, VMSA only
- B4.1.56 FCSEIDR, FCSE Process ID Register, VMSA
- B4.1.57 FPEXC, Floating-Point Exception Control register, VMSA
- B4.1.58 FPSCR, Floating-point Status and Control Register, VMSA
- B4.1.59 FPSID, Floating-point System ID Register, VMSA
- B4.1.60 HACR, Hyp Auxiliary Configuration Register, Virtualization Extensions
- B4.1.61 HACTLR, Hyp Auxiliary Control Register, Virtualization Extensions
- B4.1.62 HADFSR and HAIFSR, Hyp Auxiliary Fault Syndrome Registers, Virtualization Extensions
- B4.1.63 HAMAIR0 and HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Registers 0 and 1
- B4.1.64 HCPTR, Hyp Coprocessor Trap Register, Virtualization Extensions
- B4.1.65 HCR, Hyp Configuration Register, Virtualization Extensions
- B4.1.66 HDCR, Hyp Debug Configuration Register, Virtualization Extensions
- B4.1.67 HDFAR, Hyp Data Fault Address Register, Virtualization Extensions
- B4.1.68 HIFAR, Hyp Instruction Fault Address Register, Virtualization Extensions
- B4.1.69 HMAIRn, Hyp Memory Attribute Indirection Registers 0 and 1, Virtualization Extensions
- B4.1.70 HPFAR, Hyp IPA Fault Address Register, Virtualization Extensions
- B4.1.71 HSCTLR, Hyp System Control Register, Virtualization Extensions
- B4.1.72 HSR, Hyp Syndrome Register, Virtualization Extensions
- B4.1.73 HSTR, Hyp System Trap Register, Virtualization Extensions
- B4.1.74 HTCR, Hyp Translation Control Register, Virtualization Extensions
- B4.1.75 HTPIDR, Hyp Software Thread ID Register, Virtualization Extensions
- B4.1.76 HTTBR, Hyp Translation Table Base Register, Virtualization Extensions
- B4.1.77 HVBAR, Hyp Vector Base Address Register, Virtualization Extensions
- B4.1.78 ICIALLU, Instruction Cache Invalidate All to PoU, VMSA
- B4.1.79 ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable, VMSA
- B4.1.80 ICIMVAU, Instruction Cache Invalidate by MVA to PoU, VMSA
- B4.1.81 ID_AFR0, Auxiliary Feature Register 0, VMSA
- B4.1.82 ID_DFR0, Debug Feature Register 0, VMSA
- B4.1.83 ID_ISAR0, Instruction Set Attribute Register 0, VMSA
- B4.1.84 ID_ISAR1, Instruction Set Attribute Register 1, VMSA
- B4.1.85 ID_ISAR2, Instruction Set Attribute Register 2, VMSA
- B4.1.86 ID_ISAR3, Instruction Set Attribute Register 3, VMSA
- B4.1.87 ID_ISAR4, Instruction Set Attribute Register 4, VMSA
- B4.1.88 ID_ISAR5, Instruction Set Attribute Register 5, VMSA
- B4.1.89 ID_MMFR0, Memory Model Feature Register 0, VMSA
- B4.1.90 ID_MMFR1, Memory Model Feature Register 1, VMSA
- B4.1.91 ID_MMFR2, Memory Model Feature Register 2, VMSA
- B4.1.92 ID_MMFR3, Memory Model Feature Register 3, VMSA
- B4.1.93 ID_PFR0, Processor Feature Register 0, VMSA
- B4.1.94 ID_PFR1, Processor Feature Register 1, VMSA
- B4.1.95 IFAR, Instruction Fault Address Register, VMSA
- B4.1.96 IFSR, Instruction Fault Status Register, VMSA
- B4.1.97 ISR, Interrupt Status Register, Security Extensions
- B4.1.98 ITLBIALL, Instruction TLB Invalidate All, VMSA only
- B4.1.99 ITLBIASID, Instruction TLB Invalidate by ASID, VMSA only
- B4.1.100 ITLBIMVA, Instruction TLB Invalidate by MVA, VMSA only
- B4.1.101 JIDR, Jazelle ID Register, VMSA
- B4.1.102 JMCR, Jazelle Main Configuration Register, VMSA
- B4.1.103 JOSCR, Jazelle OS Control Register, VMSA
- B4.1.104 MAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1, VMSA
- B4.1.105 MIDR, Main ID Register, VMSA
- B4.1.106 MPIDR, Multiprocessor Affinity Register, VMSA
- B4.1.107 MVBAR, Monitor Vector Base Address Register, Security Extensions
- B4.1.108 MVFR0, Media and VFP Feature Register 0, VMSA
- B4.1.109 MVFR1, Media and VFP Feature Register 1, VMSA
- B4.1.110 NMRR, Normal Memory Remap Register, VMSA
- B4.1.111 NSACR, Non-Secure Access Control Register, Security Extensions
- B4.1.112 PAR, Physical Address Register, VMSA
- B4.1.113 PMCCNTR, Performance Monitors Cycle Count Register, VMSA
- B4.1.114 PMCEID0 and PMCEID1, Performance Monitors Common Event ID registers, VMSA
- B4.1.115 PMCNTENCLR, Performance Monitors Count Enable Clear register, VMSA
- B4.1.116 PMCNTENSET, Performance Monitors Count Enable Set register, VMSA
- B4.1.117 PMCR, Performance Monitors Control Register, VMSA
- B4.1.118 PMINTENCLR, Performance Monitors Interrupt Enable Clear register, VMSA
- B4.1.119 PMINTENSET, Performance Monitors Interrupt Enable Set register, VMSA
- B4.1.120 PMOVSR, Performance Monitors Overflow Flag Status Register, VMSA
- B4.1.121 PMOVSSET, Performance Monitors Overflow Flag Status Set register, Virtualization Extensions
- B4.1.122 PMSELR, Performance Monitors Event Counter Selection Register, VMSA
- B4.1.123 PMSWINC, Performance Monitors Software Increment register, VMSA
- B4.1.124 PMUSERENR, Performance Monitors User Enable Register, VMSA
- B4.1.125 PMXEVCNTR, Performance Monitors Event Count Register, VMSA
- B4.1.126 PMXEVTYPER, Performance Monitors Event Type Select Register, VMSA
- B4.1.127 PRRR, Primary Region Remap Register, VMSA
- B4.1.128 REVIDR, Revision ID Register, VMSA
- B4.1.129 SCR, Secure Configuration Register, Security Extensions
- B4.1.130 SCTLR, System Control Register, VMSA
- B4.1.131 SDER, Secure Debug Enable Register, Security Extensions
- B4.1.132 TCMTR, TCM Type Register, VMSA
- B4.1.133 TEECR, ThumbEE Configuration Register, VMSA
- B4.1.134 TEEHBR, ThumbEE Handler Base Register, VMSA
- B4.1.135 TLBIALL, TLB Invalidate All, VMSA only
- B4.1.136 TLBIALLH, TLB Invalidate All, Hyp mode, Virtualization Extensions
- B4.1.137 TLBIALLHIS, TLB Invalidate All, Hyp mode, Inner Shareable, Virtualization Extensions
- B4.1.138 TLBIALLIS, TLB Invalidate All, Inner Shareable, VMSA only
- B4.1.139 TLBIALLNSNH, TLB Invalidate all Non-secure Non-Hyp, Virtualization Extensions
- B4.1.140 TLBIALLNSNHIS, TLB Invalidate all Non-secure Non-Hyp IS, Virtualization Extensions
- B4.1.141 TLBIASID, TLB Invalidate by ASID, VMSA only
- B4.1.142 TLBIASIDIS, TLB Invalidate by ASID, Inner Shareable, VMSA only
- B4.1.143 TLBIMVA, TLB Invalidate by MVA, VMSA only
- B4.1.144 TLBIMVAA, TLB Invalidate by MVA, all ASIDs, VMSA only
- B4.1.145 TLBIMVAAIS, TLB Invalidate by MVA, all ASIDs, Inner Shareable, VMSA only
- B4.1.146 TLBIMVAH, TLB Invalidate by MVA, Hyp mode, Virtualization Extensions
- B4.1.147 TLBIMVAHIS, TLB Invalidate by MVA, Hyp mode, Inner Shareable, Virtualization Extensions
- B4.1.148 TLBIMVAIS, TLB Invalidate by MVA, Inner Shareable, VMSA only
- B4.1.149 TLBTR, TLB Type Register, VMSA
- B4.1.150 TPIDRPRW, PL1 only Thread ID Register, VMSA
- B4.1.151 TPIDRURO, User Read-Only Thread ID Register, VMSA
- B4.1.152 TPIDRURW, User Read/Write Thread ID Register, VMSA
- B4.1.153 TTBCR, Translation Table Base Control Register, VMSA
- B4.1.154 TTBR0, Translation Table Base Register 0, VMSA
- B4.1.155 TTBR1, Translation Table Base Register 1, VMSA
- B4.1.156 VBAR, Vector Base Address Register, Security Extensions
- B4.1.157 VMPIDR, Virtualization Multiprocessor ID Register, Virtualization Extensions
- B4.1.158 VPIDR, Virtualization Processor ID Register, Virtualization Extensions
- B4.1.159 VTCR, Virtualization Translation Control Register, Virtualization Extensions
- B4.1.160 VTTBR, Virtualization Translation Table Base Register, Virtualization Extensions
- B4.2 VMSA system control operations described by function
- B4.2.1 Cache and branch predictor maintenance operations, VMSA
- B4.2.2 TLB maintenance operations, not in Hyp mode
- B4.2.3 Hyp mode TLB maintenance operations, Virtualization Extensions
- B4.2.4 Performing address translation operations
- B4.2.5 Data and instruction barrier operations, VMSA
- B4.2.6 Cache and TCM lockdown registers, VMSA
- B4.2.7 IMPLEMENTATION DEFINED TLB control operations, VMSA
- B4.2.8 DMA support, VMSA
- B4.1 VMSA System control registers descriptions, in register order
- B5: Protected Memory System Architecture (PMSA)
- B5.1 About the PMSA
- B5.2 Memory access control
- B5.3 Memory region attributes
- B5.4 PMSA memory aborts
- B5.5 Exception reporting in a PMSA implementation
- B5.6 About the system control registers for PMSA
- B5.7 Organization of the CP14 registers in a PMSA implementation
- B5.8 Organization of the CP15 registers in a PMSA implementation
- B5.8.1 PMSA CP15 register summary by coprocessor register number
- PMSA CP15 c0 register summary, identification registers
- PMSA CP15 c1 register summary, system control registers
- PMSA CP15 c2 and c3 register summary, not used on a PMSA implementation
- PMSA CP15 c4 register summary, not used
- PMSA CP15 c5 and c6 register summary, memory system fault registers
- PMSA CP15 c7 register summary, cache maintenance and other functions
- PMSA CP15 c8 register summary, not used on a PMSA implementation
- PMSA CP15 c9 register summary, reserved for cache and TCM lockdown registers and performance monitors
- PMSA CP15 c10 register summary, not used on a PMSA implementation
- PMSA CP15 c11 register summary, reserved for TCM DMA registers
- PMSA CP15 c12 register summary, not used on a PMSA implementation
- PMSA CP15 c13 register summary, context and thread ID registers
- PMSA CP15 c14, reserved for Generic Timer Extension
- PMSA CP15 c15 register summary, IMPLEMENTATION DEFINED registers
- B5.8.2 Full list of PMSA CP15 registers, by coprocessor register number
- B5.8.3 Views of the CP15 registers
- B5.8.1 PMSA CP15 register summary by coprocessor register number
- B5.9 Functional grouping of PMSAv7 system control registers
- B5.9.1 Identification registers, functional group
- B5.9.2 MMU control registers, functional group
- B5.9.3 PL1 Fault handling registers, functional group
- B5.9.4 Other system control registers, functional group
- B5.9.5 Lockdown and DMA features, functional group
- B5.9.6 Cache maintenance operations, functional group
- B5.9.7 Miscellaneous operations, functional group
- B5.9.8 Performance Monitors, functional group
- B5.9.9 Generic Timer Extension registers
- B5.9.10 IMPLEMENTATION DEFINED registers, functional group
- B5.10 Pseudocode details of PMSA memory system operations
- B6: System Control Registers in a PMSA implementation
- B6.1 PMSA System control registers descriptions, in register order
- B6.1.1 ACTLR, IMPLEMENTATION DEFINED Auxiliary Control Register, PMSA
- B6.1.2 AIDR, IMPLEMENTATION DEFINED Auxiliary ID Register, PMSA
- B6.1.3 ADFSR and AIFSR, Auxiliary Data and Instruction Fault Status Registers, PMSA
- B6.1.4 BPIALL, Branch Predictor Invalidate All, PMSA
- B6.1.5 BPIALLIS, Branch Predictor Invalidate All, Inner Shareable, PMSA
- B6.1.6 BPIMVA, Branch Predictor Invalidate by MVA, PMSA
- B6.1.7 CCSIDR, Cache Size ID Registers, PMSA
- B6.1.8 CLIDR, Cache Level ID Register, PMSA
- B6.1.9 CNTFRQ, Counter Frequency register, PMSA
- B6.1.10 CNTKCTL, Timer PL1 Control register, PMSA
- B6.1.11 CNTP_CTL, PL1 Physical Timer Control register, PMSA
- B6.1.12 CNTP_CVAL, PL1 Physical Timer CompareValue register, PMSA
- B6.1.13 CNTP_TVAL, PL1 Physical TimerValue register, PMSA
- B6.1.14 CNTPCT, Physical Count register, PMSA
- B6.1.15 CNTV_CTL, Virtual Timer Control register, PMSA
- B6.1.16 CNTV_CVAL, Virtual Timer CompareValue register, PMSA
- B6.1.17 CNTV_TVAL, Virtual TimerValue register, PMSA
- B6.1.18 CNTVCT, Virtual Count register, PMSA
- B6.1.19 CONTEXTIDR, Context ID Register, PMSA
- B6.1.20 CP15DMB, CP15 Data Memory Barrier operation, PMSA
- B6.1.21 CP15DSB, CP15 Data Synchronization Barrier operation, PMSA
- B6.1.22 CP15ISB, CP15 Instruction Synchronization Barrier operation, PMSA
- B6.1.23 CPACR, Coprocessor Access Control Register, PMSA
- B6.1.24 CSSELR, Cache Size Selection Register, PMSA
- B6.1.25 CTR, Cache Type Register, PMSA
- B6.1.26 DCCIMVAC, Data Cache Clean and Invalidate by MVA to PoC, PMSA
- B6.1.27 DCCISW, Data Cache Clean and Invalidate by Set/Way, PMSA only
- B6.1.28 DCCMVAC, Data Cache Clean by MVA to PoC, PMSA
- B6.1.29 DCCMVAU, Data Cache Clean by MVA to PoU, PMSA
- B6.1.30 DCCSW, Data Cache Clean by Set/Way, PMSA
- B6.1.31 DCIMVAC, Data Cache Invalidate by MVA to PoC, PMSA
- B6.1.32 DCISW, Data Cache Invalidate by Set/Way, PMSA
- B6.1.33 DFAR, Data Fault Address Register, PMSA
- B6.1.34 DFSR, Data Fault Status Register, PMSA
- B6.1.35 DRACR, Data Region Access Control Register, PMSA
- B6.1.36 DRBAR, Data Region Base Address Register, PMSA
- B6.1.37 DRSR, Data Region Size and Enable Register, PMSA
- B6.1.38 FPEXC, Floating-Point Exception Control register, PMSA
- B6.1.39 FPSCR, Floating-point Status and Control Register, PMSA
- B6.1.40 FPSID, Floating-point System ID Register, PMSA
- B6.1.41 ICIALLU, Instruction Cache Invalidate All to PoU, PMSA
- B6.1.42 ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable, PMSA
- B6.1.43 ICIMVAU, Instruction Cache Invalidate by MVA to PoU, PMSA
- B6.1.44 ID_AFR0, Auxiliary Feature Register 0, PMSA
- B6.1.45 ID_DFR0, Debug Feature Register 0, PMSA
- B6.1.46 ID_ISAR0, Instruction Set Attribute Register 0, PMSA
- B6.1.47 ID_ISAR1, Instruction Set Attribute Register 1, PMSA
- B6.1.48 ID_ISAR2, Instruction Set Attribute Register 2, PMSA
- B6.1.49 ID_ISAR3, Instruction Set Attribute Register 3, PMSA
- B6.1.50 ID_ISAR4, Instruction Set Attribute Register 4, PMSA
- B6.1.51 ID_ISAR5, Instruction Set Attribute Register 5, PMSA
- B6.1.52 ID_MMFR0, Memory Model Feature Register 0, PMSA
- B6.1.53 ID_MMFR1, Memory Model Feature Register 1, PMSA
- B6.1.54 ID_MMFR2, Memory Model Feature Register 2, PMSA
- B6.1.55 ID_MMFR3, Memory Model Feature Register 3, PMSA
- B6.1.56 ID_PFR0, Processor Feature Register 0, PMSA
- B6.1.57 ID_PFR1, Processor Feature Register 1, PMSA
- B6.1.58 IFAR, Instruction Fault Address Register, PMSA
- B6.1.59 IFSR, Instruction Fault Status Register, PMSA
- B6.1.60 IRACR, Instruction Region Access Control Register, PMSA
- B6.1.61 IRBAR, Instruction Region Base Address Register, PMSA
- B6.1.62 IRSR, Instruction Region Size and Enable Register, PMSA
- B6.1.63 JIDR, Jazelle ID Register, PMSA
- B6.1.64 JMCR, Jazelle Main Configuration Register, PMSA
- B6.1.65 JOSCR, Jazelle OS Control Register, PMSA
- B6.1.66 MIDR, Main ID Register, PMSA
- B6.1.67 MPIDR, Multiprocessor Affinity Register, PMSA
- B6.1.68 MPUIR, MPU Type Register, PMSA
- B6.1.69 MVFR0, Media and VFP Feature Register 0, PMSA
- B6.1.70 MVFR1, Media and VFP Feature Register 1, PMSA
- B6.1.71 PMCCNTR, Performance Monitors Cycle Count Register, PMSA
- B6.1.72 PMCEID0 and PMCEID1, Performance Monitors Common Event ID registers, PMSA
- B6.1.73 PMCNTENCLR, Performance Monitors Count Enable Clear register, PMSA
- B6.1.74 PMCNTENSET, Performance Monitors Count Enable Set register, PMSA
- B6.1.75 PMCR, Performance Monitors Control Register, PMSA
- B6.1.76 PMINTENCLR, Performance Monitors Interrupt Enable Clear register, PMSA
- B6.1.77 PMINTENSET, Performance Monitors Interrupt Enable Set register, PMSA
- B6.1.78 PMOVSR, Performance Monitors Overflow Flag Status Register, PMSA
- B6.1.79 PMSELR, Performance Monitors Event Counter Selection Register, PMSA
- B6.1.80 PMSWINC, Performance Monitors Software Increment register, PMSA
- B6.1.81 PMUSERENR, Performance Monitors User Enable Register, PMSA
- B6.1.82 PMXEVCNTR, Performance Monitors Event Count Register, PMSA
- B6.1.83 PMXEVTYPER, Performance Monitors Event Type Select Register, PMSA
- B6.1.84 REVIDR, Revision ID Register, PMSA
- B6.1.85 RGNR, MPU Region Number Register, PMSA
- B6.1.86 SCTLR, System Control Register, PMSA
- B6.1.87 TCMTR, TCM Type Register, PMSA
- B6.1.88 TEECR, ThumbEE Configuration Register, PMSA
- B6.1.89 TEEHBR, ThumbEE Handler Base Register, PMSA
- B6.1.90 TPIDRPRW, PL1 only Thread ID Register, PMSA
- B6.1.91 TPIDRURO, User Read-Only Thread ID Register, PMSA
- B6.1.92 TPIDRURW, User Read/Write Thread ID Register, PMSA
- B6.2 PMSA system control operations described by function
- B6.1 PMSA System control registers descriptions, in register order
- B7: The CPUID Identification Scheme
- B8: The Generic Timer
- B9: System Instructions
- B9.1 General restrictions on system instructions
- B9.2 Encoding and use of Banked register transfer instructions
- B9.3 Alphabetical list of instructions
- B9.3.1 CPS (Thumb)
- B9.3.2 CPS (ARM)
- B9.3.3 ERET
- B9.3.4 HVC
- B9.3.5 LDM (exception return)
- B9.3.6 LDM (User registers)
- B9.3.7 LDRBT, LDRHT, LDRSBT, LDRSHT, and LDRT
- B9.3.8 MRS
- B9.3.9 MRS (Banked register)
- B9.3.10 MSR (Banked register)
- B9.3.11 MSR (immediate)
- B9.3.12 MSR (register)
- B9.3.13 RFE
- B9.3.14 SMC (previously SMI)
- B9.3.15 SRS (Thumb)
- B9.3.16 SRS (ARM)
- B9.3.17 STM (User registers)
- B9.3.18 STRBT, STRHT, and STRT
- B9.3.19 SUBS PC, LR (Thumb)
- B9.3.20 SUBS PC, LR and related instructions (ARM)
- B9.3.21 VMRS
- B9.3.22 VMSR
- Part C: Debug Architecture
- C1: Introduction to the ARM Debug Architecture
- C2: Invasive Debug Authentication
- C3: Debug Events
- C3.1 About debug events
- C3.2 BKPT instruction debug events
- C3.3 Breakpoint debug events
- C3.3.1 Generation of Breakpoint debug events
- C3.3.2 Breakpoint types defined by the DBGBCR
- C3.3.3 Conditions for debug event generation defined by the DBGBCR
- C3.3.4 Byte address selection and masking defined by the DBGBCR
- C3.3.5 Instruction address comparisons for debug event generation
- Condition for breakpoint generation on address match, with byte address selection
- Condition for breakpoint generation on address mismatch, with byte address selection
- Byte address selection behavior on instruction address match or mismatch
- Breakpoint address range masking behavior
- Instruction address comparisons in different instruction set states
- Instruction address comparison programming examples
- Use of instruction address mismatch breakpoints for single-stepping
- C3.3.6 Context matching comparisons for debug event generation
- C3.3.7 Linked comparisons for debug event generation
- C3.3.8 Summary of breakpoint generation options
- C3.4 Watchpoint debug events
- C3.5 Vector catch debug events
- C3.6 Halting debug events
- C3.7 Generation of debug events
- C3.8 Debug event prioritization
- C3.9 Pseudocode details of Software debug events
- C4: Debug Exceptions
- C5: Debug State
- C5.1 About Debug state
- C5.2 Entering Debug state
- C5.3 Executing instructions in Debug state
- C5.4 Behavior of non-invasive debug in Debug state
- C5.5 Exceptions in Debug state
- C5.6 Memory system behavior in Debug state
- C5.7 Exiting Debug state
- C6: Debug Register Interfaces
- C6.1 About the debug register interfaces
- C6.2 Synchronization of debug register updates
- C6.3 Access permissions
- C6.4 The CP14 debug register interface
- C6.5 The memory-mapped and recommended external debug interfaces
- C6.6 Summary of the v7 Debug register interfaces
- C6.7 Summary of the v7.1 Debug register interfaces
- C7: Debug Reset and Powerdown Support
- C8: The Debug Communications Channel and Instruction Transfer Register
- C9: Non-invasive Debug Authentication
- C10: Sample-based Profiling
- C11: The Debug Registers
- C11.1 About the debug registers
- C11.2 Debug register summary
- C11.3 Debug identification registers
- C11.4 Control and status registers
- C11.5 Instruction and data transfer registers
- C11.6 Software debug event registers
- C11.7 Sample-based profiling registers
- C11.8 OS Save and Restore registers
- C11.9 Memory system control registers
- C11.10 Management registers
- C11.11 Register descriptions, in register order
- C11.11.1 DBGAUTHSTATUS, Authentication Status register
- C11.11.2 DBGBCR, Breakpoint Control Registers
- C11.11.3 DBGBVR, Breakpoint Value Registers
- C11.11.4 DBGBXVR, Breakpoint Extended Value Registers
- C11.11.5 DBGCID0, Debug Component ID Register 0
- C11.11.6 DBGCID1, Debug Component ID Register 1
- C11.11.7 DBGCID2, Debug Component ID Register 2
- C11.11.8 DBGCID3, Debug Component ID Register 3
- C11.11.9 DBGCIDSR, Context ID Sampling Register
- C11.11.10 DBGCLAIMCLR, Claim Tag Clear register
- C11.11.11 DBGCLAIMSET, Claim Tag Set register
- C11.11.12 DBGDEVID, Debug Device ID register
- C11.11.13 DBGDEVID1, Debug Device ID register 1
- C11.11.14 DBGDEVTYPE, Device Type Register
- C11.11.15 DBGDIDR, Debug ID Register
- C11.11.16 DBGDRAR, Debug ROM Address Register
- C11.11.17 DBGDRCR, Debug Run Control Register
- C11.11.18 DBGDSAR, Debug Self Address Offset Register
- C11.11.19 DBGDSCCR, Debug State Cache Control Register
- C11.11.20 DBGDSCR, Debug Status and Control Register
- C11.11.21 DBGDSMCR, Debug State MMU Control Register
- C11.11.22 DBGDTRRX, Host to Target Data Transfer register
- C11.11.23 DBGDTRTX, Target to Host Data Transfer register
- C11.11.24 DBGEACR, External Auxiliary Control Register
- C11.11.25 DBGECR, Event Catch Register
- C11.11.26 DBGITCTRL, Integration Mode Control register
- C11.11.27 DBGITR, Instruction Transfer Register
- C11.11.28 DBGLAR, Lock Access Register
- C11.11.29 DBGLSR, Lock Status Register
- C11.11.30 DBGOSDLR, OS Double Lock Register
- C11.11.31 DBGOSLAR, OS Lock Access Register
- C11.11.32 DBGOSLSR, OS Lock Status Register
- C11.11.33 DBGOSSRR, OS Save and Restore Register
- C11.11.34 DBGPCSR, Program Counter Sampling Register
- C11.11.35 DBGPID0, Debug Peripheral ID Register 0
- C11.11.36 DBGPID1, Debug Peripheral ID Register 1
- C11.11.37 DBGPID2, Debug Peripheral ID Register 2
- C11.11.38 DBGPID3, Debug Peripheral ID Register 3
- C11.11.39 DBGPID4, Debug Peripheral ID Register 4
- C11.11.40 DBGPRCR, Device Powerdown and Reset Control Register
- C11.11.41 DBGPRSR, Device Powerdown and Reset Status Register
- C11.11.42 DBGVCR, Vector Catch Register
- C11.11.43 DBGVIDSR, Virtualization ID Sampling Register
- C11.11.44 DBGWCR, Watchpoint Control Registers
- C11.11.45 DBGWFAR, Watchpoint Fault Address Register
- C11.11.46 DBGWVR, Watchpoint Value Registers
- C12: The Performance Monitors Extension
- C12.1 About the Performance Monitors
- C12.1.1 About the Performance Monitors v2
- C12.1.2 Identification of the Performance Monitors Extension version
- C12.1.3 PMU versions, and status in the ARM architecture
- C12.1.4 Interaction with trace
- C12.1.5 Interaction with power saving operations
- C12.1.6 Interaction with Save and Restore operations
- C12.1.7 Effects of non-invasive debug authentication on the Performance Monitors
- C12.2 Accuracy of the Performance Monitors
- C12.3 Behavior on overflow
- C12.4 Effect of the Security Extensions and Virtualization Extensions
- C12.5 Event filtering, PMUv2
- C12.6 Counter enables
- C12.7 Counter access
- C12.8 Event numbers and mnemonics
- C12.9 Performance Monitors registers
- C12.1 About the Performance Monitors
- Part D: Appendixes
- A: Recommended External Debug Interface
- B: Recommended Memory-mapped and External Debug Interfaces for the Performance Monitors
- B.1 About the memory-mapped views of the Performance Monitors registers
- B.2 PMU register descriptions for memory-mapped register views
- B.2.1 PMAUTHSTATUS, Performance Monitors Authentication Status register
- B.2.2 PMCFGR, Performance Monitors Configuration Register
- B.2.3 PMCID0, Performance Monitors Component ID register 0
- B.2.4 PMCID1, Performance Monitors Component ID register 1
- B.2.5 PMCID2, Performance Monitors Component ID register 2
- B.2.6 PMCID3, Performance Monitors Component ID register 3
- B.2.7 PMDEVTYPE, Performance Monitors Device Type register
- B.2.8 PMLAR, Performance Monitors Lock Access Register
- B.2.9 PMLSR, Performance Monitors Lock Status Register
- B.2.10 PMPID0, Performance Monitors Peripheral ID register 0
- B.2.11 PMPID1, Performance Monitors Peripheral ID register 1
- B.2.12 PMPID2, Performance Monitors Peripheral ID register 2
- B.2.13 PMPID3, Performance Monitors Peripheral ID register 3
- B.2.14 PMPID4, Performance Monitors Peripheral ID register 4
- C: Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION DEFINED Events
- D: Example OS Save and Restore Sequences for External Debug Over Powerdown
- E: System Level Implementation of the Generic Timer
- E.1 About the Generic Timer specification
- E.2 Memory-mapped counter module
- E.3 Counter module control and status register summary
- E.4 About the memory-mapped view of the counter and timer
- E.5 The CNTBaseN and CNTPL0BaseN frames
- E.6 The CNTCTLBase frame
- E.7 System level Generic Timer register descriptions, in register order
- E.7.1 CNTACRn, Counter Access Control Register
- E.7.2 CNTCR, Counter Control Register
- E.7.3 CNTCV, Counter Count Value register
- E.7.4 CNTFRQ, Counter Frequency register, system level
- E.7.5 CNTNSAR, Counter Non-Secure Access Register
- E.7.6 CNTP_CTL, PL1 Physical Timer Control register, system level
- E.7.7 CNTP_CVAL, PL1 Physical Timer CompareValue register, system level
- E.7.8 CNTP_TVAL, PL1 Physical TimerValue register, system level
- E.7.9 CNTPCT, Physical Count register, system level
- E.7.10 CNTPL0ACR, Counter PL0 Access Control Register
- E.7.11 CNTSR, Counter Status Register
- E.7.12 CNTTIDR, Counter Timer ID Register
- E.7.13 CNTV_CTL, Virtual Timer Control register, system level
- E.7.14 CNTV_CVAL, Virtual Timer CompareValue register, system level
- E.7.15 CNTV_TVAL, Virtual TimerValue register, system level
- E.7.16 CNTVCT, Virtual Count register, system level
- E.7.17 CNTVOFFn, Virtual Offset register, system level
- E.7.18 CounterIDn, Counter ID registers 0-11
- E.8 Providing a complete set of counter and timer features
- E.9 Gray-count scheme for timer distribution scheme
- F: Common VFP Subarchitecture Specification
- F.1 Scope of this appendix
- F.2 Introduction to the Common VFP subarchitecture
- F.3 Exception processing
- F.4 Support code requirements
- F.5 Context switching
- F.6 Subarchitecture additions to the Floating-point Extension system registers
- F.7 Earlier versions of the Common VFP subarchitecture
- G: Barrier Litmus Tests
- G.1 Introduction
- G.2 Simple ordering and barrier cases
- G.2.1 Simple weakly consistent ordering example
- G.2.2 Message passing
- G.2.3 Address dependency with object construction
- G.2.4 Causal consistency issues with multiple observers
- G.2.5 Multiple observers of writes to multiple locations
- G.2.6 Posting a store before polling for acknowledgement
- G.2.7 WFE and WFI and barriers
- G.3 Exclusive accesses and barriers
- G.4 Using a mailbox to send an interrupt
- G.5 Cache and TLB maintenance operations and barriers
- H: Legacy Instruction Mnemonics
- I: Deprecated and Obsolete Features
- I.1 Deprecated features
- I.1.1 Use of SWP and SWPB semaphore instructions
- I.1.2 Use of VFP vector mode
- I.1.3 Use of VFP FLDMX and FSTMX instructions
- I.1.4 Use of the Fast Context Switch Extension
- I.1.5 Direct manipulation of the Endianness bit
- I.1.6 Ordering of instructions that change the CPSR interrupt masks
- I.1.7 Shareability of Device memory regions
- I.1.8 Unaligned exception returns
- I.1.9 Deprecations relating to using the AP[2:0] scheme for defining MMU access permissions
- I.1.10 Use of the Domain field in the DFSR
- I.1.11 Use of the CP15 memory barrier operations
- I.1.12 Deprecations that affect use of the SCTLR
- I.1.13 Interrupts or asynchronous aborts in a sequence of memory transactions
- I.1.14 Use of Instruction TLB and Data TLB operations
- I.1.15 Use of old mnemonics for operations to invalidate entries in a unified TLB
- I.1.16 Use of ATS12NSO** and ATS1H* operations from Secure modes at PL1
- I.1.17 Use of old mnemonics for address translation operations
- I.1.18 Use of the NSACR.RFR bit
- I.1.19 Conditional execution of Advanced SIMD instructions
- I.1.20 Use of ThumbEE instructions
- I.1.21 Deprecations that apply to Debug operation
- Debug Status and Control Register deprecations
- Watchpoint Fault Address Register deprecations
- Escalation of privilege level on CP14 and CP15 accesses in Debug state
- Use of Secure User halting debug
- Reading the Debug Program Counter Sampling Register as register 33
- Escalation of privilege level by Debug state writes to the CPSR
- Use of the CP14 interface to access certain registers and register bits
- Use of CP14 accesses to the DCC when the OS Lock is not set
- Use of a single breakpoint to set breakpoints on more than one instruction
- Use of breakpoint address masks
- Use of a byte address select in DBGWCR that is not continuous
- Use of Vector catch debug events with Monitor debug-mode
- I.2 Obsolete features
- I.3 Use of the SP as a general-purpose register
- I.4 Explicit use of the PC in ARM instructions
- I.5 Deprecated Thumb instructions
- I.1 Deprecated features
- J: Fast Context Switch Extension (FCSE)
- K: VFP Vector Operation Support
- L: ARMv6 Differences
- L.1 Introduction to ARMv6
- L.2 Application level register support
- L.3 Application level memory support
- L.4 Instruction set support
- L.5 System level register support
- L.6 System level memory model
- L.7 System Control coprocessor, CP15, support
- L.7.1 Organization of CP15 registers for an ARMv6 VMSA implementation
- L.7.2 Organization of CP15 registers for an ARMv6 PMSA implementation
- L.7.3 CP15 c0, ID support
- L.7.4 CP15 c1, System control support
- L.7.5 CP15 c1, VMSA Security Extensions support
- L.7.6 CP15 c2 and c3, VMSA memory protection and control registers
- L.7.7 CP15 c5 and c6, VMSA memory system support
- L.7.8 CP15 c5 and c6, PMSA memory system support
- L.7.9 CP15 c6, Watchpoint Fault Address Register, DBGWFAR
- L.7.10 CP15 c7, Cache and branch predictor operations
- L.7.11 CP15 c7, Miscellaneous functions
- L.7.12 CP15 c7, VMSA virtual to physical address translation support
- L.7.13 CP15 c8, VMSA TLB support
- L.7.14 CP15 c9, Cache lockdown support
- L.7.15 CP15 c9, TCM support
- L.7.16 CP15 c9, VMSA support for the Security Extensions
- L.7.17 CP15 c10, VMSA memory remapping support
- L.7.18 CP15 c10, VMSA TLB lockdown support
- L.7.19 CP15 c11, DMA support
- L.7.20 CP15 c12, VMSA support for the Security Extensions
- L.7.21 CP15 c13, Context ID support
- L.7.22 CP15 c15, IMPLEMENTATION DEFINED
- M: v6 Debug and v6.1 Debug Differences
- M.1 About v6 Debug and v6.1 Debug
- M.2 Invasive debug authentication, v6 Debug and v6.1 Debug
- M.3 Debug events, v6 Debug and v6.1 Debug
- M.4 Debug exceptions, v6 Debug and v6.1 Debug
- M.5 Debug state, v6 Debug and v6.1 Debug
- M.6 Debug register interfaces, v6 Debug and v6.1 Debug
- M.7 Reset and powerdown support
- M.8 The Debug Communications Channel and Instruction Transfer Register
- M.9 Non-invasive debug authentication, v6 Debug and v6.1 Debug
- M.10 Sample-based profiling, v6 Debug and v6.1 Debug
- M.11 The debug registers, v6 Debug and v6.1 Debug
- M.11.1 Debug register summary, v6 Debug and v6.1 Debug
- M.11.2 DBGDIDR, Debug ID Register
- M.11.3 DBGDSCR, Debug Status and Control Register, ARMv6
- M.11.4 DBGDTRRX, Host to Target Data Transfer Register
- M.11.5 DBGDTRTX, Target to Host Data Transfer Register
- M.11.6 DBGWFAR, Watchpoint Fault Address Register
- M.11.7 DBGVCR, Vector Catch Register
- M.11.8 DBGDSCCR, Debug State Cache Control Register
- M.11.9 DBGDSMCR, Debug State MMU Control Register
- M.11.10 DBGBCR, Breakpoint Control Registers
- M.11.11 DBGWCR, Watchpoint Control Registers
- M.12 Performance monitors, v6 Debug and v6.1 Debug
- N: Secure User Halting Debug
- N.1 About Secure User halting debug
- N.2 Invasive debug authentication in an implementation that supports SUHD
- N.3 Effects of SUHD on Debug state
- O: ARMv4 and ARMv5 Differences
- O.1 Introduction to ARMv4 and ARMv5
- O.2 Application level register support
- O.3 Application level memory support
- O.4 Instruction set support
- O.5 System level register support
- O.6 System level memory model
- O.7 System Control coprocessor, CP15 support
- O.7.1 Organization of CP15 registers in an ARMv4 or ARMv5 VMSA implementation
- O.7.2 Organization of CP15 registers in an ARMv4 or ARMv5 PMSA implementation
- O.7.3 CP15 c0, ID support
- O.7.4 CP15 c1, System control register support
- O.7.5 CP15 c2 and c3, VMSA memory protection and control registers
- O.7.6 CP15 c5 and c6, VMSA memory system support
- O.7.7 CP15 c2, c3, c5, and c6, PMSA support
- CP15 c2, Memory Region Cacheability Registers, DCR and ICR, ARMv4 and ARMv5
- CP15 c3, Memory Region Bufferability Register, DBR, ARMv4 and ARMv5
- CP15 c5, Memory Region Access Permissions Registers, DAPR and IAPR, ARMv4 and ARMv5
- CP15 c5, Memory Region Extended Access Permissions Registers, DEAPR and IEAPR, ARMv4 and ARMv5
- CP15 c6, Memory Region Registers, DMRR0-DMRR7 and IMRR0-IMRR7, ARMv4 and ARMv5
- O.7.8 CP15 c7, Cache and branch predictor operations
- O.7.9 CP15 c7, Miscellaneous functions
- O.7.10 CP15 c8, VMSA TLB support
- O.7.11 CP15 c9, cache lockdown support
- O.7.12 CP15 c9, TCM support
- O.7.13 CP15 c10, TLB lockdown support, VMSA
- O.7.14 CP15 c13, VMSA FCSE support
- O.7.15 CP15 c15, IMPLEMENTATION DEFINED
- P: Pseudocode Definition
- P.1 About the ARMv7 pseudocode
- P.2 Pseudocode for instruction descriptions
- P.3 Data types
- P.4 Expressions
- P.5 Operators and built-in functions
- P.5.1 Operations on generic types
- P.5.2 Operations on Booleans
- P.5.3 Bitstring manipulation
- Bitstring length and most significant bit
- Bitstring concatenation and replication
- Bitstring extraction
- Logical operations on bitstrings
- Bitstring count
- Testing a bitstring for being all zero or all ones
- Lowest and highest set bits of a bitstring
- Zero-extension and sign-extension of bitstrings
- Converting bitstrings to integers
- P.5.4 Arithmetic
- P.6 Statements and program structure
- P.7 Miscellaneous helper procedures and functions
- P.7.1 ArchVersion()
- P.7.2 Breakpoint()
- P.7.3 EndOfInstruction()
- P.7.4 GenerateAlignmentException()
- P.7.5 GenerateCoprocessorException()
- P.7.6 GenerateIntegerZeroDivide()
- P.7.7 HaveLPAE()
- P.7.8 HaveMPExt()
- P.7.9 HaveVirtExt()
- P.7.10 Hint_Debug()
- P.7.11 Hint_PreloadData()
- P.7.12 Hint_PreloadDataForWrite()
- P.7.13 Hint_PreloadInstr()
- P.7.14 Hint_Yield()
- P.7.15 InstrIsPL0Undefined()
- P.7.16 IntegerZeroDivideTrappingEnabled()
- P.7.17 IsExternalAbort()
- P.7.18 IsAlignmentFault()
- P.7.19 IsAsyncAbort()
- P.7.20 JazelleAcceptsExecution()
- P.7.21 LSInstructionSyndrome()
- P.7.22 MemorySystemArchitecture()
- P.7.23 ProcessorID()
- P.7.24 RemapRegsHaveResetValues()
- P.7.25 SwitchToJazelleExecution()
- P.7.26 ThisInstr()
- P.7.27 ThisInstrLength()
- P.7.28 TLBLookupCameFromCacheMaintenance()
- P.7.29 UnalignedSupport()
- Q: Pseudocode Index
- R: Register Index
- Glossary