ARM Architecture Reference Manual ARMv7 A And R Edition
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ARM Architecture Reference Manual
®
ARMv7-A and ARMv7-R edition
Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
ARM DDI 0406C.b (ID072512)
ARM Architecture Reference Manual
ARMv7-A and ARMv7-R edition
Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
Release Information
The following changes have been made to this document.
Change History
Date
Issue
Confidentiality
Change
05 April 2007
A
Non-Confidential
New edition for ARMv7-A and ARMv7-R architecture profiles.
Document number changed from ARM DDI 0100 to ARM DDI 0406 and contents restructured.
29 April 2008
B
Non-Confidential
Addition of the VFP Half-precision and Multiprocessing Extensions, and many clarifications and enhancements.
23 November 2011
C (C.a)
Non-Confidential
Addition of the Virtualization Extensions, Large Physical Address Extension, Generic Timer Extension, and other
additions. Many other clarifications and enhancements.
24 July 2012
C.b
Non-Confidential
Errata release for issue C.a.
Note that issue C.a, the first publication of issue C of this manual, was originally identified as issue C.
From ARMv7, the ARM® architecture defines different architectural profiles and this edition of this manual describes only the A
and R profiles. For details of the documentation of the ARMv7-M profile see Additional reading on page xxiii. Before ARMv7
there was only a single ARM Architecture Reference Manual, with document number DDI 0100. The first issue of this was in
February 1996, and the final issue, issue I, was in July 2005. For more information see Additional reading on page xxiii.
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The term ARM can refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the ARM architecture.
The context makes it clear when the term is used in this way.
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iii
iv
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Non-Confidential
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Contents
ARM Architecture Reference Manual ARMv7-A and
ARMv7-R edition
Preface
About this manual ..................................................................................................... xiv
Using this manual ...................................................................................................... xvi
Conventions .............................................................................................................. xxi
Additional reading ................................................................................................... xxiii
Feedback ................................................................................................................ xxiv
Part A
Application Level Architecture
Chapter A1
Introduction to the ARM Architecture
A1.1
A1.2
A1.3
A1.4
A1.5
Chapter A2
A1-28
A1-29
A1-30
A1-32
A1-35
Application Level Programmers’ Model
A2.1
A2.2
A2.3
A2.4
A2.5
A2.6
A2.7
A2.8
A2.9
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About the ARM architecture ................................................................................
The instruction sets .............................................................................................
Architecture versions, profiles, and variants ........................................................
Architecture extensions .......................................................................................
The ARM memory model ....................................................................................
About the Application level programmers’ model ................................................
ARM core data types and arithmetic ...................................................................
ARM core registers .............................................................................................
The Application Program Status Register (APSR) ..............................................
Execution state registers .....................................................................................
Advanced SIMD and Floating-point Extensions ..................................................
Floating-point data types and arithmetic .............................................................
Polynomial arithmetic over {0, 1} .........................................................................
Coprocessor support ...........................................................................................
Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
Non-Confidential
A2-38
A2-40
A2-45
A2-49
A2-50
A2-54
A2-63
A2-93
A2-94
v
Contents
A2.10
A2.11
A2.12
Chapter A3
Application Level Memory Model
A3.1
A3.2
A3.3
A3.4
A3.5
A3.6
A3.7
A3.8
A3.9
Chapter A4
Address space ..................................................................................................
Alignment support .............................................................................................
Endian support ..................................................................................................
Synchronization and semaphores .....................................................................
Memory types and attributes and the memory order model ..............................
Access rights .....................................................................................................
Virtual and physical addressing ........................................................................
Memory access order ........................................................................................
Caches and memory hierarchy .........................................................................
A3-106
A3-108
A3-110
A3-114
A3-125
A3-141
A3-144
A3-145
A3-155
The Instruction Sets
A4.1
A4.2
A4.3
A4.4
A4.5
A4.6
A4.7
A4.8
A4.9
A4.10
A4.11
A4.12
A4.13
A4.14
Chapter A5
About the instruction sets ..................................................................................
Unified Assembler Language ............................................................................
Branch instructions ............................................................................................
Data-processing instructions .............................................................................
Status register access instructions ....................................................................
Load/store instructions ......................................................................................
Load/store multiple instructions .........................................................................
Miscellaneous instructions ................................................................................
Exception-generating and exception-handling instructions ...............................
Coprocessor instructions ...................................................................................
Advanced SIMD and Floating-point load/store instructions ...............................
Advanced SIMD and Floating-point register transfer instructions .....................
Advanced SIMD data-processing instructions ...................................................
Floating-point data-processing instructions .......................................................
A4-160
A4-162
A4-164
A4-165
A4-174
A4-175
A4-177
A4-178
A4-179
A4-180
A4-181
A4-183
A4-184
A4-191
ARM Instruction Set Encoding
A5.1
A5.2
A5.3
A5.4
A5.5
A5.6
A5.7
Chapter A6
ARM instruction set encoding ...........................................................................
Data-processing and miscellaneous instructions ..............................................
Load/store word and unsigned byte ..................................................................
Media instructions .............................................................................................
Branch, branch with link, and block data transfer ..............................................
Coprocessor instructions, and Supervisor Call .................................................
Unconditional instructions .................................................................................
A5-194
A5-196
A5-208
A5-209
A5-214
A5-215
A5-216
Thumb Instruction Set Encoding
A6.1
A6.2
A6.3
Chapter A7
Thumb instruction set encoding ........................................................................ A6-220
16-bit Thumb instruction encoding .................................................................... A6-223
32-bit Thumb instruction encoding .................................................................... A6-230
Advanced SIMD and Floating-point Instruction Encoding
A7.1
A7.2
A7.3
A7.4
A7.5
A7.6
A7.7
A7.8
A7.9
Chapter A8
Overview ...........................................................................................................
Advanced SIMD and Floating-point instruction syntax ......................................
Register encoding .............................................................................................
Advanced SIMD data-processing instructions ...................................................
Floating-point data-processing instructions .......................................................
Extension register load/store instructions ..........................................................
Advanced SIMD element or structure load/store instructions ...........................
8, 16, and 32-bit transfer between ARM core and extension registers .............
64-bit transfers between ARM core and extension registers .............................
A7-254
A7-255
A7-259
A7-261
A7-272
A7-274
A7-275
A7-278
A7-279
Instruction Details
A8.1
vi
Thumb Execution Environment ........................................................................... A2-95
Jazelle direct bytecode execution support .......................................................... A2-97
Exceptions, debug events and checks .............................................................. A2-102
Format of instruction descriptions ..................................................................... A8-282
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Contents
A8.2
A8.3
A8.4
A8.5
A8.6
A8.7
A8.8
Chapter A9
A8-287
A8-288
A8-291
A8-294
A8-295
A8-296
A8-300
The ThumbEE Instruction Set
A9.1
A9.2
A9.3
A9.4
A9.5
Part B
About the ThumbEE instruction set .................................................................
ThumbEE instruction set encoding .................................................................
Additional instructions in Thumb and ThumbEE instruction sets ....................
ThumbEE instructions with modified behavior ................................................
Additional ThumbEE instructions ....................................................................
A9-1112
A9-1115
A9-1116
A9-1117
A9-1123
System Level Architecture
Chapter B1
The System Level Programmers’ Model
B1.1
B1.2
B1.3
B1.4
B1.5
B1.6
B1.7
B1.8
B1.9
B1.10
B1.11
B1.12
B1.13
B1.14
Chapter B2
About the System level programmers’ model ..................................................
System level concepts and terminology ..........................................................
ARM processor modes and ARM core registers .............................................
Instruction set states .......................................................................................
The Security Extensions .................................................................................
The Large Physical Address Extension ...........................................................
The Virtualization Extensions ..........................................................................
Exception handling ..........................................................................................
Exception descriptions ....................................................................................
Coprocessors and system control ...................................................................
Advanced SIMD and floating-point support .....................................................
Thumb Execution Environment .......................................................................
Jazelle direct bytecode execution ...................................................................
Traps to the hypervisor ...................................................................................
B1-1134
B1-1135
B1-1139
B1-1155
B1-1156
B1-1159
B1-1161
B1-1164
B1-1204
B1-1225
B1-1228
B1-1239
B1-1240
B1-1247
Common Memory System Architecture Features
B2.1
B2.2
B2.3
B2.4
Chapter B3
About the memory system architecture ...........................................................
Caches and branch predictors ........................................................................
IMPLEMENTATION DEFINED memory system features ...............................
Pseudocode details of general memory system operations ............................
B2-1264
B2-1266
B2-1291
B2-1292
Virtual Memory System Architecture (VMSA)
B3.1
B3.2
B3.3
B3.4
B3.5
B3.6
B3.7
B3.8
B3.9
B3.10
B3.11
B3.12
B3.13
B3.14
B3.15
B3.16
B3.17
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Standard assembler syntax fields .....................................................................
Conditional execution ........................................................................................
Shifts applied to a register .................................................................................
Memory accesses .............................................................................................
Encoding of lists of ARM core registers ............................................................
Additional pseudocode support for instruction descriptions ..............................
Alphabetical list of instructions ..........................................................................
About the VMSA ..............................................................................................
The effects of disabling MMUs on VMSA behavior .........................................
Translation tables ............................................................................................
Secure and Non-secure address spaces ........................................................
Short-descriptor translation table format .........................................................
Long-descriptor translation table format ..........................................................
Memory access control ...................................................................................
Memory region attributes ................................................................................
Translation Lookaside Buffers (TLBs) .............................................................
TLB maintenance requirements ......................................................................
Caches in a VMSA implementation .................................................................
VMSA memory aborts .....................................................................................
Exception reporting in a VMSA implementation ..............................................
Virtual Address to Physical Address translation operations ............................
About the system control registers for VMSA ..................................................
Organization of the CP14 registers in a VMSA implementation ......................
Organization of the CP15 registers in a VMSA implementation ......................
Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
Non-Confidential
B3-1308
B3-1314
B3-1318
B3-1323
B3-1324
B3-1338
B3-1356
B3-1366
B3-1378
B3-1381
B3-1392
B3-1395
B3-1409
B3-1438
B3-1444
B3-1468
B3-1469
vii
Contents
B3.18
B3.19
Chapter B4
System Control Registers in a VMSA implementation
B4.1
B4.2
Chapter B5
VMSA System control registers descriptions, in register order ....................... B4-1522
VMSA system control operations described by function ................................. B4-1740
Protected Memory System Architecture (PMSA)
B5.1
B5.2
B5.3
B5.4
B5.5
B5.6
B5.7
B5.8
B5.9
B5.10
Chapter B6
About the PMSA ..............................................................................................
Memory access control ...................................................................................
Memory region attributes ................................................................................
PMSA memory aborts .....................................................................................
Exception reporting in a PMSA implementation ..............................................
About the system control registers for PMSA ..................................................
Organization of the CP14 registers in a PMSA implementation ......................
Organization of the CP15 registers in a PMSA implementation ......................
Functional grouping of PMSAv7 system control registers ...............................
Pseudocode details of PMSA memory system operations ..............................
B5-1754
B5-1759
B5-1760
B5-1763
B5-1767
B5-1772
B5-1784
B5-1785
B5-1797
B5-1804
System Control Registers in a PMSA implementation
B6.1
B6.2
Chapter B7
PMSA System control registers descriptions, in register order ....................... B6-1808
PMSA system control operations described by function ................................. B6-1941
The CPUID Identification Scheme
B7.1
B7.2
B7.3
Chapter B8
Introduction to the CPUID scheme .................................................................. B7-1948
The CPUID registers ....................................................................................... B7-1949
Advanced SIMD and Floating-point Extension feature identification registers B7-1955
The Generic Timer
B8.1
B8.2
Chapter B9
About the Generic Timer ................................................................................. B8-1958
Generic Timer registers summary ................................................................... B8-1967
System Instructions
B9.1
B9.2
B9.3
Part C
General restrictions on system instructions ..................................................... B9-1970
Encoding and use of Banked register transfer instructions ............................. B9-1971
Alphabetical list of instructions ........................................................................ B9-1976
Debug Architecture
Chapter C1
Introduction to the ARM Debug Architecture
C1.1
C1.2
C1.3
C1.4
Chapter C2
Scope of part C of this manual ........................................................................
About the ARM Debug architecture ................................................................
Security Extensions and debug .......................................................................
Register interfaces ..........................................................................................
C1-2020
C1-2021
C1-2025
C1-2026
Invasive Debug Authentication
C2.1
C2.2
C2.3
C2.4
Chapter C3
About invasive debug authentication ..............................................................
Invasive debug with no Security Extensions ...................................................
Invasive debug with the Security Extensions ..................................................
Invasive debug authentication security considerations ...................................
C2-2028
C2-2029
C2-2031
C2-2033
Debug Events
C3.1
C3.2
C3.3
C3.4
viii
Functional grouping of VMSAv7 system control registers ............................... B3-1491
Pseudocode details of VMSA memory system operations .............................. B3-1503
About debug events ........................................................................................
BKPT instruction debug events .......................................................................
Breakpoint debug events ................................................................................
Watchpoint debug events ................................................................................
Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
Non-Confidential
C3-2036
C3-2038
C3-2039
C3-2057
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Contents
C3.5
C3.6
C3.7
C3.8
C3.9
Chapter C4
C3-2065
C3-2073
C3-2074
C3-2076
C3-2078
Debug Exceptions
C4.1
C4.2
Chapter C5
About debug exceptions .................................................................................. C4-2088
Avoiding debug exceptions that might cause UNPREDICTABLE behavior .... C4-2090
Debug State
C5.1
C5.2
C5.3
C5.4
C5.5
C5.6
C5.7
Chapter C6
About Debug state ..........................................................................................
Entering Debug state ......................................................................................
Executing instructions in Debug state .............................................................
Behavior of non-invasive debug in Debug state ..............................................
Exceptions in Debug state ..............................................................................
Memory system behavior in Debug state ........................................................
Exiting Debug state .........................................................................................
C5-2092
C5-2093
C5-2096
C5-2104
C5-2105
C5-2109
C5-2110
Debug Register Interfaces
C6.1
C6.2
C6.3
C6.4
C6.5
C6.6
C6.7
Chapter C7
About the debug register interfaces ................................................................
Synchronization of debug register updates .....................................................
Access permissions ........................................................................................
The CP14 debug register interface .................................................................
The memory-mapped and recommended external debug interfaces ..............
Summary of the v7 Debug register interfaces .................................................
Summary of the v7.1 Debug register interfaces ..............................................
C6-2114
C6-2115
C6-2117
C6-2121
C6-2126
C6-2128
C6-2137
Debug Reset and Powerdown Support
C7.1
C7.2
C7.3
C7.4
Chapter C8
Debug guidelines for systems with energy management capability ................
Power domains and debug .............................................................................
The OS Save and Restore mechanism ...........................................................
Reset and debug .............................................................................................
C7-2148
C7-2149
C7-2152
C7-2160
The Debug Communications Channel and Instruction Transfer Register
C8.1
C8.2
C8.3
C8.4
Chapter C9
About the DCC and DBGITR ..........................................................................
Operation of the DCC and Instruction Transfer Register ................................
Behavior of accesses to the DCC registers and DBGITR ...............................
Synchronization of accesses to the DCC and the DBGITR ............................
C8-2164
C8-2167
C8-2171
C8-2176
Non-invasive Debug Authentication
C9.1
C9.2
C9.3
Chapter C10
About non-invasive debug authentication ....................................................... C9-2182
Non-invasive debug authentication ................................................................. C9-2183
Effects of non-invasive debug authentication .................................................. C9-2185
Sample-based Profiling
C10.1
Chapter C11
Sample-based profiling ................................................................................. C10-2188
The Debug Registers
C11.1
C11.2
C11.3
C11.4
C11.5
C11.6
C11.7
C11.8
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Vector catch debug events ..............................................................................
Halting debug events ......................................................................................
Generation of debug events ............................................................................
Debug event prioritization ...............................................................................
Pseudocode details of Software debug events ...............................................
About the debug registers .............................................................................
Debug register summary ...............................................................................
Debug identification registers ........................................................................
Control and status registers ..........................................................................
Instruction and data transfer registers ...........................................................
Software debug event registers ....................................................................
Sample-based profiling registers ...................................................................
OS Save and Restore registers ....................................................................
Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
Non-Confidential
C11-2192
C11-2193
C11-2196
C11-2197
C11-2198
C11-2199
C11-2200
C11-2201
ix
Contents
C11.9 Memory system control registers .................................................................. C11-2202
C11.10 Management registers .................................................................................. C11-2203
C11.11 Register descriptions, in register order .......................................................... C11-2209
Chapter C12
The Performance Monitors Extension
C12.1
C12.2
C12.3
C12.4
C12.5
C12.6
C12.7
C12.8
C12.9
Part D
C12-2300
C12-2304
C12-2305
C12-2307
C12-2309
C12-2311
C12-2312
C12-2313
C12-2326
Appendixes
Appendix A
Recommended External Debug Interface
A.1
A.2
A.3
A.4
A.5
Appendix B
About the recommended external debug interface ...................................
Authentication signals ...............................................................................
Run-control and cross-triggering signals ...................................................
Recommended debug slave port ..............................................................
Other debug signals ..................................................................................
AppxA-2336
AppxA-2338
AppxA-2340
AppxA-2344
AppxA-2346
Recommended Memory-mapped and External Debug Interfaces for the
Performance Monitors
B.1
B.2
Appendix C
About the memory-mapped views of the Performance Monitors registers AppxB-2352
PMU register descriptions for memory-mapped register views ................. AppxB-2361
Recommendations for Performance Monitors Event Numbers for
IMPLEMENTATION DEFINED Events
C.1
Appendix D
ARM recommendations for IMPLEMENTATION DEFINED event numbers AppxC-2376
Example OS Save and Restore Sequences for External Debug Over
Powerdown
D.1
D.2
Appendix E
Example OS Save and Restore sequences for v7 Debug ........................ AppxD-2388
Example OS Save and Restore sequences for v7.1 Debug ..................... AppxD-2392
System Level Implementation of the Generic Timer
E.1
E.2
E.3
E.4
E.5
E.6
E.7
E.8
E.9
Appendix F
About the Generic Timer specification ......................................................
Memory-mapped counter module .............................................................
Counter module control and status register summary ...............................
About the memory-mapped view of the counter and timer ........................
The CNTBaseN and CNTPL0BaseN frames ............................................
The CNTCTLBase frame ...........................................................................
System level Generic Timer register descriptions, in register order ..........
Providing a complete set of counter and timer features ............................
Gray-count scheme for timer distribution scheme .....................................
AppxE-2396
AppxE-2397
AppxE-2400
AppxE-2402
AppxE-2403
AppxE-2405
AppxE-2406
AppxE-2423
AppxE-2425
Common VFP Subarchitecture Specification
F.1
F.2
F.3
F.4
F.5
F.6
x
About the Performance Monitors ..................................................................
Accuracy of the Performance Monitors .........................................................
Behavior on overflow .....................................................................................
Effect of the Security Extensions and Virtualization Extensions ...................
Event filtering, PMUv2 ...................................................................................
Counter enables ............................................................................................
Counter access .............................................................................................
Event numbers and mnemonics ....................................................................
Performance Monitors registers ....................................................................
Scope of this appendix .............................................................................. AppxF-2429
Introduction to the Common VFP subarchitecture .................................... AppxF-2430
Exception processing ................................................................................ AppxF-2432
Support code requirements ....................................................................... AppxF-2436
Context switching ...................................................................................... AppxF-2438
Subarchitecture additions to the Floating-point Extension system registers AppxF-2439
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Contents
F.7
Appendix G
Barrier Litmus Tests
G.1
G.2
G.3
G.4
G.5
Appendix H
Introduction ...............................................................................................
Simple ordering and barrier cases ............................................................
Exclusive accesses and barriers ...............................................................
Using a mailbox to send an interrupt .........................................................
Cache and TLB maintenance operations and barriers ..............................
AppxG-2448
AppxG-2451
AppxG-2458
AppxG-2460
AppxG-2461
Legacy Instruction Mnemonics
H.1
H.2
H.3
Appendix I
Thumb instruction mnemonics .................................................................. AppxH-2468
Other UAL mnemonic changes ................................................................. AppxH-2469
Pre-UAL pseudo-instruction NOP ............................................................. AppxH-2472
Deprecated and Obsolete Features
I.1
I.2
I.3
I.4
I.5
Appendix J
Deprecated features .................................................................................... AppxI-2474
Obsolete features ........................................................................................ AppxI-2483
Use of the SP as a general-purpose register .............................................. AppxI-2484
Explicit use of the PC in ARM instructions .................................................. AppxI-2485
Deprecated Thumb instructions .................................................................. AppxI-2486
Fast Context Switch Extension (FCSE)
J.1
J.2
J.3
Appendix K
About the FCSE ......................................................................................... AppxJ-2488
Modified virtual addresses ......................................................................... AppxJ-2489
Debug and trace ......................................................................................... AppxJ-2491
VFP Vector Operation Support
K.1
K.2
K.3
K.4
Appendix L
About VFP vector mode ............................................................................
Vector length and stride control ................................................................
VFP register banks ....................................................................................
VFP instruction type selection ...................................................................
AppxK-2494
AppxK-2495
AppxK-2496
AppxK-2497
ARMv6 Differences
L.1
L.2
L.3
L.4
L.5
L.6
L.7
Appendix M
Introduction to ARMv6 ................................................................................ AppxL-2500
Application level register support ............................................................... AppxL-2501
Application level memory support .............................................................. AppxL-2504
Instruction set support ................................................................................ AppxL-2508
System level register support ..................................................................... AppxL-2513
System level memory model ...................................................................... AppxL-2516
System Control coprocessor, CP15, support ............................................. AppxL-2523
v6 Debug and v6.1 Debug Differences
M.1
M.2
M.3
M.4
M.5
M.6
M.7
M.8
M.9
M.10
M.11
M.12
Appendix N
About v6 Debug and v6.1 Debug .............................................................. AppxM-2548
Invasive debug authentication, v6 Debug and v6.1 Debug ....................... AppxM-2549
Debug events, v6 Debug and v6.1 Debug ................................................ AppxM-2550
Debug exceptions, v6 Debug and v6.1 Debug .......................................... AppxM-2554
Debug state, v6 Debug and v6.1 Debug ................................................... AppxM-2555
Debug register interfaces, v6 Debug and v6.1 Debug .............................. AppxM-2559
Reset and powerdown support ................................................................. AppxM-2562
The Debug Communications Channel and Instruction Transfer Register . AppxM-2563
Non-invasive debug authentication, v6 Debug and v6.1 Debug ............... AppxM-2564
Sample-based profiling, v6 Debug and v6.1 Debug .................................. AppxM-2566
The debug registers, v6 Debug and v6.1 Debug ...................................... AppxM-2567
Performance monitors, v6 Debug and v6.1 Debug ................................... AppxM-2578
Secure User Halting Debug
N.1
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Earlier versions of the Common VFP subarchitecture .............................. AppxF-2446
About Secure User halting debug ............................................................. AppxN-2580
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N.2
N.3
Appendix O
Invasive debug authentication in an implementation that supports SUHD AppxN-2581
Effects of SUHD on Debug state ............................................................... AppxN-2582
ARMv4 and ARMv5 Differences
O.1
O.2
O.3
O.4
O.5
O.6
O.7
Appendix P
Introduction to ARMv4 and ARMv5 ...........................................................
Application level register support ..............................................................
Application level memory support .............................................................
Instruction set support ...............................................................................
System level register support ....................................................................
System level memory model .....................................................................
System Control coprocessor, CP15 support .............................................
AppxO-2588
AppxO-2589
AppxO-2590
AppxO-2595
AppxO-2601
AppxO-2604
AppxO-2612
Pseudocode Definition
P.1
P.2
P.3
P.4
P.5
P.6
P.7
Appendix Q
About the ARMv7 pseudocode .................................................................
Pseudocode for instruction descriptions ....................................................
Data types .................................................................................................
Expressions ...............................................................................................
Operators and built-in functions ................................................................
Statements and program structure ............................................................
Miscellaneous helper procedures and functions .......................................
AppxP-2642
AppxP-2643
AppxP-2645
AppxP-2649
AppxP-2651
AppxP-2656
AppxP-2660
Pseudocode Index
Q.1
Q.2
Appendix R
Pseudocode operators and keywords ....................................................... AppxQ-2666
Pseudocode functions and procedures ..................................................... AppxQ-2669
Register Index
R.1
R.2
Alphabetic index of ARMv7 registers, by register name ............................ AppxR-2684
Full registers index .................................................................................... AppxR-2695
Glossary
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Preface
This preface introduces the ARM® Architecture Reference Manual, ARM®v7-A and ARM®v7-R edition. It contains
the following sections:
•
About this manual on page xiv
•
Using this manual on page xvi
•
Conventions on page xxi
•
Additional reading on page xxiii
•
Feedback on page xxiv.
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xiii
Preface
About this manual
About this manual
This manual describes the A and R profiles of the ARM® architecture v7, ARMv7. It includes descriptions of:
•
The processor instruction sets:
—
the original ARM instruction set
—
the high code density Thumb® instruction set
—
the ThumbEE instruction set, that includes specific support for Just-In-Time (JIT) or Ahead-Of-Time
(AOT) compilation.
•
The modes and states that determine how a processor operates, including the current execution privilege and
security.
•
The exception model.
•
The memory model, that defines memory ordering and memory management:
—
the ARMv7-A architecture profile defines a Virtual Memory System Architecture (VMSA)
—
the ARMv7-R architecture profile defines a Protected Memory System Architecture (PMSA).
•
The programmers’ model, and its use of a coprocessor interface to access system control registers that control
most processor and memory system features.
•
The OPTIONAL Floating-point (VFP) Extension, that provides high-performance floating-point instructions
that support:
—
single-precision and double-precision operations
—
conversions between double-precision, single-precision, and half-precision floating-point values.
•
The OPTIONAL Advanced SIMD Extension, that provides high-performance integer and single-precision
floating-point vector operations.
•
The OPTIONAL Security Extensions, that facilitate the development of secure applications.
•
The OPTIONAL Virtualization Extensions, that support the virtualization of Non-secure operation.
•
The Debug architecture, that provides software access to debug features in the processor.
Note
ARMv7 introduces the architecture profiles. A separate Architecture Reference Manual describes the third profile,
the Microcontroller profile, ARMv7-M. For more information see Architecture versions, profiles, and variants on
page A1-30.
This manual gives the assembler syntax for the instructions it describes, meaning it can specify instructions in
textual form. However, this manual is not a tutorial for ARM assembler language, nor does it describe ARM
assembler language, except at a very basic level. To make effective use of ARM assembler language, read the
documentation supplied with the assembler being used.
This manual is organized into parts:
Part A
Describes the application level view of the architecture. It describes the application level view of
the programmers’ model and the memory model. It also describes the precise effects of each
instruction in User mode, the normal operating mode, including any restrictions on its use. This
information is of primary importance to authors and users of compilers, assemblers, and other
programs that generate ARM machine code. Software execution in User mode is at the PL0
privilege level, also described as unprivileged.
Note
User mode is the only mode where software execution is unprivileged.
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About this manual
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Part B
Describes the system level view of the architecture. It gives details of system registers, most of
which are not accessible from PL0, and the system level view of the memory model. It also gives
full details of the effects of instructions executed with some level of privilege, where these are
different from their effects in unprivileged execution.
Part C
Describes the Debug architecture. This is an extension to the ARM architecture that provides
configuration, breakpoint and watchpoint support, and a Debug Communications Channel (DCC)
to a debug host.
Appendixes
Provide additional information that is not part of the ARMv7 architectural requirements, including
descriptions of:
•
features that are recommended but not required
•
differences in previous versions of the architecture.
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Preface
Using this manual
Using this manual
The information in this manual is organized into parts, as described in this section.
Part A, Application Level Architecture
Part A describes the application level view of the architecture. It contains the following chapters:
Chapter A1 Introduction to the ARM Architecture
Gives an overview of the ARM architecture, and the ARM and Thumb instruction sets.
Chapter A2 Application Level Programmers’ Model
Describes the application level view of the ARM programmers’ model, including the application
level view of the Advanced SIMD and Floating-point Extensions. It describes the types of values
that ARM instructions operate on, the ARM core registers that contain those values, and the
Application Program Status Register.
Chapter A3 Application Level Memory Model
Describes the application level view of the memory model, including the ARM memory types and
attributes, and memory access control.
Chapter A4 The Instruction Sets
Describes the range of instructions available in the ARM, Thumb, Advanced SIMD, and VFP
instruction sets. It also contains some details of instruction operation that are common to several
instructions.
Chapter A5 ARM Instruction Set Encoding
Describes the encoding of the ARM instruction set.
Chapter A6 Thumb Instruction Set Encoding
Describes the encoding of the Thumb instruction set.
Chapter A7 Advanced SIMD and Floating-point Instruction Encoding
Describes the encoding of the Advanced SIMD and Floating-point Extension (VFP) instruction sets.
Chapter A8 Instruction Details
Gives a full description of every instruction available in the Thumb, ARM, Advanced SIMD, and
Floating-point Extension instruction sets, with the exception of information only relevant to
execution with some level of privilege.
Chapter A9 The ThumbEE Instruction Set
Gives a full description of the Thumb Execution Environment variant of the Thumb instruction set.
This means it describes the ThumbEE instruction set.
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Using this manual
Part B, System Level Architecture
Part B describes the system level view of the architecture. It contains the following chapters:
Chapter B1 The System Level Programmers’ Model
Describes the system level view of the programmers’ model.
Chapter B2 Common Memory System Architecture Features
Describes the system level view of the memory model features that are common to all memory
systems.
Chapter B3 Virtual Memory System Architecture (VMSA)
Describes the system level view of the Virtual Memory System Architecture (VMSA) that is part of
all ARMv7-A implementations. This chapter includes a description of the organization and general
properties of the system control registers in a VMSA implementation.
Chapter B4 System Control Registers in a VMSA implementation
Describes all of the system control registers in VMSA implementation, including the registers that
are part of the OPTIONAL extensions to a VMSA implementation. The registers are described in
alphabetical order.
Chapter B5 Protected Memory System Architecture (PMSA)
Describes the system level view of the Protected Memory System Architecture (PMSA) that is part
of all ARMv7-R implementations. This chapter includes a description of the organization and
general properties of the system control registers in a PMSA implementation.
Chapter B6 System Control Registers in a PMSA implementation
Describes all of the system control registers in PMSA implementation, including the registers that
are part of the OPTIONAL extensions to a PMSA implementation. The registers are described in
alphabetical order.
Chapter B7 The CPUID Identification Scheme
Describes the CPUID scheme. This provides registers that identify the architecture version and
many features of the processor implementation. This chapter also describes the registers that
identify the implemented Advanced SIMD and VFP features, if any.
Chapter B8 The Generic Timer
Describes the OPTIONAL Generic Timer architecture extension.
Chapter B9 System Instructions
Provides detailed reference information about system instructions, and more information about
instructions that behave differently when executed with some level of privilege.
Part C, Debug Architecture
Part C describes the Debug architecture. It contains the following chapters:
Chapter C1 Introduction to the ARM Debug Architecture
Introduces the Debug architecture, defining the scope of this part of the manual.
Chapter C2 Invasive Debug Authentication
Describes the authentication of invasive debug.
Chapter C3 Debug Events
Describes the debug events.
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Using this manual
Chapter C4 Debug Exceptions
Describes the debug exceptions that handle debug events when the processor is configured for
Monitor debug-mode.
Chapter C5 Debug State
Describes Debug state that is entered if a debug event occurs when the processor is configured for
Halting debug-mode.
Chapter C6 Debug Register Interfaces
Describes the permitted debug register interfaces and the options for their implementation.
Chapter C7 Debug Reset and Powerdown Support
Describes the reset and powerdown support in the Debug architecture, including support for debug
over powerdown.
Chapter C8 The Debug Communications Channel and Instruction Transfer Register
Describes the Debug Communication Channel (DCC) and Instruction Transfer Register (ITR), and
how an external debugger uses these features to communicate with the debug logic.
Chapter C9 Non-invasive Debug Authentication
Describes the authentication of non-invasive debug.
Chapter C10 Sample-based Profiling
Describes sample-based profiling, that provides sampling of the program counter.
Chapter C11 The Debug Registers
Describes the debug registers.
Chapter C12 The Performance Monitors Extension
Describes the OPTIONAL Performance Monitors Extension.
Part D, Appendixes
This manual contains the following appendixes:
Appendix A Recommended External Debug Interface
Describes the recommended external interface to the ARM debug architecture.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix B Recommended Memory-mapped and External Debug Interfaces for the Performance Monitors
Describes the recommended external interfaces to the Performance Monitors Extension.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
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Using this manual
Appendix C Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION
DEFINED Events
Gives the ARM recommendations for the use of the event numbers in the IMPLEMENTATION
DEFINED event number space.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix D Example OS Save and Restore Sequences for External Debug Over Powerdown
Gives software examples that perform the OS Save and Restore sequences, for v7 Debug and v7.1
Debug implementations.
Note
Chapter C7 Debug Reset and Powerdown Support describes the OS Save and Restore mechanism,
for both v7 Debug and v7.1 Debug.
Appendix E System Level Implementation of the Generic Timer
Contains the ARM Generic Timer architecture specification for the memory-mapped interface to
the Generic Timer.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix F Common VFP Subarchitecture Specification
Defines version 2 of the Common VFP Subarchitecture.
Note
This specification is not part of the ARM architecture specification. This sub-architectural
information is included here as supplementary information, for the convenience of developers and
users who might require this information.
Appendix G Barrier Litmus Tests
Gives examples of the use of the barrier instructions provided by the ARMv7 architecture.
Note
These examples are not part of the ARM architecture specification. They are included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix H Legacy Instruction Mnemonics
Describes the legacy mnemonics and their Unified Assembler Language equivalents.
Appendix I Deprecated and Obsolete Features
Lists the deprecated architectural features, with references to their descriptions in parts A to C of
the manual.
Appendix J Fast Context Switch Extension (FCSE)
Describes the Fast Context Switch Extension (FCSE). See the appendix for information about the
status of this in different versions of the ARM architecture.
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Appendix K VFP Vector Operation Support
Describes the VFP vector operations. ARM deprecates the use of these operations.
Appendix L ARMv6 Differences
Describes how the ARMv6 architecture differs from the description given in parts A and B of this
manual.
Appendix M v6 Debug and v6.1 Debug Differences
Describes how the two debug architectures for ARMv6 differ from the description given in part C
of this manual.
Appendix N Secure User Halting Debug
Describes the Secure User halting debug (SUHD) feature.
Appendix O ARMv4 and ARMv5 Differences
Describes how the ARMv4 and ARMv5 architectures differ from the description given in parts A
and B of this manual.
Appendix P Pseudocode Definition
The formal definition of the pseudocode used in this manual.
Appendix Q Pseudocode Index
Gives indexes to definitions of pseudocode operators, keywords, functions, and procedures.
Appendix R Register Index
Gives indexes to register descriptions in the manual.
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Preface
Conventions
Conventions
The following sections describe conventions that this book can use:
•
Typographic conventions
•
Signals
•
Numbers on page xxii
•
Pseudocode descriptions on page xxii
•
Assembler syntax descriptions on page xxii.
Typographic conventions
The typographical conventions are:
italic
Introduces special terminology, and denotes citations.
bold
Denotes signal names, and is used for terms in descriptive lists, where appropriate.
monospace
Used for assembler syntax descriptions, pseudocode, and source code examples.
Also used in the main text for instruction mnemonics and for references to other items appearing in
assembler syntax descriptions, pseudocode, and source code examples.
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, and are defined in the
Glossary.
Colored text
Indicates a link. This can be:
•
a URL, for example, http://infocenter.arm.com
•
a cross-reference, that includes the page number of the referenced information if it is not on
the current page, for example, Pseudocode descriptions on page xxii
•
a link, to a chapter or appendix, or to a glossary entry, or to the section of the document that
defines the colored term, for example Simple sequential execution or SCTLR.
Note
Many links are to a register or instruction definition. Remember that:
•
many system control registers are defined both in Chapter B4 System Control Registers in a
VMSA implementation and in Chapter B6 System Control Registers in a PMSA
implementation
•
many instructions are defined in multiple forms, and in some cases the ARM encodings of an
instruction are defined separately to the Thumb encodings.
Ensure that any linked definition you refer to is appropriate to your context.
Signals
In general this specification does not define processor signals, but it does include some signal examples and
recommendations. The signal conventions are:
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Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means:
•
HIGH for active-HIGH signals
•
LOW for active-LOW signals.
Lower-case n
At the start or end of a signal name denotes an active-LOW signal.
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Preface
Conventions
Numbers
Numbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers by 0x. In
both cases, the prefix and the associated value are written in a monospace font, for example 0xFFFF0000.
Pseudocode descriptions
This manual uses a form of pseudocode to provide precise descriptions of the specified functionality. This
pseudocode is written in a monospace font, and is described in Appendix P Pseudocode Definition.
Assembler syntax descriptions
This manual contains numerous syntax descriptions for assembler instructions and for components of assembler
instructions. These are shown in a monospace font, and use the conventions described in Assembler syntax on
page A8-283.
xxii
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Preface
Additional reading
Additional reading
This section lists relevant publications from ARM and third parties.
See the Infocenter, http://infocenter.arm.com, for access to ARM documentation.
ARM publications
•
•
•
•
ARM® Debug Interface v5 Architecture Specification (ARM IHI 0031).
ARM®v7-M Architecture Reference Manual (ARM DDI 0403).
CoreSight™ Architecture Specification (ARM IHI 0029).
ARM® Architecture Reference Manual (ARM DDI 0100I).
Note
—
—
•
•
•
Issue I of the ARM Architecture Reference Manual (DDI 0100I) was issued in July 2005 and describes
the first version of the ARMv6 architecture, and all previous architecture versions.
Addison-Wesley Professional publish ARM Architecture Reference Manual, Second Edition
(December 27, 2000). The contents of this are identical to issue E of the ARM Architecture Reference
Manual (DDI 0100E). It describes ARMv5TE and earlier versions of the ARM architecture, and is
superseded by DDI 0100I.
Embedded Trace Macrocell Architecture Specification (ARM IHI 0014).
CoreSight™ Program Flow Trace Architecture Specification (ARM IHI 0035).
ARM® Generic Interrupt Controller Architecture Specification (ARM IHI 0048).
Other publications
The following books are referred to in this manual, or provide more information:
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•
IEEE Std 1596.5-1993, IEEE Standard for Shared-Data Formats Optimized for Scalable Coherent Interface
(SCI) Processors, ISBN 1-55937-354-7.
•
IEEE Std 1149.1-2001, IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG).
•
ANSI/IEEE Std 754-2008, and ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point
Arithmetic. See also Floating-point standards, and terminology on page A2-55.
•
JEDEC Solid State Technology Association, Standard Manufacturer’s Identification Code, JEP106.
•
Tim Lindholm and Frank Yellin, The Java Virtual Machine Specification, Second Edition, Addison Wesley,
ISBN: 0-201-43294-3.
•
Kourosh Gharachorloo, Memory Consistency Models for Shared Memory-Multiprocessors, 1995, Stanford
University Technical Report CSL-TR-95-685.
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Preface
Feedback
Feedback
ARM welcomes feedback on its documentation.
Feedback on this manual
If you have comments on the content of this manual, send e-mail to errata@arm.com. Give:
•
the title
•
the number, ARM DDI 0406C.b
•
the page numbers to which your comments apply
•
a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
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Part A
Application Level Architecture
Chapter A1
Introduction to the ARM Architecture
This chapter introduces the ARM architecture and contains the following sections:
•
About the ARM architecture on page A1-28
•
The instruction sets on page A1-29
•
Architecture versions, profiles, and variants on page A1-30
•
Architecture extensions on page A1-32
•
The ARM memory model on page A1-35.
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A1-27
A1 Introduction to the ARM Architecture
A1.1 About the ARM architecture
A1.1
About the ARM architecture
The ARM architecture supports implementations across a wide range of performance points. The architectural
simplicity of ARM processors leads to very small implementations, and small implementations mean devices can
have very low power consumption. Implementation size, performance, and very low power consumption are key
attributes of the ARM architecture.
The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these RISC
architecture features:
•
a large uniform register file
•
a load/store architecture, where data-processing operations only operate on register contents, not directly on
memory contents
•
simple addressing modes, with all load/store addresses being determined from register contents and
instruction fields only.
In addition, the ARM architecture provides:
•
instructions that combine a shift with an arithmetic or logical operation
•
auto-increment and auto-decrement addressing modes to optimize program loops
•
Load and Store Multiple instructions to maximize data throughput
•
conditional execution of many instructions to maximize execution throughput.
These enhancements to a basic RISC architecture mean ARM processors achieve a good balance of high
performance, small program size, low power consumption, and small silicon area.
This Architecture Reference Manual defines a set of behaviors to which an implementation must conform, and a set
of rules for software to use the implementation. It does not describe how to build an implementation.
Except where the architecture specifies differently, the programmer-visible behavior of an implementation must be
the same as a simple sequential execution of the program. This programmer-visible behavior does not include the
execution time of the program.
The ARM architecture includes definitions of:
A1-28
•
An associated debug architecture, see Debug architecture versions on page A1-31 and Part C of this manual.
•
Associated trace architectures, that define trace macrocells that implementers can implement with the
associated processor. For more information see the Embedded Trace Macrocell Architecture Specification
and the CoreSight Program Flow Trace Architecture Specification.
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A1 Introduction to the ARM Architecture
A1.2 The instruction sets
A1.2
The instruction sets
The ARM instruction set is a set of 32-bit instructions providing comprehensive data-processing and control
functions.
The Thumb instruction set was developed as a 16-bit instruction set with a subset of the functionality of the ARM
instruction set. It provides significantly improved code density, at a cost of some reduction in performance. A
processor executing Thumb instructions can change to executing ARM instructions for performance critical
segments, in particular for handling interrupts.
ARMv6T2 introduced Thumb-2 technology. This technology extends the original Thumb instruction set with many
32-bit instructions. The range of 32-bit Thumb instructions included in ARMv6T2 permits Thumb code to achieve
performance similar to ARM code, with code density better than that of earlier Thumb code.
From ARMv6T2, the ARM and Thumb instruction sets provide almost identical functionality. For more
information, see Chapter A4 The Instruction Sets.
A1.2.1
Execution environment support
Two additional instruction sets support execution environments:
•
The architecture can provide hardware acceleration of Java bytecodes. For more information, see:
—
Jazelle direct bytecode execution support on page A2-97, for application level information
—
Jazelle direct bytecode execution on page B1-1240, for system level information.
The Virtualization Extensions do not support hardware acceleration of Java bytecodes. That is, they support
only a trivial implementation of the Jazelle® extension.
•
The ThumbEE instruction set is a variant of the Thumb instruction set that minimizes the code size overhead
of a Just-In-Time (JIT) or Ahead-Of-Time (AOT) compiler. JIT and AOT compilers convert execution
environment source code to a native executable. For more information, see:
—
Thumb Execution Environment on page A2-95, for application level information
—
Thumb Execution Environment on page B1-1239, for system level information.
From the publication of issue C.a of this manual, ARM deprecates any use of the ThumbEE instruction set.
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A1-29
A1 Introduction to the ARM Architecture
A1.3 Architecture versions, profiles, and variants
A1.3
Architecture versions, profiles, and variants
The ARM architecture has evolved significantly since its introduction, and ARM continues to develop it. Seven
major versions of the architecture have been defined to date, denoted by the version numbers 1 to 7. Of these, the
first three versions are now obsolete.
ARMv7 provides three profiles:
ARMv7-A
Application profile, described in this manual:
ARMv7-R
•
Implements a traditional ARM architecture with multiple modes.
•
Supports a Virtual Memory System Architecture (VMSA) based on a Memory Management
Unit (MMU). An ARMv7-A implementation can be called a VMSAv7 implementation.
•
Supports the ARM and Thumb instruction sets.
Real-time profile, described in this manual:
ARMv7-M
•
Implements a traditional ARM architecture with multiple modes.
•
Supports a Protected Memory System Architecture (PMSA) based on a Memory Protection
Unit (MPU). An ARMv7-R implementation can be called a PMSAv7 implementation.
•
Supports the ARM and Thumb instruction sets.
Microcontroller profile, described in the ARMv7-M Architecture Reference Manual:
•
Implements a programmers' model designed for low-latency interrupt processing, with
hardware stacking of registers and support for writing interrupt handlers in high-level
languages.
•
Implements a variant of the ARMv7 PMSA.
•
Supports a variant of the Thumb instruction set.
Note
Parts A, B, and C of this Architecture Reference Manual describe the ARMv7-A and ARMv7-R profiles:
•
Appendixes describe how the ARMv4-ARMv6 architecture versions differ from ARMv7.
•
Separate Architecture Reference Manuals define the M-profile architectures, see Additional reading on
page xxiii.
Architecture versions can be qualified with variant letters to specify additional instructions and other functionality
that are included as an architecture extension.
Some extensions are described separately instead of using a variant letter. For details of these extensions see
Architecture extensions on page A1-32.
The valid variants of ARMv4, ARMv5, and ARMv6 are as follows:
A1-30
ARMv4
The earliest architecture variant covered by this manual. It includes only the ARM instruction set.
ARMv4T
Adds the Thumb instruction set.
ARMv5T
Improves interworking of ARM and Thumb instructions. Adds Count Leading Zeros (CLZ) and
software Breakpoint (BKPT) instructions.
ARMv5TE
Enhances arithmetic support for digital signal processing (DSP) algorithms. Adds Preload Data
(PLD), Load Register Dual (LDRD), Store Register Dual (STRD), and 64-bit coprocessor register transfer
(MCRR, MRRC) instructions.
ARMv5TEJ
Adds the BXJ instruction and other support for the Jazelle® architecture extension.
ARMv6
Adds many new instructions to the ARM instruction set. Formalizes and revises the memory model
and the Debug architecture.
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A1.3 Architecture versions, profiles, and variants
ARMv6K
Adds instructions to support multiprocessing to the ARM instruction set, and some extra memory
model features.
ARMv6T2
Introduces Thumb-2 technology, that supports a major development of the Thumb instruction set to
provide a similar level of functionality to the ARM instruction set.
Note
Where appropriate, the terms ARMv6KZ or ARMv6Z describe the ARMv6K architecture with the ARMv6
Security Extensions, that were an OPTIONAL addition to the VMSAv6 architecture.
For detailed information about how earlier versions of the ARM architecture differ from ARMv7, see Appendix L
ARMv6 Differences and Appendix O ARMv4 and ARMv5 Differences.
The following architecture variants are now obsolete:
ARMv1, ARMv2, ARMv2a, ARMv3, ARMv3G, ARMv3M, ARMv4xM, ARMv4TxM, ARMv5, ARMv5xM,
ARMv5TxM, and ARMv5TExP.
Contact ARM if you require details of obsolete variants.
Each instruction description in this manual specifies the architecture versions that include the instruction.
A1.3.1
Debug architecture versions
Before ARMv6, the debug implementation for an ARM processor was IMPLEMENTATION DEFINED. ARMv6 defined
the first debug architecture.
The debug architecture versions are:
v6 Debug
Introduced with the original ARMv6 architecture definition.
v6.1 Debug
Introduced to ARMv6K with the OPTIONAL Security Extensions, described in Architecture
extensions on page A1-33. A VMSAv6 implementation that includes the Security Extensions must
implement v6.1 Debug.
v7 Debug
First defined in issue A of this manual, and required by any ARMv7-R implementation
An ARMv7-A implementation that does not include the Virtualization Extensions must implement
either v7 Debug or v7.1 Debug.
For more information about the Virtualization Extensions, see Architecture extensions on
page A1-33.
v7.1 Debug
First defined in issue C.a of this manual, and required by any ARMv7-A implementation that
includes the Virtualization Extensions.
For more information, see:
•
Chapter C1 Introduction to the ARM Debug Architecture, for v7 Debug and v7.1 Debug
•
About v6 Debug and v6.1 Debug on page AppxM-2548, for v6 Debug and v6.1 Debug.
Note
In this manual:
•
debug usually refers to invasive debug, that permits modification of the state of the processor
•
trace usually refers to non-invasive debug, that does not permit modification of the state of the processor.
For more information see About the ARM Debug architecture on page C1-2021.
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A1 Introduction to the ARM Architecture
A1.4 Architecture extensions
A1.4
Architecture extensions
Instruction set architecture extensions summarizes the extensions that mainly affect the Instruction Set Architecture
(ISA), either extending the instructions implemented in the ARM and Thumb instruction sets, or implementing an
additional instruction set.
Architecture extensions on page A1-33 describes other extensions to the architecture.
A1.4.1
Instruction set architecture extensions
This manual describes the following extensions to the ISA:
Jazelle
Is the Java bytecode execution extension that extended ARMv5TE to ARMv5TEJ. From
ARMv6, the architecture requires at least the trivial Jazelle implementation, but a Jazelle
implementation is still often described as a Jazelle extension.
The Virtualization Extensions require that the Jazelle implementation is the trivial Jazelle
implementation.
ThumbEE
Is a variant of the Thumb instruction set that is designed as a target for dynamically
generated code. In the original release of the ARMv7 architecture, ThumbEE was:
•
A required extension to the ARMv7-A profile.
•
An optional extension to the ARMv7-R profile.
From publication of issue C.a of this manual, ARM deprecates any use of ThumbEE
instructions. However, ARMv7-A implementations must continue to include ThumbEE
support, for backwards compatibility.
Floating-point
Is a floating-point coprocessor extension to the instruction set architectures. For historic
reasons, the Floating-point Extension is also called the VFP Extension. There have been the
following versions of the Floating-point (VFP) Extension:
VFPv1
Obsolete. Details are available on request from ARM.
VFPv2
An optional extension to:
VFPv3
•
the ARM instruction set in the ARMv5TE, ARMv5TEJ, ARMv6, and
ARMv6K architectures
•
the ARM and Thumb instruction sets in the ARMv6T2 architecture.
An OPTIONAL extension to the ARM, Thumb, and ThumbEE instruction sets in
the ARMv7-A and ARMv7-R profiles.
VFPv3 can be implemented with either thirty-two or sixteen doubleword
registers, as described in Advanced SIMD and Floating-point Extension
registers on page A2-56. Where necessary, the terms VFPv3-D32 and
VFPv3-D16distinguish between these two implementation options. Where the
term VFPv3 is used it covers both options.
VFPv3U is a variant of VFPv3 that supports the trapping of floating-point
exceptions to support code, see VFPv3U and VFPv4U on page A2-62.
VFPv3 with Half-precision Extension
VFPv3 and VFPv3U can be extended by the OPTIONAL Half-precision
Extension, that provides conversion functions in both directions between
half-precision floating-point and single-precision floating-point.
VFPv4
A1-32
An OPTIONAL extension to the ARM, Thumb, and ThumbEE instruction sets in
the ARMv7-A and ARMv7-R profiles.
VFPv4U is a variant of VFPv4 that supports the trapping of floating-point
exceptions to support code, see VFPv3U and VFPv4U on page A2-62.
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A1.4 Architecture extensions
VFPv4 and VFPv4U add both the Half-precision Extension and the fused
multiply-add instructions to the features of VFPv3. VFPv4 can be implemented
with either thirty-two or sixteen doubleword registers, see Advanced SIMD and
Floating-point Extension registers on page A2-56. Where necessary, these
implementation options are distinguished using the terms:
•
VFPv4-D32, or VFPv4U-D32, for a thirty-two register implementation
•
VFPv4-D16, or VFPv4U-D16, for a sixteen register implementation.
Where the term VFPv4 is used it covers both options.
If an implementation includes both the Floating-point and Advanced SIMD Extensions:
•
Advanced SIMD
It must implement the corresponding versions of the extensions:
—
if the implementation includes VFPv3 it must include Advanced SIMDv1
—
if the implementation includes VFPv3 with the Half-precision Extension it
must include Advanced SIMDv1 with the half-precision extensions
—
if the implementation includes VFPv4 it must include Advanced SIMDv2.
•
The two extensions use the same register bank. This means VFP must be
implemented as VFPv3-D32, or as VFPv4-D32.
•
Some instructions apply to both extensions.
Is an instruction set extension that provides Single Instruction Multiple Data (SIMD)
integer and single-precision floating-point vector operations on doubleword and quadword
registers. There have been the following versions of Advanced SIMD:
Advanced SIMDv1
It is an OPTIONAL extension to the ARMv7-A and ARMv7-R profiles.
Advanced SIMDv1 with Half-precision Extension
Advanced SIMDv1 can be extended by the OPTIONAL Half-precision Extension,
that provides conversion functions in both directions between half-precision
floating-point and single-precision floating-point.
Advanced SIMDv2
It is an OPTIONAL extension to the ARMv7-A and ARMv7-R profiles.
Advanced SIMDv2 adds both the Half-precision Extension and the fused
multiply-add instructions to the features of Advanced SIMDv1.
See the description of the Floating-point Extension for more information about
implementations that include both the Floating-point Extension and the Advanced SIMD
Extension.
A1.4.2
Architecture extensions
This manual also describes the following extensions to the ARMv7 architecture:
Security Extensions
Are an OPTIONAL set of extensions to VMSAv6 implementations of the ARMv6K architecture, and
to the ARMv7-A architecture profile, that provide a set of security features that facilitate the
development of secure applications.
Multiprocessing Extensions
Are an OPTIONAL set of extensions to the ARMv7-A and ARMv7-R profiles, that provides a set of
features that enhance multiprocessing functionality.
Large Physical Address Extension
Is an OPTIONAL extension to VMSAv7 that provides an address translation system supporting
physical addresses of up to 40 bits at a fine grain of translation.
The Large Physical Address Extension requires implementation of the Multiprocessing Extensions.
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A1.4 Architecture extensions
Virtualization Extensions
Are an OPTIONAL set of extensions to VMSAv7 that provides hardware support for virtualizing the
Non-secure state of a VMSAv7 implementation. This supports system use of a virtual machine
monitor, also called a hypervisor, to switch Guest operating systems.
The Virtualization Extensions require implementation of:
•
the Security Extensions
•
the Large Physical Address Extension
•
the v7.1 Debug architecture, see Scope of part C of this manual on page C1-2020.
If an implementation that includes the Virtualization Extensions also implements:
•
The Performance Monitors Extension, then it must implement version 2 of that extension,
PMUv2, see About the Performance Monitors on page C12-2300.
•
A trace macrocell, that trace macrocell must support the Virtualization Extensions. In
particular, if the trace macrocell is:
—
an Embedded Trace Macrocell (ETM), the macrocell must implement ETMv3.5 or
later, see the Embedded Trace Macrocell Architecture Specification
—
a Program Trace Macrocell (PTM), the macrocell must implement PFTv1.1 or later,
see the CoreSight Program Flow Trace Architecture Specification.
In some tables in this manual, an ARMv7-A implementation that includes the Virtualization
Extensions is described as ARMv7VE, or as v7VE.
Generic Timer Extension
Is an OPTIONAL extension to any ARMv7-A or ARMv7-R, that provides a system timer, and a
low-latency register interface to it.
This extension is introduced with the Large Physical Address Extension and Virtualization
Extensions, but can be implemented with any earlier version of the ARMv7 architecture. The
Generic Timer Extension does not require the implementation of any of the extensions described in
this subsection.
For more information see Chapter B8 The Generic Timer.
Performance Monitors Extension
The ARMv7 architecture:
•
reserves CP15 register space for IMPLEMENTATION DEFINED performance monitors
•
defines a recommended performance monitors implementation.
From issue C.a of this manual, this recommended implementation is called the Performance
Monitors Extension.
The Performance Monitors Extension does not require the implementation of any of the extensions
described in this subsection.
If an ARMv7 implementation that includes v7.1 Debug also includes the Performance Monitors
Extension, it must implement PMUv2.
For more information see Chapter C12 The Performance Monitors Extension.
Note
The Fast Context Switch Extension (FCSE) is an older ARM extension, described in Appendix J:
A1-34
•
ARM deprecates any use of this extension. This means in ARMv7 implementations before the introduction
of the Multiprocessing Extensions, the FCSE is OPTIONAL and deprecated.
•
The Multiprocessing Extensions obsolete the FCSE. This means that any processor that includes the
Multiprocessing Extensions cannot include the FCSE. This includes all processors that implement the Large
Physical Address Extension.
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A1.5 The ARM memory model
A1.5
The ARM memory model
The ARM instruction sets address a single, flat address space of 232 8-bit bytes. This address space is also regarded
as 230 32-bit words or 231 16-bit halfwords.
The architecture provides facilities for:
•
generating an exception on an unaligned memory access
•
restricting access by applications to specified areas of memory
•
translating virtual addresses provided by executing instructions into physical addresses
•
altering the interpretation of word and halfword data between big-endian and little-endian
•
controlling the order of accesses to memory
•
controlling caches
•
synchronizing access to shared memory by multiple processors.
For more information, see:
•
Chapter A3 Application Level Memory Model
•
Chapter B2 Common Memory System Architecture Features
•
Chapter B3 Virtual Memory System Architecture (VMSA)
•
Chapter B5 Protected Memory System Architecture (PMSA).
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A1.5 The ARM memory model
A1-36
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Application Level Programmers’ Model
This chapter gives an application level view of the ARM programmers’ model. It contains the following sections:
•
About the Application level programmers’ model on page A2-38
•
ARM core data types and arithmetic on page A2-40
•
ARM core registers on page A2-45
•
The Application Program Status Register (APSR) on page A2-49
•
Execution state registers on page A2-50
•
Advanced SIMD and Floating-point Extensions on page A2-54
•
Floating-point data types and arithmetic on page A2-63
•
Polynomial arithmetic over {0, 1} on page A2-93
•
Coprocessor support on page A2-94
•
Thumb Execution Environment on page A2-95
•
Jazelle direct bytecode execution support on page A2-97
•
Exceptions, debug events and checks on page A2-102.
Note
In this chapter, system register names usually link to the description of the register in Chapter B4 System Control
Registers in a VMSA implementation, for example FPSCR. If the register is included in a PMSA implementation,
then it is also described in Chapter B6 System Control Registers in a PMSA implementation.
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A2 Application Level Programmers’ Model
A2.1 About the Application level programmers’ model
A2.1
About the Application level programmers’ model
This chapter contains the programmers’ model information required for application development.
The information in this chapter is distinct from the system information required to service and support application
execution under an operating system, or higher level of system software. However, some knowledge of that system
information is needed to put the Application level programmers' model into context.
Depending on the implemented architecture extensions, the architecture supports multiple levels of execution
privilege, that number upwards from PL0, where PL0 is the lowest privilege level and is often described as
unprivileged. The Application level programmers’ model is the programmers’ model for software executing at PL0.
For more information see Processor privilege levels, execution privilege, and access privilege on page A3-141.
System software determines the privilege level at which application software runs. When an operating system
supports execution at both PL1 and PL0, an application usually runs unprivileged. This:
•
permits the operating system to allocate system resources to an application in a unique or shared manner
•
provides a degree of protection from other processes and tasks, and so helps protect the operating system
from malfunctioning applications.
This chapter indicates where some system level understanding is helpful, and if appropriate it gives a reference to
the system level description in Chapter B1 The System Level Programmers’ Model, or elsewhere.
The Security Extensions extend the architecture to provide hardware security features that support the development
of secure applications, by providing two Security states. The Virtualization Extensions further extend the
architecture to provide virtualization of operation in Non-secure state. However, application level software is
generally unaware of these extensions. For more information, see The Security Extensions on page B1-1156 and The
Virtualization Extensions on page B1-1161.
Note
A2-38
•
When an implementation includes the Security Extensions, application and operating system software
normally executes in Non-secure state.
•
The virtualization features accessible only at PL2 are implemented only in Non-secure state. Secure state has
only two privilege levels, PL0 and PL1.
•
Older documentation, describing implementations or architecture versions that support only two privilege
levels, often refers to execution at PL1 as privileged execution.
•
In this manual, the following terms have special meanings, defined in the Glossary:
—
IMPLEMENTATION DEFINED, see IMPLEMENTATION DEFINED.
OPTIONAL, see OPTIONAL.
—
SUBARCHITECTURE DEFINED, see SUBARCHITECTURE DEFINED.
—
UNDEFINED, see UNDEFINED.
—
UNKNOWN, see UNKNOWN.
—
UNPREDICTABLE, see UNPREDICTABLE.
—
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A2.1 About the Application level programmers’ model
A2.1.1
Instruction sets, arithmetic operations, and register files
The ARM and Thumb instruction sets both provide a wide range of integer arithmetic and logical operations, that
operate on register file of sixteen 32-bit registers, the ARM core registers. As described in ARM core registers on
page A2-45, these registers include the special registers SP, LR, and PC. ARM core data types and arithmetic on
page A2-40 gives more information about these operations.
In addition, if an implementation includes:
•
the Floating-point (VFP) Extension, the ARM and Thumb instruction sets include floating-point instructions
•
the Advanced SIMD Extension, the ARM and Thumb instruction sets include vector instructions.
Floating-point and vector instructions operate on an independent register file, described in Advanced SIMD and
Floating-point Extension registers on page A2-56. In an implementation that includes both of these extensions, they
share a common register file. The following sections give more information about these extensions and the
instructions they provide:
•
Advanced SIMD and Floating-point Extensions on page A2-54
•
Floating-point data types and arithmetic on page A2-63
•
Polynomial arithmetic over {0, 1} on page A2-93.
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A2.2 ARM core data types and arithmetic
A2.2
ARM core data types and arithmetic
All ARMv7-A and ARMv7-R processors support the following data types in memory:
Byte
8 bits
Halfword
16 bits
Word
32 bits
Doubleword 64 bits.
Processor registers are 32 bits in size. The instruction set contains instructions supporting the following data types
held in registers:
•
32-bit pointers
•
unsigned or signed 32-bit integers
•
unsigned 16-bit or 8-bit integers, held in zero-extended form
•
signed 16-bit or 8-bit integers, held in sign-extended form
•
two 16-bit integers packed into a register
•
four 8-bit integers packed into a register
•
unsigned or signed 64-bit integers held in two registers.
Load and store operations can transfer bytes, halfwords, or words to and from memory. Loads of bytes or halfwords
zero-extend or sign-extend the data as it is loaded, as specified in the appropriate load instruction.
The instruction sets include load and store operations that transfer two or more words to and from memory. Software
can load and store doublewords using these instructions.
Note
For information about the atomicity of memory accesses see Atomicity in the ARM architecture on page A3-127.
When any of the data types is described as unsigned, the N-bit data value represents a non-negative integer in the
range 0 to 2N-1, using normal binary format.
When any of these types is described as signed, the N-bit data value represents an integer in the range -2N-1 to
+2N-1-1, using two's complement format.
The instructions that operate on packed halfwords or bytes include some multiply instructions that use just one of
two halfwords, and SIMD instructions that perform parallel addition or subtraction on all of the halfwords or bytes.
Direct instruction support for 64-bit integers is limited, and most 64-bit operations require sequences of two or more
instructions to synthesize them.
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A2.2 ARM core data types and arithmetic
A2.2.1
Integer arithmetic
The instruction set provides a wide variety of operations on the values in registers, including bitwise logical
operations, shifts, additions, subtractions, multiplications, and many others. The pseudocode described in
Appendix P Pseudocode Definition defines these operations, usually in one of three ways:
•
By direct use of the pseudocode operators and built-in functions defined in Operators and built-in functions
on page AppxP-2651.
•
By use of pseudocode helper functions defined in the main text. These can be located using the table in
Appendix Q Pseudocode Index.
•
By a sequence of the form:
1.
Use of the SInt(), UInt(), and Int() built-in functions defined in Converting bitstrings to integers on
page AppxP-2653 to convert the bitstring contents of the instruction operands to the unbounded
integers that they represent as two's complement or unsigned integers.
2.
Use of mathematical operators, built-in functions and helper functions on those unbounded integers to
calculate other such integers.
3.
Use of either the bitstring extraction operator defined in Bitstring extraction on page AppxP-2652 or
of the saturation helper functions described in Pseudocode details of saturation on page A2-44 to
convert an unbounded integer result into a bitstring result that can be written to a register.
Shift and rotate operations
The following types of shift and rotate operations are used in instructions:
Logical Shift Left
(LSL) moves each bit of a bitstring left by a specified number of bits. Zeros are shifted in at the right
end of the bitstring. Bits that are shifted off the left end of the bitstring are discarded, except that the
last such bit can be produced as a carry output.
Logical Shift Right
(LSR) moves each bit of a bitstring right by a specified number of bits. Zeros are shifted in at the left
end of the bitstring. Bits that are shifted off the right end of the bitstring are discarded, except that
the last such bit can be produced as a carry output.
Arithmetic Shift Right
(ASR) moves each bit of a bitstring right by a specified number of bits. Copies of the leftmost bit are
shifted in at the left end of the bitstring. Bits that are shifted off the right end of the bitstring are
discarded, except that the last such bit can be produced as a carry output.
Rotate Right (ROR) moves each bit of a bitstring right by a specified number of bits. Each bit that is shifted off the
right end of the bitstring is re-introduced at the left end. The last bit shifted off the right end of the
bitstring can be produced as a carry output.
Rotate Right with Extend
(RRX) moves each bit of a bitstring right by one bit. A carry input is shifted in at the left end of the
bitstring. The bit shifted off the right end of the bitstring can be produced as a carry output.
Pseudocode details of shift and rotate operations
These shift and rotate operations are supported in pseudocode by the following functions:
// LSL_C()
// =======
(bits(N), bit) LSL_C(bits(N) x, integer shift)
assert shift > 0;
extended_x = x : Zeros(shift);
result = extended_x;
carry_out = extended_x;
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A2.2 ARM core data types and arithmetic
return (result, carry_out);
// LSL()
// =====
bits(N) LSL(bits(N) x, integer shift)
assert shift >= 0;
if shift == 0 then
result = x;
else
(result, -) = LSL_C(x, shift);
return result;
// LSR_C()
// =======
(bits(N), bit) LSR_C(bits(N) x, integer shift)
assert shift > 0;
extended_x = ZeroExtend(x, shift+N);
result = extended_x;
carry_out = extended_x;
return (result, carry_out);
// LSR()
// =====
bits(N) LSR(bits(N) x, integer shift)
assert shift >= 0;
if shift == 0 then
result = x;
else
(result, -) = LSR_C(x, shift);
return result;
// ASR_C()
// =======
(bits(N), bit) ASR_C(bits(N) x, integer shift)
assert shift > 0;
extended_x = SignExtend(x, shift+N);
result = extended_x;
carry_out = extended_x;
return (result, carry_out);
// ASR()
// =====
bits(N) ASR(bits(N) x, integer shift)
assert shift >= 0;
if shift == 0 then
result = x;
else
(result, -) = ASR_C(x, shift);
return result;
// ROR_C()
// =======
(bits(N), bit) ROR_C(bits(N) x, integer shift)
assert shift != 0;
m = shift MOD N;
result = LSR(x,m) OR LSL(x,N-m);
carry_out = result;
return (result, carry_out);
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// ROR()
// =====
bits(N) ROR(bits(N) x, integer shift)
if shift == 0 then
result = x;
else
(result, -) = ROR_C(x, shift);
return result;
// RRX_C()
// =======
(bits(N), bit) RRX_C(bits(N) x, bit carry_in)
result = carry_in : x;
carry_out = x<0>;
return (result, carry_out);
// RRX()
// =====
bits(N) RRX(bits(N) x, bit carry_in)
(result, -) = RRX_C(x, carry_in);
return result;
Pseudocode details of addition and subtraction
In pseudocode, addition and subtraction can be performed on any combination of unbounded integers and bitstrings,
provided that if they are performed on two bitstrings, the bitstrings must be identical in length. The result is another
unbounded integer if both operands are unbounded integers, and a bitstring of the same length as the bitstring
operand(s) otherwise. For the precise definition of these operations, see Addition and subtraction on
page AppxP-2654.
The main addition and subtraction instructions can produce status information about both unsigned carry and signed
overflow conditions. When necessary, multi-word additions and subtractions are synthesized from this status
information. In pseudocode the AddWithCarry() function provides an addition with a carry input and carry and
overflow outputs:
// AddWithCarry()
// ==============
(bits(N), bit, bit) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)
unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in);
signed_sum
= SInt(x) + SInt(y) + UInt(carry_in);
result
= unsigned_sum; // same value as signed_sum
carry_out
= if UInt(result) == unsigned_sum then '0' else '1';
overflow
= if SInt(result) == signed_sum then '0' else '1';
return (result, carry_out, overflow);
An important property of the AddWithCarry() function is that if:
(result, carry_out, overflow) = AddWithCarry(x, NOT(y), carry_in)
then:
•
if carry_in == '1', then result == x-y with:
overflow == '1' if signed overflow occurred during the subtraction
—
carry_out == '1' if unsigned borrow did not occur during the subtraction, that is, if x >= y
—
•
if carry_in == '0', then result == x-y-1 with:
overflow == '1' if signed overflow occurred during the subtraction
—
carry_out == '1' if unsigned borrow did not occur during the subtraction, that is, if x > y.
—
Together, these mean that the carry_in and carry_out bits in AddWithCarry() calls can act as NOT borrow flags for
subtractions as well as carry flags for additions.
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A2-43
A2 Application Level Programmers’ Model
A2.2 ARM core data types and arithmetic
Pseudocode details of saturation
Some instructions perform saturating arithmetic, that is, if the result of the arithmetic overflows the destination
signed or unsigned N-bit integer range, the result produced is the largest or smallest value in that range, rather than
wrapping around modulo 2N. This is supported in pseudocode by:
•
the SignedSatQ() and UnsignedSatQ() functions when an operation requires, in addition to the saturated result,
a Boolean argument that indicates whether saturation occurred
•
the SignedSat() and UnsignedSat() functions when only the saturated result is required.
// SignedSatQ()
// ============
(bits(N), boolean) SignedSatQ(integer i, integer N)
if i > 2^(N-1) - 1 then
result = 2^(N-1) - 1; saturated = TRUE;
elsif i < -(2^(N-1)) then
result = -(2^(N-1)); saturated = TRUE;
else
result = i; saturated = FALSE;
return (result, saturated);
// UnsignedSatQ()
// ==============
(bits(N), boolean) UnsignedSatQ(integer i, integer N)
if i > 2^N - 1 then
result = 2^N - 1; saturated = TRUE;
elsif i < 0 then
result = 0; saturated = TRUE;
else
result = i; saturated = FALSE;
return (result, saturated);
// SignedSat()
// ===========
bits(N) SignedSat(integer i, integer N)
(result, -) = SignedSatQ(i, N);
return result;
// UnsignedSat()
// =============
bits(N) UnsignedSat(integer i, integer N)
(result, -) = UnsignedSatQ(i, N);
return result;
SatQ(i, N, unsigned) returns either UnsignedSatQ(i, N) or SignedSatQ(i, N) depending on the value of its third
argument, and Sat(i, N, unsigned) returns either UnsignedSat(i, N) or SignedSat(i, N) depending on the value of
its third argument:
// SatQ()
// ======
(bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)
(result, sat) = if unsigned then UnsignedSatQ(i, N) else SignedSatQ(i, N);
return (result, sat);
// Sat()
// =====
bits(N) Sat(integer i, integer N, boolean unsigned)
result = if unsigned then UnsignedSat(i, N) else SignedSat(i, N);
return result;
A2-44
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Non-Confidential
ARM DDI 0406C.b
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A2 Application Level Programmers’ Model
A2.3 ARM core registers
A2.3
ARM core registers
In the application level view, an ARM processor has:
•
thirteen general-purpose 32-bit registers, R0 to R12
•
three 32-bit registers with special uses, SP, LR, and PC, that can be described as R13 to R15.
The special registers are:
SP, the stack pointer
The processor uses SP as a pointer to the active stack.
In the Thumb instruction set, most instructions cannot access SP. The only instructions that can
access SP are those designed to use SP as a stack pointer.
The ARM instruction set provides more general access to the SP, and it can be used as a
general-purpose register. However, ARM deprecates the use of SP for any purpose other than as a
stack pointer.
Note
Using SP for any purpose other than as a stack pointer is likely to break the requirements of
operating systems, debuggers, and other software systems, causing them to malfunction.
Software can refer to SP as R13.
LR, the link register
The link register is a special register that can hold return link information. Some cases described in
this manual require this use of the LR. When software does not require the LR for linking, it can use
it for other purposes. It can refer to LR as R14.
PC, the program counter
•
When executing an ARM instruction, PC reads as the address of the current instruction
plus 8.
•
When executing a Thumb instruction, PC reads as the address of the current instruction
plus 4.
•
Writing an address to PC causes a branch to that address.
Most Thumb instructions cannot access PC.
The ARM instruction set provides more general access to the PC, and many ARM instructions can
use the PC as a general-purpose register. However, ARM deprecates the use of PC for any purpose
other than as the program counter. See Writing to the PC on page A2-46 for more information.
Software can refer to PC as R15.
See ARM core registers on page B1-1143 for the system level view of these registers.
Note
In general, ARM strongly recommends using the names SP, LR and PC instead of R13, R14 and R15. However,
sometimes it is simpler to use the R13-R15 names when referring to a group of registers. For example, it is simpler
to refer to Registers R8 to R15, rather than to Registers R8 to R12, the SP, LR and PC. These two descriptions of the
group of registers have exactly the same meaning.
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A2-45
A2 Application Level Programmers’ Model
A2.3 ARM core registers
A2.3.1
Writing to the PC
In ARMv7, many data-processing instructions can write to the PC. Writes to the PC are handled as follows:
•
In Thumb state, the following 16-bit Thumb instruction encodings branch to the value written to the PC:
—
encoding T2 of ADD (register, Thumb) on page A8-310
—
encoding T1 of MOV (register, Thumb) on page A8-486.
The value written to the PC is forced to be halfword-aligned by ignoring its least significant bit, treating that
bit as being 0.
•
The B, BL, CBNZ, CBZ, CHKA, HB, HBL, HBLP, HBP, TBB, and TBH instructions remain in the same instruction set state
and branch to the value written to the PC.
The definition of each of these instructions ensures that the value written to the PC is correctly aligned for
the current instruction set state.
•
The BLX (immediate) instruction switches between ARM and Thumb states and branches to the value written
to the PC. Its definition ensures that the value written to the PC is correctly aligned for the new instruction
set state.
•
The following instructions write a value to the PC, treating that value as an interworking address to branch
to, with low-order bits that determine the new instruction set state:
—
BLX (register), BX, and BXJ
—
LDR instructions with