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BSIMSOI3.1 MOSFET MODEL
Users’ Manual

BSIM GROUP
February 2003

Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720

Copyright  2003
The Regents of the University of California
All Rights Reserved

BSIMSOI Developers:
n Dr. Pin Su
n Mr. Hui Wan
n Dr. Samuel Fung
n Prof. Mansun Chan
n Prof. Ali Niknejad
n Prof. Chenming Hu

Previous BSIMSOI/BSIMPD Developers:
n Dr. Samuel Fung
n Dr. Dennis Sinitsky
n Dr. Stephen Tang
n Dr. Pin Su
n Dr. Weidong Liu
n Dr. Robert Tu
n Prof. Mansun Chan
n Prof. Ping K. Ko
n Prof. Chenming Hu

How to get a copy of this manual and source code for the model:
http://www-device.eecs.berkeley.edu/~bsimsoi

Table of Contents

1.

Introduction

2.

MOS I-V Model
2.1.

Floating Body Operation and Effective Body Potential

2.2.

Threshold Voltage in the High Vbs Regime
2.2.1. Linear Extrapolation for the Square-Root Expression
2.2.2. Width Dependence of the Body Effect

3.

4.

2.3.

Bulk Charge Effect in the High Vbs Regime

2.4.

Single Drain Current Equation

Body Currents Model
3.1.

Diode and Parasitic BJT Currents

3.2.

New Impact Ionization Current Equation

3.3.

Gate Induced Drain Leakage Current

3.4.

Oxide Tunneling Current

3.5.

Body Contact Current

3.6.

Body Contact Parasitics

MOS C-V Model
4.1.

Charge Conservation

4.2.

Intrinsic Charges

4.3.

Source/Drain Junction Charges

4.4.

Extrinsic Capacitances

4.5.

Body Contact Parasitics

Table of Content

5.

6.

Temperature Dependence and Self-Heating
5.1.

Temperature Dependence

5.2.

Self-Heating Implementation

BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
6.1.

BSIMSOI Framework and Built-In Potential Lowering Model

6.2.

Verification

7.

BSIMSOI RF Model

8.

References

9.

Appendix A: Model Instance Syntax

10.

Appendix B: Model Parameter List

11.

Appendix C: Equation List

12.

Appendix D: Parameter Extraction

13.

Appendix E: Model Parameter Binning

Chapter 1: Introduction

BSIMSOI is an international standard model for SOI (Silicon-On-Insulator) circuit design [20,
21]. This model is formulated on top of the BSIM3v3 framework [1]. It shares the same basic
equations with the bulk model so that the physical nature and smoothness of BSIM3v3 are
retained. Most parameters related to general MOSFET operation (non-SOI specific) are directly
imported from BSIM3v3 to ensure parameter compatibility.
BSIMPD [18] is the Partial-Depletion (PD) mode of BSIMSOI. Many enhanced features are
included in BSIMPD through the joint effort of the BSIM Team at UC Berkeley and IBM
Semiconductor Research and Development Center (SRDC) at East Fishkill. In particular, the
model has been tested extensively within IBM on its state-of-the-art high speed SOI technology.
BSIMPD, a derivative of BSIM3SOIv1.3 [2], has the following features and enhancements:
•

Real floating body simulation in both I-V and C-V. The body potential is determined by
the balance of all the body current components.

•

An improved parasitic bipolar current model. This includes enhancements in the various
diode leakage components, second order effects (high-level injection and Early effect),
diffusion charge equation, and temperature dependence of the diode junction capacitance.

•

An improved impact-ionization current model. The contribution from BJT current is also
modeled by the parameter Fbjtii.

•

A gate-to-body tunneling current model, which is important to thin-oxide SOI
technologies.

•

Enhancements in the threshold voltage and bulk charge formulation of the high positive
body bias regime.

•

Instance parameters (Pdbcp, Psbcp, Agbcp, Aebcp, Nbc) are provided to model the
parasitics of devices with various body-contact and isolation structures [17].

•

An external body node (the 6th node) and other improvements are introduced to facilitate
the modeling of distributed body-resistance [17].

•

Self heating. An external temperature node (the 7th node) is supported to facilitate the
simulation of thermal coupling among neighboring devices.

•

A unique SOI low frequency noise model, including a new excess noise resulting from the
floating body effect [3].

•

Width dependence of the body effect is modeled by parameters (K1, K1w1, K1w2).

•

Improved history dependence of the body charges with two new parameters, (Fbody,
DLCB).

•

An instance parameter Vbsusr is provided for users to set the transient initial condition of
the body potential.

•

The new charge-thickness capacitance model introduced in BSIM3v3.2 [4], capMod=3, is
included.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

Chapter 2: MOS I-V Model

A typical PD SOI MOSFET structure is shown in Fig. 2.1. The device is formed on a thin SOI
film of thickness Tsi on top of a layer of buried oxide with thickness Tbox. In the floating body
configuration, there are four external biases which are gate voltage (Vg), drain voltage (Vd),
source voltage (Vs) and substrate bias (Ve). The body potential (Vb) is iterated in circuit
simulation. If a body contact is applied, there will be one more external bias, the body contact
voltage (Vp).

EXTERNAL BODY BIAS

Vp
Vg

Vd

Vs
GATE

Tox
DRAIN

SOURCE

Vb

Tsi

BODY

Tbox
SUBSTRATE

Ve

Fig. 2.1

Schematic of a typical PD SOI MOSFET.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

2-1

MOS I-V Model

Since the backgate (Ve) effect is decoupled by the neutral body, PD SOI MOSFETs have
similar characteristics as bulk devices. Hence most PD SOI models reported [5, 6] were
developed by adding some SOI specific effects onto a bulk model. These effects include parasitic
bipolar current, self-heating and body contact resistance.
BSIMPD is formulated on top of the BSIM3v3 framework. In this way, a lot of physical
effects which are common in bulk and SOI devices can be shared. These effects are reverse short
channel effect, poly depletion, velocity saturation, DIBL in subthreshold and output resistance,
short channel effect, mobility degradation, narrow width effect and source/drain series resistance
[1, 4].

2.1. Floating Body Operation and Effective Body Potential
In BSIMPD, the floating body voltage is iterated by the SPICE engine. The result of iteration
is determined by the body currents [7, 18]. In the case of DC, body currents include diode
current, impact ionization, gate-induced drain leakage (GIDL), oxide tunneling and body contact
current. For AC or transient simulations, the displacement currents originated from the capacitive
coupling are also contributive.
To ensure a good model behavior during simulations, the iterated body potential Vbs is
bounded by the following smoothing function
T1 = Vbsc + 0.5 Vbs − Vbsc − δ +


(Vbs − Vbsc − δ )2 − 4δVbsc  , Vbsc = −5V

Vbsh = φ s1 − 0.5φ s1 − T1 − δ +




(φ s1 − T1 − δ )2 + 4δT1  , φ s1 = 1.5V


(2.1)
(2.2)

Here the body potential Vbsh is equal to the Vbs bounded between (Vbsc, φs1), and is used in the
threshold voltage and bulk charge calculation. To validate the popular square root expression
φ s − Vbsh in the MOSFET model, Vbsh is further limited to 0.95φs to give the following effective
body potential
Vbseff = φ s 0 − 0.5φ s 0 − Vbsh − δ +


(φ s 0 − Vbsh − δ ) 2 + 4δVbsh  , φ s 0 = 0.95φ s

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

(2.3)

2-2

MOS I-V Model

2.2. Threshold Voltage in the High Vbs Regime
2.2.1. Linear Extrapolation for the Square-Root Epression
Using the Vbseff which is clamped to the surface potential φs, the square-root dependence
φ s − Vbseff of the threshold voltage is ensured to behave properly during simulations [20].
However the real body potential may be larger than the surface potential in state-of-the-art PD
SOI technologies. To accurately count the body effect in such a high body bias regime, we extend
the square-root expression by
1
sqrtPhisExt = φ s − Vbseff + s (Vbsh − Vbseff ) s = −
,
2 φ s − φ s0

(2.4)

where a linear extrapolation is employed for Vbsh ≥ 0.95φ s . Notice that sqrtPhisEx t = φ s − Vbseff
for Vbsh ≤ 0.95φ s .

2.2.2. Width Dependence of the Body Effect
In BSIMPD, the body effect coefficient K1 is replaced by


K

K1eff = K1  1 + ' 1w1
 W + K1 w 2 
eff



(2.5)

to model the width dependence of the body effect. Notice that K1eff approaches K1 asymptotically
as the effective channel width W’eff increases. While the body effect coefficient will be determined
by the parameters (K1w1, K1w2 ) when W’eff becomes small so that the contribution from the
channel-stop doping should be taken into account.

The complete equation of the threshold voltage Vth can be found in the Appendix C.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

2-3

MOS I-V Model

2.3. Bulk Charge Effect in the High Vbs Regime
The bulk charge factor in BSIMPD is modified from BSIM3v3 as

Abulk



K1eff

=1+ 
Vbsh
 2 (φ s + Ketas) −

1 + Keta ⋅Vbsh



A0 Leff


 Leff + 2 Tsi X dep




Leff


1 − AgsV gsteff  L + 2 T X

si
dep
 eff







2




  (2.6)
B0

 + W ' + B 

eff
1 




to accommodate the model behavior in the high body bias regime, which is important in PD SOI.
The parameter Ketas acts like an effective increment of the surface potential, which can be used to
adjust the Abulk rollup with the body potential Vbsh. While the other parameter Keta is used to tune
the rate of rollup with Vbsh. By using this new expression, the non-physical drain current roll-off
due to the dramatic Abulk rollup at high body bias can be avoided [20].

2.4. Single Drain Current Equation
After improving the Vth and Abulk behavior in the high body bias regime, we can describe the
MOSFET drain current by the same equation as BSIM3v3. The effective drain voltage Vdseff and
effective gate overdrive voltage Vgsteff introduced in BSIM3v3 [1] are employed to link
subthreshold, linear and saturation operation regions into a single expression as
I ds ,MOSFET =

Vds − Vdseff
I ds 0
(1 +
)
Rds I dso
VA
1+
Vdseff

β = µ eff Cox

Idso

Weff
Leff


Vdseff
βVgsteff 1 − Abulk

2 Vgsteff + 2 vt

=
V
1 + dseff
Esat Leff

(

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

)


 Vdseff



(2.7)

2-4

MOS I-V Model
where Rds is the source/drain series resistance, µeff is the mobility, Esat is the critical electrical field
at which the carrier velocity becomes saturated and VA accounts for channel length modulation
(CLM) and DIBL as in BSIM3v3. The substrate current body effect (SCBE) [8, 9] on VA is not
included because it has been taken into account explicitly by the real floating body simulation
determined by the body currents, which will be detailed in the next chapter.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

2-5

Chapter 3: Body Currents Model

Body currents determine the body potential and therefore the drain current through the body
effect. Beside the impact ionization current considered in BSIM3v3, diode (bipolar) current,
GIDL, oxide tunneling and body contact current are all included in the BSIMPD model [Fig. 3.1]
to give an accurate body-potential prediction in the floating body simulation [18].

3.1. Diode and Parasitic BJT Currents
In this section we describe various current components originated from Body-to-Source/Drain
(B-S/D) injection, recombination in the B-S/D junction depletion region, Source/Drain-to-Body
(S/D-B) injection, recombination current in the neutral body, and diode tunneling current.

Igb

Iii

Fig. 3.1

Idiode

Various current components inside the body.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

3-1

Body Currents Model

The backward injection current in the B-S/D diode can be expressed as

 V
I bs1 = WdiosTsi jsdif  exp bs
 ndioVt


 
 − 1
 


 V
= Wdiod Tsi jsdif  exp  bd
 ndioVt


 
 − 1
 

I bd 1

(3.1)

Here ndio , jsdif ,Wdios , Wdiod are the non-ideality factor, the saturation current, the effective B-S
diode width and the B-D diode width, respectively.
The carrier recombination and trap-assisted tunneling current in the space-charge region is
modeled by

 Vbs
I bs 2 = WdiosTsi jsrec  exp 

 0.026n recf




Vrec 0  
 − exp  Vsb
 0.026n V + V  

recr
rec 0
sb  




 Vbd
= Wdiod Tsi jsrec  exp
 0.026n

recf





Vrec 0  
 − exp Vdb
 0.026n V + V  

recr
rec 0
db  



I bd 2

(3.2)

Here n recf , n recr , jsrec are non-ideality factors for forward bias and reverse bias, the saturation
current, respectively. Note that the parameter Vrec 0 is provided to model the current roll-off in the
high reverse bias regime.
The reverse bias tunneling current, which may be significant in junctions with high doping
concentration, can be expressed as

 Vsb
Vtun0
I bs4 = WdiosTsi j stun  1 − exp
 0.026ntun Vtun0 + Vsb

I bd 4


 Vdb
Vtun0
= Wdiod Tsi j stun  1 − exp
.
n
V
0
026
tun tun 0 + Vdb




 



 



(3.3)

where jstun is the saturation current. The parameters ntun and Vtun 0 are provided to better fit the
data.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

3-2

Body Currents Model

The recombination current in the neutral body can be described by
  V  
1
I bs 3 = (1 − α bjt )I en exp bs  − 1
  ndioVt   E hlis + 1
  V  
1
I bd 3 = (1 − α bjt )I en exp bd  − 1
  ndioVt   Ehlid + 1
I en


 1
1 
= W Tsi jsbjt  Lbjt 0 
+  
 Leff Ln  

  V
= Ahli _ eff exp bs
  ndioVt

 
 − 1
 

  V
Ehlid = Ahli _ eff exp  bd
  ndioVt

 
 − 1
 

Ehlis

α bjt

N bjt

'
eff


L
= exp  − 0.5 eff

 Ln





2

(3.4)





Here α bjt is the bipolar transport factor, whose value depends on the ratio of the effective channel
length Leff and the minority carrier diffusion length Ln . jsbjt is the saturation current, while the
parameters Lbjt 0 and N bjt are provided to better fit the forward injection characteristics. Notice
that Ehlis and Ehlid , determined by the parameter Ahli , stand for the high level injection effect in
the B-S/D diode, respectively.
The parasitic bipolar transistor current is important in transient body discharge, especially in
pass-gate floating body SOI designs [7]. The BJT collector current is modeled as
  V 
 V  1
Ic = α bjt Ien exp  bs  − exp  bd  
 ndio Vt   E2 nd
  ndio Vt 
E2 nd =
Eely

Eely + Eely 2 + 4 Ehli

2
Vbs + Vbd
= 1+
VAbjt + Aely Leff

(3.5)

Ehli = Ehlis + Ehlid

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

3-3

Body Currents Model

where E2 nd is composed of the Early effect E ely and the high level injection roll-off Ehli . Note
that E2 nd → E ely as Eely >> E hli . While E2 nd → E hli as Ehli >> Eely , in which case the Early
voltage V Abjt + Aely Leff is high.
4

4

i =1

i =1

To sum up, the total B-S current is I bs = ∑ I bsi , and the total B-D current is I bd = ∑ I bdi .
The total drain current including the BJT component can then be expressed as
I ds ,total = I ds ,MOSFET + I c

(3.6)

3.2. New Impact Ionization Current Equation
An accurate impact ionization current equation is crucial to the PD SOI model since it may
affect the transistor output characteristics through the body effect [11]. Hence in BSIMPD we use
a more decent expression [22] to formulate the impact ionization current Iii as


Vdiff

I ii = α 0 ( I ds ,MOSFET + Fbjtii I c ) exp 
β +βV +β V 2 
1 diff
0 diff 
 2
Vdiff = Vds − Vdsatii


 T
 L 
Vdsatii = VgsStep + Vdsatii 0  1 + Tii 
− 1  − ii 
 Tnom
  Leff 


 Esatii Leff
VgsStep = 
1+ E L
satii eff



 S V
1

Sii 2  ii 0 gst
+
 1+ S V
 1 + S V
ii 1 gsteff
iid ds







(3.7)

Here the Fbjtii I c term represents the contribution from the parasitic bipolar current. Notice that
the classical impact ionization current model [12] adopted in BSIM3v3 is actually a special case
of Eqn. (3.6) when (β 0 , β1 , β 2 ) = (− 1,0,0) . However, the dependence of log( I ii I ds ) on the drain
overdrive voltage Vdiff is quite linear [22] for state-of-the-art SOI technologies due to thermally
assisted impact ionization [23]. In this case, (β 0 , β 1 , β 2 ) ≅ (0,0,1) .

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

3-4

Body Currents Model

The extracted saturation drain voltage Vdsatii depends on the gate overdrive voltage Vgst and
Leff . One can first extract the parameters (Vdsatii 0 , Lii ) by the Vdsatii - Leff characteristics at Vgst = 0 .
All the other parameters ( E satii , S ii1 , Sii 2 , Sii 0 , S iid ) can then be determined by the plot of Vdsatii
versus Vgs for different Leff . Notice that a linear temperature dependence of Vdsatii 0 with the
parameter Tii is also included.

3.3. Gate Induced Drain Leakage Current
GIDL can be important in PD SOI because it can affect the body potential in the low Vgs and
high Vds regime. The formula for GIDL current is:
 β
I dgidl = α gidl ⋅ E s ⋅ exp − gidl
 Es

Vds − Vgs − χ

 , E s =
3 ⋅ Tox


(3.8)

Here χ is the fitting parameter with a default value 1.2, which is the correct value for uniformly
doped substrates with no LDD or fully overlapped LDD. However, in general χ can be different
from 1.2, depending on the doping profile at the drain edge [13]. For the sake of symmetry, GIDL
current is accounted for both at the drain and source side ( I sgidl ) .

3.4. Oxide Tunneling Current
For thin oxide (below 20Å), oxide tunneling is important in the determination of floatin-body
potential [20]. In BSIMPD the following equations are used to calculate the tunneling current
density Jgb:

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

3-5

Body Currents Model

In inversion,

Vaux
A=
B=

V gbVaux  Toxref

Tox2  Toxqm






(

N tox

)

 − B á gb1 − â gb1 Vox Tox
exp

1 − Vox Vgb1


 Vox − ö g  

= VEVB ln 1 + exp
 VEVB  





J gb = A






q3
8πhφ b

(3.9)

8π 2m ox φ b3 2

3hq
φ b = 4.2eV
m ox = 0.3m 0

In accumulation,
J gb
Vaux
A=
B=

(

N tox

)

 − B á gb2 − â gb2 Vox Tox
exp

1 − Vox Vgb2


 V gb − V fb  

= VECBVt ln 1 + exp −


V
ECB




V gbVaux  Toxref

=A
Tox2  Toxqm






q3
8πhφ b






(3.10)

8π 2m ox φ b3 2

3hq
φ b = 3.1eV
m ox = 0.4m0

Please see Appendix B for model parameter descriptions.

3.5. Body Contact Current
In BSIMPD, a body resistor is connected between the body (B node) and the body contact (P
node) if the transistor has a body-tie. The body resistance is modeled by
Rbp


W eff'

=  Rbody
Leff


 
W eff'
 ||  R
  halo 2
 


, R
 bodyext = Rbsh N rb


BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

(3.11)

3-6

Body Currents Model

Here Rbp and Rbodyext represent the intrinsic and extrinsic body resistance respectively. Rbody is the
intrinsic body sheet resistance, Rhalo accounts for the effect of halo implant, Nrb is the number of
square from the body contact to the device edge and Rbsh is the sheet resistance of the body
contact diffusion.
The body contact current I bp is defined as the current flowing through the body resistor:
I bp =

Vbp
Rbp + Rbodyext

(3.12)

where Vbp is the voltage across the B node and P node. Notice that I bp = 0 if the transistor has a
floating body.

3.6. Body Contact Parasitics [17]
The effective channel width may change due to the body contact. Hence the following
equations are used:
Weff = Wdrawn − N bc dWbc − (2 − N bc )dW
Weff = Wdrawn − N bc dWbc − (2 − N bc )dW '
'

Wdiod = Weff + Pdbcp
'

(3.13)

Wdios = Weff + Psbcp
'

Here dWbc is the width offset for the body contact isolation edge. N bc is the number of body
contact isolation edge. For example: N bc = 0 for floating body devices, N bc = 1 for T-gate
structures and N bc = 2 for H-gate structures. Pdbcp / Psbcp represents the parasitic perimeter length
for body contact at drain/source side. The body contact parasitics may affect the I-V significantly
for narrow width devices [20].

After introducing all the mechanisms that contribute the body current, we can express the
nodal equation (KCL) for the body node as

(I bs + I bd ) + I bp − I ii − (I dgidl + I sgidl ) − I gb = 0
BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

(3.14)

3-7

Body Currents Model

Eqn. (3.14) is important since it determines the body potential through the balance of various
body current components. The I-V characteristics can then be correctly predicted after this critical
body potential can be well anchored.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

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Chapter 4: MOS C-V Model

BSIMPD approaches capacitance modeling by adding SOI-specific capacitive effect to the
C-V model of BSIM3v3. Similar to the I-V case, the body charges belonged to the floating body
node will be our emphasis. The model incorporates features listed below with the SOI-specific
features bold-faced and italicized.
•

Separate effective channel length and width for IV and CV models.

•

The CV model is not piece-wise (i.e. divided into inversion, depletion, and
accumulation). Instead, a single equation is used for each nodal charge covering all
regions of operation. This ensures continuity of all derivatives and enhances convergence
properties. Just like in BSIM3v3, the inversion and body capacitances are continuous at
the threshold voltage.

•

Threshold voltage formulation is consistent with the IV model. Body effect and DIBL are
automatically incorporated in the capacitance model.

•

Intrinsic capacitance model has two options. The capMod = 2 option yields capacitance
model based on BSIM3v3 short channel capacitance model. The capMod = 3 option is
the new charge-thickness model from BSIM3v3.2 [4].

•

Front gate overlap capacitance is comprised of two parts: 1) a bias independent part
which models the effective overlap capacitance between the gate and the heavily doped
source/drain, and 2) a gate bias dependent part between the gate and the LDD region.

•

Bias independent fringing capacitances are added between the gate and source as well as
the gate and drain. A sidewall source/drain to substrate (under the buried oxide)
fringing capacitance is added.

•

A source/drain-buried oxide-Si substrate parasitic MOS capacitor is added.

•

Body-to-back-gate coupling is added.

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MOS C-V Model

A good intrinsic charge model is important in bulk MOSFETs because intrinsic capacitance
comprises a sizable portion of the overall capacitance, and because a well behaved charge model
is required for robust large circuit simulation convergence. In analog applications there are
devices biased near the threshold voltage. Thus, a good charge model must be well-behaved in
transition regions as well. To ensure proper behavior, both the I-V and C-V model equations
should be developed from an identical set of charge equations so that Cij/Id is well behaved.
A good physical charge model of SOI MOSFETs is even more important than in bulk. This is
because transient behavior of the floating body depends on capacitive currents [18]. Also, due to
the floating body node, convergence issues in PD SOI are more volatile than in bulk, so that
charge smoothness and robustness are important. An example is that a large negative guess of
body potential by SPICE during iterations can force the transistor into depletion, and a smooth
transition between depletion and inversion is required. Therefore the gate/source/drain/backgate
to body capacitive coupling is important in PD SOI.

4.1. Charge Conservation

Fig. 4.1

Intrinsic charge components in BSIMPD CV model

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MOS C-V Model

To ensure charge conservation, terminal charges instead of terminal voltages are used as state
variables. The terminal charges Qg, Qd, Qs, Qb, and Qe are the charges associated with the gate,
drain, source, body, and substrate respectively. These charges can be expressed in terms of
inversion charge (Qinv), front gate body charge (QBf), source junction charge (Qjs) and drain
junction charge (Qjd). The intrinsic charges are distributed between the nodes as shown in Fig.
4.1. The charge conservation equations are:
QBf = Qac 0 + Qsub0 + Qsubs
Qinv = Qinv , s + Qinv , d

Q g = − (Qinv + Q Bf

)

Qb = Q Bf − Q e + Q js + Q jd

(4.1)

Qs = Qinv ,s − Q js
Qd = Qinv ,d − Q jd
Qg + Qe + Qb + Qs + Qd = 0
The front gate body charge (QBf) is composed of the accumulation charge (Qac0) and the bulk
charge ( Q sub 0 and Q subs ), which may be divided further into two components: the bulk charge at
Vds=0 (Qsub0), and the bulk charge induced by the drain bias (Qsubs) (similar to δQsub in
BSIM3v3).
All capacitances are derived from the charges to ensure charge conservation. Since there are
5 charge nodes, there are 25 (as compared to 16 in BSIM3v3) components. For each component:
Cij =

dQi
, where i and j denote transistor nodes. In addition,
dV j

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

∑C = ∑C
ij

i

ij

= 0.

j

4-3

MOS C-V Model

4.2. Intrinsic Charges
BSIMPD uses similar expressions to BSIM3v3 for Qinv and Q Bf . First, the bulk charge
constant AbulkCV is defined as
AbulkCV

  CLC
= Abulk 0 1 + 
  Lactive






CLE






Abulk 0 = Abulk (Vgsteff = 0)

where

(4.2)

(4.3)

This is done in order to empirically fit VdsatCV to channel length. Experimentally,
VdsatIV < VdsatCV < VdsatIV

L→∞

=

V gsteffCV
Abulk

(4.4)

The effective CV Vgst is defined as

V gs − Vth 
V gsteffCV = nv t ln1 + exp 


 nv t 

(4.5)

Then we can calculate the CV saturation drain voltage
VdsatCV = V gsteffCV / AbulkCV .

(4.6)

1
VdsCV = VdsatCV − (VdsatCV − Vds − δ + (VdsatCV − Vds − δ ) 2 + 4δVdsatCV )
2

(4.7)

Define effective CV Vds as

Then the inversion charge can be expressed as

Qinv





2
2


AbulkCV
A
V

bulkCV
dsCV
= −Wactive Lactive Cox  V gsteffCV −
VdsCV  +

2
2



AbulkCV



12V gsteffCV −
VdsCV  

2




(4.8)

where Wactive and Lactive are the effective channel width and length in CV, respectively. The
channel partition can be set by the Xpart parameter. The exact evaluation of source and drain
charges for each partition option is presented in Appendix C.

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MOS C-V Model

A parameter VFBeff is used to smooth the transition between accumulation and depletion
regions. The expression for VFBeff is:

VFBeff = V fb − 0.5 V fb − Vgb − δ +


(

)

where Vgb = Vgs − Vbseff , V fb = Vth − φ s − K1eff φ s − Vbseff

(V fb − Vgb − δ )

2


+δ2


(4.9)

.

The physical meaning of the function is the following: it is equal to Vgb for VgbVFB. Using VFBeff, the accumulation charge can be calculated as
Qac 0 = − FbodyWactive LactiveB C ox (VFBeff − V fb )

(4.10)

where LactiveB = Lactive − DLCB . Notice that the parameters Fbody and DLCB are provided to give
a better fit for the SOI-specific history dependence of the body charge [14].
The gate-induced depletion charge and drain-induced depletion charge can be expressed as
2
K1eff 
4(Vgs − VFBeff − VgsteffCV − Vbseff ) 
Q sub 0 = − FbodyWactive LactiveB Cox
−1 + 1 +
(4.11)
2

2 
K
1eff


2

V
AbulkCV VdsCV
Q subs = FbodyWactive LactiveB K 1eff C ox (1 − AbulkCV ) dsCV −

12(VgsteffCV − AbulkCV VdsCV 2 )
 2

(4.12)

respectively.
Finally, the back gate body charge can be modeled by
Qe = FbodyWactive LactiveBG C box (Ves − V fbb − Vbseff

)

(4.13)

where LactiveBG = LactiveB + 2δLbg . The parameter δLbg is provided to count the difference of LactiveB
and LactiveBG due to the source/drain extension in the front channel.
For capMod=3, the flat band voltage is calculated from the bias-independent threshold
voltage, which is different from capMod=2. For the finite thickness formulation, refer to Chapter
4 of BSIM3v3.2 Users’ Manual.

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MOS C-V Model

4.3. Source/Drain Junction Charges
Beside the junction depletion capacitance considered in BSIM3v3, the diffusion capacitance,
which is important in the forward body-bias regime [20], is also included in BSIMPD. The
source/drain junction charges Q jswg / Q jdwg can therefore be expressed as
Q jswg = Qbsdep + Qbsdif

(4.14)

Q jdwg = Qbddep + Qbddif

The depletion charges Qbsdep / Qbddep have similar expressions as in BSIM3v3 [Appendix C].
While the diffusion charges Qbsdif / Qbddif can be modeled by
Qbsdif

N dif


 1

1

= τWeff ' Tsi J sbjt 1 + Ldif 0 Lbjt 0 
+ 
L



 eff Ln 



   V
 exp bs
   n dioVt
  

 
1
 − 1
  E hlis + 1

Qbddif

N dif


 1

1

= τWeff ' Tsi J sbjt 1 + Ldif 0 Lbjt 0 
+ 
L


Ln 
eff




   V
 exp  bd
   ndioVt
  

 
1
 − 1
  E hlid + 1

(4.15)

The parameter τ represents the transit time of the injected minority carriers in the body. The
parameters Ldif 0 and N dif are provided to better fit the data.

4.4. Extrinsic Capacitances
Expressions for extrinsic (parasitic) capacitances that are common in bulk and SOI
MOSFETs are taken directly from BSIM3v3. They are source/drain-to-gate overlap capacitance
and source/drain-to-gate fringing capacitance. Additional SOI-specific parasitics added are
substrate-to-source sidewall capacitance Cessw, and substrate-to-drain sidewall capacitance Cedsw,
substrate-to-source bottom capacitance (Cesb) and substrate-to-drain bottom capacitance (Cedb)
[Fig. 4.2].

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MOS C-V Model

C essw
C esb
Fig. 4.2

SOI MOSFET extrinsic charge components. Cessw is the
substrate-to-source sidewall capacitance. Cesb is the substrateto-source bottom capacitance.

In SOI, there is a parasitic source/drain-buried oxide-Si substrate parasitic MOS structure
with a bias dependent capacitance. If Vs,d=0, this MOS structure might be in accumulation.
However, if Vs,d=Vdd, the MOS structure is in depletion with a much smaller capacitance,
because the Si substrate is lightly doped. The bias dependence of this capacitance is similar to
high frequency MOS depletion capacitance as shown in Fig. 4.3. It might be substantial in
devices with large source/drain diffusion areas. BSIMPD models it by piece-wise expressions,
with accurately chosen parameters to achieve smoothness of capacitance and continuity to the
second derivative of charge. The substrate-to-source bottom capacitance (per unit source/drain
area) Cesb is:

Cesb

Cbox


2
 Vse − Vsdfb 
1




 Cbox − A ( Cbox − Cmin ) V
 sdth − Vsdfb 
sd
=
2
 Vse − Vsdth 

1
( C − Cmin ) V − V 
Cmin +
1 − Asd box
 sdth
sdfb 


Cmin

if

Vse < Vsdfb

elseif

Vse < Vsdfb + Asd Vsdth − Vsdfb

elseif

Vse < Vsdth

(

)

(4.16)

else

Physical parameters Vsdfb (flat-band voltage of the MOS structure) and Vsdth (threshold voltage of
the MOS structure) can be easily extracted from measurement. Cmin should also be extracted
from measurement, and it can account for deep depletion as well. Asd is a smoothing parameter.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

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MOS C-V Model

The expression for Cedb is similar to Cesb. Fig. 4.3 shows the comparison of the model and
measured Cesb.
measured data
model fit

Capacitance (fF)

160

140

120

100

80
-4

-2

0

2

4

V s/d,e
Fig. 4.3

Bottom source/drain to substrate capacitance for a PD SOI
MOSFET.

Finally, the sidewall source/drain to substrate capacitance (per unit source/drain perimeter
length) can be expressed by

T
C s / d ,esw = C sdesw log1 + si
 Tbox





(4.17)

which depends on the silicon film thickness Tsi and the buried oxide thickness Tbox . The
parameter C sdesw represents the fringing capacitance per unit length.

4.5. Body Contact Parasitics
The parasitic capacitive coupling due to the body contact is considered in BSIMPD. The
BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

4-8

MOS C-V Model

instance parameter Agbcp represents the parasitic gate-to-body overlap area due to the body
contact, and Aebcp represents the parasitic substrate-to-body overlap area. The effect may be
significant for small area devices [CV part in Appendix C].

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

4-9

Chapter 5: Temperature Dependence and Self-Heating

Self-heating in SOI is more important than in bulk since the thermal conductivity of silicon
dioxide is about two orders of magnitude lower than that of silicon [15]. It may degrade the
carrier mobility, increase the junction leakage [20], enhance the impact ionization rate[24], and
therefore affect the output characteristics [16] of floating-body SOI devices.

5.1. Temperature Dependence
The temperature dependence of threshold voltage, mobility, saturation velocity and series
resistance in BSIMPD is identical to BSIM3v3. However a different temperature dependence of
diode characteristics is adopted in BSIMPD:
 − E (300 K )

T 

jsbjt = jsbjt 0 exp  g
X bjt 1 −
 Tnom 
 ndioVt
 − E (300 K )

T 

jsdif = jsdif 0 exp  g
X dif 1 −
n
V
T
dio
t
nom



 − Eg (300 K )

T 

jsrec = jsrec 0 exp 
X rec 1 −
 nrecf 0Vt
 Tnom 

 T

jstun = jstun 0 exp  Xtun 
− 1 
 Tnom



(5.1)


 T

nrecf = nrecf 0 1 + nt recf 
− 1  

 Tnom
 

 T

nrecr = nrecr 0 1 + nt recr 
− 1  
 Tnom
 


The parameters j sbjt 0 , jsdif 0 , j srec 0 , jstun 0 are diode saturation currents at the nominal temperature
Tnom , and the parameters X bjt , X dif , X rec , X tun are provided to model the temperature dependence.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

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Temperature Dependence and Self-Heating

Notice that the non-ideality factors n recf , n recr are also temperature dependent.

5.2. Self-Heating Implementation
BSIMPD models the self-heating by an auxiliary Rth C th circuit as shown in Fig. 5.1 [18]. The
temperature node (T node) will be created in SPICE simulation if the self-heating selector shMod
is ON and the thermal resistance is non-zero. The T node is treated as a voltage node and is
connected to ground through a thermal resistance Rth and a thermal capacitance Cth:
Rth =

Rth0
'
Weff

+ Wth0

'
, C th = C th0 ( Weff
+ Wth0 )

(5.2)

where Rth 0 and C th 0 are normalized thermal resistance and capacitance, respectively. Wth0 is the
minimum width for thermal resistance calculation [19]. Notice that the current source is driving a
current equal to the power dissipated in the device.
P = I ds × Vds

(5.3)

To save computation time, the turn-on surface potential φs (Phi) is taken to be a constant
within each timepoint because a lot of parameters (e.g. Xdep) are function of φs. Each timepoint
will use a φs calculated with the temperature iterated in the previous timepoint. However this
approximation may induce error in DC, transient and AC simulation. Therefore, it is a tradeoff
between accuracy and speed. The error in DC or transient is minimal if the sweeping step or time
step is sufficiently small.

IdVd

Fig. 5.1

Rth

Cth

Equivalent circuit for self-heating simulation.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

5-2

Chapter 6: BSIMSOI –

A Unified Model for PD and FD SOI MOSFETs

Using BSIMPD as a foundation, we have developed a unified model for both PD and FD SOI
circuit designs based on the concept of body-source built-in potential lowering [20, 25].

6.1. BSIMSOI Framework and Built-In Potential Lowering Model
As described in [20], we construct BSIMSOI based on the concept of body-source built-in
potential lowering, ∆Vbi. There are three modes (soiMod = 0, 1, 2) in BSIMSOI: BSIMPD
(soiMod = 0) can be used to model the PD SOI device, where the body potential is independent
on ∆Vbi (VBS > ∆Vbi). Therefore the calculation of ∆Vbi is skipped in this mode. On the other
hand, the ideal FD model (soiMod = 2) is for the FD device with body potential equal to ∆Vbi.
Hence the calculation of body current/charge, which is essential to the PD model, is skipped. For
the unified SOI model (soiMod = 1), however, both ∆Vbi and body current/charge are calculated
to capture the floating-body behavior exhibited in FD devices. As shown in Figure 6.1, this unified
model covers both BSIMPD and the ideal FD model.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

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BSIMSOI – A Unified Model for PD and FD SOI MOSFETs

soiMod=0 (BSIMPD)
soiMod=1 (Unified Model)
soiMod=2 (Ideal FD)

0.7
0.6

∆Vbi

VBS (V)

0.5
0.4
0.3
0.2

VGS=0.5V
L=0.5 µm
TSi=40nm

0.1
0.0
0.0

0.5

1.0

1.5

2.0

VDS (V)
Fig. 6.1 The body potential in the unified model approaches the VBS solved in BSIMPD for PD
devices, while returns to ∆Vbi for ideal FD devices [20].

This unified model shares the same floating-body module as BSIMPD, with a generalized
diode current model considering the body-source built-in potential lowering effect (IBS ∝ exp(q∆Vbi/kT)). Therefore, an accurate and efficient ∆Vbi model is crucial. The following formulation
for ∆Vbi is mainly based on the Poisson equation and the physical characterization for ∆Vbi, as
presented in [25].
For a given surface band bending φ (source reference), ∆Vbi can be formulated by applying the
Poisson equation in the vertical direction and continuity of normal displacement at the back
interface:

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BSIMSOI – A Unified Model for PD and FD SOI MOSFETs

∆Vbi (φ ) =



qN ch
C BOX
2
⋅ (VbGS − VFBb )
⋅  φ −
⋅ TSi + ∆VDIBL  + ηe Leff
CSi + C BOX
2ε Si


ε
ε
ε
CSi = Si , C BOX = OX , COX = OX
TSi
TBOX
TOX

CSi
C Si + C BOX

( )

(6-1).

The first term of Equation (6-1) represents the frontgate coupling. TSi is the SOI thickness. Nch
accounts for the effective channel doping, which may vary with channel length due to the nonuniform lateral doping effect. The second term of Equation (6-1) represents the backgate coupling
(VbGS). VFBb is the backgate flatband voltage. Equation (6-1) shows that the impact of frontgate on
∆Vbi reaches maximum when the buried oxide thickness, TBOX, approaches infinity.
In Equation (6-1), ∆VDIBL represents the short channel effect on ∆Vbi,

L 
Leff 


 + 2 exp − Dvbd 1 eff   ⋅ (Vbi − 2Φ B )
∆V DIBL = Dvbd 0  exp − Dvbd 1


l  
2l 




(6-2),

as addressed in [25]. Here l is the characteristic length for the short-channel-effect calculation.
Dvbd0 and Dvbd1 are model parameters. Similarly, the following equation

L 
L


ηe Leff = K1b − K 2 b ⋅  exp − Dk 2b eff  + 2 exp − Dk 2b eff

2l 
l




( )


 



(6-3)

is used to account for the short channel effect on the backgate coupling, as described in [25].
DK1b, DK2b, K1b (default 1) and K2b (default 0) are model parameters.
The surface band bending, φ, is determined by the frontgate VGS and may be approximated by

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BSIMSOI – A Unified Model for PD and FD SOI MOSFETs

φ ={

Φ ON

for VGS ≥ VT

(6-4).
Φ ON −

(

COX

COX + CSi

−1

+ C BOX

)

−1 − 1

⋅ (VT − VGS ) for VGS ≤ VT

To improve the simulation convergency, the following single continuous function from
subthreshold to strong inversion is used:

φ = Φ ON −

(

COX

COX + CSi

−1

+ C BOX

)

−1 −1


V
− Vgs _ eff − VOFF ,FD  

⋅ N OFF , FDVt ⋅ ln 1 + exp T ,FD



N OFF ,FDVt




(6-5).

Here Vgs_eff is the effective gate bias considering the poly-depletion effect. VT,FD is the threshold
voltage at VBS = ∆Vbi(φ=2ΦB). NOFF,FD (default 1) and VOFF,FD (default 0) are model parameters
introduced to improve the transition between subthreshold and strong inversion. Vt is the thermal
voltage. Notice that the frontgate coupling ratio in the subthreshold regime approaches 1 as TBOX
approaches infinity.
To accurately model ∆Vbi and thus the device output characteristics, the surface band bending
at strong inversion, ΦON, is not pinned at 2ΦB. Instead, the following equation

(

 V gsteff .FD V gsteff ,FD + 2 K 1 2Φ B
Φ ON = 2Φ B + Vt ln 1 +

moin ⋅ K 1 ⋅ Vt 2


) 



(6-6)

is used to account for the surface potential increment with gate bias in the strong inversion regime
[4]. Here moin is a model parameter. K1 is the body effect coefficient. Notice that a single
continuous function,


 Vgs _ eff − VT ,FD − VOFF ,FD  

Vgsteff ,FD = N OFF ,FDVt ⋅ ln 1 + exp



N
V
OFF
,
FD
t




BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

(6-7),

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BSIMSOI – A Unified Model for PD and FD SOI MOSFETs

has been used to represent the gate overdrive in Equation (6-6).

6.2. Verification
The BSIMPD parameter extraction methodology presented in [20] may still be used under the
unified BSIMSOI framework, provided that the link between PD and FD, ∆Vbi, can be accurately
extracted. As described in [25], a direct probe of ∆Vbi can be achieved by finding the onset of the
external body bias (through a body contact) after which the threshold voltage and hence the
channel current of the FD SOI device is modulated. When the body contact is not available,
nevertheless, model parameters related to ∆Vbi should be extracted based on the subthreshold
characteristics of the floating-body device. As shown in Figure 6.2, the reduction of ∆Vbi with
backgate bias is responsible for the transition from the ideal subthreshold swing (~ 60 mV/dec. at
room temperature) to the non-ideal one.

10

-4

10

-5

ID (A)

10

-6

-7

10

-8

10

-9

10
10
10

o

T=27 C

10

10

LG=0.5µm
VDS=0.05V

~67mV/dec.

~102mV/dec.

V bGS=4V
2V
0V
-2V
-4V
line: model

-10

-11

-12

-13

-0.5

0.0

0.5

1.0

1.5

VGS (V)
Fig. 6.2 The PD/FD transition can be captured by modeling ∆Vbi [20].

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

6-5

BSIMSOI – A Unified Model for PD and FD SOI MOSFETs

Figure 6.2 clearly shows that the PD/FD transition can be captured by the ∆Vbi approach. In
other words, ∆Vbi is indeed an index of the degree of full depletion, as pointed out in [20, 25]. As
shown in Figure 6.3, larger floating-body effect can be observed for negative backgate bias due to
smaller ∆Vbi. In case the ∆Vbi value is raised by charge sharing as described in [25], it can be
predicted that the short-channel device should exhibit less floating-body effect than the longchannel one due to larger ∆Vbi, as verified in Figure 6.4.

0.0020

L G=0.5µ m
line: model
V bGS =0V
V bGS =-1.5V
0.0015

VGS=1.5V

ID (A)

1.2V
0.0010

0.9V
0.0005

0.6V
0.0000

0.0

0.3

0.6

0.9

1.2

1.5

VDS (V)
Fig. 6.3 Larger floating-body effect can be seen for the negative backgate bias (source reference)
due to smaller ∆Vbi [20].

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

6-6

BSIMSOI – A Unified Model for PD and FD SOI MOSFETs

Fig. 6.4 Less floating-body effect can be seen for the short-channel device due to larger ∆Vbi [20].

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

6-7

Chapter 7: BSIMSOI RF model

RF Model in BSIMSOIv3.1
BSIMSOI3.1 provides the gate resistance model for devices used in RF application.
Users have four options for modeling gate electrode resistance (bias independent) and
intrinsic-input resistance (Rii, bias-dependent) by choosing model choice parameter
rgateMod.
RgateMod = 0 (zero-resistance):

In this case, no gate resistance is generated.
RgateMod = 1 (constant-resistance):

Rgeltd

In this case, only the electrode gate resistance (bias-independent) is generated by adding
an internal gate node. The electrode gate resistance Rgeltd is given by
Weff



RSHG ⋅  XGW +

3
⋅
NGCON
⋅
NSEG


Rgeltd =
NGCON ⋅ (Ldrawn − XGL )

RgateMod = 2 (RII model with variable resistance):

Rgeltd+
Rii

In this case, the gate resistance is the sum of the electrode gate resistance and the
intrinsic-input resistance Rii as given by
 I
Weff µ eff C oxeff k B T 
1

= XRCRG1 ⋅  ds + XRCRG 2 ⋅
V

qL
Rii
eff
 dseff

An internal gate node will be generated.
RgateMod = 3 (RII model with two nodes):
In this case, the gate electrode resistance is in series with the intrinsic-input resistance Rii
through two internal gate nodes, so that the overlap capacitance current will not pass
through the intrinsic-input resistance.

Rgeltd
Cgso

Rii

Cgdo

References

[1]

Y. Cheng, M. C. Jeng, Z. H. Liu, J. Huang M. Chan, P. K. Ko, and C. Hu, “A Physical
and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation”, IEEE Trans.
On Elec. Dev., vol. 42, p. 2, Feb 1997.

[2]

BSIM3SOIv1.3 Users’ Manual, UC Berkeley, Department of EECS.

[3]

W. Jin, P. C. H. Chan, S. K. H. Fung, P. K. Ko, “A Physically-Based Low-Frequency
Noise Model for NFD SOI MOSFET’s”, IEEE Intl. SOI conf., pp. 23-24, 1998.

[4]

BSIM3v3.2 Users’ Manual, UC Berkeley, Department of EECS.

[5]

D. Suh, J. G. Fossum, “A physical charge-based model for non-fully depleted SOI
MOSFET’s and its use in assessing floating-body effects in SOI CMOS circuits”, IEEE
Tran. on Electron Devices, vol. 42, no. 4, pp. 728-37, April 1995.

[6]

M. S. L. Lee, W. Redman-White, B. M. Tenbroek, M. Robinson, “Modelling of thin film
SOI devices for circuit simulation including per-instance dynamic self-heating effects”,
IEEE Intl. SOI conf., pp. 150-151, 1993.

[7]

D. Sinitsky, S. Tang, A. Jangity, F. Assaderaghi, G. Shahidi, C. Hu, “Simulation of SOI
Devices and Circuits using BSIM3SOI”, IEEE Electron Device Letters, vol. 19, no. 9,
pp. 323-325, September 1998.

[8]

G. S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989.

[9]

M. C. Jeng, “Design and Modeling of Deep-Submicrometer MOSFETs”, Ph. D.
Dissertation, UC Berkeley.

[10]

D. Sinitsky, S. Fung, S. Tang, P. Su, M. Chan, P. Ko, C. Hu, “A Dynamic Depletion SOI
MOSFET Model for SPICE”, in Dig. Tech. Papers, Symp. VLSI Technology, 1998.

[11]

D. Sinitsky, R. Tu, C. Liang, M. Chan, J. Bokor and C. Hu, “AC output conductance of
SOI MOSFETs and impact on analog applications”, IEEE Electron Device Letters,
vol.18, no.2, pp. 36-38, Feb 1997.

[12]

T. Y. Chan, P. K. Ko and C. Hu, “A Simple Method to Characterize Substrate Current in
MOSFETs”, IEEE Electron Dev. Letts., EDL-5, Dec 1984, p. 505.

[13]

S. A. Parke, J. E. Moon, H. C. Wann, P. K. Ko and C. Hu, “Design for suppression of
gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical
model”, IEEE Trans. On Electron Device, vol. 39, no. 7, pp. 1697-703, July 1992.

[14]

J. Gautier and J. Y.-C. Sun, “On the transient operation of partially depleted SOI
NMOSFET’s”, IEEE Electron device letters, vol.16, no.11, pp. 497-499, Nov 1995.

[15]

L. T. Su, D. A. Antoniadis, M. I. Flik, J. E. Chung, “Measurement and modeling of selfheating effects in SOI nMOSFETs”, IEDM tech. Digest, pp. 357-360, 1994.

[16]

R. H. Tu, C. Wann, J. C. King, P. K. Ko, C. Hu, “An AC Conductance Technique for
Measuring Self-Heating in SOI MOSFET’s”, IEEE Electron device letters, vol.16, no.2,
pp. 67-69, Feb. 1995.

[17]

P. Su, S. K. H. Fung, F. Assaderaghi, C. Hu, “A Body-Contact SOI MOSFET Model for
Circuit Simulation”, Proceedings of the 1999 IEEE Intl. SOI Conference, pp.50-51.

BSIMSOI3.1 Manual Copyright ©2003, UC Berkeley

[18]

P. Su, S. K. H. Fung, S. Tang, F. Assaderaghi and C. Hu, "BSIMPD: A Partial-Depletion
SOI MOSFET Model for Deep-Submicron CMOS Designs", Proceedings of the IEEE
2000 Custom Integrated Circuits Conference, pp.197-200.

[19]

H. Nakayama, P. Su , C. Hu, M. Nakamura, H. Komatsu, K. Takeshita, Y. Komatsu,
“Methodology of Self-Heating Free Parameter Extraction and Circuit Simulation for SOI
CMOS”, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, pp.381384.

[20]

P. Su, “An International Standard Model for SOI Circuit Design,” Ph. D. Dissertation,
Department of EECS, University of California at Berkeley, December 2002.
(http://www.eecs.berkeley.edu/~pinsu)

[21]

http://www.eigroup.org/cmc

[22]

P. Su, S. Fung, H. Wan, A. Niknejad, M. Chan and C. Hu, "An impact ionization model
for SOI circuit simulation," 2002 IEEE International SOI Conference Proceedings,
Williamsburg, VA, Oct. 2002, pp. 201-202.

[23]

P. Su, K. Goto, T. Sugii and C. Hu, "A thermal activation view of low voltage impact
ionization in MOSFETs," IEEE Electron Device Letters, vol. 23, no. 9, September 2002.

[24]

P. Su, K. Goto, T. Sugii and C. Hu, "Enhanced substrate current in SOI MOSFETs,"
IEEE Electron Device Letters, vol. 23, no. 5, pp. 282-284, May 2002.

[25]

P. Su, S. Fung, P. Wyatt, H. Wan, A. Niknejad, M. Chan and C. Hu , “On the bodysource built-in potential lowering of SOI MOSFETs,” IEEE Electron Device Letters, vol.
24, no. 2, February 2003.

BSIMSOI3.1 Manual Copyright ©2003, UC Berkeley

BSIMSOI3.1 Manual Copyright ©2003, UC Berkeley

Appendix A: Model Instance Syntax
Mname     [P node]
[B node] [T node] 
[L=] [W=]
[AD=] [AS=] [PD=] [PS=]
[NRS=] [NRD=] [NRB=]
[OFF][BJTOFF=]
[IC=,,,,]
[RTH0=] [CTH0=]
[DEBUG=]
[NBC=] [NSEG=] [PDBCP=] [PSBCP=]
[AGBCP=][AEBCP=][VBSUSR=][TNODEOUT]
[FRBODY=]

A.1. Description


Drain node



Gate node



Source node



Substrate node

[P node]

(Optional) external body contact node

[B node]

(Optional) internal body node

[T node]

(Optional) temperature node



Level 9 BSIM3SOI model name

[L]

Channel length

[W]

Channel width

[AD]

Drain diffusion area

[AS]

Source diffusion area

[PD]

Drain diffusion perimeter length

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

A-1

[PS]

Source diffusion perimeter length

[NRS]

Number of squares in source series resistance

[NRD]

Number of squares in drain series resistance

[NRB]

Number of squares in body series resistance

[OFF]

Device simulation off

[BJTOFF]

Turn off BJT current if equal to 1

[IC]

Initial guess in the order of (Vds, Vgs, Vbs, Ves, Vps). (Vps will be
ignored in the case of 4-terminal device)

[RTH0]

Thermal resistance per unit width
n if not specified, RTH0 is extracted from model card.
n if specified, it will override the one in model card.

[CTH0]

Thermal capacitance per unit width
n if not specified, CTH0 is extracted from model card.
n if specified, it will over-ride the one in model card.

[DEBUG]

Please see the debugging notes

[NBC]

Number of body contact isolation edge

[NSEG]

Number of segments for channel width partitioning [17]

[PDBCP]

Parasitic perimeter length for body contact at drain side

[PSBCP]

Parasitic perimeter length for body contact at source side

[AGBCP]

Parasitic gate-to-body overlap area for body contact

[AEBCP]

Parasitic body-to-substate overlap area for body contact

[VBSUSR]

Optional initial value of Vbs specified by user for transient analysis

[TNODEOUT]

Temperature node flag indicating the usage of T node

[FRBODY]

Layout-dependent body resistance coefficient

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

A-2

A.2. About Optional Nodes
There are three optional nodes, P, B and T nodes. P and B nodes are used for body
contact devices. Let us consider the case when TNODEOUT is not set. If user specifies four
nodes, this element is a 4-terminal device, i.e., floating body. If user specifies five nodes, the
fifth node represents the external body contact node (P). There is a body resistance between
internal body node and P node. In these two cases, an internal body node is created but it is not
accessible in the circuit deck. If user specifies six nodes, the fifth node represents the P node and
the sixth node represents the internal body node (B). This configuration is useful for distributed
body resistance simulation.
If TNODEOUT flag is set, the last node is interpreted as the temperature node. In this
case, if user specifies five nodes, it is a floating body case. If user specifies six nodes, it is a
body-contacted case. Finally, if user specifies seven nodes, it is a body-contacted case with an
accessible internal body node. The temperature node is useful for thermal coupling simulation.

A.3. Notes on Debugging
The instance parameter  allows users to turn on debugging information
selectively. Internal parameters (e.g. par) for an instance (e.g. m1) can be plotted by this
command:
plot m1#par

By default,  is set to zero and two internal parameters will be available for
plotting:
#body

Vb value iterated by SPICE

#temp

Device temperature with self-heating mode turned on

If  is set to one or minus one, more internal parameters are available for
plotting. This serves debugging purposes when there is a convergence problem. This can also
help the user to understand the model more. For  set to minus one, there will be
charge calculation even if the user is running DC simulation. Here is the list of internal
parameters:

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

A-3

#Vbs

Real Vbs value used by the IV calculation

#Vgsteff

Effective gate-overdrive voltage

#Vth

Threshold voltage

#Ids

MOS drain current

#Ic

BJT current

#Ibs

Body to source diode current

#Ibd

Body to drain diode current

#Iii

Impact ionization current

#Igidl

GIDL current

#Itun

Tunneling current

#Ibp

Body contact current

#Gds

Output conductance

#Gm

Transconductance

#Gmb

Drain current derivative wrt Vbs

These parameters are valid only if charge computation is required
#Cbb

Body charge derivative wrt Vbs

#Cbd

Body charge derivative wrt Vds

#Cbe

Body charge derivative wrt Ves

#Cbg

Body charge derivative wrt Vgs

#Qbody

Total body charge

#Qgate

Gate charge

#Qac0

Accumulation charge

#Qsub

Bulk charge

#Qsub0

Bulk charge at zero drain bias

#Qbf

Channel depletion charge

#Qjd

Parasitic drain junction charge

#Qjs

Parasitic source junction charge

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

A-4

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

A-5

Appendix B: Model Parameter List
All model parameters additional to BSIM3v3 will be shown with bold cases.

B.0. BSIMSOI Built-In Potential Lowering (∆
∆Vbi) Model Parameters
Symbol
used in
equation
SoiMod

Symbol used
in SPICE

Description

Unit

Default

soiMod

-

0

Vnonideal
NOFF,FD
VOFF,FD
K1b
K2b

vbsa
nofffd
vofffd
K1b
K2b

V
V
-

0
1
0
1
0

Dk2b

dk2b

-

0

Dvbd0

dvbd0

-

0

Dvbd1

dvbd1

-

0

MoinFD

moinfd

SOI model selector.
SoiMod=0: BSIMPD.
SoiMod=1: unified model for PD&FD.
SoiMod=2: ideal FD.
Offset voltage due to non-idealities
Smoothing parameter in FD module
Smoothing parameter in FD module
First backgate body effect parameter
Second backgate body effect parameter
for short channel effect
Third backgate body effect parameter
for short channel effect
First short channel effect parameter in
FD module
Second short channel effect parameter
in FD module
Gate bias dependence coefficient of
surface potential in FD module

-

1e3

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-1

B.1. BSIMPD Model Control Parameters
Symbol

Symbol

used in

used in

equation

SPICE

None

level

Level 9 for BSIM3SOI

-

9

Shmod

shMod

Flag for self-heating

-

0

Description

Unit

Default Notes (below

the table)
-

0 - no self-heating,
1 - self-heating
Mobmod

mobmod Mobility model selector

-

1

-

Capmod

capmod

Flag for the short channel capacitance model

-

2

nI-1

Noimod

noimod

Flag for Noise model

-

1

-

-

0

-

RgateMod rgateMod Gate resistance model selector

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-2

B.2. Process Parameters
Symbol

Symbol

used in

used in

equation

SPICE

tsi

Tsi

Silicon film thickness

m

10-7

-

tbox

Tbox

Buried oxide thickness

m

3x10-7

-

tox

Tox

Gate oxide thickness

m

1x10-8

-

Xj

Xj

S/D junction depth

m

nI-2

-

nch

Nch

Channel doping concentration

1/cm3 1.7x1017

nsub

Nsub

Substrate doping concentration

1/cm3

6x1016

nI-3

Ngate

ngate

poly gate doping concentration

1/cm3

0

-

Unit

Default

Notes (below the

Description

Unit

Default

Notes
(below the table)

-

B.3. DC Parameters
Symbol

Symbol

used in

used in

equation

SPICE

Vth0

vth0

Description

table)
Threshold voltage @Vbs=0 for long and

-

0.7

-

V1/2

0.6

-

m

0

-

m

0

-

wide device
K1

k1

First order body effect coefficient

K1w1

k1w1

First body effect width dependent
parameter

K1w2

k1w2

Second body effect width dependent
parameter

K2

k2

Second order body effect coefficient

-

0

-

K3

k3

Narrow width coefficient

-

0

-

K3b

k3b

Body effect coefficient of k3

1/V

0

-

Kb1

Kb1

Backgate body charge coefficient

-

1

-

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-3

W0

w0

Narrow width parameter

m

0

-

NLX

nlx

Lateral non-uniform doping parameter

m

1.74e-7

-

Dvt0

Dvt0

first coefficient of short-channel effect

-

2.2

-

-

0.53

-

1/V

-0.032

-

-

0

-

-

5.3e6

-

1/V

-0.032

-

on Vth
Dvt1

dvt1

Second coefficient of short-channel
effect on Vth

Dvt2

dvt2

Body-bias coefficient of short-channel
effect on Vth

Dvt0w

dvt0w

first coefficient of narrow width effect
on Vth for small channel length

Dvt1w

dvt1w

Second coefficient of narrow width
effect on Vth for small channel length

Dvt2w

dvt2w

Body-bias coefficient of narrow width
effect on Vth for small channel length

µ0

u0

Mobility at Temp = Tnom

cm2/(

NMOSFET

V-sec)

PMOSFET
Ua

ua

First-order mobility degradation

670
250

m/V

2.25e-9

-

(m/V) 5.9e-19

-

coefficient
Ub

ub

Second-order mobility degradation
coefficient

Uc

uc

Body-effect of mobility degradation

2

1/V

-.0465

-

m/sec

8e4

-

-

1.0

-

1/V

0.0

-

m

0.0

-

coefficient
vsat

vsat

Saturation velocity at Temp=Tnom

A0

a0

Bulk charge effect coefficient for
channel length

Ags

ags

Gate bias coefficient of Abulk

B0

b0

Bulk charge effect coefficient for
channel width

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-4

B1

b1

Bulk charge effect width offset

m

0.0

-

Keta

keta

Body-bias coefficient of bulk charge

V-1

0

-

V

0

-

1/V

0.0

-

0

1.0

-

Ω-

100

-

1/V

0

-

1/V1/2

0

-

-

1

-

effect
Ketas

Ketas

Surface potential adjustment for bulk
charge effect

A1

A1

First non-saturation effect parameter

A2

A2

Second non-saturation effect parameter

Rdsw

rdsw

Parasitic resistance per unit width

µmWr
Prwb

prwb

Body effect coefficient of Rdsw

Prwg

prwg

Gate bias effect coefficient of Rdsw

Wr

wr

Width offset from Weff for Rds
calculation

Nfactor

nfactor

Subthreshold swing factor

-

1

-

Wint

wint

Width offset fitting parameter from I-V

m

0.0

-

m

0.0

-

m/V

0.0

m/V1/2

0.0

m

0.0

V

-0.08

-

-

0.08

-

1/V

-0.07

-

-

0.56

-

without bias
Lint

lint

Length offset fitting parameter from I-V
without bias

DWg

dwg

Coefficient of Weff’s gate dependence

DWb

dwb

Coefficient of Weff’s substrate body bias
dependence

DWbc

Dwbc

Width offset for body contact isolation
edge

Voff

voff

Offset voltage in the subthreshold region
for large W and L

Eta0

eta0

DIBL coefficient in subthreshold region

Etab

etab

Body-bias coefficient for the
subthreshold DIBL effect

Dsub

dsub

DIBL coefficient exponent

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-5

Cit

cit

Interface trap capacitance

F/m2

0.0

-

Cdsc

cdsc

Drain/Source to channel coupling

F/m2

2.4e-4

-

capacitance
Cdscb

cdscb

Body-bias sensitivty of Cdsc

F/m2

0

-

Cdscd

cdscd

Drain-bias sensitivty of Cdsc

F/m2

0

-

Pclm

pclm

Channel length modulation parameter

-

1.3

-

Pdibl1

pdibl1

First output resistance DIBL effect

-

.39

-

-

0.086

-

-

0.56

-

correction parameter
Pdibl2

pdibl2

Second output resistance DIBL effect
correction parameter

Drout

drout

L dependence coefficient of the DIBL
correction parameter in Rout

Pvag

pvag

Gate dependence of Early voltage

-

0.0

-

δ

delta

Effective Vds parameter

-

0.01

-

α0

alpha0

The first parameter of impact ionization

m/V

0.0

-

-

0.0

-

V-1

0

-

-

0

-

V

0.1

-

V

0.9

-

-

0

-

current
Fbjtii

fbjtii

Fraction of bipolar current affecting
the impact ionization

β0

beta0

First Vds dependent parameter of
impact ionization current

β1

beta1

Second Vds dependent parameter of
impact ionization current

β2

beta2

Third Vds dependent parameter of
impact ionization current

Vdsatii0

vdsatii0

Nominal drain saturation voltage at
threshold for impact ionization
current

Tii

tii

Temperature dependent parameter
for impact ionization current

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-6

Lii

lii

Channel length dependent parameter

-

0

-

V/m

1e7

-

V-1

0.5

-

V-1

0.1

-

-

0

-

V-1

0

-

at threshold for impact ionization
current
Esatii

esatii

Saturation channel electric field for
impact ionization current

Sii0

sii0

First Vgs dependent parameter for
impact ionization current

Sii1

sii1

Second Vgs dependent parameter for
impact ionization current

Sii2

sii2

Third Vgs dependent parameter for
impact ionization current

Siid

siid

Vds dependent parameter of drain
saturation voltage for impact
ionization current

αgidl

Agidl

GIDL constant

Ω −1

0.0

-

β gidl

Bgidl

GIDL exponential coefficient

V/m

0.0

-

χ

Ngidl

GIDL Vds enhancement coefficient

V

1.2

-

ntun

Ntun

Reverse tunneling non-ideality factor

-

10.0

-

ndiode

Ndio

Diode non-ideality factor

-

1.0

-

nrecf0

Nrecf0

Recombination non-ideality factor at

-

2.0

-

-

10

-

forward bias
nrecr0

Nrecr0

Recombination non-ideality factor at
reversed bias

isbjt

Isbjt

BJT injection saturation current

A/m2

1e-6

-

isdif

Isdif

Body to source/drain injection

A/m2

1e-7

-

Recombination in depletion saturation A/m2

1e-5

-

0.0

-

saturation current
isrec

Isrec

current
istun

Istun

Reverse tunneling saturation current

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

A/m2

B-7

Ln

Ln

Electron/hole diffusion length

m

2e-6

-

Vrec0

Vrec0

Voltage dependent parameter for

V

0

-

V

0

-

-

1

-

m

0.20e-6

-

V

10

-

V/m

0

-

-

0

-

0.0

-

0.0

-

0.0

-

1e15

-

recombination current
Vtun0

Vtun0

Voltage dependent parameter for
tunneling current

Nbjt

Nbjt

Power coefficient of channel length
dependency for bipolar current

Lbjt0

Lbjt0

Reference channel length for bipolar
current

Vabjt

Vabjt

Early voltage for bipolar current

Aely

Aely

Channel length dependency of early
voltage for bipolar current

Ahli

Ahli

High level injection parameter for
bipolar current

Rbody

Rbody

Intrinsic body contact sheet resistance ohm/s
quare

Rbsh

Rbsh

Extrinsic body contact sheet resistance ohm/s
quare

Rsh

Rhalo

rsh

rhalo

Source drain sheet resistance in ohm per

ohm/s

square

quare

Body halo sheet resistance

ohm/
m

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-8

B.4. Gate-to-body tunneling parameters
Symbol
used in
equation
IgMod
Toxqm
Ntox
Toxref
ϕg

Symbol used
in SPICE

Description

Unit

Default

igMod
toxqm
ntox
toxref
ebg

m
m
V

0
Tox
1
2.5e-9
1.2

αgb1

alphaGB1

1/V

.35

βgb1

betaGB1

1/V2

.03

Vgb1

vgb1

V

300

VEVB

vevb

-

0.075

αgb2

alphaGB2

1/V

.43

βgb2

betaGB2

1/V2

.05

Vgb2

vgb2

V

17

VECB

vecb

Gate current model selector
Oxide thickness for Igb calculation
Power term of gate current
Target oxide thickness
Effective bandgap in gate current
calculation
First Vox dependent parameter for gate
current in inversion
Second Vox dependent parameter for
gate current in inversion
Third Vox dependent parameter for
gate current in inversion
Vaux parameter for valence band
electron tunneling
First Vox dependent parameter for gate
current in accumulation
Second Vox dependent parameter for
gate current in accumulation
ThirdVox dependent parameter for gate
current in accumulation
Vaux parameter for conduction band
electron tunneling

-

.026

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-9

B.5. AC and Capacitance Parameters
Symbol

Symbol

used in

used in

equation

SPICE

Xpart

xpart

Charge partitioning rate flag

CGS0

cgso

Non LDD region source-gate overlap

Description

Unit

cgdo

-

0

F/m

calcu-

Non LDD region drain-gate overlap

cgeo

Gate substrate overlap capacitance per

nC-1

lated
F/m

capacitance per channel length
CGEO

Notes (below
the table)

capacitance per channel length
CGD0

Default

calcu-

nC-2

lated
F/m

0.0

-

unit channel length
Cjswg

cjswg

Source/Drain (gate side) sidewall junction
capacitance per unit width (normalized to

F/m2

1e-10

V

.7

-

V

0.5

-

second

1e-12

-

-

-1

-

-

1

-

V

calcu-

nC-3

100nm Tsi)
Pbswg

pbswg

Source/Drain (gate side) sidewall junction
capacitance buit in potential

Mjswg

mjswg

Source/Drain (gate side) sidewall junction
capacitance grading coefficient

tt

tt

Diffusion capacitance transit time
coefficient

Ndif

Ndif

Power coefficient of channel length
dependency for diffusion capacitance

Ldif0

Ldif0

Channel-length dependency coefficient
of diffusion cap.

Vsdfb

vsdfb

Source/drain bottom diffusion
capacitance flatband voltage

Vsdth

vsdth

Source/drain bottom diffusion

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

lated
V

calcu-

nC-4

B-10

capacitance threshold voltage
Csdmin

csdmin

Source/drain bottom diffusion

lated
V

minimum capacitance
Asd

asd

Source/drain bottom diffusion

calcu-

nC-5

lated
-

0.3

-

F/m

0.0

-

F/m

0.0

-

F/m

0.0

-

F/m

0.6

-

F/m

calcu-

nC-6

smoothing parameter
Csdesw

csdesw

Source/drain sidewall fringing
capacitance per unit length

CGSl

cgsl

Light doped source-gate region overlap
capacitance

CGDl

cgdl

Light doped drain-gate region overlap
capacitance

CKAPPA

ckappa

Coefficient for lightly doped region
overlap capacitance fringing field
capacitance

Cf

cf

Gate to source/drain fringing field
capacitance

CLC

clc

Constant term for the short channel model

CLE

cle

Exponential term for the short channel

lated
m

0.1x10-7

-

none

0.0

-

m

lint

-

m

0

-

m

0.0

-

model
DLC

dlc

Length offset fitting parameter for gate
charge

DLCB

dlcb

Length offset fitting parameter for body
charge

DLBG

dlbg

Length offset fitting parameter for
backgate charge

DWC

dwc

Width offset fitting parameter from C-V

m

wint

-

DelVt

delvt

Threshold voltage adjust for C-V

V

0.0

-

Fbody

fbody

Scaling factor for body charge

-

1.0

-

acde

acde

Exponential coefficient for charge

m/V

1.0

-

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-11

thickness in capMod=3 for
accumulation and depletion regions.
moin

moin

Coefficient for the gate-bias dependent

V1/2

15.0

-

surface potential.

B.6. Temperature Parameters
Symbol

Symbol

used in

used in

equation

SPICE

Tnom

tnom

Temperature at which parameters are expected

µte

ute

Mobility temperature exponent

Kt1

kt1

Kt11

kt11

Description

Unit

Defaul

Note

t
ºC

27

-

none

-1.5

-

Temperature coefficient for threshold voltage

V

-0.11

-

Channel length dependence of the temperature

V*m

0.0

none

0.022

-

m/V

4.31e-9

-

(m/V)2 -7.61e-

-

coefficient for threshold voltage
Kt2

kt2

Body-bias coefficient of the Vth temperature
effect

Ua1

ua1

Temperature coefficient for Ua

Ub2

ub1

Temperature coefficient for Ub

18

Uc1

uc1

Temperature coefficient for Uc

1/V

-.056

nT-1

At

at

Temperature coefficient for saturation velocity

m/sec

3.3e4

-

Tcijswg

tcjswg

Temperature coefficient of Cjswg

1/K

0

-

Tpbswg

tpbswg

Temperature coefficient of Pbswg

V/K

0

-

Cth0

cth0

Normalized thermal capacity

(W*sec)

1e-5

-

/ mºC

Prt

prt

Temperature coefficient for Rdsw

Ω-µm

0

-

Rth0

rth0

Normalized thermal resistance

mºC/W

0

-

Ntrecf

Ntrecf

Temperature coefficient for Nrecf

-

0

-

Ntrecr

Ntrecr

Temperature coefficient for Nrecr

-

0

-

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-12

Xbjt

xbjt

Power dependence of jbjt on temperature

-

1

-

Xdif

xdif

Power dependence of jdif on temperature

-

Xbjt

-

Xrec

xrec

Power dependence of jrec on temperature

-

1

-

Xtun

xtun

Power dependence of jtun on temperature

-

0

-

Wth0

Wth0

Minimum width for thermal resistance

m

0

-

calculation

B.7. RF Model Parameters
Symbol
used in
equation
RgateMod

Symbol used
in SPICE

Description

rgateMod

Gate resistance model selector
rgateMod = 0 No gate resistance
rgateMod = 1 Constant gate resistance
rgateMod = 2 Rii model with variable
resistance
rgateMod = 3 Rii model with two
nodes

-

0

XRCRG1

xrcrg1

Parameter for distributed channelresistance effect for intrinsic input
resistance

-

12.0

XRCRG2

xrcrg2

-

1.0

NGCON
XGW

ngcon
xgw

m

1
0.0

XGL

xgl

Parameter to account for the excess
channel diffusion resistance for
intrinsic input resistance
Number of gate contacts
Distance from the gate contact to the
channel edge
Offset of the gate length due to
variations in patterning

m

0.0

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

Unit

Default

B-13

B.8. Model Parameter Notes
nI-1. BSIMSOI supports capmod=2 and 3 only. Capmod=0 and 1 are not supported.
nI-2. In modern SOI technology, source/drain extension or LDD are commonly used.
As a result, the source/drain junction depth (Xj) can be different from the silicon
film thickness (Tsi). By default, if Xj is not given, it is set to Tsi. Xj is not allowed
to be greater than Tsi.
nI-3. BSIMSOI refers substrate to the silicon below buried oxide, not the well region in
BSIM3. It is used to calculate backgate flatband voltage (Vfbb) and parameters
related to source/drain diffusion bottom capacitance (Vsdth, Vsdfb, Csdmin). Positive
nsub means the same type of doping as the body and negative nsub means opposite
type of doping.

nC-1. If cgso is not given then it is calculated using:
if (dlc is given and is greater 0) then,
cgso = p1 = (dlc*cox) - cgs1
if (the previously calculated cgso <0), then
cgso = 0
else cgso = 0.6 * Tsi * cox
nC-2. Cgdo is calculated in a way similar to Csdo
nC-3. If (nsub is positive)
Vsdfb = −

 10 20 ⋅ nsub 
kT
 − 0.3
log
q
 ni ⋅ ni 

Vsdfb = −

 10 20 
kT
 + 0.3
log 
q
 nsub 

else

nC-4. If (nsub is positive)
5.753 × 10 −12 nsub
 n sub 
kT
φ sd = 2
log
 , γ sd =
Cbox
q
 ni 
Vsdth = Vsdfb + φ sd + γ sd φ sd

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-14

else
φ sd = 2

5.753 × 10 −12 − nsub
 n 
kT
log − sub  , γ sd =
Cbox
q
 ni 

Vsdth = Vsdfb − φ sd − γ sd φ sd

nC-5. X sddep =

2ε si φ sd
q nsub ⋅ 10 6

, Csddep =

ε si
X sddep

, Csd min =

Csddep Cbox
Csddep + Cbox

nC-6. If cf is not given then it is calculated using
CF =

2ε ox 
4 × 10 −7 

ln1 +
π
Tox 


nT-1. For mobmod=1 and 2, the unit is m/V2. Default is -5.6E-11. For mobmod=3,
unit is 1/V and default is -0.056.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

B-15

Appendix C: Equation List

Equation List for BSIMSOI Built-In Potential Lowering
Calculation
If SoiMod=0 (default), the model equation is identical to BSIMPD equation.
If SoiMod=1 (unified model for PD&FD) or SoiMod=2 (ideal FD), the following equations (FD
module) are added on top of BSIMPD.

Vbs0 =



qN ch
C BOX
2
⋅ (Ves − VFBb )
⋅  phi −
⋅ TSi + Vnonideal + ∆VDIBL  + η e
C Si + C BOX
2ε Si


ε
ε
ε
= Si , C BOX = OX , C OX = OX
TSi
TBOX
TOX

C Si
C Si + C BOX

where C Si


L 
Leff 


 + 2 exp − Dvbd 1 eff   ⋅ (Vbi − 2Φ B )
∆V DIBL = Dvbd 0  exp − Dvbd 1



l  
2l 




L 
Leff 


 + 2 exp − Dk 2 b eff  
η e = K 1b − K 2b ⋅  exp − Dk 2 b


l  
2l 



phi = phiON −

(

C OX

C OX + C Si − + C BOX
1

)

−1 −1


 Vth ,FD − V gs _ eff − VOFF ,FD
⋅ N OFF ,FDVt ⋅ ln 1 + exp


N OFF ,FDVt



(

 V gsteff .FD V gsteff ,FD + 2 K 1 2Φ B
phiON = 2Φ B + Vt ln 1 +

MoinFD ⋅ K 1 ⋅ Vt 2


)  ,




 Vgs _ eff − Vth ,FD − VOFF ,FD
V gsteff ,FD = N OFF ,FDVt ⋅ ln 1 + exp


N OFF ,FDVt



BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley











C-1

Here Nch is the channel doping concentration. VFBb is the backgate flatband voltage.
Vth,FD is the threshold voltage at Vbs=Vbs0(phi=2Φ B). Vt is thermal voltage. K1 is the body effect
coefficient.

If SoiMod=1, the lower bound of Vbs (SPICE solution) is set to Vbs0. If SoiMod=2, Vbs is pinned
at Vbs0. Notice that there is no body node and body leakage/charge calculation in SoiMod=2.
The zero field body potential that will determine the transistor threshold voltage, Vbsmos, is then
calculated by
Vbsmos = Vbs −

C Si
(Vbs 0 (TOX → ∞ ) − Vbs )2
2qN chTSi

if Vbs ≤ Vbs0 (TOX → ∞ )

= Vbs else

The subsequent clamping of Vbsmos will use the same equation that utilized in BSIMPD.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-2

Equation List for BSIMSOI IV

Body Voltages
Vbsh is equal to the Vbs bounded between (Vbsc, φ s1 ). Vbsh is used in Vth and
Abulk calculation

(Vbs − Vbsc − δ )2 − 4δVbsc  , Vbsc = −5V


T1 = Vbsc + 0.5Vbs − Vbsc − δ +

Vbsh = φ s1 − 0.5 φ s1 − T1 − δ +




(φs1 − T1 − δ )2 + 4δT1  , φ s1 = 1.5V


Vbsh is further limited to 0.95φ s to give Vbseff.
Vbseff = φ s 0 − 0.5φ s 0 − Vbsh − δ +


(φ s 0 − Vbsh − δ ) 2 + 4δVbsh  , φ s 0 = 0.95φ s

Effective Channel Length and Width
dW ' = Wint +

Wl
Ww
Wwl
Wln +
Wwn + Wln
L
W
L W Wwn

dW = dW ' + dWg Vgsteff + dWb
dL = Lint +

(

Φ s − Vbseff − Φ s

)

Ll
L
L
+ Lwwn + Lln wl Lwn
Lln
L
W
L W

Leff = Ldrawn − 2 dL

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-3

Weff = Wdrawn − N bc dWbc − (2 − N bc )dW
Weff ' = Wdrawn − N bc dWbc − (2 − N bc )dW '
Wdiod =
Wdios =

Weff '

+ Pdbcp

N seg
Weff '
N seg

+ Psbcp

Threshold Voltage
Vth = Vtho + K1eff ( sqrtPhisExt − Φ s ) − K 2Vbseff
+ K1eff ( 1 +

N LX
T
− 1) Φ s + ( K 3 + K 3bVbseff ) ' ox
Φs
Leff
Weff + Wo

− DVT 0 w (exp( − DVT 1 w
− DVT 0 (exp( − DVT 1
− (exp( − Dsub

Leff
2lto

Weff' Leff

Leff
2l t

2ltw

) + 2 exp( − DVT 1w

) + 2 exp( − DVT 1

) + 2 exp( − Dsub

Leff
lto

Leff
lt

Weff' Leff
ltw

))(Vbi − Φ s )

))(Vbi − Φ s )

))( Etao + EtabVbseff )Vds

lt = ε si X dep / Cox (1 + DVT 2Vbseff )

(

sqrtPhisExt = φ s − Vbseff + s Vbsh − Vbseff

), s = − 2

1
φ s − φ s0



K
K1eff = K1 1 + ' 1w1 
Weff + K1w 2 

ltw = ε si X dep Cox (1 + DVT 2 wVbseff )
X dep =

2ε si ( Φ s − Vbseff )

Vbi = v t ln(

qN ch

lto = ε si X dep 0 / Cox
X dep 0 =

2ε si Φ s
qN ch

N ch N DS
)
ni 2

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-4

Poly depletion effect

V poly +

qN gate X 2 poly
1
X poly E poly =
2
2ε si

ε ox Eox = ε si E poly = 2qε si N gateV poly
Vgs − VFB − φx = V poly + Vox
a(V gs − VFB − φs − V poly )2 − V poly = 0
a=

ε 2 ox
2qε si N gateT 2 ox

Vgs _eff


qε si N gate T 2 ox 
2ε 2ox (Vgs − VFB − φ s )

= VFB + φ s +

1
+
−
1
ε 2 ox
qε si N gate T 2 ox



Effective Vgst for all region (with Polysilicon Depletion Effect)

Vgsteff

n = 1 + N factor

V _ − Vth 

2nvt ln 1 + exp( gs eff
)
2nvt


=
V
−
V

2Φ s
th − 2 Voff 
1 + 2nCox
exp − gs _ eff

qε si N ch
2 nvt



ε si / X dep
Cox

Leff
Leff 

(Cdsc + Cdscd Vds + Cdscb Vbseff ) exp( − DVT 1
) + 2 exp( − DVT 1
)
2lt
lt  Cit

+
+
Cox
Cox

Effective Bulk Charge Factor


K1eff

Abulk = 1 + 
Vbsh
 2 (φ s + Ketas) −

1 + Keta ⋅Vbsh

Abulk 0 = Abulk (Vgsteff = 0)


A0 Leff


 Leff + 2 Tsi X dep


BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley



Leff


−
A
V
1
gs
gsteff



 Leff + 2 Tsi X dep







2





B0

 + W ' + B 

eff
1 




C-5

Mobility and Saturation Velocity
For Mobmod=1
µ eff =

1 + (U a + Uc Vbseff )(

Vgsteff

µo
+ 2Vth

Tox

) + Ub (

Vgsteff + 2Vth
Tox

)2

For Mobmod=2
µ eff =

µo
V
V
1 + (Ua + Uc Vbseff )( gsteff ) + U b ( gsteff ) 2
Tox
Tox

For Mobmod=3
µ eff =

1 + [U a (

Vgstef + 2Vth
Tox

µ0
+ 2Vth 2
V
) + Ub ( gsteff
) ](1 + Uc Vbseff )
Tox

Drain Saturation Voltage
For Rds>0 or λ≠1:
Vdsat =

− b − b2 − 4ac
2a

a = Abulk 2 Weff ν sat Cox Rds + (

1
− 1) Abulk
λ

2
b = − (Vgsteff + 2ν t )( − 1) + Abulk Esat Leff + 3 Abulk (Vgsteff + 2ν t )Weff ν sat Cox Rds 
λ


c = (Vgsteff + 2ν t ) Esat Leff + 2(Vgsteff + 2ν t ) 2 Weff ν sat Cox Rds
λ = A1Vgsteff + A2

For Rds=0, λ=1:

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-6

Esat Leff (Vgsteff + 2ν t )

Vdsat =

E sat =

Abulk Esat Leff + (Vgsteff + 2ν t )
2ν sat
µeff

Vdseff
Vdseff = Vdsat −

[

1
Vdsat − Vds − δ + (Vdsat − Vds − δ )2 + 4δVdsat
2

]

Drain current expression
Ids, MOSFET =

β = µ eff Cox

Idso

1
N seg

I ds 0 (Vdseff )
V − Vdseff
(1 + ds
)
Rds Idso (Vdseff )
VA
1+
Vdseff

Weff
Leff


Vdseff
βVgsteff 1 − Abulk

2 Vgsteff + 2 vt

=
V
1 + dseff
Esat Leff

(


P V
V A = V Asat + 1 + vag gsteff
E sat Leff


)


 Vdseff




1
1
 (
+
) −1
 V ACLM V ADIBLC

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-7

VACLM =

Abulk Esat Leff + Vgsteff

VADIBLC =

(Vds − Vdseff )

Pclm Abulk Esat litl
(Vgsteff + 2ν t )

θ rout (1 + PDIBLCB Vbseff )

θ rout = PDIBLC1 [exp( − DROUT

Leff
2l t 0

(1 −

Abulk Vdsat
)
Abulk Vdsat + 2ν t

+ 2 exp(− DROUT

Esat Leff + Vdsat + 2 Rdsν sat Cox Weff Vgsteff [1 −
VAsat =

litl =

Leff
lt 0

)] + PDIBLC 2

Abulk Vdsat
]
2(Vgsteff + 2ν t )

2 / λ − 1 + Rdsν sat Cox Weff Abulk
ε si Tox TSi
ε ox

Drain/Source Resistance
Rds = Rdsw

(

1 + PrwgVgsteff + Prwb φ s − Vbseff − φ s

(10 W )
6

)

' Wr
eff

Impact Ionization Current


Vdiff

Iii = α 0 ( I ds, MOSFET + Fbjtii Ic ) exp
2
 β 2 + β 1Vdiff + β 0 Vdiff 
Vdiff = Vds − Vdsatii


 T
 L 
Vdsatii = VgsStep + Vdsatii 0 1 + Tii 
− 1  − ii 

 Tnom
  Leff 

 E satii Leff
VgsStep = 
1+ E L
satii eff



 S ii 0Vgst
1

S ii 2 
+
 1 + S V
 1+ S V
ii1 gsteff
iid ds



BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley





C-8

Gate-Induced-Drain-Leakage (GIDL)
 β
At drain, I dgidl = Wdiod α gidl E s exp  − gidl
 Es

V − Vgs − χ

 , Es = ds
3Tox


 β
At source, I sgidl = Wdiosα gidl E s exp  − gidl
 Es

−V − χ

 , Es = gs
3Tox


If Es is negative, Igidl is set to zero for both drain and source.

Oxide tunneling current
In inversion,
N

(

)

N

(

)

tox
 − B á gb1 − â gb1 Vox Tox
V gbVaux  Toxref 


J gb = A
exp
2



1 − Vox Vgb1
Tox  Toxqm 


 Vox − ö g  

Vaux = VEVB ln 1 + exp
 VEVB  





A=
B=






q3
8πhφ b
8π 2m ox φ b3 2

3hq
φ b = 4.2eV
m ox = 0.3m 0

In accumulation,

tox
 − B á gb2 − â gb2 Vox Tox
V gbVaux  Toxref 


J gb = A
exp
2



1 − Vox Vgb2
Tox  Toxqm 


 V gb − V fb  

Vaux = VECBVt ln 1 + exp −


V
ECB




A=
B=






q3
8πhφ b
8π 2m ox φ b3 2

3hq
φ b = 3.1eV
m ox = 0.4m0

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-9

Body contact current
'

Weff
N seg
Rbp =  Rbody

Leff


'
 
Weff
N seg
 ||  R
halo
 
2
 


, R
bodyext = Rbsh N rb



For 4-T device, I bp = 0
For 5-T device,
I bp =

Vbp
Rbp + Rbodyext

Diode and BJT currents
Bipolar Transport Factor
α bjt

2

 Leff  
= exp −0.5
 
 Ln  


Body-to-Source/drain diffusion

 V
I bs1 = WdiosTsi jsdif  exp bs
 ndioVt


 
 − 1
 


 V
I bd 1 = Wdiod Tsi jsdif  exp  bd
 ndioVt


 
 − 1
 

Recombination/trap-assisted tunneling current in depletion region

 Vbs
I bs 2 = WdiosTsi jsrec  exp 

 0.026n recf



 Vsb
Vrec 0  
 − exp 



0
.
026
n
V
+
V
recr
rec
0
sb

 



 Vbd
I bd 2 = Wdiod Tsi jsrec  exp
 0.026nrecf






Vrec 0  
 − exp Vdb
 0.026n V + V  

recr
rec 0
db  



BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-10

Reversed bias tunneling leakage

 Vsb
Vtun0
I bs4 = WdiosTsi j stun  1 − exp
 0.026ntun Vtun0 + Vsb


 Vdb
Vtun0
I bd 4 = Wdiod Tsi j stun  1 − exp
 0.026ntun Vtun0 + Vdb



 



 



Recombination current in neutral body
  V
I bs 3 = (1 − α bjt )I en exp bs
  n dioVt

 
1
 − 1
  E hlis + 1

  V
I bd 3 = (1 − α bjt )I en exp  bd
  ndioVt

 
1
 − 1
  E hlid + 1

I en =

Weff'
N seg


 1
1 
+ 
Tsi j sbjt  Lbjt 0 
 Leff Ln 


N bjt

  V  
E hlis = Ahli _ eff exp bs  − 1
  n dioVt  
  V  
E hlid = Ahli _ eff exp  bd  − 1
  ndioVt  

 − E g (300 K )

T 

Ahli _ eff = Ahli exp 
X bjt 1 −
n
V
T
dio
t
nom




BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-11

BJT collector current
  V 
 V  1
Ic = α bjt Ien exp  bs  − exp  bd  
 ndio Vt   E2 nd
  ndio Vt 
E2 nd =
Eely

Eely + Eely 2 + 4 Ehli

2
Vbs + Vbd
= 1+
VAbjt + Aely Leff

Ehli = Ehlis + Ehlid
Total body-source/drain current
Ibs = I bs1 + I bs 2 + Ibs 3 + Ibs 4
Ibd = Ibd 1 + Ibd 2 + Ibd 3 + Ibd 4

Total body current
Iii + Idgidl + Isgidl + Igb - Ibs - Ibd - Ibp = 0

Temperature effects
Vth( T ) = Vth( Tnom ) + ( K T 1 + K t1l / Leff + K T 2 Vbseff )(T / Tnom − 1)
µ o( T ) = µ o(Tnom ) (

T µte
)
ν sat ( T ) = ν sat ( Tnom ) − AT (T / Tnom − 1)
Tnom
,

Rdsw ( T ) = Rdsw ( Tnom ) + Prt (

T
− 1)
Tnom

Ua ( T ) = U a ( Tnom ) + U a1 (T / Tnom − 1)
Ub ( T ) = Ub ( Tnom ) + Ub1 (T / Tnom − 1)
Uc (T ) = Uc ( Tnom ) + Uc1 (T / Tnom − 1)

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-12

Rth =

(W

'
eff

Rth0

)

+ Wth0 N seg

, C th = C th0

'
Weff
+ Wth0

N seg

 − E (300 K )

T 

jsbjt = jsbjt 0 exp  g
X bjt 1 −
T
n
V
dio t
nom 


 − E (300 K )

T 

jsdif = jsdif 0 exp  g
X dif 1 −
 Tnom 
 ndioVt
 − Eg (300 K )

T 

jsrec = jsrec 0 exp 
X rec 1 −
 Tnom 
 nrecf 0Vt

 T

jstun = jstun 0 exp  Xtun 
− 1 
 Tnom



 T

nrecf = nrecf 0 1 + nt recf 
− 1  
 Tnom
 


 T

nrecr = nrecr 0 1 + nt recr 
− 1  
 Tnom
 


Eg is the energy gap energy.

Gate-to-channel current (Igc) and gate-to-S/D current (Igs and Igd)

Igc –gate to channel tunneling current

[

]

Igc = Weff Leff ⋅ A ⋅ ToxRatio ⋅ Vgs _ eff ⋅ Vaux ⋅ exp − B ⋅ Toxqm (aigc − bigc ⋅ Voxdepinv )⋅ (1 + cigc ⋅ Voxdepinv )

Note here Igc is the gate to channel current with Vds=0

 V gs _ eff − Vth 0  
 
Vaux = nigc ⋅ Vm ⋅ log1 + exp

nigc
⋅
V
tm




BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-13

ToxRatio

 Toxref
=
T
 oxqm






ntox

⋅

1
2
Toxqm

Igs and Igd –gate tunneling current between the gate and the source/drain diffusion
region

[

]

Igs = Weff Dlcig ⋅ A ⋅ ToxRatioEdg ⋅ Vgs ⋅ V gs′ ⋅ exp − B ⋅ Toxqm ⋅ Poxedge ⋅ (aigsd − bigsd ⋅ V gs′ ) ⋅ (1 + cigsd ⋅ Vgs′ )

[

]

Igd = Weff Dlcig ⋅ A ⋅ ToxRatioEdg ⋅ V gd ⋅ V gd′ ⋅ exp − B ⋅ Toxqm ⋅ Poxedge ⋅ (aigsd − bigsd ⋅ Vgd′ )⋅ (1 + cigsd ⋅ V gd′ )

ToxRatioEdge
Vgs′ =

(V



Toxref

=
T

⋅
Poxedge
 oxqm


⋅

1
(Toxqm ⋅ Poxedge )2

− V fbsd ) + 1.0e − 4 , Vgd′ =
2

gs

ntox

(V

− V fbsd ) + 1.0e − 4 .
2

gd

Partition of Igc
Igc = Igcs + I gcd
Igcs = Igc ⋅

pi gcd⋅ Vds + exp (− pi gcd⋅ Vds ) − 1 + 1.0e − 4

I gcd = Igc ⋅

pi gcd 2 ⋅V ds2 + 2.0e − 4
1 − ( pi gcd⋅ Vds + 1) ⋅ exp (− pi gcd⋅ V ds ) + 1.0e − 4
pi gcd 2 ⋅ Vds2 + 2.0e − 4

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-14

Equation List for BSIMSOI CV

Dimension Dependence
δWeff = DWC +
δLeff = DLC +

Wlc
W
W
+ Wwcwn + Wln wlcWwn
Wln
L
W
L W

Llc
L
L
+ wc
+ Lln wlc Lwn
Lln
Lwn
L
W
L W

Lactive = Ldrawn − 2δLeff
LactiveB = Lactive − DLCB
LactiveBG = LactiveB + 2δLbg
Wactive = Wdrawn − N bc dWbc − (2 − N bc )δWeff
WdiosCV =

Wactive
+ Psbcp
N seg

WdiodCV =

Wactive
+ Pdbcp
N seg

Charge Conservation
QBf = Qacc + Qsub 0 + Qsubs
Qinv = Qinv , s + Qinv , d

(

Qg = − Qinv + QBf

)

Qb = QBf − Qe + Q js + Q jd
Qs = Qinv , s − Q js
Qd = Qinv , d − Q jd
Qg + Qe + Qb + Qs + Qd = 0

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-15

Intrinsic Charges
(1) capMod = 2
Front Gate Body Charge

Accumulation Charge

VFBeff = V fb − 0.5 V fb − Vgb − δ +


(

)

(V fb − Vgb − δ )

2


+δ2


where Vgb = Vgs − Vbseff
V fb = Vth − φ s − K 1eff φ s − Vbseff + delvt

Vgs − Vth 
 delvt  
VgsteffCV = nvt ln 1 + exp 
 ⋅ exp −
 
nv
nv



t
t 

W L

Qacc = − Fbody  active activeB + Agbcp  Cox (VFBeff − Vfb )
N seg



Gate Induced Depletion Charge

Q sub 0


 Wactive LactiveB
K1eff 2


= − Fbody 
+ Agbcp Cox
N seg
2





 − 1 + 1 + 4(Vgs − VFBeff − VgsteffCV − Vbseff ) 
2


K1eff



Drain Induced Depletion Charge
VdsatCV = V gsteffCV / AbulkCV , AbulkCV

VdsCV = VdsatCV −

  CLC  CLE 
= Abulk 0 1 + 
 
  LactiveB  

1
(V
− Vds − δ + (VdsatCV − Vds − δ ) 2 + 4δ VdsatCV )
2 dsatCV

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-16

2
V


W
L
AbulkCV VdsCV
Q subs = Fbody  active activeB + Agbcp C ox ( AbulkCV − 1) dsCV −



(
−
)
N
2
12
V
A
V
2


seg
gsteffCV
bulkCV
dsCV




Back Gate Body Charge

W L
Qe = k b1 Fbody  active activeBG + Aebcp C box (Ves − V fbb − Vbseff


N seg



)

Inversion Charge

(

)

V cveff = V dsat ,CV − 0.5 V 4 + V 42 + 4δ 4V dsat ,CV whereV 4 = V dsat ,CV − V ds − δ 4 ; δ 4 = 0.02
W
L
Qinv = − active active

N seg




2
2
 
AbulkCV V cveff
AbulkCV


+ Agbcp C ox   V gsteffCV −
V cveff  +

A
2


 
12V gsteffCV − bulkCV V cveff

2






 



50/50 Charge Partition
Qinv,s = Qinv ,.d = 0.5Qinv

40/60 Charge Partition

Qinv, s

 Wactive Lactive


+ Agbcp  Cox
N seg


4
2
V
3
=−
VgsteffCV 2 AbulkCV Vcveff + Vgsteff AbulkCV Vcveff
gsteffCV −
2 

3
3
A


2 VgsteffCV − bulkCV Vcvefff 


2

)

Qinv ,d

 Wactive Lactive


+ Agbcp  Cox
N


seg
5
V
3
=−
− VgsteffCV 2 AbulkCV Vcveff + Vgsteff AbulkCV Vcveff
2  gsteffCV

3
A


2 VgsteffCV − bulkCV Vcvefff 


2

−

(

(

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

)

)

(

(

)

2

2

−

(

2
AbulkCV Vcveff
15

(

) 
3

)

3
1
AbulkCV Vcveff 

5

C-17

0/100 Charge Partition
Qinv,s = −

Wactive Lactive + Agbcp
N seg

Qinv ,d = −



(AbulkCVVcveff )2
V gsteffCV AbulkCVVcveff
+
−
Cox 
 2
A
4

24VgsteffCV − bulkCV Vcveff

2



Wactive Lactive + Agbcp
N seg










V
3A
V
(AbulkCV Vcveff )2
Cox  gsteffCV − bulkCV cveff +
 2
A
4

8 VgsteffCV − bulkCV Vcveff

2










(2) capMod = 3 (Charge-Thickness Model)
capMod = 3 only supports zero-bias flat band voltage, which is calculated from biasindependent threshold voltage. This is different from capMod = 2. For the finite thickness
( X DC ) formulation, refer to Chapter 4 of BSIM3v3.2 Users’s Manual.

Front Gate Body Charge

Accumulation Charge

VFBeff = V fb − 0.5 V fb − Vgb − δ +


(

)



(V fb − Vgb − δ ) 2 + δ 2 

where Vgb = Vgs − Vbseff
V fb = Vth − φ s − K1eff φ s − Vbseff

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-18


W L
Qacc = − Fbody  active activeB + Agbcp Coxeff Vgbacc


N seg



(

Vgbacc = 0.5 V0 + V02 + 4δV fb

)

V0 = V fb + Vbseff − Vgs − δ
Coxeff =

Cox C cen
Cox + Ccen

Ccen = ε Si X DC

Gate Induced Depletion Charge

Q sub 0

2

 Wactive LactiveB
K1eff
= − Fbody 
+ Agbcp Coxeff
2
N
seg





 − 1 + 1 + 4(Vgs − VFBeff − VgsteffCV − Vbseff ) 
2


K1eff



Drain Induced Depletion Charge
VdsatCV = (VgsteffCV − Φ δ ) / AbulkCV

(

)

 VgsteffCV VgstefCV + 2 K1eff 2Φ B 
Φ δ = Φ s − 2Φ B = vt ln 1 +

moinK1eff vt2


VdsCV = VdsatCV −

1
(V
− Vds − δ + (VdsatCV − Vds − δ ) 2 + 4δ VdsatCV )
2 dsatCV

2
W

V

AbulkCV VdsCV
L
Q subs = Fbody  active activeB + Agbcp C oxeff ( AbulkCV − 1) dsCV −



12(V gsteffCV − Φ δ − AbulkCV VdsCV 2 )
N seg
 2



BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-19

Back Gate Body Charge

W L
Qe = k b1 Fbody  active activeBG + Aebcp C box (Ves − V fbb − Vbseff

N seg



)

Inversion Charge

(

)

Vcveff = V dsat,CV − 0.5 V 4 + V 42 + 4δ 4V dsat ,CV whereV 4 = V dsat ,CV − V ds − δ 4 ; δ 4 = 0.02

W
L
Qinv = − active active + Agbcp C oxeff


N seg





2
2
AbulkCV V cveff
AbulkCV


  V gsteffCV − Φ δ − 2 Vcveff  +
A



12 V gsteffCV − Φ δ − bulkCV Vcveff

2











50/50 Charge Partition
Qinv,s = Qinv ,.d = 0.5Qinv

40/60 Charge Partition

Qinv, s

 Wactive Lactive


+ Agbcp Coxeff
 N

seg


=− 
(VgsteffCV − Φ δ )3 − 4 (V gsteffCV − Φ δ )2 (AbulkCVVcveff ) + 2 (Vgsteff − Φ δ )(AbulkCVVcveff
2 
3
3
A

 
2V gsteffCV − Φ δ − bulkCV V cvefff 
2



Qinv,d

 Wactive Lactive


+ Agbcp Coxef


N seg



(VgsteffCV − Φ δ )3 − 5 (VgsteffCV − Φ δ )2 (AbulkCVVcveff ) + (V gstefCVf − Φ δ )(AbulkCVVcveff
=−
2 
3
A

 
2V gsteffCV − Φ δ − bulkCV Vcvefff 
2



BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

)

2

)

2

−

−

2
(AbulkCVVcveff
15

1
(AbulkCVVcveff
5

C-20

) 
3



0/100 Charge Partition

Qinv, s = −



(AbulkCVVcveff )2
V gsteffCV − Φ δ AbulkCVV cveff
+
−
C oxeff 
A
2
4

24V gsteffCV − Φ δ − bulkCV V cveff

2



Wactive Lactive + Agbcp
N seg

Qinv , d = −

Wactive Lactive + Agbcp
N seg





 




2
V gsteffCV − Φ δ 3 AbulkCV Vcveff
AbulkCV Vcveff )
(

C oxeff
−
+

A
2
4

8V gsteffCV − Φ δ − bulkCV Vcveff

2



Overlap Capacitance
Source Overlap Charge
Vgs _ overlap =
Qoverlap ,s
WdiosCV

(

) (V

1
 Vgs + δ +
2

gs

+δ

)

2

+ 4δ 



4V
CKAPPA 
= CGS 0 ⋅ Vgs + CGS1Vgs − Vgs _ overlap +
− 1 + 1 + gs _ overlap

2
CKAPPA








Drain Overlap Charge
Vgd _ overlap =

Qoverlap ,d
WdiodCV

1
 Vgd + δ +
2

(

) (Vgd + δ )

2


+ 4δ 



4V _
CKAPPA 
= CGD0 ⋅Vgd + CGD1V gd − Vgd _ overlap +
− 1 + 1 + gd overlap

2
CKAPPA



 




Gate Overlap Charge

(

Qoverlap, g = − Qoverlap,s + Qoverlap, d

)

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-21








Source/Drain Junction Charge
For Vbs < 0.95φ s
Q jswg = Qbsdep + Qbsdif
else
Q jswg = Cbsdep (0.95φ s )(Vbs − 0.95φ s ) + Qbsdif
For Vbd < 0.95φ s
Q jdwg = Qbddep + Qbddif
else
Q jdwg = Cbddep (0.95φ s )(Vbd − 0.95φ s ) + Qbddif

where
1− M jswg 
 
Vbs 



Q bsdep = WdiosCV C jswg − 7
1− 1−

Pbswg 
10 1 − Mj swg  


1− M jswg 



Pbswg
T
1 −  1 − Vbd 

Q bddep = WdiodCV C jswg si− 7

Pbswg 
10 1 − Mj swg  



Tsi

Q bsdif = τ

Weff '

Q bddif = τ

Weff '

N seg

N seg

[

Pbswg

N dif


 1
1 

Tsi J sbjt 1 + Ldif 0  Lbj 0 
+
 Leff

Ln 




N dif


 1
1 



Tsi J sbjt 1 + Ldif 0  Lbj 0
+
 Leff

Ln 





]

C jswg = C jswg 0 1 + t cjswg (T − Tnom )
Pbswg = Pbswg 0 − t pbswg (T − Tnom )

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

  
Vbs

 exp n V
   dio t

 
Vbd

   exp n V
   dio t
 

 
1
 − 1
  E hlis + 1
 
1
 − 1
  E hlid + 1

C-22

Extrinsic Capacitance
Bottom S/D to Substrate Capacitance (per unit area)

C esb

Cbox


2
 Vs / d ,e − Vsdfb 

1


−
−
(
)
C
C
C
box
min 
 box A


sd
 Vsdth − Vsdfb 
=
2
V

−V 
1
(Cbox − Cmin ) s / d ,e sdth 
Cmin +
1 − Asd

 Vsdth − Vsdfb 

Cmin

if

Vs / d ,e < Vsdfb

elseif

Vs / d ,e < Vsdfb + Asd Vsdth − Vsdfb

elseif

Vs / d ,e < Vsdth

(

)

else

Sidewall S/D to Substrate Capacitance (per unit length)

T
C s / d ,esw = C sdesw log1 + si
 Tbox





BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

C-23

Appendix D: Parameter Extraction

D.1. Extraction Strategy
The complicated physics in SOI MOSFETs makes parameter extraction quite involved [20].
It is always preferable to have more measurements so that the parameters extracted can have
more valid physical meaning.

Similar to conventional bulk devices, two basic extraction

strategies can be used: single device extraction, and group device extraction. The group device
extraction is more popular because of several reasons. In analog circuit, channel length and
width scalability is very important. In digital circuit, statistical modeling is often used to predict
the circuit performance due to process variation. Hence channel length scalability is also
important.

Besides, model parameters extracted from group device extraction have better

physical meaning than that from single device extraction. In this work, we shall emphasize on
group device extraction.
Parameter extraction using body contact devices is highly recommended because parameters
related to body effect, impact ionization and leakage currents can be directly extracted [18, 19].
This yields less ambiguity in extracting technology parameters for I-V fitting purposes. In the
followings, we suggest a set of measurement suitable for PD devices.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

D-1

Parameter Extraction

D.2. Suggested I-V Measurement
Measurement set A is used to extract basic MOS I-V parameters. For each body-contacted
device :
(A1) Ids vs. Vgs @ small Vds with different Vbs, Ves=0V.
(A2) Ids vs. Vgs @ Vds=Vdd with different Vbs, Ves=0V.
(A3) Ids vs. Vds with different Vgs and different Vbs, Ves=0V.

Parameters extracted include threshold voltage, body coefficient, delta L and W, series
resistance, mobility, short channel effect, and subthreshold swing. (A2) is used to extract DIBL
parameters at subthreshold. (A3) is used to extract saturation velocity, body charge effect, output
resistance, body contact resistance and self-heating parameters.
Measurement set C is used to extract impact ionization current parameters. For each bodycontacted device :
(C1) Ib vs. Vgs @ different Vds, Vbs=0V, Ves=0V.
(C2) Ib vs. Vds @ different Vgs, Vbs=0V, Ves=0V.

Measurement set D is used to extract MOS temperature dependent parameter. For a long
channel body-contacted device:
(D1) Ids vs. Vgs @ small Vds, Vbs=0V, Ves=0V, repeat with several temperatures.
(D2) Ids vs. Vds @ different Vgs, Vbs=0V, Ves=0V, repeat with several temperatures.

Notice that the self-heating parameters have to be extracted from set A.
Measurement set E is used to extract diode parameters. For a long channel body-contacted
device or gated diode :
(E1) Idiode vs. Vbs @ Vgs=-1V, Ves=0V, repeat with several temperature

Measurement set F is used to extract BJT parameters. For each body-contacted device:
(F1) Ids vs. Ib @ Vgs=-1V, Ves=0V, Vds=1V.

Measurement set G is used to verify the floating body device data. For each floating-body
device :
(G1) Ids vs. Vgs @ small Vds.
(G2) Ids vs. Vgs @ Vds=Vdd.
(G3) Ids vs. Vds @ different Vgs.

BSIMSOI3.1 Manual Copyright © 2003, UC Berkeley

D-2

Appendix E: Model Parameter Binning

Below is the information on parameter binning regarding which model parameters can or
cannot be binned. All those parameters which can be binned follow this implementation:
PL
P
PP
+ W +
Leff Weff Leff × Weff
For example, for the parameter k1: P0 = k1, PL = lk1, PW = wk1, PP = pk1. binUnit is a
bining unit selector. If binUnit = 1, the units of Leff and Weff used in the binning equation
above have the units of microns; therwise in meters.
P = P0 +

For example, for a device with Leff = 0.5µm and Weff = 10µm. If binUnit = 1, the parameter
values for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively.
Therefore, the effective value of vsat for this device is
vsat = 1e5 + 1e4/0.5 + 2e4/10 + 3e4/(0.5*10) = 1.28e5
To get the same effective value of vsat for binUnit = 0, the values of vsat, lvsat, wvsat,
and pvsat would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus,
vsat = 1e5 + 1e-2/0.5e6 + 2e-2/10e-6 + 3e-8/(0.5e-6 * 10e-6) = 1.28e5

Model parameters that have been binned in BSIMPD2.1 are listed as follows:

E.1. DC Parameters
Symbol

Symbol

used in

used in

Description

equation SPICE
Vth0

vth0

Threshold voltage @Vbs=0 for long and wide device

K1

k1

First order body effect coefficient

K1w1

k1w1

First body effect width dependent parameter

K1w2

k1w2

Second body effect width dependent parameter

K2

k2

Second order body effect coefficient

K3

k3

Narrow width coefficient

K3b

k3b

Body effect coefficient of k3

Kb1

Kb1

Backgate body charge coefficient

W0

w0

Narrow width parameter

NLX

nlx

Lateral non-uniform doping parameter

Dvt0

Dvt0

first coefficient of short-channel effect on Vth

Dvt1

dvt1

Second coefficient of short-channel effect on Vth

Dvt2

dvt2

Body-bias coefficient of short-channel effect on Vth

Dvt0w

dvt0w

first coefficient of narrow width effect on Vth for small channel length

Dvt1w

dvt1w

Second coefficient of narrow width effect on Vth for small channel
length

Dvt2w

dvt2w

Body-bias coefficient of narrow width effect on Vth for small channel
length

µ0

u0

Mobility at Temp = Tnom

Ua

ua

First-order mobility degradation coefficient

Ub

ub

Second-order mobility degradation coefficient

Uc

uc

Body-effect of mobility degradation coefficient

vsat

vsat

Saturation velocity at Temp=Tnom

A0

a0

Bulk charge effect coefficient for channel length

Ags

ags

Gate bias coefficient of Abulk

B0

b0

Bulk charge effect coefficient for channel width

B1

b1

Bulk charge effect width offset

Keta

keta

Body-bias coefficient of bulk charge effect

Ketas

Ketas

Surface potential adjustment for bulk charge effect

A1

A1

First non-saturation effect parameter

A2

A2

Second non-saturation effect parameter

Rdsw

rdsw

Parasitic resistance per unit width

Prwb

prwb

Body effect coefficient of Rdsw

Prwg

prwg

Gate bias effect coefficient of Rdsw

Wr

wr

Width offset from Weff for Rds calculation

Nfactor

nfactor

Subthreshold swing factor

Wint

wint

Width offset fitting parameter from I-V without bias

Lint

lint

Length offset fitting parameter from I-V without bias

DWg

dwg

Coefficient of Weff’s gate dependence

DWb

dwb

Coefficient of Weff’s substrate body bias dependence

Voff

voff

Offset voltage in the subthreshold region for large W and L

Eta0

eta0

DIBL coefficient in subthreshold region

Etab

etab

Body-bias coefficient for the subthreshold DIBL effect

Dsub

dsub

DIBL coefficient exponent

Cit

cit

Interface trap capacitance

Cdsc

cdsc

Drain/Source to channel coupling capacitance

Cdscb

cdscb

Body-bias sensitivty of Cdsc

Cdscd

cdscd

Drain-bias sensitivty of Cdsc

Pclm

pclm

Channel length modulation parameter

Pdibl1

pdibl1

First output resistance DIBL effect correction parameter

Pdibl2

pdibl2

Second output resistance DIBL effect correction parameter

Drout

drout

L dependence coefficient of the DIBL correction parameter in Rout

Pvag

pvag

Gate dependence of Early voltage

δ

delta

Effective Vds parameter

α0

alpha0

The first parameter of impact ionization current

Fbjtii

fbjtii

Fraction of bipolar current affecting the impact ionization

β0

beta0

First Vds dependent parameter of impact ionization current

β1

beta1

Second Vds dependent parameter of impact ionization current

β2

beta2

Third Vds dependent parameter of impact ionization current

Vdsatii0

vdsatii0 Nominal drain saturation voltage at threshold for impact
ionization current

Tii

tii

Temperature dependent parameter for impact ionization current

Lii

lii

Channel length dependent parameter at threshold for impact
ionization current

Esatii

esatii

Saturation channel electric field for impact ionization current

Sii0

sii0

First Vgs dependent parameter for impact ionization current

Sii1

sii1

Second Vgs dependent parameter for impact ionization current

Sii2

sii2

Third Vgs dependent parameter for impact ionization current

Siid

siid

Vds dependent parameter of drain saturation voltage for impact
ionization current

αgidl

Agidl

GIDL constant

β gidl

Bgidl

GIDL exponential coefficient

χ

Ngidl

GIDL Vds enhancement coefficient

ntun

Ntun

Reverse tunneling non-ideality factor

ndiode

Ndiode

Diode non-ideality factor

nrecf0

Nrecf0

Recombination non-ideality factor at forward bias

nrecr0

Nrecr0

Recombination non-ideality factor at reversed bias

isbjt

Isbjt

BJT injection saturation current

isdif

Isdif

Body to source/drain injection saturation current

isrec

Isrec

Recombination in depletion saturation current

istun

Istun

Reverse tunneling saturation current

Vrec0

Vrec0

Voltage dependent parameter for recombination current

Vtun0

Vtun0

Voltage dependent parameter for tunneling current

Nbjt

Nbjt

Power coefficient of channel length dependency for bipolar current

Lbjt0

Lbjt0

Reference channel length for bipolar current

Vabjt

Vabjt

Early voltage for bipolar current

Aely

Aely

Channel length dependency of early voltage for bipolar current

Ahli

Ahli

High level injection parameter for bipolar current

E.2. AC and Capacitance Parameters
Symbol

Symbol

used in

used in

Description

equation SPICE
Vsdfb

vsdfb

Source/drain bottom diffusion capacitance flatband voltage

Vsdth

vsdth

Source/drain bottom diffusion capacitance threshold voltage

DelVt

delvt

Threshold voltage adjust for C-V

acde

acde

Exponential coefficient for charge thickness in capMod=3 for
accumulation and depletion regions.

moin

moin

Coefficient for the gate-bias dependent surface potential.



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