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W243HWQ/W244HWQ Series

Preface

Notebook Computer
W243HUQ/W244HUQ
Service Manual
Preface

I

Preface

Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes.

Preface

Brand and product names mentioned in this publication may or may not be copyright s and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Version 1.1
May 2011

Trademarks
Intel and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.

II

Preface

About this Manual
This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the W243HWQ/
W244HWQ series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.

Preface

Appendix A, Part Lists
Appendix B, Schematic Diagrams
Appendix C, Updating the FLASH ROM BIOS

III

Preface

IMPORTANT SAFETY INSTRUCTIONS
Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment:

Preface

1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A (65W) minimum AC/DC Adapter.

CAUTION

This Computer’s Optical Device is a Laser Class 1 Product

FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.

IV

Preface

Instructions for Care and Operation
The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1.

Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer
to any shock or vibration.

2.

Do not place anything heavy
on the computer.

Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not leave it in a place
where foreign matter or moisture may affect the system.

Don’t use or store the computer in a humid environment.

Do not place the computer on
any surface which will block
the vents.

Preface

Do not expose it to excessive
heat or direct sunlight.

3.

Do not place it on an unstable
surface.

Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power
until you properly shut down
all programs.

Do not turn off any peripheral
devices when the computer is
on.

Do not disassemble the computer by yourself.

Perform routine maintenance
on your computer.

V

Preface
4.
5.

Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data.
Take care when using peripheral devices.
Use only approved brands of
peripherals.

Unplug the power cord before
attaching peripheral devices.

Preface

Power Safety
The computer has specific power requirements:


Power Safety
Warning
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.

VI

•
•
•
•
•
•

Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
Before cleaning the computer, make sure it is disconnected from any external power supplies.
Do not plug in the power
cord if you are wet.

Do not use the power cord if
it is broken.

Do not place heavy objects
on the power cord.

Preface

Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.

Battery Guidelines

Preface

The following can also apply to any backup batteries you may have.
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.


Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.

Battery Level
Click the battery icon
in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.

VII

Preface

Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD/DVD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.

System Startup
Remove all packing materials.
Place the computer on a stable surface.
Insert the battery and make sure it is locked in position.
Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
5. Attach the AC/DC adapter to the DC-In jack at the rear of the
computer, then plug the AC power cord into an outlet, and connect
the AC power cord to the AC/DC adapter.
6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 130 degrees); use the other hand (as illustrated in Figure
1) to support the base of the computer (Note: Never lift the computer
by the lid/LCD).
7. Press the power button to turn the computer “on”.

Preface

1.
2.
3.
4.


Shut Down

Figure 1

Note that you should
always shut your
computer down by
choosing Shut Down
from the Start Menu.

Opening the Lid/LCD/
Computer with AC/DC
Adapter Plugged-In

This will help prevent
hard disk or system
problems.

130 ﾟ

VIII

Preface

Contents
Introduction ..............................................1-1
Overview ......................................................................................... 1-1
Specifications ..................................................................................1-2
External Locator - Top View with LCD Panel Open ......................1-4
External Locator - Front & Right Side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) .........................................1-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9
Mainboard Overview - Top (Connectors) .....................................1-10
Mainboard Overview - Bottom (Connectors) ...............................1-11
Overview ......................................................................................... 2-1
Maintenance Tools ..........................................................................2-2
Connections .....................................................................................2-2
Maintenance Precautions .................................................................2-3
Disassembly Steps ...........................................................................2-4
Removing the Battery ......................................................................2-5
Removing the Hard Disk Drive .......................................................2-6
Removing the Optical (CD/DVD) Device ......................................2-8
Removing and installing the ODD Bezel .......................................2-9
Removing the System Memory (RAM) ........................................2-10
Removing and Installing a Processor ............................................2-12
Removing the Wireless LAN Module ...........................................2-15
Removing the 3.75G Module ........................................................2-16
Removing the Keyboard ................................................................2-17
Removing the Top Case module ...................................................2-19

Part Lists ..................................................A-1
Part List Illustration Location ........................................................ A-2

Schematic Diagrams................................. B-1
System Block Diagram ...................................................................B-2
PROCESSOR/ DMI, PEG, FDI ......................................................B-3
PROCESSOR/ CLK, MISC, JTAG ................................................B-4
PROCESSOR/ DDR3 .....................................................................B-5
PROCESSOR/ POWER1 ...............................................................B-6
PROCESSOR/ POWER2 ...............................................................B-7
PROCESSOR/ GND .......................................................................B-8
PROCESSOR/ RESERVED ...........................................................B-9
DDR3 SO-DIMM_0 .....................................................................B-10
DDR3 SO-DIMM_1 .....................................................................B-11
LVDS, Inverter .............................................................................B-12
HDMI, CRT ..................................................................................B-13
PCH/ HDA, JTAG. SATA ............................................................B-14
PCH/ PCI-E, SMBUS, CLK .........................................................B-15
PCH/ DMI, FDI, GPIO ................................................................. B-16
PCH/ LVDS, DDI, CRT ...............................................................B-17
PCH/ PCI, USB, NVRAM ............................................................B-18
PCH/ GPIO, VSS_NCTF, RSVD .................................................B-19
PCH/ POWER1 ............................................................................B-20
PCH/ POWER2 ............................................................................B-21
PCH/ GND ....................................................................................B-22
New Card, Mini PCIE ...................................................................B-23
XI

Preface

Disassembly ...............................................2-1

Top ................................................................................................. A-3
Bottom with 3G ............................................................................. A-4
Bottom without 3G ........................................................................ A-5
SATA BLU-RAY COMBO .......................................................... A-6
SATA DVD SUPER MULTI ........................................................ A-7
LCD ............................................................................................... A-8
HDD ............................................................................................... A-9

Preface

Preface
CCD, 3G, TPM ............................................................................. B-24
Card Reader/LAN JMC261C ....................................................... B-25
INTEL LAN 82579 ...................................................................... B-26
LAN (82579), SATA HDD, ODD ............................................... B-27
USB3.0 NEC, USB CHARGER .................................................. B-28
KBC-ITE IT81518 ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
AUDIO CODEC ALC269 VIA1802 ........................................... B-31
USB, FAN, TP, MULTI CON ..................................................... B-32
5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU .......................................... B-33
VDD3, VDD5 ............................................................................... B-34
Power 1.05VS/0.75V, 1.8VS ....................................................... B-35
Power 1.05VS LAN M ................................................................. B-36
Power 0.85VS ............................................................................... B-37
Power V-Core1 ............................................................................. B-38
Power V-Core2 VGFX ................................................................. B-39
AC IN, CHARGER ...................................................................... B-40
CLICK & FINGER BOARD ....................................................... B-41
AUDIO BOARD/ USB ................................................................ B-42
Power Switch & LID Board ......................................................... B-43
EXTERNAL ODD BOARD ........................................................ B-44
FINGERPRINT BOARD ............................................................. B-45
POWER SEQUENCE .................................................................. B-46
POWER SEQUENCE 1 ............................................................... B-47
...................................................................................................... B-48

Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ....................................................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive ................................................................................................ C-1
Set the computer to boot from the external drive ........................... C-1
XII

Use the flash tools to update the BIOS ...........................................C-2
Restart the computer (booting from the HDD) ...............................C-2

Introduction

Chapter 1: Introduction
Overview
This manual covers the information you need to serv ice or upgrade the W243HWQ/W244HWQ series notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the
computer.
Operating systems (e.g. Window 7, etc.) have their own manuals as do applic ation softwares (e.g. word processing and
database programs). If you have questions about those programs, you should consult those manuals.

1.Introduction

The W243HWQ/W244HWQ series notebook is designed to be upgradeable. SeeDisassembly on page 2 - 1 for a detailed
description of the upgrade procedures for each specific component. Please take note of the warning and safety information indicated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.

Overview 1 - 1

Introduction

Specifications

Latest Specification Information
The specifications listed here are correct at the
time of sending them to the press. Certain items
(particularly processor types/speeds) may be
changed, delayed or updated due to the manufacturer's release schedule. Check with your
service center for more details.

Processor Options

Storage

Intel® Core™ i7 Processor
i7-2620M (2.70GHz)
4MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W
Intel® Core™ i5 Processor
i5-2540M (2.60GHz), i5-2520M (2.50GHz), 
i5-2410M (2.30GHz)
3MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W
Intel® Core™ i3 Processor
i3-2310M (2.10GHz)
3MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W

(Factory Option) One Changeable 12.7mm(h) Optical
Device Type Drive (Super Multi Drive Module or Blu-Ray
Combo Drive Module)
One Changeable 2.5" 9.5mm (h) SATA HDD

1.Introduction

Core Logic
Intel® HM65 Chipset

LCD


CPU
The CPU is not a user serviceable part. Accessing the CPU in any way may violate your
warranty.

High Definition Audio Compliant Interface
2 * Built-In Speakers
Built-In Microphone

Security
Security (Kensington® Type) Lock Slot
BIOS Password
(Factory Option) TPM v1.2
(Factory Option) Fingerprint Reader

14" (35.56cm), 3.6mm, HD TFT LCD
OR
14" (35.56cm), 5.2mm, HD TFT LCD

Keyboard

Memory

Pointing Device

Two 204 Pin SO-DIMM Sockets Supporting DDR3 1333MHz
Memory
Memory Expandable up to 8GB

Built-in Touchpad

(The real memory operating frequency depends on the FSB
of the processor.)

Three USB 2.0 Ports
One HDMI-Out Port
One Headphone-Out Jack
One Microphone-In Jack
One RJ-45 LAN Jack
One DC-in Jack
One External Monitor Port

Video Adapter
Intel® HD Graphics 3000
Shared Memory Architecture of up to 1748MB
MS DirectX® 10 compatible

BIOS
One 32Mb SPI Flash ROM
AMI BIOS

1 - 2 Specifications

Audio

“WinKey” keyboard (with embedded numeric keypad)

Interface

Introduction
Communication

Environmental Spec

Intel® 82579V GbE Network Adapter
(Factory Option) 1.3M Pixel USB PC Camera Module
(Factory Option) 3.75G/HSPA Mini-Card Module
WLAN/ Bluetooth Half Mini-Card Modules:
(Factory Option) Intel® WiFi Link 1000 (802.11b/g/n) Wireless LAN
(Factory Option) Intel® Centrino® Wireless-N 1030 Wireless LAN (802.11b/g/n) + Bluetooth 3.0
(Factory Option) Third-Party Wireless LAN (802.11b/g/n)
(Factory Option) Third-Party Wireless LAN (802.11b/g/n) +
Bluetooth 3.0

Temperature
Operating: 5°C - 35°C
Non-Operating: -20°C - 60°C
Relative Humidity
Operating: 20% - 80%
Non-Operating: 10% - 90%

Mini Card Slots

Dimensions & Weight
340mm (w) * 238mm (d) * 33.50 - 25.05mm (h)
2.164 kg (with 48.84WH Battery and ODD)
340mm (w) * 238mm (d) * 34.7 - 26.25mm (h)
2.183 kg (with 48.84WH Battery and ODD)

1.Introduction

Slot 1 for WLAN Module or Combo WLAN and Bluetooth
Module
(Factory Option) Slot 2 for 3.75G/HSPA Module

Card Reader
Embedded Multi-In-1 Card Reader
MMC (MultiMedia Card) / RS MMC
SD (Secure Digital) / Mini SD / SDHC/ SDXC
MS (Memory Stick) / MS Pro / MS Duo

Power
6 Cell Smart Lithium-Ion Battery Pack, 48.84WH
(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH
Full Range AC/DC Adapter
AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)

Specifications 1 - 3

Introduction
Figure 1

External Locator - Top View with LCD Panel Open

1.Introduction

Top View
1

1. PC Camera
(Optional)
2. LCD
3. Power Button
4. Hot-Key Buttons
5. LED Status
Indicators
6. Keyboard
7. Built-In
Microphone
8. Touchpad &
Buttons
9. Fingerprint
Reader (Optional)

2

4

5

6

7
8
9

1 - 4 External Locator - Top View with LCD Panel Open

3

Introduction

External Locator - Front & Right Side Views

Figure 2
Front View
1. LED Power
Indicators

FRONT VIEW

1

Right Side View
RIGHT SIDE VIEW

1

2

3

4
5

6

1. Microphone-In
Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
4. Optical Device
Drive Bay
5. Emergency Eject
Hole
6. Security Lock
Slot

External Locator - Front & Right Side Views 1 - 5

1.Introduction

Figure 3

Introduction

External Locator - Left Side & Rear View
Figure 4

1.Introduction

Left Side View
1. DC-In Jack
2. External Monitor
Port
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. USB 2.0 Port
6. Vent
7. USB 2.0 Port
8. Multi-in-1 Card
Reader

/

LEFT SIDE VIEW

2

3

4

5

7
6

1

Figure 5

REAR VIEW

Rear View
1. Battery
1

1 - 6 External Locator - Left Side & Rear View

8

Introduction

External Locator - Bottom View
Figure 6
Bottom View

1

3

3

2
6
3


4
5

3

3

Overheating

5

To prevent your computer from overheating, make sure nothing blocks any vent
while the computer is
in use.

External Locator - Bottom View 1 - 7

1.Introduction

1. Battery
2. Component Bay
Cover
3. Vent
4. Hard Disk Bay
Cover
5. Speakers
6. USIM Card Cover

Introduction
Figure 7

Mainboard Overview - Top (Key Parts)

Mainboard Top
Key Parts

1.Introduction

1. JMICRO JMC261
2. ITE IT8518E
3. AZALIA CODEC
REALTEK
ALC269

1

2

3

1 - 8 Mainboard Overview - Top (Key Parts)

Introduction

Mainboard Overview - Bottom (Key Parts)

Figure 8
Mainboard Bottom
Key Parts

2
1

3

6

5

4

Mainboard Overview - Bottom (Key Parts) 1 - 9

1.Introduction

1. Memory Slots
DDR3 SO-DIMM
2. CPU Socket (no
CPU installed)
3. Platform Controller
Hub
4. Mini-Card
Connector (WLAN
Module)
5. SIMLOCK
6. 3.75G/HSPA
Module Connector

Introduction
Figure 9

Mainboard Overview - Top (Connectors)

1.Introduction

Mainboard Top
Connectors
1. HDMI-Out Port
2. USB Port 2.0
3. Speaker Cable
Connector
4. Microphone
Cable Connector
5. Audio Board
Connector
6. TouchPad Cable
Connector
7. Keyboard Cable
Connector
8. Switch Board
Cable Connector

8

1

2

7
4

6

2

5
3

1 - 10 Mainboard Overview - Top (Connectors)

Introduction

Mainboard Overview - Bottom (Connectors)

Figure 10
9

11

8

10

1
7

1. Battery
Connector
2. ODD Connector
3. HDD Connector
4. CMOS Battery
Connector
5. CPU Fan Cable
Connector
6. Multi-in-1 Card
Reader
7. RJ-45 LAN Jack
8. External Monitor
Port
9. DC-In Jack
10. CCD Cable
Connector
11. LCD Cable
Connector

5

3

6

Mainboard Overview - Bottom (Connectors) 1 - 11

1.Introduction

4

2

Mainboard Bottom
Connectors

1.Introduction

Introduction

1 - 12

Disassembly

Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the W243HWQ/W244HWQ series notebook’s parts
and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.

To make the disassembly process easier each section may have a box in the page margin. In formation contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a 
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also.


Information

A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar.


Warning

Overview 2 - 1

2.Disassembly

Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.

Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).

Maintenance Tools
The following tools are recommended when working on the notebook PC:

2.Disassembly

•
•
•
•
•
•

M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap

Connections
Connections within the computer are one of four types:

2 - 2 Overview

Locking collar sockets for ribbon connectors

To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replacing the connection, make sure th e connector is oriented in the
same way. The pin1 side is usually not indicated.

Pressure sockets for multi-wire connectors

To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.

Pressure sockets for ribbon connectors

To release these connectors, use a small pair of needle-nose pliers to gently lift the connector awa y from its socket. When re placing the connection, make sure the connector is orie nted in
the same way. The pin1 side is usually not indicated.

Board-to-board or multi-pin sockets

To separate the boards, gently rock them from side to side as
you pull them apart. If the connec tion is very tight, use a small
flat-head screwdriver - use just enough force to start.

Disassembly

Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions:

•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies.
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire.

6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.

Power Safety
Warning
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.

Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.

Overview 2 - 3

2.Disassembly

1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
components could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight.
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor
the position of magnetized tools (i.e. screwdrivers).
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly
damaged.
5. Be careful with power. Avoid accidental shocks, discharges or explosions.



Disassembly

Disassembly Steps
The following table lists the disassembly steps, and on which pageto find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.

To remove the Battery:
1. Remove the battery

To remove the 3.75G Module:
page 2 - 5

1. Remove the battery
2. Remove the 3.75G module

page 2 - 5
page 2 - 6

To remove the Keyboard:

page 2 - 5
page 2 - 8

To remove the Top Case module:

To remove the HDD:

2.Disassembly

1. Remove the battery
2. Remove the HDD

To remove the Optical Device:
1. Remove the battery
2. Remove the Optical device
3. Removing and installing the 
ODD Bezel

page 2 - 9

To remove the System Memory:
1. Remove the battery
2. Remove the system memory

page 2 - 5
page 2 - 10

To remove and install a Processor:
1. Remove the battery
2. Remove the processor
3. Install the processor

page 2 - 5
page 2 - 12
page 2 - 14

To remove the Wireless LAN Module:
1. Remove the battery
2. Remove the WLAN module

2 - 4 Disassembly Steps

page 2 - 5
page 2 - 15

1. Remove the battery
2. Remove the keyboard
1.
2.
3.
4.
5.
6.
7.
8.

Remove the battery
Remove the HDD
Remove the system memory
Remove the processor
Remove the WLAN module
Remove the 3.75G module
Remove the keyboard
Remove the Top Case module

page 2 - 5
page 2 - 15

page 2 - 5
page 2 - 17
page 2 - 5
page 2 - 6
page 2 - 9
page 2 - 12
page 2 - 15
page 2 - 15
page 2 - 17
page 2 - 19

Disassembly

Removing the Battery
1.
2.
3.
4.

Figure 1
Battery Removal

Turn the computer off, and turn it over.
Slide the latch 1 in the direction of the arrow (Figure 1a).
Slide the latch 2 in the direction of the arrow, and hold it in place (Figure 1a).
Slide the battery 63 in the direction of the arrow 4 (Figure 1b).

a. Slide the latch and hold it
in place.
b. Slide the battery in the direction of the arrow.

b.

a.
2

3
1

2.Disassembly

4


3. Battery

Removing the Battery 2 - 5

Disassembly

Removing the Hard Disk Drive
Figure 2
HDD Assembly
Removal

2.Disassembly

a. Locate the HDD bay cover
and remove the screws.

The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
(h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Chapter 4 of the User’s Manual) when setting up a new hard disk.

Hard Disk Upgrade Process
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 (Figure 2a).



a.

HDD System Warning
New HDD’s are blank. Before you
begin make sure:
You have backed up any data
you want to keep from your old
HDD.

1


• 2 crews
S

2 - 6 Removing the Hard Disk Drive

2

You have all the CD-ROMs and
FDDs required to install your operating system and programs.
If you have access to the internet,
download the latest application
and hardware driver updates for
the operating system you plan to
install. Copy these to a removable medium.

Disassembly
3.
4.
5.
6.
7.

Remove the hard disk bay cover 63 (Figure 3b).
Grip the tab and slide the hard disk in the direction of arrow 4 (Figure 3c).
Lift the hard disk out of the bay 5 (Figure 3d).
Remove the screws 6 - 9 and the mylar cover 10 from the hard disk 11 (Figure 3e).
Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
d.

b.

5

Figure 3
HDD Assembly
Removal (cont’d.)
b. Remove the HDD bay
cover.
c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
e. Remove the screws and
mylar cover.

2.Disassembly

3

c.

e.

9
6

8
4

10

7

11


3. HDD Bay Cover
10. Mylar Cover
11. HDD

• 4 crews
S

Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4
Optical Device
Removal
a. Remove the screws.
b. Remove the cover.
c. Remove the screw and
push the optical device
out off the computer at
point 8 .

Removing the Optical (CD/DVD) Device
1.
2.
3.
4.
5.

Turn off the computer, and remove the battery (page 2 - 5).
Locate the RAM & CPU bay cover 1 , and remove screws 2 - 5 (Figure 4a).
Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
Carefully disconnect the fan cable 6 , and remove the cover 1 (Figure 4b).
Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 (Figure 4c).
6. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
screw holes should line up).
7. Restart the computer to allow it to automatically detect the new device.

2.Disassembly

a.

c.

2
3
1
4

7
5

b.


1. Component Bay Cover
9. Optical Device

• 5 crews
S

2 - 8 Removing the Optical (CD/DVD) Device

1

6

9

8

Disassembly

Removing and installing the ODD Bezel

Figure 5

1. Turn off the computer, remove the battery and remove the ODD(page 2 - 5).
2. Carefully unsnap the ODD Bezel 1 from ODD in the direction of the arrow 2 .
a.

2

ODD Bezel
a. Unsnap the ODD Bezel
in the direction of the arrow 2 .
b. Snap the bezel onto the
ODD at points 3 and
4 .

1

2.Disassembly

3. Snap the bezel onto the ODD at points 3 and 4 .
b.

4


3

1. ODD Bezel

Removing and installing the ODD Bezel 2 - 9

Disassembly
Figure 6
RAM Module
Removal

2.Disassembly

a. Locate the memory
socket.
b. Pull the release
latches.
c. Remove the module.

Removing the System Memory (RAM)
The computer has two memory socketsfor 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
DDR3 1333MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1GB, 2GB and
4GB and DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your
computer.

Memory Upgrade Process
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
2. The RAM modules will be visible at point 1 on the main board (Figure 6a).
3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the
arrows (Figure 6b).



b.

a.

Contact Warning
Be careful not to touch
the metal pins on the
module’s connecting
edge. Even the cleanest hands have oils
which can attract particles, and degrade the
module’s
performance.

1

c.

2
4

3


4. RAM Module

4.
5.
6.
7.

The RAM module 4 will pop-up (Figure 6c), and you can then remove it.
Pull the latches to release the second module if necessary.
Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
will go. DO NOT FORCE the module; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.

2 - 10 Removing the System Memory (RAM)

Disassembly
9. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay
cover).
Note that there are four 5 - 8 cover pins which need to be aligned with slots in the case, to insure a proper cover
fit, before screwing down the bay cover (Figure 7d).
d.

Figure 7
RAM Module
Removal (cont’d.)
d. Properly re-insert
bay cover pins.

5

the

6

7

10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.

Removing the System Memory (RAM) 2 - 11

2.Disassembly

8

Disassembly
Figure 8
Processor Removal
a. The CPU heat sink will
be visible at point A .
Remove the screws from
the CPU heatsink.
b. Grip the heat sink tab
and carefully lift the heat
sink up and off the computer.

Removing and Installing a Processor
Processor Removal Procedure
1.
2.
3.
4.

Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
The CPU heat sink will be visible at point A (Figure 8a).
Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure 8a).
Grip the heat sink tab and carefully lift the heat sink 4 up and off the computer (Figure 8b).
a.

2.Disassembly

3
A

1

2

b.


4. Heat Sink

• 3 crews
S

2 - 12 Removing and Installing a Processor

4

Disassembly
5.
6.
7.
8.

Turn the release latch 5 towards the unlock symbol
to release the CPU (Figure 9d).
Carefully (it may be hot) lift the CPU 6 up and out of the socket (Figure 9e).
Reverse the process to install a new CPU.
When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).

Figure 9
Processor Removal
(cont’d)
c. Turn the release latch to
unlock the CPU.
d. Lift the CPU out of the
socket.

c.

5

5

2.Disassembly

Unlock

Lock

d.


Caution

6

The heat sink, and CPU area in
general, contains parts which are
subject to high temperatures. Allow
the area time to cool before removing these parts.


6. CPU

Removing and Installing a Processor 2 - 13

Disassembly
Figure 10
Processor
Installation
a. Insert the CPU.
b. Turn the release latch towards the lock symbol.
c. Remove the sticker from
the heat sink and insert
the heat sink.
d. Tighten the screws.

Processor Installation Procedure
1. Insert the CPU A (Figure 10a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE
IT!), and turn the release latch B towards the lock symbol
(Figure 10b).
2. Remove the sticker C (Figure 10c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 10d.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 10d).
5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws (page 2 - 9).
c.

a.
A

2.Disassembly

C

d.

b.

D
3
B
1


A. CPU
D. Heat Sink

• 3 crews
S

2 - 14 Removing and Installing a Processor

2

Note:
Tighten th e scre ws
in the order as indicated on the label.

Disassembly

Removing the Wireless LAN Module
1.
2.
3.
4.

Figure 11

Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The Wireless LAN module will be visible at point 1 on the mainboard (Figure 11a).
Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 11b).
The Wireless LAN module 4 (Figure 11c) will pop-up, and you can remove it from the computer (Figure 11d).

a.

c.

Wireless LAN
Module Removal
a. Locate the WLAN.
b. Disconnect the cable
and remove the screw.
c. The WLAN module will
pop up.
d. Remove the Wireless
LAN module.

4

1

b.

d.
3
2
4


4.Wireless LAN Module

• 1 crew
S

Removing the Wireless LAN Module 2 - 15

2.Disassembly

Note: Make sure you
reconnect the antenna
cable to the “1 + 2”
socket (Figure 11b).

Disassembly
Figure 12
3.75G Module
Removal

1.
2.
3.
4.
5.

Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
The 3.75G module will be visible at point 1 on the mainboard.
Carefully disconnect the cable 2 , then remove the screw 3 from the module socket.
The 3.75G module 4 will pop-up.
Lift the 3.75G module (Figure 12d) up and off the computer.
a.

2.Disassembly

a. Remove the cover.
b. Disconnect the cable
and remove the screw.
c. The 3.75G module will
pop up.
d. Lift the 3.75G module
out.

Removing the 3.75G Module

c.

4

1 1
d.

b.



2

4. 3.75G Module.

• 1 crew
S

2 - 16

3

4

Disassembly

Removing the Keyboard

Figure 13

1. Turn off the computer, and remove the battery (page 2 - 5),and the component bay cover (page 2 - 8)
2. Remove screws 1 - 2 from the bottom of the computer and use the Eject Pin Tool to carefully push out the keyboard at point 3
3. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable.

a.

c.

Keyboard Removal
a. Remove screws from the
bottom of the computer
and use the Eject Pin
Tool to push out the keyboard at point 3 .
b.Carefully lift the keyboard
up.

3

2.Disassembly

2

1

b.

4


4. Keyboard

• 2 crews
S

Removing the Keyboard 2 - 17

Disassembly
Figure 14
Keyboard Removal
(cont’d)

4. Disconnect the keyboard ribbon cable 5 from the locking collar socket 6 (Figure 13c)
5. Carefully lift up the keyboard 4 (Figure 13d) off the computer.
c.

d.

c. Carefully lift the keyboard up and disconnect
the keyboard ribbon cable from the locking collar socket.
d. Remove the keyboard.

5

2.Disassembly

6



4

Re-Inserting the
Keyboard
When re-inserting the
keyboard firstly align the
four keyboard tabs at
the bottom (Figure 14d)
at the bottom of the keyboard with the slots in
the case.


6. Keyboard

2 - 18 Removing the Keyboard

Keyboard Tabs

Disassembly

Removing the Top Case module

Figure 15

1. Turn off the computer, and remove the battery (page 2 - 5), remove the HHD (page 2 - 6), remove the ODD (page
2 - 8), remove the Memory (page 2 - 10) , remove Processor (page 2 - 12), remove the WLAN (page 2 - 15) and
the remove Keyboard (page 2 - 17).
2. Remove screws 1 - 2 and carefully disconnect the cables 3 - 5 from the Top Case module 6 ..
a.
3
2

1
5

6

Top Case module
Removal
a. Remove screws and the
cables.
b. Remove screws from the
bottom of the computer
and use the Eject Pin
Tool to push out the keyboard at point 27 .

4

2.Disassembly

3. Remove screws 7 - 26 from the bottom of the computer and use the Eject Pin Tool to carefully push out the hinge
cover at point 27 .
b.
8
7

16

27
12

11

9

14
13

10

15
17

26
18

24

19

25


6. Top Case module

23

22

21

• 23 crews
S
20

Removing the Top Case module 2 - 19

Disassembly
Figure 16
Top Case module
Removal (cont’d)

4. Carefully lift up the hinge cover 28 off the computer.
c.
28

c. Remove the hinge cover.
d. Remove the top case
module.

28

2.Disassembly

5. Carefully unsnap the top case 29 from computer at point 30 .

d.

29
30


28. Hinge cover
29. TopCase module

2 - 20 Removing the Top Case module

Appendix A:Part Lists
This appendix breaks down the W243HWQ/W244HWQ series notebook’s construction into a series of illustrations. The
component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common ( especially screws). However, the part lists DO NOT in dicate the
total number of duplicated parts used.

A.Part Lists

Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.

A - 1

Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1

A.Part Lists

Part List Illustration
Location

A - 2

Part

W243HWQ/W244HWQ

Top

page A - 3

Bottom (w/ 3G)

page A - 4

Bottom (w/o 3G)

page A - 5

SATA BLU-RAY
COMBO

page A - 6

SATA DVD SUPER
MULTI

page A - 7

LCD

page A - 8A

HDD

page A - 9

Top

Top

黑色

(灰色)

Top A - 3

A.Part Lists

Figure A - 1

Bottom with 3G

A.Part Lists

Figure A - 2
Bottom with SIM
(W240HUQ/
W241HUQ/
W245HUQ Series)

A - 4 Bottom with 3G

Bottom without 3G

Figure A - 3

Bottom without 3G A - 5

A.Part Lists

Bottom without 3G

A.Part Lists

SATA BLU-RAY COMBO

Figure 4
SATA BLU-RAY
COMBO

A - 6 SATA BLU-RAY COMBO

SATA DVD SUPER MULTI

SATA DVD SUPER MULTI A - 7

A.Part Lists

Figure 5
SATA DVD SUPER
MULTI

LCD

A.Part Lists

Figure A - 6
LCD

銘板

A - 8

HDD

Figure A - 7

無鉛
(無鉛)

HDD A - 9

A.Part Lists

HDD

A - 10

A.Part Lists

Schematic Diagrams

Appendix B: Schematic Diagrams
This appendix has circ uit diagrams of the W243HWQ/W244HWQ notebook’s PCB’s. The fo llowing table indicates
where to find the appropriate schematic diagram.
Diagram - Page

Diagram - Page

Diagram - Page

PCH/ GPIO, VSS_NCTF, RSVD - Page B - 19

Power 1.05VS LAN M - Page B - 36

PROCESSOR/ DMI, PEG, FDI - Page B - 3

PCH/ POWER1 - Page B - 20

Power 0.85VS - Page B - 37

PROCESSOR/ CLK, MISC, JTAG - Page B - 4

PCH/ POWER2 - Page B - 21

Power V-Core1 - Page B - 38

PROCESSOR/ DDR3 - Page B - 5

PCH/ GND - Page B - 22

Power V-Core2 VGFX - Page B - 39

PROCESSOR/ POWER1 - Page B - 6

New Card, Mini PCIE - Page B - 23

AC IN, CHARGER - Page B - 40

PROCESSOR/ POWER2 - Page B - 7

CCD, 3G, TPM - Page B - 24

CLICK & FINGER BOARD - Page B - 41

PROCESSOR/ GND - Page B - 8

Card Reader/LAN JMC261C - Page B - 25

AUDIO BOARD/ USB - Page B - 42

PROCESSOR/ RESERVED - Page B - 9

INTEL LAN 82579 - Page B - 26

Power Switch & LID Board - Page B - 43

DDR3 SO-DIMM_0 - Page B - 10

LAN (82579), SATA HDD, ODD - Page B - 27

EXTERNAL ODD BOARD - Page B - 44

DDR3 SO-DIMM_1 - Page B - 11

USB3.0 NEC, USB CHARGER - Page B - 28

FINGERPRINT BOARD - Page B - 45

LVDS, Inverter - Page B - 12

KBC-ITE IT81518 - Page B - 29

POWER SEQUENCE - Page B - 46

HDMI, CRT - Page B - 13

LED, MDC, BT - Page B - 30

POWER SEQUENCE 1 - Page B - 47

PCH/ HDA, JTAG. SATA - Page B - 14

AUDIO CODEC ALC269 VIA1802 - Page B - 31

PCH/ PCI-E, SMBUS, CLK - Page B - 15

USB, FAN, TP, MULTI CON - Page B - 32

PCH/ DMI, FDI, GPIO - Page B - 16

5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU - Page B - 33

PCH/ LVDS, DDI, CRT - Page B - 17

VDD3, VDD5 - Page B - 34

PCH/ PCI, USB, NVRAM - Page B - 18

Power 1.05VS/0.75V, 1.8VS - Page B - 35

Table B - 1
SCHEMATIC
DIAGRAMS


Version Note
The schematic diagrams in this chapter
are based upon version 6-7P-W24V6-002.
If your mainboard (or
other boards) are a later version, please
check with the Service
Center for updated diagrams (if required).

B - 1

B.Schematic Diagrams

System Block Diagram - Page B - 2

Schematic Diagrams

System Block Diagram
CLICK & FINGER BOARD
6 -7 1- W2 40 2-D 01

Huron River System Block Diagram

AUDIO BOARD

VDD3,VDD5

U SB +E AR PH ONE +E XT .M IC
6 -7 1- C4 50 8-D 03

5V,3V,5VS,3VS,1.5VS,
1.5VS_CPU

POWER SWITCH BOARD

Sandy Bridge

P OW ER S WI TCH +H OT KE Y X 3
6 -7 1- E5 1Q S-D 02

37.5*37.5 mm

EXTERNAL ODD BOARD

PROCESSOR

B.Schematic Diagrams

E XT . OD D
6 -7 1- E5 1Q N-D 01

rPGA989/988

Memory Termination
1.5V,0.75VS(VTT_MEM)
1.8VS

800/1067 MHz
DDR3 / 1.5V
DDRIII
SO-DIMM0
SHEET 10

SYSTEM SMBUS
0 .1 "~1 3

DDRIII
SO-DIMM1
SHEET 11

FDI
HD MI

Sheet 1 of 46
System Block
Diagram

CLICK BOARD

0. 5" ~6 .5 "

<= 8"

VCORE
AU DI O BO AR D

CR T S WI TC H

INTERNAL
GRAPHICS

S yn ap ti c
810602-1703

L CD C ON NE CT OR ,

0.85VS

DMI*4

<1 5"

CR T CO NN EC TO R

T OU CH P AD

1.05V_LAN_M,
1.05VS_VTT

<8 "

INTERNAL
GRAPHICS

L VD S S WI TC H

VGFX_CORE

CougarPoint
Platform
Controller
Hub (PCH)

MIC
IN

HP
OUT

INT SPK R

32.768 KHz

EC
IT E 85 18 E

S PI

TP M

Az al ia C od ec
REALTEK ALC269

25x25x0.6 mm
989 Balls FCBGA

128pins LQFP
14 *14*1 .6 mm

33 MHz

INT SPK L

INT MIC

LPC
0. 5" ~1 1"

B IO S
S PI

AZALIA LINK 24 MHz

EC SMBUS
PCIE
I NT . K/ B

TH ER MA L
SE NS OR
W 83 L7 71 AW G

S MA RT
FA N

SM AR T
B AT TE RY

I nt el L AN

USB2.0
480 Mbps

8 25 79

S AT A OD D

Fi ng er Pr in t
( US B3 )
12 MHz

B - 2 System Block Diagram

USB P OR T
(U SB 0)

U SB P OR T
(U SB 1)
US B3 .0
(Optional)

US B PO RT
( US B9 )
A UD IO
B OA RD

Mi ni P CI E
S OC KE T
3 G CA RD
( US B4 )

Mi ni P CI E
S OC KE T
WL AN
( US B2 )

NEC
uPD720200
USB3.0 IC

JMICRO
JMC261 C
CARD READER

(Optional)

1" ~1 6"

SA TA H DD

<1 2"

32.768KHz

< 12 "

SATA I/II 3.0Gb/s

100 MHz

C CD
(U SB 5)

7 IN 1
SO CK ET
RJ-45

25
M Hz

Schematic Diagrams

PROCESSOR/ DMI, PEG, FDI
Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
1. 0 5 V S _ V T T
U3 4 A

15
15
15
15

DM
DM
DM
DM

G 21
E2 2
F21
D 21
G 22
D 22
F20
C 21

I_ RXP 0
I_ RXP 1
I_ RXP 2
I_ RXP 3

15
15
15
15
15
15
15
15

F DI_ T X N0
F DI_ T X N1
F DI_ T X N2
F DI_ T X N3
F DI_ T X N4
F DI_ T X N5
F DI_ T X N6
F DI_ T X N7

15
15
15
15
15
15
15
15

F DI_ T X P 0
F DI_ T X P 1
F DI_ T X P 2
F DI_ T X P 3
F DI_ T X P 4
F DI_ T X P 5
F DI_ T X P 6
F DI_ T X P 7

A2 1
H 19
E1 9
F18
B2 1
C 20
D 18
E1 7

A2 2
G 19
E2 0
G 18
B2 0
C 19
D 19
F17
J18
J17

1 . 05 V S _ V T T

R 38 9

R 3 90

1 K_ 0 4

2 4 . 9 _ 1% _ 0 4

15
15

F DI_ F S Y NC 0
F DI_ F S Y NC 1

15

F DI_ IN T

15
15

R3 8 8
*1 0 0 K _0 4

11
11

D P _ A UXP
D P _ A UXN

11
11
11
11

D P _ T XP 0
D P _ T XP 1
D P _ T XP 2
D P _ T XP 3

11
11
11
11

D
D
D
D

P _ T XN
P _ T XN
P _ T XN
P _ T XN

0
1
2
3

DM
DM
DM
DM

I _ TX [ 0 ]
I _ TX [ 1 ]
I _ TX [ 2 ]
I _ TX [ 3 ]

F D I 0 _ T X #[ 0 ]
F D I 0 _ T X #[ 1 ]
F D I 0 _ T X #[ 2 ]
F D I 0 _ T X #[ 3 ]
F D I 1 _ T X #[ 0 ]
F D I 1 _ T X #[ 1 ]
F D I 1 _ T X #[ 2 ]
F D I 1 _ T X #[ 3 ]

F D I 0 _ T X [ 0]
F D I 0 _ T X [ 1]
F D I 0 _ T X [ 2]
F D I 0 _ T X [ 3]
F D I 1 _ T X [ 0]
F D I 1 _ T X [ 1]
F D I 1 _ T X [ 2]
F D I 1 _ T X [ 3]
F DI0 _ F S Y NC
F DI1 _ F S Y NC
F DI_ IN T

J19
H 17

F DI_ L S Y N C0
F DI_ L S Y N C1

E D P _ C O MP A 1 8
A1 7
ED P_ HPD # B 1 6

D
P Q 47
*M T N 7 0 0 2Z H S 3

G
S

E M B _ HP D

I _ TX # [ 0 ]
I _ TX # [ 1 ]
I _ TX # [ 2 ]
I _ TX # [ 3 ]

H 20

DP Compensation Signal
11

DM
DM
DM
DM

C3 2 5
C3 2 4

* 0 . 1u _ 1 0 V _ X7 R _0 4
* 0 . 1u _ 1 0 V _ X7 R _0 4

D P _ A UX_ P C 1 5
D P _ A UX_ N D 1 5

C3 3 0
C3 2 9
C3 2 7
C5 4 0

*
*
*
*

0 . 1u _ 1 0 V _ X7 R
0 . 1u _ 1 0 V _ X7 R
0 . 1u _ 1 0 V _ X7 R
0 . 1u _ 1 0 V _ X7 R

_0 4
_0 4
_0 4
_0 4

D
D
D
D

P _ TX P _ 0
P _ TX P _ 1
P _ TX P _ 2
P _ TX P _ 3

C 17
F16
C 16
G 15

C3 3 1
C3 2 8
C3 2 6
C5 4 1

*
*
*
*

0 . 1u _ 1 0 V _ X7 R
0 . 1u _ 1 0 V _ X7 R
0 . 1u _ 1 0 V _ X7 R
0 . 1u _ 1 0 V _ X7 R

_0 4
_0 4
_0 4
_0 4

D
D
D
D

P _ TX N
P _ TX N
P _ TX N
P _ TX N

C 18
E1 6
D 16
F15

_0
_1
_2
_3

F DI0 _ L S Y N C
F DI1 _ L S Y N C

e D P _ C O MP I O
e D P _ I C O MP O
e DP _ HP D#

e DP _ A U X
e D P _ A U X#
e D P _ T X[ 0]
e D P _ T X[ 1]
e D P _ T X[ 2]
e D P _ T X[ 3]
e D P _ T X# [ 0 ]
e D P _ T X# [ 1 ]
e D P _ T X# [ 2 ]
e D P _ T X# [ 3 ]

PE G _ RX# [0 ]
PE G _ RX# [1 ]
PE G _ RX# [2 ]
PE G _ RX# [3 ]
PE G _ RX# [4 ]
PE G _ RX# [5 ]
PE G _ RX# [6 ]
PE G _ RX# [7 ]
PE G _ RX# [8 ]
PE G _ RX# [9 ]
P E G_ R X # [ 1 0 ]
P E G_ R X # [ 1 1 ]
P E G_ R X # [ 1 2 ]
P E G_ R X # [ 1 3 ]
P E G_ R X # [ 1 4 ]
P E G_ R X # [ 1 5 ]
P E G _R X [ 0 ]
P E G _R X [ 1 ]
P E G _R X [ 2 ]
P E G _R X [ 3 ]
P E G _R X [ 4 ]
P E G _R X [ 5 ]
P E G _R X [ 6 ]
P E G _R X [ 7 ]
P E G _R X [ 8 ]
P E G _R X [ 9 ]
PE G _ RX[1 0 ]
PE G _ RX[1 1 ]
PE G _ RX[1 2 ]
PE G _ RX[1 3 ]
PE G _ RX[1 4 ]
PE G _ RX[1 5 ]
P E G _T X # [ 0 ]
P E G _T X # [ 1 ]
P E G _T X # [ 2 ]
P E G _T X # [ 3 ]
P E G _T X # [ 4 ]
P E G _T X # [ 5 ]
P E G _T X # [ 6 ]
P E G _T X # [ 7 ]
P E G _T X # [ 8 ]
P E G _T X # [ 9 ]
P E G _ TX # [ 1 0 ]
P E G _ TX # [ 1 1 ]
P E G _ TX # [ 1 2 ]
P E G _ TX # [ 1 3 ]
P E G _ TX # [ 1 4 ]
P E G _ TX # [ 1 5 ]
P E G_ T X [ 0 ]
P E G_ T X [ 1 ]
P E G_ T X [ 2 ]
P E G_ T X [ 3 ]
P E G_ T X [ 4 ]
P E G_ T X [ 5 ]
P E G_ T X [ 6 ]
P E G_ T X [ 7 ]
P E G_ T X [ 8 ]
P E G_ T X [ 9 ]
P E G _T X [ 1 0 ]
P E G _T X [ 1 1 ]
P E G _T X [ 1 2 ]
P E G _T X [ 1 3 ]
P E G _T X [ 1 4 ]
P E G _T X [ 1 5 ]

R6 3

24 . 9 _ 1 %_ 0 4

K3 3
M3 5
L 34
J 35
J 32
H3 4
H3 1
G3 3
G3 0
F35
E3 4
E3 2
D3 3
D3 1
B3 3
C3 2

SC70-5 & SC70-3 Co-lay

Q 17
5
GN D

NC
G ND

4

1
2
3

VC C

VO

* TM P 2 0
3 .3 V
Q 16

J 33
L 35
K3 4
H3 5
H3 2
G3 4
G3 1
F33
F30
E3 5
E3 3
F32
D3 4
E3 1
C3 3
B3 2
M2 9
M3 2
M3 1
L 32
L 29
K3 1
K2 8
J 30
J 28
H2 9
G2 7
E2 9
F27
D2 8
F26
E2 5
M2 8
M3 3
M3 0
L 31
L 28
K3 0
K2 7
J 29
J 27
H2 8
G2 8
E2 8
F28
D2 7
E2 6
D2 5

2

1
VC C

1 :2 ( 4m il s: 8m il s)

OU T

T H E R M_ V O L T 2 8

C 99
3
0 . 1 u _ 10 V _ X 7 R _ 0 4

C1 0 0

GN D

0. 1u _ 1 0V _X 7 R _ 0 4

G7 1 1 S T9 U

1
3

9 /2 0
E VT

2

PL A CE NE A R U3

Sheet 2 of 46
PROCESSOR/ DMI,
PEG, FDI
On Board CPU Thermal Sensor
3 .3 V

Analog Thermal Sensor
C 97
* 0. 1 u _ 1 6V _ Y 5V _0 4
U1 1
D+ _ CP U

1
2

C

DM I_ RXN 0
DM I_ RXN 1
DM I_ RXN 2
DM I_ RXN 3

DM I_ RX [0 ]
DM I_ RX [1 ]
DM I_ RX [2 ]
DM I_ RX [3 ]

P E G_ C O MP

Q 18

V DD
D+

T HE RM
AL ER T

DGN D

S D A TA
S C LK

4
6

R 1 22

*1 0 mi l _ 04

C R I T _T E M P _ R E P # 1 8
T S # _ D I M M0 _ 1 9, 1 0

B
D -_ C P U

*2 N 39 0 4
E

15
15
15
15

B2 8
B2 6
A2 4
B2 3

P E G_ I C O MP I
P E G _I C O MP O
P E G_ R C O MP O

I _ R X # [ 0]
I _ R X # [ 1]
I _ R X # [ 2]
I _ R X # [ 3]

DMI

D M I _ T XP 0
D M I _ T XP 1
D M I _ T XP 2
D M I _ T XP 3

DM
DM
DM
DM

Intel(R) FDI

15
15
15
15

B2 7
B2 5
A2 5
B2 4

0
1
2
3

PCI EXPRESS* - GRAPHICS

ED P F unc ti on Di sa bl e
ED P_ HP D: Pu ll -u p1 0K - DI SA BL ED

I _ T XN
I _ T XN
I _ T XN
I _ T XN

eDP

1. 0 5 V S _ V T T

DM
DM
DM
DM

20 mil

3
5

7
8

S MD _C P U _T H E R M
S MC _C P U _T H E R M

1 4, 2 8
1 4, 2 8

*W 8 3 L 7 71 A W G

11/0 3
P Z 9 8 8 27 -3 6 4 B -0 1F

3, 8 , 1 1 , 1 3, 1 5 , 1 7 , 19 , 2 0 , 2 2 , 23 , 2 7 , 2 9, 3 1 , 3 2 , 3 4, 3 6 3 . 3 V
3 , 5 , 1 8 , 1 9, 2 0 , 3 5 , 37 1 . 0 5 V S _ V T T

PROCESSOR/ DMI, PEG, FDI B - 3

B.Schematic Diagrams

CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with
- typical impedance < 25 mohms

15
15
15
15

J 22
J 21
H2 2

Schematic Diagrams

PROCESSOR/ CLK, MISC, JTAG
Processor Pullups/Pull downs
1. 0 5 V S _ V T T

Sandy Bridge Processor 2/7
( CLK,MISC,JTAG )

PU/PD for JTAG signals
1. 0 5 V S _ V T T

P _T M S
P _T D I _R
P _P R E Q #
P _T D O_ R
P _T C LK
P _T R S T #

P R OC _S E L E C T #

H _ C A TE R R #

S K T OC C #

A L3 3

R 41 7

1 8 H _ T H R MT R I P #

A N3 3
PEC I

5 6_ 1 % _0 4

H _ P R O C H OT # _D A L3 2

* 10 m i _l 0 4

P R OC H OT #

A N3 2
T H E R MT R I P #

S M_ R C OM P [ 0 ]
S M_ R C OM P [ 1 ]
S M_ R C OM P [ 2 ]

* 10 m i _l 0 4

R 41 8

* 10 m i _l 0 4

P MS Y S _ P W R GD _ B U F

R6 0

H _ CP U P W RG D_ R

1 30 _ 1 %_ 0 4

Buffered reset to CPU

1 . 0 5 V S _ V TT

P M_ S Y N C _ R

A M3 4
P M _S Y N C

AP3 3
U N C O R E P W R G OOD

V D D P W R GOO D _ R V 8

B U F _C P U _ R S T#

S M _D R A M P W R OK

A R3 3
R ESET #

R1 0 5

7 5 _1 % _ 0 4

R1 0 4
43 _ 1 % _0 4

11/0 4
6
3 . 3V S
R5 3 0

10 K _ 0 4

D
Q3 6 A
MT D N 7 00 2 Z H S 6 R

2 G

TC K
TM S
T RS T #

JTAG & BPM

18 H _C P U P W R G D

R 41 9

C L K _ E X P _P
C L K _ E X P _N

A1 6
A1 5

14
14

DDR3 Compensation Signals

CL K _ DP _ P 1 4
C L K _ D P _ N 14

R8

C P UD RA M RS T #

AK1
A5
A4

S M _R C O MP _ 0
S M _R C O MP _ 1
S M _R C O MP _ 2

AP2 9
AP2 7

X DP _ P R DY #
X D P _ P R E Q#

A R2 6
A R2 7
AP3 0

X DP _ T CL K
X D P _ T MS
X DP _ T RS T #

A R2 8
AP2 6

X DP _ T DI_ R
X DP _ T DO _ R

S M_ R C OM P _ 0

R4 1 3

14 0 _ 1% _ 0 4

S M_ R C OM P _ 1

R3 8 2

25 . 5 _ 1% _ 0 4

S M_ R C OM P _ 2

R3 8 1

20 0 _ 1% _ 0 4

S3 circuit:- DRAM PWR GOOD logic

H _ TH R M T R I P # _ R

PWR MANAGEMENT

H _ P M_ S Y N C

A2 8
A2 7

S M_ D R A M R S T #

P RDY #
P RE Q #

15

C 5 85

TD I
T DO

3 . 3V

1 . 5V S _C P U

R 73
* 2 00 _ 1 %_ 0 4

X DP _ D B R_ R

M# [ 0 ]
M# [ 1 ]
M# [ 2 ]
M# [ 3 ]
M# [ 4 ]
M# [ 5 ]
M# [ 6 ]
M# [ 7 ]

A T 28
A R2 9
A R3 0
A T 30
AP3 2
A R3 1
A T 31
A R3 2

X DP _ B P M
X DP _ B P M
X DP _ B P M
X DP _ B P M
X DP _ B P M
X DP _ B P M
X DP _ B P M
X DP _ B P M

1

A

2

A

C 3

P M S Y S _P W R GD _ B U F

*B A T 5 4 A W GH

DB R #
BP
BP
BP
BP
BP
BP
BP
BP

1 0 K _0 4
D2 0

1 5 P M_ D R A M_ P W R GD
1 5, 3 4 1 . 8 V S _ P W R G D

A L 35

1230 D02

R5 7

R 58
* 39 _ 0 4
0 _R
1 _R
2 _R
3 _R
4 _R
5 _R
6 _R
7 _R

R 59

0_04

D

H _ P R O C H OT #

H_ P E C I_ R

* 10 m i _l 0 4

DP L L _ RE F _ S S C L K
D P LL _ R E F _S S C L K #

DDR3
MISC

R 40 5

THERMAL

R 41 1

H _P E C I

If P ROC HO T# i s n ot u se d, th en i t mu st
be t erm in at ed wi th a 6 8- O + -5 % pu ll -up
re si sto r to 1 .05 VS _V TT .

Q1 0

G

3 2, 3 4 , 3 5 S U S B

*M T N 7 0 02 Z H S 3

S
P Z 9 8 82 7 -3 64 B -0 1 F

1
D

S

1 0/ 29
Q3 6 B
MT D N 7 00 2 Z H S 6 R
D

Q 14

*1 . 5 K _1 % _ 04

1 . 5V

C 5 15

C9 6

G

2 8 H _ P R O C H OT _ E C

S

R1 1 2
R5 3 1

1 0 0K _0 4

1 7 , 23 P L T _ R S T #

S3 circuit:- DRAM_RST# to memory
should be high during S3

H _P R OC H O T#

4

R1 0 6
* 75 0 _ 1% _ 0 4

10/1

CAD Note: Capacitor need to be placed
close to buffer output pin

R 91

R 90

1 0 0 K _0 4

*0 _ 04

M T N 7 00 2 Z H S 3

4 7 p _5 0 V _ N P O _ 04

3

5 G

*6 8 p_ 5 0 V _N P O_ 0 4

R 47

*0 _ 0 4

R4 5
1K _ 0 4

C P UD RA M RS T #

Q8
MT N 70 0 2 Z H S 3
S
D

1 K_ 0 4
R 48

D D R 3 _ D R A MR S T # 9 , 1 0

2 , 5 , 1 8 , 19 , 2 0 , 3 5, 3 7
6, 3 2
6, 8 , 9 , 1 0 , 20 , 2 7 , 3 2, 3 4
2, 8 , 1 1 , 13 , 1 5 , 1 7, 1 9 , 2 0, 2 2 , 2 3, 27 , 2 9 , 31 , 3 2 , 3 4, 3 6
9 , 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 28 , 2 9 , 30 , 3 1 , 3 2, 3 7

B - 4 PROCESSOR/ CLK, MISC, JTAG

1 . 05 V S _ V T T
1 . 5V S _C P U
1 . 5V
3 . 3V
3 . 3V S

G

R4 6
4 . 99 K _ 1 % _0 4

B.Schematic Diagrams

C A TE R R #

18 , 2 8

BC L K
B CL K #

C2 6

A N3 4

Sheet 3 of 46
PROCESSOR/ CLK,
MISC, JTAG

R4 1 2

TR AC E WI DTH 1 0M IL , LEN GT H <5 00 MIL S
H_ S N B _ IV B #

H_ S N B _ IV B #

XD P _ D B R _ R

37

1 0 K_ 0 4
*0 . 1 u _1 0 V _ X 7R _0 4

U 3 4B

3. 3V S

1 K_ 0 4

R4 1 0

11/03

18

R 40 7

H _ C P U P W R GD _ R

6 2 _ 04

S

XD
XD
XD
XD
XD
XD

CLOCKS

R4 1 6
R1 0 8
R1 0 9
R4 1 5
R4 1 4
R9 5

MISC

5 1 _ 04
5 1 _ 04
*5 1 _ 04
5 1 _ 04
5 1 _ 04
5 1 _ 04

H _P R OC H O T#

C2 2
0 . 0 47 u _ 10 V _ X 7R _ 04

D R A MR S T _C N T R L 8 , 1 4

Schematic Diagrams

PROCESSOR/ DDR3
Sandy Bridge Processor 3/7 ( DDR3 )
U34C

9
9
9

M_A_BS0
M_A_BS1
M_A_BS2

9
9
9

M_A_CAS#
M_A_RAS#
M
_A_WE#

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M
8
N10
N8
N7
M10
M
9
N9
M
7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10
V6

AE8
AD9
AF9

SA_
DQ[0]
SA_
DQ[1]
SA_
DQ[2]
SA_
DQ[3]
SA_
DQ[4]
SA_
DQ[5]
SA_
DQ[6]
SA_
DQ[7]
SA_
DQ[8]
SA_
DQ[9]
SA_
DQ[10]
SA_
DQ[11]
SA_
DQ[12]
SA_
DQ[13]
SA_
DQ[14]
SA_
DQ[15]
SA_
DQ[16]
SA_
DQ[17]
SA_
DQ[18]
SA_
DQ[19]
SA_
DQ[20]
SA_
DQ[21]
SA_
DQ[22]
SA_
DQ[23]
SA_
DQ[24]
SA_
DQ[25]
SA_
DQ[26]
SA_
DQ[27]
SA_
DQ[28]
SA_
DQ[29]
SA_
DQ[30]
SA_
DQ[31]
SA_
DQ[32]
SA_
DQ[33]
SA_
DQ[34]
SA_
DQ[35]
SA_
DQ[36]
SA_
DQ[37]
SA_
DQ[38]
SA_
DQ[39]
SA_
DQ[40]
SA_
DQ[41]
SA_
DQ[42]
SA_
DQ[43]
SA_
DQ[44]
SA_
DQ[45]
SA_
DQ[46]
SA_
DQ[47]
SA_
DQ[48]
SA_
DQ[49]
SA_
DQ[50]
SA_
DQ[51]
SA_
DQ[52]
SA_
DQ[53]
SA_
DQ[54]
SA_
DQ[55]
SA_
DQ[56]
SA_
DQ[57]
SA_
DQ[58]
SA_
DQ[59]
SA_
DQ[60]
SA_
DQ[61]
SA_
DQ[62]
SA_
DQ[63]

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]

SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_
BS[0]
SA_
BS[1]
SA_
BS[2]

SA_
CAS#
SA_
RAS#
SA_
WE#

PZ98
827-364B- 0
1F

AB6
AA6
V9

M_A_CL
K_DDR0 9
M_A_CL
K_DDR#0 9
M_A_CKE0 9

AA5
AB5
V10

10 M_B_DQ[63:0]
M
_B_DQ0
M
_B_DQ1
M
_B_DQ2
M
_B_DQ3
M
_B_DQ4
M
_B_DQ5
M
_B_DQ6
M
_B_DQ7
M
_B_DQ8
M
_B_DQ9
M
_B_DQ10
M
_B_DQ11
M
_B_DQ12
M
_B_DQ13
M
_B_DQ14
M
_B_DQ15
M
_B_DQ16
M
_B_DQ17
M
_B_DQ18
M
_B_DQ19
M
_B_DQ20
M
_B_DQ21
M
_B_DQ22
M
_B_DQ23
M
_B_DQ24
M
_B_DQ25
M
_B_DQ26
M
_B_DQ27
M
_B_DQ28
M
_B_DQ29
M
_B_DQ30
M
_B_DQ31
M
_B_DQ32
M
_B_DQ33
M
_B_DQ34
M
_B_DQ35
M
_B_DQ36
M
_B_DQ37
M
_B_DQ38
M
_B_DQ39
M
_B_DQ40
M
_B_DQ41
M
_B_DQ42
M
_B_DQ43
M
_B_DQ44
M
_B_DQ45
M
_B_DQ46
M
_B_DQ47
M
_B_DQ48
M
_B_DQ49
M
_B_DQ50
M
_B_DQ51
M
_B_DQ52
M
_B_DQ53
M
_B_DQ54
M
_B_DQ55
M
_B_DQ56
M
_B_DQ57
M
_B_DQ58
M
_B_DQ59
M
_B_DQ60
M
_B_DQ61
M
_B_DQ62
M
_B_DQ63

M_A_CL
K_DDR1 9
M_A_CL
K_DDR#1 9
M_A_CKE1 9

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

M_A_CS#0 9
M_A_CS#1 9

AH3
AG3
AG2
AH2

M_A_ODT0 9
M_A_ODT1 9

C4
G
6
J3
M
6
AL6
AM8
AR12
AM15

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

D4
F6
K3
N6
AL5
AM9
AR11
AM14

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M
_A_DQS#[7:0] 9

M
_A_DQS[7:0] 9

M
_A_A[15:0] 9

10
10
10

M_B_BS0
M_B_BS1
M_B_BS2

10
10
10

M_B_CAS#
M_B_RAS#
M
_B_WE#

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7
R6

AA10
AB8
AB9

SB_DQ
[0]
SB_DQ
[1]
SB_DQ
[2]
SB_DQ
[3]
SB_DQ
[4]
SB_DQ
[5]
SB_DQ
[6]
SB_DQ
[7]
SB_DQ
[8]
SB_DQ
[9]
SB_DQ
[10]
SB_DQ
[11]
SB_DQ
[12]
SB_DQ
[13]
SB_DQ
[14]
SB_DQ
[15]
SB_DQ
[16]
SB_DQ
[17]
SB_DQ
[18]
SB_DQ
[19]
SB_DQ
[20]
SB_DQ
[21]
SB_DQ
[22]
SB_DQ
[23]
SB_DQ
[24]
SB_DQ
[25]
SB_DQ
[26]
SB_DQ
[27]
SB_DQ
[28]
SB_DQ
[29]
SB_DQ
[30]
SB_DQ
[31]
SB_DQ
[32]
SB_DQ
[33]
SB_DQ
[34]
SB_DQ
[35]
SB_DQ
[36]
SB_DQ
[37]
SB_DQ
[38]
SB_DQ
[39]
SB_DQ
[40]
SB_DQ
[41]
SB_DQ
[42]
SB_DQ
[43]
SB_DQ
[44]
SB_DQ
[45]
SB_DQ
[46]
SB_DQ
[47]
SB_DQ
[48]
SB_DQ
[49]
SB_DQ
[50]
SB_DQ
[51]
SB_DQ
[52]
SB_DQ
[53]
SB_DQ
[54]
SB_DQ
[55]
SB_DQ
[56]
SB_DQ
[57]
SB_DQ
[58]
SB_DQ
[59]
SB_DQ
[60]
SB_DQ
[61]
SB_DQ
[62]
SB_DQ
[63]

SB_
CLK[0]
SB_CLK#[0]
SB_CKE[0]

SB_
CLK[1]
SB_CLK#[1]
SB_CKE[1]

SB_
CLK[2]
SB_CLK#[2]
SB_CKE[2]

SB_
CLK[3]
SB_CLK#[3]
SB_CKE[3]

SB_
CS#[0]
SB_
CS#[1]
SB_
CS#[2]
SB_
CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_
MA[ 1
0]
SB_
MA[ 1
1]
SB_
MA[ 1
2]
SB_
MA[ 1
3]
SB_
MA[ 1
4]
SB_
MA[ 1
5]

SB_BS[ 0]
SB_BS[ 1]
SB_BS[ 2]

SB_CAS#
SB_RAS#
SB_WE#

AE2
AD2
R9

M_B_CLK_DDR0 10
M_B_CLK_DDR#0 10
M_B_CKE0 10

AE1
AD1
R10

M_B_CLK_DDR1 10
M_B_CLK_DDR#1 10
M_B_CKE1 10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

M_B_CS#0 10
M_B_CS#1 10

AE4
AD4
AD5
AE5

Sheet 4 of 46
PROCESSOR/
DDR3

M_B_ODT
0 10
M_B_ODT
1 10

D7
F3
K6
N3
AN5
AP9
AK12
AP15

M_B_DQ
S#0
M_B_DQ
S#1
M_B_DQ
S#2
M_B_DQ
S#3
M_B_DQ
S#4
M_B_DQ
S#5
M_B_DQ
S#6
M_B_DQ
S#7

C7
G3
J6
M3
AN6
AP8
AK11
AP14

M_B_DQ
S0
M_B_DQ
S1
M_B_DQ
S2
M_B_DQ
S3
M_B_DQ
S4
M_B_DQ
S5
M_B_DQ
S6
M_B_DQ
S7

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_B_B0
M_B_B1
M_B_B2
M_B_B3
M_B_B4
M_B_B5
M_B_B6
M_B_B7
M_B_B8
M_B_B9
M_B_B10
M_B_B11
M_B_B12
M_B_B13
M_B_B14
M_B_B15

M_B_DQS#[ 7
: 0] 10

M_B_DQS[ 7:0] 10

M_B_B[15:0] 10

PZ98827-364B-01F

PROCESSOR/ DDR3 B - 5

B.Schematic Diagrams

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ1
0
M_A_DQ1
1
M_A_DQ1
2
M_A_DQ1
3
M_A_DQ1
4
M_A_DQ1
5
M_A_DQ1
6
M_A_DQ1
7
M_A_DQ1
8
M_A_DQ1
9
M_A_DQ2
0
M_A_DQ2
1
M_A_DQ2
2
M_A_DQ2
3
M_A_DQ2
4
M_A_DQ2
5
M_A_DQ2
6
M_A_DQ2
7
M_A_DQ2
8
M_A_DQ2
9
M_A_DQ3
0
M_A_DQ3
1
M_A_DQ3
2
M_A_DQ3
3
M_A_DQ3
4
M_A_DQ3
5
M_A_DQ3
6
M_A_DQ3
7
M_A_DQ3
8
M_A_DQ3
9
M_A_DQ4
0
M_A_DQ4
1
M_A_DQ4
2
M_A_DQ4
3
M_A_DQ4
4
M_A_DQ4
5
M_A_DQ4
6
M_A_DQ4
7
M_A_DQ4
8
M_A_DQ4
9
M_A_DQ5
0
M_A_DQ5
1
M_A_DQ5
2
M_A_DQ5
3
M_A_DQ5
4
M_A_DQ5
5
M_A_DQ5
6
M_A_DQ5
7
M_A_DQ5
8
M_A_DQ5
9
M_A_DQ6
0
M_A_DQ6
1
M_A_DQ6
2
M_A_DQ6
3

DDR SYSTEM MEMORY B

M
_A_DQ[63:0]

DDR SYSTEM MEMORY A

9

U34D

Schematic Diagrams

PROCESSOR/ POWER1
Sandy Bridge Processor 4/7
POWER

U 34F

layout? check

B.Schematic Diagrams

Sheet 5 of 46
PROCESSOR/
POWER1

C 353

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 371

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 366

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 354

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 359

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 363

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 337

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 332

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 351

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 336

2 2u _ 6 . 3 V _ X 5 R _ 0 8

C 69

1 0u _ 6 . 3 V _ X 5 R _ 0 6

C 33

1 0u _ 6 . 3 V _ X 5 R _ 0 6

C 74

1 0u _ 6 . 3 V _ X 5 R _ 0 6

C 56

1 0u _ 6 . 3 V _ X 5 R _ 0 6

C 34

1 0u _ 6 . 3 V _ X 5 R _ 0 6

V C OR E

C 53

1 0u _ 6 . 3 V _ X 5 R _ 0 6

C 362

*2 2 u _ 6. 3V _X 5 R _ 08

C 360

*2 2 u _ 6. 3V _X 5 R _ 08

C 334

*2 2 u _ 6. 3V _X 5 R _ 08

C 333

*2 2 u _ 6. 3V _X 5 R _ 08

C 356

*2 2 u _ 6. 3V _X 5 R _ 08

C 62

*1 0 u _ 6. 3V _X 5 R _ 06

C 72

*1 0 u _ 6. 3V _X 5 R _ 06

C 59

*1 0 u _ 6. 3V _X 5 R _ 06

C 66

*1 0 u _ 6. 3V _X 5 R _ 06

V C OR E

PROCESSOR UNCORE POWER
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10 0

P EG AND DDR

SV 48

V C OR E

A G3 5
A G3 4
A G3 3
A G3 2
A G3 1
A G3 0
A G2 9
A G2 8
A G2 7
A G2 6
AF3 5
AF3 4
AF3 3
AF3 2
AF3 1
AF3 0
AF2 9
AF2 8
AF2 7
AF2 6
A D3 5
A D3 4
A D3 3
A D3 2
A D3 1
A D3 0
A D2 9
A D2 8
A D2 7
A D2 6
A C3 5
A C3 4
A C3 3
A C3 2
A C3 1
A C3 0
A C2 9
A C2 8
A C2 7
A C2 6
AA3 5
AA3 4
AA3 3
AA3 2
AA3 1
AA3 0
AA2 9
AA2 8
AA2 7
AA2 6
Y3 5
Y3 4
Y3 3
Y3 2
Y3 1
Y3 0
Y2 9
Y2 8
Y2 7
Y2 6
V3 5
V3 4
V3 3
V3 2
V3 1
V3 0
V2 9
V2 8
V2 7
V2 6
U3 5
U3 4
U3 3
U3 2
U3 1
U3 0
U2 9
U2 8
U2 7
U2 6
R3 5
R3 4
R3 3
R3 2
R3 1
R3 0
R2 9
R2 8
R2 7
R2 6
P3 5
P3 4
P3 3
P3 2
P3 1
P3 0
P2 9
P2 8
P2 7
P2 6

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

A H1 3
A H1 0
A G1 0
A C1 0
Y1 0
U1 0
P1 0
L 10
J 14
J 13
J 12
J 11
H1 4
H1 2
H1 1
G1 4
G1 3
G1 2
F14
F13
F12
F11
E1 4
E1 2

1 .0 5 VS _ V T T

8.5A

C 361

C 357

C 365

C 3 98

C 3 50

2 2 u _ 6 . 3 V _ X5 R _ 0 8

2 2 u _ 6 . 3V _ X5 R _ 0 8

2 2 u _ 6. 3V _X 5 R _ 08

* 22 u _ 6 . 3 V _ X 5 R _ 0 8

* 22 u _ 6 . 3 V _ X 5R _ 0 8

C 402

C 355

C 344

C 364

C 3 58

C 3 46

* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

* 22 u _ 6 . 3 V _ X 5 R _ 0 8

2 2 u _6 . 3 V _ X 5 R _0 8

C 396

C 419

C 406

C 3 97

C 3 84

* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

* 22 u _ 6 . 3 V _ X 5 R _ 0 8

2 2 u _6 . 3 V _ X 5 R _0 8

C 321

C 418

C 375

C 3 83

C 3 82

* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

2 2 u _ 6. 3V _X 5 R _ 08

2 2 u _ 6. 3 V _X 5 R _ 08

* 22 u _ 6 . 3 V _ X 5R _ 0 8

C 407

C 372

C 352

C 3 67

C 3 85

* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8

2 2 u _ 6 . 3V _ X5 R _ 0 8

2 2 u _ 6. 3V _X 5 R _ 08

2 2 u _ 6. 3 V _X 5 R _ 08

2 2 u _6 . 3 V _ X 5 R _0 8

C 381

C 394

C 420

C 3 68

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

* 2 2u _ 6 . 3 V _ X 5 R _ 0 8

* 22 u _ 6 . 3 V _ X 5 R _ 0 8

+
2 2 0 u _ 6. 3 V _6 . 3 * 6 . 3* 4 . 2

C 417
+
2 2 0 u _ 6. 3 V _6 . 3 * 6 . 3* 4 . 2

E1 1
D1 4
D1 3
D1 2
D1 1
C1 4
C1 3
C1 2
C1 1
B1 4
B1 2
A1 4
A1 3
A1 2
A1 1

V C C I O 40

* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
+ V 1 .0 5 S _ V CC P _ F

R6 2

*2 0 m i l _0 4

1 . 0 5V S _ V T T

CAD Note: H_CPU_SVIDALRT#_R,H_CPU_SVIDDAT_R
Place the PU resistors close to CPU

SVID Signals
1 .0 5 V S _ VT T

V I D A L E R T#
V IDS CL K
V ID S O UT

AJ 2 9
AJ 3 0
AJ 2 8

H _ C P U _ S V I D A L R T #_ R
H _ C P U _ S V I D C LK _ R
H _ CP U_ S VID D A T _ R

R4 0 6
R8 8
R8 5

4 3_ 1 % _ 0 4
0 _0 4
0 _0 4

H _ C P U _S V I D A L R T # 3 7
H _ C P U _S V I D C L K 3 7
H _ C P U _S V I D D A T 3 7

H _ C P U_ S V IDA L R T #
H _ C P U_ S V IDC L K
H _ C P U_ S V IDD A T _ R

7 5 _ 1 % _0 4
* 5 4. 9_ 1 % _ 0 4
1 3 0 _ 1 %_ 0 4

CAD Note: H_CPU_SVIDCLK_R
Place the PU
resistors close to VR

V C OR E _ V C C _ S E N S E 3 7
V C OR E _ V S S _ S E N S E 3 7

1126

P Z 9 88 2 7 -3 6 4 B -0 1 F

B - 6 PROCESSOR/ POWER1

V C C I O1
V C C I O2
V C C I O3
V C C I O4
V C C I O5
V C C I O6
V C C I O7
V C C I O8
V C C I O9
V C C I O 10
V C C I O 11
V C C I O 12
V C C I O 13
V C C I O 14
V C C I O 15
V C C I O 16
V C C I O 17
V C C I O 18
V C C I O 19
V C C I O 20
V C C I O 21
V C C I O 22
V C C I O 23
V C C I O 24

J 23

SVI D

ICCMAX Maximum Process or

48A

SEN SE LIN ES

PROCES SOR CORE POWER

layout? check

CORE SUPPL Y

V CO RE

V CC _ S E N S E
V SS_ SEN SE

AJ 3 5
AJ 3 4

V C OR E

1 . 0 5 V S _V TT

R 6 87

* 10 _ 0 4
V C CIO _ S E N SE
V SS IO _ S E N S E

B1 0
A1 0

V CC IO _ S E N S E _ R
V SS IO _ S E N SE

R3 7 9

10 _ 0 4
R 38 4

* 0 _ 04

V CC IO _ SE N S E 3 5
3 7 , 3 8 V C OR E
2 , 3 , 18 , 1 9 , 2 0 , 3 5 , 3 7 1 . 0 5V S _ V T T

R 38 3

1 0 _0 4

R4 0 8
R8 9
R8 6

Schematic Diagrams

PROCESSOR/ POWER2
Sandy Bridge Processor 5/7

( GRAPHICS POWER )

layout? check

POWER

U 34 G

1. 5 V

V G F X _C OR E

2 2 u _6 . 3 V _ X 5R _ 08

C 38 6

C 3 76

C 3 74

C3 1 7

C 3 77

2 2 u_ 6 . 3 V _ X5 R _0 8

2 2 u _6 . 3 V _ X 5R _ 08

22 u _ 6. 3 V _ X 5 R _ 08

22 u _ 6. 3V _ X 5 R _ 0 8

2 2 u _6 . 3 V _ X 5R _ 08

C 31 5
* 33 0 U _ 2 . 5 V _D 2 _D

C 3 14
+

C 3 18

* 2 2u _ 6 . 3V _X 5 R _ 0 8
5 6 0 u_ 2 . 5 V _ 6. 6 * 6. 6 *5 . 9

C 37 3
2 2 u_ 6 . 3 V _ X5 R _0 8

C 38 9

C3 9 0

C 3 22

2 2 u_ 6 . 3 V _ X5 R _0 8

2 2u _ 6 . 3V _X 5 R _ 0 8

2 2 u _ 6. 3 V _ X 5R _ 08

1 .8 V S

All VCCPLL = 1.2A
+ C4 5 8

C3 1 6

3 3 0 uF _2 .5 V _ 9 m_ 6 . 3 *6 10 u _ 6. 3 V _ X 5 R _ 0 6

C3 1 9

C 3 20

1 u_ 6 . 3 V _ X5 R _ 0 4

1 u _ 6. 3V _ X 5 R _ 0 4

B6
A6
A2

VCC P L L 1
VCC P L L 2
VCC P L L 3

AK3 5
AK3 4

V C C _ GT _ S E N S E 3 7
V S S _ G T_ S E N S E 3 7
V _S M _ V R E F
R1 1 4
*1 0 0K _1 % _ 04

11/03
C5 8 6
A L1
S M _ V RE F

1 K _ 1 %_ 0 4

Q1 5
*A O 3 40 2 L
S
D

V _ S M_ V R E F _ C N T

R 11 7

G

22 u _ 6. 3V _ X 5 R _ 0 8

VREF

*2 2u _ 6 . 3 V _X 5 R _ 0 8

V A X G _S E N S E
V S S A X G _S E N S E

DDR3 -1.5V RAILS

2 2 u _6 . 3 V _ X 5R _ 08

V A X G1
V A X G2
V A X G3
V A X G4
V A X G5
V A X G6
V A X G7
V A X G8
V A X G9
V A X G1 0
V A X G1 1
V A X G1 2
V A X G1 3
V A X G1 4
V A X G1 5
V A X G1 6
V A X G1 7
V A X G1 8
V A X G1 9
V A X G2 0
V A X G2 1
V A X G2 2
V A X G2 3
V A X G2 4
V A X G2 5
V A X G2 6
V A X G2 7
V A X G2 8
V A X G2 9
V A X G3 0
V A X G3 1
V A X G3 2
V A X G3 3
V A X G3 4
V A X G3 5
V A X G3 6
V A X G3 7
V A X G3 8
V A X G3 9
V A X G4 0
V A X G4 1
V A X G4 2
V A X G4 3
V A X G4 4
V A X G4 5
V A X G4 6
V A X G4 7
V A X G4 8
V A X G4 9
V A X G5 0
V A X G5 1
V A X G5 2
V A X G5 3
V A X G5 4

V _ S M _ V R E F 0 _0 4

R 1 16

1 K _ 1 %_ 0 4

11/03

* 0 . 1u _ 1 0V _ X 7 R _ 0 4

SU SB#

1 5 , 27 , 2 8 , 3 2

V _ S M _V R E F _ C N T

CAD Note: +V_SM_VREF should
have 10 mil trace width

layout? check
1 . 5V S _C P U

V D DQ 1
V D DQ 2
V D DQ 3
V D DQ 4
V D DQ 5
V D DQ 6
V D DQ 7
V D DQ 8
V D DQ 9
V D DQ 1 0
V D DQ 1 1
V D DQ 1 2
V D DQ 1 3
V D DQ 1 4
V D DQ 1 5

AF7
AF4
AF1
A C7
A C4
A C1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

All VDDQ = 12A
1230 D02
C6 0

C6 7

C 63

C6 5

C 58

1 0u _ 6 . 3V _X 5 R _ 0 6

10 u _ 6. 3 V _ X 5 R _ 06

1 0 u_ 6 . 3 V _ X5 R _0 6

1 0u _ 6 . 3V _X 5 R _ 0 6

1 0 u _ 6. 3 V _ X 5R _ 06

+

C4 0 0
33 0 U _ 2 V _ D 2 _ D

1124 for ? ? ? ?

C7 1

Sheet 6 of 46
PROCESSOR/
POWER2

1 0u _ 6 . 3V _X 5 R _ 0 6

1229 D02(W240HU)
0. 8 5 V S

SA RAIL

2 2 u_ 6 . 3 V _ X5 R _0 8

AT2 4
AT2 3
AT2 1
AT2 0
AT1 8
AT1 7
A R2 4
A R2 3
A R2 1
A R2 0
A R1 8
A R1 7
AP2 4
AP2 3
AP2 1
AP2 0
AP1 8
AP1 7
A N2 4
A N2 3
A N2 1
A N2 0
A N1 8
A N1 7
A M2 4
A M2 3
A M2 1
A M2 0
A M1 8
A M1 7
AL 2 4
AL 2 3
AL 2 1
AL 2 0
AL 1 8
AL 1 7
AK2 4
AK2 3
AK2 1
AK2 0
AK1 8
AK1 7
AJ 2 4
AJ 2 3
AJ 2 1
AJ 2 0
AJ 1 8
AJ 1 7
A H2 4
A H2 3
A H2 1
A H2 0
A H1 8
A H1 7

P Z 9 8 8 27 -3 6 4B -01 F

VC
VC
VC
VC
VC
VC
VC
VC

CS A
CS A
CS A
CS A
CS A
CS A
CS A
CS A

1
2
3
4
5
6
7
8

M2 7
M2 6
L2 6
J2 6
J2 5
J2 4
H2 6
H2 5

All VDDQ = 6A
C3 2 3

C 3 45

C 28

1 0u _ 6 . 3V _X 5 R _ 0 8

10 u _ 6. 3 V _ X 5 R _ 08

1 0 u_ 6 . 3 V _ X5 R _0 6

V C C S A _S E N S E

C2 2
C2 4

*1 0u _ 6 . 3 V _X 5 R _ 0 6
* 3 30 U _ 2 V _ D2 _ D

V CC S A _ S E N SE

R 53 2
F C _C 2 2
V C CS A _ V ID 1

C8 1 1
+P C 1 67

1230 D02
H2 3

MISC

C 3 87

GRAPHICS

C3 8 8

1.8V RAIL

C 3 69

* 0_ 0 4
R 56

V C C S A _S E N S E

1 0 K_ 0 4

1 .5 V S _ CP U

36

V CC S A _ V ID0 3 6

* 1 0K _ 0 4
R 3 93
V CC S A _ V ID1 3 6

1 0 K _ 04
R 3 86

36
1 9 , 30 , 3 2
1 8 , 19 , 3 4
3 , 8 , 9 , 1 0, 20 , 2 7 , 32 , 3 4
3 ,3 2
38
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 3 , 24 , 2 5 , 2 6, 2 8 , 2 9, 30 , 3 1 , 32 , 3 7

0 . 85 V S
1 . 5V S
1 . 8V S
1 . 5V
1 . 5V S _C P U
V GF X_ C OR E
3 . 3V S

PROCESSOR/ POWER2 B - 7

B.Schematic Diagrams

+

C 3 92

SENSE
LINES

R 11 9

All VAXG = 33A
C 39 1

Schematic Diagrams

PROCESSOR/ GND
Sandy Bridge Processor 6/7 ( GND )
U3 4H

B.Schematic Diagrams

CAD Note: 0 ohm resistor
should be placed close
to CPU

Sheet 7 of 46
CPU 6/7 (GND)

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
VSS5 3
VSS5 4
VSS5 5
VSS5 6
VSS5 7
VSS5 8
VSS5 9
VSS6 0
VSS6 1
VSS6 2
VSS6 3
VSS6 4
VSS6 5
VSS6 6
VSS6 7
VSS6 8
VSS6 9
VSS7 0
VSS7 1
VSS7 2
VSS7 3
VSS7 4
VSS7 5
VSS7 6
VSS7 7
VSS7 8
VSS7 9
VSS8 0

PZ98827 -364B-0 1F

B - 8 PROCESSOR/ GND

U34I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N 35
N 34
N 33
N 32
N 31
N 30
N 29
N 28
N 27
N 26
M34
L 33
L 30
L 27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J 34
J 31
H 33
H 30
H 27
H 24
H 21
H 18
H 15
H 13
H 10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G 35
G 32
G 29
G 26
G 23
G 20
G 17
G 11
F34
F31
F29

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

PZ98 827-3 64B-01F

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D3 5
D3 2
D2 9
D2 6
D2 0
D1 7
C3 4
C3 1
C2 8
C2 7
C2 5
C2 3
C1 0
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

Schematic Diagrams

PROCESSOR/ RESERVED
Sandy Bridge Processor 7/7
( RESERVED )

CFG Straps for Processor

U3 4 E

R 11 1

CF G 0
CF G 2
CF G 4
CF G 5
CF G 6
CF G 7

*1 K _ 0 4

CF G 4

R 11 0

H
H
H
H

*1 K _ 0 4

_ CP U
_ CP U
_ CP U
_ CP U

_R
_R
_R
_R

SVD
SVD
SVD
SVD

1 AJ 3 1
2A H 3 1
3 AJ 3 3
4A H 3 3

AJ 2 6

V R E F _ C H _ A _ D I MM B 4
V R E F _ C H _ B _ D I MM D 1

PCIE Port Bifurcation Straps

CFG[6:5]
CF G 5

CF G 6

R 99

R 92

11:
10:
01:
00:

(Default) x16 - Device 1 functions 1 and 2 disabled
x8, x8 - Device 1 function 1 enabled ; function 2 disabled
Reserved - (Device 1 function 1 disabled ; function 2 enabled)
x8,x4,x4 - Device 1 functions 1 and 2 enabled

*1 K _ 0 4

*1 K _ 0 4

PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7 0: PEG Wait for BIOS for training

F25
F24
F23
D 24
G 25
G 24
E2 3
D 23
C 30
A3 1
B3 0
B2 9
D 30
B3 1
A3 0
C 29
J20
B1 8
A1 9

CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G

R
R
R
R
R

[ 0]
[ 1]
[ 2]
[ 3]
[ 4]
[ 5]
[ 6]
[ 7]
[ 8]
[ 9]
[ 10 ]
[ 11 ]
[ 12 ]
[ 13 ]
[ 14 ]
[ 15 ]
[ 16 ]
[ 17 ]

S V D2 8
S V D2 9
S V D3 0
S V D3 1
S V D3 2

R S V D3 3
R S V D3 4
R S V D3 5

R S V D3 7
R S V D3 8
R S V D3 9
R S V D4 0

V A X G_ V A L _ S E N S E
V S S A X G_ V A L _ S E N S E
V C C _V A L_ S E N S E
V S S _ V A L _S E N S E

R
R
R
R
R

S V D4 1
S V D4 2
S V D4 3
S V D4 4
S V D4 5

R
R
R
R
R

S V D4 6
S V D4 7
S V D4 8
S V D4 9
S V D5 0

L7
AG 7
AE7
AK2
W8

AT2 6
A M 33
AJ 2 7

T8
J16
H1 6
G1 6

Sheet 8 of 46
PROCESSOR/
RESERVED

A R 35
AT3 4
AT3 3
AP3 5
A R 34

RS VD 5

RS VD 6
RS VD 7

RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD
RS VD

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

RS VD 2 4
RS VD 2 5
V C C I O_ S E L

B3 4
A3 3
A3 4
B3 5
C3 5
1. 5 V
R 40

R S V D5 1
R S V D5 2

A H 27
V CC _ DIE _ S E N S E

R S V D5 4
R S V D5 5

R S V D5 6
R S V D5 7
R S V D5 8

R 38

V R E F _C H _ A _ D I M M

*1 K _ 0 4

M V R E F _ D Q_ D I M MA 9
R 31

1 0/ 29

D R A MR S T _C N T R L 3 , 1 4

AT2
AT1
AR 1

1 .5 V
R 44

KEY

1 K _ 1 % _0 4
MV R E F _ D Q _D I M0

1 K _ 1 % _0 4

RS VD 2 7
R 93

Q7
* A O3 4 02 L
S
D

R3 9
*1 K _ 04

A N 35
A M 35

J15

CF G 7

* 0_ 0 4

AJ 3 2
AK3 2

* 0_ 0 4
R2 8

B1
V R E F _C H _ B _ D I M M

Q6
* A O3 4 02 L
S
D MV R E F _ D Q _ D I M 1

1 K _1 % _ 0 4
M V R E F _ D Q_ D I M MB 1 0

3 .3 V

R3 9 2

10 K _ 0 4

P Z 9 8 82 7 -3 64 B -0 1 F

1 0/2 9
R3 9 1

R4 9
*1 K _ 04

R2 9

1 0/ 29

1 K _1 % _ 0 4
* 10 m i l_ 0 4

H _ S N B _ I V B # _P W R C TR L
D R A MR S T _C N T R L

On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V

3 , 6 , 9 , 1 0, 2 0 , 2 7, 3 2 , 3 4 1. 5 V
2 , 3 , 11 , 1 3 , 1 5, 1 7 , 1 9, 20 , 2 2 , 23 , 2 7 , 2 9, 3 1 , 3 2, 3 4 , 3 6 3. 3 V

PROCESSOR/ RESERVED B - 9

B.Schematic Diagrams

Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
CFG4 attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port

AK2 8
AK2 9
AL 2 6
AL 2 7
AK2 6
AL 2 9
AL 3 0
AM 3 1
AM 3 2
AM 3 0
AM 2 8
AM 2 6
AN 2 8
AN 3 1
AN 2 6
AM 2 7
AK3 1
AN 2 9

G

CF G 2

1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed

G

CFG2

RESERVED

PEG Static Lane Reversal - CFG2 is for the 16x

Schematic Diagrams

DDR3 SO-DIMM_0
SO-DIMM A

B.Schematic Diagrams

4

Sheet 9 of 46
DDR3 SO-DIMM_0

4
4
4
4

M_ A _ A [ 1 5: 0]

4 M _ A_ BS0
4 M _ A_ BS1
4 M _ A_ BS2
4 M _ A_ CS # 0
4 M _ A_ CS # 1
M_ A _ C L K _ D D R
M_ A _ C L K _ D D R
M_ A _ C L K _ D D R
M_ A _ C L K _ D D R
4 M _ A_ CK E0
4 M _ A_ CK E1
4 M_ A _ C A S #
4 M_ A _ R A S #
4 M_ A _ W E #

CHANGE TO STANDARD

M_ A _ A 0
M_ A _ A 1
M_ A _ A 2
M_ A _ A 3
M_ A _ A 4
M_ A _ A 5
M_ A _ A 6
M_ A _ A 7
M_ A _ A 8
M_ A _ A 9
M_ A _ A 1 0
M_ A _ A 1 1
M_ A _ A 1 2
M_ A _ A 1 3
M_ A _ A 1 4
M_ A _ A 1 5

0
#0
1
#1

S A 0 _D I M0
S A 1 _D I M0

10 , 1 4 S MB _C L K
1 0 , 1 4 S MB _ D A T A

3 .3 VS

RN 2
1 0 K _8 P 4 R _0 4
1
8 S A 1_ D I M1
2
7 S A 0_ D I M1
3
6 S A 1_ D I M0
4
5 S A 0_ D I M0

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120

4 M _ A _ OD T 0
4 M _ A _ OD T 1

11
28
46
63
136
153
170
187

S A 1 _ D I M 1 10
S A 0 _ D I M 1 10

4

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

M_ A _ D Q S [ 7 : 0 ]

4 M_ A _ D QS # [ 7 : 0 ]

M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q

S0
S1
S2
S3
S4
S5
S6
S7

12
29
47
64
137
154
171
188

M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q

S# 0
S# 1
S# 2
S# 3
S# 4
S# 5
S# 6
S# 7

10
27
45
62
135
152
169
186

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 1 0 /A P
A1 1
A 1 2 /B C#
A1 3
A1 4
A1 5
BA0
BA1
BA2
S0 #
S1 #
CK 0
C K 0#
CK 1
C K 1#
CK E 0
CK E 1
CA S #
RA S #
W E#
SA0
SA1
SC L
SD A
OD T 0
OD T 1
DM
DM
DM
DM
DM
DM
DM
DM

0
1
2
3
4
5
6
7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0
S1
S2
S3
S4
S5
S6
S7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0 #
S1 #
S2 #
S3 #
S4 #
S5 #
S6 #
S7 #

DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 1 0
DQ 1 1
DQ 1 2
DQ 1 3
DQ 1 4
DQ 1 5
DQ 1 6
DQ 1 7
DQ 1 8
DQ 1 9
DQ 2 0
DQ 2 1
DQ 2 2
DQ 2 3
DQ 2 4
DQ 2 5
DQ 2 6
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
DQ 3 1
DQ 3 2
DQ 3 3
DQ 3 4
DQ 3 5
DQ 3 6
DQ 3 7
DQ 3 8
DQ 3 9
DQ 4 0
DQ 4 1
DQ 4 2
DQ 4 3
DQ 4 4
DQ 4 5
DQ 4 6
DQ 4 7
DQ 4 8
DQ 4 9
DQ 5 0
DQ 5 1
DQ 5 2
DQ 5 3
DQ 5 4
DQ 5 5
DQ 5 6
DQ 5 7
DQ 5 8
DQ 5 9
DQ 6 0
DQ 6 1
DQ 6 2
DQ 6 3

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
12 9
13 1
14 1
14 3
13 0
13 2
14 0
14 2
14 7
14 9
15 7
15 9
14 6
14 8
15 8
16 0
16 3
16 5
17 5
17 7
16 4
16 6
17 4
17 6
18 1
18 3
19 1
19 3
18 0
18 2
19 2
19 4

M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q

M_ A _ D Q [ 6 3: 0 ] 4

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

J D I M M2 B
1 .5 V
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

3 .3 V S

2 0 mil s
C1 0 1

C 1 02

1u _ 6 . 3V _Y 5 V _0 4

0 . 1 u _ 16 V _ Y 5 V _ 0 4

199
3 .3 V S
R 12 4

77
122
125

*1 0 K _ 0 4

198
30

2, 10 T S # _ D I M M0 _ 1
3, 10 D D R 3_ D R A M R S T #
C2 4
C2 3

1 u _ 6 . 3V _X 5 R _ 0 4
0 . 1 u _ 10 V _ X 5 R _ 0 4

8 M V R E F _ D Q_ D I M MA
R4 1

CLOS E TO SO- DIM M_ 0

1 .5 V

R9 4

1K _ 1 % _ 04

M V R E F _ D I M0

R1 0 3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

V DD S P D
NC 1
NC 2
N C TE S T
E VE NT #
RES E T #

V RE F _ D Q
V RE F _ C A

*0 _ 04

M V R E F _D I M0
C9 2
C9 1

1
126

V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD

1 u _ 6 . 3V _X 5 R _ 0 4
0 . 1 u _ 10 V _ X 5 R _ 0 4

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5

VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

V T T _M E M
V TT 1
V TT 2
G1
G2

203
204
G ND 1
G ND 2

D D R S K - 20 4 0 1-T R 5B

1 K _ 1% _ 0 4

D D R S K -2 0 40 1 -T R 5 B

? ? ? DIMM SLOT? ?

V T T _ ME M

J D I MM2 A

C1 0 3

C1 0 5

C1 0 4

C 1 06

C 1 11

1 u_ 6 . 3 V _ X5 R _0 4

1u _ 6 . 3 V _ X5 R _0 4

1u _ 6 . 3V _X 5 R _ 0 4

1 u _ 6 . 3V _X 5 R _ 0 4

1 0 u _6 . 3 V _ X 5R _ 06

1 .5 V

+ C3 4 7

+

C3 7 0

C 64

C5 7

C5 5

C6 1

C4 0

C 70

C 84

C 46

*2 2 0u _ 4 V _ V _ A

1 0 u_ 1 0 V _ Y 5 V _ 08

1 0u _ 1 0 V _Y 5 V _ 08

1 0u _ 6 . 3V _X 5 R _ 0 6

1u _ 6 . 3 V _X 5 R _0 4

1u _ 6 . 3V _X 5 R _ 0 4

1 u _ 6 . 3V _ X 5 R _ 0 4

1 u _ 6. 3 V _ X 5 R _ 0 4

1 u _ 6. 3 V _ X 5 R _ 0 4

5 6 0 u_ 2 . 5 V _ 6. 6 * 6. 6 * 5. 9

1 . 5V

B - 10 DDR3 SO-DIMM_0

C3 7

C8 6

C6 8

C 82

C 48

C 49

C 51

C5 0

C5 2

C4 7

0 . 1u _ 1 0 V _X 5 R _ 0 4

0. 1u _ 1 0V _X 5 R _ 0 4

0. 1 u _ 10 V _ X 5 R _ 0 4

0 . 1 u _ 10 V _ X 5 R _ 0 4

0 . 1 u _1 0 V _ X 5R _ 04

0 . 1 u _1 0 V _ X 5R _ 04

0 . 1 u_ 1 0 V _ X5 R _0 4

0 . 1 u_ 1 0 V _ X5 R _0 4

0 . 1u _ 1 0 V _X 5 R _ 0 4

0 . 1u _ 1 0V _X 5 R _ 0 4

3 , 6 , 8, 10 , 2 0 , 2 7, 3 2 , 3 4 1. 5 V
1 0 , 3 4 V T T_ M E M
3 , 1 0, 1 1 , 1 2 , 13 , 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 2 0, 23 , 2 4 , 25 , 2 6 , 2 8, 29 , 3 0 , 3 1, 3 2 , 3 7 3. 3 V S
1 9, 3 0 , 3 2 1. 5 V S

Schematic Diagrams

DDR3 SO-DIMM_1
4

M _B _ B [1 5 : 0 ]

_B _ B 0
_B _ B 1
_B _ B 2
_B _ B 3
_B _ B 4
_B _ B 5
_B _ B 6
_B _ B 7
_B _ B 8
_B _ B 9
_B _ B 1 0
_B _ B 1 1
_B _ B 1 2
_B _ B 1 3
_B _ B 1 4
_B _ B 1 5

0
#0
1
#1

S A 0 _D I M1
S A 1 _D I M1

98
97
96
95
92
91
90
86
89
85
1 07
84
83
1 19
80
78
1 09
1 08
79
1 14
1 21
1 01
1 03
1 02
1 04
73
74
1 15
1 10
1 13
1 97
2 01
2 02
2 00
1 16
1 20

4 M_ B _ OD T 0
4 M_ B _ OD T 1

11
28
46
63
1 36
1 53
1 70
1 87
4

M_ B _ D Q S [ 7 : 0 ]

4 M_ B _ D QS # [ 7 : 0 ]

M
M
M
M
M
M
M
M

_B _ D
_B _ D
_B _ D
_B _ D
_B _ D
_B _ D
_B _ D
_B _ D

QS 0
QS 1
QS 2
QS 3
QS 4
QS 5
QS 6
QS 7

12
29
47
64
1 37
1 54
1 71
1 88

M
M
M
M
M
M
M
M

_B _ D
_B _ D
_B _ D
_B _ D
_B _ D
_B _ D
_B _ D
_B _ D

QS # 0
QS # 1
QS # 2
QS # 3
QS # 4
QS # 5
QS # 6
QS # 7

10
27
45
62
1 35
1 52
1 69
1 86

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

0
1
2
3
4
5
6
7
8
9
10 / A P
11
12 / B C #
13
14
15

B A0
B A1
B A2
S 0#
S 1#
C K0
C K0 #
C K1
C K1 #
C KE0
C KE1
C AS#
R AS#
W E#
S A0
S A1
S CL
S DA
O DT 0
O DT 1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

M0
M1
M2
M3
M4
M5
M6
M7
QS 0
QS 1
QS 2
QS 3
QS 4
QS 5
QS 6
QS 7
QS 0 #
QS 1 #
QS 2 #
QS 3 #
QS 4 #
QS 5 #
QS 6 #
QS 7 #

DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
D Q1 0
D Q1 1
D Q1 2
D Q1 3
D Q1 4
D Q1 5
D Q1 6
D Q1 7
D Q1 8
D Q1 9
D Q2 0
D Q2 1
D Q2 2
D Q2 3
D Q2 4
D Q2 5
D Q2 6
D Q2 7
D Q2 8
D Q2 9
D Q3 0
D Q3 1
D Q3 2
D Q3 3
D Q3 4
D Q3 5
D Q3 6
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
D Q4 2
D Q4 3
D Q4 4
D Q4 5
D Q4 6
D Q4 7
D Q4 8
D Q4 9
D Q5 0
D Q5 1
D Q5 2
D Q5 3
D Q5 4
D Q5 5
D Q5 6
D Q5 7
D Q5 8
D Q5 9
D Q6 0
D Q6 1
D Q6 2
D Q6 3

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
1 29
1 31
1 41
1 43
1 30
1 32
1 40
1 42
1 47
1 49
1 57
1 59
1 46
1 48
1 58
1 60
1 63
1 65
1 75
1 77
1 64
1 66
1 74
1 76
1 81
1 83
1 91
1 93
1 80
1 82
1 92
1 94

M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

M _ B _ D Q[ 6 3 : 0 ] 4

J D I MM 1B
1 .5 V

75
76
81
82
87
88
93
94
99
10 0
10 5
10 6
11 1
11 2
11 7
11 8
12 3
12 4

3 .3 V S

2 0 mi ls
C 41 6

C 4 15

1 u _6 . 3 V _ Y 5 V _ 0 4

0 .1 u _1 6 V _ Y 5 V _ 0 4
2 , 9 TS # _ D I M M0 _ 1
3 , 9 D D R3 _D R A MRS T#

C 26
C 25

1 u_ 6 . 3 V _ X5 R _0 4
0 . 1u _ 1 0V _X 5 R _ 0 4

19 9
77
12 2
12 5
19 8
30

1
12 6

8 M V R E F _D Q_ D I MM B
R4 2

CLOS E TO SO-DIMM_ 1
R9 7

1. 5V

1K _ 1 % _ 04

MV R E F _ D IM 1

D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8

V D DS P D
N C1
N C2
N CT E ST
EVEN T#
R ESET#

V R EF _ DQ
V R EF _ CA

*0 _ 0 4

M V R E F _D I M1
C8 9
C8 8

VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD

1 u _ 6. 3V _ X 5 R _ 0 4
0 . 1 u _ 10 V _ X 5R _ 04

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

SS1 6
SS1 7
SS1 8
SS1 9
SS2 0
SS2 1
SS2 2
SS2 3
SS2 4
SS2 5
SS2 6
SS2 7
SS2 8
SS2 9
SS3 0
SS3 1
SS3 2
SS3 3
SS3 4
SS3 5
SS3 6
SS3 7
SS3 8
SS3 9
SS4 0
SS4 1
SS4 2
SS4 3
SS4 4
SS4 5
SS4 6
SS4 7
SS4 8
SS4 9
SS5 0
SS5 1
SS5 2

44
48
49
54
55
60
61
65
66
71
72
12 7
12 8
13 3
13 4
13 8
13 9
14 4
14 5
15 0
15 1
15 5
15 6
16 1
16 2
16 7
16 8
17 2
17 3
17 8
17 9
18 4
18 5
18 9
19 0
19 5
19 6

Sheet 10 of 46
DDR3 SO-DIMM_1
V T T _ ME M

VTT1
VTT2
G1
G2

20 3
20 4
GN D 1
GN D 2

D D R S K -2 0 40 1 -T R 9 D
R9 8
1K _1 % _ 04

D D R S K -2 0 4 01 -T R9 D

? ? ? DIMM SLOT? ?

La yout Note :
SO -D IMM_1 is pla ce d fa rthe r from the GMCH tha n SO -DI MM_0
V T T _ ME M

C1 1 0

C 1 09

C 10 7

C1 0 8

C 1 12

1u _ 6 . 3 V _X 5 R _ 0 4

1 u _ 6. 3V _ X 5 R _ 0 4

1 u _6 . 3 V _ X 5R _ 04

1 u_ 6 . 3 V _ X5 R_ 0 4

1 0 u _6 . 3 V _ X 5R _ 06

C3 7 9

C 78

C 38 0

C4 4

C 83

C 76

C3 9

C7 3

10 u _ 1 0V _ Y 5V _ 0 8

1 0 u _1 0 V _ Y 5 V _ 0 8

1 0 u_ 1 0 V _ Y 5 V _ 08

1 u_ 6 . 3 V _ X5 R_ 0 4

1 u _ 6. 3V _ X 5 R_ 0 4

1 u _6 .3 V _ X 5R _ 04

1 u_ 6 . 3 V _ X5 R _0 4

1u _ 6 . 3V _ X 5 R _ 0 4

C4 5

C 42

C 41

C8 1

C 36

C 85

C3 5

C3 8

C 75

C4 3

0. 1u _ 1 0V _ X 5 R_ 0 4

0 . 1 u _ 10 V _ X 5R _ 04

0 . 1 u_ 1 0 V _ X5 R _0 4

0 . 1u _ 1 0V _X 5 R _ 0 4

0 . 1 u _ 10 V _ X 5R _ 04

0 .1 u_ 1 0 V _ X5 R _0 4

0 . 1u _ 1 0V _X 5 R _ 0 4

0. 1 u _ 10 V _ X 5 R _ 04

0 . 1 u _1 0 V _ X5 R _0 4

0 . 1u _ 1 0V _X 5 R_ 0 4

1 .5 V

19 ,3 0 ,3 2
3 , 6,8 , 9 , 2 0 , 27 ,3 2 ,3 4
9 ,3 4
3 , 9 , 1 1,1 2 ,1 3, 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 ,2 0 ,23 , 2 4 , 25 , 2 6 , 2 8, 2 9 , 3 0 , 31 ,3 2 ,3 7

1 .5 VS
1 .5 V
V TT _ ME M
3 .3 VS

1. 5V

DDR3 SO-DIMM_1 B - 11

B.Schematic Diagrams

4 M_ B _ B S 0
4 M_ B _ B S 1
4 M_ B _ B S 2
4 M_ B _ CS #0
4 M_ B _ CS #1
4 M _ B _C L K _ DD R
4 M _ B _C L K _ DD R
4 M _ B _C L K _ DD R
4 M _ B _C L K _ DD R
4 M_ B _ CK E 0
4 M_ B _ CK E 1
4 M _B _C A S #
4 M _B _R A S #
4 M _B _W E #
9 S A 0 _ D IM 1
9 S A 1 _ D IM 1
9 , 14 S M B _ C L K
9, 14 S M B _ DA T A

JD I MM 1 A
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

Schematic Diagrams

LVDS, Inverter
3 . 3V S

PANEL CONNECTOR
30Pin

1 M_ 0 4

L V D S -L 1 N
L V D S -L 1 P
L V D S -L 0 N
L V D S -L 0 P

1 00 K _ 0 4

C5 8 7

B o ard ID

L V D S -L 2 N
L V D S -L 2 P

PLVDD
HI LVDS:3.3V 3A
HI eDP:3.3V 3A
LOW eDP;5V 3A

13

1229 D02(W240HU)
P LV D D

1A
3A

3 .3 VS

R 5 79
3 . 3V S

Q4 3
* A O3 4 1 5
S
D

R5 8 0

8 72 1 6 -30 0 6

C 5 18

C 51 9

C5 2 0
R 5 81

4 . 7 u_ 2 5 V _X 5 R _ 0 8
0 . 1 u _1 6 V _ Y 5 V _ 04
0 .1u _ 1 6V _ Y 5 V _ 0 4

NB _ E N A V DD

0 _0 6

5V S

*1 0 0K _ 0 4

>100 mil

P LV D D _ S E L

16
16

L V D S -LC LK N
L V D S -LC LK P

16
16

LV D S -L 1N
LV D S -L 1P

16
16

L V D S -L0 N
LV D S -L 0P

16
16

LV D S -U C LK N
LV D S -U C LK P

L V D S -L C L K N
L V D S -L C L K P
L V D S -L 1 N
L V D S -L 1 P
L V D S -L 0 N
L V D S -L 0 P

M U X _ 1N
M U X _ 1P

G1

W243 1117 ? ? 3.2

S

D

>100mil
C5 4 2

C 5 43

C 54 5

R5 7 7

1 00 K _ 0 4

B R IGH TN E S S 2 8
1230 D02

L V D S -L 2 N
L V D S -L 2 P

Q 49
M T N 7 00 2 Z H S 3

G

L V D S -L 2 N 1 6
L V D S -L 2 P 1 6
3 . 3V S

E MB _ H P D

1A

1228 D02

E M B _H P D 2

P LV D D

3A
MU X_ 2 N
MU X_ 2 P
MU X_ 0 N
MU X_ 0 P

? 4 0p in con ne cto r? , ? ? 30p in con ne cto r? ? ? ? p in pad ? ? ? ?

16
16
16
16
16
16

L V D S -U 2N
L V D S -U 2 P
L V D S -U 1 N
L V D S -U 1 P
L V D S -U 0N
L V D S -U 0 P

2
2
2
2
2
2

D P _ TX N 1
DP _ T X P 1
D P _ TX N 0
DP _ T X P 0
D P _ A UX N
D P _ A U XP

R N1 2 8
7
6
5
R N1 3 8
7
6
5
R N1 4 8
7
6
5
R N1 5 8
7
6
5

1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4

0 _8 P 4 R _ 0 4

0 _8 P 4 R _ 0 4

MU
MU
MU
MU
MU
MU

X_ 2 N
X_ 2 P
X_ 1 N
X_ 1 P
X_ 0 N
X_ 0 P

*0 _ 8P 4 R _0 4
D P _T X P 2 2
D P _ TX N 2 2
*0 _ 8P 4 R _0 4

D P _T X P 3 2
D P _ TX N 3 2

INVERTER CONNECTOR

3 . 3V
3 .3 V

B LO N

1

BL O N

2

3

14

B K L_ E N

4

U 1 6B
74 L V C 0 8 P W

C2 1 4
*0 . 1 u _1 0 V _ Y 5 V _ 04

6
5

1 0 0K _ 0 4

14

R2 6 7

7

B K L_ E N

U1 6 A
74 L V C 0 8 P W

7

28
16

3 .3 V

*1 0 0 K _0 4
14

R2 6 8

8
3 .3 V

11/18
R2 8 1

0_ 0 4

IN V _ B L ON

10

*1 00 K _ 0 4
14

R 26 6

12
28 ,3 1 LID _ S W #

U 1 6D
74 L V C 0 8 P W
11

13
7

15 , 2 8 , 37 A L L _S Y S _ P W R G D

B - 12 LVDS, Inverter

U 16 C
7 4 LV C 0 8P W

9

S B _ B L ON

7

18

R 6 08

Q4 2
MT N 7 0 02 Z H S 3

G
R3 7 0

P _ DD C_ DA T A 1 6
P _ DD C_ CL K 1 6

B RIG HT NE S S
B o ard I D _R
I N V _ B L ON

P LV D D

3A

S

P L V DD_ S E L

2

S
1

4

1.5 M_ 0 4
3 3 0 K _0 4

1 6, 28 N B _E N A V D D
P _ DD C_ DA T A
P _ DD C_ CL K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

G2

D

G
V L E D_ E N #

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

G1

Q 51 B
* MT D N 7 0 0 2Z H S 6 R
G

R 2 44
1228 D02
R 57 8

J _ LC D 1
* 87 2 16 -4 0 06

2A
Q 51 A
*M TD N 7 0 02 Z H S 6R

G2

3

Q4 5
* A O3 4 1 5
S
D

>100 mil

V LE D

D02A
R6 4 6
*2 0 0 _0 6

S

*0 . 1 u _1 6 V _ Y 5 V _ 04

G

R7 2 1
*1 0 K _ 04

6

5 VS
Q4 4
*M TN 70 0 2 Z H S 3

G

40Pin

D

C 54 4

D
3 .3V

VL ED

5

Q4 1
A O3 4 15
S
D

3A

>100 mil

*1 00 K _ 0 4

S

Sheet 11 of 46
LVDS, Inverter

PLVDD_SEL
HI ? 5V 3A
LOW ? 3.3V 3A

3 .3 VS
E MB _ H P D

G

*0 . 1 u_ 5 0V _Y 5V _ 0 6

Q5 3
2 N 7 0 02 W
G

*0 _ 0 4

D

D

D02A R3.3A_2_18.DSN

B R IG H T N E S S
B o ard ID _R R 7 2 0
I N V _ B L ON

R 2 80

C2 1 3

1 M _0 4

0 . 1 u_ 1 6V _ Y 5V _ 0 4

1 0 0 _1 % _ 04

R6 0 7

L V D S -L C L K N
L V D S -L C L K P

P _ DDC _ DA T A
P _ DDC _ CL K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

* 10 0 K _0 4

0. 1 u _5 0 V _ Y 5V _0 6

C 8 1 2 0 .2 2u _ 50 V _ Y 5 V _ 0 6

C 5 17

4

* 0. 1 u _5 0 V _ Y 5 V _ 06
P 2 0 0 3E V G

3
2
1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

* 10 u _ 10 V _ Y 5 V _0 8

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

P L V D D _S E L
8
7
6
5

2.2 K _ 0 4

0. 1 u _1 6 V _ Y 5 V _0 4

2A

.

Q4 7

B.Schematic Diagrams

30Pin & 40 Pin Co-layout--LED
PANEL.

R9

2 . 2K _ 0 4

J_ L C D 2

0. 1u _ 16 V _ Y 5 V _ 04

2A
C 8 13

R 72 7

R 10

V LE D
L2
* H C B 16 0 8K F -12 1 T2 5

G

V IN

S

VIN

12 ,1 9, 20 , 2 6,3 0 ,3 1, 3 2 , 3 7,3 8
31 ,3 2, 33 , 3 4,3 5 ,3 6, 3 7 , 3 8,3 9
2 , 3 , 8 , 13 , 1 5 ,17 , 1 9 , 20 ,2 2, 23 , 2 7,2 9 ,3 1, 3 2 , 3 4,3 6
3, 9 , 1 0 , 12 ,1 3 , 14 , 1 5 , 16 , 1 7 , 18 , 1 9 ,20 , 2 3 , 24 ,2 5, 26 , 2 8,2 9 ,3 0, 3 1 , 3 2,3 7
3 2 , 3 3,3 5

5 VS
VIN
3 . 3V
3 . 3V S
SYS1 5 V

Schematic Diagrams

HDMI, CRT

48
47

16 H D MI B _ C LK B P
16 H D MI B _ C LK B N

25

* 4. 7K _ 04
* 0_0 4

? ? ?

4 . 02 K_ 1% _04

P C0
P C1
RE X T

34
35

* 4. 7K _ 04
* 4. 7K _ 04

V C C [ 1]
V C C [ 2]
V C C [ 3]
V C C [ 4]
V C C [ 5]
V C C [ 6]
V C C [ 7]
V C C [ 8]

OE _ 1
QE _ 2

49
GN D

28
29

H D MI B _E XT 1_ SC L
H D MI B _E XT 1_ SD A

30

H D MI _H P D -C

2
11
15
21
26
33
40
46

4. 7K _ 04

D C C _E N #

4. 7K _ 04

PC 0

R 3 95
? ? ?

*4. 7 K_ 04

PC 1

10 u_ 10 V_ Y 5V _ 08

1 0u _10 V _Y 5 V_ 08

19
+ 5V
16
14

C 33 8

C 33 9

0. 1u _1 6V _Y 5 V _0 4

0. 1 u_1 6V _ Y 5V _0 4

12

TMD S _ C LOC K #

A

A

C

C

AC

RD1

10

S CL
R ES E R V ED
C L K S H I E LD
TMD S D A TA 0-

C 31

C 34 0

0. 1u _1 6V _Y 5 V _0 4

0. 1 u_1 6V _ Y 5V _0 4

2

S H I EL D 1

T MD S D AT A 1+
TMD S D A TA 2S H I E LD 2
T MD S D A T A2 +

C 30
R 64
H D MI B _C LOC K P

H D MI B _D AT A1 N

*0 _0 4

4
3
L9
1
2
*W C M20 12F 2 S-S H OR T
R 65
*0 _0 4
R 66
*0 _0 4

T MD S_ C LOC K

4
3
L1 1
1
2
*W C M20 12F 2 S-S H OR T

T MD S_ D A TA 1

R 67

H D M I_ C E C
R 70

9

T MD S _D A TA 0#

7

T MD S _D A TA 0

T MD S D A T A0 +
T MD S D AT A 1-

4

H D MI B_ E XT1 _S C L

11

T MD S C LOC K +

6

TMD S _ D AT A 1

15
13

CE C
T MD S C LOC K -

S H I E LD 0
TMD S _ D AT A 1#

H D MI _H P D -C

17
D D C C/ E C GN D

S DA

8

H D MI B _D AT A1 P

3

T MD S _D A TA 2#

1

T MD S _D A TA 2

*0 _0 4

4
3
L10
1
2
*WC M2 01 2F 2S -S H OR T
R 69
*0 _0 4
R 72
*0 _0 4
4
3
L12
1
2
*WC M2 01 2F 2S -S H OR T
R 71
*0 _0 4

5

H D MI B_ D AT A 0N
H D MI B _D A TA 0P

H D MI B_ D AT A 2N
H D MI B _D A TA 2P

Sheet 12 of 46
HDMI, CRT

C 1 28 17 -11 9A 5-L

T MD S_ C LOC K #

T MD S_ D A TA 1#

*0 _0 4

5V S
J _C R T 1
1 08 A H 15 FS T0 4A 1 C C

6-19-31001-264
R ED

1
2
3
4

CRT PORT

RD2

H D MI _H P D -C

H OT PL U G D E TE C T

18

0. 1u _1 6V _Y 5 V _0 4

3. 3 VS

C 3 49

10 0K _0 4

PS8101 (6-03-08101-032) PIN TO PIN

R5 2

C 34 8

H D MI B _E XT 1_ SD A
R5 5

H D MI B _C LOC K N

6- 20-14X30-015
10/29

1
9

C 3 11

0. 2 2u _1 0V _Y 5V _ 04

C 312

0 . 22 u_1 0V _ Y5 V _04

C 31 3

0. 22 u_ 10 V_ Y 5V _0 4

8

BYP

GN D

3

B LU E

4

GR N

5

RE D

1 0p _50 V _N P O _0 4
C1 9

10 p_ 50 V_ N PO _04

10p _5 0V _N P O _ 04
C 18

C 14

2 2p _50 V _N P O _0 4

22 p_ 50 V_ N P O _0 4
C 20

2 2p _5 0V _N P O _ 04

10 p_ 50 V_ N PO _04

V SY N C

1 0p_ 50 V _N P O _0 4

33 _0 4

11
4
5

6

TP D 7S 01 9

12

D D C D A TA

13

HS Y NC

14

V SY N C

15

D D C LK

6
7
8
C 7 1 00 0p _5 0V _X 7 R _04

VI D E O_3

R 3 73

1207

241 0 mi l

3

C 9 22 0p _5 0V _N P O _ 04

VI D E O_2

V C C _D D C

HS Y NC

GR N
BL U E

C 1 1 2 20 p_ 50V _ N PO _ 04

VI D E O_1

V C C _V I D E O
7

3 . 3V S

33 _0 4

2

F C M1 005 MF -600 T0 1
F C M1 005 MF -600 T0 1
F C M1 005 MF -600 T0 1

C 15 10 00p _5 0V _X 7 R _0 4

V C C _S Y N C

2
3 3. V S

C R T_ VS Y N C

R 3 72

C1 6

SY N C _ OU T2

16

C R T_ H SY N C

L8
L5
L3

GND1
GND2

1

5 VS

S Y N C _I N 2

14

F C M1 005 MF -600 T0 1
F C M1 005 MF -600 T0 1
F C M1 005 MF -600 T0 1

C 12

1 6 D A C _V S Y N C

D D C _ OU T2
SY N C _ OU T1

C 21

15

S Y N C _I N 1

D D C LK

C1 7

D D C _ IN 2
13

1 6 D A C _H S Y N C

D D C D A TA

12

D D C _ OU T1

15 0_1 %_ 04

D D C _ IN 1
11

1 6 D A C _D D C A C L K

9

1 0p _5 0V _N P O _ 04

1 6 D A C _D D C A D A TA

U 33

C1 3

10

L7
L6
L4

16 D A C _R E D
16 D A C _GR EE N
16 D A C _B L U E

8
7
6
5

R N1
2. 2 K_ 8P 4R _ 04

15 0_ 1% _04

R5 4

RD3

* BA V 99 R EC T I FI E R
*B A V 99 R EC T I FI E R
*B A V9 9 R E C TI F I E R

H D MI B_ E XT 1_S C L

TMD S _ C LOC K

S N 75 D P1 39
P I N 49 = GN D

3 . 3V S

1 _0 4

3 . 3V S

1
5
12
18
24
27
31
36
37
43

GN D [ 1]
GN D [ 2]
GN D [ 3]
GN D [ 4]
GN D [ 5]
GN D [ 6]
GN D [ 7]
GN D [ 8]
GN D [ 9]
GN D 1[ 0]

? ? ?

H D MI B _C L OC KP
H D MI B _C L OC KN

5V S _H D MI _ I N R 40 1

H D MI B_ E XT 1_S D A

R 13

R5 3
R5 1

H PD _ S IN K

OE #

13
14

1_0 4

J _H D MI 1

1 50 _1% _0 4

3. 3V S

R 39 6

HP D

H D MI B _D A TA 0 P
H D MI B _D A TA 0 N

R 14

10/28

S C L_ S IN K
S D A_ S IN K

DCC_ E N#
R T _E N #

3
4
6

P C0
P C1

OU T _D 4 +
OU T_ D 4-

H D MI B _D A TA 1 P
H D MI B _D A TA 1 N

16
17

R 40 0

3 , 9, 1 0, 11 , 13 1, 4, 1 5, 16 , 17 , 18, 1 9, 2 0, 23 , 24 ,2 5, 2 6, 28 , 29 , 30, 3 1, 3 2, 37 3. 3V S
11 1, 9, 2 0, 26 , 30 , 31, 3 2, 3 7, 38 5V S

HDMI, CRT B - 13

B.Schematic Diagrams

32
10

D C C _ EN #

I N _ D 4+
I N _ D 4-

19
20

5 VS

R1 5

R 61
R 68

3 .3 V S

OU T _D 3 +
OU T_ D 3-

H D MI B _D A TA 2 P
H D MI B _D A TA 2 N

.
.
.

P OR T C _H P D

OU T _D 2 +
OU T_ D 2-

I N _ D 3+
I N _ D 3-

S CL
S DA

*1 0m li _0 4 M_ P OR TB _H P D # _R 7

R 39 8

I N _ D 2+
I N _ D 2-

22
23

.
.
.

16

9
8

H D MI_ C TR L C LK
H D MI_ C TR L D A TA

1 6 H D MI _C T R LC L K
16 H D MI_ C TR L D A TA

OU T _D 1 +
OU T_ D 1-

For ESD

GN D 1
GN D 2 GND
GN D 3 GND
G ND4 GND
GND

45
44

16 H D MI B _ D 0B P
16 H D MI B _ D 0B N

5V S _H D MI

I N _ D 1+
I N _ D 1-

2. 2K _ 04

42
41

16 H D MI B _ D 1B P
16 H D MI B _ D 1B N

2 2. K _0 4

U5
39
38

16 H D MI B _ D 2B P
16 H D MI B _ D 2B N

R 4 04

A

R 40 3

AC

FOR INTEL GRAPHIC

C

5V S _H D MI

AC

HDMI PORT

Schematic Diagrams

PCH/ HDA, JTAG. SATA
RT C V CC

C4 6 8
1 8 p _5 0 V _ N P O _ 04

R TC CL EA R
1

C4 6 5
J_ R TC 1

1 u _6 . 3 V _ X5 R _0 6

*O P E N _ 1 0m i l -1 MM

R T C_ V BA T 1
2

1
2

Zo= 50O? 5 %

R2 3 7
2 0K _1 % _ 04
R 2 36

2

1 M _0 4

C2 0 6
1 u _6 . 3 V _ X5 R _0 6

R2 3 5

RT CVC C

33 0 K _ 04

R T C _X 1

A2 0

RT C_ X 2

C2 0

R T C _R S T #

D2 0

S R T C _R S T #

G2 2

S M_ I N TR U D E R #

K2 2

P CH _ INT V RM E N

NO REBOOT STRAP

30
HD A _ S P K R

SP I_ SI

R2 6 9

3. 3 A _ 1 . 5 A _H D A _I O

28

K3 4

H DA_ SD IN0

R B 7 5 1 S -4 0C 2
A

* 2 8m i l _0 6

27

HIGH = Enable
LOW = Disable

C

D 12
H D A _ S D OU T_ R

R 53 9

U S B 3 0 _S M I #

BIOS ROM
U 17
8

R2 9 4
3. 3 K _ 1 % _0 4
S P I _W P #

VD D

SI

W P#

CE #

5

SP I_ SI

2

SP I_ SO

1

S P I_ CS 0 #

R444 R176 R177 R178 R441 RN16

SO

6

R2 9 1
3. 3 K _ 1 % _0 4
S P I _H OL D # 7

GP I O 21

R1 8 3

10 K _ 0 4

*1 0 K _0 4

C3 6

0_ 0 4

N3 2

H D A _ D O C K _ E N # / GP I O 33

S A TA 4 R XN
S A T A 4 RX P
S A T A 4 T XN
S A TA 4T X P

H D A _ D O C K _ R S T# / G P I O1 3

P C H _J T A G_ T C K _B U F

J3

P C H _J T A G_ T MS

H7

P C H _J T A G_ T D I

K5

J T A G_ T C K

S A TA 5 R XN
S A T A 5 RX P
S A T A 5 T XN
S A TA 5T X P

J T A G_ T MS

S A T A I C O MP O

P C H _J T A G_ T D O

H1

J T A G_ T D O

3. 3 V S
1 0 K _0 4
R 2 29
*1 0K _0 4

S ER IRQ
AM 3
AM 1
AP7
AP5

S A T A R XN 0
S A T A R XP 0
S AT AT XN0
SAT AT XP0

2 3, 2 8
26
26
26
26

B o ard I D

AD
AD
AH
AH

7
5
5
4

SATA HDD

S A T A R XN 2 26
S A T A R XP 2 2 6
S A T A T X N2 2 6
S A T A T X P 2 26

SATA ODD

AB8
AB1 0
AF3
AF1
Y 7
Y 5
AD 3
AD 1
Y 3
Y 1
AB3
AB1
S A TA I C O MP

R 1 72

3 7 . 4 _ 1% _ 0 4

S A TA 3C OM P

R 1 71

4 9 . 9 _ 1% _ 0 4

R 4 32

7 5 0 _1 % _ 0 4

1 .0 5 VS

Y 10
S A T A I C OM P I
AB1 2
S A T A 3 R C O MP O

1 .0 5 VS

AB1 3

SP I_ SCL K

W243HWQ

X

X

X

X

X

O

W243HVQ

O

O

O

O

O

X

T3

S PI_ SC L K

R 44 4

0_ 0 4

S P I _S C L K _ R

S PI_ C S0 #

R 17 6

0_ 0 4

S P I _C S 0 # _R

Y1 4

S PI_ C S1 #

R 17 7

0_ 0 4

S P I _C S 1 # _R

T1

S PI_ SI

R 17 8

0_ 0 4

S P I _S I _R

V4

S PI_ SO

R 44 1

S P I _S O_ R

U3

3 3 _0 4

S P I _ C LK

S AT A3 R B IA S

AH 1

RB IAS _ S AT A3

P3

S A T A _ L E D#

V1 4

GP I O2 1

S P I _ C S 0#
S P I _ C S 1#

S P I _ M OS I

S AT AL ED#
S A T A 0 GP / G P I O2 1

S A T A _L E D # 29

P1
S PI_ M ISO

S A T A 1 GP / G P I O1 9

BBS_ BIT 0 1 7

S CK
4
HO L D#

VSS

C o ug a rP o in t _ R e v _ 1 p 0

M X2 5 L 32 0 6 E
P C B F o o t pri n t = M-S O P 8 B

W243HVQ

11/18

3. 3 V _ M

V DD3

H D A _S D OU T _R
H D A _S Y N C _ R
H D A _R S T #_ R
H D A _B I TC LK _R

NC4
NC_ 0 4

C2 2 6
0. 1 u _ 16 V _ Y 5V _ 0 4
U 18
3 .3 VS _ S PI

32Mbit

8
VD D

R2 9 5
3. 3 K _ 1 % _0 4
S P I _W P #

5

SP I_ SI

2

SP I_ SO

1

S P I_ CS 1 #

6

SP I_ SCL K

SI

R 21 8

R 22 3

2 1 0_ 1 % _0 6

2 1 0_ 1 % _0 6

2 1 0_ 1 % _ 06

W P#

5
6
7
8

3 3_ 8 P 4 R _ 0 4
RN 1 8

P C H _ J T A G_ T MS
P C H _ J T A G_ T D I
P C H _ J T A G_ T D O

SO
3

R2 9 6
3. 3 K _ 1 % _0 4
S P I _H OL D # 7

11/19

CE #

H D A _ S D OU T 3 0
HD A _ S YN C 3 0
H D A _R S T # 30
H DA _ B IT CL K 3 0
1 5 , 19 , 2 5 , 2 6, 3 2 3 . 3 V _M
2 0 3 . 3A _1 . 5 A _ H D A _I O
1 5 ,2 0 R T CV C C
1 1 , 1 2, 1 9 , 2 0 , 26 , 3 0 , 31 , 3 2 , 3 7, 3 8 5 V S
1 4 , 15 , 1 7 , 18 , 2 0 , 2 2, 2 3 , 2 4 , 25 , 2 8 , 32 , 3 3 , 3 5, 3 9 V D D 3
2 , 3 , 8 , 11 , 1 5 , 17 , 1 9 , 2 0, 2 2 , 2 3 , 27 , 2 9 , 31 , 3 2 , 3 4, 3 6 3 . 3 V
3 , 9 , 10 , 1 1 , 1 2, 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 6 , 28 , 2 9 , 30 , 3 1 , 3 2, 3 7 3 . 3 V S
1 4 , 15 , 1 9 , 2 0, 3 2 1 . 0 5V S

S CK
4
HO L D#

VSS

M X2 5 L 32 0 6 E
P C B F oo t p ri nt = M -S OP 8 B

W243HVQ
11/19

B - 14 PCH/ HDA, JTAG. SATA

R2 3 8

4
3
2
1

R4 5 9
10 0 _ 1% _ 0 4

R 4 58

R 21 1
1 0 0_ 1 % _0 4

5 1 _0 4

R 20 9
1 0 0_ 1 % _ 04

P C H _ J T A G_ T C K _ B U F

S P I _ S C LK _R
SP I_ SI_ R
S P I _ S O _R
S P I _ C S 0# _ R

RN 1 6
*0 _ 8 P 4 R _ 04
8
1
7
2
6
3
5
4

11

A M 10
AM 8
AP1 1
AP1 0

Y 11
J T A G_ T D I

R2 3 0

L P C _ F R A ME # 2 3 , 2 8
B oa rd I D

S A T A 3C OM P I

32Mbit

3

A3 6

S A TA 3 R XN
S A T A 3 RX P
S A T A 3 T XN
S A TA 3T X P

11/19

SPI_* = 1.5"~6.5"

3 .3 VS _ S PI

S A TA 1 R XN
S A T A 1 RX P
S A T A 1 T XN
S A TA 1T X P
S A TA 2 R XN
S A T A 2 RX P
S A T A 2 T XN
S A TA 2T X P

H DA _ S DI N1

1201

11/18

C 22 1
0 . 1 u_ 1 6 V _ Y 5 V _ 04

H DA _ RS T #

S A TA 0 R XN
S A T A 0 RX P
S A T A 0 T XN
S A TA 0T X P

H DA _ S DO
R 53 8

Flash Descriptor
Security Overide
Low = Disabled-(Default)
High = Enabled

NC_ 0 4

SPKR

A3 4

Flash Descriptor Security Overide

NC1

H DA _ S Y N C

H DA _ S DI N3

R 4 68

M E_ W E

10 K _ 0 4

V5

H DA _ B CL K

H DA _ S DI N2

E3 6
K3 6

S E R IRQ

H DA _ S DI N0

10/29

*1 K _ 0 4

R1 6 8

L P C _ A D 0 2 3, 2 8
L P C _ A D 1 2 3, 2 8
L P C _ A D 2 2 3, 2 8
L P C _ A D 3 2 3, 2 8

D 36

G3 4

W243 1117

3. 3V

3. 3 V _ M

L AD0
L AD1
L AD2
L AD3

L D R Q0 #
LD R Q 1# / G P I O2 3

C3 4

TP M FU NC TI ON :SP I_ SI H ig h Ena bl e

HDA_SDOUT

I N TV R ME N

N3 4

T1 0

HD A _ S DIN 1

*1 K _ 04

C1 7

L3 4

iTPM ENABLE/DISABLE
R 16 7

/
/
/
/

E3 4
30

3. 3 V S

0
1
2
3

C 38
A3 8
B3 7
C 37

F W H 4 / L F R A ME #
I N TR U D E R #

H DA_ SP KR
H D A _ R S T# _ R

FW H
FW H
FW H
FW H

S R TC R S T #

H D A _ S Y N C _R

NO R EB OO T ST RAP : HD A_ SP KR Hi gh E na bl e

Sheet 13 of 46
PCH/ HDA, JTAG.
SATA

R TC R S T #

IHDA

*1 K _ 04

1K _ 0 4

H DA_ SP KR

R TC X 2

SATA

R 19 5

R2 2 4

3 . 3A _1 . 5 A _ H D A _ I O

R TC X 1

JTAG

B.Schematic Diagrams

H DA_ BIT CL K _ R
3. 3 V S

*1 0 K _0 4

S E RIR Q

U3 7 A
10 M _0 4

85 2 0 5- 02 7 0 1
1

S A T A _L E D # R 4 4 5

R4 7 8

C4 6 3
1 8 p _5 0 V _ N P O _ 04

SPI

10mil
J_RTC1

3 .3 V S

X1 2

X1 3
MC -3 06 _ 3 2. 7 6 8 K H z

JO P E N 1

LPC

11/ 05

1 K_ 0 4

SATA 6G

R4 7 7
2 0K _1 % _ 04

2
1

1 u_ 6 . 3 V _ X5 R _0 6

*3 2 . 7 68 K H z

C 4 66

2
1

R 47 6

CougarPoint - M
(HDA,JTAG,SATA)

20mil

3
4

R T C_ V B A T _ 1

3
4

VDD 3

RTC

D 17
B A T5 4 C S 3
1 A
C 3
2 A

20mil

H S P I_ S CL K 2 8
H S P I _ MS I 2 8
H S P I _ MS O 2 8
H SP I_ CE# 2 8

Schematic Diagrams

PCH/ PCI-E, SMBUS, CLK
11/19

CougarPoint - M (PCI-E,SMBUS,CLK)

SM
SM
SM
SM

U 3 7B

BF 3 6
BE3 6
AY3 4
BB3 4

11/19

25
25
25
25

P C I E _ R X N 6_ I G L A N
P C I E _ R X P 6 _ I GL A N
P C I E _ T XN 6 _I GL A N
P C I E _T X P 6 _ I GL A N

PCI-E
Lane
Lane
Lane
Lane
Lane
Lane
Lane
Lane

x1
1
2
3
4
5
6
7
8

C1 7 2
C1 7 5

0 . 1 u_ 1 0 V _ X 7R _ 0 4
0 . 1 u_ 1 0 V _ X 7R _ 0 4

P C I E _T X N 6_ C
P C I E _T X P 6 _ C

B J3 8
B G3 8
AU3 6
AV3 6
B G4 0
B J4 0
AY4 0
BB4 0

Usage
X
USB3.0
WLAN
CARD READER
X
GLAN INTEL 82579
X
X

BE3 8
BC3 8
AW 3 8
AY3 8

E RN 4
E RP 4
E T N4
ETP4

P
P
P
P

E RN 5
E RP 5
E T N5
ETP5

P
P
P
P

E RN 6
E RP 6
E T N6
ETP6

A1 2

D R A MR S T _ C N TR L

C8

S ML 0 _ C L K

G1 2

S ML 0 _ D A T A

C1 3

LP D _ S P I _ I N TR #

E1 4

S MC _ C P U _ TH E R M

M1 6

S MD _ C P U _ TH E R M

S M L0 A L E R T # / GP I O 6 0

P C I E C L K R Q0 #

S M L0 C LK

S ML 1 C LK / GP I O 5 8
S ML 1 D A TA / GP I O 7 5

E RN 8
E RP 8
E T N8
ETP8

P C I E C L K R Q1 #

P C I E C L K R Q2 #

2 7 P C I E C L K R Q2 #

C L K OU T _ P C I E 1 N
C L K OU T _ P C I E 1 P

M1

M7

CL _ CL K 1

T11

CL _ DA T A 1

P1 0

C LK OU T_ D MI _ N
C L K OU T _ D M I _P

C L K OU T _ D P _ N
C L K O U T _ D P _P
C L K OU T _ P C I E 2 N
C L K OU T _ P C I E 2 P
C L K I N _ D MI _ N
C L K I N _ D M I _P

V1 0

Y3 7
Y3 6

2 2 C LK _P C I E _ M I N I #
2 2 C L K _ P C I E _ MI N I

C L K OU T _ P C I E 3 N
C L K OU T _ P C I E 3 P

C LK I N _ GN D 1 _ N
C L K I N _ G N D 1 _P

P C I E C L K R Q 3 # / GP I O 2 5
Y4 3
Y4 5

2 5 C L K _ P C I E _ I GL A N #
25 C L K _ P C I E _ I G L A N
R 17 3

0_04

10 0M H z

L A N _ C L K R E Q#

P C I E C L K R Q 4 # / GP I O 2 6

C L K OU T _ P C I E 5 N
C L K OU T _ P C I E 5 P

P E G _B _C L K R Q #

* 10 K _ 0 4
* 10 K _ 0 4

P C IE C L K RQ 1 #
D GP U _ P R S N T #
P C IE C L K RQ 2 #

R 54 3
R 46 3
R 16 9

* 10 K _ 0 4
* 10 K _ 0 4
* 10 K _ 0 4

C L K _ B UF _ C P Y C L K _ N
C L K _ B UF _ C P Y C L K _ P
C L K _ B U F _ D OT 9 6 _ N
C L K _ B U F _ D OT 9 6 _ P

R 1 32
R 1 34
R 2 32
R 2 40
R N1 9
1 0K _8 P 4 R _0 4
8
1
7
2
6
3
5
4

CL _ DA T A 1 2 2
C L K _ P C I E _I C H
C L K _ P C I E _I C H #
C L K_ SAT A#
C L K_ SAT A

CL _ RS T # 1 2 2

P E G_ C L K R E Q #
P C IE C L K RQ 2 #
C L K _ B UF _ R E F 1 4
L A N _ C L K R E Q#
IG L A N_ C L K RE Q #

P E G _ C L K R E Q#

1 0 K_ 0 4
1 0 K_ 0 4
1 0 K_ 0 4
1 0 K_ 0 4

R
R
R
R
R

21 2
17 5
20 8
23 9
25 5

Sheet 14 of 46
PCH/ PCI-E,
SMBUS, CLK

* 10 K _ 0 4
1 0 K_ 0 4
1 0 K_ 0 4
* 10 K _ 0 4
* 10 K _ 0 4

AB3 7
AB3 8

1 00 MHz

AV2 2
A U 22

CL K_ EXP_ N 3
CL K_ EXP_ P 3

A M 12
A M 13

C LK _D P _ N _ R
C LK _D P _ P _ R

BF1 8
BE1 8

C LK _P C I E _ I C H #
C LK _P C I E _ I C H

BJ 3 0
B G 30

C LK _B U F _ C P Y C L K _ N
C LK _B U F _ C P Y C L K _ P

G2 4
E2 4

C LK _B U F _ D OT 9 6_ N
C LK _B U F _ D OT 9 6_ P

AK7
AK5

C LK _S A T A #
C LK _S A T A

K4 5

C LK _B U F _ R E F 1 4

R 1 54
R 1 50

1 20 MHz

*1 0 m li _ 0 4
*1 0 m li _ 0 4

C L K _ DP _ N 3
C L K _ DP _ P 3

1 00 MHz

9 6M H z
10 0M H z
* X 8A 02 5 0 0 0F G1 H _ 2 5 MH z
C 447

14 .3 18 M Hz
33 MHz

C L K I N _ P C I LO OP B A C K

C L K OU T _ P E G_ B _ N
C L K OU T _ P E G_ B _ P

X T A L 25 _ I N
X TA L2 5 _ OU T

V4 7
V4 9

X T A L 25 _ I N
X T A L 25 _ O U T

Y4 7

X C L K _ R C O MP

R4 3 8

2 2 p _ 50 V _ N P O_ 0 4

X1

CL K _ P C I_ F B 1 7
1 M _0 4

X1 1

1126

F S X 5L _ 2 5 MH Z
C 444

2 2 p _ 50 V _ N P O_ 0 4

P E G_ B _ C LK R Q # / GP I O 5 6
X C LK _R C O MP

9 0. 9 _ 1 % _ 04

90.9-O ? % pullup to +VccIO

P C I E C L K R Q 6 # / GP I O 4 5

(1.05V, S0 rail)close to
PCH

K4 3
C L K OU T _ P C I E 7 N
C L K OU T _ P C I E 7 P

K1 2
P C I E C L K R Q 7 # / GP I O 4 6
AK1 4
AK1 3

R4 3 7

C L K OU T _ P C I E 6 N
C L K OU T _ P C I E 6 P

T1 3
V3 8
V3 7

P C I E C L K R Q7 #

R 21 9
R 26 2

E6

V4 0
V4 2
3G _ B _ C L K R Q#

25

CL _ CL K 1 2 2

CL _ RS T # 1

H4 5
P C I E C L K R Q 5 # / GP I O 4 4

AB4 2
AB4 0

P E G_ C L K R E Q #
3 G _B _C L K R Q #

R E F CL K 1 4 IN

L1 4

1124 change for layout
O nly PC IECLKRQ [2 :1 ]# on PCH a re core w e l l pow e re d.
Al l othe r PC IECLKRQ x # a re suspe nd w e ll pow e red.

C LK I N _ S A T A _ N
C L K I N _S A TA _P

L1 2

V4 5
V4 6

24 C L K _ P C I E _G L A N #
2 4 C L K _ P C I E _ GL A N

C L K I N _ D O T _9 6 N
C L K I N _ D OT _ 9 6P
C L K OU T _ P C I E 4 N
C L K OU T _ P C I E 4 P

C L K OU T _ I TP XD P _ N
C L K OU T _ I TP XD P _ P

FLEX CLOCKS

I GL A N _C L K R E Q#
2 5 I GL A N _ C L K R E Q#

1 0 K_ 0 4
1 0 K_ 0 4
* 10 K _ 0 4
* 10 K _ 0 4
* 10 K _ 0 4

S MD _ C P U _ T H E R M 2 , 2 8

A8
22 W LA N _ C L K R E Q#

24 8
25 0
48 1
54 0
54 1

S MC _ C P U _ T H E R M 2 , 2 8

C L _ RS T 1 #

C L K OU T _P E G_ A _ N
C L K O U T _ P E G _A _P

P C I E C L K R Q 2 # / GP I O 2 0

1 00 M Hz

R
R
R
R
R

3. 3 V S
S ML 0 _ D A T A

C L_ D A T A 1

C L K OU T _ P C I E 0 N
C L K OU T _ P C I E 0 P
P C I E C L K R Q 0 # / GP I O 7 3

AA4 8
AA4 7

BT_ SBD #
L P D _ S P I_ INT R #
P E G_ B _ C L K R Q#
P C IE C L K RQ 0 #
P C IE C L K RQ 7 #

S ML 0 _ C L K 2 5

C L _C L K 1

P C I E C L K R Q 1 # / GP I O 1 8
2 7 C LK _P C I E _ U S B 3 0#
2 7 C L K _ P C I E _ U S B 30

D R A MR S T _ C N T R L 3 , 8

P E G_ A _ C LK R Q # / GP I O 4 7

J2

AB4 9
AB4 7

S MB _D A T A 9 , 1 0

S ML 0 D A TA

M1 0
Y4 0
Y3 9

S MB _C L K 9 , 1 0

S ML 1 A L E R T # / P C H H O T # / GP I O 7 4

P E RN 7
P E RP 7
P E T N7
P ETP7
P
P
P
P

S MB _ D A T A

2 .2 K _ 0 4
2 .2 K _ 0 4
1 K_ 0 4

1. 0 5 V S
13 , 1 5 , 1 7 , 18 , 2 0 , 2 2 , 2 3, 2 4 , 2 5 , 2 8, 3 2 , 3 3 , 3 5, 3 9
2 , 3 , 8 , 11 , 1 3 , 1 5 , 17 , 1 9 , 2 0 , 2 2, 2 3 , 2 7 , 2 9, 3 1 , 3 2 , 3 4, 3 6
3 , 9, 10 , 1 1 , 1 2, 13 , 1 5 , 1 6 , 17 , 1 8 , 1 9 , 20 , 2 3 , 2 4 , 2 5, 2 6 , 2 8 , 2 9, 3 0 , 3 1 , 3 2, 3 7
1 3, 1 5 , 1 9 , 2 0, 3 2

VD D3
3 .3 V
3 .3 V S
1 .0 5 V S

C L K OU T F L E X 0 / GP I O 6 4
F47
C L K OU T F L E X 1 / GP I O 6 5
C L K OU T F L E X 2 / GP I O 6 6

H4 7
K4 9

D GP U _ P R S N T #

C L K OU T F L E X 3 / GP I O 6 7

C o u g arP oi n t _ R e v _ 1 p 0

PCH/ PCI-E, SMBUS, CLK B - 15

B.Schematic Diagrams

B G3 7
BH3 7
AY3 6
BB3 6

P
P
P
P

S MB _ C LK

S M C _C P U _T H E R M R 24 9
S M D _C P U _T H E R M R 25 6
D R A MR S T _C N T R L R 48 2

1

P C I E _T X N 4_ C
P C I E _T X P 4 _ C

BT_ SBD # 2 2

H1 4
C9

4

0 . 1 u_ 1 0 V _ X 7R _ 0 4
0 . 1 u_ 1 0 V _ X 7R _ 0 4

E RN 3
E RP 3
E T N3
ETP3

S M B C LK
S M B D A TA

1

C1 3 0
C1 2 9

P C I E _T X N 3_ C
P C I E _T X P 3 _ C

P
P
P
P

S MB A L E R T # / GP I O 1 1

3

P C I E _ R X N 4_ G LA N
P C I E _ R X P 4 _ GL A N
P C I E _ T XN 4 _G L A N
P C I E _T X P 4 _ GL A N

0 . 1 u_ 1 0 V _ X 7R _ 0 4
0 . 1 u_ 1 0 V _ X 7R _ 0 4

B G3 6
B J3 6
AV3 4
AU3 4

B T_ S B D #

2

24
24
24
24

C1 4 2
C1 4 3

P C I E _T X N 2_ C
P C I E _T X P 2 _ C

E RN 2
E RP 2
E T N2
ETP2

E1 2

V DD 3

_0 4
1
2
3
4

2

22 P C I E _ R XN 3 _ W L A N
22 P C I E _ R XP 3_ W L A N
22 P C I E _ T X N 3 _ W L A N
2 2 P C I E _ T XP 3_ W L A N

0 . 1 u_ 1 0 V _ X 7R _ 0 4
0 . 1 u_ 1 0 V _ X 7R _ 0 4

P
P
P
P

SMBUS

C1 3 1
C1 3 2

BE3 4
BF 3 4
BB3 2
AY3 2

P E RN 1
P E RP 1
P E T N1
P ETP1

Link

2 _ USB3 0
2_ U S B 3 0
2 _ USB3 0
2_ U S B 3 0

B G3 4
B J3 4
AV3 2
AU3 2

Controller

P C I E _ R XN
P C I E _ R XP
P C I E _ T XN
P C I E _ T XP

_R X N 1
_R X P 1
_T X N 1
_T X P 1

CLOCKS

27
27
27
27

P CIE
P CIE
P CIE
P CIE

PCI-E*

T 71
T 72
T 12
T 13

RN 9
2. 2K _ 8 P 4 R
8
7
6
5

B _ CL K
B _ D A TA
L 0 _D A T A
L 0 _C L K

Schematic Diagrams

PCH/ DMI, FDI, GPIO
3 .3 V

CougarPoint -M (DMI,FDI,GPIO)
A C_ P RE S E NT

R 5 44

10 K _ 0 4

P CIE _ W A K E #

R 4 86

10 K _ 0 4

P M_ S L P _ LA N #

R 2 47

*1 0K _0 4

S W I#

R 4 85

10 K _ 0 4

P W R_ B T N#

R 2 52

10 K _ 0 4

P M_ B A T L OW #

R 2 46

8. 2 K _ 0 4

S U S _ P W R _A C K

R 4 83

10 K _ 0 4

P M_ C L K R U N #

R 4 47

8. 2 K _ 0 4

R 63 5

* 0 _0 4

R 63 6

0_04

U3 7 C
V D D3

2
2
2
2

D MI _ R X P 0
D MI _ R X P 1
D MI _ R X P 2
D MI _ R X P 3
D
D
D
D

2
2
2
2

MI _ T XN
MI _ T XN
MI _ T XN
MI _ T XN

DM
DM
DM
DM

BE2 4
BC 2 0
BJ 1 8
BJ 2 0

D
D
D
D

AW 2 4
AW 2 0
BB1 8
AV1 8

0
1
2
3

AY 2 4
AY 2 0
AY 1 8
AU 1 8

I _T X P 0
I _T X P 1
I _T X P 2
I _T X P 3

F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R

MI 0 R X P
MI 1 R X P
MI 2 R X P
MI 3 R X P

D
D
D
D

MI 0 T XN
MI 1 T XN
MI 2 T XN
MI 3 T XN

D
D
D
D

MI 0 T XP
MI 1 T XP
MI 2 T XP
MI 3 T XP

FD
FD
FD
FD
FD
FD
FD
FD

XN
XN
XN
XN
XN
XN
XN
XN

0
1
2
3
4
5
6
7

I_ RX P 0
I_ RX P 1
I_ RX P 2
I_ RX P 3
I_ RX P 4
I_ RX P 5
I_ RX P 6
I_ RX P 7

B J1 4
AY1 4
B E 14
BH1 3
BC1 2
B J1 2
B G1 0
B G9
B G1 4
B B 14
B F 14
B G1 3
B E 12
B G1 2
B J1 0
BH9

A W 16

4 9 . 9_ 1 % _0 4

D MI _ C OMP _ R

BJ 2 4
BG 2 5

R 42 2

7 5 0_ 1 % _0 4

D MI _ Z C O MP

F D I _F S Y N C 0

D MI _ I R C OM P

F D I _F S Y N C 1

BH 2 1

D MI _ 2 R B I A S

D I _ TX N
D I _ TX N
D I _ TX N
D I _ TX N
D I _ TX N
D I _ TX N
D I _ TX N
D I _ TX N

F
F
F
F
F
F
F
F

D I _ TX P 0
D I _ TX P 1
D I _ TX P 2
D I _ TX P 3
D I _ TX P 4
D I _ TX P 5
D I _ TX P 6
D I _ TX P 7

F DI_ INT

F D I _I N T
R 42 3

1 .0 5 V S

F
F
F
F
F
F
F
F

A V 12

0
1
2
3
4
5
6
7

2
2
2
2
2
2
2
2

V DD3

1125

3 . 3V S

S U S C#
SL P_ S5 #
S L P _ M#

S AM E TH E BI O S R O M S I D E

2

F DI_ F SY N C0 2

BC1 0

R T CV CC

F DI_ F SY N C1 2

A V 14
D MI 2 R B I A S

F D I _ LS Y N C 0

DS W O DV R E N

F D I _ LS Y N C 0 2
B B 10

F D I _ LS Y N C 1

S U S_ A CK #

R 6 71

* 0_ 0 4

S U S _ P W R _A C K

R 6 70

0 _ 04

S US _ A C K #

R4 5 3

3 . 3V S

2 8 P M_ P C H _P W R OK

S U S _A C K # _R

C 12

S Y S _R E S E T #

K 3

S Y S _P W R OK

P1 2

S U SA CK #

S Y S_ RE S E T #

C 5 89

S Y S_ P W RO K

*0 . 1 u_ 1 6V _Y 5V _ 0 4
10 K _ 0 4

R2 1 3

*0 _0 4

P M_ P C H _P W R OK _ R

L22

P M_ MP W R OK

L10

P W R OK

1229 D02
A P W R OK
B1 3
3 P M_ D R A M_ P W R G D
28

D RAM P W RO K

RS M RS T #

C 21

R S MR S T#
1 0K _ 0 4

R2 6 1

DS W O DV RE N

E 22

D P W R OK

B9

P CIE _ W A K E #

N3

P M_ C L K R U N #

R S MR S T#
S US_ P W R_ AC K

2 8 S US _ P W R_ A CK

K1 6

D P W R OK

R 2 57

33 0 K _ 04

R4 7 9

*3 30 K _ 0 4

*1 0m i l _0 4

DSWODVREN - On Die DSW VR Enable

RS M RST #

HI Enabled (DEFAULT)
P C I E _ W A K E # 22 , 2 4, 2 7

W AKE#

LOW Disabled

C L K R U N # / GP I O3 2

P M _C L K R U N # 23
G8

S U S _ S TA T# / GP I O6 1

S 4 _S TA T E # 2 3
S US CL K

N1 4
D1 0

ME-POWROK

S U S C L K 28

S U S C L K / GP I O6 2

to EC

S LP _ S 5 #

0310-J
Add timing Adj

11 2 4
32

H4

S US C#

F4

S US B #

G1 0

S L P _ M#

SL P_ S4 #

VDD 3
3 .3 V _ M

S L P _ S 5# 2 8

S L P _S 5# / GP I O6 3

S U S W A R N # / S U S P W R D N A C K / GP I O3 0

SL P_ S3 #

S U S C#

28 , 3 4

SU SB#

6, 2 7 , 2 8, 3 2

S L P _ M#

28 , 3 2

R4 3 3

S LP _M

C5 9 4
3 30 0 p_ 5 0 V _X 7 R _ 0 4

E2 0

P W R _B T N #

P W RB T N#

1 7, 28 A C _ P R E S E N T

A C_ P RE S E N T

H 20

P M_ B A T LO W #

E1 0

A C P R E S E N T / GP I O 31

t o EC

S LP _ S U S #

S LP _ S U S #

S

R 62 2
*1 0 K _0 4
Q5 0
MT N 7 00 2 Z H S 3

R6 9 0
1 0K _ 0 4

D

1129
U 4 8A
7 4 L V C0 8 P W

1
3

SL P_ A#
G1 6

4 7 0K _ 0 4

2

1 1 24

S L P _ S US # 2 8

P M_ MP W R OK
R 62 3

C5 9 5
1u _ 6 . 3V _ X 5R _ 04

3 5 1. 05 V _ LA N _ P W R G D
A P 14
B A T L OW # / G P I O7 2

H _P M _ S Y N C

P M S Y N CH

0_04

7

P W R _B T N #
28

R4 7 2

D S W V R ME N

1 0 K _ 04

R2 7 0

F D I _ LS Y N C 1 2

A 18

14

28

S ys te m Pow er M ana ge me nt

1 1 24

G

Sheet 15 of 46
PCH/ DMI, FDI,
GPIO

1 1 26

SU SB#

2
2
2
2
2
2
2
2

R 62 4
1 M_ 0 4

3
0323-J

S W I#
28

A1 0

P M_ S L P _L A N #

K 14

S W I#

R I#

S LP _ L A N # / GP I O2 9

0310-J
Add

add

P M _S L P _ L A N # 2 8, 3 2 , 3 5

C o ug a rP o ni t _ R e v _ 1 p0
U 1 5 _3 . 3 V
3 .3 V

U 1 5D
7 4 L V C0 8 P W

U 1 5_ 3 . 3 V

*0 _0 4

R 63 4

0_ 0 4

3 6 0 . 85 V S _ P W R GD

3 4 D D R 1. 5 V _ P W R G D

R6 9 1

* 0_ 0 4

R 6 93
0_ 0 4

14

0 _ 04

U 1 5 _3 . 3 V
R 69 4
* 0_ 0 4

U 1 5_ 3 . 3 V

R 6 29

0 _ 04

0_ 0 4

R6 2 8

*0 _0 4
1228 D02

R 6 30

0 _ 04 1 0

8
6

7
7

R6 3 1
*1 0 K _0 4

R 54 6
*2 K _ 0 4

R5 4 5
1 0K _ 0 4

R 6 32

0_ 0 4

*0 _ 0 4

P M_ MP W R OK
R 55 1
*1 K _ 0 4

ON
? ? SUSB# -->? ? 1.05VS_VTT? SUSPEND? ? ? ? ?

B - 16 PCH/ DMI, FDI, GPIO

* 0_ 0 4 P M _P C H _ P W R OK _ R

R 62 7

0 _ 04

S Y S _ P W RO K

R2 5 3
10 K _ 0 4

A L L _S Y S _ P W R G D 1 1, 28 , 3 7

5

2
35 1 . 0 5V _ L A N _ P W R GD

R 2 78

R 62 5

9

4

1
3

A L L_ S Y S _P W R GD

13

R6 2 6

U 15 C
7 4 LV C 08 P W

1228 D02

U 15 B
7 4 L V C 0 8P W
14

U1 5 A
74 L V C 0 8 P W
R6 9 2

11 S Y S _ P W R _O K

2 8 P M _ P C H _ P W R OK

0224
3, 3 4 1 . 8V S _ P W R GD

3 7 D E LA Y _ P W R G D

3 4 D D R 1 . 5 V _P W R GD
3, 3 4 1 . 8V S _ P W R GD
U 15 _ 3. 3 V

0 1 05 D 02

12

14

R 63 3

14

1 12 9

7

VD D3

7

B.Schematic Diagrams

2
2
2
2

D MI 0 R X N
D MI 1 R X N
D MI 2 R X N
D MI 3 R X N

FD I

D MI _ R X N 0
D MI _ R X N 1
D MI _ R X N 2
D MI _ R X N 3

D MI

2
2
2
2

BC 2 4
BE2 0
BG 1 8
BG 2 0

1. 0 5 V S _ V TT _ E N 3 2 , 35

1 207

1 3, 1 9 , 2 5, 2 6 , 32
9, 1 0 , 34
1 3 , 20
1 3, 1 4 , 1 9, 2 0 , 32
2 , 3, 8 , 1 1 , 13 , 1 7, 19 , 2 0, 2 2 , 2 3, 2 7 , 2 9, 3 1 , 3 2, 3 4 , 36
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 14 , 1 6 , 17 , 1 8 , 19 , 2 0, 23 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 3 1, 3 2 , 37
13 , 1 4 , 17 , 1 8, 20 , 2 2, 2 3 , 2 4, 2 5 , 2 8, 3 2 , 3 3, 3 5 , 39

3 . 3 V _M
V T T _M E M
R TC V C C
1 . 0 5V S
3 .3 V
3 .3 V S
V D D3

Schematic Diagrams

PCH/ LVDS, DDI, CRT
CougarPoint -M
(LVDS,DDI,CRT)

U 37D
L _ BKL TEN
L _ V D D_ E N

S D V O _ TV C L K I N N
S D V O _ T V C LK I N P

P4 5
L _ BKL TC TL

2 . 3 7K _1 % _ 0 4

L V D S _ IB G

AF3 7
AF3 6
AE4 8
AE4 7

11
11
11
11
11

11
11
11

12

DAC _ B L U E

12

D A C _ GR E E N

12

DAC _ RE D

DA C_ B L U E
* 3 3p _ 5 0 V _ N P O_ 0 4

DA C_ G RE E N

* 3 3p _ 5 0 V _ N P O_ 0 4

DA C_ R E D

L V D S -L C L K N
L V D S -L C LK P
L V D S -L 0 N
L V D S -L 1 N
L V D S -L 2 N

AN 4 8
AM 4 7
AK4 7
AJ 4 8

L V D S -L 0 P
L V D S -L 1 P
L V D S -L 2 P

AN 4 7
AM 4 9
AK4 9
AJ 4 7

AF4 0
AF3 9

11
11

L V D S -U C L K N
L V D S -U C L K P

11
11
11

L V D S -U 0 N
L V D S -U 1 N
L V D S -U 2 N

AH 4 5
AH 4 7
AF4 9
AF4 5

11
11
11

L V D S -U 0 P
L V D S -U 1 P
L V D S -U 2 P

AH 4 3
AH 4 9
AF4 7
AF4 3

R2 0 0
R1 8 7
R1 9 2

C 196

AK3 9
AK4 0

1 50 _ 1 % _ 0 4
1 50 _ 1 % _ 0 4
1 50 _ 1 % _ 0 4

N 48
DA C_ B L U E
DA C_ G RE E N P 4 9
DA C_ R E D
T4 9

C 188
C 169
* 3 3p _ 5 0 V _ N P O_ 0 4

EMI

NEAR PCH

12
12
R 165

T3 9
M 40

1 2 D A C _D D C A C L K
1 2 D A C _D D C A D A T A

M 47
M 49

DAC _ HS Y N C
DA C _ V S Y NC

1 K_ 1 % _ 0 4

Connect to GND

DA C_ IR E F

T4 3
T4 2

S D V O _I N T N
S DV O _ INT P

AP3 9
AP4 0

L _ C TR L _ C L K
L _ C TR L _ D A TA
L V D _ IBG
L VD _ VBG

S D V O_ C TR L C L K
SD VO _ CT R L DAT A

L VD _ VR EF H
L VD _ VR EF L

L VD SA_ C L K#
L VD SA_ C L K
L VD SA_ D ATA# 0
L VD SA_ D ATA# 1
L VD SA_ D ATA# 2
L VD SA_ D ATA# 3
L VD
L VD
L VD
L VD

SA_ D
SA_ D
SA_ D
SA_ D

DD P B _ A UX N
D DP B _ A UX P
DD P B _ H P D

ATA0
ATA1
ATA2
ATA3

L VD SB_ C L K#
L VD SB_ C L K
L VD
L VD
L VD
L VD

SB_ D
SB_ D
SB_ D
SB_ D

ATA# 0
ATA# 1
ATA# 2
ATA# 3

L VD
L VD
L VD
L VD

SB_ D
SB_ D
SB_ D
SB_ D

ATA0
ATA1
ATA2
ATA3

C RT _ BL U E
C RT _ G RE E N
C RT _ R E D

C RT _ D DC _ CL K
C R T _ D D C _ D A TA

DD P B _ 0 N
D D P B _0 P
DD P B _ 1 N
D D P B _1 P
DD P B _ 2 N
D D P B _2 P
DD P B _ 3 N
D D P B _3 P

D D P C _ C TR L C L K
DD P C _ CT R L DA T A

D D P C_ A UX N
DD P C _ A UX P
D DP C_ H P D
D DP C_ 0 N
D D P C _0 P
D DP C_ 1 N
D D P C _1 P
D DP C_ 2 N
D D P C _2 P
D DP C_ 3 N
D D P C _3 P

D D P D _ C TR L C L K
DD P D _ CT R L DA T A

C RT _ H S Y NC
C RT _ VS YN C

D A C _I R E F
C RT _ IR T N

D D P D_ A UX N
DD P D _ A UX P
D DP D_ H P D
D DP D_ 0 N
D D P D _0 P
D DP D_ 1 N
D D P D _1 P
D DP D_ 2 N
D D P D _2 P
D DP D_ 3 N
D D P D _3 P

P3 8
M 39

AT 4 9
AT 4 7
AT 4 0
AV4 2
AV4 0
AV4 5
AV4 6
AU 4 8
AU 4 7
AV4 7
AV4 9

R 271
R 272

2 .2 K_ 0 4
2 .2 K_ 0 4

P4 6
P4 2

3 .3 VS

SDVO

R1 7 0

T4 5
P3 9

Display Port B

L _ C TR L _ C L K
L _ C TR L _ D A TA

LVDS

1 0K _0 4
1 0K _0 4

Digital Display Interface

R1 6 3
R2 1 5

S D V O_ S T A L L N
S D V O_ S TA LL P

L _ D DC _ CL K
L _ D DC _ DA T A

Sheet 16 of 46
PCH/ LVDS, DDI,
CRT

H D M I _ C T R L C L K 12
H DM I_ CT R L DA T A 1 2

AP4 7
AP4 9
AT 3 8

P C H_ D DP C _ HP D

AY 4 7
AY 4 9
AY 4 3
AY 4 5
BA4 7
BA4 8
BB4 7
BB4 9

HD
HD
HD
HD
HD
HD
HD
HD

M
M
M
M
M
M
M
M

IB _ D2 B N
IB _ D2 B P
IB _ D1 B N
IB _ D1 B P
IB _ D0 B N
IB _ D0 B P
IB _ CL K B
IB _ CL K B

_C
_C
_C
_C
_C
_C
N_ C
P_ C

R 153
C
C
C
C
C
C
C
C

1 40
1 41
1 24
1 25
1 26
1 27
1 37
1 38

*1 0 m i l_ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4
0 . 1u _ 1 0 V _ X 7 R _ 0 4

P O R T C _H P D
H
H
H
H
H
H
H
H

DM
DM
DM
DM
DM
DM
DM
DM

IB_ D
IB_ D
IB_ D
IB_ D
IB_ D
IB_ D
IB_ C
IB_ C

2B
2B
1B
1B
0B
0B
LK
LK

12

N 12
P 12
N 12
P 12
N 12
P 12
BN 1 2
BP 1 2

M 43
M 36

AT 4 5
AT 4 3
BH 4 1
BB4 3
BB4 5
BF 4 4
BE4 4
BF 4 2
BE4 2
BJ 4 2
BG 4 2

C o u g arP o in t _ R e v _ 1 p0

1 1 , 1 2 , 1 9 , 2 0 , 2 6, 30 , 3 1 , 3 2 , 3 7 , 3 8 5 V S
3 , 9 , 1 0 , 1 1 , 1 2 , 1 3, 14 , 1 5 , 1 7 , 1 8 , 1 9 , 20 , 2 3 , 2 4 , 2 5 , 2 6 , 2 8, 29 , 3 0 , 3 1 , 3 2 , 3 7 3 . 3 V S

PCH/ LVDS, DDI, CRT B - 17

B.Schematic Diagrams

3 .3 VS

T4 0
K4 7

11
P _D D C _ C LK
1 1 P _ D D C _ D A TA

CRT

Ver:1.0
pull up 2.2K

AP4 3
AP4 5
AM 4 2
AM 4 0

Display Port C

J47
M 45

B L ON
NB _ E N A V DD

Display Port D

11
1 1, 28

Schematic Diagrams

PCH/ PCI, USB, NVRAM
Boot BIOS Strap
Boot BIOS Location
LPC

0

1

Reserved

1
1

0
1

PCI
SPI

* 1 K _0 4

R 4 46

* 1 K _0 4

U 3 7E

B G2 6
BJ 2 6
B H2 5
BJ 1 6
B G1 6
A H3 8
A H3 7
AK4 3
AK4 5
C1 8
N3 0
H3
A H1 2
AM 4
AM 5
Y1 3
K2 4
L24
AB4 6
AB4 5

B B S _ B IT 1
B B S _B IT0 1 3

Flash Descriptor security override strap

Sheet 17 of 46
PCH/ PCI, USB,
NVRAM

LOW = PCI_GNT#3 swap override
HIGH = Default

PCI_GNT#3
R 22 5

* 1K _0 4

*1 K _ 0 4

BE2 8
B C3 0
BE3 2
BJ 3 2
B C2 8
BE3 0
BF3 2
B G3 2
AV2 6
BB2 6
A U2 8
A Y3 0
A U2 6
A Y2 6
AV2 8
AW 3 0

IN T_ P IR QE #

MPC Switch Control
MPC ON -- 0
MPC OFF -- 1 DEFAULT

3 .3 V

P L T _ RS T #

IN
IN
IN
IN

U 13
7 4 A HC 1 G0 8 GW

1
4

B UF _ P L T _R S T # 2 2, 24 , 2 5 , 2 7, 28

2
R 24 5

T_ P IR
T_ P IR
T_ P IR
T_ P IR

QA #
QB #
QC #
QD #

K4 0
K3 8
H3 8
G3 8

DG P U _H OL D _R S T #
DG P U _S E LE CT #
D_ G P U_ P W R_ E N #

C4 6
C4 4
E4 0

D4 7
BBS _ BIT 1
D GP U _ P W M _S E L E CT # E 4 2
P C I _G N T # 3
F4 6

1 0 0 K _0 4

2 6 S A T A _ O D D _D A #

IN T_ P IR QE #
S A T A _ OD D_ D A #
IN T_ P IR QG #
IN T_ P IR QH #

G4 2
G4 0
C4 2
D4 4

1
2
3
4

R SVD 7
R SVD 8
R SVD 9
R SVD 1 0
R SVD 1 1
R SVD 1 2
R SVD 1 3
R SVD 1 4
R SVD 1 5
R SVD 1 6
R SVD 1 7
R SVD 1 8
R SVD 1 9
R SVD 2 0
R SVD 2 1
R SVD 2 2

TP2 1
TP2 2
TP2 3
TP2 4

R SVD 2 3
R SVD 2 4

TP2 5
TP2 6
TP2 7
TP2 8
TP2 9
TP3 0
TP3 1
TP3 2
TP3 3
TP3 4
TP3 5
TP3 6
TP3 7
TP3 8
TP3 9
TP4 0

R SVD 2 8
R SVD 2 9

QA #
QB #
QC #
QD #

R E Q1 # / GP I O5 0
R E Q2 # / GP I O5 2
R E Q3 # / GP I O5 4
G N T 1 # / GP I O 5 1
G N T 2 # / GP I O 5 3
G N T 3 # / GP I O 5 5

P IR
P IR
P IR
P IR

FOR LAYOUT SWAP

I NT _ P I R QD #
D _ GP U _ P W R _ E N#
S A T A _ OD D_ DA #
I NT _ P I R QG #

A T 10
B C8
A U2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
B D4
BF6

I N T _P
D GP U
D GP U
I N T _P

QE # / G P IO
QF # / G P IO
QG # / GP IO
QH # / GP IO

2
3
4
5

1207
2 3 P C LK _T P M
1 4 C LK _ P C I _ F B
28 P C L K _ K B C

3 ,2 3

PM E#
P L T _R S T #

C6
H4 9
H4 3
J48
K4 2
H4 0

R 2 14
R 2 27

22_04
22_04

P C LK _T P M _ P C H
CL K _ P C I _ F B _ R

R 2 60

22_04

CL K _ P C I _ K B C_ R

PL T RST #

LK O
LK O
LK O
LK O
LK O

UT _ P C
UT _ P C
UT _ P C
UT _ P C
UT _ P C

I0
I1
I2
I3
I4

U SBP0 N
U SBP0 P
U SBP1 N
U SBP1 P
U SBP2 N
U SBP2 P
U SBP3 N
U SBP3 P
U SBP4 N
U SBP4 P
U SBP5 N
U SBP5 P
U SBP6 N
U SBP6 P
U SBP7 N
U SBP7 P
U SBP8 N
U SBP8 P
U SBP9 N
U SBP9 P
U SBP1 0 N
US B P 10 P
U SBP1 1 N
US B P 11 P
U SBP1 2 N
US B P 12 P
U SBP1 3 N
US B P 13 P

A T 12
BF3

C2 4
A2 4
C2 5
B2 5
C2 6
A2 6
K2 8
H2 8
E2 8
D2 8
C2 8
A2 8
C2 9
B2 9
N2 8
M2 8
L3 0
K3 0
G3 0
E3 0
C3 0
A3 0
L3 2
K3 2
G3 2
E3 2
C3 2
A3 2

U
U
U
U
U
U
U
U
U
U
U
U

S B _ P N0
SB_ PP0
S B _ P N1
SB_ PP1
S B _ P N2
SB_ PP2
S B _ P N3
SB_ PP3
S B _ P N4
SB_ PP4
S B _ P N5
SB_ PP5

27
27
31
31
22
22
31
31
23
23
23
23

USB PORT0 (J_USB3_1; USB3.0)
USB PORT1 (J_USB_1)
WLAN
FINGER PRINTER
3G
CCD

U S B _ P N9 3 1
U SB_ PP9 3 1

C3 3

US B _ B I A S

U S B RB I A S #

R 4 67

OC 0 # /
OC 1 # /
OC 2 # /
OC 3 # /
OC 4 # /
OC 5#
OC 6 # /
OC 7 # /

GP I O 5 9
GP I O 4 0
GP I O 4 1
GP I O 4 2
GP I O 4 3
/ G P IO 9
GP I O 1 0
GP I O 1 4

A1 4
K2 0
B1 7
C1 6
L1 6
A1 6
D1 4
C1 4

US B
US B
US B
US B
US B
US B
US B
US B

_O
_O
_O
_O
_O
_O
_O
_O

C# 0 1
C# 2 3
C# 4 5
C# 6 7
C# 8 9
C# 1 0 1 1
C# 1 2 1 3
C# 1 4

3 .3 V

USB PORT2 (AJ_USB1)

US B _P N1 1 2 9
U SB_ PP1 1 2 9

1126

BT PORT11

U S B _ OC # 45
U S B _ OC # 10 1 1
U S B _ OC # 67
U S B _ OC # 12 1 3

RN 6
1 0 K _ 8P 4R _ 0 4
5
4
6
3
7
2
8
1

U
U
U
U

RN 7
1 0 K _ 8P 4R _ 0 4
5
4
6
3
7
2
8
1

2 2. 6 _ 1 % _ 04

US B _ O C # 0 1 31

10/29

R2 3 3
C o ug a rP o i nt _ R e v _ 1p 0

B - 18 PCH/ PCI, USB, NVRAM

R2 2 8
R2 6 5
R2 5 1
R2 4 1

AY5
BA2

US B R B IA S

C
C
C
C
C

1 0 K _0 4
1 0 K _0 4
1 0 K _0 4
* 1 0K _ 0 4

AV5
AV1 0

PM E#
P L T _R S T #

3 .3 V S

R N4
1 0 K _ 8P 4R _ 0 4
IR Q A #
4
5
6
_ HO LD _ R S T # 3
_ SE L ECT #
2
7
IR Q E #
1
8

I N T _ P I RQ B #
I N T_ P I R QC #
I N T_ P I R QH #
D G P U_ P W M _ S E L E C T#

B3 3
K1 0
28

R N5
1 0 K _ 8P 4R _ 0 4
4
5
3
6
2
7
1
8

AT8
R SVD 2 6
R SVD 2 7

P IR
P IR
P IR
P IR

AY7
AV7
A U3
B G4

R SVD 2 5

PIN PLT_ RST# to B uffe r

*0 . 1 u _1 6 V _ Y 5 V _ 0 4
5

C 2 07

SVD
SVD
SVD
SVD

R SVD 5
R SVD 6

P C I _G NT # 3
B2 1
M2 0
A Y1 6
B G4 6

R2 4 3

R
R
R
R

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP1 0
TP1 1
TP1 2
TP1 3
TP1 4
TP1 5
TP1 6
TP1 7
TP1 8
TP1 9
TP2 0

U SB

R 2 26

CougarPoint -M (PCI,USB,NVRAM)

(NAND)

R SV D

0

PC I

BBS_BIT0

0

3

B.Schematic Diagrams

BBS_BIT1

* 0_ 0 4

A C _ P RE S E N T 1 5 , 2 8

S B _ OC
S B _ OC
S B _ OC
S B _ OC

# 01
# 14
# 23
# 89

VD D3

R6 8 9

R6 8 8

*0 _ 0 4

0 _0 4

Schematic Diagrams

PCH/ GPIO, VSS_NCTF, RSVD
1 0K _0 4

R1 8 4

*0 _ 0 4

B IO S _ RE C

CougarPoint - M (GPIO,VSS_NCTF,RSVD)

BIOS RECOVERY
DISABLE----R349 NO STUFF (DEFAULT)
ENABLE-----R349 STUFF

U 37F
S _ GP I O
28

3. 3 V S

R4 5 1

*1 0 K _ 04

R4 5 0

10 0 K _ 0 4

T7

S MI #

A4 2

D G P U _ H P D _ I N TR #

H3 6

S CI#

E3 8

I C C _E N #

C1 0

S MI #

GF X _ C R B _ D E T
28

S CI#

11/18
P M_ L A N P H Y _ E N

2 5 P M _ LA N P H Y _ E N
28

R3 1 6

0 _ 04

T A C H 4 / G P I O6 8

T A C H 1 / G P I O1

T A C H 5 / G P I O6 9

T A C H 2 / G P I O6

T A C H 6 / G P I O7 0

T A C H 3 / G P I O7

T A C H 7 / G P I O7 1

*0 _ 0 4

H O S T _A L E R T # 1

G2

S A T A _ DE T # 4

U2

28 S LP _M E _ C S W _S E V #

1124
28

D4 0

T A C H 0 / G P I O1 7

T5
E8

ICP P E #

S B _ B L ON

G P I O2 7

R 6 76

R6 9 9

* 0 _0 4

P L L_ O D V R _ E N

P8

GP I O 3 4

K1

G P I O2 8

P C H _ MU T E #

P R OC P W R GD

R 47 1

1 . 5 K _ 1 %_ 0 4

3. 3 V S
3. 3 V S

AU 1 6

HP E CI_ R

P5

K B C _R S T #

TS_ VSS2

S A T A _ OD D _ P R S N T #

V8

F DI_ O V RV L T G

M5

TS_ VSS3
S A TA 2 G P / G P I O3 6
TS_ VSS4

G A2 0

28

H _P E C I

3 ,2 8

1. 05 V S _ V T T

K B C _ RS T # 2 8

AY 1 1

H _C P U P W R G D

AY 1 0

H T H R M TR I P # _ R

T14

INIT 3 _ 3 V#

AY 1

N V _ C LE

R 1 25

3 9 0 _ 1% _ 0 6

R 4 29

1 K _ 04

10/28
AH 8 R 5 4 7

*1 0 m i _l 0 4

AK1 1 R 5 4 8

*1 0 m i _l 0 4
*1 0 m i _l 0 4

AK1 0 R 5 5 0

*1 0 m i _l 0 4

2 .2 K_ 0 4

1 . 8V S

H _ S N B _I V B # 3

DMI & FDI Termination Voltage
NV_CLE

A H 1 0R 5 4 9

3

H _T H R M T R I P # 3
R 4 30

D F_ TVS

TS_ VSS1

K4

*1 0 K _ 0 4
* 0 _0 4

I N I T 3_ 3 V #

G P I O3 5
2 6 S A T A _ OD D _ P R S N T#

R 1 37
R 1 38

T H R M TR I P #

S T P _ P C I # / GP I O3 4

0_ 0 4

1201

Set to Vss when LOW
Set to Vcc when HIGH

Sheet 18 of 46
PCH/ GPIO,
VSS_NCTF, RSVD

S A TA 3 G P / G P I O3 7
3 .3 VS

3 .3 VS
2 C R I T _ T E MP _ R E P #

V DD 3

GP I O 7 1

S A T A _ O D D _P W R G T 26

P4

G P I O2 4 / M E M_ L E D

11/18

A4 0

A 20 G A T E

E1 6
11

INTEGRATE CLOCK
DISABLE----R465 NO STUFF (DEFAULT)
ENABLE-----R465 STUFF

1 . 5 K _ 1 %_ 0 4

1 0K _ 0 4

GF X _ C R B _ D E T

M3

R1 8 1

1 0K _ 0 4

TE S T_ S E T_ U P

V1 3

R4 3 5

*0 _ 0 4

C R I T_ T E M P _ R E P # _ R

R2 2 2

1 00 K _ 0 4

MF G _ MO D E

N2

R4 4 9

T E ST _ DET

P3 7
S L O A D / GP I O 3 8

N C_ 1

S D A T A O U T 0 / GP I O3 9
S D A T A O U T 1 / GP I O4 8

V S S _ N C TF _ 1 5

S A TA 5 G P / G P I O4 9

V S S _ N C TF _ 1 6

G P I O5 7

V S S _ N C TF _ 1 7

V3

BG 2
BG 4 8

D6

BH 3
BH 4 7

1 K_ 0 4
1 K_ 0 4
*1 0 K _ 0 4

H OS T _ A L E R T# 1
H OS T _ A L E R T# 2
P M _ LA N P H Y _ E N

V S S _ N C TF _ 1 8
A4
A4 4

3 .3 VS

R N8
1 0 K _ 8P
1
2
3
4

BJ 4
V S S _N C TF _ 1

V S S _ N C TF _ 1 9

V S S _N C TF _ 2

V S S _ N C TF _ 2 0

V S S _N C TF _ 3

V S S _ N C TF _ 2 1

A4 5
4R _ 04
8
7
6
5

SC I#
SM I#
G A2 0
K B C _ R S T#

V S S _N C TF _ 4
A5
V S S _N C TF _ 5
A6

R1 7 9
R1 6 6
R2 6 4
R4 7 0
R4 5 5
R4 3 6
R4 8 0
R4 4 2

1 0 K _ 04
2 0 0K _0 4
1 0 K _ 04
1 K_ 0 4
*1 K _ 0 4
1 0 K _ 04
*1 0 K _ 0 4
1 0 K _ 04

S _ GP I O
S A T A _ OD D _ P R S N T #
D G P U _ H P D _ I N TR #
S A T A _ OD D _ P W R GT
GP I O 3 4
C R I T _T E M P _ R E P #_ R
DG P U_ P W RO K
SA T A _ DET # 4

BJ 4 6
V S S _ N C TF _ 2 2
BJ 5
V S S _ N C TF _ 2 3
BJ 6

V S S _N C TF _ 6

V S S _ N C TF _ 2 4

V S S _N C TF _ 7

V S S _ N C TF _ 2 5

V S S _N C TF _ 8

V S S _ N C TF _ 2 6

V S S _N C TF _ 9

V S S _ N C TF _ 2 7

V S S _N C TF _ 1 0

V S S _ N C TF _ 2 8

V S S _N C TF _ 1 1

V S S _ N C TF _ 2 9

V S S _N C TF _ 1 2

V S S _ N C TF _ 3 0

V S S _N C TF _ 1 3

V S S _ N C TF _ 3 1

V S S _N C TF _ 1 4

V S S _ N C TF _ 3 2

B3

C 2

B4 7

C 48

B D1

D 1

B D4 9

D 49

BE1
R1 9 4

*1 K _ 0 4

P L L _ OD V R _ E N

BE4 9

R2 0 1

1 0 0K _0 4

F D I _ OV R V L T G

BF 1

BJ 4 4
BJ 4 5

A4 6

NCTF

R4 6 2
R2 5 4
R4 6 1

E1
E4 9

BF4 9

F1
F49

C o u ga rP o i n t _ R e v _ 1 p0

1 3 , 1 4 , 1 5, 1 7 , 2 0 , 2 2, 2 3 , 2 4 , 2 5, 2 8 , 3 2 , 3 3, 3 5 , 3 9 V D D 3
2 , 3 , 5 , 1 9 , 20 , 3 5 , 3 7 1. 05 V S _ V T T
6, 1 9 , 3 4 1 . 8V S
2 , 3 , 8, 1 1 , 1 3 , 1 5, 1 7 , 1 9 , 2 0, 2 2 , 2 3 , 2 7, 2 9 , 3 1 , 3 2, 3 4 , 3 6 3 . 3V
3 , 9, 10 , 1 1 , 1 2, 13 , 1 4 , 1 5, 1 6 , 1 7 , 1 9, 2 0 , 2 3 , 2 4, 2 5 , 2 6 , 2 8, 2 9 , 3 0 , 3 1, 3 2 , 3 7 3 . 3V S

PCH/ GPIO, VSS_NCTF, RSVD B - 19

B.Schematic Diagrams

H O S T _A L E R T # 2

I C C _E N #

1 . 5 K _ 1 %_ 0 4

R 47 4

PEC I

S C L OC K / G P I O2 2

1 K _ 04

R 46 9

GP I O 7 0

R CI N#

B I OS _ R E C

*1 0 K _ 0 4

P C H _ GP I O 5 7

C 41

G P I O8

G P I O1 5

D G P U _ P W R OK

R4 6 5

S A T A _ OD D _ P W R GT

B4 1

C4

S A TA 4 G P / G P I O1 6

11/18
R4 8 4

C 40

L A N _P H Y _P W R _ C TR L / GP I O1 2
R3 1 4

O CP P E #

Internal GFX: Low (Default)
External GFX: High

V DD 3

B M B U S Y # / G P I O0

CPU/MISC

R1 8 0

GPIO

3. 3 V S

Schematic Diagrams

PCH/ POWER1
CougarPoint -M (POWER)

3 . 3V S
L1 7
H C B 1 0 05 K F -1 2 1 T2 0

layout? check
1 .0 5 VS

5 VS

P OW E R

U3 7 G

V C CA _ D A C_ 3 .3 V S

All VCCORE = 1.3A
C1 7 4

1 u_ 6 . 3 V _ Y 5 V _ 0 4

1 . 0 5 V S _ V C C A P L L _E XP

R 15 2

AA2 3
AC 2 3
AD 2 1
AD 2 3
AF 2 1
AF 2 3
AG 2 1
AG 2 3
AG 2 4
AG 2 6
AG 2 7
AG 2 9
AJ 2 3
AJ 2 6
AJ 2 7
AJ 2 9
AJ 3 1

* 2 0m i l _0 4

5

U 48
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC

CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO

RE [1 ]
RE [2 ]
RE [3 ]
RE [4 ]
RE [5 ]
RE [6 ]
RE [7 ]
RE [8 ]
RE [9 ]
RE [1 0 ]
RE [1 1 ]
RE [1 2 ]
RE [1 3 ]
RE [1 4 ]
RE [1 5 ]
RE [1 6 ]
RE [1 7 ]

1
OU T

V CC A DA C
U 47
V S S A DA C

C4 5 1

C4 5 2

C4 5 3

C5 3 9

C4 5 7

0. 0 1 u _1 6 V _ X 7R _ 04

0 . 1 u_ 1 0 V _ X5 R _0 4

1 0u _ 6 . 3V _X 5 R _ 0 6

*0 . 1 u_ 1 0 V _ X5 R _0 4

*2 2u _ 6 . 3 V _ X5 R _0 8

C4 5 9

3. 3 V S _ V C C A _ L V D

S H DN #

R 1 59

V C C A LV D S
A K 37

* 1u _ 6 . 3V _X 5 R _ 0 4
2

G ND

*A P L 5 6 03 -3 3 B

1mA

A K 36

IN
3

R 4 57
* 2 3. 7 K _ 1 % _0 4
4
SET

*2 0 m il _ 0 4

3 .3 VS

R 4 60

C1 5 6

V S S A LV D S

* 1 0K _ 1 % _ 04

1 . 8 V S _ V C C T X_ L V D

0 . 1 u_ 1 0 V _ X5 R _0 4
AM 3 7

L3 4
H C B 16 0 8 K F -1 2 1T 2 5

60mA

V C C T X _ LV D S [ 1 ]

.

AM 3 8
V C C T X _ LV D S [ 2 ]

C1 5 3

C1 5 0

C4 3 9

0. 0 1 u _1 6 V _ X 7R _ 04

0 . 0 1u _ 1 6V _X 7 R _ 0 4

2 2u _ 6 . 3V _X 5 R _ 0 8

APL5603-33B 6-02-56033-4C0
G9091-330T11UF 6-02-90913-4C0

1 .8 VS

A P 36
V C C T X _ LV D S [ 3 ]
A P 37

1 . 0 5 V S _ V C C A P L L_ E X P

V C C I O[ 2 8 ]
3 . 3V S
V C C A _ P LL _ E X P

BJ 2 2

266mA

V C C A P L LE XP
V3 3

layout? check

C4 2 4

AN 1 6

*1 0 u_ 6 . 3 V _ X5 R _0 6

AN 1 7

HVCMOS

Sheet 19 of 46
PCH/ POWER1

V C C T X _ LV D S [ 4 ]

AN 1 9

L31
* H C B 10 0 5 K F -1 2 1T 2 0

.

V C C I O[ 1 5 ]
V C C I O[ 1 6 ]
AN 2 1

1 .0 5 VS

V C C I O[ 1 7 ]

V C C 3 _3 [ 6 ]

C 14 9

C1 5 1

1 0 u _6 . 3 V _ X 5R _ 06

1 u _6 . 3 V _ Y 5 V _ 0 4

1 u _6 . 3 V _ Y 5 V _ 0 4

V3 4
1 . 5V S _1 . 8 V S

V C C I O[ 1 8 ]
AN 2 7

C 17 1

C1 7 9
0 . 1 u_ 1 0 V _ X5 R _0 4

V C C 3 _3 [ 7 ]

AN 2 6

All VCCIO = 2.92A
C 1 47

AT1 6
V C C I O[ 1 9 ]

C1 5 2

160mA

V C C V R M[ 3 ]

AP2 1
1 u_ 6 . 3 V _ Y 5 V _ 0 4

V C C I O[ 2 0 ]

1 u_ 6 . 3 V _ Y 5 V _ 04
AP2 3

AT2 0

AP2 6
V C C I O[ 2 3 ]
AT 2 4
V C C I O[ 2 4 ]

42mA
1. 05 V S _ V T T

V C C D MI [ 1 ]

VCCIO

V C C I O[ 2 2 ]

DMI

V C C I O[ 2 1 ]
AP2 4

C1 4 6

2mA
A B 36
V CC CL K DM I

V C C C L K D MI

R1 6 4

* 2 0m i l _0 4

C 12 8

1 u _ 6. 3 V _ Y 5 V _ 0 4

1 . 05 V S

1 0 u_ 6 . 3 V _ X5 R _0 6

AN 3 3
V C C I O[ 2 5 ]
3 . 3V S

AN 3 4

AG 1 6
V C C I O[ 2 6 ]

266mA

V C C D F T E R M[ 1 ]

DFT / SPI

BH 2 9
V C C 3_ 3 [ 3 ]

C1 4 4

1 .5 VS_ 1 .8 VS

0 . 1 u _1 0 V _ X 5R _ 04

160mA

AP1 6
V CC V RM [2 ]

1 . 0 5 V S _ V C C A P L L _F D I
R4 2 1

1 .0 5 V S

*0 _0 4

11/01

BG 6
V c cA F D I P L L

1 . 0 5S _ V C C _ D MI
1 . 0 5V S _V TT

AU 2 0
V CC DM I[2 ]

R 14 9

V _ N V RA M _ V CC Q

1. 8 V S

R1 4 0

3. 3V S

CougarPoint power supply range

*2 0 m il _ 0 4

AJ 1 6
V C C D F T E R M[ 3 ]

R 14 1

*0 _ 0 4

Min
1.00V
1.43V
1.71V
3.14V
4.75V

C 16 0
0 . 1 u_ 1 0 V _ X5 R _0 4

AJ 1 7
V C C D F T E R M[ 4 ]
V C C ME 3 . 3 V
R 43 9

V C C I O[ 2 7 ]

42mA

190mA
AG 1 7

V C C D F T E R M[ 2 ]

AP1 7

FDI

B.Schematic Diagrams

1 .0 5 VS

1 u _ 6. 3 V _ Y 5V _ 0 4

CRT

C 1 78

1 u _ 6 . 3V _Y 5 V _0 4

VCC CORE

C 15 8

1 0u _ 6 . 3V _X 5 R _ 0 6

LVDS

C1 6 8

U 39

1mA

V1
VCC S PI

20mA

3. 3 V S 3 . 3 V
*0 _ 0 4

11/03
R 44 0

*0 _ 0 4

R 66 6

0 _0 4

Voltage
1.05V
1.5V
1.8V
3.3V
5V

Max
1.10V
1.58V
1.89V
3.47V
5.25V

3 . 3 V _M

*2 0 m il _ 0 4
C o u g arP oi n t _ R e v _ 1 p0

C 44 6
1 u _6 . 3 V _ Y 5 V _ 0 4

1. 05 V S

1 .5 VS

1. 8 V S

1 . 5 V S _ 1 . 8V S

R1 4 3
R1 4 8
R1 4 7

B - 20 PCH/ POWER1

*0 _ 04
*2 0 mi l _ 04
*0 _ 04

13 , 1 5 , 2 5, 2 6 , 3 2
20
1 1 , 1 2, 2 0 , 2 6 , 30 , 3 1 , 3 2, 3 7 , 3 8
2 , 3 , 8 , 1 1, 1 3 , 1 5 , 17 , 2 0 , 2 2, 2 3 , 2 7 , 29 , 3 1 , 3 2, 3 4 , 3 6
3 , 9, 10 , 1 1 , 1 2, 1 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 2 0 , 23 , 2 4 , 2 5, 2 6 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 7
6, 1 8 , 3 4
3 0 ,3 2
2, 3, 5 , 1 8 , 2 0, 3 5 , 3 7
13 , 1 4 , 1 5, 2 0 , 3 2

3. 3 V _ M
1. 5 V S _ 1 . 8 V S
5V S
3. 3 V
3. 3 V S
1. 8 V S
1. 5 V S
1. 0 5 V S _ V T T
1. 0 5 V S

Schematic Diagrams

PCH/ POWER2
CougarPoint - M (POWER)

CougarPoint power supply range
Voltage
1.05V
1.5V
1.8V
3.3V
5V

1 . 0 5 V S _ V C C A _C L K
L 36
* H C B 1 00 5 K F -1 2 1T 2 0

Max
1.10V
1.58V
1.89V
3.47V
5.25V

1 . 05 V S
R4 5 2

V DD 3

0_04

P OW ER

U3 7 J
A D4 9

C1 9 4

11/18

N2 6
V CC A CL K

0 . 1 u_ 1 0 V _X 5 R _ 0 4

3mA

C 1 90
L 16
H C B 1 0 0 5K F -12 1 T 20

*0 . 1 u _1 0 V _ X 5R _0 4

P C H_ V C CDS W

V C C3 _ 3

W243 1117

266 mA

C 1 87

1 0u _ 6 . 3 V _X 5 R _ 0 6

1 u _ 6 . 3V _ Y 5V _ 0 4

DC P SUSB Y P

V C C I O [ 3 2]
V C C I O [ 3 3]

T3 8

B H2 3
AL 2 9

C 2 00

C1 7 3

P 24

V C C I O [ 3 4]

1 u _ 6 . 3V _ Y 5V _ 0 4
AA2 6

V CC A S W [4 ]
AA2 7
V CC A S W [5 ]
AA2 9
V CC A S W [6 ]
AA3 1
V CC A S W [7 ]
A C2 6

Note: C1289- STUFFED ONLY FOR CPT INTERPOSER;
UNSTUFF FOR CPT

V CC A S W [8 ]
A C2 7
V CC A S W [9 ]
A C2 9
V CC A S W [1 0 ]
A C3 1
V CC A S W [1 1 ]
A D2 9
V CC A S W [1 2 ]
A D3 1
V CC A S W [1 3 ]
W21
V CC A S W [1 4 ]
W23
W24
W26
W29

C2 0 1

0 . 1 u _ 10 V _ X 5R _ 04

W31
W33

1 . 0 5V S _V C C A _ A _ D P L

Clock and Miscellaneous

1 u_ 6 . 3 V _ Y 5 V _ 04

V CC A S W [3 ]

V CC A S W [1 5 ]

V 5R E F _ S U S

2 2 u _6 . 3 V _ X 5R _ 08

1 u_ 6 . 3 V _ Y 5 V _ 04

* 20 m i _l 0 4

1. 0 5 V S

M2 6 + V 5 A _ P C H _ V C C 5R E F S U S

1mA

*0 _ 04
0_ 0 4

R 24 2

10 _ 0 4

C 20 3

0. 1 u _ 10 V _ X 5 R _ 0 4

16mA

R 4 24

A N2 4

C4 2 6

2 2 u _6 . 3 V _ X 5R _ 08

1 u_ 6 . 3 V _ Y 5 V _ 04

C 1 64

C 1 63

1 u _ 6. 3V _ Y 5V _ 0 4

55mA

1u _ 6 . 3V _ Y 5V _ 0 4

D1 1
C

N2 2

10 _ 0 4

C 20 2

97mA

V C C S U S 3 _ 3[ 3]

V CC A S W [1 9 ]

AA1 6
V C C 3 _ 3[ 8]

V C C 3 _ 3[ 2]

V C C I O [ 1 2]
Y4 9

1mA

C 4 03

C4 1 2

C4 1 3

4 . 7 u _6 . 3 V _ X 5R _ 06

*0 . 1 u _1 0 V _ X 5R _0 4

*0 . 1 u _1 0 V _ X 5R _ 04

C 4 60

C4 6 2

C4 6 1

R2 7 5
3 .3 VS

0 . 1 u_ 1 0 V _X 5 R _ 0 4

0 _ 06 0 3

C1 8 6
1u _ 6 . 3 V _Y 5 V _0 4

T3 4

C1 8 1
0. 1u _ 1 0V _ X 5 R _ 0 4

C 19 3
0 . 1 u _1 0 V _ X5 R _0 4

C1 8 0
0 . 1u _ 1 0V _ X 5 R _ 0 4

A J2
+V 1 . 0 5 S _ S A T A 3

L15
H C B 1 6 08 K F -1 2 1 T2 5

All VCCIO=2.92A

.

C1 6 6

C 15 9

1u _ 6 . 3V _Y 5 V _0 4

* 10 u _ 6. 3 V _ X 5R _ 06

1 . 05 V S

A H1 3
A H1 4

11/18
AF1 4

BF4 7

V CC
V CC
V CC
V CC

I O[ 7 ]
DIF F C L K N[1 ]
DIF F C L K N[2 ]
DIF F C L K N[3 ]

AK1
V C C A P L LS A T A
AF1 1

1 . 5V S _1 . 8 V S

V C C V R M[ 1]
A C1 6

R2 5 8

* 0_ 0 6

R2 5 9

* 0_ 0 6

R2 7 6

0_06

A C1 7
C1 6 7

A D1 7
V C C I O[ 4]

1u _ 6 . 3V _Y 5V _0 4

T2 1
DC P SUS[1 ]
DC P SUS[2 ]

V CC RT C

1. 5V

11/18

1 . 0 5V S

DC P SS T

V _ P RO C_ IO

VDD 3 3 .3 V

1 . 0 5V S

V1 6

BJ 8

3 . 3A _ 1 . 5 A _ H D A _I O

L33
* H C B 10 0 5 K F -1 21 T 2 0
1 . 05 V S _ V C C A P L L _ S A TA 3

V C C I O[ 2]

1 .01 A

V C C A S W [ 2 2]

C o u g ar P oi n t _ R e v _ 1p 0
1 u _ 6. 3 V _ Y 5V _ 0 4

V DD 3

266mA

V C C I O[ 6]
V CC A DP L L A

A2 2

RT CV C C

11/18

1 u _6 . 3 V _ X 5R _ 04

V C C I O [ 1 3]

B D4 7

T1 7
V1 9

Sheet 20 of 46
PCH/ POWER2

W 16

AF1 3

MISC

C1 8 2

0. 095
0. 055
1 (mA )
0. 06

V C C 3 _ 3[ 1]

V CC A S W [2 0 ]

CPU

1 . 0 5 V S _V TT

1.0 5
1.0 5
3.3
1.8

V CC A S W [1 8 ]

RTC

W243 1117

V C CS S T
0 . 1 u _ 10 V _ X 5R _ 04
+ V 1 . 0 5M _ V C C S U S
* 1 u_ 6 . 3 V _ X5 R _0 4

V cc SSC
V cc DIF FC LK N
V cc ALV DS
V cc TX_ LV DS

V CC A S W [1 7 ]

1 . 05 V _ M
V 21

V C C A S W [ 2 3]
V C C A S W [ 2 1]

HDA

1 u_ 6 . 3 V _ Y 5V _0 4

C1 9 1

2 (mA )
0. 19
0. 097
1 (mA )
0. 16
0. 02

5 VS

P 22

V C C 3 _ 3[ 4]

V CC S S C
C 15 5

3.3
1.8
3.3
3.3
1.5
1.0 5

V C C S U S 3 _ 3[ 5]

A G3 3

1 .0 5 VS

+ V 1 . 0 5M _V C C S U S

V cc DSW 3_ 3
V cc DFT ER M
V cc Sus 3_ 3
V cc Sus HD A
V cc VRM
V cc ClK DM I

V C C S U S 3 _ 3[ 4]

V C C I O[ 3]

* 0 _0 4

0. 08
0. 08
1. 3
0. 042
2. 925
1. 01
0. 020

11/03

P 20

1 . 0 5V _L A N _M
R 6 37

1.0 5
1.0 5
1.0 5
1.1
1.0 5
1.0 5
3.3

3 .3 V S

V C C S U S 3 _ 3[ 2]

DC P RT C

11/03

V cc ADP LL A
V cc ADP LL B
V cc Cor e
V cc DMI
V cc IO
V cc ASW
V cc SPI

R B 75 1 S -4 0 C 2
A

R 26 3
N2 0

N1 6

AF1 7
AF3 3
AF3 4
A G3 4

1 (mA )
1 (mA )
1 (mA )
0. 266
1 (mA )

11/19

VD D3

V 5 RE F

SATA

C 4 22

* 2 2u _ 6 . 3V _ X 5 R _ 0 8

1.0 5
5
5
3.3
1.0 5

+ 5 V _ P C H _V C C 5R E F S U S

1mA

P 34

V CC A S W [1 6 ]

V CC A DP L L B
1 . 05 V S

C 4 49

S0 Ic cm ax C urr en t (A )

V _C PU_ IO
V 5R EF
V 5R EF_ Su s
V cc 3_3
V cc ADA C3

D C P S U S [ 4]
V C C S U S 3 _ 3[ 1]

V CC V RM [4 ]

80mA
80mA

1. 1V S _ V C C A _ B _ D P L

V D D3
V D D5

* 0 _0 4
L35
H C B 1 0 0 5K F -12 1 T 20

3 .3 V

* 1u _ 6 . 3V _ X 5 R _ 0 4

V C C I O[ 5]
+V C C R T C E X T

C4 2 7

R1 9 6

A N2 3 + V C CA _ US B S US C1 5 4

1. 5 V S _ 1 . 8 V S

C 4 23

R 45 6
R B 75 1 S -4 0 C 2
A
R 45 4

D1 0
C
T2 6

V CC A S W [2 ]

C 1 83

11/18

V C C S U S 3 _ 3 [ 1 0]
V C C S U S 3 _ 3[ 6]

PCI/GPIO/LPC

1 u _ 6. 3V _ Y 5V _ 0 4

0 . 1 u_ 1 0 V _ X5 R _0 4

V 24

AA2 4
2 2u _ 6 . 3V _X 5 R _ 0 8

C 19 7

0. 1 u _ 10 V _ X 5 R _ 0 4

AA1 9
AA2 1

0 _ 06 0 3

C1 8 4

V 23
V C C S U S 3 _ 3[ 9]

V CC A S W [1 ]
C4 3 8

R2 7 4

T2 4
V C C S U S 3 _ 3[ 8]

V C C I O[ 1 4 ]

DC P SUS[3 ]

DC P S US

97mA

V ol tag e Ra il V olt ag e

V CC S US H DA

T1 9

P 32

1 3 , 1 4 , 15 , 1 7 , 18 , 2 2 , 2 3, 2 4 , 2 5, 2 8 , 3 2, 33 , 3 5 , 39 V D D 3
2 7 , 3 2 , 33 , 3 5 V D D 5
2 5 , 32 , 3 5 1 . 05 V _ L A N _ M
32
1 . 05 V _ M
1 3 3 . 3A _ 1 . 5 A _ H D A _I O
19
1 . 5 V S _1 . 8 V S
1 3, 1 5 R T C V C C
2 3 , 27 , 3 1 , 32 , 3 4 , 3 5, 3 6 5 V
1 1, 1 2 , 1 9 , 26 , 3 0 , 31 , 3 2 , 3 7, 3 8 5 V S
2 , 3 , 8 , 11 , 1 3 , 1 5, 1 7 , 1 9, 2 2 , 2 3 , 27 , 2 9 , 31 , 3 2 , 3 4, 3 6 3 . 3 V
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 6 , 17 , 1 8 , 1 9, 2 3 , 2 4, 2 5 , 2 6 , 28 , 2 9 , 30 , 3 1 , 3 2, 3 7 3 . 3 V S
3 , 6 , 8 , 9 , 10 , 2 7 , 3 2, 3 4 1 . 5 V
1 3 , 14 , 1 5 , 1 9, 3 2 1 . 0 5V S
2 , 3 , 5 , 18 , 1 9 , 3 5, 3 7 1 . 0 5V S _ V T T

W243 1117

16mA
3 . 3 A _ 1. 5 A _ H D A _ I O

11/01
C 20 4

0 . 1 u_ 1 0 V _X 5 R _ 0 4
0 . 1 u_ 1 0 V _ X5 R _ 0 4

PCH/ POWER2 B - 21

B.Schematic Diagrams

*1 u _ 6. 3 V _ X 5 R _ 04

A ll V CC AS W=1 .0 1A

* 2 20 u _ 6. 3 V _ 6 . 3 *4 . 2

VD D3
T2 9

V C C S U S 3 _ 3[ 7]
V C C A P L LD MI 2

AL 2 4
C 1 61

11/18

T2 7

+ V C C A P L L _C P Y _ P C H

1 1/01

1 . 0 5 V _M

V1 2

T2 3

C1 7 6

1 . 05 V S

+C 4 36

1u _ 6 . 3V _Y 5V _0 4

V C C 3 _3 [ 5 ]

11/01

1 . 0 5V S L 3 2
H C B 1 0 0 5K F -12 1 T 20

C1 9 2

P 28
V C C I O [ 3 1]

L 30
* H C B 1 00 5 K F -1 2 1T 2 0

2 2 u _6 . 3 V _ X 5R _ 08

1. 0 5 V S
P 26

V C C I O [ 3 0]
V CC DS W 3 _ 3

3. 3 V S

C 4 41

All VCCIO=2.92A

V C C I O [ 2 9]

T1 6

USB

Min
1.00V
1.43V
1.71V
3.14V
4.75V

Schematic Diagrams

PCH/ GND
CougarPoint -M (GND)

B.Schematic Diagrams

U37I

Sheet 21 of 46
PCH/ GND

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

CougarPoint_Rev_1p0

B - 22 PCH/ GND

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF 10
AF 12
AD14
AD16
AF 16
AF 19
AF 24
AF 26
AF 27
AF 29
AF 31
AF 38
AF4
AF 42
AF 46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

U37H
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
CougarPoint_R ev _1p0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[ 100]
VSS[ 101]
VSS[ 102]
VSS[ 103]
VSS[ 104]
VSS[ 105]
VSS[ 106]
VSS[ 107]
VSS[ 108]
VSS[ 109]
VSS[ 110]
VSS[ 111]
VSS[ 112]
VSS[ 113]
VSS[ 114]
VSS[ 115]
VSS[ 116]
VSS[ 117]
VSS[ 118]
VSS[ 119]
VSS[ 120]
VSS[ 121]
VSS[ 122]
VSS[ 123]
VSS[ 124]
VSS[ 125]
VSS[ 126]
VSS[ 127]
VSS[ 128]
VSS[ 129]
VSS[ 130]
VSS[ 131]
VSS[ 132]
VSS[ 133]
VSS[ 134]
VSS[ 135]
VSS[ 136]
VSS[ 137]
VSS[ 138]
VSS[ 139]
VSS[ 140]
VSS[ 141]
VSS[ 142]
VSS[ 143]
VSS[ 144]
VSS[ 145]
VSS[ 146]
VSS[ 147]
VSS[ 148]
VSS[ 149]
VSS[ 150]
VSS[ 151]
VSS[ 152]
VSS[ 153]
VSS[ 154]
VSS[ 155]
VSS[ 156]
VSS[ 157]
VSS[ 158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

Schematic Diagrams

New Card, Mini PCIE
NEW CARD(Port 3)

10 /2 9

MINI CARD WLAN

V D D 3 3 . 3V

20 mil

R6 8 5
R6 8 6

0 _ 06
* 0_ 0 6

1125

C 47 2
0 . 1 u _1 6 V _ Y 5 V _ 04

1125
R6 0 5

15 , 2 4 , 27 P C I E _ W A K E #

11/18

R 4 90
V D D3
R 6 80
3 .3 V
1 4 W L A N _ C L K R E Q#
1 4 CL K _ P CIE _ M INI#
1 4 C L K _ P C I E _M I N I

0_ 0 4

1 0 K _ 04
* 1 0K _ 0 4

J _ MI N I 1
1
3
5
7
11
13
9
15

W AKE#
CO E X 1
CO E X 2

3 . 3V A U X _0
1 . 5 V _0
U I M _P W R
U I M_ D A T A
U I M_ C L K
U I M_ R E S E T
U I M_ V P P

C L K R E Q#
REF C L K REF C L K +
GN D 0
GN D 1

G ND5

2
6
8
10
12
14
16

R 55 2

* 0_ 0 4

R 49 1

1 0 K _0 4

B T _S B D #

V D D3
8 0 CL K

28

3 IN1

28

4
W243 1117 ? ? 3.2

KEY
21
27
29
35
23
25
31
33

28
W L A N _ D E T#
14 P C I E _ R X N 3 _ W L A N
1 4 P C I E _R XP 3_ W L A N
1 4 P C I E _T X N 3 _ W L A N
1 4 P C I E _ T XP 3_ W L A N

2 8 , 29

B T _E N

1125
R199 , R204 , R498 ? ? 0_04 for Vpro
Wake up on WLAN Function

14
14
14

R4 9 4
V DD 3
3 .3 V

C L _C L K 1
C L _D A T A 1
C L _R S T #1
VDD 3

2 8 ,2 9

B T _E N

14

B T _S B D #

*0 _ 04

R 6 81
R 6 82

0_04
* 0 _0 4

R 1 99
R 2 04
R 4 98
R4 9 9

CL _ CL K _ 1
* 0 _0 4
* 0 _0 4
CL _ DAT A _ 1
CL _ RST # _ 1
* 0 _0 4
* 1 0K _ 0 4

R5 0 1

0 _0 4

R5 5 3

*0 _ 04

17
19
37
39
41
43
45
47
49
51

GN D 2
GN D 3
GN D 4
GN D 1 1
PET n 0
PET p 0
P ERn 0
P ERp 0
R e s e rv ed 0
R e s e rv ed 1
GN D 1 2
3 . 3V A U X _ 3
3 . 3V A U X _ 4
GN D 1 3
R e s e rv ed 2
R e s e rv ed 3
R e s e rv ed 4
R e s e rv ed 5

G ND6
G ND7
G ND8
G ND9
G N D 10
W _ D I S A B LE #
P E R S E T#
S MB _ C L K
S MB _ D A T A
U S B_ DUS B_ D+
3 . 3V A U X _1
1 . 5 V _1
1 . 5 V _2
3 . 3V A U X _2
LE D _ W W A N #
L E D_ W L A N#
LE D _ W P A N #

18
26
34
40
50
20
22
30
32
36
38
24
28
48
52
42
44
46

W L A N _ E N 2 8, 2 9
B U F _P LT _ R S T # 1 7, 2 4 , 2 5, 2 7 , 2 8
U S B _D #
U S B _D

R 35 7
R 35 6

B T _ D E T # 2 8, 2 9
U S B _P N 2 1 7
U S B _P P 2 1 7

*1 0 mi l _0 4
*1 0 mi l _0 4
R 48 9

R6 8 4

0_ 0 4

VD D3

1125

*0 _0 4

3 .3 V
W L A N_ L E D # 2 9

8 8 91 0 -5 20 4 M-0 1
1228 D02

B T _S B D #

3, 6, 8 , 9 , 1 0, 2 0 , 2 7, 3 2 , 3 4
1 9, 3 0 , 3 2
2, 3 , 8 , 1 1 , 13 , 1 5 , 17 , 1 9 , 20 , 2 3 , 2 7, 2 9 , 3 1, 3 2 , 3 4, 3 6
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 17 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 6 , 2 8, 2 9 , 3 0, 3 1 , 3 2, 3 7
13 , 1 4 , 15 , 1 7 , 18 , 2 0 , 23 , 2 4 , 2 5, 2 8 , 3 2, 3 3 , 3 5, 3 9

1. 5 V
1. 5 V S
3 .3 V
3 .3 VS
V D D3

New Card, Mini PCIE B - 23

B.Schematic Diagrams

Sheet 22 of 46
New Card, Mini
PCIE

Schematic Diagrams

CCD, 3G, TPM
MINI CARD 3G(Port 6)
3. 3 V S

3G POWER

3 .3 V

R 5 09

*0 _0 6

3 G_ 3 . 3V

C
R
R
G
G

3. 3V A U X_ 0
1 . 5V _ 0
U I M _P W R
U I M_ D A T A
U I M_ C L K
UIM _ RE SE T
U I M_ V P P

LK R E Q#
EF CL K EF CL K +
ND0
ND1

2
6
8
10
12
14
16

60 mils
U I M_ P W R
U I M_ D A TA
U I M_ C LK
U I M_ R S T
U I M_ V P P

C2 0 9

R 51 2

* 0 _0 6

>48 mil

C2 8 7

C5 0 0

22 0 u _6 . 3 V _ 6. 3 *6 . 3 *4 . 2

10 u _ 10 V _ Y 5 V _ 0 8

3 G_ R
C 5 07

+

C2 1 2
0 . 1u _ 16 V _ Y 5 V _ 0 4

3 G _3 . 3 V

Q 30
A O3 4 1 5
S
D

>48 mil
C 48 3
R5 1 5
0 . 1 u _1 6 V _ Y 5 V _0 4

0 . 1u _ 16 V _ Y 5 V _ 0 4

1 0 _0 6

R5 2 0

0 . 1 u_ 1 6V _ Y 5V _ 0 4

4

1 00 K _ 04

GN D 5
W243 1117 ? ? 3.2

D

7
11
13
9
15

W AKE#
C OE X 1
C OE X 2

0_06

G

1
3
5

J _ 3 G1

R 51 1

R 5 19

B.Schematic Diagrams

28

17
19
37
39
41
43
45
47
49
51

3 G_ 3 . 3V

Sheet 23 of 46
CCD, 3G, TPM

C2 4 2

C2 6 7

0 . 1u _ 16 V _ Y 5 V _ 0 4

10 u _ 10 V _ Y 5 V _ 08

G ND2
G ND3
G ND4

GN D 6
GN D 7
GN D 8
GN D 9
G ND1 0

G ND1 1
PET n 0
PET p 0
P E R n0
P E R p0

W _ DIS AB L E #
P ERS ET #
S MB _ C L K
S M B _ DAT A
U S B _D USB _ D+

R es e rv e d0
R es e rv e d1
G ND1 2
3 .3 V A UX _ 3
3 .3 V A UX _ 4
G ND1 3
R es e rv e d2
R es e rv e d3
R es e rv e d4
R es e rv e d5

3. 3V A U X_ 1
1 . 5V _ 1
1 . 5V _ 2
3. 3V A U X_ 2
LE D _ W W A N #
L E D_ W L AN#
LE D _ W P A N #

33 0 K _0 4

Q3 5
MT N 7 0 02 Z H S 3

G

2 8 3 G _P W R _ E N

S

D

18
26
34
40
50

S

35
23
25
31
33

3 G_ D E T #

Q3 3
MT N 70 0 2Z H S 3

G

KEY
21
27
29

From H8 default HI

20
22
30
32
36
38

3G _E N

28

SIM CONN

U S B _ P N4 1 7
U SB_ PP4 1 7

24
28
48
52
42
44
46

3G _3 . 3 V
U I M _P W R

R 50 3

*4 . 7 K _0 4

U I M_ D A TA

C2 3 5

3G _ 3. 3 V

0 . 1u _ 16 V _ Y 5 V _ 0 4
C2 8 6

J _S I M1

+

M P C E C -S 0 0F 1 -T P 0 0

2 20 u _ 4V _ V _ A

R5 0 4
*1 0 mi l _0 4

1228 D02
U I M _C L K
U I M _R S T
U I M _P W R

UIM _ C

C 3
C 2
C 1

L OCK
( TO P V IE W)
U I M _C LK
U I M _R S T
U I M _P W R

U I M_ D A TA
U I M _V P P
U I M_ G N D

C 7 U I M _D
C6
C5

OPE N
C 4 8 9 C 1 7 7 06 6 1-1

S I M L OC K

R4 8 8
*1 0 mi l _0 4
U I M _D A T A
U I M _V P P

C4 7 0

C4 6 9

C 47 1

*2 2 p_ 5 0V _N P O_ 0 4

*2 2 p_ 5 0V _N P O_ 0 4

* 22 p _5 0 V _ N P O _0 4

*2 2p _ 5 0V _ N P O_ 04

3 . 3V S

TPM 1.2
As se rte d befo re en te ring S3
L PC r ese t timing :

C5 0 8

C2 8 5

C2 9 4

C3 0 0

0 . 1u _ 16 V _ Y 5 V _ 0 4

0 . 1u _ 16 V _ Y 5 V _ 0 4

0 . 1u _ 16 V _ Y 5 V _ 0 4

1u _ 1 0V _ Y 5V _ 0 6

CCD

L PCPD# ina cti ve to L RST# ina ct ive 3 2~96 us
U 28
13 , 2 8
13 , 2 8
13 , 2 8
13 , 2 8

26
23
20
17

L P C_ A D0
L P C_ A D1
L P C_ A D2
L P C_ A D3

21
17 P C LK _ T P M
1 3 , 28
3 , 17
1 3 , 28
15

L P C _ F R A ME #
P L T _R S T #
SE R IRQ
P M _C LK R U N #
R 6 42

1 5 S 4_ S T A T E #
V DD 3

L CL K
22
16
27
15
* 0_ 0 4

R7 1 9

TP M _ LP C P D #

28

T P M_ B A D D

9

HI: ACCESS
L OW: NORMAL ( Inte rnal PD)

L F RAM E #
L RE S E T #
S ER IRQ
CL K R UN #

VSB
C2 8 2

GP I O
G P I O2

6
2

R6 4 0

*0 _0 4

3 . 3V S

R6 4 1

0_ 0 4

V DD 3

V IN
V IN

V O UT

EN

G ND

2

XTAL I

14

XTAL O

8
T ESTI

4
11
18
25

C 5

C 4

0 . 1 u _1 6 V _ Y 5 V _ 04

1 u _ 6. 3 V _ Y 5 V _ 04

1 u _ 6. 3 V _ Y 5 V _ 04

1

5

J _C C D 1

T P M3 0 0 4
T P M3 0 0 5

13

W243 1117

4
3

XT AL O
ND_ 1
ND_ 2
ND_ 3
ND_ 4

C 6

*1 0 0K _0 4

0 . 1u _ 16 V _ Y 5 V _ 0 4

PP

G
G
G
G

R1 1

G5 2 43 A

28

C C D _E N
17
17
28

XT A L I

NC _ 1
NC _ 2
NC _ 3

48 mil

1

MJ_CCD1

3

*1 u _ 6. 3 V _ Y 5 V _ 04

T ES T B I/BA DD

T P M 30 0 1 1
T P M 30 0 2 3
T P M 30 0 3 12

HI: 4E/ 4F H
T PM _BADD L OW: 2E/ 2F H

C2
5

5 V _ CC D

U4 1
4
5

TPM

7

1228 D02

T PM _PP

VD D1
VD D2
VD D3

L PCPD #

1 0 K _ 04
TP M _P P

5V

L AD0
L AD1
L AD2
L AD3

10
19
24

USB _ P N5
U S B _P P 5
C C D _ D E T#

CC D_ DE T #

X7
M C -1 4 6_ 3 2 . 76 8 K H z

1
2

6 -22 -3 2R7 6- 0B4

C 3 05

8 52 0 5-0 5 0 01

From H8 default HI

C 30 2

1 8 p _5 0 V _ N P O_ 0 4

1 8 p _5 0 V _N P O_ 0 4

S L B 9 6 35 T T
R3 4 9
P C LK _ T P M

C 2 92

X TA L O

P C LK _ T P M1
X TA L I
*3 3_ 0 4

Co -l ayo ut X 7, X8

*1 0p _ 5 0V _ N P O_ 06
3 . 3V S

T P M_ L P C P D #

R 6 43

*1 0K _0 4

T P M_ P P

R 3 41

*1 0K _0 4

T P M_ B A D D

R 3 48

10 K _ 1 %_ 0 4

R 3 52

*1 0K _1 % _0 4

1
2

4
3

X8
*1 T J S 12 5 D J 4 A 42 0 P _ 32 . 7 6 8K H z

B - 24 CCD, 3G, TPM

6- 22 -32 R7 6-0 B2
6- 22 -32 R7 6-0 BG

1
2
3
4
5

13 , 1 4, 15 , 1 7, 1 8 , 2 0, 2 2 , 2 4, 2 5 , 2 8, 3 2 , 33 , 3 5 , 39 V D D 3
2 , 3, 8 , 1 1, 13 , 1 5, 1 7 , 1 9, 2 0 , 2 2, 2 7 , 2 9, 3 1 , 32 , 3 4 , 36 3 . 3 V
3 , 9 , 10 , 1 1 , 12 , 1 3 , 14 , 1 5 , 16 , 1 7, 18 , 1 9, 2 0 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 31 , 3 2 , 37 3 . 3 V S
2 7 , 3 1, 3 2 , 34 , 3 5 , 36 5 V

Schematic Diagrams

Card Reader/LAN JMC261C
S D _C L K

*1 0p _5 0V _N P O_ 04
SD _ C LK

R 4 48

11 24

MS _I N S #

1K _0 4

S D _W P

C 1 65
C 17 0
0 1. u_ 16 V_ Y 5V _0 4 2. 2 u_ 6. 3V _X 5R _ 06

0 104 D02

U 36

Car d R ead er Pull Hi gh/ Low
Res ist ors

DV DD

R 16 2

*2 0m li _0 4

DV DD

R 15 6

*2 0m li _0 4

3 .3 V _LA N _ C

11 24

R 14 4

*2 0m li _0 4

U 35

(>20mil )
C 17 7

C 44 8

10 u_ 6. 3V _ X5R _ 06
P in #3 3

0. 1u _1 6V _Y 5 V _04
Pi n#3 3

8

V CC

6
5

WP

S CL
S DA

4

A0
A1
A2

GN D

7
MP D

R 2 16

1
2
3

10 K_ 04

R 2 17

*4. 7 K_ 04

C 4 40

0. 1 u_1 6V _ Y 5V _0 4

*A T2 4C 02 B N

VD D 3

JMC261 C
(LQFP 64)

R 14 2

3 . 3V S
V C C _ C AR D

3. 3V S

(>2 0mil)

(>20mil)

(>20mil)

MP D
LA N _ PC I E _W A KE #
LA N _ SC L
LA N _ SD A

C 199

C 1 98

C 4 43

10u _6 . 3V _X 5R _ 06
P in #32

0 . 1u _1 6V _Y 5 V_ 04
P in #3 2

* 10u _6 . 3V _Y 5 V_ 06
P in# 31

C 4 42

BU F _ PL T_ R ST # 17 , 22 , 25, 2 7, 2 8

C P PE N

112 4

R 19 0

V DD3

R 4 31

1 1 /02
*20 mil _0 4

I S ON _2 51 CR 19 1

3 . 3V _L A N _C

S D _W P

0 . 1u _16 V _Y 5V _ 04
P in #3 1
3. 3 V_ LA N _ C

V DD3

*0_ 06

112 4
3 . 3V _L AN _ C

* 100 K _0 4

S D _C D #
R 4 34
P C IE _ WA K E#

15 , 22 ,2 7 P C I E_ WA K E #
PCIe Differential
Pairs = 100 Ohm

A

112 4

LA N X I N
LA N X OU T

R E XT _C

V D D R EG
(>20mil)

V DDRE G

10K _ 04

D1 6

1
2
3
4
5
6
7
A V D D 12 _7
*20 mil _0 4 8
9
10
11
12
AV D D 1 2_1 3 1 3
14
MD I O13
15
M D I O7
16
C R _ C D 1N

JMC 2 61 _C

R 20 7
*28 mi _l 06
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V D D R EG
V CC3 V
P WR C R
TE S T
MPD
WA K EN
L AN _ LE D 2
C R _L ED
R S TN
C P P EN
GN D
VD D I O
MD I O6
MD IO 1 2
MD IO 1 4
C R _ C D 0N

C

L A N _P C I E_ WA K E #

LA N _P C I E _W A KE # 2 8

*R B 75 1S -40 C 2

Sheet 24 of 46
Card Reader/LAN
JMC261C

4 IN 1 SOCKE T SD/ MMC/MS /MS Pr o

A V D D 12 _1 3

1 124

C 1 39

0 . 1u _16 V _Y 5 V_ 04
P in #7

0 . 1u_ 16 V_ Y 5V _ 04
P in #13

A V D D 12 _5 2

A V D D 12 _5 5

*0_ 04

R 4 27

*20 mi l_ 04

A V D D 12 _62

C 43 3
C 43 4

1 1/0 2

A V D D 12 _7

C 1 57

C 1 45

C 1 36

0 . 1u _16 V _Y 5 V_ 04
P in #5 2

0 . 1u_ 16 V_ Y 5V _ 04
P in #55

0 .1 u_ 16 V_ Y 5V _0 4
P in# 62

*1 0u _6. 3 V _X5 R _0 6
P in# 7
R ese rv ed

2

*1M_ 04
X 10

3
C 1 34

C 1 48

0 . 1u _16 V _Y 5 V_ 04
P in #4 3

0 . 1u_ 16 V_ Y 5V _ 04
P in #43

C 43 1

0 . 1u_ 16 V_ Y 5V _ 04

0 22 4

0103 D0 2
3. 3 V_ LA N _C

C 45 0

C 1 35

C 1 89

C 4 37

0P .in1u_#5916 V_ Y 5V _ 04

.1 u_216 V_ Y 5V _0 4
P0 in#

0P 1.in#u_2116 V_ Y 5V _0 4

P la c e all c ap a c ito rs clo s e d to ch ip .
T h e s u b s c rip t in ea c h CA P in cic a te s th e pin
n u mb e r o f JM C2 5 1/ JM C 2 61 th a t s h o u dl b e
clo s e d t o .

R3. 2_1 2_31

SD _ D 0
SD _ D 1
SD _ WP
SD _ C LK
SD _ D 3
MS_ I N S#
SD _ D 2
SD _ D 0
SD _ D 1
SD _ B S

J_ C A R D -R EV 1
CD_ S D
D A T 2_S D
C D / D A T 3_S D
C MD _ S D
V S S _S D
V D D _ SD
C L K _S D
V S S _S D
D A T 0_S D
D A T 1_S D
W P _S D
V S S _MS
V C C _ MS
S C L K_ MS
D A T 3_M S
I N S _MS
D A T 2_M S
S D I O/ D A T0 _MS
D A T 1_M S
B S _MS
GN D
V S S _MS
GN D
MD R 01 9-C 0 -104 2

P2 2
P2 3

11 24

C 4 32
2 2p _50 V _N P O_0 4

0. 1u _1 6V _Y 5 V _0 4
Pin #2

? ? ? ? P IN 6?

C 1 95

VD D 3

*10 u_ 6. 3V _X 5R _ 06

P C 1 02

P C9 9
V C C _C A R D

V C C _C A R D

C 4 78

C 4 81

C 4 80

*0 . 1u_ 16 V_ Y 5V _ 04

* 0. 1u _1 6V _Y 5 V_ 04

*0 . 1u _16 V _Y 5 V_ 04

1. 2V

V DD3

2A

P in #2

0 . 1u _1 6V _Y 5V _ 04

C 1 33

V C C _ C AR D

P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15
P 16
P 17
P 18
P 19
P 20
P 21

4

6-22-25R00-1B4
6-22-25R00-1B5

P*1in0u#5_69. 3V _X 5R _ 06
R es er ved

R 49 6
*7 5_0 4

0 . 1u_ 16 V_ Y 5V _ 04

U2 0

11 24

R 72 3
15 0_0 6

C 4 79

For JMC251 C

2
1
*F S X5 L_ 25MH z
2 2p_ 50 V_ N P O_0 4

3. 3V _ LA N _C

SD _ C LK
C 4 82

R 7 24
1 50 _0 6

LA N XI N

1

FS X5 L_ 25 MH Z
X9

11 24

V C C _ C AR D

PC I E _R X P4 _GL A N 1 4
P C IE _ R XN 4 _GLA N 14

P C I E _T XN 4 _GLA N 14
P C I E_ TX P4 _GL A N 1 4
C L K _P C I E_ GLA N 14
C L K_ PC I E _ GLA N # 14

LA N XOU T
R 4 28

V C C _C A R D

0 . 1u_ 10 V _X7 R _0 4
0 . 1u_ 10 V _X7 R _0 4

SD _ C D #
SD _ D 2
SD _ D 3
SD _ B S

Card Reader
Power

MS _I N S #

R 1 36

PC I E _R X P _4_ GLA N
PC I E _R X N _4 _GL AN

C 4 45

3. 3V _ LA N _C

DV DD

3. 3 V_ LA N _C
C 4 35

D VD D R 14 6
*20 mi l_ 04

A V D D 12 _7

R 14 5

12 K_ 1%_ 04

P R 11 5
0_ 04

5
9
7

VI N
VI N
POK

1 u_ 10 V_ Y 5V _0 6
V C N TL

6

1A

4

DV DD

VOU T
3

8
1

EN

VOU T

GN D

VF B

2

PR 1 16
1. 6K _1 %_ 04
PC 9 8

A X 66 1 5E S A
82p _5 0V _N P O_ 04

Ne ar Car dre ade r CO NN

G S71 13
6 -02 -07 113 -320
A X66 10
6 -02 -06 610 -320

P R 114
2. 4 9K _1 %_0 4
12 28 D0 2

1 3, 1 4, 15 , 17 ,1 8, 2 0, 22 , 23 ,2 5, 2 8, 32 , 33 3, 5, 3 9 V D D 3
3, 9, 1 0, 11 , 12 ,1 3, 1 4, 15 , 16 ,1 7, 1 8, 19 , 20 ,2 3, 2 5, 26 , 28 ,2 9, 3 0, 31 , 32 ,3 7 3 3. V S
3 , 6, 8, 9 1, 0, 2 0, 27 , 32 ,3 4 1 5. V
23 , 27 ,3 1, 3 2, 34 , 35 ,3 6 5 V

Card Reader/LAN JMC261C B - 25

B.Schematic Diagrams

MD I O10
MD I O9
MD I O8
V DD
V I P_ 1
V I N _1
A V D D 12
V I P_ 2
V I N _2
GN D
A V D D 33
V I P_ 3
V I N _3
A V D D 12
V I P_ 4
V I N _4

RE X T
A VD D 3 3
XN
I
XOU T
C LK N
CL K P
A V D D 12
RX P
RX N
GN D
T XN
T XP
AV D D 1 2
MD I O13
M D I O7
C R _ C D 1N

DV DD

49
50
51
MD I O8
A V D D 12_ 52 52
L AN _ MD I P0 _C 53
L AN _ MD I N 0_ C 54
A V D D 12_ 55 55
L AN _ MD I P1 _C 56
L AN _ MD I N 1_ C 57
58
59
L AN _ MD I P2 _C 60
L AN _ MD I N 2_ C 61
A V D D 12_ 62 62
L AN _ MD I P3 _C 63
64

*4. 7K _ 04

L A N _S D A

MD I O1 1
LA N _L E D 0
LA N _L E D 1
IS ON
GN D
V DDIO
V DDO
MD I O5
MD I O4
MD I O3
MD I O2
MD I O1
MD I O0
F B 12
GN D
LX

R 158

*4. 7K _ 04

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

V C C _C A R D

R 4 25
L A N _S C L R 4 26

10/29
DV DD

S WF 2 520 C F 4- R 7M-M

1124
3. 3V S V D D 3

DV DD

L3 7

For JMC251/261 only
R E GLX

S D _C D #

10 K_ 04

IS ON _ 25 1C

*4. 7 K_ 04

R 493

3 . 3V _L AN _ C
S D X C _P OW ER
S D _C L K _C
S D _B S
S D _D 3
S D _D 2
SD _ D 1
SD _ D 0
DV DD

SD X C _P OW ER
R 497

(>20mil)
R E GLX

22 _1% _0 4

1 229 D 02 (W 240 HU )
3. 3 VS

3. 3V _ LA N _C

S witching Regulator
c lose to PIN33

C 4 54 ne ar P in #41

.

JM C2 61 C

Schematic Diagrams

INTEL LAN 82579
3.3 V_M

3. 3V_M

C3

C8

0.1u_16 V_0 4

0.1 u_1 6V_ 04

3. 3V_LAN

R12

*s ho rt _0 8

0324-J
change short
0324-J
add

1. 0M_LAN

R 273

*shor t_08

0324-J
change short

C 10

C3 2

0 .1u_16V_04

10 u_6. 3V_ X5R _06

C590

C 591

0. 1u _16 V_0 4

10u _6.3V_X5R _06

3. 3VS VDD 3

R6 10
*10K_04

R61 1
10K_04

11/1 9

U 47

0.1u_10 V_X7R _04 PC I E_R XP6 _C _GLAN
0.1u_10 V_X7R _04 PC I E_R XN 6_C_GL AN

1 4 PC IE_RXP6_IG LAN
14 PCI E_R XN 6_IG LAN

41
42

1 4 PC IE_TXP6_ IGL AN
14 PCI E_TXN 6_ IGL AN

11/18

14
14

VDD 3
1 8 PM_LANPH Y_EN

R 638
R 639

SML0_C LK
SML0_D ATA
R613

10K_04

R615

0_04

R616

*1 0K_ 04

0_04
0_04

1 0K_04
1 0K_04

LAN_JTAG_ TD I
LAN_JTAG_ TD O
LAN_JTAG_ TMS
LAN_JTAG_ TC K

X16
2

0_04

32
34
33
35
9
10

LAN_XTAL_ OU T
LAN_XTAL_ IN

25MH z
1

LAN _TEST_EN

C593

27P_ 50V_N PO_04

RES_BIAS
C 592

PETp
PETn
PERp
PERn

MD I_ PLU S1
MD I_MI NU S1
MD I_ PLU S2
MD I_MI NU S2
MD I_ PLU S3
MD I_MI NU S3

SMB_ CLK
SMB_ DATA

VC T
RSVD _VC C3P3_1
RSVD _VC C3P3_2
VDD 3P3_I N

LAN _D ISABL E_N
VD D3P3_OU T

26
27
25

R 617
R 618

3. 3V_ LAN

28
31

3

11/18

R619

38
39

PE_C LKP
PE_C LKN

30
12

LED 0
LED 1
LED 2

JTAG_ TD I
JTAG_ TD O
JTAG_ TMS
JTAG_ TC K
XTAL_ OU T
XTAL_ IN

LED

C185
C215

MD I_ PLU S0
MD I_MI NU S0

PCIE
MDI

14 CL K_PC IE_I GLAN
14 C LK_PCI E_IG LAN #

CL K_R EQ_N
PE_R ST_ N

JTA G

Sheet 25 of 46
INTEL LAN 82579

44
45

SMBUS

48
36

14 IGLAN _C L KREQ#
1 7,22, 24 ,27, 28 BUF_PLT_RST#

2 7P_50V_NPO_0 4

B.Schematic Diagrams

1. 05V_LAN_M

VDD 3P3_15
VDD 3P3_19
VDD 3P3_29
VDD 1P0_47
VDD 1P0_46
VDD 1P0_37
VDD 1P0_43
VDD 1P0_11
VDD 1P0_40
VDD 1P0_22
VDD 1P0_16
VD D1P0_8

R621

1K_04

3. 01 K_1 %_0 4

LAN_MD I P0
LAN_MD I N0

17
18

LAN_MD I P1
LAN_MD I N1

20
21

LAN_MD I P2
LAN_MD I N2

23
24

LAN_MD I P3
LAN_MD I N3

6
1
2
5
4

RBI AS

CTRL_1 P0

LAN_MD IP0 26
LAN_MD IN 0 2 6
LAN_MD IP1 26
LAN_MD IN 1 2 6
LAN_MD IP2 26
LAN_MD IN 2 2 6
LAN_MD IP3 26
LAN_MD IN 3 2 6

+VCT_L AN
R 612
R 614

4. 7K_04
4. 7K_04

+V3. 3M_LAN _O UT

3. 3V_LAN

C4 67 1u_ 6. 3V_X5 R_ 06

15
19
29
1 .0M_LAN
47
46
37

R 24

*sh ort_ 08

43
11

NOTE
1.0M_LAN

40
22
16
8

Will Work at 0. 95V to 1.15V
1. 0M_LAN

TEST_EN

VSS_ EPAD
R 620

13
14

7

R 17
R 16

*0_ 06
*0_ 06

49

8257 9LM/ V

13,1 5, 19 ,26, 32 3.3 V_M
13 ,14, 15,1 7, 18,20, 22 , 23,24, 28,3 2, 33 ,35, 39 VD D3
2 0, 32,35 1.05V_LAN_M
3 ,9,1 0, 11 ,12, 13,14,1 5, 16,17, 18 ,19, 20,2 3, 2 4, 26 ,28, 29,3 0, 31,32, 37 3.3 VS

B - 26 INTEL LAN 82579

Schematic Diagrams

LAN (82579), SATA HDD, ODD
1 L25

GIGA LAN (82579)

2

4
3
*W C M 2 01 2 F 2 S -S H O R T
1 L2 6

L29

W243 1117
3. 3 V _ M

25
25
25
25

L A N_ M DIP 0
L A N_ M DIN0
L A N_ M DIP 1
L A N_ M DIN1

25
25
25
25

L A N_ M DIP 2
L A N_ M DIN2
L A N_ M DIP 3
L A N_ M DIN3

L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD

IP 0
IN0
IP 1
IN1

12
11
9
8

L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD

IP 2
IN2
IP 3
IN3

6
5
3
2

T D4 +
T D4 T D3 +
T D3 -

M X 4+
M X 4M X 3+
MX 3 -

T D2 +
T D2 T D1 +
T D1 -

MX 2 +
M X 2MX 1 +
MX 1 -

T CT 4
T CT 3
T CT 2
T CT 1

MC
MC
MC
MC

13
14
16
17

L MX 1 +
L MX 1 L MX 2 +
L MX 2 -

19
20
22
23

L MX 3 +
L MX 3 L MX 4 +
L MX 4 -

2
J _ RJ 1

4
3
*W C M2 0 12 F 2 S -S H OR T
1 L27

DL M
DL M
DL M
DL M

X1 +
X1 X2 +
X2 -

1
2
3
6

DL M
DL M
DL M
DL M

X3 +
X3 X4 +
X4 -

4
5
7
8

2

DA +
DA DB +
DB -

GN D 1
GN D 2

sh i el d
sh i el d

GN D

R7 5
*0 _ 0 4

10
7
4
1
C5 4

C3 4 3

C3 4 2

C3 4 1

0 . 0 1u _ 1 6V _ X 7 R _ 0 4

*0 . 0 1u _ 1 6V _ X 7 R _ 0 4
*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
*0 . 0 1u _ 16 V _ X 7 R _ 04

T4
T3
T2
T1

4
3
*W C M 2 01 2 F 2 S -S H O R T
1 L2 8

15
18
21
24

2

DC +
DC DD +
DD P J S -0 8 S L 3B

4
3
*W C M2 0 12 F 2 S -S H OR T

W240HU
W250HU

0101D02

PJS-08SL3B
PJS-08SO1B-1

G S T 50 0 9 LF
MC
MC
MC
MC

T_ 1
T_ 2
T_ 3
T_ 4

R4 0 2
R3 9 9
R3 9 7
R3 9 4

7 5_ 1 %
7 5_ 1 %
7 5_ 1 %
7 5_ 1 %

_0 4
_0 4
_0 4
_0 4

NM CT _ R

C3 3 5
10 0 0 p_ 2 K V _ X 7R _1 2

Sheet 26 of 46
LAN (82579), SATA
HDD, ODD

SATA HDD

SATA ODD
Zero Power ODD

J _ HD D1
S1
S2
S3
S4
S5
S6
S7

C4 8 7
C4 8 6

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

SA T A_ RXN 0
SA T A_ RXP0

C4 8 5
C4 8 4

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

S A TA T X P 0 1 3
S A TA T X N 0 1 3
S A TA R X N 0 1 3
S A TA R X P 0 1 3

3 . 3V S

1.5A

1A

S1
S2
S3
S4
S5
S6
S7

C4 3 0
C4 2 8

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

C4 2 5
C4 2 1

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

S A TA T X P 2 1 3
S A TA T X N 2 1 3
S A TA R X N 2 1 3
S A TA R X P 2 1 3

?? ?? ?? ?? ?

P1
P2
P3
P4
P5
P6

C5 2 1

S A T A _ OD D _ P R S N T # 18
S A T A _ OD D _ D A # 1 7

C4 1 1

10 u _ 10 V _ Y 5 V _ 08
C2 1 0

0 . 1u _ 1 6V _ Y 5 V _ 0 4

0 . 1u _ 1 6V _ Y 5 V _ 0 4

1u _ 6 . 3 V _Y 5 V _ 0 4
C4 7 5

C4 7 4

C4 7 6

ALLTOP-C166N5-12205-L
1-162-100561

C4 7 3

H D D _N C 1
H D D _N C 2
H D D _N C 3

U4 2
1

C4 1 0

C 40 8

C4 0 4

+C 3 93

0 . 1u _ 1 6V _ Y 5V _ 0 4

1 u _6 . 3 V _ Y 5 V _ 04

V OU T

V IN
V IN

G ND

EN

2

* 10 0 u _6 . 3 V _ B 2
0 . 1u _ 1 6V _Y 5V _0 4

C5 2 2

0 . 1u _ 1 6V _ Y 5V _ 0 4
*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

5 V S _ OD D

C 18 5 5 3-1 1 3 05 -L
H D D _N C 0

A L L T OP -C 16 6 N 5 -1 2 20 5 -L
P IN G ND 1 ~ 2 = G ND

W240HU
W250HU

G ND 1
A+
AG ND 2
BB+
G ND 3

DP
V_ 5 0
V _5 0 _ 1
MD
G ND 4
G ND 5

5V S

*0 . 1 u _1 6 V _ Y 5 V _0 4

P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5

5 VS

J _ OD D 1
SATA_ T XP0
S A T A _ T X N0

4
5
3

S A TA _O D D _P W R GT 1 8

G 52 4 3 A

1 0u _ 1 0V _Y 5V _0 8
R5 5 5

10 0 K _ 04

+ C 2 08
*1 00 u _ 6. 3 V _ B _ A
5V S
3. 3 V _ M
3. 3 V
1. 5 V
3. 3 V S

1 1 , 12 , 1 9 , 2 0, 3 0 , 3 1, 3 2 , 3 7, 3 8
1 3 , 15 , 1 9 , 2 5, 3 2
2 , 3 , 8 , 11 , 1 3 , 15 , 1 7 , 19 , 2 0 , 22 , 2 3 , 2 7, 2 9 , 3 1, 3 2 , 3 4, 3 6
3 , 6 , 8 , 9, 1 0 , 2 0, 2 7 , 3 2, 3 4
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0 , 23 , 2 4 , 25 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 7

LAN (82579), SATA HDD, ODD B - 27

B.Schematic Diagrams

N
N
N
N

Schematic Diagrams

USB3.0 NEC, USB CHARGER
3. 3 V A

1. 0 5V

3. 3 V A

W/O U SB Cha rg er

L 65

.
C 7 77
0. 1 u_ 1 0V _ X5 R _ 04
0. 1 u_ 10 V _ X5 R _0 4
0 . 1 u_ 10 V _X 5 R _0 4

C7 7 8

C 78 0
5p _5 0 V _N P O_ 0 4
0 . 1u _1 0 V _X 5R _ 0 4
0 . 01 u_ 16 V _X 7 R _0 4

C

R B 7 51 S - 4 0C 2

Sheet 27 of 46
USB3.0 NEC, USB
CHARGER

A

3 9 2K _ 1% _0 4
1 1 /0 1

R 7 25
0_ 0 4 A U X D E T_ R
R 70 2
1 0K _ 04
1 3 U S B 30 _ SM I #

J2
J1
H1

1 0/ 28

P5

P1 3

D7

OC 2I B
OC 1I B

A UX DE T
PSEL
S MI B

P P ON 2
P P ON 1

U S B _ SP I _ S C L K M2
U S B _ SP I _ C E # N 2
U S B _ SP I _ S I
N1
U S B _ SP I _ S O M1

1 u_ 6 .3 V _ X5 R _ 04

LO W PO WE R R 72 2 =0 _0 4
NO R P OW ER R7 22 = *0 _0 4
AU XD E T _R

R 7 26

*0 _0 4

R 72 2

0 _0 4

K1 3
K1 4
J1 3
P4

S P IS CK
S P ICS B
S P IS I
S P IS O

U 3 TX D N 1
U 2 D M1
U 2D P 1
U 3R XD P 1

uPD7 20200

R 3. 2 12 _3

C1 4

R 70 4
1 00 _ 04
X 19
2

* FS X 8 L_ 24 . 00 0 MH z
1
W243 1117

11 /0 2
X 18
2

2 4. 0 00 MH z / 16 pF / + 30 pp m
1

C 7 98

C 79 9
2 0p _ 50 V _N P O _0 4

3

V C C _ T PS 2 54 0

B6

S S TX 2

A6
N8

S S TX 2#
U 2 D M2

P8
B8

U2 DP 2
S S RX 2

A8

S S R X 2#

G1 4
H1 3

G_ OC #

H1 4
J1 4

P P ON

B 10

S S TX 1

C 7 96

0 . 1 u_ 10 V _X 7 R _0 4

T XP 0 _R

A 10
N1 0

S S TX 1#
G_ D M0

C 7 97

0 . 1 u_ 10 V _X 7 R _0 4

T XN 0 _ R

P 10
B 12

G_ D P 0
S S RX 1

A 12

S S R X 1#

V D D5

5

*1 0K _ 04

7

R 5 65

*1 0K _ 04 A C _ I N

8

U S B _P N 1 _A
U S B _P P 1_ A

10

3 . 3V

14
GN D

E N/DS C

I L I M0

CT L 1

I L I M1

6

R 5 64

80 mil

11

D P _I N

I L I M_S E L
*10 K _ 04
*0_ 0 4

12
O UT
D M_I N

16

R 56 1

*17 . 8K _ 1 %_ 04

15

R 56 3

*40 . 2K _ 0 4

R 56 6

*0_ 0 4

R5 6 2

9
CT L 2

NC

CT L 3

F A U LT #

13

1 0K _ 04
G_ OC #

*TP S 2 54 0
Q37
*MT N 70 0 2Z H S 3

G
2 8, 3 9

A C _I N #

CTL 1

CL OS E TO C ON N EC TO R

CTL 2

M_ PQ FP16

CT L3 : 0

X

1-- ---> De dic ate d Cha rg in g Po rt , Aut o-d e tec t

CTL 1

CTL 2

CT L3 : 1

1

1- --- -> Ch ar g ing Do wn dtr ea m Por t, BC Spe c 1. 1

CTL 1

CTL 2

CT L3 : X

1

0-- ---> Sta nd ar d Dow nstr ea m Por t, USB 2.0 Mo de .

G ND
G ND
G ND
G ND

G ND

U 2P V S S

P 12 R 7 18
N1 2

G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G

ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND

R A/ RB , US B 3. 0 c om po ne nt s,
R E/ RF , RG
R C/ RD , RE /R F, R G

1 0 /2 9

RG
W/ o US B Ch a rg er P ow er

R 5 58

US B V CC
U GN D

ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND

W / US B 3. 0, W /o U SB C ha r ge r
W /o U S B3 .0 , US B Ch ar ge r

N1 1

U 3A V S S

G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G

R A/ RB , US B 3. 0 c om po ne nt s,
U SB C ha rg er c om p on en ts , RH

USB 3 .0/ PCH U SB 2.0 C o-l ayo ut

1. 6 K _1 % _0 4

X T1
X T2
C SE L

W / US B 3. 0, U SB C ha rg er

W/ U SB C ha r ge r Po we r

P 14
P 11
P9
P7
P2
P1
N1 3
N9
N7
N3
M1 3
M1 2
M1 1
M1 0
M9
M8
M7
M6
M5
M4
M3
L1 2
L1 1
L7
L6

U S B 30 V C C

0_ 0 6

RH
R 5 59

VC C _T P S 25 4 0

100 MIL

*0 _0 6

C 16 2

0 . 1u _ 16 V _Y 5 V _ 04

C 49 5

1 0 0u _6 . 3V _ B _B

J _U S B3 _ 1

12 28 D 02

TX P 0_ R

U S B_ P N 1 _A

4

U S B_ P P 1_ A

1

Diff. trace 90ohm

L 64

3

TX N 0 _R
U S B_ P N 1 _A _ R

2

U S B_ P P 1_ A _R
SS R X1

*W C M 20 12 F 2S -S H OR T

SS R X1 #

R 1 86

0_ 04

G_ D P 0

R 1 93

0_ 04

U SB _ P N 0

17

U SB _ P P 0

11 19 - 2

S H I E LD
S H I E LD

S H I E LD
S H I E LD

G ND1
G ND3

G ND4
G ND2

W2 4 0H U: 6 -2 1 -B4 A 1 0 -0 0 9
/2 n d: 6 -2 1 -B4 A 0 0 -0 0 9
W2 5 0H UQ: 6 - 2 1- B4 A2 0 -0 0 9

R C/ RD
17

S S T X+
VBUS
S S T XD G ND
D +
SSRX+
G ND_ D
SSRX-

U S B - 09 E C E B -S D 0 01
P C B F o ot p r i nt = U S B -C 19 00 5

R A/ RB
G_ D M0

9
1
8
2
4
3
6
7
5

R 1 97

*0_ 0 4

G_ D M0 _0

R 2 03

*0_ 0 4

G_ D P 0_ 0

PCH U SB2.0

C 12
C 13
D3
D4
D1 1
D1 2
D 13
D 14
E1
E2
E1 3
E1 4
F4
F6
F7
F8
F9
F1 1
F1 2
G1
G2
G6
G7
G8
G 9
G 11
G12
G1 3
H6
H7
H 8
H 9
H 12
J3
J4
J6
J7
J8
J9
J1 1
J 12
K3
K4
L1
L2
L3
L4

2 0p _ 50 V _N P O _0 4

A1
A2
A3
A4
A5
A7
A9
A1 1
A1 3
A1 4
B3
B4
B5
B7
B9
B1 1
B1 3
B1 4
C1
C2
C3
C1 0
C1 1

G_D P 0_ 0

D M _O
DP_ O

GN D
GN D
G ND
G ND
GN D
GN D
GN D
GN D
GN D
G ND
GN D
GN D
GN D
GN D
GN D
G ND
GN D
GN D
GN D
GN D
GN D
G ND
GN D
GN D
GN D
GN D
GN D
G ND
GN D
GN D
GN D
GN D
GN D
G ND
G ND
GN D
GN D
GN D
GN D
G ND
G ND
GN D
GN D
GN D
GN D
GN D
G ND

P6

U 43

4

D6
N1 4
M1 4

2

R 56 0
P P ON V D D 5
R 58 2
28 , 32 , 33 D D _ON

U 3R X D N 1

RRE F
U 2A V S S

01 03 D 0 2

G_D M0_ 0

St uf f
P ON R S TB
U 3 T XD P 1

C8 0 0

C 79 3

0 . 1 u_ 10 V _X 5 R _0 4
0 . 01 u _1 6V _ X7 R _ 04

U 2D P 2
U 3R XD P 2

P E RS T B
PEW AKEB
P E C R EQ B

1

IN

U2 A V DD3 3

H1 1
K1 1
K1 2
L8
V D D 10
V DD1 0
V DD1 0
V DD1 0

E 11
E 12

H3
H 4
L5
V DD1 0
V DD1 0
V DD1 0

E3
E4
V DD1 0
V DD1 0

V D D 10
V D D 10

C 8
C9
D8
D9
V DD1 0
V D D 10
V D D 10
VD D 10

C4
C5
C6
C7
D5
V DD1 0
V D D 10
V D D 10
VD D 10
V DD1 0

L 13
L14

L9
L1 0

N4
N5
N6
P3
V D D 33
V D D 33
VD D 33
V DD3 3

V DD3 3
V DD3 3

V D D 33
V D D 33

80 mil

U 3R X D N 2

H2
0 _0 4 P C I E _W A K E # _R K 1
K2

R7 0 1

USB 2.0 CO -LAYOU T? ? ? ? ? ? ? ?

R 70 8

*1 5 mi _l 0 6

3. 3 V

3. 3 V
NC5

U GN D
*N C _0 4
C8 1 0

5V
5V

1 .5 V

10 K _0 4
A U XD E T

U5 3
V IN
V IN
P OK

6

3A

V C N TL
V OU T

4

D

EN
R 70 6
* 0_ 04

Q52
G

C 8 01

C 80 2

1

GN D

VF B

2

R 71 0
C 80 6

AX6610

(15nF~ 48nF)
C 8 04
R 70 9

1 0u _ 10 V _Y 5 V _ 08
0 .1 u _1 6V _ Y 5 V _0 4

2 . 4 K_ 1 %_ 04

B - 28 USB3.0 NEC, USB CHARGER

75 0_ 1% _ 04
0 . 01 5 u_ 10 V _X 7 R _0 4

0 . 1u _1 6 V_ Y 5 V _0 4
C 80 3

U SB _ F LA S H 3

R 7 11

1 K _0 4

R 7 12

4 . 7K _ 04 U SB _ H OL D # 7

C 8 09

1u _6 . 3 V_ Y 5 V _0 4

*MT N 70 0 2Z H S 3

SI

C8 0 7

C 80 8

*1 0 U _1 0 V_ 0 8

1 0 u_ 10 V _Y 5V _ 08

5

U S B _S P I _ S I _R

R 71 3

47 _0 4

2

U S B _S P I _ S O_ R

R 71 4

15 _1 %_ 0 4 U S B _ SP I _ S O

1

U S B _S P I _ C E # _R R 71 5

15 _1 %_ 0 4 U S B _ SP I _ C E #

6

U S B _S P I _ S C L K_ R R 71 6

47 _0 4

SO
W P#

CE #
S CK

V OU T

8

VD D

1. 0 5 V

1 u_ 6. 3 V _Y 5V _ 04

3

6, 1 5, 2 8 , 32 SU S B#

8

C 8 05
5
9
7

R 70 7

4 7K _ 04
U5 2

R 70 5
10 K _0 4

0 . 1u _1 6V _ Y 5 V _0 4
U S B _S P I _ V D D _ 1

2A

R7 1 7

KBC_SPI_*_R = 0.1"~0.5"

512Kb it

? ? ? ? PIN6?
3 . 3V

S

B.Schematic Diagrams

P E RX P
P E RX N

11 24
1 7 2, 2 , 24 , 25 , 28 B U F _P L T _R S T #
1 5, 2 2, 2 4 P C E
I _ W A K E#
1 4 PC I EC LK R Q 2#
A U XD E T
D6 3
R 70 3
3 . 3V

V DD5

C 79 2

U 3 TX D N 2
U 2 D M2

3. 3 V

U S B _P P 1 _A

USB C har ger c omp one nt s

3 . 3V A

U 3 T XD P 2

P E T XP
P E T XN

U S B _P N 1_ A

0 _ 04

+

F2
F1

14 P C I E _T X P2 _ U S B 30
1 4 PC I E_ T XN 2 _ U S B 30

P E CL K P
P E CL K N

0 _ 04

R 55 7

S tandard -A

0 . 1u _1 0 V_ X 7R _ 0 4 D 2
0 . 1u _1 0 V_ X 7R _ 0 4 D 1

R 55 6

G_ D P 0_ 0

D

C 79 4
C 79 5

14 P C I E _R XP 2 _U S B 3 0
1 4 PC I E_ R X N 2 _U S B 3 0

U 3A V D D 3 3

1 4 C LK _ P C I E _U S B 3 0
14 C L K _P C I E _ U S B 30 #

V DD3 3
V DD3 3
V DD3 3

F3
G3
G 4

D 10
F1 3
F 14
V DD3 3
V DD3 3
V D D 33

B2
B1

G_ D M0 _0
C 7 79

C7 8 4
C7 9 0
0 . 01 u_ 1 6V _ X7 R _ 04
0 . 01 u _1 6V _ X7 R _ 04
C 7 82
C 78 6
C7 8 8
0 . 01 u_ 16 V _ X7 R _0 4
0 . 0 1u _1 6V _ X 7R _ 0 4
0 . 01 u _1 6V _ X7 R _ 04
C 78 3
C 7 89
0. 0 1u _ 16 V _X 7R _0 4
0. 0 1u _ 16 V _X 7R _0 4
C 78 1
C 78 5
C 78 7
C 7 91
0 . 0 1u _1 6V _ X7 R _ 04
0. 0 1u _ 16 V _X 7R _0 4
0 . 0 1u _1 6V _ X 7R _ 04
0. 0 1 u_ 16 V _X 7 R _0 4

U5 1

1 0 /2 9

RE /R F

C 77 6

17

C 77 5

H C B 1 60 8 KF - 1 21 T 25

0 . 1 u_ 10 V _X 5R _0 4

S

C 77 4

PPAD

3. 3 V

0. 1 u _1 6V _ Y 5 V _0 4

U S B _ SP I _ S I

U S B _ SP I _ S C L K

4
H OLD # V SS
MX 25 L5 1 21 E MC -2 0G

31
US B V CC
20 , 32 , 33 , 3 5 V D D 5
3 , 6 , 8, 9 , 10 , 20 , 32 , 3 4 1 . 5V
2 , 3, 8 , 11 , 13 , 15 , 1 7, 1 9, 2 0, 2 2, 2 3 , 29 , 31 , 32 , 34 , 3 6 3 . 3V
2 3 , 31 , 32 , 34 , 35 , 3 6 5 V

Schematic Diagrams

KBC-ITE IT81518
KB C _ A VDD

C 2 66

0 . 1 u_ 1 6 V _Y 5 V _0 4

C2 1 1

1 0 u _1 0 V _ Y 5 V _ 08

C2 6 4

0. 1 u _ 16 V _ Y 5 V _ 0 4

.

C 22 2

C 25 6

0 . 1u _ 1 6V _Y 5V _0 4

VD D3

L1 9
H C B 10 0 5K F -12 1 T 20

VDD 3

VDD 3

V DD3

C2 3 4

C 23 3

C2 3 2

R 2 99

0 . 1u _ 1 6V _ Y 5V _ 0 4

* 0. 1 u _ 16 V _ Y 5 V _ 0 4

*0 . 1 u _1 6 V _ Y 5 V _ 04

1 0 0 K _0 4

SM C_ B AT
SM D_ B AT

0 . 1 u _1 6 V _ Y 5 V _ 04
K B C _W R E S E T #

L21

E C_ V CC

H C B 1 0 0 5K F -1 2 1 T2 0

.

3 .3 V S

K B C _ A GN D

P CL K _ K B C

K B C _W R E S E T #

1124

1124

K B C_ B E E P

LOW ACTIVE
HIGH ACTIVE

3 G_ D E T #
CC D_ DE T #
MO D E L _ I D

R 32 8
*0 _ 04
R 67 2
*0 _ 04
R 6 73
* 0_ 0 4 L C D _ B R I G H T N E S S 24
25
28
2 9 L E D _S C R O L L#
29
29
LE D _ N U M#
30
29
LE D _ C A P #
31
2 9 L E D_ B A T _ CH G
32
34
2 9 L E D _B A T_ F U LL
29
L E D _P W R

R3 2 0

0_ 0 4

8 0P O R T _ D E T #

85
86
87
88
89
90

1 25
18
21

32
P W R _S W #
11 , 3 1
L ID_ S W #

33

P W R_ B T N#

12 02
* 0_ 0 4
22

1 10
1 11
1 15
1 16
1 17
1 18

S M C_ B A T
S M D_ B A T
R 67 9
*0 _ 04
R 67 8
*0 _ 04
R 60 6
0_ 0 4

3 G_ E N

15

66
67
68
69
70
71
72
73

B AT _ DET
B A T _ V OL T
AP_ KEY#

8 0 CL K

22
8 0C L K
22 , 2 9 B T_ D E T#
22
3 IN 1
3 1 W E B _ E MA I L #
31
T P _C L K
31
T P _D A T A
23

76
77
78
79
80
81

R 6 97

W LA N _ D E T #

1 08
1 09

3

74
A V CC

VBAT

VSTBY
VST BY
VSTBY
VST BY
VSTBY
VSTB Y

G A 20 / G P B 5
K B R S T #/ G P B 6 ( P U )
P W U R E Q # / GP C 7( P U )
L 8 0L L A T / GP E 7 ( P U )
E C S C I # / GP D 3 ( P U )
E C S MI # / GP D 4 ( P U )

DAC
G
G
D
D
D
D

P J0
P J1
A C 2 / GP J 2
A C 3 / GP J 3
A C 4 / GP J 4
A C 5 / GP J 5

IT8518

ADC
AD
AD
AD
AD
AD
AD
AD
AD

C 0 / GP I 0
C 1 / GP I 1
C 2 / GP I 2
C 3 / GP I 3
C 4 / GP I 4
C 5 / GP I 5
C 6 / GP I 6
C 7 / GP I 7

F L F R A ME # / GP G 2
F L AD0 /SC E #
F L A D 1/ S I
F L AD2 /SO
F L A D 3 / GP G 6
F L CL K /S CK
( P D )F L R S T# / W U I 7 / GP G 0/ T M
( P D )K S O1 6 / GP C 3
( P D )K S O1 7 / GP C 5

C L K 0 / GP B 3
D A T 0 / GP B 4
C L K 1 / GP C 1
D A T 1 / GP C 2
C L K 2 / GP F 6 ( P U )
D A T 2 / GP F 7 ( P U )

(
(
(
(
(
(
(
(

PWM
PW M
PW M
PW M
PW M
PW M
PW M
PW M
PW M

0 / GP A 0 (
1 / GP A 1 (
2 / GP A 2 (
3 / GP A 3 (
4 / GP A 4 (
5 / GP A 5 (
6 / GP A 6 (
7 / GP A 7 (

PU
PU
PU
PU
PU
PU
PU
PU

)
)
)
)
)
)
)
)

LK 0 / G
A T0 / G
LK 1 / G
A T1 / G
LK 2 / G
A T2 / G

P F 0(
P F 1(
P F 2(
P F 3(
P F 4(
P F 5(

0
1
2
3
4
5
6
7

( P D )W U I 5 / G P E 5
( P D )L P C P D # / W U I 6 / G P E 6

)
)
)
)
)
)

PWM/COUNTER
( P D )T A C H 0 / GP D 6
( P D )T A C H 1 / GP D 7
( P D )T MR I 0/ W U I 2 / GP C 4
( P D )T MR I 1/ W U I 3 / GP C 6

CIR

R I 1# / W U I 0 / GP D 0( P U )
R I 2# / W U I 1 / GP D 1( P U )

( P D )C R X / GP C 0
( P D )C TX / G P B 2

GP INTERRUPT

LPC/WAKE UP

G I N T / GP D 5 ( P U )

0 . 1 u_ 1 6 V _Y 5 V _0 4

0/ I D
1/ I D
2/ I D
3/ I D
4/ I D
5/ I D
6/ I D
1/ I D

WAKE UP

PU
PU
PU
PU
PU
PU

P W R S W / G P E 4( P U )

UART

)GP H
)GP H
)GP H
)GP H
)GP H
)GP H
)GP H
)GP G

( P D )E G A D / G P E 1
( P D )E G C S # / G P E 2
( P D )E G C L K / G P E 3

WAKE UP

R XD / GP B 0 ( P U )
T X D / G P B 1( P U )

PD
PD
PD
PD
PD
PD
PD
PD

EXT GPIO

PS/2
PS2 C
PS2 D
PS2 C
PS2 D
PS2 C
PS2 D

( P D )L 80 H LA T / G P E 0
( P D )R I N G # / P W R F A I L # / L P C R S T# / G P B 7

1
12
27
49
91
113
1 22

K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O

10 0
10 1
10 2
10 3
10 4
10 5
10 6

K B -S O 0
K B -S O 1
K B -S O 2
K B -S O 3
K B -S O 4
K B -S O 5
K B -S O 6
K B -S O 7
K B -S O 8
K B -S O 9
K B -S O1 0
K B -S O1 1
K B -S O1 2
K B -S O1 3
K B -S O1 4
K B -S O1 5

R 2 88

*1 0 mi l _ 04

CLOCK

10 K _ 0 4
*1 0K _0 4

R 31 2

P CL K _ K B C_ R

C 24 6

*1 0 p_ 5 0V _N P O_ 0 6

B A T _ V OL T

C 21 7

1u _ 6 . 3V _ Y 5V _ 0 4

A C _I N #

C 25 8

0. 1 u _ 16 V _ Y 5 V _ 0 4

1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24

V D D3

*1 0 _ 04

C o- la y SP I RO M
U3 1
8

V DD

S I
SO

K BC_ F L AS H

3

W P#

C E#
S CK

K B C _ H OL D #

7

H O LD #

VSS

5

K B C _S P I _S I _ R

2

K B C _S P I _S O _ R

1

K B C _S P I _C E # _R

6

K B C _S P I _S C L K _R

Sheet 28 of 46
KBC-ITE IT81518

4

MX 2 5 L3 2 0 6E
P C B F o o t p rin t = M-S O P 8 B

W243HWQ

1230 D02

C K 3 2K E
C K 3 2K

R6 9 8
R6 7 4
R3 0 6
R3 1 5
R6 7 5

82
83
84

* NC_ 0 4

6 , 15 , 2 7 , 32
1 5, 3 4

C2 8 8
0 . 1 u_ 1 6 V _ Y 5 V _ 04

0 _0 4
*0 _ 0 4
*0 _ 0 4
*0 _ 0 4
*0 _ 0 4

35
17

IC PP E#
S L P _ S US #
OC P P E #
SL P_ S5 #
S U S CL K

U3 0
VDD
R 36 0

1K _ 0 4
KB C_ F L A SH

3

4. 7 K _ 0 4
K B C _ H OL D #

7

47
48

1201

5
2
1
6

K BC_ S P I_ S I_ R
K B C _ S P I _ S O _R
K B C _ S P I _ C E #_ R
K B C _ S P I _ S C LK _R

R3 6 6
R3 5 5
R3 4 2
R3 5 9

4 7 _0 4
1 5 _1 % _ 04
1 5 _1 % _ 04
4 7 _0 4

K B C_ S P I_ S I
K B C_ S P I_ S O
K B C_ S P I_ CE #
K B C_ S P I_ S CL K

4
H OL D # V S S
*P M 2 5L D 0 1 0 C -S C E

KBC
KBC
KBC
KBC

_ S P I _S
_ S P I _S
_ S P I _C
_ S P I _S

I
O
E#
CL K

C3 0 3
C2 9 0
C2 8 4
C2 9 7

*
*
*
*

33 p _ 50 V _ N P O
33 p _ 50 V _ N P O
33 p _ 50 V _ N P O
33 p _ 50 V _ N P O

_ 04
_ 04
_ 04
_ 04

6-04-25010-A91
W243HVQ

C P U_ F A NS E N 3 1
H _ P R OC H OT _ E C 3
R3 3 0
0_ 0 4
R3 3 6
* 0_ 0 4

P MP C H _ P W R OK _ R

SI
SO
C E#
SCK

W P#
R 34 6

18
15
18
15
15

R S MR S T# 1 5
K B C _R S T # 18

12 0
12 4

KBC_SPI_*_R = 0.1"~0.5"

1M b it
8

P M _ P C H _ P W R OK 1 5
V C OR E _O N 3 7

A L L _S Y S _ P W R G D 1 1 , 1 5, 3 7
11 9
12 3

P ME #_ R

R3 2 9
R3 3 5
R3 3 1

*0 _ 0 4
*0 _ 0 4
0 _0 4

19

SW I#

11 2
2
12 8

1126 POWER
PM E#
17
L A N _P C I E _ W A K E # 2 4
15

C H G_ R S T 39
CK 3 2 K E
CK 3 2 K

R3 2 6
R3 2 7
X4
1
2
X5
1
2

*1 0 M_ 0 6

NB_ ENA VDD

11 , 1 6

V D D3
J _ 80 D E B U G 1
1
2
3
4
5

*M C -1 4 6_ 3 2 . 76 8 K H z
4
3
* C M -20 0 S _ 32 . 7 6 8K H z
4
3

0 _ 04

*0 _ 0 4

3 IN1
8 0 CL K
8 0 DE T #

R 3 53
1 0 K _ 04
1228 D02

8 8 26 6 -0 50 0 1

C 26 2
* 15 p _ 50 V _ N P O _ 04

L C D _ B R I GH TN E S S
K B C _A G N D

C 2 19

P C LK _ K B C

S U S _P W R _ A C K 15
BT_ EN
2 2, 2 9
BKL _ EN
11
H S P I_ CE # 1 3
H SP I_ SCL K 1 3
H S P I _ MS O 13
H S P I _ MS I 1 3
D D _ ON
2 7, 3 2 , 3 3

C2 6 5
*1 5 p _5 0 V _ N P O _0 4
B RIG HT NE S S

R2 9 2
R2 9 3

23

SU SB#
S U S C#

93
94
95
96
97
98
99
10 7

R 33 3

11

W 250 HU Q
W 270 HU Q

RB

1228 D02
C CD_ E N

W 240 HU

V D D3

1126 POWER

K B C _S P I _ S C LK

1 0K
RA

MO D E L _ I D

3 G_ P W R _E N 2 3

K B C _S P I _ C E #
K B C _S P I _ S I
K B C _S P I _ S O

X

X

11/02

4
5
6
8
11
12
14
15

K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7

1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24

56
57

E C _V S S

NC 2

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

J_ K B 1
*8 5 2 01 -2 4 05 1

W2 50H U

4
5
6
8
11
12
14
15

RB

10 K

V D D3

GPIO

SMBUS
SM
SM
SM
SM
SM
SM

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55

0 . 1 u _1 6 V _ Y 5 V _ 04

RA

V DD 3

0104 D02

FLASH

I T 8 5 18 E

C 25 0

K S O 0/ P D 0
K S O 1/ P D 1
K S O 2/ P D 2
K S O 3/ P D 3
K S O 4/ P D 4
K S O 5/ P D 5
K S O 6/ P D 6
K S O 7/ P D 7
K S O8 / A C K #
K S O 9/ B U S Y
K S O 1 0/ P E
K S O1 1 / E R R #
K S O1 2 / S LC T
K S O1 3
K S O1 4
K S O1 5

AVSS

39
SM C_ B AT
39
SM D_ B AT
1 5 , 32 , 3 5 P M_ S L P _ LA N #
15 , 3 2
S L P _M #
3, 1 8
H_ P E C I
2 , 14 S M C _ C P U _ TH E R M
2 , 14 S M D _ C P U _ TH E R M
1 8 S LP _M E _ C S W _ S E V #

14
1 26
4
16
20
23
15

B A T _D E T
B A T _ V OL T
AP_ KEY#
TH E R M _ V OL T
TO T A L_ C U R
3G _ D E T #
C C D _D E T #

1124

30

R3 0 0
R3 0 3

2 2 , 2 9 W LA N _ E N
30
K B C_ M UT E #
13
ME _ W E
31
C P U_ F A N
3 1 W E B _W W W #
15
SUS_ AC K #
39
39
31
2
39
23
23

K/B MATRIX

K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7

75

1124

0 _0 4
*0 _ 04

KS I0 /ST B #
K S I1 /AF D #
KS I2 /INIT #
K S I 3/ S LI N #
KSI4
KSI5
KSI6
KSI7

58
59
60
61
62
63
64
65

V1 .0

* 0. 1 u _ 10 V _ X 5R _ 04

MC-146 & CM200S
Co-layout

13 , 1 4 , 1 5, 1 7 , 1 8, 2 0 , 2 2, 2 3 , 2 4, 2 5 , 3 2, 3 3 , 3 5, 39 V D D 3
3 , 9 , 10 , 1 1 , 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 2 9 , 3 0, 3 1 , 3 2, 37 3 . 3 V S

KBC-ITE IT81518 B - 29

B.Schematic Diagrams

? EC Pin 78
? ? ? HI enable

LPC

J _K B 2
8 5 2 01 -2 4 05 1

W 24 0HU /W 27 0HU

W R ST #

11/18
GA 2 0

18
2 7 ,3 9
A C_ IN#
29
L E D_ A CIN
1 5 ,1 7 AC _ PRES EN T
1 5 P M_ P C H _P W R O K
18
S MI #
18
SCI #

L A D0
L A D1
L A D2
L A D3
L P CC L K
L F R A ME #
SE R IRQ
L P C R S T #/ W U I 4 / GP D 2 ( P U )

VSS
VSS
VSS
VSS
VSS
VSS
VSS

1 3 ,2 3
L P C_ A D 0
1 3 ,2 3
L P C_ A D 1
1 3 ,2 3
L P C_ A D 2
1 3 ,2 3
L P C_ A D 3
17
P C LK _K B C
13 , 2 3 LP C _ F R A M E #
1 3 ,2 3
S E RIRQ
17 , 2 2 , 24 , 2 5 , 27 B U F _ P LT _ R S T #

V CC

U 23
10
9
8
7
13
6
5
22

26
50
92
114
1 21
127

11

0. 1 u _ 16 V _ Y 5 V _ 0 4

24

J_KB1

M OD EL _ID

RN 1 0
1 0 K _ 8P 4R _0 4
BA T _ DET
4
5
3
6
AP_ KEY #
3 G_ D E T#
2
7
1
8
C C D _D E T #

C 2 38
1

C2 5 2

RN 1 1
2 . 2 K _ 8 P 4R _ 04
4
5
3
6
2
7
1
8

Schematic Diagrams

LED, MDC, BT
Bluetooth(Port8)
3 V_ BT
J _B T 1

Port 11

3 . 3V

17
U S B _P N 1 1
17
U S B _P P 11
2 2 , 28
B T _ DE T #

1
2
3
4
5
6

B T_ E N #

R 3 23

* 8 72 1 2-0 6 G0
* 1 0K _ 0 4

D

B T _ E N#

3 .3 V

S

LE D _ A C I N

LE D _ N U M # 28
S A TA _ L E D # 1 3

6 -5 2-5 20 01- 02 7

L E D _ B A T _C H G

3

BAT LED
D1 5

K P B -3 02 5 Y S G C

K P B -3 0 25 Y S GC

4

R 1

SG

D1 4

K P B -30 2 5 Y S GC

2

D 1

C

*1 0 mi l _ 04
B

W L AN_ EN

22 , 2 8

6 -5 2- 520 01 -0 27

B

R 36 1

R 3 63

R 3 64

2 2 0 _0 4

2 2 0_ 0 4

22 0 _0 4

2 2 0 _0 4

W240HU
W250HU

B T_ E N
B T _E N

E

R 3 62

Q 3
*D TC 1 14 E U A

L E D _ S C R OL L # 28

6 -52 -5 200 1- 02 7

? ?
? ? ?

2 2 ,2 8

Q 1
D TC 11 4 E U A

3 , 6 , 8 , 9, 1 0 , 2 0, 2 7 , 3 2, 3 4 1 . 5V
2 , 3 , 8, 1 1 , 1 3, 1 5 , 1 7, 1 9 , 2 0, 2 2 , 2 3, 2 7 , 3 1, 3 2 , 3 4, 3 6 3 . 3V
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 2 8 , 3 0, 3 1 , 3 2, 3 7 3 . 3V S

H1 5
M2
M-M A R K 1

M7
M6
M -MA R K 1 M -MA R K 1

M1
M-M A R K 1

M8
M -MA R K 1
H1 2
H 10
H 6 _ 3D 4 _4 H 6_ 3 D 4 _ 4

2
3
4
5

H2 4
1

9
8
7
6

2
3
4
5

MT H 3 1 5 D 1 11

H1 1
1

9
8
7
6

2
3
4
5

MT H 31 5 D 1 1 1

1

9
8
7
6

M TH 31 5 D 1 1 1

H 3
H4
C 1 11 D 1 1 1 N C 1 1 1D 11 1 N
M5
M -MA R K 1

M4
M-M A R K 1

M3
M -MA R K 1

2
3
4
5

H5
1

9
8
7
6

2
3
4
5

MT H 3 1 5 D 1 11
S1
S MD 80 X 80

2
3
4
5

1124 Del

H2 3
C6 7 D6 7

H8
C6 7 D6 7

H 1
H2
C 1 11 D 1 1 1 N C 1 1 1D 11 1 N

H9
1

9
8
7
6

2
3
4
5

MT H 31 5 D 1 1 1

9
8
7
6

MT H 3 1 5 D 1 11

H2 1
H 19
H 4 _ 0 B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7

H1 3

9
J _ T P1
1

6

1
2
3
4
5
6

M TH 31 5 D 1 1 1

2
3
4
5

H7
1

9
8
7
6

2
3
4
5

MT H 31 5 D 1 1 1

H2 5
1

9
8
7
6

H1 6
1

9
8
7
6

2
3
4
5

1

M TH 31 5 D 1 1 1

L ED_ PW R
L E D_ A CIN
L E D_ B A T _ F UL L
L E D_ B A T _ CHG

*8 5 2 01 -0 60 5 1
GN D

? ? P IN? ?
W240HU ? ? ?
W250HU ? ?

M TH 31 5 D 1 1 1

H2 2
2
3
4
5

MT H 3 1 5 D 1 11

B - 30 LED, MDC, BT

1

H 20
H 18
H 14
H 4_ 7 B 6 _0 D 3 _ 7 H 4 _7 B 6 _ 0D 3_ 7H 6_ 3 D 4 _ 4

1

H1 7
H 6 _ 0D 3 _7

H6

9
8
7
6

28

L E D _B A T_ F U LL 2 8

W L A N _L E D # 2 2

LE D _ C A P # 2 8

6 -52 -5 200 1- 02 7

28
28

POWER ON
LED

3

1

WLAN
LED

Y

4

2 20 _ 0 4

SG

2

*1 0 u _6 . 3 V _ X5 R _0 6

4

A

SCROLL
LOCK
LED

D5

3

E

C

CAPS
LOCK
LED

C

A

D4

R Y -S P 17 0 Y G3 4 -5 M

C

R Y -S P 17 0 Y G3 4 -5 M

C

D2

NUM
LOCK
LED

R Y -S P 17 0 Y G3 4 -5 M

D3

2 2 0 _0 4
R Y -S P 1 7 0 Y G3 4- 5M

A

A

HDD/ODD
LED

R 2

1

R7

2 20 _ 0 4

2

BT
LED

R6

3

2 2 0 _0 4
1

R 5

22 0 _0 4

Y

R4

2 2 0_ 0 4

C4 6 4

1

L E D _P W R

R 3

5 0m il

* 2 8m i _l 0 6

3 .3 V S

3 . 3V S

SG

3 . 3V S

4

3. 3 V S

2

3 . 3V S

3 V_ BT

R4 7 3

5 0mi l

Y

3 .3 V S

LED

C

Sheet 29 of 46
LED, MDC, BT

1

B.Schematic Diagrams

C 25 9
*1 8 0 p_ 5 0 V _N P O_ 0 4

Q 24
* MT N 7 0 0 2Z H S 3

BT_ EN G

Schematic Diagrams

AUDIO CODEC ALC269 VIA1802
.
t
n
e
n
o
p
m
o
C
5
7

A UD IO C OD EC
ALC269 VB
VT1802P

1 .5 V S

R 5 27

*0 _ 04

R 5 29

0 _0 4

DV DD _ IO

3 . 3 V S _A U D

5 VS
R 5 10

C5 1 3
1 0 u_ 1 0 V _Y 5 V _0 8
3 .3 VS

PV D D1 _ 2

C2 9 9
0 . 1u _ 1 6V _Y 5V _0 4

C 49 8
1 0 u _1 0 V _ Y 5 V _ 08

V er y clo se t o A ud io C ode c

C2 7 1
0. 1 u _ 16 V _ Y 5 V _ 0 4

3 . 3V S _ A U D
R5 6 7

L ay ou t No te :

* 28 m i _l 0 6

ALC269 ? ?
VT1802P ? ? ?

0_04

C4 9 9
* 10 u _ 10 V _ Y 5 V _ 0 8

C 2 81

C2 8 0

C2 8 3

0 . 1 u _1 6 V _ Y 5 V _ 0 4

10 u _ 10 V _ Y 5 V _ 0 8

0 . 1 u_ 1 6V _Y 5V _0 4

C 27 0
0. 1 u _ 16 V _ Y 5 V _ 0 4

5 V S _ A UD
L4 0
H C B 1 00 5 K F -1 2 1T 2 0
1
2

5V S

C 49 7

C 4 96

C5 1 0

C 50 9

C 49 4

0 . 1 u_ 1 6 V _Y 5 V _0 4

1 0 u _1 0 V _ Y 5 V _ 08

0 . 1u _ 1 6V _ Y 5V _ 0 4

1 0 u_ 1 0 V _Y 5 V _0 8

1 u _ 6. 3 V _ Y 5 V _ 0 4

5 VS

PD #

PD #

44
45

S P K OU T R SPK O UT R+

S

D

* 10 0 K _ 04

47
48

E A P D _ MO D E
S P DIF O

Q2 7
* B S S 1 38 _ N L

G

D MI C -D A T
D MI C -C L K

S

H D A _R S T #

2
3

25
38

L I N E 2- L
LI N E 2 -R
MI C 2- L
M I C 2 -R

S P K - RS P K - R+

13

D

H DA _ S Y NC

C 2 91

J D RE F
MO N O -OU T

G P I O0
G P I O1

MI C 1- L
M I C 1 -R

ANALOG

M TN 7 00 2 Z H S 3
S

13

H D A _S D I N 0

6
B I T -C LK
R3 5 4

3 3 _0 4

A Z _ S D I N 0 _R

8

A Z _ S Y N C_ R

10

S D A T A -I N

HD A _ RS T #

11

BEEP_ R

12

L DO _ CA P
MI C 1 -V R E F O -R
M I C 2 -V R E F O

M I C 1-V R E F O-L

G

R ESET #

2
13

H D A _S P K R

BEEP_ C

AVS S1
AVSS2

G ND

DV S S 2

H P -OU T- L
H P -O U T -R

20 K _ 1 % _0 4

MI C _S E N S E

14
15

L I N E 2 -L
L I N E 2 -R

R3 6 8

39 . 2 K _ 1 %_ 0 4

HP _ S E N S E

16
17

M IC2 _ L
M IC2 _ R

CB P
O PVEE

MI C _ S E N S E 3 1
H P _ S E N S E 31

R 36 5

C 30 8

4 . 7 K _ 04

1 0 0p _ 5 0V _ N P O_ 0 4

S E N S E -B
J DR E F
M ON O -OU T

21
22

M I C 1 -L _R C 3 0 6
M I C 1 -R _ R C 3 0 7

23
24

L I N E 1 -L
L I N E 1 -R

27

V R E F -A L C 2 6 9

28
30
29

L D O _C A P
M I C 1 -V R E F O-R
M I C 2 -V R E F O

R5 2 3
C 51 2

M IC1 _ L
M IC1 _ R

C 3 01

32
33

H E A D P H ON E -L
H E A D P H ON E -R

35

C B N -A L 2 69

36
34

C B P -A L C 2 6 9
O P V E E -A L C 2 6 9

0 . 1u _ 1 6V _ Y 5V _0 4

C 3 04

ALC269

2.2u;

2 . 2u _ 6 . 3V _X 5 R _ 0 6

VT1802P

C 2 98

10u

1 0u _ 6 . 3V _ X 5 R _ 0 6

ALC269
VT1802P

HE A DP HO NE - L 3 1
HE A DP HO NE - R 3 1
C 27 2

Sheet 30 of 46
AUDIO CODEC
ALC269 VIA1802

A U DG

1 20 7

2.2u
NC

AUD G

2. 2 u _ 6. 3 V _ X 5 R _ 06

S P K OU TL +

C2 7 9

L24
F C M1 0 05 K F -1 2 1 T0 3
1
2

A L C 2 6 9 Q-V B 6 -GR

J_ S P K L 1
S P K O U T L + _L

A U DG

S P K OU TL -

4 . 7 K _ 04

17/16

2

I N T _ MI C

R1 2 8

1 K _ 04

C 2 95

*1 u _ 6. 3 V _ Y 5 V _ 0 4

8 5 20 4 -0 20 0 1
* 18 0 p _5 0 V _ N P O _0 4

S P K O U T L -_ L

R5 6 8

R130

D

Q3 9
* 2N 7 00 2 W
Q3 8
*A O 3 41 5
G

Q4 0
*2 N 7 0 02 W
G

R5 6 9
*4 . 7 K _ 04

5VS

S

S

D

3 .3VS _AUD

D

S

H E A D P H O N E -L
H E A D P H O N E -R

R 57 0

C118
4.7K_04
2.2K_04

MI C 1_ L

R 34 3

1 K _ 04

MI C 1_ R

R 35 1

1 K _ 04

AL269
VT1802P

680p
330p

R 5 71

* 10 K _ 0 4

20ms

AL269
VT1802P

J_SPKL1
2 1

8 82 6 6 -02 0 0 1
J_INTMIC1
2 1

6 8 0p _ 5 0V _ X 7 R _ 0 4

Headphone Anti-Pop Circuit

C 2 89

* 18 0 p _5 0 V _ N P O _0 4

1
2

C 11 8

3 . 3V S

F C M 10 0 5 K F -1 21 T 0 3
L2 3

1
2

C2 9 3

AUD G
J _I N T MI C 1

MI C 1-V R E F O- R R 35 0

2 . 2 K _ 04

MI C 1-V R E F O- L R 34 5

2 . 2 K _ 04

M I C 1 -L

31

M I C 1 -R

31

*1 0K _0 4
A U DG

AZ_ RST#
C5 3 8
*1 0 u _6 . 3 V _ X5 R _0 6

PD#
A UDG

Spe a ke r w i re le ngt h le ss tha n 80 00 mils , It don't ne ed LC Fil te r.
SPKOU TR +, R-, L+ , L- Trac e w idth
Spe a ke r 4 ohm-- -- --> 40m ils

*2 8 mi l _ 06

EMI Require

4 . 7u _ 6 . 3V _ X 5 R _ 0 6
4 . 7u _ 6 . 3V _ X 5 R _ 0 6

MI C 2-V R E F O R 1 3 0

E A P D _M OD E

0 . 1u _ 1 6V _ Y 5V _ 0 4

R5 3 3

2 0 K _1 % _ 04
*1 0 0p _ 50 V _ N P O_ 0 4

M I C 1 -V R E F O-L

*2 2 0 K _0 4
G

0 . 1u _ 1 6V _ Y 5V _ 0 4

C5 0 2

AUD G

ALC269
20K_1%_04
VT1802P 5.1K_1%_04

18

2. 2 u _ 6. 3 V _ X 5R _ 06

FOR VOLUMN
ADJUST

C5 0 3

1 20 1

19
20

C BN

31

4 7 K _ 04

26
37

R 3 67

49

1 u _6 . 3 V _ Y 5 V _ 04

7

K B C_ B E E P

C 30 9

42
43

28

D1 3
B A T 54 C W GH
A
C 3 BEE P
A

PVSS1
P VSS2

PC BEEP

1

R3 6 9

V RE F

S Y NC
3 .3 VS

L I N E 1- L
LI N E 1 -R

S D A T A -OU T

22 p _ 50 V _ N P O_ 04

1 3 H DA _ B IT CL K

SEN SE_ A

S e n se -B
S PD IF C2 /E AP D
S PD IF O

5
1 3 H D A _ S D OU T

Q 25

13
S e n se A

S P K - L+
S P K - L-

DIGITAL

Clo sed to SB.

.

A UD G

I N T _ MI C

R 70 0

R343 & R351

R345 & R350

AL269
VT1802P

AL269
VT1802P

1 K _ 04 I N T_ M I C _ R

1K_04
75_04
C 51 1
C 51 4

4. 7 u _ 6. 3 V _ X 5 R _ 06
4. 7 u _ 6. 3 V _ X 5 R _ 06
C3 9 5

1229 D02(W240HU)

1 .5 VS
3 .3 VS

2.2K_04
4.7K_04
MI C 2_ L
MI C 2_ R

1 20 2

0 . 1 u_ 1 6 V _Y 5 V _0 4

1 9, 3 2
3 , 9, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 20 , 2 3 , 24 , 2 5 , 26 , 2 8 , 29 , 3 1 , 3 2, 3 7

AUDIO CODEC ALC269 VIA1802 B - 31

B.Schematic Diagrams

R5 1 4

5 VS

40
41

S P K OU TL +
S P K OU TL Q3 2
31
*M T N 7 00 2 Z H S 3
31

G

4

A UDG

A V DD 1
A VD D2

A
R B 75 1 S -4 0C 2

9

C
D1 9

U 29

10 K _ 0 4

39
46

R B 75 1 S -4 0C 2

P VD D1
P V DD2

A

D1 8

D

2 8 K B C_ M UT E #

C

R5 1 8
1

H D A _ R S T#

H D A _R S T #

L 39
*H C B 1 6 08 K F -1 2 1 T2 5

A
*R B 7 51 S -4 0 C 2

DV DD1

13

C
D2 1

D V D D -I O

E A P D _ MO D E

Schematic Diagrams

USB, FAN, TP, MULTI CON
USB 2.0

FAN CONTROL

1
2
3
4

F ON #
5 VS
5 VS_ FAN
C P U_ F A N

28

U 38
F ON
V IN
V OU T
VSET

GN
GN
GN
GN

D
D
D
D

8
7
6
5

A X 9 95 S A

AX9 95 B& APE8 87 2
Co-L ayo ut
5 VS_ FAN

5 VS

1 0 0 u_ 6 . 3V _B _ B

F O N#

Port 1

C 94
0 . 1 u _1 6 V _ Y 5 V _ 04

28

C P U_ F A N

1 20 2
J _ US B _ 1
4 L 13

3

A US B _ P N1 _ R

2

1

2

A US B _ P P 1 _ R

3

GN D
GN D

2
5

C 45 6
0. 1 u _ 16 V _ Y 5 V _ 0 4
1 0 u_ 6 . 3 V _X 5 R _ 0 6

2n d Sou rce

PN:APE88 74

2 8 C P U_ F A N S E N

GN D
3 1 7 D E 0 4 P S A 7 A 2C

CO-LAY USB 3.0 J_USB2

W 24 0 H U
W 25 0 H U

5 V S _ TP
R1 3 1

*2 8m i l _0 6
R 12 9

R 1 27

C1 1 3

1 0 K _ 04

1 0 K _ 04

1 u _6 . 3 V _ Y 5 V _0 4

C 11 4

C 1 15

4 7 p_ 5 0 V _N P O_ 0 4

4 7 p _5 0 V _ N P O_ 0 4

J_ T P 2

3 17 D E 04 P S A7 A 2 C
1 -2 8 4 -8 0 0 28 1 - 1

1
2
3
4
5
6
7
8

U S B V CC

T P_ DAT A
T P_ CL K

3 . 3V S _ F P

88 4 86 -0 8 01

F L G#

32 , 3 4

0 . 1 u_ 1 6 V _Y 5 V _0 4

C 49 2

3

C5 9 7

C 49 1
1U _1 0 V _ 06

8
V IN2

C4 9 3

3 . 3V S

0. 1u _ 16 V _ Y 5 V _ 0 4

C 5 96
7

V O UT 2

0 . 1 u _1 6 V _Y 5 V _0 4

V O UT 3

4

DD_ O N#

US B _ P N 3 1 7
US B _ P P 3 1 7

F L G# V O U T 1
V IN1

L5 0
H C B 1 6 08 K F -1 2 1T 2 5

100 MIL

6

2

5V
C5 0 1

U4 0

.

*0 _0 4

5

28
28

L62
H C B 1 6 08 K F -1 2 1 T2 5

G_ U S B V C C
R5 2 4

4 . 7K _ 0 4

CLICK B'd & FP CONN
5 VS

U S B _ O C # 01

R 20 2

3. 3 V S

D A TA _ H
4
*W C M2 0 12 F 2 S -S H OR T

Sheet 31 of 46
USB, FAN, TP,
MULTI CON

1

D A TA _ L

G ND1
GN D 2
GN D 3
GN D 4

U SB_ PP1

G ND 1
GN D 2
G ND 3
GN D 4

U S B _ P N1

17

1
2
3
8 5 20 5 -03 7 0 1

C2 0 5

V+
17

3
J_ F A N 1

F ON #
V IN
V OU T
VSET

1

11 1 9 -2

*0 . 1 u_ 1 6 V _Y 5 V _0 4

1 0 u_ 6 . 3 V _ X5 R _ 0 6

1
E N#

G ND

R T9 7 15 B G S / S Y 6 2 88 D F A C
1228 D02

If system has AP ON function, uses J_SW1
If system has no AP ON function, uses J_SW2

POWER SWITCH B'd CONN

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

3 . 3V S
C2 9

C 27

J_ S W 1
AP_ KEY#

J _ A U D I O1
1
2
3
4
5
6
7
8
9
10
11
12
13
14

M I C 1 -R
M I C 1 -L
R 33 9
R 34 0

30 H E A D P H O N E -R
30 H E A D P H O N E -L
30

2 2 0 _0 4
2 2 0 _0 4

M IC_ S E N S E

30
17
17

HP _ S E N S E
USB_ PN 9
U SB_ PP9

30
30

S P K OU T R +
S P K OU T R -

H E A D P H ON E -R R
H E A D P H ON E -LL
M IC_ S E NS E
S P K _H P #
H P _ S E NS E

S P K OU T R +
S P K OU T R -

8 72 1 3 - 14 0 0 G
A UD G

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
J _ SW 2
1
2
3
4
5
6
7
8
9
10

2 0mi l

28

Q9
*M TN 70 0 2 Z H S 3

G

M _B T N #
W E B _W W W #
W E B _E M A I L #
L ID_ S W #

M_ B T N #
32
W EB_ W W W # 2 8
W E B _ E MA I L # 2 8
L ID_ S W # 1 1 ,2 8

1
2
3
4
5
6
7
8

2 0m il
M _B T N #
W EB_ W W W #
W E B _ E M A I L#
L ID_ S W #
AP_ KEY #

88 4 8 6- 0 8 01
C 5 46

AP_ O N

A P _ ON

32

V IN

*5 05 0 0 -01 0 41 -0 0 1L

1229 D02(W240HU)

27
2 , 3 , 8, 1 1 , 1 3, 1 5 , 1 7, 1 9 , 2 0, 2 2 , 23 , 2 7 , 29 , 3 2 , 34 , 3 6
1 1 , 1 2, 1 9 , 20 , 2 6 , 30 , 3 2 , 37 , 3 8
23 , 2 7 , 32 , 3 4 , 35 , 3 6
1 1 , 3 2, 3 3 , 34 , 3 5 , 36 , 3 7 , 38 , 3 9
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 26 , 2 8 , 29 , 3 0 , 32 , 3 7

B - 32 USB, FAN, TP, MULTI CON

AP_ KEY#

0 . 01 u _ 16 V _ X 7R _0 4
D

30
30

3. 3 V

3. 3 V

US B V C C
3. 3 V
5V S
5V
V IN
3. 3 V S

C5 4 7
*0 . 1 u_ 1 6 V _Y 5 V _ 0 4

C 22 3

3 .3 V S

CLOSE TO J_SW1

1.1A 60mils
5V

* 0 . 1u _ 5 0V _ Y 5 V _ 06

Audio B'd CONN

S

B.Schematic Diagrams

4
3
1
6

*A X 9 9 5B

01 0 1 D 0 2

17

5 VS_ FAN

U5 0

US B V C C
C 4 88
+

JFAN
5 VS

80 mil

Schematic Diagrams

5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU
S Y S5 V
VI N

VA

SY S 5V

V IN1

S Y S5 V
S Y S 5V

P C2

PC 1 10

PC 1 11

0 . 1u_ 50 V_ Y 5V _0 6

0. 1u _5 0V _Y 5V _ 06

0. 1u _5 0V _Y 5 V_ 06
PU 7

3

1 K _04

4

PR 2 34

*10 K_ 04

D6 1

D D _ ON #

S U SB

D D _ ON # 31 ,3 4

S U SB

10 K_ 04

3 , 34 ,3 5
SL P _M

M_ BT N #

P WR _ SW #

I N S TA N T-ON
P2 80 8B 0
1 1/0 2
VN
I

GN D

10 0K _0 4 D D _ON

R 3 71

R 60 4

6

6

0 22 4

1K _0 4

P WR _ SW # 28

D D _ ON2 G

27, 2 8, 33 D D _ ON

3

D
PQ6 7A
MTD N 70 02 ZH S 6 R
S

5 G

6, 15 , 27, 2 8 S U SB #

1

5
P R 2 21
P R 123

10 K_ 04

V DD3

D
P Q67 B
MT D N 70 02Z H S 6R
S

4

1 5, 28

PQ8 5
MTN 7 002 ZH S 3

G

S LP _M#

ON

P R 22 0

ON

1 00 K_ 04

S LP _M

15

PM_ S LP _L AN

D

7

D

D D _ON _ LA TC H

P R 237

10 K_ 04

P C2 9
0 . 1u _16 V _04

P Q86
MTN 7 00 2Z H S3

G

15, 2 8, 35 P M_ SL P_ LA N #

PC 7 8
0. 1u _1 6V _0 4

S

1 K _04

PR 2 27

1 0K _0 4

PR 2 36

V IN1

V IN

1

1

A P _ON

PR 2 26

1 00K _ 04

10/2 9
D 62 *V 15 AV LC 0 40 2

ON

O N

*V 15 AV LC 0 40 2
3.2
3 .3 V

3 . 3V S

1. 5VS
C 50 4

C 50 5

C 506

C 24 7

C 2 24

C 225

0. 0 1u_ 16 V_ X7 R _0 4

0. 0 1u _16 V _X7 R _0 4

0. 01 u_1 6V _X 7R _ 04

0. 0 1u_ 16 V_ X7 R _04

0 .0 1u _1 6V _X 7R _0 4

0. 01 u_ 16V _ X7R _ 04
S Y S 15V

5 VS
8
7

Powe r Pl ane

P R 2 19

10 u_6 . 3V _X 5R _ 06

1 00 _0 4

*1 00 K_ 04

PQ6 4B
MTN N 2 0N 0 3Q8
5

G

S U SB

4 70 p_5 0V _X 7R _ 04

1 M_0 4
3

3
P R 23 2

0. 1u _1 6V _Y 5 V_ 04
PQ6 6B
MT N N 20 N 03Q8

D D _ON #

P C2 16

0 .1 u_ 16 V_ Y 5V _0 4

1. 0 5V M_E N

P Q6 3
MT N 70 02Z H S 3

1

5

6

47 0p_ 50 V_ X7 R _0 4

P C 220

0 . 1u_ 16 V_ Y 5V _0 4

10 u_ 6. 3V _X 5R _ 06

P R 2 41

PQ9 1B
MTN N 2 0N 0 3Q8

P C 21 3

5

SL P _M

G

4 70 p_5 0V _X 7R _ 04

PC 2 22

* 100 _0 4

P Q7 2
MT N 70 02 ZH S 3

SU S B

3 3, 4, 3 5

6

P J 20

P C 21 8

6

5

PC 2 19

P C 21 2

5V S _E N 1
4

4
P C 2 21

100 K _04
P Q65 B
MT N N 20 N 03Q8

P C 21 7

1. 5 VS _E N

S

1M_ 04

PR 2 31

5 V_ EN 1

47 0p _5 0V _X 7R _0 4

5 VS

PR 2 23

3

1M_ 04

PQ6 6A
MTN N 20 N 03 Q8
2
1

1. 05 V _M

P Q91 A
MT N N 20N 0 3Q8
2
1

4

SY S 15 V VD D 5

4

P R 22 5

NM OS
5V

3A

8
7

P R 24 0

6

PQ6 5A
MTN N 20 N 03 Q8
2
1

0 308 -J
P DA bu g
S I48 00 BD Y?M E4 41 0AD -G

NMOS

1

8
7

3A

P Q64 A
MTN N 2 0N 0 3Q8
2
1

1 M_0 4

3

S Y S1 5V V D D 5

8
7

P R 21 8

D 1 . 5V S _LO

NM OS

S Y S 15 V
1 . 05V _ LA N _M

2

2

P J 19
*4 0mi l

ON

*4 0mi l

Sheet 32 of 46
5VS, 3VS, 1.5V/
0.75VS, 1.5VS CPU

ON

ON

W243 1117

1. 5VS _C PU
1230 D02

V al ue = *1M_ 04

PQ2 1B
MTN N 2 0N 0 3Q8
PC 9 5

P Q20 B
MTN N 20 N 03 Q8

6

P C 89
47 0p _50 V _X7 R _0 4

SU S B

G

P Q16
MTN 7 00 2Z H S3

P C 46

PC 1 79

*0 .1 u_ 10 V_ X7 R _04

*10 u_6 . 3V _X 5R _ 06

P Q48 B
MT N N 20 N 03 Q8
5

S US B

G

*22 00 p_ 50V _ X7R _ 04

PJ 22
*OP EN _ 5A
1

2

P Q11
*MT N 700 2Z H S 3

6

S

5

D

D D _ON #

4

5
220 0p _5 0V _X 7R _0 4

1 . 5V S _C P U EN

*2 20 _04

P C 18 0

NMOS
P Q90
P 12 03B V
8
7
3
6
2
5
1

S Y S1 5V

R 4 43

C 4 29

4

1 M_04

10A

1 . 05V S _E N

ON
C 4 55

ON

2 200 p_ 50 V_ X7 R_ 04

3. 3V _M
V DD3
8
7

V DD3

*1 0K _0 4

1 228 D 02
P C 97

P C 10 0

PR 1 06

0 . 1u_ 16 V_ Y 5V _0 4

10 u_ 6. 3V _X 5R _ 06

100 _0 4

D 3. 3V M_ LO

3

R 57 4

Q20
MT N 70 02Z H S 3

G

P R 24 3
0_ 04

Pow er P lane

PR 1 12

4

3. 3V M_ EN 1

PC 9 2

MT D N 700 2Z H S 6R
1. 05 VS _ EN _ C

4

3. 3 V_ M

P Q9 2A
MT N N 20 N 03Q8
2
1

1M_0 4

P Q87 B
G

S

NM OS
SY S 15 V

3
D

5

R 1 26
*1 00 _04

S

0 104 D02

C 4 09
*1 0u _10 V_ Y 5V _0 8

P R 71

10 0_ 04

1. 0 5V S

D1 .0 5V S _L O

P R 102

1 0u _6. 3 V_ X5 R _06

1. 0 5V _L AN _ M

0 .1 u_ 16 V_ Y5 V _04

P C 94

0. 1u _1 6V _Y 5 V_ 04

3. 3 VS _L O

4

PC 9 6

3. 3 VS _ EN 1

P R 72

S

1M_ 04

10 0K _0 4

1.05VS

10A
PJ15 MUST SHORT

PQ4 8A NMOS
*MTN N 2 0N 03 Q8
8
2
7
1

4

3

PR 2 33

12 28 D0 2

3. 3V _ EN 1

SY S 1 5V

P R 10 9

P ower Pla ne

1M_0 4

V DD3

3A

P J 15
*OPE N _ 5A -S h ort
2
1

3 . 3V S

PQ2 0A
MTN N 2 0N 03 Q8
8
2
7
1

3

S Y S1 5V

3

3A
PR 1 11

3. 3 V

1. 5V S _C P U

1 . 5V

NM OS

P Q21 A
MT N N 20N 0 3Q8
8
2
7
1

D 1 .5 V S_ C PU _ LO

3 .3 VS
NMOS

SY S 15 V V D D 3

6

3. 3V

P Q92B
MT N N 20N 0 3Q8

470 p_ 50 V_ X7 R _04
3. 3V M_ EN

PQ8 8A
* MTD N 70 02 ZH S 6R

PQ1 7
MTN 70 02 ZH S 3

G

6

S

5
PR 2 44

0_ 04 P M_S LP _L A N

PR 2 45

*0_ 04 S LP _M

W243 1117

S US B

6
D

ON

S Y S 5V
33 , 35
3 . 3V _M
13 , 15, 1 9, 25 , 26
1 . 05V _L A N _M 20 ,2 5, 3 5
1 . 05V _M 20
VA
39
1 . 5V S_ C PU 3 ,6
1 . 5V
3, 6 8, , 9, 10 , 20 ,2 7, 3 4
5V
23 , 27, 3 1, 34 , 35 ,3 6
V IN1
33
3 . 3V S
3, 9 ,1 0, 1 1, 12 , 13, 1 4, 15 , 16, 1 7, 18 , 19 ,2 0, 2 3, 24 , 25, 2 6, 28 , 29, 3 0, 31 , 37
V DD5
20 , 27, 3 3, 35
V DD3
13 , 14, 1 5, 17 , 18 ,2 0, 22 , 23 ,2 4, 2 5, 28 , 33, 3 5, 39

ON

2

G
S

1. 0 5V S _V TT _E N 1 5, 35

1
W 24 3 1 11 7

1 .0 5V S
13 ,1 4, 1 5, 19 , 20
1 .0 5V S _V TT 2 , 3, 5, 1 8, 19 , 20, 3 5, 37
3 .3 V
2, 3, 8 , 11, 1 3, 15 , 17, 1 9, 20 , 22 ,2 3, 2 7, 29 , 31, 3 4, 36
1 .5 VS
19 ,3 0
5 VS
11 ,1 2, 1 9, 20 , 26, 3 0, 31 , 37, 3 8
V IN
11 ,3 1, 3 3, 34 , 35, 3 6, 37 , 38, 3 9
S Y S1 5V 33 ,3 5

5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU B - 33

B.Schematic Diagrams

5V

1. 05V _M
1. 5V S

NMOS

1. 5 V

D 1 . 05 VM _LO

W243 1117 ? ?

S

5V

2

31

M_B T N #

2

31

10K _ 04

8

VA
2

P R 22 2

S

1

O N
D D _ ON " L " T O
" H " F R O M EC

PR 2 24

Schematic Diagrams

VDD3, VDD5
V RE F

PR1 9 5

*0 _0 4

P R7 7

0_04
PC1 9 5
1 u _ 10 V _ Y 5 V _ 0 6

P R 19 8

PR1 9 7
E N_ 3 V

E N_ 5 V

P C2 0 1
2

1
E N1

VFB1

VIN
24
V O1

P C1 9 9

8
7
6
5

PR2 0 9

18

17

P R 21 3 P R 2 10

P R 2 11

P R2 1 2
*0 _0 4

PR2 1 4

0_ 0 4

PR2 1 5

*0 _0 4

2 . 2 _0 6 0 _ 0 4

* 0 _0 4

ch an ge fo r Po wer

D

P D 24
E N _ 3 V 5V

S

PR 8 2

1
2

S

1 0 0K _ 0 4

D

0 . 1 u_ 1 0 V _X 5R _0 4

S

P R 84

P J1 1
* 4 0m i l

0_ 0 4

VDD 5
PJ 1 0
1
* 5 mm

P R7 5
P D2 1

P C6 1

A
V R E G5

0105 D02

1 0 00 p _ 50 V _ X 7R _ 04
P C 93
* 10 0 0 p_ 5 0 V _X 7 R _ 0 4
P R 22 8

Rb
+

P R1 9 6

P C 63

P C5 8

2 20 u _ 6. 3V _ 6 . 3 *6 . 3 *4 .02. 1 u _1 6 V _ Y 5 V _ 0 4
1 . 5 M_ 0 4

P R 11 3

19 . 1 K _ 1% _ 0 6

V IN

P D2 2
C

R B 0 54 0 S 2
A

P D2 3
A

R B 0 54 0 S 2
C

0 . 0 1 u_ 5 0 V _X 7 R _ 0 4

C

P C 20 7

* 5. 1 _ 0 6
SY S5 V

0104 D02 EMI

0105 D02

SYS1 0 V
P C6 9

PC2 0 8

P D 2 9 R B 0 54 0 S 2

A

22 0 0 p_ 5 0 V _X 7 R _ 0 4
4. 7 u _ 25 V _ X 5R _ 08

C

1 u_ 1 0 V _ Y 5 V _ 06

A

P C 2 10

EN_ 5 V
P D2 0
A

R B 0 54 0 S 2
C

MT N 7 0 0 2Z H S 3

SYS1 5 V
P C6 8
22 0 0 p_ 5 0 V _X 7 R _ 0 4

SYS5 V
SYS3 V
VIN
V IN1
SYS1 5 V
V DD 5
V DD 3

B - 34 VDD3, VDD5

2

G
P C 71

G
MT N 7 00 2 Z H S 3

2 7 , 28 , 3 2 D D _ O N

A

0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
P Q1 4

P Q 18

EN_ 3 V

R B 0 5 40 S 2

D

1 0K _ 0 4

D D _ ON _E N _ V D D

*0 _ 04

PL 9
4. 7 U H _ 6 . 8* 7. 3* 3. 5
2

30 K _ 1 %_ 0 6

V R E G5

V RE G 5
PR 8 6

PD 9

P C 2 09

V R E G5

1124 change
for Power

V IN1

P R9 0

VDD5

5A

M9 90 12 5
VR EF

1 124

MT N 70 0 2 Z H S 3

C

E N _A L L

*6 80 K _ 1 % _0 4

*5 . 1 _0 6

P Q 73

PQ 1 2
P 1 2 0 3B V

*R B 0 54 0 S 2

0105 D02
*1 0 00 p _ 50 V _ X 7 R _ 04

4 . 7 u_ 2 5 V _X 5 R _ 0 8

4

P C4 4

0104 D02 EMI

G

5
6
7
8

19
L GA TE 1

16

C

P C 74

4. 7 u _ 25 V _ X 5R _ 08

Ra

PD 7

A

*R B 05 4 0 S 2

P R9 3

U S B _ A C_ IN

0105 D02 1

1
2
3

EN 0

3
2
1
V R E G5

P C2 0 5

SYS5 V

P 1 20 3 B V

20

V CL K

L G A TE 2

L DO 5

12

2 0K _ 1 % _ 04

39

4

PD 8

A
*S K 3 4 S A

1 00 p _ 50 V _ N P O _ 04

P R1 9 4

PHASE 1

4

P D5

C S O D 1 4 0S H
A

22 0 u _6 . 3 V _ 6. 3* 6. 3 * 4. 2

P C6 2 P D 6

1 3K _ 1 % _ 06

U GA TE 1

S K IP S E L

C

C

P C6 5
P R7 6

21

PH ASE2

V IN

PQ 6 0
P 1 2 0 3B V

8
7
6
5

P C 72

+

P C2 0 6
0 . 1 u_ 5 0 V _ Y 5 V _ 06
P Q1 3

U GA T E 2

GN D P A D
G ND

11

14

* 5m m

Sheet 33 of 46
VDD3, VDD5

SYS5 V

1
2
3

PL 1 0
4 . 7U H _ 6 . 8 *7 . 3 *3 . 5
2
1

1

13

SYS3 V
PJ 8
2

0 . 1u _ 1 0V _ X 7 R _ 0 4

22

3
2
1

V DD3

B OO T1

uP6182

10

4

0. 1 u _ 16 V _ Y 5 V _ 04

B.Schematic Diagrams

5A

PC2 0 4

P OK

B O OT 2

0 . 1 u_ 1 0 V _ X7 R _ 0 4

C

9

P C 20 3

*1 0 K _ 04

5
6
7
8

L D O3

1u _ 1 0V _Y 5V _0 6
PQ 5 6
P 1 2 0 3B V

PR2 0 1
23

25
15

VDD3

8

C

4 . 7 u _2 5 V _ X5 R _0 8

C S O D 1 4 0S H

VO 2

PC 6 4

4 . 7u _ 2 5V _ X 5 R _ 0 8

P C1 9 8
1 00 0 p _5 0 V _ X7 R _0 4

P U1 1

*S K 3 4 S A
A

7
P C2 0 0

V RE F

T O NS E L

6

4
VFB2

EN 2

V R E G3
V IN

3

1 00 K _ 0 4

10 0 0 p_ 5 0 V _ X7 R _ 0 4

5

1 0 0K _ 0 4

3 2 ,3 5
39
1 1 , 3 1, 32 , 3 4 , 35 , 3 6 , 37 , 3 8 , 3 9
32
3 2 ,3 5
2 0 , 2 7, 32 , 3 5
1 3 , 1 4, 15 , 1 7 , 18 , 2 0 , 22 , 2 3 , 2 4, 2 5 , 2 8, 3 2 , 3 5, 3 9

Schematic Diagrams

Power 1.05VS/0.75V, 1.8VS
VIN
P D4
PU 4

A

C

1
2
3
0 . 1 u _ 10 V _ X 7 R _ 0 4

22
VB ST

24

VTT

DR V H

P R1 9 2

21

1
P C5 5

PC 5 4

20
V T T GN D

PR8 0
0_ 0 6

DR V L

5

PR8 9

* 10 K _ 1 % _ 04

NC

NC

G ND

A

4 7 K_ 0 4

P R9 8

MT N 7 00 2 Z H S 3
S

PC8 2

G

S US C #

PQ 1 9
SU SB

G

D

*0 . 1 u _ 16 V _ Y 5V _0 4

P Q2 4

S

1 0 K _1 % _ 0 6

P C 84

S

*M TN 7 0 02 Z H S 3

PJ 1 2
* 40 m i l
2

D

P Q2 2
1 5 , 28

P Q 23
MT N 7 00 2 Z H S 3
G

G

1 00 K _ 0 4

VT TEN

1

1 0 0K _ 0 4

D

3 1, 3 2

D D _ ON #

0. 1 u _ 1 6V _Y 5 V _ 04
S

M T N 7 0 0 2Z H S 3

1 .5V _CTR L1

1. 5_ CTRL0

Volt a ge

1
1
0

1
0
1

1 .5 5V
1 .6 0V
1 .6 5V

0

0

1 .7 0V
? ? ? ? PIN6?

3 .3 V

3 .3 V

5V

1 0K _0 4
PU 5

3A

V C N TL
4

1 0 0 K _0 4

V O UT

8

E N1 .8 V S

2

D

G ND

PC 6 6

*0 _ 04

PQ 9 9
G
S U S C#
S

1 5 ,2 8

M T N 7 0 0 2Z H S 3

1129

*0 . 1 u _ 16 V _ Y 5 V _ 0 4

D

P C 30 4

M T N 7 0 02 Z H S 3

P C8 5

P C8 3
1 0 u _ 6. 3 V _ X 5 R _0 6

R 69 6

AX6615ESA

G

0 . 1 u _ 16 V _ Y 5 V _ 0 4

0_ 0 4

0 . 1 u_ 1 6 V _ Y 5 V _ 04

R 69 5

S

S US B

SU SB

VFB

P C 90
PQ 1 5

3 , 32 , 3 5

PR 7 8
1 . 2 7 K _1 % _ 0 4

EN
1

1 1/09

10 u _ 6 . 3 V _X 5R _ 06

P R1 0 5

1 .8 V S
PJ 7
1

2

V O UT
3

5V

V 1. 8

0 . 1 u _ 16 V _ Y 5 V _ 0 4

1 .8 V S _ P W RG D

1 u _ 10 V _ Y 5V _0 6
6

V IN
V IN
PO K

P C5 7

5
9
7

P C5 9

2A
3 , 1 5 1 . 8 V S _ P W R GD

1.8VS

PC 9 1

1 0 u_ 6 . 3 V _ X 5 R _ 0 6

P R1 1 0

P C 67

P R1 0 3

Sheet 34 of 46
Power 1.05VS/
0.75V, 1.8VS

D D R 1. 5V _ P W R G D 1 5

P R1 1 8

5V

1 0K _1 % _ 0 6

P R1 1 7
5V

0 _0 6

0105 D02

25

7

10

P R 91

+

P R 92
1 00 K _ 0 4

D

PR 9 9

S3

12

* 1 00 0 p _5 0 V _ X 7 R _ 0 4

P R1 0 1
5V

VD DQ SET

V D D QS E T

D

9

P C7 9

S

*M T N 7 0 02 Z H S 3

S5

1 u _1 0 V _ Y 5 V _ 0 6

G

PR 7 3

3 .3 V
11

V D DQ S NS

*1 0 _ 06

P Q5 7
SU SB

P GO OD _ 6 16 3

P G OO D
1u _ 1 0 V _Y 5V _0 6

* 22 _ 0 4

13
C OM P

8

PR2 0 8

PR 1 9 3

P C7 5
*1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4

V TT _ M E M

6

0_06

* MD U 2 6 54

2. 2 _ 0 4

PC8 0

P C4 9
P C1 6 9

+

8 2 p_ 5 0 V _ N P O _ 0 4

GS7113
6-02-07113-320
AX6610
6-02-06610-320

P R 79
1 K _ 1% _ 0 4

*O P E N _ 3 A

6, 1 8 , 1 9
1 1, 3 1 , 3 2 , 3 3, 3 5 , 3 6 , 3 7, 3 8 , 3 9
2 3, 2 7 , 3 1 , 3 2, 3 5 , 3 6
2, 3 , 8 , 1 1 , 1 3, 1 5 , 1 7 , 1 9, 2 0 , 2 2 , 2 3, 2 7 , 2 9 , 3 1, 3 2 , 3 6
3, 6 , 8 , 9 , 1 0 , 2 0, 2 7 , 3 2
9 ,1 0

1 . 8V S
V IN
5V
3 . 3V
1 . 5V
V T T _M E M

Power 1.05VS/0.75V, 1.8VS B - 35

B.Schematic Diagrams

P R2 0 6

5
6
7
8
1
2
3

15
14
PC 7 6

5V

5V

*5 . 1 _ 0 6

P V CC 5
V CC 5

V T T RE F

6 . 1 9 K _ 1% _ 0 6

M D U 2 6 544
C S O D 1 4 0S H

0 . 1 u _ 10 V _ X 7 R _ 0 4

PR 8 3

16

C

5
6
7
8
PC 7 0

CS

1
2
3

*0 _ 0 6

M OD E

P Q5 0

PC 4 8

*5 6 0 u _2 . 5 V _ 6 . 3 *6

P R 20 2

4

4

0_ 0 6

P C1 8 4

0 . 1 u _1 6 V _ Y 5 V _ 0 4

*0 _ 0 6

P R8 1

P C5 2

0. 1 u _ 1 6V _Y 5V _ 0 4

P R 20 3

P GN D
C S _ GN D

PQ 5 1

5 6 0u _ 2 . 5 V _ 6. 6* 6 . 6* 5 . 9

G ND

0 _0 6

18
17

*1 0 0 0p _ X 7 R _ 0 6

5V

2

19
V T T S NS

3
P R 20 5

1 .5 V
P J6

1

*O P E N _1 2 A
2

1 0 u_ 1 0 V _ Y 5 V _ 0 8 10 u _ 1 0V _Y 5 V _ 08 * 1 0u _ 1 0V _Y 5 V _ 08

V DD Q

30A

V DD Q

LL

PD 1 7

P C1 9 4

1.5V

PL 7
1. 0 U H _ 1 1 . 5 *1 0 . 2* 3 . 0
1
2

3 .3 _ 0 6

* OP E N _ 2 A

P C1 8 6
*1 5 u _ 25 V _ 6 . 3 *4 . 4 _ C

1

PC 1 8 8
0. 1 u _ 5 0V _Y 5 V _ 0 6

PC 6 0
23

PJ 1 8
2

P C 19 1
4 . 7 u _2 5 V _ X 5 R _ 0 8

V DD Q
V L DO IN

V T T _ ME M

P C1 9 2

+
P Q 52
MD U 2 6 5 7

4

4 . 7 u_ 2 5 V _ X 5 R _ 0 8

RB 0 5 4 0 S 2

0. 1 u _ 5 0V _Y 5 V _ 0 6

VTT_MEM

PC 5 1
5
6
7
8

5V

u P6 1 6 3
P C5 6
1 0 u _ 10 V _ Y 5V _0 8

Schematic Diagrams

Power 1.05VS LAN M
V IN
PD4
P U4

A

1
2
3
24

1

P R1 9 2

21
VT T

DR V H

1
P C 19 4

P C5 5

PC 5 4

20
V T T GN D

2

5

PR8 9
P C7 6

P R 20 6

9

P R1 0 1
5V
* 10 K _ 1 % _ 04

N C

NC

C

5
6
7
8

A

1
2
3

P R9 8

SUS C#

S

M TN 7 00 2 Z H S 3

D
P Q2 4

S
D D_ O N#

1 .5 V_C TR L1

1. 5_ CTRL0

Volt a ge

1
1
0

1
0
1

1 .5 5V
1 .6 0V
1 .6 5V

0

0

1 .7 0V
? ? ? ? PIN6?

3 .3 V

5V

1 0 K _0 4
P U5

1 u _ 10 V _ Y 5V _0 6
6

3A

V C N TL
4

1 0 0 K _ 04

8

E N1 .8 V S

V O UT
2

D

G ND

R 69 6

*0 _ 04

S

M T N 7 0 0 2Z H S 3

1129

*0 . 1 u _ 16 V _ Y 5 V _ 0 4

D
PQ 9 9
S U S C#

S

M T N 7 0 0 2Z H S 3

P C 30 4

G

B - 36 Power 1.05VS LAN M

G

PC 6 6
P C8 5

P C8 3
1 0 u _ 6. 3 V _ X 5 R _0 6

0_ 0 4

0. 1 u _ 1 6V _Y 5 V _ 0 4

R 69 5

0 . 1 u_ 1 6 V _ Y 5 V _ 04

SU SB

VF B

P C 90
PQ 1 5

SUSB
3 , 3 2, 3 5

PR 7 8
1 . 2 7 K _ 1% _ 0 4

EN

1

AX6615ESA
1 1/09

GS7113
6-02-07113-320
AX6610
6-02-06610-320

0 . 1 u _ 1 6V _ Y 5 V _ 0 4

PR1 0 5

1 0u _ 6 . 3 V _X 5R _ 0 6

3
5V

1 .8 V S
PJ 7
1

2

V O UT

P C5 7

V IN
V IN
PO K

V1 .8

PC5 9

5
9
7

1. 8 V S _P W R G D

3, 1 5 1 . 8 V S _ P W R GD

1.8VS

PC 9 1

2A

1 0 u_ 6 . 3 V _ X 5 R _ 0 6

P R1 1 0

P C 67

S

0. 1u _ 1 6 V _Y 5 V _ 04
MT N 7 0 0 2 Z H S 3

3 .3 V

15 , 2 8

*0 . 1 u _ 16 V _ Y 5V _0 4

S

3 1, 32

2

D

1 5 ,2 8

P C8 2

1 0 K _ 1% _ 0 6

P C 84

*M T N 7 0 02 Z H S 3

PJ 1 2
* 4 0m i l

G

P Q1 9

G

P Q 23
MT N 7 00 2 Z H S 3
G

G

1 00 K _ 0 4

VTT EN

P Q2 2

S US B

0 _0 6

4 7 K_ 0 4

1

1 0 0K _0 4

P R 91

D D R 1. 5V _P W R G D 1 5

D

PR1 0 3

P C4 9

0105 D02

P R1 1 8

5V

1 0 K _1 % _ 0 6

P R1 1 7
5V

PC 4 8

25

7

G ND

S3

+

P R 92
1 00 K _ 0 4

D

P R9 9

10
V D DQ S E T

* 1 00 0 p _ 50 V _ X 7 R _0 4

PC7 9

S

*M T N 7 0 0 2Z H S 3

12

D
G

S5

1 u _1 0 V _ Y 5 V _ 0 6

P Q5 7
SU SB

2. 2 _ 0 4

PC8 0

P C1 8 4

PC1 6 9

PR 7 3

3 .3 V
11

V D DQ S NS

*1 0 _ 06

Sheet 35 of 46
Power 1.05VS LAN
M

8

* MD U 2 6 54

P GO O D _ 6 16 3

P GO OD
1u _ 1 0 V _ Y 5 V _0 6

* 2 2_ 0 4

13
C OM P

P R2 0 8

V T T_ M E M

6

0_06

V D D QS E T

5V

P C7 5
* 10 0 0 p _5 0 V _ X 7 R _ 0 4

B.Schematic Diagrams

15
14

P C5 2

*5 . 1 _ 0 6

P V CC 5
V CC 5

V T T RE F

P Q5 0
M D U 2 6 544

C S O D 1 4 0S H

0. 1 u _ 1 0V _ X 7 R _ 0 4

5V

1
2
3

CS

4

0 _0 6
6 . 1 9 K _ 1% _ 0 6

P D1 7

5
6
7
8
PC 7 0

PQ 5 1
P R 81
PR 8 3

8 2 p _5 0 V _ N P O _ 0 4
P R 79
1 K _ 1% _ 0 4

*O P E N _ 3 A

6, 1 8 , 1 9
1 1, 3 1 , 3 2 , 3 3, 3 5 , 3 6 , 3 7, 3 8 , 3 9
2 3, 2 7 , 3 1 , 3 2, 3 5 , 3 6
2, 3 , 8 , 1 1 , 1 3, 1 5 , 1 7 , 1 9, 2 0 , 2 2 , 2 3, 2 7 , 2 9 , 3 1, 3 2 , 3 6
3, 6, 8 , 9 , 1 0 , 2 0, 2 7 , 3 2
9 ,1 0

1 . 8V S
V IN
5V
3 . 3V
1 . 5V
V T T _M E M

+

*5 6 0 u _2 . 5 V _ 6 . 3 *6

M OD E

*0 _ 0 6

18
17
16

0 . 1 u _1 6 V _ Y 5 V _ 0 4

P G ND
CS _ G ND

0. 1 u _ 1 6V _Y 5V _ 0 4

P R 2 02

G ND
4

5 6 0u _ 2 . 5 V _ 6. 6* 6 . 6* 5 . 9

*0 _ 0 6

*1 0 0 0p _ X 7 R _ 0 6

5V

0 _0 6

2

DR V L

3

P R 2 03

1 .5 V
P J6

1

19
VT TSN S

1 0 u_ 1 0 V _ Y 5 V _ 0 8 1 0u _ 1 0 V _Y 5 V _ 08 * 1 0u _ 1 0 V _ Y 5 V _ 0 8

P R 2 05

30A

V DD Q

LL
*O P E N _1 2 A

P R8 0
0_ 0 6

VDD Q

1.5V

PL 7
1. 0U H _ 1 1 . 5 *1 0 . 2* 3 . 0
1
2

3. 3 _ 0 6

*O P E N _ 2 A

P R1 9 3

*1 5 u _ 25 V _ 6 . 3 *4 . 4 _ C

2

0. 1 u _ 1 0V _X 7 R _ 0 4

VB ST

0. 1 u _ 5 0V _Y 5V _ 0 6

PC 6 0
22
V L D OI N

P C1 8 6
+

P Q 52
MD U 2 6 5 7

4

V DD Q

V T T _ ME M

PC 1 8 8

4 . 7 u _ 25 V _ X 5 R _ 0 8

RB 0 5 4 0 S 2

23

PJ 1 8

P C 19 1

4 . 7 u_ 2 5 V _ X 5 R _ 0 8

PC5 6
10 u _ 1 0V _ Y 5 V _ 08

PC1 9 2

0. 1 u _ 5 0V _Y 5V _ 0 6

u P6 1 6 3

VTT_MEM

PC 5 1
5
6
7
8

5V

C

Schematic Diagrams

Power 0.85VS
3.3V
PC129
PR159
10K_04

0.022u_16V_X7R_04

0.725V 0.675V
0. 85VS_PWRGD 15

VIN

9. 31K_1%_04

C

PR151

47p_50V_NPO_04
*0_04

PR158

1
2

V0.85

6A

PJ5
*OPEN- 5mm
1
2

0. 85VS

Sheet 36 of 46
Power 0.85VS

PC40
PR62
0_04

PR64
0_04

+ PC1 68
PR157
100_04

3
PQ36B
PD1503YVS

PR63
12K_1%_04

1 1/0 5
PC41
PC42
0.1u_25V_X7R_06

CSP
CSN

0.85V_ON 35

PR65

6 VCCSA_VID0

1.3K_1%_04

6 VCCSA_VID1

*0.1u_16V_Y5V_04

100K_1%_04

CSN

33K_1%_04

PC25

PR155

PL4
1.0UH_6.8*7.3*3.5
1
2

11
12
13
14
15

PC124
0. 01u_16V_X7R_04

PC131 0. 01u_50V_X7R_04

22_04

1u_10V_Y5V_06

PR150

21
20
19
18
17
16
PC27
CSP

1K_1%_04

GND
PHASE
LG
VCC
RT
CSP

PR173

SET3
SET2
SET1
SET0
FB

PQ36A
PD1503YVS

8

0.1u_16V_Y5V_04

0. 1u_16V_Y5V_04

6
7
8
9
10

FOR EMI

220U_4V_D2_D

10K_1%_04

PC140

7

15K_1%_04

PU9
uP6122

5
6

PR144

4

PR36

RB0540S2

POK

PR145
10K_1%_04

PD1

100_04

01 03 D 02 W2 40X

PR1 49
VCCSA_SENSE 6
0_04

5V
0.85VS
VIN
3.3V

23,27,31, 32,34,35
6
11,31,32, 33,34,35,37, 38,39
2,3,8, 11,13,15,17, 19,20,22,23,27, 29,31,32,34

Power 0.85VS B - 37

B.Schematic Diagrams

PR35
10K_1%_04

PR148

5
4
3
2
1

10K_1%_04

EAP
SS
POK
UG
BOOT

PR146

12K_1%_04

COMP
VI D0
VI D1
EN/ PSM
CSN

PR34

PC34

A

9. 31K_1%_04
1 1/0 4

PC173 0. 1u_50V_Y5V_06

PR147

0.1u_50V_Y5V_06

5V
PR33

0.1u_50V_Y5V_06

VIN

0_04

PC47

PR137

PC197

1

4.7u_25V_X5R_08

0

0.1u_50V_Y5V_06

1

PC154

1

0

4.7u_25V_X5R_08

1

VCCSA_VID1

PC153

0

0.1u_50V_Y5V_06

0.8V

0

PC155

0.9V

VCCSA_VID0

Schematic Diagrams

Power V-Core1
PR 2 2

1.0 5VS_VTT

PC1 1
1 0_ 0 4

6 8 0 p _5 0 V _ X 7R _ 0 4

1 3 0 _ 1% _ 0 4
5 H_ C P U_ S V IDD A T
5 H _ C P U _ S V I D C LK
5 H _ C P U _ S V I D A L R T#

P R1 2

P R 1 9 1 . 2 1 K _ 1% _ 0 4

B~ 4 35 0

P C7

*7 5 _ 04

TSENS E

P R 1 31

P C1 1 3
10 0 p _ 50 V _ N P O_ 0 4

1 0 0_ 1 % _ 04
PR 1 3 0

1 K _ 04

PC 1 2
2 2 p _ 50 V _ N P O_ 0 4

P R2 1

1 2. 1 K _ 1 % _ 04

V S S _ S E N S E _ 61 3 1

0_04

C SP3

38

16 5 K _ 1 % _0 6
P R3 1

10/29

P C 15

1 20 0 P

P C 14

2 70 p _ 5 0V _X 7 R _0 4

1 3 7K _ 1 % _ 0 6

CSS UM

0_04

VR_ O N
61 31 _ VC C

5VS

P R1 2 5

2 .2 _ 0 6

VIN P

P R 14

A_G N D

R1 7

1 0 K _ 0 4 R OS C
V R MP _V I N
T SEN SEA

1 K _ 1% _ 0 4
PC 3

P C6

PR 1 8
1 u _ 6. 3V _X 5 R _ 0 4
* 1 4K _1 % _ 0 4

0. 0 1 u _ 50 V _ X 7 R _ 0 4

N C P 61 3 1 S

PR1 5 3

CS N 2
C SP2
CS N 3
C SP3
CS N 1
C SP1
D R ON
P W M1 / A D D R
P W M 3 / V B OO T
P W M2 / I S H E D
IM A X
P W M A /IM A X A
V B OO T A

10 0 K _ N T C _ 0 6 _B

A_ G ND

39
38
37
36
35
34
33
32
31
30
29
28
27

IMO NA

PR 3 9
V R 1 _P W MA

P R 13 4
24 . 3 K _ 1 % _ 04

P R3 7

OPTION:
DISALBE
V_GT

PR1 3 5
PC 1 6

*1 0 K _ 0 4
1
PJ 2

P C1 1 5

10 0 K _ N TC _ 06 _ B

* 6 mi l

1 0 0p _ 5 0 V _ N P O _0 4

1 0 0 0 p_ 5 0 V _ X7 R _ 04
P R 12 9

3 . 0 1 K _ 1% _ 0 4

P C1 1 6
3 3 00 p _ 5 0V _X 7 R _ 0 4

2
S

P Q 6 9A

P R5

*1 0 K _ 04
*MT D N 7 0 0 2Z H S 6 R

PR 7

1
P Q6 9 B

PJ 1
* 6m i l
2

S
* MT D N 7 0 02 Z H S 6 R

* 0. 1 u _ 1 6V _Y 5 V _ 04

PUT COLSE
TO V_GT
Inductor

D

1

PC 1

B~ 4 35 0

1 1, 15 , 2 8 A L L _ S Y S _ P W R G D

*1 0 m li _ 0 4
V R _O N

1 1 , 1 2, 19 , 2 0 , 2 6, 30 , 3 1 , 3 2, 38 5 V S
3 , 9 , 1 0 , 1 1, 12 , 1 3 , 1 4, 15 , 1 6 , 1 7, 18 , 1 9 , 2 0 , 23 , 2 4 , 2 5 , 26 , 2 8 , 2 9 , 30 , 3 1 , 3 2 3. 3V S
38
V_ G T
5 , 38
VCO RE
13 , 1 4 , 1 5 , 19 , 2 0 , 3 2 1. 05 V S
11 , 3 1 , 3 2 , 33 , 3 4 , 3 5 , 36 , 3 8 , 3 9 V I N
2 , 3, 5 , 1 8 , 1 9 , 20 , 3 5 1 . 0 5 V S _ V T T

38

CS P A

38

P R 13 9

1 6 5 K _ 1% _ 0 6

2

V R_ O N

G

4

PR 2 6
7 5 K _ 1 % _0 4
RT 2

CS N A

38

27 0 P _ 5 0 V _ X7 R _0 4

6

*1 0 0K _0 4

5

11 5 K _ 1 % _0 6

A_G ND

PC 1 9
0 . 0 22 u _ 1 6V _ X 7 R _ 0 4
CS P A

2

3
D

PC 1 7

1

V_ GT
PR 6

47 0 p _ 50 V _ X 7 R _ 0 4

P R 1 43
1 1 3 K _ 1% _ 0 4

20100805

C SNA

1 K_ 0 4
PC 9

G

IC C_MA X_2 1h
= R*10 uA*25 6A /2 V

A _G ND

P R2 4

P R 1 9 0 1 0 0 _ 04

PR3

A_ G ND
P J1 3
* 6 m li

DIFF OU TA

PR 2 3

3 .3 V S

A_ G ND
A_ G ND

11 3 K _ 1 % _0 4

P C2 1
A_G N D
1 00 0 p _ 50 V _ X 7 R _ 0 4

P C1 0
P R2 5
6 8 P _ 50 V _ N P O_ 0 4
1 0 _0 4

6 V C C _ GT _ S E N S E

1 0 K_ 0 4

1 0 K_ 0 4
4 1 . 2 K _ 1 %_ 0 4

A_ GN D

F BA

38

V R 1 _P W M1 3 8
PR 1 5 6

7. 5K _ 1 % _ 0 4

6 V S S _ GT _ S E N S E

CS P 1

38

V R 1 _P W M3 3 8

P R 1 32

P R1 2 7 0 _ 0 4

38

2 0 . 5 K _ 1% _ 1 / 1 6 W _ 04

C O MPA

P R1 2 6 0 _ 0 4

5 . 4 9 K _ 1% _ 0 4

P R 1 52

PR 1 5 4

CSC OM PA

A_G ND A _G ND

38

CS N 1
0. 0 4 7 u _1 0 V _ X 7 R _ 0 4

5VS

15 K _ 1 % _ 04

P R 1 9 1 1 0 0 _ 04

CS P 3

P R3 8

10 K _ 0 4

PC 1 1 8
0 . 1 u_ 1 0 V _ X 5R _ 04

A_ GN D

0 _0 4

38

5VS

C SPPA

0 . 1 u _1 0 V _ X 5R _ 0 4

PUT COLSE
TO V_GT
HOT SPOT

PC 2 3

D RO N

CSSU M A
PR1 4 0
24 K _ 1 % _ 04

38

5 . 4 9 K _ 1% _ 0 4

PR 4 3

V R1 _ P W M 3
P W M 2_ 6 1 3 1
I MA X _ 6 1 31
VR1_ PWM A
V B O OT A
P R 41
* 0 _0 4
P R4 0

2

I MO NA

5VS

CS N 3
CS PP 3
CSN 1
CS PP 1
DR ON

I MO N

P C 1 17

CS N 3
0. 0 4 7 u _1 0 V _ X 7 R _ 0 4

0_ 0 4

C S N 2 _5 V S

* 6 mi l
IL IM A

V S N A _ 6 1 31
VSPA_ 6 1 3 1

1
2

RT 1
PR 1 6 9
8 . 2 5 K _ 1% _ 0 4

0 . 1 u _ 10 V _ X 7 R _0 4

A_G N D

A_G ND

B~ 39 64

PC 2 2

A_ GN D

P J1 4
PC 1 1 4

38

PU 1

14
15
16
17
18
19
20
21
22
23
24
25
26

TSEN SEA

38

C SN3

1

P R8

H _ CPU _ SVID DAT
H _ CPU _ SVID CL K
H _ CPU _ SVID ALR T#
VR _ RD Y
VR _ RD YA
V R _ ON _ E N A B LE _6 1 3 1

VSP
TS E N S E
V R H OT #
SDIO
SCL K
A LE R T #
V R_ RD Y
V R_ RD Y A
ENA BL E
VCC
RO S C
VRM P
TS E N S E A

C SN1

PC 2 0
1 0 00 p _ 5 0V _X 7 R _0 4

1

1 5 D E L A Y _P W R G D

C SCO M P

53
52
51
50
49
48
47
46
45
44
43
42
41
40

0_ 0 4

1
2
3
4
5
6
7
8
9
10
11
12
13

1 0 _ 04

P R4 2

A_ G ND

1 0 K_ 0 4

1 0 _ 04

PR 3 2

2

PR1 1

P R 1 42
VR 1_ C SRE F

A _G ND

TSENS E
P R2 3 0

3 H _ P R O C H O T#

* 15 m i _l 0 6

EPA D
D I F F OU T
VS N
T R BST
F B
C OM P
I LI M
D R O OP
C S C OM P
C SSU M
IO UT
CSR E F
N C2
NC 1

3.3VS

PUT COLSE
TO VCORE
HOT SPOT

TR BST

PR9

V SNA
VS PA
F BA
D IF F O UT A
TR BSTA
CO M P A
IL IM A
D R OO P A
C S C OM P A
IO UT A
CSS U M A
C SPA
CSN A

VCORE

10 0 _ 0 4
V C C_ SE N SE _ 6 1 3 1

2

8 . 2 5K _ 1 % _ 0 4

1 0 0 K _ N T C _ 06 _ B

P R 1 88

1 0 K_ 0 4

Sheet 37 of 46
Power V-Core1

0_04

5 V CO RE _ V C C_ S E NS E

CO MP
IL IM

P R1 2 4

B~ 3 96 4

I MO N

R T3
1

P R 18 7

0 . 1 u_ 1 0 V _ X 7 R _ 0 4

1 00 0 p _ 50 V _ X 7 R _ 0 4

P R1 6

B - 38 Power V-Core1

38

PC8

A_ GN D

V CO RE _ O N

C SP1
PR 1 3 3

PC 5

28

Q ua d 45 W CPU
VI D1 =0 .9 V
I cc Max = 9 4A
R_ L L= 1. 9m ohm
O CP~ 1 20 A

1 3 7K _ 1 % _ 0 6

7 5 K _ 1 %_ 0 4

P C1 3
4 . 02 K _ 1 % _ 0 4 3 3 0 0 P _ 50 V _ X 7 R _ 0 4

P R2 8
P R1 2 8

P R1 4 1
PR2 7

1 0 0_ 0 4

5 V C OR E _ V S S _ S E N S E

B.Schematic Diagrams

2

1 00 K _ N T C _ 0 6_ B

H _C P U _S V I D D A T
H _C P U _S V I D C L K
H _C P U _S V I D A L R T#

P R1 8 9

PUT COLSE
TO VCORE
Phase 1
Inductor

RT 4
1

5 6 0 0p _ 5 0V _X 7 R _0 4

A_ GN D

D IFFO UT

P R 10

T R BST

5 4. 9 _ 1 % _0 4

PR1 5

2 4 . 9 K _ 1 %_ 0 4

FB

VCORE_1

PR 2 0

Qua d V CCAX G
VID 1= 1 .15 V
Ic cM a x = 26 A
R_LL= 3 .9 m ohm
OC P~ 31 A

Schematic Diagrams

Power V-Core2 VGFX
VIN

4

EN
VC C

LG

G

G

10 0 0 p_ 5 0 V _X 7 R _ 0 4

PD1 5
S

S

P R6 9

*1 5 m li _ 0 6

P R6 7

*1 5 m li _ 0 6

C SN1

SK3 4 SA

37

A

P R5 7
C SP1

37

0104 D02 EMI

LG

5

G

G

G
S

S

S

0. 1 u _ 50 V _ Y 5 V _ 06

V C OR E

10 0 0 p_ 5 0 V _X 7 R _ 0 4

P D 11

P R7 0

*1 5 m li _ 0 6

CSN 3

37

P R6 8

*1 5 m li _ 0 6

CSP 3

37

P R6 6

9
A

S K 3 4S A
5. 1 _ 0 6

*3 3 0 U _ 2 . 5V _ D 2

25A

*3 3 0 U _ 2 . 5V _ D 2

*4 . 7u _ 2 5V _X 5 R _0 8

VC OR E

P C4 3

VR EG_ SW3 _ L G

PAD

*4 . 7u _ 2 5V _X 5 R _0 8

D
S

P Q3 1
*MD U 2 6 5 4

*3 3 0 U _ 2 . 5V _ D 2

P Q 41
M DU2 6 5 4

+P C 17 6 +P C 17 2 +P C 17 8 +P C 17 4 +P C 1 7 5 + P C 1 7 0 + P C 1 7 7 + P C 1 7 1
5 60 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9

P Q4 5
MD U 2 65 4

50A

VCO RE

5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9

VC C

P L5
0. 3 6 u H _ 1 2. 9 * 14 *3 . 8
1
2

VR EG_ SW3 _ OUT

7

5, 3 7

5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9

EN

S

8

P C1 2 2

5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9

2 . 2 u _6 . 3 V _ X 5R _ 06

P C2 4

SW

GN D 6

P C 12 1

5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9

4

5VS

HG

P WM

G

C

2 K _ 1 %_ 0 4

B ST

G
0 _ 06
V R E G _S W 3_ H G

D

3

1125
P R 16 6
V R E G_ S W 3 _H G_ R

D

2

0. 2 2 u _1 0 V _ X 7R _ 06
N C P 5 9 11

P Q3 0
*MD U 2 6 5 7

Sheet 38 of 46
Power V-Core2
VGFX

P C1 2 8
*4 . 7 u _2 5 V _ X 5 R _ 0 8

0. 2 2 u _1 0 V _ X 7R _ 06

P Q 32
M DU2 6 5 7

G
G

N C P 5 9 11

5

VR EG_ SWA _L G

11/09

C

P D2

*1 5 m li _ 0 6

VGFX_CORE

P L3
0. 3 6 u H _ 1 0* 10 * 3. 5
1
2

25A

VG FX_ C OR E

PC3 7
+ P C1 4 7

+P C 16 4

*1 00 0 p _5 0 V _ X 7R _ 04
G

G

PAD
A

C S O D 1 4 0S H

9

V_GT
PR6 0

P R 59

*1 5m i l _0 6

P R 58

*1 5m i l _0 6

PR6 1

C S NA

37

C SPA

37

*5 . 1 _0 6

0105 D02

3 30 u F _ 2 . 5V _ 9 m _ 6. 3 *6

LG

VGFX_CORE

*3 30 u _ 2. 5 V _ 9 m _6 . 3 *6

VC C

P Q 43
M DU2 6 5 4

S

4

P Q4 4
*MD U 2 6 5 4

GN D 6

EN

2 K _ 1 %_ 0 4

VR EG_ SWA
D

3

PR5 4
0224

7

SW

P WM

5VS

VR EG_ SWA _H G

D

D R ON

HG 8

S

37

2

PC 3 8

V R 1 _ P W MA

2. 2u _ 6 . 3V _ X 5 R _ 0 6

37

B ST

S

S

PU 3
1

P C 12 6
0 . 1 u_ 5 0 V _Y 5V _ 0 6

PC1 2 7
*4 . 7 u _ 25 V _ X 5 R _ 0 8

P Q3 3
*MD U 2 6 5 7
2. 2_ 0 6

P C1 2 3
+

VIN

D

P C 30

D

P R5 2

1 5 u_ 2 5 V _6 . 3 *4 . 4

0104 D02 EMI

V C OR E 5 , 3 7
V _ GT
37
V G F X _C OR E 6
1 1 , 31 , 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7, 39 V I N
1 1 , 12 , 1 9 , 2 0, 2 6 , 3 0, 3 1 , 3 2, 37 5 V S

Power V-Core2 VGFX B - 39

B.Schematic Diagrams

VIN

P C 18

P C 12 0

15 u _ 25 V _ 6 . 3* 4 . 4

P C 13 0
+

1

PR3 0
0224

0. 1 u _ 50 V _ Y 5 V _ 06

*3 30 u F _ 2 5V

*4 . 7u _ 2 5V _X 5 R _0 8

VC OR E

5. 1 _ 0 6

2. 2 _ 0 6

D R ON

25A

P L6
0. 3 6 u H _ 1 2. 9 * 14 *3 . 8
1
2

VCO RE

G

9

PU 2

V R 1 _ P W M3

P C 16 1

P C3 6

V R E G_ S W 1 _ L G

5

P Q4 0
MD U 2 65 7

37

P Q2 8
*MD U 2 6 5 4

P C 14 9

PAD

P R2 9

37

S

P Q 46
M DU2 6 5 4

P C1 2 5

2. 2u _ 6 . 3V _ X 5 R _ 0 6

P Q 38
M DU2 6 5 4

GN D 6

P C1 5 2

11/03

C

2 K _ 1 %_ 0 4

5VS

SW

G

0 _ 06
V R E G _ S W 1 _H G

V R E G_ S W 1 _ OU T

7

S

D R ON

P WM

P R 16 5
V R E G_ S W 1 _ H G _ R

8

D

37

3

PR1 3 8
0224

HG

D

V R 1 _ P W M1

B ST

D

37

2

P Q3 9
*MD U 2 6 5 7

G
S

1

1125

N C P 5 9 11

D

PU 8

D

P Q 29
M DU2 6 5 7
0. 2 2 u _1 0 V _ X 7R _ 06

D

P C 11 9

2. 2 _ 0 6

D

P R1 3 6

P C 13 3
+
15 u _ 25 V _ 6 . 3* 4 . 4

P C 22 3
+

*4 . 7 u _2 5 V _ X 5 R _ 0 8

VCORE_2

Schematic Diagrams

AC IN, CHARGER
01 0 4 D 0 2

PR1 6 1

0 _ 04

PR2 5 3

* 47 0 K _0 4

V IN

EMI

PQ 2
ME P 44 3 5 Q8
5
6
7
8

4

VA

1
2
3

P C 31 2

P C 31 1

P C3 1 0

0 . 1 u_ 5 0 V _Y 5V _0 6

0. 1 u _ 50 V _ Y 5 V _ 06

V _B A T

J_ D C _ JA C K 1

11 2 9

EMI

12

P R 2 50
10 _ 06

C

A

D

P D 2 5 R B 0 5 40 S 2

B S TOZ8681 I C H M

1

V D DP

15

IA C M

3

IA C P

2

AC AV

9

VAC

S DA

V DD P

SC L

IA CM

IAC

IA CP

C O MP

A CA V

4 . 7 u_ 2 5 V _X 5 R _ 0 8

4 . 7u _ 25 V _ X 5 R _ 0 8

4 . 7 u _2 5 V _ X 5R _ 08

0 . 1 u _5 0 V _ Y 5V _ 0 6
P C 2 35

P C 30 8

P C3 0 9

P C 2 38

1 0 _0 6

4 . 7 u_ 2 5V _X 5 R _ 0 8

P R 2 57

P C 23 9

10 _ 0 6

5
10
7

S M C _ B A T _R
S M D _ B A T _R
1

8

4
3
2
1
J B A T TA 2
B T D -0 5T I 1 G

F C M1 00 5 K F -1 2 1T 0 3

IA C 1
28

C OMP _ O

2 P L 1 2 B A T _ D E T _R

B A T_ D E T

6
PR1 6 3
0 _0 4

F C M1 0 05 K F -1 2 1T 0 3 1

2

P L1 4

S MC _ B A T 2 8

F C M1 0 05 K F -1 2 1T 0 3 1

2

P L1 3

S MD _ B A T 2 8

PR1 6 4
*1 5m i l _s h or t _0 6

PC2 9 9
3 0p _ 50 V _ 0 4
PC1 3 7

PR1 6 2
1 00 _ 04

P C 2 36
1 u _ 10 V _ 0 6

P C1 3 8
1 u_ 1 0 V _0 6

PC3 0 0

0 . 47 u _ 10 V _ Y 5 V _ 0 4

3 0p _ 50 V _ 0 4
P R2 8 9

1 0 _ 06

TO TA L _ C U R 2 8

PC3 0 1
3 0p _ 50 V _ 0 4

V DD3

R es et c ir cu it

4
3
2
1
J B A T TA 1
*B T D -0 5 T C 1 B

W240HU

P C 22 7
1 u _2 5 V _ 08

1 00 0 P _5 0 V _ X 7 R _ 04

1 00 K _ 0 4

P C1 3 6
*1 u _ 25 V _ 08

IC HM

V D DA

17

P U 10
PC2 2 4
*1 u _2 5 V _ 08

IC HP

5

11

S

G

P C 13 2

4 . 7 u_ 2 5V _X 5 R _ 0 8
13

4

IC HP

B ASE

VAC

W250HU

1229 D02

H DR
5

EM I

P C 3 0 6 P C 30 7
0 . 1 u_ 5 0 V _Y 5V _ 0 6

16

1 1 30

0 . 1u _ 5 0V _ Y 5 V _ 06

C

L DR
0 _0 4 B S T

LD R

P R 16 0

P R2 5 6

P C 2 31

L X _C H G 1 4
LX

P Q9 6
MT N 70 0 2 Z H S 3

P C1 3 5

0. 0 4 7 u_ 1 0V _X 7 R _ 0 4
P C 2 37
0 . 1 u _5 0 V _ Y 5 V _0 6
BST_ L

PR2 8 8

Sheet 39 of 46
AC IN, CHARGER

JBA TT A1

PR 4
0. 0 2 _ 1% _ 32
4. 7 u _ 25 V _ X 5 R _ 0 8
P C 23 0

P C 23 4

4

P R 29 0

4 . 7 u _2 5 V _ X 5R _0 8
P C2 3 2

* 10 0 0 p_ X 7R _ 06
P Q 1B
P D 15 0 3Y V S

4 . 7 u_ 2 5V _ X 5 R _ 0 8
P C 2 33

5
6

P C 30 2

3

* 5. 1 _ 0 6

0 . 0 47 u _1 0 V _ X7 R _0 4

0224

PL 1 1
T MP C 06 0 3 H -8 R 2 M-Z 0 1

7

8

4 . 7 u _2 5 V _X 5R _0 8

10 _ 0 6

4. 7 u _2 5 V _ X 5R _ 08

P R2 8 3

1 0 _0 6

4 . 7 u_ 2 5 V _X 5 R _0 8

P C 22 5

P C 2 28

PR 1
1 5 K _0 4

MD L9 1 4S 2

0224

P C2 9 8

S MC _B A T
4 7p _ 5 0V _ N P O_ 04
P R 2 55
P R2 5 9
P Q 97
M TP 3 4 0 3N 3
S
D

V_ BAT

1 00 _ 0 4

1 0 K _ 04

P R 2 87
3 0 0K _1 % _0 4
B A T _ V OL T 28

D
C H G_ R S T

P Q9 5
1 0 0K _1 % _0 4

G

P R2 4 6

P C 2 29

6 0. 4 K _ 1 %_ 0 4

0 . 1 u _1 6 V _ Y 5 V _ 04

A C _I N #

VA

P R 2 51

27 , 2 8

P Q3 7
MT N 7 0 0 2Z H S 3

G

1M _0 4

S

28

P R 24 7

1 0 0 K _0 4

G

P R2 5 8

D

1229 D02

MT N 70 0 2Z H S 3
P R 25 2
D

S

2 0 0K _1 % _0 4

G

PCBLay out no tes

SY S3 V
S

B.Schematic Diagrams

P D1 4

P R 28 0

EMI

2
1

? ?

8. 2U H_ 7.3 *6 .6* 2. 8MM

P Q1 A
P D 1 50 3 Y V S

P R 2 49
0 . 0 2_ 1 %_ 3 2

P C 10 8

1 13 0

PR 2
1 0 0K _ 0 4

A

D02A

4

0 . 1 u_ 5 0 V _Y 5 V _ 0 6

0 . 1 u_ 5 0 V _Y 5 V _ 0 6

0 . 1 u_ 5 0 V _Y 5 V _0 6
65 W ~ 9 0W / 3 P I N (6-2 0 -B 3 41 0 -0 03 / 6 -2 0-B 3 4 2 0-0 0 3 / 6-2 0 -B 3 43 0 -0 03 / 6 -2 0-B 3 4 2 0-1 0 3)
VA
PL 2
P Q9 4
H C B 4 5 32 K -8 0 0T 9 0
ME P 44 3 5Q 8
8
P C 10 5
1
P C 30 5
7
3
2
6
2
3
5
1
G ND 1
P R 2 82
G ND 2
1 0 K _ 04

P Q9 8
MT N 70 0 2 Z H S 3

U S B _A C _ I N 3 3

1) All power traces sh ould b e routed on the outer layer s
GNDP, VAD, VSYS, LX, VCHG, VBATT

V D D3

2) Use Kelvin connections f or R3, R4
(se perate f orce and measu rement trace s)

C

3) R23 and R24 are du mmy r esisto rs, for layout purpo ses only
(se rves as single point connection betw een GNDP&GNDA)

AC
P D1 6
B A V 9 9 R E CT IF IE R

1126 POWER CHANGE

S MC _ B A T

C

S MD _ B A T

4) Fo otprint TO-236 is equivalent to SOT- 23

AC
P D2 6
B A V 9 9 R E CT IF IE R

A

A
C

5) Fo otprint SIP/1Pis a single hole axialp ad
6) All resisitors, capac itor s and semiconductor s are SMD

B A T _ DE T

AC
P D2 7
B A V 9 9 R E CT IF IE R

A
C

B A T _ V OL T

AC
A

7) Po tentio meter s, and test p oints a re axial devices

B - 40 AC IN, CHARGER

P D1 9
B A V 9 9 R E C TI F I E R

33
SY S3 V
3 2, 3 3 , 35 S Y S 1 5V
32
V A
1 3 , 14 , 1 5 , 17 , 1 8 , 20 , 2 2 , 23 , 2 4 , 25 , 2 8, 32 , 3 3, 3 5 V D D 3
11 , 3 1 , 32 , 3 3 , 34 , 3 5 , 36 , 3 7 , 38 V I N

Schematic Diagrams

CLICK & FINGER BOARD
D
R
A
O
B
R
E
G
N
I
F

CLICK BOARD
C C1
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4

C C2
*0 . 1 u _1 6 V _ Y 5 V _ 0 4
C VD D3

TU S B _ P N 10
TU S B _ P P 1 0

8 5 2 01 -0 6 0 51

CL E D _ P W R
CL E D _ A CIN
C L E D _ B A T _F U L L
C L E D _ B A T _C H G

C D2 7
2

C R4
*2 2 0 _0 4

* K P B -3 0 25 Y S GC

BAT LED

3

POWER ON
LED

1

3

1

* 22 0 _ 04

Y
SG

1
2
3
4
5
6

CT P _ CL K
C T P _ D A TA
C T P B U T TO N _ L
C T P B U T TO N _ R

CR 3

* 22 0 _ 0 4

TX I N
TX O U T

C D 26
T 3 .3 V

*K P B -30 2 5 Y S G C

TM OS I
TM C L K
TM C S
TN R E S E T
T3 . 3 V

11/04

CG ND

CG ND

CG ND

6-21-91A00-106
6-21-91A20-106

CG ND

C GN D

T US B_ P N _ R
T US B_ P P _ R

C GN D

CG ND

6-52-55002-042
6-52-55002-04E
W240HU
W250HU

23

1

24
TOP VIEW

2

2
24
BOTTON VIEW

? ? ?
? ?

4
3

RIGHT
KEY

C SW 1
T J G -53 3 -S -T / R

LIFT
KEY

C SW 2
T J G-5 3 3 -S -T / R
1
3

C T P B U TT O N _ R

2
4

5
6

5
6

2
4

CG ND

C GN D

6-53-3050B-042

CSW 4
*T J G-5 3 3 -S -T / R
1
3

C T PB UT T O N_ L

5
6

1
3

C T P B U T T ON _L

C GN D

6-53-3050B-042

Sheet 40 of 46
CLICK & FINGER
BOARD

RIGHT
KEY

CS W 3
*T J G- 53 3 -S -T / R

2
4

C TP B U T T ON _ R

5
6

LIFT
KEY

CG ND

6-53-3050B-042

6-53-3050B-042

1124
CH 3
2
3
4
5

1

CH 1
9
8
7
6

2
3
4
5

M TH 2 37 D 91
CG ND

CH 4
9
8
7
6

1

2
3
4
5

M TH 2 37 D 91
C GN D

CH 2
9
8
7
6

1

2
3
4
5

M TH 2 37 D 91

CG ND

C GN D

CG ND

CH 5
C9 5 D9 5

9
8
7
6

1

DEL TD1 , TD2

CH 6
H O -1 65 X 9 4_ 5 N P

M TH 2 37 D 9 1
C GN D

CG ND

C GN D

TBEZEL 1
TU 2
TR 1 1

*4 . 7 K _ 0 4

T MI S O

TR 1 0

*4 . 7 K _ 0 4

T MO S I

TR 9

4 . 7 K _ 04

T 3. 3 V

T X IN

T R1 9

1 M_ 0 4

T GN D

T X OU T

T RE F _ O S C

TR 1 6

T XIN_ R

4 7 K _ 04

2

1

3

4

1 u _6 . 3 V _ X 5 R _ 0 4

TC 4

2 7 p_ 5 0 V _ N P O _ 04

TR 1 4

10 0 _ 1% _ 0 4

1

T B DR IV E 2

TR 1 7

10 0 _ 1% _ 0 4

2

C GN D

* 3 2m i l _s h o rt
T R 1 5 T E S D_ G ND

TBEZEL 2

R C L A M P 0 50 2 B

HSX531S+-2 0ppm

T G ND

T C1 6

TX1
H S X5 3 1 S _ 12 M H Z

T E S D _ GN D

T 3. 3V

3 3 p_ 5 0 V _ N P O _ 04

T 3. 3 V

TC 1 5

T B DR IV E 1

3

CG ND
T NR E SE T

4 7 0 _0 4

T R1 8

T U1

TC 1 7

T C1 8

18 p _ 5 0V _N P O_ 0 4

1 8p _ 5 0 V _N P O _0 4

5
2
1
6

T MO S I
T MI S O
T MC S
T MC L K

CG ND

8
S
Q
CS #
SC K

V DD

3
W P#

T C1 0
0 . 1u _ 1 6 V _Y 5 V _ 04

0224

CG ND

CG ND

4

CG ND

VSS

HO L D#

7

M 95 1 2 8 W MN 6 TP
T US B _ P N _ R
T P D_ RE G

TR 5

3 3 0K _0 4

TC 3

1 u _6 . 3 V _ X 5 R _ 0 4

TR 4

2 7 . 4 _1 % _ 0 4

T U S B _P N 1 0

C GN D

CG ND

951206

T 3. 3 V
T 3 .3 V

T C2
4 7 p_ 5 0 V _ N P O _ 04

TC 8

TC 6

T C1 1

1 u _ 6 . 3V _X 5 R _ 0 4

1u _ 6 . 3 V _ X5 R _0 4

0 . 1u _ 1 6 V _ Y 5 V _ 0 4

T A V DD
T R E G _O U T
TC 13

CG ND

TR 13
2 . 2 _1 % _ 0 6

TC 1 2

T C1 4

T U S B _ C ON N

TR 2

1 . 5 K _ 1% _ 0 4

T US B _ P P _ R

TR 3

2 7 . 4 _1 % _ 0 4

T U SB_ PP1 0

CG ND
1 u_ 1 0 V _ 06

1u _ 1 0 V _0 6

0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
T C1
4 7 p_ 5 0 V _ N P O _ 04

CG ND

CG ND
CG ND

CLICK & FINGER BOARD B - 41

B.Schematic Diagrams

6-52-55002-042
6-52-55002-04E

CSW1~4

2
4

TAVD D

T MI S O
T U S B _ C ON N
T P D_ RE G

Pla ce Bott on

J_FP1

1
3

TBEZEL 1
TBEZEL 2

*C ON 24 A

11/0 4

CG ND

6-21-91A00-106
6-21-91A20-106

2
1

T RE F _ O S C

* 85 2 0 1 -06 0 5 1

8 84 8 6 -0 80 1
CG ND

24
22
20
18
16
14
12
10
8
6
4
2

4

1
2
3
4
5
6

T3 . 3 V

C R2

4

CJ _ T P 3

1
CT P _ D AT A
C T P _ C LK

Y

CJ _ T P 2

* 2 20 _ 0 4

CG ND

SG

CG ND

2

1
2
3
4
5
6
7
8

T J_ F P B 1
23
21
19
17
15
13
11
9
7
5
3
1

TR E G _O U T
TB D R I V E 1
TB D R I V E 2
CR 1

CJ _ T P 1

C L E D _ B A T _F U L L

C C3
*0 . 1 u _1 6 V _ Y 5 V _ 0 4

C 5 VS

CG ND

C L E D _ B A T _C H G

C L ED_ P W R

2

C 5 VS

C L ED_ A C IN

Schematic Diagrams

AUDIO BOARD/ USB
USB PORT
A _U S B V C C
AL 5
H C B 1 6 0 8K F -12 1 T 25

A_ USBV C C2

60 mil

A _U S B V C C
AU 1
5

6

50 mil s

+

F L G# V OU T 1

5 0mi ls

2

1 0 0u _ 6 . 3V _ B _ A
A C5

A C6

0. 1u _ 16 V _ Y 5 V _ 0 4

0 . 1u _ 16 V _ Y 5 V _ 0 4

A J_ U S B 1

8
V I N 2 V OU T 3

4

1 0u _ 1 0V _ Y 5V _ 0 8

A US B _ P N2

1
EN #

A R1 0
AL 6 1
4

1

*1 0 mi l _ 04
3

V+

A G ND
A US B _ P N2 _ R

2

AUSB_ PP2 _ R

3

GN D

D A TA _ L
AUSB_ PP2

R T 97 1 5 B GS / S Y 62 8 8 D F A C
A GN D

0 . 1u _ 1 6V _ Y 5V _ 0 4

7
V I N 1 V OU T 2

3

A C9

A C7

A G ND

A G N D A GN D

A GN D

1
2
*A W C M2 0 1 2F 2 S -1 6 1T 0 3

D A TA _ H
G ND 1
GN D 2
G ND 3
GN D 4

A _5 V

AC 1

4

6-02-09715-920

A R1 1

G ND

*1 0 mi l _ 04

1228 D02

U S 0 4 03 6 B C A 0 8 1

GN D 1
GN D 2
GN D 3
GN D 4

PIN SWAP

6-21-B49C0-104
6-21-B49B0-104

B.Schematic Diagrams

A G ND

TO M/B

AUDIO JACK

Sheet 41 of 46
AUDIO BOARD/
USB

A MI C 1-L

A_ 5 V

AL 6

2
6
L
1
2S J -T 3 51 -S 2 3

F C M1 0 0 5K F -12 1 T 03
AC1 0

AC 4

10 0 p _5 0 V _ N P O_ 0 4

1 0 0p _ 5 0V _ N P O_ 0 4

A J_ A U D I O1
1
2
3
4
5
6
7
8
9
10
11
12
13
14

A MI C 1 -R
A MI C 1 -L
A
A
A
A
A
A
A

5 A J _ MI C 1
4
3
R

A MI C _ S E N S E
AL 4
F C M1 0 0 5K F -12 1 T 03

A MI C 1-R

H E A D P H ON E -R
H E A D P H ON E -L
MI C _ S E N S E
S P K _H P #
HP _ S E NS E
US B _ P N2
US B _ P P 2

A S P K OU TR +
A S P K OU TR -

MIC IN

6-20-B2800-106

BLACK
AHP_ S EN SE

A _ AUD G

A S P K _ HP #
A H E A D P H O N E -R

A R3

6 8_ 0 4

AL 2

F C M 10 0 5K F -12 1 T 03

A H E A D P H O N E -L

A R5

6 8_ 0 4

AL 3

F C M 10 0 5K F -12 1 T 03

8 7 21 3 -14 0 0 G

5 A J _ HP 1
4
R
3
2
6
1

AR 9

AR 8

A C3

A C2

*1 K _ 1 %_ 0 4

* 1K _ 1 % _0 4

1 00 p _ 50 V _ N P O _ 04

L

2S J -T 3 51 -S 2 3

1 00 p _ 50 V _ N P O _0 4

HEADPHONE

A _A U D G A G N D

6-20-53A00-114

BLACK 6-20-B2800-106
A _ AUD G

AC1 4

0 . 1 u_ 1 6 V _Y 5 V _0 4

AC1 5

0 . 1 u_ 1 6 V _Y 5 V _0 4

AC1 3

0 . 1 u_ 1 6 V _Y 5 V _0 4

AC1 6

0 . 1 u_ 1 6 V _Y 5 V _0 4

A GN D

A _ A UD G

A S P K O UT R+

AL 7
F C M1 0 05 K F -1 2 1T 0 3
1
2

A S P K O UT R-

A L8
F C M1 0 05 K F -1 2 1T 0 3
1
2

A C 11
1 0 0 0p _ 50 V _ X 7R _ 04

A C8
1 80 p _ 50 V _ N P O _0 4

A _ A UD G

A H1
C 5 9D 59

A H3
C5 9 D5 9

AH 2
2
3
4
5

1

A H4
9
8
7
6

2
3
4
5

M T H 2 76 D 11 1
A GN D

B - 42 AUDIO BOARD/ USB

9
8
7
6

1

MT H 2 7 6 D 1 1 1
A GN D A G N D

AG ND

A J _ S P K R 1 J_SPK1
2 1
1
2
85 2 0 4-0 2 00 1
P C B F o ot p ri n t = 8 5 2 04 -0 2 R

A S P K O UT R+ _ R
A S P K O U T R -_ R

AC1 7
1 80 p _ 50 V _ N P O _ 04

6-20-43150-102
6-20-43110-102

Schematic Diagrams

Power Switch & LID Board
POWER SW & LED & HOT KEY
S _ 3 . 3V S

S _3 . 3 V

POWER
SWITCH
LED

S_ 3 .3 V
S R2
S _ 3. 3 V S

SD2
*B A V 99 R E C T I F I E R

S _ 3 .3 V
22 0 _ 04

2 0mi l

S R1
1
2
3
4
5
6
7
8
8 8 48 6 -0 80 1

* 5 05 0 0-0 1 0 41 -0 0 1L

6-52-56001-023
6-52-56001-028
6-52-56000-020
6-52-56001-022

6-20-94K10-108

OU T

SC 2
0 . 1 u _1 6 V _ Y 5 V _0 4

MH 2 48 -A L F A -E S O
/P T3 6 61 G -BB

3

SD 1

S LI D _ S W #

2
VC C

*0 . 1 u _1 6 V _ Y 5 V _0 4

SC1
*1 00 p _ 50 V _ N P O _ 04

S MG N D
H T-1 5 0N B -D T

S M GN D
S M GN D

S MG N D

S MG N D
1228 D02
S MGN D

6-52-56001-023
6-52-56001-028
6-52-56000-020
6-52-56001-022

S M GN D

SU1, SU2

6-02-00248-LC2
6-02-00268-LC1

3
1

6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
POWER BUTTON
SPW R _ SW 1
T J G-5 3 3-S -T / R

S W W W _S W 1
T J G-5 3 3-S -T / R
S M_ B T N #

1
3

2
4
5
6

2
4
5
6

1
3

S_ VIN

6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
WEB_EMAIL#

6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
WEB_WWW#
SW EB_ W W W #

1 1/04

SC 4

2
4

S A P _S W 1
T J G-5 3 3 -S -T/ R

S W E B _E MA I L #

1
3

2
4

S C3
S R4
*0 _ 0 4

PSW1~8
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
3
4

*0 . 1 u_ 1 6V _Y 5V _ 0 4

2

Sheet 42 of 46
Power Switch & LID
Board

6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
AP_KEY#

SR 3
* 10 0 K _ 1% _ 0 4

S MA I L _ S W 1
TJ G-5 3 3 -S -T / R
1
3
5
6

HOT KEY

FOR E4120Q/E5120Q

S A P _O N

S C5

5
6

FOR E5128Q

SR 5
*4 7K _ 0 4

*0 . 1u _ 1 6V _ Y 5V _ 0 4

1
2

S MGN D

S M GN D

S M GN D

S MG N D

S MG N D

S MG N D

S MG N D

S M GN D
S MG N D

FOR E4120Q/E5120Q
POWER BUTTON
SPW R _ SW 2
* TJ G- 53 3 -S -T / R

S M H1
2
4

S M_ B T N #

S M H2
S MH 5
H 7_ 0 D 2 _ 3 H 7 _0 D 2_ 3

2
3
4
5

1

S MH 3
9
8
7
6

2
3
4
5

1

S MH 4
9
8
7
6

2
3
4
5

1

9
8
7
6

5
6

1
3

PSW1~8
3
4
S MGN D

6-53-3150B-245
6-53-3050B-240
6-53-3050B-241

M T H 2 37 D 87

1
2

S MG N D
S M GN D

MT H 2 3 7D 87
S M GN D

MT H 2 3 7D 1 18
S M GN D

S M GN D

S MGN D

FOR E5128Q

Power Switch & LID Board B - 43

B.Schematic Diagrams

1 0 pin & 8 pi n co- la y

A

S D3
* H T -1 5 0N B -D T

S MG N D

SAP_ O N

AC

S U1
SC6

GN D

S M GN D
S _ V IN

2 0m il
1

S M _B T N #
SW EB_ W W W #
S W EB _ E M A IL #
S L ID_ S W #

C

S M GN D

SAP_ O N

20 mi l

20 mi l

1 0 0 K _1 % _ 04

A

SJ _ SW 2
S M _B TN #
S W E B _W W W #
S W E B _E M A I L #
SL ID_ S W #

A

1
2
3
4
5
6
7
8
9
10

S _ 3 . 3V

C

SJ _ SW 1

LID SWITCH IC
C

S _ 3 . 3V S

Schematic Diagrams

EXTERNAL ODD BOARD

B.Schematic Diagrams

ODD BOARD FOR E5120Q

QJ _OD D 2
S1
S2
S3
S4
S5
S6
S7

Sheet 43 of 46
EXTERNAL ODD
Board

P1
P2
P3
P4
P5
P6

QJ_ODD 1
S1
S2
S3
S4
S5
S6
S7

QJ _S ATA_ TXP1
QJ _S ATA_ TXN 1
QJ _S ATA_ R XN 1
QJ _S ATA_ R XP1

QGN D

QGND

P1
P2
P3
P4
P5
P6

QJ _OD D_ D ETE CT#
Q_5VS

Q_5VS
QJ _S ATA_ ODD _DA#

1-162-1005 62
PI N
QGN D
G N D1~2 =WG ND

242001-1
P IN
GN D 1~3=QGN D

QGND

6-21-1 4010-0 13
6-21-1 4020-0 13
6-21-1 4030-0 13

6-21-1 3A00-0 13

Q_5V S

Q C2

QC1

0. 1u_16V_Y5 V_04

*0.1u_16V_Y 5V_04

QGND

B - 44 EXTERNAL ODD BOARD

QH1
C 237D91

QH 4
C 2 37D 91

QGN D

Q GN D

QH3
C 67D 67

QH2
C 67D 67

Schematic Diagrams

FINGERPRINT BOARD
F PJ T1
F R EG_OU T
F BD R I VE1
F BD R I VE2

FPU 1
U S B_C ON NE C T

B5

FU SB _CON N

B 11

FB DR I VE 1

B 10

FB DR I VE 2

A5

FB EZE L1

B DR I VE 1
B DR I VE 2
B EZE L1A

B7
NC1

B EZE L1B

B8
NC2

B EZE L2A
NC3

F MO SI
F MC LK
F MC S
F N R ESE T
F 3.3 V

FB EZE L2

The path be m arked in RED

F3. 3V

NC4

A 10
R EG_ OU T

FGN D

FR EG _OU T

ESD _G N D 1
ESD _G N D 2

01 03 D 02

? ?

D VD D 2
C9

F GN D

ESD _G N D 3
A4

FP D_ R EG

B2

FMC S

C6

FMI SO

B4

FMOSI

B3

FMC L K

B1

FU SB _PN

C1

FU SB _PP

A2

FN R ES ET

MOS I
MC LK
U S B_D N
U SB_D P
N R ESE T

FR EF _OS C

A8
ESD _GN D 4

D GN D 2

B6

23

1

2
24
BOTTON VIEW

24
2
TOP VIEW

F GN D

A GN D
XTALI N

23

F GN D

D GN D 1
C 11

C ha ng e to 6- 21 -4 17 00 -2 12

FJ1
1

C4
R EF _O S C

FU SB _P N
FU SB _P P

Sheet 44 of 46
FINGERPRINT
BOARD

F 3.3 V

A 11

MC S

FMI SO
FU SB _C O N N
FPD _R EG

FGN D

F GN D

A1

MIS O

F AVD D

F GN D

C3

D VD D 1

P D _R E G

FBE ZEL1
FBE ZEL2

6-2 1- 41 71 0- 21 2
F AVD D

A3

FR EF _OS C

FXI N

C8
A6

XTAL OU T

FG N D
FXOU T

TCS5XF

F G ND

FINGERPRINT BOARD B - 45

B.Schematic Diagrams

C 10
AV D D

2
4
6
8
10
12
14
16
18
20
22
24

SP N Z-24S 2-VB -017-1-R

needs to be design to be short and at low impedance.

C7
B EZE L2B

A9

B9
C2

C5

F XIN
F XOU T

The TES D_GND trace has to be w ide (> 20m il)

A7

1
3
5
7
9
11
13
15
17
19
21
23

Schematic Diagrams

POWER SEQUENCE
W243HVQ/W243HWQ-D01

POWER ON SEQUENCE

DD_ON
858us

5V
1.44ms

3.3V
92.764ms

RS MRST#
(SUSPW RDNACK)
SUS_P WR_ACK
S USCLK

102ms(RSMRST# to SUSPWRDNACK)
102.1ms(RSMRST# to SUSCLK)
102.1ms(RSMRST# to SUS_ACK#)

B.Schematic Diagrams

SUS _ACK#
SLP _SUS#

95.9ms(RSMRST# to SLP_SUS#)
18.5ms(SLP_SUS# to PWRBTN#)
0ms(RSMRST# to ACPRESENT)

ACPR ESENT
PWR _BTN#

Sheet 45 of 46
POWER
SEQUENCE

80ms(RSMRST# to PWR_BTN#)
206.83ms (RSMRST# to PWR_BTN#)
21.52ms(PWR_BTN# to SLP_A#)
103.915ms

(RSMRST# to SLP_A# spec:min 5ms)

S LP_A#
S LP_ME_CS W_DEV#
103.915ms(RSMRST# to SLP_LAN#)

SLP _LAN#
102ms(RSMRST# to SLP_S5#)

SL P_S5#
36.9us (SLP_S5# to SUSC# spec:min 30us)

(SLP_S4# )SUSC#
36.9us (SUSC# to SUSB#) (spec:min 30us)

(SLP_S3# )SUSB#
1.645ms(SUSB# to 1.05V_M)

3 .3V_M
(AP WROK)PM_ MPWROK

2.05ms(SUSB# to APWROK)
2.25ms(VCCSPI to APWROK

spec:min 1ms)

1.833ms(APWOK to 1.5V);299us(SUSB# to 1.5V)
245us(SUSB# to VCCPLL)
2.05ms(PM_MPWROK to 1.8VS); 3.874ms(1,5V to 1.8VS)

(VDDQ )1.5V
(VCCPLL) 1.8VS

113.54us(1.5V to DDR1.5V_PERGD)

DDR1.5V_ PWRGD
1.51ms(1.8VS to 1.8VS_PWRGD)

1.8VS_ PWRGD
3.9248ms(SUSB# to 1.05VS_VTT_EN)

1.05VS_V TT_EN
1.158ms(1.05VS_VTT_EN to 1.05VS_VTT);2.7ms(SUSB# to 1.05VS_VTT)

(V CCP)1.05 VS_VTT
1.976ms(1.05VS_VTT to 0.85VS);4.6275ms(SUSB# to 0.85VS)

(VCCA)0 .85VS
1.925ms

0.85VS_ PWRGD
3.7ms

VT T_MEM
345.1us

(Vc cCore PC H)1.5VS
603.7us

3.3VS
500us

5VS
1.646ms

1 .05VS
5.536ms

ALL_SYS_ PWRGD

B - 46 POWER SEQUENCE

Schematic Diagrams

POWER SEQUENCE 1
W243HVQ/W243HWQ-D01

POWER ON SEQUENCE

ALL_ SYS_PWRGD
3.4974s

(Vcc AXG)O.85VS
112.83ms

(PWROK) PM_PCH_PWROK
114.11ms

PM_D RAM_PWRGD
114.11ms

VccCore (CPU)VCORE

115.6ms
3.19ms(spec:min 2ms)
715.65us
115.63ms
3.9ms(spec:max 5ms)

IMVP_PW RGD(VR_Ready)
1.21ms

DE LAY_PWRGD
1.21ms

SYS_PWROK

Sheet 46 of 46
POWER
SEQUENCE 1

1.9ms

PLT_RST#
1.9ms

BUF _CPU_RST#

POWER SEQUENCE 1 B - 47

B.Schematic Diagrams

VDD PWRGOOD_R
(UN COREPWRGOOD)
H_ CPUPWRGD

B.Schematic Diagrams

Schematic Diagrams

B - 48

BIOS Update

Appendix C:Updating the FLASH ROM BIOS
To update the FLASH ROM BIOS you must:
•
•
•
•
•
•
•

Download the BIOS
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel.
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model
(see sidebar for important information on BIOS versions).

Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the
downloaded files.
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software).

BIOS Version
Make sure you download the latest correct
version of the BIOS appropriate for the computer model you are
working on.
You
should
only
download BIOS versions
that
are
V1.01.XX or higher as
appropriate for your
computer model.
Note that BIOS versions
are not backward compatible and therefore
you may not downgrade your BIOS to an
older version after upgrading to a later version (e.g if you upgrade
a BIOS to ver 1.01.05,
you MAY NOT then go
back and flash the BIOS
to ver 1.01.04).

Set the computer to boot from the external drive
1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the “+” and “-” keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
C - 1

C:BIOS Update

Download the BIOS update from the web site.
Unzip the files onto a bootable CD/DVD/USB Flash Drive.
Reboot your computer from an external CD/DVD/USB Flash Drive.
Use the flash tools to update the flash BIOS using the commands indicated below.
Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer.
After rebooting the computer you may restart the computer again and make anyrequired changes to the default BIOS
settings.



BIOS Update

Use the flash tools to update the BIOS
1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:

C:BIOS Update

C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
restarts.

Restart the computer (booting from the HDD)
1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults (or press F9) and select “Yes” to confirm the selection.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.

Your computer is now running normally with the updated BIOS
You may now enter the BIOS and make any changes you require to the default settings.

C-2

www.s-manuals.com



---

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