簡報 Cln16ffcll Sr V1d0 2p1 Usage Guide
cln16ffcll_sr_v1d0_2p1_usage_guide
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N16FFCLL V1.0 SRAM SPICE Model
Usage Guide
© 2016 TSMC, Ltd
1
Outline
© 2016 TSMC, Ltd
Model Overview
Guideline for Eldo Usage
Model Package
Usage file and flag settings
Usage of variation model
Netlist for usage of variation model
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Simulation Environment
Simulation Environment
Simulator:
Hspice Version
I-2013.12-SP2-1
Spectre Version
MMSIM14.1_ISR12
Eldo Version
15.1
O/S:
RH COMPILER/OS VERSION
gcc 4.1.2 / Red Hat Enterprise Linux AS release 4
`IN COMPILER/OS VERSION
Visual Studio 2008 / Windows 7
SUSE COMPILER/OS VERSION
gcc 4.1.0 / SUSE Linux Enterprise Server 10
SUN COMPILER/OS VERSION
SUNWspro (SUN Studio 11) cc 5.8 / Solaris 10 SPARC
SUN X86 COMPILER/OS VERSION
SUN Studio 12.1 cc 5.10 / Solaris 10 X86
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Guideline for Eldo Usage
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For users who use Eldo with Spice format netlist, the following command is
needed for simulation.
Add one more argument “-compat” to Eldo command line.
Command
ln24:/spice2> eldo –compat -i idsat.sp –o idsat.out
Netlist
Netlist keeps unchanged
* netlist for Idsat of DUT
*---------------------------------------------------------.temp 25
Command add “-compat”
.option brief=1
.lib ‘usage.l’ TT_SRAM
.lib ‘usage.l’ pre_simu_sr
.option brief=0
Vds0 d0 0 0.85
xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u
Please note if the native Eldo binary is wrapped in a shell script in the working system,
user needs to add the argument “-compat” to Eldo command line in the script.
shell script
© 2016 TSMC, Ltd
4
Model Package
The TMI model package provided by TSMC will contain the model file,
model usage files and the compiled shared libraries for different OS
platforms. Please put the overall files of the model package in the same
directory to do the model simulation.
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Compiled TMI Shared Libraries
Model File for Hspice/Eldo
Model File for Spectre
Model Usage File for Hspice/Eldo
Model Usage File for Spectre
All necessary option settings and the relative path of the compiled shared
libraries have been set in the model usage files. Simulators will detect the
settings in the model usage files and automatically link the correct TMI
library for the corresponding platform. Just make sure that your simulators
support TMI model process.
Both ‘x’ and ‘m’ prefix of the devices are supported in TMI model.
The message similar to the one shown below will be printed in the simulation
output file if the simulation is through TMI model process.
*********************************************************
** TMI Share Library
Version is xxxxxxxxxxxxxxx
*********************************************************
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Usage file and flag settings
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Usage File
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There are two sets of corners in N16 SRAM usage file.
Library “pre_simu_sr” have to be included for device level simulation, e.g. Idlin of PG.
Library “pre_simu_sr_cell” have to be included for cell level simulation, e.g. Icell of 6T SRAM.
Disabling the Rc_M0 of PG source site and PD drain site at cell level corners is the major difference of those two
sets. By doing that, the Icell simulation at pre_simu_sr_cell stage can close to the post-simu result.
At post-simu stage, Rc_M0 is extracted by LPE. No difference between device corners and cell corners.
(pre_simu_sr / pre_simu_sr_cell are forbidden)
1. Rc_M0 at both S/D are added at presimu stage of device corners by
including “pre_simu_sr” lib.
2. Rc_M0 at PG source site and PD
drain site are disabled at pre-simu
stage of cell corners by including
“pre_simu_sr_cell” lib.
PU
Rc_M0
PU
Rc_M0
PG
PG
Icell
PD
Vss
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PD
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Usage of Pre-layout Simulation
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The “Ccosflag”, “Ccodflag”, “Rcosflag”, “Rcodflag” and “Rgflag” are globally changed parameters
for MOS device.
The contact to poly cap, contact resistor and gate resistor are included when flags are set to 1
respectively for pre-layout simulation.
User can include a “pre_simu_sr” or “pre_simu_sr_cell” library to set flags for pre-layout device
level or cell level simulation respectively. (the pre_simu_sr and pre_simu_sr_cell lib are in usage.l )
pre_simu_sr
.lib pre_simu_sr
.param ccodflag_hcsr = 1
.param ccodflag_hdsr = 1
.param ccodflag_hpsr = 1
.param ccodflag_dpfsr = 1
.param ccosflag_hcsr = 1
.param ccosflag_hdsr = 1
.param ccosflag_hpsr = 1
.param ccosflag_dpfsr = 1
.param rcodflag_hcsr = 1
.param rcodflag_hdsr = 1
.param rcodflag_hpsr = 1
.param rcodflag_dpfsr = 1
.param rcosflag_hcsr = 1
.param rcosflag_hdsr = 1
.param rcosflag_hpsr = 1
.param rcosflag_dpfsr = 1
.param rgflag_hcsr = 1
.param rgflag_hdsr = 1
.param rgflag_hpsr = 1
.param rgflag_dpfsr =1
.endl pre_simu_sr
© 2016 TSMC, Ltd
Netlist_device corners
* netlist for Idsat of DUT
*---------------------------------------------------------.temp 25.000
.lib ‘usage.l' TT_SRAM
.lib ‘usage.l' pre_simu_sr
Vgs g 0 0.850
Vss s 0 0.000
Vbs b 0 0.000
.op
.dc Vgs 0 0.850 0.850
Vds1 d1 0 0.85
xmdut1 d1 g s b nchpg_hcsr_mac nfin=2 l=0.020u
.meas idsat_temp1 find i(Vds1) when v(g)=0.85
.meas idsat1 param='-idsat_temp1*1e6'
.end
Please notice that the library “pre_simu_sr”
(or “pre_simu_sr_cell”) need to be placed
behind TT_SRAM to prevent from the
redefine (flag change back to 0).
pre_simu_sr_cell
.lib pre_simu_sr_cell
.param ccodflag_hcsr = 1
.param ccodflag_hdsr = 1
.param ccodflag_hpsr = 1
.param ccodflag_dpfsr = 1
.param ccosflag_hcsr = 1
.param ccosflag_hdsr = 1
.param ccosflag_hpsr = 1
.param ccosflag_dpfsr = 1
.param cellflag_hcsr = 1
.param cellflag_hdsr = 1
.param cellflag_hpsr = 1
.param cellflag_dpfsr = 1
.param rcodflag_hcsr = 1
.param rcodflag_hdsr = 1
.param rcodflag_hpsr = 1
.param rcodflag_dpfsr = 1
.param rcosflag_hcsr = 1
.param rcosflag_hdsr = 1
.param rcosflag_hpsr = 1
.param rcosflag_dpfsr = 1
.param rgflag_hcsr = 1
.param rgflag_hdsr = 1
.param rgflag_hpsr = 1
.param rgflag_dpfsr = 1
.endl pre_simu_sr_cell
Netlist_cell corners
* netlist for Icell of hcsr
*---------------------------------------------------------.temp 25
.lib ‘usage.l' TT_SRAM
.lib ‘usage.l' pre_simu_sr_cell
.global vdd vss
.param pwr=0.85
XPpu1 bl_in g1 vdd vdd pchpu_hcsr_mac nfin=1 l=0.02u
XPpu2 blb_in g2 vdd vdd pchpu_hcsr_mac nfin=1 l=0.02u
XNpd1 bl_in g1 vss vss nchpd_hcsr_mac nfin=2 l=0.02u
XNpd2 blb_in g2 vss vss nchpd_hcsr_mac nfin=2 l=0.02u
XNpg1 bl wl bl_in vss nchpg_hcsr_mac nfin=2 l=0.02u
XNpg2 blb wl blb_in vss nchpg_hcsr_mac nfin=2 l=0.02u
vdd vdd 0 pwr
vss vss 0 0
vbl bl 0 pwr
vblb blb 0 pwr
vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)
v1 g2 bl_in 0
v2 blb_in g1 0
.nodeset v(bl_in)=0 v(blb_in)=pwr
.tran 0.05ns 0.8ns
.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'
.meas tran standby_ip find par('(i(vss)*1e12+i(vwl)*1e12)') at '0.1ns'
.end
8
N16FFC SRAM Flag Setting
Flag settings
The usage file handles all these flags, so the users don’t need to worry about them.
A flag in instance parameters has higher priority than a flag in model setup lib.
Global Flag in setup lib
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N16FFC Flag Setting
Flag settings
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Except the flag in Lib ‘setup_sr’ which can change the flag setting globally for all transistors when
simulation, some flags are added as instance parameters for user to change the flag for specified
transistors.
A flag in instance parameters has higher priority than a flag in model setup lib.
Flag in Instant parameters
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Usage of variation model
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Common Variation Simulation Options (1)
Traditional total corner approach
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Assumes all transistors in the chip are moving toward the same direction,
which is not realistic and may be too conservative.
In some circuits, this approach is too aggressive because it assumes no
mismatch between transistors.
Global corner only (or with local Monte Carlo)
As fast as traditional total corner simulation, but is more realistic.
Not suitable for circuits with very small number of transistors and mismatchsensitive circuits (analog).
Local Monte Carlo Only
For mismatch simulation.
Full Monte Carlo simulation (Global Monte Carlo + Local Monte Carlo)
The same global variation applies to all devices, while each device gets
random local variation.
Too slow.
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Common Variation Simulation Options (2)
Worst bit Icell Simulation approach
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Defined to simulate the worst bit Icell current.
It is done by SSg corner simulation with a given “nicell” value. Users can
set value based on their interested memory size and CDF%.
Worst bit Icell simulation for dual port (DP) SRAM cell has to add extra
instance parameter “wbifactor = 1” at PortB PG devices if Icell is extracted
by PortA PG devices and vice versa. (See page-21 for sample netlist)
Worst bit Icell simulation is only available for Vdd ~ 0.8*Vdd and 125C ~ -40C.
Dual port SRAM schematic circuit
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Model Usage File
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Pre-defined libs prepared in usage file
Collect the must-used libs to prevent from misuse
5 simulation cases are included in the usage file.
Add one more lib, .lib pre_simu_sr for device level and pre_simu_sr_cell for cell level,
to address parameter setting (ex. ccoflag, cellflag).
Total variation
Total variation corner
Local variation
Global variation
Global variation
FFG and SSG
Local variation
Mismatch
SS
TT
FF
TT
Parameter_1
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Parameter_1
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Netlist for usage of variation model
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Model Usage File: Case1
Case1: Conventional fixed corner model
It is identical to the existing TSMC fixed corner
.option nomod ingold=2
+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4
.option MODSRH=0
*---------------------------------------------------------.temp 25.000
.option brief=1
.lib ‘usage.l' TT_SRAM
.option brief=0
Vgs g 0 0.850
Vss s 0 0.000
Vbs b 0 0.000
Vds0 d0 0 0.850
mdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u
.op
.dc vgs 0 0.850 0.850
.print
+ id_dut0_=par('abs(i(Vds0))')
.end
© 2016 TSMC, Ltd
Set the devices’ Fin number and Ldrawn
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Model Usage File: Case2
Case2: Global variation only corner + local variation Monte Carlo
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Users can run mismatch model on top of each global variation only corner model.
Perform functional check on corner condition and understand design margin.
This methodology can help to check the contribution from local and global respectively.
Apply on mismatch/local variation sensitivity circuits: SRAM/Diff Amp/VCO/setup time/hold time
characterization, … etc.
.option nomod ingold=2
+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4
.option MODSRH=0
*---------------------------------------------------------.temp 25.000
.option brief=1
.lib ‘usage.l ' TTGlobalCorner_LocalMC_SRAM
.option brief=0
Global variation
FFG and SSG
Local variation
Vgs g 0 0.850
Vss s 0 0.000
Vbs b 0 0.000
Vds0 d0 0 0.850
xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u
Set the devices’ Fin number and Ldrawn
.op
.dc vgs 0 0.850 0.850 sweep monte=1
.print
+ id_dut0_=par('abs(i(Vds0))')
.end
© 2016 TSMC, Ltd
Parameter 1
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Model Usage File: Case3
Case3: Local variation Monte Carlo
The same purpose as conventional mismatch model.
.option nomod ingold=2
+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4
.option MODSRH=0
*---------------------------------------------------------.temp 25.000
.option brief=1
.lib ‘usage.l' LocalMCOnly_SRAM
.option brief=0
Vgs g 0 0.850
Vss s 0 0.000
Vbs b 0 0.000
Vds0 d0 0 0.850
xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u
Set the devices’ Fin number and Ldrawn
.op
.dc vgs 0 0.850 0.850 sweep monte=1
.print
+ id_dut0_=par('abs(i(Vds0))')
.end
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Model Usage File: Case4
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Case4: Global variation Monte Carlo + Local variation Monte Carlo
Global variation: all trans share one set of random numbers for each MC run.
Local variation: Each trans applies different set of random numbers for each MC run.
The result is a distribution function which can predict the silicon distribution accurately.
Can meet the rule listed on RHS completely.
.option nomod ingold=2
+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4
.option MODSRH=0
*---------------------------------------------------------.temp 25.000
.option brief=1
.lib ‘usage.l' GlobalMC_LocalMC_SRAM
.option brief=0
total2 global2 local2
global MC + local MC
Total variation
Vgs g 0 0.850
Vss s 0 0.000
Vbs b 0 0.000
Vds0 d0 0 0.850
xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u
Set the devices’ Fin number and Ldrawn
.op
.dc vgs 0 0.850 0.850 sweep monte=1
.print
+ id_dut0_=par('abs(i(Vds0))')
.end
© 2016 TSMC, Ltd
Total variation corner
Local variation
Global variation
Parameter 1
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Model Usage File: Case5-1
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Case5-1: Worst bit Icell simulation by global parameter setting:
XPpu1 bl_in g1 vdd vdd pchpu_hcsr_mac
XPpu2 blb_in g2 vdd vdd pchpu_hcsr_mac
XNpd1 bl_in g1 vss vss nchpd_hcsr_mac
XNpd2 blb_in g2 vss vss nchpd_hcsr_mac
XNpg1 bl wl bl_in vss nchpg_hcsr_mac
XNpg2 blb wl blb_in vss nchpg_hcsr_mac
nfin=1 l=LPU
nfin=1 l=LPU
nfin=2 l=LPD
nfin=2 l=LPD
nfin=2 l=LPG
nfin=2 l=LPG
vdd vdd 0 pwr
vss vss 0 0
vbl bl 0 pwr
vblb blb 0 pwr
vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)
v1 g2 bl_in 0
v2 blb_in g1 0
.nodeset v(bl_in)=0 v(blb_in)=pwr
.tran 0.05ns 0.8ns
.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'
.end
© 2016 TSMC, Ltd
“nicell”
Set the devices’ Fin number and Ldrawn
Worst bit Icell vs. nicell
Worst bit
Icell
.option gmindc=1.0E-18 gmin=1.0E-18
.prot
.lib ‘usage.l’ SSGlobalCorner_LocalMC_SRAM
.lib ‘usage.l' pre_simu_sr_cell
.unprot
.param nicell_hcsr=6
Set the global parameter
.global vdd vss
.param pwr=0.765
.temp -30
.param LPU=20N
.param LPD=20N Set the devices’ Ldrawn
.param LPG=20N
SSg corner
0
6
nicell
20
Model Usage File: Case5-2
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Case5-2: Worst bit Icell simulation by instance parameter setting:
.option gmindc=1.0E-18 gmin=1.0E-18
.prot
.lib ‘usage.l’ SSGlobalCorner_LocalMC_SRAM
.lib ‘usage.l' pre_simu_sr_cell
.unprot
.global vdd vss
.param pwr=0.765
.temp -30
.param LPU=20N
.param LPD=20N
.param LPG=20N
Set the devices’ Ldrawn
Set the devices’ Fin number and Ldrawn
nfin=1 l=LPU
nfin=1 l=LPU
nfin=2 l=LPD
nfin=2 l=LPD
nfin=2 l=LPG
nfin=2 l=LPG
vdd vdd 0 pwr
vss vss 0 0
vbl bl 0 pwr
vblb blb 0 pwr
vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)
v1 g2 bl_in 0
v2 blb_in g1 0
.nodeset v(bl_in)=0 v(blb_in)=pwr
.tran 0.05ns 0.8ns
.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'
.end
© 2016 TSMC, Ltd
nicell=6
nicell=6
nicell=6
nicell=6
nicell=6
nicell=6
Set the instance parameter “nicell”
Worst bit Icell vs. nicell
Worst bit
Icell
XPpu1 bl_in g1 vdd vdd pchpu_hcsr_mac
XPpu2 blb_in g2 vdd vdd pchpu_hcsr_mac
XNpd1 bl_in g1 vss vss nchpd_hcsr_mac
XNpd2 blb_in g2 vss vss nchpd_hcsr_mac
XNpg1 bl wl bl_in vss nchpg_hcsr_mac
XNpg2 blb wl blb_in vss nchpg_hcsr_mac
SSg corner
0
6
nicell
21
Model Usage File: Case5-3
Case5-3: Worst bit Icell simulation for dual port SRAM cell (DP only)
PortB
© 2016 TSMC, Ltd
It has to add extra instance parameter “wbifactor=1” at PortB PG devices if Icell is
extracted by PortA PG devices and vice versa.
The usage of “nicell” is same as “case5-1 or case5-2”.
.option gmindc=1.0E-18 gmin=1.0E-18
.prot
.lib ‘usage.l’ SSGlobalCorner_LocalMC_SRAM
.lib ‘usage.l' pre_simu_sr_cell
.unprot
.param nicell_dpfsr=6
.global vdd vss
.param pwr=0.765
.temp -30
xppu1 bl_in g1 vdd vdd pchpu_dpfsr_mac nfin=1 l=0.02u
xPpu2 blb_in g2 vdd vdd pchpu_dpfsr_mac nfin=1 l=0.02u
xNpd1 bl_in g1 vss vss nchpd_dpfsr_mac
nfin=4 l=0.02u
xNpd2 blb_in g2 vss vss nchpd_dpfsr_mac nfin=4 l=0.02u
xNpg1 bl wl bl_in vss nchpg_dpfsr_mac
nfin=2 l=0.02u
xNpg2 blb wl blb_in vss nchpg_dpfsr_mac nfin=2 l=0.02u
xNpg3 blx wlx bl_in vss nchpg_dpfsr_mac nfin=2 l=0.02u wbifactor=1
xNpg4 blbx wlx blb_in vss nchpg_dpfsr_mac nfin=2 l=0.02u wbifactor=1
vdd vdd 0 pwr
vss vss 0 0
vbl bl 0 pwr
vblb blb 0 pwr
vblx blx 0 pwr
vblbx blbx 0 pwr
vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)
vwlx wlx 0 pwl (0 0 0.2ns 0 0.3ns pwr)
v1 g2 bl_in 0
v2 blb_in g1 0
.nodeset v(bl_in)=0 v(blb_in)=pwr
Extract Icell from PortA PG
.tran 0.05ns 0.8ns
.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'
.end
Worst bit Icell vs. nicell
Worst bit
Icell
PortA
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SSg corner
0
6
nicell
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Iboff Worst Case Model Usage
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The “iboff_flag” is a globally changed parameter.
The worst case Iboff scenario will be activated if user sets iboff_flag=1
The “iboff_flag” is included in all total corners.
* netlist for Idsat of DUT
*---------------------------------------------------------.temp 25
.lib ‘usage.l' tt_sram
.param iboff_flag_hcsr=1
Vds0 d0 0 0.85
xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u
.op
.dc vgs 0 0.85 0.85
.print
+ id_dut0_=par('abs(i(Vds0))')
.end
© 2016 TSMC, Ltd
SS
TT
FF
iboff_flag_hcsr=1
Iboff(pA)
Vgs g 0 0.85
Vss s 0 0
Vbs b 0 0
Iboff Worst Case
1.0E+01
iboff_flag_hcsr=0
1.0E+00
1.0E+00
1.0E+01
Isoff(pA)
1.0E+02
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