簡報 Cln16ffcll Sr V1d0 2p1 Usage Guide

cln16ffcll_sr_v1d0_2p1_usage_guide

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N16FFCLL V1.0 SRAM SPICE Model

Usage Guide

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-Outline

Model Overview

Guideline for Eldo Usage

Model Package

Usage file and flag settings

Usage of variation model

Netlist for usage of variation model

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2 Simulation Environment

-Simulation Environment

Simulator:

Hspice Version

 I-2013.12-SP2-1

Spectre Version

 MMSIM14.1_ISR12

Eldo Version

 15.1

O/S:

RH COMPILER/OS VERSION

 gcc 4.1.2 / Red Hat Enterprise Linux AS release 4

`IN COMPILER/OS VERSION

 Visual Studio 2008 / Windows 7

SUSE COMPILER/OS VERSION

 gcc 4.1.0 / SUSE Linux Enterprise Server 10

SUN COMPILER/OS VERSION

 SUNWspro (SUN Studio 11) cc 5.8 / Solaris 10 SPARC

SUN X86 COMPILER/OS VERSION

 SUN Studio 12.1 cc 5.10 / Solaris 10 X86

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-For users who use Eldo with Spice format netlist, the following command is

needed for simulation.

Add one more argument “-compat” to Eldo command line.

Please note if the native Eldo binary is wrapped in a shell script in the working system,

user needs to add the argument “-compat” to Eldo command line in the script.

* netlist for Idsat of DUT

*----------------------------------------------------------

.temp 25

.option brief=1

.lib ‘usage.l’ TT_SRAM

.lib ‘usage.l’ pre_simu_sr

.option brief=0

Vds0 d0 0 0.85

xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u

Netlist Netlist keeps unchanged

shell script

Guideline for Eldo Usage

ln24:/spice2> eldo –compat -i idsat.sp –o idsat.out

Command

Command add “-compat”

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-The TMI model package provided by TSMC will contain the model file,

model usage files and the compiled shared libraries for different OS

platforms. Please put the overall files of the model package in the same

directory to do the model simulation.

-All necessary option settings and the relative path of the compiled shared

libraries have been set in the model usage files. Simulators will detect the

settings in the model usage files and automatically link the correct TMI

library for the corresponding platform. Just make sure that your simulators

support TMI model process.

-Both ‘x’ and ‘m’ prefix of the devices are supported in TMI model.

-The message similar to the one shown below will be printed in the simulation

output file if the simulation is through TMI model process.

*********************************************************

** TMI Share Library Version is xxxxxxxxxxxxxxx

*********************************************************

Model Package

Compiled TMI Shared Libraries

Model File for Hspice/Eldo

Model Usage File for Hspice/Eldo

Model Usage File for Spectre

Model File for Spectre

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Usage file and flag settings

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6 Usage File

Rc_M0 Rc_M0

1. Rc_M0 at both S/D are added at pre-

simu stage of device corners by

including “pre_simu_sr” lib.

Vss

Icell

2. Rc_M0 at PG source site and PD

drain site are disabled at pre-simu

stage of cell corners by including

“pre_simu_sr_cell” lib.

-There are two sets of corners in N16 SRAM usage file.

Library “pre_simu_sr” have to be included for device level simulation, e.g. Idlin of PG.

Library “pre_simu_sr_cell” have to be included for cell level simulation, e.g. Icell of 6T SRAM.

Disabling the Rc_M0 of PG source site and PD drain site at cell level corners is the major difference of those two

sets. By doing that, the Icell simulation at pre_simu_sr_cell stage can close to the post-simu result.

At post-simu stage, Rc_M0 is extracted by LPE. No difference between device corners and cell corners.

(pre_simu_sr / pre_simu_sr_cell are forbidden)

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7 Usage of Pre-layout Simulation

.lib pre_simu_sr

.param ccodflag_hcsr = 1

.param ccodflag_hdsr = 1

.param ccodflag_hpsr = 1

.param ccodflag_dpfsr = 1

.param ccosflag_hcsr = 1

.param ccosflag_hdsr = 1

.param ccosflag_hpsr = 1

.param ccosflag_dpfsr = 1

.param rcodflag_hcsr = 1

.param rcodflag_hdsr = 1

.param rcodflag_hpsr = 1

.param rcodflag_dpfsr = 1

.param rcosflag_hcsr = 1

.param rcosflag_hdsr = 1

.param rcosflag_hpsr = 1

.param rcosflag_dpfsr = 1

.param rgflag_hcsr = 1

.param rgflag_hdsr = 1

.param rgflag_hpsr = 1

.param rgflag_dpfsr =1

.endl pre_simu_sr

pre_simu_sr

* netlist for Icell of hcsr

*----------------------------------------------------------

.temp 25

.lib ‘usage.l' TT_SRAM

.lib ‘usage.l' pre_simu_sr_cell

.global vdd vss

.param pwr=0.85

XPpu1 bl_in g1 vdd vdd pchpu_hcsr_mac nfin=1 l=0.02u

XPpu2 blb_in g2 vdd vdd pchpu_hcsr_mac nfin=1 l=0.02u

XNpd1 bl_in g1 vss vss nchpd_hcsr_mac nfin=2 l=0.02u

XNpd2 blb_in g2 vss vss nchpd_hcsr_mac nfin=2 l=0.02u

XNpg1 bl wl bl_in vss nchpg_hcsr_mac nfin=2 l=0.02u

XNpg2 blb wl blb_in vss nchpg_hcsr_mac nfin=2 l=0.02u

vdd vdd 0 pwr

vss vss 0 0

vbl bl 0 pwr

vblb blb 0 pwr

vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)

v1 g2 bl_in 0

v2 blb_in g1 0

.nodeset v(bl_in)=0 v(blb_in)=pwr

.tran 0.05ns 0.8ns

.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'

.meas tran standby_ip find par('(i(vss)*1e12+i(vwl)*1e12)') at '0.1ns'

.end

Netlist_device corners

.lib pre_simu_sr_cell

.param ccodflag_hcsr = 1

.param ccodflag_hdsr = 1

.param ccodflag_hpsr = 1

.param ccodflag_dpfsr = 1

.param ccosflag_hcsr = 1

.param ccosflag_hdsr = 1

.param ccosflag_hpsr = 1

.param ccosflag_dpfsr = 1

.param cellflag_hcsr = 1

.param cellflag_hdsr = 1

.param cellflag_hpsr = 1

.param cellflag_dpfsr = 1

.param rcodflag_hcsr = 1

.param rcodflag_hdsr = 1

.param rcodflag_hpsr = 1

.param rcodflag_dpfsr = 1

.param rcosflag_hcsr = 1

.param rcosflag_hdsr = 1

.param rcosflag_hpsr = 1

.param rcosflag_dpfsr = 1

.param rgflag_hcsr = 1

.param rgflag_hdsr = 1

.param rgflag_hpsr = 1

.param rgflag_dpfsr = 1

.endl pre_simu_sr_cell

pre_simu_sr_cell

* netlist for Idsat of DUT

*----------------------------------------------------------

.temp 25.000

.lib ‘usage.l' TT_SRAM

.lib ‘usage.l' pre_simu_sr

Vgs g 0 0.850

Vss s 0 0.000

Vbs b 0 0.000

.op

.dc Vgs 0 0.850 0.850

Vds1 d1 0 0.85

xmdut1 d1 g s b nchpg_hcsr_mac nfin=2 l=0.020u

.meas idsat_temp1 find i(Vds1) when v(g)=0.85

.meas idsat1 param='-idsat_temp1*1e6'

.end

Netlist_cell corners

Please notice that the library “pre_simu_sr”

(or “pre_simu_sr_cell”) need to be placed

behind TT_SRAM to prevent from the

redefine (flag change back to 0).

The “Ccosflag”, “Ccodflag”, “Rcosflag”, “Rcodflag” and “Rgflag” are globally changed parameters

for MOS device.

The contact to poly cap, contact resistor and gate resistor are included when flags are set to 1

respectively for pre-layout simulation.

User can include a “pre_simu_sr” or “pre_simu_sr_cell” library to set flags for pre-layout device

level or cell level simulation respectively. (the pre_simu_sr and pre_simu_sr_cell lib are in usage.l )

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8 N16FFC SRAM Flag Setting

-Flag settings

The usage file handles all these flags, so the users don’t need to worry about them.

A flag in instance parameters has higher priority than a flag in model setup lib.

Global Flag in setup lib

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9 N16FFC Flag Setting

-Flag settings

Except the flag in Lib ‘setup_sr’ which can change the flag setting globally for all transistors when

simulation, some flags are added as instance parameters for user to change the flag for specified

transistors.

A flag in instance parameters has higher priority than a flag in model setup lib.

Flag in Instant parameters

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Usage of variation model

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Common Variation Simulation Options (1)

-Traditional total corner approach

Assumes all transistors in the chip are moving toward the same direction,

which is not realistic and may be too conservative.

In some circuits, this approach is too aggressive because it assumes no

mismatch between transistors.

-Global corner only (or with local Monte Carlo)

As fast as traditional total corner simulation, but is more realistic.

Not suitable for circuits with very small number of transistors and mismatch-

sensitive circuits (analog).

-Local Monte Carlo Only

For mismatch simulation.

-Full Monte Carlo simulation (Global Monte Carlo + Local Monte Carlo)

The same global variation applies to all devices, while each device gets

random local variation.

Too slow.

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Common Variation Simulation Options (2)

-Worst bit Icell Simulation approach

Defined to simulate the worst bit Icell current.

It is done by SSg corner simulation with a given “nicell” value. Users can

set value based on their interested memory size and CDF%.

Worst bit Icell simulation for dual port (DP) SRAM cell has to add extra

instance parameter “wbifactor = 1” at PortB PG devices if Icell is extracted

by PortA PG devices and vice versa. (See page-21 for sample netlist)

Worst bit Icell simulation is only available for Vdd ~ 0.8*Vdd and 125C ~ -40C.

Dual port SRAM schematic circuit

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13 Model Usage File

Parameter_1

Global variation

Local variation

FFG and SSG

Mismatch

Parameter_1

Total variation

Local variation

Global variation

Total variation corner

SS TT FF

Pre-defined libs prepared in usage file

Collect the must-used libs to prevent from misuse

5 simulation cases are included in the usage file.

Add one more lib, .lib pre_simu_sr for device level and pre_simu_sr_cell for cell level,

to address parameter setting (ex. ccoflag, cellflag).

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Netlist for usage of variation model

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-Case1: Conventional fixed corner model

It is identical to the existing TSMC fixed corner

Model Usage File: Case1

.option nomod ingold=2

+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4

.option MODSRH=0

*----------------------------------------------------------

.temp 25.000

.option brief=1

.lib ‘usage.l' TT_SRAM

.option brief=0

Vgs g 0 0.850

Vss s 0 0.000

Vbs b 0 0.000

Vds0 d0 0 0.850

mdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u

.op

.dc vgs 0 0.850 0.850

.print

+ id_dut0_=par('abs(i(Vds0))')

.end

Set the devices’ Fin number and Ldrawn

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-Case2: Global variation only corner + local variation Monte Carlo

Users can run mismatch model on top of each global variation only corner model.

Perform functional check on corner condition and understand design margin.

This methodology can help to check the contribution from local and global respectively.

Apply on mismatch/local variation sensitivity circuits: SRAM/Diff Amp/VCO/setup time/hold time

characterization, … etc.

Model Usage File: Case2

.option nomod ingold=2

+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4

.option MODSRH=0

*----------------------------------------------------------

.temp 25.000

.option brief=1

.lib ‘usage.l ' TTGlobalCorner_LocalMC_SRAM

.option brief=0

Vgs g 0 0.850

Vss s 0 0.000

Vbs b 0 0.000

Vds0 d0 0 0.850

xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u

.op

.dc vgs 0 0.850 0.850 sweep monte=1

.print

+ id_dut0_=par('abs(i(Vds0))')

.end

Global variation

Local variation

FFG and SSG

Parameter 1

Set the devices’ Fin number and Ldrawn

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-Case3: Local variation Monte Carlo

The same purpose as conventional mismatch model.

Model Usage File: Case3

.option nomod ingold=2

+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4

.option MODSRH=0

*----------------------------------------------------------

.temp 25.000

.option brief=1

.lib ‘usage.l' LocalMCOnly_SRAM

.option brief=0

Vgs g 0 0.850

Vss s 0 0.000

Vbs b 0 0.000

Vds0 d0 0 0.850

xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u

.op

.dc vgs 0 0.850 0.850 sweep monte=1

.print

+ id_dut0_=par('abs(i(Vds0))')

.end

Set the devices’ Fin number and Ldrawn

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-Case4: Global variation Monte Carlo + Local variation Monte Carlo

Global variation: all trans share one set of random numbers for each MC run.

Local variation: Each trans applies different set of random numbers for each MC run.

The result is a distribution function which can predict the silicon distribution accurately.

Can meet the rule listed on RHS completely.

Model Usage File: Case4

.option nomod ingold=2

+ newtol numdgt=7 relmos=1e-4 absmos=1e-8 relv=1e-4 relvdc=1e-4

.option MODSRH=0

*----------------------------------------------------------

.temp 25.000

.option brief=1

.lib ‘usage.l' GlobalMC_LocalMC_SRAM

.option brief=0

Vgs g 0 0.850

Vss s 0 0.000

Vbs b 0 0.000

Vds0 d0 0 0.850

xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u

.op

.dc vgs 0 0.850 0.850 sweep monte=1

.print

+ id_dut0_=par('abs(i(Vds0))')

.end

222

localglobaltotal





Parameter 1

global MC + local MC

Total variation

Local variation

Global variation

Total variation corner

Set the devices’ Fin number and Ldrawn

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.option gmindc=1.0E-18 gmin=1.0E-18

.prot

.lib ‘usage.l’ SSGlobalCorner_LocalMC_SRAM

.lib ‘usage.l' pre_simu_sr_cell

.unprot

.param nicell_hcsr=6

.global vdd vss

.param pwr=0.765

.temp -30

.param LPU=20N

.param LPD=20N

.param LPG=20N

XPpu1 bl_in g1 vdd vdd pchpu_hcsr_mac nfin=1 l=LPU

XPpu2 blb_in g2 vdd vdd pchpu_hcsr_mac nfin=1 l=LPU

XNpd1 bl_in g1 vss vss nchpd_hcsr_mac nfin=2 l=LPD

XNpd2 blb_in g2 vss vss nchpd_hcsr_mac nfin=2 l=LPD

XNpg1 bl wl bl_in vss nchpg_hcsr_mac nfin=2 l=LPG

XNpg2 blb wl blb_in vss nchpg_hcsr_mac nfin=2 l=LPG

vdd vdd 0 pwr

vss vss 0 0

vbl bl 0 pwr

vblb blb 0 pwr

vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)

v1 g2 bl_in 0

v2 blb_in g1 0

.nodeset v(bl_in)=0 v(blb_in)=pwr

.tran 0.05ns 0.8ns

.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'

.end

-Case5-1: Worst bit Icell simulation by global parameter setting:

Model Usage File: Case5-1

Worst bit Icell vs. nicell

0 6

nicell

Icell

Worst bit

SSg corner

Set the devices’ Fin number and Ldrawn

Set the devices’ Ldrawn

Set the global parameter “nicell”

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Worst bit Icell vs. nicell

0 6

nicell

Icell

Worst bit

.option gmindc=1.0E-18 gmin=1.0E-18

.prot

.lib ‘usage.l’ SSGlobalCorner_LocalMC_SRAM

.lib ‘usage.l' pre_simu_sr_cell

.unprot

.global vdd vss

.param pwr=0.765

.temp -30

.param LPU=20N

.param LPD=20N

.param LPG=20N

XPpu1 bl_in g1 vdd vdd pchpu_hcsr_mac nfin=1 l=LPU nicell=6

XPpu2 blb_in g2 vdd vdd pchpu_hcsr_mac nfin=1 l=LPU nicell=6

XNpd1 bl_in g1 vss vss nchpd_hcsr_mac nfin=2 l=LPD nicell=6

XNpd2 blb_in g2 vss vss nchpd_hcsr_mac nfin=2 l=LPD nicell=6

XNpg1 bl wl bl_in vss nchpg_hcsr_mac nfin=2 l=LPG nicell=6

XNpg2 blb wl blb_in vss nchpg_hcsr_mac nfin=2 l=LPG nicell=6

vdd vdd 0 pwr

vss vss 0 0

vbl bl 0 pwr

vblb blb 0 pwr

vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)

v1 g2 bl_in 0

v2 blb_in g1 0

.nodeset v(bl_in)=0 v(blb_in)=pwr

.tran 0.05ns 0.8ns

.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'

.end

-Case5-2: Worst bit Icell simulation by instance parameter setting:

Model Usage File: Case5-2

SSg corner

Set the instance parameter “nicell”

Set the devices’ Fin number and Ldrawn

Set the devices’ Ldrawn

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Worst bit Icell vs. nicell

0 6

nicell

Icell

Worst bit

Model Usage File: Case5-3

SSg corner

-Case5-3: Worst bit Icell simulation for dual port SRAM cell (DP only)

It has to add extra instance parameter “wbifactor=1” at PortB PG devices if Icell is

extracted by PortA PG devices and vice versa.

The usage of “nicell” is same as “case5-1 or case5-2”.

PortB

PortA

Extract Icell from PortA PG

.option gmindc=1.0E-18 gmin=1.0E-18

.prot

.lib ‘usage.l’ SSGlobalCorner_LocalMC_SRAM

.lib ‘usage.l' pre_simu_sr_cell

.unprot

.param nicell_dpfsr=6

.global vdd vss

.param pwr=0.765

.temp -30

xppu1 bl_in g1 vdd vdd pchpu_dpfsr_mac nfin=1 l=0.02u

xPpu2 blb_in g2 vdd vdd pchpu_dpfsr_mac nfin=1 l=0.02u

xNpd1 bl_in g1 vss vss nchpd_dpfsr_mac nfin=4 l=0.02u

xNpd2 blb_in g2 vss vss nchpd_dpfsr_mac nfin=4 l=0.02u

xNpg1 bl wl bl_in vss nchpg_dpfsr_mac nfin=2 l=0.02u

xNpg2 blb wl blb_in vss nchpg_dpfsr_mac nfin=2 l=0.02u

xNpg3 blx wlx bl_in vss nchpg_dpfsr_mac nfin=2 l=0.02u wbifactor=1

xNpg4 blbx wlx blb_in vss nchpg_dpfsr_mac nfin=2 l=0.02u wbifactor=1

vdd vdd 0 pwr

vss vss 0 0

vbl bl 0 pwr

vblb blb 0 pwr

vblx blx 0 pwr

vblbx blbx 0 pwr

vwl wl 0 pwl (0 0 0.2ns 0 0.3ns pwr)

vwlx wlx 0 pwl (0 0 0.2ns 0 0.3ns pwr)

v1 g2 bl_in 0

v2 blb_in g1 0

.nodeset v(bl_in)=0 v(blb_in)=pwr

.tran 0.05ns 0.8ns

.meas tran cell_iu find par('i(vbl)*(-1e6)') at '0.7ns'

.end

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* netlist for Idsat of DUT

*----------------------------------------------------------

.temp 25

.lib ‘usage.l' tt_sram

.param iboff_flag_hcsr=1

Vgs g 0 0.85

Vss s 0 0

Vbs b 0 0

Vds0 d0 0 0.85

xmdut0 d0 g s b nchpg_hcsr_mac nfin=2 l=0.02u

.op

.dc vgs 0 0.85 0.85

.print

+ id_dut0_=par('abs(i(Vds0))')

.end

-The “iboff_flag” is a globally changed parameter.

-The worst case Iboff scenario will be activated if user sets iboff_flag=1

-The “iboff_flag” is included in all total corners.

Iboff Worst Case

1.0E+00

1.0E+01

1.0E+00 1.0E+01 1.0E+02

Isoff(pA)

Iboff(pA)

iboff_flag_hcsr=1

iboff_flag_hcsr=0

TT FF SS

Iboff Worst Case Model Usage

簡報 Cln16ffcll Sr V1d0 2p1 Usage Guide

cln16ffcll_sr_v1d0_2p1_usage_guide

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