CM1213A Datasheet. Www.s Manuals.com. On

User Manual: Marking of electronic components, SMD Codes D3, D3*, D3***, D3-***, D3.9, D30, D31, D32, D33, D36, D38, D38*, D38NH02L, D39, D3A, D3B, D3C, D3L, D3Q. Datasheets 1SS187, CM1213A-04S7, EMD3, EMD30, EMD38, IMD3A, MMSZ5228, RB400D, RB420D, RB421D, RB425D, RB495D, RT9011-MFPQW, RT9011-SPPQWB, STD38NH02L-1, STD38NH02LT4, Si2323DS, TZT30AW, TZT33AW, TZT36AW, TZT39AW, TZT3V9AW, TZT43AW, TZT47AW, TZT51AW, UMD3N.

Open the PDF directly: View PDF .
Page Count: 13

Download
Open PDF In Browser	View PDF

CM1213A
1, 2 and 4-Channel
Low Capacitance
ESD Protection Arrays
Product Description

The CM1213A family of diode arrays has been designed to provide
ESD protection for electronic components or subsystems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current pulse to either
the positive (VP) or negative (VN) supply rail. A Zener diode is
embedded between VP and VN, offering two advantages. First, it
protects the VCC rail against ESD strikes, and second, it eliminates the
need for a bypass capacitor that would otherwise be needed for
absorbing positive ESD strikes to ground. The CM1213A will protect
against ESD pulses up to 8 kV per the IEC 61000−4−2 standard.
These devices are particularly well−suited for protecting systems
using high−speed ports such as USB 2.0, IEEE1394 (Firewire,
iLinkt), Serial ATA, DVI, HDMI and corresponding ports in
removable storage, digital camcorders, DVD−RW drives and other
applications where extremely low loading capacitance with ESD
protection are required in a small package footprint.

http://onsemi.com

SOT23−3
SO SUFFIX
CASE 318









MARKING DIAGRAM

XXXMG
G

XXXMG
G

Note: For 6 and 8−channel Devices, See the CM1213 Datasheet
Provides ESD Protection to IEC61000−4−2 Level 4
 8 kV Contact Discharge
Low Channel Input Capacitance of 0.85 pF Typical
Minimal Capacitance Change with Temperature and Voltage
Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for
Differential Dignals
Zener Diode Protects Supply Rail and Eliminates the Need for
External By−pass Capacitors
Each I/O Pin Can Withstand Over 1000 ESD Strikes*
These Devices are Pb−Free and are RoHS Compliant**

Applications

 USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals
 IEEE1394 Firewire Ports at 400 Mbps/800 Mbps
 DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,




MSOP−10
MR SUFFIX
CASE 846AE

SC70−6
S7 SUFFIX
CASE 419AD

Features

 One, Two, and Four Channels of ESD Protection

LCD Displays
Serial ATA Ports in Desktop PCs and Hard Disk Drives
PCI Express Ports
General Purpose High−Speed Data Line ESD Protection

SC−74
SO SUFFIX
CASE 318F

SOT143
SR SUFFIX
CASE 527AF

1

1

XXX
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION
Device

Package

Shipping†

CM1213A−01SO

SOT23−3
(Pb−Free)

3,000 /
Tape & Reel

CM1213A−02SR

SOT143−4
(Pb−Free)

3,000 /
Tape & Reel

CM1213A−02SO

SC−74
(Pb−Free)

3,000 /
Tape & Reel

CM1213A−04S7

SC70−6
(Pb−Free)
MSOP−10
(Pb−Free)

3,000 /
Tape & Reel
4,000 /
Tape & Reel

CM1213A−04MR

†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

**Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2012

January, 2012 − Rev. 8

1

Publication Order Number:
CM1213A/D

CM1213A
BLOCK DIAGRAM
VP
CH1

VN
CM1213A−01SO

VP

CH4

CH1

VP

CH3

CH2

VN
CM1213A−02SR
CM1213A−02SO

http://onsemi.com
2

CH1 VN CH2
CM1213A−04MR
CM1213A−04S7

CM1213A
PACKAGE/PINOUT DIAGRAMS

Table 1. PIN DESCRIPTIONS
1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO)

Top View

Pin

Name

Type

Description

1

CH1

I/O

2

VP

PWR

Positive Voltage Supply Rail

3

VN

GND

Negative Voltage Supply Rail

CH1 (1)

ESD Channel

231

VP (2)

Name

Type

1

VN

GND

2

CH1

I/O

ESD Channel

3

CH2

I/O

ESD Channel

4

VP

PWR

3

VN (3)

2

3−Lead SOT23−3

2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR)
Pin

1

Description
Negative Voltage Supply Rail
Top View
1

CH1 (2)

2

Positive Voltage Supply Rail

2−Channel, SC−74 Package (CM1213A−02SO)
Pin

Name

Type

1

NC

−

2

VN

GND

3

CH1

I/O

ESD Channel

4

CH2

I/O

ESD Channel

5

NC

−

6

VP

PWR

4

VP (4)

3

CH2 (3)

D232

VN (1)

4−Lead SOT143−4

Description
No Connect
Negative Voltage Supply Rail

Top View

Positive Voltage Supply Rail

NC (1)

1

VN (2)

2

CH1 (3)

3

Name

Type

1

CH1

I/O

2

VN

GND

3

CH2

I/O

ESD Channel

4

CH3

I/O

ESD Channel

5

VP

PWR

6

CH4

I/O

6

VP (6)

5

NC (5)

4

CH2 (4)

6−Lead SC−74

4−Channel, 6−Lead SC70−6 (CM1213A−04S7)
Pin

233

No Connect

Description
ESD Channel
Negative Voltage Supply Rail
Top View

ESD Channel

1

VN

2

CH2

3

D38

Positive Voltage Supply Rail

CH1

6

CH4

5

VP

4

CH3

6−Lead SC70−6
4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR)
Pin

Name

Type

1

CH1

I/O

2

NC

−

3

VP

PWR

CH2

I/O

NC

−

6

CH3

I/O

7

NC

−

8

VN

GND

9

CH4

I/O

10

NC

−

ESD Channel
No Connect

Top View

Positive Voltage Supply Rail

CH1
NC
VP
CH2
NC

ESD Channel
No Connect
ESD Channel

1
2
3
4
5

10
9
8
7
6

D238

4
5

Description

NC
CH4
VN
NC
CH3

10−Lead MSOP−10

No Connect
Negative Voltage Supply Rail
ESD Channel
No Connect

http://onsemi.com
3

CM1213A
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter

Rating

Units

6.0

V

Operating Temperature Range

–40 to +85

C

Storage Temperature Range

–65 to +150

C

(VN − 0.5) to (VP + 0.5)

V

Operating Supply Voltage (VP − VN)

DC Voltage at any channel input

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Package Power Rating
SOT23−3, SOT143−4, SC−74, and SC70−6 Packages
MSOP−10 Package

Rating

Units

–40 to +85

C
mW

225
400

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)
Symbol

Parameter

Conditions

VP

Operating Supply Voltage (VP−VN)

IP

Operating Supply Current

(VP−VN) = 3.3 V

VF

Diode Forward Voltage
Top Diode
Bottom Diode

IF = 8 mA; TA = 25C

Channel Leakage Current

Min

Max

Units

3.3

5.5

V

8.0

mA
V

0.80
0.80

0.95
0.95

TA = 25C; VP = 5 V, VN = 0 V

0.1

1.0

mA

Channel Input Capacitance

At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
(Note 2)

0.85

1.2

pF

DCIN

Channel Input Capacitance Matching

At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
(Note 2)

0.02

VESD

ESD Protection − Peak Discharge
Voltage at any channel input, in system
Contact discharge per
IEC 61000−4−2 standard

ILEAK
CIN

0.60
0.60

Typ

pF
kV

TA = 25C (Notes 2 and 3)

VCL

Channel Clamp Voltage
Positive Transients
Negative Transients

TA = 25C, IPP = 1A, tP = 8/20 mS
(Note 2)

RDYN

Dynamic Resistance
Positive Transients
Negative Transients

IPP = 1A, tP = 8/20 mS
Any I/O pin to Ground
(Note 2)

1. All parameters specified at TA = –40C to +85C unless otherwise noted.
2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
3. These measurements performed with no external capacitor on VP (VP floating).

http://onsemi.com
4

8
+10
–1.7
0.9
0.5

V

W

CM1213A
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves

Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)

Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)

http://onsemi.com
5

CM1213A
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)

Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)

Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)

http://onsemi.com
6

CM1213A
APPLICATION INFORMATION
Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power
supply is represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be
approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1213A has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance
L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information

See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.
L2
VP

ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
D1

0.22 mF

ONE
CHANNEL
D2 OF
CM1213

VN

POSITIVE SUPPLY RAIL

VCC

PATH OF ESD CURRENT PULSE IESO

LINE BEING
PROTECTED

L1
CHANNEL
INPUT
25 A
0A

ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
SYSTEM OR
CIRCUITRY

BEING
PROTECTED

VCL

GROUND RAIL

CHASSIS GROUND

Figure 5. Application of Positive ESD Pulse between Input Channel and Ground

http://onsemi.com
7

CM1213A
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AP

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.

D
SEE VIEW C
3

HE

E

DIM
A
A1
b
c
D
E
e
L
L1
HE


c
1

2

e

b

0.25


A
L

A1

L1
VIEW C

SOLDERING FOOTPRINT
0.95
0.037

0.95
0.037

2.0
0.079
0.9
0.035
SCALE 10:1

0.8
0.031

http://onsemi.com
8

mm Ǔ
ǒinches

MIN
0.89
0.01
0.37
0.09
2.80
1.20
1.78
0.10
0.35
2.10
0

MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.13
0.18
2.90
3.04
1.30
1.40
1.90
2.04
0.20
0.30
0.54
0.69
2.40
2.64
−−−
10 

MIN
0.035
0.001
0.015
0.003
0.110
0.047
0.070
0.004
0.014
0.083
0

INCHES
NOM
0.040
0.002
0.018
0.005
0.114
0.051
0.075
0.008
0.021
0.094
−−−

MAX
0.044
0.004
0.020
0.007
0.120
0.055
0.081
0.012
0.029
0.104
10

CM1213A
PACKAGE DIMENSIONS
SOT−143, 4 Lead
CASE 527AF−01
ISSUE A
SYMBOL

MIN

NOM

MAX

A

0.80

1.22

D

A1

0.05

0.15

e

A2

0.75

4

3

E1

1

E

2

e1

TOP VIEW

b

0.30

0.50

0.76

0.89

c

0.08

0.20

D

2.80

E

2.10

E1

1.20

2.90
1.30

e

1.92 BSC
0.20 BSC
0.40

0.50

L1

0.54 REF

L2

0.25

0°

A1

L1

SIDE VIEW

END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC TO-253.

http://onsemi.com
9

0.60

c

L

b2

1.40

8°

q

A

3.04
2.64

e1

θ

A2

1.07

b2

L

b

0.90

L2

CM1213A
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD−01
ISSUE A

D
e

e

E1 E

SYMBOL

MIN

A

0.80

MAX
1.10

A1

0.00

0.10

A2

0.80

1.00

b

0.15

0.30

c

0.10

0.18

D

1.80

2.00

2.20

E

1.80

2.10

2.40

E1

1.15

1.25

1.35

0.65 BSC

e
L

TOP VIEW

NOM

0.26

0.36

L1

0.42 REF

L2

0.15 BSC

0.46

θ

0º

8º

θ1

4º

10º

q1

A2 A
q

q1

b

L
L1

A1

SIDE VIEW

c
END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.

http://onsemi.com
10

L2

CM1213A
PACKAGE DIMENSIONS
SC−74
CASE 318F−05
ISSUE M
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. 318F−01, −02, −03, −04 OBSOLETE. NEW
STANDARD 318F−05.

D

6

HE

1

5

4

2

3

E

DIM
A
A1
b
c
D
E
e
L
HE


b
e

C

A

0.05 (0.002)



L

A1

MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0

MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.37
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10
−

SOLDERING FOOTPRINT*
2.4
0.094

0.95
0.037

1.9
0.074

0.95
0.037

0.7
0.028
1.0
0.039

SCALE 10:1

mm Ǔ
ǒinches

*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com
11

MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0

INCHES
NOM
0.039
0.002
0.015
0.007
0.118
0.059
0.037
0.016
0.108
−

MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10

CM1213A
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL

MIN

NOM

A

E

E1

MAX
1.10

A1

0.00

0.05

0.15

A2

0.75

0.85

0.95

b

0.17

0.27

c

0.13

0.23

D

2.90

3.00

3.10

E

4.75

4.90

5.05

E1

2.90

3.00

3.10

0.50 BSC

e
L

0.40

L1
L2

θ

0.60

0.80

0.95 REF
0.25 BSC

0º

8º
DETAIL A

TOP VIEW
D

A

END VIEW

A2

A1

c

e

b

q

SIDE VIEW

L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.

L
L1
DETAIL A

FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com

N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050

http://onsemi.com
12

ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative

CM1213A/D

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Creator Tool                    : BroadVision, Inc.
Modify Date                     : 2014:01:15 12:22:42+02:00
Create Date                     : 2012:01:04 03:16:53-07:00
Metadata Date                   : 2014:01:15 12:22:42+02:00
Format                          : application/pdf
Title                           : CM1213A - Datasheet. www.s-manuals.com.
Creator                         : 
Description                     : 
Subject                         : CM1213A - Datasheet. www.s-manuals.com.
Producer                        : Acrobat Distiller 9.0.0 (Windows)
Document ID                     : uuid:422fa5fe-3262-4141-b61b-873ec3e0bfc5
Instance ID                     : uuid:331d1941-5faf-44ec-9968-c29bb32b90ff
Startup Profile                 : Print
Page Count                      : 13
Keywords                        : CM1213A, -, Datasheet., www.s-manuals.com.

EXIF Metadata provided by EXIF.tools