COBRA5272 Module R1 0 Schematic 20020819

User Manual: sentec -

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5

4

3

2

1

COBRA5272 Module R1.0

D

D

CON0301B
CON0301A
IC 0204

Reset-LED

D[31:24]

BDM-Interface

Reset-Key

Driver

/RST
IC 0701

IC 0704

Reset

IC 0203

(optional)

D[23:16]

EEPROM
Driver

Test-LED
PortA (16Bit)

Data[31:0]

PortB (8Bit)

Addr[22:0]

IC 0202

D[15:8]

Driver

SPI

C

IC 0201
IC 0601

USB

IC 0602

Driver

0802

CPU clock

UART2 fullIC

UART2

UART2 non-driven

FLASH
2MByte

SDRAM 2

IC 0207

IC 0702
IC 0703
OSC 0401
66MHz
OCX

A[22:15]

Driver

A[14:7]

Driver

JTAG
SDRAM clock

IC 0205

IC 0206

USB clock

UART1

SDRAM 1

up to 32MB

CPU

0801

up to 32MB

IC 0401
Interrupt [6:1]
UART1 fullIC

C

D[7:0]

IC 0603

OSC 0402
48MHz
OCX

A[6:0]

/CS[6:1]
Driver

Logic
/BS[3:0]

IC 0208

/CS[6:1]

Driver

Ethernet

B

IC 0501
/BS[3:0]

Driver

D0501

D0502

D0503

D0504

B

IC 0209

ETH clock OSC 0501
25MHz
OCX

Ethernet

Interrupt
Status LED 1
Status LED 2
Status LED 3

A

A

(c) 2002, senTec Elektronik GmbH
Title

Size
B

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - Overview
Monday, August 19, 2002

Re v
1.0
Sheet
1

1

of

9

5

4

3

2

1

Overview
of the BDM interface and the bus widths
configuration
D

D

/BKPT

Default for (/WSEL): LOW

DSCLK

Default for (/BUSW0): LOW
Default for (/BUSW1): HIGH

/Reset
DSI

+3.3V

DSO

BOOT ROM
Configuration
BUSW1

C

BUSW0

CON 0101

BDM-Connector

JTAG only
from CPU

PST3
PST2
PST1
PST0
DDATA3
DDATA2
DDATA1
DDATA0

PST[0..3]

Data Bus Width

0

0

=

32 Bit

0

1

=

8 Bit

1

0

=

16 Bit Default at COBRA5272 Module

1

1

=

Reserved

D D a ta[0..3]

TCK
+3.3V

/DTEA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

CON 0101 = ML26

Start Configuration for ColdFire to select
FLASH Width.

C

sch.1.2

WSEL

/CS0 Bus Width

External Supply +3.3V
=

32 Bit Default at COBRA5272 Module

1

=

16 Bit

+3.3V
VCC

+3.3V

R 0104
1k

+3.3V

Bus Width for Boot
D 0101
LED red 3mm 2mA

B

R 0101
4.7K

3
2
1

R 0103
4.7K

R 0102
4.7K

Power
active

CON 0102

to
ColdFire

WSEL/MOSI0
BUSW0/SS0
BUSW1/SPIClk0

GND
+3.3V
GND

to the Single Board

0

B

sch.1.3

Select the FLASH Bus-Configuration at Start; BDM-Connector
to program the Board and JTAG for the CPU
sch.1.1

A

A

(c) 2002, senTec Elektronik GmbH
Title

Size
B
Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - BDM + bus width
Monday, August 19, 2002

Re v
1.0
Sheet
1

2

of

9

4

3

D[0..31]

A8
A7
A6
A5
A4
A3
A2
A1

+3.3V

19
1
Data_0
Data_1
Data_2
Data_3
Data_4
Data_5
Data_6
Data_7

9
8
7
6
5
4
3
2

A22
A21
A20
A19
A18
A17
A16
A15

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

A8
A7
A6
A5
A4
A3
A2
A1

I C 0 2 06

VCC
OE
DIR

I C 0 2 02
/EX_CS1

VCC

R/W

OE
DIR
D8
D9
D10
D11
D12
D13
D14
D15

from
Sheet 7
C

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

A8
A7
A6
A5
A4
A3
A2
A1

20

+3.3V
A[0..22]

19
1

/EX_CS2

Data_8
Data_9
Data_10
Data_11
Data_12
Data_13
Data_14
Data_15

9
8
7
6
5
4
3
2

B

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

A8
A7
A6
A5
A4
A3
A2
A1

20

+3.3V

19
1
Data_16
Data_17
Data_18
Data_19
Data_20
Data_21
Data_22
Data_23

9
8
7
6
5
4
3
2

A6
A5
A4
A3
A2
A1
A0
+3.3V

D[0..31]

D24
D25
D26
D27
D28
D29
D30
D31

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

A8
A7
A6
A5
A4
A3
A2
A1

VCC

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

I C 0 2 08

A8
A7
A6
A5
A4
A3
A2
A1

VCC
OE
DIR

/EX_CS3

Addr_22
Addr_21
Addr_20
Addr_19
Addr_18
Addr_17
Addr_16
Addr_15

20

+3.3V

19
1
9
8
7
6
5
4
3
2

20

D

Addr_14
Addr_13
Addr_12
Addr_11
Addr_10
Addr_9
Addr_8
Addr_7

/CS1
/CS2
/CS3
/CS4
/CS5
/CS6
+3.3V

+3.3V

C

+3.3V

19
1
9
8
7
6
5
4
3
2

Addr_6
Addr_5
Addr_4
Addr_3
Addr_2
Addr_1
Addr_0

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

A8
A7
A6
A5
A4
A3
A2
A1

20

+3.3V
Chip Select
lines to CON 2

19
1
9
8
7
6
5
4
3
2

/ChipSel_1
/ChipSel_2
/ChipSel_3
/ChipSel_4
/ChipSel_5
/ChipSel_6

M C 7 4 L C X 2 45DT

I C 0 2 09
Data_24
Data_25
Data_26
Data_27
Data_28
Data_29
Data_30
Data_31

9
8
7
6
5
4
3
2

Address lines
to CON 2

Addr_[0..22]

VCC
OE
DIR

/BS[0..3]

M C 7 4 L C X 245DT

/BS0
/BS1
/BS2
/BS3

R/W
/OE

+3.3V

+3.3V

11
12
13
14
15
16
17
18

B8
B7
B6
B5
B4
B3
B2
B1

A8
A7
A6
A5
A4
A3
A2
A1

B

/ChipSel_[1..6]

Byte Strobe lines
to CON 2

19
1

A

+3.3V

9
8
7
6
5
4
3
2

M C 7 4 L C X 2 45DT

I C 0 2 04

20

A8
A7
A6
A5
A4
A3
A2
A1

OE
DIR

/CS[1..6]

OE
DIR

B8
B7
B6
B5
B4
B3
B2
B1

to CON 2

M C 7 4 L C X 245DT

VCC

11
12
13
14
15
16
17
18

I C 0 2 07

Data lines to CON2

D16
D17
D18
D19
D20
D21
D22
D23

A14
A13
A12
A11
A10
A9
A8
A7

Data_[0..31]

I C 0 2 03

OE
DIR

+3.3V

19
1

M C 7 4 L C X 2 45DT

M C 7 4 L C X 245DT

VCC

20

M C 7 4 L C X 2 45DT

M C 7 4 L C X 245DT

External Chip
Select

1

Addr_[0..22]

D[0..31]

from
CPU

B8
B7
B6
B5
B4
B3
B2
B1

20

OE
DIR
A[0..22]
A[0..22]

OE
DIR
11
12
13
14
15
16
17
18

VCC

to decouple CON 0301B from CPU
VCC

D0
D1
D2
D3
D4
D5
D6
D7

I C 0 2 05

Buffers

I C 0 2 01

D

2

Addr_[0..22]

5

20

+3.3V

19
1
9
8
7
6
5
4
3
2

to CON 2
/ByteStrobe_0
/ByteStrobe_1
/ByteStrobe_2
/ByteStrobe_3
R/Wo
/OEo

/ByteStrobe_[0..3]

R/Wo
/OEo
A

M C 7 4 L C X 2 45DT

(c) 2002, senTec Elektronik GmbH
Title

Size
C 0201
100nF

C 0202
100nF

C 0203
100nF

C 0204
100nF

C 0205
100nF

C 0206
100nF

C 0207
100nF

C 0208
100nF

C 0209
100nF

C 0210
1nF

C 0211
1nF

C 0212
1nF

C 0213
1nF

C 0214
1nF

C 0215
1nF

C 0216
1nF

C 0217
1nF

B

C 0218
1nF

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - Buffers
Monday, August 19, 2002

Re v
1.0
Sheet
1

3

of

9

5

4

3

2

1

Connectors
with all needed lines to use the
COBRA5272 Module

SDClk
RTS1
R x D1
RTS2
R x D2
UART2
non-driven USRT2RTS(/Int5)
USRT2RxD
+3.3V
don't connect!
LED1
ETxD1+
ETxD1don't connect!
TMS = /BKPT
TDO = TDO
TDI = DSI
TRST = DSCLK
MTMOD to CPU

B

TCK
/BKPT
to Ethernet
DSCLK

PA1
PA3
PA5
PA7(SPI_/CS3)

connect!
connect!
connect!
connect!

don't connect!
Addr_21
Addr_19
Addr_17

+3.3V
PA9
PA11(SPI_/CS1)
PA13
PA15(/Int6)

+3.3V
Addr_15
Addr_13
Addr_11
Addr_9

MISO0
BUSW1/SPIClk0

Addr_7
Addr_5
Addr_3
Addr_1

USB+3.3V
/Int4
/Int2

R/Wo
PWMout1
PWMout3(TIn2)
PB5(/TA)
PB7(TOut1)

/ByteStrobe_0
/ByteStrobe_2
+3.3V
/ChipSel_1
/ChipSel_3
/ChipSel_5

66MHz
TxD1
CTS1

Data_0
Data_2
Data_4
Data_6

TxD2
CTS2
UART2
non-driven

USRT2TxD
USRT2CTS(SPI_/CS2)

+3.3V
don't connect!

+3.3V

Data_16
Data_18
Data_20
Data_22

LED2
ERxD1+
ERxD1don't connect!
DSI
TDO
MTMOD

Data_8
Data_10
Data_12
Data_14

to Ethernet

Data_24
Data_26
Data_28
Data_30

CON 50x2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

Address bus buffered from CPU

Port A
SPI

don't
don't
don't
don't

/RST1
/RSTo0

Byte
Select

TIn1
PWMout2(TOut2)
PB4
PB6

C

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

Chip Sel.
buffered

/Int3
/Int1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

CON 0302

Data bus buffered from CPU

USB+
+3.3V

USB

WSEL/MOSI0
BUSW0/SS0

Interrupt

PA8
PA10
PA12
PA14

PortB

+3.3V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

UART2 UART2 UART1

PA0
PA2
PA4
PA6

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

Ethernet

/RST0
/RSTo0

JTAG
Eth.+CPU

D

Reset

CON 0301

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

D

don't
don't
don't
don't

connect!
connect!
connect!
connect!

Addr_22
Addr_20
Addr_18
Addr_16
+3.3V
Addr_14
Addr_12
Addr_10
Addr_8
Addr_6
Addr_4
Addr_2
Addr_0
/OEo
C

/ByteStrobe_1
/ByteStrobe_3
+3.3V
/ChipSel_2
/ChipSel_4
/ChipSel_6
Data_1
Data_3
Data_5
Data_7
Data_9
Data_11
Data_13
Data_15
+3.3V
Data_17
Data_19
Data_21
Data_23
Data_25
Data_27
Data_29
Data_31

B

CON 50x2

*Note! Don't connect all unconnected Pin's !!!
Pin's are reserved for future connections!

A

A

(c) 2002, senTec Elektronik GmbH
Title

Size
B

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - CON 1+2
Monday, August 19, 2002

Re v
1.0
Sheet
1

4

of

9

4

3

2

DSO
DS I
/BKPT
TCK
DSClk
/DTEA

5

1

MTMOD
If controlled from CON 1, Jumper
JP0401 is not f itted !
+3.3V

DSO
DSI
/BKPT
TCK
DSClk
/DTEA

/CS0 = F LASH

/ B S [ 0 ..3]

/CS[0..7]
/CS7 = S DRAM

R 0402

2

OSC 0401

ERxD[0..3]
B

E RXD0
E RXD1
E RXD2
E RXD3

/BS0
/BS1
/BS2
/BS3

+3.3V

Heartbeat-LEDs are
optional. Pin ca n drive
4mA! Use on ly Low
Current L ED's.
+3.3V
PA14

R 0422
R 0423
R 0424

LED connected to Port PA14
because of 4mA current.

R 0403
33

/OE
R/ W

P13
P14
OE
WE

TP 0405

TP 0402

TP 0406

TP 0408

/Int1
/Int2
/Int3

2
C 0403
1nF

C 0404
1nF

C 0405
100nF

C 0406
100nF

C 0407
100nF

C 0408
100nF

VCC

GND

OUT

1

TP 0405

1

TP 0401

1

TP 0408

FSC1/FSR/DFSC1

DCL0/USRT2Clk

TP 0404

TP 0402

1

TC/BYPASS

TP 0406

1

DRQ

USB-

TP 0407

D A C K/HIZ

A

TP 0407

1

to CO N 1

4

USB

(c) 2002, senTec Elektronik GmbH

3
Title

OCE FHC J 48.000

Date:
4

TP 0403

1

DIN1

Size
C

5

1

D O UT1

to CO N 1
USB+

+3.3V

OSC 0402

NC

D C L1/GEN_DCL_OUT

to SD RAM

TP 0401

USB Clock

C 0402
1nF

Data Bus
TP 0404

+3.3V

1

B

TP 0403

R 0404
33

4.7K
4.7K
4.7K

to CO N 1

C 0401
1nF

4.7K
4.7K
4.7K

+3.3V

R 0405
1.5k

A

+3.3V

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22

PB5(/TA)
TP 0406
TP 0407
TP 0408

1k

R 0440
R 0443
R 0444

to CO N 1

to C ON1
R 0437

B3
E6

16Bit/32Bi t Bus

PA0
PA3
PA1
PA2
PA4
PA5
PA6

P W M out1
PWMout2(TOut2)
PWMout3(TIn2)

+3.3V

D 0401
LED yellow 3mm 2mA

MTMOD
TEST

PST0
PST1
PST2
PST3

B1
C2
C1
D3

+3.3V

Debug LED: This LED is for test trial.

Heartbeat

PST0
PST1
PST2
PST3

DDATA0
DDATA1
DDATA2
DDATA3

C3
A2
B2
A1
DDATA0
DDATA1
DDATA2
DDATA3

TDO/DSO
TDI/DSI
TMS/BKPT
TCK/PST_Clk
TRST/DSClk
DTEA

D5
A4
B4
C4
D4
A3

/ B S _P0
/ B S _P1
/ B S _P2
/ B S _P3

A9
C8
E12
E13

N4
P4
L5
M5

M14
N12
M12
F4
CPI_Ext_Clk
DRESETEN
Reset
RSTO

F5
F6
F9
F10
G5
G10
H5
H10
J5
J6
J9
J10
K7
K8
N5
P5
K6

ECOL
EMDC
EMDIO
ECRS

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22

A[0..22]

ETXClk
ETXEN
ETXERR
ETXD0
PB10/ETXD1
PB9/ETXD2
PB8/ETXD3
ERXClk
PB14/ERXER
ERXDV
ERXD0
PB13/ERXD1
PB12/ERXD2
PB11/ERXD3
ECOL
PB15/EMDC
EMDIO
ECRS

Address Bus

ERXClk
ERXERR
ERXDV

Ethernet

ETXD0
ETXD1
ETXD2
ETXD3

D10
B12
A12
A13
A14
B13
B14
C12
C13
C14
D12
C11
B11
A11
C10
D9
D8
D7
C6
D6
B5
C5
E9

C

PB7/TOUT1
TIN1

A[0..22]

ETxD[0..3]

L7
P8
M10
N6
L8
M8
N8
N7
L9
M7
P7
M9
N9
P9
P6
P10
N10
L10

A10_PRECHG
SDBA1
SDBA0
RAS0
CAS0
SDWE
SDClk
SDClkE

ETXClk
ETXEN
ETXERR

PB6

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31

D14
H12
J14
A10
C9
B9
E14
D13

G4
M6
L6

TIn1

IC 0401
MCF 5272

L12
L13
L14
K11
K12
K13
K14
J11
J12
J13
H11
G11
F11
E11
D11
E10
A5
B6
A6
C7
B7
A7
A8
B8
F12
F13
F14
G12
G13
G14
H14
H13

A10_PRECHG
SDBA1
SDBA0
/RAS0
/CAS0
/SDWE
SDClk
SDClkE

PB4
PB6
PB7(TOut1)

ColdFire CPU

PB0/USRT1TxD
PB1/USRT1RxD
PB2/USRT1CTS
PB3/USRT1RTS
PB4/USRT1CLK

PB5/TA
TC/BYPASS
DACK/HIZ
DRQ

H4
H1
H2
H3
G3

USRT1TxD
U S RT1RxD
USRT1CTS
USRT1RTS

F3
M13
N14
N13

/Int4

RS 2 32

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14

0402
0403
0404
0405

E7
E8
F7
F8
G6
G7
G8
G9
H6
H7
H8
H9
J7
J8

TP
TP
TP
TP

USB_VDD
USB_VSS

4.7K

USBExtClk
PA0/USB_TP
PA3/USB_TN
PA1/USB_RP
PA2/USB_RN
PA4/USB_SUSP
PA5/USB_TXEN
PA6/USBRxD

R 0425

DCL0/USRT2Clk
DIN0/USRT2RxD
USRT2CTS/SPI_/CS2
USRT2RTS/Int5
DOUT0/USRT2TxD
FSC1/FSR/DFSC1
DCL1/GEN_DCL_OUT
DOUT1
DIN1
DIN3/Int4

J1
D2
E4
D1
E5
E3
E2
E1

+3.3V

/CS0 for
SPI-EEPROM

Int1/USB_Wake
Int2
Int3

TP 0401
U S RT2RxD
USRT2CTS(SPI_/CS2)
USRT2RTS(/Int5)
USRT2TxD

D[0..31]

D0/PC0
D1/PC1
D2/PC2
D3/PC3
D4/PC4
D5/PC5
D6/PC6
D7/PC7
D8/PC8
D9/PC9
D10/PC10
D11/PC11
D12/PC12
D13/PC13
D14/PC14
D15/PC15
D16/D0
D17/D1
D18/D2
D19/D3
D20/D4
D21/D5
D22/D6
D23/D7
D24/D8
D25/D9
D26/D10
D27/D11
D28/D12
D29/D13
D30/D14
D31/D15

D[0..31]

J4
K1
K2
K3
K4
L4
M1
N1
N2
P2

PA7/SPI_CS3/DOUT3
PA8/FSC0/FSR0
PA9/DGNT0
PA10/DREQ0
PA11/SPI_CS1
PA12/DFSC2
PA13/DFSC3
PA14/DREQ1
PA15/DGNT1/Int6

PWMOut1
PWMOut2/Tout2
PWMOut3/TIN2

P1
J2
J3
K5
L1
L2
L3
M2
M3

M4
P3
N3

4.7K

PA7(SPI_/CS3)
PA8
PA9
PA10
PA11(SPI_/CS1)
PA12
PA13
PA14
PA15(/Int6)

RS 2 32

VDD_0
VDD_1
VDD_2
VDD_3
VCC_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13

R 0442

BS0/DQM0
BS1/DQM1
BS2/DQM2
BS3/DQM3

+3.3V

0 Ohm
Bridge for OCX output of 66MHz

I/O-Port

MCF5272 Tes t Mode
Default= +3.3V

4.7K
4.7K
4.7K
4.7K
4.7K
4.7K

JTAG to BDM & E thernet

QSPI_DOUT/WSEL
QSPI_DIN
QSPIClk/BUSW1
SPI_CS0/BUSW0

+3.3V

R 04xx

USBLineH
USBLineL

OCE FHC J 66.000

66MHz

C

/CS4
/CS5
/CS6
/CS7

/CS0
/CS1
/CS2
/CS3

/RST1

0431
0432
0433
0434
0435
0436

/RSTo0

3

F1
F2

OUT

G1
G2

GND

/Reset

4

/CS_P0
/CS_P1
/CS_P2
/CS_P3
/CS_P4
/CS_P5
/CS_P6
/CS_P7

VCC

K9
K10
P11
N11
M11
L11
P12
B10

2

NC

BOOT
Config
& S PI

CS0
CS1
CS2
CS3
CS4
CS5
CS6
SDRAMCS/CS7

1

JTAG Mode

PST[0..3]

+3.3V

R 0426
4.7K

1

D

R
R
R
R
R
R

DData[0..3]

R 0401
4.7K

4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K

B U S W 0 /SS0

CPU Clock

0427
0428
0429
0430
0414
0415
0416
0417
0418
0419
0420
0421
0441

BUSW1/SPIClk0

SDRAM Reset
Enable

WSEL/MOSI0
MISO0

R
R
R
R
R
R
R
R
R
R
R
R
R

D

Motorola ColdFire 5272

JP 0401

4.7K

Default: BD M-Mode
+3.3V

CPU

JTAG or BDM Mode

3

2

COBRA5272 module
Document Number
COBRA5272 - Coldfire CPU

Rev
1.0

Monday, August 19, 2002

S h eet
1

5

of

9

5

4

3

for 10 or 100MBit speed
RP 0501 ARC 241 47Ohm

to
ColdFire

1
3
5
7

ETXD0

1
3
5
7

2
4
6
8

RP 0503 ARC 241 22Ohm

2
4
6
8

1
3
5
7

1
3
5
7

2
4
6
8

2
4
6
8

ECRS
ERXERR
ERXClk
ERXDV

2
4
6
8

+3.3V

7

D 0501

1

XO

TP 0502

TP 0503

DSO

1
1

TDO

TP 0504

TP 0505

TP 0501

1

TCK

TP 0506

+3.3V

TP 0504

TP 0503
DSCLK

1

TP 0506

TP 0505
/BKPT

1

/RSTo0

C0501
1nF

TP 0502

R0526
22.1K 1%

C0502

Ethernet
IC 0501
LXT972ALC

L 0501
Ferrite Bead

Hardware Configuration Settings for Jumper
JP 0502, JP 0503, JP 0504:

3
22

1
D 0502
Duo-LED rd/gr 3mm

2

JP 0502
CFG1

Desired Mode
Auto Neg

D 0503
Duo-LED rd/gr 3mm

1

Duplex

CFG1

CFG2

CFG3

10

Half
Full

1-2
1-2

1-2
1-2

1-2
2-3

100

Half
Full

1-2
1-2

2-3
2-3

1-2
2-3

100 only

Half
Full

2-3
2-3

1-2
1-2

1-2
2-3

Half
only

2-3

2-3

1-2

Half or
Full

2-3

2-3

2-3

Disabled

22

2

JP 0503
CFG2
Enabled

D 0504
+3.3V
Duo-LED rd/gr 3mm

1

Pause
Disabled

C

+3.3V

3x180Ohm
R 0518
R 0519
R 0520

LED CFG

Speed (Mbps)

1

TP 0501

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

C

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RXD0
RXD1
RXD2
RXD3
N/C
MDC
MDIO
GND
VCCIO
PWRDWN
LED/CFG1
LED/CFG2
LED/CFG3
Test1
Test0
Pause

3

TP 0501

RefClk/XI
XO
MDDIS
/Reset
TXSLEW0
TXSLEW1
GND
VCCIO
N/C
N/C
GND
Addr0
Addr1
Addr2
Addr3
Addr4

+3.3V

22

2

JP 0504
CFG3
10/100

1

OCE FHC K 25.000

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

8

EMDC
EMDIO

LED1
LED2
TP 0506

3

TP 0505

OUT

TP 0504

GND

TP 0503

2

TP 0502

R 0509
220

LED red 3mm 2mA

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

+3.3V

/MDINT
CRS
COL
GND
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
TX_ER
RX_ER
RX_CLK
VCCD
GND
RX_DV

VCC

4

RBias
GND
TPFOP
TPFON
VCCA
VCCA
TPFIP
TPFIN
GND
SD/TP
TDI
TDO
TMS
TCK
/TRST
Sleep

NC

/Int2

+3.3V

OSC 0501

E R xD[0..3]

RP 0504 ARC 241 22Ohm
ERXD0
1
2
1 2
ERXD1
3
4
3 4
ERXD2
5
6
5 6
ERXD3
7
8

25 MHz Oscillator

13

2
4
6
8

1

ECOL

1
3
5
7

3

1
3
5
7

13

ETXD1
ETXD2
ETXD3

ETxD[0..3]

1

D

RP 0502 ARC 241 47Ohm

13

D

1

Ethernet

ACHTUNG!
RP 0501, RP 0502 eigentlich 50Ohm!

ETXERR
ETXClk
ETXEN

2

Jumper on COBRA5272 Module:

JP 0502 JP 0503 JP 0504

+3.3V

+3.3V

R 0527

C 0506
1nF

C 0507
1nF

C 0508
1nF

C 0509
1nF

C 0510
100nF

C 0511
100nF

C 0512
100nF

C 0505

47 1%

10nF

R 0528

C 0513
100nF

47 1%

100K

R 0525

DSO

JTAG for
Ethernet Chip
DSCLK
TCK
/BKPT
TDO
DSO

B

to CON 1

ETxD1+
ETxD1ERxD1ERxD1+

TDO

Ethernet Data lines to magnetics

B

/BKPT

DSCLK

MURATA

TCK

100nF
+3.3V

C 0503

330pF

ATTENTION!
C 0503 and C 0504 should be 270pF!
R 0527 and C 0528 should be 49.9Ohm!

C 0504

330pF

A

A

(c) 2002, senTec Elektronik GmbH
Title

Size
B

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - Ethernet
Monday, August 19, 2002

Re v
1.0
Sheet
1

6

of

9

3

40

NC

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
GND1
GND2
GND3
GND4
GND5
GND6
GND7

C

1
3
9
14
27
43
49

A[1..20]
A20
+3.3V

+3.3V

1

DQML
DQMH
/WE
/CAS
/RAS
/CS
BA0
BA1
CKE
Clk

D[16..31]

2

15
39
16
17
18
19
20
21
37
38

16 Bit
Bus

11
10
9
8
7
6
5
4
42
41
40
39
38
37
36
35
34
3
2
43

JP 0601

A10_PRECHG
/BS2
/BS3
/SDWE
/CAS0
/RAS0
/CS7
SDBA0
SDBA1
SDClkE
S D Clk

FLASH
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

of the module (FLASH and SDRAM)

16MBit Flash Boot

A13
A14

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31

4.7K

D

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

1

Memory
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53

R 0601

A[2..14]

23
24
25
26
29
30
31
32
33
34
22
35
36

IC 0601

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

MT48LC4M16A2TG-75

SDRAM

High
16Bit

2

6
12
28
41
46
52
54

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A1

MBM29PC160BD-75

4

IC 0603

5

1
12
14
33

+3.3V

13
32

up to 2x32MB SDRAM

16Bit
Bus
D

D[16..31]

2MB FLASH
NC

R/W
/CS0
/OE

D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31

15
17
19
21
24
26
28
30
16
18
20
22
25
27
29
31

44

/WE
/CE
/OE
/Byte
C

VSS1
VSS2

VCC

23

+3.3V

A[2..14]

A13
A14

B

A10_PRECHG
/BS0
/BS1
/SDWE
/CAS0
/RAS0
/CS7
SDBA0
SDBA1
SDClkE
SDClk

23
24
25
26
29
30
31
32
33
34
22
35
36
15
39
16
17
18
19
20
21
37
38
40

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
DQML
DQMH
/WE
/CAS
/RAS
/CS
BA0
BA1
CKE
Clk
NC

IC 0602

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

Low
16Bit

MT48LC4M16A2TG-75

SDRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
GND1
GND2
GND3
GND4
GND5
GND6
GND7

2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
3
9
14
27
43
49

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

Jumper JP 0601
Jumper
fitted
not fitted

Action
FLASH access at FFE0.0000
FLASH access at FFF0.0000

D[0..15]

Other SRAMs:
+3.3V
Part

+3.3V
+3.3V

6
12
28
41
46
52
54

Memory per Chip

Manuf.

MT48LC4M16A2TG-75
MT48LC8M16A2TG-75
MT48LC16M16A2TG-75

8MB
16MB
32MB

MICRON
MICRON
MICRON

W986416
W981216
W9825+16

8MB
16MB
32MB

Winbond
Winbond
Winbond

K4S641632
K4S281632
K4S561632

8MB
16MB
32MB

Samsung
Samsung
Samsung

B

C 0601
100nF

C 0602
100nF

C 0604
100nF

C 0605
100nF

C 0606
100nF

C 0607
100nF

C 0608
100nF

C 0609
1nF

C 0610
1nF

Other FLASHs
C 0621
100nF

C 0622
100nF

C 0623
100nF

C 0624
100nF

C 0625
100nF

C 0626
100nF

C 0627
100nF

C 0628
100nF

C 0629
1nF

C 0630
1nF
Part

Memory per Chip

Manuf.

+3.3V
AM29PL160CB
MBM29PL160C

2MB
2MB

AMD
Fujitsu

A

A

C 0611
100nF

C 0612
100nF

C 0613
100nF

C 0614
100nF

C 0615
100nF

C 0616
100nF

C 0617
100nF

C 0618
100nF

C 0619
1nF

C 0620
1nF

(c) 2002, senTec Elektronik GmbH
Title

Size
B

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - Flash + SDRAM (up to 64MB)
Monday, August 19, 2002

Sheet
1

Re v
1.0
7

of

9

5

4

3

2

1

Circuits
for Reset, Chip Select and the SPI-EEPROM

D

D

+3.3V

14

from ColdFire

Reset Circuit
For Power-Up Reset and
Under-Voltage detection

1
2
13

/CS1
/CS2
/CS3

R0705
4.7K

IC 0702A

&

7

R 0701
270

74LCX11

3
4
5

GND1

RESET
GND2

3

/Reset

SOT 23-5

/Reset

/RST0

C

+3.3V
to ColdFire
and BDM

2

1
2
13

&

7

/RST0
from CON1
external /Reset

/EX_CS1

+3.3V

14

MR

LED red 3mm 2mA

14

1

6
74LCX11

IC 0703A

3
4
5

12

&

74LCX11

7

D 0701

VCC
4

IC 0702B

&

7

5

IC 0701 MAX811

detects /CS signal and
selects the buffers
+3.3V

12

+3.3V

SW 0701
Microtaster 6x6mm (Reset)

Chip Select Circuit

14

+3.3V

+3.3V

IC 0703B

6

C

/EX_CS2

74LCX11

*NOTE: Reset-IC is compatible with
MAX811/812 supervisor
+3.3V

sch.7.1

14

EX_CS = CS1 + CS2 + CS3 + CS4 + CS5 + CS6
+3.3V

WSEL/MOSI0
MISO0
BUSW1/SPIClk0
BUSW0/SS0

IC 0703C

8

/EX_CS3

&

8
74LCX11

7

74LCX11

JP 0701
/Ex_CS

+3.3V

SPI-Interface to
ColdFire

B

/CS4
/CS5
/CS6

Use -W Version or -S
Version for +3.3V.

2

ATTENTION!
CURRENTLY NOT EQUIPPED!

9
10
11

&

IC 0702C

1

14

(optional)

7

SPI-EEPROM

9
10
11

IC 0704

5
2
6
1

SDI
SDO
SClk
CS

sch.7.3

25LC640ISN

HOLD
WP
+3.3V
GND

7
3
8
4

B

Jumper 0701
Jumper
Action
fitted
/EX_CSx are always LOW
not fitted /EX_CSx are LOW, if one of /CS[1..6] is LOW

SS0 from CPU is used
to select Chip

+3.3V
These chips are pin-compatible. Manufactured by ST Microelectronics.
Same chips manufactured by ATMEL (AT25xxx), and XICOR (X25xxx).
M95P010
M95P020
M95P040
M95P080
M95P160
M95P320
M95P640

=
=
=
=
=
=
=

1kBit
2kBit
4kBit
8kBit
16kBit
32kBit
64kBit

C 0701
1nF

C 0702
1nF

C 0703
100nF

C 0704
100nF

C 0705
100nF

C 0706
1nF

C 0707
100nF

C 0708
1nF

sch.7.2
A

A

(c) 2002, senTec Elektronik GmbH
Title

Size
B

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - Reset, Chip Select and SPI EEPROM
Monday, August 19, 2002

Sheet
1

8

Re v
1.0
of

9

5

4

3

2

1

RS232
(serial interfaces)

D

D

IC 0801

12
9

USRT1RxD
USRT2RxD

11
10

USRT1TxD
USRT2TxD
C 0801

100nF

C 0802

100nF

1
3
4
5
2
6

+3.3V
C 0803
+

C

100nF

R1OUT
R2OUT
T1IN
T2IN

R1IN
R2IN
T1OUT
T2OUT

13
8

R x D1
R x D2

14
7

TxD1
TxD2

C1+
C1C2+
C2V+
V-

CON 0801
GND
TxD1
R x D1
GND

UART 1

ICL3232CVE

C 0805
1µF (Tantal-Elko)
C 0804 100nF

1
2
3
4

for external terminal

D r iven UART1

C

sch.8.1

IC 0802

12
9

USRT1CTS
USRT2CTS(SPI_/CS2)

11
10

USRT1RTS
USRT2RTS(/Int5)
C 0806

100nF

C 0807

100nF

B

VCC

+3.3V

1
3
4
5
2
6

+3.3V
C 0808

R1OUT
R2OUT
T1IN
T2IN

R1IN
R2IN
T1OUT
T2OUT

13
8
14
7

CTS1
CTS2
RTS1
RTS2

C1+
C1C2+
C2V+
V-

B

UART 2

100nF
ICL3232CVE

+

C 0810
1µF (Tantal-Elko)
C 0809 100nF

sch.8.2

This connection is used to communicate with CPU via RS232
(for terminal applications).

A

A

(c) 2002, senTec Elektronik GmbH
Title

Size
B

Date:
5

4

3

2

COBRA5272 module
Document Number
COBRA5272 - RS232
Monday, August 19, 2002

Re v
1.0
Sheet
1

9

of

9



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.2
Linearized                      : No
Page Count                      : 9
Creator                         : COBRA5272
Create Date                     : 2002:08:19 12:29:08
Title                           : COBRA5272-Module.PDF
Author                          : mihu
Producer                        : Acrobat PDFWriter 4.05 für Windows

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