Compal LA 1341 Schematics. Www.s Manuals.com. R2a Schematics

User Manual: Motherboard Compal LA-1341 ADQ00 Lindbergh - Schematics. Free.

Open the PDF directly: View PDF .
Page Count: 46

Download
Open PDF In Browser	View PDF

A

B

C

D

E

Block Diagram

Compal confidential
File Name : LA-1341
Mobile Northwood

Thermal Sensor

CPU Bypass
& CPUVID

Fan Control

page 3

page 5

System Bus

page 3

HD#(0..63)

400MHz

Memory
BUS(DDR)

SIS 650

CRT Conn

315 Graphics embedded
BGA

VB BUS

DDR-SO-DIMM X2

BANK 0, 1, 2, 3 page 10,11

page 14

LCD Conn

1

page 12,13

page 3,4,5
HA#( 3..31)

Clock Generator

MAX1617

uFCBGA/uFCPGA CPU

1

2.5V DDR 200/266 MHz

page6,7,8,9

page 15

SIS302LV
( LVDS/TVOUT )

TV-OUT Conn

page 15

page 14

IDSEL:AD16
(PIRQC#,GNT#0,REQ#0)

MUTIOL

2

IEEE 1394
VT6306

Mini PCI
port

page 22

2

RJ11 Conn
page 26

page 26

IDSEL:AD31
(PIRQB#,GNT#1,REQ#1)

PCI BUS
IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)

IDSEL:AD17
(PIRQC#,GNT#3,REQ#3)

SIS 961

AC-LINK
CONN

3.3V ATA100
page 16,17,18,19

ENE CB1420

page 21

page 31
AC-LINK

3.3V 24.576MHz

CardBus Controller

LAN
RTL 8100BL

page 25

page 23

RJ45

3

USB conn
3.3V 48MHz

3.3V 33MHz

LPC BUS

Slot 0

Slot 1

page 26

page 24

HDD IDE
Connector

3.3V 33MHz

page 24

3

page 22

SMsC
LPC47N227

Power On/Off
Reset & RTC
page 32

DC/DC Interface
Suspend
page 33

LPC to X-BUS &
Super I/O

14M_5V

page 29

Power Circuit
DC/DC
page
33,34,35,36,37,38,39

PARALLEL

page 22

SERIAL

page 31

page 27

Touch Pad

page 28

EC I/O Buffer
4

page 27

EC NS87591

CDROM IDE
Connector

page 28

page 30

BIOS

FDD

Int.KBD

page 28

4

PS/2 conn

page 30

page 32

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

2

of

46

A

HD STBP#[0..3]

U1A

DBI#[0..3]

56
56

2

R515
R525

2

56

Thermal Sensor
MAX1617

62_0603

C2

ITP_CLK#

R4

1K

2200PF

ITP_CLK

R5

1K

R6

150

R7

75

TMS

R9

39

56

C464

2

SMI#

R13

56

C465

2

CPUSLP# R14

56

C466

2

R15

56

C467

2

CPU PW RGD R16

51

2

1K

2

AC3
V6

I ERR#

TRIP#

R20

62_0603

CPURST#

PWRGOOD

AB23

VSS75

AF26

C469

R21

56

C470

2

IGNN E#

R22

56

C471

2

INTR

R23

56

C472

2

CPUPW RGD 6

NMI

R24

56

C473

BREQ0#

R25

200

2

0.1UF
1
0.1UF
1
0.1UF
1
0.1UF
1

J26
K25
K26
L25

CPURST# R27

D58

Q2
2SA1036K

2

51

+5VFAN1

+3VS

@1SS355
JP1

D3

C3

1N4148

1000PF

1
2
3

R26
10K

53398-0310

2
DEP0
DEP1
DEP2
DEP3

CPU_COMP0
CPU_COMP1

1

D1
1SS355

1

L24
P1

+5VS

Q1
FMMT619
2

D2
1N4148
CB1
2.2UF_16V_0805

FA N1

COMP0
COMP1

1

Fan1 Control circuit

0.1UF
1
0.1UF
1

R19
3.48K_1%_0603

A20M#

CPURST# 6

10K

1

62_0603 C468

R18

CPUPW RGD

R10

+5VS

2

R17

I ERR#

ITP_DBR#

0.1UF
1
0.1UF
1
0.1UF
1
0.1UF
1

1

FER R#

AB25

MAX1617

+12VS

ITP_CLK#
ITP_CLK

DBRESET

EC_SMD2 29

1

R12

AD26
AC26

CPUCLK0 12
CPUCLK0# 12

EC_SMC2 29

R11

ITP_CLK1
ITP_CLK0

RESET

1K
1

16
15
14
13
12
11
10
9

NC
STBY
SMBCLK
NC
SMBDATA
ALERT
ADD0
NC

1K

STPCLK#

INIT#

AE25

R8
2

NC
VCC
DXP
DXN
NC
ADD1
GND
GND

2

+5VS

H_THERMDA
H _THERMDC

1

TDI
TDO

AF22
AF23

DBRESET

10K

2

R3

1
2
3
4
5
6
7
8

+CPU_CORE

CP U_CLK
C PU_CLK#

R1

0.1UF

1

HDSTBP#0
HDSTBN#0
HDSTBP#1
HDSTBN#1
HDSTBP#2
HDSTBN#2
HDSTBP#3
HDSTBN#3

PROCHOT#

BCLK0
BCLK1

IERR
MCERR

C1

U2

BSEL0
BSEL1
TCK
TDI
TDO
TMS
TRST
VID0
VID1
VID2
VID3
VID4

27

C480

TRST#

R29

CPU_COMP0

R30

51.1_1%_0603

CPU_COMP1

R32

51.1_1%_0603

+3VS

HTEST0
HTEST1
HTEST2
HTEST3
HTEST4
HTEST5
HTEST6
HTEST7
HTEST8
HTEST9
HTEST10
HTEST11
HTEST12

AD6
AD5

BSEL0
BSEL1

D4
C1
D5
F7
E6

TCK
TDI
TDO
TMS
TRST#

AE5
AE4
AE3
AE2
AE1

CPU_ VID0
CPU_ VID1
CPU_ VID2
CPU_ VID3
CPU_ VID4

H_THERMTRIP#
H_PROCHOT# 4

680

1000PF

R36
@1K
BSEL0
BSEL1

+CPU_CORE

DBRESET

R538

R37
@1K

150

R40
@1K

R41
@1K

+5VS

C483

. 1UF
1
2

. 1UF

5

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

H_THERMDA
H _THERMDC
TRIP#
PROCHOT#

C484

VCC

29
R34

0

2

3
VEE

TCK
TDI
TDO
TMS
TRST#

R61
10K
39
39
39
39
39

13K_1%_0603

U42
LMV321_SOT23-5

1
2
R562
7.32K_1%_0603
RP5
8P4R_10K_0804

CPU_ VID0
CPU_ VID1
CPU_ VID2
CPU_ VID3
CPU_ VID4

Compal Electronics, Inc.
Title

SCHEMATIC, M/B LA-1341
Size

ZIF_SOCKET478_478P

FA N1

4
1
R561

PM_CPUPERF# 17
H_DPSLP# 17
+3VS

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

1

EN_FAN1

2

B3
C4
A2
C3

1

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12

R28

2

THERMDA
THERMDC
THERMTRIP
PROCHOT

FANSPEED1 29
TCK

1

1

F21
E22
J23
K22
P23
R22
W23
W22

R514

1

6
6
6

+5VS
W = 1 5mil

3

DBI0
DBI1
DBI2
DBI3

RS0#
RS1#
RS2#

56

1

DB I#0 E21
DB I#1 G25
DB I#2 P26
DB I#3 V21

F1
G5
F4

R513

+CPU_CORE

HD[0..63]
H D0
H D1
H D2
H D3
H D4
H D5
H D6
H D7
H D8
H D9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63

6

6
6
6
6
6

56

2

DSTBP0
DSTBN0
DSTBP1
DSTBN1
DSTBP2
DSTBN2
DSTBP3
DSTBN3

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

R512

1

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

J1
K5
J4
J3
H3

BREQ0#

+CPU_CORE
HTEST0
HTEST1
HTEST2
HTEST3
HTEST4
HTEST5
HTEST6
HTEST7
HTEST8
HTEST9
HTEST10
HTEST12
HTEST11

2

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

6
6
6
6
6
6
6
6
6
6
6
6
6

HDSTBN#[0..3] 6

2

RS0
RS1
RS2

ADS#
HASTB0#
HASTB1#
BNR#
D B SY#
DEFER#
D R D Y#
HIT#
HITM#
H T RDY#
BPRI#
BREQ0#
HLOCK#

HDST BN#[0..3]

1

REQ0
REQ1
REQ2
REQ3
REQ4

17
17
17
17
17
17
17
17
17

1

G1
L5
R5
G2
H5
E2
H2
F3
E3
J6
D2
H6
G4

A20M#
FERR#
INIT#
INTR
N MI
IGNNE#
SMI#
CPUSLP#
STPCLK#

2

ADS
ADSTB0
ADSTB1
BNR
DBSY
DEFER
DRDY
HIT
HITM
TRDY
BPRI
BR0
LOCK

A20M#
FER R#
INIT#
INTR
NMI
IGNN E#
SMI#
CPUSLP#
STPCLK#

2

C6
B6
W5
D1
E5
B2
B5
AB26
Y4

1

A20M
FERR
INIT
LINT0
LINT1
IGNNE
SMI
SLP
STPCLK

2

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

3 1

K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1

1
2
3
4

HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HA30
HA31

8
7
6
5

6

HA[3..31]

2

6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDSTBP#[0..3] 6

Document Number

R ev
2A

401210
D ate:
A

¬P 期五, 十一月 15, 2002

Sheet

3

of

46

A

+CPU_CORE

B

C

D

BPM4
BPM5
BPM1
BPM0

TP1

+CPU_CORE Island >
600ml

1

E

VCORE_SENSE

+CPU_CORE

AF3
AF4

8P4R-56_0804

AA21
AA6
F20
F6

C5
220PF

C6
220PF

C7
220PF

C8
220PF

(D)

AD20
AD22

VCORE_PLL
VSS_PLL

+1.2VPP

VCCIOPLL

AE23

VIO_PLL

A4

VSS_SENSE

2

+1.2VPP

L2

4.7UH_80mA
2

1

CB6
33UF_D2_16V

+

CB7
10UF_10V_1206

VSS_SENSE

1
3

TP2
+CPU_CORE

R43
49.9_1%_0603
+CPU_CORE
GTLVREF2_CPU
CB8

2/3VCORE

R46
100_1%_0603

R47
49.9_1%_0603

1UF_10V_0603
GTLVREF1_CPU
2/3VCORE
CB9

R51
100_1%_0603

1UF_10V_0603

2

+5VALW

2
R56

2

C7
C5
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
C25

CB5
10UF_10V_1206

1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

CB4
33UF_D2_16V

+

2

VSS_SENSE

4.7UH_80mA
2

1
1

VCCA
VSSA

1K
29

R57
470

PROCHOT#

1

GTLREF
GTLREF
GTLREF
GTLREF

Q8

2
3904

ZIF_SOCKET478_478P

1

VCCVIDPRG
VCCVID

AB2
AC1
V5
AC6
AB5
AC4
Y6
AA5
AB4
AA3

1
2
3
4
4

L1

Q9

R59

2
3

AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
F8
G21
G24
G3
G6
C22
C9
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4

1

8
7
6
5

GTLVREF1_CPU
GTLVREF2_CPU

1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

CB3
1UF_10V_0603

3

2

D10
D8
D6
D3
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
E1
D12
D14
D16
D18
D20
D24
D21
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14

VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE

RP108
BPM4
BPM5
BPM1
BPM0

1

3

B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10
E12
E14
E16
E18
E20
E8
F11
F13
F15
F17
F19
F9

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

4

RSP
AP0
AP1
BPM0
BPM1
BPM2
BPM3
BPM4
BPM5
BINIT

U1B

VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_SENSE

AF9
AF7
AF5
AF21
AF2
AF19
AF17
AF15
AF13
AF11
AE8
AE6
AE20
AE18
AE16
AE14
A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AE12
AE10
AD9
AD7
A5

+1.2VPP

1

2

1

H_PROCHOT# 3

470
3904

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
Size
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
¬P 期五, 十一月 15, 2002

Sheet
E

4

of

46

A

B

C

D

E

Layout note :

Layout note :

Place close to CPU power and
gr ound pin as possible
(<1inch)

Place close t o CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Please place these cap in the socket cavity area

Used ESR 25m ohm cap total ESR=2.5m ohm

+CPU_CORE

+CPU_CORE
1

1

1

CE3
+
220UF_D2_4V_25m

CE5
+
220UF_D2_4V_25m

CE4
220UF_D2_4V_25m

2

2

CE2
+
220UF_D2_4V_25m
2

2

CB14
10UF_6.3V_1206

CE1
+
220UF_D2_4V_25m
2

1
CB13
10UF_6.3V_1206

2

1

1
CB12
10UF_6.3V_1206

2

2

CB11
10UF_6.3V_1206

2

1

1
2

CB10
10UF_6.3V_1206

+

1

1

1

1

+CPU_CORE

CE6
+
220UF_D2_4V_25m

1
CE7
+
220UF_D2_4V_25m

CE10
220UF_D2_4V_25m

2

2

CE9
+
220UF_D2_4V_25m

1

1

1
CE8
+
220UF_D2_4V_25m

2

CB19
10UF_6.3V_1206

2

CB18
10UF_6.3V_1206

2

CB17
10UF_6.3V_1206

2

2

2

CB16
10UF_6.3V_1206

2

+
CB15
10UF_6.3V_1206

2

1

1

1

1

1

1

+CPU_CORE

Please place these cap on the socket north side
+CPU_CORE

0.22UF

C17
0.22UF

1

C16

2

0.22UF

1

C15

2

0.22UF

1

C14

2

0.22UF

1

1

C13

2

0.22UF

1

C12

2

0.22UF

1

C11

2

0.22UF

1

C10

2

0.22UF

1

C9

2

CB24
10UF_6.3V_1206

2

1
CB23
10UF_6.3V_1206

2

CB22
10UF_6.3V_1206

2

1

1
CB21
10UF_6.3V_1206

2

2

2

CB20
10UF_6.3V_1206

2

1

1

1

+CPU_CORE

C18
0.22UF

2

2

CB27
10UF_6.3V_1206

1
CB28
10UF_6.3V_1206

2

1

1
CB26
10UF_6.3V_1206

2

2

2

CB25
10UF_6.3V_1206

2

1

1

+CPU_CORE

CB29
10UF_6.3V_1206

1

1
CB31
10UF_6.3V_1206

CB32
10UF_6.3V_1206

2

2

2

CB30
10UF_6.3V_1206

2

1

1

+CPU_CORE

CB33
10UF_6.3V_1206

Please place these cap on the socket south side

2

CB36
10UF_6.3V_1206

1
CB37
10UF_6.3V_1206

2

1

1
CB35
10UF_6.3V_1206

2

2

CB34
10UF_6.3V_1206

2

3

1

1

+CPU_CORE

3

CB38
10UF_6.3V_1206

CB41
10UF_6.3V_1206

1
CB42
10UF_6.3V_1206

2

1

1
CB40
10UF_6.3V_1206

2

2

2

CB39
10UF_6.3V_1206

2

1

1

+CPU_CORE

CB43
10UF_6.3V_1206

1

1
CB45
10UF_6.3V_1206

CB46
10UF_6.3V_1206

2

2

2

CB44
10UF_6.3V_1206

2

1

1

+CPU_CORE

CB47
10UF_6.3V_1206

4

4

EMI Clip PAD for CPU
PAD1

PAD2
1

PAD3
1

1

Compal Electronics, Inc.
Title

PAD-2.5X3

PAD-2.5X3

PAD-2.5X3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

5

of

46

A

B

C

D

E

BCLK

RS#2
RS#1
RS#0

ADS#
HITM#
HIT#
D R D Y#
D BSY#
BNR#

ADS#
HITM#
H IT#
D R D Y#
D BSY#
BN R#

V28
T28
U28
W26
V24
V27

ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#

HREQ4#
HREQ3#
HREQ2#
HREQ1#
HREQ0#

HREQ4#
HREQ3#
HREQ2#
HREQ1#
HREQ0#

W28
W29
W24
W25
Y27

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

HASTB1#
HASTB0#

HASTB1#
HASTB0#
HA31
HA30
HA29
HA28
HA27
HA26
HA25
HA24
HA23
HA22
HA21
HA20
HA19
HA18
HA17
HA16
HA15
HA14
HA13
HA12
HA11
HA10
H A9
H A8
H A7
H A6
H A5
H A4
H A3

+CPU_CORE
R81
H NCOMP
Rds-on(n) = 10 ohm
HNCVERF = 1/3 VCCP

R83
HPCOMP
Rds-on(p) = 56 ohm
HPCVERF = 2/3 VCCP

+CPU_CORE
2

R84
150_1%_0603

C26
0.01UF

B CLK

V BD7
V BD6
V BD5
V BD4
V BD3
V BD2
V BD1
V BD0
V AD6
V AD5
V AD4
V AD7
V AD8
V AD9
VAD10
VAD11
ADE
A VSYNC
A H S YNC
VBD11
VBD10
V BD8
V BD9
V AD1
V AD0
V AD2
V AD3
BDE
VBCTL0
VBCTL1
B H S YNC
B VSYNC

D6
A3
D7
C5
A5
C6
D8
C7

A7
F9
B7
M6
M5
M4
L3
L6
L4
K6
L2
K3
J3
K4
J2
J6
J4
J1
H6
F4
F1
G6
E3
F5
E2
E4
E1
D3
D4
C2
F7
C3
E6
B2
D5

B20
B19
A19

AH27
AJ27

U21
T21
P21
N21
J17
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

F6
F3
H4
K5

VBCAD/AREQ#
AGNT#
AFRAME#
AIRDY#
ATRDY#
ADEVSEL#
ASERR#
ASTOP#

C9
A6
G2
G1
G3
G4
H5
H1

APAR

H3

VBHCLK/RBF#
VGPIO2/WBF#
VGPIO3/PIPE#

E8
F8
D9

NC
NC
NC

AD24
AA24

HASTB#1
HASTB#0

AF26
AE25
AH28
AD26
AG29
AE26
AF28
AC24
AG28
AE29
AD28
AC25
AD27
AE28
AF27
AB24
AB26
AC28
AC26
AC29
AA26
AB28
AB27
AA25
AA29
AA28
Y26
Y24
Y28

HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3

B GCLKNR65
BGCLK R66

@10
10

VBGCLK#
VBGCLK

A GCLKNR67
AGCLK R68

@10
10

VAGCLK#
VAGCLK

B V SYNC R69
B H S Y NC R70

10
10

VBVSYNC
V B HSYNC

A H S Y NC R71
A V SYNC R72

10
10

V A HSYNC
VAVSYNC

VBCLK

650-1

VAGCLK# 15
VAGCLK 15

A DE R74
B DE R75

0
@0
@0

VBD[0..11] 15
VBCTL[0..1] 15

VADE
VBDE

VADE
VBDE

15
15

VBGCLK
B HCLK
BC AD

VAGCLK#
VAGCLK

D10
B3
C4

C21

C22

C23

@10PF @10PF

K1
L1

AGCLK
A GCLKN

VBGCLK/AD_STB1
VBGCLKN/AD_STB#1

C1
D1

BGCLK
B GCLKN

HOST

VAD[0..11] 15

VBGCLK#
R76
R77
R78

VAGCLK/AD_STB0
VAGCLKN/AD_STB#0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10
10

4

V A H SYNC 15
VAVSYNC 15

V BCTL[0..1]

B5
A4

AGPCLK

VBVSYNC 15
V B H SYNC 15

VBD[0..11]

0

15

VBGCLK# 15
VBGCLK 15

VAD[0..11]
R73

SB_STB
SB_STB#

C24

@10PF @10PF
3

B10

AGPCLK0

AGPCLK0

R79

AGPCLK0 12

C25

@10

AGPRCOMP

AGPRCOMP

M1

A1XAVDD
A1XAVSS

B9
A9

A4XAVDD
A4XAVSS

B8
A8

AGPVREF
AGPVSSREF

M3
M2

AV REFGC

HDSTBN#3
HDSTBN#2
HDSTBN#1
HDSTBN#0

F20
F23
K24
P24

HDSTBN#3
HDSTBN#2
HDSTBN#1
HDSTBN#0

HDSTBP#3
HDSTBP#2
HDSTBP#1
HDSTBP#0

F21
F24
L24
N25

HDSTBP#3
HDSTBP#2
HDSTBP#1
HDSTBP#0

@10PF
+3VS
R80
A4XAVDD
A4XAVSS

AGPRCOMP
60_1%_0603
AV REFGC

R82

8.2K

HDSTBN#[0..3] 3

2

HDSTBP#[0..3] 3

B21
F19
A21
E19
D22
D20
B22
C22
B23
A23
D21
F22
D24
D23
C24
B24
E25
E23
D25
A25
C26
B26
B27
D26
B28
E26
F28
G25
F27
F26
G24
H24
G29
J26
G26
J25
H26
G28
H28
J24
K28
J29
K27
J28
M24
L26
K26
L25
L28
M26
P26
L29
N24
N26
M27
N28
P27
N29
R24
R28
M28
P28
R26
R29

HNCVREF

R85
75_1%_0603

VBCLK

DBI#3
DBI#2
DBI#1
DBI#0

3
3

LVDS

AC/BE#3
AC/BE#2
AC/BE#1
AC/BE#0

E21
A27
H27
R25

3

U5A

SBA7
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
VBCLK/SBA0

T24
T26
U29

@10PF

ST0
ST1
ST2
VBD7/AAD0
VBD6/AAD1
VBD5/AAD2
VBD4/AAD3
VBD3/AAD4
VBD2/AAD5
CBD1/AAD6
CBD0/AAD7
VAD6/AAD8
VAD5/AAD9
VAD4/AAD10
VAD7/AAD11
VAD8/AAD12
VAD9/AAD13
VAD10/AAD14
VAD11/AAD15
VADE/AAD16
VAVSYNC/AAD17
VAHSYNC/AAD18
VBD11/AAD19
VBD10/AAD20
VBD8/AAD21
VBD9/AAD22
VAD1/AAD23
VAD0/AAD24
VAD2/AAD25
VAD3/AAD26
VBDE/AAD27
VBCTL0AAD28
VBCTL1/AAD29
VBHSYNC/AAD30
VBVSYNCAAD31

RS2#
RS1#
RS0#

RS2#
RS1#
RS0#

HPCOMP
HNCOMP
HNCOMPVREF

HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#

C4XAVSS
C4XAVDD

AH25
AJ25
3
3
3
3
3

CPUCLK
CPUCLK#

U24
U26
V26
C20
D19
T27
U25

HLOCK#
DEFER#
H T RDY#
CPURST#
CPUPW RGD
BPRI#
BREQ0#

3
3
3
3
3
3

AJ26
AH26

HLOCK#
DE FER#
H T RDY#
CPURST#
CPU PW RGD
BP RI#
BREQ0#

3
3
3

113_1%_0603

10

C20

HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#24
HD#23
HD#22
HD#21
HD#20
HD#19
HD#18
HD#17
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#10
HD#9
HD#8
HD#7
HD#6
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0

3
3
3
3
3
3
3

CP UCLK1
C PUCLK1#

C1XAVSS
C1XAVDD

CPUCLK1
CPUCLK1#

H NCVREF
HN COMP
HPCOMP

12
12

C4XAVDD
C4XAVSS

4

HVREF

HA[3..31]

3 HA[3..31]

20_1%_0603

R64

HD[0..6 3]

3 HD[0..63]

SIS650

C27
0.01UF

HNCVR EF_G
D BI#0
D BI#1
D BI#2
D BI#3

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63

DBI#[0..3] 3

+CPU_CORE
+3VS
R86
75_1%_0603
1

+3VS

L3
C28
0.01UF

A4XAVDD

1

C4XAVDD

2

1

HB-1M2012-121JT
HVR EF

R89
150_1%_0603

C29
0.01UF

+3VS

L4

C31

C32

CB48

0.1UF

0.01UF

4.7UF_10V_0805

2
1

HB-1M2012-121JT
C33
0.1UF

C34

CB49

0.01UF

4.7UF_10V_0805

C30
0.1UF
A4XAVSS

C4XAVSS

BC AD
B HCLK

HV REF_G

R87

R88

4.7K

4.7K

Compal Electronics, Inc.
VBCAD
VBHCLK

15
15

Title

SCHEMATIC, M/B LA-1341
Size

place this capacitor
under 650 solder side

A

Document Number

R ev
2A

401210
D ate:
B

C

D

¬P 期五, 十一月 15, 2002

Sheet
E

6

of

46

A

B

C

D

NOTE:This page is for pure DDR SDRAM PCB
design
MA1
MD[0..63]

RDQM[0..7] 10,11

RDQS[0..7]

RDQS[0..7] 10,11

MAA[0..14]

8
7
6
5

MA0
MA3
MA2
MA5
MA4
MA7
MA6
MA9
MA8
MA14
MA13
MA12
MA11

MD[0..63] 10,11

RDQM[0..7]

MAA[0..14] 10,11

4

RP* PLACE CLOSE TO DIMM

8
7
6
5
RP9

1 RP6
2 8P4R_10_0804
3
4
8
1 RP7
7
2
6
3
5
4
8P4R_10_0804
1
2 RP8
8P4R_10_0804
3
4
4
1
4P2R_10 3
2

3

MD34
MD39
RP24
8P4R_10_0804
MD38
R DQS4
MD35
1
MD45
RP25 2
MD44
3
MD40 8P4R_10_0804 4
MD42
MD46
RP26
8P4R_10_0804
MD41
R DQS5
MD48
1
MD47
RP27 2
MD43
3
MD52 8P4R_10_0804 4
MD49
MD54
RP28
8P4R_10_0804
R DQS6
MD53
MD55
1
MD60
RP29
2
MD50
3
MD51 8P4R_10_0804 4
MD56
MD61
RP30
8P4R_10_0804
MD57
R DQS7
MD58
RP31
1
MD59
2
MD62 8P4R_10_0804 3
MD63
4

2

1

1
2
3
4

MMD4
MMD5
MMD0
MMD1
MMD6
DQS0
MMD2
MMD3
MMD12
MMD8
MMD7
MMD9
MMD13
MMD14
MMD10
DQS1
MMD11
MMD20
MMD16
MMD15
MMD21
MMD17
DQS2
MMD18
MMD22
MMD19
MMD23
MMD24
MMD28
MMD29
MMD25
DQS3
MMD30
MMD27
MMD31
MMD26
MMD32
MMD37
MMD36
MMD33

8
7
6
5
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4

8
7
6
5

8
7
6
5
8
7
6
5

1
2
3
4

8
7
6
5
8
7
6
5

1
2
3
4
8
7
6
5

8
7
6
5
8
7
6
5

1
2
3
4

8
7
6
5
8
7
6
5

1
2
3
4

MMD0
MMD1
MMD2
MMD3
MMD4
MMD5
MMD6
MMD7
DQM0
DQS0
MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15
DQM1
DQS1
MMD16
MMD17
MMD18
MMD19
MMD20
MMD21
MMD22
MMD23
DQM2
DQS2
MMD24
MMD25
MMD26
MMD27
MMD28
MMD29
MMD30
MMD31
DQM3
DQS3
MMD32
MMD33
MMD34
MMD35
MMD36
MMD37
MMD38
MMD39
DQM4
DQS4
MMD40
MMD41
MMD42
MMD43
MMD44
MMD45
MMD46
MMD47
DQM5
DQS5
MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55
DQM6
DQS6
MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63
DQM7
DQS7

MMD34
MMD39
MMD38
DQS4
MMD35
MMD45
MMD44
MMD40
MMD42
MMD46
MMD41
DQS5
MMD48
MMD47
MMD43
MMD52
MMD49
MMD54
DQS6
MMD53
MMD55
MMD60
MMD50
MMD51
MMD56
MMD61
MMD57
DQS7
MMD58
MMD59
MMD62
MMD63

8
7
6
5

1
2
3
4

+2.5V

R90
150_1%_0603

C35
0.01UF

R91

DDRVR EFA

SDREF

4

10,35

C36
R92
@0_0603
150_1%_0603

0.01UF

8
7
6
5

1
2
3
4

MAA1
MAA0
MAA3
MAA2
MAA5
MAA4
MAA7
MAA6
MAA9
MAA8
MAA14
MAA13
MAA12
MAA11

U5B
MA10

MD4
RP10
8P4R_10_0804
MD5
MD0
MD1
MD6
1
R DQS0
RP11 2
MD2
3
MD3 8P4R_10_0804 4
MD12
MD8
RP12
8P4R_10_0804
MD7
MD9
MD13
1
MD14
RP13 2
MD10
3
R DQS18P4R_10_0804 4
MD11
MD20
RP14
8P4R_10_0804
MD16
MD15
MD21
1
MD17
2
R DQS2
3
MD18
RP15 4
MD22 8P4R_10_0804
MD19
RP16
8P4R_10_0804
MD23
MD24
MD28
1
MD29
RP18
2
MD25
3
R DQS3 8P4R_10_0804 4
MD30
MD27
RP20
8P4R_10_0804
MD31
MD26
MD32
1
MD37
RP23
2
MD36
3
MD33 8P4R_10_0804 4

E

8
7
6
5
8
7
6
5

RDQM0
RDQM1

R101
R102

10
10

DQM0
DQM1

RDQM2
RDQM3

R103
R104

10
10

DQM2
DQM3

RDQM4
RDQM5

R105
R106

10
10

DQM4
DQM5

RDQM6
RDQM7

R107
R108

10
10

DQM6
DQM7

AJ23
AG22
AH21
AJ21
AD23
AE23
AF22
AF21
AD22
AH22
AD21
AG20
AE19
AF19
AE21
AD20
AD19
AH19
AF20
AH20
AF18
AG18
AH17
AD16
AD18
AD17
AF17
AJ17
AE17
AH18
AD14
AG14
AJ13
AE13
AJ15
AF14
AD13
AF13
AH13
AH14
AD10
AH10
AE9
AD8
AG10
AF10
AH9
AF9
AD9
AJ9
AH5
AG4
AE5
AH3
AG6
AF6
AF5
AF4
AH4
AJ3
AE4
AD6
AE2
AC5
AG2
AG1
AF3
AC6
AD4
AF2
AB6
AD3
AA6
AB3
AC4
AE1
AD2
AC1
AB4
AC2

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
DQS0/CSB#0
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1/CSB#1
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2/CSB#2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3/CSB#3
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4/CSB#4
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5/CSB#5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB#6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7/CSB#7

R93

10

MAA10
DDRV REFA_G

RP* place close to DIMM1
+2.5V

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14

AH11
AF12
AH12
AG12
AD12
AH15
AF15
AH16
AE15
AD15
AF11
AG8
AJ11
AG16
AF16

SRAS#
SCAS#
SWE#

AH8
AJ7
AH7

CS#0
CS#1
CS#2
CS#3
CS#4
CS#5

AE7
AF7
AH6
AJ5
AF8
AD7

CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
S3AUXSW#

AB2
AA4
AB1
Y6
AA5
Y5
Y4

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14

R94
150_1%_0603

C37
0.01UF

R95

DDRVR EFB

SDREF

10,35

R96
@0_0603
150_1%_0603

C38
0.01UF

3

DDRV REFB_G

RASCASWE-

R516
R517
R97

10
10
10

SRAS#
SCAS#
SWE#

SRAS#
SCAS#
SWE#

10,11
10,11
10,11
+2.5V

650-2

CS-0
CS-1
CS-2
CS-3

4P2R_10 1
RP19 2

R CS0#
R CS1#
R CS2#
R CS3#

4
3
1
RP21 2

4P2R_10

4
3

RCS0#
RCS1#
RCS2#
RCS3#

10,11
10,11
10,11
10,11

RP22
CKE0
CKE1
CKE2
CKE3

SDCLK

AA3

+3VS
L5
SDA VDD

S3AUXSW#
R98

@10

R99

AD11

SDRCLKI

AE11

SDAVDD

Y1

SDA VDD

SDAVSS

Y2

SDAVSS

DDRAVDD

AA1

DDRAVDD

DDRAVSS

AA2

FW DSDCLKO

C42

2
HB-1M2012-121JT
CB50

S3AUXSW# 29,32

SDCLK
10

1

C39
0.1UF

C41 @10PF

S DCLK

FWDSDCLKO

8
7
6
5
8P4R_470_0804

CKE[0..3] 10
CKE0
CKE1
CKE2
CKE3

1
2
3
4

C40
0.01UF

4.7UF_10V_0805

SDAVSS

12

2

FW DSDCLKO 13

@10PF
+3VS
L6
DDRAVDD

1

2
HB-1M2012-121JT
CB51

C43
0.1UF

DD RAVSS

C44
0.01UF

4.7UF_10V_0805

DD RAVSS

DDRVREFA
DDRVREFB

AJ19
AH2

DRAM_SEL

W3

DDRVR EFA
DDRVR EFB
R100

+3VALW
4.7K

1

SIS650

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Size

A

B

C

D

Document Number

R ev
2A

401210
D ate:

¬P 期五, 十一月 15, 2002

Sheet
E

7

of

46

A

B

C

D

E

ZS TB[0..1]

16 ZSTB[0..1]

Z STB[0..1]#

16 ZSTB[0..1]#

4

4

+1.8VS
C45

R109

10PF
R111

U 5C
SIS650

Z CLK0

12 ZCLK0

0.1UF
150_1%_0603
ZVR EF
C48

R113

10

C46

C47

0.1UF
150_1%_0603

ZUREQ
ZDREQ

U6
U1

ZUREQ
ZDREQ

16
16

ZSTB0
ZSTB0#

ZSTB0
ZSTB0#

T3
T1

ZSTB0
ZSTB#0

16
16

ZSTB1
ZSTB1#

ZSTB1
ZSTB1#

P1
P3

ZSTB1
ZSTB#1

ZA D0
ZA D1
ZA D2
ZA D3
ZA D4
ZA D5
ZA D6
ZA D7
ZA D8
ZA D9
Z AD10
Z AD11
Z AD12
Z AD13
Z AD14
Z AD15

T4
R3
T5
T6
R2
R6
R1
R4
P4
N3
P5
P6
N1
N6
N2
N4

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15

ZVR EF

U3

ZVREF

VD DZCMP
Z CMP_N
ZCMP_P
VSSZCMP

V5
U4
U2
V6

VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP

W1
W2

Z1XAVDD
Z1XAVSS

V2
V1

Z4XAVDD
Z4XAVSS

Y3
W4
W6

PCIRST#
PWROK
AUXOK

D11
E10

TRAP1
TRAP0

ZAD[0..15]

+3VS
L7
CB52
4.7UF_10V_0805

Z4XAVDD
C52

C53

0.1UF

0.01UF
Z4XAVSS

VOSCI

ZUREQ
ZDREQ

3

1
2
HB-1M2012-121JT

ZCLK

16
16

ZV REF_G

16 ZAD[0..15]

V3

Z4XAVDD
Z4XAVSS
P CIRSTP W RGD
AUXOK

16,20,29 PCIRST17,32 PW RGD
17,29 RSM_RST

TRAP1
TRAP0

C15

10PF

R110

10

R EFCLK0
14.318M INPUT REFERENCE

REFCLK0 12,15

+3VS
for 650 only

ROUT
GOUT
BOUT

VGA

650-3

R ED
GR EEN
BLUE

A12
B13
A13

HSYNC
VSYNC

F13 R115
E13 R117

33
33

H S YN C
V S YN C

VGPIO0
VGPIO1

D13 R119
D12 R120

100
100

DDCCLK
DD CDATA

B11

PIRQA#

CSYNC
RSYNC
LSYNC

E12
A11
F12

C S YN C
R S YN C
L S Y NC

VCOMP
VRSET
VVBWN

E14
D14
F14

VCOMP
VRSET
VVBWN

DACAVDD1
DACAVSS1

B12
C12

DAC AVDD1
DACAVSS1

DACAVDD2
DACAVSS2

C13
C14

DAC AVDD2
DACAVSS2

DCLKAVDD
DCLKAVSS

B15
A15

DCL KAVDD
DCLKAVSS

ECLKAVDD
ECLKAVSS

B14
A14

E CLKAVDD
ECLKAVSS

ENTEST
DLLEN#

F10
E11

TESTMODE0
TESTMODE1
TESTMODE2

C11
F11
A10

INT#A

MuTIOL

R ED
GREEN
BLUE

14
14
14

H S YN C
V S YN C

14
14

R S YN C

R112

4.7K

C S YN C

R532

@4.7K

L S Y NC

R533

@4.7K

DDCCLK 14
DDCDATA 14
PIRQA#

15,16,23

3

ENTEST

R123

P W RGD

C49

@0.1UF

4.7K

AUXOK

C51

0.1UF

ENTEST
DLLEN#

2

2

C56

+3VS
L8
1
2
HB-1M2012-121JT
C57

0.01UF

0.1UF

DCL KAVDD

CB53
4.7UF_10V_0805VVBWN

C55

0.1UF

VCOMP

C58

0.1UF

DCLKAVSS
+1.8VS
DAC AVDD1

L9

1

+1.8VS

VD DZCMP

2

L10
DAC AVDD2

HB-1M2012-121JT
C59

CB54

0.1UF

10UF_10V_1206

C60
0.01UF

R125

56.2_1%_0603

Z CMP_N

R126

56.2_1%_0603

ZCMP_P

1
C61

+3VS
VSSZCMP
E CLKAVDD
C63
0.01UF

0.1UF

1UF_10V_0603

10UF_10V_1206

DACAVSS2

L11
1
2
HB-1M2012-121JT
C62

DACAVSS1
CB57
4.7UF_10V_0805 VRSET

0.1UF

CB55

2
HB-1M2012-121JT
CB56

R127

ECLKAVSS
130_1%_0603

1

1

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Size

A

B

C

D

Document Number

R ev
2A

401210
D ate:

¬P 期五, 十一月 15, 2002

Sheet
E

8

of

46

5

4

3

2

1

NOTE:This page is for pure DDR SDRAM PCB design
+3VS
+CPU_CORE

+1.8VS

+3VALW

+3VS

CB58

+3VS
B

+1.8VS

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM

V10
V11
W18
Y9
Y10
Y12
Y14
Y16
Y18
Y19
AA8
AA9
AA10
AA13
AA14
AA15
AA16
AA17
AB8
AB9
AB13
AB17

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM

E5
E7
E9
G5
J5
L5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H8
H9
J8
J9
J10
J13
K9
K11
K13
L10
N9
N10

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

N5
R5
U5
W5
P9
P10
R9
R10
T9
T10
T11

VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ

W10
Y11
Y13
Y15
Y17
PVDDM
PVDDM
PVDDM
PVDDM
PVDDM

J14
J15
K15
K10
K12
K14
M10

P11

L12
L14
L15
L16
L18
M11
M19
N11
P19
R11
T19
U11
V19
W11
W13
W15
W17

650-4
Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M12
M13
M14
M15
M16
M17
M18
N12
N13
N14
N15
N16
N17
N18
P12
P13
P14
P15
P16
P17
P18
R12
R13
R14
R15
R16
R17
R18
T12
T13
T14
T15
T16
T17
T18
U12
U13
U14
U15
U16
U17
U18
V12
V13
V14
V15
V16
V17
V18

L17
L19
N19
R19
U19
W19

PVDDP
PVDDP
PVDDP
PVDDP
PVDDP
PVDDP

A

CB59

CB60

10UF_10V_1206
CB62

10UF_10V_1206
CB63

10UF_10V_1206
CB61

AUX1.8
AUX3.3

U10
U9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A20
A22
A24
A26
C19
C21
C23
C25
C27
E20
E22
E24
F25
H25
K25
M25
P25
T25
V25
Y25
AB25
AD25
E27
G27
J27
L27
N27
R27
U27
W27
AA27
AC27
AE27
D29
F29
H29
K29
M29
P29
T29
V29
Y29
AB29
AD29
AF29
AE24
AG25
B4
B6
C8
C10
D2
F2
H2
K2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P2
T2
V4
AD1
AF1
AC3
AE3
AG3
AG5
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AJ4
AJ6
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AG27

+1.8VALW
+3VALW

1UF_10V_0603
C64
D

1UF_10V_0603
C65

1UF_10V_0603
C66

0.1UF
C67

0.1UF

0.1UF

0.1UF

+CPU_CORE

+1.8VS

CB64

CB65

C69

C68

10UF_10V_1206
CB67

1UF_10V_0603
CB68

0.1UF
C70

0.1UF
C71

10UF_10V_1206

1UF_10V_0603

0.1UF

0.1UF

CB66
10UF_10V_1206
CB69
1UF_10V_0603

C

+3VS

+2.5V

C72

C73

0.1UF
C74

0.1UF
C75

0.1UF

0.1UF

CB70

CB71

CB72

10UF_10V_1206
CB73

1UF_10V_0603
CB74

1UF_10V_0603
CB75

10UF_10V_1206

1UF_10V_0603

1UF_10V_0603

B

Place these capacitors under 650 solder side
+1.8VS

+CPU_CORE

+1.8VS

+3VALW
C76

C77

0.1UF
CB76

0.1UF
C81

+2.5V

C78

C79

C80

0.1UF
C82

0.1UF
C83

0.1UF
C84

10UF_10V_1206
+3VS

0.1UF

+3VS

0.1UF
C85

0.1UF
C86

0.1UF
C87

C88

C89

0.1UF
C91

0.1UF
C92

0.1UF
C93

0.1UF
C94

0.1UF
C90

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

A

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C

AB5
AD5
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE22

+3VALW

U 5D

B25
C28
C29
D27
D28
E28
E29
AF23
AF24
AF25
AG24
AG26
AH23
AH24

+2.5V

OVDD
OVDD
OVDD
PVDD
PVDD
PVDD
PVDD

D

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

PVDDZ

A16
A17
A18
B16
B17
B18
C16
C17
C18
D15
D16
D17
D18
E15
E16
E17
E18
F15
F16
F17
F18

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

+CPU_CORE

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

H21
H22
J16
J20
J21
J22
K16
K17
K18
K19
K20
K21
L20
M20
N20
P20
R20
R21
T20
U20
V20
W20
Y20
Y21
AA20
AA21
AA22
AB21
AB22

+1.8VALW

SIS650

Compal Electronics, Inc.
Title

SCHEMATIC, M/B LA-1341
Size
D ate:
5

Document Number

R ev
2A

401210

+1.8VS
4

3

2

¬P 期五, 十一月 15, 2002

Sheet
1

9

of

46

B

C

D

+2.5V

121
122

CS0
CS1

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

12
26
48
62
134
148
170
184
78

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8

0

R518

SWE#
SCAS#
SRAS#

119
120
118

WE
CAS
RAS

96
95

CKE0
CKE1

@100K

7,11
7,11
7,11

SWE#
SCAS#
SRAS#

7
7

CKE2
CKE3

13
13
13
13
13
13

DDRCLK3
DDRCLK3#
DDRCLK4
DDRCLK4#
DDRCLK5
DDRCLK5#

7,11
7,11
7,11
7,11
7,11
7,11
7,11
7,11

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7

CKE2
CKE3

12,13,17 SMBDAT
12,13,17 SMBCLK

35
37
160
158
89
91

CK0
CK0
CK1
CK1
CK2
CK2

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7

11
25
47
61
133
147
169
183
77

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

SMBDT
SMBCK

193
195

+3VS

MVREF_DIM

SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD

86
85
123
124
200

NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU

3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
126
138
150
162
174
186

+3VS

SDA
SCL

194
196
198
1
2
199
197

9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

71
73
79
83
72
74
80
84

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

MD[0..63] 7,11

7,11
7,11

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA13
MAA14

112
111
110
109
108
107
106
105
102
101
115
100
99
97

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13

MAA11
MAA12

117
116
98

BA0
BA1
DU/BA2

121
122

CS0
CS1

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

12
26
48
62
134
148
170
184
78

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8

SWE#
SCAS#
SRAS#

119
120
118

WE
CAS
RAS

96
95

CKE0
CKE1

RCS0#
RCS1#

R519
R564

+2.5V

7
7

CKE0
CKE1

13
13
13
13
13
13

DDRCLK0
DDRCLK0#
DDRCLK1
DDRCLK1#
DDRCLK2
DDRCLK2#

@100K
0

CKE0
CKE1

35
37
160
158
89
91

CK0
CK0
CK1
CK1
CK2
CK2

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7

11
25
47
61
133
147
169
183
77

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

SMBDT
SMBCK

193
195

SDA
SCL

194
196
198
1
2
199
197

SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD

86
85
123
124
200

NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU

MVREF_DIM
+3VS

MVREF_DIM
MVREF_DIM
C95
0.1UF

DDRAM_SODIMM_200P-L
Outsight

C96
1000PF

JP5
Upper
4

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

71
73
79
83
72
74
80
84

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

3

2

GND
GND

BA0
BA1
DU/BA2

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ

117
116
98

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

RDQM[0..7]

R563

2

MAA11
MAA12

RCS2#
RCS3#

7,11

+2.5V

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13

3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
126
138
150
162
174
186

3

112
111
110
109
108
107
106
105
102
101
115
100
99
97

GND
GND

7,11
7,11

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA13
MAA14

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ

MAA[0..14]

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

7,11

JP4
Lower

201
202

9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192

+2.5V

4

E

201
202

A

DDRAM_SODIMM_200P-R
Insight

+2.5V

1

R128

C486
0.1UF

C487
1000PF

-CS/-RAS/-CAS/-WE
R - 0101
W - 0100

MVREF_DIM
R129

1K_1%_0603
MVREF_DIM
R130

C97
0.1UF

SDREF
C98
1000PF

7,35

PC2100 - CL2 = 15 to Data 2-2-2/2.5-3-3
CL2.5 = 18.75 to Data
DDR266 256MB 4Bks Pmax = 8W
Ptyp = 7W
64MB/128MB/256MB - 500MB/s - 1.0W
- 1000MB/s - 1.65W
- 1500MB/s - 2.5W
- 2000MB/s - 3.2W

1

Compal Electronics, Inc.

@0_0603
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1K_1%_0603

SCHEMATIC, M/B LA-1341
Size

A

B

C

D

Document Number

R ev
2A

401210
D ate:

¬P 期五, 十一月 15, 2002

Sheet
E

10

of

46

A

B

C

D

E

Decoupling capacitors
(Place near DDR SODIMM)
+2.5V

4

CB77

1UF_10V_0603

CB79

1UF_10V_0603

CB81

1UF_10V_0603

CB83

1UF_10V_0603

CB85

1UF_10V_0603

Termianation Network place closely to DIMM
4

+1.25VS

+2.5V

7,10

C99

0.1UF

C100

0.1UF

C101

0.1UF

C104

0.1UF

C105

0.1UF

C106

0.1UF

C107

0.1UF

C109

0.1UF

RDQS0

10UF_10V_1206

CB88

10UF_10V_1206

CB89

10UF_10V_1206

CB90

10UF_10V_1206

C113
C117

7,10

RDQS1

0.1UF
0.1UF

7,10

3

7,10

7,10

RDQS2

RDQS3

RDQS4

Place these decoupling capacitors close to
VTT_MEM termination resistors.
7,10

RDQS5

2

+1.25VS

+1.25VS

C137

0.1UF

C139

1000PF

C140

0.1UF

C142

1000PF

C143

0.1UF

C145

1000PF

C148

0.1UF

C150

1000PF

C151

0.1UF

C153

1000PF

C154

0.1UF

C156

1000PF

C157

0.1UF

C158

1000PF

C159

0.1UF

C160

1000PF

C162

0.015UF

C163

0.015UF

C164

0.015UF

C165

0.015UF

C166

0.015UF

CE11

+

0.015UF

CE12
1

7,10

RDQS6

MD0
MD4
MD1
MD5
RDQS0
MD6
MD2
MD3

RP32

MD7
MD8
MD12
MD9
MD13
R DQS1
MD10
MD14
MD11
MD15
MD16
MD20
MD17
MD21
RDQS2
MD18
MD22
MD19
MD23
MD24
MD28
MD25
MD29
R DQS3
MD26
MD30
MD27
MD31
MD32
MD36
MD33
MD37
RDQS4
MD38
MD34
MD39
MD35
MD44
MD40
MD45
MD41
R DQS5
MD42
MD46
MD43
MD47
MD48
MD52
MD49
MD53
R DQS6
MD54
MAA10
MAA12

RP35

RP33

RP37

RP39

RP40

RP42

RP44

RP46

RP47

RP49

RP51

RP53

RP55

RP56

4P2R_33

1
2
3
4
1
2
3
4

8
7
6
5 8P4R-33_0804
8
7
6
5 8P4R-33_0804

1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5

RP57

1
2

+1.25V Island
> 150ml

C102
0.1UF

+1.25VS

MD50
MD55
MD51
MD60

RP34

1
2
3
4

8
7
6
5 8P4R-33_0804

MD56
MD61
MD57
RDQS7
MD62
MD58
MD63
MD59

RP36

1
2
3
4
1
2
3
4

8
7
6
5 8P4R-33_0804
8
7
6
5 8P4R-33_0804

MAA14
MAA13
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

RP41

C103
1000PF

8P4R-33_0804

7,10

RDQS7

8P4R-33_0804

RP38

C110

8P4R-33_0804

C111
1000PF

0.1UF
C114
0.1UF

C115
1000PF

8P4R-33_0804

8P4R-33_0804
C123
0.1UF

C124
1000PF

8P4R-33_0804

1
2
3
4
1
2
3
4
1
2
3
4

RP43

RP45

8
7
6
5 8P4R-33_0804
8
7
6
5 8P4R-33_0804
8
7
6
5 8P4R-33_0804

MAA11

R493

33

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

R494
R495
R496
R497
R498
R499
R500
R501

33
33
33
33
33
33
33
33

SRAS#
SWE#
SCAS#
R CS2#
R CS3#
R CS0#
R CS1#

R502
R503
R504
R505
R506
R507
R508

33
33
33
33
33
33
33

3

C120
C121
1000PF

0.1UF

C125
C126
1000PF

0.1UF

8P4R-33_0804
C127
0.1UF

C128
1000PF

8P4R-33_0804

8P4R-33_0804
C131
0.1UF

C132
1000PF

8P4R-33_0804

8P4R-33_0804
C135
0.1UF

C136
1000PF

C146
0.1UF

C147
1000PF

7,10
7,10
7,10
7,10
7,10
7,10
7,10
7,10

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

7,10
7,10
7,10
7,10
7,10
7,10
7,10

SRAS#
SWE#
SCAS#
RCS2#
RCS3#
RCS0#
RCS1#

C129
C130
1000PF

0.1UF

C133
0.1UF

C134
1000PF
2

8P4R-33_0804

8P4R-33_0804
4
3

+1.25VS

C161

100UF_D2_6.3V

+

+1.25VS

MAA[0..14]

7,10 MAA[0..14]

+2.5V

CB87

MD[0..63]

7,10 MD[0..63]

100UF_D2_6.3V
1

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
¬P 期五, 十一月 15, 2002

Sheet
E

11

of

46

A

B

C

D

E

Main Clock Generator
+3VS

1: (ICS:ICS952001)
L12
HB-1M2012-121JT

Place near to the Clock Outputs

A

U6
CLOCK GEN (650)

4

C167
0.1UF

+ CB91
10UF_10V_1206

C168
0.1UF

C172
0.1UF

C169
0.1UF

C170
0.1UF

C171
0.1UF

C173
0.1UF

C174
0.1UF

1
11
13
19
28
29
42
48

VDDREF
VDDZ
VDDPCI
VDDPCI
VDD48
VDDAGP
VDDCPU
VDDSD

12

PCI_STOP#

5
8
18
24
25
32
41
46

+3VS

R143

Damping Resistors
Place near to the
Clock Outputs

CPUSTP-

2

45

32,39 VR_POK
R154

475_1%_0603

R135
R136

33
33

CP UCLK0
C PUCLK-0

CPUCLK1
CPUCLK#1

44
43

R_ CPUCLK1
R_ CPUCLK-1

R137
R138

33
33

CP UCLK1
C PUCLK-1

R139

22

S DCLK

R140

SDCLK

47

AGPCLK0
AGPCLK1

31
30

R_AGPCLK0

ZCLK0
ZCLK1

9
10

R _ZCLK0
R _ZCLK1

R141
R142

14
15
16
17
20
21
22
23

CLKFS3
CLKFS4
R_P CICLK1
R_P CICLK2
R_P CICLK3
R_P CICLK4
R_P CICLK5

R144
R145
R146
R147
R148
R149
R150

2
3
4

CLKFS0
CLKFS1
CLKFS2

48M
24_48M/MULTISEL

27
26

R_UCLK48M
MULTISEL

SCLK
SDATA

35
34

VSSREF
VSSZ
VSSPCI
VSSPCI
VSS48
VSSAGP
VSSCPU
VSSSD

PCICLK_F0/FS3
PCICLK_F1/FS4
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

CPU_STOP#

33

PD#/VTT_PWRGD

38

IREF

REF0/FS0
REF1/FS1
REF2/FS2

22
2
1000PF
22
22

AGPCLK0
AGPCLK1

33
33
33
33
33
33
33

96XPCLK
EC_PCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

R151
R152
R153

2
1000PF
33
33
33

R EFCLK0
R EFCLK1
R EFCLK2

R155

22

UCLK48M

1
C175

1
C176

R131
R132

49.9_1%_0603
49.9_1%_0603

CP UCLK1
C PUCLK-1

R133
R134

49.9_1%_0603
49.9_1%_0603

4

CPUCLK0 3
CPUCLK0# 3
CPUCLK1 6
CPUCLK1# 6
SDCLK

7

AGPCLK0 6

Z CLK0
Z CLK1

ZCLK0
ZCLK1

8
16

96XPCLK 16
EC_PCLK 29
PCLK_MINI 26
PCLK_PCM 23
PCLK_1394 22
PCLK_LAN 21
SIOPCLK 27

3

REFCLK0 8,15
REFCLK1 17
CLK_14M_SIO 25,27
UCLK48M 18

B

+3VS

L13

SMB_CK_CLK 10,13,17
SMB_CK_DAT 10,13,17

HB-1M2012-121JT

36

C177
0.1UF

R_ CPUCLK0
R_ CPUCLK-0

C178

VDDA
+3VS

C179
MULTISEL

0.1UF

R156

10K

0.01UF

VSSA

XIN

37

XOUT

17,39 PM_STPCPU#

D23
@RB751V
1

40
39

R_ SDCLK

10K

3

CPUCLK0
CPUCLK#0

CP UCLK0
C PUCLK-0

+3VS

X1

14.318MHz
C180
10PF

2

7

6

2

C181
10PF

R157

10K

CLKFS0

R159

10K

CLKFS1

R161

@10K CLKFS2

R565

10K

CLKFS3

R164

10K

CLKFS4

R166

10K

*

FS4 FS3 FS2 FS1 FS0

CPU DDR

1

1

0

0

0

100.0 133.0 80.0 66.7 33.3

ZCLK AGP

PCI

1

1

0

0

1

100.0 100.0 80.0 66.7 33.3

0

0

1

1

1

100.0 133.3 80.0 66.7 33.3

1

1

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
¬P 期五, 十一月 15, 2002

Sheet
E

12

of

46

5

4

3

2

1

Clock Buffer (DDR)
1:(ICS:ICS93722)
D

D

C

+2.5VS

U7
CLOCK BUFFER (DDR48)

L14
HB-1M2012-121JT
1
2

1

1

1

1

3
12
23

C182
0.1UF

+2.5VS

2

2

2

CB92
10UF_10V_1206

C184
0.1UF

2

+
C186
0.01UF

L15
D
HB-1M2012-121JT
1
2

10

CB93

C187
0.1UF

VDD
VDD
VDD

10,12,17 SMB_CK_CLK

C188
0.01UF

SMB_CK_CLK

7

SMB_CK_DAT

22

SDATA

8

CLK_IN

FW DSDCLKO

FW DSDCLKO

R_DD RCLK0 4P2R_0
1
R_D DRCLK0#
RP58 2

4
3

DDRC LK0
DDR CLK0#

CLK1
CLK#1

4
5

R_DD RCLK1 4P2R_0
1
R_D DRCLK1#
RP59 2

4
3

DDRC LK1
DDR CLK1#

CLK2
CLK#2

13
14

R_DD RCLK2 4P2R_0
1
R_D DRCLK2#
RP60 2

4
3

DDRC LK2
DDR CLK2#

CLK3
CLK#3

17
16

R_DD RCLK3 4P2R_0
1
R_D DRCLK3#
RP61 2

4
3

DDRC LK3
DDR CLK3#

CLK4
CLK#4

24
25

R_DD RCLK4 4P2R_0
R_D DRCLK4#
RP62

2
1

3
4

DDRC LK4
DDR CLK4#

CLK5
CLK#5

26
27

R_DD RCLK5 4P2R_0
1
R_D DRCLK5#
RP63 2

4
3

DDRC LK5
DDR CLK5#

SCLK

FB_OUT

19

GND
GND
GND
GND

28
15
11
6

FB_OUT

R167

20

FB_IN

1

+2.5VS
SMB_CK_DAT
R168
R556

DDRCLK4 10
DDRCLK4# 10
DDRCLK5 10
DDRCLK5# 10

C189
@10PF

@22

2

C190

1

470
FW DSDCLKO

NC
NC
NC

DDRCLK3 10
DDRCLK3# 10

@10PF

1 2

SMB_CK_CLK

10,12,17 SMBCLK

9
18
21

DDRCLK2 10
DDRCLK2# 10

2

1

10,12,17 SMBDAT

DDRCLK1 10
DDRCLK1# 10

C

2

FB_IN

C

DDRCLK0 10
DDRCLK0# 10

22

1

7

2
1

AVDD

4.7UF_10V_0805

10,12,17 SMB_CK_DAT

CLK0
CLK#0

R169

2

1 2

@22
C191
@10PF

B

B

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Size

4

3

2

R ev
2A

401210
D ate:

5

Document Number
¬P 期五, 十一月 15, 2002

Sheet
1

13

of

46

A

B

C

D

E

D7
W=40mils

1

1

C192

@22PF

C196
18PF

1

1

C195

C197
18PF

2

@22PF

1

C194

2

@22PF

R_BLUE
DDC_MD2
C198
18PF

CRT Connector

75_1%_0603

2

75_1%_0603
2

2

2

75_1%_0603

C193

1

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

MSEN#

R_GREEN

2

R174

1

R173

29,30

@
2

R172

@
1

@
2

BLUE

1

8

1

GREEN

1

RED

8

1

8

Q11
2N7002

D

3

100PF

DDCDATA 8

Q13
2N7002

C203

2
G

DDCCLK

2
G

C202
220PF

1

C201

68PF

1

1

C200

2

68PF

2

2

C199

2

2

R176
@10K

S

3

D

1
1

1

1
2
FBM-11-160808-121

G

1

Q12
2N7002

R175
@10K

1
R177
1
R178

+12VS

CRTVDD

8

220PF

2

2

1

1

2

D

3

VSYNC

2

S

8

1

L20

G

Q10
2N7002

1
2
FBM-11-160808-121

D

1

2

S

3

H SYNC

S

L19
8

2

JP6
CRT-15P

1

R_RED

R171
1K

2

R170
1K

3

2

3

2

3

2

0.1UF

L16
1
2
FCM2012C-800_0805
L17
1
2
FCM2012C-800_0805
L18
1
2
FCM2012C-800_0805

CRTVDD

RB411D

POLYSWITCH_0.5A

1

2

2

F1

1

1

D10 CRTVDD
DAN217
1

D9
DAN217

1

+5VS
D8
DAN217

2
100K

+12VS

2
100K

2

Cable guide

1

PAD11

PAD12

1
+3VS

1

PAD_3.2X2.2MM

1

PAD_3.2X2.2MM

PAD_3.2X2.2MM

DDR EMI Clip

3

2

3

1
2

D13
DAN217

3

D12
DAN217

2

D11
DAN217
1

PAD10

TV-Out Connector

PAD5

PAD6

PAD7

1

PAD8

1

PAD-4.5X3.5

PAD9

1

PAD-4.5X3.5

1

PAD-4.5X3.5

1

PAD-4.5X3.5

PAD-4.5X3.5

3

3

H3

H4

H5

H6

HOLEA

HOLEA

HOLEA

HOLEA HOLEA

HOLEA

1

1

1

1

H10

HOLEA

H18

H19

H20

H12

H13

H14

H15

HOLEA

HOLEA

HOLEA

HOLEA

HOLEA HOLEA HOLEA

HOLEA

HOLEA HOLEA

H21

H22

H23

HOLEA

HOLEA

HOLEA

150PF

150PF

270PF

1

1

1

1

1

1

1

1

C210

1

1

1

1

1

C209

1

C208

1

C207

2

2

150PF

270PF

75_1%_0603 75_1%_0603
2

2

2

C206

2

R181

1

R180

75_1%_0603

2

R179

H9

HOLEA

H17

H11

S CONN._suyin

H8

H16

1

R_CRMA

1

1
2
3
4
5
6
7

H7

1

H2

HOLEA HOLEA

1

H1

JP7

1

S-Video
R_LUMA

COMPS

1

COMPS

2

15

CRMA

1

CRMA

1

15

LUMA

1

LUMA

1

15

2
47PF
L21
1
2
FBM-11-160808-121
1
2
C205
47PF
L22
1
2
FBM-11-160808-121

1

1
C204

FM1

FM2

1

CF1
1

FM4

FM3

1

CF2

FM5

1

1

1

1

CF3
1

CF4
1

CF12
1

CF13
1

CF14

1

1

CF5

CF6
1

CF7
1

CF8
1

4

CF11
1

1

CF15
1

CF16
1

FM6
1

CF17
1

CF9
1

CF10
1

4

CF18

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Size
Date:

A

B

C

D

Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

14

of

46

VBCTL_2

AS
VAGCLK
VAGCLK#
XI

VBCAD
VBHCLK

VBCAD
VBHCLK

PCIRST# R207 0
VSW INGR208 @0
R210 5.6K
D_VDD
R212 0
R213 0
VREF2

16,21,22,23,24,26,28,29 PCIRST#
R211
0
VREF2
R215 C232

R522

@10K 0.1UF

2K

C

122

121
58
36

HPD
RESET#
VSWING

ISET

110
109

VsyncIN
HsyncIN

VsyncOUT
HsyncOUT

VREF2

+3VS
Q14
SI2302DS
1

HB-1M2012-601JT_0805
C226
0.1UF

+3VS
1

FB9

CB103
+
ENABLK

29

1UF_10V_0603

C230
0.1UF

@0
@0

R521
R201
R202
R203

0
@0
@0
@0

E

JP8

TX0TX0+

16,21,22,23,24,26,28,29

D_VDD

INTA#

0

TX1TX1+

PIRQA#

TX4TX4+

8,16,23

R204

R205
TXBCLKTXBCLK+

147_1%
@10K

120
119

@10K

CLOSE TO U38

PID3
PID2
PID1
PID0

D C2
D D2

XI

TX6TX6+
D

D D2
LCDVDD_C
DAC_BRIG 29
INVT_PWM 29

DISPOFF#
H
2

C235

1 L23
FBM-L11-201209-221

B+

C485
68PF
C

2
+3VS

R217
0

6
29

0.1UF

R219
10K
RB751V

1

BKOFF#

DISPOFF#

2

LCDVDD_C
ENABLK

4.7UF_10V_0805

R223

FB10

@0

B

LCDVDD

PID0
PID1
PID2
PID3

PID0
PID1
PID2
PID3

4
3
2
1

SW DIP-4
R229 @0

3

0

+

U9
1

XIN/CLK

2

XOUT/MRA/FS0

3

SR1/MRA

4

VSS

8

SR0

7 R228

MODOUT

6

SSON

5

R230

0

0

CB105

10UF_10V_1206

C236
0.1UF

C237
0.1UF

1UF_10V_0603

XI

0

R231 @0

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R227

VDD

@P2010

Title
C241
@27PF

Compal Electronics, Inc.

A

SCHEMATIC, M/B LA-1341
Size
Document Number
Custom

R ev
2A

401210

Date:
8

CB104

C240
0.1UF

1

R225
5
6
7
8

2

4
3
2
1

1

PID3
PID2
PID1
PID0

5
6
7
8

REFCLK0

SW1

+3VS
2N7002

FBM-L11-201209-221

DV DD

8P4R_10K_0804

9

TX5TX5+

@33

A

10

TXACLKTXACLK+

301LV_LQFP128

2
DTC124EK

TX2TX2+

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

JST BM40B-SRDS

CB107 +
4.7UF_10V_0805

+ CB106

0.047UF

30
30
30
30

22K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

D C2

+3VS +3VS
R206

C229
0.1UF

0.1UF

D C2
D D2
PCIRST#

CB102

1UF_10V_0603

C231

LCDVDD_C
R198
R199

1

+

HB-1M2012-601JT_0805

1
3

1

3
2

1

HB-1M2012-601JT_0805

2

TXBCLK+
TXBCLKENAVDD
ENABLK

8,12

Q17

FB8
LPLL_VDD

V2COMP

2
0.1UF

DACVDD

D14

RP70
22K

F

0.1UF

C479
+3VS

R209

2

Q15
2N7002

C224
0.1UF

C227
2

+

1UF_10V_0603

Q16
2

ENAVDD

1UF_10V_0603
+ CB100

0_0805
R216
@0

1

150K

1 2

B

C239
C238

1
LVDD3

CB101

1
L24

3

R221

R222
100K

FB6

HB-1M2012-601JT_0805

R214

VBCTL0
R220
1K

G

C222
0.1UF

TVPLL_VDD

FB7

TXACLK+
TXACLK-

38

0.1UF

R218
100K

+12VS

1UF_10V_0603
+ CB99

C220
0.1UF

10PF

LCDVDD

LCDVDD

0.1UF

+3VS
+3VS

C474
+12VS

2

2
HPINT#

SPD
SPC
AS

C219

1

123
124
125
126
56
57

1UF_10V_0603

2

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5

XI/FIN
XO

DACVDD
@75_1%_0603
@75_1%_0603
@75_1%_0603
@75_1%_0603

14
14
14

1

113
112
115
114
117
116

52
53

1
2

2

SDC
SDD
DC1
DD1
DC2
DD2

XCLK2
XCLK2#

111

1

V5V

0 LPLL_VDD
LVDD2

LVDD3

@0

TX4+
TX4TX5+
TX5TX6+
TX6-

93
91

107
108
106

AS

17
18
14
15
11
12
8
9
5
6
127
128

H2
V2
DE2
FLD/STL2

+3VS

D

LDC_4
LDC#_4
LDC_5
LDC#_5
LDC_6
LDC#_6
LDC_7
LDC#_7
LL2C
LL2C#
ENAVDD
ENABKL

CB98

+
COMPS
LUMA
CRMA

1

6
6

R197 0
D2_CLK
D2_CLK#
D_VDD
R200 0
XTLO

D2_0
D2_1
D2_2
D2_3
D2_4
D2_5
D2_6
D2_7
D2_8
D2_9
D2_10
D2_11

TV_COMP
LUMA
CRMA
R520
0
V2COMP R187
R188
R189
R190

2

6
6

101
102
104
105

TVPLL1_VDD

1

D 2_HSYNC
D2_VSYNC
D2_DE

VAHSYNC
VAVSYNC
VADE

33
34
30
31
27
28
21
22
24
25

TX0+
TX0TX1+
TX1TX2+
TX2-

VREF1

LDC_0
LDC#_0
LDC_1
LDC#_1
LDC_2
LDC#_2
LDC_3
LDC#_3
LL1C
LL1C#

FB5

HB-1M2012-601JT_0805

6 HB-1M2012-601JT_0805

VBCLK

1

6
6
6

R196
360K

P-OUT
C/HSYNC
BCO/VSYNC
DACA_0
DACA_1
DACA_2
DACA_3
DACB_0
DACB_1
DACB_2
DACB_3

2

R195
10K

+3VS
LVDD2

1

85
86
87
88
89
90
94
95
96
97
98
99

FB4
@10PF

VBCLK

2

61

+3VS

+3VS

1

H1
V1
DE1
FLD/STL1

H

C217
0.1UF

C218
@10

2

66
65
63
62

CB97

2

VAD[0..11]

XCLK1
XCLK1#

+

2

E

6

@ 0.1UF

R194 0
VREF1
8P4R_33_0804
VAD0 RP67 4
R_VAD0
5
VAD1
R_VAD1
3
6
VAD2
R_VAD2
2
7
VAD3
R_VAD3
1
8
VAD4
R_VAD4
4
5
VAD5 RP68 3
R_VAD5
6
VAD6
R_VAD6
2
7
VAD7
R_VAD7
8P4R_33_0804
1
8
VAD8
R_VAD8
4
5
VAD9 RP69 3
R_VAD9
6
VAD10
R_VAD10
2
7
VAD11
R_VAD11
8P4R_33_0804
1
8

76
74

C216
0.1UF

1

0

VBHSYNC
VBVSYNC
VBDE
VBCTL1

0.1UF
1UF_10V_0603

1

R193 C225

6
6
6
6

D1_CLK
D1_CLK#
D_VDD
D 1_HSYNC
R192 0
D1_VSYNC
D1_DE

1UF_10V_0603

0.1UF

R186

59
49
50
41
43
45
47
40
42
44
46

3
4
10
16
23
29
35
67
75
92
100
51
39
48

F

VBGCLK
VBGCLK#

C215

2

VREF1

6
6

D1_0
D1_1
D1_2
D1_3
D1_4
D1_5
D1_6
D1_7
D1_8
D1_9
D1_10
D1_11

CB96

1

VBD[0..11]

@10K

68
69
70
71
72
73
77
78
79
80
81
82

FB3
VDDV

C214
+

1UF_10V_0603

1

HB-1M2012-601JT_0805

2

6

R191

+

+3VS

LVDD1
HB-1M2012-601JT_0805

1

+3VS

CB95

2

FB2

V5V

2

G

R_VBD0
R_VBD1
R_VBD2
R_VBD3
R_VBD4
R_VBD5
R_VBD6
R_VBD7
R_VBD8
R_VBD9
R_VBD10
R_VBD11

+3VS

3

1

8P4R_33_0804
VBD0 RP64 4
5
VBD1
3
6
VBD2
2
7
VBD3
1
8
VBD4 RP65 4
5
VBD5
3
6
VBD6
2
7
VBD7
8P4R_33_0804
1
8
VBD8
4
5
VBD9 RP66 3
6
VBD10
2
7
VBD11
8P4R_33_0804
1
8

4

2

U8

RP* PLACE CLOSE TO U45 PIN OUT

5

+5VS

DACVDD
TVPLL_VDD
TVPLL1_VDD
VDDV
D_VDD
@0
@0

0.1UF

R182
R183

C212

6

LPLL_GND
LGND
LGND
LGND
LGND
LGND
LGND
DGND
DGND
DGND
DGND
TVPLL_GND
DAC_GND
DAC_GND

2

0.1UF

LPLL_VDD

H

10UF_10V_1206

1

C211

2

CB94

+

1

D_VDD

C213 2

FB1

HB-1M2012-601JT_0805

1 @100P

7

LVDD1

8

1
2
7
13
19
20
26
32
37
55
54
60
64
83 R184
84 R185
103
118

9

DV DD DV DD

LPLL_VDD
LPLLCAP
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
DAC_VDD
TVPLL_VDD
TVPLL_VCC
VDDV
DVDD
DVDD
DVDD
DVDD
V5V

10

+3VS

7

6

5

4

3

星期五, 十一月 15, 2002
2

Sheet

15

of
1

46

A

B

+3VS

D

AD[0..31]

21,22,23,26 AD[0..31]

RP71
8P4R_8.2K_0804
4
5
3
6
2
7
1
8

J5
J4
H2
H1
J3
K4
J2
J1
K5
K2
L3
K1
L1
L4
L5
L2
N5
P2
P3
P4
R2
R3
R1
T1
P5
T2
U1
U2
T3
R5
U3
V1

E

RP73
8P4R_8.2K_0804
4
5
3
6
2
7
1
8
R233
8.2K

+3VS
RP74
8P4R_8.2K_0804
GNT#0
4
5
GNT#1
3
6
GNT#2
2
7
GNT#3
1
8
GNT#4 R234
8.2K

3

21,22,23,26 CBE#[0..3]

H3
G1
G2
G3
H4

PGNT#4
PGNT#3
PGNT#2
PGNT#1
PGNT#0

CBE#3
CBE#2
CBE#1
CBE#0

K3
M4
P1
R4

C/BE#3
C/BE#2
C/BE#1
C/BE#0

PIRQA#
PIRQB#
PIRQ C#
PIRQ D#

E3
F4
E2
G4

INT#A
INT#B
INT#C
INT#D

21,22,23,26 FRAME#
21,22,23,26 IR D Y#
21,22,23,26 T RDY#
21,22,23,26 STOP#

FRAME#
IR D Y#
T RDY#
STOP#

M3
M1
M2
N4

FRAME#
IRDY#
TRDY#
STOP#

21,23,26 SERR#
21,22,23,26 PAR
21,22,23,26 DEVSEL#

S ERR#
P AR
DEVSEL#
PLOCK#

M5
N3
N1
N2

SERR#
PAR
DEVSEL#
PLOCK#

IDSAB2
IDSAB1
IDSAB0

96XPCLK
P CIRST-

Y2
C3

PCICLK
PCIRST#

IDECSB#1
IDECSB#0

PIRQA#
PIRQB#
PIRQC#
PIRQD#

12
96XPCLK
8,20,29 PCIRST-

PCI

IDSAA2
IDSAA1
IDSAA0
IDECSA#1
IDECSA#0

C245
R235

961-1

@10
@10PF

Z CLK1

12 ZCLK1

V20

ZCLK

ZSTB0
ZSTB0#

N19
N20

ZSTB0
ZSTB0#

ZSTB1
ZSTB1#

K20
K19

ZSTB1
ZSTB1#

ZUREQ
ZDREQ

N16
N17

ZUREQ
ZDREQ

S VDDZCMP
SZCMP_N

R19
N18

VDDZCMP
ZCMP_N

SZCMP_P
SVSSZCMP

R18
P18

ZCMP_P
VSSZCMP

U20
U19

Z1XAVDD
Z1XAVSS

T20
T19

Z4XAVDD
Z4XAVSS

R20
P20

VZREF
ZVSSREF

8 ZSTB0
8 ZSTB0#

2.2K

8 ZSTB1
8 ZSTB1#
R237

10

8 ZUREQ
8 ZDREQ
10PF

+1.8VS
+1.8VS

2

R238

C247

150_1%_0603

0.1UF

R239

SZ4XAVDD
SZ4XAVSS

R240

SZ VREF
@4.7K
C248

150_1%_0603

0.1UF

ZSTB0
ZSTB1

R242

T11 IDESAA2
U11 IDESAA1
W11 IDESAA0

IDESAA [0..2]

IDEIOR#A 20
IDEIOW #A 20
IDACK#A 20

IDECS#A[0..1] 20

IIOR#B
IIOW#B
IDACK#B

T14
W16
V16

IDEIOR -B
IDEIOW -B
IDAC K-B

Y18 IDESAB2
T15 IDESAB1
V17 IDESAB0

20
20
20
20

IDESAA[0..2] 20

IDECS#A [0..1]

T12 ID ECS#A1
V12 ID ECS#A0

4

IC H R D YA
IDEREQA
IDEIRQA
CBLIDA

IDEIOR -A
IDEIOW -A
IDAC K-A

IC H R D YB
IDE REQB
I DEIRQB
CBLIDB

IC H R D YB
IDEREQB
IDEIRQB
CBLIDB

20
20
20
20

IDEIOR#B 20
IDEIOW #B 20
IDACK#B 20
3

IDESAB [0..2]

IDA0
IDA1
IDA2
IDA3
IDA4
IDA5
IDA6
IDA7
IDA8
IDA9
IDA10
IDA11
IDA12
IDA13
IDA14
IDA15

IDED A0
IDED A1
IDED A2
IDED A3
IDED A4
IDED A5
IDED A6
IDED A7
IDED A8
IDED A9
IDE DA10
IDE DA11
IDE DA12
IDE DA13
IDE DA14
IDE DA15

IDB0
IDB1
IDB2
IDB3
IDB4
IDB5
IDB6
IDB7
IDB8
IDB9
IDB10
IDB11
IDB12
IDB13
IDB14
IDB15

Y16
V15
U14
W14
V13
T13
Y13
Y12
W12
W13
U13
Y14
V14
W15
Y15
U15

IDED B0
IDED B1
IDED B2
IDED B3
IDED B4
IDED B5
IDED B6
IDED B7
IDED B8
IDED B9
IDE DB10
IDE DB11
IDE DB12
IDE DB13
IDE DB14
IDE DB15

IDESAB[0..2] 20

IDECS#B [0..1]

U16 ID ECS#B1
W18 ID ECS#B0
U10
V9
W8
T9
Y7
V7
Y6
Y5
W6
U8
W7
V8
U9
Y8
T10
W9

IDECS#B[0..1] 20

IDEDA[0..15] 20

2

IDEDB[0..15] 20
SIS961

R243

+3VALW
ZA D15
ZA D14
ZA D13
ZA D12
ZA D11
ZA D10
ZAD9
ZAD8
ZAD7
ZAD6
ZAD5
ZAD4
ZAD3
ZAD2
ZAD1
ZAD0

@4.7K

Put near 961A Chip.

14

@4.7K

C243
0.1UF

IC H R D YA
IDE REQA
I DEIRQA
CBLIDA

W17
Y17
T16
U17

M18
M19
M17
M16
M20
L16
L20
L18
K18
J20
K17
K16
H20
J18
H19
H18

ZSTB0#
ZSTB1#

S ZVREF_G

MULTIO
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15

R241

SZ VREF

@4.7K

C242
0.01UF

ICHRDYB
IDREQB
IIRQB
CBLIDB

IDE

C246
96XPCLK

V11
Y9
Y10

GNT#4
GNT#3
GNT#2
GNT#1
GNT#0

P ERR#

R236

IIOR#A
IIOW#A
IDACK#A

21,22,23,26 GNT#[0..4]

RP76
8P4R_4.7K_0804

P AR

ICHRDYA
IDREQA
IIRQA
CBLIDA

W10
V10
Y11
U12

PREQ#4
PREQ#3
PREQ#2
PREQ#1
PREQ#0

RP75
8P4R_4.7K_0804
4
5
3
6
2
7
1
8
4
5
3
6
2
7
1
8

21,22,23,26 PERR#

Y3
Y4

F1
F2
E1
H5
F3

+3VS

IR D Y#
T RDY#
DEVSEL#
STOP#
PLOCK#
P ERR#
S ERR#
FRAME#

IDEAVDD
IDEAVSS

REQ#4
REQ#3
REQ#2
REQ#1
REQ#0

8,15,23
21,23,26
22
26

+1.8VS

U10A

1

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

21,22,23,26 REQ#[0..4]

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

+3VS
4

E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
A D10
A D11
A D12
A D13
A D14
A D15
A D16
A D17
A D18
A D19
A D20
A D21
A D22
A D23
A D24
A D25
A D26
A D27
A D28
A D29
A D30
A D31

PIRQB#
PIRQA#
PIRQ C#
PIRQ D#

C

8 ZAD[0..15]
P CIRST-

2

U11A
74LVC125
3

PCIRST#

15,21,22,23,24,26,28,29

+1.8VS

Analog Power supplies of Transzip function for 961A Chip.
+3VS
L26

1
CB109
4.7UF_10V_0805

2
HB-1M2012-121JT C251
0.1UF

SZ4XAVDD
C252

7

L25

1

1

S VDDZCMP

2

HB-1M2012-121JT
CB108

C249

C250

4.7UF_10V_0805

0.1UF

0.01UF

0.01UF

R244

56.2_1%_0603SZCMP_N

R245

56.2_1%_0603SZCMP_P

1

Compal Electronics, Inc.

SVSSZCMP
Title

SZ4XAVSS

SCHEMATIC, M/B LA-1341
Size

Document Number

R ev
2A

401210
D ate:
A

B

C

D

¬P 期五, 十一月 15, 2002

Sheet
E

16

of

46

A

B

Programable on-die pull-high strength for CPU_S:
( Infinite, 150, 110, 56 Ohm)

C

D

+RTCVCC
W=30mils

W4
U7
V6

BATOK
8,32

PW RGD
C256
@0.1UF

OS C32KHI
OSC32KHO

LFRAME#
LDRQ#
SIRQ
BATOK

D1

PWROK

10PF

OSC32KHI

D2

OSC32KHO

33
BIT_CLK

GPIO
E4

RTCVSS

SDATI0
SDATI1

A2
D5

AC_SDIN0
AC_SDIN1

18,25,26 AC97_SDOUT
25,26 AC97_SYNC

W2
T5

AC_SDOUT
AC_SYNC

AC_RESET#
BIT_CLK
C258

25,26 AC97_RST#
25,26 AC97_BCLK

D6
Y1

AC_RESET#
AC_BIT_CLK

R259

2
R EFCLK1@10PF
SENTEST
SPKR

12 REFCLK1
18,25 SPKR
2

29 PW RBTN_OUT#
30 SBPME#
29,32 PSON#
8,29 RSM_RST

AC97

1
@33

W3
G5
V3

OSCI
ENTEST
SPK

ACPI

PW RBTN#
PME#
PSON#

A14
B14
D14

PWRBTN#
PME#
PSON#

AUXOK
ACP ILED

A3
A15

AUXOK
ACPILED

B8

GPIO0

V2

AC_ VID0

GPIO1/LDRQ1#

T8

AC_ VID1

GPIO2/THERM#

T4

AC_ VID2

GPIO3/EXTSMI#

T6

EXT_SMI# 2

GPIO4/CLKRUN#

W1

GPIO5/PREQ5#

U5

GPIO6/PGNT5#

U4

*GPIO7

C4

+3VALW
R542

3

3

1

1
1

2

1N4148

2

1

2

3904
J6

R249
BATOK

1

1

470

C254

2

+

C255
0.01UF

15K
SIS AP note

+3VALW
U41

MIIAV DD
AC_ VID3

1

D PRSLPVR

2

+3VALW

5

MIIAVSS
D18

3

4

PM_DPRSLPVR 39

7SH08

1

2

@1N4148

D55

2
D19

1
RB751V

1
RB751V

G PIO9

GPI10/AC_SDIN3

B3

GPIO10

*GPIO11

F5

GPIO11

*GPIO12/CPUSTP#

D4

PM_STPCPU#

*GPIO13/DPRSLPVR

B1

*GPIO14

E5

D13

*GPO18/PMCLK

B15

+3VALW

1

@1K

VR _HILO#

2

SW I#

29

A C_IN

29

100K

3

29

R255

5

4

PM_GMUXSEL 39

@7SH08
R540
0
GPIO10

R258

4.7K

PM_STPCPU# 12,39
Put closed to 961A CHIP
FLASH#

OSC32KHO
16

30

VR _HILO#

E13

B2

AC_ VID4

D PRSLPVR

*GPO17/VGATEM#

AUXOK

LID_OUT# 29

GPIO14

A16 RB751V 1

A1

PM_BATLOW# 29

R IN G

E6

R254
@0
U4

S CI#

C14

3

R554

EXTSMI# 29

AC_ VID3
D20
2
1
RB751V
AC_ VID4

G PIO5

EC_THERM# 29

2 D26

L O_HI#

OS C32KHI
GPIO pins pull HIGH

R260
PM_CPUPERF# 3

2

NEED NOT to place
10M_0603

VGATMBM

close to 961A
GPIO18
GPIO19
1
2N7002
GPIO20
Q20

IDERST# 20
SMBCLK

3

SMBDAT

SMBCLK
SMBDAT

10,12,13
C260

10,12,13

32.768KHZ
X3

15PF

+3VS

AC_ VID3
R288
AC_ VID2 R287
G PIO5
R262
EXT_SMI#
R263

C261

10K
10K
10K
10K

20PF
+3VALW

Q21
2N7002

961-2

1

NEED NOT to place
close to 961A

3

+3VS

2

1
+5VS

R282

2

LAD3
LAD2
LAD1
LAD0

LFRAME#

10K
+3VS

RP77

4
3
2
1

5
6
7
8

8P4R_10K_0804
+3VS

L DRQ#
SMBDAT

R274

10K

SDATI1

R280

100K

R551

SMBCLK

R276

10K

R266

10K
10K

R IN G

R268

PW RBTN#

R270

10K

PME#

R271

10K

10K

R272

@10K

R541

10K

10K

R275

SENTEST

+3VALW

10K

10K
R279

10K

1

47

R278
ATE request

Q49

3904

VR _HILO#
GPIO19
GPIO20

2

R283
R566
R567

10K
10K
10K

AC_ VID0
AC_ VID1

R285
R286

AC_ VID4
D PRSLPVR

R284

R289

4.7K

10K
10K
10K

Compal Electronics, Inc.
Title

SCHEMATIC, M/B LA-1341
Size

PM_STPCPU#

Document Number

R ev
2A

401210
D ate:

B

R264

G PIO9

H_DPSLP# 3

AC'97 Pull-Down:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GPIO18

PM_STPCPU#

10K

1

100K

3

R277

R257

VGATMBM

R273

S IRQ
SDATI0

GPIO14

GPIO11

+3VS

A

CB111
10UF_10V_1206

1UF_10V_0603

R251

SIS961

1

4

10K

4.7K

GPI9/AC_SDIN2

*GPIO20

1

2

MIIAVSS

/Geyserville

C259
0.1UF

D16

1

Decoupling Capacitor
Place close to 961A

B9

*GPIO19

Q19

47K

RTCBATT

MIIAVDD

*GPO16/LO_HI#

2
2

R248

BATT1

C5

*GPO15/VR_HILO#

W=30mils
22UF_10V_1206

J

E7

GPI8/RING
25 AC97_SDIN0
26 AC97_SDIN1

10K

+3VALW

R250

RB751V

MIIMDIO

RTCVDD

1

0.1UF

K

D17

MIIMDC

RTC

W=30mils

2

MIICRS

E9

2

MIICOL

B7

I

200_0603

+ CB110

C253

2

MIIRXD0
MIIRXD1
MIIRXD2
MIIRXD3

D8
A5
B5
A4

D15

R246
2 1

1

MIIRXDV
MIIRXER

C7
C8

Q18

RB751V

1

A7

R247

2

MIIRXCLK

MII

C2

C1

E8
D7
C6
B4

LPC

D3

R256

MIITXD0
MIITXD1
MIITXD2
MIITXD3

MMBT3906

+ RTCVCC

1

LAD0
LAD1
LAD2
LAD3

+RTCVCC

2

B6

CPU_S

3

C257

A6

MIITXEN

1

APICCK
APICD0
APTCD1

V5
T7
U6
W5

LFRAME#
L DRQ#
S IRQ

27,29
LFRAME#
27,29
LDRQ#0
23,27,29 S IRQ

Y19
V18
W19

MIITXCLK

+RTCVCC
W=30mils

W=30mils

1

LAD0
LAD1
LAD2
LAD3

LAD0
LAD1
LAD2
LAD3

INIT#
A20M#
SMI#
INTR
NMI
IGNNE#
FERR#
STPCLK#
CPUSLP#

2

27,29
27,29
27,29
27,29

MIICLK25M

T18
P16
R17
R16
Y20
U18
T17
W20
V19

2

4

INIT#
A20M#
SMI#
INTR
NMI
IGNN E#
FERRSTPCLK#
CPUSLP#

INIT#
A20M#
SMI#
INTR
NMI
IGNNE#
FERR#
STPCLK#
CPUSLP#

A8

2

CHGRTC
3
3
3
3
3
3
3
3
3

E

U10B

C

D

¬P 期五, 十一月 15, 2002

Sheet
E

17

of

46

A

B

C

D

E

U10C
12
UCLK48M

RP78

1

UV0+
UV0UV2+
UV2-

1
2
3
4

R290

8P4R-33_0804

@33

2

5
6
7
8

4

8
7
6
5

USB0_D+
USB0_DUSB2_D+
USB2_D-

CP1

RP79

8P4C-47P

C263

4
3
2
1

4
3
2
1

8P4R-15K_0804

@10PF

RP80
UV4+
UV4UV5+
UV5-

1
2
3
4

+3VUSB

31

OC0#

31

OC2#

31

OC4#

OC0OC1OC2OC3OC4OC5-

8P4R-33_0804

CP2

RP81

CB113

8P4C-47P

C264

UV0+/RSDP0
UV0-/RSDM0
UV1+/RSDP1
UV1-/RSDM1
UV2+/RSDP2
UV2-/RSDM2
UV3+/RSDP3
UV3-/RSDM3
UV4+/RSDP4
UV4-/RSDM4
UV5+/RSDP5
UV5-/RSDM5

B19
F19
B17
E19

UV1+
UV1UV3+
UV3-

5
6
7
8

3

USBCLK48M

B18
C18
E14
D15
E16
E15
D18
D19
E18
F18
G18
G19

E17
D17
D16
F17

1UF_10V_0603 0.1UF
4.7UF_10V_0805

4
3
2
1

4
3
2
1

8P4R-15K_0804

CB114

V4

G20
J16
H17
G17
H16
G16

5
6
7
8

8
7
6
5

USB4_D+
USB4_DUSB5_D+
USB5_D-

5
6
7
8

31
31
28
28

UV0+
UV0UV1+
UV1UV2+
UV2UV3+
UV3UV4+
UV4UV5+
UV5-

5
6
7
8

31
31
31
31

UCLK48M

UCLK48M

RP83

USBVDD
USBVDD
USBVDD
USBVDD

4

E11

LINKON

C19

LREQ
LPS
CPIO21
CPIO22
CPIO23
CPIO24

A19
A20
F20
D20
E20
C20

OSC12MHI
OSC12MHO

B16
A17

D11
C11

CTL0
CYL1

R543
4.7K

USBREF

F16

USB REF

USBPVDD
USBPVSS

A18
C15

US BPVDD
USBPVSS

IVDD_AUX
IVDD_AUX

C16
C17

IPBREST#
TDFRAME
RDFRAME
IPB_RDCLK
IPB_TDCLK
IPB_OUT0
IPB_OUT1
IPB_IN0
IPB_IN1

B11
D10
A11
E10
D9
B10
A10
C10
C9

USBREFAVDD

B20

USBVSS
USBVSS
USBVSS
USBVSS
D0
D1
D2
D3
D4
D5
D6
D7

A9

SCLK

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#

A12
B12
C12
D12
E12
A13
B13
C13

8P4R-15K_0804

NC

USB

USB REF

R534
+1.8VALW

+3VUSB

433_1%_0603
L52
US BPVDD

1

2

C477

HB-1M2012-121JT
CB184
C478

0.1UF

0.01UF

4.7UF_10V_0805

3

USBPVSS
+3VUSB

4
3
2
1

SIS961
R544
+5VALW
RP84

4
3
2
1

4.7K

5
6
7
8

OC1OC5OC3-

961-3
+3VUSB

+3VALW

8P4R-10K_0804

2

2

+3VS

SB Hardware Trap

17,25
SPKR
17,25,26 AC97_SDOUT

SPKR
SDATO
OC2OC5-

R292
R293

@10k
@10k

R294
R295

@15K
@15K

0

1

Default

SPKR( LPC addr mapping)

disable

enable

0

SDATO( PCICLK PLL)

enable

disable

0

OC2-( SB debug mode)

enable

disable

1

OC5-( Trap mode)

PCI AD

ROM

1

1

1

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Size

A

B

C

D

Document Number

R ev
2A

401210
D ate:

¬P 期五, 十一月 15, 2002

Sheet
E

18

of

46

5

4

3

+3VS

D

+1.8VS

2

1

+1.8VALW

D

+3VALW
CB115

CB116

10UF_10V_1206
CB119

CB120

1UF_10V_0603

CB121

CB117

C266
10UF_10V_1206

10UF_10V_1206
CB122
10UF_10V_1206

1UF_10V_0603

1UF_10V_0603

CB123

C267

1UF_10V_0603

0.1UF

CB118

C265

1UF_10V_0603
0.1UF

0.1UF

+CPU_CORE
CB124
+1.8VS
1UF_10V_0603
C268
0.1UF

C

+CPU_CORE

U10D

G15
J15
J17
L15
L17
N15
P17
K15
G6
H15
L6
M15
R6
R10
R14

VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
PVDDZ
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

P15
R15

VTT
VTT

H6
K6
M6
P6
R7
R9
R11
R13

OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD

J6
N6
R8
R12

PVDD
PVDD
PVDD
PVDD

F9
F12

IVDD_AUX
IVDD_AUX

F7
F10
F11
F14
F15

OVDD_AUX
OVDD_AUX
OVDD_AUX
OVDD_AUX
OVDD_AUX

F8
F13

PVDD_AUX
PVDD_AUX

+3VS
+CPU_CORE
Put under 96X solder side
C269
0.1UF
+1.8VS
C270
C271
0.1UF

B

0.1UF

+3VS

+3VALW

C272

C274

C273

0.1UF

0.1UF

0.1UF

C275

C276

C277

0.1UF

0.1UF

C278

C279

CB125

0.1UF

0.1UF

10UF_10V_1206

C280

C281

C282

0.1UF

0.1UF

+1.8VALW

+1.8VALW
+3VALW

0.1UF

Power

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H8
H9
H10
H11
H12
H13
J8
J9
J10
J11
J12
K8
K9
K10
K11
L8
L9
L10
L11
M8
M9
M10
M11
N8
N9
N10
N11
N12
N13

VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ

J13
J19
K12
K13
L12
L13
L19
M12
M13
P19

C

B

SIS961

0.1UF

961-4

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Size

4

3

2

R ev
2A

401210
D ate:

5

Document Number
星期五, 十一月 15, 2002

Sheet
1

19

of

46

5

4

3

2

1

+5VS

10K

17

1

IDERST#

14

D56
2

HDD/CD-ROM Module

RP85

IDESAA0
IDESAA1
IDESAA2
IDECS-A1

+5VS
R548

4
3
2
1

U12A

PD_A0
PD_A1
PD_A2
PD_CS#3

5
6
7
8

8P4R_33_0804

1
3

CD_IDERST#

IDECS-A0

R296

PD _D[0..15]

PD_D[0..15]

+5VS
PD_CS#1

33

2

6

HD_IDERST#

IDEDA11
IDEDA4
IDEDA10
IDEDA5

5
74HCT08
16

IDEDA[0..15]

IDEDA[0..15]

RP87
4
3
2
1

+3VS
IDEDA9
IDEDA6
IDEDA8
IDEDA7

ID ECS-A[0..1]

16 IDECS#A[0..1]

R300
4.7K

R301
R302
R304
R305
R306
R308

IDEREQA
IDEIOW#A
IDEIOR#A
I CHRDYA
IDACK#A
IDEIRQA

C

PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA

82_1%_0603
22
10
10
22
82_1%_0603

R309
10K

5
6
7
8

RP88
4
3
2
1

5
6
7
8

IDEDA3
IDEDA12
IDEDA2
IDEDA13

RP89
4
3
2
1

5
6
7
8

PD_D11
PD_D4
PD_D10
PD_D5

1
R298

2
10K

1

1

CB127
1UF_10V_0603

D

C284
0.1UF

JP9

HD_IDERST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_D9
PD_D6
PD_D8
PD_D7

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#

PD_D3
PD_D12
PD_D2
PD_D13

8P4R_10_0804

R310
5.6K

CB126
10UF_10V_1206

2

1000PF

Place component's closely IDE CONN.

8P4R_10_0804
16
16
16
16
16
16

C283

2

PD_D1
PD_D14
PD_D0
PD_D15

8P4R_10_0804

IDESAA[0..2]

16 IDESAA[0..2]

5
6
7
8

8P4R_10_0804

U12B
4

8,16,29 PCIRST-

RP86
4
3
2
1

1

IDEDA1
IDEDA14
IDEDA0
IDEDA15

2

74HCT08

1

D

2

7

RB751V

+5VS
+5VS

1
R311

2
10K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_CSEL 1
R303
PD_A2
PD_CS#3

2
470
CBLIDA

1

R307

2

16
+5VS

@100K
C

+5VS

HDD CONN
+5V_IDE

SD_SBA0
SD_SBA1
SD_SBA2
SD_SCS3#

CB128
10UF_10V_1206

1UF_10V_0603

1

1

CB129

C285
0.1UF

2

5
6
7
8

2

4
3
2
1

2

IDESAB0
IDESAB1
IDESAB2
IDECS#B1

16 IDECS#B[0..1]

1

RP90

1

W=80mils

+5VS

ID ECS-B[0..1]

2

IDESAB[0..2]
16 IDESAB[0..2]

C286
1000PF

Place component's closely IDE CONN.
IDECS#B0

8P4R_33_0804
R312
33

SD_SCS1#

+3VS

16
16
16
16
16

IDEREQB
IDEIOW#B
IDEIOR#B
I CHRDYB
IDACK#B
IDEIRQB

IDEREQB
IDEIOW-B
IDEIOR-B
I CHRDYB
IDACK-B
IDEIRQB

R315
R316
R317
R318
R319
R320

25

SD_DREQ
SD_SIOW#
SD_SIOR#
SD_SIORDY
SD_DACK#
SD_IRQ15

82_1%_0603
22
10
10
22
82_1%_0603

R321
10K

IDEDB[0..15]

9
25 ACT_LED#

R322
5.6K

IDEDB[0..15]

INT_CD_L

CDROM_L

8
10

HDD_LED#
CDLED#

74HCT08

IDEDB0
IDEDB15
IDEDB1
IDEDB14

RP91
4
3
2
1

5
6
7
8

8P4R_10_0804
RP92
4
5
3
6
2
7
1
8

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

CD_IDERST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0

U12C

IDEDB5
IDEDB9
IDEDB4
IDEDB11

16

AGND
JP10

SD_D5
SD_D9
SD_D4
SD_D11
+5VS

2
R324

SD_D0
SD_D15
SD_D1
SD_D14

SD_SIOW#
SD_SIORDY
SD_IRQ15
SD_SBA1
SD_SBA0
SD_SCS1#
CDLED# 2
1
R553
+5V_IDE
@0
+5V_IDE
1
10K
SD_CSEL
2

16

1

10UF_10V_1206
2
1
R313
10K
R314
4.7K

B

+5V_IDE trace to CONN W=80mils

CB130
2

R326
470

INT_CD_R

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

CDROM_R 25

SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ
SD_SIOR#

B

CBLIDB

SD_DACK#
R323
1

SD_SBA2
SD_SCS3#
W=80mils

2
C287

1
0.1UF

1
R325

2

16

@100K
+5VS

+5V_IDE
+5V_IDE
+5V_IDE

W=80mils

2
100K

+5VS

CD-ROM CONN.

1

8P4R_10_0804
IDEDB6
IDEDB10
IDEDB8
IDEDB7
A

IDEDB3
IDEDB12
IDEDB2
IDEDB13

RP93
4
3
2
1

5
6
7
8

8P4R_10_0804
RP94
4
5
3
6
2
7
1
8

SD_D6
SD_D10
SD_D8
SD_D7
A

SD_D3
SD_D12
SD_D2
SD_D13

8P4R_10_0804

Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

2

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
1

20

of

46

5

4

3

2

1

3

+3VLAN

Q24
2SB1197K

F

1

+VDD2.5

+VDD2.5

2
4.7UH_80mA

C288

C289

C290

C291

1

D

1
L28

1

+VDD2.5

1

VDD2.5

+3VLAN

G
2
4.7UH_80mA

1
L27

1

D

1

C292

1000PF 0.1UF 1000PF

2

0.1UF

2

0.1UF

2

2

C293

+ CB131
22UF_10V_1206

2

VCTRL 2

0.1UF

CB132
4.7UF_10V_0805
CB133
4.7UF_10V_0805

1

2

1

C303

1000PF 0.1UF 1000PF

2

C302

1

1

1

C301

C304
0.1UF

X4
25 MHz

LAN_X2
VCTRL
F
+3VLAN

LAN_X2
1

LAN_X1
C306
22PF

C307
22PF

2

5.6K_1%_0603

+3VLAN

+3VALW

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1

C308
0.1UF

0.1UF

LAN_X1
R332

2

C300

2

2

0.1UF

2

1

+3VLAN

C299
1

0.1UF

2

1

1

0.1UF

2

2

2
LAN_DIS#1
RB751V
D57

2

0.1UF

C298

1

LAN_DIS#

1
2

2

+3VLAN

30

0.1UF

C297

2

51

2

R331

51
C305
0.1UF

R329 4.7K
2
1

1

R330

2

1

2

1

51

ACTIVITY#
LINK10_100#

1

1
51
2

R328

C296

2

C295

0.1UF

LAN_TDLAN_TD+

R327

1

C294

2

LAN_RDLAN_RD+

1

1

22,23,26,29,30 LAN_PME#

AD17

2 100
AD23

1
R338

2

C311

8
7
6
5

1

VCC
NC
NC
GND
9346

C309
0.1UF

+3VLAN

AD4
AD5
AD6
26
26

AD7
CBE#0

RJ45_RXRJ45_RX+

16,22,23,26
U15
LAN_RD+
LAN_RD-

CB134
4.7UF_10V_0805

1
2
3

RTL8100-L

AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

LAN_TD+
LAN_TD-

6
7
8

RD+
RDCT

RX+
RXCT

CT
TD+
TD-

CT
TX+
TX-

16
15
14
11
10
9

B

Pulse-H0022
26
26

RJ45_TXRJ45_TX+

LED2_YELN 26

75 1%_0603
C313

LINK10_100#
(LAN_10LINK)

C312

R340
75 1%_0603

R339

ACTIVITY#
(LAN_100LINK)

+3VLAN
1

LED1_GRNN 26
0.1UF

2

16,22,23,26 CBE#2
16,22,23,26 FRAME#
16,22,23,26 IR DY#
16,22,23,26 TRDY#
16,22,23,26 DEVSEL#
16,22,23,26 STOP#
16,22,23,26 PERR#
16,23,26 SERR#
16,22,23,26 PAR
16,22,23,26 CBE#1

CS
SK
DI
DO

2

AD [0..31]

STOP#
PERR#
SERR#
PAR

16,22,23,26 AD[0..31]

AD18
AD17
AD16
C/BE#2
FRAME#
I RDY#
TRDY#
DEVSEL#

AD22

B

AD21
AD20
AD19

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

0.1UF

AD2
AD3

U14
1
2
3
4

1

1

16,22,23,26 CBE#3

AUX
LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO
AD0
AD1

2

F

@10PF

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

0.1UF

RJ45_GND 26

+3VALW

2

1 2
2

AD28
AD27
AD26
AD25
AD24

C310

AUX
EECS
EESK
EEDI
EEDO
AD0
AD1
GND
AD2
AD3
VDD25
VDD
AD4
AD5
AD6
VDD25
VDD
AD7
CBE0B
GND

C314
R341
2
2

R342

200_0603
1
200_0603
1

1

AD29

@22

+3VLAN

1

+3VLAN

5.6K

2

AD31
AD30

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

C

R334

1

1
R337

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

U13

2

CLK_PCI_LAN

12 PCLK_LAN
16
GNT#3
16
REQ#3

CLK_PCI_LAN

2 R335
2 R336

2

@0 1
0 1

LED0
LED1
NC
LED2
AVDD25
AVDD
ISOLATEB
GND
TXD+
TXDAVDD
AVDD25
RXIN+
RXINGND
RTSET
RTT2
RTT3
GND
X1
X2
AVDD
AVDD25
PMEB
GND
VCTRL
NC
NC
NC
VDD25

16,23,26 PIRQB#
15,16,22,23,24,26,28,29 PCIRST#
23,24
DEV_RST#

AD22
GND
AD21
AD20
AD19
VDD
VDD25
AD18
AD17
AD16
CBE2B
FRAMEB
IRDYB
TRDYB
DEVSELB
GND
STOPB
PERRB
SERRB
PAR
CBE1B
VDD
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

C

@1000PF_1206_2KV

LED2_YELP 26
LED1_GRNP 26

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

2

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
1

21

of

46

A

B

C

D

E

IEEE1394 Controller/PHY
+3VS

+3VA
L29

HB-1M2012-121JT
CB135
4.7UF_10V_0805

CB137
1UF_10V_0603

CB136

1

1

22UF_10V_1206
+3VS

C325
R344

R343
1M_0603

1

C323
0.1UF

2

0.1UF

1

C322

2

1

C321
0.1UF

2

0.1UF

1

C320

2

1

C319
0.1UF

2

1

0.1UF

2

1
2

1
2

C318

C324
0.1UF

Enable I2C EEPROM

10PF

10PF

C317
0.1UF

C326

+3VA

1K

AD [0..31]

C316
0.1UF

0.1UF

+3VS

16,21,23,26 AD[0..31]

1

C315

24.576MHz

2

X5

R345

2K
+3VS

R346

R347

0_0603
+3VS

1K

C327
0.1UF

C331

C328
0.1UF

C329
0.1UF

C330
0.1UF

0.1UF
C332
U16

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
16
PIRQC#
15,16,21,23,24,26,28,29 PCIRST#
12
PCLK_1394

PCLK_1394

1

PCLK_1394
3

16
16

C336

GNT#0
REQ#0

AD31
AD30
AD29
AD28
AD27

@22PF

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1394_PME# 21,23,26,29,30
+3VS
1
2
3
4

AD0
AD1

A0
A1
A2
GND

VCC
WC#
SCL
SDA

8
7
6
5

EECK_LAN
EEDI_LAN

1

U17
EECK_LAN
EEDI_LAN

R349
510

24C02-27

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12

CBE#0

16,21,23,26

3

AD13
AD14
AD15
CBE#1
PAR
PERR#

16,21,23,26
16,21,23,26
16,21,23,26

54.9_1%

54.9_1%

R351

R352
2

2

1 2

R350
@33

2

LPS/CMC
PME#
VSSC2
VDDC2
VSS9
VDD6
SCL/EECK
SDA/EEDI
EEDO
EECS
AD0
AD1
VSS8
RAMVSS
RAMVDD
AD2
AD3
AD4
VDD5
AD5
AD6
AD7
VSS7
CBE0#
AD8
AD9
AD10
AD11
AD12
VSS6
VDD4
AD13
AD14
AD15
CBE1#
PAR
PERR#
VSS5

1

C335
0.1UF

VDDARX0
XREXT
NC
GNDARX1
GNDATX1
XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0
VDDARX1
VDDATX1
XTPB1M
XTPB1P
XTPA1M
XTPA1P
XTPBIAS1
GNDARX2
GNDATX2
XTPB2M
XTPB2P
XTPA2M
XTPA2P
XTPBIAS2
VDDARX2
VDDATX2
INTA#
PCIRST#
PCICLK
VSS1
GNT#
REQ#
AD31
AD30
AD29
AD28
AD27
VDD1

2

XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0

XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102

1

0.1UF

1

C334
R348
6.34K_1%_06003 47PF

GNDARX0
XCPS
VDDATX0
XO
XI
GNDATX0
PHYRESET
LINKON/TSIJMP
LREQ/TSOJMP
CTL1/PC1JMP
CTL0/PC0JMP
D7/PC2JMP
D6/CMCJMP
D5
PGND2
PVDD2
D4
D3
D2
D1
D0
MODE0
MODE1
PGND1
SCLK
PVDD1

2

VSS2
AD26
AD25
AD24
CBE3#
IDSEL
AD23
AD22
VSS3
AD21
VDD2
VDDC1
VSSC1
AD20
AD19
AD18
AD17
AD16
VSS4
CBE2#
FRAME#
IRDY#
VDD3
TRDY#
DEVSEL#
STOP#

0.1UF
C333

1
2
3
4

2

2

1

1

C338
270PF

1394_FOX

R355
5.1K_1%_0603
4

2

2
100

4
3
2
1

R354
54.9_1%

2

1
R356

16,21,23,26
16,21,23,26
16,21,23,26
16,21,23,26
16,21,23,26
16,21,23,26

C_XTPA0+
C_XTPA0C_XTPB0+
C_XTPB0-

8
7
6
5

IEEE1394-CMF

1

1
AD16
AD17
AD18
AD19
AD20

AD21

AD22
AD23

AD24
AD25
AD26

STOP#
DEVSEL#
TRDY#
IR D Y#
FRAME#
CBE#2

JP11

L30

54.9_1%

16,21,23,26 CBE#3
4

0.33UF_16V_0805

2

2

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

R353

AD16

C337

VT6306

@ X3

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

22

of

46

R488

S2_VCC

1

1

C344
0.1UF

C345
0.1UF

2

2

2

4.7UF_10V_0805

0.1UF

B

A

IRQ/DMA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
A D10
A D11
A D12
A D13
A D14
A D15
A D16
A D17
A D18
A D19
A D20
A D21
A D22
A D23
A D24
A D25
A D26
A D27
A D28
A D29
A D30
A D31

A D20

2

100

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCM_INTB#
PCM_INTA#

R368

S1_BVD1
S1_BVD2
S1_CD1#
S1_CD2#
S1_RD Y#
S1_WAIT#
S1_WP
S1_INPACK#

A_CE1#/CC/BE0#
A_CE2#/CAD10
A_WE#/CGNT#
A_IORD#/CAD13
A_IOWR#/CAD15
A_OE#/CAD11
A_VS1#/CVS1
A_VS2#/CVS2
A_REG#/CC/BE3#
A_RESET/CRST#

P13
R13
R19
W15
V15
U14
J18
M19
K17
L18

C350

1000PF

1000PF

1000PF

+3V_PCMCIA

S1_VS1
S1_VS2
S1_RST

+3VALW

R361

1

2

S1_A16

47
Placement near
to PCMCIA
controller

S1_BVD1 24
S1_BVD2 24
S1_CD1# 24
S1_CD2# 24
S1_RDY# 24
S1_WAIT# 24
S1_WP
24
S1_INPACK# 24
S1_CE1# 24
S1_CE2# 24
S1_WE#
24
S1_IORD# 24
S1_IOW R# 24
S1_OE#
24
S1_VS1
24
S1_VS2
24
S1_REG# 24
S1_RST
24

S1_A23
S1_WP

1

22K
2

S1_VCC

1

2

S1_VCC

R363

22K

R364

1

2

+3V_PCMCIA

D27
PCM_INTA#

22K
1

GND

2

PIRQA#

8,15,16

RB751V

R367
1

PCI1420-GHK

P CM_RI#

R370
S IRQ

C351

R362

PCM_PME# 21,22,26,29,30
PM_CLKRUN# 26,27,29
P CM_RI#
1
2
R369 10

1

H19
J15
V11
H17
J17
J14
H18
L14

C349

2

A_BVD1/CSTSCHG
A_BVD2/CAUDIO
A_CD1#/CCD1#
A_CD2#/CCD2#
A_READY/CINT#
A_WAIT#/CSERR#
A_WP/CCLKRUN#
A_INPACK/CREQ#

1000PF

1

S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A7
S1_A8
S1_A9
S1_A10
S1_A11
S1_A12
S1_A13
S1_A14
S1_A15
SA_A16
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25

C348

2

J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P17
P19
N17
N19
M18

1

A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18
A_A8/CC/BE1#
A_A9/CAD14
A_A10/CAD9
A_A11/CAD12
A_A12/CC/BE2#
A_A13/CPAR
A_A14/CPERR#
A_A15/CIRDY#
A_A16/CCLK
A_A17/CAD16
A_A18/RSVD
A_A19/CBLOCK#
A_A20/CSTOP#
A_A21/CDEVSEL#
A_A22/TRDY#
A_A23/CFRAME#
A_A24/CAD17
A_A25/CAD19

1

S1_D0
S1_D1
S1_D2
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_D8
S1_D9
S1_D10
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

2

H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F19
P11
V12
P12
W13
U13

2

A11

M17

M5

Slot

GRST#

VCCA

VCCB

D1
E11

F18
VCCI

VCCP
VCCP

F14
E19
F17
G15
DATA
CLOCK
LATCH
SPKOUT

B13

C13
GNT#

REQ#

E2
A5
C8
A15
C/BE0#
C/BE1#
C/BE2#
C/BE3#

Slot

A_D0/CAD27
A_D1/CAD29
A_D2/RSVD
A_D3/CAD0
A_D4/CAD1
A_D5/CAD3
A_D6/CAD5
A_D7/CAD7
A_D8/CAD28
A_D9/CAD30
A_D10/CAD31
A_D11/CAD2
A_D12/CAD4
A_D13/CAD6
A_D14/RSVD
A_D15/CAD8

+3V_PCMCIA

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2

C343

+3V_PCMCIA

U40

G2
J5
P2
P9
V14
K18
E18
F12
B10
E8
C5

22K

S2_VCC

0.1UF

DEV_RST# 21,24

2

1 2

Interface

22K

2

+3V_PCMCIA

CB138

2

A10

PCI

RIOUT#/PME#

S2_RST

Power

C14

S2_VS1
S2_VS2

PCLK

B_CE1#/CC/BE0#
B_CE2#/CAD10
B_WE#/CGNT#
B_IORD#/CAD13
B_IOWR#/CAD15
B_OE#/CAD11
B_VS1#/CVS1
B_VS2#/CVS2
B_REG#/CC/BE3#
B_RESET/CRST#

+3V_PCMCIA

0.1UF

10PF

PAR
SERR#
PERR#
STOP#
IRDY#
TRDY#
RSTIN#
DEVSEL#
FRAME#

K6
L2
P3
L5
M2
L6
U8
P7
P8
W5

+3V_PCMCIA

S1_VCC
C342

1

R366

B_BVD1/CSTSCHG
B_BVD2/CAUDIO
B_CD1#/CCD1#
B_CD2#/CCD2#
B_READY/CINT#
B_WAIT#/CSERR#
B_WP/CCLKRUN#
B_INPACK/CREQ#

C347
2
CBRST#

IDSEL

1

S2_CE1#
S2_CE2#
S2_WE#
S2_IORD#
S2_IOW R#
S2_OE#
S2_VS1
S2_VS2
S2_REG#
S2_RST

V9
W9
H3
R9
V8
W8
U9
R7

S2_VCC

W=40mils

S 1_VCC_R

1

C10

S2_A23

24
24
24
24
24
24
24
24
24
24

S2_BVD1
S2_BVD2
S2_CD1#
S2_CD2#
S2_RD Y#
S2_WAIT#
S2_WP
S2_INPACK#

W=40mils

S 2_VCC_R

+3V_PCMCIA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

R365
1

S2_BVD1
S2_BVD2
S2_CD1#
S2_CD2#
S2_RDY#
S2_WAIT#
S2_WP
S2_INPACK#

0.1UF

2

C346

H5
G1
G3
H6
F1
G5
F2
E1
G6
F5
E3
C12
A4
E6
B5
F6
B8
A8
E9
F9
B9
A9
F10
E10
F11
E13
C11
B11
A12
B12
E12
A13

S2_WP

24
24
24
24
24
24
24
24

2

33

1

+3VS

C340
0.1UF

INTA#/MFUNC0
INTB#/MFUNC1
SUSPEND#
DMAREQ#/MFUNC2
IRQSER/MFUNC3
LOCK#/MFUNC4
DMAGNT#/MFUNC5
CLKRUN#/MFUNC6

47
Placement near
to PCMCIA
controller

2

2

0.1UF

F15
E17
D19
A16
C15
E14
F13
B15

1

B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A7/CAD18
B_A8/CC/BE1#
B_A9/CAD14
B_A10/CAD9
B_A11/CAD12
B_A12/CC/BE2#
B_A13/CPAR
B_A14/CPERR#
B_A15/CIRDY#
B_A16/CCLK
B_A17/CAD16
B_A18/RSVD
B_A19/CBLOCK#
B_A20/CSTOP#
B_A21/CDEVSEL#
B_A22/CTRDY#
B_A23/CFRAME#
B_A24/CAD17
B_A25/CAD19

C341

2
@0_0805

1

1
S2_A16

R8
W7
V7
W6
V6
U6
V5
U5
N1
M3
L1
M1
T1
N3
P1
P5
P6
M6
N2
N6
N5
R1
R2
R3
W4
R6

C339

R359

C6
B6
A6
F7
A7
B7
A14
C7
F8
R360

S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A7
S2_A8
S2_A9
S2_A10
S2_A11
S2_A12
S2_A13
S2_A14
S2_A15
SB_A16
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A24
S2_A25

B_D0/CAD27
B_D1/CAD29
B_D2/RSVD
B_D3/CAD0
B_D4/CAD1
B_D5/CAD3
B_D6/CAD5
B_D7/CAD7
B_D8/CAD28
B_D9/CAD30
B_D10/CAD31
B_D11/CAD2
B_D12/CAD4
B_D13/CAD6
B_D14/RSVD
B_D15/CAD8

+3V_PCMCIA

R489

1

16,21,22,26 PERR#
16,21,26 SERR#
16,21,22,26 PAR

W10
U10
P10
H2
J1
J3
K1
K3
V10
R10
W11
H1
J2
J6
K2
K5

2
0_0805

1

1
L

16,21,22,26 FRAME#
16,21,22,26 DEVSEL#
15,16,21,22,24,26,28,29 PCIRST#
16,21,22,26 T RDY#
16,21,22,26 IR D Y#
16,21,22,26 STOP#

S2_D0
S2_D1
S2_D2
S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_D8
S2_D9
S2_D10
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15

CARDBUS
PCI1420

+3V_PCMCIA

2
10 2
10

1

1
1R357
R358

1

GNT#2
REQ#2

16,21,22,26 CBE#3
16,21,22,26 CBE#2
16,21,22,26 CBE#1
16,21,22,26 CBE#0
12
PCLK_PCM

SLATCH 24
PCM_SPK# 25

F3
L3
U7
W12
N15
G19
B14
C9
E7

16
16

RTCCLKA
SLDATA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

24
24
S1_ D[0..15]
S 1_A[0..25]
S2_ D[0..15]
S 2_A[0..25]
AD[0..31]
C/BE#[0..3]

24
S1_D[0..15]
24
S1_A[0..25]
24
S2_D[0..15]
24
S2_A[0..25]
16,21,22,26 AD[0..31]
16,21,22,26 CBE#[0..3]

PCM_INTB#
PCM_RI# 27

22K
2

1
D28

+3V_PCMCIA

2
RB751V

PIRQB#

16,21,26

22K

17,27,29 1

2

2

1

D29

RB751V

+3V_PCMCIA
PCM_SUSP# 29

Compal Electronics, Inc.
Title

SCHEMATIC, M/B LA-1341
Size

B
D ate:

Document Number

R ev
2A

401210
¬P 期五, 十一月 15, 2002

Sheet

23

of

46

CARDBUS

23
23
23
23

SOCKET

PCMCIA POWER CTRL.

S1_ D[0..15]
S 1_A[0..25]
S2_ D[0..15]
S 2_A[0..25]

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]

+12VALW
S1_VPP
+5VALW

S1_VPP

U19

1

S1_VCC

23

S1_VS2

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22
S1_A16
S1_VPP
S1_VCC

23

S1_RDY#

23

S1_WE#

23

S1_IOW R#

23

S1_IORD#

23
23
23

23

23

S1_VS1
S1_OE#
S1_CE2#

S1_CE1#

S1_CD1#

S1_A21
S1_RD Y#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOW R#
S1_A9
S1 _IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

23

3.3V
3.3V
3.3V

R570

R571

CB143

4.7UF_10V_0805

@47K @47K

S1_RST

S2_RST
CB146

S1_OE#

S2_OE#

CB147

23
4.7UF_10V_0805
23
23
4.7UF_10V_0805

+3VALW

23

@100K
R372

DATA
LATCH
CLOCK

S2_A7
S2_A24
S2_A12
S2_A23
S2_A15
S2_A22

GND

12

C352
0.1UF

S1_VCC

PCMRST# 29

C353
0.1UF

C354
0.01UF

CB148
4.7UF_10V_0805

15,16,21,22,23,26,28,29 PCIRST#

9
+3VALW POWER

8

S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

DEV_RST#

DEV_RST# 21,23

R374
10K
U11C

+3VALW

74LVC125

S2_VCC

S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10

DEV_RST# 21,23
MODIFY BY
10/27/2000

+3VALW

S2_VPP

S2_A17
S2_A8
S2_IOW R#
S2_A9
S2 _IORD#

CB144
4.7UF_10V_0805

8.2K

S2_A16

S2_A21
S2_RD Y#
S2_A20
S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13

6 TP
14
26
27
28
29

NC
STBY#
OC#

S2_VCC
TPAD1

NC
NC
NC
MODE

S2_VPP

R373

8.2K

S2_WAIT# 23

23

R371

RESET
RESET#

S2_VPP

TPS2216AI

S2_INPACK# 23

S2_VS2

13
19
18

4.7UF_10V_0805

S2_REG# 23

S2_RST

3
5
4

SLDATA
SLATCH
RTCCLKA

23
20
21
22

10

S1_RST

S2_BVD2

15
16
17

BVPP
BVCC
BVCC
BVCC

S2_VCC
S2_RDY# 23
S2_WE#

23

C355
0.1UF

C356
0.01UF

CB149
4.7UF_10V_0805

S1_VPP
S2_IOW R# 23

1

S1_WAIT#

23

S2_WAIT#
S2_A4
S2_RST
S2_A5
S2_VS2
S2_A6
S2_A25

R569

CB145
23

5V
5V
5V

4.7UF_10V_0805

C357
0.01UF

S2_IORD# 23
S2_VS1
S2_OE#
S2_CE2#

CB150
4.7UF_10V_0805

23
23
23
C358

S2_CE1#

2

23

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

CB142

@47K @47K

S2_BVD1

4.7UF_10V_0805

23

S1_CD1# 1
1000PF

2
C360

S1_CD2# 1
1000PF
S2_CD1# 1
1000PF

S2_VPP

1

S1_INPACK#

S2_A0
S2_BVD2
S2_A1
S2_REG#
S2_A2
S2_INPACK#
S2_A3

CB141

S2_CD2# 23
S2_WP
23
R568

12V
12V

1
2
30

C359
0.01UF

2

23

S2_D10
S2_D2
S2_D9
S2_D1
S2_D8
S2_D0
S2_BVD1

7
24

1

S1_REG#

S2_CD2#
S2_WP

2.2UF_16V_0805

S2_VCC

CB139
4.7UF_10V_0805

2

23

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

S1_VCC

1

S1_BVD2

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

2

23

S1_BVD1

S1_CD2#
S1_WP

157
158
159
160

23

S1_CD2#
S1_WP

157
158
159
160

23
23

b68
b34
b67
b33
GND
b66
b32
b65
b31
b64
b30
b63
GND
b29
b62
b28
b61
b27
b60
b26
GND
b59
b25
b58
b24
b57
b23
b56
GND
b22
b55
b21
b54
b20
b53
GND
b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13
GND
b46
b12
b45
b11
b44
GND
b10
b43
b9
b42
b8
GND
b41
b7
b40
b6
b39
b5
GND
b38
b4
b37
b3
b36
b2
b35
b1

8
9
10
11

2

CB140

a68
a34
a67
a33
GND
a66
a32
a65
a31
a64
a30
a63
GND
a29
a62
a28
a61
a27
a60
a26
GND
a59
a25
a58
a24
a57
a23
a56
GND
a22
a55
a21
a54
a20
a53
GND
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
GND
a46
a12
a45
a11
a44
GND
a10
a43
a9
a42
a8
GND
a41
a7
a40
a6
a39
a5
GND
a38
a4
a37
a3
a36
a2
a35
a1

AVPP
AVCC
AVCC
AVCC

1

JP12

A77
A76
A75
A74
A73
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

NC

2

25
+3VALW

CB151
4.7UF_10V_0805

2
C361
2
C362

S2_CD1# 23

S2_CD2# 1

2

1000PF

PCMC154PIN

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
¬P 期五, 十一月 15, 2002

Sheet

24

of

46

A

BEEP#

C

D

E

F

G

H

+3VS
1

29

B

+3VS

2

U11D
74LVC125
12

14

13

R375
100K_1%_0603

C363
0.22UF

1

1

2

1

R377
1
2
10K_1%_0603

U20A
74LVC14
+3VALW POWER

2

11
+3VALW POWER

2
1
1
CB152
R378
1UF_10V_0603

2
560
1

14

+3VS

23

3

PCM_SPK#

4
U20B
74LVC14
+3VALW POWER

2
1
1
CB155
R380
1UF_10V_0603

2
560

2
1
1
CB156
R382
1UF_10V_0603

2
560

MONO_IN

6

R383
10K
2

U20C
74LVC14
+3VALW POWER

1

5

SPKR

D30
RB751V
2

17,18

1

14

+3VS

2

U20D
74LVC14
8

AC97 CODEC ALC202

3

MONO_IN
MOD_AUDIO_MONR

MOD_AUDIO_MONR
+3VS

0
R558

1

20
20

2

CDROM_L
CDROM_R
INTMIC

Q26
@SI2304DS
D

S

28

3

INT_MIC

29
29

PS2_DATA
PS2_CLK
29
EC_MUTE
30
FULL_LED#
20
ACT_LED#
30 CHARGING_LED#
30 POWER1_LED#
30 POWER2_LED#
29 LED2

INTMIC

1

2

G

1

R386

2

EC_MUTE

+5VS
+5VALW
+3VALW

+12VS

1

@100K
D
Q27
@2N7002

AC97_BCLK
2

CLK_14M_SIO
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

R559

R560

@33

@33
1

2

17,26 AC97_BCLK
29
HPLUG
17,26 AC97_RST#
17,26 AC97_SYNC
17,18,26 AC97_SDOUT
17 AC97_SDIN0
26 MD_MIC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

R385
33K

AC97_BCLK

2

JP29
CLK_14M_SIO

12,27 CLK_14M_SIO

CONN

C481
1

MOD_AUDIO_MONR

1
20K
1

26 MOD_AUDIO_MON

2
R384

2

9

@22PF

3

C482
1

14

2

@22PF

CODEC CONN
2
G

MIC_MUTE 29
GND-MIC

3

S

AGND

J8
2

1

4

4

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

B

C

D

E

F

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002
G

Sheet

25
H

of

46

A

B

C

D

E

Mini-PCI Slot

+5VS

JP15

C368

CB157

0.1UF

4.7UF_10V_0805

1
2
HEADER 2
1

1

+3.3VAUX

C370
1000PF

2

2

1

C366

C372

CB158

0.1UF

4.7UF_10V_0805

220PF_3KV_1808

2

220PF_3KV_1808

2

1

C365

1

1000PF

1

C367

2

2

1

MOD_RING
MOD_TIP

1

1000PF

1

C374

2

2

1

+3VS

AD [0..31]
C376

CB160

0.1UF

4.7UF_10V_0805

AD[0..31] 16,21,22,23

JP16

127

127

129

RING

JP14
21

W=40mils
PIRQB#

PCIRST#

15,16,21,22,23,24,28,29

GNT#1

GNT#1

RJ45_TX-

21

RJ45_RX+

21
W=40mils

+3.3VAUX

W=40mils

+3VS

21

RX+
R387 75_1%_0603

RJ45_GND

RX-

RJ45_RX-

16

R389 75_1%_0603

8

TX+

7

TX-

6

RX+

5

N/C1

4

N/C2

3

RX-

2

N/C3

1

N/C4

C373

MOD_TIP

9

GND1

13

CATHODE1

16

ANODE1

15

CATHODE2

17

NPTH
LED1_GRNN

LED1_GRNN 21

LED1_GRNP

LED1_GRNP 21

LED2_YELP

ANODE2

LED2_YELN

18

N/C6

GND2

LED2_YELN 21

14

NPTH
C377

C378

C379

1

12

LED2_YELP 21

TIP

1

MOD_RING

16,21,22,23

RING

1

PAR

11

1

VH1
DSSA-P3100SB

1

10

AD27

2

2
100

2

N/C5

1

2

220PF_3KV_1808

2

1
R392

AD22
AD20
AD18
AD16

21

TX-

MINI_PME# 21,22,23,29,30
LAN_PME# 21,22,23,29,30

R390 2
1
AD30 0
AD28
AD26
AD24
MINI_IDSEL

16,21,23
16

TX+

RJ45_TX+

1

PCIRST#

PIRQB#
GNT#4

+5VS

C380

47PF

47PF

2

47PF

2

16,21,22,23
16,21,22,23
16,21,22,23

2

FRAME#
TRDY#
STOP#

2

RJ-45 & RJ-11
47PF

DEVSEL# 16,21,22,23
AD15
AD13
AD11
AD9
CBE#0

16,21,22,23
3

AD6
AD4
AD2
AD0

+5VS

AC97_SDOUT 17,18,25
AC97_RST# 17,25

C382
1000PF

C383
0.01UF

1

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

2

2

1

3

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

2

2

3
5
7
9
D33
11
1
2
13
RB751V
15
PIRQD#
17
16
PIRQD#
W=40mils
19
+3VS
21
16
REQ#4
23
PCLK_MINI
25
12
PCLK_MINI
27
REQ#1
29
16
REQ#1
31
AD31
33
AD29
35
37
AD27
R391
39
AD25
100
41
AD31
LAN_IDSEL
1
2
43
45
16,21,22,23 CBE#3
AD23
47
49
AD21
51
AD19
53
55
AD17
57
59
16,21,22,23 CBE#2
61
16,21,22,23 IR D Y#
63
CLKRUN#
65
23,27,29 PM_CLKRUN#
67
16,21,23 SERR#
69
71
16,21,22,23 PERR#
73
16,21,22,23 CBE#1
AD14
75
77
AD12
79
AD10
81
83
AD8
85
AD7
87
89
AD5
91
93
AD3
95
W=30mils
97
+5VS
AD1
99
101
103
17,25 AC97_SYNC
R393 2
22
1
105
17 AC97_SDIN1
R394 2
107
1 22
17,25 AC97_BCLK
109
2
1
+3.3VAUX
MD_AUDIO_MON 111
C384
15PF
25 MOD_AUDIO_MON
113
115
25 MD_MIC
117
119
121
27 MODEM_RI#
W=30mils
123
+5VS

1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

1

1

2

TIP
29 Wireless_OFF#

CB161
22UF_10V_1206

MD_AUDIO_MON

W=40mils

+3.3VAUX

129

Mini-PCI SLOT

+3.3VAUX

+3VALW

1

PCLK_MINI

4

the channel width 50 mils
4

R395
@10

2

1 2

DIGITAL GND

MINI_GNDA

C389
@15PF

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

26

of

46

5

4

3

2

1

SUPER I/O SMsC LPC47N227

CP4

RTS#1
RXD1
DSR#1
DCD#1

1
2
3
4

DTR#1
CTS#1
TXD1
R I#1

1
2
3
4

8
7
6
5
8P4C-220PF
CP5
8
7
6
5

+3VS

2

2

LPD[0..7]

17,29

10K

GPIO12/IO_SMI#
IO_PME#
SIRQ
CLKRUN#
PCICLK

14.3M_SIO

19

CLK14

48
54
55
56
57
58
59
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

GPIO10
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO24
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47

12,25 CLK_14M_SIO

2
10K

C

1
R403
1
R404

2
10K
2
10K

51
52
64
18

+3VS

CB163

C395

1

1

53
65
93

2

2

4.7UF_10V_0805 0.1UF

C397
0.1UF

7
31
60
76

DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#

100
99
98
97
96
95
94
92

DTR#2
CTS#2
RTS#2
DSR#2
TXD2
RXD2
DCD#2
R I#2

DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#

89
88
87
86
85
84
91
90

DTRA#
CTSA#
RTSA#
DSRA#
TXDA
RXDA
DCDA#
RIA#

IRMODE/IRRX3
IRRX2
IRTX2

63
61
62

BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0

GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23/FDC_PP
VTR
VCC
VCC
VCC
VSS
VSS
VSS
VSS

DRVDEN1
GPIO11/SYSOPT

SMsC LPC47N227
B

JP17
DCD#1(1)
DSR#1 (6)
RXD1 (2)
RTS#1 (7)
TXD1 (3)
CTS#1 (8)
DTR#1 (4)
R I#1 (9)
(5)

LPTBUSY 31
LPTPE
31
LPTSLCT 31
LPTERR# 31
LPTACK# 31
LPTINIT# 31
LPTAFD# 31
LPTSTB# 31
LPTSLCTIN# 31

COM-DB9

RP96

1
R400

2
1K

CTS#2
DSR#2
DCD#2
R I#2

1
2
3
4

+3VS

SERIAL PORT

8
7
6
5

+5VALW

16
10
11
12
8
9
5
13
4
15
14
3
1
2
49

8P4R-4.7K_0804
C

1
R401

C390
0.1UF

2
1K

IRMODE
IRRX
IRTXOUT

28

IRRX

RDATA#
WDATA#
WGATE#
HDSEL#
FDD IR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#

C392
0.1UF

2
R405
1
R406

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
3MODE#

28
28
28
28
28
28
28
28
28
28
28
28
28

1
10K
2
1K

+5VS

1K

C394
0.47UF_0805 25V
DTRA#
RTSA#
TXDA
CTSA#
RIA#
RXDA
DCDA#
DSRA#
RIA1
29,33,38
RP95
DCDA#
RIA#
CTSA#
DSRA#

Base I/O Address
* 0 = 02Eh
1 = 04Eh

1
2
3
4

V-

TOUT1
TOUT2
TOUT3
RIN1
RIN2
RIN3
RIN4
RIN5
INVLD#

FORCEON
GND

22

27
C393
0.47UF_0805 25V

3

0.47UF_080525V

C2TIN1
TIN2
TIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUTB2

23

+3VS

C391
V+

C1C2+

2
14
13
12
19
18
17
16
15
20

SUSP#

9
10
11
4
5
6
7
8

DTR#1
RTS#1
TXD1
CTS#1
R I#1
RXD1
DCD#1
DSR#1

21
25

FORCEOFF#

8
7
6
5

U22
MAX3243
B

+3VALW

+3VALW

1

+3VS
R407
10K

2
10K

R408
10K
2

1
R409

C1+

24
1

R402

8P4R-4.7K_0804

CLKRUN#

1
6
2
7
3
8
4
9
5

2

17,23,29
SIRQ
23,26,29 PM_CLKRUN#
12
SIOPCLK

1
R399

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#

26

CLKRUN#
PCLK_SIO

50
17
30
28
29

2
10K

79
78
77
81
80
66
82
83
67

VCC

PCIRST#
LPCPD#

PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7

1

SIO_PCIRST#

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

2

LFRAME#
LDRQ#

26
27
1
R398

D

LAD0
LAD1
LAD2
LAD3

24
25

+3VS

8P4C-220PF
68
69
70
71
72
73
74
75

1

20
21
22
23

LFRAME#
LDRQ#0

17,29
17,29
29

LAD[0..3]

U21

1

LAD0
LAD1
LAD2
LAD3

LAD[0..3]

10K

1

D

LPD[0..7] 31

R549

R397

D34
23

2
R410

26

MODEM_RI#

D35

2 1

1

2
RB751V

1

C399
22PF

1

2 1

RING#

33

C398
1

29
R411

10

15PF

2
RB751V

PCLK_SIO

2

14.3M_SIO

1

PCM_RI#

RIA1

3

2
Q31
2N7002
A

A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
1

27

of

46

0.1UF

1

C406
0.1UF

+3VALW

27

MTR0#

27
27
27

F DDIR#
3MODE#
STEP#

27

WDATA#

27

WGATE#

27

TRACK0#

27

WP#

27

RDATA#

27

HDSEL#

DRV0#
DSKCHG#

MTR0#
F DDIR#
3MODE#
STEP#
FDD_DET#
WDATA#
WGATE#
TRACK0#
WP#
RDATA#
HDSEL#

INDEX#

RP97 +5VS

DRV0#

DSKCHG#
INDEX#
WP#
TRACK0#

DSKCHG#

1
2
3
4

8
7
6
5
8P4R-1K_0804

MTR0#
F DDIR#
3MODE#
STEP#
FDD_DET#
WDATA#

1
2
3
4
5
6
7
8
9
10

29 SCROLLED#
29
NUMLED#
29
CAPSLED#
34
51ON#
29,30
EC_ACT#
25

INT_MIC

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

11
12
13
14
15
16
17
18
19
20

USER_BTN0#
USER_BTN1#
USER_BTN2#
USER_BTN3#

USER_BTN3#

30
30
30
30
B

29

47K

Q48
E

2

LED1

10K

C
DTA114YKA

SW BD CONN

GND-MIC need around INT_MIC

WGATE#

+3VALW

JP20

2

DRV0#
DSKCHG#

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

GND-MIC

TRACK0#

R509
+3VALW

WP#

330
1

27
27

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

RDATA#

1

INDEX#

INDEX#

HDSEL#

R555

USER_BTN3#

2
R552

10K
USER_BTN3#
Place in Closest JP20
R415
1
2
GND-MIC 0

0.1UF

6
7
8
9
10

+5VS

5
4
3
2
1

STEP#
MTR0#
RDATA#
DRV0#

+5VS

GND
AGND

+3VALW +3VALW

R510
100K

1
2

4 IN 1 CONN

C409
0.1UF

+3VALW

+5VS

2

ON/OFFBTN#

2

51ON#

ON/OFFBTN# 29

3

51ON#

+3VALW

2 2

1 7
2 8
3 9
4 10
5 11
6 12

7
8
9
10
11
12

USB5_D+
USB5_DPCIRST#

CP6
KSO2
KSO4
KSO7
KSO8

4 in1 CONN

2

1
1000PF

22K
B

D54

1
2
3
4

8
7
6
5

8P4C-100PF
CP8

RLZ20A

KSO9
KSO0
KSO5
KSO1

E

1
2
3
4

8
7
6
5

8P4C-100PF

3

22K
DTC124EK

8
7
6
5

8P4C-100PF

2

C463

1
2
3
4

1

R492
0

1
2
3
4
5
6

8
7
6
5

CP9
KSO14
KSO11
KSO10
KSO15

34

1

2
1

2

1

1

Q46

C

1
2
3
4

8P4C-100PF

J7

4.7K
EC_ON

ON/OFFBTN#

DAN202U

R491

D

S

3

29

USB5_D+
USB5_DPCIRST#

18 USB5_D+
18 USB5_D15,16,21,22,23,24,26,29 PCIRST#

1

HCH SMT1-02

1

2

1

2

4

KSO6
KSO3
KSO12
KSO13

+5VS

1
100K
ON/OFF

CP7

100K

I D2
I D1

JP30
R490

1
D53

R511

2

+5VALW

3 SW3

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INT_KB

10P8R_1K

ON/OFF BUTTON

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1

WDATA#
WGATE#
HDSEL#
F DDIR#

C404

2

0.1UF

1

C403

ID 2
ID1

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
LEDLED+
1
0
I D2
I D1

Place in Closest JP20
R416
1
2
@0

1

2

1

RP98

29
29

2

ACES 85203-2602
+5VS

2

27

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

JP18

+3VS

JP19
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

KSO[0..15]
KSI[0..7]

KSO[0..15]
KSI[0..7]

3

2

+5VS

C405

29
29

1

+5VS

1

FDD CONN.

INT_KBD CONN.

SWITCH BOARD CONN.

+3VALW

2

+3VS

2
G
@2N7002
Q47

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

NEED CLOSEST JP18 ADD BY EMI REQUEST

LID SW
29,30 LID_SW#

LID_SW#

3

SW4

4

1

2
HORNG CHIH

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

SCHEMATIC, M/B LA-1341
Document Number

Rev
2A

401210
星期五, 十一月 15 , 2002

Sheet

28

of

46

0.1UF
ECA GND

C419

17,23,27 SIRQ
17,27 LDRQ#0
17,27 LFRAME#
17,27
LAD0
17,27
LAD1
17,27
LAD2
17,27
LAD3
12 EC_PCLK

1000PF

R427

+3VALW

2

2
R424 @0

CLK_LPC_EC

1

EC_RST#
R425
100K

+3VALW

1

P C7 2

Q33

100K

2N7002

3

17

For REV.A only

570SCI#

SCI#

28
28

5
6

KSI[0..7]
KS O[0..15]

KSI[0..7]
KSO[0..15]

ADB[0..7] 30

KB A[0..18]

31

G20
KBRST#

KBRST#

ADB[0 ..7]

7
8
9
15
14
13
10
18
19
22
23

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

1
R428
@10

RP99

PS2_DATA
PS2_CLK

1 2

KBD_DATA
KBD_CLK
EXT_DATA
EXT_CLK

1
2
3
4
5

+5VS

2

10
9
8
7
6

+5VS

2

C421
@15PF

10P8R_4.7K

+3VALW

+5VALW

RP100
G20
KBRST#
BT_OFF#
570SCI#

RP101

1
2
3
4

EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

8
7
6
5

1
2
3
4

8P4R-10K_0804

8
7
6
5

EC_TINIT#
EC_TCK
EC_TDO
EC _TDI
EC_TMS

8P4R-4.7K_0804
+3VALW
RP102
FSEL#
SELIO#
F RD#
EC_SMI#

1
2
3
4

KBD_CLK
KBD_DATA
EXT_CLK
EXT_DATA
PS2_CLK
PS2_DATA
LID_SW #

32
KBD_CLK
32
KBD_DATA
32
EXT_CLK
32
EXT_DATA
25
PS2_CLK
25
PS2_DATA
28,30
LID_SW #
25
MIC_MUTE

8
7
6
5
8P4R-10K_0804

2

DA0
DA1
DA2
DA3

DA output

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

PWM
or PORTA

Key matrix scan
PORTB

8,16,20 PCIRST-

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

138
139
140
141
144
145
146
147

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

IOPJ0/RD
IOPJ1/WR0

150
151

F RD#
F W R#

SELIO

152

SELIO#

IOPD4
IOPD5
IOPD6
IOPD7

41
42
54
55

PORTI

3

10K

2

2

7

C422

1

2
74LVC32

R545

2

0.1UF

62
63
69
70
75
76

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO

PORTD-2
PORTJ-2

SIO_PCIRST#
C R Y1
R441
1

RB751V

C R Y2

1
2

10PF

32.768KHZ
X6

R442

C424

1
120K

10PF

PORTL

SEL0
SEL1
CLK

20M_0603

2
2

C423

173
174
47

PC87591VPC

ECA GND

ADP_I

C420
@0.22UF_0603

*

B

C

ENV1

TRIS

0

0

0

OBD

0

1

0

DEV

1

0

0

PROG

1

1

0

SHBM=1: Enable shared memory with host BIOS
TRIS=1: While in IRE and OBD, float all the
signals for clip-on ISE use

SMB_EC_CK1 30,36
SMB_EC_DA1 30,36
PW RBTN_OUT# 17
EC_SMC2 3
EC_SMD2 3
FANSPEED1 3
EC_ACT# 28,30
EC_MUTE 25
PCI_PME# 21,22,23,26,30

10K

R429

10K

R430

KBA1

(ENV1)

KBA2

(BADDR0)

KBA3

(BADDR1)@10K

KBA5

(SHBM)

27
7,32

A C_IN 2

A C_IN

ON/OFFBTN# 28
SLP_S5# 17,32

2

R431

10K

R432

1

A C IN

34,37

RB751V
D36

PM_CLKRUN# 23,26,27

+3VALW

2
2
2

FREAD#
FW R#

30
30

SELIO#

30

R434

1

R436 10K
1
R438 10K
1
10K

BD_ID0

2

BD_ID1

2

BD_ID2

2

R435

1

3

R437 10K
1
R439 10K
1
10K

SCROLLED# 28
NUMLED# 28
CAPSLED# 28
LED1
28
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1

113
112
104
103
48

KBA16
KBA17
KBA18

JP23

FSTCHG

35

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10

@96212-1011S

EC_TINIT#
EC_TCK
EC_TDO
EC _TDI
EC_TMS
BD_ID0
BD_ID1
BD_ID2

+5VALW

Title

D

4

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341

Size
Document Number
C ustom

R ev
2A

401210

D ate:
A

ENV0
IRE

@2M_0603

17

143
142
135
134
130
129
121
120

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

FSEL#

FSEL#

1

1

+3VALW

R ING#
SLP_S3#

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD

11
12
20
21
85
86
91
92
97
98

30

AGND

27

2

PORTK
PORTM

96

D37

1

4

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

GND1
GND2
GND3
GND4
GND5
GND6
GND7

@0

BT_OFF#

148
149
155
156
3
4
27
28

17
35
46
122
159
167
137

1

R546

EC_PCIRST#

1

5

U11B
74LVC125
6
2

33
S YSON
27,33,38 SUSP#
39
VR_ON
26 W ireless_OFF#
8,17
RSM_RST
15
ENABLK
4
PROCHOT#
15
BKOFF#

2

4

1

0

EC_SMI#
MSEN#

17 EXTSMI#
14,30
MSEN#
25 HPLUG
17 SW I#
23 PCM_SUSP#
24
PCMRST#

I/O Address
Index
Data
BADDR1-0
2E
2F
0 0
4E
4F
0 1
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
1 0
Reserved
1 1

A C_IN

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

PORTJ-1
R440
1

P C7

124
125
126
127
128
131
132
133

U25A

1

EC_ACT#

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

14

24,26,28 PCIRST#

32KX2

EC_SMC_2
EC_SMD_2

LPCPD#

PORTH

32KX1/32KCLKOUT

BD_ID0
BD_ID1
BD_ID2
EC_SMC_1
EC_SMD_1
EC_PCIRST#

PORTE

PS2 interface

2 R426

ECA GND

INVT_PWM 15
BEEP#
25
LED2
25
ACOFF
35
PM_BATLOW# 17
EC_ON
28
LID_OUT# 17
EC_THERM# 17

2
44
24
25

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

*

DAC_BRIG 15
EN_FAN1 3
IR EF
35

IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46

110
111
114
115
116
117
118
119

0.01UF
2

BATT_TEMP 36

AD P_I

26
29
30

JTAG debug port

160

1
168
169
170
171
172
175
176
1

C417
1

LI/NIMH# 36
ID 1
28
ID 2
28

32
33
36
37
38
39
40
43

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

BATT_TEMP

BATT_OVP 35

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24/LRESET2

TINT
TCK
TDO
TDI
TMS

C R Y2

BATT_TEMP
AD P_I

PORTD-1

105
106
107
108
109

158

0_0603

99
100
101
102

153
154
162
163
164
165

PORTC

C R Y1

81
82
83
84
87
88
89
90
93
94

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL/LRESET2

+3VALW

3

1

161

95

34
45
123
136
157
166

AD Input

GA20/IOPB5
KBRST/IOPB6

71
72
73
74
77
78
79
80

R423

+RTCVCC

AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9

Host interface

IOPD3/ECSCI

K SI0
K SI1
K SI2
K SI3
K SI4
K SI5
K SI6
K SI7

CLK_LPC_EC

KBA[0..18] 30

SERIRQ
LDRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
LREST1
SMI
PWUREQ

E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1

C418

2

2
1

L32
1
2
BLM11A20

1

EC_AVCC

U24

VBAT

2

BLM11A20

0.1UF

AVCC

L31

1

C416

CB168
1UF_10V_0603

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

CB169

1000PF

4.7UF_10V_0805
+3VALW

D

EC _3VDD

2
0_0603

16

1
R422

VDD

+3VALW
+3VS

C415

1

0.1UF

2

0.1UF

2

4.7UF_10V_0805

C414

1

C413

2

CB167

1

1

+3VALW

C

EC_AVCC

1

B

2

A

¬P 期五, 十一月 15, 2002

Sheet
E

29

of

46

INPUT

OUTPUT

+3VALW

C425
1

0.1UF

2
+5VALW

C426

20

0.1UF

KBA2
74LVC244

+3VALW

8
7
6
5

EC_ACT#
MSEN#

SELIO#

EC_ACT# 28,29
LID_SW#
MSEN#

28,29
14,29

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

AA
LARST#

11
1

CLK
CLR

9

RP104
1
2
3
4

CC

U25C
74LVC32

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
8

10

R446

8P4R-20K_0804

+5VALW

U27

VCC

VCC

20
14

0.1UF C427
2
1

GND

1G
2G

2

+3VALW

7

SELIO#

1
19

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

18
16
14
12
9
7
5
3

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

1

FULL_LED# 25
POWER1_LED# 25
POWER2_LED# 25
CHARGING_LED# 25
LAN_DIS# 21
1
R445

2
@0

SBPME#

17

74HCT273

CB170
2

20K

2
5
6
9
12
15
16
19

GND

13

11
29

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

10

12

SELIO#

U25D
74LVC32

2
4
6
8
11
13
15
17

7

KBA1

USER_BTN0#
USER_BTN1#
USER_BTN2#
USER_BTN3#
PID0
PID1
PID2
PID3

10

14

28
28
28
28
15
15
15
15

1
U26

1

2
1UF_10V_0603

+3VALW
R52920K
AA

1

+3VALW
2
1

CC

1
R530

2
20K

2

R447
20K
PME_51#

21,22,23,26,29 PCM_PME#

PCI_PME# 21,22,23,26,29

21,22,23,26,29 MINI_PME#

21,22,23,26,29 LAN_PME#

21,22,23,26,29 1394_PME#

+3VALW

+5VALW
C430

+3VALW
1
1

C431
1
2

R450

14

1

2

U31

29,36 SMB_EC_CK1

SST39VF040

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

4

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11

1

3

FLASH#

6

17

29,36 SMB_EC_DA1
1

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

8
7
6
5

2N7002

5

VCC
WC
SCL
SDA

A0
A1
A2
GND

1
2
3
4

NM24C164

Q34
U25B
74LVC32

R451
1K

FWR#

29

R452
1K

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

R448
10K

+12VS

2
KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

2
0.1UF

100K

2

R449
20K

0.1UF
U32

+5VALW

1

1

2

2

1

10UF_10V_1206
CB171

KBA10

FREAD#

29

ADB7
ADB6
ADB5
ADB4
ADB3

FSEL#

29

2

KBA[0..18]
ADB [0..7]

KBA[0..18]
ADB[0..7]

7

29
29

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

SCHEMATIC, M/B LA-1341
Document Number

Rev
2A

401210
星期五, 十一月 15 , 2002

Sheet

30

of

46

A

B

C

D

E

Printer Port/USB

1
R456

POLYSWITCH_0.75A

470K_0603

C438
0.1UF

1

OC0#

150UF_10V_E

R458

18

C442
2

2

0.1UF

1

1

C440

F4

L40
2

FBM-11-451616-800T

2

2551A-04G2T

+5VALW

2

L46
FBM-11-451616-800T

1
1

1

L42
USB0_VCC
FBM-11-160808-121
USB0_D2
USB0_D+
2
L44
FBM-11-160808-121
CE14
+

R_USB0_DR_USB0_D+
USBGND0

1

1

1

1
2
3
4

VCC
DD+
GND

USB_0

2

JP26

USB0_D- 18
USB0_D+ 18

1

USB0_DUSB0_D+

1000PF

2

560K_0603

USB4_DUSB4_D+
+5VALW

USB4_D- 18
USB4_D+ 18

USB Port

18
18

USB_4

USB2_D+
USB2_D-

USB2_D+
USB2_D-

USB_2

+5VALW

FBM-11-451616-800T

1

1

150UF_10V_E

OC2#

0.1UF

0.1UF
R457
560K_0603

FBM-11-451616-800T

2

560K_0603

18

1

FBM-11-451616-800T

POLYSWITCH_0.75A
R455
470K_0603

C437

2

C441
2

2

+

L45
C439

0.1UF

2

FBM-11-451616-800T
CE13

2

2551A-04G2T

C434
2

USB2_VCC

L41 FBM-11-160808-121
USB2_D2
1
USB2_D+
2
1
L43 FBM-11-160808-121

1

R_USB2_DR_USB2_D+
USBGND2

2

2551A-04G2T

1
L38
150UF_10V_E

R454

1000PF

1
2
3
4

1000PF

2

2

C435

VCC
DD+
GND

F3

2

2

2
2

0.1UF

1

OC4#
1

18

VCC
DD+
GND

1

CE17
+

C433

1
2
3
4

1

1

470K_0603

L34 FBM-11-160808-121
R_USB4_D2
1
2
1 R_USB4_D+
USBGND4
FBM-11-160808-121
L35

USB4_VCC
USB4_DUSB4_D+

2

L39

2

1
R453

JP24

1

POLYSWITCH_0.75A

JP31

1

L33
1

F2

+5V_PRN
+5V_PRN

Parallel Port
D46

LPTINIT#

27

LPTSLCTIN#

1
R462

2
33

LPT_INIT#

2
33

SLCTIN#

27

LPTSTB# 1
R461

LPTSTB#

1
R463

LPTAFD#
27

2
33

LPTERR#

+5V_PRN
RP105
1
2
3
4
5

+5V_PRN

10
9
8
7
6

FD7
FD6
FD5
FD4

2
33
AFD/3M#

FD0
LPTERR#
FD1
LPT_INIT#
FD2
SLCTIN#
FD3
FD4
FD5
FD6

10P8R_2.7K
RP106
+5V_PRN
RP107
SLCTIN#
LPT_INIT#
LPTERR#
AFD/3M#

1
2
3
4
5

+5V_PRN

10
9
8
7
6
10P8R_2.7K

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPD3
LPD2
LPD1
LPD0
LPD7
LPD6
LPD5
LPD4

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

FD3
FD2
FD1
FD0
FD7
FD6
FD5
FD4

FD7
27

LPTACK#

27

LPTBUSY

27

LPTPE

27

LPTSLCT

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

16P8R_68

1

C443
0.1UF

2

27

1
R460

2

R459
1K

27

FD0
FD1
FD2
FD3

1w=10mils
RB420D

w=10mils

3

LPD[0..7]

LPD[0..7]

1

2

+5VS
27

JP27
LPTCN-25-SUYIN

3

CP10
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

AFD/3M#
LPTERR#
LPT_INIT#
SLCTIN#

1
2
3
4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

1
2
3
4

8
7
6
5

8P4C-220PF
CP11
8
7
6
5
8P4C-220PF
CP12

FD0
FD1
FD2
FD3

1
2
3
4

8
7
6
5

8P4C-220PF
CP13
FD4
FD5
FD6
FD7

1
2
3
4

8
7
6
5

8P4C-220PF
4

4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

B

C

D

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

31

of

46

12,39

VGATE

VR_POK

12,39

+3VS

R557

PFI

56K
R547

R550
11

4

PFO#

2

1

PW RGD

13

8,17

@2K
74HCT08
R471
4.7K

U20F
74LVC14

R470
@3.3K

12

14

1

13

U12D
12

2

14

8.2K

6

RST#

2

MR#

3

0

1

2

GND

1

1

U34
MAX6342

2

5
R469
+12VS

VCC

1

2

11

U20E
74LVC14
10

+3VALW

R476
10K

1

0

0

SLP_S5#

1

1

0

1

SLP_S3#

C451
L47
29
29

EXT_CLK

1
2
CB-1608D-800T
1
2
L48
KB_AS CB-1608D-800T

EXT_DATA
KB_VCC

F5
+5VS

W=40mils 1

EVERFUSE_1.1A

L49
CHB4516G750
4516

C453

29
29

KBD_DATA
KBD_CLK

4
2
1
3

CB173

C454
4.7UF_10V_0805

1000PF
220PF
L50
1
2
CB-1608D-800T
1
2
L51
CB-1608D-800T
0603

220PF

6
5

+5VS

+5VS

D52
DAN217
3

2

C456
2

C455
2
D51
DAN217
3

220PF

JP28
KBD/PS2_6

W=40mils

2

C452
2

1

1

1

1

1

0

0

2

1

PSON#

1

1

S3AUXSW#

+5VS

1

7,29

S5

2

17,29

SLP_S3#

S3

1

SLP_S5#

S1

2

PSON#
S3AUXSW#

2

1

7,29

PSON#

PS2 CONN.
1

D50
DAN217
3

2

17,29

+5VS
2

2

R475
10K

1

1

2
D49
DAN217
3

220PF

220PF

1

2
1

Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

SCHEMATIC, M/B LA-1341
Document Number

Rev
2A

401210
星期五, 十一月 15 , 2002

Sheet

32

of

46

A

B

+1.8VALW

+1.8VS

C

D

E

+1.8VALW to +1.8VS Transfer
C457

1

CB174

22UF_10V_1206

1

R479
470

0.1UF

1

2

CB175
10UF_10V_1206

Q37
1

RU NON
1

2

1

2

S
S
S
G

1

D
D
D
D

1
2
3
4

2

8
7
6
5

1

U35 SI4800

2N7002
SUSP
2

C458

+12VALW

1

3

2

0.1UF

2

R480
47K

SYSON#

29

SYSON

SYSON#
1

38

+2.5V to +2.5VS Transfer

Q38

2
3

2N7002
+2.5V

Power

direct provide

1
2

D

3

2

1

1.8VALW/+1.5VS

S

RU NON 2
G

CB176
1UF_10V_0603
2

Q39
+12VALW

1

SI2306DS

+12VALW TO +12VS
Transfer

CB177

+12VALW

R483
10K
2

1

+2.5VS

+12VALW

2

SUSP

R481

0.1UF

100K
2

1

1

3
Q42
NDS352P

2

3
R485
470

CB180

CB179

2N7002

1
C460

1

1 2

+12VS
Q40

2

1UF_25V_0805
3

2

2

2

0.1UF

22UF_10V_1206

0.01UF

2

3

RU NON
R486
1M_0603

2N7002

2

C461

SUSP

S

SUSP#

2

1

1

D

D
D
D
D

1

1

2

8
7
6
5

SI4800
S 1
S 2
S 3
G 4

Q41

2

27,29,38 SUSP#

51K

+5VS
U36

1

1

+5VALW

3

Q44

+5VALW
1

2N7002
2 SUSP
3

+5VALW
1

1

2
G
Q43
2N7002

VON
R482

R484
100K

CB178
1UF_25V_0805

3

2

+5VALW to +5VS Transfer
+12VALW

1

1

C459

2

1

1

1UF_10V_0603

CB181

CE15
100UF_D_16V

2

2

+
4.7UF_10V_0805

+3VALW

+3VS

+3VALW to +3VS Transfer

CB183
10UF_10V_1206

1

1

C462

R487
470

0.1UF

2

CB182

22UF_10V_1206

2

S
S
S
G

4

1

2

CE16
100UF_D_16V

2

+

2

4

D
D
D
D

1
2
3
4

1

1

8
7
6
5

1

U37 SI4800

Q45
2N7002
2

SUSP

Compal Electronics, Inc.

3

RU NON

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev
2A

401210
星期五, 十一 ?15, 2002

Sheet
E

33

of

46

A

B

C

D

Vin Detector

FBM-L18-453215-900LMA 90T_1812
1
2

P1

PCN1

High 18.784 17.901 17.077 V
Low 17.877 17.043 16.195 V

V IN

PL1

P1

1

1
1

1

3

1

PR1
1M_0402_1%
2

1

2
VS

VIN

VS

PC4
100PF_0402_50V
PC5
0.1UF_50V

2

PR3
84.5K_0402_1%

P ACIN

1

4

PR6
20K_0402_1%

1

-

PC7
0.01UF_0402_16V

PZD1
RLZ4.3B

VIN

2

VIN+

P ACIN

35

PR7
10K_0402

1

(3.3V)

2

B++

2

PR11
1K_1206

1

RTCVREF

1
PR9
10K_0402

PR10
1K_1206

1

29,37

2
2

PD2
IN4148

2

ACIN

2

2
1

2

2

2

PR8
1K_1206

+

2

PR4
1K_0402

1

2

PC6
1000PF_50V

3

PU1A
LM393M

1

1

1

D IN

PR5
22K_0402_1%
1
2

PR2
10K_0402

1

PC3
1000PF_50V

1

2DC-S315-B01

PC2
100PF_0402_50V

1

PC1
1000PF_50V

2

PD1
EC10QS04

2

2

8

3

VS
2

B++
PR13
10K_0402

2
2

2
1

D
PQ2
2N7002

PRG+_G

2

PR19
47K_0402
1

P ACIN

3

1

2
2

2
G
S

Precharge detector
16.6
15.9
15.2
13.48
12.93
12.09

100K

PC12
0.22UF_1206_25V

PC8
1000PF_50V

3

ON_G

2
PR21
22K_0402

2

1
PR17
215K_0402_1%

ACIN

PC11
0.1UF_50V

1

1
2

PR15
499K_0402_1%

PRG++

1

PR16
10K_0402

1

1

1

PRG+

3.3V
VS

2
1

6

2

1

2
VS+

1

1

2

5

-

RTCVREF

PR18
33_1206

PQ1
TP0610T
3
1

PR20
100K_0402

51ON#

PC9
1000PF_50V

2

1

PZD3
RLZ4.3B

28

1

V IN_L

PZD2
RLZ6.2C

2

CH GRTCP

2

+

(6.0V)

RB715F

VMB

7

2

1

ACON

1

P RG

3

35

3

PU1B
LM393M

P C10
0.01UF_0402_16V

PD3

1

2

36,37 MAINPWON

PD4
IN4148

PR14
499K_0402_1%

2

2

VIN

PD5
RB751V

1

1

PR12
1M_0402_1%
2
1

+5VALWP

2

PQ3
DTC115EUA

BAT ONLY

100K

(3.3V)

CH GRTCP

RTCVREF

6.310

PU2

1

2

PC14
10UF_1206_10V

2

CHGRTCP+

1

3

5.683
4

PC13
1UF_0805_25V

Compal Electronics, Inc.

PZD4
RLZ16B
Title

2

3

2
PR23
200_0805

1

1

6.101

PR22
200_0805

S-81233SG(SOT-23)

4

CHGRTC

3

Precharge detector
8.597
8.247
7.904

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Document Number

R ev

2A

401210

D ate: ¬P 期五, 十一月 15, 2002
A

B

C

Sheet
D

34

of

46

A

B

C

D

1

1

2

PL2
FBM-L18-453215-900LMA 90T_1812
1
2

1

PC15

2
1

4
1

1

2

1

24

OUTC2 GND

23

3

+INE2

CS

22

-INE2 VCC(o)

21

1

FB2

OUT

20

PC19
0.1UF_50V

VH

19

VCC

18

2

V IN

1

3
2
1

PR28
47K_0402

PC18
220PF_0402_50V

1

4
PQ7
FDS4435

2

100K

ACOFF

2

29
2

1

2
G

(1.73V)

PQ9
2N7002

2

PR37 10K_0402
7
1
2

PC24
2200PF_0402_25V

FB1

PC22
0.1UF_50V
VH 1
2
PC25
0.1UF_50V

1

2

FSTCHG 29

8

-INE1

RT

17

9

+INE1

-INE3

16

1

2

1

PC27
0.1UF_0402_16V

1

OUTC1

FB3

15

11

OUTD

CTL

14

CHARGE

12

-INC1

+INC1

13

PR41 10K_0402

2

2

PR43
100K_0402_1%

2

1

2

PC26 1500PF_50V
2

1

PR44
1K_0402

1

BATT+

2

PR40
0.02_2512_1%

PD8
EC10QS04
PR45
47K_0402

3

2

3

CC=0(0.5A) ~ 2.52A
CV=16.84V (8 CELLS)
PL3
22UH_SPC-1205P-220A
1
2

PD7
1SS355

1

10

PR42 47K_0402
1
2

1

PR39
162K_0402_1%

1

29 IREF

2

2

PR38 68K_0402

1

PQ8
DTC115EKA

P C29
4.7UF_1210_25V
2
1

1

L_5

P C28
10UF_1210_25V
2
1

PC23
0.1UF_0402_16V

VREF

3

6

100K

5
6
7
8

PC21
4700PF_0402_25V

(5.0V)

1
2

IREF=1.31*Icharge
IREF=0.73 ~ 3.3V

PR36 10K_0402
5
2

2

LXCHRG

2

2

PC20
0.1UF_0402_16V

1

1

1

PR34
24K_0402_1%
PR35
11K_0402_1%

2

ACON

2

2

4

1

S

1

34

D

PR31
0_0402

+INC2

-INC2

2

L_1T

PACIN

3

34

L_2

PR27
10K_0402

2

L_3

ACY25
12.7K

L_4

2

AC OFF#
PR29
0_0402

2

1
PR32
10K_0402
2
1

2

PR33
10K_0402
1
2

0.1UF_50V

1

1

PU3
MB3878

2

PD6
1SS355

1

8
7
6
5

L_1
PR30
150K_0402

AC OFF#

4.7UF_1210_25V

PC17

4

4

2

10UF_1210_25V

PC16

1
2
3

PR26
200K_0402

2

PR25
10K_0402

PQ6
SI4835DY

1

8
7
6
5

2

1
2
3

1

1
2
3

PR24
0.02_2512_1%

1

1

B+

PQ5
SI4835DY

8
7
6
5

B++

1

PQ4
SI4835DY
V IN

Iadp=0~3.5A

P3

2

P2

L_6

1

VMB
PR48
604K_0402_1%
PC30
0.1UF_50V

8 CELL(4S2P)
: 2.0V

CHARGE 36

1
2
2

7,10

SDREF

PU4B
LM358A

PR51
@0_0402

7
1
PC34
0.01UF_50V

PR54
200K_0402_1%

6

L_9

PR52
@100K_0402_0.5%

PC31
@0.1UF_0402_16V
4

S DREF_L

2

2

2.2K_0402

PC32
@0.1UF_0402_16V

5

-

2

1

1
PR53

4

+

2

-

PR50
@100K_0402_0.5%

(1.25V)

1

3

2

+

4

1

1

1

+2.5VP

L_8

29 BATT_OVP

8

PU4A
LM358A

2

2

PR47
143K_0402_1%

PR49
1M_0402_1%

(BAT_OVP voltage = 0.110865 *VMB)

PC33
0.1UF_0402_16V

(4.2V)

1

VMB : 18.0V--> BATT_OVP

1

PR46
47.5K_0402_1%

L_7

OVP voltage : LI-MH

2

2

VS

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:
A

B

C

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

R ev

2A

401210
¬P 期五, 十一月 15, 2002

Sheet
D

35

of

46

A

B

PJP1
3MM

1

+5VALWP

PJP2
2MM

2

+5VALW

1

1

2

+12VALW

1

+2.5VP

PJP5
2MM

2

+3VALW

+1.8VALWP

D

PJP3
4MM

+12VALWP

PJP4
3MM
+3VALWP

C

2

+2.5V

PH1 under CPU botten side :
CPU thermal protection at 90(91)+-3 degree C
Recovery at 50(51)+-3 degree C

PJP6
3MM

1

+1.8VALW

2

1

+1.25VP

2

+1.25VS

1

1

CHARGE

PC119
0.1UF_0402_16V

VS

47K_0402_1%
PR59
10K_0402

PR58
3.65K_0402_1%

PR60
1K_0402_1%

3

1

-

4

L_10T

PR62
18.2K_0402_1%

1

OTP

2

PQ10
DTC115EKA

100K

100K

1SS355

2

PR64
470K_0402

PR65
249K_0402_1%

1

PC40
0.1UF_0402_16V

2

PC39
1000PF_50V

PC38
0.1UF_0402_16V

2

2

PU5A
LM393M

PR63
@1K_0402_1%

2

OTP_C

3

LI/NIMH# 29
PR61
@1K_0402_1%

PD9

+

2

1

2

*

PC36
0.1UF_50V

PC35
0.1UF_50V
PR57

rev

1

PR56
@100K_0402_1%

1
2

PR55
100K_0402_1%

L_10

2

1

+3VALWP

8

BATT+
PL4
FBM-L18-453215-900LMA 90T_1812
1

PC37
1000PF_50V

PTH1
10K_1%

CPU

VMB

35

RTCVREF

PZD5
RLZ3.6B

PR66
1K_0402

1

BATT_TEMP

2

PD10
@BAS40-04
ID
A B/I
TS
EEPROMVCC

1

PH2 near main Battery CONN :
BAT. thermal protection at 85(86)+-3 degree C
Recovery at 50(51) degree C

2
+3VALWP

CPU_ON
PC41
0.1UF_0402_16V

1
1

SMB_EC_DA1 29,30

2

PTH2
10K_1%

BATTERY

VS

1

2

*

3

PR70
100_0402

+

6

-

PR75
19.1K_0402_1%

7

OTP_B

2

3

1

PU5B
LM393M
PR76
470K_0402

4

1

5

OTP

2

PC42
0.1UF_0402_16V

rev

100K

PD13
1SS355

PC43
0.1UF_0402_16V

2
PQ12
DTC115EKA

100K

100K

PZD6
RLZ3.6B

3

PD12
@BAS40-04

PR73
10K_0402

1

L_11T

2

PR74
1K_0402_1%

8

+3VALWP

1

PQ11
DTC115EKA
100K
2

47K_0402_1%

4

PR71
3.65K_0402_1%

3

PR72

L_11

SMB_EC_CK1 29,30

34,37

PD11
@BAS40-04

PR69
100_0402

MAINPWON

2

3

RTCVREF

*

39

PR68
25.5K_0402_1%

1

SUYIN_25037A-08G1-C
3

3

VMB

2

PCN2

1
2
3
4
5
6
7
8

BATT_TEMP 29

1

PR67
1K_0402

4

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Document Number

R ev

D ate: ¬P 期五, 十一月 15, 2002
A

B

C

2A

401210
Sheet
D

36

of

46

A

B

C

D

E

PC44
2.2UF_1206_25V
1
2

2

1

2

1
2

PC54
10UF_1210_25V

1

PC53
0.1UF_50V

1

1

1
PR84
2M_0402

PR85
0.012_2512_1%
2

2.5VREF

CSH5

PC62
4.7UF_1206_10V

1

VL

1

PR91
10K_0402_1%

2

3

PR95
0_0402

PR93
47K_0402

+5V Ipeak = 6.66A ~ 10A

2

PR94
47K_0402

1

2

1
2

1

2

+

VL

1

VS
3

PD17
EP10QY03

2

2

FB5_L

PR92
@0_0402
2

2

PR89
10.5K_0402_1%

2

1

8

PC66
33PF_0402_50V

+

PC64
47UF_D_6.3V_PC

+5VALWP
1

RUN/ON3

2

L_15

2

VL

V+

DL5
BST51+

PC65
680PF_50V

2

2
1

PR90
10K_0402_1%

4
5
18
16
17
19
20
14
13
12
15
9
6
11

TIME/ON5

2

PR88
@300K_0402

LX5
12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

1

28

FB3_L

MAX1632

PC58
47PF_0402_50V

PC63
150UF_D_6.3V_FP

7

CSH3
CSL3
FB3
SKIP#
SHDN#

PR81
0_0402

1

2

PR86
10K_0402

PU6

8

PQ14
FDS6982S

1

1
2
3
10
23
1

ACIN

LX3
DL3

D H5

2

S2

1

1
2

PC61
33PF_0402_50V

1

29,34

26
24

7
G2

1

2

1

2
2
1

PD16
EP10QY03

PR87
3.57K_0402_1%

1
+

2

PC60
150UF_D_6.3V_FP
2
1

PC59
150UF_D_6.3V_FP
2
1

+

CSH3

DH3

6

D2
2

21

22

2

1

PR83
1M_0402

PR82
0.012_2512_1%

+3VALWP

BST3

27

S1

3

L_BT5

25

5
G1

1

GND

2

L_BT3

2

PR80
0_0402

D1
4

2

PC55
0.1UF_50V
2
1

PC57
47PF_0402_50V

L_13

2

1

1

2

+3.3V Ipeak = 6.66A ~ 10A

PL5
SLF12565T_100M

PC52
2200PF_50V

+12VALWP

PC56
4.7UF_1210_25V

PR79
10_1206

1

L_14

1

2

1

G2
S2

8

PT1
SDT-1205P-100

B++

1

DL3

D2
7

PC50
0.1UF_50V
1
2

VL

2

2

PD29
1SS355

PC51
4.7UF_1206_10V

LX3

PR78
0_0402
2

L_12

3

1

1

S1

6

D H3

2

4

1

1
2

PC49
10UF_1210_25V

PC48
2200PF_50V

1

PC47
0.1UF_50V

2

PQ13
FDS6982S
D1
1G

2

2

FLYBACK

3

1

VS

5

1

PD14
EC11FS2

4

SNB

PR77
22_1206
2

1

BST51

3

B++

DAP202U
PD15
BST31

2

2

1

PC45
470PF_50V
1
2

PC46
0.1UF_50V

1

1

12VDD

MAINPWON

PC67
0.047UF_50V

2

2

1

1

MAINPWON 34,36

PC68
0.047UF_50V

4

4

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

B

C

D

SCHEMATIC, M/B LA-1341
Document Number

R ev

2A

401210
星期五, 十一 ?15, 2002

Sheet
E

37

of

46

A

B

C

D

D

S

+5VALWP

6
5
2
1

4

PQ15
@SI3445DV

3

G

(+2.5V +-5%)
PL6
4.7UH SPC-1205P-4R7A

+2.5VP

D

1

1
1

PC69
470PF_0402_50V

1
2
2

2

2

PC70
220UF_D_4V_FP

1
PC73
@0.1UF_50V

+2.5VP
2.5VREF

1

PR102
10_0805

2

LA2_G

1

2

2

PR103
0_0402

16

2

PVDD2

15

VL2

14

PGND1

PGND2

13

5

AGND1

AGND2

12

6

SD

VFB

11

7

VIN/2

VCCQ

10

PVDD1

+1.25VP
PL7
5UH-SPC-06704

PC78
4.7UF_1206_16V

3

PU8

VL1

CM8500IT

2

3

100K

VCC2

2

4

LX1.25

+2.5VP

1

SD

2

D

3

-

2

1
2

PC82
0.1UF_0402_16V

2

1
PR106
1K_0402

3

3

Layout : "Compensation network close to FB pin"

1

1

PQ20 100K
DTC115EUA

+

2

LB2

1

PC84
150UF_D_4V_FP

2

2.5VREF

1

PR111
100K_0402_1%

1
PC87
4700PF_0402_25V

*

4

100K

PR153
261K_0402_1%

2

SYSON#

100K

Compal Electronics, Inc.

PQ24
@DTC115EKA

3

2

6

9

2

LB3

1
5

-

PC118
470PF_0402_50V

2

1

+

2

+

AGND

PC81
1000PF_50V

PC117
@0.1UF_50V

4
PU12B
LM393M
7

AGSEN

1

PR104
100K_0402
1

1
2

PR107
191K_0402_1%

1
4

2

27,29,33
100K

8

+2.5VP

+

8

2

PU12A
LM393M
1

LB1

2

2

2
3

VL
PC116
0.1UF_0402_16V

3
PQ23
2SA1036K

1
2

1
PR109
1K_0402

PD23
EC31QS04

PR108
10K_0402

2

L_17

1

2

3

1
1

2
1
2

PQ22
HMBT2222A

1

PC86
2200PF_0402_25V

PR152
@2M

G

PD22
RB751V

SUSP#

1

S

PC85
4.7UF_1206_16V

P C83
1000PF_50V
2
1

PL8
5UH-SPC-06704
1
2

LX1.8

6
5
2
1

4

+1.8VALWP

2

+3VALWP

1

(+1.8V+-5%)
PQ21
SI3445DV

1

PD21
@EP10QY03
PC79
4.7UF_1206_16V

2

PR105
100K_0402

3

2

P C80
220UF_D_4V_FP

2

1

PQ19
DTC115EUA

VCC1

SYSON#

1

100K

1
1

33
SYSON#

2

6

1

-

PC76
0.1UF_0402_16V
PR154
@47K

PD20
@EP10QY03

2

5

2

+

1

PU7B
LM393M
7
2

1.5VCC

1

VL

1

PC75
4700PF_0402_25V

1

2

4

2

2

PR101
47K_0402
1
2

LA2

1

LA3

P C77
0.1UF_0402_16V

2

1

3

-

1

+

2

3

PU7A
LM393M
1

LA1

2

+

8

2

PC74
0.1UF_0402_16V

2

*

3

PD19
EC31QS04

PR97
191K_0402_1%

VL

2

2

2

PR98
10K_0402

1

2
PR99
1K_0402

PR96
@2M

L_16

1

1

PQ16
SI3445DV

3

1
1

2

P C71
10UF_1210_25V
2
1

1

PQ18
2SA1036K

1

G

PQ17
HMBT2222A

PC72
2200PF_0402_25V

2

1

S

PD18
RB751V

LX2.5

6
5
2
1

4

1

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1341
Document Number

R ev

D ate: ¬P 期五, 十一月 15, 2002
A

B

C

2A

401210
Sheet
D

38

of

46

A

B

C

D

E

F

G

H

+5VALWP
CPU_B+

L_21

+5VALWP

1

100K_0402
1

3

CPU_VID0

PR121 2

100K_0402
1

12,32 VGATE
PR126
150K_0402_1%

PR122

10K_0402
2

CPU_ON

PR124

DH

23

D2

BST

26

24

D1

DL

16

25

D0

V+

1

VCC

9

CPUVCC

FB

4

CPUFB

14

1

3

120K_0402

2

VGATE
TIME
SDN/SKIP

PC115
@100UF_EC_25V
2
1

5

1

1

POS

L_20

28

3
2
1

PL10
SCR-1205-0R5

VTT1LX

2.2_1%
2
PQ27
SI4362DY

L_27
PC91 0.1UF_50V

CM+

2

+CPU_CORE

1

PR115

PQ28
SI4362DY

L_22

CPU_B+

13

3
2
1

2
1
PR117
1

PD25
EC31QS04

+CPU_CORE

0.002_2512_1%

4
PC93
0.1UF_50V

POS

PD26
EC31QS04

PR118
68_0805

4

PR123
2.8K_0402_1%

+5VALWP

PC92
220PF_50V

3
2
1

+3VALWP

CM+
+CPU_CORE

1

100K_0402
1

PR120 2

PR156
0_0402_5%

2

PR119 2

CPU_VID1

PR155
499_0603_1%
1

2

2
1
- 4
PU13
MAX4322EUK-T_SOT23-5
PR157
1K_0603_1%

1

CPU_VID2

3

D3

22

+ 3

1

2

3

100K_0402
1

2

1

PR116 2

*

27

LX

2

CPU_VID3

MAX1718

D4

5
6
7
8

CPU_ON

3

PU9
21

1

PR158
1K_0603_1%

3
2
1

36

0_0402
1

+

4

PD24
1SS355
1

PR114
2

4

+

2
2

1

PR113
20_0805
CPU_VID4

PQ26
IR7811A

2

CPUVDD

3

PQ25
IR7811A

PC114
@100UF_EC_25V
2
1

PC90
4.7UF_1210_25V

5
6
7
8

PC88
10UF_1210_25V

PR112
0_0402

PC120
0.1UF

CPU_B+

2

PC89
4.7UF_1210_25V

5
6
7
8

PL9
FBM-L18-453215-900LMA 90T_1812

5
6
7
8

B++

OVP

SUS

11

REF

S1

8

12

ILIM

S0

7

+2VREF

GND
L_18

10

1
PC98
1000PF_50V

PR130
68K_0402_1%

2
PR125
100_0402

D
+5VALWP

D

12,17

3

S

5
6
7
8

PQ34
IR7811A

1

D

CPU_B+
PQ33
IR7811A

PQ29
2N7002
2
G

17

S

PR131
100K_0402
2

PM_GMUXSEL

PQ32
2N7002

4

S

L_25
1

PR138
20K_0402_1%

PU10MAX1887

4

L_31

5

L_32

PR144
200_0402

PC108
4700PF_0402_25V

6

LX

CS-

DH

CS+

VDD

COMP

DL

3
2
1

PQ37
SI4362DY

15
L_28
PC103
0.1UF_50V

14
13

11

PR145
2.2_1%

L_23

12

CPUVDD

2

1

PQ38
SI4362DY

*

2

8

GND

PGND

3

PR140
100K_0402
PD27
EC31QS04

CPU_B+

4
2

PR142
68_0805

4

1 PD28
1SS355

PC104
10UF_1210_25V

PC105
4.7UF_1210_25V

9

PR146
200_0402

PC109
1UF_0805_25V

PC107
220PF_50V

PR147
0_0402

+1.2VPP
1
2

PC110
4.7UF_1206_16V

VR_ON

1000PF_50V
7

VR_ON

8
PR150
0_0402

4

STPCPU#

DPRSLPVR

1

1

0

PM D-S

1

0

0

BM

0

1

0

BM D-S

0

0

0

Deeper

X

0

1

A

B

VCORE'
1.30V
1.20V
1.0V

Offset

VCORE

0%

1.30V

4.62%

1.239V

2.0%

1.176V

4.62%

1.144V
C

DELAY

SENSE

ERROR

CNOISE

ON/OFF#

GND

5
6
1
3

SI91822DH-12-T1

PR149
@10K_0402_1%
PC113
0.1UF_0402_16V

4

Compal Electronics, Inc.
Title

SCHEMATIC, M/B LA-1341

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
Document Number
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 十一 ?15, 2002

R ev

2A

401210

1.0V

0%

VOUT

1

29

PC112

VIN

2

2

CPU_ON

+1.2VPP
PC111
4.7UF_1206_16V

PR148
0_0402

PU11
4

GMUXSEL

3

L_LG

+3VALWP

PM

PC106
4.7UF_1210_25V

10
3
2
1

1

1

16

3
2
1

7

CM-

S

1

L_30

BST

+CPU_CORE
+CPU_CORE

2

2

CM+

PR139
0.002_2512_1%
1

1.2VDD

1

3

V+

2

PQ36
2N7002
2
G

2

1

L_29

LIMIT

TRIG

CS+

1

3

PR143
200_0402
2

ILIM

2

2

5
6
7
8

1
PC102
4700PF_0402_25V

PL11
SCR-1205-0R5

VTT2LX

5
6
7
8

1

L_24

L_19

PR141
200_0402
2

3
2
1

D
L_26

PC101
0.1UF_0402_16V

PQ35
2N7002
2
G

3

4

D
PR151
100K_0402

3

PC100
470PF_0402_50V

PM_STPCPU#

2
G
S

PR137
1K_0402_1%

D

PR133
100K_0402

PQ31
2N7002
2
G

1

PR135
33K_0402_1%

PC99
1000PF_50V

5
6
7
8

PR134
53.6K_0402_1%

PR136
48.7K_0402_1%

PQ30
2N7002
2
G

S

PM_DPRSLPVR 17

*

*

TON

18

PR127
100K

PR129
49.9K_0402_1%

1

20

15

PC94
4.7UF_1206_16V

5
19

PM_DPRSLPVR

*

PR132
100K_0402_1%

ZMODE

1

2

NEG

CC

3

+2VREF

VDD

1

PC97
1UF_0805_25V

6

3

PC95
47PF_0402_50V

PC96
1UF_0805_25V

PM_DPRSLPVR

17
PR128
180K_0402_1%

D

E

F

G

Sheet

39
H

of

46

5

4

3

2

Power ON sequence

1

Power Off sequence

ACIN
ON/OFFBTN#
EC_ON

D

D

51ON#
+3VALW / +5VALW
/+12VALW / +1.8VALW
RSM_RST
PWRBTN_OUT#

94mS(min)

SYSON
+2.5V
PS_ON#

C

Below are Power On and Resume sequence
Power off / Suspend
C

63mS~94mS

Power off

S3AUXSW#

Suspend

SLP_S3# / SLP_S5#
SUSP#/LAN_DIS#/PCM_SUSP#
+3VS/+5VS/+12VS
+1.8VS/+2.5VS/+1.25VS

10mS(max)
Power off / Suspend
1mS(max)

VR_ON
+1.2VPP
B

B

50mS(max)

CPU_ON
CPU_CORE
VGATE

6mS(max)

CLOCK

30nS(min)

100mS (min)

PWRGD

Power off / Suspend
5mS~15mS

PCIRST#

5mS~15mS

CPUPWRGD

2mS~9mS

CPURST#
A

A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

Rev

2A

401210
星期五, 十一月 15, 2002

Sheet
1

40

of

46

5

4

3

2

1

POWER SOURCE BLOCK DIAGRAM
SUSP

+12VS

Q42
NDS352

D

+12VALW

+12VALW

SUSP
PU8
CM8500

SYSON
AC_IN

C

D

+1.25VS

+2.5V

PU7

JP4_JP5_DDR_SODIMM

U5_NB_SIS650 JP4_JP5_DDR_SODIMM

C

LM393

SUSP

+2.5VS

Q39

U7_DDR_CLOCK_BUFFER

NDS352
PU6

+5VALW

MAX1632

+5VALW

SUSP

U36
SI4800

+5VS

U37

+3VS

AC
+3VALW
B

B+
BATTERY

SUSP

U2_MAX1617 JP9_JP10_HDD_CDROM

U5_NB_SIS650 U10_SB_SIS961 U21_SIO_47N227
U6_CLOCK_GEN. U8_LVDS_TVOUT U16_1394_VIA6306
B

SI4800

VR_ON
+3VALW

PU11

SI91822DH-12-T1

+1.2VPP
U1_CPU

CPU_ON

PU12
LM393

+3VALW

PU9/PU10

MAX1718

+CPU_CORE
U1_CPU
U5_NB_SIS650
U10_SB_SIS961

MAX1887

A

SUSP

U35
SI4800

U5_NB_SIS650 U10_SB_SIS961 U24_EC_87591
U40_PCMCIA_ENE1420 U16_1394_VIA6306 U13_LAN_RTL8100B

+1.8VALW

U5_NB_SIS650 U10_SB_SIS961

+1.8VS

U5_NB_SIS650 U10_SB_SIS961
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

2

A

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

Rev
2A

401210
星期五, 十一月 15, 2002

Sheet
1

41

of

46

5

4

3

ACY25 RESET
+3VS/+2.5VS
VGATE

D

1

MAP DIAGRAM
+3VALW/+1.8VALW/+2.5V
+3VS/+1.8VS/+CPU_CORE

CLOCK

POWER FAIL

2

+CPU_CORE/+1.2VP
D

RSM_RST
PWRGD

DELAY

CPURST#

NB

CPU

CPUPWRGD

+3VS

+3VS

S3AUXSW#

PCIRST-

SIO
EC

+5VS
GPO

+3VALW/+1.8VALW
+3VS/+1.8VS/+CPU_CORE

IDE

AND

BUF

+3VALW/+3VS/+5VS
SUSP#

+5VALW

C

DC/DC

+1.25VS
RSM_RST

SYSON

SB

MINI
PCI

PCIRST#

+3VALW/+3VS

PSON#

DC/DC

+2.5V

C

DDR

1394
PWRBTN_OUT#
+3VALW
LAN_DIS#

LAN
+3VALW

PCM_SUSP#
ON/OFFBTN#

PCMCIA
+3VS

EC_ON
B

B

LVDS
RSM_RST#
ON/OFF

51ON#
BUTTON

DC/DC

+3VALW

EC

VR_ON
+1.2VP

CPUON

CPU_CORE

LAN_DIS#

VGATE
+CPU_CORE

PCM_SUSP#
+12VALW
+3VALW/+5VALW/+1.8VALW

SUSP#
SUSP

+1.2VP
+3VS/+5VS/+1.8VS/+12VS

A

A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

Rev
2A

401210
星期五, 十一月 15, 2002

Sheet
1

42

of

46

5

4

3

2

1

Power PIR
Item
1

Fixed Issue

Reason for change

Page

NO

Improve CPU_CORE voltage regulator. 39

Modify item

MB_Ver. Phase

0.3

C test

2
D

D

3
4
5
6
7

8
C

C

9
10
11

12
13
B

B

14
15
16
17
18

A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

4

3

A

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

Rev

2A

401210
¬P期五, 十一月 15, 2002
2

Sheet

43

of
1

46

5

4

UNIT
1394

U16

IDSEL

IRQ

AD16

PIRQC#

MINIPCI JP16

AD31

PIRQB#

3

GNT
GNT#0

2

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

REQ
REQ#0

GNT#1

REQ#1

D

D

LAN

U13

AD17

PIRQB#

CARDBUS U40

AD20

PIRQA/B#

GNT#3

REQ#3

GNT#2

REQ#2

SMBUS from EC
EC_SMD2,EC_SMC2 : U2 (MAX1617) AD : 1001 110
SMB_EC_CK1,SMB_EC_DA1: U31( EEPROM ) , PCN2 (BATT CONN)

C

SMBUS from SIS961
SMBCLK , SMBDAT: JP5 , JP4 , CLK GEN ( U6 ) , CLK BUF( U7 ).

C

ACY25 A-TEST Modify
Change to 310LV : Add R64,R73,R76. Del R77,R78,Q49,Q50,R539
Add DPSLP# : Add Q49 ,R551
DPRSLPVR : Change to pull Low =Del R536 Add R284 ; Add U41 ,R554.
B

AUXOK : Del CB112

B

IDERST# : Add D56 , R548
LAN : VDD2.5 add L27,C294,C297,C299
1394 : +3VA change to +3VS power , R351,R352,R353,R3354 change to 54.9_1% , R355
change to 5.1K_1% , C337 change to .33UF , C338 change to 270PF
KB : Add R552 to disconnect ON/OFF
PSON# : Connect to SLP_S5# directly. Del U33
A

S3AUXSW# : Connect to SLP_S3# directly

A

PWRGD : Add R550 transfer 5V to 3V
+2.5V : Q39 using SI2306 to transfer +2.5VS

Title

SCHEMATIC, M/B LA-1341
Size
B

H_DPSLP# : Add Q49 , R551 to connect with PM_STPCPU#

Date:
5

4

Compal Electronics, Inc.

3

2

Document Number

Rev
2A

401210
星期五, 十一月 15, 2002

Sheet
1

44

of

46

5

4

3

2

1

CDLED# : Add R553 to disconnect with JP10
USER_BTN3# : Add R552 to disconnect with JP18,R555

pull high to +3VALW

D

D

DDR termination : RP32~RP57 , R494~R508

chanage to 33 ohm

PWRGD : Del C42 , C256
SUSP# : R487 change to 75 ohm
FOR C TEST
LED1 : Q48 PIN3 CHANGE TO +3VALW
FWDSDCLKO : Add pull high resistor R556
C

PWRGD : Add pass through resistor R557

C

CRTVDD : R170,R171 change from 2.2K to 1K
GPIO19,20 : Add pull high resistor R566,R567 , del R269
EC_ON : Del Q47. R492 change to 0 ohm
EN_FAN1 : Add U42 , C483 , C484 , R561 ,R562
CLKFS2 :Del R161 ,
B

Add R565

AUXOK : Del D18 , R254

B

For MP
+5VFAN1 : Add D58 for reserve
S1_RST# ,S2_OE# , S2_RST# , S2_OE# :Add R568,R569,R570,R571 for reserve
LAN_DIS# : Del R333 , add D57 for reserve
MINI PCI : Change to REQ#4 & GNT#4

A

For MP 5/3
R248 change to 47K , R251 change to 15K

A

For MP 6/6

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

R278 change from 0 to 47 ohm
5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341
Document Number

Rev
2A

401210
星期五, 十一月 15, 2002

Sheet
1

45

of

46

5

4

3

2

1

D

D

C

C

B

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Compal Electronics, Inc.
SCHEMATIC, M/B LA-1341

Size
B
Date:
5

4

3

2

Document Number

Rev
2A

401210
星期五, 十一月 15, 2002

Sheet
1

46

of

46

A

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Producer                        : Acrobat Distiller 5.0 (Windows)
Create Date                     : 2002:11:15 06:50:26Z
Modify Date                     : 2014:09:04 23:21:57+03:00
Metadata Date                   : 2014:09:04 23:21:57+03:00
Format                          : application/pdf
Title                           : Compal LA-1341 - Schematics. www.s-manuals.com.
Creator                         : 
Subject                         : Compal LA-1341 - Schematics. www.s-manuals.com.
Document ID                     : uuid:bc0eff25-65ca-4a70-b4ef-84fc4e402270
Instance ID                     : uuid:ae2eb385-e395-4ca6-b9f0-a21fbbbbd06e
Has XFA                         : No
Page Count                      : 46
Keywords                        : Compal, LA-1341, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

EXIF Metadata provided by EXIF.tools