Compal LA 1711 Schematics. Www.s Manuals.com. Rx00 G Schematics

User Manual: Motherboard Compal LA-1711 - Schematics. Free.

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5

4

3

2

1

D

D

Prescott & Springdale Schematic with Capture CIS
and Function field
C

C

uFCPGA Prescott
2003-03-14
REV: X00-G

Cature library ball out check document
Prescott : Prescott processor Electrial,Mechanical and
Thermal Specification Rev0.5 [Check by HW:Henry,Steve]
B

B

Springdale(GMCH): Springdale GMCH External Design
Specification (EDS) REV1.0 [Check by HW: Henry,Rita]

ICH5: N/A

@ : Depop Component
1@ : Depop on Nimitz(Inspiron)
2@ : Depop on Beijing(Precision)
A

A

Compal Electronics, Inc.
Title

Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
D ate:

Document Number

R ev
X00-G

LA-1711

Tuesday, March 18, 2003

Sheet
1

1

of

54

5

4

3

2

Compal confidential

1

Block Diagram
Prescott

D

ADT7460 Thermal sensor

D

478 uFCPGA CPU

page 19

page 7,8,9

System Bus

HA#( 3..31)

HD#(0..63)

533/667MHz

VGA
Board

AGP CONN.

page 14

2.5V
266/333MHz

Channel A SO-DIMM
BANK 0, 1, 2,3 page 15

Springdale
GMCH

AGP4X/8X(1.5V)

932 FC-BGA

page 18

[CRT CONN. & TV-OUT]

Fan Control

Memory
BUS(DDR)

Clock Generator

Channel B SO-DIMM

page
10,11,12,13

BANK 0, 1, 2,3 page 16

CK409

2.5V
266/333MHz

page 6

C

C

HUB Link
DC IN

1.5V
66Mhz
266MB/S

MINI PCI

page 41

page 32

IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)

B

LAN
B CM5705M

page 29

MDC
page 27

3.3V ATA100

460 BGA

ATA100
Page
20,21,22

CardBus Controller

AC97
Codec
STAC9750

ATA100

page 42

3.3V/5V
page 43

1.5V/+VTT_GMCH

page 24

PCI7510

page 28

Transformer

ICH5

3.3V 33MHz

BATT
IN

AC-LINK

3.3V 24.576MHz

PCI BUS

HDD

page 30

1394, Smart
card

B

page 44

CDROM
USB
FDDpage 23

LPC BUS

Slot 0

3.3V 33MHz

page31

1.25V/2.5V

AMP& Phone
Jack

page 21
USB

page 45

page 25

VCORE

page31

RJ45

USBPORT 0

Macallen

X BUS

page 29

LPC to X-BUS
& Super I/O

USB2.0

Page
33,34

SST39VF080

BACK

page 47

USBPORT 1

VCORE_CTRL

BT
USBPORT 2

page 46

BACK
USBPORT 3
DOG
page 26

page 35

USBPORT 4

CHARGER

MOD

page 27

A

Touch Pad
page 35

USBPORT 6

Int.KBD

A

page 48

BACK

page 35

Compal Electronics, Inc.
Title

Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

2

of

54

5

4

3

2

1

PM TABLE
power
plane

+3VALW

+3VSUS

+5VALW

+5VSUS

Configuration List

+3VRUN
+5VRUN
+1.5VRUN

+2.5V_MEM

BOM Structure

+VCC_CORE

State

+12V

D

+VCCVID

S0

ON

ON

ON

S1

ON

ON

ON

S3

ON

ON

OFF

S5 S4/AC

ON

OFF

OFF

OFF

OFF

OFF

S5 S4/AC don't exist

D

Function

V_1P25V_DDR_VTT

PCI TABLE
C

C

PIRQ

IDSEL

REQ#/GNT#

CARD BUS

AD17

1

D,C

LAN

AD16

4

C

MINI PCI

AD19

3

PCI DEVICE

D,B(NP)
A,B(NP)

VGA

B

B

Note : "@" means all model depop

USB

"1@" means Nimitz depoped only

TABLE

"2@" means Beijing depoped only
USB PORT#

DESTINATION
Model

BACK

0
1

BT

2

BACK

3

DOG

4

MOD

5

Reserved

6

BACK

7

Reserved

Nimitz

Beijing

Smart Card

YES

YES

LAN

10/100
(4401)

1000
(5705M)

Dog House

YES

YES

Function

A

A

Compal Electronics, Inc.
Title

Index and Config.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

3

of

54

5

4

3

2

1

RBAT
D

+RTCSRC

ADAPTER

+RTC_PWR

+5VALW

+5VSUS

+3.3VRTC

+3VALW

+3VSUS

D

PWR_SRC

SUSPWROK

BATTERY
DOCK _PWR_SRC

C

C

+5VSUS

+3VSRC

+2.5VMEMP

+VCCP

+VCC_CORE

+12V

B

B

+5VHDD

+5VMOD

+5VRUN +1.5VRUN

VDDA

+3VRUN V3P3LAN

+3VSUS

+2.5V_MEM

V_1P25V_DDR_VTT

A

A

Compal Electronics, Inc.
Title

Power Rail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

4

of

54

5

4

3

2

+3VRUN

ICH_SMBCLK
D

1

CK_SCLK

7002

ICH5

+3VSUS

ICH_SMBDATA

CLK GEN.

CK_SDATA

D

7002

V_3P3_LAN
DIMM0

LAN_SMBCLK

DIMM1

7002

7002

NIC

LAN_SMBDATA
7002

CLK_SMB

+3VALW

7002

7002

DAT_SMB

MPCI
7002

C

C

24C05

ADT7460

AD7414

PCA9561

DH PORT
EC SMBus Address

SIO

CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)
DDR Temp.(AD7414ART-0) : 90h/91h (P.15)
CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)

Macallen

EC EEPROM(FM24C05U) : A0h/A1h/A2h/A3h (P.37)

SBAT_SMBCLK

VID Select(PCA9561PW) : 9Ch/9Dh (P.38)

+5VALW
VGA

SBAT_SMBDAT
B

B

PBAT_SMBCLK
PBAT_SMBDAT

1'nd
BATTERY

+5VALW

CHARGER

A

A

Compal Electronics, Inc.
Title

SMBUS TOPOLOGY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

5

of

54

5

4

3

2

1

+ 3VRUN

1

1

+ 3VRUN

1K_0603_1%~D
2

1K_0603_1%~D
2

R518

D

CLKSEL0

R215
2

@ 0_0402_5%~D
1

R206
2
R508
2

0_0402_5%~D
1
0_0402_5%~D
1

R509
2

@ 0_0402_5%~D
1

1

R519

2K_0603_1%~D

2K_0603_1%~D

C204
10U_1206_6.3V7K~D

CPU_CLKSEL1 <8>

2

1

1

2

1

C586
0.1U_0402_10V6K~D

2

1

C587
0.1U_0402_10V6K~D

CK_XTAL_IN and CK_XTAL_OUT equal length traces,
Please place R_J between Pins 4,5 of CK409 Pins
before X'tal

MCH_CLKSEL0 <10>

1

2

2

1

C554
0.1U_0402_10V6K~D

2

C552
0.1U_0402_10V6K~D

1

2

1

C551
0.1U_0402_10V6K~D

2

D

C588
0.1U_0402_10V6K~D

C553

1

C 193
4.7U_0805_6.3V6K~D

0.1U_0402_10V6K~D
2

1

U 39

C597
@ 10P_0402_50V8J~D
2
1

1
2

CK_XTAL_IN

4

REF_1
REF_0

3V66[0..3]

REF0

REF1 SRC

USB/Dot

0

0

100

66

14.3

14.3

100/200

0

MID

REF

REF

REF

REF

REF

1

200

66

14.3

14.3

100/200

48

1

0

133

66

14.3

14.3

100/200

48

1

1

166

66

14.3

14.3

100/200

48

Hi-Z

Hi-Z

Hi-Z

Hi-Z

R548
@ 2M_0603_5%~D

14.31818MHz_20P_1BX14318CC1A~D
CK_XTAL_OUT

5

Hi-Z

<21> ICH_SLP_S1#
<36> CLK_STP_CPU#

Hi-Z

<37> CK_VTT_PG#

CLKSEL0
CLKSEL1

+ 3VRUN

51
56

ICH_SLP_S1#
H_STP_PCI#
CLK_STP_CPU#

21
49
50

CK_VTT_PG#

35

CK_SCLK
CK_SD ATA

R479
1

XTAL_OUT

CPU_CLKC2
CPUCLKT1

Place crystal within
500 mils of CK409

Place near CK409

28
30

2

CPUCLKC1
PWRDWN#
PCI_STP#
CPU_STP#

CPUCLKT0

1
R 192
1K_0603_1%~D

CPUCLKC0
SCLK
SDATA

48/66MHZ_OUT/3V66_4

CK_SATA#

37

SRCLKN_100MHZ

2

66MHZ_OUT0/3V66_0

R484

49.9_0402_1%~D

CK_SATA

1
2
33_0402_5%~D

<21> CK_100M_ICH

H_STP_PCI#

66MHZ_OUT2/3V66_2
66MHZ_OUT1/3V66_1

R478
1

38

SRCLKP_100MHZ

PCICLK_F2
PCICLK_F1

1

+ 3VRUN

<20> CK_48M_ICH

2 R501
33_0402_5%~D

1

CLK48M_OUT0

31

<30> CK_48M_SCR

2 R500
33_0402_5%~D

1

CLK48M_OUT1

32

USB_48MHZ

PCICLK_F0

DOT_48MHZ
PCICLK6

R 218
@ 1K_0603_1%~D

R199
1

2

52

2

Check SPEC (250mA,300 ohm)

PCICLK5
IREF
PCICLK4

475_0603_1%~D
L45
BLM11A601S_0603~D
1
2
1

10U_1206_6.3V7K~D

1

2

VDD_PLL

PCICLK2
PCICLK1

C550
0.1U_0402_16V4Z~D

54

VSS_PLL

6
11
17
25
33

2

C166

55

VSS_SRC
VSS_IREF

+3VRUN

PCICLK3
CLK_VDD_PLL

39
53

ICH_SLP_S1#

VSS_REF
VSS_PCI
VSS_PCI
VSS_3V66
VSS_48

B

C K_CPU2

1

46

C K_CPU2#

1

44

C K_CPU1

1

43

C K_CPU1#

1

41

C K_CPU0

1

VTT_PWRGD#

66MHZ_OUT3/3V66_3

R485
1
2
33_0402_5%~D

47

CK409

SEL0
SEL1

49.9_0402_1%~D
<21> CK_100M_ICH#

2

CPUCLKT2

R_J

REF

0

MID

C598
@ 10P_0402_50V8J~D
2
1

48

X6

45

2

CPU

1

SL1

2

SL0

VSS_CPU

XTAL_IN

1

C LKREF1
C LKREF0

42
48

<34> CK_14M_SIO

VDD_CPU
VDD_CPU

1

2 R539
33_0402_5%~D

34
36

2 R538
33_0402_5%~D

VDD_48
VDD_SRC

<21> CK_14M_ICH

3
10
16
24

2.49K_0603_1%~D

VDD_REF
VDD_PCI
VDD_PCI
VDD_3V66

2.49K_0603_1%~D
2

R208

2

R214

Close to X'tal pin

1

C585
0.1U_0402_10V6K~D

1

1

MCH_CLKSEL1 <10>

C

2

1

Bring Up: Populate R509 (Because CPU
is Northwood-MT, Frequency 533MHz)

2

R530

Trace wide=20 mils

2

CPU_CLKSEL0 <8>

1

1

CLKSEL1

2

Place near each pin
W>40 mil

CK_VDD_MAIN

L17
BLM21PG600SN1D_0805~D

R529

PCICLK0

40

C K_CPU0#

1

R488 2
33_0402_5%~D
R472 2
1
49.9_0402_1%~D
R473 2
1
49.9_0402_1%~D
R489 2
33_0402_5%~D
R490 2
33_0402_5%~D
R474 2
1
49.9_0402_1%~D
R475 2
1
49.9_0402_1%~D
R491 2
33_0402_5%~D
R492 2
33_0402_5%~D
R476 2
1
49.9_0402_1%~D
R 477
1
2
49.9_0402_1%~D
R493 2
33_0402_5%~D

CK_BCLK

CK_BCLK <7>

CK_BCLK#

CK_BCLK# <7>

CK_ITP

C

CK_ITP <8>

CK_ITP#

CK_ITP# <8>

C K_HCLK

C K_HCLK <10>

Place near CK409
C K_HCLK#

CK_HCLK# <10>

29
CLK66M_OUT3

1

R543 2
33_0402_5%~D

23

CLK66M_OUT1

1

22

CLK66M_OUT0

1

9

PCICLK_F2

1

R547 2
33_0402_5%~D
R546 2
33_0402_5%~D
R540 2
33_0402_5%~D

20

PCICLK6

1

19

PCICLK5

1

14

PCICLK2

1

13

PCICLK1

1

12

PCICLK0

1

R541 2
33_0402_5%~D
R544 2
33_0402_5%~D
2

R587

33_0402_5%~D

27

CK_66M_AGP <18>

26
CK_66M_MCH <12>
CK_66M_ICH <20>
CK_33M_ICHPCI <20>

8
7

R545 2
33_0402_5%~D
R542 2
33_0402_5%~D

CK_33M_MINIPCI <32>

B

CK_33M_CBPCI <30>

18
15
CK_33M_LANPCI <28>
CK_33M_SIOPCI <34>
CK_33M_CPLD <36>

CY28409ZCT_TSSOP56~D

1

R524

1

+ 3VRUN

1

ICH_SMBCLK

1

D

ICH_SM BDATA

2

3
Q68
2N7002_SOT23~D

CK_SD ATA

2
G

<15,16,21,32> ICH_SMBDATA

R536
100K_0402_5%~D

S

2

100K_0402_5%~D

2
G

+ 3VRUN
Q69
3 2N7002_SOT23~D

A

CK_SCLK

S

<15,16,21,32> ICH_SMBCLK

D

A

D
1
G 2

3

Compal Electronics, Inc.

S
Title

Clock Generator

2N7002
5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

6

of

54

5

4

3

2

1

+ VCC_CORE

<10> H_A#[3..31]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1

C

<10> H_REQ#[0..4]

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<10> H _ADS#

R339
@ 62_0402_5%
1
2
2

AP#0
AP#1
BINIT#
IERR#

200_0402_5%
H6
D2
G2
G4

<10> H _BR0#
<10> H_BPRI#
<10> H _ BNR#
<10> H_LOCK#
<6> CK_BCLK
<6> CK_BCLK#

CK_BCLK
CK_BCLK#

AF22
AF23

F3
E3
E2

BCLK0
BCLK1

HIT#
HITM#
DEFER#

B

AMP_3-1565030-1_Prescott~D

H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

<10> H_HIT#
<10> H_HITM#
<10> H _ DEFER#

BR0#
BPRI#
BNR#
LOCK#

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74

1

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#

BOOTSELECT

R371

AC1
V5
AA3
AC3

Prescott

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

H _D#0
H _D#1
H _D#2
H _D#3
H _D#4
H _D#5
H _D#6
H _D#7
H _D#8
H _D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] <10>

C

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12

+ VCC_CORE

H _ IERR#

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

AD1

+ VCC_CORE

J1
K5
J4
J3
H3
G1

D

A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10

J C P UA

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73

D

B

+VCC_CORE

VCORE_BOOTSELECT <46>

Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6

TESTHI11

B6

FERR#

Comment

Prescott
Pin name

Comment
Pull-up 62ohm
to +VCC_CORE

Pull-up 200ohm
to +VCC_CORE

TESTHI11

Pull-up 62ohm
to +VCC_CORE

FERR#/PBE# Pull-up 62ohm
to +VCC_CORE

Northwood MT
Pin name

Comment
Connect to PLD
CPUPREF through
0ohm

G HI

Northwood

Prescott

Northwood
MT

P op

P op

P op

P op

P op

P op

FERR#
Pull-up 62ohm
to +VCC_CORE

AA20

ITPCLKOUT0 Pull-up56ohm
to +VCC_CORE

TESTHI6

Pull-up 62ohm
to +VCC_CORE

ITPCLKOUT0

Pull-up56ohm
to +VCC_CORE

P op

P op

P op

AB22

ITPCLKOUT1 Pull-up 56ohm
to +VCC_CORE

TESTHI7

Pull-up 62ohm
to +VCC_CORE

ITPCLKOUT1

Pull-up 56ohm
to +VCC_CORE

P op

P op

P op

NC

VIDPWRGD

Pull-up 2.43K ohm
to +VCCVID

NC

Depop

P op

Depop

Pull-up1Kohm to
+3VRUN & connect
to PWRIC
Connect to +VCCVID

NC

Depop

P op

Depop

Depop

P op

Depop

P op

Depop

P op

A D2
A D3

NC

float
float

VID5

A

A F3

NC

float

VCCVIDLB

float
Note: AD2,AD3 pop(bring up)
float
A

float

NC

AD20

VCCA

Connect to CPU
Filter

VCCIOPLL

Connect to CPU
Filter

VCCA

Connect to CPU
Filter

AF23

VCCIOPLL

Connect to CPU
Filter

VCCA

Connect to CPU
Filter

VCCIOPLL

Connect to CPU
Filter

AE26

V SS

Connect to GND

OPTIMIZED/ float
COMPAT#

V SS

Connect to GND

AD25

TESTHI12

Pull-up 200ohm
to +VCC_CORE

TESTHI12

Pull-up 62ohm
to +VCC_CORE

Connect to PLD
through 0ohm

DPSLP

Compal Electronics, Inc.
P op

P op

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P op

Prescott Processor in uFCPGA478
Size
C
Date:

5

4

3

2

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

7

of

54

5

4

3

2

1

+VCC_CORE

+ VCC_CORE

R 71

AD20
AE23

H _ VCCA
1
+

1
L41

C 368
33U_D2_8M_R35~D

2

2

<46> V CCSENSE
<46> VSSSENSE
1
+ VCCVID
R333
H_VSSA

2
@ 0_0402_5%~D

AD22

R_D

10U_LQH31MN100K01_100mA_10%_1206~D

CK_ITP_CPU
CK_ITP_CPU#

AC26
AD26

Pop: Prescott
Depop: Northwood
1
R 97
61.9_0603_1%

AF26

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

TCK
TDI
TDO
TMS
TRST#

ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3

VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB

DBR#
PROCHOT#
MCERR#
SLP#

VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1

R349
61.9_0603_1%
2

2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2
R 82

1

2 62_0402_5%

H_T ESTHI8
H_T ESTHI9
H_T ESTHI10
H_T ESTHI11
H_DPSLP#
H_TESTHI12

R354
R350
R347
R382
R 79

1
1
1
1
1

2
2
2
2
2

NC1
NC2
NC3
NC4
NC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

<10>
<10>
<10>
<10>

F21
J23
P23
W23

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

<10>
<10>
<10>
<10>

L5
R5

H_ADSTB#0 <10>
H_ADSTB#1 <10>

E21
G25
P26
V21

H _DINV#0
H _DINV#1
H _DINV#2
H _DINV#3

AE25

ITP_DBRESET#

C3
V6
AB26

H_PROCHOT#

+3VSUS

RE
Pop: Prescott
Depop: Northwood

0.1U_0402_16V4Z~D
6

<36>
<36>
<36>
<36>
<36>
<36>

H _V ID_PWRGD

R361
150_0402_5%~D
H_RESET# 1
2

+ VCC_CORE
R377
@ 47_0402_5%~D
2
1
R108
1
2
R379

I TP_TCK
ITP_TMS

R364
47_0402_5%~D
I TP_TDO 1
2

150_0402_5%~D
I TP_TDI
2
1

1
R370

I TP_TCK

@47_0402_5%~D

+ VCC_CORE

Close to the CPU

1

2
27.4_0603_1%~D
2

R376
39.2_0603_1%~D

CK_ITP_JITP
CK_I TP_JITP#
I TP_TCK
ITP_TRST#
ITP_TMS
I TP_TDI

5

29

P

GND6

O

4

VCORE_ENLL <46>
C121

G

I

Level shift

SN74LVC2G07DBVR_SOT23-6~D

1

2

V ID3
V ID2
V ID1
V ID0

5
6
7
8

4
3
2
1
RN7

GTL Reference Voltage

1K_8P4R_1206_5%~D

Layout note :

0.1U_0402_16V4Z~D

+CPU_GMCH_GTLREF

V ID4

1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils

+ VCC_CORE

2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GMCH_GTLREF trace
wide 12mils(min),Space
15mils

B_VID5
O PEN

B_VID4
O PEN

B_VID3
O PEN

B_VID2
OP EN

B_VID1
O PEN

B_VID0
O PEN

R357

R_A

+CPU_GTLREF

200_0603_1%~D
2

R356

R_B

169_0603_1%

2

1

1

R 340
0_0603_5%~D
C369
0.1U_0402_16V4Z~D

1

A

2

C372
220P_0402_50V8J~D

@

@

@

@

@

@

@ MOLEX_52435-2891_28P~D

R381
680_0603_5%~D
1
2

30

A

I TP_BPM#5

3

V ID3
V ID2
V ID1
V ID0

2

I TP_BPM#4

<36,46> V ID4

1K_0402_5%~D
2
1K_0402_5%~D
2

1

I TP_BPM#3

<36,46> V ID5

<36,46>
<36,46>
<36,46>
<36,46>

R 37
1
R 35
1

V ID5

2

I TP_BPM#2

+3VRUN

10K_0402_5%~D
2
+3VSUS

1

I TP_BPM#1

VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI

R155
1

U 6B

2

I TP_BPM#0

28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

ITP_DBRESET#

Close to the ITP

JITP

2

+VCC_CORE
R363
54.9_0603_1%~D
I TP_TDO
1
2
R358
54.9_0603_1%~D
H_RESET#
1
2

+3VSUS

1

SN74LVC2G07DBVR_SOT23-6~D

H _VID0
H _VID1
H _VID2
H _VID3
H _VID4
H _VID5

GND7

C 386
0.1U_0603_25V7M~D

2

G

O

2

U 6A

I

2

1

<46> VI D _PWRGD

B

H _V ID_PWRGD

2

1

1

10K_0402_5%~D
+VCC_CORE

2 62_0402_5%

1

R336
2.43K_0603_1%
1
2

2

CK_I TP_JITP#
CK_ITP_JITP

<10>
<10>
<10>
<10>

+ VCC_CORE

1

1
2

@ 0_4P2R_0404_5%~D

C

H_PROCHOT# <10>

R 83

1

4
3

C 131
2
5

CK_ITP#
CK_ITP

1

P

<6> CK_ITP#
<6> CK_ITP

CPLD Enable
Pop R380

ITP_DBRESET# <37>

1

R152
+3VSUS

R N8

C P UPREF# <36>

+ VCCVID
+ VCCVID

CK_ITP_CPU
CK_ITP_CPU#

0_4P2R_0404_5%~D

B

0_0402_5%~D

H_CPUSLP# <36>

A22
A7
AF25
AF24
AE21

AMP_3-1565030-1_Prescott~D
1
2

RH
Pop: Prescott
Depop: Northwood MT

2

E22
K22
R22
W22

R_E

R N9
CK_ITP
4
CK_ITP# 3

R_H

62_0402_5%
62_0402_5%
62_0402_5%
62_0402_5%
62_0402_5%
@

R 380 1

Prescott

THERMTRIP#

1

L24
P1

2

PLL Layout note :

A5
A4
AF3

H_T ESTHI2_7

2

10U_LQH31MN100K01_100mA_10%_1206~D
2

2 62_0402_5%
2 62_0402_5%

2

D4
C1
D5
F7
E6

1
1

1

L40
1

I TP_TCK
I TP_TDI
I TP_TDO
ITP_TMS
ITP_TRST#

+VCC_CORE

R 77
R344

1

+ VCC_CORE

AC6
AB5
AC4
Y6
AA5
AB4

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

0_0402_5%~D
2

H_T ESTHI0
H_T ESTHI1

2

10uH, DC current of 100mA parts
and close to cap

I TP_BPM#0
I TP_BPM#1
I TP_BPM#2
I TP_BPM#3
I TP_BPM#4
I TP_BPM#5

THERMDA
THERMDC

R 70
1

AE26

2

62_0402_5%
62_0402_5%
62_0402_5%
62_0402_5%
62_0402_5%
62_0402_5%

DBSY#
DRDY#
BSEL0
BSEL1

R_G

1

2
2
2
2
2
2

LINT0
LINT1
INIT#
RESET#

Pop: Northwood
Depop: Prescott

AA21
AA6
F20
F6

1

1
1
1
1
1
1

A2

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12

D

2

H_THERMTRIP#

<21,37> H_THERMTRIP#

OPTIMIZED/COMPAT#

0_0402_5%~D
2 H_DPSLP#

+CPU_GTLREF

2

+ VCC_CORE

B3
C4

GTLREF0
GTLREF1
GTLREF2
GTLREF3

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#

J26
K25
K26
L25

1

H_THER MDA
H_THERM DC

DP#0
DP#1
DP#2
DP#3

1

H5
H2
AD6
AD5

H _D B SY#
H _D R D Y#
CPU_CLKSEL0
CPU_CLKSEL1

<19> H_THERMDA
<19> H_THERMDC

R 338
R 341
R 337
R 346
R 343
R 342

D1
E5
W5
AB25

H_RESET#

RS#0
RS#1
RS#2
RSP#
TRDY#

2

H _P WRGOOD

<21> H_INTR
<21> H_NMI
<21> H_INIT#
<10> H_RESET#
<10>
<10>
<6>
<6>

C6
B6
B2
B5
AB23
Y4

H _ FERR#

R 78
1

<36> DPSLP#

2

<21> H_A20M#
<21> H _ FERR#
<21> H _IGNNE#
<21> H_SMI#
<21> H _P WRGOOD
<36> H_STPCLK#

0_0402_5%~D

VCCVID

<10> H _ TRDY#

C

CPLD Enable
Pop R76, R78

R 76
200_0402_5%

@ P AD

2

AF4

F1
G5
F4
AB2
J6

VIDPWRGD

H_RS#0
H_RS#1
H_RS#2

AD2

1

VID0
VID1
VID2
VID3
VID4
VID5

<10> H_RS#[0..2]

@ 62_0402_5%
2 H_RESET#

AE5
AE4
AE3
AE2
AE1
AD3

300_0402_5%~D
2 H _P WRGOOD

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128

R 87
1
R 84

VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181

D

Place near CPU

130_0402_5%
2 H_PROCHOT#

SKTOCC#

AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5

J C P UB
R 111
1

T1

1

1

62_0402_5%
2 H_THERMTRIP#

1

62_0402_5%
2 H _ FERR#

R129
1

1

Place near ICH

R131
1

Close to the ITP

Compal Electronics, Inc.

ITP_TRST#
Title

Between the CPU and ITP

Prescott Processor in uFCPGA478
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

8

of

54

5

4

3

2

1

Place 11 North of Socket(Stuff 6)
+VCC_CORE

1

1
C 31
22U_1210_10V6K~D

2

1
C 27
22U_1210_10V6K~D

2

2

1
C 28
22U_1210_10V6K~D

2

1
C 29
22U_1210_10V6K~D

2

1
C 32
22U_1210_10V6K~D

1
C 30
22U_1210_10V6K~D

2

2

1
C 37
@22U_1210_10V6K~D

2

1
C 39
@ 22U_1210_10V6K~D

2

1
C 35
@ 22U_1210_10V6K~D

2

1
C331
@ 22U_1210_10V6K~D

2

C 36
@ 22U_1210_10V6K~D

D

D

22uF depop reference
Springdale Chipset Platform Design Guide Rev1.11(12474)

Place 12 Inside Socket(Stuff all)
+VCC_CORE

1

1
C 46
22U_1210_10V6K~D

2

1
C 56
22U_1210_10V6K~D

2

2

1
C 55
22U_1210_10V6K~D

2

1
C 45
22U_1210_10V6K~D

2

1
C394
22U_1210_10V6K~D

2

1
C403
22U_1210_10V6K~D

2

1
C 404
22U_1210_10V6K~D

2

1
C412
22U_1210_10V6K~D

2

1
C395
22U_1210_10V6K~D

2

C382
22U_1210_10V6K~D

+VCC_CORE

1

1
C381
22U_1210_10V6K~D

2

C 411
22U_1210_10V6K~D

2

C

C

Place 9 South of Socket(Unstuff all)
+VCC_CORE

1

2

1
C 76
@ 22U_1210_10V6K~D

2

1
C 71
@ 22U_1210_10V6K~D

2

1
C 72
@ 22U_1210_10V6K~D

2

1
C 75
@ 22U_1210_10V6K~D

2

1
C 69
@ 22U_1210_10V6K~D

2

1
C 70
@ 22U_1210_10V6K~D

2

1
C 77
@ 22U_1210_10V6K~D

2

1
C 73
@ 22U_1210_10V6K~D

2

C 74
@ 22U_1210_10V6K~D

B

B

470uF _ERS10m ohm* 15,

ESR=0.5m ohm

+ VCC_CORE

1

1

+

+

C 303
470U_D4_2.5V_R10M~D

2

1
+

C302
470U_D4_2.5V_R10M~D

2

1
C304
470U_D4_2.5V_R10M~D

2

+

1
C301
470U_D4_2.5V_R10M~D

2

+

1
C300
470U_D4_2.5V_R10M~D

2

+

C 305
470U_D4_2.5V_R10M~D

2

+ VCC_CORE

1

1

+

+

C 299
470U_D4_2.5V_R10M~D

2

1
+

C294
470U_D4_2.5V_R10M~D

2

1
C298
470U_D4_2.5V_R10M~D

2

+

1
C296
470U_D4_2.5V_R10M~D

2

+
2

1
C295
470U_D4_2.5V_R10M~D

+

C 297
470U_D4_2.5V_R10M~D

2

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239

+VCC_CORE

A

A

1
+

1
C 68
470U_D4_2.5V_R10M~D

2

+
2

1
C423
470U_D4_2.5V_R10M~D

+

Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

C422
470U_D4_2.5V_R10M~D

2

Compal Electronics, Inc.
Title

CPU Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

9

of

54

4

<8> H_ADSTB#0
<8> H_ADSTB#1
C

B7
C7

<6> C K_HCLK
<6> CK_HCLK#
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>

B19
C19
C17
L19
K19
L17
G9
F9
L14
D12
E12
C15

H_DSTBP#0
H_DSTBN#0
H _DINV#0
H_DSTBP#1
H_DSTBN#1
H _DINV#1
H_DSTBP#2
H_DSTBN#2
H _DINV#2
H_DSTBP#3
H_DSTBN#3
H _DINV#3

<7> H_ADS#
<8> H _ TRDY#
<8> H _D R D Y#
<7> H _DEFER#
<7> H_HITM#
<7> H_HIT#
<7> H_LOCK#
<7> H_BR0#
<7> H _ BNR#
<7> H_BPRI#
<8> H _D BSY#

<8> H_RS#[0..2]

H_RS#0
H_RS#1
H_RS#2

<8> H_RESET#
<21,37> PW RGD_3V
H D RCOMP
H D _ SWING

+GMCH_GTLREF

F27
D24
G24
L21
E23
K21
E25
B24
B28
B26
E27
G22
C27
B27
E8
AE14
E24
C25
F23

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HADSTB0#
HADSTB1#
HCLKP
HCLKN
HDSTBP0#
HDSTBN0#
DINV0#
HDSTBP1#
HDSTBN1#
DINV1#
HDSTBP2#
HDSTBN2#
DINV2#
HDSTBP3#
HDSTBN3#
DINV3#
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS0#
RS1#
RS2#
CPURST#
PWROK#

PROCHOT#
BSEL0
BSEL1

H _D#0
H _D#1
H _D#2
H _D#3
H _D#4
H _D#5
H _D#6
H _D#7
H _D#8
H _D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

L20

H_PROCHOT#

L13
L12

AR32
AR29
AR27
AR25
AR23
AR20
AR16
AR13
AR11
AR9
AN32
AN30
AN28
AN26
AN24
AN22
AN20
AN18
AN16
AN14
AN12
AN10
AM35
AM29
AM27
AM25
AM23
AM21
AM19
AM17
AM15
AM13
AM11
AM9
AL32
AL1
AK28
AK26
AK24
AK22
AK20
AK18
AK16
AK14
AK12
AK10
AK8
AK3
AJ35
AJ32
AJ9
AJ4
AJ1
AH33
AH30
AH24
AH22
AH20
AH18
AH16
AH14
AH12
AH10
AH6
AH3
AG35
AG32
AG28
AG26
AG24
AG22
AG20
AG18
AG16
AG14
AG8
AG4
AF33
AF30
AF25
AF24
AF22
AF20
AF18
AF16
AF14
AF11
AF9
AF6
AF3
AE35
AE32
AE26
AE25
AE13
AE12

+ 3VRUN

1

B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8

R 90
330_0402_5%
2

B29
J23
L22
C29
J21
B30
D28

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

H_PROCHOT_SIO# <34>
1

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

3

D26
D30
L23
E29
B32
K23
C30
C31
J25
B31
E30
B33
J24
F25
D34
C32
F28
C34
J27
G27
F29
E28
H27
K24
E32
F31
G30
J26
G26

FSB

<7> H_REQ#[0..4]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

Q24
2

R 91

56_0402_5%~D
2
+VCC_CORE

1

MMBT3904_SOT23~D
H_PROCHOT#

H_PROCHOT# <8>

MCH_CLKSEL0 <6>
MCH_CLKSEL1 <6>

HDRCOMP
HDSWING
HDVREF
RG828SDGES_FCBGA932_SPRINGDALE~D

B

+VTT_GMCH

Follow Intel design guide R1.11(12474) page80

1

GTL Reference Voltage
R331
301_0402_1%~D

Layout note :
1. +GMCH_GTLREF Trace wide
12mils(min),Space 15mils.

H D _ SWING

+CPU_GMCH_GTLREF

1

1
R332
102_0402_1%~D

2

+VTT_GMCH

2. Place decoupling cap 220PF near GMCH.

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U 3G

AE11
AE10
AE4
AE1
AD33
AD30
AD28
AD10
AD9
AD8
AD6
AD3
AC35
AC32
AC4
AC1
AB33
AB30
AB28
AB27
AB26
AB10
AB9
AB8
AB6
AB3
AA32
AA4
AA1
Y35
Y33
Y30
Y28
Y27
Y26
Y10
Y9
Y8
Y6
Y3
W32
W18
W17
W4
V33
V30
V28
V27
V26
V19
V17
V10
V9
V8
V6
V3
U32
U19
U18
U4
T35
T33
T30
T28
T27
T26
T10
T9
T8
T6
T3
T1
R32
R4
R1
P33
P30
P28
P27
P26
P9
P8
P6
P3
N35
N32
N4
N1
M33
M30
M28
M27
M26
M6
M3
L35

L31
L26
L25
L24
K33
K29
K27
K25
K22
K20
K18
K16
K14
K12
K11
J35
J32
J28
J22
J20
J18
J16
J14
J12
J10
H33
H30
H26
H24
H22
H20
H18
H16
H14
H12
H9
H8
H5
H2
G35
G31
G28
F26
F24
F22
F20
F18

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F16
F14
F12
F10
F8
F5
F3
F1
E3
E1
D35
D33
D31
D29
D27
D25
D23
D21
D19
D17
D15
D13
D11
D9
D1
C28
C26
C24
C22
C20
C18
C16
C14
C12
C10
C8
C4
A32
A29
A27
A25
A23
A20
A16
A13
A11
A9
A7

D

C

RG828SDGES_FCBGA932_SPRINGDALE~D

B

RG828SDGES_FCBGA932_SPRINGDALE~D
C365
+GMCH_GTLREF

0.01U_0402_16V7K~D

1

2

Trace width 12mils,Space
10mils

1

U 3F

H_D#[0..63] <7>

U 3A

D

2

GND

<7> H_A#[3..31]

3

GND

5

2

R 323

2

200_0603_1%~D
R329
2
H D RCOMP

Trace width 10mils,Space
7mils

1

0_0603_5%~D
1

1

C366
220P_0402_50V8J~D
2
R335
20_0603_1%~D

A

2

A

Compal Electronics, Inc.
Title

Springdale-Host/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

10

of

54

5

4

3

DDRA_SDQ[0..63]

C

AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
P31
P32

D DRA_CLK0
DDRA_CLK0#
D DRA_CLK1
DDRA_CLK1#
D DRA_CLK2
DDRA_CLK2#

SM_VREF_A trace width of 12mils and space
12mils(min)

E34

1

1

SMXRCOMP

AK9

C 47

SMXRCOMPVOH

AN9

0.1U_0402_16V4Z~D

SM XRCOMPVOL

AL9

SBA_A0
SBA_A1
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3

AP14
AM14
AL18
AP19
AL14
AN15
AP18
AM18

SMVREF_A
SMXRCOMP
SMXRCOMPVOH
SMXRCOMPVOL

AP22
AM22
AL24
AN27
AP21
AL22
AP25
AP27

SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23

AP28
AP29
AP33
AM33
AM28
AN29
AM31
AN34

SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31

AH32
AG34
AF32
AD32
AH31
AG33
AE34
AD34

SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39

2

C 64

2

R372
42.2_0603_1%~D

T34
T32
K34
K32
T31
P34
L34
L33

2.2U_0805_16VFZ~D

J33
H34
E33
F33
K31
J34
G34
F34

1

SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63

2

R367
42.2_0603_1%~D

<16>
<16>
<16>
<16>
<16>
<16>
D D RA_SDQS4 <15,17>
DDRA_SDM4 <15,17>

2

D DRB_CKE0
D DRB_CKE1

AK19
AF19
AG19
AE18

D DRB_CLK0
DDRB_CLK0#
D DRB_CLK1
DDRB_CLK1#
D DRB_CLK2
DDRB_CLK2#

SM_VREF_B trace width
12mils and space
12mils(min)

AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
of N31
N30
AP9

C 62
SMYRCOMP

1

R104

D D RA_SDQS5 <15,17>
DDRA_SDM5 <15,17>

U26
T29
V25
W25

SM_VREF_B

+2.5V_MEM

D DRA_SDQ32
D DRA_SDQ33
D DRA_SDQ34
D DRA_SDQ35
D DRA_SDQ36
D DRA_SDQ37
D DRA_SDQ38
D DRA_SDQ39

AA33

2.2U_0805_16VFZ~D
SMYRCOMPVOH

R34

SMYRCOMPVOL

R33

SDQS_B0
SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7

SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5

SDQ_B8
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15

SWE_B#
SCAS_B#
SRAS_B#
SBA_B0
SBA_B1
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#

SDQS_B1
SDM_B1

SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMVREF_B
SMYRCOMP
SMYRCOMPVOH
SMYRCOMPVOL

SDQS_B2
SDM_B2
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQS_B3
SDM_B3
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQS_B4
SDM_B4
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQS_B5
SDM_B5

D DRA_SDQ40
D DRA_SDQ41
D DRA_SDQ42
D DRA_SDQ43
D DRA_SDQ44
D DRA_SDQ45
D DRA_SDQ46
D DRA_SDQ47

2

2

C 52

SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47

C 50

R100
150_0603_1%~D

1

2.2U_0805_16VFZ~D

1

0.1U_0402_16V4Z~D

D D RA_SDQS6 <15,17>
DDRA_SDM6 <15,17>

SDQS_B6
SDM_B6

D DRA_SDQ48
D DRA_SDQ49
D DRA_SDQ50
D DRA_SDQ51
D DRA_SDQ52
D DRA_SDQ53
D DRA_SDQ54
D DRA_SDQ55

+2.5V_MEM

2

H31
H32

SDQS_A7
SDM_A7

SMXRCOMP
1

D DRA_SDQ24
D DRA_SDQ25
D DRA_SDQ26
D DRA_SDQ27
D DRA_SDQ28
D DRA_SDQ29
D DRA_SDQ30
D DRA_SDQ31

D DRB_SCS#0
D DRB_SCS#1

SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12

Close to GMCH

SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55

1
B

<16,17> D DRB_CKE0
<16,17> D DRB_CKE1

D D RA_SDQS3 <15,17>
DDRA_SDM3 <15,17>

M32
M34

SDQS_A6
SDM_A6

Trace width of 12mils and space
10mils(min)

<16,17> DDRB_SCS#0
<16,17> DDRB_SCS#1

V34
W33
AC34
AB31
V32
V31
AD31
AB32
U34
U33

Y25
AA25

<16,17> DDRB_SBS0
<16,17> DDRB_SBS1

150_0603_1%~D

SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47

+2.5V_MEM

D DRA_SDQ16
D DRA_SDQ17
D DRA_SDQ18
D DRA_SDQ19
D DRA_SDQ20
D DRA_SDQ21
D DRA_SDQ22
D DRA_SDQ23

AF34
AF31

SDQS_A4
SDM_A4

W27
W31
W26

<16,17> D D RB_SWE#
<16,17> D DRB_SCAS#
<16,17> D DRB_SRAS#

D D RA_SDQS2 <15,17>
DDRA_SDM2 <15,17>

AM30
AP30

SDQS_A5
SDM_A5

Close to GMCH

AE27
AD26
AL29
AL27
AE23

AP23
AM24

SDQS_A2
SDM_A2

SDQS_A3
SDM_A3

SCMDCLK_A0
SCMDCLK_A0#
SCMDCLK_A1
SCMDCLK_A1#
SCMDCLK_A2
SCMDCLK_A2#
SCMDCLK_A3
SCMDCLK_A3#
SCMDCLK_A4
SCMDCLK_A4#
SCMDCLK_A5
SCMDCLK_A5#

D D RA_SDQS1 <15,17>
DDRA_SDM1 <15,17>
D D RA_SDQ8
D D RA_SDQ9
D DRA_SDQ10
D DRA_SDQ11
D DRA_SDQ12
D DRA_SDQ13
D DRA_SDQ14
D DRA_SDQ15

AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20

DDR Channel B

AL20
AN19
AM20
AP20

SWE_A#
SCAS_A#
SRAS_A#

AP15
AP16

SDQS_A1
SDM_A1

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SM A10
DDRB_SM A11
DDRB_SM A12

1

<15>
<15>
<15>
<15>
<15>
<15>

D DRA_CKE0
D DRA_CKE1

SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15

D D RA_SDQS0 <15,17>
DDRA_SDM0 <15,17>

D D RA_SDQ0
D D RA_SDQ1
D D RA_SDQ2
D D RA_SDQ3
D D RA_SDQ4
D D RA_SDQ5
D D RA_SDQ6
D D RA_SDQ7

R110
42.2_0603_1%~D

D D RA_SDQS7 <15,17>
DDRA_SDM7 <15,17>

1

2

<15,17> D DRA_CKE0
<15,17> D DRA_CKE1

AA34
Y31
Y32
W34

SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5

AN11
AP12
AP10
AP11
AM12
AN13
AM10
AL10
AL12
AP13

D DRA_SDQ56
D DRA_SDQ57
D DRA_SDQ58
D DRA_SDQ59
D DRA_SDQ60
D DRA_SDQ61
D DRA_SDQ62
D DRA_SDQ63

SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55

C 66
2.2U_0805_16VFZ~D

SDQS_B7
SDM_B7

Trace width of 12mils
and space 10mils(min)

SMYRCOMP

SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63

1

<15,17> D DRA_SCS#0
<15,17> D DRA_SCS#1

D DRA_SCS#0
D DRA_SCS#1

SDQS_A0
SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7

1

AE33
AH34

<15,17> DDRA_SBS0
<15,17> DDRA_SBS1

2

DDRB_SDQ[0..63] <16,17>

U 3C
AF15
AG11
AJ10
AE15
AL11
AE16
AL8
AF12
AK11
AG12

D DRB_SDQS0 <16,17>
DDRB_SDM0 <16,17>

D D RB_SDQ0
D D RB_SDQ1
D D RB_SDQ2
D D RB_SDQ3
D D RB_SDQ4
D D RB_SDQ5
D D RB_SDQ6
D D RB_SDQ7

D

AG13
AG15

D DRB_SDQS1 <16,17>
DDRB_SDM1 <16,17>
D D RB_SDQ8
D D RB_SDQ9
D DRB_SDQ10
D DRB_SDQ11
D DRB_SDQ12
D DRB_SDQ13
D DRB_SDQ14
D DRB_SDQ15

AE17
AL13
AK17
AL17
AK13
AJ14
AJ16
AJ18
AG21
AE21

D DRB_SDQS2 <16,17>
DDRB_SDM2 <16,17>
D DRB_SDQ16
D DRB_SDQ17
D DRB_SDQ18
D DRB_SDQ19
D DRB_SDQ20
D DRB_SDQ21
D DRB_SDQ22
D DRB_SDQ23

AE19
AE20
AG23
AK23
AL19
AK21
AJ24
AE22
AH27
AJ28

D DRB_SDQS3 <16,17>
DDRB_SDM3 <16,17>
D DRB_SDQ24
D DRB_SDQ25
D DRB_SDQ26
D DRB_SDQ27
D DRB_SDQ28
D DRB_SDQ29
D DRB_SDQ30
D DRB_SDQ31

AK25
AH26
AG27
AF27
AJ26
AJ27
AD25
AF28

C

AD29
AC31

D DRB_SDQS4 <16,17>
DDRB_SDM4 <16,17>
D DRB_SDQ32
D DRB_SDQ33
D DRB_SDQ34
D DRB_SDQ35
D DRB_SDQ36
D DRB_SDQ37
D DRB_SDQ38
D DRB_SDQ39

AE30
AC27
AC30
Y29
AE31
AB29
AA26
AA27

2

AB34
Y34
AC33

<15,17> D D RA_SWE#
<15,17> D DRA_SCAS#
<15,17> D DRA_SRAS#

SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12

DDRB_SMA[0..12]

<16,17> DDRB_SMA[0..12]

1

AL34
AM34
AP32
AP31
AM26

2.2U_0805_16VFZ~D

DDRB_SDQ[0..63]

2

AJ34
AL33
AK29
AN31
AL30
AL26
AL28
AN25
AP26
AP24
AJ33
AN23
AN21

DDR Channel A

D

C 48

DDRA_SDQ[0..63] <15,17>

U 3B
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SM A10
DDRA_SM A11
DDRA_SM A12

2

1

DDRA_SMA[0..12]

<15,17> DDRA_SMA[0..12]

SM_VREF_A

2

R109
42.2_0603_1%~D
2

RG828SDGES_FCBGA932_SPRINGDALE~D

U30
U31

D DRB_SDQS5 <16,17>
DDRB_SDM5 <16,17>
D DRB_SDQ40
D DRB_SDQ41
D DRB_SDQ42
D DRB_SDQ43
D DRB_SDQ44
D DRB_SDQ45
D DRB_SDQ46
D DRB_SDQ47

AA30
W30
U27
T25
AA31
V29
U25
R27
L27
M29

D DRB_SDQS6 <16,17>
DDRB_SDM6 <16,17>
D DRB_SDQ48
D DRB_SDQ49
D DRB_SDQ50
D DRB_SDQ51
D DRB_SDQ52
D DRB_SDQ53
D DRB_SDQ54
D DRB_SDQ55

P29
R30
K28
L30
R31
R26
P25
L32

B

J30
J31

D DRB_SDQS7 <16,17>
DDRB_SDM7 <16,17>
D DRB_SDQ56
D DRB_SDQ57
D DRB_SDQ58
D DRB_SDQ59
D DRB_SDQ60
D DRB_SDQ61
D DRB_SDQ62
D DRB_SDQ63

K30
H29
F32
G33
N25
M25
J29
G32

RG828SDGES_FCBGA932_SPRINGDALE~D

+2.5V_MEM
+2.5V_MEM

Trace width of 12mils and space
10mils(min)

C406
1U_0603_10V6K~D

R369
30.9K_0603_1%~D

2

2

2

C407
1U_0603_10V6K~D

R 368
10K_0603_1%~D

Close to GMCH <1"
Follow Intel design guide
R1.11(12474) page124,125

5

C636
0.01U_0402_16V7K~D

R102
10K_0603_1%~D

1

R106
30.9K_0603_1%~D

2.2U_0805_16VFZ~D

*
SMYRCOMPVOL

SMYRCOMPVOH
1

SM XRCOMPVOL
2

1
C400
0.01U_0402_16V7K~D

2

1

2

2

*

1

1

C 59

1

2

1

C 57
1U_0603_10V6K~D

R101
30.9K_0603_1%~D

*

1

2

C 401
0.01U_0402_16V7K~D

C 54
0.01U_0402_16V7K~D

2

R105
10K_0603_1%~D

C 61
1U_0603_10V6K~D

1

2

2

*
SMXRCOMPVOH

2.2U_0805_16VFZ~D

R 373
30.9K_0603_1%~D

2.2U_0805_16VFZ~D

1

1

1

C 53

1

R374
10K_0603_1%~D

2

C637
0.01U_0402_16V7K~D

1

2

A

2

Trace width of 12mils and space
10mils(min)

1

2.2U_0805_16VFZ~D

C 63

1

1
C 65

2
2

2

1

1

2

2

Trace width of 12mils and space
10mils(min)
2

Trace width of 12mils and space
10mils(min)

2

1

+2.5V_MEM

1

+2.5V_MEM

Close to GMCH <1"

C 58
0.01U_0402_16V7K~D

A

Close to GMCH <1"

Close to GMCH <1"

Compal Electronics, Inc.
Title

Note: Intel recommend is 31.12K,the value isn't popularize.
Follow Dell's DT team use 30.9K

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Springdale-DDR Interface
Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

11

of

54

5

4

+1.5VRUN

3

2

+1.5VRUN

+1.5VRUN

2

GC_DET_R EF

1

2

R 55

2

1
R 64
43.2_0603_1%~D

R 59
60.4_0603_1%

2

2
G

+1.5VRUN

MMBT3904_SOT23~D

S

2
R 58
39.2_0603_1%~D

D
Q13
2N7002_SOT23~D

1

1

C 38
0.1U_0402_16V4Z~D

2

2
3

<18> AGP8X_DET_GC

3

GRCOMP

1

1

2

39.2_0603_1%~D
Q10

Close GMCH ball less than 250mils

AGP_SWING

1

1

R 48
8.2K_0402_5%~D
R 45
8.2K_0402_5%~D

2

R 66

VR EFCG

D

1

1
R 57
R328

1

Note:
AGP_SWING_MCH, trace width of
12mils and space 10mils

1

1

+12V

Close to VGA Conn.

C362
0.01U_0402_16V7K~D

0_0402_5%~D

2

VR EFGC <18>

VR E FCG <18>

2
100_0603_1%~D

C385

D

Follow Springdale Chipset Platform Design guide Rev1.11(12474)

2
C361
0.01U_0402_16V7K~D

1

1

0.1U_0402_16V4Z~D

2

52.3_0603_1%~D

1

2

Close GMCH ball
less than
250mils

HI_RCOMP_MCH
U 3D

<18> G_C/BE#[0..3]

+1.5VRUN

1

Note:
HI_SWING_MCH, trace width of
12mils and space 10mils

2

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

<18> G_FRAME#
<6> CK_66M_MCH
<18> G_DEVSEL#
<18> G_I R DY#
<18> G _TRDY#
<18> G_STOP#
<18> G _PAR
<18> G_REQ#
<18> G_GNT#

R330
226_0603_1%~D

CK_66M_MCH

G_PAR

GRCOMP
AGP_SWING
VR EFGC

Y7
W5
AA3
U2
U6
H4
AB4
V11
AB5
W11
AB2
N6
M7
AC2
AC3
AD2

GCBE0
GCBE1
GCBE2
GCBE3

GADSTBF0
GADSTBS0#

GFRAME
GCLKIN
GDEVSEL
GIRDY
GTRDY
GSTOP
GPAR/ADD_DETECT
GREQ
GGNT

AGP

GRCOMP/DVOBCGCOMP
GVSWING
GVREF

1

H I_SWING_MCH

R 68
147_0603_1%
2

1

1

C355
0.1U_0402_16V4Z~D

C364
0.01U_0402_16V7K~D

2

Close to GMCH ball <250mils

C

HI_VREF_MCH

R10
R9
M4
M5

<18> G _RBF#
<18> G _WBF#
<18> G_PIPE#_DBI_HI
<18> G_DBI_LO
<18> G_ST[0..2]

G_ST0
G_ST1
G_ST2

<20> HUB_HL[0..10]

113_0603_1%
2

1

1

C 41
0.1U_0402_16V4Z~D

C 42
0.01U_0402_16V7K~D

2

Close to GMCH ball <250mils
Note:
HI_VREF_MCH trace width of
10mils and space 7mils

<20> HUB_HLSTRF
<20> HUB_HLSTRS
HI_RCOMP_MCH
H I_SWING_MCH
HI_VREF_MCH

Note:
CI_SWING_MCH, CI_VREF_MCH
trace width of 12mils and
space
20mils
226_0603_1%~D

Trace 10mils, space 7mils

2

R 74

0.8V

52.3_0603_1%~D

CI_SWING_GMCH

+1.5VRUN

R 81

1

2
CI_SWING_GMCH
CI_VREF_GMCH

1

B

1

1

C 43

R 75

0.1U_0402_16V4Z~D

147_0603_1%
2

2

2

R 40
C 44
0.01U_0402_16V7K~D

2

1

0_0402_5%~D

<21> I C H _S YNC#
<20,36> PCI_PCIRST#

1
C360

R334

0.1U_0402_16V4Z~D

113_0603_1%
2

1

1

2

AK7
AH7
AD11
AF7
AD7
AC10
AF8
AG7
AE9
AH9
AG6
AJ6
AJ5
AG2
AF2
AF4
G4
AP8
AJ8
AK4
AG10
AG9
AN35
AP34
AR1

0.35V
CI_VREF_GMCH
2

AD4
AE3
AE2

GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GST0
GST1
GST2
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HISTRF
HISTRS

GSBSTBF
GSBSTBS#

HI_RCOMP
HI_SWING
HI_VREF

GSBA0#
GSBA1#
GSBA2#
GSBA3#
GSBA4#
GSBA5#
GSBA6#
GSBA7#

CI0
CI1
CI2
CI3
CI4
CI5
CI6
CI7
CI8
CI9
CI10
CISTRF
CISTRS

CSA

1

+1.5VRUN

AF5
AG3
AK2
AG5
AK5
AL3
AL2
AL4
AJ2
AH2
AJ3
AH5
AH4

DDCA_DATA
DDCA_CLK

CI_RCOMP
CI_SWING
CI_VREF
DREFCLK
EXTTS#
ICH_SYNC#
RSTIN#

REFSET
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20

RESERVED_1
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5

1

CK_66M_MCH

2

R320
@ 22_0402_5%~D

2

AC6
AC5
AE6
AC11
AD5
AE5
AA10
AC9
AB11
AB7
AA9
AA6
AA5
W10
AA11
W6
W9
V7

G_AD_STBF0 <18>
G_AD_STBS0# <18>
G_AD[0..31] <18>

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD 10
G_AD 11
G_AD 12
G_AD 13
G_AD 14
G_AD 15

V4
V5
AA2
Y4
Y2
W2
Y5
V2
W3
U3
T2
T4
T5
R2
P2
P5
P4
M2

G_AD_STBF1 <18>
G_AD_STBS1# <18>
G_AD[0..31] <18>

G_AD 16
G_AD 17
G_AD 18
G_AD 19
G_AD 20
G_AD 21
G_AD 22
G_AD 23
G_AD 24
G_AD 25
G_AD 26
G_AD 27
G_AD 28
G_AD 29
G_AD 30
G_AD 31

C

U11
T11
R6
P7
R3
R5
U9
U10
U5
T7

G_SB_STBF <18>
G_SB_STBS# <18>
G_SBA#[0..7] <18>

G_SBA#0
G_SBA#1
G_SBA#2
G_SBA#3
G_SBA#4
G_SBA#5
G_SBA#6
G_SBA#7

H3
F2

R 42
R 41

2
2

1
1

0_0402_5%~D
0_0402_5%~D

F4
E4
H6
G5
H7
G6

R 39

2

1

0_0402_5%~D

R 43

2

1

0_0402_5%~D

R 44

2

1

0_0402_5%~D

Analog RGB/CRT guidelines for Springdale-P

B

G3
E2
D2

R 38

2

1

0_0402_5%~D

A3
A33
A35
AF13
AF23
AJ12
AN1
AP2
AR3
AR33
AR35
B2
B25
B34
C1
C23
C35
E26
M31
R25

RG828SDGES_FCBGA932_SPRINGDALE~D
C324
@ 10P_0402_50V8J~D

2

+1.5VRUN

RED
RED#
GREEN
GREEN#
BLUE
BLUE#
HSYNC
VSYNC

C363
0.01U_0402_16V7K~D

1

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15

GADSTBF1
GADSTBS1#

HUB

H UB_HL0
H UB_HL1
H UB_HL2
H UB_HL3
H UB_HL4
H UB_HL5
H UB_HL6
H UB_HL7
H UB_HL8
H UB_HL9
HUB_HL10

1

2

R 69

N3
N5
N2

GRBF
GWBF
DBI_HI
DBI_LO

VGA

2

Note:
Springdale Customer Schematic R1.2 page18
AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design
guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.

R 61
@ 10K_0402_5%~D
A

1

A

G_PAR

1: External AGP
0: Internal Graphics

Title

Springdale-AGP/HUB/VGA/CSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

12

of

54

5

4

3

2

1

Note:
Placed less than 100 mils from ball
+1.5VRUN

0.82uH, DC current of 30mA
parts and close to cap
+1.5VRUN

2

1
C348
0.47U_0603_16V7K~D

2

C 356
0.47U_0603_16V7K~D

L34
0.82U_LQM21NNR82K10_150mA_10%_0805~D

Trace 14mils
2

1

R301
0_0603_5%~D

VCCA_FSB1

1

V CCA_FSB

2

+VTT_GMCH

1

Trace 14mils

2

+ C 276
2

100U_D_10VM~D

1

C280
0.1U_0402_16V4Z~D
2

Close to GMCH

+2.5V_MEM
C414
0.1U_0402_10V6K~D

1

C

1
C 419

C405
1
2

0.1U_0402_10V6K~D
VC C _DDR_DCAP5
2
VC C _DDR_DCAP4

0.22U_0603_10V7K~D
C 49

0.47U_0603_16V7K~D
1
1

+ 3VRUN

C 410

2
VC C _DDR_DCAP1
2
0.22U_0603_10V7K~D

C367
1

Trace 14mils

R314
R315

2
2

0.1U_0402_10V6K~D
VCC_AGP_DCAP2
2
+1.5VRUN
C371
0.1U_0402_10V6K~D
VT T_DCAP3
1
2
V CCA_FSB
1 0_0402_5%~D VCCA_DPLL
1 0_0402_5%~D VC CA_DAC
1
C 421

VC C _DDR_DCAP2
2
0.1U_0402_10V6K~D
VCCA1P5_DDR _SM

AA35
AL6
AL7
AM1
AM2
AM3
AM5
AM6
AM7
AM8
AN2
AN4
AN5
AN6
AN7
AN8
AP3
AP4
AP5
AP6
AP7
AR15
AR21
AR31
AR4
AR5
AR7
E35
R35
G1
G2
AG1
Y11
A31
B4
B3
C2
AL35
AB25
AC25
AC26

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DAC
VCC_DAC
VCCA_AGP
VCCA_AGP
VCCA_FSB
VCCA_FSB
VCCA_DPLL
VCCA_DAC
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSSA_DAC

D

J6
J7
J8
J9
K6
K7
K8
K9
L6
L7
L9
L10
L11
M8
M9
M10
M11
N9
N10
N11
P10
P11
R11
T16
T17
T18
T19
T20
U16
U17
U20
V16
V18
V20
W16
W19
W20
Y16
Y17
Y18
Y19
Y20
J1
J2
J3
J4
J5
K2
K3
K4
K5
L1
L2
L3
L4
L5
Y1
D3

1

1
C337
0.1U_0402_10V6K~D

2

1

2

1
C374
@ 0.1U_0402_10V6K~D

C396
0.1U_0402_10V6K~D

Place near GMCH

2

1
C391
@ 0.1U_0402_10V6K~D

2

1
C 390
@ 0.1U_0402_10V6K~D

2

1
C377
@ 0.1U_0402_10V6K~D

2

C376
@ 0.1U_0402_10V6K~D

+2.5V_MEM

1

1
C389
@ 0.1U_0402_10V6K~D

2

1
C378
@ 0.1U_0402_10V6K~D

2

1
C 373
@ 0.1U_0402_10V6K~D

2

1
C393
@ 0.1U_0402_10V6K~D

C375
@ 0.1U_0402_10V6K~D

2

2
C

+1.5VRUN

1
C354
VCC_AGP_DCAP1

1

2

2

1
C 387
@ 0.1U_0402_10V6K~D

2

1
C379
@ 0.1U_0402_10V6K~D

2

1
C338
@ 0.1U_0402_10V6K~D

2

C353
@ 0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

+1.5VRUN

Trace 50mils, min:35mils on ball field
VC C A_DDR

2

Place near ball
Y11,routing trace
from cap to ball

Note:
Placed less than 100 mils from ball

L42

1

C358
0.1U_0402_10V6K~D

+2.5V_MEM

1

1U_LQH32CN1R0M11_1A_20%_1210~D
2

2

Place near GMCH

1

RG828SDGES_FCBGA932_SPRINGDALE~D

1uH(0.54uH-D-IN), DC current of
1000mA parts and close to cap

+1.5VRUN

A15
A21
A4
A5
A6
B5
B6
C5
C6
D5
D6
D7
E6
E7
F7

POWER

VT T_DCAP1
VT T_DCAP2
1

B

+2.5V_MEM

+1.5VRUN

+VTT_GMCH
U 3E

D

1

VCCA1P5_DDR _SM

2

R351
0_0603_5%~D

1
+

2
C398
100U_D_10VM~D

1

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page246,248

C 402

2

1
C 319
@ 0.1U_0402_10V6K~D

2

1
C359
@ 0.1U_0402_10V6K~D

2

1
C346
@ 0.1U_0402_10V6K~D

2

C351
@ 0.1U_0402_10V6K~D

B

0.1U_0402_16V4Z~D

+1.5VRUN

2

Close to GMCH

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page84

1

2

1
C 380
@ 0.1U_0402_10V6K~D

2

1
C347
@ 0.1U_0402_10V6K~D

2

C345
@ 0.1U_0402_10V6K~D

Bulk Decopuling
+VTT_GMCH

1
+
2

A

2

C308
470U_D4_2.5V_R10M~D

1

C 327
0.1U_0402_16V4Z~D

+2.5V_MEM

2

1

2

C 288
4.7U_0805_6.3V6K~D

1

1

C287
4.7U_0805_6.3V6K~D

+1.5VRUN

+1.5VRUN

2

1

2

1

C289
1U_0603_6.3V6M~D

2

C290
0.47U_0603_16V7K~D

A

Place between the VR and GMCH
1

C384

2

C370

C 322

+
2

22U_1206_10V4Z~D

1

4.7U_0805_6.3V6K~D

1

10U_0805_10V4M~D

C 329
470U_D4_2.5V_R10M~D

2

2

1

C284
4.7U_0805_6.3V6K~D

Compal Electronics, Inc.
Title

Springdale-Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Place at the output of the 1.5V VR
5

4

3

2

Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

13

of

54

5

4

3

2

1

C

1

B

E

3

2

FAN1 Control and Tachometer
+12V

+12V

D

1

D

C117
+5VRUN

2

1
2
5
6

1

C108
@ 2200P_0603_50V7K~D
FAN1_VFB
1
2

2

2

FAN1TACH_ON

Q30

2
PMBT2222_SOT23~D

C102
0.47U_0805_16V7K~D

FAN1

R151
300K_0402_5%
1
2

FAN1_VOUT
FAN1_TACH_FB

1

1

1
R150
100K_0402_5%~D

R137
1K_0402_5%~D
1
2

1

D

1
C254
1U_0805_10V6K~D

2

FAN1_TACH <34>

G

G

IN-

S

3

1

O

6

FAN1_ON

7

3

IN+

R133
10K_0402_5%~D

R136
10K_0402_5%~D

4

8

Q31
SI3457DV-T1_TSOP6~D

P

5

4

<34> FAN1_PWM

+3VRUN

0.1U_0402_16V4Z~D

U30B
LM358M_SO8~D
R286
100K_0402_5%~D
FAN1VREF
1
2

SYMBOL(SOT23-NEW)

1

2

2222

FAN1_VOUT <25>
FAN1_TACH_FB <25>

SI3457DV P channel
Vds max: +/- 30V
Vgs max: +/- 20V
Id max: 4.3A @ Vgs = -10V
65mohm @ Vgs = -10V

+ C110

D2

2

2

2

RB751V_SOD323~D

100U_D_16VM

C

C

FAN2 Control and Tachometer
+12V

+3VRUN

+12V
1

+5VRUN
Q72

4

P
O

1

FAN2_ON

3

S

FAN2_TACH <34>

G

B

1
2
5
6

1

1

FAN2TACH_ON

Q61

2

C256

PMBT2222_SOT23~D
3

C255
1U_0805_10V6K~D

R290
1K_0402_5%~D
1
2

D

1

IN-

1

2

G

<34> FAN2_PWM

R287
10K_0402_5%~D
R289
10K_0402_5%~D

2

8

SI3457DV-T1_TSOP6~D

4

B

R291
100K_0402_5%~D
FAN2VREF
1
2

2

U30A
LM358M_SO8~D
3 IN+

C625
@ 2200P_0603_50V7K~D
FAN2_VFB
1
2

2

2

FAN2

R580
300K_0402_5%
1
2

JFAN2
1

FAN2_VOUT

1
R288
100K_0402_5%~D

2

RB751V_SOD323~D

1
2
3

FAN2_TACH_FB

1
+

D17

2

0.47U_0805_16V7K~D

C622
100U_D_16VM

MOLEX_53398-0390

2

LINK CIS
19.2

A

A

Compal Electronics, Inc.
Title

FAN CONTROL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

14

of

54

5

4

3

2

1

+2.5V_MEM
+2.5V_MEM

DDRA_VREF trace width of
12mils and space 12mils(min)
1

DDRA_SMA[0..12]

JDIM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDRA_SDM[0. .7]
D D RA_SDQ0
D D RA_SDQ5
D DRA_SDQS0
D D RA_SDQ7
D D RA_SDQ6
D D RA_SDQ8

D

D DRA_SDQ13
D DRA_SDQS1
D DRA_SDQ10
D DRA_SDQ15
<11> D DRA_CLK1
<11> DDRA_CLK1#

D DRA_SDQ20
D DRA_SDQ17

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

D DRA_SDQS2
D DRA_SDQ22
D DRA_SDQ19
D DRA_SDQ28
D DRA_SDQ29
D DRA_SDQS3
D DRA_SDQ30
D DRA_SDQ27

<11> D DRA_CLK0
<11> DDRA_CLK0#

C

D DRA_CKE1

<11,17> D DRA_CKE1

DDRA_SM A12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SM A10
DDRA_SBS0
D D RA_SWE#
D DRA_SCS#0

<11,17> DDRA_SBS0
<11,17> D D RA_SWE#
<11,17> D DRA_SCS#0

D DRA_SDQ36
D DRA_SDQ32
D DRA_SDQS4
D DRA_SDQ33
D DRA_SDQ35
D DRA_SDQ44
D DRA_SDQ45
D DRA_SDQS5
D DRA_SDQ43
D DRA_SDQ42

D DRA_SDQ52
D DRA_SDQ49
B

D DRA_SDQS6
D DRA_SDQ51
D DRA_SDQ54
D DRA_SDQ60
D DRA_SDQ61
D DRA_SDQS7
D DRA_SDQ62
D DRA_SDQ59
<6,16,21,32> ICH_SMBDATA
<6,16,21,32> ICH_SMBCLK
+3VSUS

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

DQ16
DQ20
DQ17
DQ21
VDD
VDD
DQS2
DM2
DQ18
DQ22
VSS
VSS
DQ19
DQ23
DQ24
DQ28
VDD
VDD
DQ25
DQ29
DQS3
DM3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VDD
VDD
CB0
CB4
CB1
CB5
VSS
VSS
DQS8
DM8
CB2
CB6
VDD
VDD
CB3
CB7
DU
DU/RESET#
VSS
VSS
CK2
VSS
CK2#
VDD
VDD
VDD
CKE1
CKE0
DU/A13
DU/BA2
A12
A11
A9
A8
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VDD
VDD
A10/AP
BA1
BA0
RAS#
WE#
CAS#
S0#
S1#
DU
DU
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VDD
VDD
DQS4
DM4
DQ34
DQ38
VSS
VSS
DQ35
DQ39
DQ40
DQ44
VDD
VDD
DQ41
DQ45
DQS5
DM5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VDD
VDD
VDD
CK1#
VSS
CK1
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VDD
VDD
DQS6
DM6
DQ50
DQ54
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VDD
VDD
DQ57
DQ61
DQS7
DM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VDD
VDD
SDA
SA0
SCL
SA1
VDD_SPD
SA2
VDD_ID
DU

D D R A_VREF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

D D RA_SDQ1
D D RA_SDQ4
DDRA_SDM0
D D RA_SDQ2

R442

2

1

75_0603_1%~D
C507
0.1U_0402_16V4Z~D

2

<11,17> DDRA_SDM[0..7]

+2.5V_MEM
DDRA_SDQS[0.. 7]

1

<11,17> DDRA_SMA[0..12]

DDRA_SDQ[0..63]

D D RA_SDQ3
D D RA_SDQ9

R440

D DRA_SDQ12
DDRA_SDM1

D

75_0603_1%~D
2

<11,17> DDRA_SDQ[0..63]
<11,17> DDRA_SDQS[0..7]

D DRA_SDQ14
D DRA_SDQ11

D DRA_SDQ16
D DRA_SDQ21

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDM2
D DRA_SDQ18
D DRA_SDQ23
D DRA_SDQ24
D DRA_SDQ25
DDRA_SDM3
D DRA_SDQ26
D DRA_SDQ31

C

D DRA_CKE0

D D RA_CKE0 <11,17>

DDRA_SM A11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1
D DRA_SRAS#
D DRA_SCAS#
D DRA_SCS#1

DDRA_SBS1 <11,17>
D DRA_SRAS# <11,17>
D DRA_SCAS# <11,17>
D DRA_SCS#1 <11,17>

D DRA_SDQ37
D DRA_SDQ34
DDRA_SDM4
D DRA_SDQ38
D DRA_SDQ39
D DRA_SDQ40
D DRA_SDQ41
DDRA_SDM5
D DRA_SDQ47
D DRA_SDQ46
D DRA_CLK2# <11>
D DRA_CLK2 <11>
D DRA_SDQ48
D DRA_SDQ53
B

DDRA_SDM6
D DRA_SDQ55
D DRA_SDQ50
D DRA_SDQ56
D DRA_SDQ57
DDRA_SDM7
D DRA_SDQ63
D DRA_SDQ58

AMP_1565917-1~D

DIMM0
STANDARD
Follow

1

C111

1

1
C107

A

2

22U_1206_10V4Z~D

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*21

System Memory Decoupling caps

+2.5V_MEM

2

1
C113

0.1U_0402_10V6K~D 2

1
C 106

0.1U_0402_10V6K~D 2

1

1

C109

0.1U_0402_10V6K~D 2

C114

0.1U_0402_10V6K~D 2

1
C112

0.1U_0402_10V6K~D 2

1
C 101

0.1U_0402_10V6K~D

2

0.1U_0402_10V6K~D

1
C 79

2

1
C 104

0.1U_0402_10V6K~D

2

0.1U_0402_10V6K~D

C 81
2

0.1U_0402_10V6K~D

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)pag 271 each DIMM(two) requirement 0.1uF*42

+2.5V_MEM

1

1
C103

2

0.1U_0402_10V6K~D 2

1
C134

1
C124

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D 2

1
C 132
0.1U_0402_10V6K~D 2

1

1

C129

C123

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D 2

1
C128
0.1U_0402_10V6K~D 2

1
C126
0.1U_0402_10V6K~D

1
C 92

2

1
C 133

0.1U_0402_10V6K~D

2

A

0.1U_0402_10V6K~D

C105
2

0.1U_0402_10V6K~D

Compal Electronics, Inc.
Title

DDR-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

15

of

54

5

4

3

2

1

+2.5V_MEM
DDRB_SDQ[0..63]
+2.5V_MEM

DDRB_VREF trace width of
12mils and space 12mils(min)

JDIM2
DDRB_SDM[0. .7]

<11,17> DDRB_SDM[0..7]

D D RB_SDQ5
D D RB_SDQ4
D DRB_SDQS0
D D RB_SDQ6
D D RB_SDQ1
D D RB_SDQ9
D DRB_SDQ13
D DRB_SDQS1

D

D DRB_SDQ14
D DRB_SDQ10
<11> D DRB_CLK1
<11> DDRB_CLK1#

D DRB_SDQ20
D DRB_SDQ21

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

D DRB_SDQS2
D DRB_SDQ19
D DRB_SDQ22
D DRB_SDQ24
D DRB_SDQ25
D DRB_SDQS3
D DRB_SDQ30
D DRB_SDQ26

<11> D DRB_CLK0
<11> DDRB_CLK0#
<11,17> D DRB_CKE1

C

D DRB_CKE1
DDRB_SM A12
DDRB_SMA9
DDRB_SMA7
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

<11,17> DDRB_SBS0
<11,17> D D RB_SWE#
<11,17> DDRB_SCS#0

DDRB_SM A10
DDRB_SBS0
D D RB_SWE#
D DRB_SCS#0
D DRB_SDQ38
D DRB_SDQ39
D DRB_SDQS4
D DRB_SDQ33
D DRB_SDQ37
D DRB_SDQ46
D DRB_SDQ44
D DRB_SDQS5
D DRB_SDQ41
D DRB_SDQ45

D DRB_SDQ52
D DRB_SDQ49
D DRB_SDQS6
D DRB_SDQ48

B

D DRB_SDQ51
D DRB_SDQ60
D DRB_SDQ59
D DRB_SDQS7
D DRB_SDQ57
D DRB_SDQ56
<6,15,21,32> ICH_SMBDATA
<6,15,21,32> ICH_SMBCLK
+3VSUS

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

DQ16
DQ20
DQ17
DQ21
VDD
VDD
DQS2
DM2
DQ18
DQ22
VSS
VSS
DQ19
DQ23
DQ24
DQ28
VDD
VDD
DQ25
DQ29
DQS3
DM3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VDD
VDD
CB0
CB4
CB1
CB5
VSS
VSS
DQS8
DM8
CB2
CB6
VDD
VDD
CB3
CB7
DU
DU/RESET#
VSS
VSS
CK2
VSS
CK2#
VDD
VDD
VDD
CKE1
CKE0
DU/A13
DU/BA2
A12
A11
A9
A8
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VDD
VDD
A10/AP
BA1
BA0
RAS#
WE#
CAS#
S0#
S1#
DU
DU
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VDD
VDD
DQS4
DM4
DQ34
DQ38
VSS
VSS
DQ35
DQ39
DQ40
DQ44
VDD
VDD
DQ41
DQ45
DQS5
DM5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VDD
VDD
VDD
CK1#
VSS
CK1
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VDD
VDD
DQS6
DM6
DQ50
DQ54
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VDD
VDD
DQ57
DQ61
DQS7
DM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VDD
VDD
SDA
SA0
SCL
SA1
VDD_SPD
SA2
VDD_ID
DU

D D R B_VREF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

R 418
D D RB_SDQ7
D D RB_SDQ0

2

DDRB_SDM0
D D RB_SDQ2

1

75_0603_1%~D
C458
0.1U_0402_16V4Z~D

D D RB_SDQ3
D DRB_SDQ12

1

<11,17> DDRB_SMA[0..12]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

R 415
D DRB_SDQ11
DDRB_SDM1

75_0603_1%~D

D

2

DDRB_SMA[0..12]

1

+2.5V_MEM
DDRB_SDQS[0.. 7]

<11,17> DDRB_SDQS[0..7]

2

<11,17> DDRB_SDQ[0..63]

D D RB_SDQ8
D DRB_SDQ15

D DRB_SDQ16
D DRB_SDQ17

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRB_SDM2
D DRB_SDQ23
D DRB_SDQ18
D DRB_SDQ28
D DRB_SDQ29
DDRB_SDM3
D DRB_SDQ27
D DRB_SDQ31

D DRB_CKE0

D DRB_CKE0 <11,17>

C

DDRB_SM A11
DDRB_SMA8
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
D DRB_SRAS#
D DRB_SCAS#
D DRB_SCS#1

DDRB_SBS1 <11,17>
D DRB_SRAS# <11,17>
D DRB_SCAS# <11,17>
D DRB_SCS#1 <11,17>

D DRB_SDQ32
D DRB_SDQ36
DDRB_SDM4
D DRB_SDQ34
D DRB_SDQ35
D DRB_SDQ43
D DRB_SDQ40
DDRB_SDM5
D DRB_SDQ42
D DRB_SDQ47
DDRB_CLK2# <11>
D DRB_CLK2 <11>
D DRB_SDQ53
D DRB_SDQ54
DDRB_SDM6
D DRB_SDQ55

B

D DRB_SDQ50
D DRB_SDQ61
D DRB_SDQ63
DDRB_SDM7
D DRB_SDQ58
D DRB_SDQ62
+3VSUS

AMP_1565918-1~D

DIMM1
REVERSE

Follow
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 0.1uF*24

System Memory Decoupling caps
+2.5V_MEM

1

1
C116

2

1
C100

0.1U_0402_10V6K~D 2

1
C 82

0.1U_0402_10V6K~D 2

1
C 84

0.1U_0402_10V6K~D 2

1
C 98

0.1U_0402_10V6K~D 2

1
C 95

0.1U_0402_10V6K~D 2

1
C 87

0.1U_0402_10V6K~D 2

1
C125

0.1U_0402_10V6K~D 2

1
C 85

0.1U_0402_10V6K~D 2

1
C 93

0.1U_0402_10V6K~D 2

1
C 96

0.1U_0402_10V6K~D 2

C130

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D

A

A

+2.5V_MEM

1

1
C 94

2

1
C 86

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D 2

1
C 97
0.1U_0402_10V6K~D 2

1
C 80
0.1U_0402_10V6K~D 2

1
C 90

1
C 78

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D 2

1
C 91
0.1U_0402_10V6K~D 2

1
C 83
0.1U_0402_10V6K~D 2

1
C 127
0.1U_0402_10V6K~D 2

1
C 99
0.1U_0402_10V6K~D 2

1
C122
0.1U_0402_10V6K~D 2

C115
0.1U_0402_10V6K~D

Compal Electronics, Inc.
Title

DDR-SODIMM SLOT2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

16

of

54

5

4

3

2

Channel A(DIMM0) Termination
resistors & Decoupling caps
V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT
R433
1

R N 97
D D RA_SDQ1 1
D D RA_SDQ4 2

56_4P2R_0404_5%~D R N 77
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQS3
2 D DRA_SDQ29

R N66
4
3

56_4P2R_0404_5%~D
1 D DRA_SDQ42
2 D DRA_SDQ43

R N 85
D D RA_SDQ5 1
D D RA_SDQ0 2

56_4P2R_0404_5%~D R N106
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ25
2 DDRA_SDM3

R N89
4
3

56_4P2R_0404_5%~D
1 D DRA_SDQ48
2 D DRA_SDQ53

R N 84
D D RA_SDQ7 1
D DRA_SDQS0 2

56_4P2R_0404_5%~D R N 64
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ51
2 D DRA_SDQS6

R N65
4
3

56_4P2R_0404_5%~D
1 D DRA_SDQ49
2 D DRA_SDQ52

R N 96
DDRA_SDM0 1
D D RA_SDQ2 2

56_4P2R_0404_5%~D R N 63
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ60
2 D DRA_SDQ54

R N88
4
3

56_4P2R_0404_5%~D
1 DDRA_SDM6
2 D DRA_SDQ55

R N 95
D D RA_SDQ3 1
D D RA_SDQ9 2

56_4P2R_0404_5%~D R N 87
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ50
2 D DRA_SDQ56

R N76
4
3

56_4P2R_0404_5%~D
1 D DRA_SDQ27
2 D DRA_SDQ30

R N 83
D D RA_SDQ8 1
D D RA_SDQ6 2

56_4P2R_0404_5%~D R N 86
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ57
2 DDRA_SDM7

R N105
4
3

56_4P2R_0404_5%~D
1 D DRA_SDQ26
2 D DRA_SDQ31

R N 94
D DRA_SDQ12 1
DDRA_SDM1 2

56_4P2R_0404_5%~D R N 62
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQS7
2 D DRA_SDQ61

R N100
4
3

R N 82
D DRA_SDQS1 1
D DRA_SDQ13 2

56_4P2R_0404_5%~D R N 92
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ37
2 D DRA_SDQ34

R N61
4
3

R N 81
D DRA_SDQ15 1
D DRA_SDQ10 2

56_4P2R_0404_5%~D R N 91
4
4
3
3

R N 93
D DRA_SDQ14 1
D DRA_SDQ11 2

56_4P2R_0404_5%~D R N 70
4
4
3
3

D

C

1

Channel B(DIMM1) Termination
resistors & Decoupling caps
V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

56_0402_5%~D
2 D DRA_SCS#0

R N103
4
3

56_4P2R_0404_5%~D
1 DDRA_SMA8
2 DDRA_SMA6

R N104
4
3

56_4P2R_0404_5%~D
1 D DRA_CKE0
2 DDRA_SM A11

R N73
4
3

56_4P2R_0404_5%~D
1 DDRA_SMA3
2 DDRA_SMA5

R N72
4
3

56_4P2R_0404_5%~D
1 DDRA_SM A10
2 DDRA_SMA1

R N 38
D D RB_SDQ7 1
D D RB_SDQ0 2

56_4P2R_0404_5%~D
4
3

R N 25
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQS3
2 D DRB_SDQ25

R N 60
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ42
2 D DRB_SDQ47

R N 32
D D RB_SDQ4 1
D D RB_SDQ5 2

56_4P2R_0404_5%~D
4
3

R N 34
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ26
2 D DRB_SDQ30

R N 17
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ49
2 D DRB_SDQ52

R N 31
D D RB_SDQ6 1
D DRB_SDQS0 2

56_4P2R_0404_5%~D
4
3

R N 58
4
3

56_4P2R_0404_5%~D
1 DDRB_SDM6
2 D DRB_SDQ55

R N 59
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ53
2 D DRB_SDQ54

R N 39
DDRB_SDM0 1
D D RB_SDQ2 2

56_4P2R_0404_5%~D
4
3

R N 15
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ60
2 D DRB_SDQ51

R N 16
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ48
2 D DRB_SDQS6

R N 37
D D RB_SDQ3 1
D DRB_SDQ12 2

56_4P2R_0404_5%~D
4
3

R N 52
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ50
2 D DRB_SDQ61

R N 42
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ27
2 D DRB_SDQ31

R N 30
D D RB_SDQ9 1
D D RB_SDQ1 2

56_4P2R_0404_5%~D
4
3

R N 14
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQS7
2 D DRB_SDQ59

R N 43
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ29
2 DDRB_SDM3

R N 29
D DRB_SDQS1 1
D DRB_SDQ13 2

56_4P2R_0404_5%~D
4
3

R N 51
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ63
2 DDRB_SDM7

R N 13
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ56
2 D DRB_SDQ57

R N 50
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ58
2 D DRB_SDQ62

R N 55
4
3

56_4P2R_0404_5%~D
1 DDRB_SMA4
2 DDRB_SMA2

R N110
4
3

56_4P2R_0404_5%~D
1 DDRA_SMA4
2 DDRA_SMA2

56_4P2R_0404_5%~D
1 D DRA_SDQ63
2 D DRA_SDQ58

R N74
4
3

56_4P2R_0404_5%~D
1 DDRA_SMA7
2 DDRA_SMA9

56_4P2R_0404_5%~D
1 D DRA_SDQ59
2 D DRA_SDQ62

R N102
4
3

56_4P2R_0404_5%~D
1 DDRA_SMA0
2 DDRA_SBS1

D DRA_SBS1 <11,15>

R N 36
D DRB_SDQ11 1
DDRB_SDM1 2

56_4P2R_0404_5%~D
4
3

R N 12
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ39
2 D DRB_SDQ38

56_4P2R_0404_5%~D
1 DDRA_SDM4
2 D DRA_SDQ38

R N101
4
3

56_4P2R_0404_5%~D
1 D DRA_SRAS#
2 D DRA_SCAS#

D DRA_SRAS# <11,15>
D DRA_SCAS# <11,15>

R N 28
D DRB_SDQ10 1
D DRB_SDQ14 2

56_4P2R_0404_5%~D
4
3

R N 41
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ32
2 D DRB_SDQ36

56_4P2R_0404_5%~D
1 D DRA_SDQ32
2 D DRA_SDQ36

R443
1

R N 47
D D RB_SDQ8 1
D DRB_SDQ15 2

56_4P2R_0404_5%~D
4
3

R N 11
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ33
2 D DRB_SDQS4

56_0402_5%~D
2 D DRA_SCS#1

R405
1

56_0402_5%~D
2 D DRB_SCS#0

R N 24
4
3

56_4P2R_0404_5%~D
1 DDRB_SM A12
2 D DRB_CKE1

R N 23
4
3

56_4P2R_0404_5%~D
1 DDRB_SMA7
2 DDRB_SMA9

R N 56
4
3

56_4P2R_0404_5%~D
1 DDRB_SMA8
2 DDRB_SMA6

R N 21
4
3

56_4P2R_0404_5%~D
1 DDRB_SM A10
2 DDRB_SMA1

R431
1
R N 22
4
3

56_0402_5%~D
2 D DRB_SCS#1
56_4P2R_0404_5%~D
1 DDRB_SMA3
2 DDRB_SMA5
V_1P25V_DDR_VTT

R N 57
D DRB_CKE0 1
DDRB_SM A11 2

4
3

56_4P2R_0404_5%~D
C

R N 20
D D RB_SWE# 1
DDRB_SBS0 2

R N 80
D DRA_SDQ17 1
D DRA_SDQ20 2

56_4P2R_0404_5%~D R N 69
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ33
2 D DRA_SDQS4

R N109
D DRA_SDQ16 1
D DRA_SDQ21 2

56_4P2R_0404_5%~D R N 99
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ39
2 D DRA_SDQ40

R N 79
D DRA_SDQ22 1
D DRA_SDQS2 2

56_4P2R_0404_5%~D R N 68
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ44
2 D DRA_SDQ35

D DRA_CKE0
D DRA_CKE1

<11,15> D DRA_CKE0
<11,15> D DRA_CKE1

V_1P25V_DDR_VTT

<11,15> D DRA_SCS#0
<11,15> D DRA_SCS#1

R N 27
D DRB_SDQ21 1
D DRB_SDQ20 2

56_4P2R_0404_5%~D
4
3

R N 40
4
3

56_4P2R_0404_5%~D
1 DDRB_SDM4
2 D DRB_SDQ34

R N 45
DDRB_SDM2 1
D DRB_SDQ23 2

56_4P2R_0404_5%~D
4
3

R N 10
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ46
2 D DRB_SDQ37

R N 33
D DRB_SDQ19 1
D DRB_SDQS2 2

56_4P2R_0404_5%~D
4
3

R N 49
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ35
2 D DRB_SDQ43

D DRA_SCS#0
D DRA_SCS#1

R N 75
DDRA_SM A12 1
D DRA_CKE1 2

4
3

56_4P2R_0404_5%~D

56_4P2R_0404_5%~D R N 98
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ41
2 DDRA_SDM5

R N 78
D DRA_SDQ28 1
D DRA_SDQ19 2

56_4P2R_0404_5%~D R N 67
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQS5
2 D DRA_SDQ45

R N107
D DRA_SDQ23 1
D DRA_SDQ24 2

56_4P2R_0404_5%~D R N 90
4
4
3
3

56_4P2R_0404_5%~D
1 D DRA_SDQ47
2 D DRA_SDQ46

<11,15> D D RA_SWE#
<11,15> DDRA_SBS0

D D RA_SWE# 1
DDRA_SBS0 2

4
3

R N 44
D DRB_SDQ18 1
D DRB_SDQ28 2

56_4P2R_0404_5%~D
4
3

R N 19
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQS5
2 D DRB_SDQ44

R N 26
D DRB_SDQ24 1
D DRB_SDQ22 2

56_4P2R_0404_5%~D
4
3

R N 48
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ40
2 DDRB_SDM5

R N 46
D DRB_SDQ16 1
D DRB_SDQ17 2

56_4P2R_0404_5%~D
4
3

R N 18
4
3

56_4P2R_0404_5%~D
1 D DRB_SDQ45
2 D DRB_SDQ41

56_4P2R_0404_5%~D

56_4P2R_0404_5%~D
1 DDRB_SMA0
2 DDRB_SBS1

R N 53
4
3

56_4P2R_0404_5%~D
1 D DRB_SRAS#
2 D DRB_SCAS#

D DRB_SRAS# <11,16>
D DRB_SCAS# <11,16>
<11,16> D D RB_SWE#

<11,15> DDRA_SDQ[0..63]
<11,15> DDRA_SDQS[0..7]
<11,15> DDRA_SMA[0..12]
<11,15> DDRA_SDM[0..7]

DDRB_SDQ[0..63]

<11,16> DDRB_SDQ[0..63]

DDRA_SDQS[0.. 7]

<11,16> D DRB_SCS#0
<11,16> D DRB_SCS#1

DDRB_SMA[0..12]

<11,16> DDRB_SMA[0..12]

D DRB_CKE0
D DRB_CKE1

<11,16> D DRB_CKE0
<11,16> D DRB_CKE1

DDRB_SDQS[0.. 7]

D D RB_SWE#
DDRB_SBS0
DDRB_SBS1

<11,16> DDRB_SBS0
<11,16> DDRB_SBS1

<11,16> DDRB_SDQS[0..7]

DDRA_SDQ[0..63]

4
3

56_4P2R_0404_5%~D
R N 54
4
3

R N 71
R N108
DDRA_SDM2 1
D DRA_SDQ18 2

D

D DRB_SCS#0
D DRB_SCS#1

DDRB_SDM[0. .7]

<11,16> DDRB_SDM[0..7]

DDRA_SMA[0..12]
DDRA_SDM[0. .7]

V_1P25V_DDR_VTT
B

V_1P25V_DDR_VTT

B

1
1

1
C 519

2

1
C514

0.1U_0402_10V6K~D 2

1
C515

0.1U_0402_10V6K~D 2

1
C516

0.1U_0402_10V6K~D 2

1
C517

0.1U_0402_10V6K~D 2

C488
C 511

0.1U_0402_10V6K~D 2

1

2

1
C482

0.1U_0402_10V6K~D 2

1
C481

0.1U_0402_10V6K~D 2

1
C 487

0.1U_0402_10V6K~D 2

1
C477

0.1U_0402_10V6K~D 2

1
C483

0.1U_0402_10V6K~D 2

1
C436

0.1U_0402_10V6K~D 2

C437

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

V_1P25V_DDR_VTT
V_1P25V_DDR_VTT

1

1
C 504

2

1
C512

0.1U_0402_10V6K~D 2

1
C518

0.1U_0402_10V6K~D 2

1
C513

0.1U_0402_10V6K~D 2

1

C503

0.1U_0402_10V6K~D 2

1
C484

0.1U_0402_10V6K~D
2

1
C478

0.1U_0402_10V6K~D 2

1
C476

0.1U_0402_10V6K~D 2

1
C 485

0.1U_0402_10V6K~D 2

1
C479

0.1U_0402_10V6K~D 2

1
C480

0.1U_0402_10V6K~D 2

1
C439

0.1U_0402_10V6K~D 2

C440

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D

V_1P25V_DDR_VTT
V_1P25V_DDR_VTT
1

1
C 492

2

1
C498

0.1U_0402_10V6K~D 2

1
C501

0.1U_0402_10V6K~D 2

1
C500

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D 2

1
C438

1
C 493

0.1U_0402_10V6K~D 2

0.1U_0402_10V6K~D 2

1
C496
0.1U_0402_10V6K~D 2

C502

1

0.1U_0402_10V6K~D

1
C443

2

0.1U_0402_10V6K~D 2

1
C442

1
C434

1

C505

C 441

0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D

2 0.1U_0402_10V6K~D 2

4.7U_1206_16V6K~D

V_1P25V_DDR_VTT

1

1
C 499

A

2

0.1U_0402_10V6K~D 2

1
C494
0.1U_0402_10V6K~D 2

1
C486
0.1U_0402_10V6K~D 2

1

0.1U_0402_10V6K~D

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*28

5

1

C490

C510

C495

A

2

4.7U_1206_16V6K~D

2

4.7U_1206_16V6K~D

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*26

We used one DIMM, so place 4.7uF*1 ; 0.1uF*20(11/6/02')

Title

We used one DIMM, so place 4.7uF*2 ; 0.1uF*23(11/6/02')

DDR Termination Resistors
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2

Size
C
Date:

Document Number

R ev
X00-G

LA-1711
Sheet

Tuesday, March 18, 2003
1

17

of

54

3

2

1

G_ PWR_SRC

2

G_SBA#[ 0..7]
J V ID

G_ST0
G_ST2
+1.5VRUN

G_SBA#2
G_SBA#4
G_SB_STBF
G_SB_STBS#

+1.5VRUN

AGP_RST#
G_I R DY#
G _TRDY#
R U N P WROK

<34,37,43,44,46> R U N P WROK

G_STOP#
G_FRAME#
G_C/BE#3

C

G_AD 31
G_AD 29
G_AD _STBS1#
G_AD_STBF1
G_AD 27
G_AD 25

<12>
<12>
<12>
<12>

G_AD_STBF0
G_AD _STBS0#
G_AD_STBF1
G_AD _STBS1#
G_SB_STBF
G_SB_STBS#

G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
<12> G_SB_STBF
<12> G_SB_STBS#

G_C/BE#2
G_AD 21
G_AD 19
VR EFCG

<12> VR EFCG
1

G_FRAME#
G_DEVSEL#
G_I R DY#
G _TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_PIPE#_DBI_HI
G_DBI_LO

<12> G_FRAME#
<12> G_DEVSEL#
<12> G_I R DY#
<12> G _TRDY#
<12> G_STOP#
<12> G _PAR
<12> G_REQ#
<12> G_GNT#
<12> G_PIPE#_DBI_HI
<12> G_DBI_LO

2

C388
0.1U_0402_16V4Z~D

G_AD _STBS0#
G_AD_STBF0
G_AD5
G_AD3
G_AD1

<34> F PV CC
+1.5VRUN

<21> ICH_SUS_STAT#

2

1

G_AD0
F PV CC

<24> S P_DIF

F PV CC
B

G_AD 15
G_AD 13
G_AD 11
G_AD9

ICH_SU S_STAT#

+12V

C317
0.1U_0603_25V7M~D

<33> GC_BL_SUSPEND

GC_BL_SUSPEND

+5VSUS
+3VSUS

5
P

INB

1

SYS _SUSPEND

2

PCIRST _AGP#

S

Q7
2N7002_SOT23~D

G_SBA#3
G_SBA#5
G_SBA#6
G_SBA#7
G_DEVSEL#
G _RBF#
G _WBF#
G_PIPE#_DBI_HI

G _RBF# <12>
G_ WBF# <12>

G_AD 30
G_AD 28
G_AD 26

C

G_AD 24
G_AD 22

FOXCONN QT00160A-9120L

Shielding Ground Pin

G_AD 20
G_AD 18

13,14
39,40
67,68
93,94
121,122
147,148

G_AD 23
G_AD 17
G_AD 16
G_DBI_LO
G_C/BE#1
VR EFGC_R

R 88
1

2

VR EFGC <12>

@ 0_0402_5%~D

G_AD 14
G_AD 12
G_AD 10
G_AD8
G_AD7
G_AD6

+1.5VRUN

G_AD4
G_AD2

CPLD Disable
Pop R96, Depop R98

+3VRUN
G_C/BE#0
G_AGPBUSY#
G_GNT#
G_PAR

R 96
@ 10K_0402_5%~D

SBAT_SMBDAT
SBAT_SMBCLK

SBAT_SMBDAT <34>
SBAT_SMBCLK <34>

STP_AGP_R#

1

R 98
0_0402_5%~D
2

B

STP_AGP# <36>

+5VALW
+ 5VRUN
LID_CL# <33>

+5VSUS

C417
0.047U_0402_10V4M~D

+ 3VRUN

1

2

1

2

1

2

+1.5VRUN

1

2

1

2

CLOSE
TO PIN

1

2

1

2

1

2

1

2

1

2

1

2

SYS _SUSPEND <33,41>
PCIRST_AGP# <20>

3

G

INA

D

2
G

<33,37,39,44> R U N _ ON

G_SBA#0
G_SBA#1

U7
@ TC7SH32FU_SSOP5~D

O

AGP8X_DET_GC <12>
PCI_PIRQA# <20>

G_REQ#
G_ST1

+3VSUS

4

1

+1.5VRUN
AGP8X_DET_GC
PCI_PIRQA#

FOX_QT00160A-9120L~D

AGP_RST#

A GP_PWRON# 2

AGP8X_DET_CG
PCI_PIRQB#

1

<20,32> PCI_PIRQB#

R 28
100K_0402_5%~D

3

0_0402_5%~D

D

+ 3VRUN

C357
0.047U_0402_10V4M~D

1

1

C352
0.047U_0402_10V4M~D

2

0.1U_0603_25V7M~D

Make R571
100K ohm
after 6th
August

C342
0.047U_0402_10V4M~D

R322

2

C 12
1

G_ PWR_SRC

C325
0.047U_0402_10V4M~D

CK_66M_AGP

Note:
AGP8X_DET_GC :Pull low by an AGP3.0 graphics card
Floating by an AGP2.0 graphics card

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

8
7
6
5

2

+3VRUN

2
4
6
8
10
12
GND
16
18
20
22
24
26
28
30
32
34
36
38
GND
42
44
46
48
50
52
54
56
58
60
62
64
66
GND
70
72
74
76
78
80
82
84
86
88
90
92
GND
96
98
100
102
104
106
108
110
112
114
116
118
120
GND
124
126
128
130
132
134
136
138
140
142
144
146
GND
150
152
154
156
158
160

1

AGP8X_DET_CG : low -->MB
support AGP3.0

1
3
5
7
9
11
GND
15
17
19
21
23
25
27
29
31
33
35
37
GND
41
43
45
47
49
51
53
55
57
59
61
63
65
GND
69
71
73
75
77
79
81
83
85
87
89
91
GND
95
97
99
101
103
105
107
109
111
113
115
117
119
GND
123
125
127
129
131
133
135
137
139
141
143
145
GND
149
151
153
155
157
159

C334
0.047U_0402_10V4M~D

AGP8X_DET_GC : low -->AGP3.0 ; High -->AGP2.0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159

C339
0.047U_0402_10V4M~D

G_ PWR_SRC

C418
0.047U_0402_10V4M~D

CK_66M_AGP
G_REQ#
G_ST0
G_ST1
G_ST2

<6> CK_66M_AGP
<12> G_REQ#
<12> G_ST0
<12> G_ST1
<12> G_ST2

D

1
2
3
2

C397
0.047U_0402_10V4M~D

<12> G_SBA#[0..7]

G_ PWR_SRC

Q8
SI4435DY_SO8~D

GPW R_SRC_ON 4

1

PW R _SRC
1

R 30
100K_0603_5%~D
1
2

1

2

C 19
0.1U_0603_25V7M~D

1

2

C 21
0.1U_0603_25V7M~D

1

2

C 22
0.1U_0603_25V7M~D

<12> G_AD[0..31]
<12> G_C/BE#[0..3]

2

C 24
0.1U_0603_25V7M~D

<12> G_ST[0..2]

C 23
0.1U_0603_25V7M~D

C 26
0.1U_0603_25V7M~D

PW R _ SRC

C409
0.047U_0402_10V4M~D

4

C336
0.047U_0402_10V4M~D

5

R156
0_0402_5%~D
2
1

A

+12V

1

2

+5VALW

+5VRUN

1
C 413
0.1U_0402_16V4Z~D

2

A

1
C416
0.1U_0402_16V4Z~D

2

C415
0.1U_0402_16V4Z~D

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

VGA Daughter Board Conn.
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

18

of

54

5

4

3

2

1

+3VALW

D

+VCC_CORE

+3VRUN
C408

U37

2

3

<26,34,35,47> DAT_SMB
<26,34,35,47> CLK_SMB

DAT_SMB
CLK_SMB

VCC

16
1

2.5VIN

FAN3_TACH

D1+
D1-

SDA
SCL

D2+
D2-

6
7
4
9

TACH1
TACH2
TACH3
TACH4

2

PWM1
PWM2/ALERT#

GND

PWM3

14

H_THERMDA <8>

1

H_THERMDA
H_THERMDC

13
12
11
10

MCH_THERMDA
MCH_THERMDC

15

FAN3_PWM

C420
2200P_0603_50V7K~D

2

MCH_THERMDA
1

1

0.1U_0402_16V4Z~D

Q73
H_THERMDC <8>

2

MMBT3904_SOT23~D

3

2
1

R378
6.8K_0603_5%~D

2
1

R375
6.8K_0603_5%~D

CPU Temperature Sensor
D

MCH_THERMDC
R366

5

1

8

1
R365

ADT7460ARQ_QSOP16~D

2

ATF_INT# <33,47>

0_0402_5%~D

2

+3VRUN

10K_0402_5%~D

Put 3904 between MCH and DDR
Address

0101 110X (X=1-->Read; X=0-->Write)

C

C

+3VRUN

FAN3 Control and Tachometer

1

+5VRUN

2

R125
10K_0402_5%~D

1

R120
1K_0402_5%~D
FAN3TACH_ON
1
2

1

2

R118
10K_0402_5%~D

FAN3_TACH
Q29

2
PMBT2222_SOT23~D

+12V

2

FAN3

1

C89
0.47U_0805_16V7K~D

3

1

JFAN3
1
2
3

B

1
2
3
2

+5VRUN

D1

1

RB751V_SOD323~D 2

C88
10U_1206_16V4Z~D
B

1

SUYIN_250019MR003G400ZL

1
2
5
6

R117
10K_0402_5%~D

D Q28
G

2

FAN3_PWM

3
SI3456DV-T1_TSOP6~D

LINK CIS
19.2

4

S

SI3456DV: N CHANNEL
VGS: 4.5V, RDS: 65 mOHM
Id(MAX): 5.1A

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

CPU Thermal Sensor & FAN Control
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

19

of

54

5

4

3

2

1

+ 3VRUN
R N3
8.2K_8P4R_1206_5%~D

1
2
3
4

1
2
3
4

+ 3VRUN

R N 35
8.2K_8P4R_1206_5%~D

8
7
6
5

8
7
6
5

U 5A
PCI_DEVSEL#
PCI_STOP#
P CI_TRDY#
PCI_FRAME#

+ 3VRUN

+3VSUS

R425
@ 10K_0402_5%~D
2
1

<12,36> PCI_PCIRST#
<6> CK_33M_ICHPCI

R393
10K_0402_5%~D

<18>
<18,32>
<28,30>
<30,32>

1

8
7
6
5

PCI_GNTA#
PC I _ IRDY#
PCI_SERR#
PCI_PERR#

PCI_FRAME#
PC I _ IRDY#
PC I_TRDY#
PCI_DEVSEL#
PCI_STOP#
P CI_PAR
P CI_PERR#

<28,30,32> P CI_SERR#

<33> ICH_PME#
2

R398
8.2K_0402_5%~D
@

2

1
2
3
4

R N2
8.2K_8P4R_1206_5%~D

1

+ 3VRUN

D

<28,30,32>
<28,30,32>
<28,30,32>
<28,30,32>
<28,30,32>
<28,30,32>
<28,30,32>

ICH_GPIO2_PI RQE#
ICH_GPIO3_PIR QF#
ICH_GPIO4_PIR QG#
ICH_GPIO5_PIRQH#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQA#

PCI_FRAME#
PC I _ IRDY#
P CI_TRDY#
PCI_DEVSEL#
PCI_STOP#
P CI_PAR
PCI_PERR#
PCI_PLOC K#
PCI_SERR#
ICH_PME#
PCI_PCI RST#
CK_33M_ICH PCI

D2
M3
E4
L3
E5
F1
K2
L2
L4
V2
V4
N1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PI RQE#
ICH_GPIO3_PIR QF#
ICH_GPIO4_PIR QG#
ICH_GPIO5_PIRQH#

B3
E1
A2
C2
D7
A6
E2
B1

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PERR#
PLOCK#
SERR#
PME#
PCIRST#
PCICLK
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5

8
7
6
5

PCI_PLOC K#
PCI_REQ0#
PCI_REQB#
PCI_PIRQB#
PCI_PIRQA#

CK_33M_ICH PCI

<32> PCI_REQ3#
<28> PCI_REQ4#
<30> PCI_REQB#

2

<30> PCI_GNTB#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#/GPI40
REQA#/GPI0
REQB#REQ5#/GPI1

D4
A3
B7
C7
A4
E8
B4

PCI_GNT3#
PCI_GNT4#
PCI_GNTA#
PCI_GNTB#

<32> PCI_GNT3#
<28> PCI_GNT4#

C465
@ 8.2P_0402_50V8J~D

D5
C1
C5
B6
C6
A5
E7

PCI_GNT1#

<30> PCI_GNT1#

R N1
8.2K_8P4R_1206_5%~D

8
7
6
5

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQA#
PCI_REQB#

<30> PCI_REQ1#

@ 10_0402_5%~D

1

+ 3VRUN
1
2
3
4

R414
1

2
R119
8.2K_0402_5%~D

CLK_ICH _TERM

1

R N4
8.2K_8P4R_1206_5%~D

2

1
2
3
4

+ 3VRUN

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#/GPO48
GNTA#/GPO16
GNTB#/GNT5#/GPO17

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3#
C/BE2#
C/BE1#
C/BE0#

P2
F4
P4
F5
N2
D3
P3
E6
N4
C4
N5
H3
P5
B2
L1
G4
G5
K1
G2
L5
H4
M4
F2
K5
J2
J3
H2
H5
K4
G3
J5
J4

PCI_AD[0..31] <28,30,32>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

D

M2
N3
J1
E3

PCI_C_BE3# <28,30,32>
PCI_C_BE2# <28,30,32>
PCI_C_BE1# <28,30,32>
PCI_C_BE0# <28,30,32>

FW82801EB_mBGA460_ICH5~D

PCI_PIRQD#
PCI_PIRQC#
PCI_REQ2#
+1.5VRUN

+ 3VRUN
R124
2

HI_RCOMP_ICH

PCI_REQ4#
1

PCI_REQ1#
PCI_REQ3#

R 411

Note:
HI_SWING_MCH, HI_VREF_MCH
trace width of 12mils and
space 10mils

2

226_0603_1%~D

R406
1

61.9_0603_1%
2

<12> HUB_HLSTRF
<12> HUB_HLSTRS

H I _ SWING_ICH

R 410

IDE_IRQ15
IDE_IRQ14

2

1

C460
0.1U_0402_16V4Z~D

1

2

R 409

2

113_0603_1%
B

2

1

C456
0.1U_0402_16V4Z~D

1

2

C452
0.01U_0402_16V7K~D

Close to ICH ball <250mils

0_0402_5%~D
LAN_RST#
1

R392
1

@ 1K_0402_5%~D
NC_EE_DOUT
2

B11
B10
A12
B9

<24> I CH_AC_SDIN0
<27> I CH_AC_SDIN1

I C H _A C_SYNC_R
ICH_AC_RST _R#
ICH_AC_SDOUT _R
I CH_AC_SDIN0
I CH_AC_SDIN1

PCIRSTB1#

1

PCIRST_AGP# <18>

IN2

0.1"~6"

6

PCIRSTB2#

1

IN2

U 8C
74VHC08MTC_TSSOP14~D

A

10
9

IN1
OUT

8

PCIRSTB3#

1

R159
33_0402_5%~D
PCIRST _SIO#
2

PCIRST_CB# <30>

R153
33_0402_5%~D
PCIRST_1#
2

PCIRST_1# <28>

12

OUT

11

PCIRSTB4#

1

R157
33_0402_5%~D
PCIRST_2#
2

PCIRST_2# <32>

IN2

5

I C H _A C_SYNC_R

2
R385

1
33_0402_5%~D

I C H _A C_SYNC <24,27>

ICH_AC_SDOUT _R

2
R390

1
33_0402_5%~D

ICH_AC_SDOUT <24,27>

ICH_AC_SDOUT
ICH_AC_BI TCLK
I CH_AC_SDIN0
I CH_AC_SDIN1

IN2

IN1

ICH_AC_RST# <24,27>

PCIRST_SIO# <33>

R160
33_0402_5%~D
1
2

U 8D
74VHC08MTC_TSSOP14~D
13

1
33_0402_5%~D

<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>

USB_OC0#
USB_OC2#
USB_OC3#
USB_OC4#

<26>
<26>
<26>
<23>

USB_OC IS 5V
TOLERANT

USBP6+ <26>
USBP6- <26>

+5VSUS

R P2
OC0#
OC1#
OC2#
OC3#
OC4#/GPI9
OC5#/GPI10
OC6#/GPI14
OC7#/GPI15
USBRBIAS
USBRBIAS#
CLK48

C15
D15
D14
C14
B14
A14
D13
C13
A24
B24

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
R394 22.6_0603_1%~D
USBRBIAS 2
1

6
7
8
9
10

+5VSUS

10K_10P8R_1206_5%

CK_48M_ICH

2

1

@ 10_0402_5%~D

AC_SYNC
AC_RST#
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_BIT_CLK

5
4
3
2
1

R404
F24

CK_48M_ICH <6>

USB_OC6# <26>

B

Note:
USBRBIAS keep less than 500mils

2

FW82801EB_mBGA460_ICH5~D
R396
@ 10_0402_5%~D

1

4

<6> CK_66M_ICH

C431
@ 4.7P_0402_50V8C~D

R383
@ 1K_0402_5%~D
1
2

CK_66M_ICH
R 413
@ 10_0402_5%~D

2

1

C427
@10P_0402_50V8J~D

2
A

+ 3VRUN
1

R397
@10K_0402_5%~D
2
1

OUT

2
R389

R395
@10K_0402_5%~D
2
1

5

IN1

ICH_AC_RST _R#

R402
@10K_0402_5%~D
2
1

U 8B
74VHC08MTC_TSSOP14~D
4

EE_DIN
EE_CS
EE_SHCLK
EE_DOUT

USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4-

1

R162
33_0402_5%~D
PCIRST _AGP#
2

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
LAN_CLK
LAN_RST#

C23
D23
A22
B22
C21
D21
A20
B20
C19
D19
A18
B18
C17
D17
A16
B16

2

3

HI_STBF
HI_STBS
HIRCOMP
HI_VSWING
HIREF
CLK66

USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N
USBP6P
USBP6N
USBP7P
USBP7N

1

OUT
7

2

P

14

U 8A
74VHC08MTC_TSSOP14~D

IN1

G

1

B8
C12
A9
E12
D12
A13
D8

HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI11

ICH_AC_BITCLK_TERM

+3VSUS

PCI_PCI RST#

2

<24> ICH_AC_BITCLK
C118
0.1U_0402_16V4Z~D
2
1

K23
J24
N24
L20
L24
N22

R430
2

H I _VREF_ICH

I RQ_SERIRQ <21,30,33>

H20
H21
J20
H23
M23
M21
N21
M20
L22
J22
K21
G22

C10
C9
C11
D9
E9
B12
D10
E10
AA1

Close to ICH ball <250mils

IDE_IRQ15 <21,23>
IDE_IRQ14 <21>

C455
0.01U_0402_16V7K~D

1

I RQ_SERIRQ

2

147_0603_1%~D

H UB_HL0
H UB_HL1
H UB_HL2
H UB_HL3
H UB_HL4
H UB_HL5
H UB_HL6
H UB_HL7
H UB_HL8
H UB_HL9
HUB_HL10

HI_RCOMP_ICH
H I _ SWING_ICH
H I _VREF_ICH
CK_66M_ICH

1

R139
10K_0402_5%~D
2
1

R426
10K_0402_5%~D
2
1

+ 3VRUN
R401
10K_0402_5%~D
2
1

U 5B

<12> HUB_HL[0..10]

52.3_0603_1%~D
+1.5VRUN

CK_48M _ICH_TERM

1

CK_66M _ICH_TERM

R387
10K_0402_5%~D
2
1

R113
10K_0402_5%~D
2
1

C

R386
10K_0402_5%~D
2
1

C

C464
@10P_0402_50V8J~D

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

ICH5-PCI/HUB/USB/AC97
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

20

of

54

5

4

R PD DREQ

2

1

C608
@33P_0603_50V8J~D

R SD DREQ

R SD D REQ <23>

2

1

I DE_PDIOW#
I DE_PDDACK#
I D E_PDDREQ
IDE_PDIOR#
I D E_P DIORDY

AA17
AC18
AC17
AD18
AA18

IDE_PDA2
IDE_PDA1
IDE_PDA0

AC19
AD19
AA19

IDE_PDCS3#
IDE_PDCS1#

Y18
AB19

PDD15
PDD14
PDD13
PDD12
PDD11
PDD10
PDD9
PDD8
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDIOW#
PDDACK#
PDDREQ
PDIOR#
PIORDY

SDIOW#
SDDACK#
SDDREQ
SDIOR#
SIORDY

PDA2
PDA1
PDA0

SDA2
SDA1
SDA0

PDCS3#
PDCS1#

Y17

<20> IDE_IRQ14

SDD15
SDD14
SDD13
SDD12
SDD11
SDD10
SDD9
SDD8
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

SDCS3#
SDCS1#

IRQ14

IRQ15

AA23
AB24
AC24
AB22
AA20
AC22
AD22
Y19
AC20
AB20
AC21
AB21
AD24
AD23
AB23
AA22

IDE_SDD15
IDE_SDD14
IDE_SDD13
IDE_SDD12
IDE_SDD11
IDE_SDD10
I DE_SDD9
I DE_SDD8
I DE_SDD7
I DE_SDD6
I DE_SDD5
I DE_SDD4
I DE_SDD3
I DE_SDD2
I DE_SDD1
I DE_SDD0

Y22
W20
Y20
Y23
Y21

I DE_SDIOW#
I DE_SDDACK#
I D E_SDDREQ
IDE_SDIOR#
I D E_S DIORDY

W21
W23
W22

IDE_SDA2
IDE_SDA1
IDE_SDA0

V20
V22

IDE_SDCS3#
IDE_SDCS1#

Y24

IDE_IRQ15

IDE_SDD[0..15] <23>

J HDD

Top View

IDE_RST_HD D_5V
I DE_PDD7
I DE_PDD6
I DE_PDD5
I DE_PDD4
I DE_PDD3
I DE_PDD2
I DE_PDD1
I DE_PDD0

+ 5VHDD

2

R PD DREQ
I DE_PDIOW#
IDE_PDIOR#
I D E_P DIORDY
I DE_PDDACK#
IDE_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#

12/17/02 Changed by
Dell's Require

1

R 568
1K_0402_5%~D

44

I DE_SDIOW# <23>
I DE_SDDACK# <23>

43

I DE_SDIOR# <23>
I D E_S DIORDY <23>
IDE_SDA[0..2] <23>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

PIDEACT#

<38> PIDEACT#

+ 5VHDD

Connector on
bottom side

HH99227-S9

IDE_SDCS3# <23>
IDE_SDCS1# <23>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

I DE_PDD8
I DE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

+ 5VHDD
45
46
47
48

FOX_HH99227-S9~D

IDE_IRQ15 <20,23>

FW82801EB_mBGA460_ICH5~D
Please link CIS
8.1

2

R439

ICH_SLP_S1# <6>

IDE_RST_MOD_5V <23>

+ 3VRUN

3

<33> IDE_RST_HDD

Q46
@ MMBT3904_SOT23~D

R 266
@ 10K_0402_5%~D
IDE_RST_MOD_SFTON
1
2

0_0402_5%~D

1

2

1

+ 3VRUN

R271
@ 10K_0402_5%~D
1
2

1

1

1

2

1

2

R262
@ 1K_0603_5%~D
R 265
0_0402_5%~D
1
2

IDE_RST_HD D_5V

1

2

3

<33> IDE_RST_MOD
SIO_SLP_S3#

C

2

2
R269
@ 1K_0603_5%~D

R263
0_0402_5%~D
1
2

1

+5VHDD

2

+5VMOD

D

T13
@ PAD

ATA_66_PRI/PDIAG
IDE_PDA2
IDE_PDCS3#

SGND
B1 SGND
B2 SGND
SGND

49
50

R570
470_0603_5%~D
2
1

IDE_CSEL_PRI

C237
0.1U_0402_16V4Z~D

I D E_SDDREQ

R 558
0_0402_5%~D
1
2

AB17
AA16
Y16
AC16
AA15
AD16
Y15
AD15
AB14
AD14
AC15
AA14
AC14
Y14
Y13
AB16

C240
0.1U_0402_16V4Z~D

R 279
0_0402_5%~D
1
2

IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
I DE_PDD9
I DE_PDD8
I DE_PDD7
I DE_PDD6
I DE_PDD5
I DE_PDD4
I DE_PDD3
I DE_PDD2
I DE_PDD1
I DE_PDD0

C238
4.7U_1206_16V6K~D

I D E_PDDREQ

1

1

I D E_S DIORDY

R 562
4.7K_0402_5%~D
2
1

C251
@ 33P_0603_50V8J~D

D

R 274
4.7K_0402_5%~D
2
1

2

2

+ 3VRUN

I D E_P DIORDY

3

U 5C

Q51
@ MMBT3904_SOT23~D

C

IDE_RST_MOD_SFTON

R114
S PKR

1

2

+3VRUN

LK2-->USB2P0_SMI

@ 1K_0402_5%~D
U 5D

BID0

R EV

0

0

X 00

0

0

0

1

X 01

0

0

1

0

X 02

0

0

1

1

X 03

0

1

0

0

X 04

<23>
<23>
<23>
<23>

Note:
SATABIAS keep
less than
500mils

<10,37> P WRGD_3V

1
R423

CMOS_CLR
SHORT PADS

K1

R471

R154
2

ICH_RTC RST#

2

2

1

1

1

2

LPC_LFR AME#
LPC_LDRQ0#
LPC_LDRQ1#

<33> LPC_LFRAME#
<34> LPC_LDRQ0#
<33> LPC_LDRQ1#

1
2

1K_0402_5%~D

180K_0603_5%

3

A2

ICH_RTCX1
ICH_RTCX2
ICH_RTC RST#

A1

2
+3VSUS

<36,37> SU SPWROK

PW RGD_OK

2

0_0402_5%~D

D3

R158
1K_0402_5%~D
1
2

+3.3VRTC

1

T5
R4
R3
U4
T4
U5
R2
AC11
AB12
AA12
AB13
AC12

E24
AB3
Y4
Y1
AB2
AB1
W1
U2
AA3
U1
R20
P24
T21
T2
AD10
F20
Y12

ICH_SYNC#

2

1

0
BAT54C_SOT23~D

V CC_RTC

V CC_RTC

PWRGD_3V

PWRGD_OK

0

0

B ID2
B ID0
B ID1
SAT A_LED#
B ID3

0

1

0

1

0

0

1

1

R135 1

2 10K_0402_5%~D

H_THERM TRIP_R#
SIO_THRM#
ICH_INTVR MEN

R437
10M_0603_5%~D

1

2

32.768KHZ_12.5P_MC-306~D
ICH_RTCX2

R 419
@ 10K_0402_5%~D
LPC_LDRQ0#
1
2
R 121
@ 10K_0402_5%~D
LPC_LDRQ1#
1
2

I C H_RI#

2

4

1

CBS_RI#

1

2

V CC_RTC

330K_0402_5%~D
2
+3VRUN
R416

V RM_PWRGD 1
SIO_THRM#

2

10K_0402_5%~D
R422
2

H_THERMTRIP# <8,37>

@ 0_0402_5%~D

C469
@ 0.1U_0402_16V4Z~D

CPLD Disable
Depop R141

1
R420

2
10K_0402_5%~D
2
10K_0402_5%~D

A

2

+3.3VRTC
R441
100K_0402_5%~D
1
2 ICH_THERM_PWRD N#

1

ICH_THERM_PWRDN# <37>

Compal Electronics, Inc.

C BS_RI# <30>

Title

R 140
@ 0_0402_5%~D

R141
5

R 435
CK_14M_ICH <6>

C428

R138
10K_0402_5%~D
2
1

1

2
X4
C508
15P_0603_50V8J~D
2
1

+ 3VRUN

SIO_SLP_S4_S5# <33>

@ 10K_0402_5%~D
2

R400
@ 10_0402_5%~D

2

ICH_RTCX1

R434
1

1

ICH_THERM_PWRD N#

+3VSUS

1U_0805_10V6K~D1

2 @ 0_0402_5%~D
2
0_0402_5%~D

SIO_THRM# <33>

A11

1

B

+3VSUS

ICH_SUS_STAT# <18>
SIO_SLP_S3# <33>
R424 1
R429 1
2 10K_0402_5%~D
+3VSUS
V RM_PWRGD <36>
H _P WRGOOD <8>

SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
R122 1
V RM_PWRGD

H_THERM TRIP_R#

+3VSUS

10K_0402_5%~D

SIO_PWRBTN# <33>

S USCLK
ICH_BATLOW#

1

C120

10K_0402_5%~D

2
2

R132

S PKR <24>

1
2
A

C509
15P_0603_50V8J~D
2
1

+3VSUS

10K_0402_5%~D

S USCLK <36>

ICH_SMBCLK <6,15,16,32>
ICH_SMBDATA <6,15,16,32>
R149 1
1

2

R428
1

SIO_EXT_SCI# <33>

S USCLK

+VCC_CORE
3

SIO_EXT_RTE# <33>

SI O_EXT_SCI#

+3VSUS

FW82801EB_mBGA460_ICH5~D

R436
10K_0402_5%~D
2
1

1

R438

C119
0.1U_0402_10V6K~D

Y11
Y9
AC5
AD5

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

BAT54C

1

SAT ABIAS
2
24.9_0603_1%~D
<6> CK_100M_ICH
<6> CK_100M_ICH#

<33> LPC_LAD[0..3]

K2

AA10
AB10
AD9
AC9

SATA_MODTX+
SATA_MODTXSATA_MODRXSATA_MODRX+

ICH_SMBCLK
ICH_SM BDATA
ICH_SMLI NK0
ICH_SMLI NK1
LINK_ALERT# 1
R427
S PKR
I C H_RI#

SIO_EXT_SMI# <33>

SIO_EXT_RTE#
+ 3VRUN

1

1

<12> I C H _S YNC#

AD2
AD1
AD3
AA2
V5

SIO_EXT_SMI#

CK_14M _ICH_TERM 1

BID1

0

Q32
2
@ MMBT3904_SOT23~D

+3VSUS

@ 4.7P_0402_50V8C~D

BID2

0

AA8
AB8
AD7
AC7

R432
10K_0402_5%~D
2
1

BID3
B

P20
R24

+ 3VRUN

2 10K_0402_5%~D

R 143
2.7K_0402_5%
2
1

Q33
2
@ MMBT3904_SOT23~D

R127
0_0402_5%~D

2 10K_0402_5%~D
2 10K_0402_5%~D

2

B ID3

SMI#

1
1 0_0402_5%~D

R417 1
R421 1
SIO_EXT_SMI#
LAN _PME# R142 1
SIO_EXT_RTE#
SI O_EXT_SCI#

R 148
2.7K_0402_5%
2
1

B ID2

R403

2
R 134 2

GPIO6
GPIO7
GPIO8
SMBALERT#/GPI11
GPIO12
GPIO13
GPO18
GPO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
DPRSLPVR(Mobile)
GPIO25
DPSLP#(Mobile)
GPIO27
GPIO28
SATA0TXP
GPIO32
SATA0TXN
GPIO33
SATA0RXN
GPIO34
SATA0RXP
SMBCLK
SMBDATA
SATA1TXP
SMLINK0
SATA1TXN
SMLINK1
SATA1RXN
LINKALERT#
SATA1RXP
SPKR
SATARBIASP
RI#
SATARBIASN
PWRBTN#
SUSCLK
CLK100P
TP0
CLK100N
SUS_STAT#
SLP_S3#
LAD0
SLP_S4#
LAD1
SLP_S5#
LAD2
SYS_RESET#
LAD3
VRMPWRGD
LFRAME#
CPUPWRGD/GPO49
LDRQ0#
THRMTRIP#
LDRQ1#/GPI41
THRM#
INTVRMEN
RTCX1
CLK14
RTCX2
INTRUDER#
RTCRST#
RSMRST#
NC
PWROK

R388

R115

1

<20,30,33> I RQ_SERIRQ
<8> H_SMI#
<36> STPCLK#

A20GATE
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
RCIN#
SERIRQ
SMI#
STPCLK#

R5
U3
Y2
AC3
W4
W5
U21
T20
U22
R1
U20
F22
AC1
W3
V3
W2
T1
G23
F21

2

1

10K_0402_5%~D 2

2

10K_0402_5%~D 2

R161
@ 220_0402_5%

B ID1

1

R126

3

1

1

10K_0402_5%~D 2

2

B ID0

R169
@ 1K_0402_5%~D

R130

1

1

3

10K_0402_5%~D 2

1

@

2

10K_0402_5%~D
R128

@

<34> SIO_A20GATE
<8> H_A20M#
<36> CPUSLP#
<8> H _F ERR#
<8> H _IGNNE#
<8> H_INIT#
<8> H_INTR
<8> H_NMI
<33> S IO_RCIN#

+ 3VRUN

R167
@ 220_0402_5%

10K_0402_5%~D
R123
1
2

@10K_0402_5%~D
R116
1
2

1

2

@10K_0402_5%~D
R399
1
2

+ 3VRUN

T22
V23
P22
U24
R21
R23
U23
R22
P23
F23
V24
T24

10K_0402_5%~D

Disable timer timeout

ICH5-IDE/LPC/PM/GPIO/LAN
CPLD_WAKE# <36>

0_0402_5%~D
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

21

of

54

5

4

3

+ 3VRUN

2

1

+1.5VRUN
+ 3VRUN

Place0.1u near ball(VSS)
G24,H24,K24,M24,AD4
and AD18; 0.01u near to
ball AD8.

+1.5VRUN

U 5E
D

B5
F6
G1
H6
K6
L6
M10
N10
P6
R13
V19
W15
W17
W24
AD13
AD20
G19
G21

2

2

+ 5VRUN + 3VRUN

D 14

R391
RB751V_SOD323~D

E18
B15
E11
F10
F11
E13
E14
U6
V6
F16
F17
F18
K15

+3VSUS

1

1

1K_0402_5%~D

I C H _V5REF_RUN
2

C468
1U_0805_10V6K~D

1

2

C471
0.1U_0402_16V4Z~D

1

2

C472
0.1U_0402_16V4Z~D

1

Place near ball A8

C

2

2

+5VSUS +3VSUS

A8
W14
D 13

R 384
1K_0402_5%~D

E16

1

1

RB751V_SOD323~D

2

ICH_V5REF_SUS
C447
1U_0805_10V6K~D

1

2

1

AD11

V CC_RTC

C445
0.1U_0402_16V4Z~D

2

C 506
C 444
0.1U_0402_16V4Z~D

0.1U_0402_10V6K~D

2

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
V5REF
V5REF

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCCSATAPLL
VCCSATAPLL
VCCUSBPLL
VCCSUS1_5_A
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_C
VCCSUS1_5_C

V5REF_SUS
VCCRTC

V_CPU_IO
V_CPU_IO
V_CPU_IO

Place near ball(VSS)
D1,A7,H1,P1W24 and A21

K10
K12
K13
L19
P19
R10
R6
H24
J19
K19
M15
N15
N23
E15
F15
F14
W19
R12
W9
W10
W11
W6
W7
W8
E22

C432

C491

0.1U_0402_16V4Z~D
2
1
C457

C451

0.1U_0402_16V4Z~D
2
1

0.1U_0402_16V4Z~D
2
1

C453

C454

0.1U_0402_16V4Z~D
2
1

0.1U_0402_16V4Z~D
2
1

C463

C474

0.1U_0402_16V4Z~D
2
1

0.1U_0402_16V4Z~D
2
1

C449

C497

0.1U_0402_16V4Z~D
2
1

0.1U_0402_16V4Z~D
2
1

C466

C430
1

0.01U_0402_16V7K~D
2

C475
VCCSUS15_B
1

0.01U_0402_16V7K~D
2

VCCSUS15_A

F19
Y5
AA4
AB4
F7
F8

V CCSUS15_C

R15
R19
T19

1
C433

+ VCC_CORE

C448

0.1U_0402_16V4Z~D
2
1

Place near
ball (VSS)A19

AA6
AB6
C24

D

0.1U_0402_16V4Z~D
2
1

0.1U_0402_16V4Z~D
2
1
C450
0.01U_0402_16V7K~D
1
2

Place near
ball (VSS)AD4

2
0.01U_0402_16V7K~D

Place near
ball (VSS)A7

C

FW82801EB_mBGA460_ICH5~D

1

1

Place near ball AD11
Place near ball(VSS) A17

U 5F
A1
A7
A10
A15
A17
A19
A21
A23
AA5
AA7
AA9
AA11
AA13
AA21
AA24
AB5
AB7
AB9
AB11
AB15
AB18
AC2
AC4
AC6
AC8
AC10
AC13
AC23
AD4
AD6
AD8
AD17
AD21
AD12
B13
B17
B19
B21
B23
C3
C8
C16
C18
C20
C22
D1
D6
D11
D16
D18
D20
D22
D24
E17
E19
E20
E21
E23
F3
F9

B

A

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G6
G20
G24
H1
H19
H22
J6
J21
J23
K3
K11
K14
K20
K22
K24
L10
L11
L12
L13
L14
L15
L21
L23
M1
M5
M11
M12
M13
M14
M22
M24
N11
N12
N13
N14
N20
P1
P10
P11
P12
P13
P14
P15
P21
R11
R14
T23
T3
T6
U19
V1
V21
W16
W18
Y3
Y6
Y7
Y8
Y10

+1.5VRUN

+ VCC_CORE

2

1

+1.5VRUN
C429

Place near
ball T22
C470
0.1U_0402_16V4Z~D

Place near ball D24

C473

Place near ball AD6

0.1U_0402_16V4Z~D
2
1

0.1U_0402_16V4Z~D
2
1

C426
0.01U_0402_16V7K~D
1
2

C489
0.01U_0402_16V7K~D
1
2

B

Place0.1u near ball(VSS)
A17,A23,V1.Addition cap near
+3VSUS
A15,A19
C435
1U_0603_6.3V6M~D
1
2
C467
0.1U_0402_16V4Z~D
2

1
C424

0.1U_0402_16V4Z~D
2

1
C446

0.1U_0402_16V4Z~D
2

1

C425
0.01U_0402_16V7K~D
1
2

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page278
A

FW82801EB_mBGA460_ICH5~D

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

ICH5 Power & Decoupling
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

22

of

54

5

4

3

2

1

<21> IDE_SDD[0..15]
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

16

<21> SATA_MODTX-

18

<21> IDE_SDDACK#
<21> IDE_SDIOR#
<21> IDE_SDIOW#
<21> IDE_SDIORDY

IDE_SDDACK#

Reserved USB+

20

IDE_SDIOR#
IDE_SDIOW#
IDE_SD IORDY

Reserved USB-

22
24

IDE_SDCS3#

26

IDE_SDA2

28

IDE_SDA0

30

INT_CD_R

<24> INT_CD_R

INT_CD_L

<24> INT_CD_L

IDE_SDA1

32
34

C

R563
470_0603_5%~D
1
2

IDE_IRQ15

<20,21> IDE_IRQ15

BAY_MODPRES#

<33> BAY_MODPRES#

RSDDREQ

<21> RSDDREQ

CSEL2

36

IDE_SDIOR#

38

IDE_SDIOW#

40

IDE_SDD15

42
44

IDE_SDD1

46

IDE_SDD2

48

IDE_SDD12

50

IDE_SDD11

52
54

R555
0_0402_5%~D
1
2

IDE_RST_MOD_5V

<21> IDE_RST_MOD_5V
<33> USB_IDE#

+3VALW

<24> CD_AUDIORET
+3VALW

1

2

56

IDE_SDD6

58

IDE_SDD8

60

MOD_RST

62

73
13

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

64

64

CD_AUDIORET

66

66

BAY_MODPRES#

68

65
67

13

SATA_MOD_DETECT#

2

C616
0.1U_0402_16V4Z~D

11

2

C615
0.1U_0402_16V4Z~D

+3VMOD

C614
0.1U_0402_16V4Z~D

9

1

2

SATA_MOD_DETECT# <33>

1

2

C612
0.1U_0402_16V4Z~D
D

1

2

+3VALW
R569

R567

MOD_PIN15

15

1
@

2 USB_OC4#
0_0402_5%~D

SATA_MOD_DETECT#

USB_OC4# <20>

1

2

1K_0402_5%~D

17
19

USBP4_D+

21

USBP4_D-

USBP4_D+ <26>
USBP4_D- <26>

23
25

SIDEACT#

27

IDE_SDCS1#

1

2

R564

+3VMOD

1K_0402_5%~D

29
T12
31

PDIAG#

33

IDE_IRQ15

35

IDE_SDDACK#

37

IDE_SD IORDY

@ PAD

C

39
41

RSDDREQ

43

IDE_SDD0

45

IDE_SDD14

47

IDE_SDD13

1

49
51

IDE_SDD3

53

IDE_SDD4

55

IDE_SDD10

57

IDE_SDD9

2
3
6

59

4

IDE_SDD7

61
63
65

INT_CD_R

67

INT_CD_L

68

70

C617
4.7U_1206_16V6K~D

11
12

USB_IDE#

R553
100K_0402_5%~D

71

10

7

1

2

0.1U_0402_16V4Z~D

5

INT_CD_R <24>
INT_CD_L <24>

1

2

WF1F068N1A

B

R554
100K_0402_5%~D
1
2

IDE_SDD5

9

1

C601
47P_0402_50V8J~D

14

<21> SATA_MODTX+

IDE_SDCS1#
IDE_SDCS3#

7
8

5

C602
47P_0402_50V8J~D

12

6

G

IDE_SDA0
IDE_SDA1
IDE_SDA2

5

3

M2

10

<21> SATA_MODRX-

3
4

C613

1

74

8

<21> SATA_MODRX+

M1

69
6

<21> IDE_SDA[0..2]

<21> IDE_SDCS1#
<21> IDE_SDCS3#

4

G

G

swap by Dell require
Please see sketch

2

G

2

+3VMOD

1
1

72

D

+5VMOD
JMOD1

1

2

FOX_QL11343-A6B3-HT~D

B

Please link CIS
8.2

D-MODULE Detect

MB side

Module side
JMOD1

Connector

Device

Pin68

Pin64

Pin13

BAY_MODPRES#

USB_IDE#

SATA_MOD_DETECT#

LOW

LOW

HIGH

LOW

HIGH

HIGH

LOW

HIGH

LOW

HIGH

X

X

TOP VIEW

Parallel IDE

A

Host Chip
ICH5

RX+

TX+

RX-

TX-

TX+

RX+

TX-

RX-

USB Device

Device Chip

S-ATA IDE
A

None

Compal Electronics, Inc.
Title

D- MODULE

Direct connect
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

23

of

54

5

4

3

2

1

VD DA
+5VSUS

TPS793475_BYPASS

2

2

1

2

A

Y

4

D

C212
0.1U_0402_16V4Z~D

B

2
5
A
B

3

2
SP DIF_SHDN

U 20
4

Y

Z24022

<30> CBS_SPK

Z2403

R223
20K_0402_5%
1
2

Z2404
1

2

P

<33> BEEP

1

G

1

3

<21> S PKR

U 21
SN74AHCT1G86DCKR_SC70-5~D

1
1

C192
0.1U_0402_16V4Z~D
1
2
2

SN74AHCT1G86DCKR_SC70-5~D

R237
43K_0402_5%~D

R221
8.2K_0402_5%~D

1

PC_BEEPIN
C190
@1000P_0402_50V7K~D

1

5
P
A

OE#

2

U 12
Y

4

S P_DIF <18>

3

G

SP DIF

1

2

2

3

2

Z2401

single gate TTL

+ 5VRUN

C158
0.1U_0402_16V4Z~D

4

L23
BLM11A121S_0603~D

5

D

1

5
VD DA

1

P

EN BYPASS

TPS793475DBVR_SOT23-5~D

1

1

G

4

2

GND

1

<34> A UDIO_AVDD_ON

A UDIO_AVDD_ON 3

5

OUT

C216
2.2U_0805_16VFZ~D

2

2

VDDA=4.75V

IN

C215
0.1U_0402_16V4Z~D

2

1

2

C224
0.1U_0402_16V4Z~D

1

C198
1U_0805_10V6K~D

C209
0.01U_0402_16V7K~D

C208
0.1U_0402_16V4Z~D

U 22
1

SN74AHCT1G125DCKR_SC70-5~D

+ 3VRUN

<20> ICH_AC_BITCLK

<20> I C H_AC_SDIN0

2

R_ICH_AC_BI TCLK

R534
33_0402_5%~D
1
2

6

R _ICH_AC_SDIN0

8

1

2

RESET#
SYNC
SDATA_OUT

LINE_IN_L

CD_L

SDATA_IN
CD_R

C575
1
C171
1
1

1000P_0402_50V7K~D
AFLT1
2
1000P_0402_50V7K~D
AFLT2
2

29

VREFOUT
2 C176
@ 0.1U_0603_16V7K~D

28

30

27

STAC9750

AFLT1

AUX_L

AFLT2
AUX_R
VREFOUT
MIC1
VREF
MIC2

C AP2
2

1

C573
0.1U_0402_16V4Z~D

<25,50> SPK_SHUTDOWN#

1

32

SPK_SHUTDOW N#

43

SP DIF_SHDN

44

SP DIF

48

CAP2

VIDEO_L

GPIO0/NC

VIDEO_R

GPIO1/NC
PHONE

B

E APD

<25> E APD

47
31

SPDIF
PC_BEEP

NC/BPCFG

HP_OUT_L

23

C D _L

C195
1

2

19

CD_C OMM

C196
1

2

20

C D _R

C197
1

2

18

1U_0805_10V6K~D
INT_CD_L <23>
1U_0805_10V6K~D
CD_AUDIORET

CD_AUDIORET <23>

1U_0805_10V6K~D
I NT_CD_R <23>

14
C201
0.22U_0603_10V7M~D
1
2

15
21

CNB_MICIN

1

22

NB_MICIN <25>

2

C199
0.1U_0402_16V4Z~D

16
17

1

13

2

12

PC_BEEPIN

C200
0.1U_0402_16V4Z~D

39

HP_OUT_LL

R498
1

40

HP_COMM

C162
1U_0805_10V6K~D
1
2

41

HP_OUT_RR

R499
1

B

HP_COMM

@ 0_0402_5%~D
2

HP_OUT_L <25>

NC/FLTIN

2

R512
10K_0402_5%~D

C

EAPD

2

33
R526
47_0402_5%~D

1

24

1

ICH_AC_SDOUT

VD D A

2

BIT_CLK
CD_C

AC97VREFI
2

11
10
5

LINE_IN_R

C578

0.1U_0402_16V4Z~D

1

C186
2.2U_0805_16VFZ~D

2

1

C579
@ 27P_0603_50V8J~D

C571
@ 27P_0603_50V8J~D

<27> MDC_AC_BITCLK

ICH_AC_R ST#
I C H _A C_SYNC
ICH_AC_SDOUT

<20,27> ICH_AC_RST#
<20,27> I C H _A C_SYNC
<20,27> ICH_AC_SDOUT

DVDD1
DVDD2

U 16
R531
33_0402_5%~D
1
2
R525
33_0402_5%~D
1
2

1

C559
0.1U_0402_16V4Z~D

C580
0.1U_0402_16V4Z~D

1

2

L16
BLM31A260SPT_1206~D
1
2

25
38

1

2

AVDD1
AVDD2

1

2

AU DIO_AVCC

1
9

2

C161
2.2U_0805_16VFZ~D

C

C576
0.1U_0402_16V4Z~D

C170
0.1U_0402_16V4Z~D

W=30 mil

@ 0_0402_5%~D
2

HP_OUT_R <25>

ICH_AC_SD OUT_TERM

1

HP_OUT_R

34
46
45

C183
22P_0402_50V8J~D
1
2
2

XTL_24M+

3

MONO_OUT

37

AUD_MONO_OUT <50>

NC/FLTOUT
CID1
CID0

LOUT_L

35

AUD_LINE_OUT_L <25>
2

XTL_OUT

X2
1

2

XTL_IN

26
42

XTL_24M-

AVSS1
AVSS2

24.576 MHz_20P_1BX24576CC1A~D
PACKAGE : 8X4.5X1.5mm
DVSS1
DVSS2

C168
22P_0402_50V8J~D
1
2

4
7

2

C 570
@ 22P_0402_50V8J~D

1

1

C569
1000P_0402_50V7K~D

LOUT_R

36

AUD_LINE_OUT_R <25>
2

STAC9750_TQFP48~D
1

C565
1000P_0402_50V7K~D

A

A

Compal Electronics, Inc.
Title

AC97 Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

24

of

54

5

4

3

2

1

VD D A

+3VALW

+ 3VRUN

2

L46
R 511
1K_0402_5%~D

R 459
10K_0402_5%~D

AUD_LINE_OUT_L

C535
1U_0603_10V6K~D
A UD_LINE_IN_R
1
2
1

AUD_LINE_IN _L

2

NC-6

13

INL

2

C_IN T_MIC+

6

C179
0.1U_0402_16V4Z~D

7

INT_MIC+

EXT_MIC_BIAS

GND

8

OUT

EXT_MIC_IN

MIC_SELECT

1
2

3
2

HP_OUT_L

NC-20

D

4
6
8
12
16
20

MAX4411ETP-T_TQFN20~D

EMICIN
1

1
C547
1U_0603_10V6K~D

2

EXT_MIC_PLUG

1
3
5
7
9
11
13
15
17
19

EXT_MIC_BIAS
EMICIN

HP_NB_SEN SE 2
G
2N7002_SOT23~D

D

S

Q40
3

Q39

S

<33> NB_MUTE

1

D

D

3

1

1

HP_OUT _R

2

J A UDO

2
G
3

NC-16

1
2

C178
0.1U_0402_16V4Z~D
1
2

C_EXT_MIC+

AMPVCC

<24> E APD

C1N

C537
1U_0603_10V6K~D

1

C 165
1U_0805_10V6K~D

R_IN T_MIC-

R497
1K_0402_5%~D

1

SPK_SHUTDOW N#

C1P

1

NB_MICIN <24>
EXT_MIC_PLUG

1

R197
100K_0402_5%~D

<24,50> SPK_SHUTDOWN#

NC-12

EXT_MIC_BIAS

3

CMAMP110M_MSOP8~D

+ 3VRUN

NC-8

C539
1U_0603_10V6K~D

4

SGND

1

VSUP

17

IN T_MIC+

INT_MIC-

PGND

5

10

INR

SVss

C_IN T_MIC-

R505
1K_0402_5%~D

2

19

NC-4

15

5

2

2

<38> INT_MIC+

1

SVDD

2
AUD_LINE_OU T_R

C561
0.1U_0402_16V4Z~D

INT _MIC-

11
9

R 503
100K_0402_5%~D

U 13
<38> INT_MIC-

OUTL

2

1

C529
1U_0603_10V6K~D

OUTR

SHDNL#

PVss

1

C545
0.1U_0402_16V4Z~D

PVDD

SHDNR#

18

2

C157
2.2U_0805_16VFZ~D

14

2

1

R517
1K_0402_5%~D
1
2

1

U 38
HP_NB_SEN SE

2

7

1

W=15mils
AMPVCC

1
C 169
1U_0805_10V6K~D

D

2

BLM11A121S_0603~D

R_IN T_MIC+
2

1

1

2

VD DA

S

Q38
2N7002_SOT23~D

2
G

2N7002_SOT23~D

<14> FAN1_VOUT

HP_NB_SEN SE

2
4
6
8
10
12
14
16
18
20

HP_OUT_L
HP_OUT _R

HP_OUT_L <24>
HP_OUT_R <24>

FAN1_TACH_FB <14>

NAIS_AXN320C038P~D

C

C

Link CIS
20.7

60mil single end connection near JACK
JSPK
MOLEX_53398-0890~D

INT_SPK_R1

1

2

1
2
3
4
5
6
7
8

L48
2

C638
22U_1206_16V4Z_V1

+ 5VRUN

10

1

1
2
3
4
5
6
7
8

10

INT_SPK_L1

INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1
INT_SPK_L2
I NT_TWT_L1
INT_SPK_R2
IN T_TWT_R1

C639
22U_1206_16V4Z_V1
1
2

9

9

TRACE>15 mil

BLM21A05_0805

W=40mils
1

1
C627
0.1U_0402_16V4Z~D

2

Link CIS
20.7

1
C628
10U_1206_10V4Z~D

2

C629
0.1U_0402_16V4Z~D

+ 5VRUN

ROUT+

2

9

AUD_LINE_OUT_L

1

C633
2

ROUTLOUT+

5

4

INT_SPK_L1

8

INT_SPK_L2

LIN-

0.1U_0402_16V4Z~D

A UD_GAIN0

R584
@ 10K_0402_5%~D

BYPASS

1

R 585
10K_0402_5%~D

12
10

BY PASS

SHUTDOWN
1

20
13
11
1

GND1
GND2
GND3
GND4

19

1

+ 5VRUN

2

LOUT-

NC
<24,50> SPK_SHUTDOWN#

D8
@ D DA204U

3

INT_SPK_R2

2

INT_SPK_R1

D9
@ D DA204U

LIN+

0.47U_0603_16V4Z
<24> AUD_LINE_OUT_L

18
14

A UD_GAIN1

C 632
1

3

D6
@ D DA204U

3

RIN-

D7
@ D DA204U

2

GAIN1
17

0.1U_0402_16V4Z~D

R 583
@ 10K_0402_5%~D

3

C631
2

R582
10K_0402_5%~D

1

1

A UD_GAIN1

2

AUD_LINE_OU T_R

A UD_GAIN0

1

<24> AUD_LINE_OUT_R

2

1

1
GAIN0

2

RIN+

2

7

0.47U_0603_16V4Z

B

2

16
15
6
2

U 18

VDD
PVDD1
PVDD2

C 630
1

INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2

Gain Setting

B

1

2

2

C626
0.1U_0402_16V4Z~D

1

2

3

1

2

GAIN0

1
C634
0.47U_0603_16V4Z

2

GAIN1

AV(inv)

C635
@ 0.1U_0402_16V4Z~D

TI6017A2_TSSOP20

INPUT
IMPEDANCE

0

0

6dB

90K ohm

0

1

10dB

70K ohm

1

0

15.6dB

45K ohm

1

1

21.6dB

25K ohm

A

A

*

Compal Electronics, Inc.
Title

AMP and Phone Jack Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

25

of

54

<20> USBP0<20> USBP0+

D

2

U SBP0_PWR

@ 0_0402_5%~D
2

L2
DLW21SN900SQ2_0805~D
1
2
1
2
4

3

3

@ 0_0402_5%~D
2

R408
1

@ 0_0402_5%~D
2

L30
BLM21PG600SN1D_0805~D
1
2

USBP0_D+

3

4
R7
1

PLACE CHOKE(Resistors)
NEAR CONNECTOR

USBP0_D-

C3
@ 47P_0402_50V8J

1

L27
BLM21PG600SN1D_0805~D
1
2

DESTINATION

USB PORT#
C257
0.1U_0402_16V4Z~D

R8
1

4

C262
150U_D_10VM_R55~D

5

1
+
2

BACK

0

1
J USB1

2

USBP0_VCC
USBP0_DUSBP0_D+
USBP0_GND

1
2
3
4
SUYIN_2569A-04G3T

C4
@ 47P_0402_50V8J

1

BT

2

BACK

3
4

DOG
MOD

5

3

3

R407 @ 0_0402_5%~D
1
2
R6
1

<20> USBP2-

L1
DLW21SN900SQ2_0805~D
1
2
1
2

<20> USBP2+

4

4

3

R5
1

@ 0_0402_5%~D
2

1

<20> USBP3+

4

3

@ 0_0402_5%~D
2

1
+
2

USBP2_VCC
USBP2_DUSBP2_D+
USBP2_GND

1
2
3
4

1

USBP2_DU SBP6_PWR

USBP2_D+
C2
@ 47P_0402_50V8J

R566
1

2

L29
BLM21PG600SN1D_0805~D
1
2

C1
@ 47P_0402_50V8J

L28
BLM21PG600SN1D_0805~D
1
2

1
+
2

J USB3
USBP6_VCC
USBP6_DUSBP6_D+
USBP6_GND

1

2

1
2
3
4
SUYIN_2569A-04G3T

USBP3_D+
@

C8
47P_0402_50V8J

@

C

C7
47P_0402_50V8J

L31
BLM21PG600SN1D_0805~D
1

USBP3_PWR
USBP4_D-

2
1

USBP4_D- <23>

USBP4_D+

3

@ 0_0402_5%~D
2

USBP4_D+ <23>

2
C610
@ 47P_0402_50V8J

C611
@ 47P_0402_50V8J

2
L26
BLM21PG600SN1D_0805~D

1
2
3
4

D H_PORT_PWRSRC
DH_SMBDAT

5
6
7
8
9

DH_SMBCLK

T1
T2
T3
T4
PWR_SRC
SMB_DATA
SMB_ALERT
SMB_CLK
GND

S

D

1

10
11
12
13

DH_SMBDAT

3

Q6
2N7002_SOT23~D

2
G

1

SHILD1
SHILD2
SHILD3
SHILD4

Fox_UB11193-P01-TR~D

2
G

C6
@ 47P_0402_50V8J

D H_POWER_EN#

D

S

D

S

Q1
2N7002_SOT23~D

2
G

<19,34,35,47> CLK_SMB

CLK_SMB

1

3

Q4
2N7002_SOT23~D

2
G

Please link CIS
9.1

DH_SMBCLK

B

Q2
2N7002_SOT23~D

PW R _ SRC

2

D H _POWER_EN

USBP3_VCC
USBP3_DUSBP3_D+
USBP3_GND

2

2
C5
@ 47P_0402_50V8J

D AT_SMB

S

@ 0_0402_5%~D
2

<19,34,35,47> DAT_SMB

D

R9
1

USBP6_D+

3

1

3

R 17
10K_0402_5%~D

3

4

USBP6_D-

<34> DH_MOD_PRES#

1

4

R 27
10K_0402_5%~D

1

<20> USBP6+

+5VSUS

3

B

<20> USBP6-

J D OG
C260
0.1U_0402_16V4Z~D

1

1

@ 0_0402_5%~D
2

L3
DLW21SN900SQ2_0805~D
1
2
1
2

2

+

C 265
150U_D_10VM_R55~D

+5VSUS
R 10
1

Reserved

USBP3_D-

L47
DLW21SN900SQ2_0805~D
1
2
1
2
3

BACK

7

SUYIN_2569A-04G3T

@ 0_0402_5%~D
2

4

6

L25
BLM21PG600SN1D_0805~D

3

4
R 11
1

R565
1

4

2

@ 0_0402_5%~D
2

L4
DLW21SN900SQ2_0805~D
1
2
1
2

<20> USBP4+

USBP1_D- <27>

C461
@ 47P_0402_50V8J

3

<20> USBP3-

<20> USBP4-

C462
@ 47P_0402_50V8J

@ 0_0402_5%~D
2

R 12
1

C

USBP1_D-

1
2
L24
BLM21PG600SN1D_0805~D

C258
0.1U_0402_16V4Z~D

4

USBP1_D+ <27>

C 259
0.1U_0402_16V4Z~D

4

U SBP2_PWR
USBP1_D+

C 263
150U_D_10VM_R55~D

<20> USBP1-

L44
DLW21SN900SQ2_0805~D
1
2
1
2

C261
150U_D_10VM_R55~D

J USB2

<20> USBP1+

D

Reserved

R318
100K_0402_5%~D

3
2
1

1

Q66

Follow LK2 and need confirm final SPEC
FDS4435_SO8~D

U SBP6_PWR
Z2501

TPS2042ADR_SO8~D

D

U SBP0_PWR
A

5
6
7
8

0.1U_0402_16V4Z~D

1

2

1
2
3
4

GND
IN
EN1#
EN2#

OC1#
OUT1
OUT2
OC2#

8
7
6
5

D H_PORT_PWRSRC

1

Q9
2N7002_SOT23~D
2
D H _ POWER_EN <33>
G

3

2

1

D H _ PWR_OC#

2

R 316
10K_0402_5%~D
D H _P WRSRC_OC

D H _PW RSRC_OC <33>

A

D
Q64
2N7002_SOT23~D

2
G

R307
100K_0402_5%~D

USB_OC0# <20>

C9
0.1U_0805_50V7M~D

1

@ R AY _RUE250

U 31

C269

2

D H _PW RSRC

S

U SBP2_PWR

+5VSUS

1

+ 3VRUN

F2

3

2

2

L5
BLM21PG600SN1D_0805~D

D H _F USE_PWRSRC

2

USB_OC3# <20>

1

2

1

USB_OC6# <20>

F1
1.8A_33VDC_SMD185~D
1

R306
100K_0402_5%~D
1
2

8
7
6
5

1

0.1U_0402_16V4Z~D

OC1#
OUT1
OUT2
OC2#

C292

1

C268

GND
IN
EN1#
EN2#

0.022U_0603_50V4Z~D

U 32
1
2
3
4

4

R317
100K_0402_5%~D
Z2502
2
1

U SBP3_PWR
+5VSUS

S

USB_OC2# <20>

Compal Electronics, Inc.

TPS2042ADR_SO8~D
Title

USB(2.0) Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<33> USB_EN#

5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

26

of

54

5

4

3

2

1

TOP view
+3VSUS

1

1

L43
D

D

C459
0.1U_0402_16V4Z~D

1

2

BT_PWR

2

BLM11A601S_0603~D

10
FOX_HS6210_10P
JBT
10
9
8
7
6 12
5 11
4
3
2
1

<38> BT_ACTIVE
<32> COEX2_WLAN_ACTIVE
<32,34> HW_RADIO_DIS#
<32> COEX1_BT_ACTIVE

T2
PAD
@

R412
@10K_0402_5%~D
2
1

<26> USBP1_D<26> USBP1_D+

COEX2_WLAN_ACTIVE
HW_RADIO_DIS#
COEX1_BT_ACTIVE
COEX3
USBP1_DUSBP1_D+

C

JST_SM10B-SRSS-TB~D
C

+3VSUS

1

2

R454
@ 10K_0402_5%~D

C527
@22P_0402_50V8J~D

AMP_3-1612118-0~D

2

7/28 Changed to NP
by Dell's require

B

Link CIS
12.2

2

<24> MDC_AC_BITCLK

MDC_AC_BITCLK_TERM

1

R462
@ 10_0402_5%~D

C525
0.1U_0402_16V4Z~D

2

1

2

ICH_AC_SDOUT <20,24>
ICH_AC_RST# <20,24>
Z2604
2

MDC_SDIN
1

<20> ICH_AC_SDIN1

W=20 mil

1

B

R458
@ 10_0402_5%~D
1

R457
33_0402_5%~D
1
2

<20,24> ICH_AC_SYNC

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

ICH_AC_SDOUT_MDCTERM

Z2602

AUDIO_PWDN MONO_OUT/PC_BEEP
MONO_PHONE
AGND
RESERVED
AUXA_RIGHT
GND
AUXA_LEFT
+5V
CD_GND
RESERVED
CD_RIGHT
RESERVED
CD_LEFT
PRIMARY_DN
GND
RESERVED
3.3Vaux
RESERVED
GND
AC97_SYNC
3.3Vmain
AC97_SDATA_IN1 AC97_SDATA_OUT
AC97_SDATA_IN0
AC97_RESET#
GND
GND
AC97_BITCLK
AC97_MSTRCLK

R463
0_0402_5%~D
2
1

+3VSUS

R449
10K_0402_5%~D
1
2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

C159
4.7U_1206_16V6K~D

JMDC
MDM_MONO_PHONE

2

1

C526
@10P_0402_50V8J~D

2

1

C530
@10P_0402_50V8J~D

A

A

Compal Electronics, Inc.
Title

BT PORT and MDC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

27

of

54

5

4

3

2

+3VSRC

LAN_CTRL_1P2V

V_1P2_LAN

3

Q65
1@ BCP69_SOT-223

1

LAN_CTRL_2P5V 1

1

1

2

1

C279
0.1U_0402_16V4Z~D

2

C270
0.1U_0402_16V4Z~D

2

C312
0.1U_0402_16V4Z~D

C344
10U_1206_6.3V7K~D

1

Signal

2

4401
No pullup for 16KB

Pullup for 376KHz mode

LAN_EEDATA_SPROM_CS

Pullup for 16KB

No pullup

5

1

P10 LAN_EEDATA_SPROM_CS
M10 LAN_EECLK_SPROM_CLK
H12 LAN_GPIO0
K13 LAN_EEPROM_W
J13 LAN_GPIO2

T8

@ PAD

T7

@ PAD

V_3P3_LAN

LINKLEDB
SPD100LEDB
SPD1000LEDB
TRAFFICLEDB

G13
H13
G12
G14

PLLVDD2
NC

H14
P7

LINK_LED_10#
LINK_LED_100#
LINK_LED_1000#
LAN_ACT#

LINK_LED_10# <29>
LINK_LED_100# <29>
LINK_LED_1000# <29>
LAN_ACT# <29>

IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
PCI_CLK

TCK
TDI
TDO
TMS
TRST

C12
D12
B12
A12
D11

V_1P2_PLLVDD_PHY

+3VRUN

A7
B3
C5
E1
E4
G1
K3
L4
N6
P2

+3V_LOM_PCI
R310
4.7K_0402_1%~D
LAN_TRST# 2
1

C349
10U_1206_6.3V7K~D

2

1

V_2P5_LAN
XTALVDD
XTALO
XTALI

INTA
PCI_RST
GNT
REQ

VAUXPRSNT
M66EN
PME

J14
N10
N11

SO
SI
SCLK
CS

G11
E10
E11
H11

BIASVDD
RDAC

A14
D10

XTALO
XTALI

X1
25MHz_20P_1BX25000CK1A~D
2
1
2
2

C18
22P_0402_50V8J~D

1

1

LAN_SMBCLK
LAN_SMBDATA

Place within 50 mils of
ASIC pin D10
8-10mils trace width

4

C34
22P_0402_50V8J~D

5705M_CLKRUN#

LAN_BIAS
LAN_RDAC

2@ BCM4401

2

1

V_3P3_LAN

Place within 100 mils to pins N10 and N11

A10
C9

K14
L13
P11

V_2P5_LAN

2

2
L35
BLM11A601S_0603~D

V_2P5_LAN

1

C271
1000P_0402_50V7K~D

OR
BCM4401

VDDIO-PCI_A7
VDDIO-PCI_B3
VDDIO-PCI_C5
VDDIO-PCI_E1
VDDIO-PCI_E4
VDDIO-PCI_G1
VDDIO-PCI_K3
VDDIO-PCI_L4
VDDIO-PCI_N6
VDDIO-PCI_P2
VDDP_K14
VDDP_L13
VDDP_P11

A11
F11
K12
L12

VDDIO_A11
VDDIO_F11
VDDIO_K12
VDDIO_L12

C8
H4
H10
J4
K4
J11
K11
L7
L8

CSTSCHG
CLKRUN
NC_H10
NC_J4
NC_K4
NC_J11
NC_K11
NC_L7
NC_L8

1@ BCM5705M_FBGA196~D

B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13

AVDDL_F12
AVDDL_F13
AVDD_F14
AVDD_A13

F12
F13
F14
A13

NC_L11
NC_L14
NC_M8
NC_M9
LOW_POWER
NC_N8
NC_N9
NC_P9

L11
L14
M8
M9
M11
N8
N9
P9

POP
5705

R296
1@ 1K_0402_5%~D
2
1

U33
8
7
6
5

LAN_EEPROM_W
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS

VCC
WP
SCL
SDA

1
2
3
4

A0
A1
NC
GND

1@ AT24C256N-10SC_SO8

V_3P3_LAN
U34

LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK
LAN_SPROM_DOUT
LAN_SPROM_DIN

1
2
3
4

CS
SK
DI
DO

VCC
NC
ORG
GND

8
7
6
5

B

2@ AT93C86-10SC-2.7_SOIC8~D

POP
4401

1
L36
BLM11A601S_0603~D
1
2

AVDD1P2
AVDD2P5

5705M_LOWPWR
R313

2

1

1
2

1

R300
1

2
V_2P5_LAN
L6
1@BLM11A601S_0603~D

Place within 100 mils of ASIC
pins, 10-20mils trace width

1@ 0_0603_5%~D
A

2

1
1

2
V_1P2_LAN

2
2

R308

LAN_LOW_PWR <34>

2@ 0_0402_5%~D

LAN_SPROM_DOUT
LAN_SPROM_DIN

2@ 0_0402_5%~D

2@ BCM4401

Compal Electronics, Inc.

Should be pulled down for both 4401 and 5705M

Place within 100 mils of ASIC
pin A14, 10mils trace width

Title

ETHERNET

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

R299
4.7K_0402_5%~D
2
1

R302
@ 10K_0402_5%~D
2
1

BCM5705M

VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9
VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9
VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9
VSS_F10
VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9
VSS_G10
VSS_H9
VSS_K2
VSS_L6
VSS_L9
VSS_M6
VSS_M12
VSS_M13
VSS_N1
VSS_N12
VSS_N13

C277
1@ 0.1U_0402_16V4Z~D

VDDC_E12
VDDC_H5
VDDC_H6
VDDC_H7
VDDC_H8
VDDC_J5
VDDC_J6
VDDC_J7
VDDC_J8
VDDC_J9
VDDC_J10
VDDC_K5
VDDC_K6
VDDC_K7
VDDC_K8
VDDC_K9
VDDC_K10
VDDC_L5
VDDC_L10
VDDC_M14
VDDC_N14
VDDC_P8
VDDC_P12
VDDC_P13
VDDC_P14

2

1

+3VRUN

E12
H5
H6
H7
H8
J5
J6
J7
J8
J9
J10
K5
K6
K7
K8
K9
K10
L5
L10
M14
N14
P8
P12
P13
P14

1

2

P1
G2
A1

U2B

C273
1U_0805_10V6K~D

V_2P5_LAN

1

OR
BCM4401

C321
@ 8.2P_0402_50V8J~D
CLK_82540_TERM

1

V_3P3_LAN

1@ BLM11A601S_0603~D

BCM5705M

1@ BCM5705M_FBGA196~D
R319
@ 10_0402_5%~D

1

R548 is poped for 4401 with AT93C86 (16KB)
R548 is poped for 5705M EEPROM 376KHz mode

C20
1@ 0.1U_0402_16V4Z~D

J12
F4
A6

B11
C11 LAN_CTRL_2P5V
C10

2

H2
C2
J3
C3

1

2

1

LAN_SMBCLK <32>
LAN_SMBDATA <32>

2

GPIO0
GPIO1
GPIO2

LAN_SMBCLK
LAN_SMBDATA

V_1P2_LAN

2

EEDATA
EECLK

V_2P5_LAN

LAN_CTRL_1P2V

R321

LAN_AUXPWR

SYS_PME#

A4
F2
F1
G3
H3
H1
J2
A2
J1
A3

CBE3
CBE2
CBE1
CBE0

1

2

5705M

LAN_EECLK_SPROM_CLK

V_1P2_LAN

1

PCI_PIRQC#
PCIRST_1#
PCI_GNT4#
PCI_REQ4#

C4
F3
L3
M4

1

2

C293
0.1U_0402_16V4Z~D

1

2

C285
0.1U_0402_16V4Z~D

1

2

C309
0.1U_0402_16V4Z~D

2

C318
0.1U_0402_16V4Z~D

C306
0.1U_0402_16V4Z~D

1

C314
0.1U_0402_16V4Z~D

1

C307
0.1U_0402_16V4Z~D

C326
0.1U_0402_16V4Z~D

C274
0.1U_0402_16V4Z~D

1

2

C

L38

VESD1
VESD2
VESD3

LAN_TX3+ <29>
LAN_TX3- <29>
LAN_TX2+ <29>
LAN_TX2- <29>
LAN_RX1+ <29>
LAN_RX1- <29>
LAN_TX0+ <29>
LAN_TX0- <29>

1

REGSUP25
REGCTL25
REGSEN25

B9
B10
A9

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_RX1+
LAN_RX1LAN_TX0+
LAN_TX0-

2@ BLM11A601S_0603~D

REGSUP12
REGCTL12
REGSEN12

E13
E14
D13
D14
C13
C14
B13
B14

10K_0402_5%~D

PCI_PIRQC#
PCIRST_1#
PCI_GNT4#
PCI_REQ4#

R303
1K_0402_5%~D
2
1

2

1

2

V_3P3_LAN
TRD3+
TRD3TRD2+
TRD2TRD1+
TRD1TRD0+
TRD0-

SMB_CLK
SMB_DATA

CK_33M_LANPCI

1

2

C311
2@ 0.01U_0402_16V7K~D

<20,30>
<20>
<20>
<20>

V_3P3_LAN

1

2

R312
2@ 10K_0402_5%~D

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

R49
100_0603_5%~D
PCI_AD16
1
2 LAN_IDSEL
PCI_FRAME#
<20,30,32> PCI_FRAME#
PCI_IR DY#
<20,30,32> PCI_IRDY#
PC I_TRDY#
<20,30,32> PCI_TRDY#
PCI_DEVSEL#
<20,30,32> PCI_DEVSEL#
PCI_STOP#
<20,30,32> PCI_STOP#
PCI_PERR#
<20,30,32> PCI_PERR#
PCI_SERR#
<20,30,32> PCI_SERR#
PCI_PAR
<20,30,32> PCI_PAR
CK_33M_LANPCI
<6> CK_33M_LANPCI

<30,32,33> SYS_PME#

2

1

2

1

L39

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

R311
1.24K_0402_1%~D
2
1

B8
A8
C7
C6
B6
B5
A5
B4
B2
B1
C1
D3
D2
D1
E3
K1
L2
L1
M3
M2
M1
N2
N3
P3
N4
P4
M5
N5
P5
P6
M7
N7

B

A

1

1

2

U2A
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

C

<20,30,32>
<20,30,32>
<20,30,32>
<20,30,32>

2

V_2P5_LAN
C333
10U_1206_6.3V7K~D

<20,30,32> PCI_AD[0..31]

2

2

C313
0.1U_0402_16V4Z~D

2

2

C320
0.1U_0402_16V4Z~D

2

1

C283
0.1U_0402_16V4Z~D

C332
10U_1206_6.3V7K~D

1

2

2
4

1

2

C323
0.1U_0402_16V4Z~D

1

2

C340
0.1U_0402_16V4Z~D

1

2

C341
0.1U_0402_16V4Z~D

1

2

C330
0.1U_0402_16V4Z~D

Place within 100 mils to pins H14

2

C316
0.1U_0402_16V4Z~D

V_3P3_LAN

D

1

C335
0.1U_0402_16V4Z~D

1
+3V_LOM_PCI

1

1

20mils trace width

2

1

C291
0.1U_0402_16V4Z~D

E
3

C25
10U_1206_6.3V7K~D

C
4

3

B
1

1

Q5
1@ BCP69_SOT-223

1@ : Nopop Nimitz 4401
2@ : Nopop Bejing 5705M

2

C328
0.1U_0402_16V4Z~D

1

2

2

C267
10U_1206_6.3V7K~D

1

2

2
4
C266
10U_1206_6.3V7K~D

1

2

C275
0.1U_0402_16V4Z~D

1

2

C278
0.1U_0402_16V4Z~D

2

C286
0.1U_0402_16V4Z~D

1

C315
0.1U_0402_16V4Z~D

1

1

C310
0.1U_0402_16V4Z~D

2

1

2

C272
0.1U_0402_16V4Z~D

V_1P2_PLLVDD_PHY
C17
0.1U_0402_16V4Z~D

V_1P2_LAN

C11
2.2U_0805_16VFZ~D

D

L33
BLM11A601S_0603~D
1
2

2

C282
0.1U_0402_16V4Z~D

<39> ENAB_3VLAN

C
2

V_3P3_LAN
2

C281
0.1U_0402_16V4Z~D

3

G

4

BCP69

L37
BLM31A260SPT_1206~D
1
2
C343
10U_1206_6.3V7K~D

S

VAUX_LAN

C350
10U_1206_6.3V7K~D

D

Q18
SI3456DV-T1_TSOP6~D
6
5
2
1

1

V_2P5_LAN

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

28

of

54

5

4

3

2

1

JLOM

V_2P5_LAN
V_2P5_LAN
V_3P3_LAN
R20
R19
R22
R21
R24
R23
R26
R25

Magnetics pop options
4401: H1238
5705M: H5015D

LAN_TX0LAN_TX0+
LAN_RX1LAN_RX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

49.9_0603_1%~D
2
49.9_0603_1%~D
2
49.9_0603_1%~D
2
49.9_0603_1%~D
2
2 1@ 49.9_0603_1%~D
2 1@ 49.9_0603_1%~D
2 1@ 49.9_0603_1%~D
2 1@ 49.9_0603_1%~D

1
1
1
1
1
1
1
1

1

24

B2

B1

B1

A2

Z2805

1:1

1
2
3
4
5
6
7
8

JPH_RJ
LAN_TX3-

<28> LAN_TX32

1

2

23

NB_LAN_TX3-

RJ_RING
RJ_TIP

1
2

C16
0.01U_0402_16V7K~D
1@

LAN_TX3+

<28> LAN_TX3+

5

3

22

21

Z2806

20

1

NB_LAN_TX21

5

R33
10K_0402_5%~D
2
1

<28> LAN_ACT#

1:1

LAN_TX2-

C14
0.01U_0402_16V7K~D
1@

A3 LED_10_GRN#

A2

P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P1_8 SGND1
SGND2
RJ45/LED

A1 LED_100_ORG#

D

17
18

P2_2
P2_1
RJ11
FOX_JM34F23-P3552-TR~D

3

S

V_3P3_LAN
LAN_ACTLED_YEL#

2

R32
200_0603_5%~D

D

2
G

<32> WLAN_LED_ACTIVITY
1

1

10
9

B3 LAN_ACTLED_YEL#

NB_LAN_TX3+

T5

4

2

RJ_TIP
RJ_RING

6
7

6
7
5

JST_SM05B-SRSS-TB~D

T1

<28> LAN_TX2-

1
2

YEL
GRN
AMBER

NB_LAN_TX+
NB_LAN_TXNB_LAN_RX+
NB_LAN_TX2+
NB_LAN_TX2NB_LAN_RXNB_LAN_TX3+
NB_LAN_TX3-

L32
D

B2

Q3
2N7002_SOT23~D
V_3P3_LAN

R600
10K_0402_5%~D

C

6

19

T2

1

NB_LAN_TX2+

R297
10K_0402_5%~D

T6

7

18

Z2807

17

NB_LAN_RX-

2

LAN_TX2+

<28> LAN_TX2+

2

C

1:1
<28> LINK_LED_10#
8

V_3P3_LAN
1

C13
0.01U_0402_16V7K~D

D11
RB495D_SOT23~D

R293
10K_0402_5%~D

3

2

1

2

2

1

LAN_RX1-

<28> LAN_RX1-

<28> LINK_LED_100#
9

16

T3

NB_LAN_RX+

LINK_LED_1000# <28>

T7

D12

V_3P3_LAN

10

15

Z2808

R305

3

1

LAN_RX1+

<28> LAN_RX1+

1:1

1

2

1
2

B

11

14

NB_LAN_TX-

C15
0.01U_0402_16V7K~D

1@ RB495D_SOT23~D
2

2

1@ 10K_0402_5%~D

3

LAN_TX0-

<28> LAN_TX0-

D10
RB495D_SOT23~D

B

1

R292
200_0603_5%~D
1
2

LED_100_ORG#

R298
200_0603_5%~D
1
2

LED_10_GRN#

1

V_3P3_LAN

R304
10K_0402_5%~D
1
2

Q63
LAN_TX0+

12

13

T4
1@ H5015D~D

DTC144EKA

NB_LAN_TX+

T8

<32> LED_WLAN5_RADIOSTATE

2

DTC144EKA_SOT23~D

47K

2@ H1238
R3

2

1 2@ 0_0402_5%~D

NB_LAN_TX3-

R4

2

1 2@ 0_0402_5%~D

2

3

NB_LAN_TX2+

R1

2

1 2@ 0_0402_5%~D

B

E

NB_LAN_TX2-

R2

2

1 2@ 0_0402_5%~D

V_3P3_LAN
R601
10K_0402_5%~D
2
<32> LED_WLAN24_RADIOSTATE

2

DTC144EKA_SOT23~D

47K

47K
R602
10K_0402_5%~D

A

GND
CHASIS

2

1@ : Nopop Nimitz 4401
2@ : Nopop Bejing 5705M

Q62

R294
10K_0402_5%~D
2
1
1

C264
1000P_1808_3KV7K~D
1
2

4
3
2
1

RN6
75_1206_8P4R_5%~D

R295
10K_0402_5%~D
1
2

3

C

1

NB_LAN_TX3+

1

3

47K

1

A

R309
10K_0402_5%~D
2
1

5
6
7
8

<28> LAN_TX0+

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

LAN TRANSFOMER
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

29

of

54

5

4

3

2

U9B

R470
1
1
R481

P3
R3
J2
T1
P5
P6
H3

CBS_GRST#

H2

100_0603_5%~D
CBS_IDSEL
2

L5

2
@ 10K_0402_5%~D
H1

CSTSCHG/BVD1
CCLKRUN/WP
CBLOCK/A19
CINT/READY

GRST

CAUDIO/BVD2
CCD2/CD2#
CCD1/CD1#

IDSEL

CVS2/VS2#
CVS1/VS1#
CRSVD/D2
CRSVD/A18
CRSVD/D14

PCICLK

2

<6> CK_33M_CBPCI

IRDY
PERR
REQ
SERR
STOP
TRDY
PCIRST

R163
@ 10_0402_5%~D

CBS_CAUDIO
CBS_CCD2#_INTERNAL
CBS_CCD1#_INTERNAL

F12
B10

CBS_CVS2
CBS_CVS1

F8
F17
J18

CBS_CSTSCHNG <31>
CBS_CCLKRUN# <31>

CBS_CBLOCK#
CBS_CINT#

E18
C10
F10
C9
L17

2

CBS_CBLOCK# <31>
CBS_CINT# <31>
CBS_CAUDIO <31>

CBS_CVS2 <31>
CBS_CVS1 <31>

CBS_RSVD/D2
CBS_RSVD/A18
CBS_RSVD/D14

CBS_RSVD/D2 <31>
CBS_RSVD/A18 <31>
CBS_RSVD/D14 <31>

1 R502
1K_0402_5%~D
1 R486
1K_0402_5%~D

1

2

2

1

C544
0.047U_0402_10V4M~D

1

1

C542
0.047U_0402_10V4M~D

1

2

C536
0.047U_0402_10V4M~D

1

C139
@ 4.7P_0402_50V8C~D

2

2

V11

IEEE1394_TPB0N

W11

IEEE1394_TPB1P

V14

IEEE1394_TPB1N

W14

IEEE1394_TPBIAS0

U12

IEEE1394_TPBIAS1

U15

VD1/VCCD0
VD0/VCCD1
TPA1N

VD3/VPPD0
VD2/VPPD1

TPB0N

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

TPB1P
TPB1N
TPBIAS0
TPBIAS1

VR_EN

RI_OUT/PME

+1.8V_CBSD

E6
B5

CBS_VCCD0# <31>
CBS_VCCD1# <31>

A4
C5

CBS_VPPD0 <31>
CBS_VPPD1 <31>

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

RSVD
RSVD
RSVD
RSVD
SC_GPIO5
RSVD
SC_GPIO6
SC_GPIO1
SC_GPIO0

SCL
SDA
PHY_TEST_MA
SKT_SEL0
SKT_SEL1

H5
G3

TI_SUSPEND#_INTERNAL

2

J3

SYS_PME#

E2

CBS_SPK

F5
G6
F3
F2
G5
F1
H6

PCI_PIRQD#
PCI_PIRQC#
PCI_REQB#
IRQ_SERIRQ
CBS_RI#
PCI_GNTB#
CBS_MFUNC6

E3
D1

CBS_SCL
CBS_SDA

P18

PHY_TEST_MA

U10

CBS_TEST0

R10

CBS_TEST1

SC_CD
SC_RST
SC_CLK
SC_DATA
SC_GPIO3
SC_GPIO2
SC_GPIO4

1

2

1

1

2

2

C520
0.1U_0402_16V4Z~D

2

C560
0.1U_0402_16V4Z~D

2

1

C543
0.047U_0402_10V4M~D

2

1

C556
0.047U_0402_10V4M~D

2

1

C533
0.047U_0402_10V4M~D

2

1

C524
0.047U_0402_10V4M~D

2

1

1

+3V_CBSD

2

1

+3V_CBSD

+3V_CBSD
TI_SUSPEND# <34>

SYS_PME# <28,32,33>
CBS_SPK <24>
PCI_PIRQD# <20,32>
PCI_PIRQC# <20,28>
PCI_REQB# <20>
IRQ_SERIRQ <20,21,33>
CBS_RI# <21>
+3V_CBSD
PCI_GNTB# <20>
1
2
R455
10K_0402_5%~D

+3V_CBSD
2

1
4.7K_0402_5%~D
1
200_0603_5%~D
1
200_0603_5%~D

R504
2
R450
2
R447
CK_48M_SCR

XI

R18

PCI4510XI

XO

R19

PCI4510XO

B

CK_48M_SCR <6>
R453
@ 10_0402_5%~D

X3
24.576MHz_16P_1BG24576CKIA~D
1
2

PCI7510GHK_PBGA209~D

C522
0.047U_0402_10V4M~D

2

1

C521
0.047U_0402_10V4M~D

2

1

C172
10U_0805_10V4M~D

1

2

C

R446
10K_0402_5%~D
2
1

+3V_CBSD

C173
10U_0805_10V4M~D

2

C532
0.1U_0402_16V4Z~D

C562
0.1U_0402_16V4Z~D

A

1

1

1V8_VR_EN#

+1.8V_CBSD

+3VSUS

2

1

R451
0_0402_5%~D
2
1

1

L15
BLM21A601SPT_0805~D
1
2

2

R452
@ 10K_0402_5%~D
2
1

F6

CLK_48

B7
C7
F7
A6
B6
E7
C6

E1
K1
N1
W6
P19
K19
G19
A15
A10
A7

1

D15
RB751V_SOD323~D

FILTER0
FILTER1

M14
N17
N18
N19
M15
M17
M18
M19

SCR_DETECT
SCR_IF_RST
SCR_IF_CLK
SCR_IF_DATA
SCR_IF_PWR
SCR_IF_GPIO0
SCR_IF_GPIO1

ANALOGGND
ANALOGGND
ANALOGGND

VSPLL/RSVD

2

SCR_IF_GPIO4
SCR_IF_GPIO3
SCR_IF_GPIO2

SUSPEND

VDPLL

T19
R17

SCR_IF_GPIO5

ANALOGVCC
ANALOGVCC
ANALOGVCC

SPKROUT

P15

N15

<31> SCR_IF_GPIO5

G2
L18

TPB0P

N14

1

L1
W5

TPA1P

R11
U13
U14

FILTER0
FILTER1

G14
A11

This shall be output

TPA0N

W15

IEEE1394_TPB0P

VR_PORT
VR_PORT

TPA0P

U11
R12
R13

C557
0.1U_0402_10V6K~D
1
2

<31> SCR_DETECT
<31> SCR_IF_RST
<31> SCR_IF_CLK
<31> SCR_IF_DATA
<31> SCR_IF_PWR
<31> SCR_IF_GPIO0
<31> SCR_IF_GPIO1

+3V_CBSA

L13
BLM21A601SPT_0805~D
1
2
C164
10U_0805_10V4M~L

2

C160
0.047U_0402_10V4M~D

+3VSUS

V15

+3V_CBSA

<31> SCR_IF_GPIO4
<31> SCR_IF_GPIO3
<31> SCR_IF_GPIO2

CK33M_CBS_TERM

B

W12

IEEE1394_TPA1P

CBS_CCD1# <31>
CBS_CCD2# <31>

1

PCI7510GHK_PBGA209~D

2

CBS_VCC
VCCCB
VCCCB

R1

V12

IEEE1394_TPA0N

IEEE1394_TPA1N

CBS_CRST# <31>
CBS_CFRAME# <31>
<31> IEEE1394_TPBIAS0
CBS_CIRDY# <31>
2
1 R515
CBS_CTRDY# <31>
@ 1K_0402_5%~D
CBS_CDEVSEL# <31>
CBS_CSTOP# <31>
2
1
CBS_CPERR# <31>
CBS_CSERR# <31>
C167
CBS_CPAR <31>
1U_0805_10V6K~D
CBS_CREQ# <31>
+3V_CBSA
R494
CBS_CGNT# <31>
CBS_CCLK
2
1
CBS_CCLK <31>
47_0603_5%~D

CBS_CSTSCHNG
CBS_CCLKRUN#

A9
B9

V13

PCI7510

R0

D

C184
22P_0402_50V8J~D

<33> CBS_GRST#
PCI_AD17

PCI_IR DY#
PCI_PERR#
PCI_REQ1#
PCI_SERR#
PCI_STOP#
PC I_TRDY#
PCIRST_CB#

DEVSEL
FRAME
GNT

W13

PCI4510_R1

PC0
PC1
PC2

2

R507
@ 1K_0402_5%~D
2
1

2

R482
0_0402_5%~D
1
2

PCI_IRDY#
PCI_PERR#
PCI_REQ1#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCIRST_CB#

R2
N5
J1

PCI4510_R0

IEEE1394_TPA0P

<31> IEEE1394_TPB0N

C540
@ 270P_0603_50V7K~D

<20,28,32>
<20,28,32>
<20>
<20,28,32>
<20,28,32>
<20,28,32>
<20>

PCI_DEVSEL#
PCI_FRAME#
PCI_GNT1#

PAR

<31>
<31>
<31>
<31>

R516
0_0402_5%~D
1
2

<20,28,32> PCI_DEVSEL#
<20,28,32> PCI_FRAME#
<20> PCI_GNT1#

CRST/RESET
CFRAME/A23
CIRDY/A15
CTRDY/A22
CDEVSEL/A21
CSTOP/A20
CPERR/A14
CSERR/WAIT#
CPAR/A13
CREQ/INPACK#
CGNT/WE#
CCLK/A16

V10
W10
P9

VCCP
VCCP

2
1
R496
@ 1K_0402_5%~D

CBS_CRST#
B13
CBS_CFRAME#
B15
CBS_CIRDY#
F13
CBS_CTRDY#
E14
CBS_CDEVSEL#
A16
CBS_CSTOP#
E17
CBS_CPERR#
F15
CBS_CSERR#
E10
CBS_CPAR
F14
CBS_CREQ#
B12
CBS_CGNT#
D19
C15 CBS_CCLK_INTERNAL

CBS_PC0
CBS_PC1
CBS_PC2

1

<31> IEEE1394_TPA0N

C566
@ 270P_0603_50V7K~D

<20,28,32> PCI_PAR

W4

C/BE3
C/BE2
C/BE1
C/BE0

CNA

G1
M1
R1
W8
L19
H19
E19
A13
A8
A5

C555

PCI_PAR

L6
P2
U5
V7

P17

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C531

C

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PHY_CNA

2
R487
6.34K_0805_0.5%~D
<31> IEEE1394_TPA0P

CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#

CPS

1

<31> IEEE1394_TPB0P
CC/BE3/REG#
CC/BE2/A12
CC/BE1/A8
CC/BE0/CE1#

P10

C538

R495
@ 1M_0603_5%~D
1
2

PHY_CPS

CK48M_CBS_TERM

R174
0_0402_5%~D
1
2
@

R171
0_0402_5%~D
1
2

R177
0_0402_5%~D
1
2
@

R186
0_0402_5%~D
1
2

@

R483
1K_0402_5%~D
2
1
R510
10K_0402_5%~D
1
2

+3V_CBSD

0.1U_0402_16V4Z~D

CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#

8/12 Changed by
Dell's Require

+3V_CBSA

C541

B11
C14
G15
J15

+3V_CBSD

0.1U_0402_16V4Z~D

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

0.1U_0402_16V4Z~D

E8
C8
B8
E9
F9
F11
E11
C11
A12
C12
E12
C13
A14
E13
B14
F18
G17
F19
G18
H15
H14
H17
H18
J14
J17
K14
J19
K17
K15
L14
K18
L15

R191
0_0402_5%~D
1
2

PCI7510

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

0.1U_0402_16V4Z~D

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

R188
0_0402_5%~D
1
2

D

J5
J6
K2
K3
K5
K6
L2
L3
M2
M3
M6
M5
N2
N3
N6
P1
R6
P7
V5
U6
V6
R7
P8
U7
W7
R8
U8
V8
W9
V9
U9
R9

C185
22P_0402_50V8J~D

CBS_CAD[0..31] <31>

U9A
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

<20,28,32>
<20,28,32>
<20,28,32>
<20,28,32>

1

Remove R756

<20,28,32> PCI_AD[0..31]

1

2

1

2

2

1

C523
@ 4.7P_0402_50V8C~D

8/12 Changed by
Dell's Require
R444
R445
+3V_CBSD
220_0603_5%~D
@ 2.7K_0603_5%~D
CBS_SCL
2
1
2
1
CBS_SDA
2
1
2
1
R165
R164
220_0603_5%~D
@ 2.7K_0603_5%~D

A

Compal Electronics, Inc.
Title

PCMCIA Controller
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

30

of

54

5

4

3

2

1

JCBUS

R468
10K_0402_5%~D
2
1

D

T3
PAD
@
T4
PAD
@

NC_SCR_C4

R194
@ 0_0402_5%~D
SCR_C4_C
2
1

NC_SCR_C8

R193
@ 0_0402_5%~D
2
1 SCR_C8_C

R464
10K_0402_5%~D
2
1
R202
10K_0402_5%~D
2
1

R172
SCR_DETECT

2

1

SCR_DETECT_C

0_0402_5%~D
C175
4.7U_1206_16V6K~D

1

@

2

R173
10K_0402_5%~D

CBS_CAUDIO
CBS_CC/BE3#
CBS_CREQ#
CBS_CSERR#

+5VSUS

CBS_CRST#
CBS_CVS2
SCR_VPP_PIN66
CBS_CAD19
CBS_CAD17
SCR_DATA_C
CBS_CFRAME#
CBS_CTRDY#
SCR_C8_C

R185
@ 0_0402_5%~D
1
2

SCR_IF_GPIO1

C656
1
2

SCR_IF_GPIO2

100P_0402_50V8K~D

Depop if support Smart Card
<30> SCR_DETECT

SCR_IF_GPIO0

SCR_VCC_C
1

2

R203
10K_0402_5%~D
2
1

SCR_IF_GPIO3

R201
10K_0402_5%~D
2
1

SCR_IF_GPIO4

R200
10K_0402_5%~D
2
1

SCR_IF_GPIO5

R461
10K_0402_5%~D
2
1

SCR_IF_PWR

CBS_VPP
CBS_VCC

CBS_CDEVSEL#
CBS_CSTOP#
CBS_CBLOCK#
CBS_RSVD/A18
CBS_CAD16
CBS_CAD15
CBS_CAD13
CAGE50_GND
CBS_CVS1
CBS_CAD10
CBS_CAD8
CBS_RSVD/D14
CBS_CAD6
CBS_CAD4
CBS_CAD2
CBS_CCD1#

R204
0_0603_5%~D
1
2

Place near ncn6000

81
83
85

<30> IEEE1394_TPBIAS0

LOUT_H
LOUT_L

L14
22U_LQH43MN220J01K_2OHM_1812~D
1
2

SCR_VCC_C
SCR_DATA_C
SCR_CLK_C
SCR_RST_C
SCR_DETECT_C

<30>
<30>
<30>
<30>

NCN6000_TSSOP20~D

2

C528
270P_0603_50V7K~D

2

1

R189
22K_0402_5%
2
1

2

1

SCR_CLK_C
C154
56P_0402_50V8J~D

2

1

R187
22K_0402_5%
2
1

1

C151
470P_0402_50V7K~D

2

SCR_RST_C
C149
0.1U_0402_16V4Z~D

2

C150
100P_0402_50V8K~D

1

R170
10K_0402_5%~D
2
1

1

C182
0.1U_0402_16V4Z~D

C174
10U_1206_6.3V7K~D

SCR_VCC_C

2

1

5

1

AVCC1
AVCC2
AVCC3

12V

C144
0.1U_0402_16V4Z~D

2
AVPP
+5VSUS

1

5
6
C156
0.1U_0402_16V4Z~D

5V_1
5V_2
VCCD0#
VCCD1#
VPPD0
VPPD1

C155
0.1U_0402_16V4Z~D

7

2

3.3V_1
3.3V_2

SHDN#

1

3
4

16

+3VSUS

GND

2

A

10

OC#

1
2
15
14

C143
4.7U_1206_16V6K~D

2
C142
0.1U_0402_16V4Z~D

9

C145
4.7U_1206_16V6K~D

+12V

13
12
11

1

2

CBS_VCCD0#
CBS_VCCD1#
CBS_VPPD0
CBS_VPPD1

1

2

1

2

C136
1000P_0402_50V7K~D

U10

SHDN#

2

AVPP:150mA

2

8

AVCC:1A

VPPD0

1

0

0

1

0

1

1

1

0

1

1

1

0

X

X

SHDN#
CBS_VCCD0# <30>
CBS_VCCD1# <30>
CBS_VPPD0 <30>
CBS_VPPD1 <30>

VPPD1

CBS_VPP
CBS_VCC

R205
@ 0_0603_5%~D

C

8

5

4

6
7

3
2

8

1

8
7
6
5

4
3
2

TPA0+
TPA0TPB0+
TPB0-

1

SGND4
SGND3
SGND2
SGND1

4
3
2
1

4
3
2
1
MOLEX_54515-0411~D

R144
@ 0_0402_5%~D
1
2
R145
@ 0_0402_5%~D
1
2
R146
@ 0_0402_5%~D
1
2
R147
@ 0_0402_5%~D
1
2

CBS_VCC
1

CBS_VPP

1

6
7

CBS_CCLK
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#

C135
0.1U_0402_16V4Z~D

1

C137
10U_1206_6.3V7K~D

TPS2211VCC

D

82
84
86

857CM-0009~D

Place near connector

L10
BLM31A260SPT_1206~D
1
2

CBS_CINT#
CBS_CGNT#
CBS_CPERR#
CBS_CPAR
CBS_CC/BE1#
CBS_CAD14
CBS_CAD12
CAGE10_GND
CBS_CAD11
CBS_CAD9
CBS_CC/BE0#
CBS_CAD7
CBS_CAD5
CBS_CAD3
CBS_CAD1
CBS_CAD0

SCR_DETECT_C <34>

J1394

B

Place near NCN6000

82
84
86

CBS_CCLKRUN#
CBS_RSVD/D2
CBS_CAD29
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
SCR_DETECT_C
CBS_CAD23
CBS_CAD22
SCR_VCC_C
CBS_CAD21
CBS_CAD20
SCR_RST_C
CBS_CAD18
CBS_CC/BE2#
SCR_CLK_C
CBS_CIRDY#
CBS_CCLK
SCR_C4_C

FOX_1CA875Q1-T1~D

Z3008

2

81
83
85

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

L7

1

IEEE1394_TPA0P
IEEE1394_TPA0N
IEEE1394_TPB0P
IEEE1394_TPB0N

IEEE1394_TPA0P
IEEE1394_TPA0N
IEEE1394_TPB0P
IEEE1394_TPB0N

+3VSUS

C163
1U_0805_10V6K~D

20
19
18
17
16
15
14
13
12
11

R469
56.2_0603_1%~D
2
1

VBAT
LOUT_H
LOUT_L
PWR_GND
GROUND
CRD_VCC
CRD_IO
CRD_CLK
CRD_RST
CRD_DET

R456
56.2_0603_1%~D
1
2

A0
A1
PGM#
PWR_ON
STATUS
CS#
RESET#
I/O
INT#
CLOCK_IN

Link CIS
10.3

R448
5.1K_0805_5%~D
1
2

1
2
3
4
5
6
7
8
9
10

R480

SCR_IF_GPIO2
SCR_IF_GPIO3
SCR_IF_GPIO0
SCR_IF_PWR
SCR_IF_GPIO1
SCR_IF_GPIO5
SCR_IF_RST
SCR_IF_DATA
SCR_IF_GPIO4
SCR_IF_CLK

<30> SCR_IF_GPIO2
<30> SCR_IF_GPIO3
<30> SCR_IF_GPIO0
<30> SCR_IF_PWR
<30> SCR_IF_GPIO1
<30> SCR_IF_GPIO5
<30> SCR_IF_RST
<30> SCR_IF_DATA
<30> SCR_IF_GPIO4
<30> SCR_IF_CLK

R460
56.2_0603_1%~D
1
2

U17
C

56.2_0603_1%~D
2
1

+3VSUS

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

+3VSUS

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

1

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

CBS_CCD2#
CBS_CAD31
CBS_CAD30
CBS_CAD28
CBS_CSTSCHNG

VCCD1# VCCD0#

1

0

0

1

0

1

1

1

0

1

1

1

0

X

X

CBS_VPP

CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CBLOCK#
CBS_CINT#
CBS_CAUDIO
CBS_CVS2
CBS_CVS1

CBS_VCC

CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
CBS_CCD1#
CBS_CCD2#

Link CIS
22.2

CBS_CAD[0..31] <30>
CBS_CCLK <30>
CBS_CC/BE3# <30>
CBS_CC/BE2# <30>
CBS_CC/BE1# <30>
CBS_CC/BE0# <30>

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

CBS_CRST# <30>
CBS_CFRAME# <30>
CBS_CIRDY# <30>
CBS_CTRDY# <30>
CBS_CDEVSEL# <30>
CBS_CSTOP# <30>
CBS_CPERR# <30>
CBS_CSERR# <30>
CBS_CPAR <30>
CBS_CREQ# <30>
CBS_CGNT# <30>
CBS_CSTSCHNG <30>
CBS_CCLKRUN# <30>
CBS_CBLOCK# <30>
CBS_CINT# <30>
CBS_CAUDIO <30>
CBS_CVS2 <30>
CBS_CVS1 <30>
CBS_RSVD/D14 <30>
CBS_RSVD/D2 <30>
CBS_RSVD/A18 <30>
CBS_CCD1# <30>

B

A

CBS_CCD2# <30>

TPS2211ADBR_SSOP16~D

Compal Electronics, Inc.
Title
SUSPWROK_5V <39,43,45>

CardBus Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

31

of

54

5

4

3

<20,28,30> PCI_AD[0..31]

2

+3VRUN
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

D

+3VRUN

JPCI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

WLAN_LED_ACTIVITY
HW_RADIO_DIS#

<29> WLAN_LED_ACTIVITY
<27,34> HW_RADIO_DIS#

PCI_PIRQD#

<20,30> PCI_PIRQD#

CK_33M_MINIPCI

<6> CK_33M_MINIPCI

PCI_REQ3#

<20> PCI_REQ3#

PCI_AD31
PCI_AD29
@
<27> COEX2_WLAN_ACTIVE
<20,28,30> PCI_C_BE3#

R255
0_0402_5%~D
1
2

PCI_AD27
PCI_AD25
PCI_C_BE3#
PCI_AD23
PCI_AD21
PCI_AD19

CK_33M_MINIPCI
2

PCI_AD17
PCI_C_BE2#
PCI_IR DY#

<20,28,30> PCI_C_BE2#
<20,28,30> PCI_IRDY#

1

R248
@ 10_0402_5%~D

PCI_CLKRUN#
PCI_SERR#

<20,28,30> PCI_SERR#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

<20,28,30> PCI_PERR#
<20,28,30> PCI_C_BE1#

CK_33M_MINPCI_TERM

C

PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
2

1

1

+5VRUN

PCI_AD1

C230
@ 4.7P_0402_50V8C~D

+5VRUN
PCI_CLKRUN#

TIP

RING

8PMJ-3
8PMJ-6
8PMJ-7
8PMJ-8
LED1_GRNP
LED1_GRNN
CHSGND
INTB#
3.3V
RESERVED
GROUND
CLK
GROUND
REQ#
3.3V
AD31
AD29
GROUND
AD27
AD25
RESERVED
C/BE3#
AD23
GROUND
AD21
AD19
GROUND
AD17
C/BE2#
IRDY#
3.3V
CLKRUN#
SERR#
GROUND
PERR#
C/BE1#
AD14
GROUND
AD12
AD10
GROUND
AD8
AD7
3.3V
AD5
RESERVED
AD3
5V
AD1
GROUND
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND
SYS_AUDIO_OUT
SYS_AUDIO_OUT GND
AUDIO_GND
RESERVED
VCC5A

8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5
LED2_YELP
LED2_YELN
RESERVED
5V
INTA#
RESERVED
3.3VAUX
RST#
3.3V
GNT#
GROUND
PME#
RESERVED
AD30
3.3V
AD28
AD26
AD24
IDSEL
GROUND
AD22
AD20
PAR
AD18
AD16
GROUND
FRAME#
TRDY#
STOP#
3.3V
DEVSEL#
GROUND
AD15
AD13
AD11
GROUND
AD9
C/BE0#
3.3V
AD6
AD4
AD2
AD0
RESERVED
RESERVED
GROUND
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED
GROUND
SYS_AUDIO_IN
SYS_AUDIO_IN GND
AUDIO_GND
MCPIACT#
3.3VAUX

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

LED_WLAN24_RADIOSTATE
LED_WLAN5_RADIOSTATE

+5VRUN

PCI_PIRQB#

PCI_PIRQB# <18,20>
V_3P3_LAN

PCIRST_2#

PCIRST_2# <20>

PCI_GNT3#
R250
@ 0_0402_5%~D

D

LED_WLAN24_RADIOSTATE <29>
LED_WLAN5_RADIOSTATE <29>

2

PCI_GNT3# <20>

SYS_PME#
1
2
PCI_AD30

SYS_PME# <28,30,33>
COEX1_BT_ACTIVE <27>
R249
@ 10K_0402_5%~D
2
1

PCI_AD28
PCI_AD26
PCI_AD24
MINIDSEL

1

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

2

C252
0.1U_0402_16V4Z~D

1

2

C253
0.1U_0402_16V4Z~D

1

PCI_AD19

R261
100_0603_5%~D
PCI_PAR <20,28,30>

PCI_FRAME#
PC I_TRDY#
PCI_STOP#

PCI_FRAME# <20,28,30>
PCI_TRDY# <20,28,30>
PCI_STOP# <20,28,30>

PCI_DEVSEL#

PCI_DEVSEL# <20,28,30>
C

PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C_BE0#

PCI_C_BE0# <20,28,30>

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
LAN_SMBCLK
LAN_SMBDATA
MPCI_M66EN

2

R278
1K_0402_5%~D
1

R284
10K_0402_5%~D
1
2

MPCIACT#

+3VSUS

V_3P3_LAN

AMP_1318644-1~D
2

1

2
R264
10K_0402_5%~D

C249
0.1U_0402_16V4Z~D

1

C229
0.1U_0402_16V4Z~D

1

B

2

B

2

2

V_3P3_LAN

D

1

1
D

NIC_MINI_SMBCLK
Q48
2N7002_SOT23~D

1
D

3
S

ICH_SMBCLK

Q49
3 2N7002_SOT23~D

LAN_SMBCLK

S

G

<6,15,16,21> ICH_SMBCLK

LAN_SMBDATA

3
Q53
2N7002_SOT23~D

LAN_SMBDATA <28>

2
G

Q52
2N7002_SOT23~D

2

2

G

+3VSUS

NIC_MINI_SMBDAT

1

2
G

3

S

D

ICH_SMBDATA

S

<6,15,16,21> ICH_SMBDATA

R268
10K_0402_5%~D
1

1

R270
10K_0402_5%~D

LAN_SMBCLK <28>

+3VRUN

A

2

1

2

C232
0.047U_0402_10V4M~D

1

C241
0.047U_0402_10V4M~D

2

1

C227
0.047U_0402_10V4M~D

2

1

2

C246
0.047U_0402_10V4M~D

1

C234
0.047U_0402_10V4M~D

2

1

C242
0.047U_0402_10V4M~D

2

1

2

C247
0.047U_0402_10V4M~D

1

C231
0.047U_0402_10V4M~D

2

1

A

C244
0.047U_0402_10V4M~D

Compal Electronics, Inc.
Title

MINIPCI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

32

of

54

5

4

3

2

1

R182
10K_0402_5%~D
2
1

+3VRUN

1

+3VRUN
U15A

<21>
<21>
<21>
<21>
<25>
<24>

T6
PAD
@
J1397
@ 1.5mm SMT
1
1
2
2
3
3

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_RTE#
SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_RTE#
SIO_RCIN#
NB_MUTE
BEEP

E14
C16
C15
A16
D14
C14
C13
B14

SGPIO40
SGPIO41
SGPIO42
SGPIO43
SGPIO44
SGPIO45
SGPIO46
SGPIO47

DLDRQ1#
DLFRAME#

MACALLEN

DLAD0
DLAD1
DLAD2
DLAD3
DSER_IRQ
DCLKRUN#

DOCK LPC

LDRQ1#
LFRAME#

LPC

LAD0
LAD1
LAD2
LAD3
SER_IRQ
CLKRUN#

8051
GPIO

R226
10K_0402_5%~D
1
2

+3VALW

Dell GPIO rev0.7
D-Bay USB power

R UN_ON
ICH_PME#
SIO_THRM#
SUS_ON
SYS_SUSPEND
DH_PWRSRC_OC
IDE_RST_HDD
IDE_RST_MOD
GC_BL_SUSPEND
DH_POWER_EN
AC_LOW_PRES2#

<21> IDE_RST_HDD
<21> IDE_RST_MOD
<18> GC_BL_SUSPEND
<26> DH_POWER_EN
SATA_HDD_DETECT#

MODC_EN#
HDDC_EN#

<39> MODC_EN#
<39> HDDC_EN#
+3.3VRTC

2

254VCC0

1
2

R232
0_0402_5%~D

1
L12
BLM11A121S_0603~D
1
2

2

1

2

2

1

C581
0.1U_0402_16V4Z~D

2

1

C563
0.1U_0402_16V4Z~D

2

C572
0.1U_0402_16V4Z~D

2

1

C567
0.1U_0402_16V4Z~D

1

C558
0.1U_0402_16V4Z~D

2

C568
0.1U_0402_16V4Z~D

2

1

C548
0.1U_0402_16V4Z~D

1

1

C589
0.1U_0402_16V4Z~D

C546
0.1U_0402_16V4Z~D
C577
0.1U_0402_16V4Z~D

C549
0.1U_0402_16V4Z~D
C574
0.1U_0402_16V4Z~D

+3VRUN

2

LPC_LDRQ1#
LPC_LFRAME#

M3
R1
T1
P3
T4
P5

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
IRQ_SERIRQ
EC_CLKRUN#

LPC_LDRQ1# <21>
LPC_LFRAME# <21>
LPC_LAD[0..3] <21>

1

A15
D13
A14
C12
B13
A13
D12
F11
B12
A12
C11
D11
E11
B11
A11
C10
A4

FDD
LGPIO50
LGPIO51
LGPIO52
LGPIO53
LGPIO54
LGPIO55
LGPIO56
LGPIO57
LGPIO60
LGPIO61
LGPIO62
LGPIO63
LGPIO64
LGPIO65
LGPIO66
LGPIO67

LPC
GPIO

LGPIO70
LGPIO71
LGPIO72
LGPIO73
LGPIO74
LGPIO75
LGPIO76
LGPIO77

RXD1
TXD1
RTS1#
CTS#
DTR#
DSR#
DCD#

COM1

RI1#

GPIO10/WK_SE14/IRMODE/IRRX3B
IRRX
IRTX

IR

M7
R13
L11
H10
B16
F10
A6

2

D3
H2
K6
P4
E1

2

ACK#
SLCTIN#
INIT#
ALF#
STROBE#
BUSY
PE
SLCT
ERROR#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

VCC1_1
VCC1_2
VCC1_3
VCC1_4
VCC1_5
VCC1_6
VCC1_7

LPT
VCC

VCC2_1
VCC2_2
VCC2_3
VCC2_4
VCC2_5

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12

1

KPLLVCC

R5

GND
VCC2_6/PLL

2

1

C152
0.1U_0402_16V4Z~D
P6

D_SERIRQ

IRQ_SERIRQ <20,21,30>

2

RN5
10K_8P4R_1206_5%~D
8
7
6
5

10K_0402_5%~D

WRPRT#
RDATA#

1
2
3
4

INDEX#
DISKCHG#
TRK0#

1

+3VRUN

2
R520
10K_0402_5%~D

+5VSUS
C

TXD0

U42C

T11

3

A

Y

5

PAD

G5
G2
H7
H8
H6
G1
H5

RXD0
TXD0

R532

1

2

10K_0402_5%~D

CTS0#

R537

1

2

10K_0402_5%~D

DSR0#
DCD0#

R211
R527

1
1

2
2

10K_0402_5%~D
10K_0402_5%~D

B10

R I0#

R227

1

2

10K_0402_5%~D

H15
K14
M4

D_IRMODE
IRRX
IRTX

C1
F2
F1
G3
G4
D4
B1
B2
G6
F4
F3
E2
F5
E4
D1
D2
E3

ACK#

@
TC7W14FU_SSOP8~D

+3VRUN

+3VALW

D_IRMODE <38>
IRRX <38>
IRTX <38>

VCC0/BAT

C211
0.1U_0805_50V7M~D

1

L3
M1
L2
L5
M2
L4
K1
K2
K4
K3
L1
K5
M5
J7
K7

R184
100K_0402_5%~D

D_CLKRUN#

8

T5
N6
L6
R6
T6
L7
P7
N7

WPROT#
RDATA#
HDSEL#
INDEX#
DSKCHG#
TRK0#
MTR0#
DIR#
STEP#
WDATA#
WGATE#
DS0#
FPD
DRVDEN0
DRVDEN1

1

+3VRUN

R3
N4

R183
100K_0402_5%~D

P

LID_CL_SIO#

<21> SIO_PWRBTN#
<18,37,39,44> RUN_ON
<20> ICH_PME#
<21> SIO_THRM#
<43> SUS_ON
<18,41> SYS_SUSPEND
<23> SATA_MOD_DETECT#
<26> DH_PWRSRC_OC

+3.3VRTC

2

D_SERIRQ
D_CLKRUN#

G

PWRSW_SIO#
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S4_S5#

PWRSW_SIO#
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S4_S5#
NOCREG

<36> LONG/SHRT#

1

N2
P1
P2
N3
R4
T3

D

VSS13/PLL

256 - LBGA

AGND
LPC47N254V12FBGA_LBGA256~D

R217

BUSY
PE
SLCT
ERROR#

1

R231
R220
R222
R535

2

1
1
1
1

10K_0402_5%~D

2
2
2
2

+3VRUN

10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D

B

+3VRUN

+3VALW

C2
F6
J5
N1
N5
T10
R15
J11
G11
B15
H9
D6
A2

1

<39>
<21>
<28,30,32>
<19,47>
<21>
<36>

C

+3VALW

D_DLRQ1#

R196

T5
PAD
@

B

R2
T2

1

LPC47N254

2

VAUX_EN
KSO17
USB_EN#
BAY_MODPRES#
USB_IDE#

<26> USB_EN#
<23> BAY_MODPRES#
<23> USB_IDE#

SGPIO30
SGPIO31
SGPIO32
SGPIO33
SGPIO34
SGPIO35
SGPIO36
SGPIO37

+3VRUN

PCIRST_SIO# <20>

R466
100K_0402_5%~D
2

<35,38> KSO_17

F13
F14
E16
E15
E12
E13
D16
D15

H4
H3

1

CBS_GRST#

<30> CBS_GRST#
<36> C3/C4#
D4
<36> GV_HI_LO#
RB751V_SOD323~D
<39,43> VAUX_EN
KSO_17
2
1

LPCPD#
LRESET#

R195
100K_0402_5%~D

2

D

LPCPD#
PCIRST_SIO#

R523
4.7K_0402_5%~D
1
2

2

PWRSW_SIO#
ATF_INT#
SYS_PME#
DEBUG_ENABLE

4

R181
10K_0402_5%~D
2
1

R465
10K_0402_5%~D
2
1

R233
10K_0402_5%~D
2
1

+3VALW

R467
10_0402_5%~D
2
1

LID_CL_SIO#
KAGND

2
L22
BLM11A121S_0603~D

LID_CL#

LID_CL# <18>

1

1

C534
0.047U_0402_10V4M~D

2
A

A

Compal Electronics, Inc.
Title

SIO (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

33

of

54

5

4

3

2

1

+3VALW

+3VALW

KSO16
CAP_LED#
NUM_LED#
SRL_LED#

KSO16
CAP_LED#
NUM_LED#
SRL_LED#
DOCK_PSID
<41> NB_PSID

PBAT_ALARM#
SIO_MSCLK
SIO_MSDAT

D10
E10

T9
@ PAD
CLK_SM1
DAT_SM1
<35> CLK_SM2
<35> DAT_SM2

C4
C3

CLK_SM2
DAT_SM2

B3
A1

CLK_KBD
DAT_KBD

J4
J6

+5VRUN

R224
4.7K_0402_5%~D
2
1

R225
4.7K_0402_5%~D
2
1

R514
4.7K_0402_5%~D
1
2

MSCLK
MSDAT

PWRGD
VCC1_PWRGD
RESET_OUT#

EMCLK
EMDAT

MISC

IMCLK
IMDAT
KBCLK
KBDAT

PBAT_ALARM#

<42> PBAT_ALARM#
<35> KSO[0..15]
R506
4.7K_0402_5%~D
1
2

OUT0
OUT1
OUT2
OUT3
OUT4
OUT5/DS1/KBRST
OUT6/MTR1
OUT7/SMI
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO

T10
@ PAD

C

FDD_LED#
BAT_LED#
LDRQ0#
PWR_LED#

GPIO0/WK_SE02
GPIO1/WK_SE03
GPIO2/WK_SE04
GPIO3/TRIGGER
GPIO7/WK_SE06
GPIO8/WK_SE12/IRRX2
GPIO9/WK_SE13/IRTX2
GPIO17/WK_SE23/A20M
GPIO20/WK_SE25/PS2CLK/8051RX
GPIO21/WK_SE26/PS2DAT/8051TX

DAT_KBD
CLK_KBD
CLK_SM1
DAT_SM1

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

G15
G12
G16
R7
T7
K8
J8
L8
M8
N8
P8
T8
R8
R9
T9
P9
N9

GPIO6/WK_SE11/IRMODE/IRRX3A
GPIO5/WK_SE10/KSO15
GPIO4/WK_SE07/KSO14
KSO13/GPIO18
KSO12/OUT8/KBRST
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

M9
L9
K9
K10
M10
R10
N10
P10

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK
GPIO11/WK_SE15/AB2A_DATA
GPIO12/WK_SE16/AB2A_CLK
GPIO13/WK_SE17/AB2B_DATA
GPIO14/WK_SE20/AB2B_CLK
GPIO15/WK_SE21/FAN_TACH1
GPIO16/WK_SE22/FAN_TACH2
GPIO19/WK_SE24

CLOCK

PCI_CLK
24MHZ_OUT
32KHZ_OUT
CLOCKI

K/B

<35,38> KSI[0..7]
B

FLASH

C592
22P_0402_50V8J~D
CLK_32KX2

2

A3

XTAL1

J12
J9
M6
J10

3.8X12.1mm
2

C593
22P_0402_50V8J~D
1
2

CLK_32KX1

C5

XTAL2

256 - LBGA

1

R236
10K_0402_5%~D
2
1

MODE

2

EEPROM_WC

K13
K15
H1

RUNPWROK
VCC1_PWROK
RESET_OUT#

EEPROM_WC <35>
SATA_3V_ENABLE# <39>
HW_RADIO_DIS# <27,32>
LAN_LOW_PWR <28>
CHG_PBATT <48>
TI_SUSPEND# <30>
AUDIO_AVDD_ON <24>

1

3

DAT_SMB <19,26,35,47>
CLK_SMB <19,26,35,47>
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_TACH <14>
FAN2_TACH <14>
SIO_A20GATE <21>

M12
R12
T12
P11
N11
M11
R11
T11

SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0

1

<18>
<18>
<42,48>
<42,48>

C

VCC1_PWROK <35>

CK_33M_SIOPCI <6>

+5VALW

SBAT_SMBDAT

R209
22K_0603_5%~D
1
2

SBAT_SMBCLK

R522
22K_0603_5%~D
1
2

PBAT_SMBDAT

R198
22K_0603_5%~D
1
2

PBAT_SMBCLK

R513
22K_0603_5%~D
1
2

DOCK_SMBDAT

R528
10K_0402_5%~D
1
2

DOCK_SMBCLK

R533
10K_0402_5%~D
1
2

CK_14M_SIO <6>

SIO_FA[0..19] <35>

2

1

2

B

1
+3VALW

SIO_FD[0..7] <35>

LPC47N254V12FBGA_LBGA256~D

C153
0.1U_0402_16V4Z~D

2

MAX6326_SOT23~D

CK_14M_SIO

FRD# <35>
FWR# <35>
FCS# <35>

1

RESET#
GND

CK_33M_SIOPCI

FR D#
FWR#
FCS#

2

RESET_OUT# <37>

J3
J2
D5
J1

P14
N14
P15

U11
VCC

DAT_SMB
CLK_SMB
DOCK_SMBDAT
DOCK_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_TACH
FAN2_TACH
SIO_A20GATE

+3VALW

MAX6326

R230
10K_0402_5%~D
1
2

RUNPWROK <18,37,43,44,46>

C9
A9
E9
D9
H16
H14
J15
J13
G9
F9
F16

FRD#
FWR#
FCS#

3

2
LIVE_ON_BATT <39>

QBUFEN#
FAN2_PWM <14>
BREATH_LED <38>
FAN1_PWM <14>

FAN2_PWM
BREATH_LED
FAN1_PWM

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

2

BAT1_LED# <38>
LPC_LDRQ0# <21>
BAT2_LED# <38>

HW_RADIO_DIS#
LAN_LOW_PWR
CHG_PBATT
TI_SUSPEND#
AUDIO_AVDD_ON
LIVE_ON_BATT

N12
T13
P12
T14
T15
R16
N13
P16
M14
N15
N16
M13
L12
M15
M16
L14
L13
L15
L16
K11
R14
T16
P13

R228
1K_0402_5%~D

1
R550
10K_0402_5%~D

BAT1_LED#
LPC_LDRQ0#
BAT2_LED#

FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA20
FA21
FA22

FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0

X5
32.768KHZ_12.5P_MC-306~D

XOSEL

C7
F7
B6
E6
C6
A5
B5
D7
B7
E7
A7
G7

1

1

B4
K16
E5

R549
10K_0402_5%~D
2
1

R213
4.7K_0402_5%~D
1
2

<35>
<38>
<38>
<38>

H13
H12
H11
G10
G13
J14
J16
G14
F15
F12

FDD_PP#

K12

R551
10K_0402_5%~D
2
1

SIO_THERM_PWRDN
H_PROCHOT_SIO#
SCR_DETECT_C

<37> SIO_THERM_PWRDN
<10> H_PROCHOT_SIO#
<31> SCR_DETECT_C

XOSEL
EC_SCI#
MODE

A10

R235
10K_0402_5%~D
2
1

+3VALW

MACALLEN

FDC_PP#
TEST_PIN

R521
@ 10_0402_5%~D
1
2

PBAT_PRES#

<42> PBAT_PRES#

LPC47N254

D

CK_33M_SIOPCI_TERM

SBAT_PRES#

IN0/WK_EE4
IN1/WK_EE2
IN2/WK_EE3
IN3/GPWKUP
IN4/WK_SE00
IN5/WK_SE01
IN6/WK_SE05
IN7/WK_EE1

C564
@ 4.7P_0402_50V8C~D

<18> FPVCC
<39,48,49> ACAV

B9
B8
A8
C8
D8
E8
F8
G8

R207
@ 10_0402_5%~D
1
2

FPVCC
ACAV
SBAT_ALARM#

CK_14M_SIO_TERM

DOCK_SMB_INT#

SIO_KAH_PGM

C177

DOCKED
<26> DH_MOD_PRES#

L10

@ 4.7P_0402_50V8C~D

2

FPGM

R234
@ 10K_0402_5%~D
2

U15B

10K_0402_5%~D
D

R179
1K_0402_5%~D
@
R180
10K_0402_5%~D
2
1

1

DH_MOD_PRES#
R229
2

1

1

+3VALW

HW_RADIO_DIS#
A

A

LAN_LOW_PWR
CHG_PBATT

Compal Electronics, Inc.
Title

SIO (2/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

34

of

54

5

4

3

2

+3VALW

1

+3VALW

1

1

R552
@ 0_0402_5%~D

C599
0.1U_0402_16V4Z~D

2

2
U40
1
2
3
4

D

+5VRUN

NC
A1
A2
VSS

8
7
6
5

VCC
WP
SCL
SDA

EEPROM_WC
CLK_SMB
DAT_SMB

D

EEPROM_WC <34>
CLK_SMB <19,26,34,47>
DAT_SMB <19,26,34,47>

FM24C05U_SO8~D

Address

1010 00XX

CLK_SM2

MOUSEDAT
MOUSECLK

2

1

2

+5VRUN
1
L11
BLM31A260SPT_1206~D
2
1

2

C147
0.1U_0402_16V4Z~D

2

1

C141
10P_0402_50V8J~D

1

C138
10P_0402_50V8J~D

2
L9
BLM11A601S_0603~D
C146
10P_0402_50V8J~D

1

C140
10P_0402_50V8J~D

<34> CLK_SM2

C

JPALM
1
3
5
7
9
11
13
15
17
19

MOUSEVDD

1

KSO_17
KSI3
KSI2
KSI1
KSI0

<33,38> KSO_17

2

2
4
6
8
10
12
14
16
18
20

TP_Z
TP_V+
TP_Y
TP_X
TP_GND

HRS_FX6A-20P-0.8SV~D

Keep no nosie coupled,
Especially the TP_GND

+3VALW

ACES_6278-34P-DEBUG

@

<34,38> KSI[0..7]

30
29
28
27
26

TP_V+
TP_X
TP_GND
TP_Y
TP_Z

31
32
33
34

@

@

@

CN2
100P_1206_8P4C_50V8~D
1
8
2
7
3
6
4
5

CN3
100P_1206_8P4C_50V8~D
1
8
2
7
3
6
4
5
@

<34> FCS#
<34> FRD#
<34> FWR#
1

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

FCS#
FR D#
FWR#

22
24
9

2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

VCC
VCC
VPP

31
30
11

D0
D1
D2
D3
D4
D5
D6
D7

25
26
27
28
32
33
34
35

SIO_FD0
SIO_FD1
SIO_FD2
SIO_FD3
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7

1

2

1

2

B

SIO_FD[0..7] <34>
RP#/RESET#
WP#/RY/BY#
NC
NC

10
12
29
38

GND
GND

23
39

CE#
OE#
WE#

FWH_RST

2

1

VCC1_PWROK

VCC1_PWROK <34>

R219
0_0603_5%~D

MX29LV008T/B_TSOP40~D
C148
100P_0603_50V8J~D
@

@

D

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

A

+3VALW
U14

<34> SIO_FA[0..19]

JAE_FK2S030W11~D
CN4
100P_1206_8P4C_50V8~D
1
8
2
7
3
6
4
5

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

CN5
100P_1206_8P4C_50V8~D
1
8
2
7
3
6
4
5

<34> KSO[0..15]

CN6
100P_1206_8P4C_50V8~D
1
8
2
7
3
6
4
5

<34> KSO16

CN1
100P_1206_8P4C_50V8~D
1
8
2
7
3
6
4
5

B

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C

For Compal Flash Tools

JKYBRD
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

FCS#
FR D#
FWR#
SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0
SIO_FA19
SIO_FA18
SIO_FA17
SIO_FA16
SIO_FA15
SIO_FA14
SIO_FA13
SIO_FA12
SIO_FA11
SIO_FA10
SIO_FA9
SIO_FA8
SIO_FA7
SIO_FA6
SIO_FA5
SIO_FA4
SIO_FA3
SIO_FA2
SIO_FA1
SIO_FA0
FWH_RST

C202
0.1U_0402_16V4Z~D

DAT_SM2

<34> DAT_SM2

JP2
L8
BLM11A601S_0603~D
1
2

C203
0.1U_0402_16V4Z~D

R168
4.7K_0402_5%~D
2
1

R166
4.7K_0402_5%~D
2
1

SUB_6782U

SMbus address A2

G

C
1
B
2

S
2N7002

E
3

A

DTC114

Compal Electronics, Inc.
Title

INT KB & ROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

35

of

54

5

4

3

2

1

CPLD Function options Table
Function

No.

D

<8>
<8>
<8>
<8>
<8>
<8>

1
1
1
1
1
1

R15
R16
R29
R31
R34
R36

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

2
2
2
2
2
2

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

VID0
VID1
VID2
VID3
VID4
VID5

<8,46>
<8,46>
<8,46>
<8,46>
<8,46>
<8,46>

Speedstep enable

Speedstep disable

1

CPLD (U27)

Pop U27, C233, C606, R557,

Depop U27, JPLD, C233, C606, R557,

2

STPCLK# (From ICH to CPU)

Pop Q42, R254, Depop R259

Depop Q42, R254, Pop R259

3

CPUSLP# (From ICH to CPU)

Pop Q43, R561, Depop R251

Depop Q43, R561, Pop R251

4

VRMPWRGD (From Reset to ICH)

Depop R243

Pop R243

5

STP_AGP# (PLD to AGP)

Depop R96, Pop R98 (P.18)

Pop R96, Depop R98 (P.18)

6

CPUPREF# (From PLD to CPU)

Pop R380(P.8)

Depop R380 (P.8)

7

STPCPU_VR (From PLD to CPU Power)

Pop PR94, Depop PR95 (P.46)

Depop PR94, Pop PR95 (P.46)

8

DPRSLPVR (From PLD to CPU power)

Pop PR93, Depop PR92 (P.46)

Depop PR93, Pop PR92 (P.46)

9

PLD_WAKE# (From PLD to ICH)

Pop R141 (P.21)

Depop R141 (P.21)

10

PLD_DISABLE#

Pop R256, Depop R252

Depop R256, Pop R252

11

DPSLP#

Pop R76, R78(P.8)

Depop R76, R78(P.8)

12

PCI_PCIRST#(From ICH to PLD)

Pop R245

Depop R245

13

GV_HI_LO#

Pop R253

Depop R253

D

C

C

Pull low disables PLD assertion
of SSTEP or sleep and deeper
sleep on CPU

+3VSUS
1

+3VSUS

1

Pop when use CPLD

R256
10K_0402_5%~D

2

2

R253
10K_0402_5%~D
PLD_DISABLE#
1

GV_HI_LO#

+VCC_CORE

R252
@ 1K_0402_5%~D

+3VSUS

1

2

JPLD
1
2
3
4
5
6

2

R246
10K_0402_5%~D
H_STPCLK#

@ MOLEX_53261-0690~D
B

B

Depop when use CPLD

<8> H_CPUSLP#
<21,37> SUSPWROK
<21> VRM_PWRGD

H_STPCLK#
PLD_DISABLE#
I_STPCLK#
L_CPUSLP#
H_CPUSLP#

42
5
6
10
18
23

VRM_PWRGD

41
17
9
29

+3VSUS
1
A

2

1
C233
0.1U_0402_16V4Z~D

2

I/O_42
I/O_5
I/O_6
I/O_10
I/O_18
I/O_23
VCCINT
VCCINT
VCCIO
VCCIO

C606
0.1U_0402_16V4Z~D

35
37

I/O_27
I/O_28
I/O_31

27
28
31

GND
GND
GND
GND
GND
GND
GND
GND
GND

R245

1

0_0402_5%~D

2

2
CK_33M_CPLD <6>

+VCC_CORE

L_CPUSLP#
+VCC_CORE
C

PCI_PCIRST# <12,20>

I_STPCLK#
C

Q43

Q42

VCORE_DSEN# <46>
10K

2

CPLD_WAKE# <21>
SUSCLK <21>

10K

2

B

B
E

E
DTC114TKA_SC59~D

Pop when use CPLD

DTC114TKA_SC59~D

Pop when use CPLD

CLK_CPLD
<21> CPUSLP#

38
36
30
24
16
11
4
40
39

R244
@ 22_0402_5%~D

<21> STPCLK#
R251

H_CPUSLP#

1

R259
H_STPCLK#

2

@ 0_0402_5%~D

1
@

2

0_0402_5%~D

Depop when use CPLD

2

Link CIS
1.3

Dell Speedstep Support PLD

A

C

1

EPM3032A_TQFP44

Pop when use CPLD

R588
1
2
0_0402_5%~D

2

I/O_35
I/O_37

CPUPREF# <8>

O_GMUXSEL

R254
10K_0402_5%~D

1

I/O_43
I/O_44
I/O_2
I/O_8
I/O_12
I/O_13
I/O_20
I/O_14

R561
10K_0402_5%~D
I_VRMPWRGD <37>
DPSLP# <8>

DPSLP#
CLK_CPLD

1

43
44
2
8
12
13
20
14

3
15
19
21
22
25
33

VRM_PWRGD

3

2
CLK_STP_CPU#

GV_HI_LO#

I/O_3
I/O_15
I/O_19
I/O_21
I/O_22
I/O_25
I/O_33

2

@ 0_0402_5%~D

3

2

34

1

1

<33> GV_HI_LO#
<33> NOCREG
<33> C3/C4#
<6> CLK_STP_CPU#
<33> LONG/SHRT#
<18> STP_AGP#
<46> VCORE_DRSEN
<8> H_STPCLK#

1
I/O_34

2

1

R557
R559
10K_0402_5%~D

1K_0402_5%~D

TDI
TMS
TCK
TDO

1

R243
U27
1
7
26
32

+3VSUS

1

+3VSUS

+3VSUS

C225
@ 10P_0402_50V8J~D

1
3

B 2

E

DTC114TKA

Compal Electronics, Inc.
Title

PLD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

36

of

54

5

4

3

2

1

+3VSUS
SD 1.11(12474 page292) is request 8.2K ohm

1
+5VSUS

R247

1

C228
2

0.1U_0402_16V4Z~D

A

12

TC7W14FU_SSOP8~D

IN2
OUT

13

C609
0.22U_0603_10V7M~D

R UNOK

IN1
1

<39> SUSPWROK_3V

2

2

<45> V_2P5V_PWRGD

10

IN1

IN1
OUT

U26B
74VHC08MTC_TSSOP14~D
6

IN2
9

12
13

<34> RESET_OUT#

IN2
OUT

8

OUT

10

RUNPWROK

IN1

11

U25D
74VHC08MTC_TSSOP14~D

SUSPWROK <21,36>

U26A
74VHC08MTC_TSSOP14~D
+3VSUS
C603
2

1

0.1U_0402_16V4Z~D

VCC for 10 degree

MAX6509 goes in CPU cavity.

1

+3VSUS

8

P

3

OUT

IMVP_PWRGD

3

G

G

1

4

7

74VHC08MTC_TSSOP14~D

+3VRUN

GND for 2 degree

U36
Z3805

1

U4
VCC+

MAX6509SET

5

1

SET

VCC

1

C

2

C399
@ 0.047U_0402_10V4M~D

MAX6509HYST

IMVP_PWRGD

R556
100K_0603_5%~D
1
2

SET-HOT Vrsion

1
1

C605

2

1

R95
@ 10K_0402_5%~D

1U_0603_10V6K~D

8

4

A

U41A

P

HYST

Y

7

6

A

TC7W14FU_SSOP8~D

U41B
TC7W14FU_SSOP8~D
2

Y
G

OUT#

MAX6509CHU-K_SOT23-5~D

I_VRMPWRGD <36>

shall be VHC14

4

3

8

4

P

OUT

4

IN-

@ LMV331__DCK

0.1U_0402_10V6K~D

shall be VHC14

R93
10K_0402_5%~D
1

3

GND

G

GND

2

2

+3VALW

1

1

2

2

R89
18.2K_0603_1%~D
1
2

2

Z3806
R360
@ 100K_0402_1%~D
1
2

C392
@ 1000P_0402_50V7K~D

R94
@ thermistor
1
2

C51
@ 1000P_0402_50V7K~D

2

C604

5
2

IN+

U41C
TC7W14FU_SSOP8~D
5
CK_VTT_PG# <6>

Y

2

10K_0402_5%~D

Discretes go outside.

A

IN2

R581

THERM_CPU#
+3VSUS

IN1

2

<46> VCORE_PWRGD

HYST:

1

R362
@ 48.7K_0402_5%
2
1

1

<44> VTT_PWRGD

+3VSUS

U25A

P

2

Z3804

R359
48.7K_0402_1%~D

R355
@ 100K_0402_1%~D
1
2

R353
@ 2.21K_0402_1%~D
1
2

C

+3VRUN
14

+3VSUS
+3VSUS

R352
@ 16.2K_0402_1%~D
2
1

D

PWRGD_3V <10,21>

U25C
74VHC08MTC_TSSOP14~D

IN1

R UN_ON

<18,33,39,44> RUN_ON

IN2

+3VSUS

RUNPWROK <18,34,43,44,46>

3

OUT
IN2

8

OUT
IN2
+3VSUS

9

IN1

7

THERM_FF_GATE

5

+3VSUS

11

4

4

1

2

Y

4

<8> ITP_DBRESET#

14

6

+3VSUS
IMVP_PWRGD

U26C
74VHC08MTC_TSSOP14~D

P

7

Y

150_0402_5%~D

C226
0.1U_0402_16V4Z~D

2

G

A
G

1

U26D
74VHC08MTC_TSSOP14~D

G

5VRUNRC

U42B
TC7W14FU_SSOP8~D

P

U42A

P

8

8

1

2
D

POWER
SEQUENCING

+3VSUS

R560
100K_0402_5%~D

2

1

+5VRUN

0.47U_0603_16V7K~D
2

2

C607
1

Thermistor goes in CPU cavity.

R571
10K_0402_5%~D
1

Dell P/N 8K573
Semitech P/N 103KT2125-1P
SIO_THERM_PWRDN

SIO_THERM_PWRDN <34>

2

SYMBOL(SOT23-NEW)

2

2

VDD

D
CLK
VSS

CLR
1

IN

1

2

Q55

3

DTC144EKA_SOT23~D

47K

DTA114YKA

A

THERM_TRUE

G

4

TC7SH08FU_SSOP5~D
C618
0.1U_0402_16V4Z~D
1
2

4

THERM_CLEAR

3

47K
U29
O

3

GND

R572
20K_0603_5%~D
2
1

5
A

1

2

P

B

2

Q70
2N7002_SOT23~D

OUT

0.1U_0402_16V4Z~D

D16
RB751V_SOD323~D
2
1

1

1

THERM_CPU#

S

6

+RTC_PWR

THERMTRIP_3P3#

D

2
G

ICH_THERM_PWRDN# <21>

+3VSUS

<39> POWER_SW_DB#

5

THERM_PWRDWN

5

R275
100K_0402_5%~D

C619
1
2

<43> THERM_STP#

2

3

S

3

<8,21> H_THERMTRIP#

Q

7

2
G
1

2

3

Z3809
Q57
2N7002_SOT23~D

S

1

1
1

D

2
G

R282
@ 0_0402_5%~D

A

3

Q56
2N7002_SOT23~D

D

2
1

THERM_TRUE

Q60
MMBT3904_SOT23~D

2

DTC144EKA_SOT23~D

U28A
SN74ACT74PWR_TSSOP14~D

Q

R280
1K_0402_5%~D

2

14

4

Z3812
Z3813

R285
8.2K_0603_5%~D

Z3808

1

THERM_FF_GATE

R272
8.2K_0603_5%~D
2
1

+3VSUS

+VCC_CORE

2

47K

PRE

R281
0_0402_5%~D
+3VSUS

B

C620
0.1U_0402_16V4Z~D

Z3811
2

3904

3

1

E

47K

1

B

Q71
1

3

1

3

C

B

R283
1K_0402_5%~D
1
2

1

+RTC_PWR

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Thermtrip & PowerGOOD
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

37

of

54

5

4

3

2

1

+5VHDD

OUT
IN

GND

1

3
3

2

47K

DTA114YKA

+3VRUN

+3VRUN
2

<21> PIDEACT#

Q44
DTA114YKA_SOT23~D

10K

JLED1
R_BT_MPCI_ACT
BAT1_LED
BAT2_LED
R_BREATH_LED
ACTLED

3

1

D

47K

3

47K

2

<34> NUM_LED#

R_PIDEACT

LID_CL#

R56
470_0603_5%~D
2
1

R_CAP

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

CAP_LED
NUM_LED
SRL_LED

Q16
DTA114YKA_SOT23~D

10K

1

2

<34> CAP_LED#

R60
470_0603_5%~D
2
1

CAP_LED

Q12
DTA114YKA_SOT23~D

10K

KSO_17
KSI4
KSI5
KSI6

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

KSO_17 <33,35>
KSI4 <34,35>
KSI5 <34,35>
KSI6 <34,35>

D

+RTC_PWR
INT_MIC+
INT_MIC-

INT_MIC+ <25>
INT_MIC- <25>

POWER_SW#

POWER_SW# <39>

POWER_SW_EMI

2

1

R47
0_0402_5%~D

3

1

FOX_QTS1030A-2021~D

47K

2

NUM_LED

R_SRL

R46
470_0603_5%~D
2
1

SRL_LED

Q11
DTA114YKA_SOT23~D

10K

1

<34> SRL_LED#

R_NUM

R52
470_0603_5%~D
2
1

+3VRUN

C

R574
47_0805_5%~D
2
1

IR VCC

R575
1.8_1206_5%~D
2
1

+3VRUN

Z3903

R573
1.8_1206_5%~D
2
1

C

R577
@ 0_0402_5%~D
2
1

+5VALW

<33> D_IRMODE

R576
0_0402_5%~D
1
2

6
SD_MODE

VCC

5

BAT1_LED

Q21
DTA114YKA_SOT23~D

10K

R_BAT2_LED

R73
470_0603_5%~D
2
1

C621
0.1U_0402_16V4Z~D

R80
470_0603_5%~D
2
1

R578
1K_0402_5%~D
2
1

R_BAT1_LED

<33> IRTX
R579
1K_0402_5%~D
2
1

2

1

<34> BAT2_LED#

1

3

47K

Q22
DTA114YKA_SOT23~D

10K

2

1

C624
4.7U_1206_16V6K~D

2
2

<34> BAT1_LED#

IRED_ANODE

SD_MODE

RXD

IRED_CATHODE

3

TXD

MODE
GND

IR_ANODE

1
4

IRRX <33>
C623
4.7U_1206_16V6K~D

3

U43
47K

7
8

TFDU6101E_TR4~D
1

TFDU6102

2

1

2

BAT2_LED

B

B

+3VALW

2

2

+3VALW

2

Z3902
<27> BT_ACTIVE

BT_ACTIVE

R86
10K_0402_5%~D
1
2

1

Q19
MMBT3904_SOT23~D

BT_MPCI_ACTIVE

Q23
MMBT3904_SOT23~D

2
3

R92
10K_0402_5%~D
1
2 BREATH_LED_B

3

<34> BREATH_LED

1

Z3901

1

R85
150_0603_5%~D

1

R72
150_0603_5%~D

R_BT_MPCI_ACT
R_BREATH_LED
A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

LED Interface & IrDA
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

38

of

54

5

4

3

2

+RTC_PWR

+VCC_CORE

1

V_1P25V_DDR_VTT

+3VRUN

2

2

2

Z4003

Z4005

Z4006

1

R178
150_0805_5%

D

1

Q35
2N7002_SOT23~D

D

3

1

D

MOLEX_53398-0290

1

2

<18,33,37,44> RUN_ON

2
G

S

Q34
2N7002_SOT23~D

D

S

2
G

Link CIS, function f

S

47K

R260
10K_0402_5%~D

2

2
G

47K
3

G

Q36
2N7002_SOT23~D

1
2

2

Q37
DTC144EKA_SOT23~D

1

4

D

2

2

+5VRUN Source

S

6
5
2
1

2
1

2

<41> RBAT

2

2

2

C239
4.7U_1206_16V6K~D

3

S

1

R112
10K_0402_5%~D

Q47
+5VRUN
SI3456DV-T1_TSOP6~D

3

2
G

<18,33,37,44> RUN_ON

RUN_ENABLE
R107
330K_0402_5%~D
2
1

D

1

R175
22_0805_5%~D

3

1
C60
0.22U_1206_25V7M~D

1

Q25
2N7002_SOT23~D

R176
47_0805_5%~D

3

+5VSUS

TP0610T_SOT23~D

1

1

2

1

S
3

G

C67
4.7U_1206_16V6K~D

2

4

Q26

Z4001

+3VRUN

1

JRBATT

6
5
2
1

3Z4002

D

R190
100K_0402_5%~D

+3VRUN Source

D

R103
30K_0402_5%~D

2

R99
330K_0402_5%~D

Q27
SI3456DV-T1_TSOP6~D

1

2

+3VSRC

1

1

1

1

1

Run Planes Enable

1

PWR_SRC

+5VSUS
+12V
1

+5VMOD Source
1
2
5
6

R277
100K_0402_5%~D

+5VSUS
2

+12V

3
2

D

R257
100K_0402_5%~D

G

4
3

2

C600
+RTC_PWR

+RTC_PWR

1

IN

O

IN1

7

7
7

ALW_ENABLE#

MM74HCT14_TSSOP14~D

ALW_ENABLE# <43>

1
1

MM74HCT32_TSSOP14~D

MM74HCT14_TSSOP14~D

2

A

U19A
SN74LVC3G14DCTR_SSOP8~D
6
Y 7

C214
0.1U_0402_16V4Z~D

A

Y

1

2

SUSPWROK_3V <37>

U19B
SN74LVC3G14DCTR_SSOP8~D
A

+RTC_PWR

U24B

ALWON <43>

P

14

2

IN

O

4

Compal Electronics, Inc.

POWER_SW_DB# <37>

Title

PWRSW_SIO# <33>

7

G

3

5

8

8
12

G

14
13

4

3

P

O
IN1

2

IN0

G

2

P

1
11

+3.3VRTC

P

R238
+3.3VRTC
100K_0402_5%~D
U24F

G

O

P

14
P

U23D

IN0

U23A
MM74HCT32_TSSOP14~D

G

14
13

P

12

<34,48,49> ACAV
2

G
7

1

R258
100K_0402_5%~D

2

+3VSUS

2

G

14
2

1

O

+RTC_PWR

4

1
2

C223
0.1U_0402_16V4Z~D

A

IN

2

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
U24A

1

1

C220

1

4

47K

B

+RTC_PWR

<34> LIVE_ON_BATT

D5
RB751V_SOD323~D

2

<34> SATA_3V_ENABLE#

1

47K

2

2
G

SI3456DV-T1_TSOP6~D
+3VMOD

DTC144EKA_SOT23~D

3

S

C33
0.1U_0402_10V6K~D

S

D

R53
470K_0402_5%~D
2
1

3

2
G

Q45

C235
4.7U_1206_16V6K~D

3
2
D

1

R54
200K_0402_5%~D
2
1

1

Q15
2N7002_SOT23~D

S
C40
4.7U_1206_16V6K~D

C236
0.01U_0603_50V7K~D

1

2

3

Q14
2N7002_SOT23~D

SUSPWROK_5V <31,43,45>

1
2
5
6
D Q41

S

6
5
2
1

2

Q20
SI3456DV-T1_TSOP6~D
+3VSUS

1

1

2

R50
470K_0402_5%~D

B

+3VSUS

1

+12V

+3VSRC

1
R51
470K_0402_5%~D

1

1

R67
470K_0402_5%~D

S

G

1

PWR_SRC

1

R242
10K_0402_5%~D

4

1

1

Q67
2N7002_SOT23~D
3

R63
200K_0402_5%~D
2
1

S

D

2
G

+3VMOD Source

<38> POWER_SW#

2

2

2
D

2
G

<33,43> VAUX_EN

PWR_SRC

+RTC_PWR

C

R273
100K_0402_5%~D

ENAB_3VLAN <28>
Q17
2N7002_SOT23~D

SUSPWROK_5V

2

+5VMOD

1

2

47K

1

C245
4.7U_1206_16V6K~D

47K

1

1

2

<33> MODC_EN#

R65
100K_0402_5%~D

R267
100K_0402_5%~D

2

1

2

1

2

1

PWR_SRC
1

R62
100K_0402_5%~D

3

4
C243
4.7U_1206_16V6K~D

C248
0.01U_0603_50V7K~D

3

47K

+5VHDD

1

2
47K

C250
0.01U_0603_50V7K~D

1
2
5
6

3

1
2

PWR_SRC
1

S

Q58
DTC144EKA_SOT23~D
<33> HDDC_EN#

Q59
DTC144EKA_SOT23~D

D Q54
SI3456DV-T1_TSOP6~D

G
HDD_EN

S

1

1
R276
100K_0402_5%~D
C

+5HDD Source

D Q50
SI3456DV-T1_TSOP6~D

G
MOD_EN 3

2

MM74HCT14_TSSOP14~D

4

POWER CONTROL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

39

of

54

5

4

3

2

1

Fiducial Mark
FD2

FD15

1

PCMCIA Slot screw hole

CPU screw hole

FD10

1

FIDUCIAL MARK

FD12

1

FIDUCIAL MARK

FD13

1

FIDUCIAL MARK

FD11

1

FIDUCIAL MARK

1

FIDUCIAL MARK

FIDUCIAL MARK

D

D

H8
C315D110

H12
C315D110

H7
C315D110

H11
C315D110

H26
C197D91

H27
C197D91

H28
C197D91

FD9

H29
C197D91

FD8

1

FD14

1

FIDUCIAL MARK

FD7

1

FIDUCIAL MARK

FD4

1

FIDUCIAL MARK

1

FIDUCIAL MARK

FIDUCIAL MARK

1

1

1

1

1

1

1

FIDUCIAL MARK
1

FD1

1

FD3

FD6

1

FD5

1

FIDUCIAL MARK

FD16

1

FIDUCIAL MARK

FD17

1

FIDUCIAL MARK

FD18

1

FIDUCIAL MARK

1

FIDUCIAL MARK

FIDUCIAL MARK

FD19
1
FIDUCIAL MARK

MCH screw hole

H4
H_C150D110

+RTC_PWR

+RTC_PWR

14
IN0

8

O

O

5

7

7
H19
H_O115X177D95X157

C

H20
C150D110

1

H21
C150D110

1

H22
C150D110

1

H10
C315D165

1

VGA Conn. screw hole

6

IN1

G

IN1

U23B
MM74HCT32_TSSOP14~D

P

4

IN0

G

9
10

C

U23C
MM74HCT32_TSSOP14~D

P

14

1

H3
H_O115X177D95X157

1

H2
H_C150D110

1

H1
H_C99D79

1

H23
C315D165

1

H5
C315D165

1

H9
C315D165

1

1

H6
C315D165

Others screw hole

1

+RTC_PWR

8
P

14

10

+3.3VRTC
U28B
SN74ACT74PWR_TSSOP14~D
3
H33
C315D110

9

Q
D

1

1

1

1

1

1

12

MDC

G

H31
H32
C315D110 C315D110

U19C
SN74LVC3G14DCTR_SSOP8~D
Y 5

4

H30
C315D110

PRE

H16
C315D110

VDD

H17
C315D110

A

11

CLK

8

7

CLR

1

13

VSS

Q
H15
C217D157

+RTC_PWR

+RTC_PWR

B

B

9

O

7

8

MM74HCT14_TSSOP14~D

MM74HCT14_TSSOP14~D

+3VSUS

H25
C315D165

PCB
LA1711

U25B
74VHC08MTC_TSSOP14~D
4

IN1

1

1

1

O

7

PCB
H24
C315D165

IN

IN

G

FAN Conn. screw hole

6

G

5

U24D

P

U24C

P

14

14

+RTC_PWR

OUT

+RTC_PWR

6

IN2

U24E

P

14

5

IN

O

10

7

G

11

MM74HCT14_TSSOP14~D

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

PAD,Screw Hole and Spare Parts
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

40

of

54

5

4

3

2

1

2

D C_IN+

2

+12V

1

PD 2
1

PD 1
RB751V-40_SOD323~D

RB751V-40_SOD323~D

RTC_PWR Source
+RTCSRC
P R1
1

+RTC_PWR
PU 1

+RTCSRC Source

Z4202

2

1

IN
OUT

1

2

P D3
1
PR 3
4.7K_0603_5%~D

1 P R2

RTC_SHDN#

2

5

2

#SHDN

0_0603_5%~D
EC10QS04_SOD106~D

5/3+

D

P C2
10U_1206_6.3V7K~D

4

MAX1615EUK_SOT23-5~D

2

2

+RTCSRC

3
1

6.2K_0603_5%~D

GND

P C1

1000P_0603_50V7K~D

D

1

2

Z4201

P D4
2

SBATT_VCC

2

0.75A_24V_MINISMDM075/24~D

1

PQ1
1

3

EC10QS04_SOD106~D

PW R _ SRC

IRLML5103_SOT23~D

1

1

+3.3VRTC

P R4

3.3VRTC
2

100K_0603_5%~D
2

1

IN
OUT

1 PR 5

2

5

#SHDN

1

0_0603_5%~D

P C7

2

1

1

1

PC 6
0.01U_0603_50V7K~D
1

PC 4

N C_LDO_EN

FET on when in suspend, current flow is from Rbat to
PWR_SRC to sustain system during battery swap mode

2

2

2

2

PC 5
2200P_0603_50V7K~D

GND

Z4203

2200P_0603_50V7K~D

0.01U_0603_50V7K~D

SYS _SUSPEND

<18,33> SYS _SUSPEND

2

Source

PU 2

5/3+

3

4

MAX1615EUK_SOT23-5~D

2

PW R _SRC

1

PFS1
RBAT

<39> RBAT

PC 3
10U_1206_6.3V7K~D

PQ2

47K

DTC144EKA_SOT23~D

3

47K

C

C

D

2

1

+3VALW

3

PR224

S

2

G

@ 0_0603_5%~D
1
2

P R7
4.7K_0603_5%~D

IRLML5103

DC_IN+ Source
D C_IN+

DC-_1

N B_PSID

N B_PSID <34>

2
G
1

1

1

2

2

2

1

1

2

1

150K_0603_5%~D

PD28
@ VZ0603M220APT_0603

2

2
1000P_0603_50V7K~D

P C11
0.1U_0805_50V7M~D

P C13
0.1U_0805_50V7M~D

P R13
1

PC 8 2
@ 15U_D2_25M_R90~D 2

2

0_0603_5%~D
1

0.47U_1812_50V7M~D
D C IN+

3

Z4206

B

P R10
@ 100K_0603_5%~D

4
5

2

DC-_2

P C9

P C15

3

1

1

GND_1
MH1
MH2

6

GND_2

P R8

1
2

2

2

GND_3
DC+_2

7

1
0.1U_0805_50V7M~D
+

4

2
DC+_1

B

P C10
P C12
0.01U_0603_50V7K~D 0.1U_0805_50V7M~D

5

+ DC_IN

1

Low_PWR

1

P C14

1

PL2
CHT_C8BBPH853025
2

1
2
3
1

1

GND_4

PS_ID

0_0603_5%~D

P JPDC1

8

PS_ID

BLM11A121S_0603~D

Z-series AC Adaptor
Connctor

9

PR 6

PQ3
SI7447DP_SO8

PS_ID

S

1

D

PL1
PW R _ID 2

1

P Q4
2N7002_SOT23~D

P R12
100K_0603_5%~D
HRS_HR33-DL-7~D
D C IN-

2

PL4
CHT_C8BBPH853025
1
2

THE POINT

THESE CAPS MUBT BE
NEXT TO JCHG

NOTE: "THE POINT LOCATED
AT PS MODULE

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DC-IN
Size
Date:

5

4

3

2

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

41

of

54

5

4

3

2

1

D

D

+5VALW

ESD Diodes

1

PD8

2

3

PD7

2

3

PD6

2

3

2

3

PBATT+
PD5

PL21
@
@
@
DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D

CHT_C8BBPH853025

2

PJPB1

1

PC17
C

2200P_0603_50V7K~D

14
13

Z4304
Z4305
Z4306

SUB_OUT1 <50>
SUB_OUT2 <50>
SUB_DETECT <50>

PR14
10K_0603_5%~D

PR15
1
2
100_0603_5%~D

PC16
0.1U_0805_50V7M~D

2

SUB_OUT1
SUB_OUT2

2

1
2
3
12
11
10
9
8
7
6
5
4

1

SUB_OUT1
SUB_OUT2
SUB_DETECT
BATT1+
BATT2+
SMB_CLK
SMB_DAT
BATT_PRES#
SYS_PRES#
BATT_VOLT
G BATT1-(GND)
G BATT2-(GND)

+5VALW

1

2

1

1

1

@
DA204U_SOT323~D

1

Primary Battery Connector

PBAT_SMBCLK <34,48>
PBAT_SMBDAT <34,48>

PR16 2
1
100_0603_5%~D 1 PR17
2
100_0603_5%~D

PBAT_PRES# <34>
PBAT_ALARM# <34>
C

SUYIN_200275MR012G536ZL~D

SUB_OUT1
SUB_OUT2

THE POINT

1

1

TRACE

3

PD32
DA204U_SOT323~D
@
2

3

2

PD31
DA204U_SOT323~D
@

+12V
12

Please closely PJPB1

11
10
9
8
B

B

7
6
5
4
3
2
1

SUYIN_200275MRQ12G536ZL_12P
TOP view

A

A

Compal Electronics, Inc.
Title

Battery CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

42

of

54

5

4

3

2

1

VCC_MAX1999

VCC_MAX1999

R EF

Adding RC filter

2
2

2

PC23
18.2K_0603_1%~D

PR32
@ 0_0603_5%~D
1

20K_0603_1%~D
1

1

ILIM5

2

2

2

0.1U_0805_50V7M~D

P R21

VCC_MAX1999

0_0603_5%~D

1

+5VALW

1

P R22

P R20

2200P_0603_50V7K~D

1

PC22

1

2
PR18
4.7_0603_5%~D

@15U_D2_25M_R90~D
2
2
10U_1210_25V7M~D
PC19

P R19

+ @15U_D2_25M_R90~D

1

1

1
2

10U_1210_25V6K~D

1 P C21

1
P C20
+

2

2

HCB4532K-800T90_1812~D
P C18

2

PL5
1

PW R _SRC

ILIM3

@ 0_0603_5%~D

P R23

PC29

2

EC10QS04_SOD106~D

SI4810DY_SO8~D
4

2

1

2

0.1U_0805_50V7M~D

24

DL5

LX3

OUT5
N.C.
FB5
PRO

DL3

D L3
22

OUT3
ILIM5
ILIM3
REF
TON
GND
PGOOD

2

7
12
3
4

SKI P#

1
2
3

PR230

2

2
1

1

2

1

5
6
7
8

2

1

1

DH3

FB3
SKIP
ON3
ON5

25

D L5

1

3
2
1

11
5
8
13
23
2

EC10QS04_SOD106~D
P RO#

PR227
@ 0_0603_5%~D

1

P D11

+ PC32

4
21
1
9
10

Adding SKIP control

2

PQ57
SI4810DY_SO8~D

@ 0_0603_5%~D

PC33

2

150U _D2_6.3VM~D

Add the current limit

PR229
0_0603_5%~D

0.1U_0805_50V7M~D

ILIM5
ILIM3
R EF
TON

2

1

0_0603_5%~D

LX5

19

1

27

16
15

2

LX3

330U_E_6.3VM~D

LX5

1

26

DH5

BST3

+5VSUSP
PL6
1
2
4.7U_SPC-1205P-4R7B_+40-20%~D

1

PQ59

2.2_0603_5%~D

SHDN

14

2

8
7
6
5

PD10

2BST328

BST5

P R28
0.1U_0805_50V7M~D
BST5
1
2 1
2
2.2_0603_5%~D
D H5
2 PR218 1

1

1
2
3
2

1

1

PC35

P R29

VCC

18

2

6
0.1U_0805_50V7M~D
2
1BST_3 1

2

LDO5

5
6
7
8

PL7

+

0_0603_5%~D
@

SI4800DY_SO8~D

V+

3
2
1

17
PC31

PC34

P R26
0_0603_5%~D

1

4

PR228

PR37

PC30

SI4800DY_SO8~D

@ 0_0603_5%~D

0_0603_5%~D

PQ56

4

PU 3

4.7U_SPC-1205P-4R7B_+40-20%~D

D

PR27

P R24
43K_0603_1%~D

3

8
7
6
5
2

BST_5

20

1

Current limit at 6A for +5VSUSP

P R25

PQ58

1

2

PD 9
RB717F_SOT323~D

20K_0603_1%~D

2200P_0603_50V7K~D

+3VSRCP

TON
2

1

1U_0603_6.3V6M~D

PC25

1U_0603_6.3V6M~D

2

0.1U_0805_50V7M~D

SKI P#

Place these CAPs
close to FETs

1

Place these CAPs
close to FETs

PC24

4.7U_0805_6.3V6K~D

2

4.7U_1210_25V6K~D

47_0603_5%~D
P C26

2

2

PC28
2

2

PC201

0.1U_0805_50V7M~D

1

1

1

Current limit at 4A for +3.3V
D

P RO#

1
1

2

1

PC27

LDO3

P C36
1U_0805_25V4Z~D

MAX1999EEI_QSOP28~D

PW R _SRC
PR30

SUSPWROK_5V <31,39,45>

PC41
2

2

<18,34,37,44,46> R U N P WROK

2

SHDN

EXT

9

SI4835DY_SO8~D

4

(+12V+-5%,2A)

1K_0603_5%~D
PL8

REF

0.1U_0805_50V7M~D

1

1

PC39

CS

P C42

PR36
172K_0603_1%~D

6
P D13

0.04_2512_1%~D
PC224

EC31QS04~D
2

1

100P_0603_50V8J~D

P C40
47U_16V

4
2

FB

2

5

0.1UF_0603_16V7M~D

GND

2

4.7U_0805_6.3V6K~D

2

OUT

PR223

1

MAX1745_10uMAX
+3.3VRTC

+12VP

22U_SIL104-220_2.9A_30%
1
2
1

1

3

<37> THERM_STP#

VL

2

2
P C45
2
1

PQ7

VH

IN
<39> AL WON

TC7SH32FU_SSOP5~D

7

1

I0

P R40
1

4.7U_1210_25V6K~D

2

O
5

<33,39> VAUX_EN

PU19
P U4
4

PC44

PC43
1U_0805_25V4Z~D

5
6
7
8

2

I1

P

1

<33> S US_ON

G

3

1

4.7U_1210_25V6K~D

3
2
1

2

1

100K_0603_5%~D

2

1

10U_1206_10V4Z~D

10

0_1206_5%~D

P R34
P C38

8

1

P C37
1000P_0603_50V7K~D

2

240K_0603_5%~D

2

1

1

+3VALW
1

2

P R33

PR31
2K_0603_5%~D

C

+3VSRCP

2

2

1

<33> S US_ON

1

C

1

+

+

2

2 PC225

PR41

1

@ 47U_16V
20K_0603_1%~D

B

1

B

(2A,80mils ,Via NO.= 4)

PJP1
+12VP

1

2

+12V

+5VALW Source

PAD-OPEN 4x4m

1

2

+5VSUS

+5VSUSP

+RTC_PWR

PAD-OPEN 4x4m

PQ12
@SI2301DS 1P_SOT23~D

PQ13
@SI2301DS 1P_SOT23~D

(4A,160mils ,Via NO.= 8)
2

1

S

D

3

S

D

+3VALW

3

+3VSRC
G

1

+3.3VRTC

1

PJP3
+3VSRCP

+3VALW Source

+5VALW

(6A,240mils ,Via NO.= 12)

PJP2

PR45
@ 100K_0603_5%~D
Z4704
1
2

PR46
@ 100K_0603_5%~D
1
2

PC50
1
@ 0.1U_0603_25V7K~D
+
P C48
@ 47U_D2_6.3VM~D
2

1

1

PC51
1
0.47U_0603_16V7K~D
+
@
P D14
P C49
2
1
@ 47U_D2_6.3VM~D
2
RB751V-40_SOD323~D

PD15

2

2

1

2

ALW_ENABLE#

<39> ALW_ENABLE#

2

2

G

PAD-OPEN 4x4m

RB751V-40_SOD323~D

A

A

Compal Electronics, Inc.
Title

3.3V/5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

43

of

54

5

4

3

2

1

+1.5VRUNP/+VTT_GMCHP
D

D

PL9
1
2

1
PC56
@15U_D2_25M_R90~D

PR47
1M_0603_5%~D

+5VSUS

P R57
715K_0603_5%~D

1

1

9

VDDP2

11
2

VDDP1

P C76
1000P_0603_50V7K~D
+VTT_GMCHP

17

2

7

BST1

BST2

DH1

DH2

LX1

LX2

21

1
2
0_0603_5%~D

20

1 PR52

2

P C68
0.1U_0805_25V7K~D
1

PL11

PR51 2

1

C

2

0_0603_5%~D

1
2
3

P C74

0_0603_5%~D
5

4.7U_0805_6.3V6K~D
P R54

1

2

4

ILIM1

ILIM2

1

18

8.87K_0603_5%~D
1

2

DL1

2
1
2
3
4

DL2

16

P C72

P C71
+ 470U_D2_2.5VM

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2

2

2

1

PR233
0_0603_5%~D

8
7
6
5

P C73

SI4814DY_SO8~D

10

P R58

@ 47P_0603_50V8J~D

@ 0.01U_0603_50V7K~D
FBK1

FBK2

38.3K_0603_1%~D

12
1

26

2

2

2

VOUT2

1

2

VOUT1

@

2

PQ16

7.87K_0603_1%~D

24

1
PC221
+
220U_D2_4VM~D

19

P R53

1

2

1

PQ15
FDS6672A_SO8~D

2

5U_SPC_06704_5R0_2.9A_30%~D
6

1

1

PR50

4
EC31QS04~D

2

1
TON2
VCCA2

0_0603_5%~D
1

0_0603_5%~D

2

1

1

SC1485

VCCA1

PR49

PD17

PR232

P R55
36.5K_0603_1%~D

TON1

2
PC67
0.1U_0805_25V7K~D
2
1

8
7
6
5

4.7U_0805_6.3V6K~D

1U_0805_10V7K~D
P C66

1

@ 470U_D2_2.5VM
2

1

P C60
@15U_D2_25M_R90~D

2

2
2

PC70
1

PC220 +

470U_D2_2.5VM
C

1
2
3

3
1

+

4.7U_SPC-1205P-4R7B_+40-20%~D

1

25

2

1

P C69

1U_0603_6.3V6M~D
2
1

2

23
P C57
1000P_0603_50V7K~D

2

+

P C59

1U_0603_6.3V6M~D
1
2

1U_0805_10V7K~D
4

PL10

2

2

2

3

8
7
6
5

PC58
P C65

1

2
P C64
4.7U_1206_16V6K~D

0.1U_0603_25V7K~D
PQ14
IRF7811A_SO8~D

1

P C62
2

1

2200P_0603_50V7K~D

+1.5VRUNP

P C63
4.7U_1206_16V6K~D

1

PC61

1

PR48
10_0603_5%~D

1

PR231
10_0603_5%~D

P D16
DAP202U_SOT323~D

1

1

2

2

2
PC55
4.7U_1210_25V6K~D

2

2

2

1

2

PC53
0.1U_0603_25V7M~D

HCB4532K-800T90_1812~D

1
+

PW R _SRC

2

1

1

1

2

1

P C52
2200P_0603_50V7K~D

PC54
4.7U_1210_25V6K~D

EN/PSV1

EN/PSV2

P R60
20K_0603_1%~D

8

1

22
27

PGOOD1

PGOOD2

2

PR61
18.2K_0603_1%~D

13

PGND1

PGND2

AGND1

AGND2

15

2

1

1

14

1

28
P R65
1
0_0603_5%~D

PR214
0_0603_5%~D

0_0603_5%~D

2

2

SC1485
2

<18,33,37,39> R U N _ON

P U7

PR215

P R66

B

+5VSUS

2

1

+5VSUS

B

R U N PW ROK <18,34,37,43,46>

0_0603_5%~D
1

1

PR58
PR216
10K_0603_5%~D

1.225V
PRESCOTT

28.7K_0603_1%

1.45V
NORTHWOOD

38.3K_0603_1%

2

2

PR68
10K_0603_5%~D

PJP4
+1.5VRUNP

1

2

+1.5VRUN

VTT_PWRGD <37>
R UNPWROK_1P5V

PAD-OPEN 4x4m
PJP5
+VTT_GMCHP

1

2

+VTT_GMCH

PAD-OPEN 4x4m

A

A

Dell-Compal Confidential
Compal Electronics, Inc.
Title

+1.5VRUNP & +VTT_GMCHP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

B

Document Number

R ev
X00-G

LA-1711

Date: Tuesday, March 18, 2003

Sheet
1

44

of

54

5

4

3

2

1

D

D

PL12
1

P R85
1

PC222 +
PC223
@15U_D2_25M_R90~D
2
4.7U_1210_25V6K~D
2200P_0603_50V7K~D
0.1U_0805_25V7K~D

2

750K_0603_5%~D

TON2
VCCA2

VDDP1

VDDP2

11

BST2

2

21

1 PR72

20

0_0603_5%~D
P R75 2
1

6

DH1

DH2

LX1

LX2

DL1

ILIM2

0_0603_5%~D

2

2

P C89
1
1
2
3
4

0_0603_5%~D

1

P R79 2

2

PL14
1

10.7K_0603_1%~D
2

4

PC92

ILIM1

DL2

16

C

2
2.9uH

P R80
@ 100_0603_5%~D

2

1

1

8
7
6
5

SI4814DY_SO8~D

19
18

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2

12

5

V_1P25V_DDR_VTTP

PQ19

0.1U_0805_50V7M~D

P C96

2

BST1

PC94 1
1
150U _D2_6.3VM~D
+
+ P C95
150U _D2_6.3VM~D

4.7U_0805_6.3V6K~D
1

7

1

2
0_0603_5%~D

PC93

@ 1000P_0603_50V7K~D

2

P C86
1000P_0603_50V7K~D

17

PR78
1

1

9

1

VCCA1

PR71
1

0.1U_0805_50V7M~D
1 P R74
2

4

2

P C97
1000P_0603_50V7K~D
@

2

21

0_0603_5%~D
24

VOUT1

FBK2

12

2

2

150PF_0603_50V7K~D

2
PR235

7.5K_0603_1%~D

P R76
42.2K_0603_1%~D

SC1486

PC219
1U_0805_10V7K~D

8
7
6
5

8
7
6
5
4

1
2
3

PR234
0_0603_5%~D

EC31QS04~D
2

P C91
2
220U_D2_4VM~D

P R73
@ 100_0603_5%~D
1 2

+

1
2
3

2

PQ47
PQ18
FDS6672A_SO8~DFDS6672A_SO8~D PC88
2
1

PD19

1

2

1

2

3
1

P C90 1
220U_D2_4VM~D
+

C

PC85
25
1000P_0603_50V7K~D

2

2
2 UH

1

1

TON1

1

1
2
3

23
PL13

PC84
1U_0603_6.3V6M~D
2
1

2

4

+2.5V_MEMP

1

1

PC83
1U_0603_6.3V6M~D
1
2

DDR Termination Voltage

RB751V-40_SOD323~D

PC218
1U_0805_10V7K~D

2

2

2

2

10_0603_5%~D

PD30

2

PQ17
IRF7811A_SO8~D

PC217

+ 5VRUN
10_0603_5%~D

8
7
6
5

1

RB751V-40_SOD323~D
PD29

+2.5V/+1.25V

PC216

PR70

1

2

1
P R77

1

1

+5VSUS

2

4.7U_1210_25V6K~D

1

P R69
1M_0603_5%~D
1

0.1U_0805_25V7K~D

HCB4532K-800T90_1812~D

1

1

2

P C81
1
4.7U_1210_25V6K~D
+ P C82
@15U_D2_25M_R90~D
2

2

P C80

2

2

1

1

1

P C79
4.7U_1210_25V6K~D

P C78

2

1

PC77
2200P_0603_50V7K~D

PW R _ SRC

2

REFOUT

EN/PSV1

PGOOD2

10
2

FBK1

1

26
22
P R82
10K_0603_1%~D

REFIN

P R81
10_0603_5%~D
2 1

PGOOD1

13
8

2

27

PGND1

PGND2

AGND1

AGND2

15
1

1
28
<31,39,43> SUSPWROK_5V

14

PC100
1U_0603_6.3V6M~D

+2.5V_MEMP

2

PU 8
1

2

SC1486
PR217
0_0603_5%~D

PR87
10K_0603_1%~D

1

P R86
10K_0603_5%~D
@

2

B

1

B

2

2

PR88
10K_0603_1%~D

2

PC101
0.01U_0402_25V7K~D

1

1

+5VSUS

1

PR89
10K_0603_5%~D

V_2P5V_PWR GD

<37> V_2P5V_PWRGD

PJP6
PAD-OPEN 4x4m
1
2

+2.5V_MEMP

PJP7
PAD-OPEN 4x4m
1
2

+2.5V_MEM

(12A,360mils ,Via NO.=24)

A

A

PJP8
1

2

V_1P25V_DDR_VTT

V_1P25V_DDR_VTTP
PAD-OPEN 4x4m

(3A,200mils ,Via NO.=6)

Compal Electronics, Inc.
Title

1.25V/2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Date:

Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

45

of

54

5

4

3

2

1

D

D

PWR_SRC
+5VRUN
PR90
80.6K_0603_1%~D

PC102
1U_1210_50V7M

PR91

PU9
32

1

PR225
0_0603_5%~D
@
<8,36> VID4
<8,36> VID3
<8,36> VID2
<8,36> VID1
<8,36> VID0
<8,36> VID5

VCC

1
2
3
4
5
6

RAMPS

VID4
VID3
VID2
VID1
VID0
VID12.5

2

39
25

PWM1 <47>

ISEN1+
ISEN1-

24
23

ISEN1+ <47>
ISEN1- <47>

ENLL

33

DRSEN

PWM2

26

PWM2 <47>

DSEN#

ISEN2+
ISEN2-

27
28

ISEN2+ <47>
ISEN2- <47>

PWM3

20

PWM3 <47>

ISEN3+
ISEN3-

21
22

35

PWM4

31

ISEN4+
ISEN4-

30
29

2

38

EN

GND

OFS

1

<18,34,37,43,44> RUNPWROK

2

2

2N7002_SOT23~D
1U_0603_6.3V6M~D

PR116
1
2
0_0402_5%~D

1
1

1

D

PR123
2

PQ62

1

S

2

22K_0603_5%~D

PR120
2
1
0_0402_5%~D
PQ46
2N7002_SOT23~D
2 PR121 1
@
@ 0_0402_5%~D

4

+VCC_CORE

1

VCCSENSE <8>

VSSSENSE <8>

A

Compal Electronics, Inc.
Title

MMBT3904_SOT23~D

CPU_CORE_Controller

100K_0603_5%~D

3

Remote
Sensing

Place near +VCC_CORE
output capacitor

Size
Date:

5

1

1

1

PC112
4.7U_1206_16V6K~D

PR109

2

9.31K_0603_1%~D

2 PR119
@ 0_0402_5%~D

2
G

S

1

1

PR124
100K_0603_5%~D

PC111

340K_0603_1%~D

1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line.
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.

1

PQ45

PR205
5.1K_0603_1%~D

2N7002_SOT23~D
2
G

<7> VCORE_BOOTSELECT

PR204
3

PR220

3

D

PR118
27K_0603_5%~D

2
2

MIC5258

GND

1

+VCCVID

5

2

PR122
2
1
0_0603_5%~D

1

Panasonic ERTJ0EV334J (0402)
Locate this NTC resistor on
PCB between phase 2 and 3
for thermal compensation.

2
VOUT

Place close to IC
0.1UF_0603_16V7M~D
PC214

2

2

1

PR110
1M_0603_5%~D

B

PR111
1.87K_0603_1%~D
1
2

+5VRUN

8

ISL6247CR_QFN40~D

10K_0603_5%~D

PC109
PR115
@ 1000P_0603_50V7K~D @ 0_0603_5%~D
2
1
2
1

1

VDIFF
VSEN
VRTN

1

GND

PQ60
TP0610T_SOT23~D
2
PQ61

2

A

16
17
18

PR107
2
1
0_0603_5%~D

1

PG

3

4.7U_1206_16V6K~D

14

1

4

NC

2
1PC106
@ 1000P_0603_50V7K~D

3

VIN

VR-TT#
NTC

PR114

2

1

2
1

1

13

D

1.2VDD
PC110

FB

12
330K_0603_5%~D
19

PR112

PU10
2 PR117 1
0_0603_5%~D

DRSV

G

1

37

PR102
20K_0603_1%~D
1
2

S

2

PR104
90.9K_0603_1%~D
PR113
32.4K_0603_1%
VCORE_VTT

42.2K_0603_1%

+3VSUS

15

40

1

10K_0603_1%~D

PR108

COMP

PR106

10_0603_5%~D
2
PC108
220P_0603_50V8J~D
+3VRUN

B

<8> VID_PWRGD

FS

2

PR103

36

2

G
4

2
LM358M_SO8~D

ISEN4+ <47>
ISEN4- <47>
PC105
4700P_0402_25V7K~D
2
1

3

3

IN- 2
LM358M_SO8~D

1

4

IN+

O

2

100P_0603_50V8J~D

PU20A
1

2

6

P

IN-

O
G

7

PR101
17.4K_0603_1%~D

P

1

8

PC104
5

DSV

Frequency Select

8

1

9

PWM4 <47>

2

2

2

+5VRUN

@ 0_0603_5%~D

2

1

0.033U_0603_25V7M~D

+5VRUN

1

2

ISEN3+ <47>
ISEN3- <47>

1

3

@ 0_0603_5%~D

2 PR97

2

PC103

10 OCSET
PR96
1K_0603_1%~D
@
11 SOFT

2

1

1

PR98

@ 0_0603_5%~D
PR100
274_0603_1%~D
+5VRUN

1

PR99

1

2

0_0603_5%~D

IN+

C

+5VRUN

PR226
@ 0_0603_5%~D

PU20B

VCORE_PWRGD <37>

34

1

C

<36> VCORE_DSEN#

1

10K_0603_5%~D

PWM1

2

0_0603_5%~D
PR94 1
2

2

<36> VCORE_DRSEN
1 PR93

<8> VCORE_ENLL
PR95
0_0603_5%~D
@

2

7

PGOOD

1

1

PR92
@ 0_0603_5%~D
1
2

2

2

1

2

Battery Feed
Forward

2

Document Number

LA-1711

Tuesday, March 18, 2003

Rev
X00-G
Sheet
1

46

of

54

5

4

3

2

1

CPU_PW R_SRC

0.15U_0805_16V7K~D

1

1

1

PQ22
SI4362DY_SO8~D

PQ48
FDS7064N_SO8
@
4

PQ23

PQ49

SI4362DY_SO8~D
4

PR130

PR129
2.2_0805
@ FDS7064N_SO8@

4

2

32.4K_0603_1%~D

<46> ISEN1<46> ISEN1+

2

PC145

PQ26

2

2

1
2

1

1

1

PQ27
PQ51
4

SI4362DY_SO8~D

SI4362DY_SO8~D

4

4

1

1

1

1

1

1

1

1

PC123

2

2

2

2

2

2

2

2

1
+

PC139
1
@ 15U_D2_25M_R90~D
+

PC138

2
@ 15U_D2_25M_R90~D

2

PC143
1
1
@ 15U_D2_25M_R90~D
+
+

PC141 1
1
@ 15U_D2_25M_R90~D
+
+

PC140

2
@ 15U_D2_25M_R90~D

2

PC142

2
@ 15U_D2_25M_R90~D

1
+

PC144

2
2
@ 15U_D2_25M_R90~D

FDS7064N_SO8:
SI4362DY_SO8:
PQ22,PQ23,PQ26,PQ27, PQ48,PQ49,PQ50,PQ51,
PQ30,PQ31,PQ34,PQ35 PQ52,PQ53,PQ54,PQ55

1

2

+VCC_CORE

C

0.56U_ETQP4LR56WFC_21A_20%~D
PC148
@1000P_0603_50V7K~D
+3VALW
PR138
2.2_0805 2
@

1

PR139

Address select(7414ART-0)
Float: 1001 000
GND: 1001 001
VDD: 1001 010

PC151
1

2

32.4K_0603_1%~D

1

PR219
10K_0402_5%~D

0.01U_0603_16V7K~D

2

3
2
1

3
2
1

@ FDS7064N_SO8

3
2
1

3
2
1

D

Low-side two population options

4
@ FDS7064N_SO8

LG2

PC137 1
@ 15U_D2_25M_R90~D
+

PC135
15U_D2_25M_R90~D
PC136
2
2
@ 15U_D2_25M_R90~D

2

1

1

PQ50

ISL6207CB-T_SO8~D

PC149

+

Panasonic ETQ-P4LR56WFC

5

1U_0805_25V4Z~D

PC122

PC207
2200P_0603_50V7K~D

Snubber
1

LGTE

PC121

PTC resistor

Local Transistor
Swtich Decoupling

2

2

4

1

+

PL17
5
6
7
8
9

PHSE

GND

PR211
2
1
1
0_0603_5%~D
Phase2
8
5
6
7
8

PR136
@ 499K_0603_1%

PC203

1

3
2
1

EN

2

PC120

0.1U_0603_25V7M~D

5
6
7
8
9

UGTE

1U_0603_6.3V6M~D

4

3
2
1

BOOT

PWM

10U_1210_25V6K~D

2

IRF7811W_SO8~D

5
6
7
8

C

VCC

PC147
PC146

PQ25

U G2

1

7

2

5
6
7
8

5
6
7
8

2

PQ24

IRF7811W_SO8~D

PU12

3

@

1
820_0603_1%~D

2

4

6

PC119

CPU_PW R_SRC

PR133

CPU_PW R_SRC

<46> PWM2

PC118

10U_1210_25V6K~D 10U_1210_25V6K~D 10U_1210_25V6K~D
10U_1210_25V6K~D
10U_1210_25V6K~D
10U_1210_25V6K~D
10U_1210_25V6K~D

1

0.01U_0603_16V7K~D

3
2
1

3
2
1

3
2
1

3
2
1

1

DUAL FOOTPRINT

0.15U_0805_16V7K~D

0.1U_0603_25V7M~D

PC134

2

1

LG1

4

PR134
0_0603_5%~D

PC117

10U_1210_25V6K~D

2

0.56U_ETQP4LR56WFC_21A_20%~D
PC131
@ 1000P_0603_50V7K~D

1U_0805_25V4Z~D

1

2

2

2

1

2

PC116

Panasonic ETQ-P4LR56WFC

5

ISL6207CB-T_SO8~D

Input Bulk and HF Capacitors

PL16
1

2

LGTE

PC215

1

4

CPU_PW R_SRC

Snubber
1

GND

PR210
2
1
1
0_0603_5%~D
Phase1
8

5
6
7
8
9

PHSE

0.1U_0603_25V7M~D
10U_1210_25V6K~D

3
2
1

EN

2

5
6
7
8
9

UGTE

3
2
1

BOOT

PWM

CPU_PW R_SRC

CHT_C8BBPH853025

PC206

2 2

PC132
0.1U_0603_16V7K~D

PC133
2

2

0_0603_5%~D

IRF7811W_SO8~D

5
6
7
8

7

VCC

1

1

PR127
@ 499K_0603_1%

1

1

2

D

PR153
2

PW R_SRC

2

4

U G1

1

PU11

3

PC202

1

2200P_0603_50V7K~D

IRF7811W_SO8~D
4

6

PC114
1U_0603_6.3V6M~D
PC115

5
6
7
8

PR125
0_0603_5%~D

PQ21

2

PQ20

1

5
6
7
8

1

2

2

5
6
7
8

PC113

+5VRUN

<46> PWM1

PL15

Local Transistor
Swtich Decoupling

PU18

DUAL FOOTPRINT
<46> ISEN2<46> ISEN2+

PR142
2

CPU_PW R_SRC

2

PC152

0.15U_0805_16V7K~D

+3VALW

PTC resistor

Local Transistor
Swtich Decoupling

2200P_0603_50V7K~D
1U_0603_6.3V6M~D

2

2

0.1U_0603_25V7M~D
2

IRF7811W_SO8~D

2

IRF7811W_SO8~D

2

PR143
0_0603_5%~D

PC208

3

1

PC154
10U_1210_25V6K~D PC204

1

PC153

1

PQ29

1

2

PQ28

1

2

5
6
7
8

820_0603_1%~D
5
6
7
8

1

1
1

Snubber
1

LGTE

PQ30

1

1

PQ52
4

PQ31

4
PQ53

SI4362DY_SO8~D
4

4
@ FDS7064N_SO8

LG3

SI4362DY_SO8~D

FDS7064N_SO8 PR147
2.2_0805 2
@

3
2
1

3
2
1

3
2
1

3
2
1

@

PR148

PC158
1

2

32.4K_0603_1%~D

<46> ISEN3<46> ISEN3+

U G4

2

2

2

1
2

1

1

1

5
6
7
8

5
PQ34

1

SI4362DY_SO8~D

1

2

2
4
PQ35

PQ55

1

@ FDS7064N_SO8
3
2
1

3
2
1

3
2
1

SI4362DY_SO8~D
3
2
1

LG4

@ FDS7064N_SO8

Add thermal venting vias to board. Vias under parts must have a
minimum pitch of 1mm and hole size of 0.3mm to avoid solder
wicking.
A

4

4

Depending on the processor final requirments and empirical
thermal result testing a 3 phase solution may be possible. In
the 4 phase configuration a single upper mosfet may also be
sufficient.

0.56U_ETQP4LR56WFC_21A_20%~D

PC162
@ 1000P_0603_50V7K~D

PQ54
4

1U_0805_25V4Z~DISL6207CB-T_SO8~D

PL19

Snubber
1

LGTE

Panasonic ETQ-P4LR56WFC

2

4

0.1U_0603_25V7M~D

5
6
7
8
9

PC164

PC209
2200P_0603_50V7K~D

Local Transistor
Swtich Decoupling

3
2
1

PHSE

GND

PR213
2
1
1
0_0603_5%~D
Phase4
8

1U_0603_6.3V6M~D

5
6
7
8
9

EN

2

3
2
1

UGTE

PC161
10U_1210_25V6K~D PC205

4

5
6
7
8

BOOT

PWM

2

2

7

PR154
@ 499K_0603_1%
1

A

VCC

PTC resistor
PC160

IRF7811W_SO8~D

1

3

PQ33

IRF7811W_SO8~D
4

PU14
6

PQ32

5
6
7
8

2

5
6
7
8

2

PR156
2.2_0805 2
@

PR157

PC165
1

2

32.4K_0603_1%~D

DCR
Inductor
Sensing

1
0.01U_0603_16V7K~D

Compal Electronics, Inc.
Title

PR160
820_0603_1%~D

DUAL FOOTPRINT

5

1
4

Size

PTC resistor

<46> ISEN4<46> ISEN4+
3

B

1
820_0603_1%~D

0.15U_0805_16V7K~D

1001 001X (X=1-->Read; X=0-->Write)

Notes:

Sync. Rectifiers use thermally enhanced "PowerPak" technology in
an SO-8 form-factor. Optimal MOSFETS will be chosen based on
thermal performance.

PR151

PC159

<46> PWM4

1

2

CPU_PW R_SRC

PR152
0_0603_5%~D

AD7414ART-0_SOP23-6
PC210
0.1U_0402_16V4Z~D

0.01U_0603_16V7K~D

DUAL FOOTPRINT

1

ATF_INT# <19,33>

CLK_SMB <19,26,34,35>

The ISL6561(ISL6427) supports lossless current sensing including
Inductor DCR and MOSFET rDSon sensing. Schematic components are
color coded accordingly. In addition an external sense resistor
can be used for higher load-line accuracy but this will impact
system cost and efficiency.

0.56U_ETQP4LR56WFC_21A_20%~D
PC155
@ 1000P_0603_50V7K~D

5

2

4

2
0_0603_5%~D

2

2

PC157

1U_0805_25V4Z~DISL6207CB-T_SO8~D

1

1

GND

Panasonic ETQ-P4LR56WFC

5
6
7
8
9

PR145
@ 499K_0603_1%

DAT_SMB <19,26,34,35>
1
PR222

4

PL18
5
6
7
8

PHSE

SCL

6
5

3
2
1

UGTE

EN

PR212
2
1
1
0_0603_5%~D
Phase3
8
5
6
7
8

PWM

VDD

ALERT

Address

2

2

2

7

BOOT

5
6
7
8
9

3

<46> PWM3

B

VCC

3
2
1

6

SDA

GND

4

U G3

1

4
PU13

AS

2

Date:
2

CPU_CORE_Power-Stage
Document Number

R ev
X00-G

LA-1711

Sheet

Tuesday, March 18, 2003
1

47

of

54

5

4

3

2

1

DC_IN+
+5VALW

+RTC_PWR

2

PR162
1K_0603_5%~D

PR164
1

PR167

1

12.7K_0603_1%~D

8

DLOV

DHI
CCV
DLO

23

DLO

2

2

CHG_CS 1

3.2UH_12.8A

2

0.01_2512_1%~D

3
2
1
2

CSIN
BATT

CSIN

20
19

PBATT+

PC194

2
2

IMAX

9

2
1

B

10
2

1

0.1U_0603_25V7K~D
CHVREF

31.6K_0603_0.1%~D
PR189
182K_0603_0.1%~D

1 CHVREF

1

PR185
2

1

2

1_0603_1%~D
PC195
0.1U_0603_25V7K~D

280K_0603_1%~D

PR184
182K_0603_1%~D
1

1

PC186

5
18

CHVREF 4

1

2

3

1

PR182

VMAX

2

PC185
PQ40
D BSS138_SOT23~D
0.1U_0603_25V7K~D
PD23
2
G
1
2
CHG_PBATT <34>
S
RB751V-40_SOD323~D
PR191
100K_0603_5%~D
1

2
PR190
2K_0603_1%~D

GND
GND

/INT MAX1535X_QFN32~D
REF

1

16

1645_DAC
11 DAC

PR186
1

1

PR187
10K_0603_1%~D
TH

PR183
1
2
1_0603_1%~D

CSIP

SCL

2

C

PC184
15U_D2_25M_R90~D
@

21

SDA

1

15

1
PC190
4.7U_1210_25V6K~D +

PR181
@ 1.2K_1206_5%~D

2

THM

PC189
0.1U_0805_50V7M~D

PC188
4.7U_1210_25V6K~D

22

2

2

14

PC187
4.7U_1210_25V6K~D

1

PGND
CSIP

<34,42> PBAT_SMBDAT
PR188 TM
PC192
1500P_0402_50V7K~D
10K_0603_1%~D
<34,42> PBAT_SMBCLK

3

PR177

EC31QS04~D

2

1

13

1

2
PL20

4

2
2
PC193
1U_0805_25V4Z~D

1

PBATT+
PQ38
FDS6672A_SO8~D
1
PD22

26

VDD

0.01U_0603_50V7K~D

2

1

1

1

2

2
1
PC174
0.1U_0603_25V7K~D

2

24

CCS
CCI

2

2

1

3
2
1

PC171
1
2
1U_0603_6.3V6M~D

PR175
33_0603_5%~D

5
6
7
8

I.C.

29

28

17

1U_0805_25V4Z~D

2

1

12

30

2

7
PR176
1
2 C CV
10K_0603_5%~D

10K_0603_5%~D

DLOV

PC212
10U_1210_25V6K~D

2

ACIN
ACOK

PC173
2
@15U_D2_25M_R90~D

1

6

LDO

PC176
0.1U_0805_50V7M~D

1

2 PR179

0.01U_0603_50V7K~D
+5VALW
PC183

75K_0402_1%~D

1
10K_0603_5%~D
1

1 PC211
10U_1210_25V6K~D
+

1

2

ACOK 32

PC177
0.1U_0805_50V7M~D

2

2

1

FDS6679Z
4

1

1

1
0.01U_0603_50V7K~D
PC181 1
2

2 PR173

PDL

DCIN

2

5
6
7
8

0.01U_0603_50V7K~D
<34,39,49> ACAV
PR178

PC180

C

3

SRC

25

2

1

PC182

DHIV

1

27
D CIN

PC172
1
2

PDS

CSSN

31

CSSP

PR174
1
2
@ 100K_0603_5%~D

PC175
2200P_0603_50V7K~D

2

1

1

1

1

PQ37
PU6

AS2431_SOT23~D

CHAGER_SRC

0.1U_0805_25V7K~D

PR171
100K_0603_5%~D

2

MCK4532800YAT_1812

PC170
0.1U_0805_25V7K~D

PC169

2

PC168

1U_0805_25V4Z~D

1M_0603_5%~D
PU15

2

PR169
1K_0603_5%~D

PR170

CSSN

2

2

CSSP

1

1
PL22

1

2

RB751V-40_SOD323~D

1

1
2

2

10U_1210_25V6K~D

10U_1210_25V6K~D

D

ACAV

1

+SDC_IN

4.7 _0402_1%~D

2

PD20

10K_0603_1%~D
PR168
1
2

1

ACOK

2

2

PC166

1

1

PC213

PQ36
2SA1036K_SOT23~D

2 2

1

PR166
4.7 _0402_1%~D

D

3

2

2

75K_0402_1%~D

1

2

DC_IN+

PR161
PR172
100K_0603_5%~D
@

2

PR165
1
2
0.01_2512_1%~D

1

1

+SDC_IN

B

1U_0603_6.3V6M~D

VMAX=3.49V
Maximum charger voltage=17.45V
IMAX=1.6V
Maximum charger current=8A

A

A

Compal Electronics, Inc.
Title

CHARGER CONTROL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

48

of

54

5

4

3

2

1

D

D

PWR_SRC

PD25

DC_IN+ discharge path

2
@

1
PQ41
RB083L-20_SOD106~D
SI7447DP_SO8
1
2
3

5

2

2200P_0603_50V7K~D
PR199
1

1

PR198

PQ42
BSS138_SOT23~D

2K_0603_1%~D
2

PR201
1

1

D

2
G

D

3

1

3

<34,39,48> ACAV

1

2
PR200
2

S

2
G

S

1

2

10K_0603_5%~D
PQ43
BSS138_SOT23~D
PD26
2

2

PC199

4

PR197
10K_0603_5%~D

C

PC200
0.1U_0805_50V7M~D

1

C

1

2

+SDC_IN

100K_0603_5%~D

RB083L-20_SOD106~D
1
PQ44
SI7447DP_SO8

100K_0603_5%~D

1
2
3

5

PWR_SRC

4

PBATT+

PD27
2

1

1

1SS355_SOD323~D

B

B

2

PR202
470K_0603_5%~D

A

A

Compal Electronics, Inc.
Title

Battery Discharge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

49

of

54

5

4

3

2

1

+ 3VRUN

D

D

5

C640
1
2

1

A

O

4

SUB_SHUTDOWN#

TC7SH08FU_SSOP5~D

1

1

U 44

B

3

2

P

<24,25> SPK_SHUTDOWN#

G

+ 3VRUN

0.1U_0402_16V4Z~D

Need to FILTER!!!

R590
10K_0402_5%~D

1

2

+12V
D

3

2

R589
10K_0402_5%~D

S

Q74
2N7002_SOT23~D

2
G

<42> SUB_DETECT

2

1

1

C641
0.1U_0402_16V4Z~D

2

C 642
10U_1206_16V4Z~D

+12V

U 45
C 655
1000P_0402_50V7K~D
1
2

24
SUB_SHUTDOWN#

5

C

C644
1
2
AUD_MON O_OUT

<24> AUD_MONO_OUT

C645
1
2

0.22U_0603_10V7M~D
SUB_GAI N0

0.22U_0603_10V7M~D

2
3

SUB_GAI N1

4

C648
1
2

7

Gain Setting

1U_0805_10V6K~D

PVCC
INN
OUTN
INP
OUTN

1

8

11

C 646
2

51_0603_1%

L49

1
1

1

1

C 650

VREF
BYPASS

OUTP

CSOC

OUTP

AGND
19

AGND

PVCC
PGND

RSOC
PGND

SUB_OUT1 <42>

1
C 647
1000P_0402_50V7K~D

1

VCLAMP

PGND

1

20

BSP

14

2

1

2

2

C 649
1000P_0402_50V7K~D
SUB_OUT2

SUB_OUT2 <42>

BLM21PG600SN1D_0805~D

15
1U_0805_10V6K~D
16

DIODES B130

R594

17

1

2

51_0603_1%
TPA3001D1

L50

D 21

1

C652
1
2
0.22U_0603_10V7M~D

+12V

R 597
100K_0402_5%~D
Link CIS
20.2

2

R596
@ 100K_0402_5%~D

2

DIODES B130

GAIN1

6

2

2

SUB_GAI N1

1

R595
120K_0402_5%~D

1

C654
220P_0402_50V8J~D

2

C653
1U_0805_25V4Z~D

21

SUB_GAI N0

SUB_OUT1

2

BLM21PG600SN1D_0805~D

1U_0805_10V6K~D
D 20

18

1
C 651
1U_0805_10V6K~D

0.22U_0603_10V7M~D

10

GAIN0

13

R 593
@ 100K_0402_5%~D
2

2

R592
100K_0402_5%~D

C643
1
2

2

C

9

2

23
22

2

BSN

1

1

S UB_VREF

SHDN-

12

S UB_VREF

1

R591

VCC

B

B

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Subwoofer
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

50

of

54

5

4

3

Version Chang
Changee List ( P. I. R. List )
Item
It em Page#
D

T itle
Prescott
Processor

D ate

Request
Reque st
O wner

2

1

Page
Pag e 1/3
Issue
Is sue Description

Solution
So lution Description

R ev.

2/17/2003

Compal

ITP Connector default depopulate

Depop RN8 (RN8 is populted on M00)

X00-A

SpringdaleDDR Interface

2/17/2003

Compal

Resistor value SPEC isn't meet Intel recommend

Correct R367,R109 from 40.2_0603_1% to 42.2_0603_1%
(M00 R109,R367 are mount 42.2_0603_1%)

X00-A

21

ICH5-IDE/LPC/
PM/GPIO/LAN

2/17/2003

Compal

Dell M00 Board Bring up issue item4:
ICH5 PIN Y18, A19 are swapped on JHDD in the schematics and
Pins V20, V22 are also swapped. HDD can't boot.

Swap IDE_PDCS1# and IDE_PDCS3#;
Swap IDE_SDCS1# and IDE_SDCS3#.

X00-A

4

23

D-MODULE

2/17/2003

Compal

Correct power net from +3.3VMOD to +3VMOD

X00-A

5

23

D-MODULE

2/17/2003

DELL

Need to cross the TX and RX lines on the motherboard side

6

26

USB(2.0)
Connector

2/17/2003

DELL

Del all mark "2@" symbol, All components default must
populate. Nimitz and Beijing both are support Dog House.

Del all mark "2@" symbol, All components default must
populate. (All mark"2@" components are populate on M00 Board)

X00-A

1

8

2

11

3

C

Dell M00 Board Bring up issue item5:
+3.3VMOD power net no power source.we have two signal names
for +3.3VMOD /+3VMOD, need jump wire.

Change
Change
Change
Change

JMOD1
JMOD1
JMOD1
JMOD1

pin8 from SATA_MODTX+ to SATA_MODRX+
pin10 from SATA_MODTX- to SATA_MODRXpin14 from SATA_MODRX+ to SATA_MODTX+
pin16 from SATA_MODRX- to SATA_MODTX-

X00-A

C

7

37

Thermtrip &
PowerGOOD

2/17/2003

Compal

Dell M00 Board Bring up issue item3:
No generate system clock.
U25 Pin1 and Pin 2 need to be shorted together, VCORE_PWRGD is
an OD signal and it does not have a pullup.

VCORE_PWRGD signal add a 10K_0402_5%(R581) resistor pull up
to +3VSUS.

X00-A

8

25

AMP and
PHONE JACK

2/27/2003

DELL

Change OP amplifier power from +12V to +5V ,change audio
amplifier as same as Abacus-MT

Change audio amplifier from TPA3002D2PHP to TI6017A2
(BOM need change)

X00-C

9

29

LAN Transfomer 2/27/2003

DELL

ME Connectors are interfere

Change RJ11/RJ45 receptacle connector to staddle type

X00-C

10

18

11

6,34,36

VGA Daughter
Board Conn.

3/05/2003

Compal

Dell EE issue item38:
Change AGP connector vendor

Change connector from ACES_88075-1600 to FOXCONN
FOXCONN_QT00160A-9120L (BOM need change)

X00-D

Clock Generator

3/05/2003

DELL

Dell EE issue item22:
This change is required due to not getting the 24MHz clk
of the EC to work.

1.Del 24M_CLK net and R210(33_0402_5%)
2.Add series termination R587(33_0402_5%) near CK409 and
R588(0_0402_5%) near the CPLD. Add net name from CK409 to
CPLD. (BOM need change)

X00-D

B

B

12

8

Prescott
Processor

3/05/2003

DELL

Dell EE issue item23:

To prevent backdrive in S3

Change RN7,R35,R37 pullups from +3VSUS to +3VRUN.

X00-D

13

21

ICH5-IDE/LPC/
PM/GPIO/LAN

3/05/2003

DELL

Dell EE issue item25:

This pin is not 5V tolerant.

Change R388 pullup from +5VRUN to +3VRUN.

X00-D

14

33,36

SIO (1/2) & PLD

3/05/2003

DELL

Dell EE issue item26:
Change name of the follow signal from GV_LO_HI# to GV_HI_LO#

Change name of the follow signal from GV_LO_HI# to GV_HI_LO#

X00-D

15

25

AMP and Phone
Jack Interface

3/05/2003

DELL

Dell EE issue item39:
1.Change the population option for R583 and R584 to no pop
2.Change the voltage rai lto D7, D6, D9, D8 to +5VRUN

1.R583,R584 Add "@" symbol and depop.
2.Change power from +12V to +5VRUN.

X00-D

16

18

VGA Daughter
Board Conn.

3/05/2003

DELL

Dell EE issue item37:
Table for ST1 and ST2, were did this table come from?

Delete ST1,ST2 table and R324~R327 (BOM need change)

X00-D

17

12

Springdale-AGP
/HUB/VGA/CSA

3/05/2003

DELL

Dell EE issue item36:
AGP8X_DET_GC circuit need to change per the errata change.

Change Q13 from MMBT3904 to 2N7002; R55 from 33.2_0603_1% to
39.2_0603_1% (BOM need change)

X00-D

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

D

2

EE_P.I.R History
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

51

of

54

5

4

3

2

1

Version Chang
Changee List ( P. I. R. List ) Page
Pag e 2/3
Item
It em Page#
D

C

B

T itle

D ate

Request
Reque st
O wner

Issue
Is sue Description

Solution
So lution Description

R ev.

18

21

ICH5-IDE/LPC/
PM/GPIO/LAN

3/07/2003

Compal

HDD pinout are reversed

Change pinout and and connector part number(BOM need change)

X00-E

19

23

D- MODULE

3/07/2003

Compal

Change D- Module connector (Mating Height issue)

Change connector from JAE_WM1F068N1A to Foxconn
QL11343-A6B3-HT

X00-E

20

26

USB(2.0)
Connector

3/07/2003

Compal

ME Connectors are interfere

Change connector to staddle type. Foxconn Fox_UB11193-P01-TR
(BOM need change)

X00-E

21

11

Springdale-DDR
Interface

3/07/2003

Compal

Dell M00 Board Bring up issue item34,35:
SMXRCOMPVOH - add 0.1UF cap from +2.5V (pin2 of C65) to GND
SMYRCOMPVOH - add 0.1UF cap from +2.5V (pin2 of C53) to GND

Add C636 and C637(0.1U_0402_16V4Z) [BOM need change]

X00-E

22

36

PLD

3/08/2003

DELL

Dell M00 Board Bring up issue item27
Need to change PLD pinout per the right package program.

Follow CPLD rework instruction, correct U27 symbol pin out.

X00-E

23

36

PLD

3/08/2003

DELL

Dell M00 Board Bring up issue item28
Eliminate the VID MUX and keep the zero Ohm resistors

Del U1,C10,R14,R18,RP1,R13 (BOM need change)

X00-E

3/08/2003

DELL

Dell M00 Board Bring up issue item24
Change the table on pg 36 to reflect the correct refdes and
components see PLD rework instructions

Page36: Pop U27, C233, C606, R557 ;Pop Q42, R254, Depop R259 ;
Pop Q43, R561, Depop R251,R243 ; Pop R256, Depop R252; pop
R245, R253
Page18: Depop R96, Pop R98
Page8 :Pop R76,R78,R380
Page46: PR94,PR93, Depop PR95,PR92 [BOM need change]

X00-E

24

8,18,36

25

8

Prescott
Processor

3/12/2003

DELL

Dell M00 Board Bring up issue item32
Depop pullup R84 on H_RESET# since we have another pullup R358

Depop R84 ,62_0402_5%(BOM need change)

X00-F

26

11

Springdale-DDR
Interface

3/12/2003

DELL

Value is not correct

Change C636,C637 (0.01U_0402_16V7K) [Add it on BOM]

X00-F

27

14

FAN CONTROL

3/12/2003

Compal

ME connector design change

Change JFAN2 from MOLEX_53261-0310 to MOLEX_53398-0390; Delete
JFAN1 [BOM need change]

X00-F

28

15,19

CPU Thermal
Sensor & FAN
Control

3/12/2003

DELL

To saving cost

Delete U35(AD7414ART-0),R345(10K_0402_5%),R348(0_0402_5%),
C383(0.1U_0402_16V4Z); Add Q73(MMBT3904) [BOM change]

X00-F

29

19

CPU Thermal
Sensor & FAN
Control

3/12/2003

Compal

ME connector design change

Change JFAN3 from MOLEX_53261-0310 to SUYIN_250019MR003G400ZL
[BOM need change]

X00-F

30

25

AMP and
PHONE JACK

3/12/2003

Compal

ME connector design change

Change JSPK from MOLEX_53261-0690 to MOLEX_53398_0890;
change JP1 from HRS_DF20-10DP-1V to NAIS_AXN320C038P; Add
C638,C639(22U_1206_16V4Z) [BOM need change]

X00-F

Subwoofer

3/12/2003

DELL

Add Subwoofer circuit

Page24: U16 pin37 connect to C646 pin1(AUD_MONO_OUT)
Page25: Del R586(100K_0402_5%) [BOM need change]
Page50 : Add subwoofer circuit [Add ]

X00-F

31

CardBus Socket

3/12/2003

DELL

All model support smart card function

Update page3 Table and change mark "1@" symbol to "@"

X00-F

33

21

ICH5-IDE/LPC/
PM/GPIO/LAN

3/12/2003

DELL

Follow Intel DG (12837)ICH_SYNC# circuit implementation

Depop R161,R167,R169,Q32,Q33 and pop R438(0_0402_5%)
need change]

34

31

CardBus Socket

3/13/2003

Compal

Correct Item32

Populate U17 and L14, delete "1@" symbol [Don't need change
BOM]

31

32

24,25,50

for phone Jack and Int.SPK

A

[BOM

5

4

3

2

A

EE_P.I.R History
Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

B

X00-G

Compal Electronics, Inc.
Size

C

X00-F

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

52

of

54

5

4

Version Chang
Changee List ( P. I. R. List )
Item
It em Page#
D

35

27,31

36

31

37

38

T itle

D ate

3

2

1

Page3/3
Page3 /3

Request
Reque st
O wner

Issue
Is sue Description

Solution
So lution Description

R ev.

3/14/2003

Compal

ME connector design change

Page27 :Change JMDC from FOX_QT8A0301-3011 to AMP_3-1612118-0
Page31: Change JCBUS form FCI_61082-081001 to
FOX_1CA87501-T1~D; Change J1394 from FOX_UV31413-K8 [BOM need
change]

X00-G

CardBus Socket

3/14/2003

DELL

Dell Schematic issue item12
Please add a 100PF cap to SC_DATA_C per TI late recommendation

Add C656(100P_0402_50V7K). [BOM need change]

X00-G

8

Prescott
Processor

3/14/2003

DELL

H_DPSLP# doubule pull up

Depop R79(62_0402_5%) , [BOM need change]

X00-G

25

AMP and
PHONE JACK

3/14/2003

DELL

Dell Schematic issue item48
Remove comment above U18 and

Connect C638 and C639 to INT_TWT_R1 and INT_TWT_L1 at JSPK

X00-G

remove the wires in the bottom

39

25

AMP and
PHONE JACK

3/14/2003

DELL

Dell Schematic issue item48
Change the pinout of JAUDO

Change net FAN1_TACH_FN from pin16 to pin18, pin15,16 connect
to GND

X00-G

40

29

LAN TRANSFOMER

3/14/2003

DELL

Dell Schematic issue item45,46
the BJT werent driving the LED enough

1.Change Q3 from DTC144KA_SOT23 to 2N7002
2.LED_WLAN5_RADIOSTATE, LED_WLAN24_RADIOSTATE, and
WLAN_LED_ACIVITY. Add 10K_0402_5% pulldown resistor(R600~R602)
[BOM need change]

X00-G

Dell Schematic issue item48
Move D18 and D19 to page 42, and update all component Symbols

Move D18 and D19 to page 42, and update all component
Symbols , move C655 from current location to in between
C645 and U45 pin 2 and change value to 1000P_0402_50V7K

Dell Schematic issue item30
Springdale DG P65 recommed a 10 Ohm resistor
to Pin VDD_48 (pin34) of Ck409

Reserved power source option: populate R589, depopulate R599
[BOM need change]

X00-G

C

41

50

Subwoofer

3/14/2003

DELL

42

6

Clock Generator

3/14/2003

DELL

Delete by Dell's update issue_0314 ;X00-H

from CK_VDD_MAIN

C

X00-G

43

11

Springdale-DDR
Interface

3/18/2003

Compal

Intel recommend is 31.12K,the value isn't popularize.
Follow Dell's DT team use 30.9K

Change R101,106,369,373 from 31.12K_0603_1% to 30.9K_0603_1%
;[BOM need change]

X00-H

44

25

AMP and
PHONE JACK

3/18/2003

Compal

Add one net

Change JAUDO pin11 from NC to AMPVCC

X00-H

3/18/2003

Compal

Single name issue

Delete pin 22 of U27 net and show text ; move U25B from page39
to page40, change pin4,5 to GND and pin6 to NC.

X00-H

45

36,39,40

D

for Phone Jack board pullup source.

B

B

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

EE_P.I.R History
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

53

of

54

5

4

3

2

1

POWER Version Change List ( P. I. R. List )
Item
It em Page#
D

1

45

2

43

3

46,47

4

46

T itle
1.25V/2.5V

D ate

Request
Reque st
O wner

Issue
Is sue Description

Solution
So lution Description

Dell M00 Board Bring up issue item13:
Make SUSPOWROK_5V a strong pullup.

2/26/2003

Compal

3.3V/5V

2/26/2003

DELL

Dell M00 Board Bring up issue item21:
Need to add pads for voltage/temp tolerance measurements.
Request from our Reliability engineers.

CPU_CORE_Controller
CPU_CORE_Power-Stage

2/26/2003

DELL

Dell M00 Board Bring up issue item29:
Change CPU controller and driver VCC to +5VRUN
to reduce S3 current.

3/05/2003

DELL

CPU_CORE_Controller

R ev.

Depop PR86 (PR86 is populted on M00)

X00-B

Add voltage divider at +5VSUSP(PR227, PR229)
Add voltage divider at +3VSRCP(PR228, PR230)

X00-B

Change PU9 and PU11, PU12, PU13, PU14 VCC
to +5VRUN

X00-B

Dell X00 Board issue item40,41:
Change the power rail to the following components
PU20A/B, PC214 from +5VSUS to +5VRUN

D

X00-D
PR99,

Change the power rail of PR99 and PU20A/B,
PC214,PR97 from +5VSUS to +5VRUN

Change the power rail to the following component PR114
from +3VSRC to +3VRUN

Change the power rail of PR114 from +3VSRC to +3VRUN

Intersil ISL6225B IC issue. So change controller IC.

Change PU7 to SC1485 and PU8 to SC1486.

Dell X00 Board issue item47:
Intle in the DG 1.21 update have changed the DDR voltage
to 2.6V and Term voltage to 1.3.

Change PR72 to 42.2K

C

C

5

44,45

6

45

+1.5VRUNP/ +VTT_GMCHP
1.25V/2.5V

1.25V/2.5V

3/07/2003

DELL

3/12/2003

DELL

X00-E

X00-F

B

B

A

A

Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Power_P.I.R History
Size

Document Number

R ev
X00-G

LA-1711
Date:

Sheet

Tuesday, March 18, 2003
1

54

of

54

www.s-manuals.com



---

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