Compal LA 1711 Schematics. Www.s Manuals.com. Rx00 G Schematics

User Manual: Motherboard Compal LA-1711 - Schematics. Free.

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Page Count: 55

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D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

154Tuesday, March 18, 2003

Compal Electronics, Inc.

Cover Sheet

Prescott & Springdale Schematic with Capture CIS

and Function field

uFCPGA Prescott

2003-03-14

REV: X00-G

@ : Depop Component

1@ : Depop on Nimitz(Inspiron)

2@ : Depop on Beijing(Precision)

Prescott : Prescott processor Electrial,Mechanical and

Thermal Specification Rev0.5 [Check by HW:Henry,Steve]

Cature library ball out check document

Springdale(GMCH): Springdale GMCH External Design

Specification (EDS) REV1.0 [Check by HW: Henry,Rita]

ICH5: N/A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

254Tuesday, March 18, 2003

Compal Electronics, Inc.

Block Diagram

MINI PCI

PCI BUS

Prescott

page 23

GMCH

page 32

Slot 0

ATA100

page 7,8,9

Transformer

AMP& Phone

Jack

page 35

LPC BUS

BATT

IN

Page

33,34

page 26

page 18

page 27

Fan Control

USB

FDD

BACK

478 uFCPGA CPU

IDSEL:AD20

(PIRQA/B#,GNT#2,REQ#2)

USB

Macallen

AGP CONN.

page 42

3.3V 24.576MHz

VCORE

page 6

page31

page 21

Touch Pad

LPC to X-BUS

& Super I/O

page 14

USB2.0

1.5V/+VTT_GMCH

page

10,11,12,13

HA#(3..31)

Springdale

page 47

BT

SST39VF080

page 44

AGP4X/8X(1.5V)

page 41

3.3V ATA100

Clock Generator

HD#(0..63)

RJ45

Compal confidential

page 27

AC97

Codec

page 19

DC IN

CK409

3.3V 33MHz

page31

VCORE_CTRL

USBPORT 0

page 30

page 48

Memory

BUS(DDR)

MDC

page 25

BACK

Int.KBD

USBPORT 1

HUB Link

CDROM

ADT7460 Thermal sensor

CHARGER

page 24

page 28

ICH5

3.3V 33MHz

page 46

STAC9750

USBPORT 2

PCI7510

LAN

BCM5705M

DOG

USBPORT 3

1394, Smart

card

[CRT CONN. & TV-OUT]

System Bus

page 35

USBPORT 4

page 29

MOD

460 BGA

page 35

3.3V/5V

X BUS

CardBus Controller

Block Diagram

533/667MHz

ATA100

2.5V

266/333MHz

HDD

VGA

Board

1.5V

66Mhz

266MB/S

page 43

932 FC-BGA

page 29

AC-LINK

1.25V/2.5V

page 45

page 16

BANK 0, 1, 2,3

Channel B SO-DIMM

BANK 0, 1, 2,3

page 15

Channel A SO-DIMM

2.5V

266/333MHz

Page

20,21,22

USBPORT 6 BACK

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

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2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

354Tuesday, March 18, 2003

Compal Electronics, Inc.

Index and Config.

PM TABLE

ON

ON

AD17

OFF

PCI DEVICE

TABLE

CARD BUS

IDSEL

S0

TABLE

3

1

PCI

ON

ON

MINI PCI

S3

USB

ON

OFF

ON

+3VSUS

OFF

+5VSUS

AD19

+5VALW

S1

S5 S4/AC don't exist

+VCC_CORE

AD16

REQ#/GNT#

+5VRUN

ON

power

plane +3VRUN

4

S5 S4/AC

ON

ON

+3VALW

State

OFFOFF

LAN

+2.5V_MEM

OFF

Note : "@" means all model depop

"2@" means Beijing depoped only

"1@" means Nimitz depoped only

Configuration List

Function

BOM Structure

VGA

PIRQ

D,C

C

D,B(NP)

A,B(NP)

2

BT

3DOG

BACK

1

4

BACK

MOD

USB PORT#

0

DESTINATION

5

6

7

BACK

Reserved

Reserved

+1.5VRUN

V_1P25V_DDR_VTT

+12V

+VCCVID

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Nimitz Beijing

Model

Smart Card

LAN

Dog House

YES

10/100

(4401) 1000

(5705M)

YES YES

Function

YES

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

454Tuesday, March 18, 2003

Compal Electronics, Inc.

Power Rail

+5VHDD

+5VALW

+5VSUS

BATTERY

RBAT

+RTCSRC

+5VMOD

PWR_SRC

+12V

+RTC_PWR

+3VALW+3.3VRTC

DOCK _PWR_SRC

ADAPTER

+5VRUN

+5VSUS

+3VSUS

SUSPWROK

VDDA

+VCC_CORE

+VCCP

+2.5V_MEM

+2.5VMEMP

V_1P25V_DDR_VTTV3P3LAN

+3VSRC

+3VRUN +3VSUS+1.5VRUN

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

554Tuesday, March 18, 2003

Compal Electronics, Inc.

SMBUS TOPOLOGY

VGA

+3VRUN

CK_SDATA

DIMM1

CLK GEN.

SBAT_SMBCLK

Macallen

7002

ICH5

7002

SBAT_SMBDAT

DAT_SMB

7002

+3VALW

7002

DH PORT

CLK_SMB

7002

ADT7460

+5VALW

V_3P3_LAN

NIC

ICH_SMBDATA

+3VSUS

ICH_SMBCLK

MPCI

DIMM0

24C05

7002

CK_SCLK

LAN_SMBDATA

LAN_SMBCLK

SIO

PBAT_SMBCLK

PBAT_SMBDAT

+5VALW

1'nd

BATTERY

CHARGER

7002

7002

EC SMBus Address

DDR Temp.(AD7414ART-0) : 90h/91h (P.15)

CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)

CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)

EC EEPROM(FM24C05U) : A0h/A1h/A2h/A3h (P.37)

VID Select(PCA9561PW) : 9Ch/9Dh (P.38)

AD7414 PCA9561

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CK_BCLK

CLK_STP_CPU# CK_HCLK

ICH_SLP_S1#

CK_HCLK#

CK_ITP

CK_ITP#

CK_BCLK#

CLK66M_OUT1

PCICLK6

CK_CPU1

PCICLK5

PCICLK1

CK_CPU2#

PCICLK_F2

CK_CPU1#

CLK66M_OUT3

CLK66M_OUT0

CK_CPU2

CK_CPU0#

PCICLK2

CK_CPU0H_STP_PCI#

CK_SCLK

CK_SDATA

CK_VTT_PG#

CLKSEL0

CLKSEL1

ICH_SMBDATA

CK_SCLKICH_SMBCLK

CK_SDATA

CLKSEL0

CLKSEL1

CLK_VDD_PLL

CLK48M_OUT1

CLK48M_OUT0

CLKREF0

CLKREF1

CK_SATA

CK_SATA#

H_STP_PCI#

ICH_SLP_S1#

CK_XTAL_OUT

CK_XTAL_IN

PCICLK0

CK_VDD_MAIN+3VRUN

+3VRUN

+3VRUN

+3VRUN

+3VRUN

+3VRUN

+3VRUN

ICH_SLP_S1#<21>

CK_48M_SCR<30>

CK_48M_ICH<20>

CK_66M_MCH <12>

CK_66M_AGP <18>

CLK_STP_CPU#<36>

CK_VTT_PG#<37>

CK_33M_CBPCI <30>

CK_33M_LANPCI <28>

CK_33M_MINIPCI <32>

CK_33M_SIOPCI <34>

CK_33M_ICHPCI <20>

CK_66M_ICH <20>

CK_14M_ICH<21>

CK_ITP <8>

CK_ITP# <8>

ICH_SMBCLK<15,16,21,32>

ICH_SMBDATA<15,16,21,32>

CPU_CLKSEL0 <8>

CPU_CLKSEL1 <8>

MCH_CLKSEL0 <10>

MCH_CLKSEL1 <10>

CK_14M_SIO<34>

CK_100M_ICH<21>

CK_100M_ICH#<21>

CK_HCLK <10>

CK_HCLK# <10>

CK_BCLK# <7>

CK_BCLK <7>

CK_33M_CPLD <36>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

654Tuesday, March 18, 2003

Compal Electronics, Inc.

Clock Generator

Place near each pin

W>40 mil

Place near CK409

SL0 SL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot

Trace wide=20 mils

CK409

Place crystal within

500 mils of CK409

1

3

G

D

S2

2N7002

0 0 100 66 14.3 14.3 100/200

0 MID REF REF REF REF REF

0 1 200

48

REF

66 14.3 100/200 48

1 0 133 66 14.3

1 1 166

1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

66 14.3 100/200

48

48

Check SPEC (250mA,300 ohm)

14.3

14.3

14.3

Place near CK409

CK_XTAL_IN and CK_XTAL_OUT equal length traces,

Please place R_J between Pins 4,5 of CK409 Pins

before X'tal

R_J

Close to X'tal pin

Bring Up: Populate R509 (Because CPU

is Northwood-MT, Frequency 533MHz)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

100/200

R489

33_0402_5%~D

1 2

R536

100K_0402_5%~D

12

R519

2K_0603_1%~D

12

C551

0.1U_0402_10V6K~D

1

2

C586

0.1U_0402_10V6K~D

1

2

X6

14.31818MHz_20P_1BX14318CC1A~D

12

R543

33_0402_5%~D

1 2

R542

33_0402_5%~D

1 2

R208

2.49K_0603_1%~D

12

R530

2K_0603_1%~D

12

R587 33_0402_5%~D

1 2

R491

33_0402_5%~D

1 2

R488

33_0402_5%~D

1 2

R500

33_0402_5%~D

12

L45

BLM11A601S_0603~D

1 2

R478

49.9_0402_1%~D

1 2

R218

1K_0603_1%~D@

12

R485

33_0402_5%~D

1 2

R524

100K_0402_5%~D

12

R199

475_0603_1%~D

1 2

C204

10U_1206_6.3V7K~D

1

2

C552

0.1U_0402_10V6K~D

1

2

R541

33_0402_5%~D

1 2

C553

0.1U_0402_10V6K~D

1

2

R540

33_0402_5%~D

1 2

C193

4.7U_0805_6.3V6K~D

1

2

G

D

S

Q68

2N7002_SOT23~D

2

1 3

C554

0.1U_0402_10V6K~D

1

2

R206 0_0402_5%~D

12

R476

49.9_0402_1%~D

1 2

C166

10U_1206_6.3V7K~D

1

2

G

D

S

Q69

2N7002_SOT23~D

2

1 3

R518

1K_0603_1%~D

12

R508 0_0402_5%~D

12

C587

0.1U_0402_10V6K~D

1

2

C588

0.1U_0402_10V6K~D

1

2

R545

33_0402_5%~D

1 2

C598

10P_0402_50V8J~D@

12

R509 0_0402_5%~D@

12

R538

33_0402_5%~D

12

R493

33_0402_5%~D

1 2

R547

33_0402_5%~D

1 2

R484

33_0402_5%~D

1 2

U39

CY28409ZCT_TSSOP56~D

REF_1

1

VDD_PCI 10

VDD_PCI 16

VDD_3V66 24

VDD_48 34

VSS_REF

6VDD_REF 3

REF_0

2

CPUCLKT2 47

CPU_CLKC2 46

CPUCLKT1 44

CPUCLKC1 43

CPUCLKT0 41

CPUCLKC0 40

48/66MHZ_OUT/3V66_4 29

66MHZ_OUT2/3V66_2 26

66MHZ_OUT1/3V66_1 23

66MHZ_OUT0/3V66_0 22

PCICLK_F2 9

PCICLK_F1 8

PCICLK_F0 7

PCICLK6 20

PCICLK5 19

PCICLK4 18

PCICLK3 15

PCICLK2 14

PCICLK1 13

PCICLK0 12

XTAL_IN

4

XTAL_OUT

5

VSS_PCI

11

VSS_PCI

17

PWRDWN#

21

VSS_3V66

25

66MHZ_OUT3/3V66_3 27

SCLK

28

SDATA

30

USB_48MHZ

31

DOT_48MHZ

32

VSS_48

33

VTT_PWRGD#

35

VDD_SRC 36

SRCLKN_100MHZ

37

SRCLKP_100MHZ

38

VSS_SRC

39

VDD_CPU 42

VSS_CPU 45

VDD_CPU 48

PCI_STP#

49

CPU_STP#

50

SEL0

51

IREF

52

VSS_IREF

53

VSS_PLL

54

SEL1

56

VDD_PLL

55

R501

33_0402_5%~D

12

C585

0.1U_0402_10V6K~D

1

2

R490

33_0402_5%~D

1 2

C550

0.1U_0402_16V4Z~D

1

2

R529

1K_0603_1%~D

12

R214

2.49K_0603_1%~D

12

R192

1K_0603_1%~D

12

C597

10P_0402_50V8J~D@

12

R215 0_0402_5%~D@

12

R473

49.9_0402_1%~D

1 2

L17

BLM21PG600SN1D_0805~D

1 2

R477

49.9_0402_1%~D

1 2

R474

49.9_0402_1%~D

1 2

R472

49.9_0402_1%~D

1 2

R544

33_0402_5%~D

1 2

R546

33_0402_5%~D

1 2

R475

49.9_0402_1%~D

1 2

R479

49.9_0402_1%~D

1 2

R548

2M_0603_5%~D @

12

R492

33_0402_5%~D

1 2

R539

33_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CK_BCLK#

H_A#3

H_A#4

H_A#5

H_A#6

H_A#7

H_A#8

H_A#9

H_A#10

H_A#11

H_A#12

H_A#13

H_A#14

H_A#15

H_A#16

H_A#17

H_A#18

H_A#19

H_A#20

H_A#21

H_A#22

H_A#23

H_A#24

H_A#25

H_A#26

H_A#27

H_A#28

H_A#31

H_A#29

H_A#30

H_D#0

H_D#1

H_D#2

H_D#3

H_D#4

H_D#5

H_D#6

H_D#7

H_D#8

H_D#9

H_D#10

H_D#11

H_D#12

H_D#13

H_D#14

H_D#15

H_D#16

H_D#17

H_D#18

H_D#19

H_D#20

H_D#21

H_D#22

H_D#23

H_D#24

H_D#25

H_D#26

H_D#27

H_D#28

H_D#29

H_D#30

H_D#31

H_D#32

H_D#33

H_D#34

H_D#35

H_D#36

H_D#37

H_D#38

H_D#39

H_D#40

H_D#41

H_D#42

H_D#43

H_D#44

H_D#45

H_D#46

H_D#47

H_D#48

H_D#49

H_D#50

H_D#51

H_D#52

H_D#53

H_D#54

H_D#55

H_D#56

H_D#57

H_D#58

H_D#59

H_D#60

H_D#61

H_D#62

H_D#63

H_IERR#

H_REQ#0

H_REQ#1

H_REQ#2

H_REQ#3

H_REQ#4

CK_BCLK

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

H_REQ#[0..4]<10>

CK_BCLK#<6>

H_D#[0..63] <10>H_A#[3..31]<10>

H_HIT#<10>

H_BPRI#<10>

H_BR0#<10>

H_ADS#<10>

H_HITM#<10>

CK_BCLK<6>

H_BNR#<10> H_LOCK#<10>

H_DEFER#<10>

VCORE_BOOTSELECT <46>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Prescott Processor in uFCPGA478

C

754Tuesday, March 18, 2003

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Pull-up56ohm

to +VCC_CORE

Pull-up 56ohm

to +VCC_CORE

Pull-up 62ohm

to +VCC_CORE

Prescott

B6 FERR# FERR#/PBE# Pull-up 62ohm

to +VCC_CORE

Pull-up 62ohm

to +VCC_CORE

Reference Intel document

Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood

Pin name

Prescott

Pin name

Comment Comment

AA20 ITPCLKOUT0 Pull-up56ohm

to +VCC_CORE

TESTHI6 Pull-up 62ohm

to +VCC_CORE

Pop

Pop

Pop

Pop

Pop

PopDepop

Pop

Pop

DepopPop

Northwood

Pop

Depop

Depop

AB22 ITPCLKOUT1 Pull-up 56ohm

to +VCC_CORE

TESTHI7 Pull-up 62ohm

to +VCC_CORE

AD2 NC VIDPWRGD Pull-up 2.43K ohm

to +VCCVID

float

AD3 NC float VID5 Pull-up1Kohm to

+3VRUN & connect

to PWRIC

AF3 NC float VCCVIDLB Connect to +VCCVID

Northwood

MT

Northwood MT

Pin name

AD20 VCCA VCCIOPLLConnect to CPU

Filter

FERR#

ITPCLKOUT0

ITPCLKOUT1

Connect to CPU

Filter

AF23 Connect to CPU

Filter

Connect to CPU

Filter

NC

NC

NC

VCCA

VCCIOPLL VCCA VCCIOPLL

VSSAE26 VSS Connect to GND OPTIMIZED/

COMPAT#

Comment

float

Pop

Pop

Pop

TESTHI12 TESTHI12AD25 DPSLP

Connect to CPU

Filter

Connect to CPU

Filter

Connect to GND Pop

float

float

float

Depop

Depop

Depop

Pull-up 62ohm

to +VCC_CORE Pop

Pull-up 200ohm

to +VCC_CORE

Connect to PLD

through 0ohm Pop Pop

A6 TESTHI11 GHIPull-up 200ohm

to +VCC_CORE

Pull-up 62ohm

to +VCC_CORE

Connect to PLD

CPUPREF through

0ohm PopPop Pop

TESTHI11

Note: AD2,AD3 pop(bring up)

Prescott

JCPUA

AMP_3-1565030-1_Prescott~D

A#3

K2

A#4

K4

A#5

L6

A#6

K1

A#7

L3

A#8

M6

A#9

L2

A#10

M3

A#11

M4

A#12

N1

A#13

M1

A#14

N2

A#15

N4

A#16

N5

A#17

T1

A#18

R2

A#19

P3

A#20

P4

A#21

R3

A#22

T2

A#23

U1

A#24

P6

A#25

U3

A#26

T4

A#27

V2

A#28

R6

A#29

W1

A#30

T5

A#31

U4

A#32

V3

A#33

W2

A#34

Y1

A#35

AB1

REQ#0

J1

REQ#1

K5

REQ#2

J4

REQ#3

J3

REQ#4

H3

ADS#

G1

AP#0

AC1

AP#1

V5

BINIT#

AA3

IERR#

AC3

BNR#

G2 BPRI#

D2 BR0#

H6

LOCK#

G4

DEFER#

E2 HITM#

E3 HIT#

F3

D#0 B21

D#1 B22

D#2 A23

D#3 A25

D#4 C21

D#5 D22

D#6 B24

D#7 C23

D#8 C24

D#9 B25

D#10 G22

D#11 H21

D#12 C26

D#13 D23

D#14 J21

D#15 D25

D#16 H22

D#17 E24

D#18 G23

D#19 F23

D#20 F24

D#21 E25

D#22 F26

D#23 D26

D#24 L21

D#25 G26

D#26 H24

D#27 M21

D#28 L22

D#29 J24

D#30 K23

D#31 H25

D#32 M23

D#33 N22

D#34 P21

D#35 M24

D#36 N23

D#37 M26

D#38 N26

D#39 N25

D#40 R21

D#41 P24

D#42 R25

D#43 R24

D#44 T26

D#45 T25

D#46 T22

D#47 T23

D#48 U26

D#49 U24

D#50 U23

D#51 V25

D#52 U21

D#53 V22

D#54 V24

D#55 W26

D#56 Y26

D#57 W25

D#58 Y23

D#59 Y24

D#60 Y21

D#61 AA25

D#62 AA22

D#63 AA24

VCC_0 A10

VCC_1 A12

VCC_2 A14

VCC_3 A16

VCC_4 A18

VCC_5 A20

VCC_6 A8

VCC_7 AA10

VCC_8 AA12

VCC_9 AA14

VCC_10 AA16

VCC_11 AA18

VCC_12 AA8

VCC_13 AB11

VCC_14 AB13

VCC_15 AB15

VCC_16 AB17

VCC_17 AB19

VCC_18 AB7

VCC_19 AB9

VCC_20 AC10

VCC_21 AC12

VCC_22 AC14

VCC_23 AC16

VCC_24 AC18

VCC_25 AC8

VCC_26 AD11

VCC_27 AD13

VCC_28 AD15

VCC_29 AD17

VCC_30 AD19

VCC_31 AD7

VCC_32 AD9

VCC_33 AE10

VCC_34 AE12

VCC_35 AE14

VCC_36 AE16

VCC_37 AE18

VCC_38 AE20

VCC_39 AE6

VCC_40 AE8

VCC_41 AF11

VCC_42 AF13

VCC_43 AF15

VCC_44 AF17

VCC_45 AF19

VCC_46 AF2

VCC_47 AF21

VCC_48 AF5

VCC_49 AF7

VCC_50 AF9

VCC_51 B11

VCC_52 B13

VCC_53 B15

VCC_54 B17

VCC_55 B19

VCC_56 B7

VCC_57 B9

VCC_58 C10

VCC_59 C12

VCC_61 C14

VCC_62 C16

VCC_63 C18

VCC_64 C20

VCC_65 C8

VCC_66 D11

VCC_67 D13

VCC_68 D15

VCC_69 D17

VCC_70 D19

VCC_71 D7

VCC_72 D9

VCC_74

E12 VCC_75

E14 VCC_76

E16 VCC_77

E18 VCC_78

E20 VCC_79

E8 VCC_80

F11

VSS_0

H1

VSS_1

H4

VSS_2

H23

VSS_3

H26

VSS_4

A11

VSS_5

A13

VSS_6

A15

VSS_7

A17

VSS_8

A19

VSS_9

A21

VSS_10

A24

VSS_11

A26

VSS_12

A3

VSS_13

A9

VSS_14

AA1

VSS_15

AA11

VSS_16

AA13

VSS_17

AA15

VSS_18

AA17

VSS_19

AA19

VSS_20

AA23

VSS_21

AA26

VSS_22

AA4

VSS_23

AA7

VSS_24

AA9

VSS_25

AB10

VSS_26

AB12

VSS_27

AB14

VSS_28

AB16

VSS_29

AB18

VSS_30

AB20

VSS_31

AB21

VSS_32

AB24

VSS_33

AB3

VSS_34

AB6

VSS_35

AB8

VSS_36

AC11

VSS_37

AC13

VSS_38

AC15

VSS_39

AC17

VSS_40

AC19

VSS_41

AC2

VSS_42

AC22

VSS_43

AC25

VSS_44

AC5

VSS_45

AC7

VSS_46

AC9

BOOTSELECT

AD1

VSS_47

AD10

VSS_48

AD12

VSS_49

AD14

VSS_50

AD16

VSS_51

AD18

VSS_52

AD21

VSS_53

AD23

VSS_54

AD4

VSS_55

AD8

BCLK0

AF22

BCLK1

AF23

VCC_81

F13

VCC_82

F15

VCC_83

F17

VCC_84

F19

VCC_85

F9

VCC_73 E10

R371 200_0402_5%

1 2

R339

62_0402_5%@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_RS#0

H_RS#1

H_RS#2

H_FERR#

H_RESET#

H_PWRGOOD

H_THERMDC

H_THERMDA

H_THERMTRIP#

ITP_TDI

ITP_BPM#1

ITP_TDO

ITP_DBRESET#

ITP_BPM#3

ITP_BPM#0

ITP_TCK

ITP_BPM#5

H_RESET#

ITP_BPM#4

ITP_TCK

ITP_BPM#2

ITP_TRST#

ITP_TMS

ITP_TDI

ITP_TCK

ITP_TDO

H_RESET#

ITP_BPM#0

ITP_BPM#3

ITP_BPM#4

ITP_DBRESET#

H_PROCHOT#

ITP_TCK

ITP_TDI

ITP_TMS

ITP_TRST#

ITP_TDO

H_TESTHI2_7

H_TESTHI8

H_TESTHI9

H_TESTHI10

H_FERR#

H_THERMTRIP#

H_RESET#

H_PROCHOT#

H_PWRGOOD

ITP_BPM#1

ITP_BPM#2

ITP_BPM#5

H_VSSA

H_VCCA

H_VID_PWRGD

ITP_TMS

VID3

VID4

VID5

CK_ITP

CK_ITP#

CK_ITP_CPU#

VID2

VID1

VID0

CK_ITP#

CK_ITP

ITP_TRST#

H_VID_PWRGD

H_DPSLP#

H_TESTHI11

H_DPSLP#

H_TESTHI0

H_TESTHI1

CK_ITP_JITP#

CK_ITP_JITP

CK_ITP_JITP

CK_ITP_JITP#

CK_ITP_CPU

CK_ITP_CPU#

CK_ITP_CPU

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+CPU_GTLREF

+CPU_GTLREF

+CPU_GMCH_GTLREF

+VCC_CORE

+VCCVID

+VCC_CORE

+VCC_CORE

+3VRUN

+VCCVID

+VCC_CORE

+VCCVID

+VCC_CORE

+3VSUS

+3VSUS

+3VSUS

+3VSUS

+VCC_CORE

H_DSTBN#3 <10>

H _D INV# 3 <10>

H_DSTBP#1 <10>

H _D INV# 0 <10>

H _D INV# 2 <10>

H _D INV# 1 <10>

H_RS#[0..2]<10>

H_A20M#<21> H_FERR#<21> H_IGNNE#<21> H_SMI#<21>

H_STPCLK#<36>

H_DBSY#<10>

H_RESET#<10>

H_DRDY#<10>

H_INIT#<21>

H_PWRGOOD<21>

H_THERMTRIP#<21,37>

H_THERMDC<19> H_THERMDA<19>

H_CPUSLP# <36>

H_DSTBN#0 <10>

H_DSTBN#1 <10>

H_DSTBN#2 <10>

H_DSTBP#2 <10>

H_DSTBP#0 <10>

H_DSTBP#3 <10>

H_ADSTB#0 <10>

H_ADSTB#1 <10>

H_TRDY#<10>

H_INTR<21> H_NMI<21>

CPU_CLKSEL0<6> CPU_CLKSEL1<6>

ITP_DBRESET# <37>

H_PROCHOT# <10>

VCCSENSE<46> VSSSENSE<46>

H_VID0<36> H_VID1<36> H_VID2<36> H_VID3<36> H_VID4<36> H_VID5<36> VID5<36,46>

VID4<36,46>

VID3<36,46> VID2<36,46> VID1<36,46> VID0<36,46>

CK_ITP#<6> CK_ITP<6>

VID_PWRGD<46>

VCORE_ENLL <46>

CP UPREF# <36>

DPSLP#<36>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Prescott Processor in uFCPGA478

C

854Tuesday, March 18, 2003

Compal Electronics, Inc.

Place near ICH

Place near CPU

Close to the CPU

3. Place decoupling cap 220PF near CPU.

GTL Reference Voltage

2. Place R_A and R_B near CPU.

Layout note :

R_A

R_B

+CPU_GMCH_GTLREF trace

wide 12mils(min),Space

15mils

1. +CPU_GTLREF Trace wide

12mils(min),Space 15mils

1.Place cap within 600 mils of

the VCCA and VSSA pins.

10uH, DC current of 100mA parts

and close to cap

PLL Layout note :

2.H_VCCIOPLL,HVCCA,HVSSA trace wide

12 mils(min)

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Close to the ITP

Close to the ITP

R_D

Pop: Prescott

Depop: Northwood

R_E

RE

Pop: Prescott

Depop: Northwood

R_G

Pop: Northwood

Depop: Prescott

Between the CPU and ITP

Level shift

R_H

RH

Pop: Prescott

Depop: Northwood MT

H_TESTHI12

CPLD Enable

Pop R380

CPLD Enable

Pop R76, R78

RN8

0_4P2R_0404_5%~D @

14 23

R358

54.9_0603_1%~D

1 2

R381

680_0603_5%~D

1 2

R356

169_0603_1%

12

R37 1K_0402_5%~D

1 2

B_VID3

OPEN

@

1

122

C121

0.1U_0402_16V4Z~D

1 2

R349

61.9_0603_1%

12

R347 62_0402_5%

1 2

R380 0_0402_5%~D

1 2

R379 47_0402_5%~D @

12

R333 0_0402_5%~D@

1 2

R344 62_0402_5%

1 2

R364

47_0402_5%~D

1 2

R131 62_0402_5%

1 2

R97

61.9_0603_1%

12

R342 62_0402_5%

1 2

U6B

SN74LVC2G07DBVR_SOT23-6~D

O4

I

3

P5

G

2

R346 62_0402_5%

1 2

R70 0_0402_5%~D

1 2

R343 62_0402_5%

1 2

R357

200_0603_1%~D

12

R363

54.9_0603_1%~D

1 2

R361

150_0402_5%~D

1 2

Prescott

JCPUB

AMP_3-1565030-1_Prescott~D

RS#0

F1

RS#1

G5

RS#2

F4

RSP#

AB2

TRDY#

J6

A20M#

C6

FERR#

B6

IGNNE#

B2

SMI#

B5

PWRGOOD

AB23

STPCLK#

Y4

TESTHI12 AD25

LINT0

D1

LINT1

E5

INIT#

W5

RESET#

AB25

DRDY#

H2 DBSY#

H5

THERMDC

C4 THERMDA

B3

TDI

C1 TCK

D4

TDO

D5

TMS

F7

TRST#

E6

COMP1

P1 COMP0

L24

DP#0 J26

DP#1 K25

DP#2 K26

DP#3 L25

VSS_57 AE11

VSS_58 AE13

VSS_59 AE15

VSS_60 AE17

VSS_61 AE19

VSS_62 AE22

VSS_63 AE24

OPTIMIZED/COMPAT# AE26

VSS_65 AE7

VSS_66 AE9

VSS_67 AF1

VSS_68 AF10

VSS_69 AF12

VSS_70 AF14

VSS_71 AF16

VSS_72 AF18

VSS_73 AF20

SKTOCC# AF26

VSS_75 AF6

VSS_76 AF8

VSS_77 B10

VSS_78 B12

VSS_79 B14

VSS_80 B16

VSS_81 B18

VSS_82 B20

VSS_83 B23

VSS_84 B26

VSS_85 B4

VSS_86 B8

VSS_87 C11

VSS_88 C13

VSS_89 C15

VSS_90 C17

VSS_91 C19

VSS_92 C2

VSS_93 C22

VSS_94 C25

VSS_95 C5

VSS_96 C7

VSS_97 C9

VSS_98 D10

VSS_99 D12

VSS_100 D14

VSS_101 D16

VSS_102 D18

VSS_103 D20

VSS_104 D21

VSS_105 D24

VSS_106 D3

VSS_107 D6

VSS_108 D8

VSS_109 E1

VSS_110 E11

VSS_111 E13

VSS_112 E15

VSS_113 E17

VSS_114 E19

VSS_115 E23

VSS_116 E26

VSS_117 E4

VSS_118 E7

VSS_119 E9

VSS_120 F10

VSS_121 F12

VSS_122 F14

VSS_123 F16

VSS_124 F18

VSS_125 F2

VSS_126 F22

VSS_127 F25

VSS_128 F5

VID0

AE5

VID1

AE4

VID2

AE3

VID3

AE2

VID4

AE1

GTLREF0 AA21

GTLREF1 AA6

GTLREF2 F20

GTLREF3 F6

NC1 A22

NC2 A7

TESTHI0 AD24

TESTHI1 AA2

TESTHI2 AC21

TESTHI3 AC20

TESTHI4 AC24

TESTHI5 AC23

TESTHI6 AA20

TESTHI7 AB22

TESTHI8 U6

TESTHI9 W4

TESTHI10 Y3

TESTHI11 A6

VSS_129

F8

VSS_130

G21

VSS_131

G24

VSS_132

G3

VSS_133

G6

VSS_134

J2

VSS_135

J22

VSS_136

J25

VSS_137

J5

VSS_138

K21

VSS_139

K24

VSS_140

K3

VSS_141

K6

VSS_142

L1

VSS_143

L23

VSS_144

L26

VSS_145

L4

VSS_146

M2

VSS_147

M22

VSS_148

M25

VSS_149

M5

VSS_150

N21

VSS_151

N24

VSS_152

N3

VSS_153

N6

VSS_154

P2

VSS_155

P22

VSS_156

P25

VSS_157

P5

VSS_158

R1

VSS_159

R23

VSS_160

R26

VSS_161

R4

VSS_162

T21

VSS_163

T24

VSS_164

T3

VSS_165

T6

VSS_166

U2

VSS_167

U22

VSS_168

U25

VSS_169

U5

VSS_170

V1

VSS_171

V23

VSS_172

V26

VSS_173

V4

VSS_174

W21

VSS_175

W24

VSS_176

W3

VSS_177

W6

VSS_178

Y2

VSS_179

Y22

VSS_180

Y25

VSS_181

Y5

BSEL0

AD6

BSEL1

AD5

BPM#0

AC6

BPM#1

AB5

BPM#2

AC4

BPM#3

Y6

BPM#4

AA5

BPM#5

AB4

DSTBN#0 E22

DSTBN#1 K22

DSTBN#2 R22

DSTBN#3 W22

DSTBP#0 F21

DSTBP#1 J23

DSTBP#2 P23

DSTBP#3 W23

ITP_CLK0

AC26

ITP_CLK1

AD26

ADSTB#0 L5

ADSTB#1 R5

DBI#0 E21

DBI#1 G25

DBI#2 P26

DBI#3 V21

DBR# AE25

VCCIOPLL

AD20

VCCSENSE

A5

VCCA

AE23

VCCVID

AF4

THERMTRIP#

A2

PROCHOT# C3

MCERR# V6

SLP# AB26

VSSA

AD22

VSSSENSE

A4

VIDPWRGD

AD2

VID5

AD3

NC5 AE21

NC4 AF24

NC3 AF25

VCCVIDLB

AF3

B_VID2

OPEN

@

1

122

JITP

MOLEX_52435-2891_28P~D@

TDI

1TMS

2TRST#

3NC1

4TCK

5NC2

6TDO

7BCLKN

8BCLKP

9GND0

10 FBO

11 RESET#

12 BPM5#

13

BPM4#

15

BPM3#

17

BPM2#

19

BPM1#

21

BPM0#

23 DBA#

24 DBR#

25 VTAP

26 VTT0

27 VTT1

28

GND1

14

GND2

16

GND3

18

GND4

20

GND5

22

GND6 29

GND7

30

R152

10K_0402_5%~D

1 2

C131

0.1U_0402_16V4Z~D

1 2

C386

0.1U_0603_25V7M~D

1

2

R341 62_0402_5%

1 2

R78 0_0402_5%~D

1 2

R87 300_0402_5%~D

1 2

C369

0.1U_0402_16V4Z~D

1

2

R129 62_0402_5%

1 2

R79 62_0402_5%

@

1 2

B_VID5

OPEN

@

1

122

L40 10U_LQH31MN100K01_100mA_10%_1206~D

1 2

R111 130_0402_5%

1 2

U6A

SN74LVC2G07DBVR_SOT23-6~D

O6

I

1

P5

G

2

R84 62_0402_5%@

1 2

+

C368

33U_D2_8M_R35~D

1

2

R354 62_0402_5%

1 2

R83 62_0402_5%

1 2

R155 10K_0402_5%~D

1 2

B_VID0

OPEN

@

1

122

C372

220P_0402_50V8J~D

1

2

R377

47_0402_5%~D@

12

R77 62_0402_5%

1 2

RN9

0_4P2R_0404_5%~D

14 23

R370 27.4_0603_1%~D

1 2

R35 1K_0402_5%~D

1 2

R350 62_0402_5%

1 2

R108 150_0402_5%~D

1 2

B_VID4

OPEN

@

1

122

R76

200_0402_5%

12

B_VID1

OPEN

@

1

122

R340

0_0603_5%~D

12

R338 62_0402_5%

1 2

R382 62_0402_5%

1 2

R336

2.43K_0603_1%

1 2

R337 62_0402_5%

1 2

R82 62_0402_5%

1 2

L41 10U_LQH31MN100K01_100mA_10%_1206~D

1 2

R376

39.2_0603_1%~D

1 2

R71

0_0402_5%~D

1 2

RN7 1K_8P4R_1206_5%~D

18 27 36 45

T1

PAD@

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

CPU Decoupling

C

954Tuesday, March 18, 2003

Place 11 North of Socket(Stuff 6)

Place 12 Inside Socket(Stuff all)

Place 9 South of Socket(Unstuff all)

Compal Electronics, Inc.

Decoupling Reference Requirement:

560uF Polymer, ESR:5m ohm(each) * 10

22uF X5R * 32

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11

(12474)page239

22uF depop reference

Springdale Chipset Platform Design Guide Rev1.11(12474)

470uF _ERS10m ohm* 15, ESR=0.5m ohm

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C403

22U_1210_10V6K~D

1

2

+

C295

470U_D4_2.5V_R10M~D

1

2

+

C298

470U_D4_2.5V_R10M~D

1

2

C411

22U_1210_10V6K~D

1

2

C32

22U_1210_10V6K~D

1

2

+

C299

470U_D4_2.5V_R10M~D

1

2

C72

22U_1210_10V6K~D

@

1

2

C46

22U_1210_10V6K~D

1

2

C29

22U_1210_10V6K~D

1

2

C77

22U_1210_10V6K~D

@

1

2

C76

22U_1210_10V6K~D

@

1

2

+

C302

470U_D4_2.5V_R10M~D

1

2

+

C297

470U_D4_2.5V_R10M~D

1

2

C404

22U_1210_10V6K~D

1

2

C35

22U_1210_10V6K~D

@

1

2

C69

22U_1210_10V6K~D

@

1

2

C71

22U_1210_10V6K~D

@

1

2

+

C422

470U_D4_2.5V_R10M~D

1

2

C382

22U_1210_10V6K~D

1

2

+

C68

470U_D4_2.5V_R10M~D

1

2

C56

22U_1210_10V6K~D

1

2

+

C294

470U_D4_2.5V_R10M~D

1

2

+

C303

470U_D4_2.5V_R10M~D

1

2

C74

22U_1210_10V6K~D

@

1

2

C55

22U_1210_10V6K~D

1

2

C381

22U_1210_10V6K~D

1

2

C394

22U_1210_10V6K~D

1

2

+

C305

470U_D4_2.5V_R10M~D

1

2

+

C423

470U_D4_2.5V_R10M~D

1

2

+

C300

470U_D4_2.5V_R10M~D

1

2

C412

22U_1210_10V6K~D

1

2

C70

22U_1210_10V6K~D

@

1

2

C39

22U_1210_10V6K~D

@

1

2

C37

22U_1210_10V6K~D

@

1

2

+

C301

470U_D4_2.5V_R10M~D

1

2

C331

22U_1210_10V6K~D

@

1

2

C75

22U_1210_10V6K~D

@

1

2

C31

22U_1210_10V6K~D

1

2

C395

22U_1210_10V6K~D

1

2

+

C304

470U_D4_2.5V_R10M~D

1

2

+

C296

470U_D4_2.5V_R10M~D

1

2

C27

22U_1210_10V6K~D

1

2

C36

22U_1210_10V6K~D

@

1

2

C73

22U_1210_10V6K~D

@

1

2

C45

22U_1210_10V6K~D

1

2

C30

22U_1210_10V6K~D

1

2

C28

22U_1210_10V6K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_REQ#4

H_REQ#0

H_REQ#2

H_REQ#1

H_REQ#3

H_D#11

H_D#23

H_D#46

H_D#21

H_D#2

H_D#50

H_D#31

H_D#37

H_D#58

H_D#35

H_D#39

H_D#27

H_D#5

H_D#52

H_D#30

H_D#8

H_D#10

H_D#51

H_D#44

H_D#60

H_D#18

H_D#4

H_D#43

H_D#56

H_D#59

H_D#14

H_D#63

H_D#28

H_D#48

H_D#3

H_D#62

H_D#34

H_D#36

H_D#24

H_D#13

H_D#55

H_D#57

H_D#22

H_D#20

H_D#16

H_D#29

H_D#9

H_D#1

H_D#0

H_D#53

H_D#17

H_D#26

H_D#45

H_D#33

H_D#40

H_D#7

H_D#47

H_D#41

H_D#25

H_D#38

H_D#15

H_D#54

H_D#61

H_D#49

H_D#42

H_D#6

H_D#32

H_D#12

H_D#19

H_A#26

H_A#19

H_A#11

H_A#25

H_A#22

H_A#18

H_A#7

H_A#20

H_A#14

H_A#21

H_A#27

H_A#23

H_A#12

H_A#30

H_A#29

H_A#16

H_A#4

H_A#6

H_A#10

H_A#9

H_A#28

H_A#5

H_A#31

H_A#15

H_A#24

H_A#3

H_A#17

H_A#8

H_A#13

H_RS#2

H_RS#0

H_RS#1 H_PROCHOT#

HD_SWING

HD_SWING

HDRCOMP

HDRCOMP

H_PROCHOT#

+GMCH_GTLREF

+VTT_GMCH

+GMCH_GTLREF

+CPU_GMCH_GTLREF

+VTT_GMCH

+3VRUN

+VCC_CORE

H_REQ#[0..4]<7>

H_HITM#<7>

H_BNR#<7>

H_DRDY#<8>

H_DBSY#<8>

H_ADS#<7>

H_DINV#1<8>

H_DINV#2<8>

H_D#[0..63] <7>

CK_HCLK<6>

H_A#[3..31]<7>

H_ADSTB#0<8> H_ADSTB#1<8>

CK_HCLK#<6>

H_DSTBN#0<8> H_DSTBP#0<8>

H_DINV#0<8> H_DSTBP#1<8> H_DSTBN#1<8>

H_DSTBP#2<8> H_DSTBN#2<8>

H_DINV#3<8>

H_DSTBP#3<8> H_DSTBN#3<8>

H_DEFER#<7>

H_TRDY#<8>

H_HIT#<7> H_LOCK#<7>

H_BR0#<7>

H_BPRI#<7>

H_RESET#<8>

H_RS#[0..2]<8> MCH_CLKSEL0 <6>

MCH_CLKSEL1 <6>

H_PROCHOT# <8>

PWRGD_3V<21,37>

H_PROCHOT_SIO# <34>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Springdale-Host/GND

C

10 54Tuesday, March 18, 2003

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

2. Place decoupling cap 220PF near GMCH.

Layout note :

GTL Reference Voltage

1. +GMCH_GTLREF Trace wide

12mils(min),Space 15mils.

Trace width 12mils,Space

10mils

Follow Intel design guide R1.11(12474) page80

Trace width 10mils,Space

7mils

FSB

U3A

RG828SDGES_FCBGA932_SPRINGDALE~D

HA3#

D26

HA4#

D30

HA5#

L23

HA6#

E29

HA7#

B32

HA8#

K23

HA9#

C30

HA10#

C31

HA11#

J25

HA12#

B31

HA13#

E30

HA14#

B33

HA15#

J24

HA16#

F25

HA17#

D34

HA18#

C32

HA19#

F28

HA20#

C34

HA21#

J27

HA22#

G27

HA23#

F29

HA24#

E28

HA25#

H27

HA26#

K24

HA27#

E32

HA28#

F31

HA29#

G30

HA30#

J26

HA31#

G26

HREQ0#

B29

HREQ1#

J23

HREQ2#

L22

HREQ3#

C29

HREQ4#

J21

HADSTB0#

B30

HADSTB1#

D28

HCLKP

B7

HCLKN

C7

HDSTBP0#

B19

HDSTBN0#

C19

DINV0#

C17

HDSTBP1#

L19

HDSTBN1#

K19

DINV1#

L17

HDSTBP2#

G9

HDSTBN2#

F9

DINV2#

L14

HDSTBP3#

D12

HDSTBN3#

E12

DINV3#

C15

ADS#

F27

HTRDY#

D24

DRDY#

G24

DEFER#

L21

HITM#

E23

HIT#

K21

HLOCK#

E25

BREQ0#

B24

BNR#

B28

BPRI#

B26

DBSY#

E27

RS0#

G22

RS1#

C27

RS2#

B27

CPURST#

E8

PWROK#

AE14

HDRCOMP

E24

HDSWING

C25

HDVREF

F23

HD0# B23

HD1# E22

HD2# B21

HD3# D20

HD4# B22

HD5# D22

HD6# B20

HD7# C21

HD8# E18

HD9# E20

HD10# B16

HD11# D16

HD12# B18

HD13# B17

HD14# E16

HD15# D18

HD16# G20

HD17# F17

HD18# E19

HD19# F19

HD20# J17

HD21# L18

HD22# G16

HD23# G18

HD24# F21

HD25# F15

HD26# E15

HD27# E21

HD28# J19

HD29# G14

HD30# E17

HD31# K17

HD32# J15

HD33# L16

HD34# J13

HD35# F13

HD36# F11

HD37# E13

HD38# K15

HD39# G12

HD40# G10

HD41# L15

HD42# E11

HD43# K13

HD44# J11

HD45# H10

HD46# G8

HD47# E9

HD48# B13

HD49# E14

HD50# B14

HD51# B12

HD52# B15

HD53# D14

HD54# C13

HD55# B11

HD56# D10

HD57# C11

HD58# E10

HD59# B10

HD60# C9

HD61# B9

HD62# D8

HD63# B8

PROCHOT# L20

BSEL0 L13

BSEL1 L12

R332

102_0402_1%~D

12

R331

301_0402_1%~D

12

R323

200_0603_1%~D

12

C365

0.01U_0402_16V7K~D

1

2

GND

U3G

RG828SDGES_FCBGA932_SPRINGDALE~D

VSS

L31

VSS

L26

VSS

L25

VSS

L24

VSS

K33

VSS

K29

VSS

K27

VSS

K25

VSS

K22

VSS

K20

VSS

K18

VSS

K16

VSS

K14

VSS

K12

VSS

K11

VSS

J35

VSS

J32

VSS

J28

VSS

J22

VSS

J20

VSS

J18

VSS

J16

VSS

J14

VSS

J12

VSS

J10

VSS

H33

VSS

H30

VSS

H26

VSS

H24

VSS

H22

VSS

H20

VSS

H18

VSS

H16

VSS

H14

VSS

H12

VSS

H9

VSS

H8

VSS

H5

VSS

H2

VSS

G35

VSS

G31

VSS

G28

VSS

F26

VSS

F24

VSS

F22

VSS

F20

VSS

F18

VSS F16

VSS F14

VSS F12

VSS F10

VSS F8

VSS F5

VSS F3

VSS F1

VSS E3

VSS E1

VSS D35

VSS D33

VSS D31

VSS D29

VSS D27

VSS D25

VSS D23

VSS D21

VSS D19

VSS D17

VSS D15

VSS D13

VSS D11

VSS D9

VSS D1

VSS C28

VSS C26

VSS C24

VSS C22

VSS C20

VSS C18

VSS C16

VSS C14

VSS C12

VSS C10

VSS C8

VSS C4

VSS A32

VSS A29

VSS A27

VSS A25

VSS A23

VSS A20

VSS A16

VSS A13

VSS A11

VSS A9

VSS A7

Q24

MMBT3904_SOT23~D

2

3 1

GND

U3F

RG828SDGES_FCBGA932_SPRINGDALE~D

VSS

AR32

VSS

AR29

VSS

AR27

VSS

AR25

VSS

AR23

VSS

AR20

VSS

AR16

VSS

AR13

VSS

AR11

VSS

AR9

VSS

AN32

VSS

AN30

VSS

AN28

VSS

AN26

VSS

AN24

VSS

AN22

VSS

AN20

VSS

AN18

VSS

AN16

VSS

AN14

VSS

AN12

VSS

AN10

VSS

AM35

VSS

AM29

VSS

AM27

VSS

AM25

VSS

AM23

VSS

AM21

VSS

AM19

VSS

AM17

VSS

AM15

VSS

AM13

VSS

AM11

VSS

AM9

VSS

AL32

VSS

AL1

VSS

AK28

VSS

AK26

VSS

AK24

VSS

AK22

VSS

AK20

VSS

AK18

VSS

AK16

VSS

AK14

VSS

AK12

VSS

AK10

VSS

AK8

VSS

AK3

VSS

AJ35

VSS

AJ32

VSS

AJ9

VSS

AJ4

VSS

AJ1

VSS

AH33

VSS

AH30

VSS

AH24

VSS

AH22

VSS

AH20

VSS

AH18

VSS

AH16

VSS

AH14

VSS

AH12

VSS

AH10

VSS

AH6

VSS

AH3

VSS

AG35

VSS

AG32

VSS

AG28

VSS

AG26

VSS

AG24

VSS

AG22

VSS

AG20

VSS

AG18

VSS

AG16

VSS

AG14

VSS

AG8

VSS

AG4

VSS

AF33

VSS

AF30

VSS

AF25

VSS

AF24

VSS

AF22

VSS

AF20

VSS

AF18

VSS

AF16

VSS

AF14

VSS

AF11

VSS

AF9

VSS

AF6

VSS

AF3

VSS

AE35

VSS

AE32

VSS

AE26

VSS

AE25

VSS

AE13

VSS

AE12

VSS AE11

VSS AE10

VSS AE4

VSS AE1

VSS AD33

VSS AD30

VSS AD28

VSS AD10

VSS AD9

VSS AD8

VSS AD6

VSS AD3

VSS AC35

VSS AC32

VSS AC4

VSS AC1

VSS AB33

VSS AB30

VSS AB28

VSS AB27

VSS AB26

VSS AB10

VSS AB9

VSS AB8

VSS AB6

VSS AB3

VSS AA32

VSS AA4

VSS AA1

VSS Y35

VSS Y33

VSS Y30

VSS Y28

VSS Y27

VSS Y26

VSS Y10

VSS Y9

VSS Y8

VSS Y6

VSS Y3

VSS W32

VSS W18

VSS W17

VSS W4

VSS V33

VSS V30

VSS V28

VSS V27

VSS V26

VSS V19

VSS V17

VSS V10

VSS V9

VSS V8

VSS V6

VSS V3

VSS U32

VSS U19

VSS U18

VSS U4

VSS T35

VSS T33

VSS T30

VSS T28

VSS T27

VSS T26

VSS T10

VSS T9

VSS T8

VSS T6

VSS T3

VSS T1

VSS R32

VSS R4

VSS R1

VSS P33

VSS P30

VSS P28

VSS P27

VSS P26

VSS P9

VSS P8

VSS P6

VSS P3

VSS N35

VSS N32

VSS N4

VSS N1

VSS M33

VSS M30

VSS M28

VSS M27

VSS M26

VSS M6

VSS M3

VSS L35

R91 56_0402_5%~D

1 2

R329

0_0603_5%~D

12

R90

330_0402_5%

12

C366

220P_0402_50V8J~D

1

2

R335

20_0603_1%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDRA_SDQ2

DDRA_SDQ33

DDRA_SDQ56

DDRA_SDQ26

DDRA_SDQ0

DDRA_SDQ21

DDRA_SDQ22

DDRA_SDQ12

DDRA_SDQ3

DDRA_SDQ14

DDRA_SMA3

DDRA_SDQ29

DDRA_SMA7

DDRA_SDQ62

DDRA_SDQ18

DDRA_SDQ38

DDRA_SDQ17

DDRA_SDQ34

DDRA_SDQ40

DDRA_SDQ23

DDRA_SDQ27

DDRA_SDQ41

DDRA_SDQ46

DDRA_SDQ1

DDRA_CKE1

DDRA_SMA2

DDRA_SDQ60

DDRA_SDQ59

DDRA_SDQ58

DDRA_SDQ61

DDRA_SDQ4

DDRA_SDQ57

DDRA_SDQ43

DDRA_CKE0

DDRA_SDQ52

DDRA_SDQ39

DDRA_SDQ7

DDRA_SMA0

DDRA_SMA1

DDRA_SDQ47

DDRA_SDQ6

DDRA_SDQ31

DDRA_SDQ15

DDRA_SDQ45

DDRA_SDQ20

DDRA_SMA10

DDRA_SMA6

DDRA_SMA[0..12]

DDRA_SDQ37

DDRA_SDQ10

DDRA_SDQ5

DDRA_SDQ50

DDRA_SDQ16

DDRA_SDQ9

DDRA_SDQ13

DDRA_SCS#1

DDRA_SDQ8

DDRA_SDQ30

DDRA_SDQ51

DDRA_SDQ24

DDRA_SMA5

DDRA_SDQ35

DDRA_SMA12

DDRA_SMA9

DDRA_SDQ25

DDRA_SDQ54

DDRA_SDQ42

DDRA_SDQ28

DDRA_SDQ63

DDRA_SDQ48

DDRA_SDQ49

DDRA_SDQ55

DDRA_SDQ[0..63]

DDRA_SDQ36

DDRA_SDQ32

DDRA_SDQ53

DDRA_SDQ19

DDRA_SCS#0

DDRA_SDQ44

DDRA_SDQ11

DDRA_SMA4

DDRA_SMA8

DDRA_SMA11

DDRB_SDQ52

DDRB_SDQ48

DDRB_SDQ45

DDRB_SDQ25

DDRB_SDQ1

DDRB_SMA1

DDRB_SDQ43

DDRB_SDQ28

DDRB_SDQ16

DDRB_SDQ15

DDRB_SDQ7

DDRB_SDQ31

DDRB_SDQ26

DDRB_SDQ13

DDRB_SDQ12

DDRB_SDQ10

DDRB_SMA4

DDRB_SDQ60

DDRB_SDQ50

DDRB_SDQ46

DDRB_SDQ39

DDRB_SMA6

DDRB_SDQ[0..63]

DDRB_SDQ18

DDRB_SDQ6

DDRB_SDQ4

DDRB_SMA12

DDRB_SCS#0

DDRB_SDQ55

DDRB_SDQ49

DDRB_SDQ38

DDRB_SDQ27

DDRB_SMA10

DDRB_SMA11

DDRB_SDQ51

DDRB_SDQ44

DDRB_SDQ35

DDRB_SDQ30

DDRB_SDQ22

DDRB_SDQ17

DDRB_SDQ0

DDRB_SMA7

DDRB_SMA5

DDRB_SDQ62

DDRB_SDQ14

DDRB_SDQ3

DDRB_SDQ2

DDRB_SMA2

DDRB_SMA9

DDRB_SCS#1

DDRB_SDQ58

DDRB_SDQ24

DDRB_SDQ54

DDRB_SDQ47

DDRB_SDQ19

DDRB_SMA0

DDRB_SDQ42

DDRB_SDQ40

DDRB_SMA[0..12]

DDRB_SDQ36

DDRB_SDQ29

DDRB_SMA3

DDRB_SDQ63

DDRB_SDQ34

DDRB_SDQ21

DDRB_SMA8

DDRB_SDQ61

DDRB_SDQ59

DDRB_SDQ56

DDRB_SDQ33

DDRB_SDQ20

DDRB_SDQ53

DDRB_SDQ41

DDRB_SDQ32

DDRB_SDQ23

DDRB_SDQ9

DDRB_SDQ8

DDRB_SDQ57

DDRB_SDQ37

DDRB_SDQ11

DDRB_SDQ5

DDRB_CKE0

DDRB_CKE1

SMYRCOMPVOH

SMYRCOMPVOH

SMYRCOMPVOL

SMYRCOMPVOL

SMXRCOMPVOH

SMXRCOMP

SMXRCOMPVOH

SMXRCOMPVOL

SMXRCOMPVOL

SMYRCOMP

SMXRCOMP

SMYRCOMP

+2.5V_MEM +2.5V_MEM

+2.5V_MEM SM_VREF_B

SM_VREF_A

+2.5V_MEM

+2.5V_MEM +2.5V_MEM

+2.5V_MEM

DDRA_SMA[0..12]<15,17>

DDRA_SDQ[0..63] <15,17>

DDRA_SWE#<15,17> DDRA_SCAS#<15,17> DDRA_SRAS#<15,17>

DDRA_SBS0<15,17> DDRA_SBS1<15,17>

DDRA_CLK0<15> DDRA_CLK0#<15> DDRA_CLK1<15> DDRA_CLK1#<15> DDRA_CLK2<15> DDRA_CLK2#<15>

DDRB_SMA[0..12]<16,17>

DDRB_SBS1<16,17>

DDRB_SWE#<16,17>

DDRB_SBS0<16,17>

DDRB_SRAS#<16,17> DDRB_SCAS#<16,17>

DDRB_CLK1<16> DDRB_CLK1#<16>

DDRB_CLK2#<16>

DDRB_CLK0<16>

DDRB_CLK2<16>

DDRB_CLK0#<16>

DDRB_SDQ[0..63] <16,17>

DDRA_SDQS0 <15,17>

DDRA_SDM0 <15,17>

DDRA_SDM1 <15,17>

DDRA_SDQS1 <15,17>

DDRA_SDM2 <15,17>

DDRA_SDQS2 <15,17>

DDRA_SDM3 <15,17>

DDRA_SDQS3 <15,17>

DDRA_SDM4 <15,17>

DDRA_SDQS4 <15,17>

DDRA_SDM5 <15,17>

DDRA_SDQS5 <15,17>

DDRA_SDM6 <15,17>

DDRA_SDQS6 <15,17>

DDRA_SDM7 <15,17>

DDRA_SDQS7 <15,17>

DDRB_SDM0 <16,17>

DDRB_SDQS0 <16,17>

DDRB_SDQS1 <16,17>

DDRB_SDM1 <16,17>

DDRB_SDQS2 <16,17>

DDRB_SDM2 <16,17>

DDRB_SDQS3 <16,17>

DDRB_SDM3 <16,17>

DDRB_SDQS4 <16,17>

DDRB_SDM4 <16,17>

DDRB_SDQS5 <16,17>

DDRB_SDM5 <16,17>

DDRB_SDQS6 <16,17>

DDRB_SDM6 <16,17>

DDRB_SDQS7 <16,17>

DDRB_SDM7 <16,17>

DDRA_SCS#0<15,17> DDRA_SCS#1<15,17> DDRB_SCS#0<16,17> DDRB_SCS#1<16,17>

DDRA_CKE0<15,17> DDRA_CKE1<15,17> DDRB_CKE0<16,17> DDRB_CKE1<16,17>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Springdale-DDR Interface

C

11 54Tuesday, March 18, 2003

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Trace width of 12mils

and space 10mils(min)

Trace width of 12mils and space

10mils(min) Trace width of 12mils and space

10mils(min)

Trace width of 12mils and space

10mils(min)

Trace width of 12mils and space

10mils(min)

Trace width of 12mils and space

10mils(min)

Close to GMCH <1" Close to GMCH <1"

Close to GMCH <1" Close to GMCH <1"

Close to GMCH

Close to GMCH

SM_VREF_A trace width of 12mils and space

12mils(min) SM_VREF_B trace width of

12mils and space

12mils(min)

*

*

*

*

Follow Intel design guide

R1.11(12474) page124,125 Note: Intel recommend is 31.12K,the value isn't popularize.

Follow Dell's DT team use 30.9K

C400

0.01U_0402_16V7K~D

1

2

C53

2.2U_0805_16VFZ~D

1

2

C59

2.2U_0805_16VFZ~D

1

2

R106

30.9K_0603_1%~D

12

R373

30.9K_0603_1%~D

12

C57

1U_0603_10V6K~D

1

2

R368

10K_0603_1%~D

12

C401

0.01U_0402_16V7K~D

1

2

C62

2.2U_0805_16VFZ~D

1

2

R369

30.9K_0603_1%~D

12

R110

42.2_0603_1%~D

12

C52

2.2U_0805_16VFZ~D

1

2

C406

1U_0603_10V6K~D

1

2

R100

150_0603_1%~D

12

R374

10K_0603_1%~D

12

DDR Channel B

U3C

RG828SDGES_FCBGA932_SPRINGDALE~D

SMAA_B0

AG31

SMAA_B1

AJ31

SMAA_B2

AD27

SMAA_B3

AE24

SMAA_B4

AK27

SMAA_B5

AG25

SMAA_B6

AL25

SMAA_B7

AF21

SMAA_B8

AL23

SMAA_B9

AJ22

SMAA_B10

AF29

SMAA_B11

AL21

SMAA_B12

AJ20

SMAB_B1

AE27

SMAB_B2

AD26

SMAB_B3

AL29

SMAB_B4

AL27

SMAB_B5

AE23

SWE_B#

W27

SCAS_B#

W31

SRAS_B#

W26

SBA_B0

Y25

SBA_B1

AA25

SCS_B0#

U26

SCS_B1#

T29

SCS_B2#

V25

SCS_B3#

W25

SCKE_B0

AK19

SCKE_B1

AF19

SCKE_B2

AG19

SCKE_B3

AE18

SCMDCLK_B0

AG29

SCMDCLK_B0#

AG30

SCMDCLK_B1

AF17

SCMDCLK_B1#

AG17

SCMDCLK_B2

N27

SCMDCLK_B2#

N26

SCMDCLK_B3

AJ30

SCMDCLK_B3#

AH29

SCMDCLK_B4

AK15

SCMDCLK_B4#

AL15

SCMDCLK_B5

N31

SCMDCLK_B5#

N30

SMVREF_B

AP9

SMYRCOMP

AA33

SMYRCOMPVOH

R34

SMYRCOMPVOL

R33

SDQS_B0 AF15

SDM_B0 AG11

SDQ_B0 AJ10

SDQ_B1 AE15

SDQ_B2 AL11

SDQ_B3 AE16

SDQ_B4 AL8

SDQ_B5 AF12

SDQ_B6 AK11

SDQ_B7 AG12

SDQS_B1 AG13

SDM_B1 AG15

SDQ_B8 AE17

SDQ_B9 AL13

SDQ_B10 AK17

SDQ_B11 AL17

SDQ_B12 AK13

SDQ_B13 AJ14

SDQ_B14 AJ16

SDQ_B15 AJ18

SDQS_B2 AG21

SDM_B2 AE21

SDQ_B16 AE19

SDQ_B17 AE20

SDQ_B18 AG23

SDQ_B19 AK23

SDQ_B20 AL19

SDQ_B21 AK21

SDQ_B22 AJ24

SDQ_B23 AE22

SDQS_B3 AH27

SDM_B3 AJ28

SDQ_B24 AK25

SDQ_B25 AH26

SDQ_B26 AG27

SDQ_B27 AF27

SDQ_B28 AJ26

SDQ_B29 AJ27

SDQ_B30 AD25

SDQ_B31 AF28

SDQS_B4 AD29

SDM_B4 AC31

SDQ_B32 AE30

SDQ_B33 AC27

SDQ_B34 AC30

SDQ_B35 Y29

SDQ_B36 AE31

SDQ_B37 AB29

SDQ_B38 AA26

SDQ_B39 AA27

SDQS_B5 U30

SDM_B5 U31

SDQ_B40 AA30

SDQ_B41 W30

SDQ_B42 U27

SDQ_B43 T25

SDQ_B44 AA31

SDQ_B45 V29

SDQ_B46 U25

SDQ_B47 R27

SDQS_B6 L27

SDM_B6 M29

SDQ_B48 P29

SDQ_B49 R30

SDQ_B50 K28

SDQ_B51 L30

SDQ_B52 R31

SDQ_B53 R26

SDQ_B54 P25

SDQ_B55 L32

SDQS_B7 J30

SDM_B7 J31

SDQ_B56 K30

SDQ_B57 H29

SDQ_B58 F32

SDQ_B59 G33

SDQ_B60 N25

SDQ_B61 M25

SDQ_B62 J29

SDQ_B63 G32

C66

2.2U_0805_16VFZ~D

1

2

C636

0.01U_0402_16V7K~D

1

2

C61

1U_0603_10V6K~D

1

2

C407

1U_0603_10V6K~D

1

2

R101

30.9K_0603_1%~D

12

R109

42.2_0603_1%~D

12

R367

42.2_0603_1%~D

12

DDR Channel A

U3B

RG828SDGES_FCBGA932_SPRINGDALE~D

SMAA_A0

AJ34

SMAA_A1

AL33

SMAA_A2

AK29

SMAA_A3

AN31

SMAA_A4

AL30

SMAA_A5

AL26

SMAA_A6

AL28

SMAA_A7

AN25

SMAA_A8

AP26

SMAA_A9

AP24

SMAA_A10

AJ33

SMAA_A11

AN23

SMAA_A12

AN21

SMAB_A1

AL34

SMAB_A2

AM34

SMAB_A3

AP32

SMAB_A4

AP31

SMAB_A5

AM26

SWE_A#

AB34

SCAS_A#

Y34

SRAS_A#

AC33

SBA_A0

AE33

SBA_A1

AH34

SCS_A0#

AA34

SCS_A1#

Y31

SCS_A2#

Y32

SCS_A3#

W34

SCKE_A0

AL20

SCKE_A1

AN19

SCKE_A2

AM20

SCKE_A3

AP20

SCMDCLK_A0

AK32

SCMDCLK_A0#

AK31

SCMDCLK_A1

AP17

SCMDCLK_A1#

AN17

SCMDCLK_A2

N33

SCMDCLK_A2#

N34

SCMDCLK_A3

AK33

SCMDCLK_A3#

AK34

SCMDCLK_A4

AM16

SCMDCLK_A4#

AL16

SCMDCLK_A5

P31

SCMDCLK_A5#

P32

SMVREF_A

E34

SMXRCOMP

AK9

SMXRCOMPVOH

AN9

SMXRCOMPVOL

AL9

SDQS_A0 AN11

SDM_A0 AP12

SDQ_A0 AP10

SDQ_A1 AP11

SDQ_A2 AM12

SDQ_A3 AN13

SDQ_A4 AM10

SDQ_A5 AL10

SDQ_A6 AL12

SDQ_A7 AP13

SDQS_A1 AP15

SDM_A1 AP16

SDQ_A8 AP14

SDQ_A9 AM14

SDQ_A10 AL18

SDQ_A11 AP19

SDQ_A12 AL14

SDQ_A13 AN15

SDQ_A14 AP18

SDQ_A15 AM18

SDQS_A2 AP23

SDM_A2 AM24

SDQ_A16 AP22

SDQ_A17 AM22

SDQ_A18 AL24

SDQ_A19 AN27

SDQ_A20 AP21

SDQ_A21 AL22

SDQ_A22 AP25

SDQ_A23 AP27

SDQS_A3 AM30

SDM_A3 AP30

SDQ_A24 AP28

SDQ_A25 AP29

SDQ_A26 AP33

SDQ_A27 AM33

SDQ_A28 AM28

SDQ_A29 AN29

SDQ_A30 AM31

SDQ_A31 AN34

SDQS_A4 AF34

SDM_A4 AF31

SDQ_A32 AH32

SDQ_A33 AG34

SDQ_A34 AF32

SDQ_A35 AD32

SDQ_A36 AH31

SDQ_A37 AG33

SDQ_A38 AE34

SDQ_A39 AD34

SDQS_A5 V34

SDM_A5 W33

SDQ_A40 AC34

SDQ_A41 AB31

SDQ_A42 V32

SDQ_A43 V31

SDQ_A44 AD31

SDQ_A45 AB32

SDQ_A46 U34

SDQ_A47 U33

SDQS_A6 M32

SDM_A6 M34

SDQ_A48 T34

SDQ_A49 T32

SDQ_A50 K34

SDQ_A51 K32

SDQ_A52 T31

SDQ_A53 P34

SDQ_A54 L34

SDQ_A55 L33

SDQS_A7 H31

SDM_A7 H32

SDQ_A56 J33

SDQ_A57 H34

SDQ_A58 E33

SDQ_A59 F33

SDQ_A60 K31

SDQ_A61 J34

SDQ_A62 G34

SDQ_A63 F34

C637

0.01U_0402_16V7K~D

1

2

C50

0.1U_0402_16V4Z~D

1

2

R105

10K_0603_1%~D

12

C63

2.2U_0805_16VFZ~D

1

2

C48

2.2U_0805_16VFZ~D

1

2

C47

0.1U_0402_16V4Z~D

1

2

R104

150_0603_1%~D

12

R372

42.2_0603_1%~D

12

C64

2.2U_0805_16VFZ~D

1

2

C54

0.01U_0402_16V7K~D

1

2

R102

10K_0603_1%~D

12

C58

0.01U_0402_16V7K~D

1

2

C65

2.2U_0805_16VFZ~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

G_AD4

G_SBA#2

G_SBA#7

G_C/BE#3

G_PAR

CK_66M_MCH G_AD3

G_AD13

G_AD22

G_SBA#1

G_ST1

HUB_HL10

G_SBA#0

G_SBA#3

G_SBA#6

G_AD0

G_AD1

G_AD28

G_AD30

HUB_HL5

HUB_HL9

G_AD27

G_ST2

HUB_HL1

G_AD8

G_AD17

G_AD11

G_AD12

G_AD16

G_AD24

G_C/BE#1

G_AD5

G_AD6

HUB_HL6

G_AD15

G_AD29

G_C/BE#2

HUB_HL3

HUB_HL8

G_AD2

G_AD7

G_AD20

G_AD26

G_ST0

HUB_HL4

G_AD18

G_AD23

G_SBA#5

G_AD14

HUB_HL0

HUB_HL2

CK_66M_MCH

G_AD25

G_C/BE#0

G_AD19

G_AD31

G_SBA#4

HUB_HL7

G_AD9

G_AD10

G_AD21

GRCOMP

GRCOMP

GC_DET_REF

AGP_SWING

VREFGC

AGP_SWING

HI_RCOMP_MCH

HI_RCOMP_MCH

HI_SWING_MCH

HI_VREF_MCH

HI_SWING_MCH

HI_VREF_MCH

CI_SWING_GMCH

CI_VREF_GMCH

CI_SWING_GMCH

CI_VREF_GMCH

VREFCG

G_PAR

+1.5VRUN

+1.5VRUN +12V +1.5VRUN

+1.5VRUN

+1.5VRUN

+1.5VRUN

+1.5VRUN

+1.5VRUN

G_SB_STBF <18>

HUB_HL[0..10]<20>

G_GNT#<18>

G_DEVSEL#<18>

G_WBF#<18> G_RBF#<18>

HUB_HLSTRS<20>

G_AD[0..31] <18>

G_SB_STBS# <18>

G_C/BE#[0..3]<18>

G_PIPE#_DBI_HI<18> G_DBI_LO<18>

CK_66M_MCH<6>

HUB_HLSTRF<20>

G_AD_STBS0# <18>

G_AD_STBF1 <18>

G_FRAME#<18>

G_ST[0..2]<18>

G_IRDY#<18>

G_REQ#<18>

G_AD_STBF0 <18>

G_AD[0..31] <18>

G_AD_STBS1# <18>

G_SBA#[0..7] <18>

G_PAR<18>

G_TRDY#<18> G_STOP#<18>

AGP8X_DET_GC<18>

PCI_PCIRST#<20,36>

VRE FCG <18> VREFGC <18>

ICH_SYNC#<21>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Springdale-AGP/HUB/VGA/CSA

C

12 54Tuesday, March 18, 2003

Close to GMCH ball <250mils

Close to GMCH ball <250mils

Note:

CI_SWING_MCH, CI_VREF_MCH

trace width of 12mils and

space 20mils

Note:

Springdale Customer Schematic R1.2 page18

AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design

guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.

Close GMCH ball less than 250mils

Follow Springdale Chipset Platform Design guide Rev1.11(12474)

Close to VGA Conn.

Close GMCH ball

less than

250mils

0.8V

0.35V

Analog RGB/CRT guidelines for Springdale-P

1: External AGP

0: Internal Graphics

Trace 10mils, space 7mils

Note:

HI_SWING_MCH, trace width of

12mils and space 10mils

Note:

HI_VREF_MCH trace width of

10mils and space 7mils

Note:

AGP_SWING_MCH, trace width of

12mils and space 10mils

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R41 0_0402_5%~D

12

R43 0_0402_5%~D

12

R39 0_0402_5%~D

12

C355

0.1U_0402_16V4Z~D

1

2

C38

0.1U_0402_16V4Z~D

1

2

Q10

MMBT3904_SOT23~D

2

3 1

R64

43.2_0603_1%~D

12

VGA

AGP

HUB CSA

U3D

RG828SDGES_FCBGA932_SPRINGDALE~D

GCBE0

Y7

GCBE1

W5

GCBE2

AA3

GCBE3

U2

GFRAME

U6

GCLKIN

H4

GDEVSEL

AB4

GIRDY

V11

GTRDY

AB5

GSTOP

W11

GPAR/ADD_DETECT

AB2

GREQ

N6

GGNT

M7

GRCOMP/DVOBCGCOMP

AC2

GVSWING

AC3

GVREF

AD2

GRBF

R10

GWBF

R9

DBI_HI

M4

DBI_LO

M5

GST0

N3

GST1

N5

GST2

N2

HI0

AF5

HI1

AG3

HI2

AK2

HI3

AG5

HI4

AK5

HI5

AL3

HI6

AL2

HI7

AL4

HI8

AJ2

HI9

AH2

HI10

AJ3

HISTRF

AH5

HISTRS

AH4

HI_RCOMP

AD4

HI_SWING

AE3

HI_VREF

AE2

CI0

AK7

CI1

AH7

CI2

AD11

CI3

AF7

CI4

AD7

CI5

AC10

CI6

AF8

CI7

AG7

CI8

AE9

CI9

AH9

CI10

AG6

CISTRF

AJ6

CISTRS

AJ5

CI_RCOMP

AG2

CI_SWING

AF2

CI_VREF

AF4

DREFCLK

G4

EXTTS#

AP8

ICH_SYNC#

AJ8

RSTIN#

AK4

RESERVED_1

AG10

RESERVED_2

AG9

RESERVED_3

AN35

RESERVED_4

AP34

RESERVED_5

AR1

GADSTBF0 AC6

GADSTBS0# AC5

GAD0 AE6

GAD1 AC11

GAD2 AD5

GAD3 AE5

GAD4 AA10

GAD5 AC9

GAD6 AB11

GAD7 AB7

GAD8 AA9

GAD9 AA6

GAD10 AA5

GAD11 W10

GAD12 AA11

GAD13 W6

GAD14 W9

GAD15 V7

GADSTBF1 V4

GADSTBS1# V5

GAD16 AA2

GAD17 Y4

GAD18 Y2

GAD19 W2

GAD20 Y5

GAD21 V2

GAD22 W3

GAD23 U3

GAD24 T2

GAD25 T4

GAD26 T5

GAD27 R2

GAD28 P2

GAD29 P5

GAD30 P4

GAD31 M2

GSBSTBF U11

GSBSTBS# T11

GSBA0# R6

GSBA1# P7

GSBA2# R3

GSBA3# R5

GSBA4# U9

GSBA5# U10

GSBA6# U5

GSBA7# T7

DDCA_DATA H3

DDCA_CLK F2

RED F4

RED# E4

GREEN H6

GREEN# G5

BLUE H7

BLUE# G6

HSYNC G3

VSYNC E2

REFSET D2

NC_1 A3

NC_2 A33

NC_3 A35

NC_4 AF13

NC_5 AF23

NC_6 AJ12

NC_7 AN1

NC_8 AP2

NC_9 AR3

NC_10 AR33

NC_11 AR35

NC_12 B2

NC_13 B25

NC_14 B34

NC_15 C1

NC_16 C23

NC_17 C35

NC_18 E26

NC_19 M31

NC_20 R25

R57 100_0603_1%~D

1 2

R59

60.4_0603_1%

12

R328

52.3_0603_1%~D

12

C363

0.01U_0402_16V7K~D

1

2

C41

0.1U_0402_16V4Z~D

1

2

R61

10K_0402_5%~D@

1 2

C324

10P_0402_50V8J~D

@

1

2

C42

0.01U_0402_16V7K~D

1

2

R69

113_0603_1%

12

R320

22_0402_5%~D @

12

R330

226_0603_1%~D

12

C360

0.1U_0402_16V4Z~D

1

2

C385 0.1U_0402_16V4Z~D

12

R55

39.2_0603_1%~D

1 2

R334

113_0603_1%

12

C44

0.01U_0402_16V7K~D

1

2

C364

0.01U_0402_16V7K~D

1

2

R75

147_0603_1%

12

C361

0.01U_0402_16V7K~D

1

2

R48

8.2K_0402_5%~D

12

R42 0_0402_5%~D

12

C362

0.01U_0402_16V7K~D

1

2

R66 0_0402_5%~D

12

R38 0_0402_5%~D

12

R74

226_0603_1%~D

12

G

D

S

Q13

2N7002_SOT23~D

2

13

R44 0_0402_5%~D

12

R68

147_0603_1%

12

R58

39.2_0603_1%~D

12

R45

8.2K_0402_5%~D

12

R40 0_0402_5%~D

12

R81

52.3_0603_1%~D

1 2

C43

0.1U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VTT_DCAP1

VTT_DCAP2

VTT_DCAP3

VCC_AGP_DCAP1

VCC_AGP_DCAP2

VCC _DDR_DCAP5

VCC _DDR_DCAP4

VCC _DDR_DCAP1

VCC _DDR_DCAP2

VCCA_FSB1 VCCA_FSB

VCCA_FSB

VCC A_DDR

VCCA_DPLL

VCCA_DAC

VCCA1P5_DDR_SM

VCCA1P5_DDR_SM

+1.5VRUN

+2.5V_MEM

+VTT_GMCH

+1.5VRUN

+3VRUN

+1.5VRUN

+1.5VRUN

+1.5VRUN

+VTT_GMCH

+2.5V_MEM +1.5VRUN

+VTT_GMCH

+2.5V_MEM

+1.5VRUN

+2.5V_MEM

+2.5V_MEM

+1.5VRUN

+1.5VRUN

+1.5VRUN

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Springdale-Decoupling

C

13 54Tuesday, March 18, 2003

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Trace 14mils

Trace 14mils

Trace 14mils

Close to GMCH

0.82uH, DC current of 30mA

parts and close to cap

Close to GMCH

Trace 50mils, min:35mils on ball field

1uH(0.54uH-D-IN), DC current of

1000mA parts and close to cap

Place near ball

Y11,routing trace

from cap to ball

Place near GMCH Place near GMCH

Bulk Decopuling

Note:

Placed less than 100 mils from ball

Note:

Placed less than 100 mils from ball

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11

(12474)page246,248

Place at the output of the 1.5V VR

Place between the VR and GMCH

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page84

C410 0.22U_0603_10V7K~D

1 2

C390

0.1U_0402_10V6K~D@

1

2

C356

0.47U_0603_16V7K~D

1

2

C377

0.1U_0402_10V6K~D@

1

2

C367 0.1U_0402_10V6K~D

1 2

+

C308

470U_D4_2.5V_R10M~D

1

2

+

C276

100U_D_10VM~D

1

2

C322

10U_0805_10V4M~D

1

2

C419 0.22U_0603_10V7K~D

1 2

C391

0.1U_0402_10V6K~D@

1

2

C287

4.7U_0805_6.3V6K~D

1

2

C387

0.1U_0402_10V6K~D@

1

2

C353

0.1U_0402_10V6K~D@

1

2

C380

0.1U_0402_10V6K~D@

1

2

C347

0.1U_0402_10V6K~D@

1

2

C327

0.1U_0402_16V4Z~D

1

2

C345

0.1U_0402_10V6K~D@

1

2

C351

0.1U_0402_10V6K~D@

1

2

C319

0.1U_0402_10V6K~D@

1

2

C338

0.1U_0402_10V6K~D@

1

2

R314 0_0402_5%~D

12

R301

0_0603_5%~D

12

C421 0.1U_0402_10V6K~D

1 2

C405 0.1U_0402_10V6K~D

1 2

C49 0.47U_0603_16V7K~D

1 2

+

C329

470U_D4_2.5V_R10M~D

1

2

C414

0.1U_0402_10V6K~D

1

2

C290

0.47U_0603_16V7K~D

1

2

POWER

U3E

RG828SDGES_FCBGA932_SPRINGDALE~D

VTT

F7 VTT

E7 VTT

E6 VTT

D7 VTT

D6 VTT

D5 VTT

C6 VTT

C5 VTT

B6 VTT

B5

VCCA_FSB

A31

VTT

A21 VTT

A15

VCC_DDR

AA35

VCCA_DDR

AL35

VCC_DDR

AL6

VCC_DDR

AL7

VCC_DDR

AM1

VCC_DDR

AM2

VCC_DDR

AM3

VCC_DDR

AM5

VCC_DDR

AM6

VCC_DDR

AM7

VCC_DDR

AM8

VCC_DDR

AN2

VCC_DDR

AN4

VCC_DDR

AN5

VCC_DDR

AN6

VCC_DDR

AN7

VCC_DDR

AN8

VCC_DDR

AP3

VCC_DDR

AP4

VCC_DDR

AP5

VCC_DDR

AP6

VCC_DDR

AP7

VCC_DDR

AR15

VCC_DDR

AR21

VCC_DDR

AR31

VCC_DDR

AR4

VCC_DDR

AR5

VCC_DDR

AR7

VCC_DDR

E35

VCC_DDR

R35

VCC_DAC

G1

VCC_DAC

G2

VCCA_AGP

Y11

VCCA_FSB

B4

VCCA_DPLL

B3

VCCA_DAC

C2

VCCA_DDR

AB25

VCCA_DDR

AC25

VCCA_DDR

AC26

VCC J6

VCC J7

VCC J8

VCC J9

VCC K6

VCC K7

VCC K8

VCC K9

VCC L6

VCC L7

VCC L9

VCC L10

VCC L11

VCC M8

VCC M9

VCC M10

VCC M11

VCC N9

VCC N10

VCC N11

VCC P10

VCC P11

VCC R11

VCC T16

VCC T17

VCC T18

VCC T19

VCC T20

VCC U16

VCC U17

VCC U20

VCC V16

VCC V18

VCC V20

VCC W16

VCC W19

VCC W20

VCC Y16

VCC Y17

VCC Y18

VCC Y19

VCC Y20

VCCA_AGP

AG1

VCC_AGP J1

VCC_AGP J2

VCC_AGP J3

VCC_AGP J4

VCC_AGP J5

VCC_AGP K2

VCC_AGP K3

VCC_AGP K4

VCC_AGP K5

VCC_AGP L1

VCC_AGP L2

VCC_AGP L3

VCC_AGP L4

VCC_AGP L5

VCC_AGP Y1

VSSA_DAC D3

VTT

A4

VTT

A6 VTT

A5

C389

0.1U_0402_10V6K~D@

1

2

C370

4.7U_0805_6.3V6K~D

1

2

R315 0_0402_5%~D

12

C284

4.7U_0805_6.3V6K~D

1

2

C376

0.1U_0402_10V6K~D@

1

2

C375

0.1U_0402_10V6K~D@

1

2

C354

0.1U_0402_10V6K~D

1 2

L42

1U_LQH32CN1R0M11_1A_20%_1210~D

1 2

C288

4.7U_0805_6.3V6K~D

1

2

C371 0.1U_0402_10V6K~D

1 2

C346

0.1U_0402_10V6K~D@

1

2

C358

0.1U_0402_10V6K~D

1

2

C393

0.1U_0402_10V6K~D@

1

2

C402

0.1U_0402_16V4Z~D

1

2

C348

0.47U_0603_16V7K~D

1

2

C373

0.1U_0402_10V6K~D@

1

2

R351

0_0603_5%~D

12

C337

0.1U_0402_10V6K~D

1

2

C289

1U_0603_6.3V6M~D

1

2

C379

0.1U_0402_10V6K~D@

1

2

C280

0.1U_0402_16V4Z~D

1

2

C396

0.1U_0402_10V6K~D

1

2

C359

0.1U_0402_10V6K~D@

1

2

+

C398

100U_D_10VM~D

1

2

C384

22U_1206_10V4Z~D

1

2

L34

0.82U_LQM21NNR82K10_150mA_10%_0805~D

1 2

C378

0.1U_0402_10V6K~D@

1

2

C374

0.1U_0402_10V6K~D@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FAN1_VFB

FAN1TACH_ON

FAN1_TACH_FB

FAN2TACH_ON

FAN1_VOUT

FAN2_VOUT FAN2_TACH_FB

FAN2_ON

FAN2VREF

FAN1VREF FAN1_ON

FAN2_VFB

+5VRUN

+12V

+12V

+3VRUN

+5VRUN

+3VRUN+12V

+12V

FAN2_PWM<34> FAN2_TACH <34>

FAN1_TACH <34>

FAN1_PWM<34>

FAN1_VOUT <25>

FAN1_TACH_FB <25>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

14 54Tuesday, March 18, 2003

Compal Electronics, Inc.

FAN CONTROL

FAN2

FAN1 Control and Tachometer

FAN1

1

E3

2222 SYMBOL(SOT23-NEW)

2

C

B

FAN2 Control and Tachometer

SI3457DV P channel

Vds max: +/- 30V

Vgs max: +/- 20V

Id max: 4.3A @ Vgs = -10V

65mohm @ Vgs = -10V

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LINK CIS

19.2

R137

1K_0402_5%~D

1 2

R287

10K_0402_5%~D

12

R286

100K_0402_5%~D

1 2

R580

300K_0402_5%

1 2

U30A

LM358M_SO8~D

P8

IN+

3

IN-

2

G

4

O1

JFAN2

MOLEX_53398-0390

1

2

3

Q30

PMBT2222_SOT23~D

2

3 1

R289

10K_0402_5%~D

1 2

R290

1K_0402_5%~D

1 2

C255

1U_0805_10V6K~D

1

2

S

G

D

Q72

SI3457DV-T1_TSOP6~D

3

6

245

1

R151

300K_0402_5%

1 2

C254

1U_0805_10V6K~D

1

2

+

C622

100U_D_16VM

1

2

R291

100K_0402_5%~D

1 2

C102

0.47U_0805_16V7K~D

1

2

R136

10K_0402_5%~D

1 2

C256

0.47U_0805_16V7K~D

1

2

C625

2200P_0603_50V7K~D@1 2

C108

2200P_0603_50V7K~D @

1 2

Q61

PMBT2222_SOT23~D

2

3 1

D17

RB751V_SOD323~D

2 1

S

G

D

Q31

SI3457DV-T1_TSOP6~D

3

6

245

1

C117

0.1U_0402_16V4Z~D

1

2

D2

RB751V_SOD323~D

2 1

R150

100K_0402_5%~D

12

U30B

LM358M_SO8~D

P8

IN+

5

IN-

6

G

4

O7

+

C110

100U_D_16VM

1

2

R288

100K_0402_5%~D

12

R133

10K_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDRA_SDQS[0..7]

DDRA_SDM[0..7]

DDRA_SMA[0..12]

DDRA_SDQ[0..63]

DDRA_SDQ56

DDRA_SDQ26

DDRA_SDQ23

DDRA_SDQ36

DDRA_SDQ28

DDRA_SDQ15

DDRA_SDQS1

DDRA_SDQS0

DDRA_SDQ55

DDRA_SDQ60

DDRA_SDQ51

DDRA_SMA8

DDRA_SDQ12

DDRA_CKE1

DDRA_SDQ42

DDRA_SCAS#

DDRA_SMA0

DDRA_SDQ31

DDRA_SDM7

DDRA_SDQ61

DDRA_SMA11

DDRA_SDQ25

DDRA_SDQ35

DDRA_SDQ10

DDRA_SDQ53

DDRA_SDQ48

DDRA_SDQ43

DDRA_SMA10

DDRA_SDQ63

DDRA_SDQ50

DDRA_SDQS6

DDRA_SDQ39

DDRA_SDQ24

DDRA_SDM2

DDRA_SDQ3

DDRA_SDQ54

DDRA_SMA6

DDRA_SDQ11

DDRA_SDQ4

DDRA_SDQ1

DDRA_SDQS4

DDRA_SMA1

DDRA_SDQ8

DDRA_SDQ58

DDRA_SDQ46

DDRA_SDM5

DDRA_SDQ62

DDRA_SCS#0

DDRA_SDQ5

DDRA_SDQ52

DDRA_SDQ2

DDRA_SWE#

DDRA_SDQS2

DDRA_VREF

DDRA_SDQ49

DDRA_SDM4

DDRA_SMA4

DDRA_SDQ21

DDRA_SDQ30

DDRA_SDQ19

DDRA_SDQ37

DDRA_SRAS#

DDRA_SDQ16

DDRA_SMA5

DDRA_SDQ13

DDRA_SDQ57

DDRA_SDM6

DDRA_SDQ47

DDRA_SCS#1

DDRA_SDQ14

DDRA_SDM0

DDRA_SDQ32

DDRA_SDQ27

DDRA_SDQ40

DDRA_SMA2

DDRA_SDM3

DDRA_SMA9

DDRA_SMA12

DDRA_SDQ17

DDRA_SDQ6

DDRA_SDQS5

DDRA_SDQ34

DDRA_SDQ9

DDRA_SMA7

DDRA_SDQS7

DDRA_SDQ45

DDRA_SBS1

DDRA_SDQ33

DDRA_SMA3

DDRA_SDQ20

DDRA_SDQ7

DDRA_SDQ41

DDRA_SDQ38

DDRA_SDQ0

DDRA_SDQ59

DDRA_CKE0

DDRA_SDQ18

DDRA_SDM1

DDRA_SDQ44

DDRA_SBS0

DDRA_SDQS3

DDRA_SDQ29

DDRA_SDQ22

+2.5V_MEM

+3VSUS

+2.5V_MEM

+2.5V_MEM

+2.5V_MEM

+2.5V_MEM

DDRA_CLK2# <11>

DDRA_SCS#0<11,17>

ICH_SMBDATA<6,16,21,32>

DDRA_CKE1<11,17>

DDRA_CLK2 <11>

DDRA_CLK0#<11>

DDRA_SCS#1 <11,17>

DDRA_SMA[0..12]<11,17>

DDRA_SDQS[0..7]<11,17>

DDRA_SDM[0..7]<11,17>

DDRA_CKE0 <11,17>

DDRA_CLK0<11>

DDRA_CLK1<11> DDRA_CLK1#<11>

ICH_SMBCLK<6,16,21,32>

DDRA_SDQ[0..63]<11,17>

DDRA_SWE#<11,17> DDRA_SBS0<11,17> D DRA_SCAS# <11,17>

DDRA_SRAS# <11,17>

DDRA_SBS1 <11,17>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

15 54Tuesday, March 18, 2003

Compal Electronics, Inc.

DDR-SODIMM SLOT1

DIMM0

STANDARD

System Memory Decoupling caps

DDRA_VREF trace width of

12mils and space 12mils(min)

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11

(12474)pag 271 each DIMM(two) requirement 0.1uF*42

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page22

each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*21

Follow

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

JDIM1

AMP_1565917-1~D

VREF

1

VSS

3

DQ0

5

DQ1

7

VDD

9

DQS0

11

DQ2

13

VSS

15

DQ3

17

DQ8

19

VDD

21

DQ9

23

DQS1

25

VSS

27

DQ10

29

DQ11

31

VDD

33

CK0

35

CK0#

37

VSS

39

DQ16

41

DQ17

43

VDD

45

DQS2

47

DQ18

49

VSS

51

DQ19

53

DQ24

55

VDD

57

DQ25

59

DQS3

61

VSS

63

DQ26

65

DQ27

67

VDD

69

CB0

71

CB1

73

VSS

75

DQS8

77

CB2

79

VDD

81

CB3

83

DU

85

VSS

87

CK2

89

CK2#

91

VDD

93

CKE1

95

DU/A13

97

A12

99

A9

101

VSS

103

A7

105

A5

107

A3

109

A1

111

VDD

113

A10/AP

115

BA0

117

WE#

119

S0#

121

DU

123

VSS

125

DQ32

127

DQ33

129

VDD

131

DQS4

133

DQ34

135

VSS

137

DQ35

139

DQ40

141

VDD

143

VREF 2

VSS 4

DQ4 6

DQ5 8

VDD 10

DM0 12

DQ6 14

VSS 16

DQ7 18

DQ12 20

VDD 22

DQ13 24

DM1 26

VSS 28

DQ14 30

DQ15 32

VDD 34

VDD 36

VSS 38

VSS 40

DQ20 42

DQ21 44

VDD 46

DM2 48

DQ22 50

VSS 52

DQ23 54

DQ28 56

VDD 58

DQ29 60

DM3 62

VSS 64

DQ30 66

DQ31 68

VDD 70

CB4 72

CB5 74

VSS 76

DM8 78

CB6 80

VDD 82

CB7 84

DU/RESET# 86

VSS 88

VSS 90

VDD 92

VDD 94

CKE0 96

DU/BA2 98

A11 100

A8 102

VSS 104

A6 106

A4 108

A2 110

A0 112

VDD 114

BA1 116

RAS# 118

CAS# 120

S1# 122

DU 124

VSS 126

DQ36 128

DQ37 130

VDD 132

DM4 134

DQ38 136

VSS 138

DQ39 140

DQ44 142

VDD 144

DQ41

145

DQS5

147

VSS

149

DQ42

151

DQ43

153

VDD

155

VDD

157

VSS

159

VSS

161

DQ48

163

DQ49

165

VDD

167

DQS6

169

DQ50

171

VSS

173

DQ51

175

DQ56

177

VDD

179

DQ57

181

DQS7

183

VSS

185

DQ58

187

DQ59

189

VDD

191

SDA

193

SCL

195

VDD_SPD

197

VDD_ID

199

DQ45 146

DM5 148

VSS 150

DQ46 152

DQ47 154

VDD 156

CK1# 158

CK1 160

VSS 162

DQ52 164

DQ53 166

VDD 168

DM6 170

DQ54 172

VSS 174

DQ55 176

DQ60 178

VDD 180

DQ61 182

DM7 184

VSS 186

DQ62 188

DQ63 190

VDD 192

SA0 194

SA1 196

SA2 198

DU 200

C92

0.1U_0402_10V6K~D

1

2

C133

0.1U_0402_10V6K~D

1

2

C111

22U_1206_10V4Z~D

1

2

C132

0.1U_0402_10V6K~D

1

2

C112

0.1U_0402_10V6K~D

1

2

C126

0.1U_0402_10V6K~D

1

2

C109

0.1U_0402_10V6K~D

1

2

C79

0.1U_0402_10V6K~D

1

2

C106

0.1U_0402_10V6K~D

1

2

C129

0.1U_0402_10V6K~D

1

2

R442

75_0603_1%~D

12

C123

0.1U_0402_10V6K~D

1

2

C105

0.1U_0402_10V6K~D

1

2

C134

0.1U_0402_10V6K~D

1

2

C81

0.1U_0402_10V6K~D

1

2

C124

0.1U_0402_10V6K~D

1

2

C104

0.1U_0402_10V6K~D

1

2

C107

0.1U_0402_10V6K~D

1

2

C114

0.1U_0402_10V6K~D

1

2

C113

0.1U_0402_10V6K~D

1

2

R440

75_0603_1%~D

12

C507

0.1U_0402_16V4Z~D

1

2

C103

0.1U_0402_10V6K~D

1

2

C128

0.1U_0402_10V6K~D

1

2

C101

0.1U_0402_10V6K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDRB_SMA4

DDRB_SDQ10

DDRB_SDQ5

DDRB_SDM7

DDRB_SDQ47

DDRB_SMA3

DDRB_SDQ36

DDRB_SDQ54

DDRB_SDQ15

DDRB_SDQ[0..63]

DDRB_SCS#0

DDRB_SMA[0..12]

DDRB_SDM3

DDRB_SMA7

DDRB_SDQ21

DDRB_SDQ18

DDRB_SMA6

DDRB_SDQ30

DDRB_SDQ3

DDRB_SDQS4

DDRB_SDQ49

DDRB_SDQS6

DDRB_SMA2

DDRB_SDQ8

DDRB_SDQ2

DDRB_SMA8

DDRB_SDQ41

DDRB_SDM2

DDRB_SDQ62

DDRB_SDQ16

DDRB_SDQ24

DDRB_SDQ61

DDRB_SDQ35

DDRB_SDQS[0..7]

DDRB_SDQ57

DDRB_SDQ60

DDRB_SDQS5

DDRB_SDQ20

DDRB_SMA12

DDRB_SDQ19

DDRB_SDM[0..7]

DDRB_SDM0

DDRB_SDQ1

DDRB_SDQ44

DDRB_SRAS#

DDRB_SDQ43

DDRB_SDQ63

DDRB_SDQ55

DDRB_SDM5

DDRB_SDQ9

DDRB_SDM4

DDRB_SBS0

DDRB_SDQ59

DDRB_SDM6

DDRB_SDQ56

DDRB_SDQ12

DDRB_SDQ25

DDRB_SCAS#

DDRB_SDQ6

DDRB_SDQ31

DDRB_SDQ27

DDRB_SDQ26

DDRB_SDQ34

DDRB_SDQ58

DDRB_SDQ53

DDRB_SDQ13

DDRB_SMA11

DDRB_SDQ39

DDRB_SDQ50

DDRB_SDQ40

DDRB_SMA10

DDRB_SDQ23

DDRB_SDQ28

DDRB_SDQ22

DDRB_SDQ17

DDRB_SDQ45

DDRB_SDQ32

DDRB_SDQ51

DDRB_SDQ52

DDRB_SDM1

DDRB_SMA0

DDRB_SDQ37

DDRB_SDQ0

DDRB_SCS#1

DDRB_SDQ11

DDRB_SDQ29

DDRB_SBS1

DDRB_SDQS7

DDRB_SMA1

DDRB_CKE0

DDRB_SDQ46

DDRB_SDQ42

DDRB_SDQS3

DDRB_SDQ14

DDRB_SMA5

DDRB_SWE#

DDRB_SDQ48

DDRB_SMA9

DDRB_SDQ4

DDRB_SDQS0

DDRB_SDQ38

DDRB_SDQ7

DDRB_SDQS2

DDRB_SDQS1

DDRB_SDQ33

DDRB_CKE1

DDRB_VREF

+2.5V_MEM+2.5V_MEM

+3VSUS

+3VSUS

+2.5V_MEM

+2.5V_MEM

+2.5V_MEM

DDRB_SDM[0..7]<11,17>

DDRB_CLK1<11>

ICH_SMBCLK<6,15,21,32>

DDRB_SCS#0<11,17>

ICH_SMBDATA<6,15,21,32>

DDRB_SMA[0..12]<11,17>

DDRB_SCS#1 <11,17>

DDRB_CKE1<11,17>

DDRB_SDQ[0..63]<11,17>

DDRB_CLK1#<11>

DDRB_CKE0 <11,17>

DDRB_CLK2# <11>

DDRB_SDQS[0..7]<11,17>

DDRB_CLK2 <11>

DDRB_CLK0#<11> DDRB_CLK0<11>

DDRB_SWE#<11,17> DDRB_SBS0<11,17> D DRB_SCAS# <11,17>

DDRB_SRAS# <11,17>

DDRB_SBS1 <11,17>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

16 54Tuesday, March 18, 2003

Compal Electronics, Inc.

DDR-SODIMM SLOT2

REVERSE

DIMM1

System Memory Decoupling caps

DDRB_VREF trace width of

12mils and space 12mils(min)

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page26

each Channel(two DIMMs) requirement 0.1uF*24

Follow

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C130

0.1U_0402_10V6K~D

1

2

C91

0.1U_0402_10V6K~D

1

2

C78

0.1U_0402_10V6K~D

1

2

R415

75_0603_1%~D

12

C86

0.1U_0402_10V6K~D

1

2

C87

0.1U_0402_10V6K~D

1

2

C84

0.1U_0402_10V6K~D

1

2

C97

0.1U_0402_10V6K~D

1

2

C95

0.1U_0402_10V6K~D

1

2

C99

0.1U_0402_10V6K~D

1

2

C98

0.1U_0402_10V6K~D

1

2

C94

0.1U_0402_10V6K~D

1

2

C93

0.1U_0402_10V6K~D

1

2

C96

0.1U_0402_10V6K~D

1

2

C127

0.1U_0402_10V6K~D

1

2

C90

0.1U_0402_10V6K~D

1

2

C458

0.1U_0402_16V4Z~D

1

2

C85

0.1U_0402_10V6K~D

1

2

C125

0.1U_0402_10V6K~D

1

2

C80

0.1U_0402_10V6K~D

1

2

C115

0.1U_0402_10V6K~D

1

2

R418

75_0603_1%~D

12

C83

0.1U_0402_10V6K~D

1

2

C116

0.1U_0402_10V6K~D

1

2

C122

0.1U_0402_10V6K~D

1

2

JDIM2

AMP_1565918-1~D

VREF

1

VSS

3

DQ0

5

DQ1

7

VDD

9

DQS0

11

DQ2

13

VSS

15

DQ3

17

DQ8

19

VDD

21

DQ9

23

DQS1

25

VSS

27

DQ10

29

DQ11

31

VDD

33

CK0

35

CK0#

37

VSS

39

DQ16

41

DQ17

43

VDD

45

DQS2

47

DQ18

49

VSS

51

DQ19

53

DQ24

55

VDD

57

DQ25

59

DQS3

61

VSS

63

DQ26

65

DQ27

67

VDD

69

CB0

71

CB1

73

VSS

75

DQS8

77

CB2

79

VDD

81

CB3

83

DU

85

VSS

87

CK2

89

CK2#

91

VDD

93

CKE1

95

DU/A13

97

A12

99

A9

101

VSS

103

A7

105

A5

107

A3

109

A1

111

VDD

113

A10/AP

115

BA0

117

WE#

119

S0#

121

DU

123

VSS

125

DQ32

127

DQ33

129

VDD

131

DQS4

133

DQ34

135

VSS

137

DQ35

139

DQ40

141

VDD

143

VREF 2

VSS 4

DQ4 6

DQ5 8

VDD 10

DM0 12

DQ6 14

VSS 16

DQ7 18

DQ12 20

VDD 22

DQ13 24

DM1 26

VSS 28

DQ14 30

DQ15 32

VDD 34

VDD 36

VSS 38

VSS 40

DQ20 42

DQ21 44

VDD 46

DM2 48

DQ22 50

VSS 52

DQ23 54

DQ28 56

VDD 58

DQ29 60

DM3 62

VSS 64

DQ30 66

DQ31 68

VDD 70

CB4 72

CB5 74

VSS 76

DM8 78

CB6 80

VDD 82

CB7 84

DU/RESET# 86

VSS 88

VSS 90

VDD 92

VDD 94

CKE0 96

DU/BA2 98

A11 100

A8 102

VSS 104

A6 106

A4 108

A2 110

A0 112

VDD 114

BA1 116

RAS# 118

CAS# 120

S1# 122

DU 124

VSS 126

DQ36 128

DQ37 130

VDD 132

DM4 134

DQ38 136

VSS 138

DQ39 140

DQ44 142

VDD 144

DQ41

145

DQS5

147

VSS

149

DQ42

151

DQ43

153

VDD

155

VDD

157

VSS

159

VSS

161

DQ48

163

DQ49

165

VDD

167

DQS6

169

DQ50

171

VSS

173

DQ51

175

DQ56

177

VDD

179

DQ57

181

DQS7

183

VSS

185

DQ58

187

DQ59

189

VDD

191

SDA

193

SCL

195

VDD_SPD

197

VDD_ID

199

DQ45 146

DM5 148

VSS 150

DQ46 152

DQ47 154

VDD 156

CK1# 158

CK1 160

VSS 162

DQ52 164

DQ53 166

VDD 168

DM6 170

DQ54 172

VSS 174

DQ55 176

DQ60 178

VDD 180

DQ61 182

DM7 184

VSS 186

DQ62 188

DQ63 190

VDD 192

SA0 194

SA1 196

SA2 198

DU 200

C82

0.1U_0402_10V6K~D

1

2

C100

0.1U_0402_10V6K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDRB_SDQ34

DDRB_SDQ33

DDRA_SDQ56

DDRA_SBS1 DDRB_SDQ11

DDRA_SDM0

DDRA_SDQ50

DDRA_SDQ38

DDRA_SDM1

DDRA_SDQ29

DDRA_SDQ8

DDRA_SDQ59

DDRB_SDQ4

DDRB_SDQ13

DDRA_SDQ32

DDRB_SDQ31

DDRA_SDQS5

DDRA_SDQ30

DDRA_SDQ40

DDRA_SDQ47

DDRB_SDQ0

DDRB_SDQ40

DDRA_SDQ27

DDRB_SDQ18

DDRA_SDQ2

DDRA_SDQ13

DDRB_SDQ41

DDRB_SDQS6

DDRB_SDQ54

DDRB_SMA8

DDRB_CKE1

DDRB_SDQ17

DDRB_SDQ32DDRA_SRAS#

DDRB_SDQ27

DDRB_SMA0

DDRB_SMA10

DDRA_SMA8

DDRA_SDQ17

DDRB_SDQS4

DDRA_SMA9

DDRA_SDQ33

DDRB_SDQ2

DDRB_SDQ8

DDRA_SDM7

DDRB_SDQ45

DDRB_SDQ12

DDRB_SDM4

DDRA_SDQS1

DDRA_SDQ6

DDRA_SDQ54

DDRA_SDQ36

DDRB_SDQ3

DDRB_SDM5

DDRA_SDQ48

DDRB_SDQ21

DDRA_SDQ0

DDRB_SDQS0

DDRB_SDQ61

DDRA_SCAS#

DDRA_SDQ1

DDRB_SDQ58

DDRA_SDQ41

DDRA_SMA4

DDRB_SDQ26

DDRA_SDQ58 DDRB_SDM7

DDRA_SDQ14

DDRA_SDQ9

DDRB_SDQ49

DDRA_SDQ7

DDRA_SDQS7

DDRB_SDQ30

DDRA_SDQ39

DDRB_SDQ35

DDRA_SDM5

DDRA_SDQ12

DDRA_SMA3

DDRB_SDQ16

DDRB_SDQ6

DDRB_SDQ47

DDRA_SDM2

DDRB_SMA5

DDRB_SDQ53

DDRB_SDQ42

DDRA_SDQ57

DDRA_SDQ10

DDRB_SDQ28

DDRA_SDQ4

DDRB_SDQS5

DDRA_SMA6

DDRA_SDQS3

DDRB_SDQ37

DDRB_SDQ51

DDRB_SDQS1

DDRB_SDQS7

DDRB_SDQ48

DDRB_SDQ20

DDRB_SDM6

DDRB_SDQ63

DDRA_CKE0

DDRA_SDQS6

DDRB_SDQ44

DDRA_SCS#0

DDRA_SDQ28

DDRA_SDQ31

DDRB_SRAS#

DDRB_SDQ55

DDRB_SDQ46

DDRB_SDQ50

DDRB_SMA9

DDRA_SDQS0

DDRA_SDQ5

DDRB_SMA1

DDRB_SMA3

DDRB_SDQ10

DDRB_SDQ14

DDRB_SDQ29

DDRA_SDQ23

DDRA_SDQS4

DDRA_SDQ34

DDRA_SDQ19

DDRA_SMA10

DDRA_SDQ24

DDRA_SDQ53

DDRA_SDM4

DDRA_SDQ63

DDRA_SDQ45

DDRA_SDQ37

DDRB_SDQ9

DDRA_SDQ55

DDRB_SDQ59

DDRA_SMA7

DDRA_SDQ26

DDRA_SDQ51 DDRA_SDQ49

DDRB_SCAS#

DDRB_SDM3

DDRB_SMA6

DDRB_SDQ24

DDRB_SBS1

DDRB_SCS#1

DDRB_SMA12

DDRB_SDQS2

DDRB_SDQ15DDRA_SDQ11

DDRA_SDQ3

DDRB_SMA7

DDRB_SDQ1

DDRB_SDQ36

DDRA_SDQ44

DDRB_SDQ5

DDRB_SDQ60

DDRA_SDQ25

DDRB_SDQ62DDRB_SDQ38

DDRB_SDM2

DDRA_SMA1

DDRA_SMA5

DDRA_SDQ18

DDRA_SDQ21

DDRA_SDQ60

DDRA_SDQ42 DDRB_SDQS3

DDRB_SDQ39

DDRB_SDQ23

DDRA_SDQS2

DDRA_SDQ43

DDRA_SDQ62

DDRA_SDQ52

DDRA_SDQ22

DDRA_SDM3

DDRA_SDQ61

DDRA_SDQ16

DDRB_SDQ22

DDRA_SDQ46

DDRB_SDQ57

DDRB_SDQ25

DDRA_SMA0 DDRB_SDM1

DDRB_SDM0

DDRA_SDQ15

DDRA_SDQ20

DDRA_SMA2

DDRB_SDQ43

DDRB_SDQ52

DDRB_SDQ56

DDRB_SDQ19

DDRA_SDQ35

DDRB_SDQ7

DDRA_SMA11

DDRA_SDM6

DDRA_SDM[0..7]

DDRA_SDQ[0..63]

DDRA_SMA[0..12]

DDRA_SDQS[0..7]

DDRB_SDQS[0..7]

DDRB_SDM[0..7]

DDRB_SDQ[0..63]

DDRB_SMA[0..12]

DDRB_SBS0

DDRB_SWE#

DDRB_SMA11

DDRB_CKE0

DDRB_CKE0

DDRB_CKE1

DDRB_SCS#0

DDRB_SCS#1

DDRB_SMA4

DDRB_SMA2

DDRB_SBS0

DDRB_SBS1

DDRA_CKE1

DDRA_SWE#

DDRA_SBS0

DDRA_SMA12

DDRA_CKE0

DDRA_CKE1

DDRA_SCS#0

DDRA_SCS#1

DDRA_SCS#1

DDRB_SWE#

DDRB_SCS#0

V_1P25V_DDR_VTTV_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTTV_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

V_1P25V_DDR_VTT

DDRA_SRAS# <11,15>

DDRB_SCAS# <11,16>

DDRA_SCAS# <11,15>

DDRB_SRAS# <11,16>

DDRA_SDQS[0..7]<11,15>

DDRA_SMA[0..12]<11,15>

DDRA_SDM[0..7]<11,15>

DDRA_SDQ[0..63]<11,15>

DDRB_SDQS[0..7]<11,16>

DDRB_SMA[0..12]<11,16>

DDRB_SDM[0..7]<11,16>

DDRB_SDQ[0..63]<11,16> DDRB_CKE0<11,16> DDRB_CKE1<11,16>

DDRB_SCS#0<11,16> DDRB_SCS#1<11,16>

DDRB_SBS1<11,16> DDRB_SBS0<11,16>

DDRA_CKE0<11,15> DDRA_CKE1<11,15>

DDRA_SCS#0<11,15> DDRA_SCS#1<11,15>

DDRA_SBS1 <11,15>

DDRA_SWE#<11,15> DDRA_SBS0<11,15>

DDRB_SWE#<11,16>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

DDR Termination Resistors

C

17 54Tuesday, March 18, 2003

Channel A(DIMM0) Termination

resistors & Decoupling caps Channel B(DIMM1) Termination

resistors & Decoupling caps

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page22

each Channel(two DIMMs) requirement 4.7u*2 ;

0.1uF*28

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page26

each Channel(two DIMMs) requirement 4.7u*2 ;

0.1uF*26

We used one DIMM, so place 4.7uF*2 ; 0.1uF*23(11/6/02')

We used one DIMM, so place 4.7uF*1 ; 0.1uF*20(11/6/02')

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

RN104 56_4P2R_0404_5%~D

14 23

C481

0.1U_0402_10V6K~D

1

2

RN51 56_4P2R_0404_5%~D

14 23

C495

0.1U_0402_10V6K~D

1

2

RN63 56_4P2R_0404_5%~D

14 23

RN100 56_4P2R_0404_5%~D

14 23

C516

0.1U_0402_10V6K~D

1

2

RN69 56_4P2R_0404_5%~D

14 23

RN22 56_4P2R_0404_5%~D

14 23

RN101 56_4P2R_0404_5%~D

14 23

RN94 56_4P2R_0404_5%~D

1 4

2 3

RN110 56_4P2R_0404_5%~D

14 23

C499

0.1U_0402_10V6K~D

1

2

RN11 56_4P2R_0404_5%~D

14 23

RN14 56_4P2R_0404_5%~D

14 23

RN55 56_4P2R_0404_5%~D

14 23

C436

0.1U_0402_10V6K~D

1

2

RN19 56_4P2R_0404_5%~D

14 23

RN56 56_4P2R_0404_5%~D

14 23

RN88 56_4P2R_0404_5%~D

14 23

RN39 56_4P2R_0404_5%~D

1 4

2 3

RN68 56_4P2R_0404_5%~D

14 23

RN97 56_4P2R_0404_5%~D

1 4

2 3

RN29 56_4P2R_0404_5%~D

1 4

2 3

RN54 56_4P2R_0404_5%~D

14 23

RN76 56_4P2R_0404_5%~D

14 23

RN105 56_4P2R_0404_5%~D

14 23

RN43 56_4P2R_0404_5%~D

14 23

RN27 56_4P2R_0404_5%~D

1 4

2 3

RN65 56_4P2R_0404_5%~D

14 23

RN21 56_4P2R_0404_5%~D

14 23

C434

0.1U_0402_10V6K~D

1

2

C513

0.1U_0402_10V6K~D

1

2

RN66 56_4P2R_0404_5%~D

14 23

C494

0.1U_0402_10V6K~D

1

2

RN10 56_4P2R_0404_5%~D

14 23

C517

0.1U_0402_10V6K~D

1

2

RN67 56_4P2R_0404_5%~D

14 23

RN73 56_4P2R_0404_5%~D

14 23

C515

0.1U_0402_10V6K~D

1

2

RN108 56_4P2R_0404_5%~D

1 4

2 3

RN107 56_4P2R_0404_5%~D

1 4

2 3

RN60 56_4P2R_0404_5%~D

14 23

RN84 56_4P2R_0404_5%~D

1 4

2 3

RN23 56_4P2R_0404_5%~D

14 23

RN16 56_4P2R_0404_5%~D

14 23

C443

0.1U_0402_10V6K~D

1

2

C500

0.1U_0402_10V6K~D

1

2

RN95 56_4P2R_0404_5%~D

1 4

2 3

C484

0.1U_0402_10V6K~D

1

2

RN61 56_4P2R_0404_5%~D

14 23

C518

0.1U_0402_10V6K~D

1

2

C480

0.1U_0402_10V6K~D

1

2

RN25 56_4P2R_0404_5%~D

14 23

RN24 56_4P2R_0404_5%~D

14 23

RN41 56_4P2R_0404_5%~D

14 23

R433 56_0402_5%~D

1 2

RN79 56_4P2R_0404_5%~D

1 4

2 3

RN12 56_4P2R_0404_5%~D

14 23

RN98 56_4P2R_0404_5%~D

14 23

RN92 56_4P2R_0404_5%~D

14 23

C502

0.1U_0402_10V6K~D

1

2

C505

4.7U_1206_16V6K~D

1

2

C504

0.1U_0402_10V6K~D

1

2

C514

0.1U_0402_10V6K~D

1

2

C498

0.1U_0402_10V6K~D

1

2

RN31 56_4P2R_0404_5%~D

1 4

2 3

RN40 56_4P2R_0404_5%~D

14 23

C441

0.1U_0402_10V6K~D

1

2

RN30 56_4P2R_0404_5%~D

1 4

2 3

RN17 56_4P2R_0404_5%~D

14 23

RN33 56_4P2R_0404_5%~D

1 4

2 3

RN57

56_4P2R_0404_5%~D

1 4

2 3

RN83 56_4P2R_0404_5%~D

1 4

2 3

C503

0.1U_0402_10V6K~D

1

2

RN50 56_4P2R_0404_5%~D

14 23

RN82 56_4P2R_0404_5%~D

1 4

2 3

RN46 56_4P2R_0404_5%~D

1 4

2 3

C439

0.1U_0402_10V6K~D

1

2

RN91 56_4P2R_0404_5%~D

14 23

C492

0.1U_0402_10V6K~D

1

2

RN64 56_4P2R_0404_5%~D

14 23

RN81 56_4P2R_0404_5%~D

1 4

2 3

RN52 56_4P2R_0404_5%~D

14 23

RN75

56_4P2R_0404_5%~D

1 4

2 3

C438

0.1U_0402_10V6K~D

1

2

RN87 56_4P2R_0404_5%~D

14 23

RN28 56_4P2R_0404_5%~D

1 4

2 3

C510

4.7U_1206_16V6K~D

1

2

C487

0.1U_0402_10V6K~D

1

2

RN103 56_4P2R_0404_5%~D

14 23

RN96 56_4P2R_0404_5%~D

1 4

2 3

C493

0.1U_0402_10V6K~D

1

2

RN74 56_4P2R_0404_5%~D

14 23

C483

0.1U_0402_10V6K~D

1

2

R431 56_0402_5%~D

1 2

RN78 56_4P2R_0404_5%~D

1 4

2 3

C479

0.1U_0402_10V6K~D

1

2

RN109 56_4P2R_0404_5%~D

1 4

2 3

C440

0.1U_0402_10V6K~D

1

2

RN15 56_4P2R_0404_5%~D

14 23

C486

0.1U_0402_10V6K~D

1

2

RN45 56_4P2R_0404_5%~D

1 4

2 3

RN26 56_4P2R_0404_5%~D

1 4

2 3

RN59 56_4P2R_0404_5%~D

14 23

RN58 56_4P2R_0404_5%~D

14 23

RN71

56_4P2R_0404_5%~D

1 4

2 3

RN37 56_4P2R_0404_5%~D

1 4

2 3

RN53 56_4P2R_0404_5%~D

14 23

C476

0.1U_0402_10V6K~D

1

2

RN32 56_4P2R_0404_5%~D

1 4

2 3

RN77 56_4P2R_0404_5%~D

14 23

C496

0.1U_0402_10V6K~D

1

2

RN44 56_4P2R_0404_5%~D

1 4

2 3

C488

0.1U_0402_10V6K~D

1

2

RN86 56_4P2R_0404_5%~D

14 23

C478

0.1U_0402_10V6K~D

1

2

C511

0.1U_0402_10V6K~D

1

2

RN48 56_4P2R_0404_5%~D

14 23

RN47 56_4P2R_0404_5%~D

1 4

2 3

RN62 56_4P2R_0404_5%~D

14 23

RN89 56_4P2R_0404_5%~D

14 23

C437

0.1U_0402_10V6K~D

1

2

RN93 56_4P2R_0404_5%~D

1 4

2 3

RN102 56_4P2R_0404_5%~D

14 23

RN36 56_4P2R_0404_5%~D

1 4

2 3

R443 56_0402_5%~D

1 2

C482

0.1U_0402_10V6K~D

1

2

RN13 56_4P2R_0404_5%~D

14 23

C442

0.1U_0402_10V6K~D

1

2

C501

0.1U_0402_10V6K~D

1

2

C519

0.1U_0402_10V6K~D

1

2

R405 56_0402_5%~D

1 2

RN38 56_4P2R_0404_5%~D

1 4

2 3

RN99 56_4P2R_0404_5%~D

14 23

RN85 56_4P2R_0404_5%~D

1 4

2 3

RN34 56_4P2R_0404_5%~D

14 23

C477

0.1U_0402_10V6K~D

1

2

RN49 56_4P2R_0404_5%~D

14 23

C485

0.1U_0402_10V6K~D

1

2

RN90 56_4P2R_0404_5%~D

14 23

RN70 56_4P2R_0404_5%~D

14 23

RN72 56_4P2R_0404_5%~D

14 23

C490

4.7U_1206_16V6K~D

1

2

RN18 56_4P2R_0404_5%~D

14 23

RN80 56_4P2R_0404_5%~D

1 4

2 3

RN42 56_4P2R_0404_5%~D

14 23

C512

0.1U_0402_10V6K~D

1

2

RN20

56_4P2R_0404_5%~D

1 4

2 3

RN106 56_4P2R_0404_5%~D

14 23

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

G_ST0

CK_66M_AGP

G_ST2

G_REQ#

G_DBI_LO

G_ST1

G_AD_STBF1

G_DEVSEL#

G_PIPE#_DBI_HI

G_STOP#

G_FRAME#

G_AD_STBS0#

G_AD_STBF0

G_AD_STBS1#

G_REQ#

G_TRDY#

G_SB_STBS#

G_IRDY#

G_PAR

G_SB_STBF

G_GNT#

G_SBA#[0..7]

AGP_PWRON# GPWR_SRC_ON

PCIRST_AGP#

SYS_SUSPEND

AGP_RST#

G_AD23

G_SBA#6

G_AD28

G_AD12

G_AD7

G_AD17

G_C/BE#0

G_PIPE#_DBI_HI

G_AD2

G_AD30

G_AD24

G_AD4

G_PAR

G_DBI_LO

G_AD20

PCI_PIRQA#

G_REQ#

G_SBA#7

G_AD18

G_AD22

G_SBA#0

G_DEVSEL#

G_SBA#5

G_AD14

G_WBF#

G_C/BE#1

G_RBF#

AGP8X_DET_GC

SBAT_SMBDAT

G_AD26

G_SBA#3

G_AD10

VREFGC_R

G_AD6

G_ST1

G_AD8

G_AD16

G_GNT#

G_SBA#1

SBAT_SMBCLK

G_ST2

G_AD21

G_AD3

CK_66M_AGP

ICH_SUS_STAT#

G_AD27

G_FRAME#

G_C/BE#2

G_SBA#4

G_STOP#

G_AD5

G_C/BE#3

G_AD13

G_ST0

AGP8X_DET_CG

G_IRDY#

G_AD_STBF1

G_AD1

G_AD15

G_AD29

RUNPWROK

G_TRDY#

G_AD_STBF0

G_AD9

G_AD0

G_SB_STBS#

VREFCG

G_AD_STBS1#

G_AD11

G_SBA#2

GC_BL_SUSPEND

G_AD_STBS0#

AGP_RST#

G_SB_STBF

PCI_PIRQB#

G_AD31

G_AD19

G_AD25

STP_AGP_R#

FPVCC

FPVCC

+5VSUS

+5VRUN

+3VRUN

+12V

+1.5VRUN

PWR_SRC G_PWR_SRC

G_PWR_SRC

G_PWR_SRC

+3VRUN

+1.5VRUN

+3VSUS

PWR_SRC

+5VALW

+12V

+1.5VRUN

G_PWR_SRC

+1.5VRUN

+1.5VRUN

+3VRUN

+5VALW

+3VRUN

+1.5VRUN

+5VSUS +5VRUN

+3VSUS

G_DBI_LO<12>

G_ST2<12>

G_REQ#<12>

G_FRAME#<12>

G_AD_STBF0<12>

G_AD[0..31]<12>

G_ST0<12>

G_GNT#<12>

G_SB_STBS#<12>

G_IRDY#<12>

G_ST1<12>

G_AD_STBS0#<12>

G_SB_STBF<12>

G_C/BE#[0..3]<12>

G_AD_STBF1<12>

G_TRDY#<12>

G_AD_STBS1#<12>

G_SBA#[0..7]<12>

G_DEVSEL#<12>

G_REQ#<12>

G_STOP#<12>

CK_66M_AGP<6>

G_PAR<12>

G_ST[0..2]<12>

G_PIPE#_DBI_HI<12>

RUN_ON<33,37,39,44>

SYS_SUSPEND <33,41>

PCIRST_AGP# <20>

SBAT_SMBCLK <34>

PCI_PIRQA# <20>

VREFGC <12>

SBAT_SMBDAT <34>

G_RBF# <12>

G_WBF# <12>

AGP8X_DET_GC <12>

VREFCG<12>

RUNPWROK<34,37,43,44,46>

PCI_PIRQB#<20,32>

SP_DIF<24>

ICH_SUS_STAT#<21>

GC_BL_SUSPEND<33>

STP_AGP# <36>

FPVCC<34>

LID_CL# <33>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

18 54Tuesday, March 18, 2003

Compal Electronics, Inc.

VGA Daughter Board Conn.

67,68

147,148

121,122

Shielding Ground Pin

93,94

13,14

39,40

Note:

AGP8X_DET_GC :Pull low by an AGP3.0 graphics card

Floating by an AGP2.0 graphics card

AGP8X_DET_GC : low -->AGP3.0 ; High -->AGP2.0 AGP8X_DET_CG : low -->MB

support AGP3.0

CLOSE

TO PIN

Make R571

100K ohm

after 6th

August

G_AGPBUSY#

FOXCONN QT00160A-9120L

CPLD Disable

Pop R96, Depop R98

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C334

0.047U_0402_10V4M~D

1

2

C336

0.047U_0402_10V4M~D

1

2

C19

0.1U_0603_25V7M~D

1

2

C418

0.047U_0402_10V4M~D

1

2

R98

0_0402_5%~D

1 2

R88

0_0402_5%~D @

1 2

C413

0.1U_0402_16V4Z~D

1

2

Q8

SI4435DY_SO8~D

3 6

5

7

8

2

4

1

C409

0.047U_0402_10V4M~D

1

2

C24

0.1U_0603_25V7M~D

1

2

C26

0.1U_0603_25V7M~D

1

2

C417

0.047U_0402_10V4M~D

1

2

R96

10K_0402_5%~D@

1 2

R322 0_0402_5%~D

12

C23

0.1U_0603_25V7M~D

1

2

R30

100K_0603_5%~D

1 2

JVID

FOX_QT00160A-9120L~D

66 66

GND 68

70 70

72 72

74 74

76 76

78 78

80 80

82 82

84 84

86 86

88 88

90 90

91

91

GND

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

GND

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

GND

147

149

149

151

151

153

153

155

155

157

157

159

159

92 92

GND 94

96 96

98 98

100 100

102 102

104 104

106 106

108 108

110 110

112 112

114 114

116 116

118 118

120 120

GND 122

124 124

126 126

128 128

130 130

132 132

134 134

136 136

138 138

140 140

142 142

144 144

146 146

GND 148

150 150

152 152

154 154

156 156

158 158

160 160

22

44

66

88

10 10

12 12

GND 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

GND 40

42 42

44 44

46 46

48 48

50 50

52 52

54 54

56 56

58 58

60 60

62 62

64 64

1

1

3

3

5

5

7

7

9

9

11

11

GND

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

GND

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

GND

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

C12

0.1U_0603_25V7M~D

1

2

C415

0.1U_0402_16V4Z~D

1

2

R156

0_0402_5%~D

12

C357

0.047U_0402_10V4M~D

1

2

C325

0.047U_0402_10V4M~D

1

2

C388

0.1U_0402_16V4Z~D

1

2

R28

100K_0402_5%~D

12

C416

0.1U_0402_16V4Z~D

1

2

C22

0.1U_0603_25V7M~D

1

2

C397

0.047U_0402_10V4M~D

1

2

C21

0.1U_0603_25V7M~D

1

2

G

D

S

Q7

2N7002_SOT23~D

2

13

C339

0.047U_0402_10V4M~D

1

2

C342

0.047U_0402_10V4M~D

1

2

C317

0.1U_0603_25V7M~D

1

2

U7

TC7SH32FU_SSOP5~D@

INB 1

INA 2

O

4

P5

G

3

C352

0.047U_0402_10V4M~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_THERMDC

FAN3_PWM

FAN3TACH_ON

FAN3_TACH

FAN3_PWM

FAN3_TACH

CLK_SMB

DAT_SMB

MCH_THERMDA

MCH_THERMDC

MCH_THERMDC

MCH_THERMDA

H_THERMDA

+3VRUN +VCC_CORE

+12V

+5VRUN

+5VRUN

+3VRUN

+3VALW

+3VRUN

CLK_SMB<26,34,35,47> DAT_SMB<26,34,35,47>

H_THERMDA <8>

H_THERMDC <8>

ATF_INT# <33,47>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

19 54Tuesday, March 18, 2003

Compal Electronics, Inc.

CPU Thermal Sensor & FAN Control

SI3456DV: N CHANNEL

VGS: 4.5V, RDS: 65 mOHM

Id(MAX): 5.1A

FAN3

FAN3 Control and Tachometer

CPU Temperature Sensor

Address 0101 110X (X=1-->Read; X=0-->Write)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LINK CIS

19.2

Put 3904 between MCH and DDR

R378

6.8K_0603_5%~D

1 2

S

G

D

Q28

SI3456DV-T1_TSOP6~D

3

6

2

4 5

1

R118

10K_0402_5%~D

1 2

R125

10K_0402_5%~D

12

C420

2200P_0603_50V7K~D

1

2

R366

0_0402_5%~D

1 2

D1

RB751V_SOD323~D

2 1

R375

6.8K_0603_5%~D

1 2

C89

0.47U_0805_16V7K~D

1

2

C408

0.1U_0402_16V4Z~D

1 2

C88

10U_1206_16V4Z~D

1

2

R117

10K_0402_5%~D

12

Q29

PMBT2222_SOT23~D

2

3 1

U37

ADT7460ARQ_QSOP16~D

SDA

16

SCL

1

TACH1

6

TACH2

7

TACH3

4

TACH4

9

2.5VIN 14

D1+ 13

D1- 12

D2+ 11

D2- 10

PWM1 15

PWM2/ALERT# 5

PWM3 8

VCC

3

GND

2

R120

1K_0402_5%~D

1 2

Q73

MMBT3904_SOT23~D

2

3 1

JFAN3

SUYIN_250019MR003G400ZL

1

1

2

2

3

3

R365 10K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_SERR#

PCI_DEVSEL#

PCI_REQB#

IDE_IRQ14

PCI_TRDY#

PCI_IRDY#

PCI_PIRQA#

PCI_DEVSEL#

IRQ_SERIRQ

PCI_PERR#

PCI_PCIRST#

PCI_REQ1#

PCI_PIRQB#

PCI_SERR#

PCI_REQ4#

PCI_STOP#

PCI_PERR#

PCI_FRAME#

PCIRSTB4#

PCIRST_SIO#

PCIRST_2#

PCI_REQA#

PCI_STOP#

PCI_REQ0#

PCI_PIRQD#

PCI_PIRQC#

PCI_PLOCK#

PCI_FRAME#

PCI_PLOCK#

PCI_IRDY#

PCI_REQ3#

PCI_GNTA#

PCI_PAR

PCI_REQ2#

PCI_TRDY#

IDE_IRQ15

PCIRSTB1#

PCI_AD31

PCI_AD30

PCI_AD29

PCI_AD28

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

PCI_AD22

PCI_AD21

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD0

PCI_PCIRST#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

ICH_GPIO2_PIRQE#

ICH_GPIO3_PIRQF#

ICH_GPIO4_PIRQG#

ICH_GPIO5_PIRQH#

PCI_REQ1#

PCI_REQ2#

PCI_REQ3#

PCI_REQ4#

ICH_GPIO5_PIRQH#

ICH_GPIO4_PIRQG#

ICH_GPIO3_PIRQF#

ICH_GPIO2_PIRQE#

PCI_GNT1#

PCI_GNT3#

PCI_GNT4#

CK_33M_ICHPCI

CLK_ICH_TERM

CK_33M_ICHPCI

PCI_GNTA#

PCI_GNTB#

PCI_REQA#

PCI_REQB#

HUB_HL0

HUB_HL1

HUB_HL2

HUB_HL3

HUB_HL4

HUB_HL5

HUB_HL6

HUB_HL7

HUB_HL8

HUB_HL9

HUB_HL10

USB_OC0#

USB_OC2#

USB_OC3#

USB_OC4#

ICH_AC_BITCLK_TERM

ICH_AC_SYNC_R

ICH_AC_SDOUT_R

ICH_AC_RST_R#

ICH_AC_SDIN0

ICH_AC_BITCLK

ICH_AC_SDIN1

HI_SWING_ICH

HI_VREF_ICH

ICH_PME#

HI_SWING_ICH

HI_VREF_ICH

HI_RCOMP_ICH

HI_RCOMP_ICH

CK_66M_ICH_TERM

CK_66M_ICH

CK_66M_ICH

ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_SDOUT_R

ICH_AC_SDIN0

ICH_AC_SDIN1

USBRBIAS

CK_48M_ICH_TERM

CK_48M_ICH

LAN_RST#

NC_EE_DOUT

USB_OC7#

USB_OC1#

USB_OC5#

USB_OC6#

PCI_REQ0#

ICH_AC_SDOUT

PCIRSTB3# PCIRST_1#

PCIRST_AGP#

PCIRSTB2#

+3VRUN

+3VRUN

+3VSUS

+3VRUN

+3VRUN

+3VRUN +3VRUN

+3VRUN

+3VRUN

+3VSUS

+5VSUS

+1.5VRUN

+1.5VRUN

+5VSUS

+3VRUN

IDE_IRQ14 <21>

IRQ_SERIRQ <21,30,33>

PCI_PAR<28,30,32>

PCI_IRDY#<28,30,32>

PCI_PERR#<28,30,32>

PCI_FRAME#<28,30,32>

PCI_DEVSEL#<28,30,32> PCI_TRDY#<28,30,32>

PCI_STOP#<28,30,32>

PCIRST_SIO# <33>

PCIRST_2# <32>

IDE_IRQ15 <21,23>

PCI_AD[0..31] <28,30,32>

PCI_C_BE3# <28,30,32>

PCI_C_BE2# <28,30,32>

PCI_C_BE1# <28,30,32>

PCI_C_BE0# <28,30,32>

PCI_SERR#<28,30,32>

PCI_PIRQA#<18> PCI_PIRQB#<18,32> PCI_PIRQC#<28,30> PCI_PIRQD#<30,32>

PCI_REQ1#<30>

PCI_REQ3#<32> PCI_REQ4#<28>

PCI_GNT1#<30>

PCI_GNT3#<32> PCI_GNT4#<28>

CK_33M_ICHPCI<6>

PCI_GNTB#<30>

PCI_REQB#<30>

HUB_HL[0..10]<12>

HUB_HLSTRF<12> HUB_HLSTRS<12>

USBP4+ <26>

USBP4- <26>

USBP3+ <26>

USBP3- <26>

USBP2+ <26>

USBP2- <26>

USBP1+ <26>

USBP1- <26>

USBP0+ <26>

USBP0- <26>

USB_OC0# <26>

USB_OC2# <26>

USB_OC3# <26>

USB_OC4# <23>

ICH_AC_SDOUT <24,27>

ICH_A C_SYNC <24,27>

ICH_AC_RST# <24,27>

ICH_PME#<33> PCI_PCIRST#<12,36>

CK_66M_ICH<6>

ICH_AC_SDIN0<24> ICH_AC_SDIN1<27>

ICH_AC_BITCLK<24>

CK_48M_ICH <6>

USBP6- <26>

USBP6+ <26>

USB_OC6# <26>

PCIRST_1# <28>

PC IRST_AGP# <18>

PCIRST_CB# <30>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

20 54Tuesday, March 18, 2003

Compal Electronics, Inc.

ICH5-PCI/HUB/USB/AC97

USB_OC IS 5V

TOLERANT

Close to ICH ball <250mils

Close to ICH ball <250mils

Note:

HI_SWING_MCH, HI_VREF_MCH

trace width of 12mils and

space 10mils

0.1"~6"

Note:

USBRBIAS keep less than 500mils

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R119

8.2K_0402_5%~D

12

C460

0.1U_0402_16V4Z~D

1

2

R162

33_0402_5%~D

1 2

C431

4.7P_0402_50V8C~D

@

1

2

C464

10P_0402_50V8J~D

@

1

2

R414

10_0402_5%~D@

12

RN35

8.2K_8P4R_1206_5%~D

18 27 36 45

C118

0.1U_0402_16V4Z~D

12

R398

8.2K_0402_5%~D

@

12

U8D

74VHC08MTC_TSSOP14~D

IN1

13

IN2

12 OUT 11

RN1

8.2K_8P4R_1206_5%~D

18 27 36 45

R387

10K_0402_5%~D

12

C427

10P_0402_50V8J~D

@

1

2

R153

33_0402_5%~D

1 2

R159

33_0402_5%~D

1 2

R395

10K_0402_5%~D@

12

C465

8.2P_0402_50V8J~D

@

1

2

C456

0.1U_0402_16V4Z~D

1

2

R390 33_0402_5%~D

12

R426

10K_0402_5%~D

12

U5A

FW82801EB_mBGA460_ICH5~D

PIRQA#

B3

PIRQB#

E1

PIRQC#

A2

PIRQD#

C2

PIRQE#/GPI2

D7

PIRQF#/GPI3

A6

PIRQG#/GPI4

E2

PIRQH#/GPI5

B1

REQ0#

D5

REQ1#

C1

REQ2#

C5

REQ3#

B6

REQ4#/GPI40

C6

REQA#/GPI0

A5

REQB#REQ5#/GPI1

E7

GNT0#

D4

GNT1#

A3

GNT2#

B7

GNT3#

C7

GNT4#/GPO48

A4

GNTA#/GPO16

E8

GNTB#/GNT5#/GPO17

B4

FRAME#

D2

IRDY#

M3

TRDY#

E4

DEVSEL#

L3

STOP#

E5

PAR

F1

PERR#

K2

PLOCK#

L2

SERR#

L4

PME#

V2

PCIRST#

V4

PCICLK

N1

AD31 P2

AD30 F4

AD29 P4

AD28 F5

AD27 N2

AD26 D3

AD25 P3

AD24 E6

AD23 N4

AD22 C4

AD21 N5

AD20 H3

AD19 P5

AD18 B2

AD17 L1

AD16 G4

AD15 G5

AD14 K1

AD13 G2

AD12 L5

AD11 H4

AD10 M4

AD9 F2

AD8 K5

AD7 J2

AD6 J3

AD5 H2

AD4 H5

AD3 K4

AD2 G3

AD1 J5

AD0 J4

C/BE3# M2

C/BE2# N3

C/BE1# J1

C/BE0# E3

U8C

74VHC08MTC_TSSOP14~D

IN1

10

IN2

9OUT 8

R157

33_0402_5%~D

1 2

R386

10K_0402_5%~D

12

R413

10_0402_5%~D@

1 2

RN4

8.2K_8P4R_1206_5%~D

18 27 36 45

R409

113_0603_1%

12

R383

1K_0402_5%~D@

1 2

R404

10_0402_5%~D@

12

R410

147_0603_1%~D

12

R124

52.3_0603_1%~D

1 2

RN3

8.2K_8P4R_1206_5%~D

18 27 36 45

R393

10K_0402_5%~D

1 2

C452

0.01U_0402_16V7K~D

1

2

R401

10K_0402_5%~D

12

R392 1K_0402_5%~D@

1 2

R430 0_0402_5%~D

12

R396

10_0402_5%~D@

1 2

R406 61.9_0603_1%

1 2

R425

10K_0402_5%~D@

12

R402

10K_0402_5%~D@

12

RN2

8.2K_8P4R_1206_5%~D

18 27 36 45

R160

33_0402_5%~D

1 2

R389 33_0402_5%~D

12

U8A

74VHC08MTC_TSSOP14~D

IN1

1

IN2

2OUT 3

P14

G

7

R385 33_0402_5%~D

12

R397

10K_0402_5%~D@

12

U5B

FW82801EB_mBGA460_ICH5~D

HI0

H20

HI1

H21

HI2

J20

HI3

H23

HI4

M23

HI5

M21

HI6

N21

HI7

M20

HI8

L22

HI9

J22

HI10

K21

HI11

G22

HI_STBF

K23

HI_STBS

J24

HIRCOMP

N24

HI_VSWING

L20

HIREF

L24

CLK66

N22

LAN_RXD0

C10

LAN_RXD1

C9

LAN_RXD2

C11

LAN_TXD0

D9

LAN_TXD1

E9

LAN_TXD2

B12

LAN_RSTSYNC

D10

LAN_CLK

E10

LAN_RST#

AA1

EE_DIN

B11

EE_CS

B10

EE_SHCLK

A12

EE_DOUT

B9

AC_SYNC

B8

AC_RST#

C12

AC_SDOUT

A9

AC_SDIN0

E12

AC_SDIN1

D12

AC_SDIN2

A13

AC_BIT_CLK

D8

USBP0P C23

USBP0N D23

USBP1P A22

USBP2P C21

USBP2N D21

USBP3P A20

USBP3N B20

USBP4P C19

USBP4N D19

USBP5P A18

USBP5N B18

USBP6P C17

USBP6N D17

USBP7P A16

USBP7N B16

USBP1N B22

OC0# C15

OC1# D15

OC2# D14

OC3# C14

OC4#/GPI9 B14

OC5#/GPI10 A14

OC6#/GPI14 D13

OC7#/GPI15 C13

USBRBIAS A24

USBRBIAS# B24

CLK48 F24

RP2

10K_10P8R_1206_5%

10

9

8

7

6

1

2

3

4

5

R394 22.6_0603_1%~D

12

U8B

74VHC08MTC_TSSOP14~D

IN1

4

IN2

5OUT 6

C455

0.01U_0402_16V7K~D

1

2

R411

226_0603_1%~D

12

R139

10K_0402_5%~D

12

R113

10K_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IDE_PDD3

IDE_PDD14

LPC_LAD2

IDE_PDD0

LPC_LDRQ0#

IDE_PDD10

LPC_LAD1

IDE_PDD9

IDE_PDDACK#

IDE_PDIOW#

ATA_66_PRI/PDIAG

LPC_LFRAME#

IDE_PDD2

IDE_PDCS1#

IDE_PDD4

IDE_PDD5

IDE_RST_HDD_5V

IDE_PDIORDY

IDE_IRQ14

IDE_PDD13

IDE_PDD15

IDE_PDD11

IDE_PDCS3#

IDE_PDA2

LPC_LAD3

IDE_PDD1

LPC_LAD0

IDE_PDIORDY

IDE_PDA0

IDE_PDIOR#

IDE_PDA1

IDE_PDD12

RPD DREQ

LPC_LDRQ0#

IDE_PDD6

IDE_SDIORDY

IDE_CSEL_PRI

LPC_LDRQ1#

PIDEACT#

IDE_PDD7 IDE_PDD8

LPC_LDRQ1#

IDE_SDD7

IDE_PDD6

IDE_PDD15

IDE_PDD7

IDE_PDD2

IDE_SDD6

IDE_PDDREQ

IDE_PDD3

IDE_PDD11

IDE_SDA0

IDE_SDD12

IDE_SDD1

IDE_PDD5

IDE_SDD9

IDE_SDD11

IDE_PDIOW#

IDE_SDD2

IDE_PDD9

IDE_IRQ15

IDE_PDD10

IDE_SDD3

IDE_PDA2

IDE_PDIOR#

IDE_SDD10

IDE_PDD14

IDE_SDD4

IDE_SDD8

IDE_SDD14

IDE_PDD12

IDE_SDIORDY

IDE_PDD0

IDE_PDA1

IDE_PDD8

IDE_SDD0

IDE_SDDACK#

IDE_SDD13

IDE_PDDACK#

IDE_SDA2

IDE_PDD4

IDE_PDIORDY

IDE_PDD1

IDE_PDD13

IDE_SDIOW#

IDE_PDA0 IDE_SDA1

IDE_SDDREQ

IDE_SDD15

IDE_SDD5

RSD DREQ

IDE_PDDREQ

IDE_SDDREQ

IDE_SDIOR#

RPD DREQ

SMI#

H_THERMTRIP_R#

SATABIAS

ICH_SMBCLK

ICH_SMLINK1

ICH_SMBDATA

ICH_SMLINK0

LINK_ALERT#

SPKR

ICH_RTCX1

ICH_RTCX2

ICH_RTCX1

ICH_RTCX2

ICH_RTCRST#

PWRGD_OK

ICH_RI#

ICH_BATLOW#

SIO_SLP_S3#

VRM_PWRGD

SIO_THRM#

ICH_THERM_PWRDN#

ICH_THERM_PWRDN#

BID1

BID3

BID0

BID1

BID2

BID3

LAN_PME#

IDE_RST_MOD_SFTON

IDE_RST_HDD_5V

IDE_RST_MOD_SFTON

SIO_THRM#

VRM_PWRGD

SIO_EXT_SMI#

SIO_EXT_SMI#

SIO_EXT_RTE#

SIO_EXT_RTE#

SIO_EXT_SCI#

SIO_EXT_SCI#

BID0

SPKR

CK_14M_ICH_TERM

ICH_INTVRMEN

SIO_SLP_S3#

SUSCLK

SUSCLK

SIO_SLP_S5#

SIO_SLP_S4#

BID2

VCC_RTC

H_THERMTRIP_R#

ICH_RTCRST#

SATA_LED#

IDE_PDCS1#

IDE_PDCS3# IDE_SDCS1#

IDE_SDCS3#

CBS_RI#ICH_RI#

+3VRUN

+5VHDD

+3VRUN

+5VHDD

+5VHDD

+3VSUS

+3VSUS

+3.3VRTC

+3VSUS

+3VSUS

+3.3VRTC

+3VSUS

+3VSUS

+3VRUN

+3VSUS

+3VRUN

+5VHDD

+3VRUN

+5VMOD

+3VRUN

+3VRUN

VCC_RTC

VCC_RTC

+3VRUN

+VCC_CORE

+3VRUN

+3VRUN

+3VSUS

PIDEACT#<38>

LPC_LAD[0..3]<33>

IDE_SDA[0..2] <23>

IDE_SDD[0..15] <23>

IDE_SDDACK# <23>

IDE_SDCS3# <23>

I DE_ SD IO W# <23>

IDE_SDIORDY <23>

RSDDREQ <23>

IDE_IRQ14<20> IDE_IRQ15 <20,23>

IDE_SDIOR# <23>

LPC_LFRAME#<33> LPC_LDRQ0#<34> LPC_LDRQ1#<33>

H_PWRGOOD <8>

CPUSLP#<36> H_A20M#<8>

H_IGNNE#<8>

H_INTR<8> H_NMI<8>

SIO_A20GATE<34>

H_FERR#<8>

H_INIT#<8>

SIO_RCIN#<33>

H_SMI#<8>

STPCLK#<36>

ICH_SMBCLK <6,15,16,32>

ICH_SMBDATA <6,15,16,32>

SPKR <24>

SUSPWROK<36,37>

ICH_SUS_STAT# <18>

SIO_SLP_S3# <33>

ICH_SLP_S1# <6>

SIO_SLP_S4_S5# <33>

VRM_PWRGD <36>

SIO_THRM# <33>

CK_14M_ICH <6>

ICH_THERM_PWRDN# <37>

IDE_RST_HDD<33>IDE_RST_MOD<33> IDE_RST_MOD_5V <23>

IRQ_SERIRQ<20,30,33>

SIO_EXT_SMI# <33>

SIO_EXT_RTE# <33>

SIO_EXT_SCI# <33>

CK_100M_ICH#<6> CK_100M_ICH<6>

SATA_MODTX+<23> SATA_MODTX-<23>

SATA_MODRX+<23> SATA_MODRX-<23>

SUSCLK <36>

ICH_SYNC#<12>

PWRGD_3V<10,37>

SI O_PWRBTN# <33>

H_THERMTRIP# <8,37>

IDE_SDCS1# <23>

CBS_RI# <30>

CPLD_WAKE# <36>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

21 54Tuesday, March 18, 2003

Compal Electronics, Inc.

ICH5-IDE/LPC/PM/GPIO/LAN

12/17/02 Changed by

Dell's Require

Note:

SATABIAS keep

less than

500mils

3

BAT54C

K2 K1

2A1A2

1

BID0BID1BID2BID3 REV

0000

000

00 0

00

000

1

1

11

1

X00

X01

X02

X03

X04

LK2-->USB2P0_SMI

Disable timer timeout

ICH_SYNC# PWRGD_3V PWRGD_OK

0

1

0

0

0

0

001

111

CPLD Disable

Depop R141

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Please link CIS

8.1

Connector on

bottom side

HH99227-S9

2

1

43

44

Top View

R432

10K_0402_5%~D

12

R141 0_0402_5%~D

1 2

C238

4.7U_1206_16V6K~D

1

2

C120

1U_0805_10V6K~D

1

2

R134 0_0402_5%~D

12

R423 24.9_0603_1%~D

1 2

R122 10K_0402_5%~D

1 2

JHDD

FOX_HH99227-S9~D

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

SGND 45

SGND 46

SGND 47

SGND 48

B1

49

B2

50

R114

1K_0402_5%~D@

1 2

R127

0_0402_5%~D

12

R429 0_0402_5%~D

1 2

R439 0_0402_5%~D

1 2

R269

1K_0603_5%~D@

1 2

R143

2.7K_0402_5%

12

R417 10K_0402_5%~D

1 2

R138

10K_0402_5%~D

12

R265

0_0402_5%~D

1 2

R148

2.7K_0402_5%

12

C509

15P_0603_50V8J~D

12

R142 10K_0402_5%~D

1 2

R128

10K_0402_5%~D

@

1 2

X4

32.768KHZ_12.5P_MC-306~D

1 2

R40310K_0402_5%~D

12

R399

10K_0402_5%~D@

1 2

R274

4.7K_0402_5%~D

12

R416

10K_0402_5%~D

1 2

R167

220_0402_5%@

12

R438

0_0402_5%~D

1 2

R441

100K_0402_5%~D

1 2

R419

10K_0402_5%~D@

1 2

C469

0.1U_0402_16V4Z~D@

1

2

R149 10K_0402_5%~D

1 2

R279

0_0402_5%~D

1 2

R435 330K_0402_5%~D

1 2

C251

33P_0603_50V8J~D

@

1

2

R427 10K_0402_5%~D

1 2

R263

0_0402_5%~D

1 2

R558

0_0402_5%~D

1 2

D3

BAT54C_SOT23~D

3 2

1

R135 10K_0402_5%~D

1 2

R568

1K_0402_5%~D

12

Q33

MMBT3904_SOT23~D@

2

3 1

R161

220_0402_5%@

12

R154

180K_0603_5%

1 2

R436

10K_0402_5%~D

12

R13010K_0402_5%~D

12

R140

0_0402_5%~D@

12

R266

10K_0402_5%~D@

1 2

R422

0_0402_5%~D@

1 2

U5C

FW82801EB_mBGA460_ICH5~D

PDD15

AB17

PDD14

AA16

PDD13

Y16

PDD12

AC16

PDD11

AA15

PDD10

AD16

PDD9

Y15

PDD8

AD15

PDD7

AB14

PDD6

AD14

PDD5

AC15

PDD4

AA14

PDD3

AC14

PDD2

Y14

PDD1

Y13

PDD0

AB16

PDIOW#

AA17

PDDACK#

AC18

PDDREQ

AC17

PDIOR#

AD18

PIORDY

AA18

PDA2

AC19

PDA1

AD19

PDA0

AA19

PDCS3#

Y18

PDCS1#

AB19

IRQ14

Y17

SDD0 AA22

SDD1 AB23

SDD2 AD23

SDD3 AD24

SDD4 AB21

SDD5 AC21

SDD6 AB20

SDD7 AC20

SDD8 Y19

SDD9 AD22

SDD10 AC22

SDD11 AA20

SDD12 AB22

SDD13 AC24

SDD14 AB24

SDD15 AA23

SDIOW# Y22

SDDACK# W20

SDDREQ Y20

SDIOR# Y23

SIORDY Y21

SDA2 W21

SDA1 W23

SDA0 W22

SDCS3# V20

SDCS1# V22

IRQ15 Y24

R169

1K_0402_5%~D@

12

C608

33P_0603_50V8J~D@

1

2

R158

1K_0402_5%~D

1 2

R121

10K_0402_5%~D@

1 2

R11510K_0402_5%~D

12

C508

15P_0603_50V8J~D

12

R570

470_0603_5%~D

12

T13

PAD@

C119

0.1U_0402_10V6K~D

1

2

R420 10K_0402_5%~D

1 2

U5D

FW82801EB_mBGA460_ICH5~D

A20GATE

T22

A20M#

V23

CPUSLP#

P22

FERR#

U24

IGNNE#

R21

INIT#

R23

INTR

U23

NMI

R22

RCIN#

P23

SERIRQ

F23

SMI#

V24

STPCLK#

T24

DPRSLPVR(Mobile)

P20

DPSLP#(Mobile)

R24

SATA0TXP

AA8

SATA0TXN

AB8

SATA0RXN

AD7

SATA0RXP

AC7

SATA1TXP

AA10

SATA1TXN

AB10

SATA1RXN

AD9

SATARBIASP

Y11

SATARBIASN

Y9

CLK100P

AC5

CLK100N

AD5

LAD0

T5

LAD1

R4

LAD2

R3

LAD3

U4

LFRAME#

T4

LDRQ0#

U5

LDRQ1#/GPI41

R2

RTCX1

AC11

RTCX2

AB12

RTCRST#

AA12

RSMRST#

AB13

PWROK

AC12

GPIO6 R5

GPIO7 U3

GPIO8 Y2

SMBALERT#/GPI11 AC3

GPIO12 W4

GPIO13 W5

GPO18 U21

GPO19 T20

GPIO20 U22

GPIO21 R1

GPIO22 U20

GPIO23 F22

GPIO24 AC1

GPIO25 W3

GPIO27 V3

GPIO28 W2

GPIO32 T1

GPIO33 G23

GPIO34 F21

SMBCLK AD2

SMBDATA AD1

SMLINK0 AD3

SMLINK1 AA2

LINKALERT# V5

SPKR E24

RI# AB3

PWRBTN# Y4

SUSCLK Y1

TP0 AB2

SUS_STAT# AB1

SLP_S3# W1

SLP_S4# U2

SLP_S5# AA3

SYS_RESET# U1

VRMPWRGD R20

CPUPWRGD/GPO49 P24

THRMTRIP# T21

THRM# T2

INTVRMEN AD10

CLK14 F20

INTRUDER# Y12

NC A11

SATA1RXP

AC9

C240

0.1U_0402_16V4Z~D

1

2

R400

10_0402_5%~D@

1 2

R562

4.7K_0402_5%~D

12

R123

10K_0402_5%~D

@

1 2

Q32

MMBT3904_SOT23~D@

2

3 1

Q46

MMBT3904_SOT23~D@

2

3 1

R132 10K_0402_5%~D

1 2

C428

4.7P_0402_50V8C~D@

1

2

R116

10K_0402_5%~D@

1 2

R424 0_0402_5%~D

@

1 2

R421 10K_0402_5%~D

1 2

R388

10K_0402_5%~D

12

R428

10K_0402_5%~D

1 2

R437

10M_0603_5%~D

12

R434 10K_0402_5%~D

@

1 2

Q51

MMBT3904_SOT23~D @

2

3 1

R262

1K_0603_5%~D

@

1 2

R471

1K_0402_5%~D

1 2

CMOS_CLR

SHORT PADS

11

2

2

R271

10K_0402_5%~D@

1 2

R12610K_0402_5%~D

12

C237

0.1U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ICH_V5REF_RUN

ICH_V5REF_SUS

VCCSUS15_A

VCCSUS15_B

VCCSUS15_C

+3VRUN

+3VRUN +1.5VRUN

+5VRUN

+3VSUS

+3VSUS

+5VSUS

+VCC_CORE

+VCC_CORE

+1.5VRUN+3VRUN

+1.5VRUN +1.5VRUN

VCC_RTC

+3VSUS

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

22 54Tuesday, March 18, 2003

Compal Electronics, Inc.

ICH5 Power & Decoupling

Place near ball(VSS)

D1,A7,H1,P1W24 and A21

Place0.1u near ball(VSS)

A17,A23,V1.Addition cap near

A15,A19

Place near

ball T22

Place0.1u near ball(VSS)

G24,H24,K24,M24,AD4

and AD18; 0.01u near to

ball AD8.

Place near

ball (VSS)A19

Place near

ball (VSS)AD4

Place near

ball (VSS)A7

Place near ball A8

Place near ball(VSS) A17

Place near ball AD11

Place near ball D24 Place near ball AD6

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11

(12474)page278

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

D13

RB751V_SOD323~D

21

C447

1U_0805_10V6K~D

1

2

C506

0.1U_0402_10V6K~D

1

2

C453

0.1U_0402_16V4Z~D

12

C432

0.1U_0402_16V4Z~D

12

C466

0.1U_0402_16V4Z~D

12

C471

0.1U_0402_16V4Z~D

1

2

U5F

FW82801EB_mBGA460_ICH5~D

VSS

A1

VSS

A10

VSS

A15

VSS

A17

VSS

A19

VSS

A21

VSS

A23

VSS

A7

VSS

AA11

VSS

AA13

VSS

AA21

VSS

AA24

VSS

AA5

VSS

AA7

VSS

AA9

VSS

AB11

VSS

AB15

VSS

AB18

VSS

AB5

VSS

AB7

VSS

AB9

VSS

AC10

VSS

AC13

VSS

AC2

VSS

AC23

VSS

AC4

VSS

AC6

VSS

AC8

VSS

AD17

VSS

AD21

VSS

AD12

VSS

AD4

VSS

AD6

VSS

AD8

VSS

B13

VSS

B17

VSS

B19

VSS

B21

VSS

B23

VSS

C16

VSS

C18

VSS

C20

VSS

C22

VSS

C3

VSS

C8

VSS

D1

VSS

D11

VSS

D16

VSS

D18

VSS

D20

VSS

D22

VSS

D24

VSS

D6

VSS

E17

VSS

E19

VSS

E20

VSS

E21

VSS

E23

VSS

F3

VSS

F9

VSS G20

VSS G24

VSS G6

VSS H1

VSS H19

VSS H22

VSS J21

VSS J23

VSS J6

VSS K11

VSS K14

VSS K20

VSS K22

VSS K24

VSS K3

VSS L10

VSS L11

VSS L12

VSS L13

VSS L14

VSS L15

VSS L21

VSS L23

VSS M1

VSS M11

VSS M12

VSS M13

VSS M14

VSS M22

VSS M24

VSS M5

VSS N11

VSS N12

VSS N13

VSS N14

VSS N20

VSS P1

VSS P10

VSS P11

VSS P12

VSS P13

VSS P14

VSS P15

VSS P21

VSS R11

VSS R14

VSS T23

VSS T3

VSS T6

VSS U19

VSS V1

VSS V21

VSS W16

VSS W18

VSS Y10

VSS Y3

VSS Y6

VSS Y7

VSS Y8

C435

1U_0603_6.3V6M~D

1 2

C463

0.1U_0402_16V4Z~D

12

C430 0.01U_0402_16V7K~D

1 2

C448

0.1U_0402_16V4Z~D

12

C468

1U_0805_10V6K~D

1

2

C474

0.1U_0402_16V4Z~D

12

C449

0.1U_0402_16V4Z~D

12

C451

0.1U_0402_16V4Z~D

12

C491

0.1U_0402_16V4Z~D

12

C454

0.1U_0402_16V4Z~D

12

C425

0.01U_0402_16V7K~D

1 2

C475 0.01U_0402_16V7K~D

1 2

C444

0.1U_0402_16V4Z~D

1

2

U5E

FW82801EB_mBGA460_ICH5~D

VCC3_3

F6

VCC3_3

G1

VCC3_3

H6

VCC3_3

K6

VCC3_3

L6

VCC3_3

M10

VCC3_3

N10

VCC3_3

P6

VCC3_3

R13

VCC3_3

V19

VCC3_3

W15

VCC3_3

W17

VCC3_3

W24

VCC3_3

AD13

VCC3_3

AD20

VCC3_3

G19

VCC3_3

G21

VCCSUS3_3

E18

VCCSUS3_3

B15

VCCSUS3_3

E11

VCCSUS3_3

F10

VCCSUS3_3

F11

VCCSUS3_3

E13

VCCSUS3_3

E14

VCCSUS3_3

U6

VCCSUS3_3

V6

VCCSUS3_3

F16

VCCSUS3_3

F17

VCCSUS3_3

F18

VCCSUS3_3

K15

V5REF

A8

V5REF

W14

V5REF_SUS

E16

VCCRTC

AD11

VCC1_5 K10

VCC1_5 K12

VCC1_5 K13

VCC1_5 L19

VCC1_5 P19

VCC1_5 R10

VCC1_5 R6

VCC1_5 H24

VCC1_5 J19

VCC1_5 K19

VCC1_5 M15

VCC1_5 N15

VCC1_5 N23

VCC1_5 E15

VCC1_5 F15

VCC1_5 F14

VCC1_5 W19

VCC1_5 R12

VCC1_5 W9

VCC1_5 W10

VCC1_5 W11

VCC1_5 W6

VCC1_5 W7

VCC1_5 W8

VCCSATAPLL AA6

VCCSATAPLL AB6

VCCUSBPLL C24

VCCSUS1_5_A F19

VCCSUS1_5_B Y5

VCCSUS1_5_B AA4

VCCSUS1_5_B AB4

VCCSUS1_5_C F7

VCCSUS1_5_C F8

VCC1_5 E22

V_CPU_IO R15

V_CPU_IO R19

V_CPU_IO T19

VCC3_3

B5

C429

0.1U_0402_16V4Z~D

12

C446

0.1U_0402_16V4Z~D

12

C426

0.01U_0402_16V7K~D

1 2

R391

1K_0402_5%~D

1 2

C470

0.1U_0402_16V4Z~D

1

2

C424

0.1U_0402_16V4Z~D

12

C473

0.1U_0402_16V4Z~D

12

C472

0.1U_0402_16V4Z~D

1

2

D14

RB751V_SOD323~D

21

C450

0.01U_0402_16V7K~D

1 2

C467

0.1U_0402_16V4Z~D

12

C497

0.1U_0402_16V4Z~D

12

R384

1K_0402_5%~D

1 2

C457

0.1U_0402_16V4Z~D

12

C445

0.1U_0402_16V4Z~D

1

2

C433 0.01U_0402_16V7K~D

1 2

C489

0.01U_0402_16V7K~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

INT_CD_R

IDE_SDDACK#

BAY_MODPRES#

RSDDREQ

IDE_SDIORDY

IDE_IRQ15

IDE_SDCS1#

IDE_SDIOW#

INT_CD_L

IDE_SDCS3#

IDE_SDIOR#

IDE_RST_MOD_5V

IDE_SDD12

IDE_SDD1

IDE_SDD8

USBP4_D+

IDE_IRQ15

IDE_SDD11

BAY_MODPRES#

IDE_SDD13

IDE_SDD14

RSDDREQ

IDE_SDCS1#

IDE_SDD10

IDE_SDD3

IDE_SDD0

IDE_SDIOR#

IDE_SDDACK#

IDE_SDA1

IDE_SDA2

IDE_SDD7

IDE_SDD6

IDE_SDIORDY

IDE_SDD4

IDE_SDA0

IDE_SDD9

IDE_SDD2

IDE_SDIOW#

IDE_SDD15

IDE_SDCS3#

CD_AUDIORET

MOD_RST

IDE_SDD5

USBP4_D-

INT_CD_L

INT_CD_R

SATA_MOD_DETECT#

IDE_SDD8

IDE_SDD7

IDE_SDD12

IDE_SDA1

IDE_SDD2

IDE_SDD1

IDE_SDD3

IDE_SDA0

IDE_SDD11

IDE_SDD4

IDE_SDD10

IDE_SDD13

CSEL2

IDE_SDD9

IDE_SDD14

IDE_SDD15

IDE_SDA2

IDE_SDD0

IDE_SDD6

USB_IDE#

IDE_SDD5

MOD_PIN15

PDIAG#

SATA_MOD_DETECT#USB_OC4#

SIDEACT#

+3VALW +3VALW

+5VMOD +3VMOD

+3VMOD

+3VMOD

+3VALW

INT_CD_R<24>

IDE_SDIOR#<21>

IDE_SDCS1#<21>

IDE_SDA[0..2]<21>

INT_CD_L<24>

IDE_SDIORDY<21>

IDE_SDCS3#<21>

IDE_SDD[0..15]<21>

IDE_SDIOW#<21>

RSDDREQ<21>

IDE_IRQ15<20,21>

BAY_MODPRES#<33>

IDE_SDDACK#<21> USBP4_D+ <26>

USBP4_D- <26>

INT_CD_R <24>

INT_CD_L <24>

USB_IDE#<33>

IDE_RST_MOD_5V<21>

CD_AUDIORET<24>

SATA_MOD_DETECT# <33>

USB_OC4# <20>

SATA_MODTX+<21>

SATA_MODTX-<21>

SATA_MODRX-<21>

SATA_MODRX+<21>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

23 54Tuesday, March 18, 2003

Compal Electronics, Inc.

D- MODULE

WF1F068N1A

1

3

4

6

2

TOP VIEW

5

Reserved USB+

Reserved USB-

swap by Dell require

Please see sketch

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Parallel IDE

USB Device

S-ATA IDE

None

BAY_MODPRES#

Pin68

USB_IDE#

Pin64

SATA_MOD_DETECT#

Pin13

JMOD1

Device

LOW

LOW

LOW

LOW

LOW

HIGH

HIGH HIGH

HIGH

HIGH X X

D-MODULE Detect

MB side Module side

Direct connect

Connector

Host Chip

ICH5 Device Chip

TX+

TX-

TX+

TX-

RX+

RX+

RX-

RX-

Please link CIS

8.2

C614

0.1U_0402_16V4Z~D

1

2

T12 PAD@

R563

470_0603_5%~D

1 2

C615

0.1U_0402_16V4Z~D

1

2

C616

0.1U_0402_16V4Z~D

1

2

R555

0_0402_5%~D

1 2

R554

100K_0402_5%~D

1 2

JMOD1

FOX_QL11343-A6B3-HT~D

11

2

2

33

4

4

55

6

6

77

8

8

99

10

10

11 11

12

12

13 13

14

14

15 15

16

16

17 17

18

18

19 19

20

20

21 21

22

22

23 23

24

24

25 25

26

26

27 27

28

28

29 29

30

30

31 31

32

32

33 33

34

34

35 35

36

36

37 37

38

38

39 39

40

40

41 41

42

42

43 43

44

44

45 45

46

46

47 47

48

48

49 49

50

50

51 51

52

52

53 53

54

54

55 55

56

56

57 57

58

58

59 59

60

60

61 61

62

62

63 63

64

64

65 65

66

66

67 67

68

68

M1 73

M2

74

G69

G71

G

70

G

72

C613

0.1U_0402_16V4Z~D

1

2

R564 1K_0402_5%~D

1 2

C602

47P_0402_50V8J~D

1

2

C612

0.1U_0402_16V4Z~D

1

2

C617

4.7U_1206_16V6K~D

1

2

R569

1K_0402_5%~D

1 2

R553

100K_0402_5%~D

1 2

C601

47P_0402_50V8J~D

1

2

R567

0_0402_5%~D@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ICH_AC_SDOUT

ICH_AC_RST#

R_ICH_AC_BITCLK

CD_AUDIORET

CAP2

SPK_SHUTDOWN#

ICH_AC_SDOUT_TERM

XTL_24M+

R_ICH_AC_SDIN0

EAPD

CD_COMM

HP_COMM

SPDIF_SHDN

CD_L

CD_R

VREFOUT

ICH_AC_SDOUT

AC97VREFI CNB_MICIN

AFLT2

ICH_AC_SYNC

AUDIO_AVDD_ON TPS793475_BYPASS

AFLT1

XTL_24M-

AU DIO_AVCC

Z2402

Z2401

Z2403 PC_BEEPINZ2404

PC_BEEPIN

SPDIF

SPDIF_SHDN

SPDIF

HP_OUT_LL

HP_OUT_RR

+3VRUN

VDDA

VDDA

+5VSUS

VDDA

+5VRUN

INT_CD_R <23>

ICH_AC_RST#<20,27>

AUD_LINE_OUT_L <25>

SPK_SHUTDOWN#<25,50>

EAPD<25>

ICH_AC_SDOUT<20,27>

CD_AUDIORET <23>

MDC_AC_BITCLK<27>

NB_MICIN <25>

ICH_AC_SYNC<20,27>

INT_CD_L <23>

AU D_LINE_OUT_R <25>

AUDIO_AVDD_ON<34>

HP_OUT_R <25>

ICH_AC_BITCLK<20>

ICH_AC_SDIN0<20>

CBS_SPK<30>

BEEP<33>

SPKR<21>

SP_DIF <18>

HP_OUT_L <25>

AUD_MONO_OUT <50>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

24 54Tuesday, March 18, 2003

Compal Electronics, Inc.

AC97 Codec

PACKAGE : 8X4.5X1.5mm

W=30 mil

VDDA=4.75V

4

1

5

single gate TTL

23

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C578

0.1U_0402_16V4Z~D

1

2

C565

1000P_0402_50V7K~D

1

2

R499 0_0402_5%~D@

1 2

C200

0.1U_0402_16V4Z~D

1 2

C158

0.1U_0402_16V4Z~D

1

2

C212

0.1U_0402_16V4Z~D

1

2

C224

0.1U_0402_16V4Z~D

1

2

C192

0.1U_0402_16V4Z~D

1 2

C201

0.22U_0603_10V7M~D

1 2

R525

33_0402_5%~D

1 2

C575 1000P_0402_50V7K~D

1 2

R526

47_0402_5%~D

1 2

C183

22P_0402_50V8J~D

1 2

C573

0.1U_0402_16V4Z~D

1

2

C190

1000P_0402_50V7K~D

@

1

2

C579

27P_0603_50V8J~D@

1

2

C168

22P_0402_50V8J~D

1 2

U21

SN74AHCT1G86DCKR_SC70-5~D

A

1

B

2Y4

P5

G

3

R531

33_0402_5%~D

1 2

R498 0_0402_5%~D@

1 2

C162

1U_0805_10V6K~D

1 2

C197 1U_0805_10V6K~D

1 2

C576

0.1U_0402_16V4Z~D

1

2

C195 1U_0805_10V6K~D

1 2

C171 1000P_0402_50V7K~D

1 2

U22

TPS793475DBVR_SOT23-5~D

OUT 5

BYPASS 4

GND

2

EN

3

IN

1

X2

24.576 MHz_20P_1BX24576CC1A~D

1 2

C176

0.1U_0603_16V7K~D

@

1 2

C196 1U_0805_10V6K~D

1 2

R512

10K_0402_5%~D

12

C215

0.1U_0402_16V4Z~D

1

2

C186

2.2U_0805_16VFZ~D

1

2

R534

33_0402_5%~D

1 2

C580

0.1U_0402_16V4Z~D

1

2

C209

0.01U_0402_16V7K~D

1

2

C161

2.2U_0805_16VFZ~D

1

2

C571

27P_0603_50V8J~D@

1

2

L23

BLM11A121S_0603~D

1 2

C570

22P_0402_50V8J~D

@

1

2

C216

2.2U_0805_16VFZ~D

1

2

C198

1U_0805_10V6K~D

1

2

L16

BLM31A260SPT_1206~D

1 2

R237

43K_0402_5%~D

1 2

U12

SN74AHCT1G125DCKR_SC70-5~D

A

2Y4

P5

G

3

OE# 1

R221

8.2K_0402_5%~D

12

STAC9750

U16

STAC9750_TQFP48~D

PC_BEEP 12

PHONE 13

AUX_L 14

AUX_R 15

VIDEO_L 16

VIDEO_R 17

CD_L 18

CD_C 19

CD_R 20

MIC1 21

MIC2 22

LINE_IN_L 23

LINE_IN_R 24

SDATA_OUT

5

BIT_CLK

6

SDATA_IN

8

SYNC

10 RESET#

11

XTL_IN

2

XTL_OUT

3

LOUT_L 35

LOUT_R 36

MONO_OUT 37

CID0

45 CID1

46

GPIO0/NC

43

GPIO1/NC

44

HP_OUT_L 39

HP_COMM 40

HP_OUT_R 41

EAPD

47

NC/FLTOUT

34

NC/FLTIN

33

CAP2

32

NC/BPCFG

31

AFLT2

30

AFLT1

29

VREFOUT

28

VREF

27

DVDD1 1

DVDD2 9

AVDD1 25

AVDD2 38

DVSS1

4

DVSS2

7

AVSS1

26

AVSS2

42

SPDIF

48

C199

0.1U_0402_16V4Z~D

1 2

C170

0.1U_0402_16V4Z~D

1

2

C559

0.1U_0402_16V4Z~D

1

2

R223

20K_0402_5%

1 2

C208

0.1U_0402_16V4Z~D

1

2

U20

SN74AHCT1G86DCKR_SC70-5~D

A

1

B

2Y4

P5

G

3

C569

1000P_0402_50V7K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

INT_SPK_R1

INT_SPK_L1

INT_SPK_R1

HP_NB_SENSE

INT_SPK_L2

INT_SPK_R2

INT_SPK_R2

SPK_SHUTDOWN#

C_INT_MIC+

R_INT_MIC-

R_INT_MIC+

C_INT_MIC-

EXT_MIC_PLUG

EXT_MIC_BIAS

C_EXT_MIC+

INT_MIC+

AMPVCC

INT_MIC-

EMICIN

EXT_MIC_PLUG

EXT_MIC_BIAS

EMICIN

AUD_LINE_IN_R

AUD_LINE_IN_L

AUD_LINE_OUT_R

AUD_LINE_OUT_L

HP_OUT_R

HP_OUT_L

INT_SPK_L2

INT_SPK_L1

AUD_LINE_OUT_L

AUD_LINE_OUT_R

AUD_GAIN0

AUD_GAIN1

INT_SPK_R1

INT_SPK_R2

INT_SPK_L1

INT_SPK_L2

AUD_GAIN0

AUD_GAIN1

BYPASS

INT_SPK_L2

INT_TWT_L1

INT_SPK_R2

INT_TWT_R1

HP_OUT_L

HP_NB_SENSE

HP_OUT_R

HP_NB_SENSE

INT_SPK_R1

INT_SPK_L1

AMPVCC

SPK_SHUTDOWN#<24,50>

AUD_LINE_OUT_L<24>

AUD_LINE_OUT_R<24>

+3VRUN

VDDA

VDDA +3VALW +3VRUN

+5VRUN

+5VRUN

+5VRUN

NB_MUTE<33>

SPK_SHUTDOWN#<24,50>

EAPD<24>

NB_MICIN <24>

INT_MIC-<38>

INT_MIC+<38>

HP_OUT_R <24>

HP_OUT_L <24>

FAN1_VOUT<14> FAN1_TACH_FB <14>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

25 54Tuesday, March 18, 2003

Compal Electronics, Inc.

AMP and Phone Jack Interface

TRACE>15 mil

60mil single end connection near JACK

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

GAIN0 GAIN1 AV(inv) INPUT

0

1

6dB

15.6dB

21.6dB

IMPEDANCE

90K ohm

70K ohm

45K ohm

25K ohm

10dB0

0

0

11

1

*

Gain Setting

W=40mils

Link CIS

20.7

Link CIS

20.7

W=15mils

C628

10U_1206_10V4Z~D

1

2

C547

1U_0603_10V6K~D

1

2

C626

0.1U_0402_16V4Z~D

1

2

R503

100K_0402_5%~D

1 2

R497

1K_0402_5%~D

1 2

L48

BLM21A05_0805

1 2

C157

2.2U_0805_16VFZ~D

1

2

G

D

S

Q40

2N7002_SOT23~D

2

13

C165

1U_0805_10V6K~D

1

2

L46

BLM11A121S_0603~D

1 2

R505

1K_0402_5%~D

1 2

C630

0.47U_0603_16V4Z

1 2

R197

100K_0402_5%~D

1 2

D8DDA204U@

1

3

2

C545

0.1U_0402_16V4Z~D

1

2

C627

0.1U_0402_16V4Z~D

1

2

R584

10K_0402_5%~D @

12

C631

0.1U_0402_16V4Z~D

1 2

C561

0.1U_0402_16V4Z~D

1 2

C169

1U_0805_10V6K~D

1

2

C629

0.1U_0402_16V4Z~D

1

2

C632

0.47U_0603_16V4Z

1 2

D9DDA204U@

1

3

2

C635

0.1U_0402_16V4Z~D

@

1

2

C535

1U_0603_10V6K~D

1 2

R582

10K_0402_5%~D

12

R511

1K_0402_5%~D

1 2

C633

0.1U_0402_16V4Z~D

1 2

G

D

S

Q38

2N7002_SOT23~D

2

13

C529

1U_0603_10V6K~D

1

2

C179

0.1U_0402_16V4Z~D

1 2

C639

22U_1206_16V4Z_V1

1 2

U18

TI6017A2_TSSOP20

GND4

1GND3

11 GND2

13 GND1

20

VDD 16

PVDD1 15

RIN-

17

BYPASS 10

NC 12

LOUT- 8

LOUT+ 4

ROUT- 14

ROUT+ 18

RIN+

7

LIN-

5

LIN+

9

GAIN0 2

GAIN1 3

PVDD2 6

SHUTDOWN

19

C634

0.47U_0603_16V4Z

1

2

JSPK

MOLEX_53398-0890~D

1

1

2

2

3

3

4

4

5

5

6

6

99

10

10

7

7

8

8

C537

1U_0603_10V6K~D

1

2

C539

1U_0603_10V6K~D

1 2

R583

10K_0402_5%~D@

12

C178

0.1U_0402_16V4Z~D

1 2

R459

10K_0402_5%~D

12

D6D DA204U@

1

3

2

C638

22U_1206_16V4Z_V1

1 2

U38

MAX4411ETP-T_TQFN20~D

C1P

1

PGND

2

C1N

3

NC-4 4

PVss

5

NC-6 6

SVss

7

NC-8 8

OUTL 9

SVDD 10

INR

15

SHDNR#

14

INL

13

NC-12 12

OUTR 11

NC-20 20

PVDD 19

SHDNL#

18

SGND

17

NC-16 16

U13

CMAMP110M_MSOP8~D

EXT_MIC_IN

8

GND

7

EXT_MIC_BIAS 3

MIC_SELECT 1

INT_MIC+

6

INT_MIC-

5

OUT 2

VSUP 4

D7DDA204U@

1

3

2

G

D

S

Q39

2N7002_SOT23~D

2

13

JAUDO

NAIS_AXN320C038P~D

1

3

5

7

9

2

4

6

8

10

11

13

15

17

19

12

14

16

18

20

R517

1K_0402_5%~D

1 2

R585

10K_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USBP3_D-

USBP0_D+

USBP3_D-

USBP4_D-

USBP1_D-

USBP1_D+ USBP2_D+

USBP0_D-

USBP0_D+

USBP3_D+

USBP0_VCC

USBP2_D+

DH_SMBCLK

USBP3_D+

USBP2_VCC

DH_SMBCLK

DH_SMBDAT

DH_PORT_PWRSRC

CLK_SMB

USBP0_D-

DH_SMBDAT

DH_PORT_PWRSRC

Z2502

DAT_SMB

USBP4_D+

USBP2_D-

USBP2_GND

DH_PWRSRC_OC

USBP2_D-

USBP0_GND

DH_PWR_OC#

DH_F USE_PWRSRC

USBP3_VCC

USBP3_GND

USBP6_D+

Z2501

DH_PWRSRC

USBP6_VCC

USBP6_D-

USBP6_D+

DH_POWER_EN#

DH _POWER_EN

USBP6_GND

USBP6_D-

USBP0_PWR

USBP2_PWR

USBP0_PWR

USBP2_PWR

+3VRUN

PWR_SRC

USBP3_PWR

USBP6_PWR

USBP6_PWR

USBP3_PWR

+5VSUS

+5VSUS

+5VSUS

+5VSUS

USBP2-<20>

USB_OC0# <20>

DAT_SMB<19,34,35,47>

USBP4_D+ <23>

USB_OC2# <20>

USBP3+<20>

USBP3-<20>

DH_PWRSRC_OC <33>

USBP1-<20>

DH_POWER_EN <33>

USBP1+<20>

USBP4-<20>

USBP1_D+ <27>

CLK_SMB<19,34,35,47>

USBP4+<20>

USBP1_D- <27>

USBP4_D- <23>

USBP0+<20>

USBP2+<20>

USBP0-<20>

USBP6+<20>

USBP6-<20>

USB_OC6# <20>

USB_OC3# <20>

USB_EN#<33>

DH_MOD_PRES#<34>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

26 54Tuesday, March 18, 2003

Compal Electronics, Inc.

USB(2.0) Connector

2

BT

3DOG

BACK

1

5

PLACE CHOKE(Resistors)

NEAR CONNECTOR

BACK

MOD

USB PORT#

0

DESTINATION

6BACK

Follow LK2 and need confirm final SPEC

4

7

Reserved

Reserved

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Please link CIS

9.1

C259

0.1U_0402_16V4Z~D

1

2

G

D

S

Q4

2N7002_SOT23~D

2

13

L25

BLM21PG600SN1D_0805~D

1 2

R317

100K_0402_5%~D

12

JUSB1

SUYIN_2569A-04G3T

1

2

3

4

R10 0_0402_5%~D@

1 2

L5

BLM21PG600SN1D_0805~D

1 2

L44

DLW21SN900SQ2_0805~D

1

1

4

433

22

R316

10K_0402_5%~D

12

U31

TPS2042ADR_SO8~D

GND

1

IN

2

OC2# 5

OUT2 6

OC1# 8

EN1#

3

EN2#

4

OUT1 7

C5

47P_0402_50V8J@C647P_0402_50V8J@

L29

BLM21PG600SN1D_0805~D

1 2

C260

0.1U_0402_16V4Z~D

1

2

C9

0.1U_0805_50V7M~D

1

2

C3

47P_0402_50V8J@

R407 0_0402_5%~D@

1 2

C257

0.1U_0402_16V4Z~D

1

2

F1

1.8A_33VDC_SMD185~D

1 2

R8 0_0402_5%~D@

1 2

R408 0_0402_5%~D@

1 2

L28

BLM21PG600SN1D_0805~D

1 2

L26

BLM21PG600SN1D_0805~D

1 2

R6 0_0402_5%~D@

1 2

G

D

S

Q64

2N7002_SOT23~D

2

13

C7

47P_0402_50V8J@

R318

100K_0402_5%~D

1 2

G

D

S

Q6

2N7002_SOT23~D

2

1 3

G

D

S

Q1

2N7002_SOT23~D

2

13

L24

BLM21PG600SN1D_0805~D

1 2

G

D

S

Q9

2N7002_SOT23~D

2

13

F2

RAY_RUE250@

+

C265

150U_D_10VM_R55~D

1

2

R566 0_0402_5%~D@

1 2

JDOG

Fox_UB11193-P01-TR~D

T1

1

T2

2

T3

3

T4

4

PWR_SRC

5

SMB_DATA

6

SMB_ALERT

7

SMB_CLK

8

GND

9

SHILD1

10

SHILD2

11

SHILD3

12

SHILD4

13

L3

DLW21SN900SQ2_0805~D

1

1

4

433

22

R17

10K_0402_5%~D

1 2

R11 0_0402_5%~D@

1 2

L47

DLW21SN900SQ2_0805~D

1

1

4

433

22

R307

100K_0402_5%~D

12

L2

DLW21SN900SQ2_0805~D

1

1

4

433

22

L4

DLW21SN900SQ2_0805~D

1

1

4

433

22

Q66

FDS4435_SO8~D

4

7

8

6

5

1

2

3

R5 0_0402_5%~D@

1 2

G

D

S

Q2

2N7002_SOT23~D

2

1 3

R565 0_0402_5%~D@

1 2

U32

TPS2042ADR_SO8~D

GND

1

IN

2

OC2# 5

OUT2 6

OC1# 8

EN1#

3

EN2#

4

OUT1 7

+

C261

150U_D_10VM_R55~D

1

2

+

C263

150U_D_10VM_R55~D

1

2

C268

0.1U_0402_16V4Z~D

1

2

C269

0.1U_0402_16V4Z~D

1

2

C147P_0402_50V8J@

JUSB3

SUYIN_2569A-04G3T

1

2

3

4

L1

DLW21SN900SQ2_0805~D

1

1

4

433

22

C611

47P_0402_50V8J@

JUSB2

SUYIN_2569A-04G3T

1

2

3

4

L30

BLM21PG600SN1D_0805~D

1 2

R306

100K_0402_5%~D

1 2

+

C262

150U_D_10VM_R55~D

1

2

C462

47P_0402_50V8J@

C8

47P_0402_50V8J@

C461

47P_0402_50V8J@

R9 0_0402_5%~D@

1 2

C258

0.1U_0402_16V4Z~D

1

2

C292

0.022U_0603_50V4Z~D

1

2

C610

47P_0402_50V8J@

L27

BLM21PG600SN1D_0805~D

1 2

R27

10K_0402_5%~D

1 2

C2

47P_0402_50V8J@

R7 0_0402_5%~D@

1 2

C447P_0402_50V8J@

L31

BLM21PG600SN1D_0805~D

1 2

R12 0_0402_5%~D@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Z2604

MDC_SDIN

MDC_AC_BITCLK_TERM

Z2602

ICH_AC_SDOUT_MDCTERM

COEX1_BT_ACTIVE

USBP1_D-

USBP1_D+

COEX3

BT_PWR

HW_RADIO_DIS#

COEX2_WLAN_ACTIVE

+3VSUS

+3VSUS

+3VSUS

ICH_AC_SDOUT <20,24>

MDC_AC_BITCLK<24>

ICH_AC_SYNC<20,24>

ICH_AC_RST# <20,24>

BT_ACTIVE<38>

USBP1_D+<26> USBP1_D-<26>

HW_RADIO_DIS#<32,34>

COEX1_BT_ACTIVE<32>

COEX2_WLAN_ACTIVE<32>

ICH_AC_SDIN1<20>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

27 54Tuesday, March 18, 2003

Compal Electronics, Inc.

BT PORT and MDC

W=20 mil

1

10

FOX_HS6210_10P

TOP view

7/28 Changed to NP

by Dell's require

MDM_MONO_PHONE

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Link CIS

12.2

L43

BLM11A601S_0603~D

12

C525

0.1U_0402_16V4Z~D

1

2

JBT

JST_SM10B-SRSS-TB~D

1

2

3

4

5

6

7

8

9

10

11

12

JMDC

AMP_3-1612118-0~D

MONO_OUT/PC_BEEP 1

AGND 3

AUXA_RIGHT 5

AUXA_LEFT 7

CD_GND 9

CD_RIGHT 11

CD_LEFT 13

GND 15

AC97_SDATA_OUT 23

3.3Vmain 21

3.3Vaux 17

GND 19

AC97_RESET# 25

GND 27

AC97_MSTRCLK 29

AUDIO_PWDN

2

MONO_PHONE

4

RESERVED

6

GND

8

+5V

10

RESERVED

12

RESERVED

14

PRIMARY_DN

16

RESERVED

18

RESERVED

20

AC97_SYNC

22

AC97_SDATA_IN1

24

AC97_SDATA_IN0

26

GND

28

AC97_BITCLK

30

R457

33_0402_5%~D

1 2

C459

0.1U_0402_16V4Z~D

1

2

R412

10K_0402_5%~D@12

R454

10K_0402_5%~D@

12

C527

22P_0402_50V8J~D

@

1

2

R462

10_0402_5%~D@

1 2

R458

10_0402_5%~D@

1 2

R449

10K_0402_5%~D

1 2

C530

10P_0402_50V8J~D

@

1

2

C526

10P_0402_50V8J~D

@

1

2

C159

4.7U_1206_16V6K~D

1

2

T2

PAD

@

R463

0_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_C_BE1#

PCI_REQ4#

LAN_GPIO0

PCI_AD17

PCI_STOP#

PCI_AD29

PCI_C_BE0#

LAN_GPIO2

PCI_AD26

PCI_TRDY# LAN_TRST#

V_1P2_PLLVDD_PHY

XTALI

PCI_AD7

LAN_CTRL_1P2V

LAN_SMBCLK

SYS_PME#

PCI_AD27

LAN_CTRL_1P2V

PCI_AD21

PCIRST_1#

LAN_CTRL_2P5V

PCI_AD25

PCI_AD13

LAN_EEDATA_SPROM_CS

LAN_ACT#

PCI_AD10

LAN_EEPROM_W

PCI_PAR

V_1P2_PLLVDD_PHY

PCI_SERR#

LAN_CTRL_2P5V

PCI_AD1

PCI_AD3

PCI_C_BE2#

CK_33M_LANPCI

PCI_C_BE3#

PCI_FRAME#

PCI_AD20

PCI_IRDY#

PCI_AD12

PCI_AD0

LAN_AUXPWR

LAN_SMBDATA

PCI_PERR#

LAN_TX3+

PCI_AD16

LINK_LED_10#

PCI_AD18

PCI_GNT4#

LAN_EEDATA_SPROM_CS

PCI_PIRQC#

LAN_BIAS

PCI_AD30

PCI_AD4

LAN_TX3-

LAN_EECLK_SPROM_CLK

LAN_TX2-

CLK_82540_TERM

PCI_AD9

PCI_AD31

PCI_AD14

PCI_AD22

PCI_AD15

PCI_AD11

CK_33M_LANPCI

PCI_AD28

PCI_AD19

PCI_AD16

PCI_AD5

LAN_EECLK_SPROM_CLK

LAN_TX2+

PCI_AD8

PCI_DEVSEL#

LINK_LED_100#

LAN_RDAC

PCI_AD24

PCI_AD23

VAUX_LAN

PCI_AD6

PCI_AD2

LAN_EEPROM_W

LAN_TX0-

LAN_TX0+

LAN_RX1+

LAN_RX1-

AVDD1P2

LAN_IDSEL

XTALO

5705M_LOWPWR

AVDD2P5

5705M_CLKRUN#

LAN_EEDATA_SPROM_CS

LAN_EECLK_SPROM_CLK

LAN_SPROM_DOUT

LAN_SPROM_DIN

LAN_SPROM_DOUT

LAN_SPROM_DIN

LINK_LED_1000#

LAN_SMBDATA

LAN_SMBCLK

V_2P5_LAN

V_2P5_LAN

V_3P3_LAN

V_2P5_LAN

V_1P2_LAN

V_3P3_LAN

V_3P3_LAN

V_3P3_LAN

V_2P5_LAN

V_1P2_LAN

+3VRUN

V_1P2_LAN

V_1P2_LAN

V_3P3_LAN

V_2P5_LAN

V_2P5_LAN

V_2P5_LAN

V_2P5_LAN

V_1P2_LAN

+3VSRC

V_3P3_LAN

+3V_LOM_PCI

V_3P3_LAN +3VRUN

+3V_LOM_PCI V_3P3_LAN

PCI_IRDY#<20,30,32>

LAN_TX2+ <29>

PCI_C_BE1#<20,30,32>

PCI_SERR#<20,30,32>

PCI_TRDY#<20,30,32>

CK_33M_LANPCI<6>

PCI_AD[0..31]<20,30,32>

SYS_PME#<30,32,33>

LAN_ACT# <29>

PCI_GNT4#<20>

LINK_LED_10# <29>

PCI_REQ4#<20>

PCI_DEVSEL#<20,30,32>

PCI_FRAME#<20,30,32>

PCI_C_BE3#<20,30,32> PCI_C_BE2#<20,30,32>

ENAB_3VLAN<39>

PCI_PERR#<20,30,32>

LINK_LED_100# <29>

PCI_C_BE0#<20,30,32>

LAN_TX3- <29>

LAN_TX2- <29>

LAN_TX3+ <29>

PCI_PAR<20,30,32>

PCIRST_1#<20> PCI_PIRQC#<20,30>

PCI_STOP#<20,30,32>

LAN_TX0- <29>

LAN_TX0+ <29>

LAN_RX1- <29>

LAN_RX1+ <29>

LAN_LOW_PWR <34>

LINK_LED_1000# <29>

LAN_SMBDATA <32>

LAN_SMBCLK <32>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

28 54

Tuesday, March 18, 2003

Compal Electronics, Inc.

ETHERNET

2

BCP69

4

C

1

E

3

C

B

R548 is poped for 4401 with AT93C86 (16KB)

R548 is poped for 5705M EEPROM 376KHz mode

2@ BCM4401

2@ BCM4401

Signal 4401 5705M

LAN_EECLK_SPROM_CLK

LAN_EEDATA_SPROM_CS

No pullup for 16KB

Pullup for 16KB

Pullup for 376KHz mode

No pullup

1@ : Nopop Nimitz 4401

2@ : Nopop Bejing 5705M

Place within 100 mils to pins N10 and N11

Place within 100 mils to pins H14

20mils trace width

Place within 50 mils of

ASIC pin D10

8-10mils trace width

Place within 100 mils of ASIC

pin A14, 10mils trace width

Place within 100 mils of ASIC

pins, 10-20mils trace width

OR

BCM4401 OR

BCM4401

POP

5705

POP

4401

Should be pulled down for both 4401 and 5705M

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R302

10K_0402_5%~D@ 12

C349

10U_1206_6.3V7K~D

1

2

BCM5705M

U2A

BCM5705M_FBGA196~D1@

AD31

B8

AD30

A8

AD29

C7

AD28

C6

AD27

B6

AD26

B5

AD25

A5

AD24

B4

AD23

B2

AD22

B1

AD21

C1

AD20

D3

AD19

D2

AD18

D1

AD17

E3

AD16

K1

AD15

L2

AD14

L1

AD13

M3

AD12

M2

AD11

M1

AD10

N2

AD9

N3

AD8

P3

AD7

N4

AD6

P4

AD5

M5

AD4

N5

AD3

P5

AD2

P6

AD1

M7

AD0

N7

CBE3

C4

CBE2

F3

CBE1

L3

CBE0

M4

IDSEL

A4

FRAME

F2

IRDY

F1

TRDY

G3

DEVSEL

H3

STOP

H1

PERR

J2

SERR

A2

PAR

J1

PCI_CLK

A3

INTA

H2

PCI_RST

C2

GNT

J3

REQ

C3

VAUXPRSNT

J12

M66EN

F4

PME

A6

TRD3+ E13

TRD3- E14

TRD2+ D13

TRD2- D14

TRD1+ C13

TRD1- C14

TRD0+ B13

TRD0- B14

REGSUP12 B9

REGCTL12 B10

REGSEN12 A9

REGSUP25 B11

REGCTL25 C11

REGSEN25 C10

VESD1 P1

VESD2 G2

VESD3 A1

EEDATA P10

EECLK M10

GPIO1 K13

GPIO2 J13

LINKLEDB G13

SPD100LEDB H13

SPD1000LEDB G12

TRAFFICLEDB G14

PLLVDD2 H14

NC P7

TCK C12

TDI D12

TDO B12

TMS A12

TRST D11

XTALVDD J14

XTALO N10

XTALI N11

SO G11

SI E10

SCLK E11

CS H11

BIASVDD A14

RDAC D10

SMB_CLK A10

SMB_DATA C9

GPIO0 H12

C326

0.1U_0402_16V4Z~D

1

2

C277

0.1U_0402_16V4Z~D1@

1

2

R310

4.7K_0402_1%~D 12

R296

1K_0402_5%~D 1@

12

C283

0.1U_0402_16V4Z~D

1

2

Q65

BCP69_SOT-2231@

3

1

2

4

R313 0_0402_5%~D 2@

1 2

C311

0.01U_0402_16V7K~D 2@

1

2

L6

BLM11A601S_0603~D

1@

1 2

C310

0.1U_0402_16V4Z~D

1

2

C335

0.1U_0402_16V4Z~D

1

2

L38

BLM11A601S_0603~D 1@

1 2

C18

22P_0402_50V8J~D 1

2

L39

BLM11A601S_0603~D2@

1 2

L35

BLM11A601S_0603~D

1 2

C278

0.1U_0402_16V4Z~D

1

2

R319

10_0402_5%~D@

12

C340

0.1U_0402_16V4Z~D

1

2

C323

0.1U_0402_16V4Z~D

1

2

R312

10K_0402_5%~D2@

12

C309

0.1U_0402_16V4Z~D

1

2

BCM5705M

U2B

BCM5705M_FBGA196~D1@

VDDC_E12

E12

VDDC_H8

H8

VDDC_J5

J5

VDDC_J6

J6

VDDC_J7

J7

VDDC_J8

J8

VDDC_J9

J9

VDDC_J10

J10

VDDC_K5

K5

VDDC_K6

K6

VDDC_K7

K7

VDDC_K8

K8

VDDC_N14

N14

VDDC_P8

P8

VDDC_P12

P12

VDDC_P13

P13

VDDC_P14

P14

VDDIO-PCI_A7

A7

VDDIO-PCI_B3

B3

VDDIO-PCI_C5

C5

VDDIO-PCI_E1

E1

VDDIO-PCI_E4

E4

VDDIO-PCI_G1

G1

VDDIO-PCI_K3

K3

VDDIO-PCI_L4

L4

VDDIO-PCI_N6

N6

VDDIO-PCI_P2

P2

VDDP_K14

K14

VDDP_L13

L13

VDDP_P11

P11

NC_J11

J11

NC_K11

K11

NC_L7

L7

NC_L8

L8

VSS_D7 D7

VSS_D8 D8

VSS_D9 D9

VSS_E2 E2

VSS_E5 E5

VSS_E6 E6

VSS_E7 E7

VSS_E8 E8

VSS_E9 E9

VSS_F5 F5

VSS_F6 F6

VSS_F7 F7

VSS_F8 F8

VSS_F9 F9

VSS_F10 F10

VSS_G4 G4

VSS_G5 G5

VSS_G6 G6

VSS_G7 G7

VSS_G8 G8

VSS_G9 G9

VSS_G10 G10

VSS_H9 H9

VSS_K2 K2

VSS_L6 L6

VSS_L9 L9

VSS_M6 M6

VSS_M12 M12

VSS_M13 M13

VSS_N1 N1

VSS_N12 N12

VSS_N13 N13

AVDDL_F12 F12

AVDDL_F13 F13

AVDD_F14 F14

NC_L11 L11

NC_L14 L14

NC_M8 M8

VDDC_H7

H7 VDDC_H6

H6 VDDC_H5

H5

VDDC_K9

K9

VDDC_K10

K10

VDDC_L5

L5

VDDC_L10

L10

VDDC_M14

M14

VSS_D6 D6

VSS_D5 D5

VSS_D4 D4

VSS_B7 B7

AVDD_A13 A13

NC_M9 M9

LOW_POWER M11

NC_N8 N8

NC_N9 N9

NC_P9 P9

NC_H10

H10

NC_J4

J4

NC_K4

K4

VDDIO_A11

A11

VDDIO_F11

F11

VDDIO_K12

K12

VDDIO_L12

L12

CLKRUN

H4 CSTSCHG

C8

C321

8.2P_0402_50V8J~D@

1 2

C25

10U_1206_6.3V7K~D

1

2

C11

2.2U_0805_16VFZ~D

1

2

C291

0.1U_0402_16V4Z~D

1

2

C20

0.1U_0402_16V4Z~D1@

1

2

C330

0.1U_0402_16V4Z~D

1

2

C279

0.1U_0402_16V4Z~D

1

2

C332

10U_1206_6.3V7K~D

1

2

U34

AT93C86-10SC-2.7_SOIC8~D 2@

CS

1

SK

2

DI

3

DO

4

VCC 8

NC 7

ORG 6

GND 5

R299

4.7K_0402_5%~D

12

C282

0.1U_0402_16V4Z~D

1

2

L33

BLM11A601S_0603~D

1 2

C341

0.1U_0402_16V4Z~D

1

2

C320

0.1U_0402_16V4Z~D

1

2

C17

0.1U_0402_16V4Z~D

1

2

C312

0.1U_0402_16V4Z~D

1

2

C318

0.1U_0402_16V4Z~D

1

2

S

GD

Q18

SI3456DV-T1_TSOP6~D

3

6

245

1

R321

10K_0402_5%~D

1 2

C314

0.1U_0402_16V4Z~D

1

2

T7 PAD@

L37

BLM31A260SPT_1206~D

1 2

R300 0_0603_5%~D1@

1 2

C275

0.1U_0402_16V4Z~D

1

2

C350

10U_1206_6.3V7K~D

1

2

U33

AT24C256N-10SC_SO81@

A0 1

A1 2

NC 3

GND 4

VCC

8

WP

7

SCL

6

SDA

5

C307

0.1U_0402_16V4Z~D

1

2

L36

BLM11A601S_0603~D

1 2

R303

1K_0402_5%~D

12

X1

25MHz_20P_1BX25000CK1A~D

12

C316

0.1U_0402_16V4Z~D

1

2

R308 0_0402_5%~D2@

1 2

C273

1U_0805_10V6K~D

1

2

C293

0.1U_0402_16V4Z~D

1

2

C344

10U_1206_6.3V7K~D

1

2

C315

0.1U_0402_16V4Z~D

1

2

C285

0.1U_0402_16V4Z~D

1

2

C266

10U_1206_6.3V7K~D

1

2

C281

0.1U_0402_16V4Z~D

1

2

C333

10U_1206_6.3V7K~D

1

2

C313

0.1U_0402_16V4Z~D

1

2

C274

0.1U_0402_16V4Z~D

1

2

C286

0.1U_0402_16V4Z~D

1

2

C34

22P_0402_50V8J~D

1

2

R311

1.24K_0402_1%~D

12

C270

0.1U_0402_16V4Z~D

1

2

C306

0.1U_0402_16V4Z~D

1

2

Q5

BCP69_SOT-2231@

3

1

2

4

C328

0.1U_0402_16V4Z~D

1

2

C271

1000P_0402_50V7K~D

1

2

C343

10U_1206_6.3V7K~D

1

2

C272

0.1U_0402_16V4Z~D

1

2

T8 PAD@

R49

100_0603_5%~D

1 2

C267

10U_1206_6.3V7K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LAN_TX2-

LAN_TX2+

NB_LAN_TX3+

NB_LAN_RX+

LAN_TX0+

Z2807

NB_LAN_TX2-

Z2805

NB_LAN_TX-

Z2806

NB_LAN_TX2-

NB_LAN_TX3+

Z2808

NB_LAN_TX3-

LAN_TX3-

NB_LAN_RX-

NB_LAN_TX2+

NB_LAN_TX3-

NB_LAN_TX2+

NB_LAN_TX+

LAN_ACTLED_YEL#

LED_100_ORG#

LAN_RX1+

LAN_RX1-

LED_10_GRN#

RJ_TIP

LAN_ACTLED_YEL#

RJ_RING

NB_LAN_RX+

NB_LAN_RX-

NB_LAN_TX-

NB_LAN_TX2+

NB_LAN_TX3+

NB_LAN_TX3-

NB_LAN_TX+

LAN_TX3-

LAN_TX3+

LAN_TX2-

LAN_RX1+

LAN_TX0+

LAN_TX0-

LAN_RX1-

NB_LAN_TX2-

LED_100_ORG#

LAN_TX3+

LED_10_GRN#

LAN_TX0-

RJ_RING

RJ_TIP

LAN_TX2+

V_2P5_LAN

V_3P3_LAN

V_3P3_LAN

V_3P3_LAN

V_3P3_LAN

V_3P3_LAN

V_3P3_LAN

V_2P5_LAN

V_3P3_LAN

LINK_LED_10#<28>

LAN_ACT#<28>

WLAN_LED_ACTIVITY<32>

LINK_LED_100#<28>

LED_WLAN24_RADIOSTATE<32>

LED_WLAN5_RADIOSTATE<32>

LAN_TX3+<28>

LAN_TX2+<28>

LAN_TX0+<28>

LAN_RX1-<28>

LAN_RX1+<28>

LAN_TX3-<28>

LAN_TX2-<28>

LINK_LED_1000# <28>

LAN_TX0-<28>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

29 54Tuesday, March 18, 2003

Compal Electronics, Inc.

LAN TRANSFOMER

DTC144EKA

C

GND

CHASIS

EB

1

23

Magnetics pop options

4401: H1238

5705M: H5015D

2@ H1238

1@ : Nopop Nimitz 4401

2@ : Nopop Bejing 5705M

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C15

0.01U_0402_16V7K~D

1

2

R19 49.9_0603_1%~D

1 2

R600

10K_0402_5%~D

12

R2 0_0402_5%~D2@

12

RJ45/LED

RJ11

JLOM

FOX_JM34F23-P3552-TR~D

B1

B1

P1_1

1

P1_2

2

P1_3

3

P1_4

4

P1_5

5

P1_6

6

P1_7

7

P1_8

8

SGND2 18

P2_2

10

P2_1

9

YEL B3

B2

B2

GRN A3

A2

A2

SGND1 17

AMBER A1

R21 49.9_0603_1%~D

1 2

R24 49.9_0603_1%~D 1@

1 2

R297

10K_0402_5%~D

12

JPH_RJ

JST_SM05B-SRSS-TB~D

1

1

2

2

5

5

66

77

R33

10K_0402_5%~D

12

R4 0_0402_5%~D2@

12

47K

47K

Q62

DTC144EKA_SOT23~D

2

13

C264

1000P_1808_3KV7K~D

1 2

R293

10K_0402_5%~D

12

D11

RB495D_SOT23~D

2

31

1:1

T1

1:1

T5

T2 T6

T3 T7

1:1

T4 T8

1:1

L32

H5015D~D1@

1

2

3

4

5

6

7

8

9

10

11

12 13

14

15

16

17

18

19

20

21

22

23

24

R295

10K_0402_5%~D

1 2

R20 49.9_0603_1%~D

1 2

C13

0.01U_0402_16V7K~D

1

2

R23 49.9_0603_1%~D1@

1 2

R1 0_0402_5%~D2@

12

47K

47K

Q63

DTC144EKA_SOT23~D

2

13

D12

RB495D_SOT23~D

1@

2

3

1

G

D

S

Q3

2N7002_SOT23~D

2

13

R304

10K_0402_5%~D

1 2

R309

10K_0402_5%~D

12

R26 49.9_0603_1%~D1@

1 2

R601

10K_0402_5%~D

12

R3 0_0402_5%~D2@

12

D10

RB495D_SOT23~D

2

31

RN6

75_1206_8P4R_5%~D

1 8

2 7

3 6

4 5

R292

200_0603_5%~D

1 2

R602

10K_0402_5%~D

12

R32

200_0603_5%~D

1 2

R305

10K_0402_5%~D1@

1 2

C14

0.01U_0402_16V7K~D

1@

1

2

C16

0.01U_0402_16V7K~D

1@

1

2

R25 49.9_0603_1%~D1@

1 2

R294

10K_0402_5%~D

12

R22 49.9_0603_1%~D

1 2

R298

200_0603_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IEEE1394_TPBIAS0

CBS_CAD30

PCI_AD23

PCI_AD2

PCI_AD15

CBS_CAD9

CBS_GRST# IRQ_SERIRQ

CBS_CC/BE0#

SCR_IF_PWR

CBS_PC2

PCI_AD14

PCI_AD5

CBS_CCD2#_INTERNAL

PCI_AD17

CBS_CSERR#

CBS_CAD19

IEEE1394_TPB0P

PCI4510_R0

CBS_CRST#

IEEE1394_TPA0N

CBS_CAD10

CK33M_CBS_TERM

CBS_SDA

CBS_CAD21

CBS_CAUDIO

CBS_CAD1

SCR_IF_DATA

CBS_CAD13

CBS_CCLK_INTERNAL

PCI_AD17

SYS_PME#

CBS_CFRAME#

PCI_GNT1#

PCI_AD18

PHY_CNA

CBS_TEST1

PCI_AD21

CBS_SCL

PCI_C_BE3#

CBS_CAD25

PCI_REQ1#

CBS_CAD15

CBS_CSTOP#

SCR_IF_RST PCI4510XI

PCI_AD24

SCR_IF_GPIO2

CBS_CIRDY#

PCI_AD9

CBS_CGNT#

PCI_AD16

1V8_VR_EN#

CBS_SPK

PCI_AD12

CBS_CAD18

CBS_SCL

PCI4510_R1

CBS_SDA

CBS_CAD24

CBS_CAD28

PCI_AD13

PCI_AD28

PCI_PERR#

CBS_CAD20

CBS_CVS1

CBS_CAD6

CBS_CPERR#

PCI_SERR#

SCR_IF_GPIO0

SCR_IF_CLK

PCI_AD11

SCR_IF_GPIO5

CBS_CTRDY#

IEEE1394_TPA0P

CBS_CC/BE2#

PCI_TRDY#

PCI_C_BE1#

CBS_CAD12

SCR_IF_GPIO1

PCI_PIRQD#

PCI_C_BE2#

TI_SUSPEND#_INTERNAL

CBS_CC/BE3#

PCI_AD10

CBS_CVS2

CK_48M_SCR

PCI_PIRQC#

CBS_CSTSCHNG

PCI_AD31

PCI_AD30

CBS_CAD7

PCI_AD25

CBS_CINT#

IEEE1394_TPB1N

PCI_AD4

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_STOP#

PCI_AD29

FILTER1

CBS_CAD17

PCI_GNTB#

CBS_CBLOCK#

PCI_AD22

SCR_IF_GPIO3

CBS_CAD5

PCI4510XO

CBS_CAD26

CBS_RSVD/D14

CBS_CCD1#_INTERNAL

PCI_AD0

IEEE1394_TPA1P

PHY_TEST_MA

CBS_CREQ#

CBS_CCLK

CBS_RSVD/A18

PCI_AD7

CBS_CAD29

CBS_CAD2

PCI_IRDY#

PCI_AD27

CBS_CAD23

PCI_REQB#

CBS_RI#

PCI_AD19

PCI_AD1

IEEE1394_TPB1P

CBS_CAD3

CBS_CAD14

PCI_AD26

CBS_CAD0

SCR_DETECT

FILTER0

PCI_AD20

CBS_CAD16

PCI_AD8

CBS_CAD31

SCR_IF_GPIO4

CK48M_CBS_TERM

CBS_IDSEL

CBS_CDEVSEL#

CBS_CC/BE1#

CBS_RSVD/D2

CBS_PC0

CBS_CAD8

PCIRST_CB#

CBS_CAD22

PCI_AD3

CBS_CAD11

IEEE1394_TPBIAS1

CBS_CAD27

PCI_C_BE0#

CBS_CPAR

CBS_CCLKRUN#

IEEE1394_TPB0N

CBS_TEST0

PCI_AD6

CBS_CAD4

CBS_MFUNC6

PHY_CPS

CBS_PC1

IEEE1394_TPA1N

+3V_CBSD

CBS_VCC

+3V_CBSD

+1.8V_CBSD

+3V_CBSD

+3V_CBSD

+3V_CBSA

+3VSUS

+3V_CBSD

+3V_CBSD

+3V_CBSD

+3V_CBSA

+3V_CBSA

+3V_CBSA

+3VSUS

+3V_CBSD

+3V_CBSD

+1.8V_CBSD

SCR_IF_GPIO4<31>

CBS_CFRAME# <31>

CBS_CPAR <31>

CBS_RSVD/D2 <31>

CBS_CCD2# <31>CBS_CCLKRUN# <31>

SCR_DETECT<31>

CBS_CAD[0..31] <31>

PCI_C_BE2#<20,28,32>

CBS_CVS1 <31>

PCI_FRAME#<20,28,32>

PCI_GNTB# <20>

PCI_PAR<20,28,32>

CBS_RSVD/A18 <31>

IEEE1394_TPA0P<31>

SCR_IF_DATA<31>

CBS_CSTSCHNG <31>

CBS_CPERR# <31>

CBS_CC/BE3# <31>

PCI_GNT1#<20>

CBS_CSERR# <31>

SYS_PME# <28,32,33>

PCI_C_BE3#<20,28,32>

SCR_IF_GPIO3<31>

PCI_REQB# <20>

PCI_AD[0..31]<20,28,32>

SCR_IF_RST<31>

CBS_CGNT# <31>

CBS_CSTOP# <31>

CBS_CAUDIO <31>

CBS_CC/BE2# <31>

PCI_SERR#<20,28,32> CBS_SPK <24>

PCIRST_CB#<20>

CBS_CIRDY# <31>

SCR_IF_GPIO2<31>

CBS_RSVD/D14 <31>

CBS_VPPD0 <31>

PCI_C_BE1#<20,28,32>

CK_48M_SCR <6>

IRQ_SERIRQ <20,21,33>

IEEE1394_TPA0N<31>

CBS_CBLOCK# <31>

CBS_CCD1# <31>

PCI_PIRQD# <20,32>

IEEE1394_TPB0P<31>

CBS_GRST#<33>

PCI_STOP#<20,28,32>

SCR_IF_GPIO0<31>

CBS_CTRDY# <31>

CBS_CREQ# <31>

CBS_CC/BE1# <31>

PCI_PERR#<20,28,32> PCI_REQ1#<20>

SCR_IF_CLK<31>

CBS_RI# <21>

PCI_IRDY#<20,28,32>

IEEE1394_TPB0N<31>

CBS_VCCD0# <31>

SCR_IF_GPIO1<31>

CBS_CDEVSEL# <31>

CBS_CINT# <31>

CBS_CC/BE0# <31>

IEEE1394_TPBIAS0<31>

CBS_CCLK <31>

CBS_CRST# <31>

SCR_IF_PWR<31>

TI_SUSPEND# <34>

PCI_C_BE0#<20,28,32>

CBS_CVS2 <31>

PCI_TRDY#<20,28,32>

CBS_VPPD1 <31>

PCI_DEVSEL#<20,28,32>

CBS_VCCD1# <31>

CK_33M_CBPCI<6>

SCR_IF_GPIO5<31>

PCI_PIRQC# <20,28>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

30 54Tuesday, March 18, 2003

Compal Electronics, Inc.

PCMCIA Controller

This shall be output

8/12 Changed by

Dell's Require

8/12 Changed by

Dell's Require

Remove R756

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R515

1K_0402_5%~D@12

R452

10K_0402_5%~D@

12

R496

1K_0402_5%~D

@

12

R171

0_0402_5%~D

1 2

R188

0_0402_5%~D

1 2

L15

BLM21A601SPT_0805~D

1 2

C520

0.1U_0402_16V4Z~D

1

2

PCI7510

U9A

PCI7510GHK_PBGA209~D

AD31

J5

AD30

J6

AD29

K2

AD28

K3

AD27

K5

AD26

K6

AD25

L2

AD24

L3

AD23

M2

AD22

M3

AD21

M6

AD20

M5

AD19

N2

AD18

N3

AD17

N6

AD16

P1

AD15

R6

AD14

P7

AD13

V5

AD12

U6

AD11

V6

AD10

R7

AD9

P8

AD8

U7

AD7

W7

AD6

R8

AD5

U8

AD4

V8

AD3

W9

AD2

V9

AD1

U9

AD0

R9

C/BE3

L6

C/BE2

P2

C/BE1

U5

C/BE0

V7

PAR

W4

DEVSEL

R2

FRAME

N5

GNT

J1

IDSEL

L5

IRDY

P3

PERR

R3

REQ

J2

SERR

T1

STOP

P5

TRDY

P6

CCLK/A16 C15

CCLKRUN/WP B9

CRST/RESET B13

CRSVD/D2 F8

CRSVD/D14 J18

CRSVD/A18 F17

CAD31/D10 E8

CAD30/D9 C8

CAD29/D1 B8

CAD28/D8 E9

CAD27/D0 F9

CAD26/A0 F11

CAD25/A1 E11

CAD24/A2 C11

CAD23/A3 A12

CAD22/A4 C12

CAD21/A5 E12

CAD20/A6 C13

CAD19/A25 A14

CAD18/A7 E13

CAD17/A24 B14

CAD16/A17 F18

CAD15/IOWR# G17

CAD14/A9 F19

CAD13/IORD# G18

CAD12/A11 H15

CAD11/OE# H14

CAD10/CE2# H17

CAD9/A10 H18

CAD8/D15 J14

CAD7/D7 J17

CAD6/D13 K14

CAD5/D6 J19

CAD4/D12 K17

CAD3/D5 K15

CAD2/D11 L14

CAD1/D4 K18

CAD0/D3 L15

CC/BE3/REG# B11

CC/BE2/A12 C14

CC/BE1/A8 G15

CC/BE0/CE1# J15

CPAR/A13 F14

CAUDIO/BVD2 F10

CBLOCK/A19 E18

CCD1/CD1# L17

CCD2/CD2# C9

CDEVSEL/A21 A16

CFRAME/A23 B15

CGNT/WE# D19

CINT/READY C10

CIRDY/A15 F13

CPERR/A14 F15

CREQ/INPACK# B12

CSERR/WAIT# E10

CSTOP/A20 E17

CSTSCHG/BVD1 A9

CTRDY/A22 E14

CVS1/VS1# B10

CVS2/VS2# F12

PCICLK

H1

PCIRST

H3

GRST

H2

C524

0.047U_0402_10V4M~D

1

2

C521

0.047U_0402_10V4M~D

1

2

C172

10U_0805_10V4M~D

1

2

R516

0_0402_5%~D

1 2

C556

0.047U_0402_10V4M~D

1

2

C557

0.1U_0402_10V6K~D

1 2

C540

270P_0603_50V7K~D

@

1

2

R483

1K_0402_5%~D

12

C522

0.047U_0402_10V4M~D

1

2

X3

24.576MHz_16P_1BG24576CKIA~D

1 2

R163

10_0402_5%~D

@

1 2

C566

270P_0603_50V7K~D@

1

2

R165

220_0603_5%~D

12

C139

4.7P_0402_50V8C~D @

1

2

R453

10_0402_5%~D

@

1 2

C173

10U_0805_10V4M~D

1

2

R446

10K_0402_5%~D

12

R482

0_0402_5%~D

1 2

R495

1M_0603_5%~D@

1 2

C160

0.047U_0402_10V4M~D

1

2

R510

10K_0402_5%~D

1 2

C184

22P_0402_50V8J~D

1

2

C560

0.1U_0402_16V4Z~D

1

2

C555

0.1U_0402_16V4Z~D

1

2

C543

0.047U_0402_10V4M~D

1

2

R444

220_0603_5%~D

12

D15

RB751V_SOD323~D

2 1

R445

2.7K_0603_5%~D@

12

L13

BLM21A601SPT_0805~D

1 2

C544

0.047U_0402_10V4M~D

1

2

C542

0.047U_0402_10V4M~D

1

2

C536

0.047U_0402_10V4M~D

1

2

R494

47_0603_5%~D 12

R450 200_0603_5%~D 12

R502

1K_0402_5%~D

12

C541

0.1U_0402_16V4Z~D

1

2

C533

0.047U_0402_10V4M~D

1

2

R487

6.34K_0805_0.5%~D

1 2

C531

0.1U_0402_16V4Z~D

1

2

C538

0.1U_0402_16V4Z~D

1

2

R447 200_0603_5%~D 12

R504 4.7K_0402_5%~D 12

PCI7510

U9B

PCI7510GHK_PBGA209~D

CNA

P17

CPS

P10 VCC G1

VCC M1

VCC R1

VCC W8

VCC L19

VCC H19

VCC E19

VCC A13

VCC A8

VCC A5

VCCCB G14

VCCCB A11

VCCP L1

VCCP W5

VR_PORT G2

VR_PORT L18

VD1/VCCD0 E6

VD0/VCCD1 B5

VD3/VPPD0 A4

VD2/VPPD1 C5

GND E1

GND K1

GND N1

GND W6

GND P19

GND K19

GND G19

GND A15

GND A10

GND A7

MFUNC0 F5

MFUNC1 G6

MFUNC2 F3

MFUNC3 F2

MFUNC4 G5

MFUNC5 F1

MFUNC6 H6

RI_OUT/PME J3

SPKROUT E2

SUSPEND G3

SKT_SEL1 R10

VR_EN H5

SCL E3

SDA D1

SKT_SEL0 U10

PHY_TEST_MA P18

CLK_48 F6

RSVD

N15

RSVD

M14

RSVD

N17

RSVD

N18

SC_GPIO5

N19

RSVD

M15

SC_GPIO6

M17

SC_GPIO1

M18

SC_GPIO0

M19

SC_CD

B7

SC_RST

C7

SC_CLK

F7

SC_DATA

A6

SC_GPIO3

B6

SC_GPIO2

E7

SC_GPIO4

C6

ANALOGGND

U11

ANALOGGND

R12

ANALOGGND

R13

ANALOGVCC

R11

ANALOGVCC

U13

ANALOGVCC

U14

VDPLL

P15

VSPLL/RSVD

N14

XI R18

XO R19

FILTER0

T19

FILTER1

R17

PC0

V10

PC1

W10

PC2

P9

R0

W13

R1

V13

TPA0P

V12

TPA0N

W12

TPA1P

V15

TPA1N

W15

TPB0P

V11

TPB0N

W11

TPB1P

V14

TPB1N

W14

TPBIAS0

U12

TPBIAS1

U15

R455 10K_0402_5%~D

1 2

C562

0.1U_0402_16V4Z~D

1

2

R191

0_0402_5%~D

@

1 2

C523

4.7P_0402_50V8C~D

@

1

2

C532

0.1U_0402_16V4Z~D

1

2

C185

22P_0402_50V8J~D

1

2

R507

1K_0402_5%~D @ 12

C164

10U_0805_10V4M~L

1

2

R174

0_0402_5%~D

@

1 2

R486

1K_0402_5%~D

12

R481 10K_0402_5%~D @

1 2

C167

1U_0805_10V6K~D

12

R164

2.7K_0603_5%~D@

12

R177

0_0402_5%~D

@

1 2

R451

0_0402_5%~D

12

R186

0_0402_5%~D

1 2

R470 100_0603_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CBS_CFRAME#

CBS_CC/BE1#

CBS_CDEVSEL#

CBS_CCD1#

CBS_RSVD/D14

CBS_CC/BE3#

CBS_CPERR#

CBS_CC/BE0#

CBS_CPAR

CBS_CSTSCHNG

CBS_CRST#

CBS_RSVD/D2

CBS_CVS2

CBS_CCLKRUN#

CBS_CREQ#

CBS_CIRDY#

CBS_CAUDIO

CBS_CBLOCK#

CBS_CSERR#

CBS_CVS1

CBS_RSVD/A18

CBS_CSTOP#

CBS_CINT#

CBS_CTRDY#

CBS_CC/BE2#

CBS_CCLK

CBS_CGNT#

CBS_CCD2#

CBS_CCD2# CBS_CCLKRUN#

SCR_IF_GPIO0

CBS_VCCD0#

SCR_C4_C

SCR_IF_GPIO3

TPB0-

Z3008

TPA0+

CBS_VPPD0

CBS_VPPD1

SCR_IF_PWR

SCR_IF_GPIO2

IEEE1394_TPB0N

NC_SCR_C8

IEEE1394_TPA0P

SCR_DETECT_C

CBS_VCCD1#

SCR_IF_GPIO4

SCR_C8_C

SCR_IF_GPIO5

SCR_IF_GPIO1

IEEE1394_TPB0P

SCR_DETECT

TPA0-

TPB0+

IEEE1394_TPA0N

TPS2211VCC

SCR_CLK_C

SCR_DATA_C

SCR_RST_C

SCR_IF_GPIO5

SCR_DETECT_C

SCR_IF_PWR

LOUT_H

SCR_IF_DATA

SCR_VCC_C

SCR_IF_GPIO1

SCR_IF_GPIO4

SCR_IF_GPIO0

SCR_IF_CLK

SCR_IF_GPIO3 LOUT_L

SCR_IF_RST

SCR_VCC_C

NC_SCR_C4

SCR_IF_GPIO2

CBS_CAD4

CBS_CAD28

CBS_CAD8

CBS_CAUDIO

CBS_CREQ#

CBS_CAD17

CBS_CFRAME#

CBS_CTRDY#

CBS_CAD16

CBS_CIRDY#

CAGE10_GND

CBS_CAD5

CBS_CAD22

CBS_CAD25

CBS_CAD7

CBS_CAD16

CBS_CPAR

SCR_VPP_PIN66

CBS_CAD15

CBS_CAD26

CBS_CAD17

CBS_CAD5

CBS_CAD3

CBS_CAD31

CBS_CAD19

CBS_CBLOCK#

CAGE50_GND

CBS_CAD7

CBS_CAD3

CBS_CAD15

CBS_CAD23

CBS_CAD12

CBS_CAD1

CBS_CAD18

CBS_CAD14

CBS_CAD30

SCR_C8_C

CBS_CAD10

CBS_CAD20

CBS_CC/BE1#

CBS_CSERR# CBS_CAD22

CBS_CAD21

CBS_CAD11

CBS_CAD11

CBS_CAD10

CBS_CAD1

SCR_VCC_C

CBS_CC/BE3#

CBS_CAD29

CBS_CAD27

CBS_CAD21

CBS_CAD19

CBS_CDEVSEL#

CBS_CAD13

CBS_CAD6

CBS_CAD24

SCR_VCC_C

CBS_CC/BE2#

CBS_CAD2

CBS_CAD26

CBS_CAD6

SCR_RST_C SCR_CLK_C

SCR_DATA_C

CBS_CSTOP#

CBS_CAD2

CBS_RSVD/D2

CBS_CAD18

SCR_C4_C

CBS_CAD8

CBS_RSVD/D14

CBS_CCLK

CBS_CAD12

CBS_CRST#

CBS_CAD4

CBS_CAD13

CBS_CAD31

CBS_CAD30

SCR_CLK_C

CBS_CGNT#

CBS_CPERR#

CBS_CC/BE0#

CBS_CAD24

CBS_CAD23

CBS_RSVD/A18

CBS_CINT#

CBS_CAD9

CBS_CAD0

CBS_CAD20

CBS_CVS2

CBS_CVS1

CBS_CAD27

CBS_CSTSCHNG

SCR_DETECT_C

CBS_CAD9

CBS_CAD29

CBS_CAD28

CBS_CCD1#

CBS_CAD25

SCR_RST_C

CBS_CAD14

CBS_CAD0

+3VSUS

+3VSUS

CBS_VPP

+12V

+5VSUS

CBS_VCC

+3VSUS

+5VSUS

CBS_VPP

CBS_VCC

+3VSUS

CBS_VCC

CBS_VPP

CBS_CPAR <30>

CBS_CVS2 <30>

CBS_CGNT# <30>

CBS_CIRDY# <30>

CBS_CVS1 <30>

CBS_CC/BE2# <30>

CBS_CSTSCHNG <30>

CBS_CBLOCK# <30>

CBS_CSERR# <30>

CBS_CAUDIO <30>

CBS_CCD1# <30>

CBS_CTRDY# <30>

CBS_RSVD/D14 <30>

CBS_CDEVSEL# <30>

CBS_CREQ# <30>

CBS_RSVD/D2 <30>

CBS_CFRAME# <30>

CBS_CINT# <30>

CBS_RSVD/A18 <30>

CBS_CC/BE3# <30>

CBS_CCLK <30>

CBS_CC/BE0# <30>

CBS_CSTOP# <30>

CBS_CAD[0..31] <30>

CBS_CC/BE1# <30>

CBS_CRST# <30>

CBS_CCLKRUN# <30>

CBS_CPERR# <30>

CBS_CCD2# <30>

CBS_VPPD1 <30>

CBS_VCCD0# <30>

CBS_VPPD0 <30>

SUSPWROK_5V <39,43,45>

CBS_VCCD1# <30>

IEEE1394_TPB0P<30>

IEEE1394_TPBIAS0<30>

IEEE1394_TPA0N<30>

SCR_DETECT<30>

IEEE1394_TPB0N<30>

IEEE1394_TPA0P<30>

SCR_IF_GPIO0<30>

SCR_IF_GPIO1<30>

SCR_IF_RST<30> SCR_IF_GPIO5<30>

SCR_IF_GPIO4<30>

SCR_IF_GPIO3<30>

SCR_IF_CLK<30>

SCR_IF_GPIO2<30>

SCR_IF_DATA<30>

SCR_IF_PWR<30>

SCR_DETECT_C <34>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

31 54Tuesday, March 18, 2003

Compal Electronics, Inc.

CardBus Socket

Place near connectorPlace near NCN6000

1

SHDN#

0

0

X

1

SHDN#

AVPP:150mA

1

1

VCCD0#

1

VPPD1

1

1

X

0

VPPD0

0

1

1

0

1

0

0

1

X

1

1

1

1

1

AVCC:1A

0

X0

VCCD1#

0

CBS_VPP

CBS_VCC

Place near ncn6000

Depop if support Smart Card

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Link CIS

22.2

Link CIS

10.3

C151

470P_0402_50V7K~D

1

2

R172

0_0402_5%~D@

12

R193

0_0402_5%~D @ 12

C155

0.1U_0402_16V4Z~D

1

2

U10

TPS2211ADBR_SSOP16~D

VCCD0# 1

VCCD1# 2

3.3V_1

3

3.3V_2

4

5V_1

5

5V_2

6

GND

7

OC# 8

12V

9

AVPP 10

AVCC3 11

AVCC2 12

AVCC1 13

VPPD1 14

VPPD0 15

SHDN#

16

R204

0_0603_5%~D

1 2

C145

4.7U_1206_16V6K~D

1

2

C163

1U_0805_10V6K~D

1

2

U17

NCN6000_TSSOP20~D

A0

1

A1

2

PGM#

3

PWR_ON

4

STATUS

5

CS#

6

RESET#

7

I/O

8

CLOCK_IN

10 CRD_DET 11

INT#

9CRD_RST 12

CRD_CLK 13

CRD_IO 14

CRD_VCC 15

GROUND 16

PWR_GND 17

LOUT_L 18

LOUT_H 19

VBAT 20

C150

100P_0402_50V8K~D

1

2

R468

10K_0402_5%~D

12

R146

0_0402_5%~D@

1 2

R201

10K_0402_5%~D

12

R461

10K_0402_5%~D

12

R464

10K_0402_5%~D

12

C175

4.7U_1206_16V6K~D

1

2

R145

0_0402_5%~D@1 2

R144

0_0402_5%~D@

1 2

JCBUS

FOX_1CA875Q1-T1~D

11

22

33

44

55

66

77

88

99

10 10

11 11

12 12

13 13

14 14

15 15

16 16

17 17

18 18

19 19

20 20

21 21

22 22

23 23

24 24

25 25

26 26

27 27

28 28

29 29

30 30

31 31

32 32

33 33

34 34

35 35

36 36

37 37

38 38

39 39

40 40

41

41 42

42 43

43 44

44 45

45 46

46 47

47 48

48 49

49 50

50 51

51 52

52 53

53 54

54 55

55 56

56 57

57 58

58 59

59 60

60 61

61 62

62 63

63 64

64 65

65 66

66 67

67 68

68 69

69 70

70 71

71 72

72 73

73 74

74 75

75 76

76 77

77 78

78 79

79 80

80

81

81 82 82

83

83 84 84

85

85 86 86

R456

56.2_0603_1%~D

1 2

R189

22K_0402_5%

12

J1394

MOLEX_54515-0411~D

1

12

23

34

4

SGND1

5SGND2

6SGND3

7SGND4

8

R205

0_0603_5%~D

@

1 2

C144

0.1U_0402_16V4Z~D

1

2

R202

10K_0402_5%~D

12

L14

22U_LQH43MN220J01K_2OHM_1812~D

1 2

C156

0.1U_0402_16V4Z~D

1

2

R170

10K_0402_5%~D

12

L10

BLM31A260SPT_1206~D

1 2

R480

56.2_0603_1%~D

12

R173

10K_0402_5%~D

12

R185

0_0402_5%~D@

1 2

C143

4.7U_1206_16V6K~D

1

2

L7

857CM-0009~D

11

22

33

44

5

5

6

6

7

7

8

8

C174

10U_1206_6.3V7K~D

1

2

R460

56.2_0603_1%~D

1 2

C528

270P_0603_50V7K~D

1

2R147

0_0402_5%~D@1 2

R469

56.2_0603_1%~D

12

C656

100P_0402_50V8K~D

1 2

R194

0_0402_5%~D @ 12

C137

10U_1206_6.3V7K~D

1

2

C149

0.1U_0402_16V4Z~D

1

2

R200

10K_0402_5%~D

12

C136

1000P_0402_50V7K~D

1

2

T4

PAD

@

C135

0.1U_0402_16V4Z~D

1

2

C142

0.1U_0402_16V4Z~D

1

2

C182

0.1U_0402_16V4Z~D

1

2

R203

10K_0402_5%~D

12

T3

PAD

@

C154

56P_0402_50V8J~D

1

2

R187

22K_0402_5%

12

R448

5.1K_0805_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_AD27

PCI_AD10

PCI_AD21

PCI_AD17

PCI_TRDY#

PCI_AD8

PCI_PIRQD#

PCI_AD28

PCI_AD18

PCI_AD0

PCI_AD15

MPCIACT#

PCI_AD31

PCI_AD2

PCI_PIRQB#

PCI_AD13

PCI_FRAME#

PCI_AD29

HW_RADIO_DIS#

PCI_AD29 PCI_AD26

PCI_AD8

PCI_C_BE2#

PCI_AD20

PCI_AD24

PCI_AD14

PCI_AD6

PCI_REQ3#

PCI_AD30

PCI_AD9

PCI_AD28

PCI_SERR# PCI_STOP#

LAN_SMBCLK

PCI_AD6

WLAN_LED_ACTIVITY

PCI_AD27

PCI_AD18

PCI_AD16

PCI_AD16

PCI_AD23

PCI_AD13

PCI_PERR#

ICH_SMBDATA

PCI_C_BE3#

PCI_AD12

LAN_SMBDATA

PCI_AD7

PCI_GNT3#

PCI_AD31

PCI_AD5

PCI_AD4

PCI_AD2

LED_WLAN24_RADIOSTATE

PCI_AD5

PCI_AD23

PCI_AD3

PCI_AD7

PCI_AD30

PCI_AD3

PCI_AD1

PCI_AD19

PCI_AD1

ICH_SMBCLK

PCI_AD20

PCI_AD21

PCI_C_BE1#

PCI_AD24

PCI_AD12

PCI_AD22

PCI_AD9

PCI_AD10

PCI_DEVSEL#

PCI_AD14

LED_WLAN5_RADIOSTATE

PCI_AD19

PCI_AD26

MINIDSEL

PCI_AD25

PCI_AD17

PCI_AD19

PCI_AD25

PCI_AD11

PCI_PAR

PCI_AD0

PCI_AD15

PCI_C_BE0#

PCI_AD22

PCI_AD4

PCI_IRDY#

PCI_AD11

PCI_CLKRUN#

PCIRST_2#

NIC_MINI_SMBDAT

NIC_MINI_SMBCLK LAN_SMBCLK

MPCI_M66EN

CK_33M_MINIPCI

SYS_PME#

PCI_CLKRUN#

CK_33M_MINPCI_TERM

CK_33M_MINIPCI

LAN_SMBDATA

+5VRUN

+3VRUN

V_3P3_LAN

+5VRUN

V_3P3_LAN +3VSUS

+5VRUN

+3VRUN+3VRUN

V_3P3_LAN

+3VSUS

LED_WLAN24_RADIOSTATE <29>

PCI_PIRQB# <18,20>

PCI_STOP# <20,28,30>

PCI_PAR <20,28,30>

PCI_IRDY#<20,28,30>

PCI_GNT3# <20>

PCI_DEVSEL# <20,28,30>

PCI_PIRQD#<20,30>

HW_RADIO_DIS#<27,34>

PCI_SERR#<20,28,30>

ICH_SMBCLK<6,15,16,21>

PCI_C_BE0# <20,28,30>

LED_WLAN5_RADIOSTATE <29>

ICH_SMBDATA<6,15,16,21>

PCI_REQ3#<20>

PCI_TRDY# <20,28,30>

WLAN_LED_ACTIVITY<29>

PCI_C_BE3#<20,28,30>

PCIRST_2# <20>

PCI_PERR#<20,28,30>

PCI_C_BE2#<20,28,30>

PCI_FRAME# <20,28,30>

PCI_C_BE1#<20,28,30>

PCI_AD[0..31]<20,28,30>

LAN_SMBCLK <28>

COEX1_BT_ACTIVE <27>

CK_33M_MINIPCI<6>

COEX2_WLAN_ACTIVE<27>

SYS_PME# <28,30,33>

LAN_SMBDATA <28>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

32 54Tuesday, March 18, 2003

Compal Electronics, Inc.

MINIPCI

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R268

10K_0402_5%~D

1 2

C246

0.047U_0402_10V4M~D

1

2C242

0.047U_0402_10V4M~D

1

2

C229

0.1U_0402_16V4Z~D

1

2

R249

10K_0402_5%~D@

12

C247

0.047U_0402_10V4M~D

1

2

R278

1K_0402_5%~D

12

C244

0.047U_0402_10V4M~D

1

2

R270

10K_0402_5%~D

1 2

C252

0.1U_0402_16V4Z~D

1

2

C241

0.047U_0402_10V4M~D

1

2

C230

4.7P_0402_50V8C~D

@

1

2

C227

0.047U_0402_10V4M~D

1

2

G

D

S

Q52

2N7002_SOT23~D

2

13

C234

0.047U_0402_10V4M~D

1

2

R284

10K_0402_5%~D

1 2

R255

0_0402_5%~D@1 2

R264

10K_0402_5%~D

12

C231

0.047U_0402_10V4M~D

1

2

G

D

S

Q48

2N7002_SOT23~D

2

13

G

D

S

Q49

2N7002_SOT23~D

2

1 3

C249

0.1U_0402_16V4Z~D

1

2

JPCI

AMP_1318644-1~D

RING 2

TIP

1

8PMJ-1 4

8PMJ-3

3

8PMJ-2 6

8PMJ-6

5

8PMJ-4 8

8PMJ-7

7

8PMJ-5 10

8PMJ-8

9

LED2_YELP 12

LED1_GRNP

11

LED2_YELN 14

LED1_GRNN

13

RESERVED 16

CHSGND

15

5V 18

INTB#

17

INTA# 20

3.3V

19

RESERVED 22

RESERVED

21

3.3VAUX 24

GROUND

23

RST# 26

CLK

25

3.3V 28

GROUND

27

GNT# 30

REQ#

29

GROUND 32

3.3V

31

PME# 34

AD31

33

RESERVED 36

AD29

35

AD30 38

GROUND

37

3.3V 40

AD27

39

AD28 42

AD25

41

AD26 44

RESERVED

43

AD24 46

C/BE3#

45

IDSEL 48

AD23

47

GROUND 50

GROUND

49

AD22 52

AD21

51

AD20 54

AD19

53

PAR 56

GROUND

55

AD18 58

AD17

57

AD16 60

C/BE2#

59

GROUND 62

IRDY#

61

FRAME# 64

3.3V

63

TRDY# 66

CLKRUN#

65

STOP# 68

SERR#

67

3.3V 70

GROUND

69

DEVSEL# 72

PERR#

71

GROUND 74

C/BE1#

73

AD15 76

AD14

75

AD13 78

GROUND

77

AD11 80

AD12

79

GROUND 82

AD10

81

AD9 84

GROUND

83

C/BE0# 86

AD8

85

3.3V 88

AD7

87

AD6 90

3.3V

89

AD4 92

AD5

91

AD2 94

RESERVED

93

AD0 96

AD3

95

RESERVED 98

5V

97

RESERVED 100

AD1

99

GROUND 102

GROUND

101

M66EN 104

AC_SYNC

103

AC_SDATA_OUT 106

AC_SDATA_IN

105

AC_CODEC_ID0# 108

AC_BIT_CLK

107

AC_RESET# 110

AC_CODEC_ID1#

109

RESERVED 112

MOD_AUDIO_MON

111

GROUND 114

AUDIO_GND

113

SYS_AUDIO_IN 116

SYS_AUDIO_OUT

115

SYS_AUDIO_IN GND 118

SYS_AUDIO_OUT GND

117

AUDIO_GND 120

AUDIO_GND

119

MCPIACT# 122

RESERVED

121

3.3VAUX 124

VCC5A

123

R250

0_0402_5%~D@1 2

C253

0.1U_0402_16V4Z~D

1

2

G

D

S

Q53

2N7002_SOT23~D

2

1 3

R248

10_0402_5%~D @

1 2

C232

0.047U_0402_10V4M~D

1

2

R261

100_0603_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NB_MUTE

KAGND

SIO_SLP_S4_S5#

SIO_THRM#

MODC_EN#

LPC_LDRQ1#

BAY_MODPRES#

DISKCHG#

KSO_17

WRPRT#

+3.3VRTC

RDATA#

LID_CL_SIO#

PWRSW_SIO#

BUSY

D_CLKRUN#

SYS_PME#

USB_IDE#

PE

DH_PWRSRC_OC

KPLLVCC

INDEX#

DEBUG_ENABLE LPCPD#

IRQ_SERIRQ

SIO_RCIN#

VAUX_EN

ACK#

SUS_ON

SIO_EXT_SMI#

EC_CLKRUN#

ATF_INT#

BEEP

TRK0#

HDDC_EN#

LID_CL#

LPC_LAD1

DEBUG_OUT

PCIRST_SIO#

RI0#

SYS_SUSPEND

KSO17

LPC_LAD2

IDE_RST_HDD

SIO_EXT_SCI#

DH_POWER_EN

254VCC0

SIO_SLP_S3#

LPC_LFRAME#

IDE_RST_MOD

CBS_GRST# D_DLRQ1#

RUN_ON

GC_BL_SUSPEND

DEBUG_ENABLE

D_SERIRQSIO_EXT_RTE#

RXD0

ICH_PME#

LPC_LAD3

USB_EN#

SLCT

ATF_INT#

LPC_LAD0

SYS_PME#

AC_LOW_PRES2#

LID_CL_SIO#

CTS0#

DSR0#

DCD0#

ERROR#

D_IRMODE

IRRX

IRTX

PWRSW_SIO#

D_SERIRQ

D_CLKRUN#

TXD0

TXD0

+3VRUN

+3VALW

+3VRUN

+3VALW

+3VRUN

+3VRUN

+3.3VRTC

+3VRUN

+3VALW

+3VALW

+3VRUN

+3VALW

+3VRUN

+3VRUN

+3VRUN

+5VSUS

SUS_ON<43>

MODC_EN#<39>

ATF_INT#<19,47>

PCIRST_SIO# <20>

KSO_17<35,38>

SIO_EXT_RTE#<21>

LPC_LDRQ1# <21>

DH_POWER_EN<26>

ICH_PME#<20>

GC_BL_SUSPEND<18>

BAY_MODPRES#<23>

SIO_SLP_S3#<21>

USB_IDE#<23>

VAUX_EN<39,43>

SIO_SLP_S4_S5#<21>

SIO_THRM#<21>

IDE_RST_HDD<21>

SATA_MOD_DETECT#<23> SYS_SUSPEND<18,41>

LPC_LFRAME# <21>

SYS_PME#<28,30,32>

IDE_RST_MOD<21>

RUN_ON<18,37,39,44>

SIO_EXT_SMI#<21> LPC_LAD[0..3] <21>

USB_EN#<26>

NB_MUTE<25> SIO_RCIN#<21>

LID_CL# <18>

IRQ_SERIRQ <20,21,30>

SIO_EXT_SCI#<21>

CBS_GRST#<30> C3/C4#<36>

DH_PWRSRC_OC<26>

HDDC_EN#<39>

BEEP<24>

PWRSW_SIO#<39>

NOCREG<36>

GV_HI_LO#<36>

D_IRMODE <38>

IRRX <38>

IRTX <38>

SIO_PWRBTN#<21>

LONG/SHRT#<36>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

33 54Tuesday, March 18, 2003

Compal Electronics, Inc.

SIO (1/2)

SATA_HDD_DETECT#

D-Bay USB power

Dell GPIO rev0.7

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R527 10K_0402_5%~D

1 2

C563

0.1U_0402_16V4Z~D

1

2

R222 10K_0402_5%~D

1 2

T11

PAD

@

L12

BLM11A121S_0603~D

1 2

R535 10K_0402_5%~D

1 2

C572

0.1U_0402_16V4Z~D

1

2

J1397

1.5mm SMT@

11

22

33

T6

PAD

@

LPC47N254

256 - LBGA

GPIO

FDD

COM1

LPT

GND

MACALLEN

LPC

8051

GPIO

VCC

IR

LPC

DOCK LPC

U15A

LPC47N254V12FBGA_LBGA256~D

SGPIO30

F13

SGPIO31

F14

SGPIO32

E16

SGPIO33

E15

SGPIO34

E12

SGPIO35

E13

SGPIO36

D16

SGPIO37

D15

VSS4 N1

SGPIO41

C16

SGPIO42

C15

SGPIO43

A16

SGPIO44

D14

SGPIO45

C14

SGPIO46

C13

SGPIO47

B14

LGPIO54

T6

LGPIO55

L7

LGPIO56

P7

LGPIO57

N7

LGPIO60

A15

LGPIO61

D13

LGPIO62

A14

LGPIO63

C12

LGPIO50

T5

LGPIO51

N6

LGPIO52

L6

LGPIO64

B13

LGPIO53

R6

WPROT# L3

RDATA# M1

HDSEL# L2

INDEX# L5

DSKCHG# M2

TRK0# L4

MTR0# K1

DIR# K2

STEP# K4

WDATA# K3

WGATE# L1

DS0# K5

DRVDEN0 J7

DRVDEN1 K7

FPD M5

RXD1 G5

TXD1 G2

RTS1# H7

CTS# H8

DTR# H6

DSR# G1

DCD# H5

RI1# B10

GPIO10/WK_SE14/IRMODE/IRRX3B H15

ACK# C1

SLCTIN# F2

INIT# F1

ALF# G3

STROBE# G4

BUSY D4

PE B1

SLCT B2

ERROR# G6

PD0 F4

PD1 F3

PD2 E2

PD3 F5

PD4 E4

PD5 D1

PD6 D2

PD7 E3

VSS1 C2

VSS2 F6

VSS3 J5

VSS5 N5

VSS6 T10

VSS7 R15

VSS8 J11

SGPIO40

E14

LGPIO65

A13

LGPIO66

D12

LGPIO67

F11

LGPIO70

B12

LGPIO71

A12

LGPIO72

C11

LGPIO73

D11

LGPIO74

E11

LGPIO75

B11

LGPIO76

A11

LGPIO77

C10

VSS9 G11

VCC0/BAT

A4

VCC1_1

M7

VCC1_2

R13

VCC1_3

L11

VCC2_1

D3

VCC2_2

H2

VCC2_3

K6

VCC2_4

P4

IRRX K14

IRTX M4

VCC1_4

H10

VCC1_5

B16

VCC1_6

F10

VCC1_7

A6

LDRQ1# R3

LPCPD# H4

LFRAME# N4

LAD0 M3

LAD1 R1

LAD2 T1

LAD3 P3

SER_IRQ T4

CLKRUN# P5

DLDRQ1# R2

DLFRAME# T2

DLAD0 N2

DLAD1 P1

DLAD2 P2

DLAD3 N3

DSER_IRQ R4

DCLKRUN# T3

LRESET# H3

VCC2_6/PLL

R5

VCC2_5

E1

VSS12 D6

VSS11 H9

VSS10 B15

AGND A2

VSS13/PLL

P6

RN5

10K_8P4R_1206_5%~D

1 8

2 7

3 6

4 5

C534

0.047U_0402_10V4M~D

1

2

R195

100K_0402_5%~D

12

R183

100K_0402_5%~D

12

L22

BLM11A121S_0603~D

1 2

C558

0.1U_0402_16V4Z~D

1

2

R467

10_0402_5%~D 12

R220 10K_0402_5%~D

1 2

C549

0.1U_0402_16V4Z~D

1

2

R523

4.7K_0402_5%~D

1 2

C574

0.1U_0402_16V4Z~D

1

2

R217 10K_0402_5%~D

1 2

C546

0.1U_0402_16V4Z~D

1

2

R196 10K_0402_5%~D

1 2

R537 10K_0402_5%~D

1 2

R184

100K_0402_5%~D

12

C589

0.1U_0402_16V4Z~D

1

2

C211

0.1U_0805_50V7M~D

1

2

T5

PAD

@

R181

10K_0402_5%~D

12

C577

0.1U_0402_16V4Z~D

1

2

D4

RB751V_SOD323~D

2 1

R465

10K_0402_5%~D

12

R226

10K_0402_5%~D

1 2

R233

10K_0402_5%~D

12

R231 10K_0402_5%~D

1 2

R182

10K_0402_5%~D

12

C567

0.1U_0402_16V4Z~D

1

2

C568

0.1U_0402_16V4Z~D

1

2

R227 10K_0402_5%~D

1 2

R532 10K_0402_5%~D

1 2

U42C

TC7W14FU_SSOP8~D

P8

A

3Y5

G

4

C548

0.1U_0402_16V4Z~D

1

2

R466

100K_0402_5%~D

12

C581

0.1U_0402_16V4Z~D

1

2

R520

10K_0402_5%~D

1 2

R211 10K_0402_5%~D

1 2

R232

0_0402_5%~D

12

C152

0.1U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DAT_SMB

FWR#

SBAT_SMBDAT

PBAT_ALARM#

KSO16

FCS#

PBAT_ALARM#

SIO_FA16

KSO4

CK_14M_SIO_TERM

KSO14

KSI0

NUM_LED#

SIO_KAH_PGM

KSO10

FAN1_TACH

CHG_PBATT

FDD_PP#

FAN2_TACH

CLK_SM2

CK_33M_SIOPCI_TERM

SIO_FA3

PBAT_SMBDAT

CK_33M_SIOPCI

SIO_FA9

BAT2_LED#

SIO_FA2

MODE

FAN2_PWM

SIO_FD0

DAT_SM1

LPC_LDRQ0#

KSI3

PBAT_SMBDAT

SIO_FA10

BREATH_LED

SIO_FA6

HW_RADIO_DIS#

CLK_32KX2

RUNPWROK

PBAT_SMBCLK

DAT_KBD

PBAT_PRES#

SIO_FA18

SIO_FA5

SIO_FD4

SIO_FA15

SIO_FA0

SIO_THERM_PWRDN

KSI7

FRD#

CK_14M_SIO

KSO6

CAP_LED#

KSO7

EEPROM_WC

SIO_A20GATE

KSO2

KSO1

SIO_FA11

RESET_OUT#

BAT1_LED#

KSO5

SRL_LED#

SIO_FD1

SIO_FA19

SIO_FA8

SBAT_SMBCLK

KSO12

SIO_FD6

SBAT_SMBCLK

KSO0

KSO8

LIVE_ON_BATT

KSO13

KSO15

SIO_FD2

SIO_FA14

SIO_FA12

KSI1 SIO_FA17

KSI5

FPVCC

SIO_FA13

SBAT_SMBDAT

TI_SUSPEND#

ACAV

KSO11

SCR_DETECT_C

DAT_SM2

SIO_FD5

SIO_FD3

KSI2

PBAT_SMBCLK

KSO9

VCC1_PWROK

CLK_SM1

SIO_FA1

SIO_FD7

CLK_KBD

KSI4

SIO_FA7

KSO3

KSI6

SIO_FA4

XOSEL

H_PROCHOT_SIO#

FAN1_PWM

LAN_LOW_PWR

AUDIO_AVDD_ON

SIO_MSCLK

SIO_MSDAT

HW_RADIO_DIS#

LAN_LOW_PWR

CHG_PBATT

CLK_KBD

DAT_SM1

CLK_SM1

CLK_32KX1

CLK_SMB

DOCK_SMBDAT

DOCK_SMBCLK

DOCK_SMBDAT

DOCK_SMBCLK

DAT_KBD

+3VALW

+5VALW

+3VALW

+3VALW

+3VALW

+5VRUN

+3VALW

+3VALW

KSO16<35>

H_PROCHOT_SIO#<10>

SBAT_SMBCLK <18>

SCR_DETECT_C<31> EEPROM_WC <35>

FAN1_PWM <14>

FAN1_TACH <14>

SIO_FA[0..19] <35>

CK_14M_SIO <6>

BAT1_LED# <38>

PBAT_SMBCLK <42,48>

DAT_SM2<35>

NB_PSID<41>

CLK_SM2<35>

PBAT_SMBDAT <42,48>

LPC_LDRQ0# <21>

CK_33M_SIOPCI <6>

PBAT_PRES#<42>

KSI[0..7]<35,38>

KSO[0..15]<35>

FAN2_PWM <14>

SIO_FD[0..7] <35>

CHG_PBATT <48>

SIO_THERM_PWRDN<37>

BREATH_LED <38>

SRL_LED#<38>

SIO_A20GATE <21>

PBAT_ALARM#<42>

BAT2_LED# <38>

FCS# <35>

NUM_LED#<38>

TI_SUSPEND# <30>

FRD# <35>

VCC1_PWROK <35>

RUNPWROK <18,37,43,44,46>

HW_RADIO_DIS# <27,32>

FAN2_TACH <14>

FPVCC<18>

FWR# <35>

DAT_SMB <19,26,35,47>

RESET_OUT# <37>

SBAT_SMBDAT <18>

LIVE_ON_BATT <39>

CAP_LED#<38> LAN_LOW_PWR <28>

AUDIO_AVDD_ON <24>

ACAV<39,48,49>

CLK_SMB <19,26,35,47>

DH_MOD_PRES#<26>

SATA_3V_ENABLE# <39>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

34 54Tuesday, March 18, 2003

Compal Electronics, Inc.

SIO (2/2)

3.8X12.1mm

1

3

MAX6326

2

SBAT_ALARM#

QBUFEN#

DOCK_PSID

DOCKED

DH_MOD_PRES#

DOCK_SMB_INT#

SBAT_PRES#

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

X5

32.768KHZ_12.5P_MC-306~D

12

R209

22K_0603_5%~D

1 2

R225

4.7K_0402_5%~D

12

R522

22K_0603_5%~D

1 2

R213

4.7K_0402_5%~D

1 2

R551

10K_0402_5%~D

12

C177

4.7P_0402_50V8C~D@

1

2

T9

PAD@

R236

10K_0402_5%~D

12

T10

PAD@

C593

22P_0402_50V8J~D

1 2

LPC47N254

256 - LBGA

GPIO

K/B

MISC

MACALLEN

CLOCK

FLASH

U15B

LPC47N254V12FBGA_LBGA256~D

XTAL1

A3

XTAL2

C5

FPGM L10

AB1B_DATA E9

AB1B_CLK D9

TEST_PIN K12

PCI_CLK J3

PWRGD K13

IN0/WK_EE4

B9

IN1/WK_EE2

B8

IN2/WK_EE3

A8

IN3/GPWKUP

C8

IN4/WK_SE00

D8

IN5/WK_SE01

E8

IN6/WK_SE05

F8

IN7/WK_EE1

G8

GPIO0/WK_SE02

H13

GPIO1/WK_SE03

H12

GPIO2/WK_SE04

H11

GPIO3/TRIGGER

G10

GPIO4/WK_SE07/KSO14

G16 GPIO5/WK_SE10/KSO15

G12 GPIO6/WK_SE11/IRMODE/IRRX3A

G15

GPIO7/WK_SE06

G13

GPIO17/WK_SE23/A20M

G14

GPIO19/WK_SE24 F16

GPIO20/WK_SE25/PS2CLK/8051RX

F15

GPIO21/WK_SE26/PS2DAT/8051TX

F12

IMCLK

B3

IMDAT

A1

KBCLK

J4

KBDAT

J6

EMCLK

C4

EMDAT

C3

FDD_LED# J12

BAT_LED# J9

LDRQ0# M6

XOSEL B4

OUT7/SMI D7

24MHZ_OUT J2

EC_SCI# K16

OUT11/PWM1 G7

OUT10/PWM0 A7

OUT9/PWM2 E7

OUT8/KBRST B7

RESET_OUT# H1

32KHZ_OUT D5

VCC1_PWRGD K15

CLOCKI J1

AB1A_DATA C9

AB1A_CLK A9

MODE E5

KSI7

M9

KSI6

L9

KSI5

K9

KSI4

K10

KSI3

M10

KSI2

R10

KSI1

N10

KSI0

P10

KSO13/GPIO18

R7

KSO12/OUT8/KBRST

T7

KSO11

K8

KSO10

J8

KSO9

L8

KSO8

M8

KSO7

N8

KSO6

P8

KSO5

T8

KSO4

R8

KSO3

R9

KSO2

T9

KSO1

P9

KSO0

N9

GPIO11/WK_SE15/AB2A_DATA H16

GPIO12/WK_SE16/AB2A_CLK H14

GPIO13/WK_SE17/AB2B_DATA J15

GPIO14/WK_SE20/AB2B_CLK J13

GPIO15/WK_SE21/FAN_TACH1 G9

OUT1 F7

OUT2 B6

OUT3 E6

OUT4 C6

OUT0 C7

PWR_LED# J10

GPIO16/WK_SE22/FAN_TACH2 F9

OUT5/DS1/KBRST A5

OUT6/MTR1 B5

GPIO9/WK_SE13/IRTX2

J16 GPIO8/WK_SE12/IRRX2

J14

FD0 T11

FD1 R11

FD2 M11

FD3 N11

FD4 P11

FD5 T12

FD6 R12

FD7 M12

FA0 N12

FA1 T13

FA2 P12

FA3 T14

FA4 T15

FA5 R16

FA6 N13

FA7 P16

FA8 M14

FA9 N15

FA10 N16

FA11 M13

FA12 L12

FA13 M15

FA14 M16

FA15 L14

FA16 L13

FA17 L15

FA18 L16

FA19 K11

FA20 R14

FA21 T16

FA22 P13

FRD# P14

FWR# N14

FCS# P15

FDC_PP# A10

MSCLK

D10

MSDAT

E10

R228

1K_0402_5%~D

12

R521

10_0402_5%~D

@

1 2

R234

10K_0402_5%~D @

12

R550

10K_0402_5%~D

12

R506

4.7K_0402_5%~D

1 2

C153

0.1U_0402_16V4Z~D

1

2

R229

10K_0402_5%~D

12

R235

10K_0402_5%~D

12

C592

22P_0402_50V8J~D

1 2

R207

10_0402_5%~D@

1 2

C564

4.7P_0402_50V8C~D @

1

2

R549

10K_0402_5%~D

12

R179

1K_0402_5%~D

@

12

R180

10K_0402_5%~D 12

R224

4.7K_0402_5%~D

12

R230

10K_0402_5%~D

1 2

R198

22K_0603_5%~D

1 2

U11

MAX6326_SOT23~D

RESET#

3

GND 2

VCC 1

R528

10K_0402_5%~D

1 2

R513

22K_0603_5%~D

1 2

R533

10K_0402_5%~D

1 2

R514

4.7K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DAT_SMB

SIO_FA3

SIO_FA1

KSI3

KSO9

SIO_FA7

SIO_FA15

KSO10

CLK_SM2

SIO_FA2

VCC1_PWROK

SIO_FA4

KSI1

SIO_FA18

KSI5

FRD#

KSI6

SIO_FA8

MOUSECLK

SIO_FA16

KSI4

SIO_FA11

KSI7

SIO_FA5

KSO16

CLK_SMB

DAT_SM2

SIO_FA12

MOUSEDAT

SIO_FA9

KSI6

FWR#

FCS#

SIO_FA17

SIO_FA0

KSI5

SIO_FA13

SIO_FA6

KSI1

KSI7

SIO_FA14

KSI2

SIO_FA19

KSI4

KSI0

KSI0

KSI2

KSI3

SIO_FA10

FWH_RST

EEPROM_WC

TP_V+

TP_Y

KSI0

KSI3

KSI1

KSI2

KSO_17

TP_GND

TP_X

MOUSEVDD

TP_Z

TP_GND

TP_Y

TP_X

TP_V+

TP_Z

FCS#

FRD#

FWR#

SIO_FD6

SIO_FD5

SIO_FD4

SIO_FD3

SIO_FD2

SIO_FD1

SIO_FD0

SIO_FA19

SIO_FA18

SIO_FA17

SIO_FA16

SIO_FA15

SIO_FA14

SIO_FA13

SIO_FA12

SIO_FA11

SIO_FA10

SIO_FA9

SIO_FA8

SIO_FA7

SIO_FA6

SIO_FA5

SIO_FA4

SIO_FA3

SIO_FA2

SIO_FA1

SIO_FA0

FWH_RST

SIO_FD2

SIO_FD6

SIO_FD4

SIO_FD0

SIO_FD7

SIO_FD7

SIO_FD3

SIO_FD5

SIO_FD1

KSO8

KSO11

KSO4

KSO6

KSO7

KSO2

KSO10

KSO4

KSO9

KSO0

KSO1

KSO5

KSO2

KSO14

KSO13

KSO12

KSO15

KSO5

KSO3

KSO13

KSO14

KSO12

KSO15

KSO6

KSO1

KSO7

KSO3

KSO11

KSO0

KSO8

+3VALW

+5VRUN

+3VALW

+5VRUN

+3VALW

+3VALW

FCS#<34>

DAT_SMB <19,26,34,47>

FWR#<34>

KSI[0..7]<34,38>

VCC1_PWROK <34>

DAT_SM2<34>

SIO_FA[0..19]<34>

FRD#<34>

CLK_SM2<34>

SIO_FD[0..7] <34>

CLK_SMB <19,26,34,47>

EEPROM_WC <34>

KSO[0..15]<34>

KSO_17<33,38>

KSO16<34>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

35 54Tuesday, March 18, 2003

Compal Electronics, Inc.

INT KB & ROM

2N7002

B

2

Keep no nosie coupled,

Especially the TP_GND

S

C

1

GE

3

SUB_6782U

SMbus address A2

D

DTC114

Address 1010 00XX

For Compal Flash Tools

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C138

10P_0402_50V8J~D

1

2

C202

0.1U_0402_16V4Z~D

1

2

JKYBRD

JAE_FK2S030W11~D

1

3

5

7

11

9

13

15

17

19

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

31

32

33

34

R219

0_0603_5%~D

12

L8

BLM11A601S_0603~D

1 2

C147

0.1U_0402_16V4Z~D

1

2

C140

10P_0402_50V8J~D

1

2

C141

10P_0402_50V8J~D

1

2

JP2

ACES_6278-34P-DEBUG

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

C146

10P_0402_50V8J~D

1

2

CN4

100P_1206_8P4C_50V8~D

@

1 8

2 7

3 6

4 5

C148

100P_0603_50V8J~D

@

1

2

L9

BLM11A601S_0603~D

1 2

C203

0.1U_0402_16V4Z~D

1

2

CN5

100P_1206_8P4C_50V8~D

@

1 8

2 7

3 6

4 5

R166

4.7K_0402_5%~D

12

R168

4.7K_0402_5%~D

12

C599

0.1U_0402_16V4Z~D

1

2

JPALM

HRS_FX6A-20P-0.8SV~D

1

3

5

7

9

11

13

15

17

19

2

4

6

8

10

12

14

16

18

20

L11

BLM31A260SPT_1206~D

12

CN3

100P_1206_8P4C_50V8~D

@

1 8

2 7

3 6

4 5

CN1

100P_1206_8P4C_50V8~D

@

1 8

2 7

3 6

4 5

CN6

100P_1206_8P4C_50V8~D

@

1 8

2 7

3 6

4 5

U14

MX29LV008T/B_TSOP40~D

A0

21

A1

20

A2

19

A3

18

A4

17

A5

16

A6

15

A7

14

A8

8

A9

7

A10

36

A11

6

A12

5

A13

4

A14

3

A15

2

A16

1

A18

13

CE#

22

OE#

24

D0 25

D1 26

D2 27

D3 28

D4 32

D5 33

D6 34

D7 35

GND 39

A17

40

WE#

9

VCC 30

VCC 31

GND 23

A19

37

NC 29

NC 38

VPP 11

RP#/RESET# 10

WP#/RY/BY# 12

U40

FM24C05U_SO8~D

NC

1

A1

2

SDA 5

SCL 6

VCC 8

A2

3

VSS

4

WP 7

R552

0_0402_5%~D@

12

CN2

100P_1206_8P4C_50V8~D

@

1 8

2 7

3 6

4 5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GV_HI_LO#

H_STPCLK#

L_CPUSLP# I_STPCLK#

I_STPCLK#

DPSLP#

GV_HI_LO#

L_CPUSLP#

H_STPCLK#

VRM_PWRGD

H_CPUSLP# CLK_CPLD

PLD_DISABLE#

PLD_DISABLE#

VRM_PWRGD

H_STPCLK#H_CPUSLP#

CLK_STP_CPU#

CLK_CPLD

+3VSUS

+3VSUS

+VCC_CORE

+3VSUS

+VCC_CORE +VCC_CORE

+3VSUS +3VSUS

+3VSUS

+3VSUS

CPUSLP#<21> STPCLK#<21>

H_VID0<8> VID0 <8,46>

VID1 <8,46>

VID2 <8,46>

VID3 <8,46>

VID4 <8,46>

VID5 <8,46>

H_VID1<8> H_VID2<8> H_VID3<8> H_VID4<8> H_VID5<8>

CPUPREF# <8> CK_33M_CPLD <6>

PCI_PCIRST# <12,20>

SUSCLK <21>

CPLD_WAKE# <21>

GV_HI_LO#<33> NOCREG<33> C3/C4#<33>

CLK_STP_CPU#<6> LONG/SHRT#<33> STP_AGP#<18>

H_STPCLK#<8>

H_CPUSLP#<8>

I_VRMPWRGD <37>

VRM_PWRGD<21>

VCORE_DRSEN<46>

SUSPWROK<21,37>

VCORE_DSEN# <46>

DPSLP# <8>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

36 54Tuesday, March 18, 2003

Compal Electronics, Inc.

PLD

Pull low disables PLD assertion

of SSTEP or sleep and deeper

sleep on CPU

Dell Speedstep Support PLD

Pop when use CPLD

Pop when use CPLDPop when use CPLD

Depop when use CPLD

Depop when use CPLD

Pop when use CPLD

Depop PR93, Pop PR92 (P.46)Pop PR93, Depop PR92 (P.46)

STPCPU_VR (From PLD to CPU Power)

No.

1

2

3

4

5

6

7

8

9

Speedstep enable Speedstep disable

Pop U27, C233, C606, R557, Depop U27, JPLD, C233, C606, R557,

Function

CPLD (U27)

STPCLK# (From ICH to CPU) Pop Q42, R254, Depop R259

CPUSLP# (From ICH to CPU)

Depop Q42, R254, Pop R259

Pop Q43, R561, Depop R251 Depop Q43, R561, Pop R251

VRMPWRGD (From Reset to ICH) Depop R243 Pop R243

STP_AGP# (PLD to AGP) Pop R96, Depop R98 (P.18)Depop R96, Pop R98 (P.18)

DPRSLPVR (From PLD to CPU power)

PLD_WAKE# (From PLD to ICH) Depop R141 (P.21)Pop R141 (P.21)

Depop PR94, Pop PR95 (P.46)Pop PR94, Depop PR95 (P.46)

CPUPREF# (From PLD to CPU) Depop R380 (P.8)Pop R380(P.8)

10

E

DTC114TKA

1

3

B

C

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Link CIS

1.3

PLD_DISABLE# Pop R256, Depop R252 Depop R256, Pop R252

11 DPSLP# Pop R76, R78(P.8) Depop R76, R78(P.8)

12 PCI_PCIRST#(From ICH to PLD) Pop R245 Depop R245

GV_HI_LO#13 Pop R253 Depop R253

CPLD Function options Table

O_GMUXSEL

R31 0_0402_5%~D

1 2

R16 0_0402_5%~D

1 2

R588

0_0402_5%~D

1 2

R29 0_0402_5%~D

1 2

R253

10K_0402_5%~D

12

C233

0.1U_0402_16V4Z~D

1

2

R36 0_0402_5%~D

1 2

R34 0_0402_5%~D

1 2

R251

0_0402_5%~D @

1 2

R243

0_0402_5%~D @

1 2

R252

1K_0402_5%~D@

12

R245 0_0402_5%~D

1 2

R559

10K_0402_5%~D

12

R244

22_0402_5%~D @

12

10K

B

C

E

Q43

DTC114TKA_SC59~D

2

13

C225

10P_0402_50V8J~D

@

1

2

R256

10K_0402_5%~D

12

R15 0_0402_5%~D

1 2

10K

B

C

E

Q42

DTC114TKA_SC59~D

2

13

C606

0.1U_0402_16V4Z~D

1

2

R259

0_0402_5%~D@

1 2

R561

10K_0402_5%~D

12

R246

10K_0402_5%~D

12

R557 1K_0402_5%~D

1 2

R254

10K_0402_5%~D

12

JPLD

MOLEX_53261-0690~D@

1

2

3

4

5

6

U27

EPM3032A_TQFP44

TDI

1

TMS

7

TCK

26

TDO

32

I/O_43

43

I/O_44

44

I/O_2

2

I/O_8

8

I/O_12

12

I/O_13

13

I/O_20

20

I/O_14

14

I/O_42

42

I/O_5

5

I/O_6

6

I/O_10

10

I/O_18

18

GND 39

GND 40

GND 4

GND 11

GND 16

GND 24

GND 36

I/O_3 3

I/O_27 27

GND 30

I/O_15 15

I/O_19 19

I/O_21 21

I/O_22 22

I/O_25 25

I/O_33 33

VCCINT

41

I/O_35 35

I/O_37 37

I/O_28 28

I/O_31 31

I/O_34 34

GND 38

VCCINT

17

VCCIO

9

VCCIO

29

I/O_23

23

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

THERMTRIP_3P3#

Z3808

Z3813

Z3812

THERM_CPU#

Z3805

THERM_PWRDWN

Z3804

THERM_TRUE Z3809

THERM_CLEAR

Z3806

SIO_THERM_PWRDN

Z3811

THERM_TRUE

5VRUNRC

THERM_CPU#

IMVP_PWRGD

RUNPWROK

IMVP_PWRGD

IMVP_PWRGD

THERM_FF_GATE

RUNOK

RUN_ON

THERM_FF_GATE

MAX6509SET

MAX6509HYST

+3VSUS

+3VSUS

+3VSUS

+RTC_PWR

+RTC_PWR

+3VSUS

+5VSUS

+3VSUS

+5VRUN

+3VALW

+3VSUS

+3VSUS

+VCC_CORE

+3VSUS

+3VRUN

+3VSUS

+3VRUN

+3VSUS

+3VSUS

SUSPWROK <21,36>

RUN_ON<18,33,39,44>

RUNPWROK <18,34,43,44,46>

THERM_STP#<43>

H_THERMTRIP#<8,21>

POWER_SW_DB#<39>

V_2P5V_PWRGD<45>

SIO_THERM_PWRDN <34>

SUSPWROK_3V<39>

ITP_DBRESET#<8>

RESET_OUT#<34>

PWRGD_3V <10,21>

I_VRMPWRGD <36>

VCORE_PWRGD<46> CK_VTT_PG# <6>

ICH_THERM_PWRDN# <21>

VTT_PWRGD<44>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

37 54Tuesday, March 18, 2003

Compal Electronics, Inc.

Thermtrip & PowerGOOD

+3VSUS

Semitech P/N 103KT2125-1P

VCC for 10 degree

IN

2

MAX6509 goes in CPU cavity.

SET-HOT Vrsion

Discretes go outside.

Dell P/N 8K573

HYST:

POWER

SEQUENCING

Thermistor goes in CPU cavity.

GND for 2 degree

C

BE

3

1

2

3904 SYMBOL(SOT23-NEW)

+3VSUS

shall be VHC14

shall be VHC14

+3VSUS

+3VSUS

OUT

GND

3

DTA114YKA

1

SD 1.11(12474 page292) is request 8.2K ohm

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

R360

100K_0402_1%~D@ 1 2

R89

18.2K_0603_1%~D

1 2

R275

100K_0402_5%~D

1 2

R94

thermistor@

1 2

U25D

74VHC08MTC_TSSOP14~D

IN1

13

IN2

12

OUT 11

U25A

74VHC08MTC_TSSOP14~D

IN1

1

IN2

2OUT 3

P14

G

7

U42B

TC7W14FU_SSOP8~D

P8

A

6Y2

G

4

R355

100K_0402_1%~D@1 2

R247

150_0402_5%~D

12

U28A

SN74ACT74PWR_TSSOP14~D

D

2

CLK

3

Q5

Q6

VDD 14

PRE 4

VSS

7

CLR

1

U29

TC7SH08FU_SSOP5~D

B

1

A

2

G

3

O4

P5

C51

1000P_0402_50V7K~D @

1

2

R362

48.7K_0402_5%@

12

R359

48.7K_0402_1%~D

1 2

C609

0.22U_0603_10V7M~D

1

2

R282

0_0402_5%~D

@

1 2

C392

1000P_0402_50V7K~D@

1

2

C620

0.1U_0402_16V4Z~D

1

2

U36

LMV331__DCK@

IN+

1

GND

2

IN-

3

VCC+ 5

OUT 4

R581

10K_0402_5%~D

1 2

R93

10K_0402_5%~D

1 2

C604

0.1U_0402_10V6K~D

1

2

U4

MAX6509CHU-K_SOT23-5~D

SET

1

GND

2

OUT#

3

VCC 5

HYST 4

U26D

74VHC08MTC_TSSOP14~D

IN1

13

IN2

12

OUT 11

C603 0.1U_0402_16V4Z~D

1 2

C228 0.1U_0402_16V4Z~D

1 2

D16

RB751V_SOD323~D

2 1

C605

1U_0603_10V6K~D

1

2

C618

0.1U_0402_16V4Z~D

1 2

R281

0_0402_5%~D

1 2

R560

100K_0402_5%~D

12

U41B

TC7W14FU_SSOP8~D

P8

A

6Y2

G

4

R572

20K_0603_5%~D

12

C607 0.47U_0603_16V7K~D

1 2

C399

0.047U_0402_10V4M~D

@

1

2

Q60

MMBT3904_SOT23~D

2

3 1

G

D

S

Q70

2N7002_SOT23~D

2

13

U25C

74VHC08MTC_TSSOP14~D

IN1

10

IN2

9

OUT 8

U26C

74VHC08MTC_TSSOP14~D

IN1

10

IN2

9OUT 8

G

D

S

Q56

2N7002_SOT23~D

2

1 3

R285

8.2K_0603_5%~D

1 2

47K

47K

Q55

DTC144EKA_SOT23~D

2

13

U26B

74VHC08MTC_TSSOP14~D

IN1

4

IN2

5OUT 6

G

D

S

Q57

2N7002_SOT23~D

2

13

C226

0.1U_0402_16V4Z~D

1

2

R95

10K_0402_5%~D@

1 2

R352

16.2K_0402_1%~D@12

R556

100K_0603_5%~D

1 2

R353

2.21K_0402_1%~D@ 1 2

U42A

TC7W14FU_SSOP8~D

P8

A

1Y7

G

4

47K

47K

Q71

DTC144EKA_SOT23~D

2

13

R272

8.2K_0603_5%~D

12

C619 0.1U_0402_16V4Z~D

1 2

U41A

TC7W14FU_SSOP8~D

P8

A

1Y7

G

4

U41C

TC7W14FU_SSOP8~D

P8

A

3Y5

G

4

R283

1K_0402_5%~D

1 2

U26A

74VHC08MTC_TSSOP14~D

IN1

1

IN2

2OUT 3

P14

G

7

R571

10K_0402_5%~D

1 2

R280

1K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CAP_LED

Z3901

SRL_LED

R_BT_MPCI_ACT

BT_MPCI_ACTIVE

R_SRL

ACTLED

NUM_LEDR_NUM

BREATH_LED_B BT_ACTIVE

R_BAT1_LED

Z3902

BAT1_LED

R_BAT2_LED BAT2_LED

R_CAP

R_BREATH_LED

R_BT_MPCI_ACT

R_BREATH_LED

KSO_17

INT_MIC-

KSI5

INT_MIC+

KSI6

KSI4

POWER_SW#

BAT1_LED

BAT2_LED

CAP_LED

NUM_LED

SRL_LED

POWER_SW_EMI

R_PIDEACT

SD_MODE

IR_ANODE

Z3903IRVCC

+5VALW

+3VALW

+3VRUN +3VRUN

+3VALW

+RTC_PWR

+3VRUN +3VRUN

+5VHDD

SRL_LED#<34>

CAP_LED#<34>

BT_ACTIVE<27>

BAT2_LED#<34>

BAT1_LED#<34>

BREATH_LED<34>

NUM_LED#<34>

INT_MIC- <25>

INT_MIC+ <25>

POWER_SW# <39>

KSO_17 <33,35>

KSI4 <34,35>

KSI5 <34,35>

KSI6 <34,35>

IRRX <33>

D_IRMODE<33>

IRTX<33>

PIDEACT#<21>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

38 54Tuesday, March 18, 2003

Compal Electronics, Inc.

LED Interface & IrDA

1

2 3

DTA114YKA

OUT

IN GND

TFDU6102

LID_CL#

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

10K

47K

Q16

DTA114YKA_SOT23~D

2

1 3

R85

150_0603_5%~D

1 2

R573

1.8_1206_5%~D 12

C624

4.7U_1206_16V6K~D

1

2

10K

47K

Q44

DTA114YKA_SOT23~D

2

1 3

R574

47_0805_5%~D 12

R578

1K_0402_5%~D

12

JLED1

FOX_QTS1030A-2021~D

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

Q23

MMBT3904_SOT23~D

2

3 1

10K

47K

Q22

DTA114YKA_SOT23~D

2

1 3

R86

10K_0402_5%~D

1 2

R80

470_0603_5%~D

12

Q19

MMBT3904_SOT23~D

2

3 1

10K

47K

Q11

DTA114YKA_SOT23~D

2

1 3

R579

1K_0402_5%~D

12

R73

470_0603_5%~D

12

10K

47K

Q21

DTA114YKA_SOT23~D

2

1 3

R92

10K_0402_5%~D

1 2

R575

1.8_1206_5%~D 12

R576

0_0402_5%~D

1 2

C623

4.7U_1206_16V6K~D

1

2

R52

470_0603_5%~D

12

R577

0_0402_5%~D @

12

R46

470_0603_5%~D

12

R47

0_0402_5%~D

12

R72

150_0603_5%~D

1 2

R60

470_0603_5%~D

12

10K

47K

Q12

DTA114YKA_SOT23~D

2

1 3

R56

470_0603_5%~D

12

C621

0.1U_0402_16V4Z~D

1

2

U43

TFDU6101E_TR4~D

VCC

6

SD_MODE

5

IRED_CATHODE

2

TXD

3

IRED_ANODE 1

RXD 4

MODE 7

GND 8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MOD_EN

HDD_EN

RUN_ENABLE

Z4002

Z4003

Z4001

Z4005

Z4006

SUSPWROK_5V

ALW_ENABLE#

+RTC_PWR

+5VSUS

+5VHDD

+RTC_PWR

+3VSRC

+RTC_PWR

+5VSUS

+VCC_CORE

+3VRUN

+RTC_PWR

+RTC_PWR

+RTC_PWR

PWR_SRC

+12V

+12V

+5VSUS

+5VRUN

+RTC_PWR

+5VMOD

V_1P25V_DDR_VTT +3VRUN

+3VSRCPWR_SRC

+3VSUS

PWR_SRC

PWR_SRC

PWR_SRC

+3VSUS

+3.3VRTC +3.3VRTC

+12V

+3VMOD

+3VSUS

MODC_EN#<33>

RUN_ON<18,33,37,44>

ALW_ENABLE# <43>

LIVE_ON_BATT<34>

POWER_SW#<38>

POWER_SW_DB# <37>

ACAV<34,48,49>

HDDC_EN#<33>

PWRSW_SIO# <33>

SUSPWROK_5V <31,43,45>

VAUX_EN<33,43>

ENAB_3VLAN <28>

RUN_ON<18,33,37,44>

ALWON <43>

SUSPWROK_3V <37>

SATA_3V_ENABLE#<34>

RBAT<41>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

39 54Tuesday, March 18, 2003

Compal Electronics, Inc.

POWER CONTROL

+5HDD Source

2

+5VMOD Source

2

+3VRUN Source

2

Run Planes Enable

+5VRUN Source

11

2

1

2

1

11

11

+3VMOD Source

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Link CIS, function f

C250

0.01U_0603_50V7K~D

1

2

R238

100K_0402_5%~D

12

U24B

MM74HCT14_TSSOP14~D

IN

3

P14

G

7

O4

C245

4.7U_1206_16V6K~D

1

2

C223

0.1U_0402_16V4Z~D

1

2

C33

0.1U_0402_10V6K~D

1

2

Q26

TP0610T_SOT23~D

1 3

2

C220

0.1U_0402_16V4Z~D

1 2

G

D

S

Q67

2N7002_SOT23~D

2

13

R112

10K_0402_5%~D

12

47K

47K

Q37

DTC144EKA_SOT23~D

2

13

R62

100K_0402_5%~D

12

47K

47K

Q45

DTC144EKA_SOT23~D

2

13

G

D

S

Q36

2N7002_SOT23~D

2

13

U19A

SN74LVC3G14DCTR_SSOP8~D

P8

A

1Y7

G

4

R258

100K_0402_5%~D

12

U24A

MM74HCT14_TSSOP14~D

IN

1

P14

G

7

O2

C248

0.01U_0603_50V7K~D

1

2

R65

100K_0402_5%~D

12

S

G

D

Q20

SI3456DV-T1_TSOP6~D

3

6

245

1

C214

0.1U_0402_16V4Z~D

1

2

R260

10K_0402_5%~D

12

U23D

MM74HCT32_TSSOP14~D

IN0

12

IN1

13 O11

P14

G

7

R53

470K_0402_5%~D

12

R175

22_0805_5%~D

12

G

D

S

Q34

2N7002_SOT23~D

2

13

47K

47K

Q59

DTC144EKA_SOT23~D

2

13

G

D

S

Q25

2N7002_SOT23~D

2

13

U19B

SN74LVC3G14DCTR_SSOP8~D

P8

A

6Y2

G

4

R190

100K_0402_5%~D

12

S

GD

Q47

SI3456DV-T1_TSOP6~D

3

6

245

1

C600

0.1U_0402_16V4Z~D

1 2

R51

470K_0402_5%~D

12

R176

47_0805_5%~D

12

R50

470K_0402_5%~D

12

S

GD

Q50

SI3456DV-T1_TSOP6~D

3

6

2

4 5

1

G

D

S

Q15

2N7002_SOT23~D

2

13

C40

4.7U_1206_16V6K~D

1

2

S

GD

Q27

SI3456DV-T1_TSOP6~D

3

6

245

1

R103

30K_0402_5%~D

12

47K

47K

Q58

DTC144EKA_SOT23~D

2

13

S

G

D

Q41

SI3456DV-T1_TSOP6~D

3

6

2

4 5

1

C235

4.7U_1206_16V6K~D

1

2

G

D

S

Q17

2N7002_SOT23~D

2

13

U24F

MM74HCT14_TSSOP14~D

IN

13

P14

G

7

O12

R63

200K_0402_5%~D

12

R54

200K_0402_5%~D

12

C60

0.22U_1206_25V7M~D

1

2

G

D

S

Q35

2N7002_SOT23~D

2

13

R242

10K_0402_5%~D

12

R107

330K_0402_5%~D

12

C236

0.01U_0603_50V7K~D

1

2

R67

470K_0402_5%~D

12

R276

100K_0402_5%~D

12

S

G

D

Q54

SI3456DV-T1_TSOP6~D

3

6

2

4 5

1

R178

150_0805_5%

12

D5

RB751V_SOD323~D

2 1

R277

100K_0402_5%~D

12

R257

100K_0402_5%~D

12

R99

330K_0402_5%~D

12

C239

4.7U_1206_16V6K~D

1

2

C243

4.7U_1206_16V6K~D

1

2

R267

100K_0402_5%~D

12

U23A

MM74HCT32_TSSOP14~D

IN0

1

IN1

2O3

P14

G

7

G

D

S

Q14

2N7002_SOT23~D

2

13

JRBATT

MOLEX_53398-0290

1

2

C67

4.7U_1206_16V6K~D

1

2

R273

100K_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+RTC_PWR +RTC_PWR

+RTC_PWR

+RTC_PWR +3.3VRTC

+RTC_PWR

+RTC_PWR

+RTC_PWR

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

40 54Tuesday, March 18, 2003

Compal Electronics, Inc.

PAD,Screw Hole and Spare Parts

Fiducial Mark

MDC

CPU screw hole

MCH screw hole

VGA Conn. screw hole

PCB

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FAN Conn. screw hole

PCMCIA Slot screw hole

Others screw hole

+3VSUS

U28B

SN74ACT74PWR_TSSOP14~D

D

12

CLK

11

Q9

Q8

VDD 14

PRE 10

VSS

7

CLR

13

FD7

FIDUCIAL MARK

1

H19

H_O115X177D95X157

1

FD13

FIDUCIAL MARK

1

FD11

FIDUCIAL MARK

1

H15

C217D157

1

H28

C197D91

1

FD4

FIDUCIAL MARK

1

H8

C315D110

1

FD10

FIDUCIAL MARK

1

FD18

FIDUCIAL MARK

1

H1

H_C99D79

1

H12

C315D110

1

FD3

FIDUCIAL MARK

1

H29

C197D91

1

U24D

MM74HCT14_TSSOP14~D

IN

9

P14

G

7

O8

H20

C150D110

1

U23C

MM74HCT32_TSSOP14~D

IN0

9

IN1

10 O8

P14

G

7

H24

C315D165

1

U19C

SN74LVC3G14DCTR_SSOP8~D

P8

A

3Y5

G

4

H31

C315D110

1

H16

C315D110

1

FD12

FIDUCIAL MARK

1

H7

C315D110

1

FD9

FIDUCIAL MARK

1

H30

C315D110

1

FD5

FIDUCIAL MARK

1

H10

C315D165

1

FD15

FIDUCIAL MARK

1

H21

C150D110

1

FD1

FIDUCIAL MARK

1

H3

H_O115X177D95X157

1

H32

C315D110

1

H6

C315D165

1

U24C

MM74HCT14_TSSOP14~D

IN

5

P14

G

7

O6

H25

C315D165

1

U25B

74VHC08MTC_TSSOP14~D

IN1

4

IN2

5OUT 6

FD2

FIDUCIAL MARK

1

H23

C315D165

1

H9

C315D165

1

H11

C315D110

1

H22

C150D110

1

FD14

FIDUCIAL MARK

1

FD6

FIDUCIAL MARK

1

H5

C315D165

1

H33

C315D110

1

H26

C197D91

1

H4

H_C150D110

1

FD16

FIDUCIAL MARK

1

H17

C315D110

1

H2

H_C150D110

1

FD8

FIDUCIAL MARK

1

PCB

LA1711

1

U24E

MM74HCT14_TSSOP14~D

IN

11

P14

G

7

O10

FD17

FIDUCIAL MARK

1

FD19

FIDUCIAL MARK

1

H27

C197D91

1

U23B

MM74HCT32_TSSOP14~D

IN0

4

IN1

5O6

P14

G

7

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_ID

SBATT_VCC

Z4203

Z4202

Z4206

SYS_SUSPEND

Z4201

DCIN-

DCIN+

NC_LDO_EN

RTC_SHDN#

+DC_IN

RBAT

PS_ID NB_PSID

PWR_SRC

DC_IN+

+RTCSRC

DC_IN+

PWR_SRC

+12V

+RTCSRC +RTC_PWR

+3.3VRTC

+3VALW

SYS_SUSPEND<18,33>

RBAT<39>

PS_ID N B _PS ID <34>PS_ID

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

41 54Tuesday, March 18, 2003

Compal Electronics, Inc.

DC-IN

S

21

NOTE: "THE POINT LOCATED

AT PS MODULE

THESECAPSMUBTBE

NEXT TO JCHG

THE POINT

3

IRLML5103

G

D

+RTCSRC Source

FET on when in suspend, current flow is from Rbat to

PWR_SRC to sustain system during battery swap mode

DC_IN+ Source

Z-series AC Adaptor

Connctor

RTC_PWR Source

3.3VRTC Source

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PR8

150K_0603_5%~D

12

PR13

0_0603_5%~D

1 2

PC12

0.1U_0805_50V7M~D

12

PC5

2200P_0603_50V7K~D

12

PD4

EC10QS04_SOD106~D

2 1

HRS_HR33-DL-7~D

PJPDC1

Low_PWR 1

DC+_1 2

DC+_2 3

DC-_1 4

DC-_2 5

GND_1

6

GND_2

7

GND_3

8

GND_4

9

MH1

MH2

PC2

10U_1206_6.3V7K~D

12

PL4

CHT_C8BBPH853025

1 2

PR224

0_0603_5%~D@

1 2

PL2

CHT_C8BBPH853025

1 2

PC15

0.47U_1812_50V7M~D

1 2

PC3

10U_1206_6.3V7K~D

12

PD1

RB751V-40_SOD323~D

21

PD28

VZ0603M220APT_0603@

1

2

PQ3

SI7447DP_SO8

3

2

4

1

5

PQ1

IRLML5103_SOT23~D

2

13

PC10

0.01U_0603_50V7K~D

12

PC1

1000P_0603_50V7K~D

12

47K

47K

PQ2

DTC144EKA_SOT23~D

2

13

PC14

0.1U_0805_50V7M~D

12

PC4

2200P_0603_50V7K~D

12

+

PC8

15U_D2_25M_R90~D@

1

2

PR4

100K_0603_5%~D

12

PC13

0.1U_0805_50V7M~D

12

PR12

100K_0603_5%~D

12

PC7

0.01U_0603_50V7K~D

12

PL1

BLM11A121S_0603~D

12

PFS1

0.75A_24V_MINISMDM075/24~D

21

MAX1615EUK_SOT23-5~D

PU1

IN

1

GND

2

OUT 3

5/3+ 4

#SHDN

5

PR6

0_0603_5%~D

1 2

PR7

4.7K_0603_5%~D

1 2

PC9

1000P_0603_50V7K~D

1 2

PR5

0_0603_5%~D

1 2

PR3

4.7K_0603_5%~D

12

PR10

100K_0603_5%~D@

12

PR1

6.2K_0603_5%~D

1 2

PR2

0_0603_5%~D

1 2

PD2

RB751V-40_SOD323~D

21

G

D

S

PQ4

2N7002_SOT23~D

2

1 3

PC11

0.1U_0805_50V7M~D

12

PD3

EC10QS04_SOD106~D

21

PC6

0.01U_0603_50V7K~D

12

MAX1615EUK_SOT23-5~D

PU2

IN

1

GND

2

OUT 3

5/3+ 4

#SHDN

5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Z4306

Z4304

Z4305

SUB_OUT1

SUB_OUT2

SUB_OUT2

SUB_OUT1

+5VALW

+5VALW

PBATT+

+12V

PBAT_SMBDAT <34,48> PBAT_PRES# <34>

PBAT_SMBCLK <34,48>

PBAT_ALARM# <34>

SUB_OUT1 <50>

SUB_OUT2 <50>

SUB_DETECT <50>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

42 54Tuesday, March 18, 2003

Compal Electronics, Inc.

Battery CONN.

TRACE

Primary Battery Connector

THE POINT

ESD Diodes

SUYIN_200275MRQ12G536ZL_12P

TOP view

1

2

3

4

5

6

7

8

9

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

10

11

12

Please closely PJPB1

PJPB1

SUYIN_200275MR012G536ZL~D

SUB_OUT1 1

SUB_DETECT 3

BATT2-(GND) 4

BATT1-(GND) 5

BATT_VOLT 6

SMB_DAT 9

G

14

G

13

SUB_OUT2 2

SYS_PRES# 7

BATT_PRES# 8

SMB_CLK 10

BATT2+ 11

BATT1+ 12

PR17

100_0603_5%~D

1 2

PD31

DA204U_SOT323~D

@

1

3

2

PR14

10K_0603_5%~D

12

PR16

100_0603_5%~D

1 2

PD8

DA204U_SOT323~D

@

1

3

2

PL21

CHT_C8BBPH853025

12

PC17

2200P_0603_50V7K~D

1 2

PC16

0.1U_0805_50V7M~D

1 2

PD6

DA204U_SOT323~D

@

1

3

2

PD7

DA204U_SOT323~D

@

1

3

2

PR15

100_0603_5%~D

1 2

PD32

DA204U_SOT323~D

@

1

3

2

PD5

DA204U_SOT323~D

@

1

3

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TON

BST3

BST5

ILIM5

BST_3 LX5

BST_5

ILIM3

ILIM5

SKIP#

PRO#

ILIM3

TON

Z4704ALW_ENABLE#

REF

REF

LX3

DH5

PRO# SKIP#

DL3

DL5

PWR_SRC

+5VSUSP

+5VALW

+3.3VRTC

+3VALW

+3VSRCP

VCC_MAX1999

+3VSRCP

+RTC_PWR +3VALW

+5VALW +3.3VRTC

VCC_MAX1999

VCC_MAX1999

+5VSUS

+12V

+3VSRCP

+12VP

+5VSUSP

+3VSRC

+12VP

PWR_SRC

ALW_ENABLE#<39>

SUS_ON<33>

VAUX_EN<33,39>

THERM_STP#<37>

SUS_ON<33>

SUSPWROK_5V <31,39,45>

ALWON<39> RUNPWROK<18,34,37,44,46>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

43 54Tuesday, March 18, 2003

Compal Electronics, Inc.

3.3V/5V

Place these CAPs

close to FETs

Place these CAPs

close to FETs

Current limit at 4A for +3.3V

Add the current limit

Adding RC filter

Current limit at 6A for +5VSUSP

+5VALW Source +3VALW Source

(+12V+-5%,2A)

Adding SKIP control

(2A,80mils ,Via NO.= 4)

(4A,160mils ,Via NO.= 8)

(6A,240mils ,Via NO.= 12)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

+

PC34

330U_E_6.3VM~D

1

2

PC31

0.1U_0805_50V7M~D

12

PR229

0_0603_5%~D

1 2

PC23

2200P_0603_50V7K~D

12

PQ59

SI4810DY_SO8~D

3 6

5

7

8

2

4

1

PR24

43K_0603_1%~D

1 2

PR21

0_0603_5%~D@

1 2

PQ57

SI4810DY_SO8~D

3 6

5

7

8

2

4

1

PC27

0.1U_0805_50V7M~D

12

PC42

0.1UF_0603_16V7M~D

12

PR25

20K_0603_1%~D

1 2

PR26

0_0603_5%~D

1 2

PL7

4.7U_SPC-1205P-4R7B_+40-20%~D

1 2

PQ56

SI4800DY_SO8~D

3 6

5

7

8

2

4

1

PR34

100K_0603_5%~D

1 2

+

PC21

@15U_D2_25M_R90~D

1

2

PC26

1U_0603_6.3V6M~D

12

PL8

22U_SIL104-220_2.9A_30%

1 2

PC22

0.1U_0805_50V7M~D

12

PC224

100P_0603_50V8J~D

12

PR33

240K_0603_5%~D

1 2

+

PC40

47U_16V

1

2

PD10

EC10QS04_SOD106~D

2 1

PC30

0.1U_0805_50V7M~D

1 2

PC41

4.7U_1210_25V6K~D

12

PJP2

PAD-OPEN 4x4m

1 2

PQ13

@SI2301DS 1P_SOT23~D

G

2

D3

S

1

PR27

0_0603_5%~D

1 2

PR227

0_0603_5%~D@

1 2

PR228

0_0603_5%~D@

1 2

+

PC225

47U_16V@

1

2

PR30

0_1206_5%~D

1 2

PU19

MAX1745_10uMAX

SHDN

7

VH 8

FB 4

IN 10

CS 6

VL

2

REF

3

GND

1

OUT 5

EXT 9

PR32

0_0603_5%~D

1 2

PD13

EC31QS04~D

2 1

PC37

1000P_0603_50V7K~D

12

PC19

10U_1210_25V7M~D

12

PR22

0_0603_5%~D@

1 2

PC50

0.1U_0603_25V7K~D@

12

PQ7

SI4835DY_SO8~D

36

5

7

82

4

1

PR20

20K_0603_1%~D

1 2

PD9

RB717F_SOT323~D

3

1

2

PR45

100K_0603_5%~D@

1 2

PR46

100K_0603_5%~D@

1 2

PR40

1K_0603_5%~D

1 2

PD14

RB751V-40_SOD323~D

2 1

PC39

4.7U_0805_6.3V6K~D

12

PR41

20K_0603_1%~D

1 2

PR19

18.2K_0603_1%~D

1 2

PL6

4.7U_SPC-1205P-4R7B_+40-20%~D

1 2

PC25

1U_0603_6.3V6M~D

12

PC201

4.7U_1210_25V6K~D

12

PU3

MAX1999EEI_QSOP28~D

SHDN

6

BST3

28

DH3

26

LX3

27

DL3

24

OUT3

22

LX5 15

DL5 19

FB5 9

PRO 10

ILIM5 11

ILIM3 5

REF 8

V+

20

VCC

17

LDO5 18

BST5 14

DH5 16

OUT5 21

N.C. 1

TON 13

GND 23

SKIP

12

LDO3

25

FB3

7

ON3

3

ON5

4

PGOOD 2

PU4

TC7SH32FU_SSOP5~D

I0

2

I1

1

O4

P

5G3

PJP3

PAD-OPEN 4x4m

1 2

PC29

2200P_0603_50V7K~D

12

PL5

HCB4532K-800T90_1812~D

1 2

PR218

0_0603_5%~D @

12

PC24

4.7U_0805_6.3V6K~D

12

PR31

2K_0603_5%~D

1 2

PR37

0_0603_5%~D

@

1 2

PD15

RB751V-40_SOD323~D

2 1

PC44

4.7U_1210_25V6K~D

12

PQ12

@SI2301DS 1P_SOT23~D

G

2

D3

S

1

PC28

0.1U_0805_50V7M~D

12

PR29

2.2_0603_5%~D

1 2

+

PC32

150U _D2_6.3VM~D

1

2

+

PC49

47U_D2_6.3VM~D@

1

2

PC36

1U_0805_25V4Z~D

12

PR28

2.2_0603_5%~D

1 2

PR36

172K_0603_1%~D

12

PC45

0.1U_0805_50V7M~D

12

PJP1

PAD-OPEN 4x4m

1 2

PR223

0.04_2512_1%~D

1 2

PR230

0_0603_5%~D

1 2

+

PC20

@15U_D2_25M_R90~D

1

2

PC18

10U_1210_25V6K~D

12

PC33

0.1U_0805_50V7M~D

12

PC43

1U_0805_25V4Z~D

12

PR23

47_0603_5%~D

12

PC38

10U_1206_10V4Z~D

12

PD11

EC10QS04_SOD106~D

2 1

PQ58

SI4800DY_SO8~D

3 6

5

7

8

2

4

1

PR18

4.7_0603_5%~D

1 2

PC51

0.47U_0603_16V7K~D

@

12

+

PC48

47U_D2_6.3VM~D@

1

2

PC35

0.1U_0805_50V7M~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_SRC

+5VSUS

+1.5VRUNP

+5VSUS

+VTT_GMCHP

+5VSUS

+1.5VRUNP

+VTT_GMCHP

+1.5VRUN

+VTT_GMCH

RUNPWROK_1P5V

RUN_ON<18,33,37,39>

RUNPWROK <18,34,37,43,46>

VTT_PWRGD <37>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

+1.5VRUNP & +VTT_GMCHP

Compal Electronics, Inc.

44 54Tuesday, March 18, 2003

+1.5VRUNP/+VTT_GMCHP

PR58

1.225V

PRESCOTT

1.45V

NORTHWOOD

28.7K_0603_1%

38.3K_0603_1%

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

B

Dell-Compal Confidential

+

PC220

470U_D2_2.5VM@

1

2

PR61

18.2K_0603_1%~D

12

PC58

1U_0603_6.3V6M~D

1 2

PC68

0.1U_0805_25V7K~D

12

PR65

0_0603_5%~D

12

PQ15

FDS6672A_SO8~D

3 6

5

7

8

2

4

1

PR216

10K_0603_5%~D

12

PC70

4.7U_0805_6.3V6K~D

12

PC62

0.1U_0603_25V7K~D

12

PC52

2200P_0603_50V7K~D

12

+

PC69

470U_D2_2.5VM

1

2

PJP5

PAD-OPEN 4x4m

1 2

PC74

4.7U_0805_6.3V6K~D

12

PC63

4.7U_1206_16V6K~D

12

PR55

36.5K_0603_1%~D

12

PR214

0_0603_5%~D

12

PC61

2200P_0603_50V7K~D

12

PL10

4.7U_SPC-1205P-4R7B_+40-20%~D

1 2

PC72

47P_0603_50V8J~D@

12

PC76

1000P_0603_50V7K~D

12

PR233

0_0603_5%~D

12

+

PC60

@15U_D2_25M_R90~D

1

2

PR215

0_0603_5%~D

12

PR53

8.87K_0603_5%~D

1 2

PR48

10_0603_5%~D

1 2

PR66

0_0603_5%~D

12

PR58

38.3K_0603_1%~D

12

PR57

715K_0603_5%~D

12

PC53

0.1U_0603_25V7M~D

1 2

PC54

4.7U_1210_25V6K~D

12

PC66

1U_0805_10V7K~D

1 2

PC57

1000P_0603_50V7K~D

12

PD17

EC31QS04~D

2 1

+

PC56

@15U_D2_25M_R90~D

1

2

PR47

1M_0603_5%~D

1 2

PC67

0.1U_0805_25V7K~D

12

PC55

4.7U_1210_25V6K~D

12

SI4814DY_SO8~D

PQ16

D1

2G1 8

G2

3

S1/D2 5

D1

1

S1/D2 7

S2

4S1/D2 6

PD16

DAP202U_SOT323~D

3

2

1

PC73

0.01U_0603_50V7K~D@

12

+

PC221

220U_D2_4VM~D

@

1

2

PR52

0_0603_5%~D

1 2

+

PC71

470U_D2_2.5VM

1

2

PQ14

IRF7811A_SO8~D

3 6

5

7

8

2

4

1

PL11

5U_SPC_06704_5R0_2.9A_30%~D

1 2

PR50

0_0603_5%~D

1 2

PR231

10_0603_5%~D

1 2

PC64

4.7U_1206_16V6K~D

12

PL9

HCB4532K-800T90_1812~D

1 2

PR54

7.87K_0603_1%~D

1 2

PC65

1U_0805_10V7K~D

12

PJP4

PAD-OPEN 4x4m

1 2

PR232

0_0603_5%~D

12

PR60

20K_0603_1%~D

12

PR49

0_0603_5%~D

1 2

PC59

1U_0603_6.3V6M~D

12

PR68

10K_0603_5%~D

12

PR51

0_0603_5%~D

1 2

SC1485

PU7

SC1485

PGND1

1

DL1

2

VDDP1

3

ILIM1

4

LX1

5

DH1

6

BST1

7

EN/PSV2 8

TON2 9

VOUT2 10

VCCA2 11

FBK2 12

PGOOD2 13

AGND2 14

PGND2 15

DL2 16

VDDP2 17

ILIM2 18

LX2 19

DH2 20

BST2 21

EN/PSV1

22

TON1

23

VOUT1

24

VCCA1

25

FBK1

26

PGOOD1

27

AGND1

28

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

V_2P5V_PWRGD

+2.5V_MEMP

PWR_SRC

+5VSUS

+2.5V_MEMP

+5VSUS

V_1P25V_DDR_VTTP

+2.5V_MEMP +2.5V_MEM

V_1P25V_DDR_VTT

V_1P25V_DDR_VTTP

+5VRUN

V_2P5V_PWRGD<37>

SUSPWROK_5V<31,39,43>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

45 54Tuesday, March 18, 2003

Compal Electronics, Inc.

1.25V/2.5V

+2.5V/+1.25V

DDR Termination Voltage

(3A,200mils ,Via NO.=6)

(12A,360mils ,Via NO.=24)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PR77

10_0603_5%~D

12

PC85

1000P_0603_50V7K~D

12

PR71

0_0603_5%~D

1 2

PC83

1U_0603_6.3V6M~D

1 2

PC100

1U_0603_6.3V6M~D

1 2

PR234

0_0603_5%~D

1 2

PC78

0.1U_0805_25V7K~D

12

PC96

4.7U_0805_6.3V6K~D

1 2

PR81

10_0603_5%~D

1 2

+

PC222

@15U_D2_25M_R90~D

1

2

PC93

1000P_0603_50V7K~D@

12

PL13

2UH

1 2

PR88

10K_0603_1%~D

12

PR69

1M_0603_5%~D

1 2

+

PC82

@15U_D2_25M_R90~D

1

2

PR74

0_0603_5%~D

1 2

PR78

7.5K_0603_1%~D

1 2

PR87

10K_0603_1%~D

12

PQ47

FDS6672A_SO8~D

3 6

5

7

8

2

4

1

PC77

2200P_0603_50V7K~D

12

PR89

10K_0603_5%~D

1 2

PR80

100_0603_5%~D@

12

PQ18

FDS6672A_SO8~D

3 6

5

7

8

2

4

1

PC216

4.7U_1210_25V6K~D

12

PR79

10.7K_0603_1%~D

1 2

PR85

750K_0603_5%~D

12

PR73

100_0603_5%~D@

12

PC223

2200P_0603_50V7K~D

12

SC1486

PU8

SC1486

PGND1

1

DL1

2

VDDP1

3

ILIM1

4

LX1

5

DH1

6

BST1

7

REFIN 8

TON2 9

REFOUT 10

VCCA2 11

FBK2 12

PGOOD2 13

AGND2 14

PGND2 15

DL2 16

VDDP2 17

ILIM2 18

LX2 19

DH2 20

BST2 21

EN/PSV1

22

TON1

23

VOUT1

24

VCCA1

25

FBK1

26

PGOOD1

27

AGND1

28

+

PC94

150U _D2_6.3VM~D

1

2

PC97

1000P_0603_50V7K~D

@

12

+

PC90

220U_D2_4VM~D

1

2

PR75

0_0603_5%~D

1 2

PJP7

PAD-OPEN 4x4m

1 2

PR217

0_0603_5%~D

1 2

PJP8

PAD-OPEN 4x4m

1 2

PC80

4.7U_1210_25V6K~D

12

PR82

10K_0603_1%~D

12

PC81

4.7U_1210_25V6K~D

12

PR72

0_0603_5%~D

1 2

PD29

RB751V-40_SOD323~D

21

PR235

0_0603_5%~D

1 2

PC84

1U_0603_6.3V6M~D

12

PD30

RB751V-40_SOD323~D

21

PC79

4.7U_1210_25V6K~D

12

+

PC91

220U_D2_4VM~D

1

2

PR86

10K_0603_5%~D

@

1 2

PC89

0.1U_0805_50V7M~D

12

PC219

1U_0805_10V7K~D

12

PC88

0.1U_0805_50V7M~D

12

+

PC95

150U _D2_6.3VM~D

1

2

PR76

42.2K_0603_1%~D

12

PQ17

IRF7811A_SO8~D

3 6

5

7

8

2

4

1

PC217

0.1U_0805_25V7K~D

12

PJP6

PAD-OPEN 4x4m

1 2

PC101

0.01U_0402_25V7K~D

12

PC92

150PF_0603_50V7K~D

12

SI4814DY_SO8~D

PQ19

D1

2G1 8

G2

3

S1/D2 5

D1

1

S1/D2 7

S2

4S1/D2 6

PC86

1000P_0603_50V7K~D

1 2

PL12

HCB4532K-800T90_1812~D

1 2

PR70

10_0603_5%~D

1 2

PD19

EC31QS04~D

2 1

PC218

1U_0805_10V7K~D

12

PL14

2.9uH

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.2VDD

+VCCVID

+3VSUS

+3VRUN

+5VRUN PWR_SRC

+5VRUN

+VCC_CORE

+5VRUN

+5VRUN

+5VRUN

+5VRUN

ISEN1- <47>

ISEN2- <47>

PWM2 <47>

PWM4 <47>

ISEN3- <47>

ISEN2+ <47>

PWM3 <47>

ISEN3+ <47>

VCORE_PWRGD <37>

PWM1 <47>

ISEN1+ <47>

ISEN4+ <47>

ISEN4- <47>

VID1<8,36> VID0<8,36> VID5<8,36>

VCORE_ENLL<8>

VID2<8,36> VID3<8,36> VID4<8,36>

VCORE_DRSEN<36>

VCORE_DSEN#<36>

RUNPWROK<18,34,37,43,44>

VCORE_VTT

VSSSENSE <8>

VCCSENSE <8>

VID_PWRGD<8>

VCORE_BOOTSELECT<7>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

46 54Tuesday, March 18, 2003

Compal Electronics, Inc.

CPU_CORE_Controller

Panasonic ERTJ0EV334J (0402)

Locate this NTC resistor on

PCB between phase 2 and 3

for thermal compensation. Remote

Sensing

Battery Feed

Forward

Frequency Select

Place close to IC

Place near +VCC_CORE

output capacitor

1. When mode control signal is

high/ low, the VR will operate to

Northwood/ Prescott load line.

2. VID5(12.5) should be pulled

high, when the VR operates to

Nothwood load line.

PU20A

LM358M_SO8~D

P8

IN+ 3

IN- 2

G

4

O

1

PR111

1.87K_0603_1%~D

1 2

PR94

0_0603_5%~D

12

PR103

10K_0603_1%~D

12

PR90

80.6K_0603_1%~D

1 2

PR95

0_0603_5%~D

@

12

PQ62

MMBT3904_SOT23~D

2

3 1

PR123

22K_0603_5%~D

12

PR112

330K_0603_5%~D

1 2

PR204

9.31K_0603_1%~D

12

PR119

0_0402_5%~D@12

PR93

0_0603_5%~D

1 2

PR110

1M_0603_5%~D

12

PR117

0_0603_5%~D

12 PC110

4.7U_1206_16V6K~D

12

PR99

0_0603_5%~D@

12

PR226

0_0603_5%~D@

1 2

PC109

1000P_0603_50V7K~D@

12

G

D

S

PQ46

2N7002_SOT23~D

2

13

PR115

0_0603_5%~D@

12

PR91

10K_0603_5%~D

12

PC111

1U_0603_6.3V6M~D

12

PR120

0_0402_5%~D

@

12

PU9

ISL6247CR_QFN40~D

VCC

32

PGOOD 39

VID4

1

VID3

2

VID2

3

VID1

4

VID0

5

VID12.5

6

PWM1 25

PWM4 31

PWM2 26

PWM3 20

ISEN1+ 24

ISEN4+ 30

ISEN2+ 27

ISEN3- 22

FS

36

VDIFF 16

DRSV

37

COMP 15

OCSET

10

FB 13

SOFT

11

VSEN 17

VRTN 18

OFS 8

ENLL

34

VR-TT#

38 NC 14

DSV

9

ISEN1- 23

ISEN4- 29

ISEN2- 28

ISEN3+ 21

DSEN#

35

NTC

40

GND

19

GND

12

RAMPS 7

DRSEN

33

G

D

S

PQ45

2N7002_SOT23~D

2

13

PR92

0_0603_5%~D@

1 2

PR102

20K_0603_1%~D

1 2

PU10

MIC5258

PG

4

VOUT 5

EN

3

VIN

1

GND 2

PC103

0.033U_0603_25V7M~D

12

PC105

4700P_0402_25V7K~D

12

G

D

S

PQ61

2N7002_SOT23~D

2

13

PR104

90.9K_0603_1%~D

12

PR225

0_0603_5%~D

@

1 2

PR113

32.4K_0603_1%

12

PR109

100K_0603_5%~D

12

PR122

0_0603_5%~D

12

PR101

17.4K_0603_1%~D

12

PU20B

LM358M_SO8~D

P8

IN+ 5

IN- 6

G

4

O

7

PR107

0_0603_5%~D

12

PR97

0_0603_5%~D@

12

PC112

4.7U_1206_16V6K~D

12

PR114

10K_0603_5%~D

1 2

PR121

0_0402_5%~D@

12

PR106

0_0603_5%~D

1 2

PR100

274_0603_1%~D

12

PR124

100K_0603_5%~D

1 2

PR98

0_0603_5%~D@

12

PC108

220P_0603_50V8J~D

12

PR116

0_0402_5%~D

1 2

PR220

340K_0603_1%~D

1 2

PC104

100P_0603_50V8J~D

12

PQ60

TP0610T_SOT23~D

2

13

PR108

42.2K_0603_1%

1 2

PR205

5.1K_0603_1%~D

1 2

PR96

1K_0603_1%~D

@

12

PR118

27K_0603_5%~D

1 2

PC102

1U_1210_50V7M

12

PC214

0.1UF_0603_16V7M~D

1 2

PC106

1000P_0603_50V7K~D@12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LG1 UG1UG2

Phase2

LG2UG3

Phase3

LG3UG4

Phase4

LG4

Phase1

PWR_SRC CPU_PWR_SRC

CPU_PWR_SRC

CPU_PWR_SRC

CPU_PWR_SRC

CPU_PWR_SRC

CPU_PWR_SRC

+5VRUN

CPU_PWR_SRC

+VCC_CORE

+3VALW

+3VALW

PWM1<46>

ISEN1-<46> ISEN1+<46>

PWM2<46>

ISEN2-<46> ISEN2+<46>

PWM3<46>

ISEN3-<46> ISEN3+<46>

PWM4<46>

ISEN4-<46> ISEN4+<46>

DAT_SMB <19,26,34,35>

CLK_SMB <19,26,34,35>

ATF_INT# <19,33>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

47 54Tuesday, March 18, 2003

Compal Electronics, Inc.

CPU_CORE_Power-Stage

Input Bulk and HF Capacitors

Snubber

Local Transistor

Swtich Decoupling

Notes:

The ISL6561(ISL6427) supports lossless current sensing including

Inductor DCR and MOSFET rDSon sensing. Schematic components are

color coded accordingly. In addition an external sense resistor

can be used for higher load-line accuracy but this will impact

system cost and efficiency.

Sync. Rectifiers use thermally enhanced "PowerPak" technology in

an SO-8 form-factor. Optimal MOSFETS will be chosen based on

thermal performance.

Depending on the processor final requirments and empirical

thermal result testing a 3 phase solution may be possible. In

the 4 phase configuration a single upper mosfet may also be

sufficient.

Add thermal venting vias to board. Vias under parts must have a

minimum pitch of 1mm and hole size of 0.3mm to avoid solder

wicking.

DCR

Inductor

Sensing

Panasonic ETQ-P4LR56WFC

Panasonic ETQ-P4LR56WFC

Local Transistor

Swtich Decoupling

Snubber

Panasonic ETQ-P4LR56WFC

Local Transistor

Swtich Decoupling

Snubber

Panasonic ETQ-P4LR56WFC

Local Transistor

Swtich Decoupling

Snubber

Address 1001 001X (X=1-->Read; X=0-->Write)

Address select(7414ART-0)

Float: 1001 000

GND: 1001 001

VDD: 1001 010

Low-side two population options

SI4362DY_SO8:

PQ22,PQ23,PQ26,PQ27,

PQ30,PQ31,PQ34,PQ35

FDS7064N_SO8:

PQ48,PQ49,PQ50,PQ51,

PQ52,PQ53,PQ54,PQ55

DUAL FOOTPRINT

DUAL FOOTPRINT

DUAL FOOTPRINT

DUAL FOOTPRINT

PTC resistor

PTC resistor

PTC resistor

PTC resistor

PQ52

FDS7064N_SO8@

3 6

5

7

8

2

4

19

PQ28

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PQ20

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PC155

1000P_0603_50V7K~D

@

12

PC146

1U_0603_6.3V6M~D

12

PC118

10U_1210_25V6K~D

12

PC122

10U_1210_25V6K~D

12

PR143

0_0603_5%~D

1 2

PR152

0_0603_5%~D

1 2

PQ26

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

PC165

0.01U_0603_16V7K~D

12

PR156

@

2.2_0805

1 2

PC154

10U_1210_25V6K~D

12

PR127

499K_0603_1%

@

1 2

PL17

0.56U_ETQP4LR56WFC_21A_20%~D

1 2

PR211

0_0603_5%~D

12

PR129

@

2.2_0805

1 2

PL15

CHT_C8BBPH853025

1 2

PC215

0.1U_0603_25V7M~D

12

PC147

10U_1210_25V6K~D

12

PQ29

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PQ54

FDS7064N_SO8@

3 6

5

7

8

2

4

19

PC153

1U_0603_6.3V6M~D

12

+

PC136

15U_D2_25M_R90~D@

1

2

PC158

0.01U_0603_16V7K~D

12

PC133

1U_0805_25V4Z~D

1 2

PC209

2200P_0603_50V7K~D

12

PQ49

FDS7064N_SO8@

3 6

5

7

8

2

4

19

PC115

10U_1210_25V6K~D

1 2

PR147

@

2.2_0805

1 2

PR130

32.4K_0603_1%~D

12

PQ53

FDS7064N_SO8

@

3 6

5

7

8

2

4

19

PQ50

FDS7064N_SO8@

3 6

5

7

8

2

4

19

PR142

820_0603_1%~D

12

PC164

1U_0805_25V4Z~D

1 2

PC203

0.1U_0603_25V7M~D

12

PC120

10U_1210_25V6K~D

12

+

PC142

15U_D2_25M_R90~D@

1

2

+

PC140

15U_D2_25M_R90~D@

1

2

PC208

2200P_0603_50V7K~D

12

PR222 0_0603_5%~D

1 2

PQ23

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

PC149

1U_0805_25V4Z~D

1 2

PQ35

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

PR145

499K_0603_1%

@

1 2

PR136

499K_0603_1%

@

1 2

PC119

10U_1210_25V6K~D

12

PR219

10K_0402_5%~D

12

PC134

0.01U_0603_16V7K~D

12

PR148

32.4K_0603_1%~D

12

PU13

ISL6207CB-T_SO8~D

BOOT 2

PWM

3

VCC

6

EN

7

LGTE 5

GND

4

PHSE 8

UGTE 1

PU12

ISL6207CB-T_SO8~D

BOOT 2

PWM

3

VCC

6

EN

7

LGTE 5

GND

4

PHSE 8

UGTE 1

PC205

0.1U_0603_25V7M~D

12

PC159

0.15U_0805_16V7K~D

1 2

PQ25

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PL19

0.56U_ETQP4LR56WFC_21A_20%~D

1 2

PC207

2200P_0603_50V7K~D

12

PL16

0.56U_ETQP4LR56WFC_21A_20%~D

1 2

PU18

AD7414ART-0_SOP23-6

SDA 6

ALERT 5

SCL 4

AS

1

GND

2

VDD

3

PQ34

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

PR157

32.4K_0603_1%~D

12

PR125

0_0603_5%~D

1 2

PQ22

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

PR151

820_0603_1%~D

12

PC145

0.15U_0805_16V7K~D

1 2

PQ32

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PC151

0.01U_0603_16V7K~D

12

PC204

0.1U_0603_25V7M~D

12

PQ48

FDS7064N_SO8

@

3 6

5

7

8

2

4

19

PC152

0.15U_0805_16V7K~D

1 2

PC132

0.1U_0603_16V7K~D

1 2

PC202

0.1U_0603_25V7M~D

12

PQ31

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

+

PC144

15U_D2_25M_R90~D@

1

2

PU11

ISL6207CB-T_SO8~D

BOOT 2

PWM

3

VCC

6

EN

7

LGTE 5

GND

4

PHSE 8

UGTE 1

PC113

0.15U_0805_16V7K~D

12

PC210

0.1U_0402_16V4Z~D

12

+

PC143

15U_D2_25M_R90~D@

1

2

PQ24

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PQ30

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

+

PC141

15U_D2_25M_R90~D@

1

2

PC131

1000P_0603_50V7K~D

@

12

PQ27

SI4362DY_SO8~D

3 6

5

7

8

2

4

1

PC116

10U_1210_25V6K~D

12

PR213

0_0603_5%~D

12

PQ55

FDS7064N_SO8@

3 6

5

7

8

2

4

19

PC206

2200P_0603_50V7K~D

12

PC160

1U_0603_6.3V6M~D

12

PC117

10U_1210_25V6K~D

12

PR160

820_0603_1%~D

1 2

+

PC138

15U_D2_25M_R90~D@

1

2

PR153

0_0603_5%~D

12

PC157

1U_0805_25V4Z~D

1 2

PQ33

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

PR133

820_0603_1%~D

12

PR134

0_0603_5%~D

1 2

PR212

0_0603_5%~D

12

PR210

0_0603_5%~D

12

PC148

1000P_0603_50V7K~D

@

12

PR154

499K_0603_1%

@

1 2

PC162

1000P_0603_50V7K~D

@

12

PU14

ISL6207CB-T_SO8~D

BOOT 2

PWM

3

VCC

6

EN

7

LGTE 5

GND

4

PHSE 8

UGTE 1

PL18

0.56U_ETQP4LR56WFC_21A_20%~D

1 2

PR138

@

2.2_0805

1 2

PC123

10U_1210_25V6K~D

12

PQ21

IRF7811W_SO8~D

3 6

5

7

8

2

4

1

+

PC135

15U_D2_25M_R90~D

@

1

2

+

PC137

15U_D2_25M_R90~D@

1

2

PC161

10U_1210_25V6K~D

12

PC114

1U_0603_6.3V6M~D

12

PQ51

FDS7064N_SO8@

3 6

5

7

8

2

4

19

PR139

32.4K_0603_1%~D

12

+

PC139

15U_D2_25M_R90~D@

1

2

PC121

10U_1210_25V6K~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DCIN

DLO

CSSP

CHG_CS

CSSN

CCV

1645_DAC

CHVREF

TM

TH

CSIN

CSIP

ACOK

ACOK

CHVREF

CHVREF

ACAV

DLOV

+SDC_IN

+5VALW

DC_IN+

+SDC_IN

PBATT+

PBATT+

+5VALW +RTC_PWR

DC_IN+

CHAGER_SRC

CHG_PBATT <34>

PBAT_SMBCLK<34,42>

PBAT_SMBDAT<34,42>

ACAV<34,39,49>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

48 54Tuesday, March 18, 2003

Compal Electronics, Inc.

CHARGER CONTROL

VMAX=3.49V

Maximum charger voltage=17.45V

IMAX=1.6V

Maximum charger current=8A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PQ37

FDS6679Z

36

5

7

82

4

1

PR170

12.7K_0603_1%~D

12

PC177

0.1U_0805_50V7M~D

1 2

PR182

31.6K_0603_0.1%~D

12

PC193

1U_0805_25V4Z~D

1 2

PC195

0.1U_0603_25V7K~D

1 2

PR185

280K_0603_1%~D

12

PC176

0.1U_0805_50V7M~D

1 2

PC187

4.7U_1210_25V6K~D

12

PR183

1_0603_1%~D

1 2

PR188

10K_0603_1%~D

1 2

G

D

S

PQ40

BSS138_SOT23~D

2

13

PU6

MAX1535X_QFN32~D

DHI 26

CSIN 20

DLO 23

SDA

14

CCS

6

CCV

8

CSSP 29

PDS

31

THM

13

VDD

12

SRC

27

ACIN

3

ACOK

32

DCIN

1

CCI

7

LDO 2

VMAX 9

BATT 19

DLOV 24

PDL 30

DHIV 25

CSSN 28

SCL

15

/INT

16

CSIP 21

PGND 22

DAC

11

REF

4

GND

18

IMAX

10

GND

5

I.C. 17

PR178

10K_0603_5%~D

12

PR174

100K_0603_5%~D@1 2

PR169

1K_0603_5%~D

1 2

+

PC173

@15U_D2_25M_R90~D

1

2

PC169

0.1U_0805_25V7K~D

1 2

PQ36

2SA1036K_SOT23~D

2

31

PR187

10K_0603_1%~D

1 2

PU15

AS2431_SOT23~D

1 3

2

PR191

100K_0603_5%~D

1 2

PD23

RB751V-40_SOD323~D

21

PR177

0.01_2512_1%~D

1 2

PC211

10U_1210_25V6K~D

12

PC213

10U_1210_25V6K~D

12

PC172

0.01U_0603_50V7K~D

1 2

+

PC184

15U_D2_25M_R90~D

@

1

2

PR186

1_0603_1%~D

1 2

PC171

1U_0603_6.3V6M~D

1 2

PR184

182K_0603_1%~D

1 2

PD20

RB751V-40_SOD323~D

21

PC168

1U_0805_25V4Z~D

1 2

PC212

10U_1210_25V6K~D

12

PC188

4.7U_1210_25V6K~D

12

PR179

10K_0603_5%~D

12

PR181

1.2K_1206_5%~D@

1 2

PC174

0.1U_0603_25V7K~D

12

PC166

10U_1210_25V6K~D

12

PC185

0.1U_0603_25V7K~D

1 2

PD22

EC31QS04~D

2 1

PR172

100K_0603_5%~D

@

1 2

PR175

33_0603_5%~D

1 2

PR189

182K_0603_0.1%~D

1 2

PR161

75K_0402_1%~D

12

PR173

75K_0402_1%~D

12

PC175

2200P_0603_50V7K~D

12

PR164

10K_0603_1%~D

1 2

PC183

0.01U_0603_50V7K~D

12

PL22

MCK4532800YAT_1812

12

PR162

1K_0603_5%~D

12

PC192

1500P_0402_50V7K~D

1 2

PC182

1U_0805_25V4Z~D

12

PC194

0.1U_0603_25V7K~D

1 2

PR167

4.7 _0402_1%~D

1 2

PC190

4.7U_1210_25V6K~D

12

PR168

1M_0603_5%~D

1 2

PR190

2K_0603_1%~D

1 2

PC181

0.01U_0603_50V7K~D

1 2 PR176

10K_0603_5%~D

1 2

PQ38

FDS6672A_SO8~D

3 6

5

7

8

2

4

1

PR166

4.7 _0402_1%~D

1 2

PC189

0.1U_0805_50V7M~D

1 2

PC180

0.01U_0603_50V7K~D

1 2

PR171

100K_0603_5%~D

12

PC170

0.1U_0805_25V7K~D

1 2

PL20

3.2UH_12.8A

1 2

PC186

1U_0603_6.3V6M~D

1 2

PR165

0.01_2512_1%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+SDC_IN

PWR_SRC

PWR_SRC

PBATT+

ACAV<34,39,48>

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

49 54Tuesday, March 18, 2003

Compal Electronics, Inc.

Battery Discharge

DC_IN+ discharge path

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

G

D

S

PQ42

BSS138_SOT23~D

2

13

PR199

100K_0603_5%~D

12

PR198

10K_0603_5%~D

12

G

D

S

PQ43

BSS138_SOT23~D

2

13

PR200

2K_0603_1%~D

12

1SS355_SOD323~D

PD27

2 1

PC199

2200P_0603_50V7K~D

12

PR197

10K_0603_5%~D

1 2

RB083L-20_SOD106~DPD26

2 1

PR202

470K_0603_5%~D

12

PQ44

SI7447DP_SO8

3

2

4

1

5

PQ41

SI7447DP_SO8

3

2

4

1

5

PR201

100K_0603_5%~D

12

PC200

0.1U_0805_50V7M~D

1 2

RB083L-20_SOD106~D

PD25

@

2 1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SUB_GAIN0

SUB_GAIN1

SUB_VREF

SUB_SHUTDOWN#

SUB_VREF

SUB_OUT1AUD_MONO_OUT

SUB_SHUTDOWN#

SUB_GAIN0

SUB_GAIN1

SUB_OUT2

+3VRUN

+3VRUN

+12V

+12V

+12V

SUB_DETECT<42>

SPK_SHUTDOWN#<24,25>

AUD_MONO_OUT<24> SUB_OUT1 <42>

SUB_OUT2 <42>

Title

Size Document Number R ev

Date: Sheet of

LA-1711

X00-G

Subwoofer

50 54Tuesday, March 18, 2003

Gain Setting

Need to FILTER!!!

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Link CIS

20.2

D20 DIODES B130

C652

0.22U_0603_10V7M~D

1 2

C641

0.1U_0402_16V4Z~D

1

2

R596

100K_0402_5%~D@

12

C645

0.22U_0603_10V7M~D

1 2

R593

100K_0402_5%~D @

12

C650

1U_0805_10V6K~D

12

R594

51_0603_1%

1 2

C644

0.22U_0603_10V7M~D

1 2

C640 0.1U_0402_16V4Z~D

1 2

R595

120K_0402_5%~D

12

C651

1U_0805_10V6K~D

1

2

C643

0.22U_0603_10V7M~D

1 2

C654

220P_0402_50V8J~D

1

2

U45

TPA3001D1

INN

1

INP

2

GAIN0

3

GAIN1

4

SHDN-

5

PGND

6

VCLAMP

7

BSN 8

PVCC 9

OUTN 10

OUTN 11

PGND

12

PGND

13

OUTP 14

OUTP 15

PVCC 16

BSP 17

AGND

18

AGND

19

RSOC

20

CSOC

21

BYPASS

22

VREF

23

VCC

24

U44

TC7SH08FU_SSOP5~D

B

1

A

2

G

3

O4

P5

R597

100K_0402_5%~D

12

C649

1000P_0402_50V7K~D

1

2

C647

1000P_0402_50V7K~D

1

2

R589

10K_0402_5%~D

12

R592

100K_0402_5%~D

12

R591

51_0603_1%

1 2

C655

1000P_0402_50V7K~D

1 2

C653

1U_0805_25V4Z~D

1

2

D21

DIODES B130

C648

1U_0805_10V6K~D

1 2

R590

10K_0402_5%~D

12

C646

1U_0805_10V6K~D

12

C642

10U_1206_16V4Z~D

1

2

L50

BLM21PG600SN1D_0805~D

1 2

L49

BLM21PG600SN1D_0805~D

1 2

G

D

S

Q74

2N7002_SOT23~D

2

13

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

EE_P.I.R History

51 54Tuesday, March 18, 2003

So

SoSo

Solution Description

lution Descriptionlution Description

lution Description R

RR

Rev.

ev.ev.

ev.

Compal2/17/2003

Page#

Page#Page#

Page#

18

Correct R367,R109 from 40.2_0603_1% to 42.2_0603_1%

(M00 R109,R367 are mount 42.2_0603_1%)

ITP Connector default depopulate Depop RN8 (RN8 is populted on M00)

T

TT

Title

itleitle

itle

Prescott

Processor

Version Chang

Version ChangVersion Chang

Version Change List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

e List ( P. I. R. List )

It

ItIt

Item

emem

em Is

IsIs

Issue Description

sue Descriptionsue Description

sue DescriptionD

DD

Date

ateate

ate Reque

RequeReque

Request

stst

st

O

OO

Owner

wnerwner

wner

X00-A

Resistor value SPEC isn't meet Intel recommendSpringdale-

DDR Interface

2

21 ICH5-IDE/LPC/

PM/GPIO/LAN Swap IDE_PDCS1# and IDE_PDCS3#;

Swap IDE_SDCS1# and IDE_SDCS3#.

11 2/17/2003

3 Compal

Compal

4 23 D-MODULE Compal +3.3VMOD power net no power source.we have two signal names

for +3.3VMOD /+3VMOD, need jump wire.

Correct power net from +3.3VMOD to +3VMOD

5 23 D-MODULE

2/17/2003

2/17/2003

2/17/2003 DELL Need to cross the TX and RX lines on the motherboard side Change JMOD1 pin8 from SATA_MODTX+ to SATA_MODRX+

Change JMOD1 pin10 from SATA_MODTX- to SATA_MODRX-

Change JMOD1 pin14 from SATA_MODRX+ to SATA_MODTX+

Change JMOD1 pin16 from SATA_MODRX- to SATA_MODTX-

6 26 USB(2.0)

Connector 2/17/2003 DELL Del all mark "2@" symbol, All components default must

populate. Nimitz and Beijing both are support Dog House. Del all mark "2@" symbol, All components default must

populate. (All mark"2@" components are populate on M00 Board)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

7 37 Thermtrip &

PowerGOOD 2/17/2003 Compal

No generate system clock.

VCORE_PWRGD signal add a 10K_0402_5%(R581) resistor pull up

to +3VSUS.

Compal Electronics, Inc.

Dell M00 Board Bring up issue item3:

U25 Pin1 and Pin 2 need to be shorted together, VCORE_PWRGD is

an OD signal and it does not have a pullup.

ICH5 PIN Y18, A19 are swapped on JHDD in the schematics and

Pins V20, V22 are also swapped. HDD can't boot.

Dell M00 Board Bring up issue item4:

Dell M00 Board Bring up issue item5:

8 25 AMP and

PHONE JACK 2/27/2003 DELL Change OP amplifier power from +12V to +5V ,change audio

amplifier as same as Abacus-MT Change audio amplifier from TPA3002D2PHP to TI6017A2

(BOM need change) X00-C

9 29 LAN Transfomer 2/27/2003 DELL ME Connectors are interfere Change RJ11/RJ45 receptacle connector to staddle type

10 18 VGA Daughter

Board Conn. 3/05/2003 Compal

Change AGP connector vendor

Change connector from ACES_88075-1600 to FOXCONN

FOXCONN_QT00160A-9120L (BOM need change)

X00-A

X00-A

X00-A

X00-A

X00-A

X00-A

X00-C

X00-DDell EE issue item38:

11 6,34,36 Clock Generator 3/05/2003 DELL

This change is required due to not getting the 24MHz clk

of the EC to work.

Dell EE issue item22: 1.Del 24M_CLK net and R210(33_0402_5%)

2.Add series termination R587(33_0402_5%) near CK409 and

R588(0_0402_5%) near the CPLD. Add net name from CK409 to

CPLD. (BOM need change)

12 8 Prescott

Processor 3/05/2003 DELL Dell EE issue item23: To prevent backdrive in S3 Change RN7,R35,R37 pullups from +3VSUS to +3VRUN.

13 21 ICH5-IDE/LPC/

PM/GPIO/LAN 3/05/2003 DELL Dell EE issue item25: This pin is not 5V tolerant. Change R388 pullup from +5VRUN to +3VRUN.

14 33,36 SIO (1/2) & PLD 3/05/2003 DELL Dell EE issue item26:

Change name of the follow signal from GV_LO_HI# to GV_HI_LO#

Change name of the follow signal from GV_LO_HI# to GV_HI_LO#

X00-D

X00-D

X00-D

X00-D

15 25 AMP and Phone

Jack Interface 3/05/2003 DELL Dell EE issue item39:

1.Change the population option for R583 and R584 to no pop

2.Change the voltage rai lto D7, D6, D9, D8 to +5VRUN

1.R583,R584 Add "@" symbol and depop.

2.Change power from +12V to +5VRUN. X00-D

16 18 VGA Daughter

Board Conn. 3/05/2003 DELL

Table for ST1 and ST2, were did this table come from?

Delete ST1,ST2 table and R324~R327 (BOM need change) X00-D

17 12 Springdale-AGP

/HUB/VGA/CSA 3/05/2003 DELL

Dell EE issue item37:

Dell EE issue item36:

AGP8X_DET_GC circuit need to change per the errata change.

Change Q13 from MMBT3904 to 2N7002; R55 from 33.2_0603_1% to

39.2_0603_1% (BOM need change) X00-D

Pag

PagPag

Page 1/3

e 1/3e 1/3

e 1/3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

EE_P.I.R History

52 54Tuesday, March 18, 2003

So

SoSo

Solution Description

lution Descriptionlution Description

lution Description R

RR

Rev.

ev.ev.

ev.

Compal3/07/2003

Page#

Page#Page#

Page#

18 21 HDD pinout are reversed Change pinout and and connector part number(BOM need change)

T

TT

Title

itleitle

itle

Version Chang

Version ChangVersion Chang

Version Change List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

e List ( P. I. R. List )

It

ItIt

Item

emem

em Is

IsIs

Issue Description

sue Descriptionsue Description

sue DescriptionD

DD

Date

ateate

ate Reque

RequeReque

Request

stst

st

O

OO

Owner

wnerwner

wner

X00-E

Pag

PagPag

Page 2/3

e 2/3e 2/3

e 2/3

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

2319

ICH5-IDE/LPC/

PM/GPIO/LAN

D- MODULE 3/07/2003 Compal Change D- Module connector (Mating Height issue) X00-E

20 26 USB(2.0)

Connector 3/07/2003 Compal Change connector to staddle type. Foxconn Fox_UB11193-P01-TR

(BOM need change)

Change connector from JAE_WM1F068N1A to Foxconn

QL11343-A6B3-HT

ME Connectors are interfere X00-E

21 Springdale-DDR

Interface

11 3/07/2003 Compal

SMXRCOMPVOH - add 0.1UF cap from +2.5V (pin2 of C65) to GND

Dell M00 Board Bring up issue item34,35:

SMYRCOMPVOH - add 0.1UF cap from +2.5V (pin2 of C53) to GND

Add C636 and C637(0.1U_0402_16V4Z) [BOM need change] X00-E

22 Dell M00 Board Bring up issue item27

Need to change PLD pinout per the right package program.

Follow CPLD rework instruction, correct U27 symbol pin out. X00-E3/08/200336 PLD DELL

23 36 PLD 3/08/2003 DELL Dell M00 Board Bring up issue item28

Eliminate the VID MUX and keep the zero Ohm resistors

Del U1,C10,R14,R18,RP1,R13 (BOM need change) X00-E

24 8,18,36 3/08/2003 DELL Dell M00 Board Bring up issue item24

Change the table on pg 36 to reflect the correct refdes and

components see PLD rework instructions

Page36: Pop U27, C233, C606, R557 ;Pop Q42, R254, Depop R259 ;

Pop Q43, R561, Depop R251,R243 ; Pop R256, Depop R252; pop

R245, R253

Page18: Depop R96, Pop R98

Page8 :Pop R76,R78,R380

Page46: PR94,PR93, Depop PR95,PR92 [BOM need change]

X00-E

25 8 Prescott

Processor 3/12/2003 DELL Dell M00 Board Bring up issue item32

Depop pullup R84 on H_RESET# since we have another pullup R358

Depop R84 ,62_0402_5%(BOM need change) X00-F

26 11 Springdale-DDR

Interface 3/12/2003 DELL Value is not correct Change C636,C637 (0.01U_0402_16V7K) [Add it on BOM]

27 14 FAN CONTROL 3/12/2003 Compal ME connector design change Change JFAN2 from MOLEX_53261-0310 to MOLEX_53398-0390; Delete

JFAN1 [BOM need change]

28 15,19 CPU Thermal

Sensor & FAN

Control

3/12/2003 DELL To saving cost Delete U35(AD7414ART-0),R345(10K_0402_5%),R348(0_0402_5%),

C383(0.1U_0402_16V4Z); Add Q73(MMBT3904) [BOM change]

29 19 CPU Thermal

Sensor & FAN

Control

3/12/2003 Compal ME connector design change Change JFAN3 from MOLEX_53261-0310 to SUYIN_250019MR003G400ZL

[BOM need change]

30 25

X00-F

X00-F

X00-F

X00-F

AMP and

PHONE JACK 3/12/2003 Compal ME connector design change for phone Jack and Int.SPK Change JSPK from MOLEX_53261-0690 to MOLEX_53398_0890;

change JP1 from HRS_DF20-10DP-1V to NAIS_AXN320C038P; Add

C638,C639(22U_1206_16V4Z) [BOM need change]

X00-F

31 24,25,50 Subwoofer 3/12/2003 DELL Add Subwoofer circuit Page24: U16 pin37 connect to C646 pin1(AUD_MONO_OUT)

Page25: Del R586(100K_0402_5%) [BOM need change]

Page50 : Add subwoofer circuit [Add ]

X00-F

32 31 CardBus Socket 3/12/2003 DELL All model support smart card function Update page3 Table and change mark "1@" symbol to "@" X00-F

33 21 ICH5-IDE/LPC/

PM/GPIO/LAN 3/12/2003 DELL Follow Intel DG (12837)ICH_SYNC# circuit implementation Depop R161,R167,R169,Q32,Q33 and pop R438(0_0402_5%) [BOM

need change] X00-F

34 31 CardBus Socket 3/13/2003 Compal X00-GCorrect Item32 Populate U17 and L14, delete "1@" symbol [Don't need change

BOM]

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

EE_P.I.R History

53 54Tuesday, March 18, 2003

Page3

Page3Page3

Page3/3

/3/3

/3

So

SoSo

Solution Description

lution Descriptionlution Description

lution Description R

RR

Rev.

ev.ev.

ev.

Compal3/14/2003

Page#

Page#Page#

Page#

35 27,31 Page27 :Change JMDC from FOX_QT8A0301-3011 to AMP_3-1612118-0

Page31: Change JCBUS form FCI_61082-081001 to

FOX_1CA87501-T1~D; Change J1394 from FOX_UV31413-K8 [BOM need

change]

T

TT

Title

itleitle

itle

Version Chang

Version ChangVersion Chang

Version Change List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

e List ( P. I. R. List )

It

ItIt

Item

emem

em Is

IsIs

Issue Description

sue Descriptionsue Description

sue DescriptionD

DD

Date

ateate

ate Reque

RequeReque

Request

stst

st

O

OO

Owner

wnerwner

wner

X00-GME connector design change

36 31 CardBus Socket 3/14/2003 DELL

Please add a 100PF cap to SC_DATA_C per TI late recommendation

Dell Schematic issue item12 Add C656(100P_0402_50V7K). [BOM need change] X00-G

37 Prescott

Processor

8 3/14/2003 DELL H_DPSLP# doubule pull up Depop R79(62_0402_5%) , [BOM need change] X00-G

38 25 AMP and

PHONE JACK 3/14/2003 DELL Dell Schematic issue item48

Remove comment above U18 and remove the wires in the bottom

Connect C638 and C639 to INT_TWT_R1 and INT_TWT_L1 at JSPK X00-G

39 25 AMP and

PHONE JACK 3/14/2003 DELL Dell Schematic issue item48

Change the pinout of JAUDO

Change net FAN1_TACH_FN from pin16 to pin18, pin15,16 connect

to GND X00-G

40 29 LAN TRANSFOMER 3/14/2003 DELL Dell Schematic issue item45,46

the BJT werent driving the LED enough

X00-G1.Change Q3 from DTC144KA_SOT23 to 2N7002

2.LED_WLAN5_RADIOSTATE, LED_WLAN24_RADIOSTATE, and

WLAN_LED_ACIVITY. Add 10K_0402_5% pulldown resistor(R600~R602)

[BOM need change]

41 Dell Schematic issue item48

50 Subwoofer 3/14/2003 DELL Move D18 and D19 to page 42, and update all component Symbols

Move D18 and D19 to page 42, and update all component

Symbols , move C655 from current location to in between

C645 and U45 pin 2 and change value to 1000P_0402_50V7K

X00-G

42 6 Clock Generator 3/14/2003 DELL Dell Schematic issue item30

Springdale DG P65 recommed a 10 Ohm resistor from CK_VDD_MAIN

to Pin VDD_48 (pin34) of Ck409

Reserved power source option: populate R589, depopulate R599

[BOM need change] X00-G

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Delete by Dell's update issue_0314 ;X00-H

43 Springdale-DDR

Interface

11 3/18/2003 Compal Intel recommend is 31.12K,the value isn't popularize.

Follow Dell's DT team use 30.9K Change R101,106,369,373 from 31.12K_0603_1% to 30.9K_0603_1%

;[BOM need change] X00-H

44 25 AMP and

PHONE JACK 3/18/2003 Compal Add one net for Phone Jack board pullup source. Change JAUDO pin11 from NC to AMPVCC X00-H

45 36,39,40 3/18/2003 Compal Single name issue Delete pin 22 of U27 net and show text ; move U25B from page39

to page40, change pin4,5 to GND and pin6 to NC. X00-H

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-1711

X00-G

Power_P.I.R History

54 54Tuesday, March 18, 2003

So

SoSo

Solution Description

lution Descriptionlution Description

lution Description R

RR

Rev.

ev.ev.

ev.

Compal2/26/2003

Page#

Page#Page#

Page#

145

Add voltage divider at +5VSUSP(PR227, PR229)

Add voltage divider at +3VSRCP(PR228, PR230)

Make SUSPOWROK_5V a strong pullup.

Depop PR86 (PR86 is populted on M00)

T

TT

Title

itleitle

itle

1.25V/2.5V

POWER Version Change

POWER Version Change POWER Version Change

POWER Version Change List ( P. I. R. List )

List ( P. I. R. List )List ( P. I. R. List )

List ( P. I. R. List )

It

ItIt

Item

emem

em Is

IsIs

Issue Description

sue Descriptionsue Description

sue DescriptionD

DD

Date

ateate

ate Reque

RequeReque

Request

stst

st

O

OO

Owner

wnerwner

wner

X00-B

Need to add pads for voltage/temp tolerance measurements.

Request from our Reliability engineers.

3.3V/5V2

46,47 CPU_CORE_Controller

CPU_CORE_Power-Stage Change PU9 and PU11, PU12, PU13, PU14 VCC

to +5VRUN

43 2/26/2003

3 DELL

DELL

2/26/2003

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Compal Electronics, Inc.

X00-B

X00-B

Dell M00 Board Bring up issue item21:

Dell M00 Board Bring up issue item13:

Dell M00 Board Bring up issue item29:

Change CPU controller and driver VCC to +5VRUN

to reduce S3 current.

4 46 CPU_CORE_Controller X00-D3/05/2003 DELL Dell X00 Board issue item40,41:

Change the power rail to the following components PR99,

PU20A/B, PC214 from +5VSUS to +5VRUN

Change the power rail to the following component PR114

from +3VSRC to +3VRUN

Change the power rail of PR99 and PU20A/B,

PC214,PR97 from +5VSUS to +5VRUN

Change the power rail of PR114 from +3VSRC to +3VRUN

5 44,45 +1.5VRUNP/ +VTT_GMCHP

1.25V/2.5V

3/07/2003 DELL Intersil ISL6225B IC issue. So change controller IC. Change PU7 to SC1485 and PU8 to SC1486. X00-E

6 45 1.25V/2.5V 3/12/2003 DELL Dell X00 Board issue item47:

Intle in the DG 1.21 update have changed the DDR voltage

to 2.6V and Term voltage to 1.3.

Change PR72 to 42.2K X00-F

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