Compal LA 2771 Schematics. Www.s Manuals.com. R0.8 Schematics
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A B C D E 1 1 Compal confidential 2 2 Schematics Document AMD K8 with ATI RS480M+ATI SB400 3 3 2005-08-29 REV:0.8 4 4 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 1 of 53 A B C D E Compal confidential File Name : LA-2771 Memory BUS(DDR) DDR-SO-DIMM-0 Mobile AMD Athlon 64 Thermal Sensor ADM1032 1 page 4 2. 5V DDR- 400 754 pin DDR-SO-DIMM-1 page 4, 5, 6, 7 Fan Control 1 BANK 0, 1, 2, 3 page 8,10 Clock Generator ICS 951412 BANK 0, 1, 2, 3 page 9,10 page 4 2. 5V DDR- 400 page 16 HT 16x16 1000MHZ 1 x PCIE LVDS Panel Interface page New Card Connector page ATI-RS480M 27 17 705 BGA TV tuner page 11, 12, 13, 14 CRT & TV OUT 2 page 18 2 x PCIE USB conn X3 page 34 USB2.0 Side Port(VRAM) 16M x 16 page 15 ATI-SB400 BT Conn AC-LINK page 34 ATA-100 Primary IDE PCI BUS 3.3V 33 MHz 564 BGA Audio CKT AMOM page page 19, 20, 21, 22 MINI PCI page 30 LAN RTL 8100CL LPC BUS page 25,26,27 page 29 MODEM AMOM page 31 PATA HDD Connector CardBus Controller TI PCI7411/PCI1510 2 page 34 A-Link Express 32 AMP & Audio Jack page 33 page 24 3 3 CDROM Connector RTC CKT. RJ45 CONN page 19 page 29 Slot 0 1394 page 27 page 25 Card reader page 24 ENE KB910/L page 26 page 37, 38 SPR CONN. Power OK CKT. page 42 Touch Pad Int.KBD page 35 page 35 Power On/Off CKT. BIOS page 35 4 *RJ45 CONN *MIC IN JACK *LINE OUT JACK *1394 CONN *SPDIF CONN *DC JACK *TVOUT CONN *USB CONN x1 *CIR x1 page 39 DC/DC Interface CKT. Power Circuit DC/DC Compal Secret Data Security Classification 2005/03/01 Issued Date page 43~49 2005/04/06 Deciphered Date B C Title Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 4 page 40 page 41 D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 2 of 53 A BOM STATUS : Voltage Rails VRAM@ ,VRAMIC@, SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@ ,15_EXO@,CIR@ ,D@, C@, 15.4@, DOCK@, WL_LED@ +5VS power plane +3VS +12VALW +5V +5VALW +2.5V +3VALW +1.25V +1.8VALW State +2.5VS +1.8VS +1.5VS +2.5VDDA 45@ ( for 45 level RTC battery ) +CPU_CORE +1.2V_HT S0 O O O S1 O O O S3 O O X S5 S4/AC O X X X X X HAL10 17" VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@ ,CIR@ ,D@ ,DOCK@,WL_LED@ HAL20 FF 15.4" VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,15_EXP@ ,CIR@ ,C@ ,DOCK@,WL_LED@, 15.4@(LED) HAL20 DF 15.4" EXP@, C@ ,DOCK@ ,15.4@(LED), CIR@, WLAN@, 15_EXP@ S5 S4/AC don't exist O MEANS ON X MEANS OFF PCI Devices 1 1 INTERNAL DEVICE IDSEL # REQ/GNT # PIRQ SM BUS IDE A LPC I/F PCI to PCI B AC97 AUDIO A C97 MODEM B OHCI#1 USB D OHCI#1 USB D EHCI USB D SAT A#1 A SAT A#2 A EXTERNAL Wire less LAN AD18 3 F LAN AD22 1 G CARD BUS & 1394 AD20 2 E ,H Compal Secret Data Security Classification 2005/03/01 Issued Date Deciphered Date 2005/04/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Notes List Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 3 of 53 A B C D E ZZZ1 L A -2771 REV 0 <11> H_CADIP[0..15] <11> H_CADIN[0..15] H_CADIP[0..15] H_CADOP[0..15] H_CADIN[0..15] H_CADON[0..15] 4 H_CADOP[0..15] <11> H_CADON[0..15] <11> Fan Control Circuit 4 JP1A +5VS 3 B+ 1 -IN 1 2 5 6 FAN1_ON 1 OUT Q1 SI3456DV-T1_TSOP6 3 R1 10K_0402_5% S U1A LM358A_SO8 1 +IN 2 G 4 EN_FAN1 3 +3VS D P <37,38> 2 C1 10U_1206_16V4Z 8 C2 0.1U_0402_16V4Z 2 1 2 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 G JP2 R3 150K_0402_5% D1 1N4148_SOT23 @ 2 2 2 1 1 2 3 C4 10U_0805_10V4Z 1 1 C3 1000P_0402_50V7K FAN1 1 2 R2 100K_0402_5% 3 N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29 4 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 1 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 2 T25 R25 U27 U26 V25 U25 W27 W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25 T27 T28 V29 U29 V27 V28 Y29 W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28 HTT Interface Claw Hammer-DTR H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H _CADIN9 H_CADIP8 H _CADIN8 H_CADIP7 H _CADIN7 H_CADIP6 H _CADIN6 H_CADIP5 H _CADIN5 H_CADIP4 H _CADIN4 H_CADIP3 H _CADIN3 H_CADIP2 H _CADIN2 H_CADIP1 H _CADIN1 H_CADIP0 H _CADIN0 ACES_85205-0300 3 <37,38> FAN_SPEED1 1 @ C5 1000P_0402_50V7K +1.2V_HT R4 R5 +1.2V_HT R6 R7 <11> <11> <11> <11> H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 49.9_0402_1% 2 49.9_0402_1% 2 <11> <11> 1 1 H_CTLIP0 H_CTLIN0 44.2_0603_1% 2 44.2_0603_1% 1 1 2 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 Y25 W25 Y27 Y28 H_CTLIP0 H_CTLIN0 R27 R26 T29 R29 LVREF1 LVREF0 AF27 AE26 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_REF1 L0_REF0 LDTSTOP_L J26 J27 J29 K29 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 N25 P25 P28 P27 H_CTLOP0 H_CTLON0 AJ27 LDTSTOP# H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 2 H_CTLOP0 <11> H_CTLON0 <11> LDTSTOP# <13,19> 1 2 R8 680_0402_5% FOX_PZ75403-2941-42 <11> <11> <11> <11> +2.5VS Thermal Sensor ADM1032 THERMDA_CPU THERMDC_CPU THERMDA_CPU <6> THERMDC_CPU <6> +3VS 2 2 W =1 5mil U2 <37,38> EC_SMC_2 <37,38> EC_SMD_2 EC_SMC_2 8 EC_SMD_2 7 6 5 2 SCLK VDD SDATA D+ ALERT# GND DTHERM# 1 2 THERMDA_CPU 3 THERMDC_CPU 1 2 C7 1 C6 0.1U_0402_16V4Z 2200P_0402_50V7K 4 ADM1032AR_SOP8 1 1 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title Claw Harmmer & Fan THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 4 of 53 A B C D E 50 mil width/20 mil space +1.25VREF_CPU JP1B 3 <8> DDR_SDM[0..7] DDR_SDM7 DDR_SDM6 DDR_SDM5 DDR_SDM4 DDR_SDM3 DDR_SDM2 DDR_SDM1 DDR_SDM0 <8> DDR_SDQS[0..7] DDR_SDQS7 DDR_SDQS6 DDR_SDQS5 DDR_SDQS4 DDR_SDQS3 DDR_SDQS2 DDR_SDQS1 DDR_SDQS0 MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0 R1 A13 A7 C2 H1 AA1 AG1 AH7 AH13 T1 A14 A8 D1 J1 AB1 AJ2 AJ8 AJ13 MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0 Claw Hammer-DTR 1 MEMCKEA MEMCKEB MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0 AE8 AE7 DDR_CKE0 DDR_CKE1 D10 C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4 DDR_CLK7 DDR_CLK7# DDR_CLK6 DDR_CLK6# DDR_CLK5 DDR_CLK5# DDR_CLK4 DDR_CLK4# MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0 D8 C8 E8 E7 D6 E6 C4 E5 DDR_SCS#3 DDR_SCS#2 DDR_SCS#1 DDR_SCS#0 MEMRASA_L MEMCASA_L MEMWEA_L H5 D4 G5 DDR_SRASA# DDR_SCASA# DDR_SWEA# MEMBANKA1 MEMBANKA0 K3 H3 DDR_SBSA1 DDR_SBSA0 MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10 MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5 DDR_SMAA13 DDR_SMAA12 DDR_SMAA11 DDR_SMAA10 DDR_SMAA9 DDR_SMAA8 DDR_SMAA7 DDR_SMAA6 DDR_SMAA5 DDR_SMAA4 DDR_SMAA3 DDR_SMAA2 DDR_SMAA1 DDR_SMAA0 H4 F5 F4 DDR_SRASB# DDR_SCASB# DDR_SWEB# L5 J5 DDR_SBSB1 DDR_SSB0 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3 DDR_SMAB13 DDR_SMAB12 DDR_SMAB11 DDR_SMAB10 DDR_SMAB9 DDR_SMAB8 DDR_SMAB7 DDR_SMAB6 DDR_SMAB5 DDR_SMAB4 DDR_SMAB3 DDR_SMAB2 DDR_SMAB1 DDR_SMAB0 MEMRASB_L MEMCASB_L MEMWEB_L MEMBANKB1 MEMBANKB0 MEMADDB_B13 MEMADDB_B12 MEMADDB_B11 MEMADDB_B10 MEMADDB_B9 MEMADDB_B8 MEMADDB_B7 MEMADDB_B6 MEMADDB_B5 MEMADDB_B4 MEMADDB_B3 MEMADDB_B2 MEMADDB_B1 MEMADDB_B0 MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0 DDR_CKE0 <8> DDR_CKE1 <9> DDR_CLK7 <8> DDR_CLK7# <8> DDR_CLK6 <9> DDR_CLK6# <9> DDR_CLK5 <8> DDR_CLK5# <8> DDR_CLK4 <9> DDR_CLK4# <9> DDR_SCS#3 DDR_SCS#2 DDR_SCS#1 DDR_SCS#0 DDR_CLK7 R12 1 2 120_0402_5% DDR_CLK7# DDR_CLK6 R13 1 2 120_0402_5% DDR_CLK6# DDR_CLK5 R14 1 2 120_0402_5% DDR_CLK5# DDR_CLK4 R15 1 2 120_0402_5% DDR_CLK4# <9> <9> <8> <8> DDR_SRASA# <8> DDR_SCASA# <8> DDR_SWEA# <8> 2 +2.5V DDR_SBSA1 <8> DDR_SBSA0 <8> R16 DDR_SMAA[0..13] <8> 1 2 MEMZN MEMZP A16 B15 A12 B11 A17 A15 C13 A11 A10 B9 C7 A6 C11 A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3 J2 L2 M1 W1 W3 AC1 AC3 W2 Y1 AC2 AD1 AE1 AE3 AG3 AJ4 AE2 AF1 AH3 AJ3 AJ5 AJ6 AJ7 AH9 AG5 AH5 AJ9 AJ10 AH11 AJ11 AH15 AJ15 AG11 AJ12 AJ14 AJ16 1K_0402_1% +1.25VREF_CPU 2 DDR_SDQ63 DDR_SDQ62 DDR_SDQ61 DDR_SDQ60 DDR_SDQ59 DDR_SDQ58 DDR_SDQ57 DDR_SDQ56 DDR_SDQ55 DDR_SDQ54 DDR_SDQ53 DDR_SDQ52 DDR_SDQ51 DDR_SDQ50 DDR_SDQ49 DDR_SDQ48 DDR_SDQ47 DDR_SDQ46 DDR_SDQ45 DDR_SDQ44 DDR_SDQ43 DDR_SDQ42 DDR_SDQ41 DDR_SDQ40 DDR_SDQ39 DDR_SDQ38 DDR_SDQ37 DDR_SDQ36 DDR_SDQ35 DDR_SDQ34 DDR_SDQ33 DDR_SDQ32 DDR_SDQ31 DDR_SDQ30 DDR_SDQ29 DDR_SDQ28 DDR_SDQ27 DDR_SDQ26 DDR_SDQ25 DDR_SDQ24 DDR_SDQ23 DDR_SDQ22 DDR_SDQ21 DDR_SDQ20 DDR_SDQ19 DDR_SDQ18 DDR_SDQ17 DDR_SDQ16 DDR_SDQ15 DDR_SDQ14 DDR_SDQ13 DDR_SDQ12 DDR_SDQ11 DDR_SDQ10 DDR_SDQ9 DDR_SDQ8 DDR_SDQ7 DDR_SDQ6 DDR_SDQ5 DDR_SDQ4 DDR_SDQ3 DDR_SDQ2 DDR_SDQ1 DDR_SDQ0 MEMVREF1 R17 1 <8> DDR_SDQ[0..63] D14 C14 1 1 C8 C9 1K_0402_1% 2 2 2 2 MEMZN MEMZP A CHANGEL ADDRESS 1 1 R10 1 R11 B CHANGEL ADDRESS AG12 34.8_0603_1% 34.8_0603_1% DDR Memory +2.5V 2 1000P_0402_50V7K 0.1U_0402_16V4Z DDR_SRASB# <9> DDR_SCASB# <9> DDR_SWEB# <9> DDR_SBSB1 <9> DDR_SBSB0 <9> DDR_SMAB[0..13] <9> 3 N3 N1 U3 V1 N2 P1 U1 U2 FOX_PZ75403-2941-42 4 4 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title Claw Harmmer/DDR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 5 of 53 A B C D E +1.25V Near Power Supply +2.5VS + 2 220U_D2_2.5VM 1 R18 1K_0402_5% R20 10K_0402_5% 2 R19 2 2 Q2 1 H_THERMTRIP_S# 1 3 1H_THERMTRIP# MMBT3904_SOT23 H_THERMTRIP# <20> JP1C Claw Hammer-DTR H_THERMTRIP_S# H_RST_CPU# H_RST# @ C31 2 CPUCLK0_H C21 1 <19> 3900P_0402_50V7K 1 2 CPUCLK0_L C32 C33 100U_6.3V_M 2 1 Miscellaneous RESET_L PWROK AJ21 AH21 AH19 AJ19 CLKIN_H CLKIN_L FBCLKOUT_H FBCLKOUT_L A23 A24 B23 COREFB_H COREFB_L CORE_SENSE AE12 AF12 AE11 VDDIOFB_H VDDIOFB_L VDDIO_SENSE AH25 AJ25 VDDA1 VDDA2 Clock Place within 0.5" from CPU Route as 80 Ohm DIFF impedence 8/5/20 PAD PAD PAD VDDIOFB_H VDDIOFB_L VDDIO_SENSE T4 T6 T8 +VDDA <48> <48> <48> 2 2 <48> 0.22U_0603_10V7K <48> 2 CPU_COREFB CPU_COREFB# <48> CPU_COREFB <48> CPU_COREFB# R o u te a s D I F F p a ir 10/5/10 2 AE18 THERMTRIP_L 3900P_0402_50V7K L1 LQG21F4R7N00_0805 3300P_0402_50V7K 1 2 1 1 1 1 + C34 C35 C36 +2.5VDDA C LKIN CLKIN# FBCLKOUT 2 R23 FBCLKOUT# 1 80.6_0402_1% 2 <16> H_PWRGD H_PWRGD R22 169_0402_1% Place 169 Ohm within 0.5" from CPU Route as DIF 5/5/5/20 A20 AF20 0.001U_0402_50V7M 2 1 <19> <16> 50 mil/20 mil VID4 VID3 VID2 VID1 VID0 4.7U_0805_6.3V6K VID4 VID3 VID2 VID1 VID0 AG13 AF14 AG14 AF15 AE15 VID4 VID3 VID2 VID1 VID0 D B RDY DBREQ# AH17 AE19 DBRDY DBREQ_L 07/11 change for reduce H_RST# glitch Debug +2.5VS D 1 3 S H_RST# THERMDA_CPU THERMDC_CPU <4> THERMDA_CPU <4> THERMDC_CPU 1 1 H_RST# 680_0402_5% 1 H_PWRGD 680_0402_5% 2 R26 2 R28 2 SUSP G Q61 2N7002_SOT23 SUSP TDO TMS TCK TRST# TDI 2 2 J1 A26 A27 THERMDA THERMDC <41,47> @ R32 100_0402_5% 1 3 1 C40 2 C41 2 0.22U_0603_10V7K 1 C42 2 +1.25V PAD PAD A22 E20 E17 B21 A21 TDO TMS TCK TRST_L TDI JTAG 4.7U_0805_6.3V6K 1 0.22U_0603_10V7K JOPEN + C10 2 C11 220U_D2_2.5VM +1.25V 2 680_0402_5% 1 +3VALW 1 1 1 +2.5VS T17 T18 TP_K8_A28 TP_K8_AJ28 D29 D27 D25 C28 C26 B29 B27 D17 A18 B17 C17 C16 A28 AJ28 VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VTT_A VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B VTT_B VTT_SENSE AG10 E14 D12 E13 C12 D22 C22 B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9 AE23 AF23 AF22 AF21 C1 J3 R3 AA2 D3 AG2 B18 AH1 AE21 C20 AG4 C6 AG6 AE9 AG9 AF18 AJ23 AH23 AE24 AF24 C15 AG18 AH18 AG17 AJ18 C18 A19 D20 C21 D18 C19 B19 TP_M_RESET# T1 PAD TP_K8_D22 TP_K8_C22 T2 T3 PAD PAD C12 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 1 1 1 1 1 1 1 1 C13 C14 C15 C16 C17 C18 C19 C20 2 2 4.7U_0805_6.3V6K 2 2 4.7U_0805_6.3V6K 2 2 4.7U_0805_6.3V6K 2 2 4.7U_0805_6.3V6K 1 2 4.7U_0805_6.3V6K +1.25V 1 C22 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 1 1 1 1 1 1 1 1 C23 C24 C25 C26 C27 C28 C29 C30 2 2 0.22U_0603_10V7K CLAW_ANALOG3 CLAW_ANALOG2 CLAW_ANALOG1 CLAW_ANALOG0 T5 T7 T9 T10 2 2 0.22U_0603_10V7K 2 2 0.22U_0603_10V7K PAD PAD PAD PAD 2 2 0.22U_0603_10V7K 2 0.22U_0603_10V7K R24 0_0805_5% 1 2 +2.5VS U3 +3VS 1 IN 2 GND 2 C37 @ 1U_0603_10V4Z 3 1 OUT SHDN @ BYP +2.5VDDA 5 2 4 G914E_SOT23-5 C39 @ 0.01U_0402_16V7K 1 1 2 C38 1U_0603_10V4Z 2 +2.5V +2.5V BPSCLK BPSCLK# TP_K8_AE24 TP_K8_AF24 TP_K8_C15 TP_CPU_BP3 TP_CPU_BP2 BP1 BP0 SIN CHN BRN# SCANCLK1 SCANCLK2 SCANEN SCANSHENB SCANSHENA R25 R27 R29 R30 R31 R33 R34 1 1 T11 T12 T13 T14 T15 1 1 1 1 2 820_0402_5% 2 820_0402_5% PAD PAD PAD PAD PAD 2 2 2 2 680_0402_5% 680_0402_5% 680_0402_5% 680_0402_5% +2.5VS RP1 SCANCLK2 SCANCLK1 SCANEN SCANSHENB 4 3 2 1 5 6 7 8 2 680_0402_5% 1 680_1206_8P4R_5% AH29 AH27 AG28 AG26 AF29 AE28 AF25 +1.2V_HT AG15 AF16 AG16 AH16 AJ17 AE13 +1.25V 3 VTT_SENSE T16 PAD KEY1 KEY0 FOX_PZ75403-2941-42 +2.5VS +1.2V_HT 4 DBREQ# D B RDY TCK TMS TDI TRST# TDO R41 @ 560_0402_5% 2 1 R40 @ 560_0402_5% 2 1 R39 @ 560_0402_5% 2 1 R38 @ 560_0402_5% 2 1 R37 @ 560_0402_5% 2 1 R36 @ 560_0402_5% 2 1 @ 560_0402_5% 2 1 R35 1 + +2.5VS 2 4 6 8 10 12 14 16 18 20 22 24 26 1 C44 C45 0.22U_0603_10V7K 1 C46 2 2 0.22U_0603_10V7K 1 0.22U_0603_10V7K 1 C47 C48 2 2 0.22U_0603_10V7K 1 2 C49 0.22U_0603_10V7K 4 Compal Secret Data Security Classification 2005/03/01 Issued Date SAMTEC_ASP-68200-07 A C43 1 2 2 100U_D2_10VM JP3 1 3 5 7 9 11 13 15 17 19 21 23 0.22U_0603_10V7K 250 mil 2005/04/06 Deciphered Date B C Title Claw Harmmer(MISC) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 6 of 53 A B C +CPU_CORE 2 3 4 L28 R28 W28 AC28 AF28 AH28 C29 F2 H2 K2 M2 P2 T2 V2 Y2 AB2 AD2 AH2 B4 AH4 B6 G6 J6 L6 N6 R6 U6 AA6 AC6 AH6 F7 H7 K7 M7 P7 T7 V7 AB7 AD7 B8 G8 J8 L8 N8 R8 U8 W8 AC8 AH8 F9 H9 K9 M9 P9 T9 V9 Y9 AD9 B10 G10 J10 L10 N10 R10 U10 W10 AC10 AH10 F11 H11 K11 Y11 AB11 AD11 B12 G12 AA12 AC12 AH12 F13 H13 K13 Y13 AB13 AD13 AF17 G14 J14 AA14 AC14 AE14 D16 E15 K15 AB15 AD15 AH14 E16 G16 J16 AA16 AC16 AE29 AJ26 E18 F17 H17 K17 Y17 L7 AC15 H18 B20 E21 H22 J23 H24 F26 N7 L9 V10 G13 K14 Y14 AB14 G15 J15 AA15 H16 K16 Y16 AB16 G17 J17 AA17 AC17 AE17 F18 K18 Y18 AB18 AD18 AG19 E19 G19 AC19 AA19 J19 F20 H20 K20 M20 P20 T20 V20 Y20 AB20 AD20 G21 J21 L21 N21 R21 U21 W21 AA21 AC21 F22 K22 M22 P22 T22 V22 Y22 AB22 AD22 E23 G23 L23 N23 R23 U23 W23 AA23 AC23 B24 D24 F24 K24 M24 P24 T24 V24 Y24 AB24 AD24 AH24 AE25 K26 P26 V26 E +2.5V JP1D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD POWER 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS POWER JP1E B2 AH20 AB21 W22 M23 L24 AG25 AG27 D2 AF2 W6 Y7 AA8 AB9 AA10 J12 B14 Y15 AE16 J18 G20 R20 U20 W20 AA20 AC20 AE20 AG20 AJ20 D21 F21 H21 K21 M21 P21 T21 V21 Y21 AD21 AG21 B22 E22 G22 J22 L22 N22 R22 U22 AG29 AA22 AC22 AG22 AH22 AJ22 D23 F23 H23 K23 P23 T23 V23 Y23 AB23 AD23 AG23 E24 G24 J24 N24 R24 U24 W24 AA24 AC24 AG24 AJ24 B25 C25 B26 D26 H26 M26 T26 Y26 AD26 AF26 AH26 C27 B28 D28 G28 F15 H15 AB17 AD17 B16 G18 AA18 AC18 D19 F19 H19 K19 Y19 AB19 AD19 AF19 J20 L20 N20 D VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28 +CPU_CORE 820U_E9_2_5V_M_R7 1 330U_D_2VM_R15 1 + 1 + C50 2 + C52 C51 2 1 + 2 820U_E9_2_5V_M_R7 @ 330U_D_2VM_R15 1 1 + C53 2 + C54 2 @ 330U_D_2VM_R15 C55 2 330U_D_2VM_R15 1 +CPU_CORE +CPU_CORE 10U_0805_10V4Z 1 1 C56 2 10U_0805_10V4Z 1 C57 2 1 C58 2 10U_0805_10V4Z 10U_0805_10V4Z 1 C59 2 1 C60 2 10U_0805_10V4Z 0.1U_0402_16V4Z 1 C61 2 1 C62 2 10U_0805_10V4Z C63 2 1000P_0402_50V7K 4 in Socket Cavity 2 on backside under Socket +CPU_CORE 4.7U_0805_6.3V6K 1 1 C64 2 4.7U_0805_6.3V6K 1 C65 2 4.7U_0805_6.3V6K 1 C66 2 4.7U_0805_6.3V6K 1 C67 2 4.7U_0805_6.3V6K 1 C68 2 1 C69 2 C70 4.7U_0805_6.3V6K 2 4.7U_0805_6.3V6K 2 Close to socket CPU Decouping Capacitor +CPU_CORE 0.22U_0603_10V7K +CPU_CORE 1 1 C71 0.22U_0603_10V7K 1 1 C72 2 C73 2 0.22U_0603_10V7K C74 2 2 Loop Bandwidth Bulk Cappacitance KHz uF 0.22U_0603_10V7K 1 1 C75 2 C76 2 Total ESR 2.5m ohm (AMD) 20 23000 50 9000 0.9m ohm * 300 1500 2.5m ohm 0.22U_0603_10V7K 0.22U_0603_10V7K In Socket Cavity +2.5V +2.5V 0.22U_0603_10V7K 4.7U_0805_6.3V6K 1 1 C77 1 C78 C79 1 C80 0.22U_0603_10V7K 1 1 C81 C82 0.22U_0603_10V7K 1 C83 1 C84 3 2 2 2 4.7U_0805_6.3V6K 0.22U_0603_10V7K 2 2 2 0.22U_0603_10V7K 2 2 0.22U_0603_10V7K Near Socket For EMI require +CPU_CORE 1000P_0402_50V7K FOX_PZ75403-2941-42 1 1 @C721 2 @ C722 2 1000P_0402_50V7K 1000P_0402_50V7K 1 1 @ C723 2 @C724 2 1000P_0402_50V7K 4 FOX_PZ75403-2941-42 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title Claw Harmmer(Power) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 7 of 53 A B DDR _DQ[0..63] DD R_SDQ[0..63] DDR _DQS[0..7] DDR_SDM[0..7] D DR_DM[0..7] DDR_DQ[0..63] <9> +2.5V DDR_DQ0 DDR_DQ5 DDR_DQS0 DDR_DQ3 1 DDR_DQ7 DDR_DQ9 DDR_SDQ26 DDR_SDQ31 DDR_SDQ30 DDR_SDQ27 1 2 3 4 DDR_DQ26 DDR_DQ31 DDR_DQ30 DDR_DQ27 DDR_SDQ62 DDR_SDQ58 DDR_SDQ63 DDR_SDQ59 1 2 3 4 10_0804_8P4R_5% DDR_SDQ23 DDR_SDQ22 DDR_SDQ28 DDR_SDQ25 1 2 3 4 8 7 6 5 DDR_DQ62 DDR_DQ58 DDR_DQ63 DDR_DQ59 DDR_DQ29 DDR_DQ24 DDR_DQS3 DDR_DM3 DDR_SDQ61 DDR_SDQ57 DDR_SDM7 DDR_SDQS7 1 2 3 4 8 7 6 5 10_0804_8P4R_5% 10_0804_8P4R_5% RP20 RP21 8 7 6 5 DDR_DQ23 DDR_DQ22 DDR_DQ28 DDR_DQ25 DDR_SDQ55 DDR_SDQ51 DDR_SDQ56 DDR_SDQ60 1 2 3 4 10_0804_8P4R_5% 8 7 6 5 DDR_DQS2 DDR_DM2 DDR_DQ18 DDR_DQ19 DDR_SDQS6 DDR_SDM6 DDR_SDQ54 DDR_SDQ50 1 2 3 4 10_0804_8P4R_5% DDR_SDQ14 DDR_SDQ15 DDR_SDQ10 DDR_SDQ11 1 2 3 4 DDR_DQ55 DDR_DQ51 DDR_DQ56 DDR_DQ60 DDR_DQ26 DDR_DQ27 Note: DDR_SMAA13 Recommend for AMD 8 7 6 5 DDR_DQS6 DDR_DM6 DDR_DQ54 DDR_DQ50 RP17 8 7 6 5 DDR_DQ16 DDR_DQ20 DDR_DQ17 DDR_DQ21 DDR_SDQ53 DDR_SDQ48 DDR_SDQ49 DDR_SDQ52 1 2 3 4 <5> 8 7 6 5 10_0804_8P4R_5% RP14 RP15 8 7 6 5 DDR_DQ14 DDR_DQ15 DDR_DQ10 DDR_DQ11 DDR_SDQ42 DDR_SDQ47 DDR_SDQ43 DDR_SDQ46 1 2 3 4 10_0804_8P4R_5% RP11 8 7 6 5 DDR_CKE0 DDR_DQ53 DDR_DQ48 DDR_DQ49 DDR_DQ52 10_0804_8P4R_5% 1 2 3 4 DDR_DQ24 DDR_DQS3 10_0804_8P4R_5% RP16 DDR_SDQ16 DDR_SDQ20 DDR_SDQ17 DDR_SDQ21 DDR_DQS2 DDR_DQ18 DDR_DQ19 DDR_DQ28 RP19 8 7 6 5 DDR_DQ20 DDR_DQ17 10_0804_8P4R_5% RP18 1 2 3 4 DDR_CLK5 DDR_CLK5# DDR_DQ61 DDR_DQ57 DDR_DM7 DDR_DQS7 2 DDR_SDQS2 DDR_SDM2 DDR_SDQ18 DDR_SDQ19 <5> <5> DDR_CKE0 DDR_SMAA12 DDR_SMAA9 DDR_SMAA7 DDR_SMAA5 DDR_SMAA3 DDR_SMAA1 <5> <5> <5> DDR_DQ42 DDR_DQ47 DDR_DQ43 DDR_DQ46 DDR_SBSA0 DDR_SWEA# DDR_SCS#0 DDR_SMAA10 DDR_SBSA0 DDR_SWEA# DDR_SCS#0 DDR_SMAA13 10_0804_8P4R_5% DDR_DQ32 DDR_DQ36 RP12 DDR_DQS4 DDR_DQ34 3 DDR_SDQ12 DDR_SDQS1 DDR_SDM1 DDR_SDQ13 1 2 3 4 8 7 6 5 DDR_DQ12 DDR_DQS1 DDR_DM1 DDR_DQ13 DDR_SDQ44 DDR_SDQ45 DDR_SDM5 DDR_SDQS5 1 2 3 4 10_0804_8P4R_5% 8 7 6 5 DDR_DQ44 DDR_DQ45 DDR_DM5 DDR_DQS5 DDR_DQ38 DDR_DQ40 DDR_DQ44 DDR_DQS5 10_0804_8P4R_5% DDR_DQ47 DDR_DQ46 Layout note RP7 DDR_SDQ6 DDR_SDQ7 DDR_SDQ8 DDR_SDQ9 1 2 3 4 RP8 8 7 6 5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_SDQ35 DDR_SDQ39 DDR_SDQ40 DDR_SDQ41 1 2 3 4 10_0804_8P4R_5% RP4 DDR_SDQS0 DDR_SDM0 DDR_SDQ2 DDR_SDQ3 1 2 3 4 8 7 6 5 DDR_DQS0 DDR_DM0 DDR_DQ2 DDR_DQ3 DDR_SDQS4 DDR_SDM4 DDR_SDQ34 DDR_SDQ38 1 2 3 4 DDR_DQ35 DDR_DQ39 DDR_DQ40 DDR_DQ41 DDR_DQ48 DDR_DQ49 10_0804_8P4R_5% DDR_DQS6 DDR_DQ50 RP5 DDR_DQ55 DDR_DQ56 8 7 6 5 DDR_DQS4 DDR_DM4 DDR_DQ34 DDR_DQ38 DDR_DQ61 DDR_DQS7 DDR_DQ58 DDR_DQ59 <9,16,20,28> SB_SDAT <9,16,20,28> SB_SCLK RP3 8 7 6 5 Place these resistors close to DIMM0, all trace length<500 mil 10_0804_8P4R_5% RP2 DDR_SDQ0 DDR_SDQ4 DDR_SDQ5 DDR_SDQ1 8 7 6 5 1 2 3 4 10_0804_8P4R_5% 4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS 40mil 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DDR_DQ4 DDR_DQ1 DDR_DM0 DDR_DQ2 DDR_DQ0 DDR_DQ4 DDR_DQ5 DDR_DQ1 DDR_SDQ32 DDR_SDQ33 DDR_SDQ36 DDR_SDQ37 10_0804_8P4R_5% 1 2 3 4 8 7 6 5 +3VS DDR_DQ32 DDR_DQ33 DDR_DQ36 DDR_DQ37 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID 2 +1.25VREF_MEM C85 0.1U_0402_16V4Z 1 DDR_DQ6 DDR_DQ8 DDR_DQ13 DDR_DM1 DDR_DQ10 DDR_DQ11 DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU DDR_DM2 DDR_DQ22 DDR_DQ23 DDR_DQ25 RP9 47_0804_8P4R_5% DDR_SMAA3 8 1 DDR_SMAA1 7 2 DDR_SMAA10 6 3 DDR_SBSA0 5 4 DDR_DQ29 DDR_DM3 DDR_DQ30 DDR_DQ31 2 RP10 47_0804_8P4R_5% DDR_SMAA11 8 1 DDR_SMAA8 7 2 DDR_SMAA6 6 3 DDR_SMAA4 5 4 RP13 47_0804_8P4R_5% DDR_SMAA2 8 1 DDR_SMAA0 7 2 DDR_SBSA1 6 3 DDR_SRASA# 5 4 DDR_CKE0 DDR_SMAA11 DDR_SMAA8 DDR_SMAA6 DDR_SMAA4 DDR_SMAA2 DDR_SMAA0 DDR_SBSA1 DDR_SRASA# DDR_SCASA# DDR_SCS#1 DDR_SBSA1 <5> DDR_SRASA# <5> DDR_SCASA# <5> DDR_SCS#1 <5> DDR_SMAA13 1 47_0402_5% DDR_SWEA# 1 47_0402_5% DDR_SCASA# 1 47_0402_5% 2 R42 2 R43 2 R44 DDR_SCS#0 1 68_0402_5% DDR_SCS#1 1 68_0402_5% DDR_CKE0 1 68_0402_5% 2 R45 2 R46 2 R47 DDR_DQ37 DDR_DQ33 DDR_DM4 DDR_DQ35 3 DDR_DQ39 DDR_DQ41 DDR_DQ45 DDR_DM5 DDR_DQ42 DDR_DQ43 DDR_CLK7# <5> DDR_CLK7 <5> +2.5V DDR_DQ53 DDR_DQ52 DDR_DM6 DDR_DQ54 R48 1K_0402_1% +1.25VREF_MEM DDR_DQ51 DDR_DQ60 DDR_DQ57 DDR_DM7 1 R49 1K_0402_1% DDR_DQ62 DDR_DQ63 2 1 C86 C87 0.1U_0402_16V4Z 1000P_0402_50V7K 2 4 SO-DIMM0 10_0804_8P4R_5% Issued Date Compal Secret Data 2005/03/01 2005/04/06 Deciphered Date C D E Title DDR-SODIMM0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B +1.25V RP6 47_0804_8P4R_5% DDR_SMAA12 8 1 DDR_SMAA9 7 2 DDR_SMAA7 6 3 DDR_SMAA5 5 4 DDR_DQ16 DDR_DQ21 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 AMP_1565918-1 Security Classification A 1 RP23 8 7 6 5 1 2 3 4 DDR_DQ14 DDR_DQ15 10_0804_8P4R_5% RP22 DDR_SDQ29 DDR_SDQ24 DDR_SDQS3 DDR_SDM3 DDR_DQ12 DDR_DQS1 RP25 8 7 6 5 H JP4 DDR_DM[0..7] <9> RP24 G +2.5V DDR_DQS[0..7] <9> DDR_SMAA[0..13] <5> DDR_SMAA[0..13] F 1 <5> DDR_SDM[0..7] DD R_SDQS[0..7] E 1 2 <5> DDR_SDQ[0..63] D 2 <5> DDR_SDQS[0..7] C F Size Document Number Custom Date: Tuesday, August 30, 2005 G R ev 0.8 LA-2771 Sheet 8 H of 53 A B <8> DDR_DQS[0..7] <8> DDR_DQ[0..63] <8> DDR_DM[0..7] <5> DDR_SMAB[0..13] C D DDR _DQS[0..7] D DR_DM[0..7] DDR_SMAB[0..13] DDR_DQ0 DDR_DQ5 DDR_DQ7 DDR_DQ9 3 +1.25V DDR_DQ12 DDR_DQS1 RP26 68_0804_8P4R_5% DDR_DQ2 1 8 DDR_DM0 2 7 DDR_DQ1 3 6 DDR_DQ4 4 5 RP27 68_0804_8P4R_5% DDR_DQ3 1 8 DDR_DQS0 2 7 DDR_DQ5 3 6 DDR_DQ0 4 5 RP29 68_0804_8P4R_5% DDR_DM1 1 8 DDR_DQ13 2 7 DDR_DQ8 3 6 DDR_DQ6 4 5 RP30 68_0804_8P4R_5% DDR_DQS1 1 8 DDR_DQ12 2 7 DDR_DQ9 3 6 DDR_DQ7 4 5 DDR_DQ20 DDR_DQ17 RP32 68_0804_8P4R_5% DDR_DQ21 1 8 DDR_DQ16 2 7 DDR_DQ11 3 6 DDR_DQ10 4 5 RP33 68_0804_8P4R_5% DDR_DQ17 1 8 DDR_DQ20 2 7 DDR_DQ15 3 6 DDR_DQ14 4 5 DDR_DQ24 DDR_DQS3 RP35 68_0804_8P4R_5% DDR_DQ25 1 8 DDR_DQ23 2 7 DDR_DQ22 3 6 DDR_DM2 4 5 RP36 68_0804_8P4R_5% DDR_DQ28 1 8 DDR_DQ19 2 7 DDR_DQ18 3 6 DDR_DQS2 4 5 RP38 68_0804_8P4R_5% DDR_DQ31 1 8 DDR_DQ30 2 7 DDR_DM3 3 6 DDR_DQ29 4 5 RP39 68_0804_8P4R_5% DDR_DQ27 1 8 DDR_DQ26 2 7 DDR_DQS3 3 6 DDR_DQ24 4 5 RP40 68_0804_8P4R_5% DDR_DQ35 1 8 DDR_DM4 2 7 DDR_DQ33 3 6 DDR_DQ37 4 5 RP41 68_0804_8P4R_5% DDR_DQ34 1 8 DDR_DQS4 2 7 DDR_DQ36 3 6 DDR_DQ32 4 5 RP42 68_0804_8P4R_5% DDR_DM5 1 8 DDR_DQ45 2 7 DDR_DQ41 3 6 DDR_DQ39 4 5 RP43 68_0804_8P4R_5% DDR_DQS5 1 8 DDR_DQ44 2 7 DDR_DQ40 3 6 DDR_DQ38 4 5 RP44 68_0804_8P4R_5% DDR_DQ52 1 8 DDR_DQ53 2 7 DDR_DQ43 3 6 DDR_DQ42 4 5 RP45 68_0804_8P4R_5% DDR_DQ49 1 8 DDR_DQ48 2 7 DDR_DQ46 3 6 DDR_DQ47 4 5 RP46 68_0804_8P4R_5% DDR_DQ60 1 8 DDR_DQ51 2 7 DDR_DQ54 3 6 DDR_DM6 4 5 RP47 68_0804_8P4R_5% DDR_DQ56 1 8 DDR_DQ55 2 7 DDR_DQ50 3 6 DDR_DQS6 4 5 DDR_DQ14 DDR_DQ15 <5> <5> DDR_CLK4 DDR_CLK4# DDR_DQS2 DDR_DQ18 DDR_DQ19 DDR_DQ28 DDR_DQ26 DDR_DQ27 Note: DDR_SMAA13 Recommend for AMD <5> DDR_CKE1 DDR_CKE1 DDR_SMAB12 DDR_SMAB9 DDR_SMAB7 DDR_SMAB5 DDR_SMAB3 DDR_SMAB1 <5> DDR_SBSB0 <5> DDR_SWEB# <5> DDR_SCS#2 DDR_SMAB10 DDR_SBSB0 DDR_SWEB# DDR_SCS#2 DDR_SMAB13 DDR_DQ32 DDR_DQ36 DDR_DQS4 DDR_DQ34 DDR_DQ38 DDR_DQ40 DDR_DQ44 DDR_DQS5 Layout note RP48 68_0804_8P4R_5% DDR_DQ63 1 8 DDR_DQ62 2 7 DDR_DM7 3 6 DDR_DQ57 4 5 +1.25VREF_MEM JP5 1 2 +2.5V +2.5V DDR _DQ[0..63] DDR_DQS0 DDR_DQ3 +1.25V E RP49 68_0804_8P4R_5% DDR_DQ59 1 8 DDR_DQ58 2 7 DDR_DQS7 3 6 DDR_DQ61 4 5 Place these resistor closely DIMM1, all trace length<=800mil DDR_DQ47 DDR_DQ46 DDR_DQ48 DDR_DQ49 DDR_DQS6 DDR_DQ50 DDR_DQ55 DDR_DQ56 DDR_DQ61 DDR_DQS7 DDR_DQ58 DDR_DQ59 <8,16,20,28> SB_SDAT <8,16,20,28> SB_SCLK +3VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 20 mil width 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR_DQ16 DDR_DQ21 DDR_DQ4 DDR_DQ1 DDR_DM0 DDR_DQ2 1 2 C88 0.1U_0402_16V4Z 1 DDR_DQ6 DDR_DQ8 DDR_DQ13 DDR_DM1 DDR_DQ10 DDR_DQ11 +1.25V RP28 47_0804_8P4R_5% DDR_SMAB5 1 8 DDR_SMAB7 2 7 DDR_SMAB9 3 6 DDR_SMAB12 4 5 DDR_DM2 DDR_DQ22 RP31 47_0804_8P4R_5% DDR_SBSB0 1 8 DDR_SMAB10 2 7 DDR_SMAB1 3 6 DDR_SMAB3 4 5 DDR_DQ23 DDR_DQ25 DDR_DQ29 DDR_DM3 DDR_DQ30 DDR_DQ31 RP34 47_0804_8P4R_5% DDR_SMAB4 1 8 DDR_SMAB6 2 7 DDR_SMAB8 3 6 DDR_SMAB11 4 5 2 RP37 47_0804_8P4R_5% DDR_SRASB# 1 8 DDR_SBSB1 2 7 DDR_SMAB0 3 6 DDR_SMAB2 4 5 DDR_CKE1 DDR_SMAB11 DDR_SMAB8 DDR_SMAB6 DDR_SMAB4 DDR_SMAB2 DDR_SMAB0 DDR_SBSB1 DDR_SRASB# DDR_SCASB# DDR_SCS#3 DDR_SBSB1 <5> DDR_SRASB# <5> DDR_SCASB# <5> DDR_SCS#3 <5> DDR_DQ37 DDR_DQ33 DDR_SMAB13 1 47_0402_5% DDR_SWEB# 1 47_0402_5% DDR_SCASB# 1 47_0402_5% 2 R50 2 R51 2 R52 DDR_SCS#2 1 68_0402_5% DDR_CKE1 1 68_0402_5% DDR_SCS#3 1 68_0402_5% 2 R53 2 R54 2 R55 DDR_DM4 DDR_DQ35 3 DDR_DQ39 DDR_DQ41 DDR_DQ45 DDR_DM5 DDR_DQ42 DDR_DQ43 Layout note Place these resistor close by DIMM1, all trace length Max=0.8" DDR_CLK6# <5> DDR_CLK6 <5> DDR_DQ53 DDR_DQ52 DDR_DM6 DDR_DQ54 DDR_DQ51 DDR_DQ60 DDR_DQ57 DDR_DM7 DDR_DQ62 DDR_DQ63 +3VS 4 4 TYCO_1470804-2 DIMM1 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title DDR-SODIMM1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 9 of 53 A B C D +1.25V +2.5V 330U_6.3V_M 1 1 + 4.7U_0805_6.3V6K 10U_0805_10V4Z 1 + C89 2 1 C90 2 330U_6.3V_M Layout note : E 1 C91 2 1 C92 2 C94 2 4.7U_0805_6.3V6K 1 1 C93 2 10U_0805_10V4Z Near DIMMs Place one cap close to every 2 pull up resistors termination to +1.25V +1.25V 0.1U_0402_16V4Z 1 C95 2 1 C96 2 0.1U_0402_16V4Z 1 C97 2 0.1U_0402_16V4Z 1 C98 2 0.1U_0402_16V4Z 1 C99 2 0.1U_0402_16V4Z 1 C100 2 0.1U_0402_16V4Z 1 C101 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C102 2 C103 2 0.1U_0402_16V4Z 1 C104 2 0.1U_0402_16V4Z 1 C105 2 0.1U_0402_16V4Z 1 C106 2 0.1U_0402_16V4Z +1.25V 0.1U_0402_16V4Z 1 C107 1 C108 0.1U_0402_16V4Z 1 C109 1 C110 0.1U_0402_16V4Z 1 C111 1 C112 0.1U_0402_16V4Z 1 C113 1 0.1U_0402_16V4Z 1 C114 C115 1 C116 0.1U_0402_16V4Z 1 C117 1 C118 2 2 2 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +1.25V 0.1U_0402_16V4Z 1 C119 2 1 C120 2 0.1U_0402_16V4Z 1 C121 2 0.1U_0402_16V4Z 1 C122 2 0.1U_0402_16V4Z 1 C123 2 0.1U_0402_16V4Z 1 C124 2 0.1U_0402_16V4Z 1 C125 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C126 2 C127 2 0.1U_0402_16V4Z 1 C128 2 0.1U_0402_16V4Z +1.25V 0.1U_0402_16V4Z 3 1 C129 2 1 C130 2 0.1U_0402_16V4Z 1 C131 2 0.1U_0402_16V4Z 1 C132 2 0.1U_0402_16V4Z 1 C133 2 0.1U_0402_16V4Z 1 C134 2 0.1U_0402_16V4Z 1 C135 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C136 2 C137 2 0.1U_0402_16V4Z 1 C138 2 0.1U_0402_16V4Z 1 C139 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +2.5V 0.1U_0402_16V4Z C141 2 3 C140 2 +1.25V 1 1 1 C142 2 0.1U_0402_16V4Z 1 C143 2 0.1U_0402_16V4Z 1 C144 2 0.1U_0402_16V4Z 1 C145 2 0.1U_0402_16V4Z 1 C146 2 0.1U_0402_16V4Z 1 C147 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C148 2 C149 2 0.1U_0402_16V4Z 1 C150 2 0.1U_0402_16V4Z 1 C151 2 0.1U_0402_16V4Z 1 C152 2 0.1U_0402_16V4Z +2.5V +1.25V 0.1U_0402_16V4Z 1 C153 2 4 1 2 0.1U_0402_16V4Z C154 0.1U_0402_16V4Z 1 C155 2 0.1U_0402_16V4Z 1 2 C156 0.1U_0402_16V4Z 1 C157 2 0.1U_0402_16V4Z 1 2 C158 0.1U_0402_16V4Z 1 C159 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C160 2 C161 2 1 C162 2 4 0.1U_0402_16V4Z +2.5V Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title DDR Decoupling THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 10 of 53 5 4 <4> H_CADIP[0..15] <4> H_CADIN[0..15] <4> H_CADOP[0..15] <4> H_CADON[0..15] 3 2 <15> H_CADIP[0..15] H_CADIN[0..15] 1 NMAA[0..14] <15> NMDA[0..63] NMAA[0..14] NMDA[0..63] H_CADOP[0..15] H_CADON[0..15] D <15> NDQMA[0..7] <15> NDQSA[0..7] NDQMA[0..7] ND QSA[0..7] D <4> <4> H_CLKOP1 H_CLKON1 <4> <4> H_CLKOP0 H_CLKON0 <4> <4> H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 R29 R28 T30 R30 T28 T29 V29 U29 Y30 W30 Y28 Y29 AB29 AA29 AC29 AC28 H_CLKOP1 H_CLKON1 Y26 W26 H_CLKOP0 H_CLKON0 W29 W28 H_CTLOP0 H_CTLON0 H_CTLOP0 H_CTLON0 +1.2V_HT T26 R26 U25 U24 V26 U26 W25 W24 AA25 AA24 AB26 AA26 AC25 AC24 AD26 AC26 R56 R58 1 1 2 49.9_0402_1% 2 49.9_0402_1% P29 N29 D27 E27 HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N HT_RXCLK1P HT_RXCLK1N HYPER TRANSPORT CPU I/F C H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N HT_TXCLK1P HT_TXCLK1N HT_RXCLK0P HT_RXCLK0N HT_TXCLK0P HT_TXCLK0N HT_RXCTLP HT_RXCTLN HT_TXCTLP HT_TXCTLN HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN R24 R25 N26 P26 N24 N25 L26 M26 J26 K26 J24 J25 G26 H26 G24 G25 H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H _CADIN9 H_CADIP8 H _CADIN8 L30 M30 L28 L29 J29 K29 H30 H29 E29 E28 D30 E30 D28 D29 B29 C29 H_CADIP7 H _CADIN7 H_CADIP6 H _CADIN6 H_CADIP5 H _CADIN5 H_CADIP4 H _CADIN4 H_CADIP3 H _CADIN3 H_CADIP2 H _CADIN2 H_CADIP1 H _CADIN1 H_CADIP0 H _CADIN0 L24 L25 H_CLKIP1 H_CLKIN1 F29 G29 H_CLKIP0 H_CLKIN0 M29 M28 H_CTLIP0 H_CTLIN0 B28 A28 R57 1 NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13 NMAA14 AF17 AK17 AH16 AF16 AJ22 AJ21 AH20 AH21 AK19 AH19 AJ17 AG16 AG17 AH17 AJ18 MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 NDQMA0 NDQMA1 NDQMA2 NDQMA3 NDQMA4 NDQMA5 NDQMA6 NDQMA7 AG26 AJ29 AE21 AH24 AH12 AG13 AH8 AE8 MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7 NDQSA0 NDQSA1 NDQSA2 NDQSA3 NDQSA4 NDQSA5 NDQSA6 NDQSA7 AF25 AH30 AG20 AJ25 AH13 AF14 AJ7 AG8 MEM_DQS0P MEM_DQS1P MEM_DQS2P MEM_DQS3P MEM_DQS4P MEM_DQS5P MEM_DQS6P MEM_DQS7P AG25 AH29 AF21 AK25 AJ12 AF13 AK7 AF9 MEM_DQS0N MEM_DQS1N MEM_DQS2N MEM_DQS3N MEM_DQS4N MEM_DQS5N MEM_DQS6N MEM_DQS7N H_CLKIP1 <4> H_CLKIN1 <4> H_CLKIP0 <4> H_CLKIN0 <4> H_CTLIP0 <4> H_CTLIN0 <4> 2 100_0402_1% 216RS480M_BGA706 NMRASA# NMCASA# NMWEA# NMCSA0# NMCKEA <15> <15> <15> <15> <15> NMRASA# NMCASA# NMWEA# NMCSA0# NMCKEA <15> <15> NMCLKA0 NMCLKA0# NMCLKA0 NMCLKA0# AE17 AH18 AE18 AJ19 AF18 AK16 AJ16 MEM_A I/F U4B U4A MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_CKP MEM_CKN +2.5VS 2 0.47U_0603_16V7K 2 0.47U_0603_16V7K AE28 AJ4 MEM_CAP1 MEM_CAP2 1 C163 1 C164 1 R59 R60 1 1 2 AJ20 MEM_VREF R63 +1.8VS 1K_0402_1% 2 C166 0.1U_0402_16V4Z 2 1K_0402_5% 1K_0402_1% AK20 1 2 2 C165 0.1U_0402_16V4Z B 1 1 2 R61 0_0805_5% MPVDD AJ15 AJ14 C167 1 2 MEM_VMODE MEM_VREF MPVDD MPVSS MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63 MEM_COMPP MEM_COMPN AF28 AF27 AG28 AF26 AE25 AE24 AF24 AG23 AE29 AF29 AG30 AG29 AH28 AJ28 AH27 AJ27 AE23 AG22 AF23 AF22 AE20 AG19 AF20 AF19 AH26 AJ26 AK26 AH25 AJ24 AH23 AJ23 AH22 AK14 AH14 AK13 AJ13 AJ11 AH11 AJ10 AH10 AE15 AF15 AG14 AE14 AE12 AF12 AG11 AE11 AJ9 AH9 AJ8 AK8 AH7 AJ6 AH6 AJ5 AG10 AF11 AF10 AE9 AG7 AF8 AF7 AE7 NMDA0 NMDA1 NMDA2 NMDA3 NMDA4 NMDA5 NMDA6 NMDA7 NMDA8 NMDA9 NMDA10 NMDA11 NMDA12 NMDA13 NMDA14 NMDA15 NMDA16 NMDA17 NMDA18 NMDA19 NMDA20 NMDA21 NMDA22 NMDA23 NMDA24 NMDA25 NMDA26 NMDA27 NMDA28 NMDA29 NMDA30 NMDA31 NMDA32 NMDA33 NMDA34 NMDA35 NMDA36 NMDA37 NMDA38 NMDA39 NMDA40 NMDA41 NMDA42 NMDA43 NMDA44 NMDA45 NMDA46 NMDA47 NMDA48 NMDA49 NMDA50 NMDA51 NMDA52 NMDA53 NMDA54 NMDA55 NMDA56 NMDA57 NMDA58 NMDA59 NMDA60 NMDA61 NMDA62 NMDA63 AH5 AD30 R62 1 R64 1 C B 2 61.9_0402_1% 2 61.9_0402_1% +2.5VS 216RS480M_BGA706 1U_0603_10V4Z MEM_VREF , MPVDD (20mils) A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title RS480M-HT/VMEM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 11 of 53 5 4 3 2 1 D D U4C C AE1 AE2 AB2 AC2 <28> <28> PCIE_RX0P PCIE_RX0N <28> <28> PCIE_RX1P PCIE_RX1N <19> <19> <19> <19> SB_RX0P SB_RX0N PCIE_RX0P PCIE_RX0N AB5 AB4 PCIE_RX1P PCIE_RX1N Y4 AA4 SB_RX0P SB_RX0N AG1 AH1 SB_RX1P SB_RX1N SB_RX1P SB_RX1N R65 1 R66 1 AC5 AC6 2 10K_0402_1% AH3 2 8.25K_0402_1% AJ3 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N PCIE I/F TO VIDEO D8 D7 D5 D4 E4 F4 G5 G4 H4 J4 H5 H6 G1 G2 K5 K4 L4 M4 N5 N4 P4 R4 P5 P6 P2 R2 T5 T4 U4 V4 W1 W2 A7 B7 B6 B5 A5 A4 B3 B2 C1 D1 D2 E2 F2 F1 H2 J2 J1 K1 K2 L2 M2 M1 N1 N2 R1 T1 T2 U2 V2 V1 Y2 AA2 AD2 AD1 GPP_RX0P GPP_RX0N GPP_TX0P GPP_TX0N GPP_RX1P GPP_RX1N GPP_TX1P GPP_TX1N AA1 AB1 GPP_RX2P GPP_RX2N GPP_TX2P GPP_TX2N Y5 Y6 GPP_RX3P GPP_RX3N GPP_TX3P GPP_TX3N SB_RX0P SB_RX0N PCIE I/F TO SLOT PCIE I/F TO SB SB_RX1P SB_RX1N PCE_ISET PCE_TXISET B C W5 W4 17_EXP@ PCIE_TX0P_C C168 1 2 0.1U_0402_16V4Z PCIE_TX0N_C C169 1 2 0.1U_0402_16V4Z 17_EXP@ 15_EXP@ PCIE_TX1P_C C691 1 2 0.1U_0402_16V4Z PCIE_TX1N_C C692 1 2 0.1U_0402_16V4Z 15_EXP@ PCIE_TX0P PCIE_TX0N PCIE_TX0P <28> PCIE_TX0N <28> PCIE_TX1P PCIE_TX1N PCIE_TX1P <28> PCIE_TX1N <28> AF2 AG2 SB_TX0P_C C170 1 SB_TX0N_C C171 1 2 0.1U_0402_16V4Z SB_TX0P 2 0.1U_0402_16V4Z SB_TX0N SB_TX0P <19> SB_TX0N <19> SB_TX1P SB_TX1N AC4 AD4 SB_TX1P_C C172 1 SB_TX1N_C C173 1 2 0.1U_0402_16V4Z SB_TX1P 2 0.1U_0402_16V4Z SB_TX1N SB_TX1P <19> SB_TX1N <19> PCE_PCAL PCE_NCAL AH2 AJ2 R67 R68 SB_TX0P SB_TX0N 1 1 2 150_0402_1% 2 82.5_0402_1% +1.2V_HT B 216RS480M_BGA706 A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title RS480M PCIE/DVI Controller THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 12 of 53 AVDD , AVDDI , AVDDQ , +NB_PLLVDD , +NB_HTPVDD +NB_VDDR3 , LPVDD , LVDDR18D , LVDDR18A (20mils) +3VS L2 1 2 FBML10160808121LMT_0603 C174 0.1U_0402_16V4Z AVDD 1 2 +1.8VS 2 2 2 C177 <18,40> TV_CRMA <18,40> TV_LUMA <18,40> TV_COMPS R69 1 +1.8VS L5 1 2 FBML10160808121LMT_0603 C180 10U_0805_10V4Z +2.5VS +1.8VS 1 R554 1 2 150_0603_1% C186 10U_0805_10V4Z 2 R70 2.2K_0402_5% CRT_R CRT_G CRT_B <18> <18> 2 CRT_VSYNC CRT_HSYNC <18> <18> 3VDDCCL 3VDDCDA 2 +3VS AVDDQ AVSSQ B25 A25 A24 C Y COMP CRT_R CRT_G CRT_B C25 A26 B26 RED GREEN BLUE A11 B11 C26 E11 F11 DAC_VSYNC DAC_HSYNC RSET DAC_SCL DAC_SDA CRT_VSYNC CR T_HSYNC 715_0402_1% 3VDDCCL 3VDDCDA 1U_0603_10V4Z 1 1 +NB_PLLVDD C181 2 2 +NB_HTPVDD A14 B14 PLLVDD PLLVSS M23 L23 HTPVDD HTPVSS 1U_0603_10V4Z 1 1 C187 2 2 <19,24,28,35> NB_RST# <42> NB_PWRGD <4,19> LDTSTOP# <19> ALLOW_LDTSTOP SUS_STAT# R71 5.6K_0402_5% E24 D24 L9 1 2 FBML10160808121LMT_0603 C188 1 1U_0603_10V4Z <16> NB_RST# NB_PWRGD LDTSTOP# ALLOW_LDTSTOP SUS_STAT# D14 B15 B12 C12 AH4 +NB_VDDR3 H13 H12 VDDR3_1 VDDR3_2 NB_REFCLK A13 B13 OSCIN OSCOUT 2 NB_REFCLK 1 SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP SUS_STAT# R75 2 R76 1 1 10K_0402_5% B9 NB STRAPS(Internal pull up) DEF_GPIO0:SIDE PORT EN# PAD High, SIDE PORT MEMORY DISABLE 2 3K_0402_5% T20 Low, SIDE PORT MEMORY ENABLE DEF_GPIO1:LOAD ROM STRAPS # BMREQ# EDID_CLK_LCD <19> BMREQ# <17> EDID_CLK_LCD High, LOAD ROM STRAP DISABLE F10 C10 C11 AF4 AE4 LVDSB0+ LVDSB0LVDSB1+ LVDSB1LVDSB2+ LVDSB2- TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N B16 A16 D16 C16 B17 A17 E17 D17 LVDSA0+ LVDSA0LVDSA1+ LVDSA1LVDSA2+ LVDSA2- TXCLK_UP TXCLK_UN TXCLK_LP TXCLK_LN B20 A20 B18 C17 LVDSBC+ LVDSBCLVDSAC+ LVDSAC- LPVDD LPVSS LVDDR18D LVDDR18A_1 LVDDR18A_2 E18 F17 E19 G20 H20 LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8 G19 E20 F20 H18 G18 F19 H19 F18 GFX_CLKP GFX_CLKN HTTSTCLK HTREFCLK SB_CLKP SB_CLKN TVCLKIN DFT_GPIO0/RSV DFT_GPIO1/RSV DFT_GPIO2/RSV DFT_GPIO3/RSV DFT_GPIO4/RSV DFT_GPIO5/RSV TMDS_HPD BMREQb I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N MIS. STRP_DATA DDC_DATA TESTMODE +3VS LVDSB0+ LVDSB0LVDSB1+ LVDSB1LVDSB2+ LVDSB2- <17> <17> <17> <17> <17> <17> LVDSA0+ LVDSA0LVDSA1+ LVDSA1LVDSA2+ LVDSA2- <17> <17> <17> <17> <17> <17> +1.8VS L4 1 2 FBML10160808121LMT_0603 0.1U_0402_16V4Z LVDSBC+ LVDSBCLVDSAC+ LVDSAC- <17> <17> <17> <17> 1 1 2 2 C178 C179 1U_0603_10V4Z LPVDD L6 0.1U_0402_16V4Z 1 2 FBML10160808121LMT_0603 1 1 +1.8VS C182 C183 1U_0603_10V4Z 2 2 LVDDR18D L7 LVDDR18A 0.1U_0402_16V4Z 1 2 1 1 FBML10160808121LMT_0603 C184 2 2 C185 1U_0603_10V4Z ENVDD ENABLT E14 F14 F13 ENVDD ENABLT B8 A8 10K_0402_5% P23 R74 HTREFCLK N23 1 SBLINKCLK SBLINKCLK# E8 E7 2 +1.8VS <17> <17,37,38> @ HTREFCLK <16> SBLINKCLK <16> SBLINKCLK# <16> C13 C14 C15 A10 T21 PAD E10 EDID_DAT_LCD B10 E12 R80 EDID_DAT_LCD <17> 4.7K_0402_5% 1 2 2 216RS480M_BGA706 2 R81 4.7K_0402_5% R82 4.7K_0402_5% 1 Low, LOAD ROM STRAP ENABLE F12 E13 D13 D18 C18 B19 A19 D19 C19 D20 C20 LVDS_DIGON LVDS_BLON LVDS_BLEN CLOCKs 1 <20> <18> <18> <18> AVDDQ TV_CRMA TV_LUMA TV_COMPS TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N R453 1K_0402_5% 2 1 1 AVDD1 AVDD2 AVSSN1 AVSSN2 AVDDDI AVSSDI R72 1K_0402_5% 2 1 C176 10U_0805_10V4Z 1 B27 C27 D26 D25 C24 B24 LVDS 1 2 FBML10160808121LMT_0603 1 C175 0.1U_0402_16V4Z PLL PWR 1U_0603_10V4Z PM L3 CRT/TVOUT U4D AVDDI +1.8VS EDID_CLK_LCD EDID_DAT_LCD Compal Secret Data Security Classification Issued Date 2005/03/01 Deciphered Date 2005/04/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title RS480M VIDEO_IF/CLOCK GEN Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 13 of 53 5 4 3 2 1 C B VSS89 A U15 V14 R15 T14 N15 V12 N13 P14 U17 T16 R17 P12 T12 R13 W13 W17 P18 V18 M18 U13 N17 W15 V16 T18 M14 M12 M16 P16 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 U19 AC16 AG18 AC23 AD8 AD11 AD13 AD16 AD19 AD23 AG5 AG6 AG21 AD17 AG15 AG12 AF30 AG24 AG9 AC19 AG27 AC11 AD7 AJ30 AC21 AK5 AK10 AC13 AD21 AK22 AK29 W19 AE26 AE27 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 T27 R27 AD28 F24 F27 G28 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSSA1 VSSA2 VSSA3 VSSA4 VSSA5 VSSA6 VSSA7 VSSA8 VSSA9 VSSA10 VSSA11 VSSA12 VSSA13 VSSA14 VSSA15 VSSA16 VSSA17 VSSA18 VSSA19 VSSA20 VSSA21 VSSA22 VSSA23 VSSA24 VSSA25 VSSA26 VSSA27 VSSA28 VSSA29 VSSA30 VSSA31 VSSA32 VSSA33 VSSA34 VSSA35 VSSA36 VSSA37 VSSA38 VSSA39 VSSA40 VSSA41 VSSA42 VSSA43 VSSA44 VSSA45 VSSA46 VSSA47 VSSA48 VSSA49 VSSA50 VSSA51 VSSA52 VSSA53 VSSA54 VSSA55 VSSA56 VSSA57 VSSA58 VSSA59 VSSA60 VSSA61 VSSA62 VSSA63 VSSA64 VSSA65 VSSA66 VSSA67 VSSA68 R5 AE5 V5 N3 F7 F5 R3 AA6 T3 M6 C5 F8 M8 Y8 V3 C3 W3 K8 D3 C6 AA3 A2 AB3 P8 J6 C8 AD3 V8 F3 AE3 AF3 M5 AB7 G3 B4 P7 AA5 C9 C7 J5 R6 J3 AD5 D6 C4 K3 AB8 T7 Y7 AD6 K7 H7 M3 V6 H8 C2 AG3 L6 AJ1 M7 V7 F6 E6 U5 U6 E5 L5 T8 +1.2V_HT +1.2V_HT 2005.08.11 for ATI Suggestion VSSA22 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 2 1 C191 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 C230 C232 C240 C242 C200 C243 C244 C238 C205 C234 C207 C236 C252 +2.5VS VSSA59 +1.8VS 22U_1206_10V4Z 2 1 C215 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C216 C217 C218 C219 C220 C221 C222 C223 C224 C226 C228 C229 C231 C233 C235 C237 C239 C241 L10 FBML10160808121LMT_0603 VDD18 1 2 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA12_13 1 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 22U_1206_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z F28 H28 M24 J28 N19 K28 T23 L27 2 2 2 2 2 1 C250 1 1 1 1 C253 C255 C257 C259 C261 4.7U_0805_6.3V6K N27 U27 V27 G27 V24 H27 K24 AB24 P27 J27 AA27 K27 P24 AB27 AB23 V23 G23 E23 W23 K23 J23 H23 U23 AA23 D23 F23 C23 B23 A23 VDDHT30 A29 VDDHT31 AC30 AK23 AK28 AK11 AK4 AE30 AC14 AD12 AC18 AC20 AD10 AD14 AD15 AD20 AC10 AD18 AC12 AD22 AC22 AH15 H15 AC17 AC15 B21 C21 A22 B22 C22 F21 F22 E21 G21 VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD_HT20 VDD_HT21 VDD_HT22 VDD_HT23 VDD_HT24 VDD_HT25 VDD_HT26 VDD_HT27 VDD_HT28 VDD_HT29 VDD_HT30 VDD_HT31 VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6 VDD_MEM7 VDD_MEM8 VDD_MEM9 VDD_MEM10 VDD_MEM11 VDD_MEM12 VDD_MEM13 VDD_MEM14 VDD_MEM15 VDD_MEM16 VDD_MEM17 VDD_MEM18 VDD_MEMCK VDD18_1 VDD18_2 VDD18_3 VDD_CORE47 VDD_CORE46 VDD_CORE45 VDD_CORE44 VDD_CORE43 VDD_CORE42 VDD_CORE41 VDD_CORE40 VDD_CORE39 VDDA12_14 VDDA12_1 VDDA12_2 VDDA12_3 VDDA12_4 VDDA12_5 VDDA12_6 VDDA12_7 VDDA12_8 VDDA12_9 VDDA12_10 VDDA12_11 VDDA12_12 VDDA12_13 VDDA18_1 VDDA18_2 VDDA18_3 VDDA18_4 VDDA18_5 VDDA18_6 VDDA18_7 VDDA18_8 VDDA18_9 VDDA18_10 VDDA18_11 VDDA18_12 VDDA18_13 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9 VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35 VDD_CORE36 VDD_CORE37 VDD_CORE38 H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7 B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5 AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21 C190 1 2 22U_1206_10V4Z C192 1 2 1U_0603_10V4Z C195 C198 C202 C201 2 2 2 2 1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 0.1U_0402_16V4Z D 2005.08.11 for ATI Suggestion VDDA12_13 R84 0_0805_5% 2 1 VDDA18 C210 C211 C212 C213 C214 1 1 1 1 1 2 2 2 2 2 +1.8VS 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18_13 +1.2V_HT C702 1 2 @ 100U_D2_6.3M_R45 C225 1 C227 1 2 22U_1206_10V4Z 2 22U_1206_10V4Z C197 C199 C193 C194 C196 C203 C204 C206 C208 C245 C246 C247 C248 C249 C251 C209 C254 C256 C258 C260 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 07/04 for +1.2V_HT ripple 216RS480M_BGA706 VSSA22 B VDDA18_13 1 M27 H24 N28 P25 P28 E26 K25 U28 V25 V28 R23 2 C262 4.7U_0805_6.3V6K VSSA59 VDDHT30 1 2 C263 4.7U_0805_6.3V6K VSS30 VDDHT31 1 2 C264 4.7U_0805_6.3V6K VSS89 A Compal Secret Data Security Classification 2005/03/01 Issued Date 216RS480M_BGA706 5 2 U4E + VSS30 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 POWER D G10 G12 AD29 AD27 AC27 G15 G14 Y24 G13 E9 D15 D9 AD9 G11 F16 G30 AB28 AB25 D12 AD24 AA28 G17 Y23 AC9 R19 Y27 C28 G16 F25 B30 T24 F26 W27 D11 H11 AD25 H17 H10 H16 H14 E16 D10 E15 F15 GROUND U4F 2005/04/06 Deciphered Date 4 3 Title RS480M Power/GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 14 of 53 5 4 +2.5VS VRAM@ 10U_0805_10V4Z 1 VRAM@ C265 10U_0805_10V4Z 1 C266 2 VRAM@ 0.1U_0402_16V4Z 1 C267 2 1 2 VRAM@ 0.1U_0402_16V4Z 1 C268 C269 2 VRAM@ 0.1U_0402_16V4Z 3 1 1 C270 2 VRAM@ 0.1U_0402_16V4Z 2 2 VRAM@ 0.1U_0402_16V4Z 1 C272 1 C273 2 1 C274 2 VRAM@ 0.1U_0402_16V4Z +2.5VS VRAM@ 10U_0805_10V4Z VRAM@ 0.1U_0402_16V4Z 1 C271 2 VRAM@ C275 10U_0805_10V4Z 2 1 2 VRAM@ 0.1U_0402_16V4Z 1 C276 C277 2 VRAM@ 0.1U_0402_16V4Z 1 VRAM@ 0.1U_0402_16V4Z 1 C278 2 1 1 C279 2 VRAM@ 0.1U_0402_16V4Z VRAM@ 0.1U_0402_16V4Z C280 2 1 1 C281 2 VRAM@ 0.1U_0402_16V4Z 1 C282 2 VRAM@ 0.1U_0402_16V4Z C283 2 VRAM@ 0.1U_0402_16V4Z 1 C284 2 2 VRAM@ 0.1U_0402_16V4Z D D C 1 (20mil) 1 C286 VRAM@ 0.1U_0402_16V4Z 2 R88 VRAM@ 1K_0402_1% 2 VREF_1 49 VREF NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 29 30 31 32 35 36 37 38 39 40 28 41 42 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12 NC0 NC1 NC2 NC3 NC4 NC5 NC6 14 17 19 25 43 50 53 CK CK# CKE 45 46 44 NMCLKA0 NMCLKA0# NMCKEA BA0 BA1 26 27 NMAA13 NMAA14 CS# RAS# CAS# WE# 24 23 22 21 NMCSA0# NMRASA# NMCASA# NMWEA# VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2 6 12 52 58 64 34 48 66 <11> NMAA[0..14] NMAA[0..14] NMDA[0..63] <11> NMDA[0..63] <11> NDQMA[0..7] <11> NDQSA[0..7] NDQMA[0..7] ND QSA[0..7] +2.5VS 1 UDQS0 UDM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 18 33 3 9 15 55 61 R85 VRAM@ 1K_0402_1% 2 51 47 54 56 57 59 60 62 63 65 VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 NMCKEA <11> (20mil) 1 2 R86 VRAM@ 1K_0402_1% NDQSA2 NDQMA2 NMDA16 NMDA17 NMDA18 NMDA19 NMDA20 NMDA21 NMDA22 NMDA23 LDQS0 LDM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 1 NMCSA0# NMRASA# NMCASA# NMWEA# <11> <11> <11> <11> R87 VRAM@ 1K_0402_1% C285 VRAM@ 0.1U_0402_16V4Z 2 1 +2.5VS 16 20 2 4 5 7 8 10 11 13 +2.5VS U6 +2.5VS U7 NDQSA3 NDQMA3 NMDA24 NMDA25 NMDA26 NMDA27 NMDA28 NMDA29 NMDA30 NMDA31 2 NDQSA5 NDQMA5 NMDA40 NMDA41 NMDA42 NMDA43 NMDA44 NMDA45 NMDA46 NMDA47 16 20 2 4 5 7 8 10 11 13 LDQS0 LDM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NDQSA4 NDQMA4 NMDA32 NMDA33 NMDA34 NMDA35 NMDA36 NMDA37 NMDA38 NMDA39 51 47 54 56 57 59 60 62 63 65 UDQS0 UDM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VREF_2 49 VREF NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 29 30 31 32 35 36 37 38 39 40 28 41 42 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12 VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 1 18 33 3 9 15 55 61 NC0 NC1 NC2 NC3 NC4 NC5 NC6 14 17 19 25 43 50 53 CK CK# CKE 45 46 44 NMCLKA0 NMCLKA0# NMCKEA BA0 BA1 26 27 NMAA13 NMAA14 CS# RAS# CAS# WE# 24 23 22 21 NMCSA0# NMRASA# NMCASA# NMWEA# VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2 6 12 52 58 64 34 48 66 C @ HY5DU561622CT-4_TSOPII66 @ HY5DU561622CT-4_TSOPII66 +2.5VS U8 2 51 47 54 56 57 59 60 62 63 65 UDQS0 UDM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VREF_1 49 NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 29 30 31 32 35 36 37 38 39 40 28 41 42 VREF A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12 NC0 NC1 NC2 NC3 NC4 NC5 NC6 CK CK# CKE BA0 BA1 CS# RAS# CAS# WE# VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2 14 17 19 25 43 50 53 NMCLKA0 NMCLKA0 NMCLKA0# NMCKEA 45 46 44 26 27 NMAA13 NMAA14 24 23 22 21 NMCSA0# NMRASA# NMCASA# NMWEA# NMCLKA0 <11> R89 VRAM@ 56_0402_5% C287 VRAM@ 0.01U_0402_16V7K 1 2 1 C289 VRAM@ 0.1U_0402_16V4Z R90 VRAM@ 56_0402_5% 6 12 52 58 64 34 48 66 2 NMCLKA0# NMCLKA0# <11> +2.5VS +2.5VS VRAM@ VRAM@ 220P_0402_50V8J 1000P_0402_50V7K 220P_0402_50V8J VRAM@ 1000P_0402_50V7K NDQSA6 NDQMA6 NMDA48 NMDA49 NMDA50 NMDA51 NMDA52 NMDA53 NMDA54 NMDA55 16 20 2 4 5 7 8 10 11 13 LDQS0 LDM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NDQSA7 NDQMA7 NMDA56 NMDA57 NMDA58 NMDA59 NMDA60 NMDA61 NMDA62 NMDA63 51 47 54 56 57 59 60 62 63 65 UDQS0 UDM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VREF_2 49 NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 29 30 31 32 35 36 37 38 39 40 28 41 42 @ HY5DU561622CT-4_TSOPII66 Z ZZ VRAM@ A 2 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12 NC0 NC1 NC2 NC3 NC4 NC5 NC6 CK CK# CKE BA0 BA1 CS# RAS# CAS# WE# VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2 1 18 33 3 9 15 55 61 14 17 19 25 43 50 53 B 45 46 44 NMCLKA0 NMCLKA0# NMCKEA 26 27 NMAA13 NMAA14 24 23 22 21 NMCSA0# NMRASA# NMCASA# NMWEA# 6 12 52 58 64 34 48 66 1 C740 1 1 C738 2 C739 VRAM@ 2 X 7 6 V R AM 2 C741 2 1 220P_0402_50V8J X 7 6 V R AM VREF VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 @ HY5DU561622CT-4_TSOPII66 2 C737 Z ZZ +2.5VS U9 1 18 33 3 9 15 55 61 1 NDQSA0 NDQMA0 NMDA0 NMDA1 NMDA2 NMDA3 NMDA4 NMDA5 NMDA6 NMDA7 VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 2 LDQS0 LDM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 1 1 C288 VRAM@ 0.1U_0402_16V4Z 16 20 2 4 5 7 8 10 11 13 2 B NDQSA1 NDQMA1 NMDA8 NMDA9 NMDA10 NMDA11 NMDA12 NMDA13 NMDA14 NMDA15 1000P_0402_50V7K VRAM@ 1 C742 1 1 C743 2 C744 2 VRAM@ A 220P_0402_50V8J VRAM@ 1000P_0402_50V7K 07/04 For EMI Compal Secret Data Security Classification SAMSUNG@ SAMSUNG X76 VRAM 2005/03/01 Issued Date HYNIX@ HYNIX X76 VRAM 2005/04/06 Deciphered Date 5 4 3 Title VGA DDR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 15 of 53 A B C D E +3V_CLK (40 mils) F 0.1U_0402_16V4Z C293 2 1 C294 2 10U_0805_10V4Z 1 C295 2 1 2 0.1U_0402_16V4Z C296 1 C297 2 1 C298 2 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 43 14 21 35 32 51 48 56 2 L13 CHB2012U121_0805 3 XTALIN_CLK XTALOUT_CLK 2 NB_REFCLK R101 1 R106 1 6 NC SB_SCLK SB_SDAT 7 8 SCLK SDATA 2 33_0402_5% 52 2 475_0402_1% @ R111 10K_0402_5% 1 2 NC_CLKSEL1# NC_CLKSEL0# <28> NC_CLKSEL0# 37 11 10 1 2 39 38 CPUCLK8T0 CPUCLK8C0 CPUCLK8T1 CPUCLK8C1 45 44 41 40 CPUCLK0H CPUCLK0L R91 R92 SRCCLKT7 SRCCLKC7 SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 ATIGCLKT1 ATIGCLKC1 ATIGCLKT0 ATIGCLKC0 SRCCLKT0 SRCCLKC0 12 13 16 17 18 19 22 23 24 25 27 28 30 29 34 33 PCIECLK0_R PCIECLK0#_R PCIECLK1_R PCIECLK1#_R 17_EXP@ 17_EXP@ R93 1 R95 1 R469 1 R471 1 15_EXP@ 15_EXP@ 2 2 2 2 SBSRCCLK_R SBSRCCLK#_R R97 R99 2 33_0402_5% 2 33_0402_5% REF2 IREF CLKREQB# CLKREQA# GND GND GNDSRC GNDSRC GNDSRC GNDSRC GNDATI GNDPCI GNDHTT GNDCPU PCICLK0 FS0/REF0 FS1/REF1 FS2 USB_48MHz HTTCLK0 SBLINKCLK_R SBLINKCLK#_R 2 15_0402_1% 2 15_0402_1% 1 1 1 1 R107 1 R109 1 CPUCLK0_H <6> CPUCLK0_L <6> 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% PCIECLK0 PCIECLK0# PCIECLK1 PCIECLK1# 17_EXP@ 17_EXP@ R94 1 R96 1 R470 1 R472 1 15_EXP@ 15_EXP@ 2 2 2 2 SBSRCCLK SBSRCCLK# R98 1 R100 1 2 49.9_0402_1% 2 49.9_0402_1% SBLINKCLK SBLINKCLK# 2 33_0402_5% 2 33_0402_5% R108 1 R110 1 PCIECLK0 PCIECLK0# 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% PCIECLK1 PCIECLK1# PCIECLK1 <28> PCIECLK1# <28> SBSRCCLK SBSRCCLK# SBSRCCLK <19> SBSRCCLK# <19> 2 49.9_0402_1% 2 49.9_0402_1% SBLINKCLK SBLINKCLK# FS0 FS1 FS2 4 47 R112 1 2 33_0402_5% R113 1 2 33_0402_5% CLK_48M_CB <25> @ R114 1 R115 1 2 33_0402_5% 2 33_0402_5% USBCLK_EXT <20> HTREFCLK <13> Express Card(17) Express Card(15.4) 2 50 54 53 9 PCIECLK0 <28> PCIECLK0# <28> SBLINKCLK <13> SBLINKCLK# <13> A link Express A link Express SB_OSC_INT <20> 1 5 55 36 26 20 15 31 49 46 42 VDDA GNDA VDD48 X1 X2 <8,9,20,28> SB_SCLK <8,9,20,28> SB_SDAT <13> VDDCPU VDDSRC VDDSRC VDDSRC VDDATI VDD_PCI VDDHTT VDDREF 1 2 Y1 2 1 C300 22P_0402_50V8J 1 2 14.31818MHz_20P_1BX14318BE1A C301 22P_0402_50V8J 2 1 U10 +3VS C299 2.2U_0805_10V4Z 1 2 1 C291 10U_0805_10V4Z 1 C290 0.1U_0402_16V4Z C292 2 L12 CHB2012U121_0805 2 1 0.1U_0402_16V4Z +3V_VDD 1 2 L11 CHB2012U121_0805 1 +3VS +3V_CLK 0.1U_0402_16V4Z 1 H +3V_VDD (20mils) +3V_VDD +3VS G R116 51.1_0402_1% 2 ICS951412AGLFT_TSSOP56 3 3 +3V_CLK 1 1 R120 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 R119 2 2 1 EXT CLK FREQUENCY SELECT TABLE(MHZ) R118 FS2 FS1 FS0 1 1 2 @ 8.2K_0402_5% R122 2 R121 R123 @ 8.2K_0402_5% 2 1 FS0 FS1 FS2 @ 8.2K_0402_5% * 4 SRCCLK [2:1] HTT PCI USB 0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved 0 0 1 X 100.00 X/3 X/6 48.00 Reserved 0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved 0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved 1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved 1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved 1 1 1 200.00 100.00 66.66 33.33 48.00 Normal HAMMER operation 2005/03/01 2005/04/06 Deciphered Date B C D 4 E Title Clock Generator THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A COMMENT Compal Secret Data Security Classification Issued Date CPU F Size Document Number Custom Date: Tuesday, August 30, 2005 G R ev 0.8 LA-2771 Sheet 16 H of 53 A B C D E F G H +3VS 2 LCD Panel & inverter Connector 1 1 R124 JP6 C302 0.01U_0402_16V7K 1 2 <13> <13> <13> <13> LVDSB1+ LVDSB1- LVDSB1+ LVDSB1- LVDSBC+ LVDSBCWL_LED# DISPOFF# INVT_PWM DAC_BRIG LVDSBC+ LVDSBC- <37,38> INVT_PWM <37,38> DAC_BRIG +5VS EDID_CLK_LCD <13> EDID_CLK_LCD EDID_DAT_LCD <13> EDID_DAT_LCD INVPWR_B+ GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 4.7K_0402_5% 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 LVDSB2+ LVDSB2- LVDSB2+ <13> LVDSB2- <13> LVDSB0+ LVDSB0- <37,38> D2 CH751H-40_SC76 1 2 BKOFF# LVDSB0+ <13> LVDSB0- <13> LVDSA1+ LVDSA1- LVDSA1+ <13> LVDSA1- <13> LVDSAC+ LVDSAC- 1 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 +LCDVDD +LCDVDD DISPOFF# D3 CH751H-40_SC76 1 2 <13,37,38> ENABLT LVDSAC+ <13> LVDSAC- <13> LVDSA2+ LVDSA2- LVDSA2+ LVDSA2- LVDSA0+ LVDSA0- <13> <13> B+ LVDSA0+ <13> LVDSA0- <13> INVPWR_B+ L14 1 2 0_0805_5% @ L15 1 2 0_0805_5% +3VS ACES_88242-4000 2 2 2 WL_LED# 5/6 Add current limit resister Q4 MMBT3904_SOT23 WL_LED@ 2 2 <30,34,35> WIRELESS_LED WL_LED@ R127 1K_0402_5% 1 2 1 WIRELESS_LED 3 1 R581 150_0402_5% WL_LED@ 1 R128 100K_0402_5% WL_LED@ 3 3 +5VALW Q5 SI2301BDS_SOT23 R130 100K_0402_5% 1 3 D 1 1 2 100_0402_1% S R129 +3VS +LCDVDD 2 1 +LCDVDD 2N7002_SOT23 Q6 2 G D 0.047U_0402_16V4Z 2 G S C303 1 C304 1 1 3 1 Q7 DTC124EK_SC59 ENVDD ENVDD 2 2 4.7U_0805_10V4Z 2 C306 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 3 <13> 2 1 C305 4 4 Compal Secret Data Security Classification Issued Date 2005/03/01 2005/04/06 Deciphered Date A B C D E Title LVDS Panel Interface THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. F Size Document Number Custom Date: Tuesday, August 30, 2005 G R ev 0.8 LA-2771 Sheet 17 H of 53 A B C D E +R_CRT_VCC , +CRTVDD (40mils) +5VS +CRTVDD D6 2 CRT CONNECTOR +R_CRT_VCC F1 1 1 RB491D_SOT23 2 1.1A_6VDC_FUSE 1 C307 0.1U_0402_16V4Z 6/11 change D6 from RB411to RB491(higher current rating) 2 1 U12 Y CRT_VSYNC_R 4 2 1 2 3 74AHCT1G125GW_SOT353-5 S D 3VDDCDA <13> Q9 2N7002_SOT23 2 G 1 1 1 2 2 3VDDCCL S 33_0402_5% 33_0402_5% 3VDDCDA 3 3 2 G 1 1 D C RT_VSYNCRFL 1 2 L20 FBM-L11-160808-800LMT_0603 16 17 Q8 2N7002_SOT23 R553 1 2 L19 FBM-L11-160808-800LMT_0603 CR T_HSYNCRFL C315 10P_0402_50V8K 1 5 P A OE# CRT_VSYNC 2 G <13> CRT_VSYNC 2 C318 220P_0402_25V8K 2 +CRTVDD R135 4.7K_0402_5% 1 R137 20_0402_5% 2 CRTL_B 1 R134 4.7K_0402_5% 2 2 1 220P_0402_25V8K R552 1 R136 20_0402_5% 3 74AHCT1G125GW_SOT353-5 2 1 C316 CR T_HSYNC_R 4 Y 2 1 C317 10P_0402_50V8K A 2 1 CRTL_G C313 22P_0402_25V8K 5 P 2 OE# CRT_HSYNC U11 G <13> CR T_HSYNC 1 C314 1 2 0.1U_0402_16V4Z 1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 M_SEN# CRTL_R M_SEN# C312 22P_0402_25V8K R131 75_0402_5% 1 2 CRT_B <37,38> C311 22P_0402_25V8K CRT_B C310 10P_0402_50V8K <13> CRT_G R133 75_0402_5% 1 2 CRT_G C309 10P_0402_50V8K <13> CRT_R R132 75_0402_5% 1 2 CRT_R C308 10P_0402_50V8K <13> +CRTVDD 2 1 JP8 SUYIN_070112FR015S222XU L16 FCM2012C-800_0805 1 2 L17 FCM2012C-800_0805 1 2 L18 FCM2012C-800_0805 1 2 R138 3VDDCCL <13> R139 4.7K_0402_5% 2 +3VS 4.7K_0402_5% TV-Out Connector S-Video CRMA_CL TV_COMPS L23 FLM1608081R8K_0603 1 2 COMPS_CL 1 2 2 R143 1 2 1 2 1 2 C324 330P_0402_50V7K 2 1 1 2 3 4 5 6 7 C323 330P_0402_50V7K 2 1 JP9 C322 330P_0402_50V7K 1 C321 270P_0402_50V7K TV_CRMA C320 270P_0402_50V7K LUMA_CL L22 FLM1608081R8K_0603 1 2 C319 270P_0402_50V7K TV_COMPS L21 FLM1608081R8K_0603 1 2 R140 75_0402_1% 2 1 <13,40> TV_CRMA TV_LUMA R142 75_0402_1% 2 1 <13,40> 3 TV_LUMA R141 75_0402_1% 2 1 <13,40> 1 2 3 4 5 6 7 3 GND GND 8 9 SUYIN_030006FR007T107ZL TVGND 0_0805_5% 4 4 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title CRT Connector & TV-OUT CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 18 of 53 4 3 <12> <12> <12> <12> 8.2K_0804_8P4R_5% SB_TX0P SB_TX0N SB_TX1P SB_TX1N R151 R153 R154 R156 RP52 1 2 3 4 8 7 6 5 PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 1 1 1 1 2 2 2 2 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% L24 2 +1.8VS R157 R158 PCIE_VDDR 1 SB_TX0P M29 SB_TX0N N29 SB_TX1P M28 SB_TX1N N28 SB_TX2P J29 SB_TX2N K29 SB_TX3P J28 SB_TX3N K28 150_0402_1% 2 1 G27 2 1 H27 150_0402_1% 2 1 G28 4.12K_0402_1% R30 FBM-L11-321611-260-LMT_1206 8.2K_0804_8P4R_5% R159 RP53 1 2 3 4 8 7 6 5 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 PCIE_PVDD C331 1 2 1U_0603_10V4Z C332 1 2 10U_0805_10V4Z C333 1 2 0.1U_0402_16V4Z L25 8.2K_0804_8P4R_5% 1 2 3 4 1 FBM-L11-321611-260-LMT_1206 RP54 C 2 +1.8VS 8 7 6 5 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5 C335 1 C336 C337 C338 C339 C340 C341 C342 C343 8.2K_0804_8P4R_5% 1 2 R161 8.2K_0402_5% 1 2 R162 8.2K_0402_5% PCI_REQ#6 PCI_GNT#6 PCIE_VDDR 2 22U_1206_10V4Z 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z RP55 1 2 3 4 8 7 6 5 PCI_FRAME# PCI_IR DY# PC I_TRDY# PCI_STOP# PCIE_PVDD (20mils) PCIE_VDDR (40mils) 8.2K_0804_8P4R_5% PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# RP56 8 7 6 5 PCI_SERR# PCI_PAR PCI_DEVSEL# LOCK# 8.2K_0804_8P4R_5% 2 1 R169 10K_0402_5% PCI_CLKRUN# R173 20M_0603_5% 2 1 2 PCI_PERR# 1 B C344 18P_0402_50V8J 1 2 2 1 R166 8.2K_0402_5% <25> <30> <29> <25> PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# R171 20M_0603_5% 1 2 3 4 Y2 4 1 OUT NC IN NC PCIE_VSS_1 PCIE_VSS_2 PCIE_VSS_3 PCIE_VSS_4 PCIE_VSS_5 PCIE_VSS_6 PCIE_VSS_7 PCIE_VSS_8 PCIE_VSS_9 PCIE_VSS_10 PCIE_VSS_11 PCIE_VSS_12 PCIE_VSS_13 PCIE_VSS_14 PCIE_VSS_15 AJ8 AK7 AG5 AH5 AJ5 AH6 AJ6 AK6 AG7 AH7 B2 SB_32KH0 B1 C345 18P_0402_50V8J <4,13> LDTSTOP# <13> ALLOW_LDTSTOP <6> H_PWRGD <13> <6> BMREQ# H_RST# LDTSTOP# ALLOW_LDTSTOP H_PWRGD BMREQ# H_RST# PCIE_PVDD H28 F29 H29 H26 F27 G29 L29 J26 L28 J27 N27 M26 K27 P29 P30 SB_32KHI 2 PCIE_CALI PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 PCIE_VDDR_8 PCIE_VDDR_9 32.768KHZ_12.5PF_6H03200468 1 PCIE_CALRP PCIE_CALRN F26 R29 G26 P26 K26 L26 P28 N26 P27 3 2 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N C29 A28 C28 B29 D29 E4 B30 F28 E28 E29 D25 E27 D27 D28 CPU_STP#/DPSLP# PCI_STP# INTA# INTB# INTC# INTD# INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 X1 X2 CPU_PG/LDT_PG INTR/LINT0 NMI/LINT1 INIT# SMI# SLP#/LDT_STP# IGNNE# A20M# FERR# STPCLK#/ALLOW_LDTSTP LDT_PG/SSMUXSEL/GPIO0 DPRSLPVR BMREQ# LDT_RST# CHS-215SB400-02_BGA564 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1# SERIRQ RTCCLK RTC_IRQ#/ACPWR_STRAP VBAT RTC_GND AG25 AH25 AJ25 AH24 AG24 AH26 AG26 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LDRQ0# LDRQ1# AK27 SIRQ C2 F3 RTC_CLK AUTO_ON# C329 1 2 @ 0.1U_0402_16V4Z +3VALW C330 1 2 2 0.1U_0402_16V4Z I O 2 33_0402_5% PCI_RST# R155 1 3 PCI_RST# <25,27,29,30,35,37,38> U44A SN74LVC125APWLE_TSSOP14 PC I_AD[0..31] PCI_AD[0..31] <23,25,29,30> A_RST# 5 I U44B O R144 33_0402_5% 1 2 6 C NB_RST# <13,24,28,35> SN74LVC125APWLE_TSSOP14 +3VS PCI_CBE#0 <25,29,30> PCI_CBE#1 <25,29,30> PCI_CBE#2 <25,29,30> PCI_CBE#3 <25,29,30> PCI_FRAME# <25,29,30> PCI_DEVSEL# <25,29,30> PCI_IRDY# <25,29,30> PCI_TRDY# <25,29,30> PCI_PAR <25,29,30> PCI_STOP# <25,29,30> PCI_PERR# <25,29,30> PCI_SERR# <25,29,30> SIRQ R163 1 2 10K_0402_5% LDRQ0# LDRQ1# R164 1 R165 1 2 10K_0402_5% 2 10K_0402_5% LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 R167 R168 R170 R172 2 2 2 2 1 1 1 1 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% PCI_REQ#1 <29> PCI_REQ#2 <25> PCI_REQ#3 <30> PCI_GNT#1 <29> PCI_GNT#2 <25> PCI_GNT#3 <30> B PCI_CLKRUN# <35> LPC_AD0 <35,37,38> LPC_AD1 <35,37,38> LPC_AD2 <35,37,38> LPC_AD3 <35,37,38> LPC_FRAME# <35,37,38> LDRQ0# <35> SIRQ BATT1 <25,35,37,38> CR2032 RTC BATTERY RTC_CLK <23> AUTO_ON# <23> A2 A1 JP10 +RTCVCC 2 C346 1 +RTCVCC C347 1U_0603_10V4Z W=20mils R174 1K_0402_5% 1 2 BATT1.1 J2 0.1U_0402_16V4Z JOPEN A + 1 W=20mils + - 2 2 PCI_PIRQF# PCI_PIRQE# PCI_PIRQG# PCI_PIRQH# AJ7 W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1 2 22_0402_5% 1 D 1 8 7 6 5 PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11 AD8/ROMA9 AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0#/ROMA10 CBE1#/ROMA1 CBE2#/ROMWE# CBE3# FRAME# DEVSEL#/ROMA0 IRDY# TRDY#/ROMOE# PAR/ROMA19 STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/PDMA_REQ0# REQ4#/PLL_BP33/PDMA_REQ1# REQ5#/GPIO13 REQ6#/GPIO31 GNT0# GNT1# GNT2# GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1# GNT5#/GPIO14 GNT6#/GPIO32 CLKRUN# LOCK# PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_FRAME# PCI_DEVSEL# PCI_IR DY# PC I_TRDY# PCI_PAR PCI_STOP# PCI_PERR# PCI_SERR# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4 PCI_REQ#5 PCI_REQ#6 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6 PCI_CLKRUN# LOCK# 14 RP51 1 2 3 4 PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N CLK_PCI_PCM <25> CLK_PCI_TPM <35> CLK_PCI_LAN <23,29> CLK_PCI_MINI <23,30> CLK_PCI_EC <23,37,38> CLK_PCI_SIO_R <23,35> CLK_PCI6 <23> CLK_PCI7 <23> CLK_PCI8 <23> 1 8.2K_0804_8P4R_5% M30 N30 K30 L30 H30 J30 F30 G30 P SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C OE# 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K G 2 2 2 2 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% 7 1 1 1 1 2 2 2 2 2 4 C325 C326 C327 C328 1 1 1 1 1 OE# SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX0P SB_RX0N SB_RX1P SB_RX1N PCICLK0_R R146 PCICLK1_R @ R451 PCICLK2_R R147 PCICLK3_R R148 PCICLK4_R R149 CLK_PCI_SIO_R CLK_PCI6 CLK_PCI7 CLK_PCI8 PCICLK9_R R150 PCICLKFB R152 <12> <12> <12> <12> L4 L3 L2 L1 M4 M3 M2 M1 N4 N3 N2 8.2K_0402_5% 2 1 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PC I CLKS 8 7 6 5 L PC 1 2 3 4 PCIE_RCLKP PCIE_RCLKN PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9 PCICLK_FB PCI INTERFACE RP50 D SBSRCCLK SBSRCCLK# SB400 A_RST# C PU AH8 SBSRCCLK L27 SBSRCCLK# M27 RTC <16> <16> 1 U14A PCI EXPRESS INTERFACE A_RST# +3VS 2 5/11 EMI change 8.2K_0402_5% R145 1 2 XTAL 5 A SUYIN_060003FA002TX00NL~D Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title SB400-PCI_EXP/PCI/LPC/RTC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 19 of 53 5 4 3 2 1 +3VALW R177 1 2 10K_0402_5% NC_CP# R178 1 2 4.7K_0402_5% SLP_S3# R179 1 2 4.7K_0402_5% SLP_S5# R181 1 2 4.7K_0402_5% PCIE_PME# R182 1 2 4.7K_0402_5% EC_FLASH# R184 1 2 10K_0402_5% SYS_RESET# R185 1 2 10K_0402_5% BT_ON# R186 1 2 10K_0402_5% BT_DET# R187 1 2 10K_0402_5% S3_STATE @ R556 1 2 10K_0402_5% KB_RST# U14B R190 1 2 2.2K_0402_5% SB_SCLK R191 1 2 2.2K_0402_5% SB_SDAT R192 1 2 10K_0402_5% LPC_SMI# R193 1 2 10K_0402_5% AGP_STP# R194 1 2 10K_0402_5% AGP_BUSY# PCIE_PME# <37,38> EC_RSMRST# <16> SB_OSC_INT R195 1 R196 1 R197 1 +3VALW AC97_RST# R205 1 2 10K_0402_5% AC97_BITCLK R207 1 2 10K_0402_5% AC97_SDIN0 R208 1 2 10K_0402_5% AC97_SDIN1 R209 1 EXP_RST# SB_SPKR SB_SCLK SB_SDAT +3VS Y4 1 1 1 1 R204 1 R206 1 2 2@ B25 C25 C23 D24 D23 A27 C24 A26 B26 B27 C26 C27 D26 ACPI/WAKE UP EVENTS ROM_CS#/GPIO1 GHI#/GPIO6 VGATE/GPIO7 AGP_STP#/GPIO4 AGP_BUSY#/GPIO5 FANOUT0/GPIO3 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 DDC2_SCL/GPIO11 DDC2_SDA/GPIO12 J2 K3 J3 K2 NC1 NC4 NC3 NC2 <31> AC97_SYNC <31> AC97_RST# <23,40> SB_SPDIFO SB_OSC_INT R210 1 R211 1 AC97_BITCLK 2 33_0402_5% AC97_SDIN0 AC97_SDIN1 AC97_SDIN2 2 33_0402_5% AC97_RST# SB_SPDIFO G1 G2 H4 G3 G4 H1 H3 H2 AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_SYNC AC_RST# SPDIF_OUT R212 @ 1M_0402_5% 1 C361 1 * 2 @20P_0402_50V8J HYNIX 128MB 14M_X2 GPIO12 0 GPIO11 1 SAMSUMG 128MB 1 1 No VRAM 0 0 Reserved 1 0 A15 B15 C15 D16 C16 D15 B8 C8 C7 B7 B6 A6 B5 A5 USBCLK_EXT <16> 11.8K_0603_1% 1 USB_VREFOUT OVCUR#0 BT_DET# LID_OUT# OVCUR#3 OVCUR#4 EC_SCI# BT_ON# EC_SMI# USBP7+ USBP7- A10 B10 USBP6+ USBP6- USB_HSDP5+ USB_HSDM5- A14 B14 USBP5+ USBP5- USB_HSDP4+ USB_HSDM4- A13 B13 USBP4+ USBP4- USB_HSDP3+ USB_HSDM3- A18 B18 USBP3+ USBP3- USB_HSDP2+ USB_HSDM2- A17 B17 USB_HSDP1+ USB_HSDM1- A21 B21 USBP1+ USBP1- USB_HSDP0+ USB_HSDM0- A20 B20 USBP0+ USBP0- AVDDC AVSSC AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24 2 R183 T19 PAD A11 B11 AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 10K_0402_5% 10K_0402_5% 2 @14.31818MHz_20P_1BX14318BE1A R199 R200 R201 R203 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% AGP_STP# AGP_BUSY# EXP_RST# SB_SPKR SB_SCLK SB_SDAT 2 10K_0402_5% 2 10K_0402_5% 2@ 10K_0402_5% 2 10K_0402_5% SIO_CLK 2 1 B 14M_X2 EXP_RST# 2 10K_0402_5% 2@ 20P_0402_50V8J 14M_X1/OSC B23 check ATI for 2'nd hdd <31> AC97_BITCLK <23,31> AC97_SDOUT <31> AC97_SDIN0 C357 1 A23 RSMRST# AC97_SDIN2 2 8.2K_0402_5% R198 1 SB_OSC_INT AK24 <28> <31> <8,9,16,28> <8,9,16,28> 2 10K_0402_5% D1 14M_X2 C R202 1 EC_RSMRST# USB INTERFACE <28> WL_ON 2 LPC_SMI# S3_STATE CH751H-40_SC76 SYS_RESET# PCIE_PME# USB PWR +3VS 48M_X1/USBCLK TALERT#/TEMP_ALERT#/GPIO10 48M_X2 BLINK/GPM6# USB_RCOMP PCI_PME#/GEVENT4# USB_VREFOUT RI#/EXTEVNT0# USB_ATEST1 SLP_S3# USB_ATEST0 SLP_S5# USB_OC0#/GPM0# PWR_BTN# USB_OC1#/GPM1# PWR_GOOD USB_OC2#/FANOUT1/GPM2# SUS_STAT# USB_OC3#/GPM3# TEST1 USB_OC4#/GPM4# TEST0 USB_OC5#/GPM5# GA20IN USB_OC6#/FAN_ALERT#/GEVENT6# KBRST# USB_OC7#/CASE_ALERT#/GEVENT7# SMBALERT#/THRMTRIP#/GEVENT2# LPC_PME#/GEVENT3# USB_HSDP7+ LPC_SMI#/EXTEVNT1# USB_HSDM7VOLT_ALERT#/S3_STATE/GEVENT5# SYS_RESET#/GPM7# USB_HSDP6+ WAKE#/GEVENT8# USB_HSDM6- CLK / RST EC_RSMRST# 2 10K_0402_5% R188 1 R189 1 D SB400 GPIO <37,38> EC_GA20 <37,38> KB_RST# <6> H_THERMTRIP# <30> WL_ON C6 D5 C4 D3 B4 E3 B3 C3 D4 F2 E2 AJ26 AJ27 D6 C5 A25 D8 D7 D2 (NOT USED) @ R557 1 <37,38> EC_THERM# <39> EC_FLASH# <37,38> EC_SWI# <28> NC_CP# <37,38> SLP_S3# <37,38> SLP_S5# <37,38> PWRBTN_OUT# <42> SB_PWRGD <13> SUS_STAT# EC_THERM# EC_FLASH# EC_SWI# NC_CP# SLP_S3# SLP_S5# PWRBTN_OUT# SB_PWRGD SUS_STAT# 2 10K_0402_5% 2 10K_0402_5% EC_GA20 KB_RST# H_THERMTRIP# 1 D7 AC 97 D OVCUR#0 <34> BT_DET# <34> LID_OUT# <37,38> OVCUR#3 <34> OVCUR#4 <35> EC_SCI# <37,38> BT_ON# <34> EC_SMI# <37,38> USBP7+ USBP7- <28> <28> Express Card 15.4 USBP6+ USBP6- <34> <34> Bluetooth USBP5+ USBP5- <35> <35> Right side USB USBP4+ USBP4- <35> <35> Right side USB USBP3+ USBP3- <34> <34> Left side USB USBP1+ USBP1- <40> <40> Docking USBP0+ USBP0- <34> <34> Left side USB C C21 C18 D13 D10 D20 D17 C14 C11 AVDDTX A16 AVDDC L26 FBM-L11-321611-260-LMT_1206 2 1 +3VALW AVDDRX AVDDTX B16 A9 A12 A19 A22 B9 B12 B19 B22 C9 C10 C12 C13 C17 C19 C20 C22 D9 D11 D12 D14 D18 D19 D21 D22 C350 1 2 10U_0805_10V4Z C351 1 2 1U_0603_10V4Z C352 1 C353 1 C354 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z L27 FBM-L11-321611-260-LMT_1206 2 1 +3VALW AVDDRX C355 1 2 10U_0805_10V4Z C356 1 2 1U_0603_10V4Z C358 1 C359 1 C360 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z B L28 FBM-L11-321611-260-LMT_1206 2 1 +3VALW AVDDC C362 1 2 10U_0805_10V4Z C363 1 2 1U_0603_10V4Z C364 1 2 0.1U_0402_16V4Z CHS-215SB400-02_BGA564 AVDDC (20mils) AVDDTX , AVDDRX (40mils) A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title SB400-USB/ACPI/AC97/GPIO THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 20 of 53 5 4 3 2 D 1 D U14C SATA_TX1+ SATA_TX1- AK18 AJ18 SATA_RX1SATA_RX1+ AK14 AJ14 SATA_TX2+ SATA_TX2- AK13 AJ13 SATA_RX2SATA_RX2+ AK11 AJ11 SATA_TX3+ SATA_TX3- AK10 AJ10 SATA_RX3SATA_RX3+ AJ15 SATA_CAL AJ16 SATA_X1 AK16 SATA_X2 AK8 B SATA_ACT# AH15 PLLVDD_SATA AH16 XTLVDD_SATA AG10 AG14 AH12 AG12 AG18 AG21 AH18 AG20 AVDD_SATA_1 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_4 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 AVDD_SATA_8 AG9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AH9 AG11 AG15 AG17 AG19 AG22 AG23 AF9 AH17 AH23 AH13 AH20 AK9 AJ12 AK17 AK23 AH10 AJ23 PRIMARY ATA 66/100 AK19 AJ19 SERIAL ATA SATA_RX0SATA_RX0+ AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20 AVSS_SATA_21 AVSS_SATA_22 AVSS_SATA_23 AVSS_SATA_24 AVSS_SATA_25 AVSS_SATA_26 AVSS_SATA_27 AVSS_SATA_28 AVSS_SATA_29 AVSS_SATA_30 AVSS_SATA_31 AVSS_SATA_32 PIDE_IORDY PIDE_IRQ PIDE_A0 PIDE_A1 PIDE_A2 PIDE_DACK# PIDE_DRQ PIDE_IOR# PIDE_IOW# PIDE_CS1# PIDE_CS3# AD30 AE28 AD27 AC27 AD28 AD29 AE27 AE30 AE29 AC28 AC29 PD_IORDY PD_IRQA PD_A0 PD_A1 PD_A2 PD_DACK# PD_DREQ# PD_IOR# PD_IOW# PD_CS#1 PD_CS#3 PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8 PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15 AF29 AF27 AG29 AH30 AH28 AK29 AK28 AH27 AG27 AJ28 AJ29 AH29 AG28 AG30 AF30 AF28 PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 V29 T27 T28 U29 T29 V30 U28 W29 W30 R27 R28 SD_IORDY SD_IRQA SD_SBA0 SD_SBA1 SD_SBA2 SD_DACK# SD_DREQ# SD_SIOR# SD_SIOW# SD_SCS1# SD_SCS3# V28 W28 Y30 AA30 Y28 AA28 AB28 AB27 AB29 AA27 Y27 AA29 W27 Y29 V27 U27 SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SIDE_IORDY SIDE_IRQ SIDE_A0 SIDE_A1 SIDE_A2 SIDE_DACK# SIDE_DRQ SIDE_IOR# SIDE_IOW# SIDE_CS1# SIDE_CS3# SECONDARY ATA 66/100 C SB400 SATA_TX0+ SATA_TX0- AK21 AJ21 SERIAL ATA POWER AK22 AJ22 SIDE_D0/GPIO15 SIDE_D1/GPIO16 SIDE_D2/GPIO17 SIDE_D3/GPIO18 SIDE_D4/GPIO19 SIDE_D5/GPIO20 SIDE_D6/GPIO21 SIDE_D7/GPIO22 SIDE_D8/GPIO23 SIDE_D9/GPIO24 SIDE_D10/GPIO25 SIDE_D11/GPIO26 SIDE_D12/GPIO27 SIDE_D13/GPIO28 SIDE_D14/GPIO29 SIDE_D15/GPIO30 AVSS_SATA_33 AVSS_SATA_34 AVSS_SATA_35 AVSS_SATA_36 AVSS_SATA_37 AVSS_SATA_38 AVSS_SATA_39 AVSS_SATA_40 AVSS_SATA_41 AVSS_SATA_42 AVSS_SATA_43 AVSS_SATA_44 AVSS_SATA_45 PD_IORDY <24> PD_IRQA <24> PD_A0 <24> PD_A1 <24> PD_A2 <24> PD_DACK# <23,24> PD_DREQ# <24> PD_IOR# <24> PD_IOW# <24> PD_CS#1 <24> PD_CS#3 <24> PD _D[0..15] SD_IORDY <24> SD_IRQA <24> SD_SBA0 <24> SD_SBA1 <24> SD_SBA2 <24> SD_DACK# <24> SD_DREQ# <24> SD_SIOR# <24> SD_SIOW# <24> SD_SCS1# <24> SD_SCS3# <24> PD_D[0..15] <24> C SD _D[0..15] SD_D[0..15] <24> AG13 AH22 AK12 AH11 AJ17 AH14 AH19 AJ20 AH21 AJ9 AG16 AK15 AK20 B CHS-215SB400-02_BGA564 A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title SB400-IDE/SATA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 21 of 53 +3VS U14D 2 22U_1206_10V4Z C366 C367 C368 C369 C370 C371 C372 C373 C374 C375 C376 C377 C378 C379 C380 C381 C382 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A30 D30 E24 E25 J5 K1 K5 N5 P5 R1 U5 U26 U30 V5 V26 Y1 Y26 AA5 AA26 AB5 AC30 AD5 AD26 AE1 AE5 AE26 AF6 AF7 AF24 AF25 AK1 AK4 AK26 AK30 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +1.8VS C383 1 C384 1 2 22U_1206_10V4Z 2 22U_1206_10V4Z C385 C386 C387 C388 C389 C390 C391 C392 C393 C394 C395 C396 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z M12 M13 M18 M19 N12 N13 N18 N19 V12 V13 V18 V19 W12 W13 W18 W19 +3VALW C397 1 2 22U_1206_10V4Z C398 C399 C400 C401 C402 2 2 2 2 2 1 1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A3 A7 E6 E7 E1 F5 +1.8VALW C403 1 2 10U_0805_10V4Z C404 1 C405 1 C406 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z C408 C409 C410 C411 2 2 2 2 E9 E10 E20 E21 E13 E14 E16 E17 C407 2 C30 AG6 AVDD_CK +1.8VS V5_VREF 2 C412 1U_0603_10V4Z 1 2 1 C413 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z +1.2V_HT 1 +3VS D8 CH751H-40_SC76 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z L29 FBM-L11-321611-260-LMT_1206 2 +5VS R213 1K_0402_5% 1 2 1 1 1 1 C414 1 2 10U_0805_10V4Z C415 1 2 1U_0603_10V4Z C416 1 2 0.1U_0402_16V4Z VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 SB400 POWER C365 1 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_1.8V_1 S5_1.8V_2 S5_1.8V_3 S5_1.8V_4 USB_PHY_1.8V_1 USB_PHY_1.8V_2 USB_PHY_1.8V_3 USB_PHY_1.8V_4 CPU_PWR V5_VREF A24 B24 AVDDCK AVSSCK A4 A8 A29 B28 C1 E5 E8 E11 E12 E15 E18 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 E19 E22 E23 E26 E30 F1 F4 G5 H5 J1 J4 K4 L5 M5 P1 R5 R26 T5 T26 T30 W1 W5 W26 Y5 AB26 AB30 AC5 AC26 AD1 AF5 AF8 AF23 AF26 AG8 AJ1 AJ24 AJ30 AK5 AK25 M14 M15 M16 M17 N14 N15 N16 N17 P12 P13 P14 P15 P16 P17 P18 P19 R12 R13 R14 R15 R16 R17 R18 R19 T12 T13 T14 T15 T16 T17 T18 T19 U12 U13 U14 U15 U16 U17 U18 U19 V14 V15 V16 V17 W14 W15 W16 W17 CHS-215SB400-02_BGA564 V5_VREF (20mils) AVDD_CK(40mils) Compal Secret Data Security Classification Issued Date 2005/03/01 Deciphered Date 2005/04/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title SB400-Power/GND Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 22 of 53 R223 10K_0402_5% R224 10K_0402_5% @ 2 R222 10K_0402_5% @ 2 R221 10K_0402_5% +3VS 1 1 R220 10K_0402_5% +3VS 2 R219 10K_0402_5% 1 1 1 1 +3VS 2 R218 10K_0402_5% +3VS 2 R217 10K_0402_5% @ +3VS 1 1 +3VS 2 R216 10K_0402_5% +3VS 2 2 R215 10K_0402_5% @ AUTO_ON# AC97_SDOUT RTC_CLK SB_SPDIFO CLK_PCI_MINI CLK_PCI_EC CLK_PCI_SIO_R CLK_PCI6 CLK_PCI7 CLK_PCI8 CLK_PCI_LAN 1 R233 10K_0402_5% @ R234 2 @ 10K_0402_5% 2 R232 10K_0402_5% 2 2 R231 10K_0402_5% @ 1 1 1 1 R230 10K_0402_5% @ 2 R229 10K_0402_5% @ 2 R228 10K_0402_5% @ 2 R227 10K_0402_5% 1 1 1 R226 10K_0402_5% 2 2 R225 @ 10K_0402_5% 2 1 D 1 <19> AUTO_ON# <20,31> AC97_SDOUT <19> RTC_CLK <20,40> SB_SPDIFO <19,30> CLK_PCI_MINI <19,37,38> CLK_PCI_EC <19,35> CLK_PCI_SIO_R <19> CLK_PCI6 <19> CLK_PCI7 <19> CLK_PCI8 <19,29> CLK_PCI_LAN +3VS 2 2 R214 10K_0402_5% D +3VALW 2 1 +3VS 1 +3VALW REQUIRED STRAPS 1 3 1 4 2 5 PCI_CLK2 PCI_CLK3 PCI_CLK4 CLK_PCI_LAN CLK_PCI_MINI CLK_PCI_EC CLK_PCI_SIO CLK_PCI6 CLK_PCI7 48MHz OSC MODE USB PHY PWRDOWN DISABLE INTERNAL 4 8MHz PCIE_CM_SET LOW CPU I/F = K8 DEFAULT DEFAULT DEFAULT DEFAULT ACPWRON PULL HIGH AUTO_ON# AC97_SDOUT RTC_CLK SB_SPDIFO MANUAL PWR ON USE DEBUG STRAPS INTERNAL RTC SIO 24MHz C DEFAULT DEFAULT PCI_CLK5 PCI_CLK8 ROM TYPE H,H = PCI ROM C H,L = PMC LPC ROM PCIE_CM_SET High CPU I/F = P4 DEFAULT 1 R242 10K_0402_5% @ R243 10K_0402_5% @ R244 10K_0402_5% 2 R241 10K_0402_5% @ +3VS 1 +3VS 2 R240 10K_0402_5% @ +3VS 2 R239 10K_0402_5% 2 R238 10K_0402_5% +3VS 1 +3VS 1 +3VS 2 2 R237 10K_0402_5% L,L = FWH ROM 1 +3VS L,H = NORMAL LPC ROM PD_DACK# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PD_DACK# PULL HIGH USE LONG RESET PULL LOW USE SHORT RESET 1 1 2 R253 10K_0402_5% R254 10K_0402_5% @ 2 1 R252 10K_0402_5% 2 R251 10K_0402_5% 2 R250 10K_0402_5% 2 2 R249 10K_0402_5% @ 1 1 1 1 R248 10K_0402_5% @ 2 R247 10K_0402_5% @ 2 R246 10K_0402_5% @ 2 2 R245 1K_0402_5% @ 1 B 1 B PD_DACK# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 1 <21,24> <19,25,29,30> <19,25,29,30> <19,25,29,30> <19,25,29,30> <19,25,29,30> <19,25,29,30> <19,25,29,30> <19,25,29,30> <19,25,29,30> +3VS R236 10K_0402_5% 2 2 R235 10K_0402_5% EXTERNAL 4 8MHz USB PHY PWRDOWN ENABLE DEFAULT 1 1 DEBUG STRAPS +3VS 1 +3VS 48MHz XTAL MODE SIO 48MHz 2 DEFAULT EXTERNAL RTC (NOT SUPPORTED W/ IT8712 ) 1 IGNORE DEBUG STRAPS 2 AUTO PWR ON 1 PULL LOW PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 RESERVED RESERVED RESERVED RESERVED BYPASS PCI PLL BYPASS ACPI BCLK BYPASS IDE PLL PCI_AD25 USE EEPROM PCIE STRAPS PCI_AD24 USE PCI PLL USE ACPI BCLK USE IDE PLL USE DEFAULT PCIE STRAPS DEFAULT DEFAULT DEFAULT DEFAULT PCI_AD23 RESERVED DEFAULT A Compal Secret Data Security Classification 2005/03/01 Issued Date A 2005/04/06 Deciphered Date 5 4 3 Title Hardware Trap THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 23 of 53 5 4 3 2 1 Main HDD Second HDD +5VS 10U_0805_10V4Z +5VS 2HDD@ 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2HDD@ 0.1U_0402_16V4Z 1 1 @ C719 + 100U_C_4VM 1 C417 2 1 C418 2 1 C419 2 2 2 1U_0603_10V4Z 1 @ C720 + 100U_C_4VM C420 1 C421 2 2 2 2 JP11 NB_RST# PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0 2 PD_IOR# @C726 1000P_0402_50V7K @C725 1000P_0402_50V7K PD_IOW# 1 1 +5VS 1 2 +5VS @ R257 100K_0402_5% C 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 PD_DREQ# PD_IOW# PD_IOR# PD_IORDY PD_DACK# PD_IRQA PD_A1 PD_A0 PD_CS#1 HDD_LED# <21> PD_DREQ# <21> PD_IOW# <21> PD_IOR# <21> PD_IORDY <21,23> PD_DACK# <21> PD_IRQA <21> PD_A1 <21> PD_A0 <21> PD_CS#1 2 C424 2 2HDD@ 0.1U_0402_16V4Z D PD _D[0..15] PD_D[0..15] <13,19,28,35> NB_RST# EMI 1 C423 2HDD@ 1U_0603_10V4Z 0.1U_0402_16V4Z D <21> 1 C422 JP12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 GNDGND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 NB_RST# PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 PCSEL PD_DREQ# PD_IOW# PD_IOR# PD_IORDY PD_DACK# PD_IRQA PD_A1 PD_A0 PD_CS#1 HDD_LED# R255 470_0402_5% 1 2 PDIAG PD_A2 PD_CS#3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 PD_A2 <21> PD_CS#3 <21> +5VS +5VS SUYIN_200138FR044G213ZL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 GNDGND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 PCSEL_S PDIAG PD_A2 PD_CS#3 2HDD@ R256 10K_0402_5% 1 2 @ R572 10K_0402_5% 1 2 +5VS +5VS +5VS C SUYIN_200138FR044G213ZL +5VS 1 +5VS 1U_0603_10V4Z R258 100K_0402_5% CD_LED# D10 CH751H-40_SC76 1 2 1 2 HDD_LED# D9 CH751H-40_SC76 1 2 C425 10U_0805_10V4Z ACT_LED# ACT_LED <36> 0.1U_0402_16V4Z 1 1 C426 2 C427 2 1 C428 2 2 0.1U_0402_16V4Z B B <21> SD _D[0..15] SD_D[0..15] JP13 <31> CDROM_L <31> CD_AGND <13,19,28,35> NB_RST# EMI 1 2 SD_SIOR# @C728 1000P_0402_50V7K @C727 1000P_0402_50V7K SD_SIOW# 1 +5VS 2 <21> <21> <21> <21> @ R261 <21> 100K_0402_5% <21> 1 2 SD_SIOW# SD_IORDY SD_IRQA SD_SBA1 SD_SBA0 SD_SCS1# CDROM_L CD_AGND NB_RST# SD_D7 SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0 SD_SIOW# SD_IORDY SD_IRQA SD_SBA1 SD_SBA0 SD_SCS1# CD_LED# +5VS +5VS R262 470_0402_5% 2 1 SEC_CSEL A 07/11 for defined by different ODD vender. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 CDROM_R CDROM_R <31> SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SD_DREQ# SD_SIOR# SD_DREQ# <21> SD_SIOR# <21> SD_DACK# SD_DACK# <21> PDIAG# R260 1 SD_SBA2 SD_SCS3# W=80mils 2 Pin4 of CD_ROM connector is NC if use Pioneer ODD(DVD Dual DVR-K12TBC/DVR-K13TBC) 1 2 @ 100K_0402_5% +5VS SD_SBA2 <21> SD_SCS3# <21> +5VS +5VS +5VS C429 0.1U_0402_16V4Z A SUYIN_800059MR050S119ZL Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title HDD/CDROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 24 of 53 5 4 3 2 1 +3VS +VDDPLL 0.1U_0402_16V4Z 2 1 2 MC_PWR_CTRL_0 MC_PWR_CTRL_1 E3 F5 F6 SD_CD# MS_CD# SM_CD# G5 F3 H5 G3 G2 G1 MS_CLK/SD_CLK/SM_EL_WP# MS_BS/SD_CMD/SM_WE# MS_DATA3/SD_DAT3/SM_D3 MS_DATA2/SD_DAT2/SM_D2 MS_DATA1/SD_DAT1/SM_D1 MS_SDIO(DATA0)/SD_DAT0/SM_D0 SDCLK_SMRE# SDCMD_SMALE SDD0_SMD4 SDD1_SMD5 SDD2_SMD6 SDD3_SMD7 SDWP#_SMCE# J5 J3 H3 J6 J1 J2 H7 SD_CLK/SM_RE#/SC_GPIO1 SD_CMD/SM_ALE/SC_GPIO2 SD_DAT0/SM_D4/SC_GPIO6 SD_DAT1/SM_D5/SC_GPIO5 SD_DAT2/SM_D6/SC_GPIO4 SD_DAT3/SM_D7/SC_GPIO3 SD_WP/SM_CE# SMCLE SM_RB# J7 K1 K2 SM_CLE/SC_GPIO0 SM_R/B SM_PHYS_WP#/SC_FCB L2 K5 K3 K7 L1 L3 L5 RSVD RSVD RSVD RSVD RSVD RSVD RSVD MSCLK_SDCLK_SMELWP# MSBS_SDCMD_SMWE# MSD3_SDD3_SMD3 MSD2_SDD2_SMD2 MSD1_SDD1_SMD1 MSD0_SDD0_SMD0 <26> MSCLK_SDCLK_SMELWP# <26> MSBS_SDCMD_SMWE# <26> MSD3_SDD3_SMD3 <26> MSD2_SDD2_SMD2 <26> MSD1_SDD1_SMD1 <26> MSD0_SDD0_SMD0 <26> SDCLK_SMRE# <26> SDCMD_SMALE <26> SDD0_SMD4 <26> SDD1_SMD5 <26> SDD2_SMD6 <26> SDD3_SMD7 <26> SDWP#_SMCE# AVDD AVDD AVDD 2 F1 F2 SD_CD# MS_CD# SM_CD# SD_CD# MS_CD# SM_CD# VDPLL_33 VDPLL_15 R13 R14 V17 1 <26> <26> <26> U17B VR_PORT VR_PORT 2 2 7411@ R265 10K_0402_5% MC_PWRON# +3VS 1 1 +3VS <26> MC_PWRON# 7411@ C438 0.1U_0402_16V4Z VCCP W10 VCCP W3 1 1 V19 T18 7411@ M19 C437 H1 1 2 7411@ C434 1U_0603_10V4Z 2 2 7411@ C435 10U_0805_10V4Z D 1 7411@C432 0.01U_0402_16V7K 2 7411@ C431 1U_0603_10V4Z 7411@ C430 1 10U_0805_10V4Z +3VS 7411@ C433 0.01U_0402_16V7K +3VS PCI_CBE#[0..3] <19,29,30> D PCI_AD[0..31] <19,23,29,30> AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C <26> <26> SMCLE SM_RB# 1 CLK_48M_CB 1 @ C440 10P_0402_25V8K <27> VCCD1# 7411@ 2 R273 1 @ R274 1 CLOSE TO CHIP B 4 3 2 1 4 3 2 1 JP15 SUYIN_020204FR004S506ZL 7411@ R278 56.2_0603_1% 1 7411@ R276 1 2 4.7K_0402_5% 7411@ R285 4.7K_0402_5% 1 2 1 2 +3VS 7411@ R287 10K_0402_5% 7411@ R9 0_0402_5% 2 PHY_TEST P12 W17 T19 M1 R17 7411@ R281 6.34K_0402_1% U18 1 2 U19 XTPBIAS0 U15 XTPA0+ V15 XTPA0W15 XTPB0+ V14 XTPB0W14 XTPBIAS1 U17 XTPA1+ V18 XTPA1W18 XTPB1+ V16 XTPB1W16 CPS M11 C NA P15 X_OUT R19 X_IN R18 R12 U13 V13 PCI7411 PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# TEST0 NC RSVD CLK_48 PHY_TEST_MA R0 R1 TPBIAS0 TPA0P TPA0N TPB0P TPB0N TPBIAS1 TPA1P TPA1N TPB1P TPB1N CPS CNA XO XI PC0(TEST1) PC1(TEST2) PC2(TEST3) PCICLK PCIRST# GRST# RI_OUT#/PME# SUSPEND# SPKROUT MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 2 5 7411@ R293 2 1 56.2_0603_1% 56.2_0603_1% 7411@ R292 2 1 PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 P9 V7 R8 U7 W8 N8 W5 V8 U8 U1 T2 PCI_PAR PCI_FRAME# PC I_TRDY# PCI_IR DY# PCI_STOP# PCI_DEVSEL# PCI_PERR# PCI_SERR# PCI_REQ#2 PCI_GNT#2 P5 R3 T1 T3 CLK_PCI_PCM PCI_RST# R2 R282 1 7411@ 2 4.7K_0402_5% PCM_SPK N3 M5 P1 P2 P3 N5 R1 PCI_PIRQE# PCI_PIRQH# M3 M2 for EMI CLK_PCI_PCM <19> C442 PCI_RST# <19,27,29,30,35,37,38> 10P_0402_25V8K L7 H2 PCI_PAR <19,29,30> PCI_FRAME# <19,29,30> PCI_TRDY# <19,29,30> PCI_IRDY# <19,29,30> PCI_STOP# <19,29,30> R275 7411@ PCI_DEVSEL# <19,29,30> PCI_AD20 1 2 100_0402_5% PCI_PERR# <19,29,30> PCI_SERR# <19,29,30> R279 07/04 PCI_REQ#2 <19> 10_0402_5% PCI_GNT#2 <19> 1 2 1 2 +3VS B PCM_SPK <31> PCI_PIRQE# <19> PCI_PIRQH# <19> SIRQ <19,35,37,38> SIRQ 7411@ R286 1 2 4.7K_0402_5% +3VS CARD_LED CARD_LED <26,36> R464 1 2 +3VS 4.7K_0402_5% 7411@ 7411@1 R289 2 220_0402_5% 1 2 220_0402_5% 7411@ R290 R291 1 2 10K_0402_5% 7411@ PCI7411GHK_PBGA288 when VR_EN# is low, internal regulator is actived 7411@ C445 1 2 +VDDPLL 0.1U_0402_16V4Z X_IN 1 1U_0603_10V4Z 1 VR_EN# W4 W7 W9 W11 C 7411@ C447 10P_0402_50V8J XTPBIAS1 XTPA1+ XTPA1XTPB1+ XTPB1- 7411@ R296 1M_0402_5% X1 7411@ 2 XTPA1+ XTPA1XTPB1+ XTPB1- 1 SCL SDA PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 put C445 as close to controller as possible 7411@ R297 7411@ R295 5.1K_0603_1% 56.2_0603_1% 2 1 2 1 A <40> <40> <40> <40> 2 7411@ C449 7411@ R294 220P_0603_50V8J 56.2_0603_1% 2 1 7411@ C446 N12 U14 U16 2 2 1 2 7411@ R277 56.2_0603_1% 1 CLK_48M_CB1 CLK_48M_CB +3VS 7411@ R288 7411@ R284 5.1K_0603_1% 56.2_0603_1% 2 1 2 1 GND4 GND3 GND2 GND1 8 7 6 5 1 7411@ C444 7411@ R283 220P_0603_50V8J 56.2_0603_1% 2 1 2 7411@ C443 1U_0603_10V4Z <16> 2 220_0402_5% 2 220_0402_5% C/BE3# C/BE2# C/BE1# C/BE0# VSSPLL VSSPLL 2 +3VS P14 T17 7411@ R272 10K_0402_5% 1 2 AGND AGND AGND @ R271 10_0402_5% U2 V1 V2 U3 W2 V3 U4 V4 V5 U5 R6 P6 W6 V6 U6 R7 V9 U9 R9 N9 V10 U10 R10 N10 V11 U11 R11 W12 V12 U12 N11 W13 A X_OUT 24.576MHZ_16P_XSL024576FG1H 7411@ C448 10P_0402_50V8J Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 4 3 Title PCI7411(1/3) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 1 25 of 53 5 4 3 2 1 1 CARD_LED <25,36> CARD_LED D 3 MC_PWRON# <25> MC_PWRON# S 7411@ Q12 2N7002_SOT23 2 G 7411@ R456 0_0402_5% 1 2 D 1 +3VS D @ D30 CH751H-40_SC76 SD_CD# 2 1 2 @ R457 100K_0402_5% 2 1 SM_CD# SD_CD# <25> SM_CD# <25> 8/23 Relocate Damping resistor to solve Sandisk Card issue @ D31 CH751H-40_SC76 JP14 <25> <25> <25> <25> <25> MSCLK_SDCLK_SMELWP# 1 R269 7411@ 330_0402_5% MSD0_SDD0_SMD0 MSD1_SDD1_SMD1 MSD2_SDD2_SMD2 MSD3_SDD3_SMD3 SDD0_SMD4 SDD1_SMD5 SDD2_SMD6 SDD3_SMD7 MSD0_SDD0_SMD0 MSD1_SDD1_SMD1 MSD2_SDD2_SMD2 MSD3_SDD3_SMD3 <25> SDD0_SMD4 <25> SDD1_SMD5 <25> SDD2_SMD6 <25> SDD3_SMD7 MSCLK_SDCLK_SMELWP# SM_PHYS_WP# MSBS_SDCMD_SMWE# SDCMD_SMALE 2 <25> MSBS_SDCMD_SMWE# <25> SDCMD_SMALE +VCC_SM 7411@ C439 0.1U_0402_16V4Z SM_CD# 07/11 change net name +3VS C +VCC_5IN1 @ U51 IN 3 SET 2 5 @ OUT 1 ON# 4 GND 2 MC_PWRON# 1 2 SM_RB# SDCLK_SMRE# SDWP#_SMCE# <25> SDCLK_SMRE# <25> SDWP#_SMCE# <25> SMCLE SMCLE 34 33 32 31 21 22 23 24 SM-D0 SM-D1 / XD-D1 SM-D2 / XD-D2 SM-D3 / XD-D3 SM-D4 / XD-D4 SM-D5 / XD-D5 SM-D6 / XD-D6 SM-D7 / XD-D7 35 43 36 37 SM_WP-IN / XD_WP-IN SM-WP-SW #SM_-WE / XD_-WE #SM-ALE / XD-ALE 25 3 29 26 27 28 30 2 38 SM-LVD SM-CD-SW SM_-VCC / XD_-VCC #SM_R/-B / XD_R/-B #SM_-RE / XD_-RE #SM_-CE / XD_-CE #SM_-CD SM-CD-COM SM-CLE / XD-CLE 5 IN 1 SD-DAT3 SD-DAT2 SD-DAT1 CONN SD-DAT0 SD-WP-SW SD-CMD SD_CLK SD-VCC NC SD-CD-SW SD-CD-COM 11 12 6 7 5 10 8 9 4 42 41 MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-SCLK MS-INS MS-BS MS-VCC 15 14 16 18 19 17 13 20 XD-VCC XD-CD GND GND 40 39 1 44 22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 2 2 2 2 22_0402_5% 2 33_0402_5% 2 MSD3_SDD3_SMD3 7411@ R459 MSD2_SDD2_SMD2 7411@ R460 MSD1_SDD1_SMD1 7411@ R461 MSD0_SDD0_SMD0 7411@ R462 SDWP#_SMCE# MSBS_SDCMD_SMWE# 1 7411@ R458 MSCLK_SDCLK_SMELWP# 1 7411@ R266 +VCC_5IN1 1 1 1 1 SD_CD# MSD0_SDD0_SMD0 MSD1_SDD1_SMD1 MSD2_SDD2_SMD2 MSD3_SDD3_SMD3 MSCLK_SDCLK_SMELWP# MS_CD# MSBS_SDCMD_SMWE# C +VCC_5IN1 SM_CD# +VCC_SM TAITN_R007-N3P-15-S AATI4610AIGV-T1_SOT23-5 R573 1 10K_0402_1% 07/11 change net name +VCC_5IN1 +VCC_SM 2 1 1 2 1 B 1 1 2 2 1 7411@ C436 10U_0805_10V4Z 2 7411@ R264 47K_0603_5% 2 2 1 R546 7411@ 100K_0402_5% 1 2 7411@ R551 47K_0603_5% R544 7411@ 100K_0402_5% 7411@ C698 10U_0805_10V4Z 2 2 1 MC_PWRON# 1 G G 2 3 1 1 D S D S 3 2 7411@ C690 0.1U_0402_16V4Z +VCC_SM Q11 7411@ SI2301BDS_SOT23 7411@ C689 0.1U_0402_16V4Z +VCC_5IN1 Q50 7411@ SI2301BDS_SOT23 7411@ C688 0.1U_0402_16V4Z +3VS B 7411@ C687 0.1U_0402_16V4Z 07/11 change net name 07/11 change net name SM_CTRL# +VCC_SM MS_CD# MS_CD# 1 2 D33 7411@ CH751H-40_SC76 1 <25> D 3 D32 7411@ CH751H-40_SC76 SD_CD# 1 2 S Q51 7411@ 2N7002_SOT23 2 G <25> SDWP#_SMCE# <25> SM_RB# SDWP#_SMCE# R549 10K_0402_5% 1 2 SM_RB# R550 10K_0402_5% 1 2 07/25 for XD log A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title PCI7411(2/3) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 26 of 53 5 4 2 2 7411@ C452 0.1U_0402_16V4Z 1 2 1 2 2 7411@ C454 0.01U_0402_16V7K 7411@ C455 1U_0603_10V4Z 1 1 2 1 1 2 7411@ C457 0.01U_0402_16V7K 2 CardBus Power Switch U18 1 2 7411@ C459 0.01U_0402_16V7K <19,25,29,30,35,37,38> PCI_RST# +S1_VCC 2 2 7411@ R299 33_0402_5% 1 2 S1_RST A6 S1_BVD2 A2 S1_CD1# S1_CD2# S1_VS1 S1_VS2 C15 E5 A3 E8 S1_D14 S1_D2 S1_A18 B13 D2 C10 D19 K19 RSVD RSVD H8 H9 H10 H11 H12 J8 M7 J12 M9 M10 M12 K8 K12 N7 DATA CLOCK LATCH PCI 7411 A_CC/BE3#/A_REG# A_CC/BE2#/A_A12 A_CC/BE1#/A_A8 A_CC/BE0#/A_CE1# A_CPAR/A_A13 A_CFRAME#/A_A23 A_CTRDY#/A_A22 A_CIRDY#/A_A15 A_CSTOP#/A_A20 A_CDEVSEL#/A_A21 A_CBLOCK#/A_A19 A_CPERR#/A_A14 A_CSERR#/A_WAIT# A_CREQ#/A_INPACK# A_CGNT#/A_WE# A_CSTSCHG/A_BVD1(STSCHG/RI) A_CCLKRUN#/A_WP(IOIS16) A_CCLK/A_A16 A_CINT#/A_READY(IREQ) A_CRST#/A_RESET A_CAUDIO/A_BVD2(SPKR#) A_CCD1#/A_CD1# A_CCD2#/A_CD2# A_CVS1/A_VS1# A_CVS2/A_VS2# A_CRSVD/A_D14 A_CRSVD/A_D2 A_CRSVD/A_A18 A_USB_EN# B_USB_EN# S1_CD2# N1 L6 N2 17 18 14 13 +3VS C460 7411@ 0.1U_0402_16V4Z 1 2 AVPP NC0 NC4 5V 5V AVCC AVCC GND NC1 NC2 NC5 NC6 NC7 NC8 1 24 2 1 2 D C461 7411@ 4.7U_0805_10V4Z C466 7411@ 0.1U_0402_16V4Z 1 2 11 23 22 16 6 1 2 C467 7411@ 4.7U_0805_10V4Z +S1_VCC U47 9 12V VCC VCC VCC 13 12 11 B15 A16 B16 A17 C16 D17 C19 D18 E17 E19 G15 F18 H14 H15 G17 K17 L13 K18 L15 L17 L18 L19 M17 M14 M15 N19 N18 N15 M13 P18 P17 P19 F15 G18 K14 M18 K13 G19 H17 J13 J17 H19 J19 J18 B18 E18 J15 F14 A18 H18 B19 F17 C17 N13 B17 C18 F19 N17 A15 K15 +5VS JP16 VPP 10 69 70 PCI7411GHK_PBGA288 7411@ 7411@ C471 10P_0402_50V8J 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 S1_D3 S1_CD1# S1_D4 S1_D11 S1_D5 S1_D12 S1_D6 S1_D13 S1_D7 S1_D14 S1_CE1# S1_D15 S1_A10 S1_CE2# S1_OE# S1_VS1 S1_A11 S1_IORD# S1_A9 S1_IOWR# S1_A8 S1_A17 S1_A13 S1_A18 S1_A14 S1_A19 S1_WE# S1_A20 S1_RDY# S1_A21 +S1_VCC +S1_VPP S1_A16 S1_A22 S1_A15 S1_A23 S1_A12 S1_A24 S1_A7 S1_A25 S1_A6 S1_VS2 S1_A5 S1_RST S1_A4 S1_WAIT# S1_A3 S1_INPACK# S1_A2 S1_REG# S1_A1 S1_BVD2 S1_A0 S1_BVD1 S1_D0 S1_D8 S1_D1 S1_D9 S1_D2 S1_D10 S1_WP S1_CD2# 5 6 VCCD0 VCCD1 VPPD0 VPPD1 1 2 15 14 5V 5V +3VS 3 4 3.3V 3.3V 2 GND GND DATA3 CD1# DATA4 DATA11 DATA5 DATA12 DATA6 DATA13 DATA7 DATA14 CE1# DATA15 ADD10 CE2# OE# VS1# ADD11 IORD# ADD9 IOWR# ADD8 ADD17 ADD13 ADD18 ADD14 ADD19 WE# ADD20 READY ADD21 VCC VCC VPP VPP ADD16 ADD22 ADD15 ADD23 ADD12 ADD24 ADD7 ADD25 ADD6 VS2# ADD5 RESET ADD4 WAIT# ADD3 INPACK# ADD2 REG# ADD1 BVD2 ADD0 BVD1 DATA0 DATA8 DATA1 GND DATA9 GND DATA2 DATA10 WP CD2# GND GND @ R454 10K_0402_5% OC C TPS_CLK VCCD1# TPS_LATCH TPS_DATA VCCD1# <25> 8 @ TPS2211AIDBR_SSOP16 1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD +S1_VCC +S1_VPP B A SANTA_130609-1_LT Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 4 3 Title PCI7411(3/3) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 NC3 3.3V 7411@ SNP1X21DBR SSOP-24 2 close to card bus conn TPS_DATA TPS_CLK TPS_LATCH A 7411@ C470 10P_0402_50V8J 20 7 +S1_VPP G7 G8 G13 H13 J9 J10 J11 K9 K10 K11 L8 L9 L10 L11 L12 M8 S1_CD1# 12V 12V C469 7411@ 4.7U_0805_10V4Z GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E2 E1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C5 F9 B10 G12 S1_A13 G10 S1_A23 C8 S1_A22 A8 S1_A15 B8 S1_A20 A9 S1_A21 C9 S1_A19 E10 S1_A14 F10 S1_WAIT# B3 S1_INPACK# E7 S1_WE# B9 S1_BVD1 B2 S1_WP C3 S1_CLK E9 S1_RDY# C4 B S1_A16 S1_REG# S1_A12 S1_A8 S1_CE1# A_CAD31/A_D10 A_CAD30/A_D9 A_CAD29/A_D1 A_CAD28/A_D8 A_CAD27/A_D0 A_CAD26/A_A0 A_CAD25/A_A1 A_CAD24/A_A2 A_CAD23/A_A3 A_CAD22/A_A4 A_CAD21/A_A5 A_CAD20/A_A6 A_CAD19/A_A25 A_CAD18/A_A7 A_CAD17/A_A24 A_CAD16/A_A17 A_CAD15/A_IOWR# A_CAD14/A_A9 A_CAD13/A_IORD# A_CAD12/A_A11 A_CAD11/A_OE# A_CAD10/A_CE2# A_CAD9/A_A10 A_CAD8/A_D15 A_CAD7/A_D7 A_CAD6/A_D13 A_CAD5/A_D6 A_CAD4/A_D12 A_CAD3/A_D5 A_CAD2/A_D11 A_CAD1/A_D4 A_CAD0/A_D3 VCCA VCCA U17A D1 C1 D3 C2 B1 B4 A4 E6 B5 C6 B6 G9 C7 B7 A7 A10 E11 G11 C11 B11 C12 B12 A12 E12 C13 F12 A13 C14 E13 A14 B14 E14 A5 A11 1 S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3 9 10 C468 7411@ 0.1U_0402_16V4Z 1 2 +3VS DATA CLOCK LATCH RESET# OC# SHDN# 2 C463 7411@ 4.7U_0805_10V4Z +S1_VCC C 8 19 +S1_VCC 7411@ C465 0.1U_0402_16V4Z 3 4 5 12 15 21 +5VS 1 1 7411@ C464 0.1U_0402_16V4Z +S1_VPP C462 7411@ 0.1U_0402_16V4Z 1 2 D 1 TPS_DATA TPS_CLK TPS_LATCH PCI_RST# SHDN 1 1 7411@ C458 0.1U_0402_16V4Z GND 7411@ C450 1U_0603_10V4Z 1 1 7 2 +3VS 7411@ C456 0.1U_0402_16V4Z 7411@ C453 0.01U_0402_16V7K 2 16 +3VS 7411@ C451 0.1U_0402_16V4Z 3 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 27 of 53 A B C D E Express Card Power Switch 5 6 3.3Vin1 3.3Vin2 20 +1.5VS_PEC 1.5Vin1 1.5Vin2 1.5Vout1 1.5Vout2 OC# RCLKEN PERST# 23 22 9 RCLKEN PERST# <20> <20> USBP7USBP7+ USBP7USBP7+ 2 0_0402_5% 1 2 1 2 17_EXP@ 0_0402_5% <20> PCIE_PME# R306 1 2 +3V_PEC EXP@ 0_0402_5% <16> <16> +1.5VS_PEC +1.5VS_PEC USB7USB7+ NC_CP# PCIE_PME#_R PERST# +3VS_PEC NC_CLKSEL0# NC_CP# PCIECLK0# PCIECLK0 PCIECLK0# PCIECLK0 <12> <12> PCIE_RX0N PCIE_RX0P <12> <12> PCIE_TX0N PCIE_TX0P 1 3 1 10 12 13 24 11 EXP_RST# D S NC_CLKSEL0# <16> @ Q14 2N7002_SOT23 S EXP@ Q55 2N7002_SOT23 2 G JP17 SB_SCLK SB_SDAT <8,9,16,20> SB_SCLK <8,9,16,20> SB_SDAT NC1 NC2 NC3 NC4 NC5 GND close to JP36 <20> NC_CLKSEL0# D 2 G 3 CPUSB# CPPE# STBY# SHDN# SYSRST# EXP@ TPS2231PWPR_PWP24 17_EXP@ R473 R474 1 EXP@ R302 10K_0402_5% 16 17 1 14 15 4 3 2 SUSP# SYSON NB_RST# <37,38,39,41> SUSP# <37,38,41,46> SYSON <13,19,24,35> NB_RST# Aux_out 2 3.3Vaux_in 18 19 NC_CP# NC_CP# 7 8 +3VS 21 0.1U_0402_16V4Z <20> 3.3Vout1 3.3Vout2 +3V_PEC EXP@ C474 +3VALW 0.1U_0402_16V4Z 2 1 +1.5VS EXP@ C476 2 1 1 +3VS_PEC U20 +3VS 1 EXP@ C472 0.1U_0402_16V4Z 2 1 PCIE_RX0N PCIE_RX0P PCIE_TX0N PCIE_TX0P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Near to Express Card slot. 17 GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND +3VS_PEC +3V_PEC 2 4.7U_0805_10V4Z 1 17_EXP@ C479 0.1U_0402_16V4Z 1 C480 2 17_EXP@ 2 17_EXP@ C717 0.1U_0402_16V4Z 1 1 2 2 C478 17_EXP@ 4.7U_0805_10V4Z +1.5VS_PEC 4.7U_0805_10V4Z 1 17_EXP@ C481 0.1U_0402_16V4Z 1 C482 2 17_EXP@ 2 GND GND FOX_1CH4110C 3 3 JP36 USBP7USBP7+ NC_CP# SB_SCLK SB_SDAT <8,9,16,20> SB_SCLK <8,9,16,20> SB_SDAT +1.5VS_PEC +1.5VS_PEC +3V_PEC PCIE_PME#_R PERST# +3VS_PEC <16> <16> PCIECLK1# PCIECLK1 <12> <12> PCIE_RX1N PCIE_RX1P <12> <12> PCIE_TX1N PCIE_TX1P NC_CLKSEL0# NC_CP# PCIECLK1# PCIECLK1 PCIE_RX1N PCIE_RX1P PCIE_TX1N PCIE_TX1P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 4 Near to Express Card slot. 15.4 GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND +3VS_PEC +3V_PEC 4.7U_0805_10V4Z 1 15_EXP@ C694 0.1U_0402_16V4Z 1 C695 2 15_EXP@ 2 15_EXP@ C718 0.1U_0402_16V4Z 1 1 2 2 C693 15_EXP@ 4.7U_0805_10V4Z +1.5VS_PEC 4.7U_0805_10V4Z 1 15_EXP@ C696 0.1U_0402_16V4Z 1 C697 2 15_EXP@ 2 GND GND 4 FOX_1CH4110C Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title Express Card THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 28 of 53 5 4 3 2 1 +3VALW C483 1U_0603_10V4Z 2 1 R307 300_0603_5% 1 2 JP18 12 Amber LED- 11 Amber LED+ 3 ACTIVITY# CTRL25 +3VALW Q15 2SB1188_SC62 1 8 V2.5_LAN 2 7 MDO1- 07/11 Swap net for HP request 5 C484 4.7U_0805_10V4Z 4 2 PC I_AD[0..31] <19,23,25,30> PCI_AD[0..31] R308 3.6K_0402_5% 1 2 U21 PCI_AD22 1 R315 2 <19,25,30> PCI_PAR <19,25,30> PCI_FRAME# <19,25,30> PCI_IRDY# <19,25,30> PCI_TRDY# <19,25,30> PCI_DEVSEL# <19,25,30> PCI_STOP# <19,25,30> PCI_PERR# <19,25,30> PCI_SERR# <19> <19> PCI_REQ#1 PCI_GNT#1 <19> PCI_PIRQG# <30,37,38> PME_EC# LAN_IDSEL 100_0402_5% PCI_PAR PCI_FRAME# PCI_IR DY# PC I_TRDY# PCI_DEVSEL# PCI_STOP# 46 PCI_PERR# PCI_SERR# 70 75 PCI_REQ#1 PCI_GNT#1 30 29 76 61 63 67 68 69 PCI_PIRQG# 25 PME_EC# 31 PCI_RST# <19,25,27,30,35,37,38> PCI_RST# <19,23> CLK_PCI_LAN 92 77 60 44 CLK_PCI_LAN 1 2 R318 10K_0402_5% 27 28 65 4 17 128 1 CLK_PCI_LAN 2 R322 10_0402_5% 1 C504 10P_0402_50V8K 2 A 07/04 for EMI 21 38 51 66 81 91 101 119 EEDO AUX/EEDI EESK EECS 108 109 111 106 LAN_EEDO LAN_EEDI LAN_EECLK LAN_EECS 4 3 2 1 LED0 LED1 LED2 NC/LED3 117 115 114 113 ACTIVITY# LINK_100# AT93C46-10SI-2.7_SO8 1 2 5 6 TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI1- TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI1NC/MDI2+ NC/MDI2NC/MDI3+ NC/MDI3- LWAKE ISOLATE# RTSET NC/SMBCLK NC/SMBDATA 105 23 127 72 74 NC/M66EN C/BE#0 C/BE#1 C/BE#2 C/BE#3 NC/HSDAC+ NC/HG NC/LG2 NC/LV2 GND NC NC VCC LINK_100# 1 C485 0.1U_0402_16V4Z 2 MDO0+ 1 10 9 +3VALW 15 PR4+ PR2D PR3PR3+ PR2+ PR1SHLD2 PR1+ SHLD1 14 13 Green LEDGreen LED+ SUYIN_100073FR012S100ZL R311 R312 R313 1 1 1 TXD+/MDI0+ TXD-/MDI02 1K_0402_5% 2 15K_0402_5% 2 5.6K_0603_1% C487 0.1U_0402_16V4Z 1 2 RXIN+/MDI1+ RXIN-/MDI1- +3VS R313 5.6K for 8100CL 8 7 6 3 2 1 TDTD+ CT CT RDRD+ TXTX+ CT CT RXRX+ 9 10 11 MDO0+ MDO0MCT0 14 15 16 MCT1 MDO1+ MDO1- MDO0+ MDO0- <40> <40> MDO1+ MDO1- <40> <40> R310 75_0402_5% 2 1 2 1 R314 75_0402_5% C486 RJ45_GND 2 C 1 1000P_1206_2KV7K 88 NS0013_16P 10 120 11 123 124 126 IDSEL PAR FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# REQ# GNT# NC/VSS NC/VSS NC/GND NC/GND NC/GND NC/GND NC/GND NC/GND INTA# CTRL25 PME# RTT3/CRTL18 RST# VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 CLK CLKRUN# GND/VSS GND/VSS GND/VSS GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST 9 13 Y5 25MHZ_16P_XSL025000FK1H LAN_X1 2 LAN_X2 1 1 1 22 48 62 73 112 118 C488 27P_0402_50V8J GND GND GND GND 2 2 close to chip TXD+/MDI0+ C489 27P_0402_50V8J TXD-/MDI0- CTRL25 8 AVDD33/AVDDL AVDD33/AVDDL AVDD33/AVDDL NC/AVDDL 26 41 56 71 84 94 107 +3VALW 1 2 1 C491 0.1U_0402_16V4Z 2 1 C492 0.1U_0402_16V4Z 2 1 C493 0.1U_0402_16V4Z 2 NC/VDD18 NC/VDD18 NC/VDD18 NC/VDD18 NC/VDD18 C490 0.01U_0402_16V7K 2 1 2 1 R317 49.9_0402_1% B close to magnetic 1 C494 0.1U_0402_16V4Z 2 C495 0.1U_0402_16V4Z RXIN+/MDI1+ 3 7 20 16 +3VALW 1 2 VDD25/VDD18 VDD25/VDD18 VDD25/VDD18 VDD25/VDD18 R316 49.9_0402_1% 2 1 125 RXIN-/MDI1- AVDD25/HSDAC- 32 54 78 99 1 C497 0.1U_0402_16V4Z 2 R319 49.9_0402_1% 2 1 C496 0.01U_0402_16V7K 2 1 2 1 R320 49.9_0402_1% 1 C498 0.1U_0402_16V4Z 2 C499 0.1U_0402_16V4Z V2.5_LAN 1 1 C500 0.1U_0402_16V4Z 2 1 C501 0.1U_0402_16V4Z 2 1 C502 0.1U_0402_16V4Z 2 C503 0.1U_0402_16V4Z 24 45 64 110 116 V_12P 1 C505 12 RTL8100CL_LQFP128 2 R323 0_0402_5% 1 2 A V2.5_LAN 0.1U_0402_16V4Z Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 4 3 Title LAN-8100CL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 3 MDO0- +3VALW 2 LAN_X1 LAN_X2 2 35 52 80 100 R309 300_0603_5% 1 2 MDO1+ 16 SHLD3 U23 121 122 NC/AVDDH NC/HV DO DI SK CS 5 6 7 8 14 15 18 19 X1 X2 LAN I/F PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 Power <19,25,30> <19,25,30> <19,25,30> <19,25,30> 104 103 102 98 97 96 95 93 90 89 87 86 85 83 82 79 59 58 57 55 53 50 49 47 43 42 40 39 37 36 34 33 +3VALW U22 PCI I/F PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 C B 6 1 D SHLD4 PR4- 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 29 of 53 A B C D E D11 3 LAN RESERVED 1 2 1 1N4148_SOT23 <20> 1000P_0402_50V7K WL_ON <19> PCI_PIRQF# +3VS 1 1 C506 2 4.7U_0805_10V4Z C507 2 1 C508 0.1U_0402_16V4Z 2 <19,23> CLK_PCI_MINI <19> PCI_REQ#3 <19,23,25,29> PCI_AD31 <19,23,25,29> PCI_AD29 <19,23,25,29> PCI_AD27 <19,23,25,29> PCI_AD25 <34> CH_DATA <19,25,29> PCI_CBE#3 <19,23,25,29> PCI_AD23 <19,25,29> PCI_AD21 <19,25,29> PCI_AD19 1 CLK_PCI_MINI 07/04 for EMI R325 10_0402_5% <19,25,29> PCI_AD17 <19,25,29> PCI_CBE#2 <19,25,29> PCI_IRDY# R326 1 2 2 1 2 <19,25,29> PCI_SERR# C512 10P_0402_50V8K <19,25,29> PCI_PERR# <19,25,29> PCI_CBE#1 <19,25,29> PCI_AD14 <19,25,29> PCI_AD12 <19,25,29> PCI_AD10 <19,25,29> PCI_AD8 <19,25,29> PCI_AD7 <19,25,29> PCI_AD5 <19,25,29> PCI_AD3 +5VS <19,25,29> PCI_AD1 +5VS MINI_LED WL_ON PCI_PIRQF# W = 40 mils CLK_PCI_MINI PCI_REQ#3 PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 CH_DATA PCI_CBE#3 PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17 PCI_CBE#2 PCI_IR DY# 2 10K_0402_5% PCI_SERR# PCI_PERR# PCI_CBE#1 PCI_AD14 PCI_AD12 PCI_AD10 PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 W = 30 mils PCI_AD1 W = 30 mils 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 1 KEY 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 2 KEY 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 127 128 TIP LAN RESERVED JP19 1 <17,34,35> WIRELESS_LED RING 2 1 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 W = 30 mils +5VS PCI_PIRQF# W = 40 mils +3VALW PCI_RST# <19,25,27,29,35,37,38> PCI_RST# W = 40 mils PCI_GNT#3 1000P_0402_50V7K 1 PCI_GNT#3 <19> PME_EC# CH_CLK PCI_AD30 C509 0.1U_0402_16V4Z PME_EC# <29,37,38> CH_CLK <34> PCI_AD30 <19,23,25,29> PCI_AD28 PCI_AD26 PCI_AD24 1 2 R324 100_0402_5% PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 PCI_FRAME# PC I_TRDY# PCI_STOP# PCI_AD28 <19,23,25,29> PCI_AD26 <19,23,25,29> PCI_AD24 <19,23,25,29> PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 PCI_AD18 1 1 C510 2 +3VS C511 2 2 4.7U_0805_10V4Z IDSEL : AD18 <19,25,29> <19,25,29> <19,25,29> <19,25,29> <19,25,29> PCI_FRAME# <19,25,29> PCI_TRDY# <19,25,29> PCI_STOP# <19,25,29> PCI_DEVSEL# 2 +5VS PCI_DEVSEL# <19,25,29> PCI_AD15 PCI_AD13 PCI_AD11 0.1U_0402_16V4Z PCI_AD15 <19,25,29> PCI_AD13 <19,25,29> PCI_AD11 <19,25,29> PCI_AD9 PCI_CBE#0 1 C513 PCI_AD9 <19,25,29> PCI_CBE#0 <19,25,29> PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 1 1 C514 2 4.7U_0805_10V4Z C515 2 1000P_0402_50V7K 2 <19,25,29> <19,25,29> <19,25,29> <19,25,29> +3VALW @ R327 10K_0402_5% 1 2 @ 1000P_0402_50V7K 1 @ C516 4.7U_0805_10V4Z R328 10K_0402_5% 1 2 W=40mils 1 1 C517 2 C518 2 2 0.1U_0402_16V4Z +3VS +3VALW 127 128 QTC_C102A-052B11 3 3 4 4 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title Mini PCI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 30 of 53 A B C D E 1 +3VAMP_CODEC R329 10K_0402_1% +VDDA_CODEC 1 8/23 Change to DGND 5 2 8 DELAY 6 SENSE or ADJ 1 R332 7 ERROR 1 CNOISE SD 1 3 GND C524 SI9182DH-AD_MSOP8 10K_0402_5% 1 2 R331 47K_0603_1% 1 R333 27K_0603_1% 2 C522 1U_0603_10V4Z 2 GPIO4 0 0 disable HP-out 0 1 disable EQ/HP-out(sys HP only) 1 0 enable HP-out 1 1 disable EQ/HP-0ut(sys HP only) 1 20 <20> AC97_SDIN0 R353 1 2 33_0402_5% 21 <20> AC97_BITCLK R354 1 2 33_0402_5% 22 11 3 12 14 <34,35,40> MUTE_LED MONO_INR 45 @ C525 0.1U_0402_16V4Z 1 2 C535 1U_0603_10V4Z C534 0.1U_0402_16V4Z C533 0.1U_0402_16V4Z 1 33 44 AVDD44 AVDD33 SDATA_IN0 REF_FLT VC_SCA VREF_SCA BIT_CLK C537 1 2 10U_0805_10V4Z C538 2 C539 2 C540 2 1 2.2U_0603_6.3V4Z 1 2.2U_0603_6.3V4Z 1 2.2U_0603_6.3V4Z ID0# LINE_OUTL LINE_OUTR DOCK_L+ DOCK_R+ 38 37 36 REF_FLT VC_SCA VREF_SCA 34 MBIAS/AVDD ID1# +CODEC_REF EAPD LINE_OUTL <33> LINE_OUTR <33> @ R355 2 SPDIFO @ R356 1 GPIO_5 DSPKOUT 24 25 XTLO XTLI 1 @ R587 1 2 R357 33_0402_5% CX20468-31_TQFP48 2 10K_0402_5% C546 1 2 15P_0402_50V8J 3 DOCK_L+ 2 G 1 1 C730 1 A B DOCK_LOUT_R <40> 2 100U_6.3V_M R567 1 2 33_0805_5% DOCK_LOUT_R R568 1 2 1K_0402_5% 2 100U_6.3V_M R569 1 2 33_0805_5% DOCK_LOUT_L R570 1 2 1K_0402_5% 1 2 @ R589 0_0402_5% 4 DOCK_LOUT_L <40> 5/10 HP requirement 2 Compal Secret Data Security Classification 2005/03/01 Issued Date 07/25 Audio POP issue 2 15P_0402_50V8J 2N7002_SOT23 3 0_0402_5% @ R590 GNDA 2 3 1 2 S <33,35,40> D GNDA Q60 2 1 5/13 HP requirement cap. high 5.7mm C731 1 8/23 reseve C700, slowly turn on Q59/Q60 @ R338 0_1206_5% 1 2 2 + 1 HP_PLUG_D <33> 2 1 close to dock side Q59 2N7002_SOT23 S DOCK_R+ R337 0_1206_5% 1 2 JACK_DET_D <33> 1 1 + 2 G S 2 CDROM_R <24> CD_AGND <24> CDROM_L <24> D12 CH751H-40_SC76 X2 24.576MHZ_16P_XSL024576FG1H C547 D 1U_0603_10V4Z 1 3 <35> 2 4.7K_0402_5% 2 2.7K_0402_5% 2 4.7K_0402_5% D36 CH751H-40_SC76 1 2 2 10K_0402_5% 48 2 G @ C700 1 D 1 2 1K_0402_5% <35,40> 47 GPIO_4 PC_BEEP R345 1 R347 1 R348 1 1 4.7K_0402_5% SPDIFO 46 S_PDIF MIC CDROM_R_R CD_GNA CDROM_R_L @ R555 0_0402_5% 1 2 39 40 42 43 Q58 2N7002_SOT23 R588 +5VALW @C527 0.1U_0402_16V4Z 1 2 GND 23 LINE_OUT_L LINE_OUT_R HP_OUT_L HP_OUT_R AC_ONLY MIC_IN CDROM_RC_R C DGNDA CDROM_RC_L 27 28 LINE_IN_L LINE_IN_R SDATA_OUT SYNC AC_RESET# 29 32 31 30 1 <37,38> MUTE_GATE @ C526 0_0402_5% 1 2 4 VDD_CLK PWRCLKN 2 6 9 19 26 13 CD_IN_R CD_IN_GND CD_IN_L C545 0.1U_0402_16V4Z 15 16 17 MIC_IN DIB_DATAP C544 1U_0603_10V4Z AC97_SDOUT AC97_SYNC AC97_RST# <20,23> AC97_SDOUT <20> AC97_SYNC <20> AC97_RST# R342 3K_0402_5% DIB_DATAN PWRCLKP C662 0.1U_0402_16V4Z 2 C543 0.1U_0402_16V4Z R349 1 1 C542 0.1U_0402_16V4Z 8 PWRCLKN +CODEC_REF R352 4.7K_0402_5% 2 1 2 0_0402_5% PWRCLKP <32> 2 2 7 2 1 R351 2.7K_0402_5% 2 1 2 0_0402_5% 2 +VDDA_CODEC R350 4.7K_0402_5% 2 1 4 2 1 R340 0_0805_5% 1 2 2 3 2 0_0402_5% 1 1 2 0_0402_5% R344 1 AGND35 AGND41 R343 1 DIB_DATAP RCOSC1 35 41 DIB_DATAN VDDC18 VDDC10 1 <32> <32> 18 10 U25 <32> R346 1 5 2 VDD5 1 GNDC2 GND8 GNDC9 GNDC19 AVSS_CLK 2 +3VAMP_CODEC R341 249K_0402_1% 2 1 2 1 C532 0.1U_0402_16V4Z 2 1 C531 0.1U_0402_16V4Z 1 C530 0.1U_0402_16V4Z 2 C529 0.1U_0402_16V4Z C528 10U_0805_10V4Z 1 GPIO5 Place decoupling caps near the power pins of SmartAMC device. RCOSC1 1 2 1 For Layout: +3VDD_CODEC 2 C541 150P_0402_50V8J @ C523 0.1U_0402_16V4Z 0.01U_0402_16V7K SB_SPKR <20> R339 0_0805_5% 1 2 2 C536 150P_0402_50V8J 1 2 8/23 Change to DGND +3VALW (3.33V) 250mA 1 VOUT 2 2 2 1 2 1 VIN 3 1 Q16 Q17 MMBT3904_SOT23 MMBT3904_SOT23 3 PCM_SPK R336 560_0402_5% 2 1 2 C521 0.1U_0402_16V4Z R334 2.4K_0402_5% 1 2 R335 560_0402_5% 1 2 2 4 +5VS C520 10U_0805_10V4Z 1 <25> C519 1U_0603_10V4Z 1 2 MONO_INR MONO_IN1 U24 W=40Mil 2 MONO_IN R330 0_0402_5% 1 2 2005/04/06 Deciphered Date C Title AMOM_codec THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 31 of 53 1 MTP28 1 MTP52 VDD MTP59 BR908_CC 1 2 2 MC928 VDD DIB_P1 1 MR922 0_0402_5% 2 20 RAC2 19 1 DIB_P2 DVdd TAC2 18 27 TRDC DIB_P EIC MTP61 MTP62 1 RBias Vc_LSD PRI SEC 1 MC974 @ 0.001U_0402_50V7M MC944 2 2 0.001U_0402_50V7M 0.1U_0402_10V6K AGND_LSD 8 22 25 Vc VZ EIO NC1 NC2 NC3 EIF TXO 2 29 5 10 VRef PADDLE 6 2 MC976 4 9 1 17 16 TXF 14 13 3 3 @ 30U_82154R_1%_1:1.67 @ HEADER8 MJ1B 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Vref_LSD MC940 1U_0603_6.3V6M MTP63 1 1 1 3 DGnd 2 GPIO1 11 2 2 1 E&T_3800-02 1 MTP42 2 4 1 4 RXI CX20493-58_QFN28 23 1 DIB_N DC_GND 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 28 AGnd 1 MJ1 DIB_N2 MJ2 1 MTP73 MT922 2 0_0402_5% MR924 15 MTP25 1 12 MTP41 1 DIB_N1 2 10P_1808_3KV 1 1 MC924 DIB_DATAN 1 1 MTP65 MR938 110_0603_5% MTP31 MR928 27_0805_5% 1 @ HEADER8 2 <31> 1 1 PWR+ 2 7 2 AGND_LSD TAC1 1 1 3 MTP72 24 2 AVdd 1 5 1 2 10P_1808_3KV 1 CLK MTP30 PWR+ MTP60 Check 0.047u or 10p cap MC922 DIB_DATAP 26 21 2 30U_82154R_1%_1:1.67 MTP27 1 <31> 2 SEC MC970 0.1U_0402_10V6K RAC1 3 PRI PCLK 1 2 MMZ1608D301BT_0603 1 MBR908B BAV99DW-7_SOT363 1 MTP35 1 MTP38 MFB902 R ING_2 MOD_RING 1 2 1 MTP39 MR902 MMZ1608D301BT_0603 1M_0805_5% MC902 RAC1 MC906 1 2 RAC 1/RING 1 2 0.033U_1206_100V7K 1 470P_1808_3KV MC904 TAC1 MBR904 2 1 TAC1/TIP 1 2 0.033U_1206_100V7K MMBD3004S_SOT23 1M_0805_5% 2 TIP_2 MTP34 MR904 1 MTP40 1 TRDC MR906 1 2 6.8M_0805_5% 1 MTP33 1 MC958 MC918 AGND_LSD GND 1 1 MTP32 EIC 1 2 0.1U_0603_16V7K MBR906 MC908 0.015U_0603_25V7K 2 MMBD3004S_SOT23 470P_1808_3KV MR910 2 237K_0805_1% AGND_LSD RXI 1 RXI-1 2 1 MTP71 MFB904 TIP_2 MOD_TIP 1 2 1 MTP70 MMZ1608D301BT_0603 AGND_LSD R Bias 1 MR9542 59K_0402_1% 1 2 MC966 0.01U_0805_100V7M MTP69 MC910 VZ 1 1 MR908 2 BRIDGE_CC 1 2 348K_0805_1% 0.047U_1206_100V7K AGND_LSD MTP68 MTP67 C 1 EIO 1 MQ902 2 B PMBTA42_SOT23 Use 59K_0402_1% for MR954 E EIF MQ904 C 1 TXO MQ906 2 B PMBTA42_SOT23 FZT458TA_SOT223 E MTP66 1 TXF 1 MTP64 DGND_LSD 2 MTP24 MC962 47P_0603_50V8J C906 and C908 must be Y3 type Capacitors for Nordic Countries only MTP37 3 PWRCLKP 3 MFB906 1 <31> 2 MTP58 MU902 1 MTP36 1 2 AGND_LSD 1 MRV902 TB3100M-13-01_SMB 1 MTP23 MR932 MC926 15K_0402_5% 10P_0402_50V8J 1 2 CLK2 1 2 CLK 1 1 PWRCLKN 3 <31> 4 BR908_AC1 1 4 2 1 MT902 MC978 0.1U_0402_10V6K 2 1 1 1 1 MC930 2.2U_0805_10V6K 1 1 MTP29 MTP22 3 6 MBR908A BAV99DW-7_SOT363 1 0.1U_0402_10V6K 1 1 MTP26 GND MTP49 AGND_LSD DGND_LSD AGND_LSD AGND_LSD AGND_LSD Compal Secret Data Security Classification Issued Date 2005/03/01 Deciphered Date 2005/04/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title AMOM_modem Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 32 of 53 A B C D E HEADPHONE OUT/LINE OUT +5VAMP R362 0_1206_5% 1 2 0.1U_0402_16V4Z 1 C548 10U_0805_10V4Z 1 Gain Settings 1 C549 2 +5VS GAIN0 GAIN1 SE/BTL# 0 0 0 0 1 0 1 0 0 15.6 dB 1 1 0 21.6 dB X X 1 4.1 dB C550 2 PVDD2 PVDD1 C552 1 2 0.047U_0603_16V7K LINE_C_OUTR 23 VDD U26 C551 1 RLINEIN 9 4 16 21 SPKLSPKL+ SPKRSPKR+ SE C553 1 2 0.47U_0603_16V7K 8 RIN LOUTLOUT+ ROUTROUT+ C554 1 2 0.47U_0603_16V7K 10 LIN SE/BTL# 15 HP/LINE# 17 2 0.47U_0603_16V7K HP_C_OUTR 20 RHPIN SPKL+ <35> SPKR+ <35> 1 * 10 dB 18 7 19 0.1U_0402_16V4Z LINE_OUTR 6 dB 2 1 <31> Av(inv) 10 dB BYPASS 22 1 JP22 SPKL+ SPKLSPKR+ SPKR- 11 SHUTDOWN# 2 GND1 GND2 GND3 GND4 1 12 13 24 2 3 2 1 C558 0.47U_0603_10V7K @ R365 100K_0402_5% R366 100K_0402_5% 1 2 3 4 TPA0312PWP_TSSOP24 2 1 2 @ 1 2 @ C562 47P_0402_50V8J PC-BEEP C561 47P_0402_50V8J GAIN1 GAIN0 14 EC_MUTE# <37,38> EC_MUTE# LLINEIN C560 47P_0402_50V8J 2 0.47U_0603_16V7K LHPIN 5 C559 47P_0402_50V8J C557 1 6 1 2 0.047U_0603_16V7K LINE_C_OUTL 2 2 0.47U_0603_16V7K C556 1 2 HP_C_OUTL C555 1 1 LINE_OUTL @ R364 100K_0402_5% 2 <31> 1 +5VS R363 100K_0402_5% 1 2 @ 1 2 3 4 ACES_85205-0400 1 2 2 @ +5VS 1 C735 0.1U_0402_16V4Z 1 I0 U52 O I1 4 SE G 2 HP_PLUG 3 JACK_DET P 5 2 TC7SH32FU_SSOP5 5/13 HP requirement +5VS 3 3 +5VS D 1 100K_0402_5% Q53 2N7002_SOT23 JACK_DET_D <31> 1 Q57 2N7002_SOT23 3 Q52 2N7002_SOT23 D 2 G D 3 3 S R359 100K_0402_5% 2 Q24 2N7002_SOT23 S D S 2 G S R358 1 1 1 1 2 3 JACK_DET# 3 2 2 1 2 <40> HP_PLUG_D <31> D 2 G 2 2 1 1 2 Q54 2N7002_SOT23 JACK_DET# G S JACK_DET 100K_0402_5% G 3 HP_PLUG# 2 G +3VS 100K_0402_5% R434 100K_0402_5% R586 R367 100K_0402_5% D +5VS 1 1 1 HP_PLUG 2 <35> R433 100K_0402_5% R571 100K_0402_5% HP_PLUG# +3VS 2 +5VS R368 1 +5VS 1 +5VS S Q56 2N7002_SOT23 4 4 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title AMP & Audio jack THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 33 of 53 +5V +USB_VCCB U28 ON# 4 GND 2 2 0.1U_0402_16V4Z 1 2 10K_0402_5% 0.47U_0603_16V7K 2 AATI4610AIGV-T1_SOT23-5 R370 USB CONNECTOR 0/3 (Left side) C566 R369 OVCUR#2 1 R371 20K_0402_5% C570 1000P_0402_50V7K R563 0_0402_5% 2 2 2 OVCUR#3 OVCUR#3 <20> <20> L33 USBP0+ USBP0+ 4 USBP0- USBP0- 1 +5V +USB_VCCB ON# GND 2 SET 2 3 @ C574 @ R372 2 10K_0402_5% 1 0.47U_0603_16V7K + 2 AATI4610AIGV-T1_SOT23-5 @ R373 2 OVCUR#3 1 1 4.7K_0402_1% @ 1 R374 20K_0402_5% 2 2 3 3 1 2 2 USBP0+_R JP23 1 2 3 4 USBP0-_R 1 @ C578 2 9 10 11 12 1 2 R559 0_0402_5% W=40mils 1 C568 0.1U_0402_16V4Z 1 4 C567 100U_6.3V_M OUT IN 1 5 4 WCM2012F2S-900T04_0805 +USB_VCCC @ U29 0.1U_0402_16V4Z R562 0_0402_5% 1 2 R561 0_0402_5% 1 2 <20> @ C573 2 1 07/05 for EMI 07/05 for EMI OVCUR#0 <20> 1 1 1 4.7K_0402_1% 1 2 1 2 3 4 5 6 7 8 5 6 7 8 USBP3+_R L34 WCM2012F2S-900T04_0805 USBP3+ 3 3 4 4 USBP3+ <20> USBP3-_R 2 USBP3- USBP3- <20> 2 1 1 1 2 R560 0_0402_5% GND GND GND GND SUYIN_020122MR008S573ZR @ 0_0603_5% 1 2 R564 +USB_VCCC +USB_VCCB W=40mils 1000P_0402_50V7K 1 2 1 2 C575 100U_6.3V_M SET 1 C576 0.1U_0402_16V4Z 3 OUT C577 1000P_0402_50V7K IN C569 1000P_0402_50V7K 5 1 C565 2 1 1 + 2 BT CONNECTOR 5/4 reserve BT_ON# G 2 <20> D28 3 1 1 +3V_BT +USB_VCCB D35 USBP0+_R D C582 1U_0603_10V4Z S +3VALW C581 1U_0603_10V4Z 1 2 1 2 AO3413_SOT23 Q18 USBP3-_R 2 3 D1+ D2+ GND VCC D2- D1- 4 USBP3+_R 5 6 USBP0-_R @ IP4220CZ6_SO6 JP25 3 <17,30,35> WIRELESS_LED 1 2 1N4148_SOT23 <20> <20> USBP6+ USBP6- <30> <30> <20> CH_DATA CH_CLK BT_DET# R375 R376 1 1 USBP6+ USBP6WIRELESS_LED_BT 2 100_0402_5% 2 100_0402_5% BT_DET# 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ACES_87213-0800 <35> ON/OFFBTN# 0.1U_0402_16V4Z 2 <35,37,38> KSI0 0.1U_0402_16V4Z 2 <35,37,38> KSI1 0.1U_0402_16V4Z 2 <35,37,38> KSI3 0.1U_0402_16V4Z 2 <35,37,38> KSI4 0.1U_0402_16V4Z 2 <35,37,38> KSO17 0.1U_0402_16V4Z 2 <17,30,35> WIRELESS_LED 0.1U_0402_16V4Z 2 <35,37,38> VOL_UP# 0.1U_0402_16V4Z 2 <35,37,38> VOL_DWN# 0.1U_0402_16V4Z 2 <35,37,38> LID_SW# 0.1U_0402_16V4Z 2 <35,37,38> NUMLED# 0.1U_0402_16V4Z 2 <31,35,40> MUTE_LED 0.1U_0402_16V4Z 2 <35,37,38> PWR_ACTIVE# 0.1U_0402_16V4Z 2 <35,36,38> PA_LED_ALW 0.1U_0402_16V4Z 2 <35,36> PR_LED_ALW 0.1U_0402_16V4Z 2 <35,36> PA_LED 0.1U_0402_16V4Z 2 <35,36> PR_LED 0.1U_0402_16V4Z 2 <35,36> PA_LED_VS 0.1U_0402_16V4Z 2 <35,36> PR_LED_VS 0.1U_0402_16V4Z 2 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ C753 C754 C755 C756 C757 C758 C759 C760 C761 C762 C763 C764 C765 C766 C767 C768 C769 C770 C771 Issued Date 2005.08.11 for EMI solution Compal Secret Data Security Classification 2005/03/01 Deciphered Date 2005/04/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Bluetooth & USB CONN Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 34 of 53 4 KSI6 C665 C@1 2 100P_0402_50V8J KSI1 C586 D@ 1 2 100P_0402_50V8J KSO9 C666 C@1 2 100P_0402_50V8J KSI4 C587 D@ 1 2 100P_0402_50V8J KSI4 C667 C@1 2 100P_0402_50V8J KSI6 C588 D@ 1 2 100P_0402_50V8J KSI5 C668 C@1 2 100P_0402_50V8J KSI3 C589 D@ 1 2 100P_0402_50V8J KSO0 C669 C@1 2 100P_0402_50V8J Power BTN D13 DAN202U_SC70 2 C670 C@1 2 100P_0402_50V8J KSI3 C671 C@1 2 100P_0402_50V8J JP27 KSO2 C592 D@ 1 2 100P_0402_50V8J KSO5 C672 C@1 2 100P_0402_50V8J 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 KSO4 C593 D@ 1 2 100P_0402_50V8J KSO1 C673 C@1 2 100P_0402_50V8J KSO0 2 100P_0402_50V8J KSI0 C674 C@1 2 100P_0402_50V8J 2 100P_0402_50V8J KSO2 C675 C@1 2 100P_0402_50V8J KSO5 C597 D@ 1 2 100P_0402_50V8J KSO4 C676 C@1 2 100P_0402_50V8J KSO6 C598 D@ 1 2 100P_0402_50V8J KSO7 C677 C@1 2 100P_0402_50V8J KSO3 C599 D@ 1 2 100P_0402_50V8J KSO8 C678 C@1 2 100P_0402_50V8J KSO7 C600 D@ 1 2 100P_0402_50V8J KSO6 C679 C@1 2 100P_0402_50V8J KSO8 C601 D@ 1 2 100P_0402_50V8J KSO3 C680 C@1 2 100P_0402_50V8J KSO9 C602 D@ 1 2 100P_0402_50V8J KSO12 C681 C@1 2 100P_0402_50V8J KSO10 C603 D@ 1 2 100P_0402_50V8J KSO13 C682 C@1 2 100P_0402_50V8J KSO11 C604 D@ 1 2 100P_0402_50V8J KSO14 C683 C@1 2 100P_0402_50V8J KSO12 C605 D@ 1 2 100P_0402_50V8J KSO11 C684 C@1 2 100P_0402_50V8J KSO13 C606 D@ 1 2 100P_0402_50V8J KSO10 C685 C@1 2 100P_0402_50V8J KSO14 C607 D@ 1 2 100P_0402_50V8J KSO15 C686 C@1 2 100P_0402_50V8J KSO15 C660 D@ 1 2 100P_0402_50V8J KSO17 C661 D@ 1 2 100P_0402_50V8J +3VL 5/3 change 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D 1 Q19 DTC124EK_SC59 R378 4.7K_0402_5% C595 D14 RLZ20A_LL34 2 1000P_0402_50V7K <37,38,45> EC_ON EC_ON WHEN R=0,Vbe=1.35V WHEN R=33K,Vbe=0.8V D 2 G Q20 @ 2N7002_SOT23 S ACES_85201-2405 LDO5 TP to MB CONN Consumer IR C CIR@ R379 100_0402_5% 5/9 change 2 ACES_85201-2605 C594 D@ 1 KSO16 C596 D@ 1 KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 <37,38> EC_PWR_ON# <43> 15.4 ( TYPE "C" KB) 1 KSI2 2 100P_0402_50V8J ON/OFF# 1 I 2 100P_0402_50V8J C591 D@ 1 5/3 change 100K_0402_5% 2 +3VL ON /OFF# 3 ON/OFFBTN# 1 C590 D@ 1 KSO1 R377 1 1 2 100P_0402_50V8J 2 C585 D@ 1 1 2 100P_0402_50V8J KSI5 O 2 100P_0402_50V8J C@1 KSI2 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C C@1 C664 2 KSI7 KSI0 KSI5 KSI1 KSI4 KSI6 KSI3 KSI2 KSO1 KSO2 KSO4 KSO0 KSO16 KSO5 KSO6 KSO3 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO17 C663 KSI7 JP20 KSO[0..17] <34,37,38> D KSI1 2 100P_0402_50V8J G <34,37,38> 2 100P_0402_50V8J C584 D@ 1 2 KSI[0..7] KSO[0..17] C583 D@ 1 KSI0 1 1 KSI[0..7] KSI7 2 3 INT_KBD CONN.( TYPE "D" KB) 3 3 5 @ C701 1 2 0.1U_0402_10V6K JP35 +5V <37,38> <37,38> TP_DATA TP_CLK 1 2 3 4 5 6 7 8 TP_DATA TP_CLK +3VS TPM(reserve) 1 1 C610 @ C611 1 @ C612 1 @ C613 CIR@ C608 4.7U_0805_6.3V6K 1 1 2 2 <37,38,40> CIR@ C609 0.1U_0402_10V6K U30 CIR@ 3 4 CIR_IN CIR_IN Vs OUT GND GND 1 2 TSOP6236TR_4P @ ACES_87152-0807 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 8 13 27 12 23 20 1 LCLK LFRAME# LRESET# SERIRQ CLKRUN# BADDR NC NC NC NC 1 14 15 28 @ R380 10K_0402_5% +3VS 2 Switch board conn 1 @ R381 300_0402_5% GND GND GND GND 2 4 10 18 24 @ R384 4.7K_0402_5% @ R382 10K_0402_5% <17,30,34> WIRELESS_LED <34,37,38> VOL_UP# <34,37,38> VOL_DWN# <34,37,38> LID_SW# <34,37,38> NUMLED# <31,34,40> MUTE_LED Base I/O Address SLD9630TT_TSSOP28 0 = 02Eh * 1 = 04Eh <34,37,38> PWR_ACTIVE# +5VALW <34,36,38> PA_LED_ALW <34,36> PR_LED_ALW +5V <34,36> PA_LED <34,36> PR_LED +5VS <34,36> PA_LED_VS <34,36> PR_LED_VS +3VALW JP30 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FOR LPC SIO DEBUG PORT +5VS ON/OFFBTN# KSI0 KSI1 KSI3 KSI4 KSO17 WIRELESS_LED VOL_UP# VOL_DWN# LID_SW# NUMLED# MUTE_LED PWR_ACTIVE# PA_LED_ALW PR_LED_ALW PA_LED PR_LED PA_LED_VS PR_LED_VS +3VS B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 JP29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +5V <20> <20> <20> USBP4+ USBP4OVCUR#4 <20> <20> USBP5+ USBP5- SPDIFO <31,40> SPDIFO <40> DOCK_MIC <31> MIC R582 18K_0402_5% DOCK_MIC 1 2 MIC +5VS <33> <33> <33> USBP4+ USBP4OVCUR#4 USBP5+ USBP5- HP_PLUG# SPKR+ SPKL+ 2005/07/21 HP_PLUG# SPKR+ SPKL+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ACES_87213-2000 R583 2K_0402_5% ACES_85201-2505 8/23 Add +3VALW power rail for Boxster lid Switch LPC_AD[0..3] <19,37,38> LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LDRQ0# PCI_RST# Audio board conn JP28 <34> ON/OFFBTN# <34,37,38> KSI0 <34,37,38> KSI1 <34,37,38> KSI3 <34,37,38> KSI4 2 CLK_PCI_TPM LPC_FRAME# NB_RST# SIRQ PCI_CLKRUN# CLK_PCI_TPM LPC_FRAME# NB_RST# SIRQ PCI_CLKRUN# @ R452 10K_0402_5% 1 2 1 2 @ R383 4.7K_0402_5% <19> <19,37,38> <13,19,24,28> <19,25,37,38> <19> 26 17 16 21 22 9 1 1 B LPCPD# TESTEN TESTIO PACCESS PENABLE CLKOVD TPM SLD 9630 TT 1.1 2 LAD0 LAD1 LAD2 LAD3 1 2 3 6 7 2 +3VS LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VDDC VDD VDD VDD <19,37,38> <19,37,38> <19,37,38> <19,37,38> 19 5 11 25 +3VS @ U31 5/3 pin swap A LPC_FRAME# <19,37,38> LDRQ0# <19> PCI_RST# <19,25,27,29,30,37,38> CLK_PCI_SIO SIRQ <19,25,37,38> @ R385 10K_0402_5% 2 1 1 2 CLK_PCI_SIO_R <19,23> @ R386 22_0402_5% Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title KBD,ON/OFF,T/P,LED/B,DEBUG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ACES_85201-2005 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 35 of 53 5 4 3 2 For PA For PR FOR POWER BUTTON BACKLIGHT SYSTEM POWER FOR POWER BUTTON BACKLIGHT SYSTEM POWER "Vertical" R390 150_0402_5% 1 2 D <37,38> PMLED_1# "Right Angle" 15.4@ D17 D18 1 1 2 PA_LED <34,35> PMLED_1# R389 15.4@ 680_0402_5% 1 2 D 2 PR_LED 1 HT-170NBQA_0805 <34,35> 3 12-21UYOC/S530-A2/TR8_YEL R392 150_0402_5% 2 1 <37,38> BATLED_0# R391 15.4@ 680_0402_5% BATLED_0# 2 1 D20 1 2 PA_LED_ALW <34,35,38> 15.4@ D19 2 3 12-21UYOC/S530-A2/TR8_YEL HT-170NBQA_0805 <24> R393 150_0402_5% 1 2 ACT_LED D21 1 PR_LED_ALW <34,35> 1 2 ACT_LED PA_LED_VS <34,35> R394 15.4@ 680_0402_5% 1 2 15.4@ D22 2 PR_LED_VS <34,35> 1 3 12-21UYOC/S530-A2/TR8_YEL HT-170NBQA_0805 5/4 change C R395 D@ 150_0402_5% 1 2 <37,38> CAPSLED# D@ D23 1 PA_LED_VS 2 CAPSLED# R396 15.4@ 680_0402_5% 1 2 D24 1 15.4@ PR_LED_VS 2 C 17-21UYOC/S530-A2/TR8_ORG HT-170NBQA_0805 CAPSLED# 15.4@ R574 150_0402_5% 1 2 15.4@ 1 for 15.4 PA D34 PA_LED_VS 2 HT-170NBQA_0805 PR_LED_VS <34,35> 5/10 change PA_LED_VS <34,35> "Right Angle" 2 2 "Vertical" D25 17-21UYOC/S530-A2/TR8_ORG D26 PA@ HT-110NBQA_0805 B B 1 1 2 2 PR@ 1 R468 1K_0402_5% CARD_LED 2 1 Q21 2 3 <25,26> CARD_LED 1 R397 150_0402_5% PA@ 1 PR@ R566 680_0402_5% MMBT3904_SOT23 7411@ 7411@ A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title INDICATE LED THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 36 of 53 B C D +EC_AVCC ECAGND <38> +3VL <38> <38> 1 TP_DATA 2 1 TP_CLK C R Y1 C R Y2 C R Y1 C R Y2 <35,38> <35,38> OUT NC 1 IN 2 Y6 32.768KHZ_12.5P_1TJS125DJ2A073 NC 2 3 C619 10P_0402_50V8K 1 4 1 2 TP_CLK TP_DATA <20,38> EC_RSMRST# C620 10P_0402_50V8K<20,38> M_SEN# CONA# ENABLT BKOFF# DOCK_VOL_UP# FSTCHG CAPSLED# NUMLED# EC_SMI# EC_MUTE# EC_SWI# VOL_UP# 48 54 55 62 63 69 70 75 161 159 VCCBAT BATGND 16 34 45 123 136 157 166 95 96 GND1 GND2 GND3 GND4 GND6 GND7 VCCA AGND VLDT_EN SCL1 SDA1 SCL2 SDA2 163 164 169 170 EC_SMC_1 EC_SMD_1 EC_SMC_2 EC_SMD_2 GPIO20/E51CS#/ISPEN_TP GPIO21/E51RXD/ISPCLK GPIO22/E51TXD/ISPDAT A20/GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO2A GPIO2B LRST#/GPIO2C GPIO2D TOUT2/GPIO2F 105 106 107 108 109 118 119 148 149 155 156 162 165 168 175 EC_TINIT# URXD UTXD 2 26 29 30 44 76 172 ON /OFF# AC IN CIR_IN SLP_S3# SLP_S5# VOL_DWN# PME_EC# SM BUS PS2 interface GPIO2 XCLKI XCLKO GPIO00/E51IT0 GPIO01/E51IT1 GPIO04 GPIO07 GPIO08 GPIO09 NUMLOCK#/GPIO0A GPIO0B CLKRUN#/GPIO0C GPIO0D GPIO0E SCROLLLOCK#/GPIO0F GPWU0 GPWU1 GPWU2 GPWU3 GPWU4 GPWU5 GPWU6/TIN1 GPWU or GPI GPIO0 GPIO10 CAPLOCK#/GPIO11 FNLOCK#/GPIO12 GPIO13 GPIO1 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18/XIO8CS# GPIO19/XIO9CS# GPIO1A/XIOACS# GPIO1B/XIOBCS# GPIO1C/XIOCCS# GPIO1D/XIODCS# GPIO1E/XIOECS# GPIO1F/XIOFCS# BIOS I/F KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19 124 125 126 127 128 131 132 133 143 142 135 134 130 129 121 120 113 112 104 103 <20,38> EC_SWI# <34,35,38> VOL_UP# 3 4 8 20 21 22 23 24 25 27 28 41 Key matrix scan 85 86 91 92 93 94 97 98 KBA[0..19] <38,39> ADB[0..7] 5/3 change +3VL KBA1 @ R401 10K_0402_5% 1 2 KBA3 @ R402 10K_0402_5% 1 2 ACOFF EC_ON LID_OUT# <38,44> KBA5 910@ R404 10K_0402_5% 1 2 EC_ON <35,38,45> LID_OUT# <20,38> D@ R406 1K_0402_5% VLDT_EN <38,42> GPIO5 FAN_SPEED1 BID FAN_SPEED1 <4,38> GPIO6 C@ R409 1K_0402_5% EC_SMC_1 EC_SMD_1 EC_SMC_2 EC_SMD_2 URXD UTXD AIR_ACIN LID_SW# SYSON SUSP# VR_ON PCI_RST# PWRBTN_OUT# EC_THERM# <38,39,49> <38,39,49> <4,38> <4,38> 2 <38> <38> Board ID AIR_ACIN <38,44> LID_SW# <34,35,38> Cayenne 17" High R406 SYSON SUSP# VR_ON Boxter 15.4" L ow R409 <28,38,41,46> <28,38,39,41> <38,48> PCI_RST# <19,25,27,29,30,35,38> PWRBTN_OUT# <20,38> EC_THERM# <20,38> 5/3 change ON/OFF# <35,38> ACIN <38,43,45> CIR_IN <35,38,40> SLP_S3# <20,38> SLP_S5# <20,38> VOL_DWN# <34,35,38> PME_EC# <29,30,38> PMLED_1# PWR_ACTIVE# BATLED_0# +3VL 910@ R412 10K_0402_5% PMLED_1# <36,38> PWR_ACTIVE# <34,35,38> BATLED_0# <36,38> 3 EC_TINIT# GPIO5 MUTE_GATE <31,38> GPIO6 910@ 910@ R413 10K_0402_5% KB910_LQFP176 FSEL# FWR# FR D# <38,39> C617 0.22U_0603_10V7K INVT_PWM <17,38> ACOFF <44> 1 158 160 PSCLK1 PSDAT1 PSCLK2 PSDAT2 PSCLK3 PSDAT3 PWM2/GPOW2/FAN1PWM PWM7/GPOW7/FAN2PWM FAN/PWM GPIO05/FAN3PWM/TEST_TP FANFB1/TOUT1/GPIO2E GPWU7/TIN2/FANFB2 GPIO06/FANFB3/DPLL_TP 36 43 11 171 176 12 PWM0/GPOW0 PWM1/GPOW1 PWM3/GPOW3 PWM4/GPOW4 PWM5/GPOW5 PWM6/GPOW6 PWM or GPOW ADP_I 1 1 2 C R Y1 C R Y2 EC_SCI# <38,44> FSTCHG <36,38> CAPSLED# <34,35,38> NUMLED# <20,38> EC_SMI# <33,38> EC_MUTE# 3 110 111 114 115 116 117 EC_RSMRST# EC_SCI# <18,38> M_SEN# <38,40> CONA# <13,17,38> ENABLT <17,38> BKOFF# <38,40> DOCK_VOL_UP# KBD_CLK KBD_DATA PS2_CLK PS2_DATA TP_CLK TP_DATA KSO0/GPOK0 KSO1/GPOK1 KSO2/GPOK2 KSO3/GPOK3 KSO4/GPOK4 KSO5/GPOK5 KSO6/GPOK6 KSO7/GPOK7 KSO8/GPOK8 KSO9/GPOK9 KSO10/GPOK10 KSO11/GPOK11 KSO12/GPOK12 KSO13/GPOK13 KSO14/GPOK14 KSO15/GPOK15 KSO16/GPOK16 KSO17/GPOK17 INVT_PWM 2 DAC_BRIG <17,38> EN_FAN1 <4,38> IREF <38,44> <38> 2 2 49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68 153 154 32 33 37 38 39 40 DOCK_VOL_DWN# <38,40> ADP_IR 1 PS2_CLK KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 DAC_BRIG EN_FAN1 IR EF R399 10K_0402_5% 1 <38> 2 2 1 KSO[0..17] BID DOCK_VOL_DWN# 1 1 PS2_DATA <34,35,38> KSO[0..17] KSI0/GPIK0 KSI1/GPIK1 KSI2/GPIK2 KSI3/GPIK3 KSI4/GPIK4 KSI5/GPIK5 KSI6/GPIK6 KSI7/GPIK7 BATT_OVP <38,44> BID 99 100 101 102 1 42 47 174 DA0/GPODA0 DA1/GPODA1 DA2/GPODA2 DA output or GPO DA3/GPODA3 DA4/GPODA4 DA5/GPODA5 DA6/GPODA6 DA7/GPODA7 GPIO02/GA20 GPIO03/KBRST# BATT_OVP ADP_IR 1 1 71 72 73 74 77 78 79 80 0.01U_0402_16V7K C616 1 2 ECAGND 81 82 83 84 87 88 89 90 RD# WR# IOCS# MEMCS# +5VS R407 910@ 10K_0402_5% 2 R408 910@ 10K_0402_5% 2 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSI[0..7] BATT_TEMP <38,49> 150 151 152 173 KBD_CLK <20,38> EC_GA20 <20,38> KB_RST# <34,35,38> KSI[0..7] 2 17 35 46 122 167 137 ECAGND KBD_DATA 1 5 6 Host interface D0 D1 D2 D3 D4 D5 D6 D7 2 1 EC_GA20 KB_RST# C618 0.1U_0402_16V4Z PWR/GND 910@ C614 1U_0603_10V6K AD0/GPIAD0 AD1/GPIAD1 AD2/GPIAD2 AD3/GPIAD3 AD4/GPIAD4 AD Input or GPI AD5/GPIAD5 AD6/GPIAD6 AD7/GPIAD7 138 139 140 141 144 145 146 147 2 JOPEN +5VS R403 910@ 10K_0402_5% 2 R405 910@ 10K_0402_5% 2 +5V R410 10K_0402_5% R411 10K_0402_5% 1 J3 SERIRQ LFRAME# LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LCLK ECRST# ECSCI# 2 ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 1 +3VL EC_RST# R400 47K_0402_5% 1 2 7 9 15 14 13 10 18 19 31 A0 A1/XIOP_TP A2 A3 A4/DMRP_TP A5/EMWB_TP A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 <38> 5/3 change SIRQ LPC_FRAME# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 CLK_PCI_EC EC_RST# VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 U32 <19,25,35,38> SIRQ <19,35,38> LPC_FRAME# <19,35,38> LPC_AD0 <19,35,38> LPC_AD1 <19,35,38> LPC_AD2 <19,35,38> LPC_AD3 <19,23,38> CLK_PCI_EC 1 5/3 change 1 FSEL# <38,39> FWR# <38,39> FRD# <38,39> 910@ R414 10K_0402_5% 2 +3VL 5/3 change E 2 A KBA[0..19] AD B[0..7] EC DEBUG port 6/27 change JP31 1 2 3 4 1 2 3 4 URXD UTXD LDO5 4 4 ACES_85205-0400 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title EC KB910 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 37 of 53 5 4 3 5/3 change 5/3 change 0.1U_0402_16V4Z +3VL 1 5/3 change Close to PR184 2 1 2 2 C625 2 C626 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 5/3 change +3VL GA20/ GPIO00/GA20 KBRST#/GPIO01/KBRST# SERIRQ LPC_FRAME# / LFRAME# LPC AD3/LAD3 LPC AD2/LAD2 Host LPC AD1/LAD1 INTERFACE LPC AD0/LAD0 CLK_PCI_EC/PCICLK PCIRST# EC RST#/ ECRST# EC SCI#/SCI#/GPIO0E PM_CLKRUN#/ CLKRUN# KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 63 64 65 66 67 68 69 70 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPI032 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPI035 KSI6/GPIO36 KSI7/GPIO37 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 89 90 key Matrix scan KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F EC URXD/KSO16/GPIO48 EC UTXD/KSO17/GPIO49 EC_SMD_2 EC_SMC_2 EC_SMD_1 EC_SMC_1 88 87 86 85 EC SMD2/ GPIO47/SDA2 EC SMC2/GPIO46/SCL2 EC SMD1/GPIO44/SDA1 EC SMC1/GPIO44/SCL1 UTXD URXD PMLED_1# NUMLED# BATLED_0# 34 35 38 40 99 101 100 102 104 2 1 2 3 5 6 9 10 12 14 15 42 24 44 1 2 1 C628 15P_0402_50V8J <34,35,37> KSO17 EC_SMD_2 EC_SMC_2 EC_SMD_1 EC_SMC_1 5/3 change 10K_0804_8P4R_5% +3VL RP58 8 7 6 5 B 1 2 3 4 FSEL# FR D# EC_SMI# LID_SW# 10K_0804_8P4R_5% 4/27 change +3VL +3VS R575 4.7K_0402_5% 1 2 PME_EC# R418 10K_0402_5% 1 2 VOL_UP# 75 DAC_BRIG EN_FAN1 IR EF AIR_ACIN INVT_PWM/GPIO0F/PWM1 BEEP#/GPIO10/PWM2 OUT BEEP/GPIO12/PWM3 ACOFF/GPIO18/PWM4 FAN SPEED1/GPIO14/FANFB1 FAN SPEED2/GPIO15/FANFB2 25 27 30 31 32 33 INVT_PWM CONA# VLDT_EN ACOFF FAN_SPEED1 VOL_DWN# PSCLK1 PSDAT1 PSCLK2 PSDAT2 PSCLK3 PSDAT3 91 92 93 94 95 96 PWR_ACTIVE# DOCK_VOL_UP# TP_CLK TP_DATA 125 126 128 130 131 132 133 134 111 112 113 114 115 116 117 118 119 120 121 122 123 124 110 109 108 107 106 98 ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19 <4,37> <4,37> <37,39,49> <37,39,49> EC_SMD_2 EC_SMC_2 EC_SMD_1 EC_SMC_1 <37> UTXD <37> URXD <36,37> PMLED_1# <34,35,37> NUMLED# <36,37> BATLED_0# <36,37> CAPSLED# <28,37,41,46> SYSON <20,37> EC_RSMRST# <17,37> BKOFF# <20,37> SLP_S3# <20,37> LID_OUT# <20,37> SLP_S5# <20,37> EC_SMI# <20,37> EC_SWI# <34,35,37> LID_SW# <28,37,39,41> SUSP# <20,37> PWRBTN_OUT# <29,30,37> PME_EC# <37> <37> C R Y2 C R Y1 CAPSLED# SYSON EC_RSMRST# BKOFF# SLP_S3# LID_OUT# SLP_S5# EC_SMI# EC_SWI# LID_SW# SUSP# PWRBTN_OUT# PME_EC# C R Y2 C R Y1 4 7 8 16 17 18 19 20 21 22 23 140 138 Data BUS Address BUS SM BUS PCM_SPK#/EMAIL_LED#/ GPIO16 SB_SPKR/PWR_SUSP_LED#/ GPIO17 PWRLED#/ GPIO19 NUMLED#/ GPIO1A BATT CHGI LED#/ E51CS# BATT LOW LED#/ E51MR0 CAPS LED#/ E51TMR1 ARROW LED#/ E51 INT0 SYSON/GPIO56/ E51 INT1 XCLKO XCLKI ADB0/D0 ADB1/D1 ADB2/D2 ADB3/ D3 ADB4/D4 ADB5/D5 ADB6/D6 ADB7/D7 KBA0/A0 KBA1/A1 KBA2/A2 KBA3/A3 KBA4/A4 KBA5/A5 KBA6/A6 KBA7/A7 KBA8/A8 KBA9/A9 KBA10/A10 KBA11/A11 KBA12/A12 KBA13/A13 KBA14/A14 KBA15/A15 KBA16/A16 KBA17/A17 KBA18/A18 KBA19/A19 SELIO2#/ GPIO43 SELIO#/ GPIO50 FRD#/RD# FWR#/WR# FSEL#/SELMEM# EC_RSMRST#/ GPIO02 BKOFF#/GPIO03 PM SLP S3#/GPIO04 EC LID OUT#/GPIO06 PM SLP S05#/ GPIO07 EC SMI#/GPIO08 EC SWI#/GPIO09 LID SW#/ GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC PME#/GPIO0D KB910L_LQFP144 R419 10K_0402_5% 1 2 VOL_DWN# PS2 interface EC ON/ GPIO1B AC IN/ GPIO1C ECTHERM#/GPIO11 ONOFF/GPIO18 PCMRST#/GPIO1E WL OFF#/GPIO1F AGND KSO[0..16] R415 10_0402_5% 1 2 3 4 76 78 79 80 ALI/MH#/GPIO40 FSTCHG/GPIO41 VR ON/ GPIO42 GPIO57/GPIO57 GPIO58/GPIO58 GPIO59/GPIO59 84 97 135 136 144 DAC_BRIG <17,37> EN_FAN1 <4,37> IREF <37,44> AIR_ACIN <37,44> EC_ON AC IN EC_THERM# ON /OFF# VOL_UP# 41 43 29 36 45 46 81 82 83 137 142 143 INVT_PWM <17,37> CONA# <37,40> VLDT_EN <37,42> ACOFF <37,44> FAN_SPEED1 <4,37> VOL_DWN# <34,35,37> PWR_ACTIVE# <34,35,37> DOCK_VOL_UP# <37,40> TP_CLK <35,37> TP_DATA <35,37> AD B[0..7] ADB[0..7] <37,39> KBA[0..19] C KBA[0..19] <37,39> B ENABLT DOCK_VOL_DWN# FR D# FWR# FSEL# 1 ENABLT <13,17,37> DOCK_VOL_DWN# <37,40> FRD# <37,39> FWR# <37,39> FSEL# <37,39> EC_ON <35,37,45> ACIN <37,43,45> EC_THERM# <20,37> ON/OFF# <35,37> VOL_UP# <34,35,37> MUTE_GATE <31,37> 2 @ R600 0_0402_5% M_SEN# FSTCHG FSTCHG <37,44> VR_ON VR_ON <37,48> ACIN_2 CIR_IN CIR_IN <35,37,40> EC_MUTE# EC_MUTE# <33,37> M_SEN# <18,37> 8/23 reseve R600, currently M_SEN# isn't used 07/28 for lower power consumption ECAGND ECAGND <37> R420 10K_0402_5% 1 2 DOCK_VOL_UP# A BATT_TEMP <37,49> BATT_OVP <37,44> ADP_IR <37> BID <37> 77 KSO[0..16] 07/04 for EMI RP57 DAC_BRIG/DA0/GPIO3D EN DFAN1/DA1/GPIO3D IREF2/DA2 EN DFAN2/DA3/ GPIO3F DA output or GPO PWR KSI[0..7] CLK_PCI_EC +5VALW BATT_TEMP BATT_OVP ADP_IR BID BATTEMP/AD0/GPIO38 BATT OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A AD BID0/AD3/GPIO3B AD INtput or GPI FAN/PWM <34,35,37> KSI[0..7] 1 High : PA Low : PR 71 72 73 74 EC_AVCC / AVCC EC_GA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC PCI_RST# EC_RST# EC_SCI# 11 26 37 105 127 141 U33 <35,37> 8 7 6 5 1 ECAGND D C 2 +EC_AVCC 2 +3VL R585 2K_0402_5% 5/11 add 1 2 L31 FBML10160808121LMT_0603 1 +EC_AVCC 1 C624 0.1U_0402_16V4Z <20,37> EC_GA20 <20,37> KB_RST# <19,25,35,37> SIRQ <19,35,37> LPC_FRAME# <19,35,37> LPC_AD3 <19,35,37> LPC_AD2 <19,35,37> LPC_AD1 <19,35,37> LPC_AD0 <19,23,37> CLK_PCI_EC <19,25,27,29,30,35,37> PCI_RST# R584 <37> EC_RST# 1K_0402_5% <20,37> EC_SCI# 2 1 <34,35,36> PA_LED_ALW 1 C623 VCC/ EC VCC VCC / EC VCC VCC / EC VCC VCC / EC VCC VCC VCC @ R577 0_0805_5% 1 2 1 C622 GND GND GND GND GND GND +3VALW D C621 4.7U_0805_6.3V6K 139 129 103 13 28 39 LDO3 R576 0_0805_5% 1 2 L30 FBML10160808121LMT_0603 1 2 0.01U_0402_16V7K +3VL 2 ACIN_2 R596 0_0402_5% 1 2 @ AC IN A R421 10K_0402_5% 1 2 DOCK_VOL_DWN# 4/27 pop Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title EC KB910L THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 38 of 53 <37,38> ADB[0..7] <37,38> KBA[0..19] AD B[0..7] KBA[0..19] 5/3 change 5/3 change KBA18 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 SST39VF040-70-4C-NH_PLCC32 +3VL +3VL SUSP# KBA19 KBA10 ADB7 ADB6 ADB5 ADB4 1 <28,37,38,41> @ C630 0.1U_0402_16V4Z R422 @ 10K_0402_5% 2 Q22 @ 2N7002_SOT23 2 G 0.1U_0402_16V4Z KBA17 +3VALW U35A ADB3 ADB2 ADB1 ADB0 FR D# FWE# 3 A B O 1 1 3 S 1 C629 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 D 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 KBA16 KBA15 KBA14 KBA13 KBA12 KBA11 KBA9 KBA8 FWE# RESET# +3VL FWE# KBA17 KBA14 KBA13 KBA8 KBA9 KBA11 FR D# KBA10 FSEL# ADB7 ADB6 ADB5 ADB4 ADB3 2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 14 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 G KBA18 KBA16 KBA15 KBA12 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 KBA0 ADB0 ADB1 ADB2 JP32 EC_FLASH# <20> 2 @ SN74LVC32APWLE_TSSOP14 7 U34 FSEL# KBA0 FWR# <37,38> R578 0_0402_5% 1 2 SUYIN-80065A-040G2T 5/4 change +3VLE 5/3 change FSEL# FRD# CE# OE# WE# 31 30 D0 D1 D2 D3 D4 D5 D6 D7 25 26 27 28 32 33 34 35 ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 10 11 12 29 38 RESET# RP# NC READY/BUSY# NC0 NC1 5/3 change +3VLE 1 +3VLE C631 0.1U_0402_16V4Z 1 R423 100K_0402_5% 2 5/3 change 1 2 <37,38,49> EC_SMC_1 <37,38,49> EC_SMD_1 U37 8 7 6 5 2 22 24 9 VCC0 VCC1 VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 AT24C16AN-10SI-2.7_SO8 +3VL @ R424 100K_0402_5% 1 FSEL# FR D# FWE# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 +3VALW R425 100K_0402_5% 2 <37,38> <37,38> 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 LDO3 @ R580 0_0402_5% 1 2 +3VL U36 KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19 R579 0_0402_5% 1 2 GND0 GND1 23 39 @ SST39VF080-70_TSOP40 Compal Secret Data Security Classification Issued Date 2005/03/01 Deciphered Date 2005/04/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title BIOS & EC I/O Port Size Document Number Custom Date: R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet 39 of 53 A B C D E 07/07 for EMI R591 0_0402_5% 1 2 DOCK_LOUT_R_R 1 L32 DOCK@ KC FBM-L18-453215-900LMA90T_1812 1 2 DOCK_VIN 2 DOCKVIN 1 1 DOCK@ C632 1000P_0402_50V7K DOCK_LOUT_R <31> @ C745 1000P_0402_50V7K 1 2 2 1 C633 DOCK@ 1000P_0402_50V7K R592 0_0402_5% 1 2 DOCK_LOUT_L_R 1 Tampa 2 DOCK_LOUT_L <31> @ C746 1000P_0402_50V7K 2 JP33 <31,35> SPDIFO <20,23> SB_SPDIFO <29> <29> <33> R426 DOCK@ 22_0402_5% 1 2 MDO1+ MDO1JACK_DET# DOCK@ 1 2 @ R428 22_0402_5% 1 @ C729 1000P_0402_50V7K 2 R427 1 +5VS <31,34,35> MUTE_LED <25> XTPA1+ <25> XTPA1<25> XTPB1+ <25> XTPB1- MDO1+ MDO1JACK_DET# SPDIFO_L 2 100_0402_5% MUTE_LED XTPA1+ XTPA1XTPB1+ XTPB1- EMI 2 +5V DOCK_PRESENT +3VALW 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 GND DOCK_PRES_GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 MDO0+ MDO0- MDO0+ <29> MDO0- <29> DOCK_MIC DOCK_MIC <35> DOCK_LOUT_R_R DOCK_LOUT_L_R R429 DOCK@ 200_0402_5% 1 2 USBP1USBP1+ USBP1- <20> USBP1+ <20> 1 DOCK_VOL_UP# <37,38> C634 DOCK@ 1000P_0402_50V7K 2 2 TV_COMPS_R TV_LUMA_R TV_CRMA_R R431 DOCK@ 200_0402_5% 2 1 CIR_IN CIR_IN +5V V_Bat <35,37,38> 1K_0402_5% 2 V_Bat <44> DOCK@ 1 R432 2 DOCKVIN DOCK_VOL_DWN# <37,38> 1 C635 DOCK@ 1000P_0402_50V7K 1 DOCKVIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 FOX_QL11293-H212CR-FR 2 R430 DOCK@ 10K_0402_5% CONA# 1 <37,38> Q23 DOCK@ MMBT3904_SOT23 2 07/07 for EMI 3 DOCK_PRESENT +5V C637 DOCK@ 10U_0805_10V4Z DOCK_PRES_GND R593 0_0603_5% 2 1 TV_COMPS_R 1 DOCK@ C636 0.1U_0402_16V4Z 1 1 1 2 2 2 @ C638 1000P_0402_50V7K 2 3 TV_COMPS <13,18> 1 C747 @ 270P_0402_25V8K C748 @ 330P_0402_50V7K 2 3 R594 0_0603_5% 2 1 TV_LUMA_R 1 2 TV_LUMA <13,18> 1 C749 @ 270P_0402_25V8K C750 @ 330P_0402_50V7K 2 R595 0_0603_5% 2 1 TV_CRMA_R 1 2 TV_CRMA <13,18> 1 C751 @ 270P_0402_25V8K C752 @ 330P_0402_50V7K 2 4 4 Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date A B C Title DOCK CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 E 40 of 53 C D E F G H +5VALW +5VALW 1 B 1 A I +5VALW to +5V Transfer +5VALW SUSP 1 SI4800DY_SO8 47 C640 10U_0805_10V4Z C641 2 G 28,37,38,39 SUSP# R437 2 SYSON# SYSON# D S 1 @ C732 0.1U_0402_16V4Z 2 1 @ C733 0.1U_0402_16V4Z 2 1 @ C734 0.1U_0402_16V4Z 2 D 2 G 28,37,38,46 SYSON Q25 2N7002_SOT23 +1.8VS S +3VALW Q26 2N7002_SOT23 +3VS +3VS 470_0402_5% 2 2 2 1 47K_0402_5% 1 SUSP 10K_0402_5% 3 6,47 1 1 2 3 4 S S S G 3 2 R438 100K_0402_5% 0.1U_0402_16V4Z D D D D 1 8 7 6 5 1 1 C639 10U_0805_10V4Z +3VALW 1 R436 2 +5V U38 B+ +5VALW R435 2 1 J 3 SYSON# 2 G 1 SUSON 1 D D +5VALW C642 0.01U_0402_16V7K 2 S S 1 3 1 2 + Q28 2N7002_SOT23 2 2 SYSON# G Q27 2N7002_SOT23 @ C703 100U_C_4VM 2 FM1 FM2 1 +5VALW to +5VS Transfer FM3 1 1 FM4 FM5 1 1 FM6 1 3 3 +3VALW to +3VS Transfer +5VALW CF1 +5VS CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 +3VALW 1 +1.8VALW R442 2 10_0805_5% D D D D 1 1 1 1 1 1 1 1 1 1 1 1 4 H11 HOLEA 0.1U_0402_16V4Z S S S G 1 1 C654 C655 H19 HOLEA 2 SI4800DY_SO8 10U_0805_10V4Z 2 470_0402_5% 2 SUSP G Q33 2N7002_SOT23 R444 2 1 RU NON H27 HOLEA 1 H28 HOLEA 1 C656 0.01U_0402_16V7K 3 S 22K_0402_5% 2 H23 HOLEA 7 H33 HOLEA H25 HOLEA 6 H26 HOLEA H29 HOLEA H30 HOLEA H31 HOLEA H32 HOLEA 1 D 2 SUSP G Q32 2N7002_SOT23 1 H22 HOLEA 1 1 3 S H20 HOLEA R443 D 7 H34 HOLEA 1 1 1 1 +2.5V R445 R446 1 2 470_0402_5% 1 2 470_0402_5% D 2 SYSON# G Q35 2N7002_SOT23 3 S 2 SYSON# G S Compal Secret Data Security Classification 3 D 8 Issued Date 2005/03/01 Deciphered Date 8 2005/04/06 Title DC/DC Interface & Hole THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A H10 HOLEA 5 1 2 RU NON Q34 2N7002_SOT23 H9 HOLEA 1 C652 1 6 +1.25V H8 HOLEA H17 HOLEA 1 C651 10U_0805_10V4Z C653 10U_0805_10V4Z H16 HOLEA 1 2 1 1 2 3 4 2 SI4800DY_SO8 1 8 7 6 5 1 S S S G H7 HOLEA 2 2 D D D D 1 1 C650 10U_0805_10V4Z H6 HOLEA +1.8VS U42 07/11 change H15 HOLEA 1 0.1U_0402_16V4Z 1 +2.5VS 1 2 3 4 H5 HOLEA 1 1 H14 HOLEA +1.8VALW to +1.8VS Transfer +2.5V to +2.5VS Transfer U41 H4 HOLEA H13 HOLEA 1 H12 HOLEA 5 8 7 6 5 H3 HOLEA 2 2 +2.5V H2 HOLEA 1 S @ C704 100U_C_4VM H1 HOLEA 1 + @ C705 100U_C_4VM 1 1 1 2 SUSP G @Q29 2N7002_SOT23 1 1 + D RU NON 2 SUSP G Q30 2N7002_SOT23 1 S 1 2 @ R440 470_0402_5% 1 C649 0.01U_0402_16V7K CF10 CF11 CF12 C648 3 S 2 3 D D +5VALW 10U_0805_10V4Z 1 2 1 C647 1 1 SI4800DY_SO8 1 1 2 3 4 1 3 S S S G +3VALW 1 RU NON 1 SUSP 2 G Q31 2N7002_SOT23 2 470_0402_5% D D D D 2 2 1 4 2 8 7 6 5 1 C646 10U_0805_10V4Z R439 1 2 C645 1 SI4800DY_SO8 R441 100K_0402_5% 1 C644 10U_0805_10V4Z 1 1 1 S S S G 1 2 D D D D 1 1 1 0.1U_0402_16V4Z U40 1 C643 10U_0805_10V4Z B+ +3VS 0.1U_0402_16V4Z 1 2 3 4 2 U39 8 7 6 5 B C D E F G H Size Document Number Custom Date: I R ev 0.8 LA-2771 Tuesday, August 30, 2005 Sheet of 41 J 53 5 4 3 2 1 +3VALW 2 +3VALW C657 0.1U_0402_16V4Z +3VALW +3VALW D D C658 0.1U_0402_16V4Z 2 R450 10K_0402_5% U43B SN74LVC14APWLE_TSSOP14 I 1 C659 0.47U_0603_16V7K 2 14 P 14 5 O 6 9 U43C SN74LVC14APWLE_TSSOP14 I O G U43A SN74LVC14APWLE_TSSOP14 P R448 200K_0402_5% 1 2 4 O 7 I G 14 3 7 7 1 2 G O G I 7 1 P P R447 470K_0402_5% 1 2 VLDT_EN VLDT_EN 1 37,38 14 1 8 R449 10_0402_5% 1 2 SB_PWRGD 20 U43D SN74LVC14APWLE_TSSOP14 2 NB_PWRGD 13 note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms, SUSP# goes to low after SB_PWRGD goes to low for power down. 14 +3VALW T1 P 11 I O G VLDT_EN 7 C 10 VLDT_EN# VLDT_EN# 47 VLDT_EN U43E SN74LVC14APWLE_TSSOP14 C NB_PWRGD SB_PWRGD T2 SUSP# +1.8VS B B B 14 9 O 6 10 A P U35B P A B G 5 U35C O SN74LVC32APWLE_TSSOP14 7 O 4 8 +3VL G I U44C 7 9 OE# 10 14 +3VL 8 SN74LVC32APWLE_TSSOP14 SN74LVC125APWLE_TSSOP14 SN74LVC125APWLE_TSSOP14 13 B 14 U35D P A O 11 13 I O G 11 +3VALW SN74LVC32APWLE_TSSOP14 7 14 12 O P U44D G I 7 12 OE# 13 +3VL 12 U43F SN74LVC14APWLE_TSSOP14 A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title P_OK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 42 of 53 5 4 3 2 1 VIN Detector 2 1 3 PD29 @ SBM1040-13_POWERMITE3 DOCK_VIN 1 ADPIN D D VIN 2 PR2 82.5K_0603_0.1% 2 2 B+ PR8 1K_1206_5% VIN 8 N40 3 + P N35 2 - 1 PACIN 1 O 4 PU1A LM393M_SO8 PZD1 RLZ4.3B_LL34 8/29 Change to 0.022uF for AC Off issue PR9 10K_0603_5% 1 2 ACIN <37,38,45> PACIN <44> PR7 10K_0603_5% 2 PC7 1000P_0402_50V7K PR4 1K_0603_5% 2 1 1 1 PR6 19.6K_0603_0.1% 2 1 1 1 1 2 PCN1 2 PC6 0.022U_0603_25V7K N41 PR5 22K_0603_1% 2 G 2 PJP21 @ JUMP_43X118 PR3 10K_0805_5% 2 1 2 1 PC5 1 1 PC4 1000P_0402_50V7K 2 1 PC3 100P_0402_50V8J 2 1 1 2 1 3 2 PC2 1000P_0402_50V7K 4 PC1 100P_0402_50V8J VS 1 VIN 0.01U_0603_50V7K 1 3 PD1 @ SBM1040-13_POWERMITE3 2 2 N50 2 PR1 1M_0603_0.5% 1 2 1 1 2 2 ADPIN 2 Vin Detector : Boxster 14.352 13.950 13.555 13.818 13.411 13.000 PJP20 @ JUMP_43X118 PL1 FBM-L18-453215-900LMA90T_1812 ACES_88290-0400M 1 Vin Detector : Cayenne 18.234 17.841 17.449 17.597 17.210 16.813 RTCVREF 3.3V PD2 C 1 1 PR10 1K_1206_5% 2 PR11 47_1206_5% 1 VL B+ 2 1 1 Precharge detector 14.805 14.333 13.872 13.355 12.933 12.465 1 1 B PR22 1.5M_0603_1% 2 PR21 200K_0603_1% PC12 1000P_0402_50V7K 2 N38 1 N30 N31 D VL 2 PR24 10K_0603_5% 1 ACIN : Boxster 2N32 G 2 1 PC11 4.7U_0805_6.3V6K PC10 1U_0805_50V4Z PU1B LM393M_SO8 5 6 2 2 GND - 2 1 ACIN : Cayenne N36 + O 1 2 PC13 0.1U_0603_25V7K IN 7 S PQ2 2N7002_SOT23 3 1 OUT 1 PR20 @ 200_0603_5% 3 1 2 2 PR19 @ 200_0603_5% 1 2 3.3V N39 N29 1 3 PR17 200_0603_5% PU2 G920AT24U_SOT89 8 2 <44> ACON <45,49> MAINPWON 2 PR18 280K_0603_1% PD5 RB715F_SOT323 RTCVREF 2 PR16 1M_0402_1% 1 1 2 N33 B 1 2 VS PR14 22K_0603_5% CHGRTC PR15 10K_0603_5% 2 PC14 1000P_0603_50V7K 2 1 PR183 47_1206_5% 2 2 1 N621 PC8 0.22U_1206_25V7K 2 2 PR12 1K_1206_5% VS 2 1 <35> EC_PWR_ON# Cayenne : PR5=22K; PR6=19.6K Boxster : PR5=47K; PR6=27K PD4 1N4148_SOD80 PQ1 TP0610K_SOT23 1 PR13 100K_0603_1% 1N4148_SOD80 P 1 C 1 G 3 2 4 CHGRTCP 1 2 PJP24 @ JUMP_43X39 2 2 1 1 PD3 1N4148_SOD80 1 BATT+ 1 N37 N34 PC9 0.1U_0603_25V7K 2 2 1 PACIN PR23 1M_0402_1% +5VALWP 2 +5VALW PJP3 @ JUMP_43X118 1 1 2 2 +3VALWP PJP5 @ JUMP_43X118 1 1 2 2 +2.5VP PJP7 @ JUMP_43X118 1 1 2 2 A PJP9 @ JUMP_43X118 1 1 2 2 +3VALW +2.5V PJP2 @ JUMP_43X118 1 1 2 2 +1.8VALW +1.5VSP PJP4 @ JUMP_43X118 1 1 2 2 +1.5VS +1.25VP PJP6 @ JUMP_43X118 1 1 2 2 +1.25V +1.2V_HTP PJP8 @ JUMP_43X118 1 1 2 2 +1.8VALWP PJP10 @ JUMP_43X118 1 1 2 2 Precharge detector 12.384 12.000 11.624 10.927 10.600 10.223 PQ3 DTC115EUA_SC70 3 +5VALWP PJP1 @ JUMP_43X118 1 1 2 2 BATT Detector 7.558 7.333 6.108 5.933 7.112 5.704 Cayenne : PR21=200K Boxster : PR21=300K +1.2V_HT Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date 4 3 Title DCIN / Precharge THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 A 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 43 of 53 5 4 1 <40> V_Bat 3 2 1 Charger B+ 2 PD30 SKS30-04AT_TSMA Iadp=0~3.0A 4 Cayenne : PR34=2.74k Boxster : PR34=4.7K GND 23 1 2 1 2 PR29 0_0402_5% 2 3887FB25 0.01U_0603_50V7K 2.74K_0402_1% 3887VREF 6 3887VCC(O) FB2 OUT 20 3887OUT VH 19 PC23 3887VH 1 2 VREF 5.0V FB1 VCC ACOFF# 2 PQ6 AO4407_SO8 PC20 0.1U_0603_25V7K 4 2 0.1U_0603_25V7K 1 2 N151 2 3887FB17 PR37 1K_0603_1% PC25 3887-INE1 1500P_0603_50V7K 8 1 2 21 18 -INE1 RT +INE1 -INE3 17 3887RT 1 2 68K_0603_5% 16 3887-INE3 2 IREF=1.096*Icharge IREF=0.548~3.288V 1 PR43 2 2 100K_0603_1% PC31 0.1U_0402_16V7K 1 174K_0603_1% CTL -INC1 +INC1 2 B C 14 13 3887+INC1 PD9 @ SKS30-04AT_TSMA 1 BATT+ PD10 SKS30-04AT_TSMA MB3887_SSOP24 Battery OVP voltage : 4S2P : 18V--> BATT_OVP= 2.0V (BAT_OVP=0.1112*VMB) <37,38> PR39 0.02_2512_1% 1 OUTD 15 2 3887-INC112 FB3 2 3887OUTD11 1 PR42 OUTC1 1 3887OUTC1 10 PC27 3887FB3 1 2 N141 2 47K_0603_1% 1500P_0603_50V7K ACON N49 PL2 15U_PLFC1045P-150A_3.7A_20% 1 2 2 PR41 IREF ACOFF PQ7 DTC115EUA_SC70 PC26 0.1U_0603_25V7K 1 2 PR38 3887+INE1 9 2 1 PR40 10K_0603_1% 1 -INE2 VCC(o) 4.2V 1 2 PR44 49.9K_0603_0.1% PC30 4.7U_1206_25V6K 2 1 PC21 PR34 2 N161 22 PC29 4.7U_1206_25V6K 2 1 1 CS PC19 2200P_0402_50V7K 1 2 3 2 1 3887-INE2 4 PR30 10K_0603_5% 3887CS 3 2 1 ACON <37,38> VIN 1 OUTC2 24 PC28 4.7U_1206_25V6K 2 1 PR36 3K_0603_5% <43> 2 +INC2 5 6 7 8 S PR33 31.6K_0603_1% 1 2 3 <43>PACIN 1 2 2 G PC24 0.1U_0402_16V7K D 2 1 PR35 11K_0402_1% 1 PD8 1SS355_SOD323 PC22 0.1U_0402_16V7K 2 1 2 N1 2 1 PACIN -INC2 3887+INE2 3 +INE2 PQ8 2N7002_SOT23 C ACOFF# 1 1 1 1 PR31 10K_0402_1% 3 1 3 PQ42 2N7002_SOT23 S 2 47K_0603_5% N12 PR32 150K_0402_1% 1 PU3 2 D 2 G PR28 ADP_I 2 PQ41 DTC115EUA_SC70 D IS 2 <37> 1 1 47K PR27 200K_0402_5% PC18 2200P_0402_50V7K 1 47K 2 PC156 0.1U_0603_25V7K 2 1 3 PQ40 DTA144EUA_SC70 2 2 2 PR188 47K_0402_5% PQ5 AO4407_SO8 D PC17 0.1U_0603_25V7K 1 0.02_2512_1% 1 2 2 PR25 8 7 6 5 2 1 PJP12 @ JUMP_43X118 1 1 2 2 PC16 4.7U_1206_25V6K 1 2 3 4 1 2 3 P3 4 8 7 6 5 PQ4 AO4407_SO8 1 VIN PR26 15K_0603_5% 8 7 6 5 B++ PQ39 AO4407_SO8 D 1 1 2 3 P2 2 PD31 SKS30-04AT_TSMA PC15 4.7U_1206_25V6K 1 1 PR45 150K_0603_0.1% B CC=0.4~3.0A BATT_Charge Voltage Select 4S2P CV=16.8V PR44 = 49.9K_0603_0.1% 3S2P/3S3P CV=12.6V PR44 = 150K_0603_0.1% 3S2P/3S3P : 13.5V--> BATT_OVP= 2.0V (BAT_OVP=0.14753 *BATT+) VS PR45=150K_0603_0.1% PR45=300K_0603_0.1% BATT++ 1 2 2 2 PR52 10K_0603_5% 1 D S PQ10 2 G 2N7002_SOT23 <37,38> FSTCHG 2 PQ11 DTC115EUA_SC70 PR53 10.2K_0603_1% A 3 1 PC33 0.01U_0402_25V7Z N11 VIN PR51 (17V+-5%) 42.2K_0603_1% 2 4 N21 1 RTCVREF 1 2 A N20 2 PZD2 RLZ4.3B_LL34 PR54 105K_0603_0.5% 2 6 2 3 - 1 0 - 3 1 0 G PQ9 DTC115EUA_SC70 N13 + 47K_0603_5% PR49 10K_0603_5% 2 1 N19 3 2 P PR50 4.22K_0603_1% 2 1 N181 8 1 1 PU4A LM358ADR_SO8 PR48 499K_0603_1% 1 5 N17 2 <37,38> BATT_OVP + 3887CS PR47 1 7 3887CS 1 PU4B LM358ADR_SO8 +3VALWP VS PR46 340K_0603_1% 2 0.01U_0402_25V7Z 2 PC32 1 1 <37,38> AIR_ACIN PR55 0_0603_5% Compal Secret Data Security Classification 2 BATT_OVP Select 4S2P PR55 = 0_0603_5% 3S2P/3S3P PR55 = 40.2K_0603_1% Issued Date 2005/03/01 2006/03/01 Deciphered Date 5 4 3 Title Charger THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 44 of 53 5 4 3 2 1 +3VALWP/+5VALWP D D PC136 0.1U_0603_25V7K 2 1 BST5B 1999_B++ PC137 0.1U_0603_25V7K 2 1 BST3B 3 PJP23 @ JUMP_43X118 2 2 2 1 1 B+ PD26 CHP202U_SC70 1 2 S 1 7 2 FB3 2 1 1 2 2 1 1 PR170 0_0402_5% PL12 10UH_D104C-919AS-100M_4.5A_20% 2 BST3A D H3 DL3 LX3 N61 +3VALWP 2 @ PR178 0_0402_5% 2 PR184 0_0805_5% + PC155 220U_6.3VM_R15 1 2 PC152 4.7U_0805_6.3V6K 2 1 LDO3 LDO3P 1 1 PR177 @ 3.57K_0402_1% MAX8734AEEI+_QSOP28 PR179 0_0402_5% 2 N601 PD27 SKUL30-02AT_SMA 2 B PC153 0.047U_0603_16V7K PQ37 2N7002_SOT23 ACIN S PQ38 2N7002_SOT23 1 D D 3 2 G S 2 G A PQ36 2N7002_SOT23 Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date 4 3 Title +3VALWP/+5VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 C SI4914DY-T1-E3 SO8 3HG PR172 PR169 499K_0402_1% 200K_0402_1% 1 2 2 1 10 25 23 ILIM5 PC144 2200P_0402_50V7K 2 1 2 1 REF 11 28 26 24 27 22 PR171 PR168 499K_0402_1% 118K_0402_1% 2 17 13 20 FB3 PGOOD SKIP# 1 2 1 3 2 D ILIM3 8 7 6 5 1 PR187 100K_0402_5% PC146 1U_0603_10V6K 2 1PC148 0.1U_0603_25V7K 4.7U_1206_25V6K SHDN# ON5 ON3 0.22U_0603_16V7K PC151 2 1 1 2 N59 LDO3P 1 ILIM5 BST3 DH3 DL3 LX3 OUT3 1 PR182 0_0402_5% 2 1 MAINPWON 3 12 8 806K_0603_1% 2 G 6 4 3 LX5 DL5 OUT5 FB5 N.C. VL PC150 @ 1U_1206_25V7K 5 DH5 D1 G1 D1 S1/D2 G2 S1/D2 S2 S1/D2 1 ACIN <38,44> 2VREF_1999 PR181 EC_ON 1 PR175 10K_0402_5% 1 2 N57 ILIM3 PR167 0_0402_5% 2VREF_1999 1 2 3 4 PRO# PR174 47K_0402_5% 2 1 N56 VCC 15 19 21 9 1 P2 2 2 PR173 @ 10.2K_0402_1% 1 2 1 @ N58 2 LX5 DL5 BST5 V+ 16 TON 14 D H5 FB5 PR176 0_0402_5% 1 2 PD28 SKUL30-02AT_SMA PC154 220U_6.3VM_R15 B 2 BST5A LDO3 2 PU12 +5VALWP + PC145 2 1 1 2 3 4 PL11 10UH_D104C-919AS-100M_4.5A_20% GND S S S G 1 PQ34 SI4810BDY-T1-E3 SO8 PQ32 PC141 0.1U_0402_16V7K N63 18 1 2 3 4 D D D D 8 7 6 5 PR185 0_0805_5% 1 2 VL PC147 4.7U_0805_6.3V6K 2 1 LDO5 PR163 0_0402_5% 1 2 5HG LD05 S S S G 1 1 PR166 4.7_1206_5% PC143 4.7U_1206_25V6K 2 1 2 PR165 47_0402_5% 1 8 7 6 5 D D D D PQ33 SI4800BDY-T1-E3_SO8 C A 1999_B++ P2 PR164 0_0402_5% PC142 4.7U_1206_25V6K 2 1 PC140 2200P_0402_50V7K 2 1 PC139 4.7U_1206_25V6K 2 1 PC138 4.7U_1206_25V6K 2 1 VL 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 45 of 53 5 4 3 2 1 +1.8VALWP/+2.5VP D D B+ PJP15 @ JUMP_43X118 1 1 2 2 2 PR81 0_0603_5% +5VALWP 1 2 PC65 4.7U_1206_25V6K 1 2 5 6 7 8 PC64 4.7U_1206_25V6K 1 2 1 2 D D D D MAX8743_VCCB 1 2 MAX8743B_SKIP# 1 PR95 @ 0_0402_5% 2 PR98 0_0402_5% G S S S PR93 3.3K_0603_1% 2 1 2 PC132 220U_6.3VM_R15 1 2 PD18 @SKS10-04AT_TSMA 2 2 1 PR87 @ 15K_0402_1% 1 MAX8743B_ILIM2 MAX8743B_ILIM1 1.936V 1.365V 13 3 1 D D D D G S S S 4 3 2 1 SYSON <37,38,41> PC74 4.7U_0805_6.3V6K 4 3 2 1 5 6 7 8 VDDB PC68 9 UVP 22 B ILIM2 ILIM1 1 + 2 1 PR91 0_0402_5% OVP ON1 2 PR89 0_0402_5% 7 5 PC75 @ 100P_0402_50V8K 11 FB2.5 2.5ON PQ18 SI4810BDY-T1-E3 SO8 2 1.8ON 15 14 12 DH2.5A B 1 PR94 69.8K_0603_1% 1 2 PR90 0_0402_5% PR88 0_0402_5% D H2.5 1 2 LX2.5 DL2.5 19 18 17 20 16 PR96 150K_0603_1% PR97 100K_0603_1% 1 PGOOD TON 21 1 +3VALWP 2 8 1 PC76 @ 100P_0402_50V8K 2 1 2 PR92 0_0402_5% FB1.8 BST2 DH2 LX1 LX2 DL1 DL2 MAX8743EEI_QSOP28 CS2 CS1 OUT1 OUT2 FB2 FB1 ON2 C +2.5VP PL5 4.7UH_PLFC1045P-4R7A_5.5A_30% 1 2 1 2 28 1 2 2 27 24 VDD DH1 PC77 0.22U_0603_16V7K LX1.8 DL1.8 BST1 REF 26 PR84 0_0402_5% BST2.5 1 2 PC70 0.1U_0603_25V7K 10 25 D H1.8 1MAX8743B_REF BST1.8 VCC PU6 2 1 PC69 0.1U_0603_25V7K PR86 0_0402_5% DH1.8A 1 2 SKIP 1 PR83 0_0402_5% 2 6 2 2 PQ17 SI4800BDY-T1-E3_SO8 4 V+ 1U_0603_16V6K 2 1 2 PC66 4.7U_0805_6.3V6K MAX8743_VCCB GND 1 PR85 @ 0_0402_5% 2 1 2 PC72 4.7U_0805_6.3V6K 2 + PC131 220U_6.3VM_R15 1 1 PL4 5U_TPRH6D38-5R0M-N_2.9A_20% PR82 20_0603_1% BST2.5A SI4914DY-T1-E3 SO8 +1.8VALWP PD17 @SKS10-04AT_TSMA 8 7 6 5 23 C D1 G1 D1 S1/D2 G2 S1/D2 S2 S1/D2 PC67 0.1U_0603_25V7K 2 1 1 2 3 4 2 3 BST1.8A PQ16 PC63 2200P_0402_50V7K MAX8743B_V+ 1 PC62 4.7U_1206_25V6K 2 PD16 CHP202U_SC70 1 1 1 1 PC61 4.7U_1206_25V6K 2 1 2 PC60 4.7U_1206_25V6K 1 2 PC59 2200P_0402_50V7K MAX8743_B++ A A Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date 5 4 3 Title +1.8VALWP/+2.5VP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 46 of 53 5 4 3 2 1 +1.2V_HTP/+1.5VSP/+1.25VP +2.5V +1.8VS 2 1 1 PJP17 @ JUMP_43X118 1 C 3 VREF NC 7 4 VOUT NC 8 TP 9 +3VALW 1 1 APL5331KAC-TR_SO8 1 1 S PQ20 2N7002_SOT23 2 G PR104 10K_0402_1% 2 2 PC87 @ 0.1U_0402_16V7K +1.5VSP PC83 0.1U_0402_16V7K 2 1 N9 D 3 SUSP PC86 10U_1206_6.3V7K 1 2 2 2 PC85 @ 0.1U_0402_16V7K PR103 0_0402_5% 1 2 +1.25VP PC82 0.1U_0402_16V7K PR102 3.3K_0603_1% 2 PQ19 2N7002_SOT23 5 VREF1.5 APL5331KAC-TR_SO8 1 S N4 2 G 1 1 SYSON# 1 <41> 3 VREF1.25 D 6 NC 1 9 PR99 2K_0402_1% VCNTL GND PC84 10U_1206_6.3V7K TP PC80 10U_1206_6.3V7K VIN 2 1 8 2 7 NC 1 NC VOUT 1 2 VREF 4 1 3 2 NC VIN1.5 +3VALW 2 GND 5 2 PR100 3.3K_0603_1% PR101 0_0402_5% 1 2 6 PC79 1U_0603_10V6K VCNTL 2 PC78 10U_1206_6.3V7K PU8 VIN 2 1 1 1 2 PU7 VIN1.25 PC81 1U_0603_10V6K PJP16 @ JUMP_43X118 1 2 2 D 2 D C PJP18 @ JUMP_43X39 UGATE1.2 1 FB1.2 PQ22 2N7002_SOT23 6 8 PHASE1.2 4 LGATE1.2 S PHASE 2 1 2 1 1UGATE1.21 PQ21 SI4800BDY-T1-E3_SO8 PR161 0_0402_5% FB PC89 22U_1206_6.3V6M 5 6 7 8 D D D D B 1 PL6 2.0UH_PLC-0735-2R0_5A_30% 2 5 6 7 8 PR108 0_0402_5% UGATE D 2 G PC95 @ 0.1U_0402_16V7K 3 GND LGATE + PQ24 SI4810BDY-T1-E3 SO8 4 3 2 1 G S S S APW7057KC-TRL_SOP8 +5VALW PC90 22U_1206_6.3V6M D D D D 1 N6 2 3 1 2 <42> VLDT_EN# 2 1 1 + 2 PR109 5.1K_0402_1% 1 2 +1.2V_HTP PC134 220U_6.3VM_R15 2 OCSET 2 PJP19 @ JUMP_43X118 PC133 220U_6.3VM_R15 BOOT1.2 G S S S 1 2 7 PD19 1N4148_SOD80 1 VCC OCSET1.2 BOOT 2 4 3 2 1 1 2 PU9 1 PR106 6.49K_0402_1% B PC88 1U_0603_6.3V6M 5 2 1 2 PC91 470P_0402_50V8J N5 2 PR105 @ 10_0603_5% 2 1 1 APW7057_VCC PC92 0.1U_0402_16V7K 1 1 2 2 +5VALW 1 2 PC96 0.1U_0402_16V7K 1 PR110 10K_0402_1% A A Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date 5 4 3 Title +1.2VSP/+1.5VP/+1.25VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 47 of 53 2 CPU_B+ PR111 10_0402_5% 2 1 +5VS 14 35 1544CCI 1 PC111 1544BSTS 33 1544DHS 34 1544LXS 39 1544CSN 13 1544GNDS 2 1 PC102 2200P_0402_50V7K 1 2 PC101 0.01U_0402_50V4Z 1 2 2 5 6 7 8 +5VS 1544BSTSA B PD22 1SS355_SOD323 CPU_B+ PQ28 FDS6294_SO8 21544DHMB4 1 PR142 0_0402_5% 2 5 6 7 8 4 2 2 PR143 @10_0402_5% 1 PR159 0_0402_5% 1 N55 4 B PL9 .56UH_MPC1040LR56_ 23A_20% 1 2 N48 PC121 680P_0603_50V8J PR145 820_0402_5% 1 2 PC120 0.47U_0603_16V7K <6> 2 3 2 1 Near CPU GND CPU_COREFB# CPU_COREFB GNDS 1544CSP 2 CSN GND 1544DLS 1 SKIP 32 40 2 1 PC118 0.01U_0402_50V4Z CSP PD23 11 DLS SUS @ 2 1.82K_0402_1% SKS30-04AT_TSMA 18 OFS PR135 1 2 1 PC117 4.7U_1206_25V6K N26 LXS 820_0402_5% 2 1 3 DHS ILIM 1 2 7 1544SUS REF PR133 2 470P_0402_50V8J 2 1 PC116 4.7U_1206_25V6K 1544OFS BSTS PC114 1000P_0402_50V7K 1 2 1544REF 2 1 PR140 0_0402_5% 9 CCI TON PR144 4.7_1206_5% 8 CCV 1 1544REF 1 2 PC112 0.22U_0603_16V7K 1544ILIM 2 1 12 PQ30 FDS6676AS_SO8 1 PR137 121K_0402_1% 2 PR139 80.6K_0402_1% 1 2 1544REF1 PC113 100P_0402_50V8J PR136 2 71.5K_0402_1% 2 1 1 PC110 270P_0402_50V7K 1544TON 2 1 PC115 2200P_0402_50V7K 1 2 PR134 200K_0402_1% PC107 0.47U_0603_16V7K <6> 1544FB C 1 PR130 0_0402_5% 1544OAIN- 15 N3 2 16 FB PC108 680P_0603_50V8J 2 1000P_0402_50V7K OAIN- TIME 1 SHDN# 1 1 6 3 2 1 PR131 @ 100K_0402_5% 1544TIME PR132 1 60.4K_0603_1% 1544CCV 2 5 6 7 8 2 PQ29 FDS6676AS_SO8 2 5 6 7 8 1 1 3 2 1 1544SHDN# 2 PR128 0_0402_5% N47 2 1 4 2 OAIN+ 4 PQ27 FDS6676AS_SO8 S1 1544OAIN+ 3 2 1 1544CMN 17 5 PQ26 FDS6676AS_SO8 1544CMP 38 3 2 1 37 1 VROK 2 25 PR121 @10_0402_5% CPU VCC SENSE PC109 1 2 1544VROK PR119 0.001_2512_5% PR129 1.82K_0402_1% 1 2 31 1 PGND 2 2 1544DLM OVP 1 PR127 499_0402_1% 29 19 N25 PR126 499_0402_1% DLM 2 1 D4 1 20 1544OVP 2 D4 +CPU_CORE 1 PR124 820_0402_5% LXM 1544LXM PL8 1 D3 27 CMP + 2 .56UH_MPC1040LR56_ 23A_20% 2 21 PR117 0_0402_5% 2 1544DHMA 1 PD21 SKS30-04AT_TSMA D3 2 PR123 4.7_1206_5% 1544DHM 2.2_0402_5% CMN + 2 4 5 6 7 8 1544BSTM 1 PR115 28 MAX1544ETL 1 5 6 7 8 26 DHM S0 D 1 3 2 1 BSTM D2 4 VR_ON 1 D1 22 2 23 D2 PU10 PC106 0.22U_0603_16V7K D1 C 38> 1 PC105 36 PD20 1SS355_SOD323 1 VGATE 30 V+ 2 VID4 2 PQ25 FDS6294_SO8 2 2.2_0402_5% VID3 <6> VDD D0 PR138 1 <6> VCC 24 PC119 2 1 VID2 10 D0 0.22U_0603_16V7K VID1 <6> 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 2 0_0402_5% 0.01U_0402_50V4Z <6> 2 PR113 2 PR114 2 PR116 2 PR118 2 PR120 1544VCC 2 PR122 1 PR125 +5VS 1544BSTMA 1 2 1 PR141 100_0402_5% VID0 2 2 1544VCC <6> PC100 4.7U_1206_25V6K 1 2 2 1 PC103 2.2U_0603_6.3V6K PC104 1U_0603_10V6K B+ PL7 FBM-L18-453215-900LMA90T_1812 1 1 PR112 2 10K_0402_5% 1 D PC99 4.7U_1206_25V6K +3VS 1 PC135 68U_25V_M 3 PC98 68U_25V_M 4 2 5 1 2 PC122 1 1544OAIN+ 2 PR146 820_0402_5% @ 1000P_0402_50V7K PC123 1544OAIN+ 1 A A 2 @ 1000P_0402_50V7K Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date 5 4 3 Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 48 of 53 5 4 3 2 1 D D Battery Connect/OTP BATT+ BATT+ BATT++ 1 BATT+ 1 SMD 2 SMD 1 SMC 3 SMC 1 RES 4 8 G Temp 5 7 G GND 6 PR150 100_0402_5% 2 1 PCN2 SUYIN_200045MR006G110ZR PC124 0.01U_0402_25V7Z EC_SMD_1 <37,38,39> 2 PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C EC_SMC_1 <37,38,39> PR151 100_0402_5% 1 TS 2 2 PC125 1000P_0402_50V7K CPU 2 BATT_TEMP BATT_TEMP <37,38> C PR147 1K_0402_5% 2 C 1 1 2 PL10 FBM-L18-453215-900LMA90T_1812 PR162 @ 0_0402_5% 1 2 +3VALWP PR149 6.49K_0402_1% VL PH1 100K_0603_1%_TH11-4H104FT PR152 470K_0402_1% 1 2 1 N28 PR153 470K_0402_1% PU11A O - 1 + D 3 8 2 S P 3 OTPREF N22 1 PQ31 2N7002_SOT23 2 G B LM393M_SO8 1 PC128 1000P_0402_50V7K VS - PU11B O 4 6 + P 5 G 8 2 2 PR158 470K_0402_1% 2 PR157 20K_0603_1% 2 PC127 0.22U_0603_16V7K 1 1 1 VL N10 1 2 PR156 470K_0402_1% G B 4 2 PR155 215K_0603_1% 1 2 2 PR154 0_0402_5% N27 <43,46> VL 1 2 2 1 S M A RT Battery: 1 . B ATT+ 2.SMBD 3 . S M BC 4 . R es 5 . T e mp 6 . G ND MAINPWON 1 PJPB1 battery connector PC126 0.1U_0603_25V7K VS 7 LM393M_SO8 A A Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date 5 4 3 Title BATTERY CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom LA-2771 Date: R ev 0.8 Sheet Tuesday, August 30, 2005 1 49 of 53 5 4 3 Version change list (P.I.R. List) Item D 1 Reason for change Add the functionality to turn on the system on from Off and S4 with the consumer IR. C Power section 45 Change 3/5VALWP regulator from MAX1902 to MAX1999 2005.04.08 Change PCN1 from SP02000AO00 to DC040001P00. 2005.04.08 49 3 Because EMI test fail 48 cause precharge can't finisn. Page 1 of 1 Modify List Change PCN1 from SP020022200 to SP020024800. Because V_bat to Calgary havn a leakage current, 1 PG# 2 4 2 Date B.Ver# D Change CPU_CORE HI-SIDE MOS from AO4408 to FDS6294, LOW-SIDE from AO4410 to FDS6676AS 2005.05.18 44 Add PD30 and PD31 to supply the V_bat power. 2005.06.09 5 Add air-adapter detector 44 Add PU4 to detector air-adapter in. 2005.07.02 6 Adjust the MB3887 CC to CP response cause the adapter OCP. 44 Change the PR31 from 100k_0402_1% to 10k_0402_1% 2005.07.29 C Change the PR34 from 10k_0402_1% to 2.74k_0402_1% Change the PC21 from 4700p_0603_50V to 0.01u_0603_50v B B A A Compal Electronics, Inc. Title PWR PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 0.8 B Date: Tuesday, August 30, 2005 Sheet 1 50 of 53 5 I tem 4 Fixed Iss ue Rea son for change 2 PA GE 1 Mod ify List M. B. V er. 0 .2 H P Jac k + SPDIF change type 3 1 , 33 Support CI R wake up from battery mode 4 , 37 , 38 , 41 , 35 for Marvell express card Rest timing 2 0 , 28 for s o me HDD's LED alway on 24 Del: D29 , R259 , Q10 0 .2 5 for card bus can't work 27 S1_ V CC and S1_ V PP c ha nge to +S1_VCC and +S1_VPP 0 .2 6 For nissan common design 35 JP28 an d JP29 pin swap 0 .2 For keyboard issue 37 Del: D 27 1 w ak e u p fr om LAN 38 A dd: R575(Pu ll UP PME_EC#) 0 .3 2 For V O L_UP,DOWN function issue 38 P O P: R418, R419, R420, R421 0 .3 <2005.05.3> 1 For CI R wake up 38 A dd: R576 , R577 to option 0 .3 <2005.05.4> 1 E C 910L include portion circuit 39 A dd: R578 , Del: C630 , R422 , Q22 , U35A 0 .3 2 ME c hange LED type 36 D18, D20,D21 from right angle change to vertical type 0 .3 <2005.05.6> 1 Add wireless LED c urrent limit resister 17 Add: R581 current limit resister 0 .3 <2005.05.9> 1 TP conn pin reverse 35 Pin swap <2005.05.10> 1 ME c hange LED type 36 D25 from right angle change to vertical type 2 HP requirement from 75 ohm change to 33 ohm 33 R567 , R569 from 75 ohm c h ange to 33 ohm 3 For nissan common design 35 A dd: R582 , R583 1 For 2 w ay and 4 way touch pad 36 A dd: R584 , R585 <2005.04.18> 1 3 2 3 D 4 C B <2005.05.11> 12V A LW change to B+ +3V A LW c hange to LDO3 , +5VALW change to LDO5 0 .2 A dd: Q 55 D 0 .2 0 .2 7 <2005.04.27> Del : U 27 , C563 , C564 A dd: Q 52 , Q 53 , Q 54 , Q 56 , Q 57 , R571 , C730 , C731 , R567 , R569 , R568 , R570 B 0 .4 update JP23 dual USB connector to reverse type <2005.06.10> C DFX modific atio n for Rev0.4 MB C h a n g e M R 9 5 4 , M C 9 2 8 , M R 9 2 4 , M R 9 22, MR932, MC944, MC970, MC976, MC978, MC926 to c orrec t pad size with Compal layout rule update USB connector to reverse type Change D6 form RB411 to RB491 A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title HW PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 51 of 53 5 I tem <2005.06.27> 1 <2005.07.04> 1 Fixed Iss ue <2005.07.11> Mod ify List M. B. V er. 0 .5 For +1.8VS EMI 11 Change R61, R84 value from 0 ohm to 120 ohm For +1.2V_HT power ripple 14 For +2.5VS EMI 15 Add C737, C738, C741, C742 220P 50V8J 0402 4 For +2.5VS EMI 15 Add C739, C740, C743, C744 1000P 50V7K 0402 5 For Mini-PCI_CLK EMI 30 Mount R325 and C512 For CardBus chip PCI_CLK EMI 25 For LAN chip PCI_CLK EMI 29 Mount R322 and C504 8 For EC K/B chip PCI_CLK EMI 30 Mount R415 and C628 1 For USB EMI 34 Add L33, L34 2 For USB EMI 34 change R561,R559,R562,R560 size from 0603 to 0402 1 For dock Docking audio noise 31 Add Q58, R589, Q60, R590, Q59, R589 2 For Dock_LOUTR/L EMI 40 Add R591, C745, R592, C746 3 For Docking TV_out signals EMI 40 Add R593, C747, R594, C748,C749, C750, R595, C751, C752 1 For accelerate +2.5VS discharge speed 40 change R442 size and value from 470_0402 to 10_0805 2 For LAN lamp 29 Swap Activity and Link Lamp 7 <2005.07.07> PA GE 1 Add Q61 6 <2005.07.05> Rea son for change 2 41 3 C 3 For clear H_RST# glitch 2 D 4 0 .5 D Change C197, C209, C254, C248, C251, C256, C258 value 0 .5 from 0.1U 16V4Z 0402 to 1U 6.3V4Z 0402 mount 0 .5 0 .5 R279 and C442 0 .5 0 .5 C B B <2005.07.25> 1 For SanDisk SD 256M card could not work issue 25 For SanDisk SD 256M card could not work issue 25 Delete R463, R465, R466, R476, R268 For SanDisk SD 256M card could not work issue 26 Delete R270, R267, R547, R548 For SanDisk SD 256M card could not work issue 26 Mount R550 and R549 1 For lower power consumption 38 Add and un-mount R596 2 For CRT Assy 18 change CRT footprint 2 3 4 <2005.07.28> delete U48 Quick switch reserve schematics A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title HW PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 52 of 53 5 I tem <2005.08.11> 4 Fixed Iss ue 3 2 Rea son for change PA GE 1 Delect all reserve 0 ohm resistors. 41 Delete R24, R125, R21 , R73 , R263, R565 0 .5 2 For EMI solution on switch connector 11 Add C753~C771 total 19 pcs 0 .5 3 For ATI suggestion on RS480 14 4 Relocate damping resistor to solve Sandisk issue 26 Relocate R266, R458, R459, R460, R461, R462 0 .8 5 Change from AGND to DGND for Codec precision improvement 31 Change Q16/Q17 pin3 and R334 pin2 to DGND 0 .8 6 Add +3VALW power rail for Boxster lid switch use 35 Add +3VALW to JP28 pin25 0 .8 7 Reserve C700, for soft start if necessary Reserve C700 0 .8 8 Reserve R600 M_SEN#, currently this signal isn't used Reserve R600 0 .8 D <2005.08.23> 1 Mod ify List M. B. V er. D Change C200, C202, C242, C232 0 .5 from 0.1U 16V4Z 0402 to 1U 6.3V4K 0402 31 38 C C 1 2 1 2 3 1 2 B B 1 2 3 4 1 2 A A Compal Secret Data Security Classification 2005/03/01 Issued Date 2005/04/06 Deciphered Date 5 4 3 Title HW PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Size Document Number Custom Date: R ev 0.8 LA-2771 Sheet Tuesday, August 30, 2005 1 53 of 53 www.s-manuals.com
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