Compal LA 2821 Schematics. Www.s Manuals.com. 2821p R0.5 Schematics

User Manual: Motherboard Compal LA-2821 AngelFire 3.0 - Schematics. Free.

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A

B

C

D

E

1

1

Compal confidential

2

2

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic
2005-11-24
3

3

REV:0.5

4

4

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Sheet
Rev
0.5

LA-2821P

Date:

A

B

C

D

Friday, November 25, 2005

Sheet
E

1

of

52

A

B

C

Compal confidential

D

E

AngelFire 3.0

File Name : LA-2821P

1

Accelerometer
LIS3LV02DQ

1

Fan Control
page 4

Mobile Yonah
uFCPGA-478 CPU

page 27

Thermal Sensor
ADM1032AR

page 4,5,6

Clock Generator
ICS954306

page 4

Accelerometer
LIS3LV02DQ

page 15

page 27

FSB
H_A#(3..31)

MXM III connector

533/667MHz

H_D#(0..63)

DDR2 -400/533/667

PCI-E x 16

Intel Calistoga MCH
945PM

page 18

CRT / TV-OUT

USB conn x2
(Docking)

PCBGA 1466

page 7,8,9,10,11,12

LCD CONN

USB2.0

USB conn x2

DMI

page 17

BT Conn

PCI-E BUS

AC-LINK/Azalia

Intel ICH7-M
Mini-Card

TI PCI7612

page 27

page 25,26

page 20

page 26

Slot 0/Smart Card

page 23

New Card USBx1

page 30

page 24

MDC1.5

page 29

page 34

AD1981HD

AMP & Audio Jack
MAX9710ETPpage

page 28

SPI

page 24

SPI ROM
SST25LF080A
page 23

6in1 Slot
page 23

page 20

PATA Slave

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

PATA ODD Connector
page 20

page 37

4

Security Module

SMSC Super I/O
LPC47N217
page 31

SMSC KBC 1021

page 32

page 33

Touch Pad CONN.

DC/DC Interface CKT.

page 34

Int.KBD
page 34

COM1
( Docking )

page 35

3

Docking CONN.

LPC BUS

page 34

29

SATA HDD Connector

SATA Master

Power OK CKT.

Power On/Off CKT.

2

page 19,20,21,22

page 23,24

1394 port

RJ45/11 CONN

FingerPrinter AES2501
page 30
USBx1

30

Audio CKT

mBGA-652

CardBus Controller

3

RTC CKT.

page 35

page 30

USB conn x2
(Sub Board)

PCI BUS

page 32

page 13,14

USB2.0 HUB /
page
FP Conn

2

LED

BANK 0, 1, 2, 3

Dual Channel

page 16

10/100/1000 LAN
BCM5753M

DDR2-SO-DIMM X2

Flash ROM
SST49LF008A
page 32

LPT
( Docking )

page 34

page 35

4

page 36

TrackPoint CONN.

page 34
Compal Secret Data

Security Classification

Power Circuit DC/DC

2005/03/10

Issued Date

Page 38,39,40,41,42,43,44,45,46,47

2006/03/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Compal Electronics, Inc.

B

C

D

Block Diagram
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
E

2

of

52

5

4

3

2

Symbol Note :

Voltage Rails

D

Power Plane

Description

S0-S1

S3

VIN

Adapter power supply (18.5V)

N/A

N/A

N/A

AC or battery power rail for power circuit

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

1.05V power rail for Processor I/O and MCH/ICH core power ON

OFF

OFF

+0.9VS

: means Digital Ground

S5

B+
+VCCP

0.9V switched power rail for DDRII Vtt

ON

OFF

OFF

+1.5VS

1.5V switched power rail for PCI-E interface

ON

OFF

OFF

+1.8V

1.8V power rail for DDRII

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail for MCH video PLL

ON

OFF

OFF

+2.5VALW

3.3V always on power rail

ON

ON

ON*

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+RTC_VCC

RTC power

ON

ON

ON

: means Analog Ground

L

9/15

: Modified Area Mark(Compare with EAL60).

*
*
*

Bus

PCI Device ID

1
0
0
0
0
0
0
0
0
0
0
0
0

Azalia
PCI-E
USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F
DMA
PMU

IDSEL #

D8

AD24

D27

AD11

D28

AD12

D29

AD13

D30

AD14

D30

AD14

D30

AD14

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

*
*
*
*
*
*
*
*
*
*
*

External PCI Devices
DEVICE

PCI Device ID

Mini-PCI

D4

AD20

IDSEL #

REQ/GNT #
0

F

CARD BUS

D6

AD22

2

CDEG

: Modified Area Mark.
: C-BOM impact

Internal PCI Devices
DEVICE

Note: Layout Related Memo

: Question Area Mark.(Wait check)

C

LAN

D

: Layout Note related Area Mark.

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

B

1

PIRQ

*
*

@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function reserve.
C
FWH@ : means just build when FWH I/F BIOS function reserve.
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
TPM1.2@ : means just build when TPM1.2 function enable.
TPM@ : means just build when TPM function enable.
SC@ : means just build when SmartCard function enable.
SATA@ : means just build when SATA I/F HDD enable.
NOSATA@ : means just build when SATA I/F HDD disable.
NC@ : means just build when New Card function enable.
NONC@ : means just build when New Card function disable.
MDC1.5@ : means just build when MDC1.5 function enable.
7612@ : means just build when TI PCI7612 chip selected.
7611@ : means just build when TI PCI7611MLS chip selected.
250@ : means just build when SMsC LPC47N250 chip selected.
1021@ : means just build when SMsC KBC1021 chip selected.
1981HD@ : means just build when AD1981HD chip selected.
B
45@ : means need be mounted when 45 level assy or rework stage.
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.
NODP@ : means just build when No DP design Clock Gen. selected.
DP@ : means just build when DP design Clock Gen. selected.
LPNO@ : means just build when No LP design ICS Clock Gen. selected.
LP@ : means just build when LP design ICS Clock Gen. selected.
DB@ : means just build when Mini-PCI E Debug Card function enable.
* : means define for SMT build when this stage

I2C / SMBUS ADDRESSING

A

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

USB HUB

5C

01011100

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List
Rev
0.5

LA-2821P

Date:

5

4

3

2

Friday, November 25, 2005

Sheet
1

3

of

52

5

7

4

H_A#[3..31]

3

H_D#[0..63]

JP8A

2

1

+3VS

5/10

7
R443

7
7
7

H_LOCK#
H_RESET#

H_RS#[0..2]

7

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

B

21

XDP_DBRESET#
7 H_DBSY#
20 H_DPSLP#
20,45 H_DPRSTP#
7 H_DPWR#

45

H_PROCHOT#

+VCCP

1 R447
2
56_0402_5%
20
7

R27
R28

H_PWRGOOD
H_CPUSLP#

2 @ 1K_0402_5%
2 51_0402_5%

1
1

7,20

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2

AD4
AD3
AD1
AC4

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

HOST CLK

CONTROL

RS0#
RS1#
RS2#
TRDY#

C20
E1
B5
E5
D24
AC2
AC1
D21

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

MISC

1
0.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK
XDP_TCK

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

STPCLK#
SMI#

D5
A3

R523 1

2

56_0402_1%

XDP_TDO

R525 1

2

56_0402_5%

XDP_BPM#5

R526 1

2

56_0402_5%

XDP_TRST#

R521 1

2

56_0402_5%

XDP_TCK

R522 1

2

56_0402_5%

CLK_CPU_XDP
CLK_CPU_XDP#
+VCCP 1K_0402_1%
H_RESET#_R
1 R441
2 H_RESET#
XDP_DBRESET#_R 2 R444
1 XDP_DBRESET#
200_0402_1%
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
1 R191
2 0_0402_5%

LEGACY CPU

THERMAL
THERMDA DIODE
THERMDC
THERMTRIP#

H_STPCLK#
H_SMI#

D

CLK_CPU_XDP 15
CLK_CPU_XDP#
15

SAMTE_BSH-030-01-L-D-A
C

Thermal Sensor ADM1032AR-2
+3VS

2

C69
0.1U_0402_16V4Z

1

R24
U5

1
H_THERMDA

2

H_THERMDC

3

THERM#

4

VDD

C68

1

2

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

8

ICH_SMBCLK

7

ICH_SMBDATA

6

THERM_SCI#

10K_0402_5%

THERM_SCI#

7
7
7
7

+3VS

1

ADM1032AR-2_MSOP8

2

10K_0402_5%

H_DSTBN#[0..3]

7

H_DSTBP#[0..3]

7

Address:1001_101
13,14,15,18,21,25,27
13,14,15,18,21,25,27

ICH_SMBCLK
ICH_SMBDATA

B

ICH_SMBCLK
ICH_SMBDATA

+5VS

PWM Fan Control circuit

JP6

1

D1

H_A20M# 20
H_FERR#
20
H_IGNNE#
20
H_INIT# 20
H_INTR 20
H_NMI 20

H_STPCLK#
H_SMI# 20

21

5

R25

CH751H-40_SC76

2

+3VS

1

C65
4.7U_0805_10V4Z

2

1
2

C63
0.1U_0402_16V4Z

ACES_85205-0200

FAN

20
33

FOX_PZ47903-2741-42_YONAH

1

FAN_PWM
THERM#

2

D

U31
G

INB

O

4

Q69
AO6402_TSOP6

3

TC7SH00FUF_SSOP5

@ ZD1

S

INA

3

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

J26
M26
V23
AC20

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

2
C539

2200P_0402_50V7K
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DINV0#
DINV1#
DINV2#
DINV3#

BPM0#
BPM1#
BPM2#
BPM3#

XDP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

H_THERMDA
A24
H_THERMDC
A25
H_THERMTRIP# C7

H_THERMTRIP#

BCLK0
BCLK1

+VCCP

XDP_TMS

1

+VCCP

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

7 H_ADS#
7 H_BNR#
7 H_BPRI#
7 H_BR0#
7 H_DEFER#
7 H_DRDY#
7 H_HIT#
7 H_HITM#

R448
56_0402_5%
1
2

A22
A21

R442
H_PWRGOOD 2
1H_PWRGOOD_R
1K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

1

CLK_CPU_BCLK
CLK_CPU_BCLK#

15 CLK_CPU_BCLK
15 CLK_CPU_BCLK#

XDP_BPM#1
XDP_BPM#0

XDP_TDI

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

1

C

XDP_BPM#3
XDP_BPM#2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

This shall place near CPU
R524 1
56_0402_5%
2

2

ADSTB0#
ADSTB1#

+VCCP

JP31
XDP_BPM#5
XDP_BPM#4

1

RLZ5.1B_LL34

2

L2
V4

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ITP-XDP Connector

2

H_ADSTB#0
H_ADSTB#1

DATA GROUP

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

2 @ 1K_0402_5%

1
2
5
6

H_ADSTB#0
H_ADSTB#1

K3
H2
K2
J3
L5

ADDR GROUP

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

4

7
7

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

YONAH

5

H_REQ#[0..4]

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

XDP_DBRESET#_R

P

7

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

G

D

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

+VCCP

A

1

A

R439
H_DPSLP#

@ 56_0402_5%

@ 56_0402_5%
R440
H_DPRSTP# 1
2

B

2 2

R30

1

2

C

1 OCP#
Q6
@ MMBT3904_SOT23

OCP#

2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

21,47

Date:

5

Compal Electronics, Inc.
Yonah CPU in mFCPGA479

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

H_PROCHOT# 3

Compal Secret Data

Security Classification

@ 56_0402_5%

4

3

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

4

of

52

4

3

+VCCP

Length match within 25 mils
The trace width 18 mils space
45 VCCSENSE
7 mils
45 VSSSENSE

+VCC_CORE

2

V_CPU_GTLREF

R42
100_0402_1%
1
2

1

R41
100_0402_1%
1
2

VCCSENSE

+1.5VS

C70
0.01U_0402_16V7K

R37
1K_0402_1%

VSSSENSE

2

R39
2K_0402_1%

Close to CPU pin AD26
within 500mils.

1

2

Close to CPU pin
within 500mils.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

0

0

1

H_PSI#

H_PSI#

AE6

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2
AD26

V_CPU_GTLREF

166

0

1

1

15
15
15

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

R473
54.9_0402_1%
2
1

R470
27.4_0402_1%
2
1

R36
54.9_0402_1%
2
1

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

B22
B23
C21

COMP0
COMP1
COMP2
COMP3

R26
U26
U1
V1
E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

+VCC_CORE

R35
27.4_0402_1%
2
1

AF7
AE7

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

JP8C
D

1

45

C

+VCC_CORE

+VCCP

45
45
45
45
45
45
45

1

JP8B
VCCSENSE
VSSSENSE

B26
C72
10U_0805_10V4Z

1

D

2

VCCSENSE
VSSSENSE
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

5

B

D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

FOX_PZ47903-2741-42_YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C

B

FOX_PZ47903-2741-42_YONAH

A

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
Yonah CPU in mFCPGA479

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

5

of

52

5

4

3

2

1

+VCC_CORE

D

1
Place these capacitors on L8
(North side,Secondary Layer)

2

D

1

C412
10U_0805_6.3V6M

2

1

C413
10U_0805_6.3V6M

2

1

C414
10U_0805_6.3V6M

2

1

C415
10U_0805_6.3V6M

2

1

C416
10U_0805_6.3V6M

2

1

C417
10U_0805_6.3V6M

2

C425
10U_0805_6.3V6M

1

2

C479
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

2

1

C411
10U_0805_6.3V6M

2

1

C481
10U_0805_6.3V6M

2

1

C480
10U_0805_6.3V6M

2

1

C486
10U_0805_6.3V6M

2

1

C418
10U_0805_6.3V6M

2

1

C482
10U_0805_6.3V6M

2

C483
10U_0805_6.3V6M

1

2

C484
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

2

1

C441
10U_0805_6.3V6M

2

1

C423
10U_0805_6.3V6M

2

1

C432
10U_0805_6.3V6M

2

1

C422
10U_0805_6.3V6M

2

1

C446
10U_0805_6.3V6M

2

1

C424
10U_0805_6.3V6M

2

C445
10U_0805_6.3V6M

1

2

C485
10U_0805_6.3V6M

C

C

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

2

1

C442
10U_0805_6.3V6M

2

1

C435
10U_0805_6.3V6M

2

1

C436
10U_0805_6.3V6M

2

1

C443
10U_0805_6.3V6M

2

1

C444
10U_0805_6.3V6M

2

1

C427
10U_0805_6.3V6M

2

C426
10U_0805_6.3V6M

1

2

C431
10U_0805_6.3V6M

Mid Frequence Decoupling

+VCC_CORE
330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

@ 820U_E9_2_5V_M_R7

South Side Secondary
C408
@ 330U_D2E_2.5VM_R9

North Side Secondary
1

1

1

1

1

1

1

+

+

+

+

+

+

+

C409

2

C67

2

C66

2

C117

2

C125

2

C119

2

2

1
+ C120

2

ESR <= 1.5m ohm
Capacitor > 1980uF

@ 820U_E9_2_5V_M_R7

B

B

@ 330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

+VCCP

1
C434
220U_D2_2VK_R9

+

2

1

2

C437
0.1U_0402_10V6K

1

2

1

C429
0.1U_0402_10V6K

2

C421
0.1U_0402_10V6K

1

2

C438
0.1U_0402_10V6K

1

2

1

C428
0.1U_0402_10V6K

2

C433
0.1U_0402_10V6K

Place these inside
socket cavity on L8
(North side
Secondary)

A

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
CPU Bypass capacitors

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

6

of

52

R350
54.9_0402_1%
2
1

J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

R395
24.9_0402_1%
2
1

R339
24.9_0402_1%
2
1

B

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HCLKN
HCLKP
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3

4

13
13
14
14
H_REQ#[0..4]

D8
G8
B8
F8
A8

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

B9
C13

H_ADSTB#0
H_ADSTB#1

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HRS0#
HRS1#
HRS2#

B4
E6
D6

H_RS#0
H_RS#1
H_RS#2

13
13
14
14

4

H_ADSTB#0
H_ADSTB#1

4
4

CLK_MCH_BCLK#
15
CLK_MCH_BCLK
15
H_DSTBN#[0..3]
4

H_DSTBP#[0..3]

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

4

21
21
21
21

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

21
21
21
21

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AE35
AF39
AG35
AH39

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

21
21
21
21

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AE37
AF41
AG37
AH41

21
21
21
21

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AC37
AE41
AF37
AG41

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

AY35
AR1
AW7
AW40

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

AW35
AT1
AY7
AY40

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AU20
AT20
BA29
AY29

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

AW13
AW12
AY21
AW21

M_OCDOCMP0
M_OCDOCMP1

AL20
AF10

M_ODT0
M_ODT1
M_ODT2
M_ODT3

BA13
BA12
AY20
AU21

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

13
13
14
14

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

13
13
14
14

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

13
13
14
14

+1.8V

R419 1
1
R413

4
4
4
4

M_ODT0
M_ODT1
M_ODT2
M_ODT3

2 80.6_0402_1%
2
80.6_0402_1%

SMRCOMPN
SMRCOMPP

21,45

DPRSLPVR

19,20,21,23,25,27,32,33

VGATE_INTEL
21,33 PM_POK

R597
R590

DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SM_RCOMPN
SM_RCOMPP

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#

PWROK

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

Layout Note:
Route as short
as possible

1

M_OCDOCMP0
M_OCDOCMP1

1
R17

221_0603_1%

2

1
R351

2

40.2_0402_1%

@ 100_0402_1%

H32

CLKREQC#

15
15
15
D

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLKREQC#

5/16

15
15

15

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

C

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

B

R353
2
1
10K_0402_5%
R362
2
1
@ 10K_0402_5% 8/24

GMCH_A27

R15
2
1
10K_0402_5%

GMCH_A26

R14
2
1
10K_0402_5%

GMCH_C40

R338
2
1
10K_0402_5%

2

GMCH_D41

R342
2
1
10K_0402_5%

DDR_THERM#

2

40.2_0402_1%

R343
H_SWNG1

1

2

0.1U_0402_16V4Z
C359

1
R18

2

2

100_0402_1%

1

0.1U_0402_16V4Z
C328

1
R344

2

GMCH_C40
GMCH_D41

R400

2

R411

1

1

1

2

R412

1

V_DDR_MCH_REF

2

+VCCP

H_SWNG0
100_0402_1%

0.1U_0402_16V4Z

C40
D41

2

V_DDR_MCH_REF

C385
0.1U_0402_16V4Z

13,14,44

221_0603_1%

100_0402_1%
C330

GMCH_A27
GMCH_A26

PM_EXTTS#1

13,14

H_VREF
200_0402_1%

1
R360

2
1

A27
A26

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T1
T2
CFG5 11
T4
CFG7 11
T3
CFG9 11
T7
CFG11 11
CFG12 11
CFG13 11
T6
T5
CFG16 11
T8
CFG18 11
CFG19 11
CFG20 11

@ 100_0402_1%

+VCCP

R348

AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#

PM_EXTTS#0

+1.8V

+VCCP

2

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
PAD
CFG11
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
PAD
CFG18
CFG19
CFG20

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

+3VS

R409

2

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

4

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

1

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

SM_VREF0
SM_VREF1

CALISTOGA_A2_FCBGA1466

CALISTOGA_A2_FCBGA1466

A

D_REF_CLKN
D_REF_CLKP
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

K28

2 @ 0_0402_5%
2 0_0402_5%

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

SM_CK0
SM_CK1
SM_CK2
SM_CK3

G28
F25
H26
G6
AH33
AH34

MCH_ICH_SYNC#

1
1

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

AK1
AK41

PM_BMBUSY#
21 PM_BMBUSY#
PM_EXTTS#0
R65
0_0402_5%
PM_EXTTS#1
1
2
H_THERMTRIP#
4,20 H_THERMTRIP#
PWROK
PLTRST_R#
2
1
PLT_RST#
R408
100_0402_1%
19

21,45

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

AV9
AT9

V_DDR_MCH_REF

H_RESET# 4
H_ADS# 4
H_TRDY#
4
H_DPWR# 4
H_DRDY#
4
H_DEFER#
4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY#
4
H_CPUSLP#
4

H_RS#[0..2]

Description at page11.

U4B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

CFG

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

CLK

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

PM

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

1

DDR MUXING

+VCCP

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

2

DMI

C

R381
54.9_0402_1%
2
1

H_A#[3..31]

U4A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

D

L

3

NC

H_D#[0..63]

HOST

4

4

RESERVED

5

DDR_THERM#

A

1 PM_EXTTS#0
0_0402_5%

Stuff R1202 & R1203 for A1 Calistoga
Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

Calistoga (1/6)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

7

of

52

5

4

3

2

1

D

D

13

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

C

13

13

DDR_A_DQS#[0..7]

DDR_A_MA[0..13]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

AU12
AV14
BA20

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AY13
AW14
AY14
AK23
AK24

U4E

SA_BS0
SA_BS1
SA_BS2

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR SYS MEMORY A

13

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

B

13 DDR_A_CAS#
13 DDR_A_RAS#
13 DDR_A_WE#
T11 PAD
T12 PAD

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]

13
14
14
14
14

14

14

14

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_MA[0..13]

14 DDR_B_CAS#
14 DDR_B_RAS#
14 DDR_B_WE#
T9 PAD
T10 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

AR24
AU23
AR27
AK16
AK18

CALISTOGA_A2_FCBGA1466

SB_BS0
SB_BS1
SB_BS2

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR SYS MEMORY B

U4D
13
13
13

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D[0..63]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

14

C

B

CALISTOGA_A2_FCBGA1466

A

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Calistoga (2/6)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

8

of

52

5

4

3

2

1

D

D

L

PEGCOMP trace width
and spacing is 18/25 mils.

U4C

B37
B34
A36
C37
B35
A37

G30
D30
F29
A32
A33
E26
E27
C

+1.5VS

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

J20
B16
B18
B19
J29
K30

R363 2
R355 2

B

1 10K_0402_5%
1 10K_0402_5%

+VCCP

H23
G23
E23
D23
C22
B22
A21
B21
J22

LA_DATA#0
LA_DATA#1
LA_DATA#2
LB_DATA0
LB_DATA1
LB_DATA2
LB_DATA#0
LB_DATA#1
LB_DATA#2
LA_CLK
LA_CLK#
LB_CLK
LB_CLK#
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
TVDAC_A
TVDAC_B
TVDAC_C
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

CRT

C26
C25

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

LA_DATA0
LA_DATA1
LA_DATA2

TV

A16
C18
A19

EXP_COMPI
EXP_COMPO

LVDS

F30
D29
F28

SDVOCTRL_DATA
SDVOCTRL_CLK

CRT_IREF

PCI-EXPRESS GRAPHICS

H27
H28

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D40
D38

PEGCOMP

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

1

+1.5VS_PCIE
R331
24.9_0402_1%
2
PEG_RXP[0..15]

18

PEG_RXN[0..15]

18

C

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

C22
C24
C26
C30
C32
C34
C37
C41
C45
C47
C49
C51
C53
C56
C58
C61

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

C20
C23
C25
C28
C31
C33
C35
C38
C43
C46
C48
C50
C52
C54
C57
C60

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0

PEG_M_TXP[0..15]

18

PEG_M_TXN[0..15]

18

B

CALISTOGA_A2_FCBGA1466

A

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Calistoga (3/6)
Rev
0.5

LA-2821P

Date:

5

4

3

2

Friday, November 25, 2005

Sheet
1

9

of

52

5

4

3

2

1

D

D

U4H

2

1

2

C368
2.2U_0805_16V4Z

C339
4.7U_0805_10V4Z

C

1

2

1

2

C317
0.47U_0603_10V7K

MCH_A6

1

MCH_D2

1

2

C55
0.47U_0603_10V7K
MCH_AB1

2

C318
0.22U_0603_10V7K

C336
0.22U_0603_10V7K

B

+1.5VS

B30
C30
A30

+1.5VS_PCIE

W=40 mils

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

AB41
AJ41
L41
N41
R41
V41
Y41

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

AC33
G41
H41

+1.5VS_3GPLL
+2.5VS

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

E21
F21
G21

MCH_CRTDAC

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

B26
C39
AF1

VCCA_LVDS
VSSA_LVDS

A38
B39

+1.5VS_HPLL
1
2
R356
0_0805_5%

VCCA_MPLL

AF2

+1.5VS_MPLL

VCCA_TVBG
VSSA_TVBG

H20
G20

+1.5VS

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

E19
F19
C20
D20
E20
F20

+1.5VS

VCCD_HMPLL0
VCCD_HMPLL1

AH1
AH2

+1.5VS

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

A28
B28
C28

10U_0805_6.3V6M

1
+

C297
220U_D2_4VM_R25

2

R410
2
1
0_0805_5%

1 C315

1 C380

2

2

+1.5VS

10U_0805_6.3V6M

9/15
+2.5VS

J5

P O W E R

2
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

2

1

+VCCP

1

PAD-SHORT 2x2m
J4
2
1

+2.5VS

2

PAD-No SHORT 2x2m
1 R333
2
@ 0_0805_5%

close pin G41
C

PCI-E/MEM/PSB PLL decoupling
+1.5VS_3GPLL

D21
H19

VCCHV0
VCCHV1
VCCHV2

A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+1.5VS
R398
1
2
0.5_0805_1%

C371

VCCD_TVDAC
VCCDQ_TVDAC

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

1

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

C329
0.1U_0402_16V4Z

+

C42
220U_D2_2VK_R9

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

H22

1

2

1

2

R396
2
1
0_0805_5%

C378

C387

10U_0805_6.3V6M

@ 0.1U_0402_16V4Z

+1.5VS_TVDAC

+1.5VS
R332
2
1
0_0805_5%

@ 0.022U_0402_16V7K

1

1

2

2

0.1U_0402_16V4Z

C324

1

1

C316

2

2

C319
@ 0.022U_0402_16V7K

@ 10U_0805_6.3V6M

+1.5VS_TVDAC
+1.5VS_HPLL

+1.5VS_MPLL
+3VS
C322
0.1U_0402_16V4Z

1

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

VCC_SYNC

1

1

2

2

R23
2
1
0_0805_5%

45mA Max.

+1.5VS

R22
2
1
0_0805_5%

45mA Max.

+1.5VS

C320
10U_0805_6.3V6M

C373
0.1U_0402_16V4Z

1

2

1

2

C62

C374

10U_0805_6.3V6M

0.1U_0402_16V4Z

1

1

2

2

C59
10U_0805_6.3V6M

B

+1.5VS

1

2

C377
0.1U_0402_16V4Z

+VCCP

CALISTOGA_A2_FCBGA1466

A

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Calistoga (4/6)
Rev
0.5

LA-2821P

Date:

5

4

3

2

Friday, November 25, 2005

Sheet
1

10

of

52

5

4

3

2

1

Strap Pin Table
CFG[3:17] have internal pull up

2

2

10U_0805_6.3V6M
C

1
C64
220U_D2_2VK_R9

C386

+

2

1
+

2
@ 330U_D2E_2.5VM_R9
B

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

+VCCP
+1.8V

CALISTOGA_A2_FCBGA1466

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1 VCCSM_LF2
AJ1 VCCSM_LF1

1

2

C398
0.47U_0603_10V7K

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C390
0.47U_0603_10V7K

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

1

2

Place near pin AV1 & AJ1

011
001

1

2

C395
0.47U_0603_10V7K

C389
0.47U_0603_10V7K

CFG[2:0]

1

2

= 667MT/s FSB
= 533MT/s FSB

CFG5

0 = DMI x 2
1 = DMI x 4

CFG7

0 = Reserved
1 = Mobile Yonah CPU

CFG9

0 = Lane Reversal Enable *
1 = Normal Operation (Default)

*(Default)

1 = Calistoga

00
01
10
11

CFG[13:12]
+1.8V

2

1

2

1
C388

2

1

2

=
=
=
=

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation * (Default)

CFG16

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled *(Default)

CFG18

0 = 1.05V
1 = 1.5V

CFG19

0 = Normal Operation * (Default)
1 = DMI Lane Reversal Enable

*(Default)

0 = No SDVO Device Present
(Default)

SDVO_CTRLDATA

*

1 = SDVO Device Present

CFG20
(PCIE/SDVO select)

0 = Only PCIE or SDVO is
operational. * (Default)
1 = PCIE/SDVO are operating
simu.

C

1

2

Place near pin BA23
1
C407

*

0 = Reserved

Place near pin AT41 & AM41

1

D

*(Default)

(According to Intel Napa Schematic Checklist & CRB
Rev1.502 document 2.2Kohm pull-down resistor no request)

CFG11

0.1U_0402_16V4Z

P O W E R

VCCSM_LF4
VCCSM_LF5

C384

1

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

0.1U_0402_16V4Z

1

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

0.1U_0402_16V4Z

C338

2

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C381

1

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

0.1U_0402_16V4Z

C337

C343
1U_0603_10V4Z

10U_0805_6.3V6M

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C382

2

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

CFG[19:18] have internal pull down

+1.8V

U4G

C406
0.47U_0603_10V7K

2

1

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

2

1

C375
0.22U_0603_10V7K

1

C333
0.22U_0603_10V7K

C367
0.22U_0603_10V7K

D

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+VCCP

+1.5VS

1

C405

2
10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

+ C402

2

@ 220U_D2_4VM

L

7

CFG5

7

CFG7

7

CFG9

7

CFG11

7

CFG12

7

CFG13

7

CFG16

7
7
7

CFG18
CFG19
CFG20

R349

1

2 @

2.2K_0402_5%

R340

1

2 @

2.2K_0402_5%

R354

1

2 @

2.2K_0402_5%

R341

1

2 @

2.2K_0402_5%

R365

1

2 @

2.2K_0402_5%

R371

1

2 @

2.2K_0402_5%

R359

1

2 @

2.2K_0402_5%

R370
R368
R369

1
1
1

2 @ 1K_0402_5%
2 @ 1K_0402_5%
2 @ 1K_0402_5%

@wait DB-1 test verify
+3VS

C404
0.47U_0603_10V7K

U4F

+VCCP

1

B

2

Place near pin BA15

CALISTOGA_A2_FCBGA1466
A

A

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

Calistoga (5/6)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

11

of

52

5

4

3

2

U4I

D

C

B

AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

1

U4J

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
CALISTOGA_A2_FCBGA1466

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

D

C

B

CALISTOGA_A2_FCBGA1466

A

A

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Calistoga (6/6)
Rev
0.5

LA-2821P

Date:

2

Friday, November 25, 2005

Sheet
1

12

of

52

5

4

3

2

1

+1.8V

V_DDR_MCH_REF

DDR_A_DQS#[0..7]

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_MA[0..13]

DDR_A_D2
DDR_A_D3

D

DDR_A_D8
DDR_A_D14

Layout Note:
Place near JP34

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_D21
DDR_A_D17

2

1

C95

C91

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C93

2

0.1U_0402_16V4Z

2

1

C105

C464

2

1

0.1U_0402_16V4Z

C462

2

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C463

2

2.2U_0805_16V4Z

2

1

C461

2.2U_0805_16V4Z

C467

2.2U_0805_16V4Z

1

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D19

2

DDR_A_D25
DDR_A_D24
DDR_A_DM3
DDR_A_D27
DDR_A_D30

C

7

DDR_CKE0_DIMMA
8

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_A_BS#2

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

8 DDR_A_BS#0
8 DDR_A_WE#

+0.9V
7

2

1

2

7

M_ODT1

DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

1

DDR_A_D34
DDR_A_D38

2

DDR_A_DQS#4
DDR_A_DQS4

C114

C113

C112

C110

C111

C115

C84

C82

C81

C80

C78

C79

C83

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

8 DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D41

B

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D52
DDR_A_D53
+0.9V

DDR_A_MA5
DDR_A_MA8

RP11
1
2
RP7

DDR_A_MA1
DDR_A_MA3

1
2

4
3

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

RP13 56_0404_4P2R_5%
4
1 DDR_A_BS#2
3
2 DDR_CKE0_DIMMA

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D51
DDR_A_D55

56_0404_4P2R_5% RP18 56_0404_4P2R_5%
4
4
1 DDR_A_MA7
3
3
2 DDR_A_MA6

DDR_A_D56
DDR_A_D61

RP15 56_0404_4P2R_5% RP12 56_0404_4P2R_5%
DDR_A_RAS#
1
4
4
1 DDR_A_MA9
DDR_CS0_DIMMA# 2
3
3
2 DDR_A_MA12
DDR_A_BS#0
DDR_A_MA10

A

DDR_A_D58
DDR_A_D59

RP10 56_0404_4P2R_5% RP17 56_0404_4P2R_5%
1
4
4
1 DDR_A_MA4
2
3
3
2 DDR_A_MA2
RP9

DDR_A_CAS#
DDR_A_WE#

DDR_A_DM7

1
2

4,14,15,18,21,25,27
4,14,15,18,21,25,27

ICH_SMBDATA
ICH_SMBCLK

ICH_SMBDATA
ICH_SMBCLK
+3VS

56_0404_4P2R_5% RP16 56_0404_4P2R_5%
4
4
1 DDR_A_MA0
3
3
2 DDR_A_BS#1

C96

RP8 56_0404_4P2R_5% RP14 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2
3
4
1 M_ODT0
M_ODT1
1
4
3
2 DDR_A_MA13

0.1U_0402_16V4Z

56_0404_4P2R_5% RP19 56_0404_4P2R_5%
4
1 DDR_CKE1_DIMMA
3
2 DDR_A_MA11

1

2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

FOX_ASOA426-M4R-TR

SO-DIMM A
REVERSE

DDR_A_D7
DDR_A_D1
DDR_A_DM0
DDR_A_D5
DDR_A_D6

1

2

1

2

D

DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

7

DDR_THERM#

7,14

7

DDR_A_D9
DDR_A_D15

DDR_A_D20
DDR_A_D16
DDR_THERM#
DDR_A_DM2
DDR_A_D18
DDR_A_D23
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

7

DDR_A_BS#1
8
DDR_A_RAS#
8
DDR_CS0_DIMMA#

7

C

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

M_ODT0

7

DDR_A_D36
DDR_A_D33
DDR_A_DM4
DDR_A_D37
DDR_A_D32
DDR_A_D40
DDR_A_D44
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D48
DDR_A_D49
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1
M_CLK_DDR#1

7
7

DDR_A_DM6
DDR_A_D50
DDR_A_D54
DDR_A_D60
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

A

Top side
Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
DDRII-SODIMM SLOT1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

7,14,44

R38
10K_0402_5%
2
1

8

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C92

DDR_A_D0
DDR_A_D4

DDR_A_DQS[0..7]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C97

DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

0.1U_0402_16V4Z

8
8

V_DDR_MCH_REF

JP9

DDR_A_D[0..63]

2.2U_0805_16V4Z

8

R40
10K_0402_5%
2
1

8

+1.8V

4

3

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

13

of

52

5

4

3

2

DDR_B_D[0..63]
DDR_B_DM[0..7]

DDR_B_D0
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0

D

DDR_B_D7
DDR_B_D3

Layout Note:
Place near JP34

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

+1.8V

2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D21
DDR_B_D20

1

C454

C106

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C455

2

0.1U_0402_16V4Z

2

1

C94

0.1U_0402_16V4Z

2

1

C107

C466

2

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C460

2

2.2U_0805_16V4Z

2

1

C108

2.2U_0805_16V4Z

C109

2.2U_0805_16V4Z

1

DDR_B_DQS#2
DDR_B_DQS2

2

DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

C

7

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_CKE2_DIMMB

8

DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9V

2

1

2

7

DDR_B_BS#0
DDR_B_WE#

8 DDR_B_CAS#
DDR_CS3_DIMMB#

1

7

M_ODT3

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D37
DDR_B_D36

2
C471

C472

C473

C474

C475

C476

C477

C90

C89

C88

C87

C86

C85

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

8
8

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34

B

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D47

+0.9V

DDR_B_MA1
DDR_B_MA3

RP34
1
2

DDR_B_BS#0
DDR_B_MA10

RP35 56_0404_4P2R_5% RP6
1
4
4
2
3
3
RP3

DDR_B_MA0
DDR_B_BS#1

1
2

4
3

RP32 56_0404_4P2R_5%
DDR_B_MA9
4
1
DDR_B_MA12
3
2

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50

56_0404_4P2R_5% 5/16
DDR_B_MA7
1
DDR_CKE3_DIMMB
2

DDR_B_D60
DDR_B_D61

56_0404_4P2R_5% RP33 56_0404_4P2R_5%
DDR_B_MA5
4
4
1
DDR_B_MA8
3
3
2

RP2

V_DDR_MCH_REF

7,13,44

RP36 56_0404_4P2R_5% RP4
1
4
4
2
3
3
RP37
56_0404_4P2R_5% RP1
DDR_CS3_DIMMB# 2
3
4
M_ODT3
1
4
3

56_0404_4P2R_5%
DDR_B_MA4
1
DDR_B_MA2
2

56_0404_4P2R_5% RP31
4
3

DDR_B_D58
DDR_B_D59
4,13,15,18,21,25,27
4,13,15,18,21,25,27

ICH_SMBDATA
ICH_SMBCLK

ICH_SMBDATA
ICH_SMBCLK
+3VS
C453

56_0404_4P2R_5%
M_ODT2
1
DDR_B_MA13
2

1
2

0.1U_0402_16V4Z

1

2

FOX_ASOA426-M2RN-7F

SO-DIMM B
STANDARD

DDR_B_DM0
DDR_B_D6
DDR_B_D2

1

2

2

D

DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3
M_CLK_DDR#3

7

DDR_THERM#

7,13

7

DDR_B_D14
DDR_B_D15

DDR_B_D16
DDR_B_D18
DDR_THERM#
DDR_B_DM2
DDR_B_D17
DDR_B_D19
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
C

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

7

DDR_B_BS#1
8
DDR_B_RAS#
8
DDR_CS2_DIMMB#

7

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13

M_ODT2

7

DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

7
7

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R33

1

2

+3VS

10K_0402_5%
A

Bottom side

DDR_B_BS#2
DDR_CKE2_DIMMB

Compal Secret Data

Security Classification

56_0404_4P2R_5%

2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
DDRII-SODIMM SLOT2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

1

R34

56_0404_4P2R_5% 5/16
DDR_B_MA6
1
DDR_B_MA11
2

DDR_B_DM7

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

DDR_B_D4
DDR_B_D1

10K_0402_5%

56_0404_4P2R_5% RP5
DDR_B_RAS#
1
4
4
DDR_CS2_DIMMB# 2
3
3
DDR_B_CAS#
DDR_B_WE#
A

DDR_B_D48
DDR_B_D53

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C103

DDR_B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

C99

8

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

0.1U_0402_16V4Z

DDR_B_DQS[0..7]

V_DDR_MCH_REF
JP29
2.2U_0805_16V4Z

8

+1.8V

1

8
8

1

+1.8V

DDR_B_DQS#[0..7]

2

8

4

3

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

14

of

52

5

4

3

2

1

+CK_VDD_MAIN1

FSLA

CLKSEL2

CLKSEL1

CLKSEL0

0

0

1

1

0

CPU
MHz
133

1

166

SRC
MHz
100
100

PCI
MHz

2
0_0805_5%

1

33.3

2

33.3
1
R453

+3VS

2
0_0805_5%

1

FSB Frequency Selet:
CPU Driven

*(Default)
533MHz

2

Stuff

CLK_Ra

CLK_Rb

CLK_Rc

No Stuff

CLK_Rd

CLK_Re

CLK_Rf

Stuff

CLK_Rd

CLK_Re

CLK_Rf

No Stuff

CLK_Ra

CLK_Rb

Stuff

CLK_Rd

CLK_Rf

1

C452
10U_0805_10V4Z

2

1

C451
.01U_0402_16V7K

1

C496
10U_0805_10V4Z

2

1

C430
0.1U_0402_16V4Z

CLK_Ra

No Stuff

CLK_Rb

+3VS

R506
1
2
NODP@ 0_0805_5%

+VCCP

1

R508
1
2
DP@ 0_0805_5%

2

1

C457
10U_0805_10V4Z
+CK_VDD_DP

CLK_Rc

CLK_Rc

2

1

0.1U_0402_16V4Z

+CK_VDD_MAIN1

5

CPU_BSEL0

1
R575
0_0402_5%

CK_VDD_REF

7

R576
1K_0402_5%

2

CLK_Ra

50
55

R538
2
2
R551

CLK_48M_ICH
CLK_48M_CB

21 CLK_48M_ICH
24 CLK_48M_CB

1

MCH_CLKSEL0

2

2

21

1

C

2

33

1

0.1U_0402_16V4Z

CLK_Rd
1

24

2

41

1

C447
0.1U_0402_16V4Z

10
5

0.1U_0402_16V4Z
2 R474
1 CLKIREF
DP@ 0_0402_5%
C448

2
R550
8.2K_0402_5%
FSA 2
1

12_0402_5%
1
1 FSA
12_0402_5%
FSB

15

1 R489
33_0402_5%

CLKREF1

59

LPNO@ 4.7K_0402_1% 1

2 R472

CLKIREF

46

0.1U_0402_16V4Z

2

CLK_ENABLE#

19

R566
1K_0402_5%

2

MCH_CLKSEL1

1
@ R539

2

0_0402_5%

CLK_Re

9
2 R534
1 PCI_ICH
33_0402_5%
R496
12_0402_5%
2
1 CLKREF0
2
1
R498
12_0402_5%
PCI_MINI
1 R513 PCI_CLK3
1 R532
1 R528 PCI_EC

10K_0402_5% 2
@ 10K_0402_5% 2
33_0402_5% 2

32

CLK_PCI_TCG

33_0402_5% 2

23

CLK_PCI_PCM

33_0402_5% 2

4,13,14,18,21,25,27

+VCCP

CLK_ENABLE#

CLK_14M_KBC
CLK_14M_SIO

+3VS
CLK_PCI_EC

33

B

8

7

R564
1K_0402_5%

CLK_Rb

H_STP_CPU#
H_STP_PCI#

CLK_PCI_ICH

CLK_PCI_ICH

33 CLK_14M_KBC
31 CLK_14M_SIO

1
1
2

CK_VDD_REF

1

CK_VDD_48

2

D

R548
2.2_0805_1%

2

1

C465
0.1U_0402_16V4Z

2

ICH_SMBDATA
ICH_SMBCLK

0.1U_0402_16V4Z
C439 2

X1

VDD48

X2

7

VDDPCI
SATACLKT
VDDSRC
SATACLKC

62
1
2

1 R519

PCI_CLK5

3

1 R533

PCI_PCM

6

CLK_XTAL_IN

56

CLK_XTAL_OUT

28

VDDSRC

CPUCLKT0

VDDCPU

CPUCLKC0

VDDREF
FSLA/USB_48MHz

CPUCLKC1

L

CPU_BSEL2

1
R492
0_0402_5%

MCH_CLKSEL2

7

2

31

CLK_PCI_SIO

LCDCLK_SST/SRCCLKT0
IREF
LCDCLK_SSC/SRCCLKC0
PCI/SRC_STOP#

SRCCLKT2

Vtt_PwrGd#/PD

SRCCLKC2

**SEL_LCDCLK#/PCICLK_F1
REF0/PCICLK1

SATA1/SRCCLKC4

MCH_BCLK

48

MCH_BCLK#

CLK_MCH_BCLK
2
24_0402_5%
CLK_MCH_BCLK#
2
24_0402_5%

*SEL_PCI1/PCICLK3

18

PCIE_MXM

19

PCIE_MXM#

11/14
22

PCIE_LOM

23

PCIE_LOM#

30

PCIE_SATA

31

PCIE_SATA#

*CLKREQB#

63

CLKREQB#

**SEL_SATA2/PCICLK5

SRCCLKC1

21

PCICLK6

SCLK

13

DOTT_96MHz

14

27

CLK_PCI_DB

R531

2

1 DB@

DOTC_96MHz

PCI_CLK3

CLK_Rc

@ R493

SRCCLKT3

26

PCIE_DOCK

27

PCIE_DOCK#

SATA2/SRCCLKT5

35

PCIE_ICH

SATA2/SRCCLKC5

34

*CPUCLKT2_ITP/CLKREQC#

45

SRCCLKT6

37

SRCCLKC6

36

NOXDP@ : means just build when XDP function disable.

4

GND

1

+3VS

XDP@ : means just build when XDP function enable.
When this time, docking PCI express will not work.

12

GND

SRCCLKT8

43

17

GND

SRCCLKC8

42

58

GND

47

LCD(Low)/SRC(High)
clock select
+3VS

Pin44/45 function select

GNDSRC

SRCCLKT7

40

GNDSRC

SRCCLKC7

38

32

GNDSATA

1

2

R535

R501

10K_0402_5%

NOXDP@10K_0402_5%

CLK_PCIE_LOM
2
24_0402_5%
CLK_PCIE_LOM#
2
24_0402_5%

1
R558
1
R559

CLK_PCIE_SATA
2
24_0402_5%
CLK_PCIE_SATA#
2
24_0402_5%

7

CLK_MCH_BCLK
2
R459
CLK_MCH_BCLK# 2
R460

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

CLK_PCIE_MXM

1
R562
CLK_PCIE_MXM#
1
R563

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_PCIE_LOM

1
R554
CLK_PCIE_LOM#
1
R555

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_PCIE_SATA
1
R567
CLK_PCIE_SATA# 1
R568

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_MCH_3GPLL 1
R466
CLK_MCH_3GPLL# 1
R467

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_PCIE_MCARD 1
R464
CLK_PCIE_MCARD# 1
R465

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_PCIE_ICH

1
R468
CLK_PCIE_ICH#
1
R469

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_CPU_XDP

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

C

+3VS
CLKREQA#

18,25

CLK_PCIE_MXM

18

CLK_PCIE_MXM#
CLK_PCIE_LOM

18
25

CLK_PCIE_LOM#

25

CLK_PCIE_SATA

20

CLK_PCIE_SATA#

20

2
R507

1

CPPE#
10K_0402_5%

CPPE#

19,35

1
R542
1
R543

CLK_PCIE_DOCK
2
24_0402_5%
CLK_PCIE_DOCK#
2
24_0402_5%

CLK_PCIE_DOCK

35

CLK_PCIE_DOCK#

35

CLK_PCIE_ICH
2
CLK_PCIE_ICH
21
24_0402_5%
PCIE_ICH#
CLK_PCIE_ICH#
2
CLK_PCIE_ICH#
21
24_0402_5%
R461
2
1 NOXDP@ 10K_0402_5%
+3VS
CLKREQC#
2
1
CLKREQC#
7
R479 NOXDP@ 0_0402_5%
CPU_XDP
CLK_CPU_XDP
1
2
CLK_CPU_XDP 4
R480
XDP@ 33_0402_5%
MCH_3GPLL
CLK_MCH_3GPLL
1
2
CLK_MCH_3GPLL
7
R484
24_0402_5%
MCH_3GPLL# 1
CLK_MCH_3GPLL#
2
CLK_MCH_3GPLL#
7
R485
24_0402_5%

1
R486
1
R487

R451

1 NOXDP@ 10K_0402_5%

2

CLKREQD#
2
1
R455 NOXDP@ 0_0402_5%
CPU_XDP#
CLK_CPU_XDP#
1
2
R481
XDP@ 33_0402_5%
PCIE_MCARD 1
CLK_PCIE_MCARD
2
R482
24_0402_5%
PCIE_MCARD# 1
CLK_PCIE_MCARD#
2
R483
24_0402_5%

2
R462
CLK_CPU_XDP#
2
R463
CLK_PCIE_DOCK
2
R556
CLK_PCIE_DOCK# 2
R557

+3VS

CLKREQD#

B

27

CLK_CPU_XDP#

L

4

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

27

If LP Chip stuff, all 49.9_0402
could be removed .

27

2

A

1
R504

@ 10K_0402_5%

XDP@ 10K_0402_5%

= 100MHz
*High:Pin18/19
Low:Pin18/19 = 96MHz

High:Pin44/45 = CLKREQ

*Low:Pin44/45 = CPUCLK2_ITP

Compal Secret Data

Security Classification
Issued Date

@ PAD-No SHORT 2x2m

2

1
R540
1
R541

7

CLK_MCH_BCLK#

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

2

2

PCI_MINI

R536

2

J14

PCI_ICH

1

1 2

300_0402_5%

CLK_PCIE_MXM
2
24_0402_5%
CLK_PCIE_MXM#
2
24_0402_5%

CLK_MCH_BCLK

CLK_CPU_BCLK
2
R457
CLK_CPU_BCLK# 2
R458

ICS954306BGLFT_TSSOP64

A

R549

44

+3VS

1

CLK_ENABLE#

*CPUCLKC2_ITP/CLKREQD#

39

R537
@ 10K_0402_5%

GNDCPU

25

1

2

CLK_Rf

1
R552
1
R553

4

11/14

SRCCLKC3

12_0402_5%

0_0402_5%

@ 10K_0402_5%
CLKREQA#

4

CLK_CPU_BCLK#

20

SRCCLKT1

53

12_0402_5%

1

64

**SEL_SATA1/PCICLK4

ICH_SMBCLK

1

1
R477
1
R478

CLK_CPU_BCLK

*REQ_SEL/PCICLK2

SDATA

2

0_0402_5%

49

51

CPU_STOP#

54

R518

2

Routing the trace at least 10mil
CLK_CPU_BCLK
2
24_0402_5%
CLK_CPU_BCLK#
2
24_0402_5%

1

2

R491
1K_0402_5%

R517 1
CPU_BCLK

11/21

1

5

1

2

1
R475
CPU_BCLK#
1
R476

52

Place near U25
Place these components
near each pin within 40
mils.

1 27P_0402_50V8J

Routing the trace at0_0402_5%
least 10mil

2
R510

FSLC/TEST_SEL/REF1

ICH_SMBDATA

1K_0402_5%

C440 2

R527 1

FSLB/TEST_MODE

R490
R494
8.2K_0402_5%
CLKREF1 2
1

L

29

VDDSATA

SATA1/SRCCLKT4
60

1 27P_0402_50V8J

Y6
14.31818MHZ_20P_6X1430004201

57

2

4,13,14,18,21,25,27

Place crystal within
500 mils of CK410
C450

VDD

2

21 H_STP_CPU#
21 H_STP_PCI#
37,45

FSB

R454
1
2
1_0805_1%

*CLKREQA#

61

1
R565
0_0402_5%

.01U_0402_16V7K

C495

R561

+VCCP

CPU_BSEL1

C468

CPUCLKT1
11

CLK_14M_ICH 2

CLK_14M_ICH

1K_0402_5%

5

2

U30

1

C469

+CK_VDD_DP

CLK_Re

DP@

2

C470

CK_VDD_48

+VCCP

@ R560
56_0402_5%

.01U_0402_16V7K

+CK_VDD_DP

16

667MHz

2

1

C449

+CK_VDD_MAIN2

Table : ICS954306
D

1
R502

+3VS

1

FSLB

2

FSLC

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

Clock generator
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

15

of

52

C

D

+RCRT_VCC

1.1A_6VDC_FUSE

W=40mils

1

BLUE
GREEN
RED

CH491D_SC59
C420

1

0.1U_0402_16V4Z

1

2

1

@

3

@ 18P_0402_50V8J

2
+3VS
FOX_DZ11A91-L7

@ 18P_0402_50V8J

2

D_HSYNC

35

D_VSYNC

35

D_VSYNC

1

2

C325

+CRTVDD

+CRTVDD

R446

@ 5P_0402_50V8C

R445

2.2K_0402_5%

2.2K_0402_5%

35

51K_0402_5%

D_DDCDATA

D_DDCDATA

1
Q68

BSS138_SOT23

Place cloce to MXM connector JP39
35

D_DDCCLK

D_DDCCLK

1
Q67

3

M_DDCCLK

D

L

M_DDCDATA

3
S

51K_0402_5%

2

1

2

R308

1

R306

2

16
17

D_HSYNC

R310
4 VSYNC
1
2
Y
0_0603_5%
U23
SN74AHCT1G125GW_SOT353-5
1
C326
@ 5P_0402_50V8C

2

C75

1 R450
2
2.2K_0402_5%

5
1

3

G

A

2

2

@
R312
1
2
0_0603_5%

Y

2

2

1

1

M_DDCDATA

2

18

2
G

U24
SN74AHCT1G125GW_SOT353-5
HSYNC
4

2

1

S

M_VSYNC

A

2

1

2

18

2

0.1U_0402_16V4Z

P
OE#

M_HSYNC

G

18

P
OE#

5
1

0.1U_0402_16V4Z

C73

150_0402_1%

2
G

1

BLUE_R

R664

D

2

1 @

GREEN_R

R666

150_0402_1%

1

1

C294

RED_R

2

+5VS

C293

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

1

+5VS

R31
1
2
0_0603_5%
R29
C76
1
2
0_0603_5%
R26
1
2@ 18P_0402_50V8J
0_0603_5%

RED

RED

C77
5P_0402_50V8C

35

R665

150_0402_1%

JP7
GREEN

C74
5P_0402_50V8C

1

11/17

2

BLUE

BLUE
GREEN

C71
5P_0402_50V8C

35
35

1

2

2

CRT Connector

+CRTVDD

D3

2

1

F1

1

2

+5VS

E

1

B

1 R449
2
2.2K_0402_5%

A

M_DDCCLK

18

BSS138_SOT23

Place cloce to MXM connector JP39

L

TV-Out Connector
Place cloce to TV-Out connector JP1
+3VS

1

3

3

2

2

3

2

D8
@ DAN217_SC59

1

D6
@ DAN217_SC59

1

D7
@ DAN217_SC59

3

L
3

JP10

18,35

M_LUMA

18,35
18,35

M_CRMA
M_COMP

M_LUMA
M_CRMA
M_COMP
C478
@ 18P_0402_50V8J

1

2

C459

1

2

1

2

R545 1

2 0_0603_5%

M_LUMA_R

R516 1
R529 1

2 0_0603_5%
2 0_0603_5%

M_CRMA_R
M_COMP_R

1
2
3
4
5
6
7
SUYIN_33007SR-07T1-C

C488

L

Place cloce to TV-Out connector JP1

@ 18P_0402_50V8J

@ 18P_0402_50V8J

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
CRT & TVout Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

D

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
E

16

of

52

5

4

3

2

1

D

D

MXM LVDS CONN

LCD POWER CIRCUIT

B+_LCD
C286

2

1

0.1U_0603_50V4Z
+3VALW
S

LCDVDD
C287

PAD-SHORT 2x2m
J2
33

INV_PWM

2

1

@ PAD-No SHORT 2x2m

D

100_0402_1%

M_TXB2+ 18
M_TXB2- 18

D
Q55
2N7002_SOT23

M_TXB1+ 18
M_TXB1- 18

R309

1
R315

2
G

1

2

47K_0402_5%

S

M_TXB0+ 18
M_TXB0- 18

2

1M_0402_5%
C298
1
2

1

C288

1

0.047U_0402_16V7K
C12

1

C289
C

1

1

3

2

Q56
DTC124EK_SC59

M_TXACLK+ 18
M_TXACLK- 18
M_TXA2+ 18
M_TXA2- 18

18

M_ENAVDD

M_TXA1+ 18
M_TXA1- 18

2

4.7U_0805_10V4Z

2

@ 4.7U_0805_10V4Z

0.1U_0402_16V4Z

M_ENAVDD 2

3

C

2

1

R307

M_TXBCLK+ 18
M_TXBCLK- 18

3

M_PWM

1
2
1
3
4
3
5
6
5
7
8
7
9
10
9
11
12
11
13
14
13
15
16
15
17
18
17
19
20
19
21
22
21
23
24
23
25
26
25
27
28
27
29
30
29
31
32
31
33
34
33
35
36
35
37
38
37
39
40
39
41
42
41
43
44
43
45
46
45
47
48
47
49
50
49
ACES_87216-5002

2
G

2
4
6
KC FBM-L11-201209-221LMA30T_0805 8
10
+3VS
12
14
LCDVDD
16
18
20
22
24
LID_SW#
26
21,34 LID_SW#
ALS_EN
28
19 ALS_EN
30
32
+5VS_INV
34
18 M_LCD_CLK
36
18 M_LCD_DAT
38
40
42
44
46
48
50

J1
18

JP3

1

68P_0402_50V8J
L13
2

1

B+

Q1
AO3413_SOT23

LCDVDD

1

1 2

2

M_TXA0+ 18
M_TXA0- 18

Q10
DTA114YKA_SC59

3

1

+5VS_INV

B

10K

47K

+5VS

B

7

R86

2
1

O
B

D

3

A

U11A
SN74LVC08APW_TSSOP14

3
2

2

M_ENBLT

2

18

1

G

LID_SW#

S

P

14

+3VS

R80

Q13
BSS138_SOT23

2
G

100K_0402_5%

1

1

100K_0402_5%

A

A

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LCD CONN.
Rev
0.5

LA-2821P

Date:

2

Friday, November 25, 2005

Sheet
1

17

of

52

5

4

9

PEG_RXN[0..15]

9

PEG_RXP[0..15]

9

PEG_M_TXN[0..15]

9

PEG_M_TXP[0..15]

3

+1.8VS +5VS

B+
D

2

+1.8VS

MXM_CD0#

JP5A
0.1U_0603_50V4Z

1
+

C9
100U_25V_M

2

1

C11

2

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
RUNPWROK
5VRUN
GND
GND
GND

1

2

PEG_RXN1
PEG_RXP1

C292
4.7U_0805_10V4Z

PWR_GD 33,36,37,45,47
15,25 CLKREQA#

R311

+3VS

PEG_RXN14
PEG_RXP14
PEG_RXN13
PEG_RXP13
PEG_RXN12
PEG_RXP12
C

PEG_RXN11
PEG_RXP11
PEG_RXN10
PEG_RXP10
PEG_RXN9
PEG_RXP9
PEG_RXN8
PEG_RXP8
PEG_RXN7
PEG_RXP7
PEG_RXN6
PEG_RXP6
PEG_RXN5
PEG_RXP5
PEG_RXN4
PEG_RXP4
PEG_RXN3
PEG_RXP3
PEG_RXN2
PEG_RXP2

PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND

B

VGA_RST#

MXM Address:100_1100

26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108

PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2

CLK_PCIE_MXM#
CLK_PCIE_MXM

15 CLK_PCIE_MXM#
15 CLK_PCIE_MXM
1
2
@ 0_0402_5%
21 VGA_RST#

4,13,14,15,21,25,27
4,13,14,15,21,25,27
R303

ICH_SMBDATA R320 1
ICH_SMBCLK R319 1

ICH_SMBDATA
ICH_SMBCLK

21

MXM_CD1#

PEG_M_TXN15
PEG_M_TXP15

21,47

PEG_M_TXN14
PEG_M_TXP14

21,25,27,28,29,33,35,36,40,43,44
25,33,40,41,42,47
ADP_PRES

PEG_M_TXN13
PEG_M_TXP13

2 0_0402_5% MXM_SMBDATA
2 0_0402_5% MXM_SMBCLK
MXM_THERM#
M_HSYNC
M_VSYNC
M_DDCCLK
M_DDCDATA

MXM_THERM#
16 M_HSYNC
16 M_VSYNC
16 M_DDCCLK
16 M_DDCDATA

1
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107

109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229

PEG_RXN0
PEG_RXP0

@ 8.2K_0402_5%
PEG_RXN15
PEG_RXP15

MXM_CD0#

JP5B

2
4
6
8
10
12
14
16
18
20
22
24

2

9/15

1
3
5
7
9
11
13
15
17
19
21
23

1

+5VALW
SLP_S3#
R313

SLP_S3#
1
2
0_0402_5%

PEG_M_TXN12
PEG_M_TXP12
PEG_M_TXN11
PEG_M_TXP11
PEG_M_TXN10
PEG_M_TXP10
PEG_M_TXN9
PEG_M_TXP9
PEG_M_TXN8
PEG_M_TXP8
PEG_M_TXN7
PEG_M_TXP7
PEG_M_TXN6
PEG_M_TXP6
35

PEG_M_TXN5
PEG_M_TXP5
PEG_M_TXN4
PEG_M_TXP4

DVI_DETECT
DVI_CLKDVI_CLK+

DVI_DETECT
35 DVI_CLK35 DVI_CLK+

DVI_TX2DVI_TX2+

35 DVI_TX235 DVI_TX2+

PEG_M_TXN3
PEG_M_TXP3

DVI_TX1DVI_TX1+

35 DVI_TX135 DVI_TX1+

PEG_M_TXN2
PEG_M_TXP2

DVI_TX0DVI_TX0+

35 DVI_TX035 DVI_TX0+

PEX_RX1#
GND
PEX_RX1
PEX_TX1#
GND
PEX_TX1
PEX_RX0#
GND
PEX_RX0
PEX_TX0#
GND
PEX_TX0
PEX_REFCLK#
PRSNT1#
PEX_REFCLK
TV_C/HDTV_Pr
CLK_REQ#
GND
PEX_RST#
TV_Y/HDTV_Y
RSVD
GND
RSVD
TV_CVBS/HDTV_Pb
SMB_DAT
GND
SMB_CLK
VGA_RED
THERM#
GND
VGA_HSYNC
VGA_GRN
VGA_VSYNC
GND
DDCA_CLK
VGA_BLU
DDCA_DAT
GND
IGP_UCLK#
LVDS_UCLK#
IGP_UCLK
LVDS_UCLK
GND
GND
RSVD
LVDS_UTX3#
RSVD
LVDS_UTX3
RSVD
GND
IGP_UTX2#
LVDS_UTX2#
IGP_UTX2
LVDS_UTX2
GND
GND
IGP_UTX1#
LVDS_UTX1#
IGP_UTX1
LVDS_UTX1
GND
GND
IGP_UTX0#
LVDS_UTX0#
IGP_UTX0
LVDS_UTX0
GND
GND
IGP_LCLK#/DVI_B_CLK#
LVDS_LCLK#
IGP_LCLK/DVI_B_CLK
LVDS_LCLK
DVI_B_HPD/GND
GND
RSVD
LVDS_LTX3#
RSVD
LVDS_LTX3
GND
GND
IGP_LTX2#/DVI_B_TX2#
LVDS_LTX2#
IGP_LTX2/DVI_B_TX2
LVDS_LTX2
GND
GND
IGP_LTX1#/DVI_B_TX1#
LVDS_LTX1#
IGP_LTX1/DVI_B_TX1
LVDS_LTX1
GND
GND
IGP_LTX0#/DVI_B_TX0#
LVDS_LTX0#
IGP_LTX0/DVI_B_TX0
LVDS_LTX0
DVI_A_HPD
GND
DVI_A_CLK#
DDCC_DAT
DVI_A_CLK
DDCC_CLK
GND
LVDS_PPEN
DVI_A_TX2#
LVDS_BL_BRGHT
DVI_A_TX2
LVDS_BLEN
GND
DDCB_DAT
DVI_A_TX1#
DDCB_CLK
DVI_A_TX1
2V5RUN
GND
GND
DVI_A_TX0#
3V3RUN
DVI_A_TX0
3V3RUN
GND
3V3RUN

110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230

21

D

PEG_M_TXN1
PEG_M_TXP1
PEG_M_TXN0
PEG_M_TXP0
MXM_CD0#
MXM_CRMA

+3VS
R305
1
2
@ 8.2K_0402_5%

MXM_LUMA
MXM_COMP
M_RED
M_GRN
M_BLU
M_TXBCLK- 17
M_TXBCLK+ 17

M_TXB2- 17
M_TXB2+ 17
M_TXB1- 17
M_TXB1+ 17

C

M_TXB0- 17
M_TXB0+ 17
M_TXACLK- 17
M_TXACLK+ 17

M_TXA2- 17
M_TXA2+ 17
M_TXA1- 17
M_TXA1+ 17
M_TXA0- 17
M_TXA0+ 17
M_LCD_DAT 17
M_LCD_CLK
17
M_ENAVDD 17
M_PWM 17
M_ENBLT 17
DVI_DDC_DAT
35
DVI_DDC_CLK
35
+2.5VS
+3VS

1

ACES_88990-2D28_GF

B

C4

ACES_88990-2D28_GF

2

TV-Out Termination/EMI Filter

CRT Termination/EMI Filter

Place cloce to MXM connector JP39
M_LUMA

M_LUMA

16,35

M_RED

MXM_CRMA

MXM_CRMA

L9 1
2
CHB1608U301_0603

M_CRMA

M_CRMA

16,35

M_GRN

MXM_COMP

MXM_COMP

L7 1
2
CHB1608U301_0603

M_COMP

M_COMP

16,35

M_BLU

1

1
R317

150_0402_1%

150_0402_1%

C17
82P_0402_50V8J

1

2

C18

1

2

C19

1

2

C13
82P_0402_50V8J

1

2

C15

1

1

2

2

C14

R10

82P_0402_50V8J

R11

@ 150_0402_1%

2

R314

150_0402_1%

2

R316

2

2

82P_0402_50V8J

L4
1
2
HLC0603CSCC39NJT_0603
L5
1
2
HLC0603CSCC39NJT_0603
L2
1
2
HLC0603CSCC39NJT_0603

L1
1
2
HLC0603CSCCR11JT_0603
L6
1
2
HLC0603CSCCR11JT_0603
L3
1
2
HLC0603CSCCR11JT_0603

RED_LL
GREEN_LL

BLUE_LL

D_RED

D_RED

D_GREEN

35

D_GREEN

D_BLUE

D_BLUE

35
35

1

L8 1
2
CHB1608U301_0603

1

MXM_LUMA

1

MXM_LUMA

@ 150_0402_1%

1

R2
@ 150_0402_1%

2

L

1

Place those components as close as
MXMIII connector within 500 mils.

2

L

4.7U_0805_10V4Z

2

C3

1

2
18P_0402_50V8J

1

C7

C2

18P_0402_50V8J
2

18P_0402_50V8J

A

A

82P_0402_50V8J

82P_0402_50V8J

Place those components as close
as MXMIII connector within 500 mils.
Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

MXM III CONN
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

18

of

52

5

4

3

2

1

D

D

+5VS

2

+3VS

2 8.2K_0402_5%

PCI_DEVSEL#

R613 1

2 8.2K_0402_5%

PCI_STOP#

1

R616 1

2 8.2K_0402_5%

PCI_TRDY#

1

R89
R617 1

R611 1

2 8.2K_0402_5%

PCI_FRAME#

R619 1

2 8.2K_0402_5%

PCI_PLOCK#

R625 1

2 8.2K_0402_5%

PCI_IRDY#

330_0402_5%

C

+3VS

9/2

R106 1

2 8.2K_0402_5%

PCI_PIRQA#

R107 1

2 8.2K_0402_5%

PCI_PIRQB#

R105 1

2 8.2K_0402_5%

PCI_PIRQC#

R635 1

2 8.2K_0402_5%

PCI_PIRQD#

R626 1

2 8.2K_0402_5%

PCI_PIRQE#

R628 1

2 8.2K_0402_5%

PCI_PIRQF#

R624 1

2 8.2K_0402_5%

PCI_PIRQG#

R632 1

2@ 8.2K_0402_5%

PCI_PIRQH#

R631 1

2 8.2K_0402_5%

PCI_REQ0#

R610 1

2 8.2K_0402_5%

PCI_REQ1#

R607 1

2 8.2K_0402_5%

PCI_REQ2#

R627 1

2 8.2K_0402_5%

CPPE#

23
23

PCI_PIRQC#
PCI_PIRQD#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9

C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#

Interrupt
PIRQA#
PIRQB#
PIRQC#
PIRQD#

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

3

B15
C12
D12
C15

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2#
PCI_GNT2#

PCI_REQ4#
ICH_GPIO48
CPPE#
ALS_EN#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

C26
A9
B19

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

G8
F7
F8
G7

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

S

23
23

+3VS
CPPE#

15,35

5

PCI_REQ3#

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_PCIRST#

23
23
23
23

1
2

2

PCI_PLTRST#

CLK_PCI_ICH
15
PCI_PME# 23

1

12
13

23,24

R676

A

O
B

R66
@ 0_0402_5%
2
1

ACCEL_INT

MCH_ICH_SYNC#

2

11/23

2 R636
1
0_0402_5%
AE9
AG8
AH8
F21
AH20

PCI_RST#

C

R675

0_0402_5%

23

PCI_RST#

4

+3VS

PCI_SERR#
23,33
PCI_STOP# 23
PCI_TRDY#
23
PCI_FRAME#
23

PCI_PIRQG#

Y

R71
0_0402_5%
1

PCI_DEVSEL# 23
PCI_PERR#
23

23

A

U9

@ TC7SH08FU_SSOP5

PCI_IRDY#
23
PCI_PAR 23

PCI_PIRQE#

B

P

2 8.2K_0402_5%

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

G

PCI_REQ4#

R618 1

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

PCI

3

2 8.2K_0402_5%

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

14

PCI_PERR#

R615 1

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

17

P

PCI_SERR#

2 8.2K_0402_5%

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

ALS_EN

Q15
2N7002_SOT23

ALS_EN# 2
G

G

2 8.2K_0402_5%

R623 1

U10B

PCI_AD[0..31]

7

R622 1

23

ALS_EN
D

11

1

2

0_0402_5%
U11D
SN74LVC08APW_TSSOP14

PLT_RST#

PLT_RST#

7,20,21,23,25,27,32,33

27

7

ICH7M_B0_BGA652
R612 1

2 8.2K_0402_5%

ICH_GPIO48

B

B

Place closely pin A9

2

CLK_PCI_ICH
ALS_EN#

1

R621
@10_0402_5%

R83

1
@ 8.2P_0402_50V

SPI@ 1K_0402_5%

1
2

C145

2

A

A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

ICH7-M(1/4)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

19

of

52

5

4

1 18P_0402_50V8J

IN

1

R96

NC

OUT

4

10M_0402_5%

ICH_RTCX2

ICH_RTCRST# AA3
R629

CMOS_CLR1
1
2

ICH_INTVRMEN W4
SM_INTRUDER# Y5

1
2
1M_0402_5%

+RTCVCC

SHORT PADS

V3
U3
U5
V4
T5
AC97_BITCLK_MDC

33_0402_5%

1

2 R100

AC97_BITCLK_CODEC

33_0402_5%

1

2 R113

33_0402_5% 1

2 R240

34
28

34

AC97_SYNC_CODEC
34

28

AC97_RST#_MDC

AC97_RST#_CODEC

33_0402_5%

1

2 R253

U1
R6

33_0402_5% 2

1 R630

AC97_RST#

R5

AC97_SDIN0
AC97_SDIN1

T2
T3
T1

28
34

C

28

AC97_SDOUT_CODEC
34

33_0402_5% 2

1 R245

33_0402_5% 2

AC97_SDOUT

T4

LAN_CLK
LAN_RSTSYNC

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

AF18

LAN_RXD0
LAN_RXD1
LAN_RXD2

FERR#
GPIO49 / CPUPWRGD

LAN_TXD0
LAN_TXD1
LAN_TXD2

IGNNE#
INIT3_3V#
INIT#
INTR

ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

R103

2

332K_0402_1%
15
15

CLK_PCIE_SATA#
CLK_PCIE_SATA

1

CLK_PCIE_SATA#
CLK_PCIE_SATA

R620
R101

1

@ 0_0402_5%

24.9_0402_1%

AF1
AE1
AH10
AG10

+3VS

RCIN#
SMI#
NMI
STPCLK#

4.7K_0402_5% 2
8.2K_0402_5% 2

1 R609
1 R608

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

B

AG16
AH16
AF16
AH15
AF15

AC3
AA5

LPC_DRQ#0
LPC_DRQ#1

AB3

LPC_FRAME#

LPC_DRQ#0
LPC_DRQ#1

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP

IDE
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

H_CPUSLP_R#

AF24
AH25
AG26

DPRSLP# R58
H_DPSLP#
R54
H_FERR#

AG24

H_PWRGOOD

AG22
AG21
AF22
AF25

H_IGNNE#
FWH_INIT#
H_INIT#
H_INTR

27,31,32,33

10K_0402_5%
1 R61
GATEA20 33
H_A20M# 4

1 0_0402_5%
1 56_0402_5%
4

2

+3VS

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
RSVD
GND
V12
V12
V12

T14

PAD

2

H_DPRSTP# 4,45
H_DPSLP# 4
+VCCP

H_FERR#

H_PWRGOOD
H_IGNNE#
T26
PAD
H_INIT# 4
H_INTR 4

AG23
AF23
AH24

H_SMI#
H_NMI

AH22

R598 2
1
0_0402_5%
THRMTRIP_ICH#

4

4

9/8
+3VS +VCCP

GND

KB_RST#

33

DDREQ

H_THERMTRIP#

H_STPCLK#

H_STPCLK#

11/18
+5VS

32

RTC1

2

R423
1
2
1K_0402_5%

+
RTC2

JP28

1

2

IDE_LED#

1

3900P_0402_50V7K
SATA_TXN0
2

1

3900P_0402_50V7K
SATA_TXP0
2

C149
SATA_TXP0_C

2

1U_0603_10V4Z

BATT1

L

W=20mils

-

2
+5VS

2

RTC BATTERY

+5VS
+5VS

1
R499 2
R503

1

3900P_0402_50V7K
SATA_RXP0
2

C173
SATA_RXP0_C

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#
B

PD_DACK#
PDIAG# R509 1
PD_A2
PD_CS#3
W=80mils

2

2

+5VS

+5VS
+5VS
+5VS

1

C104

100K_0402_5%

0.1U_0402_16V4Z

C147

1
C98

1
C100

1
C101

1
C102

10U_0805_10V4Z
2

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z

PCB-MB

2

4

U11B
SN74LVC08APW_TSSOP14

A

O
B

L

Place component's closely IDE CONN. JP37

P

PLT_RST#

G

3900P_0402_50V7K
SATA_RXN0
2

0.1U_0402_16V4Z

6
R88

2

1 33_0402_5% ODD_RST#
PLT_RST_B# 27,31

7

1

C156

+3VS

5
C175
SATA_RXN0_C

2

+5VS

ZZZ

7,19,21,23,25,27,32,33

A

0.1U_0402_16V4Z

2
1
2
4
3
4
6
5
6
8
7
8
10
9
10
12
11
12
14
13
14
15
16 16
17
18 18
19
20 20
21
22 22
23
24 24
25
26 26
27
28 28
29
30 30
31
32 32
33
34 34
35
36 36
37
38 38
39
40 40
41
42 42
43
44 44
45
46 46
47
48 48
49
50 50
OCTEK_CDR-50DU1

SEC_CSEL
2
1@ 4.7K_0402_5%
470_0402_5%

E&T_7651

14

45@ CR2025

2

1

C151

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

8/24

1

L Near ICH7(U26) side.

0.1U_0402_16V4Z

Place component's closely IDE CONN. JP45

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
IDE_DSP#

1

DAN202U_SC70
C150
SATA_TXN0_C

1

C153

JP13

R512

3
1

2

ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

CH751H-40_SC76

R430

1
2
100_0402_5%
C403

10U_0805_10V4Z

10K_0402_5%

D32

1

C148

4

D35

1

1

ODD CONN

+3VL

7/6

23

C

2

ICH7M_B0_BGA652

+RTCVCC

+5VS

4,7

R1031 must be placed close to U26.AF26
within 2" and R1030 must be placed close
to R1031 within 2".

PD_CS#1
PD_CS#3

PD_DREQ

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

+5VS

1 R591
2
24.9_0402_1%

L

AE15

SATA_RXN0
SATA_RXP0

56_0402_5%

H_STPCLK#

PD_A0
PD_A1
PD_A2

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

D

SATA_TXP0
SATA_TXN0

R592

H_SMI# 4
H_NMI 4

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

S1
S2
S3
S4
S5
S6
S7

OCTEK_SAT-22DN1G_NR

L

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

24

1 10K_0402_5%

2

KB_RST#

AE16
AD16

DCS1#
DCS3#

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AG27

GND
A+
AGND
BB+
GND

31

LPC_FRAME#

GATEA20
H_A20M#

AH17
AE17
AF17

JP20

GND

AE22
AH28

AF26

DA0
DA1
DA2

SATALED#

2

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

R60

THERMTRIP#

ACZ_SDOUT

1

AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6

ICH_INTVRMEN

CPUSLP#

TP1 / DPRSTP#
TP2 / DPSLP#

1 R247
IDE_LED#

AA6
AB5
AC4
Y6

2
A20GATE
A20M#

SATA

R102
@ 332K_0402_1%

2

AC97_SDIN0
AC97_SDIN1

+RTCVCC

1

+3VALW

AC97_SDOUT_MDC

LFRAME#
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

1 R269

2

AC97_BITCLK
AC97_SYNC

33_0402_5%

LDRQ0#
LDRQ1# / GPIO23

AC-97/AZALIA

28

AC97_SYNC_MDC

U7
V6
V7

INTVRMEN
INTRUDER#

LAN

W1
Y1
Y2
W3

C159
1U_0603_10V4Z
1
2

RTCRST#

LAD0
LAD1
LAD2
LAD3

27,31,32,33

1

2

1 18P_0402_50V8J

2

RTXC1
RTCX2

LPC

2

AB1
AB2

LPC_AD[0..3]

RTC

C157
R645 1
20K_0402_5%

SATA CONN
U10A

1

NC

3

2

2

32.768KHZ_12.5P_1TJS125BJ2A251

+RTCVCC

1

ICH_RTCX1

Y1

D

2

1

2

CPU

C158

3

A

L Near Device(JP45) side.
Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

ICH7-M(2/4)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

20

of

52

5

4

3

2

1

Place closely pin B2

1

L

R79

2

2
3

7
ICH_SMB_DATA

2

G

2

G

A21

23,31,32,33

3

23,31,32,33 SIRQ
4 THERM_SCI#

PWROK_ICH7

V_3P3_LAN
R603
27

+3VALW

1

PCIE_WAKE#

+3VALW

2
0_0402_5%

R600
10K_0402_5%
R589 1
2 LINKALERT#

7,45

10K_0402_5%
R594 1
2 OCP#

VGATE_INTEL
7,33 PM_POK

1

PWROK_ICH7

1

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

27 PCIE_RXN2
27 PCIE_RXP2
27 PCIE_TXN2
27 PCIE_TXP2

0.1U_0603_16V7K
0.1U_0603_16V7K

2
2

SATA
GPIO

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

GPIO11 / SMBALERT#
GPIO18 / STPPCI#
GPIO20 / STPCPU#
GPIO26
GPIO27
GPIO28
GPIO32 / CLKRUN#

PWROK
GPIO16 / DPRSLPVR
TP0 / BATLOW#
PWRBTN#
LAN_RST#
RSMRST#

AF19
AH18
AH19
AE19

AC1
B2

WAKE#
SERIRQ
THRM#
VRMPWRGD

GPIO

GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

Need update symbol
1 R67
2
0_0402_5%

MXM_THERM#

HDD_STP

1
@ 10_0402_5%

CLK_14M_ICH
CLK_48M_ICH

C20
B24
D23
F22

SLP_S3#
SLP_S4#
SLP_S5#

AA4

PM_POK

AC22

DPRSLPVR

C21

ICH_LOW_BAT#

C23

ON/OFFBTN#

C19

PLT_RST#

Y4

2

CLK_14M_ICH
CLK_48M_ICH

1

C541

1 C133
1 C134

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

F26
F25
E28
E27

1 C127
1 C128

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

H26
H25
G28
G27

10K_0402_5%

D14
PREP# 1

2

ISO_PREP#

35 PCIE_RXN4
35 PCIE_RXP4
35 PCIE_TXN4
35 PCIE_TXP4

CH751H-40_SC76

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

1 C129
1 C130

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

P
8

A

9

M24_RST#

B

10

PLT_RST#

O
7

VGA_RST#

G

14

+3VS

PLT_RST#

L

7,19,20,23,25,27,32,33

U11C
SN74LVC08APW_TSSOP14

SPI_CLK
SPI_CS#

R1292/R1293 should be placed
less than 100 mils from U26.
SPI_CLK
SPI_CS#

SPI_SI
SPI_SO

R98

SPI@ 47_0402_5%
1
2

R99

SPI@ 47_0402_5%
1
2

PERn1
PERp1
PETn1
PETp1
PERn2
PERp2
PETn2
PETp2

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

M26
M25
L28
L27

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

PERn6
PERp6
PETn6
PETp6

R2
P6
P1

SPI_CLK
SPI_CS#
SPI_ARB

P5
P2

SPI_MOSI
SPI_MISO

SPI

32
32

32 SPI_SI
32 SPI_SO
+3VALW
R97
1
2 SPI_CS#
SPI@ 10K_0402_5%
R110
1
2 SPI_SI
SPI@ 10K_0402_5%
R111
1
2 SPI_SO
SPI@ 10K_0402_5%

29
29
30
30
18

USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#

D3
C4
D5
D4
E5
C3
A2
B3

A

@ 4.7P_0402_50V8C

2

@ 4.7P_0402_50V8C

15
15

T16 PAD
SLP_S3#
SLP_S4#
SLP_S5#

18,25,27,28,29,33,35,36,40,43,44
44
36,44

R601
8.2K_0402_5%
2
1

R633
PM_POK 7,33
1
2 10K_0402_5%
DPRSLPVR 7,45

PM_RSMRST#
R634 10K_0402_5%
1
2

ON/OFFBTN#

34

PM_RSMRST#

33

L

1

LOW_BAT#

33

CH751H-40_SC76
R74
10K_0402_5%
2
1

+3VL

DPRSLPVR 2

1
R599
@ 100K_0402_5%

GPIO9_SB
E20
T28 PAD
CB_IN#
A20
GPIO12_SB
F19
T30 PAD
LID_SW#
E19
LID_SW# 17,34
R4 LANLINK_STATUS#_SB
LANLINK_STATUS#_SB
25
GPIO15_SB
E22
T25 PAD
XMIT_OFF
R3
XMIT_OFF 27
BT_OFF
D20
BT_OFF 30
NPCI_RST#
AD21
NPCI_RST# 31,33
AD20
R605 1
AE20
2
DOCK_ID
35
@ 0_0402_5%
GPIO39_SB
T29 PAD

THERM_SCI#

+3VALW

D13

2

2
R602

1
@ 0_0402_5%

LOM_LOW_PWR

25

1

CABLE_DETECT

25,26

C

J16

2

PAD-SHORT 2x2m

R1015 need be removed when ICH7M ES2 samples used,
but need be stuffed when ICH7M ES1 samples used.

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

USB

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

7
7
7
7

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

7
7
7
7

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

7
7
7
7

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD25
AD24
AC28
AC27

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

7
7
7
7

DMI_CLKN
DMI_CLKP

AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

C25
D25

DMI_IRCOMP

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS

D2
D1

USBRBIAS

CLK_PCIE_ICH#
CLK_PCIE_ICH
R588
1

24.9_0402_1%
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

B

15
15

Within 500 mils
+1.5VS

RP20
USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

30
30
32
32
29
29
29
29
30
30
30
30
35
35
35
35

4
3
2
1

5
6
7
8

R1284,R1285 and R1286 should
be placed close to U26.

18,47

MXM_CD1#

MXM_CD1#

1
R639

+3VALW

10K_1206_8P4R_5%

R641 22.6_0402_1%
1
2

USB_OC#4

R638
10K_0402_5%
1
2

USB_OC#5

R644
10K_0402_5%
1
2

MXM_CD0#

R642
10K_0402_5%
1
2

R643
100K_0402_5%
MXM_CD1#_R 1
2

Within 500 mils

ICH7M_B0_BGA652

L

C542
D

32

1 R72
2
100_0402_5%

ICH_SUSCLK

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

ICH7M_B0_BGA652
18

11/22

R76

2

2

AC21
AC18
E21

GPIO0 / BM_BUSY#

DIRECT MEDIA INTERFACE

+3VS

10K_0402_5%

18

AD22

SPKR
SUS_STAT#
SYS_RST#

PCI-EXPRESS

+3VALW

R78

PREP#

AC19
U2

R640

@ 10_0402_5%

U10D

11/21

26,35

AG18

11/14

LP_EN#

0_0402_5%
2
2 @ 0_0402_5%

1
1

25 PCIE_RXN1
25 PCIE_RXP1
25 PCIE_TXN1
25 PCIE_TXP1

10K_0402_5%
R606 1
2 LID_SW#

B

R64
R59

RUNSCI_EC#
ISO_PREP#
LP_EN#

33 RUNSCI_EC#
35 ISO_PREP#
1
2
10K_0402_5%
25

10K_0402_5%
R596 1
2 XDP_DBRESET#

B21
E23

ICH_PCIE_WAKE# F20
SIRQ
AH21
THERM_SCI#
AF20

1

G

Q8
BSS138_SOT23

T31
T32

2

LOM_PCIE_WAKE#

FWH_WP#
FWH_TBL#

D

25

T27

GPIO27_SB
T49
1
2 GPIO28_SB
0_0402_5%
PM_CLKRUN#
PM_CLKRUN#
PAD
PAD

S

8.2K_0402_5%
1
2 PM_CLKRUN#

AC20
AF21

PAD
M24_RST# R586
R604
1K_0402_5%
1
2

+3VALW

R73

B23

11/14

@ 10K_0402_5%
1
2 THERM_SCI#

R63

OCP#
H_STP_PCI#
H_STP_CPU#

AB18

RI#

GPIO

D

S

C

A19
A27
A22

GPIO26_SB
PAD

+5VS

10K_0402_5%
1
2 SIRQ

A28

SB_SPKR
LPC_PD#
XDP_DBRESET#
PM_BMBUSY#

PM_BMBUSY#

4,47 OCP#
15 H_STP_PCI#
15 H_STP_CPU#

ICH_SMB_CLK
1
Q14
@ 2N7002_SOT23

3

+3VS

R68

ICH_RI#

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

SYS

D

S

@ 2N7002_SOT23
Q11
1

ICH_SMBCLK

ICH_SMBCLK

28 SB_SPKR
32,33 LPC_PD#
4 XDP_DBRESET#

@ 2.2K_0402_5%

ICH_SMBDATA

ICH_SMBDATA

R587
1
2
8.2K_0402_5%
R84

@ 2.2K_0402_5%

4,13,14,15,18,25,27

C22
B22
A26
B25
A25

+3VALW

1

1

+3VS

1

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

Clocks

R77

SMB

2 0_0402_5%
2 0_0402_5%

1
1

POWER MGT

1

2

R82
ICH_SMBCLK
ICH_SMBDATA

2

10K_0402_5%

1

10K_0402_5%
D

U10C

2.2K_0402_5%

R637

2

R593
2.2K_0402_5%

4,13,14,15,18,25,27

R213,R233 change from 2.2Kohm to
10Kohm when Q23,Q24,R206,R204 stuffed.

R81

2

2

2
R595

R75

CLK_14M_ICH

1

+3VALW

1

+3VALW

Place closely pin AC1

CLK_48M_ICH

A

9/14

2 MXM_CD1#_R
0_0402_5%

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

ICH7-M(3/4)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

21

of

52

5

4

3

2

1

+VCCP
U10F

2

D15
CH751H-40_SC76

C505

2

C507

2

0.1U_0402_16V4Z

9/15

1

1

2
0.1U_0402_16V4Z

1

2

100_0402_5%

1

ICH_V5REF_RUN

1

2

1

C517
0.1U_0402_16V4Z

2

Place closely pin
D28,T28,AD28.

C515
0.1U_0402_16V4Z

2

1

+5VALW +3VALW

R90

D17

C

1

CH751H-40_SC76

2

10_0402_5%

1

2

ICH_V5REF_SUS
C532
0.1U_0402_16V4Z

+3VS

C508
0.1U_0402_16V4Z

1

2

Place closely pin AG28 within 100mlis.
+1.5VS_DMIPLLR

B27

1

2

0_0805_5%

C527

+1.5VS

1

2

+3VALW
C537
0.1U_0402_16V4Z

0.1U_0402_16V4Z

B

C504
0.01U_0402_16V7K

R585

2

0.5_0805_1%

1

2

+1.5VS_DMIPLL

1

C534
0.1U_0402_16V4Z

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

1

2

Place closely pin AG5.
+3VS

1

2

AD2

+1.5VS
C146
1U_0603_10V4Z

1

2

+1.5VS
C543
0.1U_0402_16V4Z

1
T18
T17

PAD
PAD

1

2

PAD-SHORT 2x2m

1

J17

A

+3VS

1

E3

VccSus3_3[19]

C1

VccUSBPLL

ICH_SUSLAN

J18
+3VALW

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]

VccSATAPLL

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

V5
V1
W2
W7

2

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

AA2
Y7

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccDMIPLL

Vcc3_3[2]

ICH_AA2
ICH_Y7

Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA

Vcc3_3[1]

AH11

Place closely pin AG9.

1

2

AG28

+1.5VS

2

C521
0.1U_0402_16V4Z

R584

1

+1.5VS_DMIPLL

C503
10U_0805_10V4Z

+1.5VS

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

1
C519

1

C513

2

1

+

C131

2

2

9/15
1U_0603_10V4Z

220U 6.3V M

U6

+3VS

R7

C523
1
2

AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

+3VS

1

2

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

1

2

1

2

2

C518
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
2
C512
0.1U_0402_16V4Z
1
2

C511
0.1U_0402_16V4Z

C520
4.7U_0805_10V4Z

1

2

+3VS

W5

+RTCVCC

P7
1
A24
C24
D19
D22
G19

2

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

1

2

1

C533
0.1U_0402_16V4Z

1

C529
0.1U_0402_16V4Z

AB17
AC17

2

2

+3VALW
C528
0.1U_0402_16V4Z

1

1

2

2

+3VALW
C538
0.1U_0402_16V4Z

+1.5VS

T7
F17
G17
AB8
AC8

1

2

VccSus1_05[1]

K7

C530 0.1U_0402_16V4Z
ICH_K7
PAD

T19

VccSus1_05[2]
VccSus1_05[3]

C28
G20

ICH_C28
ICH_G20

T13
T15

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

1

+VCCP

+3VS

C531
0.1U_0402_16V4Z

220U 6.3V M

C506

V5REF_Sus

0.1U_0402_16V4Z

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C536
0.1U_0402_16V4Z

+

U10E

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C535
0.1U_0402_16V4Z

2

1
R614

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

1
C132

V5REF[2]

F6

0.1U_0402_16V4Z
+3VS

AD17
ICH_V5REF_SUS

D

+5VS

V5REF[1]

C525
0.1U_0402_16V4Z

+1.5VS

G10

C522
0.1U_0402_16V4Z

ICH_V5REF_RUN

A1
H6
H7
J6
J7

PAD
PAD
+1.5VS

1

2

C516
0.1U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

D

C

B

ICH7M_B0_BGA652

ICH7M_B0_BGA652
C540
A

2

2

0.1U_0402_16V4Z

PAD-No SHORT 2x2m

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

ICH7-M(4/4)
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

22

of

52

+VCC_SD

SDCLK_SMRE#
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

A4
C5
C6
A5
B5
E6
E7

SMCLE
SC_CD#

SC_CD#

1 R117
2
0_0402_5%
SC_CLK_R
SC_RST
24 SC_RST
0_0402_5% 1
2 R143
+SC_PWR
SC_DATA
24 SC_DATA
SC_OC#
R129
@ 10K_0402_5%
R130
@ 10K_0402_5%
SM_PHYS_WP#/SC_FCB
SM_RB#/SC_RFU

24

SC_CLK

B4

SC_CLK

9/10
+3VS

9/10

F3
E2
F5
G6
E1
F2
G5
E3
D1

MS_CLK/SD_CLK/SM_EL_WP#
MS_BS/SD_CMD/SM_WE#
MS_DATA3/SD_DAT3/SM_D3
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1
MS_SDIO(DATA0)/SD_DAT0/SM_D0
SD_CLK/SM_RE#/SC_GPIO1
SD_CMD/SM_ALE/SC_GPIO2
SD_DAT0/SM_D4/SC_GPIO6
SD_DAT1/SM_D5/SC_GPIO5
SD_DAT2/SM_D6/SC_GPIO4
SD_DAT3/SM_D7/SC_GPIO3
SD_WP/SM_CE#
SM_CLE/SC_GPIO0

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#

@ 15P_0402_50V8J

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

G1
H5
H2
H1
J1
J2
J3

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
FM_LED#

2
2
2
2
2

1
1
1
1
1

G2
G3

220_0402_5%
220_0402_5%

2
2

1 R146
1 R134

PCI_PERR#
PCI_SERR#
PCI_REQ2#
PCI_GNT2#

SM_RB#
SDCLK_SMRE#
SDWP#_SMCE#
SM_CD#

2

SMCLE

4

XD_CD#

1
2
1

TAITW_R007-010-N3

56.2_0603_1%
R195

CLK_PCI_PCM
15
PCI_RST# 19,24
PLT_RST# 7,19,20,21,25,27,32,33

1

R201

C207
1U_0603_10V4Z

XTPBIAS0
XTPB0XTPB0+
XTPA0XTPA0+

28

PCI_PIRQC#
19
PCI_PIRQD#
19
PCI_PIRQG#
19
SIRQ 21,31,32,33
PCI_PIRQE#
19

2

56.2_0603_1%
JP17

1
2
3
4
R187

1

2 GRST#
0_0402_5%

21,31,32,33

3

AMP_440168-2

R183

56.2_0603_1%

R124
PRST#

C189

1 R135

2

+VCC_MS+VCC_SM_XD

XD_CD#

270P_0603_50V8J
220_0402_5%

2
2

40
39
1
44

R17

PCI7612ZHK_PBGA257

PCM_SPK

1
2
43K_0402_5%
+3VS

56.2_0603_1%

1

R186
5.1K_0603_1%

2

+VCC_MS +3VS

L

CLOSE TO CHIP

2
0_0402_5%

2 SC_FCB
0_0402_5%
2 SM_PHYS_WP# R153 1
2
@ 0_0402_5%
7612@ 0_0402_5%

R159 1
2 XD_CD#/SM_PHYS_WP#
7612@ 0_0402_5%
R182 1
2 SM_CD#
7611@ 0_0402_5%

PWR_CTRL_1/SM_R/B#
MC_PWRON#
SC_FCB

1
2
3
4

R91

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
OC#

L

CLOSE TO CHIP

XTPBIAS1
XTPB1+
XTPB1-

10K_0402_5%

R193
1K_0402_5%

TPS2061IDGN_MSOP8~N

24

XD_CD#/SM_PHYS_WP#

C152 2

1 10U_0805_10V4Z

C154 2

1 0.01U_0402_16V7K

1K_0402_5%

2

R131 1
7612@

24

1

SC_RFU

R200

1

2

C212
1U_0603_10V4Z
4

24

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
TI PCI7612 PCI/CardReader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

A

2

+VDDPLL

2 SC_RFU
0_0402_5%
R1421
2 SM_RB#
7611@ 0_0402_5%
R1401

L

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MS_CD#
MSBS_SDCMD_SMWE#

15
14
16
18
19
17
13
20

R231

R1411

R152 1

2

XD-VCC
XD-CD
GND
GND

SD_DAT3 10_0402_5%2 R122 MSD3_SDD3_SMD3
11
SD_DAT2 10_0402_5%2 R123 MSD2_SDD2_SMD2
12
SD_DAT1 10_0402_5%2 R119 MSD1_SDD1_SMD1
6
SD_DAT0 10_0402_5%2 R120 MSD0_SDD0_SMD0
7
SDWP#_SMCE#
5
10 0_0402_5% 1
2 R121 MSBS_SDCMD_SMWE#
8 0_0402_5% 1
2 R118 MSCLK_SDCLK_SMELWP#
9
Place the parts close to JP41
4
+VCC_SD
SD_CD#
42
41

1

SM_PHYS_WP#/SC_FCB

1
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-SCLK
MS-INS
MS-BS
MS-VCC

SM-LVD
SM-CD-SW
SM_-VCC / XD_-VCC
#SM_R/-B / XD_R/-B
#SM_-RE / XD_-RE
#SM_-CE / XD_-CE
#SM_-CD
SM-CD-COM
SM-CLE / XD-CLE

19
19,33
19
19

PM_CLKRUN#

K2

Q27
2N7002_SOT23

SD_CD#
1
@ RB751V_SOD323
SM_CD#
1
@ RB751V_SOD323

2
D21
2
D22

SD-DAT3
SD-DAT2
SD-DAT1
CONN SD-DAT0
SD-WP-SW
SD-CMD
SD_CLK
SD-VCC
N/C
SD-CD-SW
SD-CD-COM

+3VS

R145
R133
R132
R144
R137

1

2

1

PCI_PAR 19
PCI_FRAME#
19
PCI_TRDY#
19
PCI_IRDY#
19
PCI_STOP# 19
PCI_DEVSEL# 19

PCM_SPK

Q22
2N7002_SOT23

3

25
3
29
26
27
28
30
2
38

5 IN 1

SM_WP-IN / XD_WP-IN
SM-WP-SW
#SM_-WE / XD_-WE
#SM-ALE / XD-ALE

U12
SM_RB#/SC_RFU

1

2

1

1

1

1

1

SPKROUT

H3

2

2
2

2

2

2

2

2
2

0.1U_0402_16V4Z

R151
43K_0402_5%
PCM_SPK

VSSPLL

AGND
AGND
AGND

C168

35
43
36
37

SM-D0 / XD-D0
SM-D1 / XD-D1
SM-D2 / XD-D2
SM-D3 / XD-D3
SM-D4 / XD-D4
SM-D5 / XD-D5
SM-D6 / XD-D6
SM-D7 / XD-D7

2

2

R14
U13
U14

1

C164

R161 2
1 PCI_AD22
100_0402_5%

10K_0402_5%

1

JP24

34
33
32
31
21
22
23
24

SM_CD#

J5

VR_EN#

2

@ 10_0402_5%

19

+VCC_SM_XD

SUSPEND#

1
R149

PCI_PME#

R116 MSCLK_SDCLK_SMELWP#
SM_PHYS_WP#
1
2
7611@ 33_0402_5% MSBS_SDCMD_SMWE#
SDCMD_SMALE

CLK_PCI_PCM
0_0402_5%
PRST#
R150 1
2
R136 1
GRST#
2
CB_PME#
@ 0_0402_5%

SCL
SDA

1

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

L1
K3
K5
L5

SC_CD#
SC_CLK
SC_RST
SC_VCC_5V
SC_DATA
SC_OC#
SC_PWR_CTRL
SC_FCB
SC_RFU

TEST0

3
Q20
@ 2N7002_SOT23

PCLK
PRST#
GRST#
RI_OUT#/PME#

CLK_PCI_PCM

P12

U7
R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

CB_PME#

3

1

A7
E8
B6
A6
C7
B7

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

@ 10K_0402_5%

D

FM_LED# 2
G
Q30
S
@ 2N7002_SOT23

R148

1

2

2 22_0402_5%
MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

P2
U5
V7
W10

3

2

24

1

C/BE3#
C/BE2#
C/BE1#
C/BE0#

MC_PWRON#

R165

1

MSCLK_SDCLK_SMELWP#

SD_CD#
MS_CD#
SM_CD#

SDCLK_SMRE#

SD_CD#

1

E9
A8
B8

MC_PWR_CTRL_0
MC_PWR_CTRL_1/SM_R/B#

MS_CD#

2

XI

R164
10K_0402_5%

MSBS_SDCMD_SMWE#

+3VS

10K_0402_5%

1

XO

SM_RB#
+3VS

1

R127

2

SD_CD#
MS_CD#
SM_CD#
R175

+3VS

1

PHY_TEST_MA

PCI7612/7412

C8
F8

100K_0402_5%

2

TPBIAS1
TPA1P
TPA1N
TPB1P
TPB1N

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

1

TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N

M1
M2
M3
M6
M5
N1
N2
N3
P3
R1
R2
P5
R3
T1
T2
W4
W7
R8
U8
V8
W9
V9
U9
R9
V10
U10
R10
W11
V11
U11
P11
R11

2

P1
W8

U19
P15
VDDPLL_33
VDDPLL_15

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

X_OUT
2
24.576MHZ_16P_1BG24576CK1A
10P_0402_50V8J
MC_PWRON#
PWR_CTRL_1/SM_R/B#

100K_0402_5%

R154
@47K_0402_5%

10U_0805_10V4Z

+3VS

1

R19

10U_0805_10V4Z

9/6

2

1

X_IN

R126

SDWP#_SMCE#

2

C241 1

R115

1

D

Y2

R18

R125

C178

2

S

2

X_OUT

R114

Keep +VDD_PLL33/+VDDPLL33/+VDD_PLL
/+VDDPLL at least 10 mils

L

X_IN

2

10P_0402_50V8J
R237
@ 1M_0402_5%

L12
1
2+VDDPLL33
CHB1608U301_0603
+VDDPLL
2
1
C232 0.1U_0402_16V4Z

R128
@47K_0402_5%

2

G

P17

+VDD_PLL

1
C165

100K_0402_5%

D

1 R230
2
@ 4.7K_0402_5%

+3VS

+VDD_PLL33

22K_0402_5%

S

W17
V16
W16
V15
W15

XTPB1+
XTPB1-

+3VS

D

XTPBIAS1

PAD-SHORT 2x2m

0.1U_0402_16V4Z

S

R13
V14
W14
V13
W13

2

G

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

R0
R1

J7

G

R228 6.34K_0402_1%
T18
1
2
T19

AVDD_33
AVDD_33
AVDD_33

U16B

VR_PORT
VR_PORT

P13
P14
U15

2

2

VCCP
VCCP

1U_0603_10V4Z

K1 C169
K19

1

1U_0603_10V4Z C234

0.01U_0402_16V7K
C230

1U_0603_10V4Z
C219

10U_0805_10V4Z
C227

2

2

J6
PAD-No SHORT 2x2m

G

2

1

0.1U_0402_16V4Z
1
2
0_0805_5%
1
1
C174
C185

G

2
1

1

1

+VCC_MS
+VCC_SM_XD
SI2301BDS_SOT23
Q28
3
1
D

1
2
0_0805_5%

+VCC_MS
+VCC_SD
SI2301BDS_SOT23
Q21
3
1

S

PCI_CBE#[0..3]

1

3

+VCC_MS

R173

D

R229

PCI_CBE#[0..3]

C242 1

+3VS

PCI_AD[0..31]

PCI_AD[0..31]

E

S

19

+3VS_CBVCCP

D

2

+3VS_CBPLL

+3VS
19

C

1

B

1

A

B

C

D

Friday, November 25, 2005

Sheet
E

23

of

52

2

E13
E18
H18
L17

S1_A13
S1_A23
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16_C
1 R227
2 S1_A16
33_0402_5% S1_RDY#
CPS
+3VS
CLK_48M_CB
15 CLK_48M_CB
S1_A22
S1_BVD2
R189 1
S1_RST
2 CPS
4.7K_0402_5%

1

CLK_48M_CB

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

H14
E19
F17
G18
F19
H15
G19
C12
C14
G17
A12
A11
F18
E12
R12
F1
G15
B12
C15
N15
B11
A13
B16

R147

C202

C228
0.1U_0402_16V4Z

0.1U_0402_16V4Z

A15
J19

2

19,23

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

PCI7612/7412

RSVD/D2
RSVD/A18
RSVD/D14
RSVD/VD0/VCCD1#

XD_CD#/SM_PHYS_WP#

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

DATA
CLOCK
LATCH
RESET#
OC#
SHDN#

+S1_VPP
+SC_PWR

8
19

+S1_VCC

9
10

PCI_RST#

DATA/VD2/VPPD1
CLOCK/VD1/VCCD0#
LATCH/VD3/VPPD0

A2
A17
A18
B1
B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3
D17
D18
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18
E5

Near to PCMCIA slot.
+S1_VCC

17
18
1

2

1

C211
10U_0805_10V4Z

2

+S1_VPP

1

2

1

C201
10U_0805_10V4Z

C200
0.1U_0402_16V4Z

S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#
C231
1
2

S1_CD1#

S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5

100P_0402_50V8J
C197
1
2

S1_CD2#

100P_0402_50V8J
S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23

B10 S1_D2
H17 S1_A18
M19 S1_D14

S1_A15
S1_A22
S1_A16_C

+3VS

C4

43K_0402_5%
R160 1
2
@ 43K_0402_5%
R166 1
2

A3

XD_CD#/SM_PHYS_WP#

B9
A9
C9

2

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1

CB_DAT
CB_CLK
CB_LATCH

+S1_VPP
+S1_VCC
XD_CD#/SM_PHYS_WP#

CB_CLK

23

S1_RDY#
S1_A21
S1_WE#
S1_A20
S1_A14
S1_A19
S1_A13
S1_A18
S1_A8
S1_A17

33

S1_A9
S1_IOWR#
S1_A11
S1_IORD#
S1_OE#
S1_VS1
S1_A10

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+SC_PWR

S1_CE2#
S1_CE1#
S1_D15
S1_D7
S1_D14
S1_D6
S1_D13

1
1

R208

+SC_PWR

1

2

@ 10K_0402_5%

2

C218
0.1U_0402_16V4Z

S1_D5
S1_D12
S1_D4
S1_D11
S1_D3
S1_CD1#

R168

2

@ 22K_0402_5%

1

R169

C199

1

SC_RST

1

SC_DATA

1
C180

R190

1

C184

AVCC
AVCC

GND

1

BVCC
BVCC

NC
NC
NC
NC

1

11

2

23
22
16
6

2

1

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

2

NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE
GND
NONE
NONE
NONE
NONE
I/O
NONE
NONE
GND
VCC
NONE
NONE
NONE
NONE
RST
DET2
GND
VPP
CLK
NONE
GND
NONE
NONE
DET1
RFU4
NONE
GND
RFU8
NONE
NONE
NONE
NONE
NONE
NONE
GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE
GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE
GND
NONE
NONE
NONE
NONE
NONE
NONE
GND
GND

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150

2

SC_DATA

SC_DATA

23

+SC_PWR

SC_RST

SC_CLK

SC_CD#
SC_FCB
SC_RFU

SC_RST

23

SC_CLK

23

SC_CD#
SC_FCB

23
23

SC_RFU

23

3

TYCO_1123088-1_LT

@ 22K_0402_5%
@ 470P_0402_50V7K

GND
GND
CD2#
WP
D10
D2
D9
D1
GND
D8
D0
STSCHG#
A0
SPKR#
A1
REG#
GND
A2
INPACK#
A3
WAIT#
A4
RESET
A5
GND
VS2#
A6
A25
A7
A24
A12
A23
GND
A15
A22
A16
A52/A18/VCCP
NONE
A51/A17/VCC
READY
A21
WE#
GND
A20
A14
A19
A13
A18
A8
A17
GND
A9
IOWR#
A11
IORD#
OE#
VS1#
A10
GND
CE2#
CE1#
D15
D7
D14
D6
D13
GND
D5
D12
D4
D11
D3
CD1#
GND
GND

2

@ 100P_0402_50V8J

2

@ 22K_0402_5%

2

4

2

24
2
1

R176

1

@ 22K_0402_5%
@ 56P_0402_50V8J

5V
5V
5V

9/8

PCI7612ZHK_PBGA257

SC_CLK

AVPP
BVPP

+3VS

JP23

C166
@ 10P_0402_50V8J

14
13

TPS2224ADBR_HTSSOP24

A_USB_EN#

F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

1

3.3V
3.3V

0.1U_0402_16V4Z

2

@ 10_0402_5%

E10

20
7

C210

3

2

12V
12V

+5VS

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#
CPAR/A13
CFRAME#/A23
CIRDY#/A15
CSTOP#/A20
CDEVSEL#/A21
CBLOCK#/A19
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/A16
CINT#/READY(IREQ#)
CPS
CLK_48
CTRDY#/A22
CAUDIO/BVD2(SPKR#)
CRST#/RESET

3
4
5
12
15
21

0.1U_0402_16V4Z

S1_REG#
S1_A12
S1_A8
S1_CE1#

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

C258

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
J15
J18
K15
K17
K18
L15
L18
L19
M17
M18
N19
M15
N17
N18
P19

2

E

U19

1

VCCB
VCCB

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

1

D

+S1_VCC

0.1U_0402_16V4Z
C233

1

F6
F9
F12
F14
J6
J14
L6
L14
P6
P8
P10

U16A

2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

2

1

C

10U_0805_10V4Z
C235

2

1
C229

2

1

C203
0.1U_0402_16V4Z

2

1

C182
0.1U_0402_16V4Z

2

1

C179
0.1U_0402_16V4Z

2

1

C187
0.1U_0402_16V4Z

2

1

C195
0.1U_0402_16V4Z

1

B

C170
0.1U_0402_16V4Z

0.1U_0402_16V4Z

A

+3VS

4

L

Place the parts close to JP9
Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
TI PCI7612 CB/SmartCard

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

D

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
E

24

of

52

3

PLT_RST#

1

J10 1

+3VALW

2

Layout Notice : Place as close
chip as possible.

3

D11

V_3P3_LAN

1

LOM_LOW_PWR

REGSUP12
REGCTL12
REGSEN12
REGOUT25
REGSUP25

L13
K12
K13

V_2P5_LAN

M13

V_3P3_LAN

1

2

C304
4.7U_0805_10V4Z

2
C309

C303

1

1

0.1U_0402_16V4Z

PLT_RST#_LAN

PCIE_RXP1

21

1

1
0.1U_0402_16V4Z

2

C300
10U_0805_6.3V6M

11/21

PCIE_TXP1

21

C306

LOM_WAKE#

1

CLK_PCIE_LOM#
15
CLK_PCIE_LOM 15

3

LOM_PCIE_WAKE#

21

4.7U_0805_10V4Z

Q107
@BSS84_SOT23
R654 1
2 0_0402_5%

V_3P3_LAN

R646

R364

10K_0402_5%

4.7K_0402_5%

2

1

1

C299
0.1U_0402_16V4Z

Place close U6 pin M13

R656 1
2
@ 100K_0402_5%

V_2P5_LAN

D
Q108
@ BSS84_SOT23

R658

S

D

S

R655 1
R657 1
R648 1

2

1

NIC_PD#

NIC_PD

@ 10U_1206_6.3V6M
1
1
C364 + C372

+3VS V_3P3_LAN

2
G

1

11/18

@ 0_0402_5%

B9

2

NIC_PD_N

1

C6
G4
C5
F4
E5

C

NIC_PD
10K_0402_5%

@ 4.7K_0402_5%

RDAC

V_3P3_LAN

R345

2
G

21

L
11/15

TCK
TDI
TDO
TMS
TRST#

2
PCIE_TXN1

S

D7
C2

21

2
C352

2@ 0_0402_5%
2@ 0_0402_5%
2@ 10K_0402_5%

Q76
@ 2N7002_SOT23

2
G

BCM5753KFBG C0_FPBGA196~D

0.1U_0402_16V4Z

11/21

L

1

2

2

68U_B2_4VM

Place close U6 pin N13
B

1.2K_0402_1%

C334
27P_0402_50V8J

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

11/18

11/21
V_3P3_LAN
C379
1
2

5

@ 0.1U_0402_16V4Z

1

11/18R659

R660

@ SN74LVC1G17DBVR_SOT23-5

P

R416

2

1

G

I

2

@ 100K_0402_5%

1

C396

11/18
V_3P3_LAN

@ 0.1U_0402_16V4Z
2

R667

+3VALW

1N4148_SOD80
2

2
1
@ 10K_0402_5%

1
P

AT24C256_SO8

O
NC

0_0402_5%

2
D34
1

4
1

2

@ 0_0402_5%

5751_GPIO1
5751_EECLK
5751_EEDAT

LOM_LOW_PWR

LOM_LOW_PWR

3

1

11/21

21

+3VS

1

V_3P3_LAN

5

8
7
6
5

VCC
WP
SCL
SDA

R406
1K_0402_5%
2
1

R404
1K_0402_5%
2
1

U28

R405
1K_0402_5%
2
1

U27
0.1U_0402_16V4Z

A0
A1
NC
GND

2

S

C376

1
2
3
4

V_1P2_LAN
BCP69_SOT223
Q54
4
3
2

REGSUP12
Q4
2N7002_SOT23

D

LOM_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM
2
1
R328 4.7K_0402_5%

PCIE_RXN1

2

XTALI

V_3P3_LAN

2

C307
0.1U_0402_16V4Z

1

C366
4.7U_0805_10V4Z

Must having maximized
copper under pin 2 & 4 of Q13

D

1

N8

1

27P_0402_50V8J

D

2

M8

B5
M6
N6
C4

2

3

M4

C342 1
PCIE_C_RXN1
0.1U_0402_16V4Z
C344 1
PCIE_C_RXP1
0.1U_0402_16V4Z

1

N4

2
1

C331

1

VAUX_1.2_CTL

1

WAKE#
REFCLKREFCLK+
REFCLK_SEL
PCIE_TST
PERST#

TEST
M10

XTALO

Clock

N10

XTALI

2

L

V_1P2_LAN

R373

2

1

2

V_3P3_LAN

REGSUP12
VAUX_1.2_CTL

N13

25MHZ_16P_XSL025000FK1H
B

LP_EN#
2
G
2N7002_SOT23

2
G

SLP_S3#

2

LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#

Bias

XTALO

2

1

2

1
18,21,27,28,29,33,35,36,40,43,44

PCIE_RXDN

PCI-E
B10
C10
B11
C9

1 R679
2
10K_0402_5%

1
200_0402_1%

Q3

S

D
Q5
2
G
2N7002_SOT23 S

R326

2
R347
Y4
1

1

2

1
2
4.7K_0402_5%

1

2
LAN_ACT#

LAN_ACT#

V_3P3_LAN

J5

ADP_PRES

9/13

PCIE_RXDP

LANLINK_STATUS#

3

Q78
2N7002_SOT23
1 R680
2
@ 0_0402_5%
LANLINK_STATUS#
LANLINK_STATUS#
26,35

LOW_PWR

PCIE_TXDP

LED

26,35

18,33,40,41,42,47

R407

PCIE_TXDN

10K_0402_5%

1

LANLINK_STATUS#_SB

PWR_IND#
ATTN_IND#
ATTN_BTTN#

D

21

2 2
G

S

2

4.7K_0402_5%
10K_0402_5%

D

@ 0_0402_5%

11/14

2

R663

H2
J2
B3

2

R673

1

2

V_3P3_LAN

1

1

1
R678

R21

NIC_PD

NIC_PD

R335

Hot Plug
Support

C

1

2

1

CS#

V_3P3_LAN

10K_0402_5%

26

3

V_3P3_LAN

2

2

SCLK

11/23

+3VALW

26
26
26
26
26
26
26
26

2 R19
1
47K_0402_5%

3

SI
SO

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-

V_3P3_LAN

2

1

D10

EECLK
EEDATA

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-

1

F11
E10

Misc

H10
J11

SMB_CLK
SMB_DATA

C12
C13
D12
D13
E12
E13
F12
F13

1

4.7K_0402_5%
@RB751V_SOD323

3

5751_EECLK
5751_EEDAT

GPIO0_TST_CLKOUT
GPIO1

Media

ICH_LAN_SMBCLK D9
ICH_LAN_SMBDATA D8

Power
Control

J10
J12

5751_GPIO1

Regulator
Control

R391
1
2
10K_0402_5%

TRD3+
TRD3TRD2+
TRD2TRD1+
TRD1TRD0+
TRD0-

R20

11/21

C544
2
@ 0.1U_0402_16V7K

PLT_RST#_LAN

BCM5753
9/7

3
Q2
SI2301BDS_SOT23

D36

2

9/7

U25A
D

R329

1

1

2

ICH_SMBCLK
4,13,14,15,18,21,27
ICH_SMBDATA 4,13,14,15,18,21,27

3

ICH_SMBCLK
ICH_SMBDATA

1

1

@ 0_0402_5%

2 0_0402_5%
2 0_0402_5%

D

ICH_LAN_SMBCLK R367 1
ICH_LAN_SMBDATA R336 1

G

2@ 1K_0402_5%
2@ 1K_0402_5%

2

S

5/16

R366 1
R337 1

D

R330
V_3P3_LAN

S

G

1

PAD-NO SHORT 2x2m
SI2301BDS_SOT23
Q57
220K_0402_5%
2

C358
0.1U_0402_16V4Z

7,19,20,21,23,27,32,33

2

C357
0.1U_0402_16V4Z

4

C308
0.1U_0402_16V4Z

5

R334

2
1

I

O
NC

4
1

R661 1
2
0_0402_5%

CLKREQA#

U38
SN74LVC1G17DBVR_SOT23-5

15,18

21,26

2

CABLE_DETECT

A

C400

2

@ 0_0402_5%

D

S

2

1 R668
2
0_0402_5%

NIC_PD_N

LP_EN#
2
G
Q66
2N7002_SOT23

LP_EN#

21

D

@ 2N7002_SOT23
Q60
ICH_LAN_SMBDATA
1

3

0.1U_0402_16V4Z

2
3

D

S

ICH_SMBCLK

ICH_LAN_SMBCLK
1
Q65
@ 2N7002_SOT23

3
2

G

Compal Secret Data

Security Classification

G

Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

2

2

R426

1
1

@ 2.2K_0402_5%

S

ICH_SMBDATA

R424
2
1
10K_0402_5%

10K_0402_5%

CABLE_DETECT

R361

@ 2.2K_0402_5%

+3VS

R425

CKT Notice : CABLE IN, CABLE_DETECT=0
CABLE OUT, CABLE_DETECT=1

1

0.1U_0402_16V7K

1

1

C550

2

2
121K_0402_1%

G

1
R662

3

NIC_PD_N
+3VS

+5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

BCM5753M
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

25

of

52

A

5

4

3

2

1

T22

Layout Notice : 1.2V decoupling CAP.
Place as close chip as possible.

0_0603_5%

TD3-

MX3-

16

MDO1-

6

MX3+

TCT3

MCT3

TD2-

MX2-

17

MDO1+

18

MCT1

C301
2 R318
1
1
2
75_0402_1%
1000P_1808_3KV7K
MDO2-

19

VMAINPRSNT 1

3

Q106

4

LAN_TX3-

3

LAN_TX3+

2

TRM_CT

1

MX2+

TCT2

MCT2

TD1-

MX1-

TD1+

MX1+

1:1

2
1
C347
0.1U_0402_16V7K

TRM_CT

TD21+

1:1

2
1
C346
0.1U_0402_16V7K

5

TCT1

MCT1

20

MDO2+

21

MCT2

22

MDO3-

23

MDO3+

24

MCT3

24HST1041A-3B_24P

2

1

11/14

V_1P2_LAN

Layout Notice : Filter place as close
chip as possible.

V_3P3_LAN

0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1

49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%

2
2
2
2
2
2
2
2

LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

2
1
0_0603_5%

25
25
25
25
25
25
25
25

XTALVDD

2
C353

0.1U_0402_16V4Z
R376

2
1
0_0603_5%

R392
2
1
0_0603_5%

Layout Notice : Place
termination as close as
BCM5753M as possible

B

21,25

CABLE_DETECT

LAN_ACT#_R
2 R13
2 LANLINK_STATUS#_R
150_0402_5%

CABLE_DETECT

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_87212-1400

1

C10
0.1U_0402_16V4Z

2

2
1
BLM11A601S_0603
C370
4.7U_0805_10V4Z

2
1
BLM11A601S_0603
C369

AVDDL

2

2

1

1

2

2

C355
0.1U_0402_16V4Z
V_3P3_LAN

GPHY_PLLVDD

R324

C354
@ 4.7K_0402_5%

4.7U_0805_10V4Z

L10
2
1
BLM11A601S_0603
C36

L15
2
1
BLM11A601S_0603
C313
4.7U_0805_10V4Z
V_3P3_LAN_LED

1

1

2

2

0.1U_0402_16V4Z
T20
PCIE_PLLVDD

1

1

1

2

PAD

C39
0.1U_0402_16V4Z

L

T59 , T60 place together
V_3P3_LAN

PCIE_SDS_VDD

2

1

R327 1

2 @ 4.7K_0402_5%

C321

1

T21
PAD
2 @ 4.7K_0402_5%

R374 1

2 @ 4.7K_0402_5%

0.1U_0402_16V4Z
R16

D

S

1

1

3

Q64
FDN338P_SOT23

2

G

R380

PCIE_SDS_VDD

1

L18

4.7U_0805_10V4Z

V_3P3_LAN

2

11/14
AVDD2

L17
JP4

100K_0402_5%

1
A

S Q63
2N7002_SOT23

A2
A6
A10
B4
D3
E11
G2
H11
K3
M2
P12
B6
H4
M12
J13
C7
H12
L5
A1
A4
A5
A7
A9
B2
B7
B8
C8
D1
D2
D4
D5
E1
E2
E4
F2
F3
G1
G3
H1
H3
J3
J4
K1
K2
K11
L1
L2
L3
L4
L8
L9
L11
M1
M5
M9
N2
N3
N9
P1
P2
G11
G12
B12
G13

PCIE_PLLVDD
GPHY_PLLVDD

L7
H13

D

2
G
3

PREP#

2

1

2

1

2

1

2

1

2

1

2
D

1

U25B

E6
E7
E8
E9
J6
J7
J9
K5

AVDD1
AVDD2

AVDDL

2
21,35

1

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7

BCM5753

VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31

GND

VDDP_0
VDDP_1
VDDP_2
XTALVDD
VAUXPRSNT
VMAINPRSNT
PCIE_SDSVDD
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
AVDDL_0
AVDDL_1
AVDD_0
AVDD_1

Disconnected

35
35
35
35
35
35
35
35

L

LAN_AUXPWR
VMAINPRSNT

V_1P2_LAN

Keep JP5.1/2/3 at least 10mils

150_0402_5% 1
LAN_ACT#
LANLINK_STATUS#
1
R12
MDO3+
MDO3+
MDO3MDO3MDO2+
MDO2+
MDO2MDO2MDO1+
MDO1+
MDO1MDO1MDO0+
MDO0+
MDO0MDO0-

1K_0402_5% 1 R358

2

25,35

25,35 LAN_ACT#
LANLINK_STATUS#

1

2
C356

0.1U_0402_16V4Z

To RJ-45 CONN.

V_3P3_LAN XTALVDD V_2P5_LAN

AVDD1

2
C340

0.1U_0402_16V4Z

V_3P3_LAN_LED

1

1

2 C363 R3891
R3881
2 C362 R3871
R3861
2 C361 R3851
R3841
2 C360 R3831
R3821

0.1U_0402_16V4Z 1

1

2

Digial power

R393
0.1U_0402_16V4Z 1

1

2

VMAINPRSNT_R

V_2P5_LAN

C

1

2

2 0_0402_5%

2 R322
1
75_0402_1%

C302
2 R321
1
1
2
75_0402_1%
1000P_1808_3KV7K

2

@ BSS84_SOT23

R653 1
LAN_TX2+

1

2

LAN_TX2-

TD3+

2
G

7

2

S

8

TRM_CT

D

LAN_TX1+

1:1

2
1
C345
0.1U_0402_16V7K

V_1P2_LAN

C323

R325

25

10K_0402_5%

11/22

C327

9/10
NIC_PD

D

V_2P5_LAN

C311
0.1U_0402_16V4Z

9

LAN_TX1-

+3VS

2 R323
1
75_0402_1%
C335
0.1U_0402_16V4Z

MCT0

C44
0.1U_0402_16V4Z

15

C16
0.1U_0402_16V4Z

MDO0+

MCT4

0.1U_0402_16V4Z

14

TCT4

TD4+

0.1U_0402_16V4Z

MX4+

10

1

TRM_CT

1:1

LAN_TX0+ 11

2
1
C348
0.1U_0402_16V7K

C310
0.1U_0402_16V4Z

MDO0-

C21
0.1U_0402_16V4Z

13

C332
0.1U_0402_16V4Z

MX4-

C312
0.1U_0402_16V4Z

TD4-

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8
DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30
DC_31
DC_32
DC_33
DC_34
DC_35
DC_36
DC_37
DC_38
DC_39

Don't care

12

2

C27
4.7U_0805_10V4Z

1

C40
0.1U_0402_16V4Z

LAN_TX0-

R672
V_2P5_LAN

Analog
power

PCIE_PLLVDD
GPHY_PLLVDD

PLL

BIAS

BIASVDD

A3
A8
A12
A14
B1
C1
C3
C11
F1
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H6
H7
H8
H9
J1
M3
M7
N1
N7
P11
P14

C

A11
A13
B14
C14
D6
D14
E3
E14
F14
G14
H5
H14
J8
J14
K4
K6
K7
K8
K9
K10
K14
L6
L10
L12
L14
M11
M14
N5
N11
N12
N14
P3
P4
P5
P6
P7
P8
P9
P10
P13

B

V_2P5_LAN
L16
1
2
1 BLM11A601S_0603
C351

B13

BCM5753KFBG C0_FPBGA196~D

A

0.1U_0402_16V4Z
2

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
Magnetic & RJ45/RJ11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

26

of

52

B

C

D

E

+3VS
+3VS

1

C217
0.01U_0402_16V7K

2

C171
0.1U_0402_16V4Z

1

1

C493
4.7U_0805_10V4Z

2

C492
0.01U_0402_16V7K

2

1

2

C489
0.1U_0402_16V4Z

1

2

1

C494
4.7U_0805_10V4Z

2

3

1

C491
0.1U_0402_16V4Z

R515

2

18,21,25,28,29,33,35,36,40,43,44

1

Q70
@ SI2301BDS_SOT23

1
2
@ 100K_0402_5%

9/8

D

SLP_S3#

2
G
Q71
S
@ 2N7002_SOT23

SLP_S3#

1

3

1

+3VS_MINI

1
2
0_0805_5%

1

2

1

+3VALW

G

2

C214
0.01U_0402_16V7K

+3VALW

D

1

+1.5VS

S

C167
0.01U_0402_16V7K

9/12 +3VS_MINI

R505

2

A

+3VS_ACL_IO
R55
1
2
ACCEL@ 0_0603_5%

11

3

Vdd

Reserved2

Mini-Express Card
RDY/INT

6

ACCEL_INT

19
21

20

2
1
ACCEL@ 0_0402_5%

Reserved3
SDO

4

15

2

1

ICH_SMBDATA

13

4,13,14,15,18,21,25
4,13,14,15,18,21,25

15

12

+3VS_ACL

21
21

R48
1
2
ACCEL@ 10K_0402_5%

16

2
R43

PCIE_RXN2
PCIE_RXP2

PCIE_RXN2 1 R546
PCIE_RXP2 1
R547
21
21

1
0_0402_5%

CLK_PCI_DB

DB_LPC_RST#
CLK_PCI_DB
0_0402_5%
2 PCIE_C_RXN2
2 PCIE_C_RXP2
0_0402_5%
PCIE_TXN2
PCIE_TXP2

PCIE_TXN2
PCIE_TXP2

ACCEL@ LIS3LV02DQ_QFN28

8/30

2

ACCEL@ 0.1U_0402_16V4Z

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

15 CLK_PCIE_MCARD#
15 CLK_PCIE_MCARD

GND

C135

2

17

1

GND

C121

CK
GND

1

CS

29

C136
@ 0.01U_0402_16V7K

SCL/SPC

5

ACCEL@ 10U_0805_6.3V6M

10

ICH_SMBCLK

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13

PADDLE

+3VS_ACL

1
7
8
14
15
21
22
23
24
25
26
27
28

2

2

2

PCIE_WAKE#
30 CH_DATA
30 CH_CLK
CLKREQD#

9

1
R50
ACCEL@ 0_0402_5%

PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQD#

Reserved1
SDA/SDI/SDO

DB_PWR
DB_PWR_LED#
DB_NUM_LED#
DB_CAPS_LED#

5/26

L

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

Must be placed in the center of the system.
pin29 is the center EMI pad which STMicro
recommended not to be connected

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1

GND2

7,19,20,21,23,25,32,33

11/22

2

1

+3VS

PAD-No SHORT 2x2m
J11
2
1
+3VALW

XMIT_OFF#

2

PAD-SHORT 2x2m
ICH_SMBCLK
4,13,14,15,18,21,25
ICH_SMBDATA 4,13,14,15,18,21,25
USB20_N1_R_MC
USB20_P1_R_MC

9/8

WW_LED#
WL_LED#
WP_LED#

WL_LED#

32
32

32

54
WW_LED#

R497

1

2@ 0_0402_5%

WP_LED#

R500

1

2@ 0_0402_5%

WL_LED#

H29
H28
HOLE_MC HOLE_MC

1

3

2

R104
2
1
0_0402_5%

Mini-Card Stand Off

@ 100K_0402_5%
XMIT_OFF#

1

XMIT_OFF

PLT_RST#
J12

R112

D

3

2
21

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0

1

1
R92
@ 10K_0402_5%

9/16

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

FOX_AS0B226-S40N-7F

+3VALW

3

+1.5VS +3VS_MINI

JP30

R45

1

18

Vdd

+3VS_ACL

19

+3VS_ACL

R56
1
2
@ 0_0805_5%
2
1
+3VS_ACL_IO
D11
R44
ACCEL@ CH751H-40_SC76
U6
2
1
ACCEL@ 0_0402_5%

Vdd_IO

+3VS

S

Q17
@ 2N7002_SOT23

2
G

L

Must be placed close to JP44.

20,31,32,33 LPC_FRAME#
20,31,32,33 LPC_AD3
20,31,32,33 LPC_AD2
20,31,32,33 LPC_AD1
20,31,32,33 LPC_AD0
20,31 PLT_RST_B#
33,34 NUM_LED#
33,34 CAPS_LED#
32,33,35 STB_LED#

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST_B#
NUM_LED#
CAPS_LED#
STB_LED#
+3VL

R452
R471
R456
R488
R495
R544
R530
R520
R514
R511

1
1
1
1
1
1
1
1
1
1

2DB@
2DB@
2DB@
2DB@
2DB@
2DB@
2DB@
2DB@
2DB@
2DB@

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0603_5%

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0
DB_LPC_RST#
DB_NUM_LED#
DB_CAPS_LED#
DB_PWR_LED#
DB_PWR

9/12

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
Mini-Card/Mini-PCI/Accelerometer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

D

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
E

27

of

52

A

B

C

D

E

F

G

VDDA_CODEC

1

VDDA_CODEC

H

SLP_S3#

1

18,21,25,27,29,33,35,36,40,43,44

+5VAMP

R287

U17

0.1U_0402_16V4Z 150K_0402_1%

2

R283

2
G

PCM_SPK

3

1

S

Q48
2N7002_SOT23

1

MONO_IN_HD
2
1981HD@ 0.1U_0402_16V4Z

2

+ C198

2

C193

3
C194

2
C269

2

22U_B_10V

1

1U_0603_10V4Z

1

100P_0402_50V8J

49.9K_0402_1% 1

GND
C205

2

1

+ C213

2

R206

22U_B_10V

2

C216
0.1U_0402_16V4Z
1

0.01U_0402_16V7K

1
2
1
3

4

1

1 R198
2
0_1206_5%

143K_0402_1%

Place R258 between DGND & AGND & close to U14

10K_0402_5%
C279
1
2

S

ADJ

EN

0.01U_0402_16V7K

R288

21

5

MIC5205BM5_SOT23-5

VDDA_CODEC

D

OUT

2

1
C264

R213

IN

1

2

1

2

1

10K_0402_5%

2

23

D

1
R277

1

1

2

10K_0402_5%
C276
1
2

R279

1

2

0.1U_0402_16V4Z 150K_0402_1%

2
G

SB_SPKR

Q51
2N7002_SOT23

2

2

+3VS
VDDA_CODEC

R225

2

2

C251

1
U21

35

DLINE_IN_L

35

DLINE_IN_R

R290
R289
R291
R292

2
1
2
1

1
2
1
2

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%

PAD T44

15

C283 1

2 1U_0603_10V4Z

INT_MICL_C

16

HP_LOUT_L

23

LINE_IN_L

HP_LOUT_R

DLINE_IN_RC_R

24

LINE_IN_R

PAD T47

18

CD_L

DLINE_IN_R_R C275 1

2 1U_0603_10V4Z

29
R297 1
R236 1
20

Place close to U14

20
20

11/17

2
C545

1
0.1U_0805_25V7M

2
C259

1
0.1U_0805_25V7M

2
C206

1
0.1U_0805_25V7M

2
C284

1
0.1U_0805_25V7M

1
C272
1
MIC2
C273
2 2.67K_0402_1%
2
R284
2 2.2K_0402_5%

PAD T45

20

PAD T46

19

MIC1_C
2
1U_0603_10V4Z
MIC2_C
2
1U_0603_10V4Z
SENSE_A
1SENSE_B
@ 0_0402_5%

CD_GND

21

MIC1

22

MIC2

13
34

SENSEA
SENSEB

11

RESET#

10

SYNC

AC97_SDOUT_CODEC

5

L11
1
2
FBM-L10-160808-301-T_0603
PAD T35

2

SENSE_A_A
1 R293
2
39.2K_0402_1%
SENSE_A_B
1 R294
2
20K_0402_1%
SENSE_A_C
1 R286
2
10K_0402_1%

10U_1206_16V4Z
C282
1U_0603_10V4Z

SENSE_A_A

29

SENSE_A_B

29

VDDA_CODEC

1
R296

2

@ 10K_0402_5%

D

35
36
37

LINE_OUTL

29

LINE_OUTR

29

Q52

2
G

2N7002_SOT23 S

T33 PAD

39

L_HP

29

41

R_HP

29

47
48
4
7

SDATA_OUT

8

1

R295

100K_0402_5%

2 10P_0402_25V8K
AC97_BITCLK_CODEC

LINE_IN_SENSE

LINE_IN_SENSE

35

2

C285
0.1U_0603_50V

20

@ 10_0402_5%
2
1
R248
AC97_SDIN0_CODEC
R226 2
PIN44 R224
1
R218 2
R241 1

1
2@ 10P_0402_25V8K
C249
R252 1
2
AC97_SDIN0
33_0402_5%
1 @ 4.7K_0402_5% PORT_A_SNS
2 @ 4.7K_0402_5%
1 10K_0402_5%
2 @ 4.7K_0402_5%

GPIO_0
GPIO_1
GPIO_2
GPIO_3

43
44
2
3

VREF

27

AUD_REF

28
29
30
32
12

CODEC_REF
AFILT1
AFILT2
AFILT4
MONO_IN_HD

T41
PAD
T43 PAD
T42 PAD
T38 PAD

31
33
40
45
46

AFILT3
PIN33
PIN40

T40 PAD
T39 PAD
T34 PAD

3

20
PORT_A_SNS

29

PR_INSERT#

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_F
MIC_BIAS_D
PCBEEP
N/C
N/C
N/C
NC
NC

EAPD
SPDIFO
DVSS1
DVSS2

1

6

CD_R

AC97_RST#_CODEC

EAPD

2

SENSE_A

C238

0.1U_0402_16V4Z

C247

BIT_CLK
SDATA_IN

AC97_SYNC_CODEC

29,33

LINE_OUT_R
MONO_OUT

17

DLINE_IN_RC_L

MIC1

AUX_R

LINE_OUT_L

MIC4

INT_MICR_C

2 1U_0603_10V4Z

29

AUX_L

MIC3

2 1U_0603_10V4Z

3

1

1

14

C270 1

VDDA_CODEC

2

1

3

PAD T48

DLINE_IN_R_L C274 1

INT_MIC

C239

2

29

AVDD1

0.1U_0402_16V4Z 10U_1206_16V4Z

1

2

C266

1

1

1
2
0_0805_5%

9

2

C222

1

2

1

DVDD2

C225

DVDD1

1

38

2

C224

25

0.1U_0402_16V4Z

1

AVDD2

C265

0.1U_0402_16V4Z +3VS_CODEC

1

0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVSS1
AVSS2

26
42

T36
T37

1

C256

1

1U_0603_10V4Z

2

C250
0.1U_0402_16V4Z

2

PAD
PAD

PIN42

AD1981HDJSTZ-REEL_LQFP48

4

4

R219

2

1

Issued Date

GND

GNDA

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@ 0_1206_5%

2005/03/10

2006/03/10

Deciphered Date

Title

AC97 CODEC AD1981HD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

F

Friday, November 25, 2005

G

Sheet

28
H

of

52

A

B

C

D

E

AMP. FOR INTERNAL SPEAKER
+5VALW

+5VAMP
R220
@ 10U_1206_6.3V6M
1

1

0_1206_5%
C252

1

C208

+

C246

1

1

C240

1

1

1

2

1

1

C248
D18

28

LINE_OUTR

28

LINE_OUTL

R272

LINE_C_OUTR 1
2 LINE_C_R_OUTR
10K_0402_5%
0.1U_0402_16V4Z

5

INR

BIAS

10 dB

1

OUTR+
INL
OUTR-

4

MUTE

OUTL+

2

9

R_SPK-

1
C160

19

1
2 LINE_C_R_OUTL
16.5K_0402_1%
10 dB
L_SPK+

17

L_SPK-

PGND1
PGND2
PGND3
PGND4

EP
21

2
G
Q40
S
@ 2N7002_SOT23

NC1
NC2
NC3
NC4

3
10
13
16

MAX9710ETP_QFN20

D

1
3

R273

Q47 S
2N7002_SOT23
C281

1

2

2

28

C188

C278

0.1U_0402_16V4Z

USB20_N2
USB20_P2

21
21

USB20_N3
USB20_P3

1

2

21 USB_OC#2
21 USB_OC#3
30,35,36 SLP_S5

2.2U_0603_6.3V6K

SENSE_A_B

1

0.1U_0603_25V7K_V1

DLINE_OUT_L

1
2
100K_0402_5%
1

3

DOCK_HPS#

2

D

+5VALW

21
21

D

2
G

MIC_SENSE

35 DLINE_OUT_L
35 DLINE_OUT_R
28 R_HP
28 INT_MIC
28 L_HP
28

MIC1

28

MIC2

3

Q37 S
2N7002_SOT23

USB20_N2
USB20_P2

0_0402_5%
R162 2
USB20_N2_R
1
R170 2
USB20_P2_R
1
0_0402_5%
0_0402_5%
R174 2
USB20_N3_R
1
R180 2
USB20_P3_R
1
0_0402_5%

GAIN1

0

0

Av(inv)
6 dB

0

1

10 dB

1

0

15.6 dB

1

1

21.6 dB

2

JP25

1
2
3
USB20_N3
4
USB20_P3
5
6
7
8
SLP_S5
9
10
11
+5VALW
12
VDDA_CODEC
MIC_SENSE
13
DLINE_OUT_L
14
15
1
2 C191
2
1 R207
16
100U_D2_6.3VM
15_0805_5% 17
1
2 C192
2
1 R217
18
100U_D2_6.3VM
15_0805_5% 19
20
21
22
+

2
1

100K_0402_5%

2
G
35

R258

+

1

100K_0402_5%

2
G

Q50
2N7002_SOT23 S

GAIN0

1

2

R278

D

3

3

2
G

100P_0402_50V8J

VDDA_CODEC

1

1

100K_0402_5%

D

C163

VDDA_CODEC
R285

Q49
2N7002_SOT23 S

2
2
100P_0402_50V8J

To Audio / USB Board CONN

VDDA_CODEC

28 PORT_A_SNS
28 SENSE_A_A

2

1

1
2
3
4
E&T_3801-04

U39 Gain Settings

2
G
Q39
S
2N7002_SOT23

A_SD

100P_0402_50V8J
1
1
C161
C162

100P_0402_50V8J
2

3

33

EAPD

D

1

28,33

SHDN

2 0_0402_5%

11/14

1K_0402_5%

14

6
11
15
20

R650

2 10K_0402_5%

1

R649 1

2

1
2 LINE_C_R_OUTR
16.5K_0402_1%
10 dB
R_SPK+

3

MUTE_LED#

1

34

R203 1

2

1
2
3
4

R256

OUTL-

SLP_S3#

1

7

R271

2
1
0_0402_5%

18,21,25,27,28,33,35,36,40,43,44

2

L_SPK+
L_SPKR_SPK+
R_SPK-

width
LC262Keep 10 mil1U_0603_10V4Z
R257

LINE_C_OUTL 1
2 LINE_C_R_OUTL
10K_0402_5%
0.1U_0402_16V4Z

@ PACDN042_SOT23~D

JP19

R270

C260
1
2

@ PACDN042_SOT23~D

U20

VDD
PVDD1
PVDD2

10 dB
C261
1
2

0.1U_0402_16V4Z

2

2
2
2
@ 1U_0603_10V4Z

3

2

2

@ 150U_D_6.3VM

3

2

12
8
18

@ 10U_1206_6.3V6M

D19

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

3

ACES_87212-2200

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
AMP & Audio Jack

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

D

Friday, November 25, 2005

Sheet
E

29

of

52

5

4

3

2

1

USB CONNECTOR 1
+5VALW

USB_VCCA

USB_VCCB

+5VALW

U36
U7

1
2
3
4

GND
IN
IN
EN#

USB_OC#4
USB_VCCB

OUT
OUT
OUT
OC#

SLP_S5
G548A2P1U_SO8

8
7
6
5

J13

(4A,160mils ,Via NO.=8)
1 USB_OC#5
0_0402_5%

10
12

VCC VCC
D0- D1D0+ D1+
VSS VSS
G2
G4

G1
G3

5
6
7
8

USB20_N5_R
USB20_P5_R

R51
2
2
R52

0_0402_5%
1USB20_N5
1USB20_P5
0_0402_5%

W=40mils
USB20_N5
USB20_P5

21
21

9
11

1

2

TYCO_1-1734062-1

1

2

1
+

2

8
7
6
5

C126
220U 6.3V M

1
2
3
4

C122
0.1U_0402_16V4Z

R53
1USB20_N4_R
1USB20_P4_R
R57

USB20_N4
USB20_P4

1
2
3
4

GND
IN
IN
EN#

D

SLP_S5

SLP_S5

USB_OC#5
USB20_N5
USB20_P5

D12
@ PACDN042_SOT23~D

OUT
OUT
OUT
OC#

29,35,36

TPS2041BDR_SO8

11/17

21

PAD-OPEN 3x3m
1
2
USB_OC#4 2
R49

0_0402_5%
USB20_N4 2
USB20_P4 2
0_0402_5%

C123
1000P_0402_50V7K

USB20_N4
USB20_P4

USB_OC#5

21

2

USB_OC#4
USB_VCCA

U35

2

21
21

3

2

1

D10
@ PACDN042_SOT23~D

1

1

2

+

2

SLP_S5

+5VALW

1

TPS2041BDR_SO8

2

JP16

W=40mils

8
7
6
5

3

OUT
OUT
OUT
OC#

1

GND
IN
IN
EN#

C498
1000P_0402_50V7K

4.7U_0805_10V4Z

1
2
3
4

C499
0.1U_0402_16V4Z

C137

1

C118
220U 6.3V M

D

C

C

BT Connector
JP18

1
2
USB20_P0_R
3
USB20_N0_R
4
5
R674 1
6
R677 1
7
8
ACES_87212-0800

1 0_0402_5%
1 0_0402_5%

USB20_P0
USB20_N0

R87
2 100_0402_5%
2 100_0402_5%

21
21

B

2

11/23

USB20_P0
USB20_N0

BT_LED 32
CH_DATA 27
CH_CLK 27

3

B

+3VAUX_BT

R85

2
2

D16

1

@ PACDN042_SOT23~D

+3VALW

+3VAUX_BT
Q12

SI2301BDS_SOT23

1

2

1

R69

1U_0603_10V4Z

100K_0402_5%

BT_OFF

1

C143

2

1

2

C142
4.7U_0805_10V4Z

1 0.01U_0402_16V7K
C138

1
2
47K_0402_5%

A

C144

2

2

C140

R70
21

1

G

2

0.1U_0402_16V4Z

D

S

3

1

2

@0.1U_0402_16V4Z
A

9/14

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
USB I/O & BT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

2

Friday, November 25, 2005

Sheet
1

30

of

52

A

B

C

D

E

1

1

+3VS
RP29
DCD#1
RI#1
CTS#1
DSR#1

1
2
3
4

8
7
6
5

+5VS

2

4.7K_1206_8P4R_5%
IRRX

1
2
R427
1K_0402_5%

D31

1

CH751H-40_SC76

+5VS_PRN
RXD1
U29

21,33 NPCI_RST#
20,27 PLT_RST_B#
+3VS

10K_1206_8P4R_5%
R428
SIO_IRQ
1
2
10K_0402_5%
R437
SIO_DPIO45
1
2
10K_0402_5%

R431
R432
R433

2 0_0402_5%
2 @ 0_0402_5%
2 10K_0402_5%

1
1
1

+3VS

1
R417

20,27,32,33 LPC_FRAME#
20 LPC_DRQ#0

21,23,32,33 PM_CLKRUN#
15 CLK_PCI_SIO
21,23,32,33 SIRQ
2
10K_0402_5%
15

CLK_14M_SIO

CARD_ID#

High : Compal MXM
Low : Standard MXM

10K_0402_5%
R421

1

2

EXPCRD_RST#

35

SER_SHD

35

0_0402_5%
R422

1

2

SIO_RST#
SIO_PD#

17
18

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

19
20
21
6

CLK_14M_SIO

9

SW_EXPCRD_RST#

9/8

10K_0402_5%
+3VS
R435

1

2

LFRAME#
LDRQ#
PCI_RESET#
LPCPD#
CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#
CLK14

23
24
25
27
28
29
30
31
32
33
34
35
36
SW_EXPCRD_RST# 40

R8

2

15
16

SIO_GPIO40
PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

+3VS

1

LPC_FRAME#
LPC_DRQ#0

PID0

IRRX2
IRTX2
IRMODE/IRRX3

FIR

INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

CLOCK

GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

8
22
43
52

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

SERIAL I/F

SIO_GPIO12
SIO_GPIO10
SIO_GPIO44
SIO_GPIO43

LPC I/F

2

1
2
3
4

LAD0
LAD1
LAD2
LAD3

VSS
VSS
VSS
VSS

PARALLEL I/F

RP30

8
7
6
5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

10
12
13
14

GPIO

20,27,32,33
20,27,32,33
20,27,32,33
20,27,32,33

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

VTR
VCC
VCC
VCC
VCC

POWER

10K_0402_5%

35

RP28

R403
1

62
63
64
1
2
3
4
5

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

37
38
39

IRRX

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

1K_0402_5%

2

TXD1 35
DSR#1 35
RTS#1 35
CTS#1 35
DTR#1 35
RI#1 35
DCD#1 35

LPD3
LPD2
LPD1
LPD0

1
2
3
4

8
7
6
5

4.7K_1206_8P4R_5%
RP27
LPD7
LPD6
LPD5
LPD4

1
2
3
4

8
7
6
5

2

4.7K_1206_8P4R_5%

7
11
26
45
54

LPTINIT# 35
LPTSLCTIN# 35
LPD0 35
LPD1 35
LPD2 35
LPD3 35
LPD4 35
LPD5 35
LPD6 35
LPD7 35
LPTSLCT 35
LPTPE 35
LPTBUSY 35
LPTACK# 35
LPTERR# 35
LPTAFD# 35
LPTSTB# 35

RP26
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

C391

1

C397

1

C383

1

8
7
6
5

4.7K_1206_8P4R_5%
RP25

1
2
3
4

LPTSTB#
LPTAFD#
LPTERR#

8
7
6
5

4.7K_1206_8P4R_5%
R414
LPTSLCTIN#

1

LPTINIT#

4.7K_0402_5%
R418
1
2

+3VS

1

1
2
3
4

2

4.7K_0402_5%
C401

LPC47N217_STQFP64
R436
3

1

2

2

Base I/O Address
0 = 02Eh
* 1 = 04Eh

PID1

2

2

2
3

10K_0402_5%

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z

R429

1

2

SIO_GPIO11

10K_0402_5%
R438

2

SIO_GPIO40

10K_0402_5%

CLK_14M_SIO

1

CLK_PCI_SIO

1

1

1

2

R420
@ 10_0402_5%

2

2

R434
@ 10_0402_5%

1
C410
@18P_0402_50V8K

2

C399
@10P_0402_25V8K

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
SUPER I/O LPC47N217

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

D

Friday, November 25, 2005

Sheet
E

31

of

52

5

4

3

2

1

+5VS

3

47K

1

BIOS ROM

+3VS

R221
10K

2

2

150_0402_5%

1

SPI_CLK

6

SPI_SI

SPI_SI

SPI_CLK

6

HOLD

SPI_SI

5

S

D

2

Q

34

R108
1
2 SPI_WP#
SPI@ 3.3K_0402_5%
R155
1
2 SPI_HOLD#
SPI@ 3.3K_0402_5%

C

1

Mini-PCIE Card LED
1

W

8/26
WL/BT_LED

30

D

BT_LED

S

WL_LED

2
G
Q35
2N7002_SOT23

SPI@ SST25LF080A_SO8-200mil

C

9/12

R109

5

2
D
Q
@ MX25L8005MI-15G_SO8-150mil

1
2
SPI@ 47_0402_5%

L

SPI_SO

SPI_SO

1 R199
2
100K_0402_5%
R95
1
2
100K_0402_5%

BT_LED

BT_LED

WL_LED

21

2
G
Q36
2N7002_SOT23

D

S

8/23

1 R212
2
@ 0_0402_5%

R1291 should be placed less
than 100 mils from U61 & U65.

The chip must be placed on PCB easily
rework place for debug.

L

2N7002_SOT23
Q41
D

+3VL
21

HDD_STP

1

3

47K

HDD_STP

+3VS

9/6

AMBER_BATLED# 2
Q44
DTA114YKA_SC59

AMBER_BATLED#

S

HDD_STP#
100K_0402_5%

2

2

33

47K

R211

+3VL

10K

2
G

Q42

3

47K

33

GREEN_BATLED#

GREEN_BATLED#

47K

DTA114YKA_SC59

1

C

+3VS

10K

3

SPI_CS#

S

D

WL_LED

BLUE LED

3

7

HOLD

1

D28

LTST-S110TBKT-5A
+3VALW

10K

2

20

C

1

SPI_HOLD#

7

SPI_CS#

4

VSS

Wireless LED

4

VSS

W

SPI_HOLD#

VCC

27

1

SPI_CLK

3

VCC

3

SPI_CS#

21

2

SPI_WP#

3

1

8

21

21

U13

1

C172
SPI@ 0.1U_0402_16V4Z

U14

8

3

SPI_WP#

8/26

1

+3VALW

3

8/26

D

WL_LED#

Q34
DTA114YKA_SC59

2

+3VALW

IDE_LED#

IDE_LED#

10K

2

Q45
Q46
DTA114YKA_SC59

R234
R243

R242

150_0402_5%

2

150_0402_5%

2

150_0402_5%

2

2

150_0402_5%

1
1

R233

1

1

1 1

DTA114YKA_SC59

PAD
PAD

T23
T24

CLKRUN#

TEST1
TESTB1/BADD

8
9

2 R390
1
TPM1.2@ 0_0402_5%

2 R377
1
@ 4.7K_0402_5%

Finger printer

TPM_XTALO

14

TPM_XTALI

13

3

4

OUT

C341

2

1

0_0402_5%
2
1
2
1
0_0402_5%

47K

USB20_N1_R
USB20_P1_R

D9
@ PACDN042_SOT23~D

GND
GND
GND
GND
TPM_XTALI

JP15

9/8

R46
R47

USB20_N1
USB20_P1

XTALI/32K IN

1
2
3
4
5
6
7
8
ACES_87212-0800

27,33,35

STB_LED# 2

STB_LED#

10K

Q38
DTA114YKA_SC59
34

STB_LED
R222
150_0402_5%

L

TPM1.2@ 10M_0402_5%

Place R1365/R1366 close to JP38.2/JP38.3
and minimize the stub length.
USB20_N1_R

R570
2

@ 0_0402_5%
1 USB20_N1_R_MC

2
R569

1 USB20_P1_R_MC
@ 0_0402_5%
9/8

TPM_XTALO
USB20_P1_R

USB20_N1_R_MC

27

USB20_P1_R_MC

27

POWER LED
GREEN

A

17-21SYGC/S530-E1/TR8_GRN
D29

1

TPM1.2@ 18P_0402_50V8J

2

R394

2

NC

3
12
1

USB20_N1
USB20_P1

TPM1.2@ SLB 9635 TT 1.2_TSSOP28

TPM1.2@ 18P_0402_50V8J
C365
2
1

Y5
A

XTALO

9/13

TPM1.2@ 32.768KHZ_12.5P_1TJS125BJ2A251
2 NC
IN 1

NC
NC
NC

21
21

+3VL

2

2

1
2

R375
TPM1.2@ 0_0402_5%

1
2
@ 0_0402_5%

9/8

PP

1

C124
0.1U_0402_16V4Z

3

SLB 9635 TT 1.2

1

R378
Base I/O Address
0 = 02Eh
TPM1.2@ 4.7K_0402_5%
* 1 = 04Eh

3

R397

3

+3VS

1

Place R1447 close to Y8.1

CLK_TPM

4

+3VS

25
18
11
4

2

L
33

2

2
TPM_GPIO
TPM_GPIO2

1

6
2

1

R379
@ 4.7K_0402_5%

7

4

VSB

VDD
VDD
VDD

B

GPIO
GPIO2

1

15

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

TPM1.2@ 0.1U_0402_16V4Z

2

LPC_PD#

26
23
20
17
22
16
28
27
21

GREEN

5

24
19
10

2

AMBER

C350

1

21,33

LPC_AD0
20,27,31,33 LPC_AD0
LPC_AD1
20,27,31,33 LPC_AD1
LPC_AD2
20,27,31,33 LPC_AD2
LPC_AD3
20,27,31,33
LPC_AD3
+3VS
LPC_FRAME#
20,27,31,33 LPC_FRAME#
PLT_RST#
7,19,20,21,23,25,27,33
PLT_RST#
1 R402
2
TPM1.2@ 10K_0402_5% 21,23,31,33 SIRQ
SIRQ
LPC_PD# 2 R401
CLK_PCI_TCG
1
15 CLK_PCI_TCG
TPM1.2@ 0_0402_5%
C3922
1
2 R415
1
+3VS
@ 10_0402_5%
@ 10P_0402_50V8K
PM_CLKRUN#
21,23,31,33 PM_CLKRUN#

GREEN
1

1

D27

19-22SOVGC/TR8_GRN/ORG

AMBER

TPM1.2@ 0.1U_0402_16V4Z
1
1
C349
C393
C394

TPM1.2@ 0.1U_0402_16V4Z
2
2
2
U26
TPM1.2@ 0.1U_0402_16V4Z

B

HDD LED

19-22SOVGC/TR8_GRN/ORG

2

1

+3VALW

D30

1

+3VS

Battery LED

3

9/2

TPM1.2 on board

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
TCG/BIOS ROM/PS2/LED/SW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

32

of

52

5

4

3

+3VL

1

C196
0.1U_0402_16V4Z

2

C215
0.1U_0402_16V4Z

1

2

C243
0.1U_0402_16V4Z

1

2

C255
0.1U_0402_16V4Z

1

2

C257
4.7U_0805_10V4Z

2

1

+3VS

1

1

2

2

1

C244
0.1U_0402_16V4Z

2

1

C226
0.1U_0402_16V4Z

2

1

C209
0.1U_0402_16V4Z

2

C236
4.7U_0805_10V4Z

+3VL

BIOS debug port
Place under KB area

D

RP21

8
7
6
5

KSI7
KSI6
KSI5
KSI4

10K_1206_8P4R_5%

Pin3 250 : KSO12/OUT8/KBRST
+5VS

34

KSI[0..7]

R192

1

2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK

10K_0402_5%
R197
1
2 TP_DATA
10K_0402_5%

25
24
23
22
21
20
19
18

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

10K_1206_8P4R_5%

L

+3VS

Note: R94 must be removed when
R1354 stuff and R87 remove.

21,23,31,32 PM_CLKRUN#
21,23,31,32 SIRQ
15 CLK_PCI_EC
21 RUNSCI_EC#

R216
1
2 LPCPD#
10K_0402_5%
R262

1

2

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

34 TP_CLK
34 TP_DATA
35 KBD_CLK
35 KBD_DATA
35 PS2_CLK
35 PS2_DATA

10K_0402_5%

21,31 NPCI_RST#
7,19,20,21,23,25,27,32
PLT_RST#
21,32 LPC_PD#
Pin34 250 -- LPCPD#

11/14 NPCI_RST#
PLT_RST#
ADP_EN

R651
R652
R215
R223

1
1
1
1

2
2
2
2

PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#

44
46
43
59

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#

40
39
37
35
41
42
34

0_0402_5%
@ 0_0402_5%
@ 0_0402_5%
@ 0_0402_5%

LPCPD#
CRY1
CRY2

2 @ 2M_0402_5%
R266
2
1
120K_0402_5%

XTAL1
XTAL2

51

VCC0

2

2

10P_0402_50V8J

1

55

+RTCVCC

1

2

GPIO07/PWM3
GPIO08/RXD
GPIO09/TXD
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2
GPIO17/A20M
GPIO20/PS2CLK
GPIO21/PS2DAT
GPIO24/KSO16
GPIO27

AB1A_DATA
AB1A_CLK

Access Bus Interface

AB1B_DATA
AB1B_CLK
PGM Strap/GPIO25
EA Strap#/GPIO26/KSO17
CLOCK
32KHZ_OUT/GPIO22
RESET_OUT#/GPIO06
PWRGD
VCC1_PWRGD
24MHZ_OUT/GPIO19/WINDMON

LFRAME#
LRESET#
LPCPD#/GPIO23

4

1
IN
C267

OUT

@ 10P_0402_50V8J

LAD[3]
LAD[2]
LAD[1]
LAD[0]

Y3

NC

1

C237

NC

2

TEST PIN

10P_0402_50V8J

C263

1U_0603_10V4Z

2

1

1

2

BATSELB_A#
KBRST#
INV_PWM
FAN_PWM
CHGCTRL

82
62
63
64
66

FWP#
ON/OFFBTN_KBC#
LOW_BAT#
KSO14
KSO15

68
69
70

PM_RSMRST#
GPIO8 R280 1
GPIO9 R281 1

71
72
73
74
75
76
77

BATCON
EC_GPIO12
EC_GPIO13
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M
NUM_LED#
SLP_S3#
R185 1
MODE
Pin57 250 -- MODE
R202 1

78
80
1
57

56
83
48
58
49
61
60
50
52

JP21

10K_0402_5%

41

2

KB_RST#

GPIO9
GPIO8

20

CH751H-40_SC76

Pin82 250 -- nFWP
ON/OFFBTN_KBC#
LOW_BAT# 21
KSO14 34
KSO15 34
PM_RSMRST# 21

34
+3VL

2 250@ 0_0402_5% KSO16
2 250@ 0_0402_5% KSO17
D24
2
BATCON 41

1

ADP_PRES

CH751H-40_SC76
2 R255
1
+3VL
10K_0402_5%
D26
1
2
GATEA20
CH751H-40_SC76

THM_MAIN# 1 R259
2
210K_0402_1%
EC_GPIO12 1 R263
2
100K_0402_5%
EC_GPIO13 1 R194
2
100K_0402_5%

18,25,40,41,42,47

THM_MBAY# 46
PCI_SERR#
19,23
THM_MAIN# 46

C

20

+3VL

NUM_LED# 27,34
SLP_S3# 18,21,25,27,28,29,35,36,40,43,44
KSO16 34

RP24
AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

2
1021@ 0_0402_5%
Pin1 250 -- TEST Pin ( NC !! )
2 0_0402_5%
EAPD 28,29

EC_GPIO10
AMBER_BATLED#
STB_LED#
CAPS_LED#

KBC1021_TQFP100

0.1U_0402_16V4Z

AGND FILTER

ADP_ID
ADP_PS1

47

ADP_PS0

47

FWP#

2

10_0402_5% 10P_0402_50V8K
@
@

R274

1

PM_POK

2

10K_0402_5%
B

+3VL

R264 1

0.1U_0402_16V4Z

C245

2 1

EC_GPIO12

R251 1

PGM

2

R246
CLK_14M_KBC 1

+3VL

EC_GPIO12

MODE

1

100K_0402_5%

AMBER_BATLED# 32
STB_LED# 27,32,35
CAPS_LED# 27,34

EC_GPIO19

C254
1
2

8
7
6
5

R250
NUM_LED#

Pin91 250 -- nDMS_LED

2
0_0402_5%
2
0_0402_5%
EC_GPIO10 R214 1
2
0_0402_5%
R260
1
2
@ 33_0402_5%
S_CLK
R261
1
2
0_0402_5%
R399
1
2
@ 0_0402_5%

1
2
3
4

4.7K_1206_8P4R_5%

AB1A_DATA 46
AB1A_CLK 46

AB1B_DATA
AB1B_DATA 46
AB1B_CLK
AB1B_CLK 46
R204 1
2 0_0402_5%
A_SD 29
Pin56 250 -- PGM
PGM
Pin83 250 -- nEA ( pull up !! )
EA#
1
2 R238
KSO17 34
1021@ 0_0402_5%
CLK_14M_KBC
CLK_14M_KBC 15
S_CLK
PM_POK
PM_POK 7,21
PWR_GD_EC
Pin58 250 -- 32KHz_OUT
VCC1_PWRGD
VCC1_PWRGD
37
Pin49 250 -- Reset Out
EC_GPIO19
Pin50 250 -- 24MHz_Out
TEST
1
2
Pin52 250 -- XOSEL
R249
300_0402_5%

91
88
90
89

1
2
3
4
5
6
@ ACES_85201-0602

VCC1_PWRGD

D25

1

INV_PWM 17
FAN_PWM 4
CHGCTRL
40,41

AB1A_DATA
AB1A_CLK

86
87
84
85

BATSELB_A#

1 R647
2
100K_0402_5%

C253

32.768KHZ_12.5P_1TJS125DJ2A073

98
97
96
95
93

KBC_PWR_ON
42
GREEN_BATLED# 32

FWP#

DMS_LED#/GPIO10
BAT_LED#
PWR_LED#/8051TX
FDD_LED#/8051RX

C268

3

2

@ 10_0402_5%

Power Mgmt/SIRQ

AGND

1

R265 1

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

53
54

CLK_PCI_EC
R232

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

LPC
Bus

20,27,31,32 LPC_AD3
20,27,31,32 LPC_AD2
20,27,31,32 LPC_AD1
20,27,31,32 LPC_AD0
20,27,31,32 LPC_FRAME#

RUNSCI_EC#

26
27
29
31
32
33

Miscellaneous

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

GPIO01
GPIO02
GPIO03
GPIO04/KSO14
GPIO05/KSO15

KBC_PWR_ON
GREEN_BATLED#

GND
GND
GND
GND
GND
GND
GND

8
7
6
5

92
79
65
45
36
28
8

1
2
3
4

OUT0
OUT1/IRQ8#
OUT7/SMI#
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

RP23

C

B

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18

99
100

D

+3VL
R205

General Purpose I/O Interface

RP22

17
16
15
14
13
12
10
9
7
6
5
4
3
2

Keyboard/Mouse Interface

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

2

KSO[0..13]

VCC2
VCC2
VCC2

KSO[0..13]

30
38
47

U18
34

10K_1206_8P4R_5%

1
2
3
4

11
67
81
94

+3VL

KSI3
KSI2
KSI1
KSI0

VCC1
VCC1
VCC1
VCC1

8
7
6
5

SMSC_LPC47N250_TQFP-100P

1
2
3
4

JP22

47

CB_CLK

1
2
3
4
5
6

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

24

ADP_EN

ADP_EN

CLK_TPM

47

@ ACES_85201-0602

32

For KBC debugging used.

R268 1
2
250@ 10K_0402_5%
R267 1
2
@ 1K_0402_5%
R2761
2
@ 1K_0402_5%

1. For normal operation:
+3VL

Un-install R29,R65

J9
PGM 1
2 R2821
2
NO SHORT PADS
1K_0402_5%
PWR_GD_EC

R670 1
R669 1

PWR_GD
2 0_0402_5%
2 @ 0_0402_5% PGD_IN

11/21

A

PWR_GD 18,36,37,45,47
PGD_IN 37,45

FWP#
TEST
EA#

250@
R127
R128
R977
R62

1021@
R129
R131
R78

2. For KBC internal ROM flash:

2005/03/10

2006/03/10

Deciphered Date

A

Install R29,R65

Compal Secret Data

Security Classification
Issued Date

R2752
1
@ 1K_0402_5%
R2542
1
@ 1K_0402_5%
R2352
1
1K_0402_5%

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

LPC47N1021
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
1

33

of

52

INT_KBD CONN.

SWITCH BOARD.
+3VS

+3VL

+5VS

JP1

29

1
3
ON/OFF#
5
MUTE_LED# 7
KSO2
9
KSI6
11
KSI7
13
KSI5
15
17
19
21
23
25
27
29

MUTE_LED#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

STB_LED
KSI0
NUM_LED#
CAPS_LED#
KSI1
WL/BT_LED
LID_SW#_2nd
KSI2

STB_LED

33

KSO[0..17]

33

KSI[0..7]

2 LID_SW#
0_0402_5%

1
R1

11/3

JP12

NUM_LED#
CAPS_LED#

27,33
27,33

WL/BT_LED

32

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

KSI4

LID_SW#

KSI[0..7]

32

ACES_88028-3000
LID_SW#_2nd

KSO[0..17]

17,21

MDC 1.5 Conn.

27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

ACES_85203-26021
+3VS

JP26

R239 1
2
33_0402_5%

AC97_SYNC_MDC
AC97_SDIN1_MDC
AC97_RST#_MDC

13
14
15
16
17
18
19
20

+3VS

1
C220

1

MDC1.5@ 1000P_0402_50V7K
2
MDC1.5@

C223

2
4
6
8
10
12

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

1

CP1
AC97_BITCLK_MDC

AC97_BITCLK_MDC

KSO0
KSO2
KSO3
KSO4

20

2
1
1
2
R209
C221
@ 10_0402_5% @ 10P_0402_25V8K

13
14
15
16
17
18
19
20

AC97_SYNC_MDC
20 AC97_SDIN1
20 AC97_RST#_MDC

1
3
5
7
9
11

AC97_SDOUT_MDC

AC97_SDOUT_MDC

20

MDC1.5@

4
3
2
1

CP4
KSO12
KSO1
KSO17
KSO13

5
6
7
8

100P_1206_8P4C_50V8

4
3
2
1

KSO5
KSO6
KSO7
KSO8

Connector for MDC Rev1.5
C204

@ 4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

4
3
2
1

CP5
KSO15
KSO16
KSI2
KSI3

5
6
7
8

100P_1206_8P4C_50V8

4
3
2
1

5
6
7
8

100P_1206_8P4C_50V8

CP3

4
3
2
1

5
6
7
8

100P_1206_8P4C_50V8

CP2

TYCO_1-179396-2~D

KSO9
KSO10
KSO14
KSO11

CP6
KSI6
KSI4
KSI1
KSI5

5
6
7
8

100P_1206_8P4C_50V8

4
3
2
1

5
6
7
8

100P_1206_8P4C_50V8
CP7
KSI0
KSI7

4
3
2
1

5
6
7
8

100P_1206_8P4C_50V8

Power button

+3VL

+3VL

1

+3VL

1

R163

ON/OFF#

13

1
C177
1U_0603_10V4Z

2

I
G

ON/OFF#

100K_0402_5%
1
C183

1

U15F
SN74LVC14APWLE_TSSOP14
R172
2
O 12 1

ON/OFFBTN_KBC#

ON/OFFBTN_KBC#

2

+5VS

JP11
+3VALW

Q29
2N7002_SOT23

R179
SP_DATA

1
2
100K_0402_5%

S

8
6
4
2

D23
1U_0603_10V4Z

T/P BOARD.

33

D

2
G
3

14
P

2
35

TrackPoint CONN.

100K_0402_5%

100K_0402_5%

2

R167

7

20

Update to 18x8 angelfire keyboard matrix

1

2

ON/OFFBTN#

ON/OFFBTN#

8
6
4
2

JP14

7
5
3
1

7
5
3
1

+5VS
SP_CLK

1
+5VS

E&T_6700-Q08N-00R

21

RB751V_SOD323

2

C116

0.1U_0402_16V4Z

11/3

1
2
3
4
5
SP_DATA
6
7
SP_CLK
8
ACES_87212-0800

2005/03/10

Deciphered Date

2006/03/10

+5VS

TP_DATA
TP_CLK

Compal Secret Data

Security Classification
Issued Date

33 TP_DATA
33 TP_CLK

Title

1

2

C490
0.1U_0402_16V4Z

Compal Electronics, Inc.
MDC/KBD/ON_OFF/LID

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet

34

of

52

A

B

C

D

E

1

+5VALW

R357

11/22
2

220K_0402_5%
JP2

11/18

SLP_S5#_5R

1000P_0402_50V7K
2

2

2
G
Q62
2N7002_SOT23

SLP_S5

D
Q77

S

2
G

1

C546

ON/OFF#

ON/OFF#

26
26

MDO2+
MDO2-

26
26

MDO0+
MDO0-

MDO2+
MDO2MDO0+
MDO0LAN_ACT#_DOCK
LANLINK_STATUS#_DOCK

16 D_VSYNC
16 D_HSYNC
16 D_DDCDATA
16 D_DDCCLK
18 DVI_DETECT

D_DDCDATA
D_DDCCLK
DVI_DETECT
D_RED
D_GREEN
D_BLUE

2

16,18
16,18
16,18
28

M_COMP
M_CRMA
M_LUMA

LINE_IN_SENSE
47

ACOCP_EN#

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

31

DCD#1
31 RI#1
31 DTR#1
31 CTS#1
31 RTS#1
31 DSR#1
31 TXD1
31 RXD1

LPTSTB#
LPTAFD#
LPTERR#

31 LPTSTB#
31 LPTAFD#
31 LPTERR#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

1

11/23
JP27B

2

DOCKVIN

DETECT
MDO3+
MDO3-

MDO3+
MDO3-

26
26

MDO1+
MDO1-

MDO1+
MDO1-

26
26

PWR_LED
SLP_S5#_5R
1
2
11/22
R346
10K_0402_5%
DVI_DDC_CLK
DVI_DDC_CLK
18
DVI_DDC_DAT
DVI_DDC_DAT
18
DVI_TX2DVI_TX2+
DVI_TX1-

DVI_TX2-

18

DVI_TX2+

18

DVI_TX1-

18
21

DVI_TX1+
DVI_CLKDVI_CLK+

DVI_TX1+

18

DVI_CLK-

18

DVI_CLK+

DVI_TX0DVI_TX0+
DOCK_ADP_SIGNAL
DOCK_ID

18

DVI_TX0+

18

USB20_N6

21

USB20_P6

21

USB20_N7

21

18

DVI_TX0-

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

31 LPTACK#
31 LPTBUSY
31 LPTPE
31 LPTSLCT
31 LPD7
31 LPD6
31 LPD5
31 LPD4
31 LPD3
31 LPD2
31 LPD1
31 LPD0
31 LPTSLCTIN#
31 LPTINIT#

USB20_P7

USB20_N6 R301 2
1USB20_N6_R
0_0402_5%
USB20_P6 R300 2
1USB20_P6_R
0_0402_5%
USB20_N7 R304 2
1USB20_N7_R
0_0402_5%
USB20_P7 R298 2
1USB20_P7_R
0_0402_5%
SER_SHD
31 SER_SHD
EXPCRD_RST#
31 EXPCRD_RST#
DETECT

165
166
167
168
169
170

DOCK_ADP_SIGNAL
DOCK_ID
21
+3VS
R9

DOCK_ID

5/24

1

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

KBD_DATA 33
KBD_CLK 33
CPPE# 15,19
PS2_DATA 33
PS2_CLK 33
DOCK_HPS#
29

DLINE_IN_L
DLINE_IN_R

DLINE_IN_L
DLINE_IN_R

DLINE_OUT_L
DLINE_OUT_R

PCIE_TXP4

PCIE_TXP4

PCIE_TXN4

PCIE_TXN4

PCIE_C_RXP4

1 R3
2PCIE_RXP4
0_0402_5%
1 R4
2PCIE_RXN4
0_0402_5%

PCIE_C_RXN4

28
28

DLINE_OUT_L
DLINE_OUT_R

CLK_PCIE_DOCK

29
29

21
21

21

PCIE_RXN4

21

CLK_PCIE_DOCK

CLK_PCIE_DOCK#

2

PCIE_RXP4

15

CLK_PCIE_DOCK#

PREP#
VA_ON#

PREP#

15

21,26

1

34

1
2
ACES_85205-0200

PREP#

S
@ 2N7002_SOT23

@1U_0603_10V6K

P1

1
2
@ 22K_0402_5%

1000P_0402_50V7K

JP27A

G1

DOCK_MOD_RING
DOCK_MOD_TIP

R671

1

D

3

29,30,36

3

1

1

L14
KC FBM-L18-453215-900LMA90T_1812
2
1
VIN
DOCKVIN
1
1
C314
C305

GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND

171
172
173
174
175
176

1K_0402_5%

G2
DOCK_MOD_RING RING

ADP_SIGNAL
R299

JAE_SP03-14588-PCL03
DOCK_ADP_SIGNAL 1

G2

P2

RING

TIP

C1
1

P2
TIP

2

C291
0.1U_0402_16V4Z

+5VS

2

@ 10K_0402_5%

1

R302

2

DOCK CONN. 184PIN

2

@ 22U_0805_6.3V4Z
DOCK_MOD_TIP
9/15

JAE_SP03-14588-PCL03

2

L

Note: Place C1 close to JP27.P2 pin

1K_0402_1%
3

3

Place them close to U50/U51/U52

RED
GREEN
BLUE

V_3P3_LAN

1

R372
2
1
10K_0402_5%

+3VS
C5

2

1

C6

2

U3
0.1U_0402_16V4Z
18

D_BLUE
16 BLUE

ISO_PREP#

1
2

ISO_PREP#

4

OE

R352
10K_0402_5%

U1

U2
0.1U_0402_16V4Z

VCC
A
B

+3VS

2

18

D_GREEN
16 GREEN

5

D_GREEN
GREEN

1
2

ISO_PREP#

4

0.1U_0402_16V4Z

VCC
A
B
OE

18

D_RED
16 RED

5

D_RED
RED

1
2

ISO_PREP#

4

VCC

4

3

GND
FSA66P5X_SC70-5

3

GND
FSA66P5X_SC70-5

S

Q58
2N7002_SOT23
LAN_ACT#

PWR_LED

A
B

27,32,33

STB_LED#

OE

LAN_ACT#

25,26

LANLINK_STATUS#_DOCK

D
Q61
2N7002_SOT23

2
G
3

21

5

D_BLUE
BLUE

1

D

2
G

2

1

1

+3VS
C8

LAN_ACT#_DOCK

1

+3VALW

3

D_BLUE R6

1
2
@ 0_0402_5%
1
2
@0_0402_5%
1
2
@0_0402_5%

18,21,25,27,28,29,33,36,40,43,44

S

S

Q59
2N7002_SOT23
LANLINK_STATUS#

LANLINK_STATUS#

25,26

4

SLP_S3#

Compal Secret Data

Security Classification
Issued Date

D

2
G

3

GND
FSA66P5X_SC70-5

1

D_GREEN
R5

3

D_RED R7

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Docking CONN.
Rev
0.5

LA-2821P

Date:

D

Friday, November 25, 2005

Sheet
E

35

of

52

A

B

+5VALW to +5VS Transfer

C

E

+1.8V to +1.8VS Transfer
+1.8V

+1.8VS

+5VS
S

+5VALW

D

Q53
SI2306DS-T1 1N_SOT23

U22

D
S 1
2
D
S
3
D
S
4
D
G
SI4800DY_SO8
2 10U_0805_10V4Z
C277

3

D

1
1

1

C271

C295
1U_0603_10V4Z

2

2

1

1

C280
10U_0805_10V4Z

1

C296
+5VALW

2

2

1U_0603_10V4Z

1

1

8
7
6
5

2
G

1

R62

RUNON
RUNON

100K_0402_5%

2

0.1U_0402_16V4Z

B+
J3

+3VALW

1

21,44

+3VS

SLP_S5#

SLP_S5#

U37

1

C514

330K_0402_5%

D
D
D
D

S
S
S
G

1

2

C510

2

1

C509

2

+VCCP

C29

+VCCP

C526 1

2 @ 0.1U_0603_50V4Z

+3VALW

R583

+3VS

C155 1

2 @ 0.1U_0603_50V4Z

+3VALW

470_0402_5%

+3VS

C141 1

2 @ 0.1U_0603_50V4Z

+5VS

+3VS

C139 1

2 @ 0.1U_0603_50V4Z

+5VS
+3VS

1

1

RUNON
0.1U_0402_16V4Z

1 2

D

3

PAD-SHORT 2x2m

2

2

S

1

Q75
2N7002_SOT23

SLP_S3 2
G

2

Q9
2N7002_SOT23

10U_0805_10V4Z

1
2
3
4

SI4800DY_SO8
2 10U_0805_10V4Z

J15

S

C501
0.01UF_0402_25V7K

1

0.1U_0603_50V4Z

2

+1.5VS

C524 1

2 @ 0.1U_0603_50V4Z

+3VALW

C419 1

2 0.1U_0402_16V4Z

+3VS

C290 1

2 0.1U_0402_16V4Z

+3VS

2

+3VL

1

8
7
6
5

1

R582

D

2
G

2

PAD-SHORT 2x2m

1

SLP_S5

SLP_S5

3

29,30,35

+3VALW to +3VS Transfer

R244

2

100K_0402_5%

+2.5VS

18,21,25,27,28,29,33,35,40,43,44

SLP_S3#

SLP_S3#

U32

1

8
7
6
5

C456

D
D
D
D

1
2
3
4

S
S
S
G

1

SI4800DY_SO8
2 10U_0805_10V4Z

C487

2

1

2

1
+2.5VALW

D

3

SLP_S3

+2.5VALW to +2.5VS Transfer

S

Q43
2N7002_SOT23

2
G

C458
10U_0805_10V4Z

RUNON
0.1U_0402_16V4Z
3

3

Discharge circuit
+1.8V

+1.8VS

+2.5VS

1

1

1

18,33,37,45,47

+1.5VS

+5VS
R94

R571

R574

R138

R32

470_0402_5%

470_0402_5%

470_0402_5%

470_0402_5%

1

1

1

+0.9V

1

PWR_GD

+3VS

R93

R577

S

SLP_S3 2
G

470_0402_5%

Q16
2N7002_SOT23

1 2

Q18
2N7002_SOT23

D

D

3

S

SLP_S3 2
G

1 2

2
D

3

Q7
2N7002_SOT23

1

S

SLP_S3 2
G

470_0402_5%

3

Q19
2N7002_SOT23

1 2

S

SLP_S3 2
G

D

3

Q74
2N7002_SOT23

1 2

S

SLP_S5 2
G

D

3

Q73
2N7002_SOT23

1 2

S

2
G

D

3

1 2
SLP_S5 1 R573
2
@ 0_0402_5%
SLP_S3 1 R572
2
0_0402_5%

D

3

470_0402_5%

S

SLP_S3 2
G

Q72
2N7002_SOT23

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

D

DC/DC Circuits
Rev
0.5

LA-2821P

Friday, November 25, 2005

Sheet
E

36

of

52

+1.8VS

+3VS

+3VS

2

2

2

+3VL

+3VL

+3VL

2

2

R184

2

100K_0402_5%

RB751V_SOD323
SN74LVC14APWLE_TSSOP14

D

S

P

+3VS

9

I

0.1U_0402_16V4Z

1
1

3

E

+3VL

VCC1_PWRGD
U15D

1

E
Q26
MMBT3904_SOT23

C181

1

2

R156

O

8

C186

33

Q33
2N7002_SOT23

2
G

G

1

4

3

O

14

I

2

SN74LVC14APWLE_TSSOP14

+5VS

10K_0402_5%

P

1

D20

7

C

U15B

G

1

Q25
MMBT3904_SOT23

3

3

1

C

2
B

R171
1
2
47K_0402_5%

2

O
G

I

7

1
2
B

U15A

P

1

1

1

R188

330_0402_5%

14

R157

14

R158
330_0402_5%

7

R139
1K_0402_5%

1

+3VL
+3VL

SN74LVC14APWLE_TSSOP14

0.1U_0402_16V4Z

1

1
R177

2

2

10K_0402_5%
C176

J8

0.1U_0402_16V4Z

1

180K_0402_5%

1

D

3

S

1

14

U15C

D

P

2

I

6

O

2

2

R210

7

Q31
MMBT3904_SOT23

SN74LVC14APWLE_TSSOP14

1

H24
HOLEA

1

H27
HOLEA

1

H19
HOLEA

1

1

H6
H8
HOLEAHOLEA

1

H5
HOLEA

S

E

3

H25
HOLEA

Q32
MMBT3904_SOT23

2
B

H4
HOLEA

1

H2
HOLEA

1

H1
HOLEA

1

H3
HOLEA
Q24
2N7002_SOT23

2
G

1

1
1

10

O

C

2
B

U15E

G

I

3

1

1

1

330_0402_5%

C

VCCP_POK

UNUSED PARTS

2

R178
330_0402_5%

11

43

18,33,36,45,47

+3VL

14

R196
1K_0402_5%

PWR_GD

0.1U_0402_16V4Z

+2.5VS

2

2

+2.5VS

C190

SN74LVC14APWLE_TSSOP14

P

+1.5VS

7

1

1

R181

PWR_GD

Q23
2N7002_SOT23

2
G

G

5

560K_0402_5%

2

PAD-SHORT 2x2m

H26
HOLEA

H16
HOLEA

H13
H18
HOLEAHOLEA

H20
HOLEA

H17
HOLEA

+3VS

45

0.1U_0603_16V7K

1

FM2

1

FM4

1

FM5

1

1

1

1

1

FM6

1

5
U34
PGD_IN
O 4
NC 1
SN74LVC1G17DBVR_SOT23-5

I

CF1
PGD_IN

1

33,45

CF2

1

CF3

1

CF4

1

CF5

1

CF6

1

CF7

1

CF9

1

CF11
1

1

CF12
1

CF8

CF10

1

2

R581
1
2
@ 0_0402_5%
PAD1

M1
HOLEA

M2
HOLEA

H11
H12
H23
H21
HOLEAHOLEAHOLEAHOLEA

H10
HOLEA

H14
H9
HOLEA HOLEA

H15
HOLEA

1

1

1

1

1

PAD-R118x71

1

1
1

CLK_ENABLE#

PGD_IN_1

2

FM3

1

1

CLK_ENABLE#

1 R580
2
O 4
100K_0402_5%
NC 1
SN74LVC1G17DBVR_SOT23-5
C497

FM1

0.1U_0402_16V4Z

1

15,45

PGD_IN_1

11/21

U33

I

2

1

R579
1
2
@ 0_0402_5%

2

C500

1

2 RB751V_SOD323

P

R578
1
2
0_0402_5%

1

G

5

D33

P

2

1

G

L

3

PWR_GD

1

+3VS

Need be tune to
3msec time delay

1

3

C502
0.1U_0402_16V4Z

1

1

3

E

11/21

CPU

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

POK CKT
Rev
0.5

LA-2821P

Date:

Friday, November 25, 2005

Sheet

37

of

52

5

4

3

2

1

D

D

AC
Adapter
in

ADP_EN#

VIN

+3VALWP

LM358
Thermal
Protector

SWITCH

MAINPWON

ENBL2 ENBL1

B+

APL5151
LDO
(3V)

VL

VL

+2.5VALWP 0.4A
VL

SHDN#

+3VALWP

+5VS

TPS51020
DC/DC
(3V/5V)

C

APL5508
LDO
(2.5V)

PWR_GD

B+

+3VLP 0.1A

C

VCC

SHDN#

+5VALWP
VIN

ISL6260&ISL6208
DC/DC
(CPU_CORE)

BQ24703
Charger

MAX8743
DC/DC
(1.05V/1.5V)

B+
B

SLP_S3#

ENBL1/ENBL2

+1.5VSP 4.2A
CPU_CORE
( 44A)
+1.05V_VCCP 6.4A

BATSELB_A

Battery
Selector
Circuit

BATSELB_A#

Battery A
8 Cell

VCC

Battery B
8 Cell

B+
SWITCH

A

B

+5VALWP

SWITCH

SWITCH

Battery
Connector
A

Battery
Connector
B

SLP_S3#/SLP_S5#

TPS51116
DC/DC
(+1.8VP/+0.9VSP)

+1.8VP 7A

+0.9VP 2A

S3/S5

A

BATT
BATT_A

Title

POWER BLOCK DIAGRAM

BATT_B
Size
Date:
2

Document Number
Friday, November 25, 2005

Rev
Sheet

38
1

of

52

A

B

C

D

1

1

VIN
PJP13

9

GND_3
GND_4

PWR2

2

FOX_JPD113E-LB103-7F

2

PC2
1000P_0402_50V7K

1

GND_2

1

PR1
15K_0402_5%

2

1

PC3
100P_0402_50V8J
2
1

PWR1

PC4
1000P_0402_50V7K
2
1

ADPIN

GND_1

2

8

GND2

PL1
FBMA-L18-453215-900LMA90T_1812

ADP_SIGNAL

1

7

5

2

6

SINGAL

1

4

GND1

PC1
100P_0402_50V8J

3

2

2

3

3

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Compal Electronics, Inc.
DCIN

Size
Document Number
Custom LA-2821
Date:

Rev

Friday, November 25, 2005

Sheet
D

39

of

52

A

B

C

D

1

1

VIN

P2

BATT
PQ3
AO4407_SO8

P4
PQ5
AO4407_SO8
1
2
3

1
2
3

1
2
3

1
1
2

1
2

AC_CHG

PU6

REF

ANODE

1.24VREF

CATHODE

3

NC

2

NC

1

LMV431ACM5X_SOT23-5

RHU002N06_SOT323

D

S

PQ13
2
G

D

PC17
10U_1206_25VAK

PC16
4.7U_1206_25V6K
2
1

1
PR57
47K_0603_0.5%

2

2

PR64
15K_0402_1%

2

1

PQ12
2
G

3

33K_0402_1%

2
1
PC205
470P_0402_50V7K

PR61
100_0402_5%

PR59
75K_0402_1%

1

1

41

2
2

1
PR39
3K_0402_1%
2
1

1
2
1

41

2
1
PC25
100P_0402_50V8J

VL

5

ALARM

2

1
PR63
@ 47K_0402_1%

LM393DG_SO8

PR38
3K_0402_1%

2
PR47
604K_0603_0.1%

1
AC_CHG

PR67

1

4

2

1
2

8
-

7

2

5
6
7
8
1
2

18,25,33,41,42,47

BATT

1

BATT

3

1 2

G

CV=16.8V (8 CELLS LI-ION)
CC=3A

PR43
150_0402_1%

BQ24703VREF

G

O

2

0.1U_0402_16V7K

PR58
2
100K_0402_5%

P

+

4

PC26
0.022U_0402_16V7K
2
1

6

PC19

SE_CHG-

2
P

5

PD8
EC31QS04

PR50
10K_0603_0.1%

1

PU5B

2

15U_PLC1045P-150A_3.7A_20%

+3VL

PC24
@ 0.1U_0402_16V7K

1

PR33
0.015_2512_1%
1
2

1

PU4
SN74LVC1G17DBVR_SOT23-5
ADP_PRES
O 4
NC 1

3

LX_CHG

6
1
17
23
14

PR52
4.7K_0402_5%

2
1M_0402_5%

PL3

SE_CHG+

1
2

2
1
PR45
10K_0402_1%

8

LM393DG_SO8

4
1

2
1

I

G

-

2

BATT

18
20

PR56

10K_0603_1%

2

1

O

BATSET
BATDEP
GND
NC4
NC3

4

BQ24703_QFN28

PC22
0.1U_0402_10V6K

+3VL

5

PR62

PU5A

P

+

2

COMP
NC1
NC2

VS
VHSP

PQ8
SI4835BDY-T1-E3_SO8
DH_CHG

2

100K_0603_1%

1
2
1

3

1

2

PR240
2.15K_0402_1%
1
2
12.4K_0603_0.1%

PR44
PR49

VL

PR55
130K_0402_1%

4

+3VL

ENABLE
ACSEL
ALARM
SRSET
ACSET
ACPRES
IBAT
VREF

ACDRV#

1

+3VL

2
330K_0402_5%

5
28
19
2
3
27
13
4
7
10
11

150P_0402_50V8J
PC21
2
1

1
2
1

PR42

1

2

PC20

P2

3

1U_0603_6.3V6M
2
1

ACDET

PR41
PR36
80.6K_0402_1%
100K_0402_1%
2
1

2 PR32
1
+3VL
100K_0402_5%
BQ24703VREF

PR35
100K_0402_1%

2
1

2

PC15
1

CHGCTRL

1U_0603_6.3V6M

33,41

2 PR29
1
1K_0402_1%
ALARM

2
191K_0402_1%

25
22
21
16
15
12
24

1

PR31

1

ACDRV#
VCC
PWM#
SRP
SRN
BATP
BATDRV#

2

PR51
604K_0402_1%

AC_CHG

CHGLIM

ACN
ACP
ACDET

1 2

47

8
9
26

PC18
4.7U_0805_6.3V6K

2
1
PR376
@ 0_0402_5%

SLP_S3#

PU2

PC14
1U_0805_25V4Z

D

S

PQ91
@RHU002N06_SOT323

9,33,35,36,43,44

PD6
RLZ16B_LL34

PR26
0_0402_5%
2
1

PC23
4.7U_0805_10V6K

1

2

PC198
1U_0603_6.3V6M
1
2
PR339
1K_0402_1%

47

PC12
4.7U_1206_25V6K

1
2

2
2

1

ADP_EN#

1

3

PD32
@1N4148_SOD80
1 1
2

4

CHG_B+

ADP_PRES

4

RHU002N06_SOT323

3

2

G

2

PR15
0_0402_5%
1
2

47

1

ACN
PR338
100_0402_1%

PD33
1N4148_SOD80

8
7
6
5

PL2
FBM-L11-322513-151LMAT_1210
1
2

PC11
10U_1206_25VAK

PR17
1
2
0_0402_5%

ACDRV#

PR372
0.015_2512_1%
1
2

PR20
150K_0402_5%
+3VL

P2

4

4

B+

PR14
200K_0402_5%

2

8
7
6
5

2

47K

47K

8
7
6
5

1

PR16
1

PC10
47P_0402_50V8J
1
2
2

1
2
3

0.1U_0603_16V7K
2
1

PQ6
DTA144EUA_SC70
1

3

PC138
2
1

47K_0402_5%
2

PQ4
AO4407_SO8

S

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.
Charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

LA-2821

Date:

C

Friday, November 25, 2005
D

Sheet

40

of

52

A

B

C

D

S

PQ16
RHU002N06_SOT323
D

1

2

3
+3VL

PR71
1.5M_0402_5%

PD11
RLZ6.2C_LL34

2
1

5

3

NC

P

PU9

Y

4

D

S

BATT

SN74LVC1G14DCKR_SC70-5

1

3

1

G

A

D
PQ19
RHU002N06_SOT323

2
G

ADP_PRES

18,25,33,40,42,47

S

SN74AHC1G08DCKR_SC70
PQ26
BATT_IN 2
G
RHU002N06_SOT323

1

1

PR77
4.7K_0402_5%

B540C_SMC

RHU002N06_SOT323

PQ24
AO4407_SO8

D

PQ25
AO4407_SO8

1
2
3

S

S

2
2

S

1

BATT

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

1

2

D

1
2
3

PR79
470K_0402_5%

BATT_A

2

1

S

2
G

PD13

2
4

3

1
2

4

1
2

PQ22
RHU002N06_SOT323

D

4

O
IN2

10K_0402_5%
PC197
220P_0402_50V7K

3

IN1

1

1

2

1

1

D

3

5

4

SN74LVC1G14DCKR_SC70-5

3

Y

P

A

PD12

1

1N4148_SOD80
PQ23
2
G

G

2

PU11
PR78

3

P
BATSELB_A#

BATSELB_A

G

33

BATSELB_A#

PU10

NC

5

CFET_A

PR75
470K_0402_5%

3

1
PR76
10K_0402_5%

2

PQ20
RHU002N06_SOT323
BATT_IN 2
G

2

+3VL

2

+3VL

1

1
PQ21
PMBT2222A_SOT23-3

1

PR74
470K_0402_5%

3

2

3

2

BATT_IN
PD10
1N4148_SOD80

S

3

2
G

1
2
PR73
22K_0402_5%

2

1000P_0402_50V7K

2
0_0402_5%

+3VL

2
PC30

PR69

3 1

2

2
G

PQ18
RHU002N06_SOT323

G

1
2
PR72
22K_0402_5%

1

PQ17
D RHU002N06_SOT323

1

2

1
2
100_0402_5%

RB715F_SOT323

1

74LVC1G02_04_SOT353

1

PR68

D

1

2
G

3

G
74LVC1G02_04_SOT353

PQ15
RHU002N06_SOT323

2
3

2

1

PD9

BATT_B

4

1

O
INA

INA

3

PU7

INB

S

1

1000P_0402_50V7K

BATSELB_A#

2

PC29
1

2

4

2

1

P
O

0.1U_0603_50V4Z

PC27
1
PU8

INB

1

PC28
BATSELB_A

1

ALARM

2
PR70
47K_0402_5%

40

P

+3VL

1

BATT_A

G

5

5

2

1

@ 0.1U_0402_10V6K

+3VL

+3VL

1

4

1
2

1N4148_SOD80

PQ32
RHU002N06_SOT323

D

D

S

D

S

2
G

RHU002N06_SOT323

3

10K_0402_5%

PR86
4.7K_0402_5%

2

1

PQ31
2
G

2

1

B540C_SMC

2

3

2

PR88

PD15

1

3

SN74AHC1G08DCKR_SC70

PD16

1

3

PR80
470K_0402_5%

1
2
3

BATT_B
4

2
4

PQ28
AO4407_SO8

3

O

1
+3VL

2

IN2

G
ADP_PRES

1

5
IN1

2

P

1

2

PR85
470K_0402_5%

D

S

1

1
PQ29
PMBT2222A_SOT23-3

BATSELB_A#

3

3

1

RHU002N06_SOT323

PU13

PR87
10K_0402_5%
1

AC_CHG

PQ30

1
2
3

PR81
470K_0402_5%

1 2

40

PQ27
AO4407_SO8

G

PR84
10K_0402_1%

PR82
220K_0402_5%
1
2

G

I

1

PC31
1

2

2

SN74LVC1G17DBVR_SOT23-5
PU12
O 4
NC 1

3

1

1N4148_SOD80

1
2
PR83
470K_0402_5%

2

P

PD14

2

5
CHGCTRL

0.22U_0402_10V4Z

33,40

2

+3VL

3

S

CFET_B
PQ33

5

1

PQ34

1
2

PR237
100K_0402_5%

RB715F_SOT323

2

O
NC

I

4
1

BATCON

2
G

RHU002N06_SOT323

3

3

P

CFET_B

1
4

BATT_IN
PU14

3

2

G

PD17
CFET_A

33

RHU002N06_SOT323
BATT_IN 2
G

D

S
4

SN74LVC1G17DBVR_SOT23-5

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.
Battery selector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

LA-2821

Date:

C

Friday, November 25, 2005
D

Sheet

41

of

52

5

4

3

2

1

1
PR103
@ 0_0402_5%

27

2
G
PQ98
RHU002N06_SOT323

S

2
47

+

2

5
C

26

DDR#
REF_X

TPS51020DBTR_TSSOP30

ENBL1
OUT2_U
ENBL2
OUT2_D

SSTRT2

VBST2

COMP2

VO2

17

DH_3.3V_1

18

16
11

PR104
0_0402_5%

DL_3.3V
BST_3.3V 2
1
PC43
0.1U_0603_50V4Z

PQ38
DH_3.3V_2

20

7

OUTGND2

19

8
7
6
5

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

1
2
3
4

AO4912_SO8

PR109
10K_0402_5%

4

INV2

GND

SKIP#

SSTRT1

LX_3.3V

+3VALWP

PL6
10U_PLC1045-100_3.6A_20%
1
2

ADP_PRES 18,25,33,40,41,47
1

2
1 2
1
PR112
PC50
330_0402_5%
3300P_0603_50V7K

+

2
D

LX_5V
DL_5V

1

PC38
150U_D2_6.3VM_R45

24
VIN

VO1_VDDQ

28

2

PC39
220U_D3L_6.3M_R40

1
2

PC35
2.2U_1206_25V7K

2
1
PR98
12.7K_0402_1%
TRIP2

REG5_IN

+
DH_5V_1

2

B

PR113
10K_0402_1%

1
+3VALWP

1
+3VALW_POK

23

25

OUT1_D

1

PR365
100K_0402_5%

1
2

LL1

VREG5

2

PR106
1M_0402_5%
2
1

15

2

A

1

A

3

3

PR115
100K_0402_5%
2
1

VL

PQ42
SI2301BDS-T1-E3_SOT23-3

3
2
1
PR369
100K_0402_5%

1

4

2

5

2

BP

PC52
1U_0603_10V6K

Vout

PC53
@ 0.33U_0603_10V7K
2
1

SHDN#

1

Vin

2

3

GND

PC51
1U_0603_10V6K

1

14

1

30
29

2
PC47
820P_0603_50V7K
1
2

PR105
@1M_0402_5%
2
1

PQ101
SI2301BDS-T1-E3_SOT23-3

2

PU16
APL5151_SOT23-5

1

2
G
PQ41
RHU002N06_SOT323

+3VLP

VL

2

S

3

3

S

D

2ADP_PRES
G
PQ40
RHU002N06_SOT323

OUT1_U

PGOOD

1
1

D

B

33 KBC_PWR_ON

1

S

10

13

2
G
3

PQ39
RHU002N06_SOT323

VBST1

LL2

2

D

PR107
100K_0402_5%
1

1

VL

PR335
0_0402_5%

2

3

PC46
820P_0603_50V7K
1
2

2

1

+5VALWP

8

LX_5V

1

PC199
220U_D3L_6.3M_R40

1

46 MAINPWON

2

2

PC45
2200P_0402_50V7K
2
1

1

PC41 0.1U_0402_16V7K
9

BST_5V

PC36
0.1U_0603_50V4Z

OUTGND1
6

+5VALWP
PL5
10U_PLC1045-100_3.6A_20%

1

B++

COMP1

PR108
@ 0_0402_5%
1
2

2

1

PR102
100K_0402_5%
1
2

2
1
PC48
4700P_0402_25V7K

1

2
PR187
154K_0603_1%

21

PC40
4.7U_0805_10V4Z

+5VALWP

AO4912_SO8
PR100
0_0402_5%
1
2

2

12
22

C

PC42
0.47U_0603_10V7K

PR97
17.4K_0402_1%
2
1

+3VALW_POK

D

1

INV1

2
1
PR110
3.9K_0402_1%

VL

2

1
2
PR111
29.4K_0402_1%

PR101
0_0402_5%
1
2

PU15

1

TRIP1

PC37
4700P_0603_50V7K
2
1
2
1
PR96
2.7K_0402_1%

PR99
10K_0402_1%
1
2

VL

1
2
3
4

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

PL4
FBM-L11-322513-151LMAT_1210
2
1
B+

PC33
10U_1206_25VAK

1
8
7
6
5

PC34
2200P_0402_50V7K
2
1

PQ37
DH_5V_2

D

PC44
4.7U_1206_25V6K
2
1

PR90
49.9K_0402_1%
1
2

PC32
4700P_0603_50V7K
2
1 2
1
PR91
330_0402_5%

B++

2

PC120
@ 1500P_0402_50V7K

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3.3VALW/5VALW
Rev

LA-2821

Date:

2

Friday, November 25, 2005

Sheet
1

42

of

52

A

B

C

D

PL23
FBM-L11-322513-151LMAT_1210
2
1

1

2

PR328
0_0402_5%

8

2

7
5

1

PR342
0_0402_5%

2
+1.8VP

+1.05V_VCCP

1

PR319
0_0402_5%

13
3

1
2

PC203
220U_B2_2.5VM

PR258
5.1K_0402_1%

1
2
PR259
100K_0402_5%
2
1

1

PR341
47K_0402_5%
2
1

1

1
2

PR266
100K_0402_1%

PR267
100K_0402_1%

D

1

2

2
G

+5VALW

S
PQ93
RHU002N06_SOT323

D

2
G

2

PQ92 S
RHU002N06_SOT323

1

3

1

SLP_S3#

2

S

PQ95
RHU002N06_SOT323

PR371
@ 0_0402_5%
2
1

VCCP_POK 37

2
G
PQ94
RHU002N06_SOT323

PJP1

1

2

PR262
20K_0402_1%
2
1

PC147
0.22U_0603_10V7K

D

2

3

S

PR268
0_0402_5%

2

1

D

2
G
1

1

PR343
47K_0402_5%
1
2

3

+5VALW

1.5VSP/ +1.05V_VCCP/+2.5VALWP

+1.5VSP

2
1
@ 0_0402_5%

+

2
2

PR263
0_0402_5%

1

VCC_MAX8743

PR265

18,21,25,27,28,29,33,35,36,40,44 SLP_S3#

3

DL_1.5V

2VREF
PR260
100K_0402_5%
2
1

PC201
@ 0.001U_0402_50V7M

1

PC73
4.7U_0805_6.3V6K

GND

3
1

OUT

2

1
2

PC72
1U_0603_10V6K

IN

LX_1.5V

15
14
12

2
2

+3VALWP

DH_1.5V_1

1

PR261
10K_0402_1%

2

PU20
+2.5VALWP
APL5508-25DC-TRL_SOT89-3

ILIM2
ILIM1

PC185
4.7U_1206_25V6K

2
PGOOD
TON
ON1

DH_1.5V_2

1

FB1

PR333
0_0402_5%
2

2

OUT2
FB2
ON2

19
18
17
20
16

1

+1.5VSP

PL21
3.3UH_PCMC063T-3R3MN_6A_20%
1
2

PQ86

PC200
@ 0.001U_0402_50V7M

22 PC195

9
UVP

CS1
OUT1

MAX8743EEI+T_QSOP28~N

(400mA,40mils ,Via NO.= 1)

VCC

LX1
DL1

OVP

11

BST2
DH2
LX2
DL2
CS2

21

PC144
0.1U_0603_50V4Z
1

8
7
6
5

1

PR370
@ 0_0402_5%
1
2

VDD

2

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

3

2
1

2

1
2
28
1

DH1

REF

DL_1.05V

PR327
0_0402_5%
1
2

10

27
24

SKIP

LX_1.05V

VCC_MAX8743

6

26

GND

S
S
S
G
1
2
3
4

DH_1.05V_1

BST1

4
V+ 1U_0805_16V7K
2
1

PC194
0.1U_0603_50V4Z
2
1

8
7
6
5
D
D
D
D

PU28

2

25

SLP_S3#

1
2
3
4

BST_1.05V_1

PR330
0_0402_5%

PR331
0_0402_5%

PR257
100K_0402_1%

1

1
2
3

BST_1.05V_2

2

1

1

AO4912_SO8

BST_1.5V_2

1

23

2

2

DH_1.05V_2

PQ78
AO4702_SO8
PR329
5.1K_0402_1%

1
2

PC145
4.7U_0805_6.3V6K
1

PC191
330U_D2E_2.5VM

+

2

2

PC186
4.7U_1206_16V4Z

BST_1.5V_1

1

PR332
20_0603_5%

2

8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4

PC192
0.1U_0603_50V4Z

PL22
3.3UH_PCMB104E-3R3MS_11A_20%
2
1

+1.05V_VCCP

1

1U_0805_50V4Z
PC190

PC188
2200P_0402_50V7K

1

1

PD31
CHP202UPT_SOT323-3
PQ79
AO4404_SO8

B+

+5VALW
PC57
4.7U_1206_25V6K

1

1

2

PC189
2200P_0402_50V7K
2
1

MAX8743_B+

1
PR340
0_0402_5%

SLP_S3# 18,21,25,27,28,29,33,35,36,40,44

3

PJP2

2

PAD-OPEN 3x3m
PJP3
PAD-OPEN 4x4m
1
2
PJP5
PAD-OPEN 4x4m
1
2

+1.5VS

+5VALWP

1

2

+5VALW

(4A,160mils ,Via NO.=8)

(4.5A,180mils ,Via NO.= 9)
PAD-OPEN 4x4m
PJP4

+1.8V

(7A,280mils ,Via NO.= 14)

+3VALWP

1

2

+3VALW

(3A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m
PJP6
+VCCP

(6A,240mils ,Via NO.= 12)

+3VLP

2

1

+3VL

(100mA,20mils ,Via NO.= 1)

PAD-OPEN 2x2m

4

PJP12
PAD-OPEN 4x4m
1
2

4

PJP11
+2.5VALWP

2

1

+2.5VALW

(400mA,40mils ,Via NO.= 1)

PAD-OPEN 2x2m
PJP7
+0.9VP

1

2

+0.9V

(2A,80mils ,Via NO.= 4)

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.
2.5VALW/1.5VS/1.05VCCP

PAD-OPEN 3x3m

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

LA-2821

Date:

C

Friday, November 25, 2005
D

Sheet

43

of

52

5

4

3

2

1

D

D

DDR_B+

PL15
FBM-L11-322513-151LMAT_1210
2
1

3

VTTGND

LL

18

LX_1.8V

4

VTTSNS

DRVL

17

DL_1.8V

5

GND

PGND

16

CS

15

B

VDDQSET

S3

11

TPS51116_HTSSOP20

2

2
10

PR234
0_0402_5%
2
1
PR314
@ 0_0402_5%
2
1
PR236
0_0402_5%
2
1

PR232
3_0402_5%
2
1

1

+5VALWP

2
PR389
0_0402_5%

+1.8V

14.3K_0603_0.1%
PR238

SLP_S5# 21,36
B

SLP_S4# 21
SLP_S3# 18,21,25,27,28,29,33,35,36,40,43

1

SLP_S5# 21,36

PC137
@ 0.001U_0402_50V7M

1
2

1
2

PC136
@ 0.001U_0402_50V7M

PR323
2
1
@0_0402_5%

1

@

1

12

2

2

S5

PQ64
AO4702_SO8

C

PR388
0_0402_5%

4
3
2
1

G
S
S
S
13

1

VDDQSNS

+

PR233
20K_0603_1%

9

V5IN
PGOOD

2

COMP

1

VTTREF

8

14
1

7

1

10K_0603_0.1%
PR239
2

+5VALWP

MODE

PC122
4.7U_0805_10V6K

2

1

PR324
0_0402_5%
1
2

+1.8VP

PL16
1.8U_D104C-919AS-1R8N_9.5A_30%
1
2

PC123
0.001U_0402_50V7M

6

PC130
0.033U_0402_16V7K

2

7,13,14 V_DDR_MCH_REF

PC129
22U_1206_6.3V6M

2

DH_1.8V_2

1

19

2

DRVH

PC133
22P_0402_50V8J
2
1

VTT

PC124
10U_1206_25VAK

PC204
220U_D2_4VM

2

PC125
2200P_0402_50V7K
2
1

5
6
7
8
D
D
D
D
20

G
S
S
S

VBST

B+

4
3
2
1

VLDOIN

PQ63
AO4404_SO8

5
6
7
8

1
2

1

PC121
0.1U_0603_50V4Z
BST_1.8V_2 1
2

D
D
D
D

+0.9VP

PR231
0_0402_5%
BST_1.8V_1 1
2
PR230
0_0402_5%
DH_1.8V_1 1
2

1

C

PU27

PC128
10U_0805_10V4Z

1
2
1
2

PC127
10U_0805_10V4Z

PR242
0_1206_5%

+1.5VS

A

A

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
1.8V/0.9VS
Document Number

Rev

LA-2821
Friday, November 25, 2005

Sheet
1

44

of

52

6

5

4

3

2

1

PR270
0_0402_5%
2
1
BST_CPU1_1

1

FCCM UGATE

8

DH_CPU1

2

PWM PHASE

7

LX_CPU1

3

GND

4

1

2

8
7
6
5

1

2 PR304

2

2

DH_CPU2

7

LX_CPU2

GND

4

35

VR_ON

12

VSEN

VDIFF

10

FB

9

COMP

8

VW

ISEN3

21

OCSET

7

VSUM

17

PC162
10U_1206_25VAK
2
1

PC161
10U_1206_25VAK
2
1

PC160
2200P_0402_50V7K
2
1

PC159
0.01U_0402_50V4Z
2
1

5

8
7
6
5

2

1

D
D
D
D
PQ85
FDS6688S_SO8

PR287
10_0402_1%

D

2

1

PR318
@ 0_0402_5%
VSUM

VO

DL_CPU2

PR297
2
1
11.5K_0402_1%
C

VO

VSUM

PR311
1K_0402_1%
2
1

2

PR310
6.19K_0603_1%
2
1

2

3
2
1

+5VS

PC183
1

1

RTN

2
1
0_0402_5%
25

+VCC_CORE

PC166
0.22U_0603_16V7K
2
1

PR290
10K_0402_1%
1
2

PR293
5.11K_0402_1%
PR312

PWM3

2

PR301
3K_0402_1%

13
11

1

1

CLK_EN#

0.36UH_MPC1040LR36_24A_20%

2

PGD_IN

38

LGATE

ISL6208CRZ-T_QFN8

2

PSI#

2

BOOT

2

8

PWM PHASE

S
S
S
G

24

FCCM UGATE

2

1
2
3
4

FCCM

VCC

6

E

PL20

PQ84
FDS6688S_SO8
1 S
D 8
2 S
D 7
3 S
D 6
4
5
G
D

ISEN2

PC180
1

1000P_0402_50V7K
PR307
2
1
6.98K_0402_1%

BST_CPU2_1

39

40
ISEN2

22

PC176
51K_0603_1%
0.022U_0402_16V7K

220P_0402_25V8K

B

1

PWM2

1

PH3
10KB_0603_5%_ERTJ1VR103J
2
1
PR308
1K_0402_1%

1
PC179
2

1

DPRSLPVR

1

DROOP

1

1.2K_0402_1%

26

4

PC165
0.22U_0603_16V7K
1
2

5

3

14

2 PR300

PR299
2
1
0_0402_5%

3V3

2
DPRSTP#

36

1000P_0402_50V7K

PR298
PC173
180_0603_1% 1800P_0402_50V7K
2
1
1
2

18

37

PC168
2
1

5 VSSSENSE

PWM2

1

1000P_0402_50V7K

VIN

VID0
VID1
VID2
VID3
VID4
VID5
VID6

PQ83
SI7840DP-T1-E3_SO8

PU32

PC177
1000P_0402_50V7K

PR315
100_0402_1%
2
1

PC167
1

23

PU31

28
29
30
31
32
33
34

2

2

ISEN1

ISEN1

1

1
PR316
100_0402_1%

SOFT

0.1U_0402_16V7K

2 PR296 1
0_0402_5%

PWM1

27

PC178
0.22U_0603_16V7K
1
2

2 PR295 1
0_0402_5%

PWM1

PC182
2
1

PR294 0_0402_5%
2
1

PR280
0_0402_5%
2
1
PC163
1U_0603_10V6K

NTC

VO

499_0402_1%

2 PR292 1
0_0402_5%

1

+CPU_B+

PGOOD

RBIAS

5

16

1

5 VCCSENSE

C

VGATE_INTEL 7,21

ISL6260CRZ-T_QFN40

PR303
4.53K_0402_1%
2
1

1

33,37 PGD_IN

18,33,36,37,47 PWR_GD

3

DFB

1

7,21 DPRSLPVR

15,37 CLK_ENABLE#

VR_TT#

15

1

VDD

VSS

470KB_0402_5%_ERTJ0EV474J
PR2811
0_0402_5%
2 PR283 1
0_0402_5%
2 PR285 1
0_0402_5%
2 PR288 1
0_0402_5%

2 PR291

5 H_PSI#

20

19
1

2 PR289
0_0402_5%

4

6
2

2 PR282
0_0402_5%
2 PR284
0_0402_5%
2 PR286
0_0402_5%

4,20 H_DPRSTP#

+VCC_CORE

2
PR326
0_0402_5%

BST_CPU2_2

NTC

PH21

2

0.015U_0402_16V7K

37 PGD_IN_1

VO

DL_CPU1

1

PR277
0_0402_5%
2
1

PR278 1
2
147K_0402_1%
1
PC164
4.22K_0603_1% 2
1

D

F

VSUM

+5VS

2 PR279

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

1

NTC

4 H_PROCHOT#

5
5
5
5
5
5
5

2

PR317
@ 0_0402_5%

1
PR275
1.91K_0603_1%

0.01U_0402_16V7K

E

PR271
10_0402_1%

PC157
0.22U_0603_16V7K
2
1

PR274
5.11K_0402_1%

1

PC184
2
1

+VCC_CORE

8
7
6
5
D
D
D
D
S
S
S
G

2

FDS6688S_SO8
PQ82

PC158
1U_0603_10V6K
2
1

F

2

PR272
10K_0402_1%
1
2

1
2
3
4

PR273
10_0603_5%
2

+3VS

D
D
D
D

ISL6208CRZ-T_QFN8

+5VS

S
S
S
G

LGATE

G

PL19
0.36UH_MPC1040LR36_24A_20%

FDS6688S_SO8
PQ81

VCC

2

H

2

BOOT

6

+

B+

3
2
1

PC155
0.22U_0603_16V7K
1
2

PU30

5

1
2
3
4

PC154
1U_0603_10V6K
2
1

G

1

0.01U_0402_25V7K
PC156
2
1

PR269
10_0603_5%

1

4
BST_CPU1_2

2

+5VS

PC153
10U_1206_25VAK
2
1

PQ80
SI7840DP-T1-E3_SO8
+CPU_B+

PL24
FBMA-L18-453215-900LMA90T_1812
1
2

PC152
10U_1206_25VAK
2
1

5

H

PC151
2200P_0402_50V7K
2
1

PC150
0.01U_0402_50V4Z
2
1

+CPU_B+

PC196
68U_25V_M

7

1

8

B

@

330P_0402_50V7K

A

A

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
C
RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
3

2

Compal Electronics, Inc.
CPU_CORE
Document Number

Rev

LA-2821
Friday, November 25, 2005

Sheet

45
1

of

52

A

B

C

D

VMB_A

1
2

1

BATT_A

PL13

PCN2

EC_SMD_A
EC_SMC_A

33

8
P
4

8

1

2

5

1

2

6

+

1

1
1

PR192
PR193
2.55K_0603_1% 150K_0402_1%

2

2

2

PC107
0.22U_0603_10V7K

PR191
150K_0402_1%

-

4

33
33

2

7

D

S

2
G

LM358ADR_SO8

PQ56
RHU002N06_SOT323

2

1

AB1A_CLK

-

LM358ADR_SO8

2

AB1A_DATA

EC_SMC_A1

0
G

+5VALW

EC_SMD_A1
2

PU21B

1

2

1

2

THM_MAIN#

PU21A
3

MAINPWON 42

PR190
15K_0603_1%

2

2

PR188
PR189
100_0402_5% 100_0402_5%

PD27
@SM05_SOT23

PD26
@ SM24_SOT23

PR186
1K_0402_5%

1

1

1

2

3

CPU

1

1

3

TYCO_C-1746706_6P

P

1
PC105
0.01U_0402_50V4Z

PH1
10K_TH11-3H103FT_0603_1%

6

2

PC104
1000P_0402_50V7K

1

+

0
G

PR334
2
1
@ 330K_0402_5%

2

GND

PR185
47K_0402_1%
1
2

+5VALW

1
1

2
3
4
5

3

SMD
SMC
RES
TS

FBMA-L18-453215-900LMA90T_1812
1
2

1

2

BATT+

PC106
0.1U_0402_10V6K

+5VALW

PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
Recovery at 43 +-3 degree C

PC108
1000P_0402_50V7K

VMB_B
PCN3

PL14
FBMA-L18-453215-900LMA90T_1812
1
2

SUYIN_20163S-06G1-K

1
PC109
1000P_0402_50V7K

2

PD19
@ SM24_SOT23

PC110
0.01U_0402_50V4Z

3

1

3

1

6

PR1941
2
1K_0402_5%
1
2
+3VL
PR195
PR197
210K_0402_1%
1K_0402_5%
PD20

2

GND

EC_SMD_B
EC_SMC_B
AB/I_B
TS_B

3

2
3
4
5

2

SMD
SMC
B/I
TS

BATT_B

2

1

1

BATT+

3
1

PR200
100_0402_5%

1

1

2
PR201

@SM05_SOT23
THM_MBAY#

33

2

2

100_0402_5%
EC_SMD_B1
EC_SMC_B1

AB1B_DATA
AB1B_CLK

33
33

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Compal Electronics, Inc.
BATTERY CONN

Size
Document Number
Custom LA-2821
Date:

Rev

Friday, November 25, 2005

Sheet
D

46

of

52

4

3

2

1

S

5

+5VS
+3VS

+5VS

S

@ 68K_0402_5%

PR382
D

2
+3VALW
G
PQ106
@RHU002N06_SOT323

ADP_EN#

2
G
1

PC115
1U_0805_16V7K

2

1

1

47K

PR383
221K_0603_1%
2

2

2
1 1
3

47K

PR385
150K_0402_5%
2 2
1 2

PC117
2
1

2
1
PR384
220K_0402_5%

PR387
220K_0402_5%
2
1

2

P
G
4

1
3

D

S

1

2
G

PQ107
RHU002N06_SOT323

ADP_PRES

1
1

4

2

+

6

-

1

LM393DG_SO8

E

B

1

+3VS

PR364
10K_0402_5%
PU34B

O
4

PR358
3.48K_0402_1%

33

2

8
5

P

1 2
PQ62
MMBT3904_SOT23

PR361
21K_0402_1%
1
2

G

1

1
1

C

2
B

ADP_PS0

1

+5VS
PR362
1M_0402_5%
1
2

CHGLIM

PR224
100K_0402_5%
1
2

PU34A

O
-

2

8
2

+

P

3

PR363
10K_0402_5%

G

2

+5VS
PR360
1M_0402_5%
1
2

7
ADP_PS1

33

LM393DG_SO8

3

2
1

2

PQ97
RHU002N06_SOT323

2

1

PR351
47K_0402_5%

2
1N4148_SOD80

1

LM393DG_SO8

S

2
G

PD34

1

0.027U_0603_16V7K

1
PR218
2

2
7

40
33

PC202
0.1U_0805_50V7M

PR359
10K_0402_5%
1
2

PR357
21K_0402_1%

1
O

3

-

PU33B

2
1
PR368
220K_0402_5%

6

4
3

1 2

D

2
G
PQ104 S
@RHU002N06_SOT323
18,21

8

2

2
1
1

2

P

1
+

P

5

ADP_EN
D

CH355PT_SOD323-2

+3VS

2
1N4148_SOD80

PR356
71.5K_0402_1%

33

PR353
47K_0402_5%

PR352
220K_0402_5%

1

40

A

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.
ADP_OCP

3

1
1 2

@29.4K_0402_1%

2
MXM_CD1#

PR386

1 2

3

1

S

2
G
PQ103
RHU002N06_SOT323

40

PR225
@100K_0402_5%

G

1
1

PR381
40.2K_0402_1%

S

D

ADP_ID

VIN

LM393DG_SO8

2

8

PR348
10K_0402_1%
2
1

1
2
PR367
0_0402_5%
2
1

PR379
442K_0402_1%
2
1

PQ100
@RHU002N06_SOT323

2
G

ACN

1

PR350
1M_0402_5%
1
2

VIN

PR349
10K_0402_1%

3

A

D

470K_0402_5%
PC207
1U_0603_10V6K
+3VS

G

-

4

2

O

2

1K_0402_5%

1

PU33A

PR346
1M_0402_5%
1
2

PR345
10K_0603_1%

PR355

2

2
8

2

PR347
22.6K_0402_1%

2

2

PR344
137K_0402_1%

+

PD36

+3VS

2

PC206
3900P_0402_50V7K

PR354
10K_0402_5%

1

1

3

ADP_SIGNAL

1

1

G

VIN

PR380

1

42

PD37
1N4148_SOD80
PD35

4,21

ACOCP_EN#

C

LX_5V

18,25,33,40,41,42

+3VALW

VIN

2
0_0402_5%

PR221
10_0402_5%

S

1

3

PQ108
DTA144EUA_SC70
1

3

PR390
47K_0402_5%

D

S

ADP_SIGNAL

OCP#

35
PQ61
RHU002N06_SOT323

3

18,33,36,37,45

2

1

PR249
3.9K_0402_5%
2
1

3

PWR_GD

CH355PT_SOD323-2

B

1

1

1
PR220
2

1

C
18,25,33,40,41,42
PQ102
2
B
MMBT3904_SOT23
E
PR373
1
2
PD38
124K_0402_1%
2

PQ96
NDS0610_SOT23

2
PR217
604K_0603_1%

2

1
D

1

LM393DG_SO8

1

2
G

2
PD22

1

VIN

PD30
@ CH751H-40PT_SOD323-2
1
2

1

PR378
10K_0402_5%

PU25A

PR223

ADP_PRES

2

B+

LM393DG_SO8

2
0_0402_5%

PR252
3.9K_0402_5%

LMV431ACM5X_SOT23-5

PR226
0_0402_5%

-

PR206

1

2

+5VS
PQ105
NDS0610_SOT23
D

2

O

2

1
2
PR227
470K_0402_5%

NC

1

2

ANODE

2

7.87K_0402_1%

1
0.1U_0402_16V7K

NC
5

3

1

CATHODE

+

7

2

1

PC119
2
1

REF

PR222

4

PQ59
MMBT3906_SOT23

3
O

-

422_0603_1%

PU26

+

4

2

PC116
0.22U_0603_16V7K

6

PR216
2K_0402_5%
2
1

LM358ADR_SO8

4
1

C

2
0_0402_5%

80.6K_0402_1%

1

1

100K_0402_5%

1

-

7

1

6

5
PR212

0

3

+

PU25B

PR207
133K_0402_1%

G

8

PU24B

P

5

G

2
6.81K_0402_1%
1
2
1
2
PR213
PR214
10K_0402_1%
100K_0603_0.5%

PR377
10K_0402_5%

1

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

PR208

P

8

1
PR209
2

1

1

PC118
1U_0805_50V4Z

1

PR211

0_0402_5%

8
G

2

LM358ADR_SO8

4

2
PR210
0_0402_5%

-

B

2

PR251
330K_0402_5%
2
1

P4

E

P

PU24A
3

+

0

C

1

PD21

D

D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size
Document Number
Custom LA-2821
Date:

Friday, November 25, 2005

Rev
Sheet
1

47

of

52

1

2

3

4

5

24. Remove the R1153 2.2Kohm pull-high resistor for leverage AF1.0 CFG9 setup.  94.04.01.
-Remove R1153(@2.2K_0402). (Modify CKT&BOM)
1. Change +0.9V discharge circuit control signal from SLP_S3 to SLP_S5.  94.03.26.
25. Add net name for USB signals layout rule create.  94.04.04.
-Change Q27.2(2N7002) connection from SLP_S3 to SLP_S5. (Modify CKT&Layout)
-Add net names USB20_N1_R, USB20_P1_R, USB20_N4_R, USB20_P4_R, USB20_HUB_N1_R,
2. Just reserve a test pad for TPM_GPIO directly.  94.03.28.
USB20_HUB_P1_R on JP16.6/7/2/3 JP22.4/3. (Modify CKT&Layout)
-Del R1248 and connect TP62 to JP33.8 directly. (Modify CKT&Layout)
4th Netin
3. Change TPM1.2 +3VL Power Rail to +3VALW by Customer request.  94.03.28.
26. Remove the R555,R612 8.2Kohm pull-high resistors because the signals be double pulled up.
 94.04.04.
-Change +3VL that connects to R1242.1 to +3VALW. (Modify CKT&Layout)
1
-Remove R555,R612(@8.2K_0402). (Modify CKT&BOM)
4. Correct U25.39/38's net name from CLK_PCIE_NC/NC# to PCIE_NC/NC# .  94.03.28.
-Change U25.39/38 connection from CLK_PCIE_NC/CLK_PCIE_NC# to PCIE_NC/PCIE_NC#. (Modify CKT&Layout)
27. Reserve Audio mute control signals on KBC to leverage AF1.0 designing.  94.04.04.
-Reserve R140,R141(@0_0402) onU47.57/56 for EAPD/A_SD. (Modify CKT&Layout)
5. Change the RC parts for POK Time delay request.  94.03.29.
-Change R117 from 100K_0402_5% to 150K_0402_1%. (Modify CKT&BOM)
28. Correct net name for USB signals layout rule create.  94.04.04.
-Change C87 from 0.1U_0402 to 0.47U_0603_X7R. (Modify CKT,BOM&Layout)
-Correct net names to USB20_N2_R, USB20_P2_R, USB20_N3_R, USB20_P3_R, USB20_N6_R,
USB20_P6_R, USB20_N7_R, USB20_P7_R, on JP27.1/2/4/5 JP30.2/4/6/8. (Modify CKT&Layout)
6. Update the PCI7611MLS/PCI7612 related schematic by Vendor recommend.  94.03.29.
-Change R93,R97 from 7612@0_0402 to 0_0402; R103 from 7611@0_0402 to @0_0402. (Modify CKT&BOM)
29. Add (NC@0_0402) to connect CP_USB# and NC_CPPE# for New Card function usage. 
94.04.04.
-Add R1308(0_0402) between U42.K3 and U42.K5; change R106 from 0_0402 to @0_0402. (Modify CKT,BOM&Layout)
-Change R1299 from 43K_0402 to @43K_0402. (Modify CKT&BOM)
-Add R1316(NC@0_0402) to connect CP_USB# and NC_CPPE#. (Modify CKT,BOM&Layout)
-Change R1272,R1273 from @10K_0402 to @100K_0402. (Modify CKT&BOM)
7. Reserve a 68UF Cap. by LAN Chip Vendor request.  94.03.29.
5th Netin
-Reserve C976(@68U_B2_4VM) close to U6.M14. (Modify CKT,BOM&Layout)
30. Del JP39.157's ADP_PRES connection to leverage AF1.0 and standard MXM pin definition. 
8. Reserve two resistors(@0_0402) to isolate VGATE and VGATE_INTEL.  94.03.29.
94.04.04.
-Reserve R1306(@0_0402) between PU31.40 and U45.2. (Modify CKT,BOM&Layout)
-Del JP39.157's ADP_PRES connection. (Modify CKT&Layout)
-Reserve R1307(@0_0402) between U48.4 and PR326.2. (Modify CKT,BOM&Layout)
31. Reserve the circuit to control the mute to block the speaker pop on power up by customer recommend.
9. Change Calistoga LVDS function power source to GND for disabling by customer recommend.  94.03.29.
 94.04.04.
-Change U15.B30/C30/A30 connection from +2.5VS to GND. (Modify CKT&Layout)
-Reserve D59(@RB751V), R613(@1M_0402), R431(@10K_0402), C93(@2.2U_0805), R439(@10K_0402),
2
-Change U15.A28/B28/C28 connection from +1.5VS to GND. (Modify CKT&Layout)
R438(@10_0402) and the related circuit on U39.19. (Modify CKT,BOM&Layout)
10. Remove DPRSLPVR Pull-down resistor by customer recommend.  94.03.29.
-Change R1015 from 100K_0402_5% to @100K_0402_5%. (Modify CKT&BOM)
11. Stuff SPI related function Pull-High resistors by customer/Intel recommend.  94.03.29.
-Change R1284~R1286 from @10K_0402_5% to 10K_0402_5%. (Modify CKT&BOM)
12. Reserve 0 ohm resistor for PM_EXTTS#1 and DPRSLPVR connection by Customer/Intel recommend. 
94.03.29.
-Reserve R1309(@0_0402_5%) between PM_EXTTS#1 and DPRSLPVR connection. (Modify CKT&Layout)
13. Add +1.8V discharge circuit.  94.03.30.
-Add R1310(470_0402_5%) and Q90(2N7002_SOT23) for +1.8V discharge schematic related. (Modify CKT,BOM&Layout)
14. Change ICH7 HD function power source to +3VS for wake on ring function from Azalia modem disabling by
customer recommend.  94.03.30.
-Change U26.R7 connection from +3VALW to +3VS. (Modify CKT&Layout)
15. Change TPM1.2 +3VL Power Rail to +3VALW by Customer request.  94.03.30.
-Change +3VL that connects to C193.1 to +3VALW. (Modify CKT&Layout)
16. Update ICH7M HD Audio, Codec Chip and MDC related Schematic.  94.03.30.
3
-Add R1313,R1314,R1315(33_0402) for ICH7/MDC/Codec related update. (Modify CKT,BOM&Layout)
-Create net name AC97_RST#_MDC, AC97_RST#_CODEC, AC97_SYNC_MDC, AC97_SYNC_CODEC,
AC97_SDOUT_MDC, AC97_SDOUT_CODEC, AC97_BITCLK_MDC, AC97_BITCLK_CODEC, AC97_SDIN0_CODEC,
AC97_SDIN1_MDC for ICH7/MDC/Codec related update. (Modify CKT&Layout)
17. Reserve 0ohm option resistors for +0.9V discharge circuit control signal SLP_S3 and SLP_S5 selecting . 
94.03.30.
-Reserve R1311(@0_0402) to connect SLP_S5 to Q27.2. (Modify CKT&Layout)
Gerber Out 4/14
-Add R1312(0_0402) to connect SLP_S3 to Q27.2. (Modify CKT,BOM&Layout)
18. Populate the 68UF Cap. and reserve 10UF Cap. by LAN Chip Vendor/Customer request.  94.03.30.
-Change C976 from @68U_B2_4VM to 68U_B2_4VM, remove C243(@10U_1206_6.3V). (Modify CKT&BOM)
19. Swapping DDR2 SO-DIMM Data Group pin definition for Layout routing smoothly.  94.03.31.
-Swapping JP34 and JP10 Data Group pin definition. (Modify CKT&Layout)
3th Netin
20. Correct Calistoga chip power pin connection base on CRB Rev:1.301 recommend.  94.04.01.
-Disconnect U15.AV1 and U15.AJ1 to +1.8V and modify the related schematic. (Modify CKT&Layout)
-Change U15.AT41/AM41 net name from MCH_AT41/MCH_AM41 to VCCSM_LF4/VCCSM_LF5. (Modify CKT&Layout)
4
21. Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R to meet Intel Napa ESL request.  94.04.01.
-Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R. (Modify CKT,BOM&Layout)
22. Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R to meet Intel request, avoid thermal risk. 
94.04.01.
Security Classification
Compal Secret Data
Compal Electronics, Inc.
-Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R. (Modify CKT&BOM)
Title
2005/03/10
2006/03/10
Issued Date
Deciphered Date
23. Update ICS954306 PCB Footprint for Layout routing.  94.04.01.
H/W2 EE Dept. PIR SHEET(1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
-Change U25 PCB Footprint from ICS954306_TSSOP64 to ICS954306BGLFT_TSSOP64.
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2821P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
(Modify CKT,BOM&Layout)
Date:
Friday, November 25, 2005
Sheet
48
of
52

EAL80 from Pre DB-1 Step to DB-1 Step LA-2821 REV:0.0 -> 0.1 Modify <94.03.26.~94.04.08. >

1

2

3

4

1

2

3

4

5

1

2

3

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

1

2

3

4

1. Change HDD I/F from PATA to SATA.  94.05.10.
-Change U26.AF18 from NC to IDE_LED#. (Modify CKT&Layout)
-Change U26.AF3 from GND to SATA_RXN0_C. (Modify CKT&Layout)
-Change U26.AE3 from GND to SATA_RXP0_C. (Modify CKT&Layout)
-Change U26.AG2 from NC to SATA_TXN0_C. (Modify CKT&Layout)
-Change U26.AH2 from NC to SATA_TXP0_C. (Modify CKT&Layout)
-Add R1256(24.9_0402_1%) between U26.AH10/AG10 and GND. (Modify CKT,BOM&Layout)
-Del R1326,R1327(NOSATA@0_0402). (Modify CKT,BOM&Layout)
-Add JP45, C955~C958(3900P_0402) and related schematic for SATA connector. (Modify CKT,BOM&Layout)
2. Remove R1294(1K_0402) Pull-High to +3VS to avoid double Pull-High risk.  94.05.10.
-Remove R1294(@1K_0402). (Modify CKT&BOM)
3. Add the accelerometer device LIS3LV02DQ and modify the related schematic .  94.05.11.
-Add U64(LIS3LV02DQ_QFN28),R1355(0_0805_5%),R1356(0_0603_5%),R1357~R1361(0_0402_5%),
R1362(10K_0402_5%),C994(0.01U_0402_16V7K),C995(0.1U_0402_16V4Z) and C996(4.7U_0805_10V4Z)
at the center of the system . (Modify CKT,BOM&Layout)
-Add R1364(0_0402_5%) between "ACCEL_INT#" and U26.E20(SB_GPIO9); Reserve R1363(@0_0402_5%) between
"ADP_PWRID" and U26.E20(SB_GPIO9) . (Modify CKT,BOM&Layout)
-Reserve R1354(@0_0402_5%) between "ACCEL_INT#" and U47.34(KBC_GPIO23) . (Modify CKT,BOM&Layout)
4. Change USB port assignments as customer request .  94.05.11.
-Change R1317(NC@0_0402_5%) connection Net from "USB20_P0_HUB" to "USB20_P1_HUB" and from "USB20_P0" to
"USB20_P1" . (Modify CKT&Layout)
-Change R1318(NC@0_0402_5%) connection Net from "USB20_N0_HUB" to "USB20_N1_HUB" and from "USB20_N0" to
"USB20_N1" . (Modify CKT&Layout)
-Change R562(0_0402_5%) connection Net from "USB20_HUB_P1_R" to "USB20_P0_R" and from "USB20_HUB_P1" to
"USB20_P0" . (Modify CKT&Layout)
-Change R586(0_0402_5%) connection Net from "USB20_HUB_N1_R" to "USB20_N0_R" and from "USB20_HUB_N1" to
"USB20_N0" . (Modify CKT&Layout)
-Change R983(NONC@0_0402_5%) connection Net from "USB20_P0" to "USB20_P1" . (Modify CKT&Layout)
-Change R982(NONC@0_0402_5%) connection Net from "USB20_N0" to "USB20_N1" . (Modify CKT&Layout)
-Change R1335(0_0402_5%) connection Net from "USB20_HUB_P2_R" to "USB20_HUB_P1_R" and from
"USB20_HUB_P2" to "USB20_HUB_P1" . (Modify CKT&Layout)
-Change R1334(0_0402_5%) connection Net from "USB20_HUB_N2_R" to "USB20_HUB_N1_R" and from
"USB20_HUB_N2" to "USB20_HUB_N1" . (Modify CKT&Layout)
-Change R1276(NC@0_0402_5%) connection Net from "USB20_P5_R" to "USB20_HUB_P2_R" and from
"USB20_P5" to "USB20_HUB_P2" . (Modify CKT&Layout)
-Change R1274(NC@0_0402_5%) connection Net from "USB20_N5_R" to "USB20_HUB_N2_R" and from
"USB20_N5" to "USB20_HUB_N2" . (Modify CKT&Layout)
-Change R607(0_0402_5%),D51.3 connection Net from "USB20_P1_R" to "USB20_P5_R" and from
"USB20_P1" to "USB20_P5" . (Modify CKT&Layout)
-Change R606(0_0402_5%),D51.2 connection Net from "USB20_N1_R" to "USB20_N5_R" and from
"USB20_N1" to "USB20_N5" . (Modify CKT&Layout)
-Change U53(NC@USB2502) pin15 connection from Net "USB_OC#0" to "USB_OC#1" . (Modify CKT&Layout)
-Change U41(TPS2041B) pin5 connection from Net "USB_OC#1" to "USB_OC#5" . (Modify CKT&Layout)
5. Change PCIE port assignments as customer request .  94.05.12.
-Change U26.K26/K25/J28/J27 to NC . (Modify CKT&Layout)
-Change C712 connection from PCIE_C_TXN3 to PCIE_C_TXN4 ; from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)
-Change C713 connection from PCIE_C_TXP3 to PCIE_C_TXP4 ; from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&Layout)
-Change C952 connection from PCIE_C_TXN4 to PCIE_C_TXN5 ; from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)
-Change C953 connection from PCIE_C_TXP4 to PCIE_C_TXP5 ; from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&Layout)
-Change C959 connection from PCIE_C_RXN3 to PCIE_C_RXN4 ; from PCIE_RXN3 to PCIE_RXN4 . (Modify CKT&Layout)
-Change C960 connection from PCIE_C_RXP3 to PCIE_C_RXP4 ; from PCIE_RXP3 to PCIE_RXP4 . (Modify CKT&Layout)
-Change JP9.A24 connection from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)
-Change JP9.A25 connection from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&Layout)
-Change R1347 connection from PCIE_C_RXN4 to PCIE_C_RXN5 ; from PCIE_RXN4 to PCIE_RXN5 . (Modify CKT&Layout)
-Change R1346 connection from PCIE_C_RXP4 to PCIE_C_RXP5 ; from PCIE_RXP4 to PCIE_RXP5 . (Modify CKT&Layout)
-Change JP30.151 connection from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)
-Change JP30.149 connection from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&Layout)

4

Compal Secret Data

Security Classification
Issued Date

5

6. Change SRC clock assignments as customer request .  94.05.13.
-Change U25.20 connection from "MCH_3GPLL" to "PCIE_LOM". (Modify CKT&Layout)
-Change U25.21 connection from "MCH_3GPLL#" to "PCIE_LOM#". (Modify CKT&Layout)
-Change U25.22 connection from "PCIE_LOM" to "PCIE_NC". (Modify CKT&Layout)
-Change U25.23 connection from "PCIE_LOM#" to "PCIE_NC#". (Modify CKT&Layout)
-Change U25.26 connection from "PCIE_MCARD" to "PCIE_DOCK". (Modify CKT&Layout)
-Change U25.27 connection from "PCIE_MCARD#" to "PCIE_DOCK#". (Modify CKT&Layout)
-Change U25.37 connection from "PCIE_DOCK" to "MCH_3GPLL". (Modify CKT&Layout)
1
-Change U25.36 connection from "PCIE_DOCK#" to "MCH_3GPLL#". (Modify CKT&Layout)
-Change U25.39 connection from "PCIE_NC" to "PCIE_MCARD". (Modify CKT&Layout)
-Change U25.38 connection from "PCIE_NC#" to "PCIE_MCARD#". (Modify CKT&Layout)
7. Change CLKREQ assignments as customer request .  94.05.13.
-Change R1344.2 connection from "CLKREQB#" to "CLKREQC#". (Modify CKT&Layout)
-Change R1279.1/R1280.1/C961.1 connection from "CLKREQD#" to "CLKREQA#". (Modify CKT&Layout)
-Change R1336 connection from "CLKREQB#" to "CLKREQD#"; from "CLKREQB#_MC" to "CLKREQD#_MC".
(Modify CKT&Layout)
-Add R1120(NOXDP@10K_0402) from net "CLKREQC#" to +3VS pull-high . (Modify CKT,BOM&Layout)
-Change R1142 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)
-Add R1147(NOXDP@10K_0402) from net "CLKREQD#" to +3VS pull-high . (Modify CKT,BOM&Layout)
-Change R1254 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)
-Change R1106(10K_0402) connection from +3VS pull-high to between CLKREQB# and CPPE# .
(Modify CKT&Layout)
8. Reserve test Mini-Card that supports USB interface as customer request .  94.05.13.
-Add R1365(@0_0402) between JP38.2 and JP44.36 . (Modify CKT&Layout)
2
-Add R1366(@0_0402) between JP38.3 andto JP44.38 . (Modify CKT&Layout)
9. Del R1344 & R1336 and short directly because of double reserved .  94.05.16.
-Del R1344(@0_0402_5%) and short directly . (Modify CKT&Layout)
-Del R1336(0_0402_5%) and short directly . (Modify CKT,BOM&Layout)
10. Update LAN Controller schematic related caused by chipset changed from BCM5751M to BCM5753M .
 94.05.16.
-Update the related schematic. (Modify CKT&Layout)
-Change R275,R289 from 47K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)
-Change R276 from 4.7K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)
-Add R1370,R1371(0_0402) and reserve R1372,R1373(@2.2K_0402),Q92,Q93(@2N7002) for SMBus
connection . (Modify CKT,BOM&Layout)
-Add R1367(1K_0402) from U6.H12 to +3VS . (Modify CKT,BOM&Layout)
11. Remove U37,D32,R504, and C577. Remove CLKREQA# connection from NIC to CK clock by customer
recommend .  94.05.16.
-Remove U37,D32,R504, and C577 . (Modify CKT,BOM&Layout)
12. Update Accelerometer related schematic by Vendor STMicro recommend .  94.05.16.
3
-Remove C994(@0.01U_0402), Change C996 from 4.7U_0805 to 10U_0805 . (Modify CKT,BOM&Layout)
13. Modify ICH7 Power_OK connection to be able to be enable same as NB .  94.05.16.
-Add R1368(0_0402) and reserve R1369(@0_0402) for U26.AD22 connection . (Modify CKT,BOM&Layout)
14. Swap RP11,RP13 pin connection for DDR2 shift trace routing issue improving .  94.05.16.
-Change RP11.2 connection from DDR_B_MA11 to DDR_CKE3_DIMMB . (Modify CKT&Layout)
-Change RP11.1 connection from DDR_CKE3_DIMMB to DDR_B_MA7 . (Modify CKT&Layout)
-Change RP13.2 connection from DDR_B_MA6 to DDR_B_MA11 . (Modify CKT&Layout)
-Change RP13.1 connection from DDR_B_MA7 to DDR_B_MA6 . (Modify CKT&Layout)
1st Netin
15. Update the SATA supported related .  94.05.17.
-Delete JP23,R458,R1324,R1325,R300 . (Modify CKT,BOM&Layout)
-Add C997(10U_0805),C998~C1000(0.1U_0402) close to JP45 +3VS pins . (Modify CKT,BOM&Layout)
16. Dual design SPI ROM for SOP8-150mil/200mil package .  94.05.17.
-Add U65(SPI@SST25LF080A-200mil) . (Modify CKT,BOM&Layout)
17. TPM1.2 on board designing reserve related .  94.05.17.
-Add U66(TPM1.2@SLB9635TT),C1001~C1004(0.1U_0402),C1005,C1006(18P_0402),Y8(32.768KHz),
4
R1375~R1381 and related schematic update . (Modify CKT,BOM&Layout)
2nd Netin

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

4

Friday, November 25, 2005

Sheet
5

49

of

52

1

2

3

4

5

31. Update Clock Gen. schematic related by customer recommend .  94.05.23.
-Reserve R1393(@0_0402_5%) from U25.46(CLKIREF) to +CK_VDD_DP . (Modify CKT&Layout)
18. Update TPM1.2 on board designing schematic.  94.05.18.
-Reserve C1011(@0.1U_0402) from U25.46(CLKIREF) to GND . (Modify CKT&Layout)
-Change pin5 (VSB) to +3VALW and move C1004 to connect to pin5 . (Modify CKT&Layout)
-Reserve R1394(@10K_0402) from U25.2(PCI_EC) to +3VS . (Modify CKT&Layout)
-Delete SMBus connection with R1380,R1381 on U66.2 & U66.6; Connect U66.6 to JP33.8, U66.2 to T87 .
-Remove R1353,R1333(@0_0402_5%) . (Modify CKT&BOM)
(Modify CKT,BOM&Layout)
32. Update AC97 Codec to keep AD1981HD only schematic related by customer recommend and DFx issue
-Delete +3V power from JP33.4 . (Modify CKT&Layout)
improved .  94.05.23.
-Delete +3V power reserved schematic and parts include Q91,C977,C978 . (Modify CKT,BOM&Layout)
-Del C391,R403,R406,R388,R158,R159,C410,C408,C401,C398,R415,R364,C397,R1085(CLK_14M_CODEC)
1
19. Add DC/DC schematic about +2.5VALW to +2.5VS for power sequence fail issue fixed.  94.05.18.
,R418 and short U14.42 to GNDA . (Modify CKT,BOM&Layout)
-Add U67(SI4800DY_SO8),C1007,C1008,C1009 . (Modify CKT,BOM&Layout)
-Add T88~T101 test point on the bottom side . (Modify CKT&Layout)
20. Delete MDC 1.0 Connector reserved related to save layout space .  94.05.18.
33. Update ICH7 SPI I/F related schematic by customer recommend .  94.05.24.
-Del JP25(MDC1.0 Conn),C13(0.1U_0402) . (Modify CKT,BOM&Layout)
-Change R1284.1,R1285.1 and R1286.1 connection from +3VS to +3VALW . (Modify CKT&Layout)
21. Change the power source designing from +3VALW to +3VS for DB-2 LS-2712 issue fixed .  94.05.18.
34. Update TI PCI7611MLS/PCI7612 related schematic by customer recommend .  94.05.24.
-Change JP18.1 and JP18.3 connection from +3VALW to +3VS . (Modify CKT&Layout)
-Change R594.2 and R602.2 connection from +VCC_SD to +VCC_SM_XD . (Modify CKT&Layout)
3rd Netin
35. Update ICH7 SATA I/F related schematic by customer recommend .  94.05.24.
22. Change the ICH7 RTC Cap. Value for SVTP measure fail issue fixed .  94.05.19.
-Del JP45 pin8,9,10 +3VS connection . (Modify CKT&Layout)
-Change C516,C528 from 18P_0402 to 10P_0402 . (Modify CKT&BOM)
-Del C997~C1000 . (Modify CKT,BOM&Layout)
23. Update LAN chip schematic related by customer recommend .  94.05.19.
36. Update ICH7 PATA I/F related schematic for SATA HDD support .  94.05.24.
-Change R275,R289 from 1K_0402 to @1K_0402 . (Modify CKT&BOM)
-Add R556(100K_0402) . (Modify CKT&BOM)
-Del D32,R504,C577,U37 . (Modify CKT,BOM&Layout)
37. Change some Capacitors for Lead Free designing .  94.05.25.
-Add R1380(0_0402) and reserve R1381(@0_0402) . (Modify CKT,BOM&Layout)
-Remove C939(@220U_C6_6.3V) and add C983(330U_D2E_2.5V) . (Modify CKT&BOM)
-Del C40,C45,C53,C62,C64 for +3VS power rail cancel . (Modify CKT,BOM&Layout)
-Remove C633(@47U_25V_M) and add C1013~C1017(10U_1206_25V6M) . (Modify CKT,BOM&Layout)
24. Update KBC related designing by customer recommend .  94.05.20.
-Remove C671(@100U_6.3V_M) and add C1012(150U_D_6.3VM) . (Modify CKT,BOM&Layout)
-Add ADP_EN to S_CLK(GPIO22) by R1385(0_0402) . (Modify CKT,BOM&Layout)
-Remove C670(@220U_C6_6.3V) and add C979(330U_DD2E_2.5V) . (Modify CKT&BOM)
2
-Add ADP_ID to EC_GPIO19 by R1382(0_0402) . (Modify CKT,BOM&Layout)
-Remove C1,C527(@100U_6.3V) and add CC568,C567(150U_D_6.3V) . (Modify CKT&BOM)
-Add ADP_PS1 to EC_GPIO12 by R1383(0_0402) . (Modify CKT,BOM&Layout)
38. Update the Accelerometer related and install the related BOM for Accelerometer enable . 
-Add ADP_PS0 to EC_GPIO10 by R1384(0_0402) . (Modify CKT,BOM&Layout)
-Change the net name from ACCEL_INT# to ACCEL_INT, ACCEL#_SB to ACCEL_SB, ACCEL_INT#_KBC
-Remove R87(@0_0402) . (Modify CKT&BOM)
to ACCEL_INT_KBC . (Modify CKT&Layout)
25. Update ICH7 related designing by customer recommend .  94.05.20.
-Note R94 must be removed when R1354 stuff and R87 remove . (Modify CKT&BOM)
-Change R1363 from 0_0402 to ACCEL@0_0402 . (Modify CKT&BOM)
-Reserve D61,C1018,R1395,Q95 between ACCEL_INT and Q78.1 . (Modify CKT&Layout)
-Change R1363.2 connection from ADP_PWRID to ADP_ID . (Modify CKT&Layout)
-Remove R1358,R1360 . (Modify CKT&BOM)
9rd Netin/BOM Transfer
-Reserve R1386(@0_0402) from PREP2# to U26.AD20(ICH7_GPIO38) . (Modify CKT&Layout)
-Reserve R1387(@10K_0402) from PREP2# to +3VS . (Modify CKT&Layout)
39. Update Docking related schematic for Customer Smart Adaptor new function request . 
-Change JP30.118 and R1387.1 net name to DOCK_ID . (Modify CKT&Layout)
26. Update LAN chip schematic related by customer recommend .  94.05.20.
-Add JP30.117(DOCK_ADP_SIGNAL) to ADP_SIGNAL by R1401(1K_0402_1%) . (Modify CKT,BOM&Layout)
-Change R73.1 and R36.1 connection from +3VS to V_3P3_LAN . (Modify CKT&Layout)
27. Update CardReader chip schematic related by customer recommend .  94.05.20.
40. Update AD1981HD related schematic for Vendor ADI review result . 
-Del U46 and related net . (Modify CKT,BOM&Layout)
-Change U18.2 connection from GND to AGND, move R258 between C551.1 and U18.2 . (Modify CKT&Layout)
-Del R591,R593 . (Modify CKT,BOM&Layout)
-Change C409,C427,C431 from 0.1U_0402 to 0.1U_0805 . (Modify CKT,BOM&Layout)
-Change R594 connection to between +VCC_SD and SDWP#_SMCE# . (Modify CKT&Layout)
-Add R1400(0_1206) between GND and AGND close to Codec area . (Modify CKT,BOM&Layout)
-Change R602 connection to between +VCC_SD and SM_RB# . (Modify CKT&Layout)
-Disconnect U14.14 and U14.15, disconnect U14.40 and U14.33 to AGND and add T102,T103,T104 on pin 14,40,33 .
3
(Modify CKT&Layout)
-Change JP41.36 connection to MSBS_SDCMD_SMWE# . (Modify CKT&Layout)
-Change JP41.27 connection to SDCLK_SMRE# . (Modify CKT&Layout)
-Add R1399(0_0805) replace L36(CHB2012U121(0805)) . (Modify CKT&BOM)
-Change JP41.28 connection to SDWP#_SMCE# . (Modify CKT&Layout)
-Add C1019(10P_0402) to GND . (Modify CKT,BOM&Layout)
-Change JP41.26 connection to SM_RB# . (Modify CKT&Layout)
41. Update Accelerometer related schematic for Customer review result . 
-Add R1388(0_0402) between MC_PWRON# and MC_PWRON . (Modify CKT,BOM&Layout)
-Remove R1355(@0_0805), add D62(ACCEL@CH751H) between U64.3/19 and +3VS . (Modify CKT,BOM&Layout)
-Remove Q77,D45,D46,R595,D48 . (Modify CKT&BOM)
-Del R1358 and R1360 pull-down resistors . (Modify CKT,BOM&Layout)
-Add R1398(0_0402) to GND, del U64.29 to GND connection . (Modify CKT,BOM&Layout)
28. Update Clock Gen. schematic related by customer recommend .  94.05.20.
-Del R1328,R1329,R1330,R1331,R1332 and related net . (Modify CKT,BOM&Layout)
42. Change the Audio Amp chip from TI TPA6017A2_TSSP20 to MAXIM MAX9710_QFN20 and update related
schematic for Customer Spec modified request . 
-Change U25.15 connection to FSB . (Modify CKT&Layout)
-Change U25.16,24,41 connection to +CK_VDD_DP . (Modify CKT&Layout)
-Change U39 from TPA6017A2_TSSOP20 to MAX9710ETP_QFN20 . (Modify CKT,BOM&Layout)
-Change C734,C735,C736 connection to +CK_VDD_DP . (Modify CKT&Layout)
-Del D59,R613,R431,C93,R439,R438,C663,C664,R971~R974,C661 . (Modify CKT,BOM&Layout)
-Add R1389(NODP@0_0805),R1390(DP@0_0805),C1010(10U_0805) and related net . (Modify CKT,BOM&Layout)
-Change C503,C502 from 0.047U to 0.1U . (Modify CKT,BOM&Layout)
-Change R1352,R1333 from @0_0402 to 0_0402 . (Modify CKT,BOM&Layout)
-Add R1403(10K_0402) from U39.5 to C503.2, R1404(10K_0402) from U39.5 to U39.7 . (Modify CKT,BOM&Layout)
-Add R1405(10K_0402) from U39.1 to C502.2, R1406(10K_0402) from U39.1 to U39.19 . (Modify CKT,BOM&Layout)
29. Update MXM schematic related by customer recommend .  94.05.23.
-Add R1407(0ohm) from U39.4 to AGND;Add C1020(10U_1206) from +5VALW and GND . (Modify CKT,BOM&Layout)
-Reserve R1391(@0_0402) from JP39.125 to CLKREQA# . (Modify CKT&Layout)
-Add C1021(1U_0603) from U39.2 to AGND . (Modify CKT,BOM&Layout)
-Add R1392(0_0402) from JP39.157 to ADP_PRES . (Modify CKT,BOM&Layout)
4
-Change C662 from @100U_6.3V to @150U_D_6.3V . (Modify CKT&Layout)
30. Update LAN chip schematic related by customer recommend .  94.05.23.
-Reserve R284(@4.7K_0402_5%) from U6.L3 to V_3P3_LAN . (Modify CKT&Layout)
-Add T59 on U6.L3 . (Modify CKT&Layout)
-Add T60 on U6.M5 . (Modify CKT&Layout)
Security Classification
Compal Secret Data
Compal Electronics, Inc.
-Reserve Q94(@2N7002_SOT23) and change R1380 connection as update schematic . (Modify
Title
2005/03/10
2006/03/10
Issued Date
Deciphered Date
CKT&Layout)
H/W2
EE Dept. PIR SHEET(3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
-Del R1381 and short Q29.3 to GND directly . (Modify CKT&Layout)
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2821P

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

1

2

3

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Date:

Friday, November 25, 2005

Sheet
5

50

of

52

1

2

3

4

5

16. Modify PCMCIA Connector design for M/E team request .  94.09.08.
-Change JP9 PCBFootprint from SLINK_AFH-1000-17A0-3_104P to TYCO_C-PT05-023-D1_150P_LT.
43. Reserve a 0ohm resistor for time delay pass through schematic by Customer request.  94.05.27.
(Modify CKT,BOM&Layout)
-Reserve R1402(@0_0402) between PWR_GD and PGD_IN . (Modify CKT&Layout)
17. Delete New Card, USB HUB related design for customer Spec update .  94.09.08.
44. Change the resistor value to tune the delay schematic by Customer request.  94.05.27.
-Delete R1272,R1273,R1274,R1275,R1276,R1277,R1278,R1279,R1280,R1282,R1316,C959,C960,C961,C962,
-Change R38 from 100K_0402 to 47K_0402 . (Modify CKT&BOM)
C963,C964,C965,C966,C967,C968,C969,C970,C971,C972,C973,U60,R535,C541,L34,C521,C529,C535,C517,
45. Change BOM option for Intel chipset ver:A1 by Customer recommend .  94.05.27.
C558,C540,C559,R981,U53,Y6,R984,C22,C27,L37,R1353,R537,R539,R523,R1317,R1318,R1099,R1102,
-Change R1309 from @0_0402 to 0_0402, remove R1015(@100K_0402) . (Modify CKT&BOM)
R1100,R1103,C712,C713; Add T107. (Modify CKT,BOM&Layout)
1
46. Add a 0ohm resistor for debug by Customer recommend .  94.05.27.
-Delete R982,R983 reserve. (Modify CKT&Layout)
-Add R1408(0_0402) between U26.H22 and H_STPCLK# . (Modify CKT,BOM&Layout)
18. Modify MiniCard related design for customer request.  94.09.08.
47. Add a 0.1UF CAP to improve Cut Moat issue for RGB signals .  94.05.27.
-Add Q101,Q102,R1445; Reserve R1444(@0_0805). (Modify CKT,BOM&Layout)
-Add C1022(0.1U_0603) between +3VS and +VCCP . (Modify CKT,BOM&Layout)
19. Delete FWH I/F BIOS related design for customer request.  94.09.08.
48. Add 10Kohm pull-high to +VCC_SM_XD for TI FAE recommend .  94.05.27.
-Del &U21(SST49LF008A-33-4C-NH),U21,U20,R273,R278,RP42,R1125,C42,C333. (Modify CKT,BOM&Layout)
-Add R1396 and R1397(10K_0402) Pull-High to +VCC_SM_XD for MSBS_SDCMD_SMWE# and SDCLK_SMRE# .
-Del R279,C43 reserve. (Modify CKT&Layout)
(Modify CKT,BOM&Layout)
-Add T108,T109,T110. (Modify CKT&Layout)
49. Update TPM related schematic for Vendor review result .  94.05.27.
-Delete BIOS_SEL1 and replace with short to GND directly. (Modify CKT&Layout)
-Add R1409(TPM1.2@0_0402) from U66.7 to GND, remove R1379(@4.7K_0402) . (Modify CKT,BOM&Layout)
20. Wire VGA Thermal inform signal with System side for function workable.  94.09.09.
-Change C193.1 connection from +3V to +3VALW for TPM1.2 . (Modify CKT&Layout)
-Add R252(0_0402). (Modify CKT&BOM)
21. Modify MiniCard related design for customer.  94.09.10.
EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >
-Add J44(JUMP_43X39) and reserve J45(@JUMP_43X39) for Power Source option. (Modify CKT&Layout)
1. Add discharge circuit for BT_LED and WL_LED to solve the LED always light on issue.  94.08.23.
-Change R1444.1 connection from +3VALW to +3VS. (Modify CKT&Layout)
-Add R1440 and R1441(100K_0402) for BT_LED and WL_LED discharge . (Modify CKT,BOM&Layout)
-Remove Q101,Q102,R1445 and add R1444. (Modify CKT&BOM)
2. Remove DPRSLPVR NB side PullHigh resistor for Intel document update.  94.08.24.
22. Modify TI PCI7612 designing for vendor request .  94.09.10.
-Remove R1209(@10K_0402) for DPRSLPVR . (Modify CKT&BOM)
-Change R573.1 power connection to +SC_PWR from +5VS. (Modify CKT&Layout)
2
3. Keep TPM1.2 on Board and Delete TPM1.1 Module Connector designing.  94.08.24.
-Change power rail to R615 & R616 to +3VS from +5VS and remove both R615 & R616. (Modify CKT,BOM&Layout)
-Del JP33,R1236,R1242,R1253,C191,C192,C193 and related schematic. (Modify CKT,BOM&Layout)
23. Modify LAN Transformer designing for customer request .  94.09.10.
4. Update TPM1.2 chip PCB layout footprint.  94.08.24.
-Change R270,R271 connection by add C333 between ground and R270/R271 . (Modify CKT,BOM&Layout)
-Change U66 PCB Footprint from SLD9630TT_TSSOP28 to SLB-9635-TT-1P2_TSSOP28. (Modify CKT&Layout)
24. Create an option to use the 32KHz clock from KBC for TPM1.2 for customer request .  94.09.10.
5. Correct ODD CSEL option setting.  94.08.24.
-Reserve R1446(@0_0402) to connect U47.58 and U66.13. (Modify CKT&Layout)
-Remove R460(@4.7K_0402) and add R557(470_0402). (Modify CKT&BOM)
25. Delete MiniPCI Debug I/F reserve for Layout space free .  94.09.12.
6. Correct SPI I/F Power Source for Capell_Valley_CRB_Schematics_Rev1_502.pdf update .  94.08.26.
-Del R1117,R235,R441,R447,R451,R452 and JP20. (Modify CKT,BOM&Layout)
-Change U61.8, U65.8, R1287.1 and R1288.1 Power Rail from +3VS to +3VALW. (Modify CKT&Layout)
-Del R448,C537,R437 and Q49 reserve. (Modify CKT&Layout)
7. Modify Mini-Card debug interface design for customer update .  94.08.30.
-Change R1420.1 connection from +3VALW to +3VL. (Modify CKT&Layout)
-Move +3VALW from pin 39 to pin 45 and move CAPS_LED# from pin 41 to pin 51. (Modify CKT&Layout)
-Change C292,C538,C542 power source from +3VS to +3VS_MINI. (Modify CKT&Layout)
8. Update ADI1981HD CIS symbol and PCB Footprint .  94.08.30.
-Add H29,H30(H_C236D157)(MiniCard Stand Off). (Modify CKT,BOM&Layout)
-Update U14 CIS symbol and change PCB Footprint from AD1981B_LQFP48 to AD1981HDJSTZ-REEL_LQFP48.
26. Change Jopen PAD for CIC DFx request .  94.09.12.
(Modify CKT&Layout)
-Change J29 PCBfootprint to JUMP_43X39. (Modify CKT&Layout)
9. Change PCI-E Ports for ICH7 modify .  94.08.31.
27. Change LAN chip desgin to switch LAN power with LP_EN# for customer request .  94.09.13.
-Change ExpressCard (NC) connection to port 3, Change Docking connection to port 4. (Modify CKT&Layout)
-Install R15(4.7K_0402_5%) and no-stuff U36(@SN74LVC1G17DBVR_SOT23-5). (Modify CKT&BOM)
10. Update Accelerometer related design for customer request .  94.09.02.
28. Modify TPM1.2 related design about the ADP_EN for customer request .  94.09.13.
3
-Del D61, C1018, R1395 & Q95. (Modify CKT&Layout)
-Reserve R1447(@0_0402) close to Y8.1. (Modify CKT&Layout)
-Add Q75, R187; change D12 to Dual LED. (Modify CKT,BOM&Layout)
-Reserve R1448(@0_0402) for ADP_EN. (Modify CKT&Layout)
-Add net HDD_STP# from GPIO19 of ICH7 to Q75. (Modify CKT&Layout)
29. Modify BT related design for customer request .  94.09.14.
-Install R1374 and change R1060 to no-stuff. (Modify CKT&BOM)
-Change R454 to 47K from 1K. (Modify CKT&BOM)
-Del R1363 and R1364; Add SB GPIO test pad T80,T89,T99,T106. (Modify CKT,BOM&Layout)
-Reserve a 0.1uF cap (no-stuff) from R454.2 to ground. (Modify CKT&Layout)
11. Modify Mini-Card debug interface design for customer update .  94.09.02.
30. Modify LAN chip related design for customer request .  94.09.14.
-Remove R1435 and R1436(@0_0402). (Modify CKT&BOM)
-Add R458(0_0402) between Q100.2 and Q94.1. (Modify CKT,BOM&Layout)
12. Modify TI PCI7612 designing for vendor request .  94.09.06.
31. Modify BITCLK related design for EMI request .  94.09.14.
-Change R573 from 10K_0402 to 0_0402. (Modify CKT&BOM)
-Reserve R1032,C722 close to U14.6. (Modify CKT&Layout)
-Change R594,R1396 and R1397 from 10K_0402 to 100K_0402. (Modify CKT&BOM)
-Move R1028, C721 close to JP32.12; R1314,R371 close to U26.U1. (Modify CKT&Layout)
-Change R602 from 10K_0402 to 22K_0402. (Modify CKT&BOM)
32. Modify LID_SW# related design for M/E request .  94.09.14.
13. Update Accelerometer related design for customer request .  94.09.02.
-Add R1449 close to JP18.16. (Modify CKT,BOM&Layout)
-Add net HDD_STP from GPIO19 of ICH7 to Q84.2. (Modify CKT&Layout)
33. Modify Clock Gen. related design for Vendor request .  94.09.14.
-Add Q84(2N7002) and R1442(100K_0402) for HDD_STP. (Modify CKT,BOM&Layout)
-Change R1092 from 475_0402_1% to 4.7K_0402_1%. (Modify CKT&BOM)
-Reserve R1443(@0_0402) for HDD_STP#. (Modify CKT&Layout)
34. Modify NB chip CFG11 related design for Intel CRB Rev1_502 update .  94.09.14.
14. Update ICH7 GPIO related design for customer request .  94.09.06.
-Remove R1154(@2.2K_0402_5%). (Modify CKT&BOM)
4
-Del R1321 and R1323 related reserved schematic. (Modify CKT&Layout)
35. Modify Smart AC Adaptor related design for customer request .  94.09.14.
15. Modify LAN controller related for customer request .  94.09.07.
-Change R1237 from 10K_0402 to 100K_0402. (Modify CKT&BOM)
-Add and change R277 from @0_0402 to 10K_0402. (Modify CKT&BOM)
-Remove R1380(@0_0402) and add Q94(2N7002). (Modify CKT&BOM)
Security Classification
Compal Secret Data
Compal Electronics, Inc.
-Change R506 pull-up to +3VALW from V_3P3_LAN. (Modify CKT&Layout)
Title
2005/03/10
2006/03/10
Issued Date
Deciphered Date
-Add Q100(SI2301BDS), reserve R83(@0_0402) and related schematic. (Modify CKT,BOM&Layout)
H/W2 EE Dept. PIR SHEET(4)

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.30. >

1

2

3

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

4

Friday, November 25, 2005

Sheet
5

51

of

52

1

2

3

4

5

EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

1

2

36. Add DDR2 Module Thermal inform function to NB for customer request.  94.09.15.
-Add R1450(0_0402) between DDR_THERM# and PM_EXTTS#0 . (Modify CKT,BOM&Layout)
37. Reserve a cap at JP30.P2 pin for +5VS of Docking for customer request.  94.09.15.
-Reserve C1033(@22U_0805_6.3V4Z) close to JP30.P2. (Modify CKT&Layout)
38. Delete Bulk Cap. Daul Layout design reserve for DFx request.  94.09.15.
-Change C633 from @47U_25V(Non-LF) to 100U_25V(250',10sec,LF); Del C1013~C1017 . (Modify CKT,BOM&Layout)
-Del C823(100U 6.3V M B (6.3X6.0) CV-AX),C939,C830,C806(220U_C6_6.3V_M_R15) . (Modify CKT&Layout)
-Del C979(220U_D2_2VK_R9); Change C670 to SF22001M300. (Modify CKT,BOM&Layout)
-Del C1012(150U_D_6.3VM); Change C671 to SF22001M300. (Modify CKT,BOM&Layout)
-Del C567,C568(150U_D_6.3VM); Change C1,C527 to SF22001M300. (Modify CKT,BOM&Layout)
39. Remove all Clock Gen. pairs Pull-Down Resistors for LP design recommend.  94.09.15.
-Remove R1071,R1073,R1076,R1082,R1119,R1122,R1094,R1096,R1258,R1260,R1112,R1116,R1250,R1252,
R1124,R1127,R1134,R1137,R1238,R1239. (Modify CKT&BOM)
40. Modify XMIT_OFF related design for S/W request.  94.09.16.
-Add R1424(0_0402) between XMIT_OFF and XMIT_OFF#. (Modify CKT,BOM&Layout)
41. Modify TI PCMCIA Controller related design for Vendor request.  94.09.16.
-Add R591(0_0402) close to U42.E2. (Modify CKT,BOM&Layout)
-Add R617~R620,R623,R624(0_0402) close to JP41. (Modify CKT,BOM&Layout)
-Reserve C369,C372,C373,R593,R599,R613,R614 close to JP9. (Modify CKT&Layout)
-Remove R565. (Modify CKT&BOM)
42. Modify Audio Codec related design to avoid a small amount of noise on pin 2 could cause the codec to power
up in a test mode.  94.09.21.
-Change R422 from @0_0402 to 10K_0402. (Modify CKT&BOM)
43. Modify ICH7 related design for ICH7M & 3945abg Host Interface auto-detect sequence Issue (Sighting# 80332).
 94.09.21.
-Change decoupling caps (C710 & C711) from 0.1uF_0402 to 0.15uF_0603). (Modify CKT,BOM&Layout)
44. Modify Clock Gen. all series termination resistors for the differential signals related design for ICS recommend.
 94.09.21.
-Change R1070,R1072,R1075,R1081,R1118,R1121,R1257,R1259,R1093,R1095,R1144,R1145,R1123,R1126,R1111,
R1115,R1249,R1251 from 33_0402 to 24_0402. (Modify CKT&BOM)

1

2

3

3

4

4

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(5)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.5

LA-2821P

Date:

4

Friday, November 25, 2005

Sheet
5

52

of

52

www.s-manuals.com



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