Compal LA 2821 Schematics. Www.s Manuals.com. 2821p R0.5 Schematics

User Manual: Motherboard Compal LA-2821 AngelFire 3.0 - Schematics. Free.

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Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Cover Sheet
Custom
152Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
REV:0.5
Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic
Schematics Document
2005-11-24
Compal confidential
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Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Block Diagram
252Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Power On/Off CKT.
File Name : LA-2821P
LPC BUS
Compal confidential
PCBGA 1466
page 20
H_A#(3..31)
CardBus Controller
TI PCI7612
page 30
BANK 0, 1, 2, 3
USB conn x2
533/667MHz
DMI
page 23,24
DC/DC Interface CKT.
Mobile Yonah
page 34
USB2.0
FSB
Clock Generator
ICS954306
Power Circuit DC/DC
PATA ODD Connector
PCI BUS
uFCPGA-478 CPU
page 34
DDR2-SO-DIMM X2
page 36
Intel Calistoga MCH
page 4page 4,5,6
RTC CKT.
page 15
DDR2 -400/533/667
mBGA-652
page 37
page 4
page 7,8,9,10,11,12
Intel ICH7-M
Thermal Sensor
ADM1032AR
page 13,14
page 19,20,21,22
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK
Power OK CKT.
page 20
Slot 0/Smart Card
page 24
page 18
Fan Control
PCI-E x 16
page 16
CRT / TV-OUT
Dual Channel
SMSC Super I/O
LPC47N217 SST49LF008A
Flash ROM
Security Module
COM1 LPT
Touch Pad CONN. Int.KBD
SMSC KBC 1021
6in1 Slot
LCD CONN
page 17
MXM III connector
page 23
page 32
page 33
page 34page 34
page 31page 32
Page 38,39,40,41,42,43,44,45,46,47
page 25,26
page 26
10/100/1000 LAN
BCM5753M
RJ45/11 CONN
PCI-E BUS
1394 port
page 23
page 35page 35
USB2.0 HUB /
FP Conn
page 30
FingerPrinter AES2501
USBx1
page 30
BT Conn
page 30
( Docking )( Docking )
page 32
LED
SPI
page 23
page 28page 29
AD1981HD
Audio CKTAMP & Audio Jack
MAX9710ETP
USB conn x2
(Sub Board)
page 29
H_D#(0..63)
AngelFire 3.0
USB conn x2
(Docking)
page 35
AC-LINK/Azalia page 34
MDC1.5
page 20
SATA HDD Connector
SATA Master
PATA Slave
page 27
Mini-Card
945PM
Accelerometer
LIS3LV02DQ
page 27
New Card USBx1
page 24
SPI ROM
SST25LF080A
page 27
Accelerometer
LIS3LV02DQ
TrackPoint CONN.
page 34
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Notes List
352Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
IDSEL #
VIN
SMBUS
OFF
Power Plane
F
N/AN/A
PATA/SATA
LPC I/F
ON
AC or battery power rail for power circuit
AC97 Audio
+CPU_CORE
+0.9VS
S3
D31
+1.5VS
AC97 MODEM
D29
OFF
0
+VCCP
D8
2
N/A
1 0 1 0 0 1 0 0
Internal PCI Devices
A4
USB1.1/2.0
I2C / SMBUS ADDRESSING
D30
C D E G
ON
1 0 1 0 0 0 0 0
D2
CARD BUS
A0
CLOCK GENERATOR (EXT.)
HEX
D30
DDR SO-DIMM 1
0.9V switched power rail for DDRII Vtt
S0-S1
D6
D30
ONOFF
ON
D4
PCI Device ID
N/A
N/A
ADDRESS
DEVICE
OFF
PCI Device ID
Description
Mini-PCI
DDR SO-DIMM 0
DEVICE
1.05V power rail for Processor I/O and MCH/ICH core power
PCI to PCI (DMI to PCI)
Adapter power supply (18.5V)
1 1 0 1 0 0 1 0
External PCI Devices
LAN
N/A
REQ/GNT #
OFF
D31
OFF
DEVICE
Core voltage for CPU
OFF
AD22
OFF
PIRQ
S5
D31
1.5V switched power rail for PCI-E interface
B+
Voltage Rails
AD20
OFF2.5V switched power rail for MCH video PLL
5V always on power rail
ON
3.3V always on power rail
3.3V switched power rail+3VS
ON*
RTC powerONON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+1.8V
OFF
OFF
ON
ON
+3VALW
OFF
ON
5V switched power rail
ON
+2.5VS
+RTC_VCC
+5VS
ON
ON
ONOFF
+5VALW
ON
1.8V power rail for DDRII
ON*
ON+1.8VSOFFOFF1.8V switched power rail
D28PCI-E
AzaliaD27
IDSEL #
AD24
AD11
AD12
AD13
AD14
AD15
AD14
AD14
AD15
AD15
Bus
0
1
0
0
0
0
0
0
0
0
AD15D31
0
CPU I/F
0
D31AD15DMA
0
D31AD15PMU
ONOFFOFF
: Layout Note related Area Mark.
: Question Area Mark.(Wait check)
: Modified Area Mark.
: C-BOM impact
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function reserve.
L
Note: Layout Related Memo
: Modified Area Mark(Compare with EAL60).
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
USB HUB5C0 1 0 1 1 1 0 0
TPM1.2@ : means just build when TPM1.2 function enable.
TPM@ : means just build when TPM function enable.
SC@ : means just build when SmartCard function enable.
SATA@ : means just build when SATA I/F HDD enable.
NOSATA@ : means just build when SATA I/F HDD disable.
NONC@ : means just build when New Card function disable.
NC@ : means just build when New Card function enable.
MDC1.5@ : means just build when MDC1.5 function enable.
FWH@ : means just build when FWH I/F BIOS function reserve.
7612@ : means just build when TI PCI7612 chip selected.
7611@ : means just build when TI PCI7611MLS chip selected.
45@ : means need be mounted when 45 level assy or rework stage.
250@ : means just build when SMsC LPC47N250 chip selected.
1021@ : means just build when SMsC KBC1021 chip selected.
1981HD@ : means just build when AD1981HD chip selected.
9/15
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.
3.3V always on power rail+2.5VALWONONON*
* : means define for SMT build when this stage
*NODP@ : means just build when No DP design Clock Gen. selected.
DP@ : means just build when DP design Clock Gen. selected.
*
LPNO@ : means just build when No LP design ICS Clock Gen. selected.
*
*
*
*
*
*
*
*
*
*
*
LP@ : means just build when LP design ICS Clock Gen. selected.
*DB@ : means just build when Mini-PCI E Debug Card function enable.
*
*
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
H_A#28
H_THERMDA
H_FERR#
H_ADSTB#0
H_A#23
H_REQ#2
H_A#31
H_REQ#0
H_A#17
H_BNR#
H_A#29
H_DSTBP#0
H_A#8
H_DEFER#
H_REQ#1
H_A#3
H_RS#0
H_DSTBN#1
H_A#6
XDP_BPM#2
H_BPRI#
H_ADS#
H_A#25
XDP_BPM#3
H_RS#1
H_DSTBP#1
H_A#4
H_IERR#
H_HITM#
H_DSTBN#0
H_INTR
H_DSTBN#2
H_A#22
H_A#7
H_REQ#4
XDP_DBRESET#
H_DRDY#
H_A#15
H_A#14
H_A20M#
H_DINV#0
H_DSTBP#2
H_DINV#2
H_DINV#3
H_DINV#1
H_DSTBN#3
H_DSTBP#3
H_NMI
H_A#30
H_A#27
H_A#18
H_A#10
H_BR0#
H_LOCK#
H_A#11
H_A#21
H_A#26
H_A#13
H_A#9
XDP_BPM#0
H_DPSLP#
H_A#20
H_A#16
H_A#12
H_HIT#
H_ADSTB#1
H_THERMTRIP#
H_DBSY#
H_A#19
H_A#24
H_A#5
H_RS#2
H_RESET#
XDP_BPM#1
H_REQ#3
H_SMI#
H_STPCLK#
XDP_TCK
XDP_TRST#
XDP_TMS
H_CPUSLP#
XDP_TDO
XDP_TDI
H_PWRGOOD
XDP_BPM#5
H_DPRSTP#
H_TRDY#
CLK_CPU_BCLK
CLK_CPU_BCLK#
ICH_SMBCLK
ICH_SMBDATA
H_THERMDA
H_THERMDC
THERM#
THERM_SCI#
ICH_SMBDATA
ICH_SMBCLK
THERM#
FAN
H_THERMDC
XDP_BPM#4
H_DPWR#
TEST1
TEST2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#7
H_D#6
H_D#4
H_D#5
H_D#11
H_D#10
H_D#8
H_D#9
H_D#15
H_D#14
H_D#12
H_D#13
H_D#19
H_D#18
H_D#16
H_D#17
H_D#23
H_D#22
H_D#20
H_D#21
H_D#27
H_D#26
H_D#24
H_D#25
H_D#31
H_D#30
H_D#28
H_D#29
H_D#35
H_D#34
H_D#32
H_D#33
H_D#39
H_D#38
H_D#36
H_D#37
H_D#43
H_D#42
H_D#40
H_D#41
H_D#47
H_D#46
H_D#44
H_D#45
H_D#51
H_D#50
H_D#48
H_D#49
H_D#55
H_D#54
H_D#52
H_D#53
H_D#59
H_D#58
H_D#56
H_D#57
H_D#63
H_D#62
H_D#60
H_D#61
H_INIT#
H_IGNNE#
H_PROCHOT#
H_PROCHOT# OCP#
H_DPSLP#
H_DPRSTP#
XDP_BPM#3
ICH_SMBDATA
ICH_SMBCLK
XDP_BPM#2
XDP_DBRESET#_R
XDP_BPM#1
XDP_BPM#0
XDP_PRE
XDP_DBRESET#XDP_DBRESET#_R
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
XDP_TDO
XDP_TRST#
XDP_TMS
XDP_TDI
XDP_TDO
H_RESET#H_RESET#_R
H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP
CLK_CPU_XDP#
XDP_BPM#4
XDP_BPM#5
XDP_BPM#5
ICH_SMBDATA13,14,15,18,21,25,27
ICH_SMBCLK13,14,15,18,21,25,27
THERM_SCI#21
FAN_PWM33
H_D#[0..63]7
H_A#[3..31]7
H_REQ#[0..4]7
H_ADSTB#07 H_ADSTB#17
CLK_CPU_BCLK#15 CLK_CPU_BCLK15
H_ADS#7 H_BNR#7
H_BR0#7
H_DRDY#7 H_HIT#7 H_HITM#7
H_BPRI#7
H_DEFER#7
H_LOCK#7 H_RESET#7
H_RS#[0..2]7
H_TRDY#7
H_DBSY#7 H_DPSLP#20 H_DPRSTP#20,45 H_DPWR#7
H_CPUSLP#7
H_THERMTRIP#7,20
H_DINV#07
H_DINV#17
H_DINV#27
H_DINV#37
H_DSTBN#[0..3]7
H_DSTBP#[0..3]7
H_A20M#20
H_FERR#20
H_IGNNE#20
H_INIT#20
H_INTR20
H_NMI20
H_STPCLK#20
H_SMI#20
XDP_DBRESET#21
H_PROCHOT#45
OCP#21,47
CLK_CPU_XDP15
CLK_CPU_XDP#15
H_PWRGOOD20
+VCCP
+3VS
+3VS
+5VS
+3VS
+VCCP
+VCCP
+3VS
+VCCP +VCCP
+VCCP
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Yonah CPU in mFCPGA479
452Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
Thermal Sensor ADM1032AR-2
PWM Fan Control circuit
ITP-XDP Connector
This shall place near CPU
Address:1001_101
5/10
D1
CH751H-40_SC76
2 1
JP6
ACES_85205-0200
1
2
JP31
SAMTE_BSH-030-01-L-D-A
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1 2
OBSFN_C0 4
OBSFN_C1 6
GND3 8
OBSDATA_C0 10
OBSDATA_C1 12
GND5 14
OBSDATA_C2 16
OBSDATA_C3 18
GND7 20
OBSFN_D0 22
OBSFN_D1 24
GND9 26
OBSDATA_D0 28
OBSDATA_D1 30
GND11 32
OBSDATA_D2 34
OBSDATA_D3 36
GND13 38
ITPCLK/HOOK4 40
ITPCLK#/HOOK5 42
VCC_OBS_CD 44
RESET#/HOOK6 46
DBR#/HOOK7 48
GND15 50
TD0 52
TRST# 54
TDI 56
TMS 58
GND17 60
R2851_0402_5%
1 2
U31
TC7SH00FUF_SSOP5
INB
1
INA
2O4
G
3P5
R52556_0402_5%
1 2
R447
56_0402_5%
1 2
C63
0.1U_0402_16V4Z
1
2
R52356_0402_1%
1 2
C68
2200P_0402_50V7K
1 2
R271K_0402_5%@
1 2
S
G
D
Q69
AO6402_TSOP6
3
6
2
4 5
1
R443 1K_0402_5%@
1 2
R444
200_0402_1%
12
R52656_0402_5%
1 2
R30
56_0402_5%@
12
R24
10K_0402_5%
12
R448
56_0402_5%
1 2
C5390.1U_0402_16V4Z
12
R439
56_0402_5%@
1 2
R25
10K_0402_5%
1 2
C69
0.1U_0402_16V4Z 1
2
R440
56_0402_5%@
1 2
R442
1K_0402_5%
12
R52156_0402_5%
1 2
R1910_0402_5%
1 2
U5
ADM1032AR-2_MSOP8
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
R52256_0402_5%
1 2
C65
4.7U_0805_10V4Z
1
2
R441
1K_0402_1%
1 2
E
B
C
Q6
MMBT3904_SOT23@
2
3 1
ZD1
RLZ5.1B_LL34
@
12
R52456_0402_5%
1 2
ADDR GROUP
CONTROL
HOST CLK
MISC
DATA GROUP
THERMAL
DIODE
LEGACY CPU
YONAH
JP8A
FOX_PZ47903-2741-42_YONAH
A3#
J4
A4#
L4
A5#
M3
A6#
K5
A7#
M1
A8#
N2
A9#
J1
A10#
N3
A11#
P5
A12#
P2
A13#
L1
A14#
P4
A15#
P1
A16#
R1
A17#
Y2
A18#
U5
A19#
R3
A20#
W6
A21#
U4
A22#
Y5
A23#
U2
A24#
R4
A25#
T5
A26#
T3
A27#
W3
A28#
W5
A29#
Y4
A30#
W2
A31#
Y1
REQ0#
K3
REQ1#
H2
REQ2#
K2
REQ3#
J3
REQ4#
L5
ADSTB0#
L2
ADSTB1#
V4
BCLK0
A22
BCLK1
A21
ADS#
H1
BNR#
E2
BPRI#
G5
BR0#
F1
DEFER#
H5
DRDY#
F21
HIT#
G6
HITM#
E4
IERR#
D20
LOCK#
H4
RESET#
B1
RS0#
F3
RS1#
F4
RS2#
G3
TRDY#
G2
BPM0#
AD4
BPM1#
AD3
BPM2#
AD1
BPM3#
AC4
DBR#
C20
DBSY#
E1
DPSLP#
B5
DPWR#
D24
PRDY#
AC2
PREQ#
AC1
PROCHOT#
D21
PWRGOOD
D6
SLP#
D7
TCK
AC5
TDI
AA6
TDO
AB3
TEST1
C26
TEST2
D25
TMS
AB5
TRST#
AB6
THERMDA
A24
THERMDC
A25
THERMTRIP#
C7
D0# E22
D1# F24
D2# E26
D3# H22
D4# F23
D5# G25
D6# E25
D7# E23
D8# K24
D9# G24
D10# J24
D11# J23
D12# H26
D13# F26
D14# K22
D15# H25
D16# N22
D17# K25
D18# P26
D19# R23
D20# L25
D21# L22
D22# L23
D23# M23
D24# P25
D25# P22
D26# P23
D27# T24
D28# R24
D29# L26
D30# T25
D31# N24
D32# AA23
D33# AB24
D34# V24
D35# V26
D36# W25
D37# U23
D38# U25
D39# U22
D40# AB25
D41# W22
D42# Y23
D43# AA26
D44# Y26
D45# Y22
D46# AC26
D47# AA24
D48# AC22
D49# AC23
D50# AB22
D51# AA21
D52# AB21
D53# AC25
D54# AD20
D55# AE22
D56# AF23
D57# AD24
D58# AE21
D59# AD21
D60# AE25
D61# AF25
D62# AF22
D63# AF26
DINV0# J26
DINV1# M26
DINV2# V23
DINV3# AC20
DSTBN0# H23
DSTBN1# M24
DSTBN2# W24
DSTBN3# AD23
DSTBP0# G22
DSTBP1# N25
DSTBP2# Y25
DSTBP3# AE24
A20M# A6
FERR# A5
IGNNE# C4
INIT# B3
LINT0 C6
LINT1 B4
STPCLK# D5
SMI# A3
DPRSTP#
E5
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
COMP3
COMP2
H_PSI#
COMP1
COMP0
CPU_VID1
CPU_VID0
CPU_VID3
CPU_VID4
CPU_VID2
CPU_VID5
CPU_VID6
CPU_BSEL1
CPU_BSEL2
CPU_BSEL0
VSSSENSE
VCCSENSE
VSSSENSE
VCCSENSE
H_PSI#45
CPU_VID045 CPU_VID145 CPU_VID245 CPU_VID345 CPU_VID445 CPU_VID545 CPU_VID645
CPU_BSEL015 CPU_BSEL115 CPU_BSEL215
VCCSENSE45 VSSSENSE45
+VCCP
+VCC_CORE
+VCCP
V_CPU_GTLREF
V_CPU_GTLREF
+1.5VS
+VCC_CORE
+VCC_CORE
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Yonah CPU in mFCPGA479
552Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
Close to CPU pin AD26
within 500mils.
CPU_BSELCPU_BSEL2CPU_BSEL1
133
166
00
0
1
CPU_BSEL0
1
1
Length match within 25 mils
The trace width 18 mils space
7 mils
Close to CPU pin
within 500mils.
R470
27.4_0402_1%
12
R39
2K_0402_1%
12
C70
0.01U_0402_16V7K
1
2
R41
100_0402_1%
1 2
POWER, GROUND
YONAH
JP8C
FOX_PZ47903-2741-42_YONAH
VCC
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VSS K1
VSS J2
VSS M2
VSS N1
VSS T1
VSS R2
VSS V2
VSS W1
VSS A26
VSS D26
VSS C25
VSS F25
VSS B24
VSS A23
VSS D23
VSS E24
VSS B21
VSS C22
VSS F22
VSS E21
VSS B19
VSS A19
VSS D19
VSS C19
VSS F19
VSS E19
VSS B16
VSS A16
VSS D16
VSS C16
VSS F16
VSS E16
VSS B13
VSS A14
VSS D13
VSS C14
VSS F13
VSS E14
VSS B11
VSS A11
VSS D11
VSS C11
VSS F11
VSS E11
VSS B8
VSS A8
VSS D8
VSS C8
VSS F8
VSS E8
VSS G26
VSS K26
VSS J25
VSS M25
VSS N26
VSS T26
VSS R25
VSS V25
VSS W26
VSS H24
VSS G23
VSS K23
VSS L24
VSS P24
VSS N23
VSS T23
VSS U24
VSS Y24
VSS W23
VSS H21
VSS J22
VSS M22
VSS L21
VSS P21
VSS R22
VSS V22
VSS U21
VSS Y21
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
F7 VCC
A7
R35
27.4_0402_1%
12
R37
1K_0402_1%
12
POWER, GROUNG, RESERVED SIGNALS AND NC
YONAH
JP8B
FOX_PZ47903-2741-42_YONAH
PSI#
AE6
GTLREF
AD26
VCCSENSE
AF7
VCCA
B26
VCC
AB20
VCC
AA20
VCC
AF20
VCC
AE20
VCC
AB18
VCC
AB17
VCC
AA18
VCC
AA17
VCC
AD18
VCC
AD17
VCC
AC18
VCC
AC17
VCC
AF18
VCC
AF17
RSVD
T22
RSVD
V3
RSVD
B2
RSVD
C3
VSS AB26
VSS AA25
VSS AD25
VSS AE26
VSS AB23
VSS AC24
VSS AF24
VSS AE23
VSS AA22
VSS AD22
VSS AC21
VSS AF21
VSS AB19
VSS AA19
VSS AD19
VSS AC19
VSS AF19
VSS AE19
VSS AB16
VSS AA16
VSS AD16
VSS AC16
VSS AF16
VSS AE16
VSS AB13
VSS AA14
VSS AD13
VSS AC14
VSS AF13
VSS AE14
VSS AB11
VSS AA11
VSS AD11
VSS AC11
VSS AF11
VSS AE11
VSS AB8
VSS AA8
VSS AD8
VSS AC8
VSS AF8
VSS AE8
VSS AA5
VSS AD5
VSS AC6
VSS AF6
VSS AB4
VSS AC3
VSS AF3
VSS AE4
VSS AB1
VSS AA2
VSS AD2
VSS AE1
VSS B6
VSS C5
VSS F5
VSS E6
VSS H6
VSS J5
VSS M5
VSS L6
VSS P6
VSS R5
VSS V5
VSS U6
VSS Y6
VSS A4
VSS D4
VSS E3
VSS H3
VSS G4
VSS K4
VSS L3
VSS P3
VSS N4
VSS T4
VSS U3
VSS Y3
VSS W4
VSS D1
VSS C2
VSS F2
VSS G1
RSVD
B25
VSSSENSE
AE7
VCCP
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
T6
VCCP
R6
VCCP
K21
VCCP
J21
VCCP
M21
VCCP
N21
VCCP
T21
VCCP
R21
VCCP
V21
VCCP
W21
VCCP
V6
VCCP
G21
VID0
AD6
VID1
AF5
VID2
AE5
VID3
AF4
VID4
AE3
VID5
AF2
VID6
AE2
BSEL0
B22
BSEL1
B23
BSEL2
C21
COMP0
R26
COMP1
U26
COMP2
U1
COMP3
V1
RSVD
C23
RSVD
C24
RSVD
AA1
RSVD
AA4
RSVD
AB2
RSVD
AA3
RSVD
M4
RSVD
N5
RSVD
T2
RSVD
D2
RSVD
F6
RSVD
D3
RSVD
C1
RSVD
AF1
RSVD
D22
VCC
E7
R36
54.9_0402_1%
12
C72
10U_0805_10V4Z
1
2
R473
54.9_0402_1%
12
R42
100_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
+VCCP
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
CPU Bypass capacitors
652Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Mid Frequence Decoupling
ESR <= 1.5m ohm
Capacitor > 1980uF
South Side Secondary
Place these inside
socket cavity on L8
(North side
Secondary)
North Side Secondary
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
Place these capacitors on L8
(North side,Secondary Layer)
C435
10U_0805_6.3V6M
1
2
C443
10U_0805_6.3V6M
1
2
C431
10U_0805_6.3V6M
1
2
C429
0.1U_0402_10V6K
1
2
C485
10U_0805_6.3V6M
1
2
C415
10U_0805_6.3V6M
1
2
C438
0.1U_0402_10V6K
1
2
+
C409
330U_D2E_2.5VM_R9@
1
2
C480
10U_0805_6.3V6M
1
2
+
C120
820U_E9_2_5V_M_R7@
1
2
C484
10U_0805_6.3V6M
1
2
C425
10U_0805_6.3V6M
1
2
C481
10U_0805_6.3V6M
1
2
+
C119
820U_E9_2_5V_M_R7@
1
2
C428
0.1U_0402_10V6K
1
2
C441
10U_0805_6.3V6M
1
2
+
C125
330U_D2E_2.5VM_R7
1
2
C418
10U_0805_6.3V6M
1
2
C436
10U_0805_6.3V6M
1
2
C417
10U_0805_6.3V6M
1
2
+
C66
330U_D2E_2.5VM_R7
1
2
C416
10U_0805_6.3V6M
1
2
C445
10U_0805_6.3V6M
1
2
+
C67
330U_D2E_2.5VM_R7
1
2
C432
10U_0805_6.3V6M
1
2
C411
10U_0805_6.3V6M
1
2
C433
0.1U_0402_10V6K
1
2
C437
0.1U_0402_10V6K
1
2
C444
10U_0805_6.3V6M
1
2
C442
10U_0805_6.3V6M
1
2
+
C117
330U_D2E_2.5VM_R7
1
2
C413
10U_0805_6.3V6M
1
2
C483
10U_0805_6.3V6M
1
2
+
C434
220U_D2_2VK_R9
1
2
C479
10U_0805_6.3V6M
1
2
C482
10U_0805_6.3V6M
1
2
C427
10U_0805_6.3V6M
1
2
C423
10U_0805_6.3V6M
1
2
C486
10U_0805_6.3V6M
1
2
+
C408
330U_D2E_2.5VM_R9@
1
2
C426
10U_0805_6.3V6M
1
2
C421
0.1U_0402_10V6K
1
2
C414
10U_0805_6.3V6M
1
2
C422
10U_0805_6.3V6M
1
2
C412
10U_0805_6.3V6M
1
2
C424
10U_0805_6.3V6M
1
2
C446
10U_0805_6.3V6M
1
2
5 4 3 2
2
1
1
DD
CC
BB
AA
H_SWNG0
H_VREF
PM_EXTTS#0
V_DDR_MCH_REF
M_OCDOCMP1
PM_EXTTS#1
H_RS#0
H_ADSTB#1
H_SWNG1
H_XRCOMP
CFG3
DMI_TXP1
H_REQ#0
CFG7
CFG5
DDR_CKE0_DIMMA
M_CLK_DDR3
DMI_RXN2
H_HIT#
H_DSTBP#0
H_REQ#4
H_SWNG0
CFG15
DDR_CKE1_DIMMA
M_OCDOCMP0
DMI_TXN1
DMI_TXN0
H_BNR#
H_REQ#2
M_ODT1
DMI_TXP2
H_DSTBP#2
CLK_MCH_3GPLL
CFG13
M_CLK_DDR#0
DMI_RXP2
H_REQ#3
CFG9
H_DINV#2
CLK_MCH_BCLK#
H_REQ#1
H_YSCOMP
MCH_CLKSEL0
DDR_CKE3_DIMMB
H_BPRI#
H_DINV#0
CFG18
CFG4
M_CLK_DDR#1
DMI_RXP1
DMI_RXP0
DMI_TXP0
H_CPUSLP#
H_DPWR#
H_ADS#
H_DSTBP#3
H_DSTBN#3
CFG16
DMI_RXN1
M_OCDOCMP0
CLK_MCH_BCLK
PLTRST_R#
CFG19
CFG12
DDR_CS1_DIMMA#
SMRCOMPN
H_DSTBP#1
H_DINV#3
H_RS#2
H_ADSTB#0
CFG17
CFG8
CFG6
DDR_CKE2_DIMMB
DMI_RXN0
H_LOCK#
H_RESET#
M_ODT3
M_OCDOCMP1
M_CLK_DDR#2
DMI_TXP3
DMI_TXN3
H_DBSY#
H_BR0#
H_DSTBN#1
H_DSTBN#0
CLK_MCH_3GPLL#
CFG20
V_DDR_MCH_REF
H_DSTBN#2
H_RS#1
H_XSCOMP
CFG10
MCH_CLKSEL2
DDR_CS0_DIMMA#
SMRCOMPP
M_CLK_DDR#3
PM_BMBUSY#
CFG11
DDR_CS3_DIMMB#
DMI_RXN3
H_HITM#
H_DRDY#
PM_EXTTS#0
DDR_CS2_DIMMB#
M_ODT2
M_ODT0
H_DEFER#
H_TRDY#
H_DINV#1
H_THERMTRIP#
CFG14
M_CLK_DDR2
M_CLK_DDR1
M_CLK_DDR0
H_VREF
H_YRCOMP
DMI_TXN2
DMI_RXP3
PM_EXTTS#1
MCH_CLKSEL1
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#11
H_D#13
H_D#9
H_D#14
H_D#8
H_D#15
H_D#12
H_D#10
H_D#19
H_D#21
H_D#17
H_D#22
H_D#16
H_D#23
H_D#20
H_D#18
H_D#27
H_D#29
H_D#25
H_D#30
H_D#24
H_D#31
H_D#28
H_D#26
H_D#35
H_D#37
H_D#33
H_D#38
H_D#32
H_D#39
H_D#36
H_D#34
H_D#43
H_D#45
H_D#41
H_D#46
H_D#40
H_D#47
H_D#44
H_D#42
H_D#51
H_D#53
H_D#49
H_D#54
H_D#48
H_D#52
H_D#50
H_D#55
H_D#59
H_D#61
H_D#57
H_D#62
H_D#56
H_D#63
H_D#60
H_D#58
H_SWNG1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#11
H_A#8
H_A#10
H_A#12
H_A#9
H_A#13
H_A#15
H_A#17
H_A#14
H_A#21
H_A#18
H_A#20
H_A#22
H_A#19
H_A#26
H_A#23
H_A#25
H_A#27
H_A#24
H_A#31
H_A#28
H_A#30
H_A#29
H_A#16
GMCH_A27
GMCH_A26
GMCH_C40
GMCH_D41
PWROK
PWROK
GMCH_C40
GMCH_D41
GMCH_A27
GMCH_A26
CLKREQC#
PM_EXTTS#0DDR_THERM#
H_D#[0..63]4 H_A#[3..31]4
H_REQ#[0..4]4
H_ADSTB#14
H_ADSTB#04
CLK_MCH_BCLK#15
CLK_MCH_BCLK15
H_DSTBN#[0..3]4
H_DSTBP#[0..3]4
H_DINV#04
H_DINV#14
H_DINV#24
H_DINV#34
H_RESET#4
H_ADS#4
H_TRDY#4
H_DPWR#4
H_DRDY#4
H_DEFER#4
H_BR0#4
H_BNR#4
H_BPRI#4
H_DBSY#4
H_CPUSLP#4
H_HITM#4
H_HIT#4
H_LOCK#4
H_RS#[0..2]4
DMI_TXN021 DMI_TXN121 DMI_TXN221 DMI_TXN321
DMI_TXP021 DMI_TXP121 DMI_TXP221 DMI_TXP321
M_CLK_DDR013 M_CLK_DDR113 M_CLK_DDR214 M_CLK_DDR314
M_CLK_DDR#013 M_CLK_DDR#113 M_CLK_DDR#214 M_CLK_DDR#314
DDR_CS0_DIMMA#13 DDR_CS1_DIMMA#13 DDR_CS2_DIMMB#14 DDR_CS3_DIMMB#14
DDR_CKE0_DIMMA13 DDR_CKE1_DIMMA13 DDR_CKE2_DIMMB14 DDR_CKE3_DIMMB14
M_ODT013 M_ODT113 M_ODT214 M_ODT314
PM_BMBUSY#21
H_THERMTRIP#4,20
MCH_ICH_SYNC#19
V_DDR_MCH_REF13,14,44
MCH_CLKSEL015
CFG511
CFG711
CFG911
CFG1111
CFG1211
CFG1311
MCH_CLKSEL215
MCH_CLKSEL115
CFG1611
CFG1811
CFG1911
CFG2011
CLK_MCH_3GPLL15
CLK_MCH_3GPLL#15
VGATE_INTEL21,45 PM_POK21,33
DPRSLPVR21,45
CLKREQC#15
PLT_RST#19,20,21,23,25,27,32,33
DMI_RXN021 DMI_RXN121 DMI_RXN221 DMI_RXN321
DMI_RXP021 DMI_RXP121 DMI_RXP221 DMI_RXP321
DDR_THERM#13,14
+VCCP
+VCCP+VCCP
+VCCP
+3VS
+1.8V
+1.8V
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Calistoga (1/6)
752Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.
Layout Note:
Route as short
as possible
Description at page11.
Stuff R1202 & R1203 for A1 Calistoga
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
L
H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.
5/16
8/24
T1
PAD
C359
0.1U_0402_16V4Z
1
2
T3
PAD
R350
54.9_0402_1%
12
T6
PAD
R5900_0402_5%
1 2
R41380.6_0402_1%
1 2
R351
221_0603_1%
12
R17
221_0603_1%
12
C330
0.1U_0402_16V4Z
1
2
R381
54.9_0402_1%
12
T8
PAD
T2
PAD
R344
100_0402_1%
12
R362
10K_0402_5%@12
R400
40.2_0402_1%
12
R412
40.2_0402_1%
12
R343
0_0402_5%
12
T5
PAD
R15
10K_0402_5%
12
R339
24.9_0402_1%
12
T7
PAD
C328
0.1U_0402_16V4Z
1
2
R338
10K_0402_5%
12
R650_0402_5%
1 2
R342
10K_0402_5%
12
HOST
U4A
CALISTOGA_A2_FCBGA1466
HD0#
F1
HD1#
J1
HD2#
H1
HD3#
J6
HD4#
H3
HD5#
K2
HD6#
G1
HD7#
G2
HD8#
K9
HD9#
K1
HD10#
K7
HD11#
J8
HD12#
H4
HD13#
J3
HD14#
K11
HD15#
G4
HD16#
T10
HD17#
W11
HD18#
T3
HD19#
U7
HD20#
U9
HD21#
U11
HD22#
T11
HD23#
W9
HD24#
T1
HD25#
T8
HD26#
T4
HD27#
W7
HD28#
U5
HD29#
T9
HD30#
W6
HD31#
T5
HD32#
AB7
HD33#
AA9
HD34#
W4
HD35#
W3
HD36#
Y3
HD37#
Y7
HD38#
W5
HD39#
Y10
HD40#
AB8
HD41#
W2
HD42#
AA4
HD43#
AA7
HD44#
AA2
HD45#
AA6
HD46#
AA10
HD47#
Y8
HD48#
AA1
HD49#
AB4
HD50#
AC9
HD51#
AB11
HD52#
AC11
HD53#
AB3
HD54#
AC2
HD55#
AD1
HD56#
AD9
HD57#
AC1
HD58#
AD7
HD59#
AC6
HD60#
AB5
HD61#
AD10
HD62#
AD4
HD63#
AC8
HVREF1
K13
HXRCOMP
E1
HXSCOMP
E2
HYRCOMP
Y1
HYSCOMP
U1
HXSWING
E4
HYSWING
W1
HA3# H9
HA4# C9
HA5# E11
HA6# G11
HA7# F11
HA8# G12
HA9# F9
HA10# H11
HA11# J12
HA12# G14
HA13# D9
HA14# J14
HA15# H13
HA16# J15
HA17# F14
HA18# D12
HA19# A11
HA20# C11
HA21# A12
HA22# A13
HA23# E13
HA24# G13
HA25# F12
HA26# B12
HA27# B14
HA28# C12
HA29# A14
HA30# C14
HA31# D14
HREQ#0 D8
HREQ#1 G8
HREQ#2 B8
HREQ#3 F8
HREQ#4 A8
HADSTB#0 B9
HADSTB#1 C13
HRS0# B4
HRS1# E6
HRS2# D6
HCLKN AG1
HCLKP AG2
HDINV#0 J7
HDINV#1 W8
HDINV#2 U3
HDINV#3 AB10
HDSTBN#0 K4
HDSTBN#1 T7
HDSTBN#2 Y5
HDSTBN#3 AC4
HDSTBP#0 K3
HDSTBP#1 T6
HDSTBP#2 AA5
HDSTBP#3 AC5
HCPURST# B7
HADS# E8
HTRDY# E7
HDPWR# J9
HDRDY# H8
HDEFER# C3
HHITM# D4
HHIT# D3
HLOCK# B3
HBREQ0# C7
HBNR# C6
HBPRI# F6
HDBSY# A7
HCPUSLP# E3
HVREF0
J13
DMI
DDR MUXING
CFG
PM
CLKNC
RESERVED
U4B
CALISTOGA_A2_FCBGA1466
DMIRXN0
AE35
DMIRXN1
AF39
DMIRXN2
AG35
DMIRXN3
AH39
DMIRXP0
AC35
DMIRXP1
AE39
DMIRXP2
AF35
DMIRXP3
AG39
DMITXN0
AE37
DMITXN1
AF41
DMITXN2
AG37
DMITXN3
AH41
DMITXP0
AC37
DMITXP1
AE41
DMITXP2
AF37
DMITXP3
AG41
SM_CK0
AY35
SM_CK1
AR1
SM_CK2
AW7
SM_CK3
AW40
SM_CK0#
AW35
SM_CK1#
AT1
SM_CK2#
AY7
SM_CK3#
AY40
SM_OCDCOMP0
AL20
SM_OCDCOMP1
AF10
SM_ODT0
BA13
SM_ODT1
BA12
SM_ODT2
AY20
SM_ODT3
AU21
SM_RCOMPN
AV9
SM_RCOMPP
AT9
SM_VREF0
AK1
SM_VREF1
AK41
SM_CKE0
AU20
SM_CKE1
AT20
SM_CKE2
BA29
SM_CKE3
AY29
SM_CS0#
AW13
SM_CS1#
AW12
SM_CS2#
AY21
SM_CS3#
AW21
CFG16 G18
CFG1 K18
CFG2 J18
CFG3 F18
CFG4 E15
CFG5 F15
CFG6 E18
CFG7 D19
CFG8 D16
CFG9 G16
CFG10 E16
CFG11 D15
CFG12 G15
CFG13 K15
CFG14 C15
CFG15 H16
CFG0 K16
CFG17 H15
CFG18 J25
CFG19 K27
CFG20 J26
G_CLKP AG33
G_CLKN AF33
D_REF_CLKN A27
D_REF_CLKP A26
D_REF_SSCLKN C40
D_REF_SSCLKP D41
NC0 A3
NC1 A39
NC2 A4
NC3 A40
NC4 AW1
NC5 AW41
NC6 AY1
NC7 BA1
NC8 BA2
NC9 BA3
NC10 BA39
NC11 BA40
NC12 BA41
NC13 C1
NC14 AY41
NC15 B2
NC16 B41
NC17 C41
NC18 D1
PM_BMBUSY#
G28
PM_EXTTS0#
F25
PM_EXTTS1#
H26
PM_THERMTRIP#
G6
PWROK
AH33
RSTIN#
AH34
RESERVED1 T32
RESERVED2 R32
RESERVED3 F3
RESERVED4 F7
RESERVED5 AG11
RESERVED6 AF11
RESERVED7 H7
RESERVED8 J19
RESERVED9 A41
RESERVED10 A34
RESERVED11 D28
RESERVED12 D27
RESERVED13 A35
ICH_SYNC#
K28
CLK_REQ# H32
R41980.6_0402_1%
1 2
C385
0.1U_0402_16V4Z
1
2
R353
10K_0402_5%
12
R18
100_0402_1%
12
R395
24.9_0402_1%
12
R14
10K_0402_5%
12
R360
100_0402_1%
12
R408100_0402_1%
12
R409
100_0402_1%@
12
R348
200_0402_1%
12
R5970_0402_5%@
1 2
T4
PAD
R411
100_0402_1%@
12
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
DDR_B_D11
DDR_B_D57
DDR_B_D46
DDR_B_D7
DDR_B_D0
DDR_B_D44
DDR_B_D40
DDR_B_D30
DDR_B_D27
DDR_B_D15
DDR_B_D3
DDR_B_D35
DDR_B_D25
DDR_B_D23
DDR_B_D49
DDR_B_D37
DDR_B_D19
DDR_B_D48
DDR_B_D47
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D62
DDR_B_D60
DDR_B_D9
DDR_B_D2
DDR_B_D52
DDR_B_D50
DDR_B_D22
DDR_B_D56
DDR_B_D51
DDR_B_D39
DDR_B_D28
DDR_B_D17
DDR_B_D45
DDR_B_D6
DDR_B_D61
DDR_B_D58
DDR_B_D1
DDR_B_D54
DDR_B_D41
DDR_B_D31
DDR_B_D12
DDR_B_D5
DDR_B_D38
DDR_B_D32
DDR_B_D20
DDR_B_D16
DDR_B_D14
DDR_B_D33
DDR_B_D63
DDR_B_D59
DDR_B_D42
DDR_B_D55
DDR_B_D53
DDR_B_D43
DDR_B_D29
DDR_B_D26
DDR_B_D13
DDR_B_D4
DDR_B_BS#2
DDR_B_D34
DDR_B_D24
DDR_B_D21
DDR_B_D10
DDR_B_WE#
DDR_B_RAS#
DDR_A_D35
DDR_A_D15
DDR_A_D14
DDR_A_D21
DDR_A_BS#2
DDR_A_D28
DDR_A_D11
DDR_A_D7
DDR_A_WE#
DDR_A_D31
DDR_A_D16
DDR_A_D59
DDR_A_D56
DDR_A_D42
DDR_A_D25
DDR_A_D9
DDR_A_D60
DDR_A_D55
DDR_A_D13
DDR_A_D0
DDR_A_D62
DDR_A_D3
DDR_A_D1
DDR_A_D41
DDR_A_D20
DDR_A_D43
DDR_A_D24
DDR_A_CAS#
DDR_A_D54
DDR_A_D52
DDR_A_D33
DDR_A_D12
DDR_A_D19
DDR_A_D46
DDR_A_D23
DDR_A_D18
DDR_A_D63
DDR_A_D34
DDR_A_D26
DDR_A_D22
SA_RCVENIN#
SA_RCVENOUT# SB_RCVENIN#
SB_RCVENOUT#
DDR_A_D27
DDR_A_D2
DDR_A_D32
DDR_A_D6
DDR_A_D49
DDR_A_D47
DDR_A_D58
DDR_A_D40
DDR_A_D36
DDR_A_D5
DDR_A_D48
DDR_A_D10
DDR_A_D8
DDR_A_D57
DDR_A_D39
DDR_A_D37
DDR_A_D30
DDR_A_D4
DDR_A_D45
DDR_A_D53
DDR_A_D51
DDR_A_D17
DDR_A_D38
DDR_A_D29
DDR_A_D44
DDR_A_D50
DDR_A_D61
DDR_A_DQS6 DDR_B_DQS7
DDR_B_MA9
DDR_A_MA13
DDR_A_MA7
DDR_A_DM1
DDR_A_MA5
DDR_A_DM7
DDR_B_MA0
DDR_A_DQS7
DDR_A_DM5
DDR_B_MA7
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DM3
DDR_B_DQS1
DDR_B_DM1
DDR_A_BS#0
DDR_A_DQS#6
DDR_B_DQS5
DDR_B_DM0
DDR_A_MA4
DDR_A_MA8
DDR_A_DQS#7
DDR_A_MA10
DDR_A_DQS5
DDR_A_DM2
DDR_A_DQS0
DDR_B_MA2
DDR_B_MA13
DDR_B_DM5
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_BS#1
DDR_A_DQS#1
DDR_A_MA2
DDR_B_MA4
DDR_A_DQS#5
DDR_B_DM6
DDR_B_DQS4
DDR_A_DQS1
DDR_A_MA9
DDR_A_DQS4
DDR_A_DM0
DDR_A_MA0
DDR_B_MA5
DDR_A_DM4
DDR_A_DQS#2
DDR_A_DQS3
DDR_B_MA3
DDR_A_MA11 DDR_B_MA11
DDR_B_BS#0
DDR_A_DM6
DDR_B_MA6DDR_A_MA6
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_A_DQS#0
DDR_A_DM3
DDR_A_MA3
DDR_A_MA12
DDR_B_MA8
DDR_A_DQS2
DDR_B_DQS#0
DDR_B_MA10
DDR_B_DM7
DDR_A_MA1
DDR_B_MA12
DDR_B_DQS#2
DDR_B_DM4
DDR_B_DQS#6
DDR_B_MA1
DDR_B_DQS2
DDR_B_DQS6
DDR_B_DM2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_RAS# DDR_B_CAS#
DDR_A_BS#1
DDR_A_BS#013 DDR_A_BS#113 DDR_A_BS#213
DDR_A_DM[0..7]13
DDR_A_DQS[0..7]13
DDR_A_DQS#[0..7]13
DDR_A_MA[0..13]13
DDR_A_CAS#13 DDR_A_RAS#13
DDR_A_WE#13
DDR_B_BS#014 DDR_B_BS#114 DDR_B_BS#214
DDR_B_DM[0..7]14
DDR_B_DQS[0..7]14
DDR_B_DQS#[0..7]14
DDR_B_MA[0..13]14
DDR_B_CAS#14
DDR_B_RAS#14
DDR_B_WE#14
DDR_A_D[0..63]13 DDR_B_D[0..63]14
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Calistoga (2/6)
852Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
T12PAD T10PAD
T11PAD
DDR SYS MEMORY B
U4E
CALISTOGA_A2_FCBGA1466
SB_DQ0 AK39
SB_DQ1 AJ37
SB_DQ2 AP39
SB_DQ3 AR41
SB_DQ4 AJ38
SB_DQ5 AK38
SB_DQ6 AN41
SB_DQ7 AP41
SB_DQ8 AT40
SB_DQ9 AV41
SB_DQ10 AU38
SB_DQ11 AV38
SB_DQ12 AP38
SB_DQ13 AR40
SB_DQ14 AW38
SB_DQ15 AY38
SB_DQ16 BA38
SB_DQ17 AV36
SB_DQ18 AR36
SB_DQ19 AP36
SB_DQ20 BA36
SB_DQ21 AU36
SB_DQ22 AP35
SB_DQ23 AP34
SB_DQ24 AY33
SB_DQ25 BA33
SB_DQ26 AT31
SB_DQ27 AU29
SB_DQ28 AU31
SB_DQ29 AW31
SB_DQ30 AV29
SB_DQ31 AW29
SB_DQ32 AM19
SB_DQ33 AL19
SB_DQ34 AP14
SB_DQ35 AN14
SB_DQ36 AN17
SB_DQ37 AM16
SB_DQ38 AP15
SB_DQ39 AL15
SB_DQ40 AJ11
SB_DQ41 AH10
SB_DQ42 AJ9
SB_DQ43 AN10
SB_DQ44 AK13
SB_DQ45 AH11
SB_DQ46 AK10
SB_DQ47 AJ8
SB_DQ48 BA10
SB_DQ49 AW10
SB_DQ50 BA4
SB_DQ51 AW4
SB_DQ52 AY10
SB_DQ53 AY9
SB_DQ54 AW5
SB_DQ55 AY5
SB_DQ56 AV4
SB_DQ57 AR5
SB_DQ58 AK4
SB_DQ59 AK3
SB_DQ60 AT4
SB_DQ61 AK5
SB_DQ62 AJ5
SB_DQ63 AJ3
SB_BS0
AT24
SB_BS1
AV23
SB_BS2
AY28
SB_CAS#
AR24
SB_RAS#
AU23
SB_WE#
AR27
SB_RCVENIN#
AK16
SB_RCVENOUT#
AK18
SB_DM0
AK36
SB_DM1
AR38
SB_DM2
AT36
SB_DM3
BA31
SB_DM4
AL17
SB_DM5
AH8
SB_DM6
BA5
SB_DM7
AN4
SB_DQS0
AM39
SB_DQS1
AT39
SB_DQS2
AU35
SB_DQS3
AR29
SB_DQS4
AR16
SB_DQS5
AR10
SB_DQS6
AR7
SB_DQS7
AN5
SB_DQS0#
AM40
SB_DQS1#
AU39
SB_DQS2#
AT35
SB_DQS3#
AP29
SB_DQS4#
AP16
SB_DQS5#
AT10
SB_DQS6#
AT7
SB_DQS7#
AP5
SB_MA0
AY23
SB_MA1
AW24
SB_MA2
AY24
SB_MA3
AR28
SB_MA4
AT27
SB_MA5
AT28
SB_MA6
AU27
SB_MA7
AV28
SB_MA8
AV27
SB_MA9
AW27
SB_MA10
AV24
SB_MA11
BA27
SB_MA12
AY27
SB_MA13
AR23
DDR SYS MEMORY A
U4D
CALISTOGA_A2_FCBGA1466
SA_DQ0 AJ35
SA_DQ1 AJ34
SA_DQ2 AM31
SA_DQ3 AM33
SA_DQ4 AJ36
SA_DQ5 AK35
SA_DQ6 AJ32
SA_DQ7 AH31
SA_DQ8 AN35
SA_DQ9 AP33
SA_DQ10 AR31
SA_DQ11 AP31
SA_DQ12 AN38
SA_DQ13 AM36
SA_DQ14 AM34
SA_DQ15 AN33
SA_DQ16 AK26
SA_DQ17 AL27
SA_DQ18 AM26
SA_DQ19 AN24
SA_DQ20 AK28
SA_DQ21 AL28
SA_DQ22 AM24
SA_DQ23 AP26
SA_DQ24 AP23
SA_DQ25 AL22
SA_DQ26 AP21
SA_DQ27 AN20
SA_DQ28 AL23
SA_DQ29 AP24
SA_DQ30 AP20
SA_DQ31 AT21
SA_DQ32 AR12
SA_DQ33 AR14
SA_DQ34 AP13
SA_DQ35 AP12
SA_DQ36 AT13
SA_DQ37 AT12
SA_DQ38 AL14
SA_DQ39 AL12
SA_DQ40 AK9
SA_DQ41 AN7
SA_DQ42 AK8
SA_DQ43 AK7
SA_DQ44 AP9
SA_DQ45 AN9
SA_DQ46 AT5
SA_DQ47 AL5
SA_DQ48 AY2
SA_DQ49 AW2
SA_DQ50 AP1
SA_DQ51 AN2
SA_DQ52 AV2
SA_DQ53 AT3
SA_DQ54 AN1
SA_DQ55 AL2
SA_DQ56 AG7
SA_DQ57 AF9
SA_DQ58 AG4
SA_DQ59 AF6
SA_DQ60 AG9
SA_DQ61 AH6
SA_DQ62 AF4
SA_DQ63 AF8
SA_BS0
AU12
SA_BS1
AV14
SA_BS2
BA20
SA_CAS#
AY13
SA_RAS#
AW14
SA_WE#
AY14
SA_RCVENIN#
AK23
SA_RCVENOUT#
AK24
SA_DM0
AJ33
SA_DM1
AM35
SA_DM2
AL26
SA_DM3
AN22
SA_DM4
AM14
SA_DM5
AL9
SA_DM6
AR3
SA_DM7
AH4
SA_DQS0
AK33
SA_DQS1
AT33
SA_DQS2
AN28
SA_DQS3
AM22
SA_DQS4
AN12
SA_DQS5
AN8
SA_DQS6
AP3
SA_DQS7
AG5
SA_DQS0#
AK32
SA_DQS1#
AU33
SA_DQS2#
AN27
SA_DQS3#
AM21
SA_DQS4#
AM12
SA_DQS5#
AL8
SA_DQS6#
AN3
SA_DQS7#
AH5
SA_MA0
AY16
SA_MA1
AU14
SA_MA2
AW16
SA_MA3
BA16
SA_MA4
BA17
SA_MA5
AU16
SA_MA6
AV17
SA_MA7
AU17
SA_MA8
AW17
SA_MA9
AT16
SA_MA10
AU13
SA_MA11
AT17
SA_MA12
AV20
SA_MA13
AV12
T9PAD
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_M_TXN6
PEG_M_TXN9
PEG_M_TXP7
PEG_M_TXP3
PEG_M_TXN5
PEG_M_TXP12
PEG_M_TXN1
PEG_M_TXN13
PEG_M_TXP5
PEG_M_TXN4
PEG_M_TXP14
PEG_M_TXP8
PEG_M_TXN0
PEG_M_TXP9
PEG_M_TXN12
PEG_M_TXN3
PEG_M_TXP6
PEG_M_TXN14
PEG_M_TXP2
PEG_M_TXN11
PEG_M_TXP1
PEG_M_TXN8
PEG_M_TXP0
PEG_M_TXN2
PEG_M_TXP15
PEG_M_TXP4
PEG_M_TXN10
PEG_M_TXN7
PEG_M_TXP10
PEG_M_TXP13
PEG_M_TXN15
PEG_M_TXP11
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXN12
PEG_TXN13
PEG_TXN10
PEG_TXN14
PEG_TXN4
PEG_TXN6
PEG_TXN1
PEG_TXN0
PEG_TXN15
PEG_TXN7
PEG_TXN8
PEG_TXN2
PEG_TXN3
PEG_TXN5
PEG_TXN9
PEG_TXN11
PEGCOMP
PEG_RXP[0..15]18
PEG_RXN[0..15]18
PEG_M_TXP[0..15]18
PEG_M_TXN[0..15]18
+1.5VS_PCIE
+VCCP
+1.5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Calistoga (3/6)
952Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
L
PEGCOMP trace width
and spacing is 18/25 mils.
C490.1U_0402_16V4Z
C510.1U_0402_16V4Z
C220.1U_0402_16V4Z
C560.1U_0402_16V4Z
C250.1U_0402_16V4Z
C480.1U_0402_16V4Z
C410.1U_0402_16V4Z
C330.1U_0402_16V4Z
C370.1U_0402_16V4Z
C530.1U_0402_16V4Z
C380.1U_0402_16V4Z
C520.1U_0402_16V4Z
R35510K_0402_5%
12
C610.1U_0402_16V4Z
C300.1U_0402_16V4Z
C540.1U_0402_16V4Z
C460.1U_0402_16V4Z
LVDS TV CRT
PCI-EXPRESS GRAPHICS
U4C
CALISTOGA_A2_FCBGA1466
SDVOCTRL_CLK
H28 SDVOCTRL_DATA
H27
LA_DATA0
B37
LA_DATA1
B34
LA_DATA2
A36
LVREFH
C33
LVREFL
C32
TVDAC_A
A16
TVDAC_B
C18
TVDAC_C
A19
TV_IREF
J20
TV_IRTNA
B16
TV_IRTNB
B18
TV_IRTNC
B19
DDCCLK
C26
DDCDATA
C25
LA_DATA#0
C37
LA_DATA#1
B35
LA_DATA#2
A37
LB_DATA0
F30
LB_DATA1
D29
LB_DATA2
F28
LB_DATA#0
G30
LB_DATA#1
D30
LB_DATA#2
F29
LA_CLK
A32
LA_CLK#
A33
LB_CLK
E26
LB_CLK#
E27
LBKLT_CTL
D32
LBKLT_EN
J30
LCTLA_CLK
H30
LCTLB_DATA
H29
LDDC_CLK
G26
LDDC_DATA
G25
LVDD_EN
F32
LIBG
B38
LVBG
C35
VSYNC
H23
HSYNC
G23
BLUE
E23
BLUE#
D23
GREEN
C22
GREEN#
B22
RED
A21
RED#
B21
CRT_IREF
J22
EXP_COMPI D40
EXP_COMPO D38
EXP_RXN0 F34
EXP_RXN1 G38
EXP_RXN2 H34
EXP_RXN3 J38
EXP_RXN4 L34
EXP_RXN5 M38
EXP_RXN6 N34
EXP_RXN7 P38
EXP_RXN8 R34
EXP_RXN9 T38
EXP_RXN10 V34
EXP_RXN11 W38
EXP_RXN12 Y34
EXP_RXN13 AA38
EXP_RXN14 AB34
EXP_RXN15 AC38
EXP_RXP0 D34
EXP_RXP1 F38
EXP_RXP2 G34
EXP_RXP3 H38
EXP_RXP4 J34
EXP_RXP5 L38
EXP_RXP6 M34
EXP_RXP7 N38
EXP_RXP8 P34
EXP_RXP9 R38
EXP_RXP10 T34
EXP_RXP11 V38
EXP_RXP12 W34
EXP_RXP13 Y38
EXP_RXP14 AA34
EXP_RXP15 AB38
EXP_TXN0 F36
EXP_TXN1 G40
EXP_TXN2 H36
EXP_TXN3 J40
EXP_TXN4 L36
EXP_TXN5 M40
EXP_TXN6 N36
EXP_TXN7 P40
EXP_TXN8 R36
EXP_TXN9 T40
EXP_TXN10 V36
EXP_TXN11 W40
EXP_TXN12 Y36
EXP_TXN13 AA40
EXP_TXN14 AB36
EXP_TXN15 AC40
EXP_TXP0 D36
EXP_TXP1 F40
EXP_TXP2 G36
EXP_TXP3 H40
EXP_TXP4 J36
EXP_TXP5 L40
EXP_TXP6 M36
EXP_TXP7 N40
EXP_TXP8 P36
EXP_TXP9 R40
EXP_TXP10 T36
EXP_TXP11 V40
EXP_TXP12 W36
EXP_TXP13 Y40
EXP_TXP14 AA36
EXP_TXP15 AB40
TV_DCONSEL1
J29
TV_DCONSEL0
K30
C240.1U_0402_16V4Z
C230.1U_0402_16V4Z
C280.1U_0402_16V4Z
C580.1U_0402_16V4Z
C500.1U_0402_16V4Z
C260.1U_0402_16V4Z
C570.1U_0402_16V4Z
C320.1U_0402_16V4Z
C450.1U_0402_16V4Z
C340.1U_0402_16V4Z
C200.1U_0402_16V4Z
C470.1U_0402_16V4Z
R36310K_0402_5%
12
C350.1U_0402_16V4Z
C600.1U_0402_16V4Z
R331
24.9_0402_1%
1 2
C310.1U_0402_16V4Z
C430.1U_0402_16V4Z
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
MCH_D2
MCH_A6
MCH_AB1
MCH_CRTDAC
+1.5VS
+1.5VS_PCIE
+1.5VS
+1.5VS+1.5VS_3GPLL
+1.5VS_HPLL
+3VS
+1.5VS
+1.5VS_MPLL
+1.5VS
+1.5VS
+1.5VS_3GPLL
+1.5VS
+VCCP
+1.5VS_MPLL +1.5VS_HPLL
+1.5VS+1.5VS
+2.5VS
+2.5VS
+VCCP
+2.5VS
+1.5VS_TVDAC
+1.5VS_TVDAC +1.5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Calistoga (4/6)
1052Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
W=40 mils
45mA Max.45mA Max.
close pin G41
PCI-E/MEM/PSB PLL decoupling
9/15
C322
0.1U_0402_16V4Z
1
2
C387
0.1U_0402_16V4Z@
1
2
C315
10U_0805_6.3V6M
1
2
C319
0.022U_0402_16V7K@
1
2
C339
4.7U_0805_10V4Z
1
2
C62
10U_0805_6.3V6M
1
2
R398
0.5_0805_1%
1 2
C377
0.1U_0402_16V4Z
1
2
C336
0.22U_0603_10V7K
1
2
C324
0.022U_0402_16V7K@
1
2
C373
0.1U_0402_16V4Z
1
2
J4
PAD-No SHORT 2x2m
2 1
C317
0.47U_0603_10V7K
1
2
R22
0_0805_5%
12
C371
0.1U_0402_16V4Z
1
2
C320
10U_0805_6.3V6M
1
2
C378
10U_0805_6.3V6M
1
2
C380
10U_0805_6.3V6M
1
2
C316
10U_0805_6.3V6M@
1
2
+
C297
220U_D2_4VM_R25
1
2
P O W E R
U4H
CALISTOGA_A2_FCBGA1466
VCC_SYNC H22
VCCTX_LVDS0 B30
VCCTX_LVDS1 C30
VCC3G0 AB41
VCC3G1 AJ41
VCC3G2 L41
VCC3G3 N41
VCC3G4 R41
VCC3G5 V41
VCC3G6 Y41
VCCA_3GBG G41
VSSA_3GBG H41
VCCA_3GPLL AC33
VCCTX_LVDS2 A30
VCCA_LVDS A38
VSSA_LVDS B39
VCCA_MPLL AF2
VCCA_TVBG H20
VSSA_TVBG G20
VCCA_TVDACA0 E19
VCCA_TVDACA1 F19
VCCA_TVDACB0 C20
VCCA_TVDACB1 D20
VCCA_TVDACC0 E20
VCCA_TVDACC1 F20
VCCAUX1 AF31
VCCAUX2 AE31
VCCAUX3 AC31
VCCAUX4 AL30
VCCAUX5 AK30
VCCAUX6 AJ30
VCCAUX7 AH30
VCCAUX8 AG30
VCCAUX9 AF30
VCCAUX10 AE30
VCCAUX11 AD30
VCCAUX12 AC30
VCCAUX13 AG29
VCCAUX14 AF29
VCCAUX15 AE29
VCCAUX16 AD29
VCCAUX17 AC29
VCCAUX18 AG28
VCCAUX19 AF28
VCCAUX20 AE28
VTT0
AC14
VTT1
AB14
VTT2
W14
VTT3
V14
VTT4
T14
VTT5
R14
VTT6
P14
VTT7
N14
VTT8
M14
VTT9
L14
VTT10
AD13
VTT11
AC13
VTT12
AB13
VTT13
AA13
VTT14
Y13
VTT15
W13
VTT16
V13
VTT17
U13
VTT18
T13
VTT19
R13
VTT20
N13
VTT21
M13
VTT22
L13
VTT23
AB12
VTT24
AA12
VTT25
Y12
VTT26
W12
VTT27
V12
VTT28
U12
VTT29
T12
VTT30
R12
VTT31
P12
VTT32
N12
VTT33
M12
VTT34
L12
VTT35
R11
VTT36
P11
VTT37
N11
VTT38
M11
VTT39
R10
VTT40
P10
VTT41
N10
VTT42
M10
VTT43
P9
VTT44
N9
VTT45
M9
VTT46
R8
VTT47
P8
VTT48
N8
VTT49
M8
VTT50
P7
VTT51
N7
VTT52
M7
VTT53
R6
VTT54
P6
VTT55
M6
VTT56
A6
VTT57
R5
VTT59
N5
VTT60
M5
VTT61
P4
VTT62
N4
VTT63
M4
VTT64
R3
VTT65
P3
VTT66
N3
VTT67
M3
VTT68
R2
VTT69
P2
VTT70
M2
VTT71
D2
VTT72
AB1
VTT73
R1
VTT74
P1
VTT75
N1
VTT76
M1
VCCA_CRTDAC0 E21
VCCA_CRTDAC1 F21
VSSA_CRTDAC2 G21
VCCA_DPLLA B26
VCCA_DPLLB C39
VCCA_HPLL AF1
VCCD_HMPLL0 AH1
VCCD_HMPLL1 AH2
VCCD_LVDS0 A28
VCCD_LVDS1 B28
VCCD_LVDS2 C28
VCCD_TVDAC D21
VCCDQ_TVDAC H19
VCCHV0 A23
VCCHV1 B23
VCCHV2 B25
VCCAUX21 AH22
VCCAUX22 AJ21
VCCAUX23 AH21
VCCAUX24 AJ20
VCCAUX25 AH20
VCCAUX26 AH19
VCCAUX27 P19
VCCAUX28 P16
VCCAUX29 AH15
VCCAUX30 P15
VCCAUX31 AH14
VCCAUX32
AG14
VCCAUX33
AF14
VCCAUX34
AE14
VCCAUX35
Y14
VCCAUX36
AF13
VCCAUX37
AE13
VCCAUX38
AF12
VCCAUX39
AE12
VCCAUX40
AD12
VCCAUX0 AK31
VTT58
P5
R356
0_0805_5%
1 2
R333
0_0805_5% @
1 2
C318
0.22U_0603_10V7K
1
2
C368
2.2U_0805_16V4Z
1
2
C374
0.1U_0402_16V4Z
1
2
J5
PAD-SHORT 2x2m
2 1
C329
0.1U_0402_16V4Z
1
2
+
C42
220U_D2_2VK_R9
1
2
C59
10U_0805_6.3V6M
1
2
R396
0_0805_5%
12
C55
0.47U_0603_10V7K
1
2
R23
0_0805_5%
12
R332
0_0805_5%
12
R410
0_0805_5%
12
5 4 3 2
2
1
1
DD
CC
BB
AA
VCCSM_LF1
VCCSM_LF2
VCCSM_LF5
VCCSM_LF4
CFG187
CFG137
CFG197
CFG167
CFG97
CFG207
CFG117
CFG127
CFG57
CFG77
+VCCP
+1.5VS
+VCCP
+1.8V
+VCCP
+1.8V
+3VS
+1.8V
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Calistoga (5/6)
1152Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place near pin BA15
Place near pin BA23
Place near pin AT41 & AM41
Place near pin AV1 & AJ1
CFG[13:12]
1 = PCIE/SDVO are operating
simu.
CFG7
CFG19
(Default)
CFG20
0 = DMI x 2
CFG18
CFG[19:18] have internal pull down
*
Strap Pin Table
*
10 = All Z Mode Enabled
0 = Reserved
(Default)
1 = Normal Operation
CFG5
SDVO_CTRLDATA
*
1 = DMI Lane Reversal Enable
(Default)
*
1 = Dynamic ODT Enabled(Default)
*
(Default)
00 = Reserved
1 = 1.5V
*
*
1 = DMI x 4
CFG[3:17] have internal pull up
0 = No SDVO Device Present
(Default)
*
*
(Default)
(Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO is
operational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
01 = XOR Mode Enabled
001 = 533MT/s FSB
CFG16
0 = 1.05V
011 = 667MT/s FSB
0 = Lane Reversal Enable
CFG9
1 = SDVO Device Present
CFG[2:0]
1 = Mobile Yonah CPU
11 = Normal Operation
CFG11
1 = Calistoga
0 = Reserved
*
(According to Intel Napa Schematic Checklist & CRB
Rev1.502 document 2.2Kohm pull-down resistor no request)
L
@wait DB-1 test verify
C343
1U_0603_10V4Z
1
2P O W E R
U4G
CALISTOGA_A2_FCBGA1466
VCC0
AA33
VCC1
W33
VCC2
P33
VCC3
N33
VCC4
L33
VCC5
J33
VCC6
AA32
VCC7
Y32
VCC8
W32
VCC9
V32
VCC10
P32
VCC11
N32
VCC12
M32
VCC13
L32
VCC14
J32
VCC15
AA31
VCC16
W31
VCC17
V31
VCC18
T31
VCC19
R31
VCC20
P31
VCC21
N31
VCC22
M31
VCC23
AA30
VCC24
Y30
VCC25
W30
VCC26
V30
VCC27
U30
VCC28
T30
VCC29
R30
VCC30
P30
VCC31
N30
VCC32
M30
VCC33
L30
VCC34
AA29
VCC35
Y29
VCC36
W29
VCC37
V29
VCC38
U29
VCC39
R29
VCC40
P29
VCC41
M29
VCC42
L29
VCC43
AB28
VCC44
AA28
VCC45
Y28
VCC_SM5 AY34
VCC_SM6 AW34
VCC_SM7 AV34
VCC_SM8 AU34
VCC_SM9 AT34
VCC_SM10 AR34
VCC_SM11 BA30
VCC_SM12 AY30
VCC_SM13 AW30
VCC_SM14 AV30
VCC_SM15 AU30
VCC_SM16 AT30
VCC_SM17 AR30
VCC_SM18 AP30
VCC_SM19 AN30
VCC_SM20 AM30
VCC_SM21 AM29
VCC_SM22 AL29
VCC_SM23 AK29
VCC_SM24 AJ29
VCC_SM25 AH29
VCC_SM26 AJ28
VCC_SM27 AH28
VCC_SM28 AJ27
VCC_SM29 AH27
VCC_SM30 BA26
VCC_SM31 AY26
VCC_SM32 AW26
VCC_SM33 AV26
VCC_SM34 AU26
VCC_SM35 AT26
VCC_SM36 AR26
VCC_SM37 AJ26
VCC_SM38 AH26
VCC_SM39 AJ25
VCC_SM40 AH25
VCC_SM41 AJ24
VCC_SM42 AH24
VCC_SM43 BA23
VCC_SM44 AJ23
VCC_SM45 BA22
VCC_SM46 AY22
VCC_SM47 AW22
VCC_SM48 AV22
VCC_SM49 AU22
VCC_SM50 AT22
VCC_SM51 AR22
VCC_SM52 AP22
VCC_SM53 AK22
VCC_SM54 AJ22
VCC_SM55 AK21
VCC_SM56 AK20
VCC_SM57 BA19
VCC_SM58 AY19
VCC_SM59 AW19
VCC_SM60 AV19
VCC_SM61 AU19
VCC_SM62 AT19
VCC_SM63 AR19
VCC_SM64 AP19
VCC_SM65 AK19
VCC_SM66 AJ19
VCC_SM67 AJ18
VCC_SM68 AJ17
VCC_SM69 AH17
VCC_SM70 AJ16
VCC_SM71 AH16
VCC_SM72 BA15
VCC_SM3 AU40
VCC_SM4 BA34
VCC_SM73 AY15
VCC_SM74 AW15
VCC_SM75 AV15
VCC_SM76 AU15
VCC_SM77 AT15
VCC_SM78 AR15
VCC_SM79 AJ15
VCC_SM80 AJ14
VCC_SM81 AJ13
VCC_SM82 AH13
VCC_SM83 AK12
VCC_SM84 AJ12
VCC_SM85 AH12
VCC_SM86 AG12
VCC_SM87 AK11
VCC_SM88 BA8
VCC_SM89 AY8
VCC_SM90 AW8
VCC_SM91 AV8
VCC_SM92 AT8
VCC_SM93 AR8
VCC_SM94 AP8
VCC_SM95 BA6
VCC_SM96 AY6
VCC_SM97 AW6
VCC_SM98 AV6
VCC_SM99 AT6
VCC_SM1 AT41
VCC_SM0 AU41
VCC_SM2 AM41
VCC46
V28
VCC47
U28
VCC48
T28
VCC49
R28
VCC50
P28
VCC51
N28
VCC52
M28
VCC53
L28
VCC54
P27
VCC55
N27
VCC56
M27
VCC57
L27
VCC58
P26
VCC59
N26
VCC60
L26
VCC61
N25
VCC62
M25
VCC63
L25
VCC64
P24
VCC65
N24
VCC66
M24
VCC67
AB23
VCC68
AA23
VCC69
Y23
VCC70
P23
VCC71
N23
VCC72
M23
VCC73
L23
VCC74
AC22
VCC75
AB22
VCC76
Y22
VCC77
W22
VCC78
P22
VCC79
N22
VCC80
M22
VCC81
L22
VCC82
AC21
VCC83
AA21
VCC84
W21
VCC85
N21
VCC86
M21
VCC87
L21
VCC88
AC20
VCC89
AB20
VCC90
Y20
VCC91
W20
VCC92
P20
VCC93
N20
VCC94
M20
VCC95
L20
VCC96
AB19
VCC97
AA19
VCC98
Y19
VCC99
N19
C381
0.1U_0402_16V4Z
1
2
C337
10U_0805_6.3V6M
1
2
C333
0.22U_0603_10V7K
1
2
R3712.2K_0402_5%@
1 2
+
C402
220U_D2_4VM@
1
2
C389
0.47U_0603_10V7K
1
2
R3691K_0402_5%@
1 2
+
C64
220U_D2_2VK_R9
1
2
C338
10U_0805_6.3V6M
1
2
C367
0.22U_0603_10V7K
1
2
C382
0.1U_0402_16V4Z
1
2
+
C386
330U_D2E_2.5VM_R9@
1
2
R3652.2K_0402_5%@
1 2
C404
0.47U_0603_10V7K
1
2
R3681K_0402_5%@
1 2
C388
0.1U_0402_16V4Z
1
2
R3542.2K_0402_5%@
1 2
R3592.2K_0402_5%@
1 2
C406
0.47U_0603_10V7K
1
2
C398
0.47U_0603_10V7K
1
2
R3492.2K_0402_5%@
1 2
P O W E R
U4F
CALISTOGA_A2_FCBGA1466
VCC_NCTF1
AC27
VCC_NCTF2
AB27
VCC_NCTF3
AA27
VCC_NCTF4
Y27
VCC_NCTF5
W27
VCC_NCTF6
V27
VCC_NCTF7
U27
VCCAUX_NCTF52 Y15
VCC_NCTF9
R27
VCC_NCTF10
AD26
VCC_NCTF11
AC26
VCC_NCTF12
AB26
VCC_NCTF13
AA26
VCC_NCTF14
Y26
VCC_NCTF15
W26
VCC_NCTF16
V26
VCC_NCTF17
U26
VCC_NCTF18
T26
VCC_NCTF19
R26
VCC_NCTF20
AD25
VCC_NCTF21
AC25
VCC_NCTF22
AB25
VCC_NCTF23
AA25
VCC_NCTF24
Y25
VCC_NCTF25
W25
VCCAUX_NCTF53 W15
VCC_NCTF27
U25
VCC_NCTF28
T25
VCC_NCTF29
R25
VCC_NCTF30
AD24
VCC_NCTF31
AC24
VCC_NCTF32
AB24
VCC_NCTF33
AA24
VCC_NCTF34
Y24
VCC_NCTF35
W24
VCC_NCTF36
V24
VCCAUX_NCTF54 V15
VCC_NCTF38
T24
VCC_NCTF39
R24
VCC_NCTF40
AD23
VCC_NCTF41
V23
VCC_NCTF42
U23
VCC_NCTF43
T23
VCC_NCTF44
R23
VCC_NCTF45
AD22
VCC_NCTF46
V22
VCC_NCTF47
U22
VCC_NCTF48
T22
VCC_NCTF49
R22
VCC_NCTF50
AD21
VCC_NCTF51
V21
VCC_NCTF52
U21
VCC_NCTF53
T21
VCC_NCTF54
R21
VCC_NCTF55
AD20
VCC_NCTF56
V20
VCC_NCTF57
U20
VCC_NCTF58
T20
VCCAUX_NCTF55 U15
VCC_NCTF60
AD19
VCC_NCTF61
V19
VCC_NCTF62
U19
VCC_NCTF63
T19
VCC_NCTF64
AD18
VCC_NCTF65
AC18
VCC_NCTF66
AB18
VCC_NCTF67
AA18
VCC_NCTF68
Y18
VCC_NCTF69
W18
VCC_NCTF70
V18
VCC_NCTF71
U18
VCC_NCTF72
T18
VCC_NCTF0
AD27 VCCAUX_NCTF0 AG27
VCCAUX_NCTF1 AF27
VCCAUX_NCTF2 AG26
VCCAUX_NCTF3 AF26
VCCAUX_NCTF4 AG25
VCCAUX_NCTF5 AF25
VCCAUX_NCTF6 AG24
VCCAUX_NCTF7 AF24
VCCAUX_NCTF8 AG23
VCCAUX_NCTF9 AF23
VCCAUX_NCTF10 AG22
VCCAUX_NCTF11 AF22
VCCAUX_NCTF12 AG21
VCCAUX_NCTF13 AF21
VCCAUX_NCTF14 AG20
VCCAUX_NCTF15 AF20
VCCAUX_NCTF16 AG19
VCCAUX_NCTF17 AF19
VCCAUX_NCTF18 R19
VCCAUX_NCTF19 AG18
VCCAUX_NCTF20 AF18
VCCAUX_NCTF21 R18
VCCAUX_NCTF22 AG17
VCCAUX_NCTF23 AF17
VCCAUX_NCTF24 AE17
VCCAUX_NCTF25 AD17
VCCAUX_NCTF26 AB17
VCCAUX_NCTF27 AA17
VCCAUX_NCTF28 W17
VCCAUX_NCTF29 V17
VCCAUX_NCTF30 T17
VCCAUX_NCTF31 R17
VCCAUX_NCTF32 AG16
VCCAUX_NCTF33 AF16
VCCAUX_NCTF34 AE16
VCCAUX_NCTF35 AD16
VCCAUX_NCTF36 AC16
VCCAUX_NCTF37 AB16
VCCAUX_NCTF38 AA16
VCCAUX_NCTF39 Y16
VCCAUX_NCTF40 W16
VCCAUX_NCTF41 V16
VCCAUX_NCTF42 U16
VCCAUX_NCTF43 T16
VCCAUX_NCTF44 R16
VCCAUX_NCTF45 AG15
VCCAUX_NCTF46 AF15
VCCAUX_NCTF47 AE15
VCCAUX_NCTF48 AD15
VCCAUX_NCTF49 AC15
VCCAUX_NCTF50 AB15
VSS_NCTF0 AE27
VCCAUX_NCTF51 AA15
VSS_NCTF1 AE26
VCC_NCTF59
R20
VCCAUX_NCTF56 T15
VSS_NCTF2 AE25
VSS_NCTF3 AE24
VSS_NCTF4 AE23
VSS_NCTF5 AE22
VSS_NCTF6 AE21
VSS_NCTF7 AE20
VSS_NCTF8 AE19
VSS_NCTF9 AE18
VSS_NCTF10 AC17
VSS_NCTF11 Y17
VSS_NCTF12 U17
VCC_NCTF26
V25
VCCAUX_NCTF57 R15
VCC_NCTF37
U24
VCC_NCTF8
T27
VCC100
M19
VCC101
L19
VCC102
N18
VCC103
M18
VCC104
L18
VCC105
P17
VCC106
N17
VCC107
M17
VCC108
N16
VCC109
M16
VCC110
L16
VCC_SM100 AR6
VCC_SM101 AP6
VCC_SM102 AN6
VCC_SM103 AL6
VCC_SM104 AK6
VCC_SM105 AJ6
VCC_SM106 AV1
VCC_SM107 AJ1
R3701K_0402_5%@
1 2
C390
0.47U_0603_10V7K
1
2
C395
0.47U_0603_10V7K
1
2
C405
10U_0805_6.3V6M
1
2
C375
0.22U_0603_10V7K
1
2
C407
10U_0805_6.3V6M
1
2
R3402.2K_0402_5%@
1 2
C384
0.1U_0402_16V4Z
1
2
R3412.2K_0402_5%@
1 2
5 4 3 2
2
1
1
DD
CC
BB
AA
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Calistoga (6/6)
1252Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
P O W E R
U4J
CALISTOGA_A2_FCBGA1466
VSS200
AN21
VSS201
AL21
VSS202
AB21
VSS203
Y21
VSS204
P21
VSS205
K21
VSS206
J21
VSS207
H21
VSS208
C21
VSS209
AW20
VSS210
AR20
VSS211
AM20
VSS212
AA20
VSS213
K20
VSS214
B20
VSS215
A20
VSS216
AN19
VSS217
AC19
VSS218
W19
VSS219
K19
VSS220
G19
VSS221
C19
VSS222
AH18
VSS223
P18
VSS224
H18
VSS225
D18
VSS226
A18
VSS227
AY17
VSS228
AR17
VSS229
AP17
VSS230
AM17
VSS231
AK17
VSS232
AV16
VSS233
AN16
VSS234
AL16
VSS235
J16
VSS236
F16
VSS237
C16
VSS238
AN15
VSS239
AM15
VSS240
AK15
VSS241
N15
VSS242
M15
VSS243
L15
VSS244
B15
VSS245
A15
VSS246
BA14
VSS247
AT14
VSS248
AK14
VSS249
AD14
VSS250
AA14
VSS251
U14
VSS252
K14
VSS253
H14
VSS254
E14
VSS255
AV13
VSS256
AR13
VSS257
AN13
VSS258
AM13
VSS259
AL13
VSS260
AG13
VSS261
P13
VSS262
F13
VSS266
AC12
VSS267
K12
VSS268
H12
VSS269
E12
VSS270
AD11
VSS271
AA11
VSS272
Y11
VSS273
J11
VSS274
D11
VSS275
B11
VSS276
AV10
VSS277
AP10
VSS278
AL10
VSS279
AJ10
VSS265
D13
VSS264
B13
VSS263
AY12
VSS285 AW9
VSS286 AR9
VSS287 AH9
VSS288 AB9
VSS289 Y9
VSS290 R9
VSS292 G9
VSS291 E9
VSS293 A9
VSS294 AG8
VSS295 AD8
VSS296 AA8
VSS297 U8
VSS298 K8
VSS299 C8
VSS300 BA7
VSS301 AV7
VSS302 AP7
VSS303 AL7
VSS304 AJ7
VSS305 AH7
VSS306 AF7
VSS307 AC7
VSS308 R7
VSS309 G7
VSS310 D7
VSS311 AG6
VSS312 AD6
VSS313 AB6
VSS314 Y6
VSS317 K6
VSS318 H6
VSS319 B6
VSS320 AV5
VSS321 AF5
VSS322 AD5
VSS323 AY4
VSS324 AR4
VSS325 AP4
VSS326 AL4
VSS327 AJ4
VSS328 Y4
VSS329 U4
VSS330 R4
VSS331 J4
VSS332 F4
VSS333 C4
VSS334 AY3
VSS335 AW3
VSS336 AV3
VSS337 AL3
VSS341 AD3
VSS345 AT2
VSS346 AR2
VSS347 AP2
VSS348 AK2
VSS351 AB2
VSS352 Y2
VSS353 U2
VSS354 T2
VSS355 N2
VSS356 J2
VSS357 H2
VSS359 C2
VSS360 AL1
VSS358 F2
VSS349 AJ2
VSS350 AD2
VSS344 G3
VSS343 AA3
VSS342 AC3
VSS340 AF3
VSS338 AH3
VSS280 AG10
VSS281 AC10
VSS282 W10
VSS283 U10
VSS284 BA9
VSS315 U6
VSS316 N6
VSS339 AG3
P O W E R
U4I
CALISTOGA_A2_FCBGA1466
VSS0
AC41
VSS1
AA41
VSS2
W41
VSS3
T41
VSS4
P41
VSS5
M41
VSS6
J41
VSS7
F41
VSS8
AV40
VSS9
AP40
VSS10
AN40
VSS11
AK40
VSS13
AH40
VSS14
AG40
VSS15
AF40
VSS16
AE40
VSS17
B40
VSS18
AY39
VSS19
AW39
VSS21
AR39
VSS22
AN39
VSS24
AC39
VSS25
AB39
VSS26
AA39
VSS27
Y39
VSS28
W39
VSS29
V39
VSS30
T39
VSS31
R39
VSS32
P39
VSS33
N39
VSS34
M39
VSS35
L39
VSS36
J39
VSS37
H39
VSS20
AV39
VSS23
AJ39
VSS12
AJ40
VSS38
G39
VSS40
D39
VSS41
AT38
VSS42
AM38
VSS43
AH38
VSS44
AG38
VSS45
AF38
VSS46
AE38
VSS47
C38
VSS48
AK37
VSS49
AH37
VSS50
AB37
VSS51
AA37
VSS52
Y37
VSS53
W37
VSS54
V37
VSS55
T37
VSS56
R37
VSS57
P37
VSS58
N37
VSS59
M37
VSS60
L37
VSS61
J37
VSS62
H37
VSS63
G37
VSS64
F37
VSS65
D37
VSS66
AY36
VSS67
AW36
VSS68
AN36
VSS69
AH36
VSS70
AG36
VSS71
AF36
VSS72
AE36
VSS73
AC36
VSS74
C36
VSS75
B36
VSS76
BA35
VSS77
AV35
VSS78
AR35
VSS79
AH35
VSS80
AB35
VSS81
AA35
VSS82
Y35
VSS83
W35
VSS84
V35
VSS85
T35
VSS86
R35
VSS87
P35
VSS88
N35
VSS89
M35
VSS90
L35
VSS91
J35
VSS92
H35
VSS93
G35
VSS94
F35
VSS95
D35
VSS96
AN34
VSS97
AK34
VSS98
AG34
VSS99
AF34
VSS39
F39
VSS100 AE34
VSS101 AC34
VSS102 C34
VSS103 AW33
VSS104 AV33
VSS105 AR33
VSS106 AE33
VSS107 AB33
VSS108 Y33
VSS109 V33
VSS110 T33
VSS111 R33
VSS112 M33
VSS113 H33
VSS114 G33
VSS115 F33
VSS116 D33
VSS117 B33
VSS118 AH32
VSS119 AG32
VSS120 AF32
VSS121 AE32
VSS122 AC32
VSS123 AB32
VSS124 G32
VSS125 B32
VSS126 AY31
VSS127 AV31
VSS128 AN31
VSS129 AJ31
VSS130 AG31
VSS131 AB31
VSS132 Y31
VSS133 AB30
VSS134 E30
VSS135 AT29
VSS136 AN29
VSS137 AB29
VSS138 T29
VSS139 N29
VSS140 K29
VSS141 G29
VSS142 E29
VSS143 C29
VSS144 B29
VSS145 A29
VSS146 BA28
VSS147 AW28
VSS148 AU28
VSS149 AP28
VSS150 AM28
VSS151 AD28
VSS152 AC28
VSS153 W28
VSS154 J28
VSS155 E28
VSS156 AP27
VSS157 AM27
VSS158 AK27
VSS159 J27
VSS160 G27
VSS161 F27
VSS162 C27
VSS163 B27
VSS164 AN26
VSS165 M26
VSS166 K26
VSS167 F26
VSS168 D26
VSS169 AK25
VSS170 P25
VSS171 K25
VSS172 H25
VSS173 E25
VSS174 D25
VSS175 A25
VSS176 BA24
VSS177 AU24
VSS178 AL24
VSS179 AW23
VSS180 AT23
VSS181 AN23
VSS182 AM23
VSS183 AH23
VSS184 AC23
VSS185 W23
VSS186 K23
VSS187 J23
VSS188 F23
VSS189 C23
VSS190 AA22
VSS191 K22
VSS192 G22
VSS193 F22
VSS194 E22
VSS195 D22
VSS196 A22
VSS197 BA21
VSS198 AV21
VSS199 AR21
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
DDR_A_MA11
V_DDR_MCH_REF
DDR_CKE1_DIMMA
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
ICH_SMBCLK
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7
DDR_A_MA12
DDR_A_MA5
DDR_A_WE#
DDR_A_D8
DDR_A_D3
DDR_A_D2
DDR_A_D17
DDR_A_D21
DDR_A_D30
DDR_A_D27
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DM3
DDR_A_DM1
DDR_A_DM2
DDR_A_DM0
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
ICH_SMBDATA
DDR_CKE0_DIMMA
DDR_A_MA8
DDR_CS1_DIMMA#
DDR_A_MA11
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_CAS#
DDR_A_BS#1
DDR_A_RAS#
DDR_A_D15
DDR_A_D20
DDR_A_D9
DDR_A_D16
DDR_A_D28
DDR_A_D26
DDR_A_D31
DDR_A_D33
DDR_A_D36
DDR_A_D37
DDR_A_D29
DDR_A_D32
DDR_A_D49
DDR_A_D48
DDR_A_D54
DDR_A_DM6
DDR_A_DM4
DDR_A_DM5
DDR_A_DM7
DDR_A_MA13
DDR_A_DQS5
DDR_A_BS#0
DDR_A_BS#2
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA4
DDR_A_BS#2
DDR_A_BS#1
DDR_A_MA6
DDR_A_MA9
DDR_CKE0_DIMMA
DDR_A_MA2
DDR_A_MA12
DDR_A_MA5
DDR_A_MA1
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS#0
DDR_A_MA8
DDR_A_MA3
DDR_A_MA10
DDR_CS0_DIMMA#
M_ODT1
DDR_CS1_DIMMA#
M_ODT1
DDR_A_WE#
M_ODT0
DDR_A_MA13
DDR_A_MA7
M_ODT0
DDR_A_D59
DDR_A_D58
DDR_A_D63
DDR_A_D62
DDR_A_D60
DDR_A_D57
DDR_A_D56
DDR_A_D61
DDR_A_D50DDR_A_D51
DDR_A_D55
DDR_A_D52
DDR_A_D53
DDR_A_D42
DDR_A_D43 DDR_A_D47
DDR_A_D46
DDR_A_D41
DDR_A_D45 DDR_A_D40
DDR_A_D44
DDR_A_D39
DDR_A_D35
DDR_A_D34
DDR_A_D38
DDR_A_D25
DDR_A_D24
DDR_A_D22
DDR_A_D19 DDR_A_D23
DDR_A_D18
DDR_A_D13
DDR_A_D12
DDR_A_D0
DDR_A_D4
DDR_A_D14
DDR_A_D7
DDR_A_D1
DDR_A_D5
DDR_A_D6
DDR_A_D11
DDR_A_D10
DDR_THERM#
DDR_A_DQS#[0..7]8
DDR_A_DQS[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8
DDR_A_MA[0..13]8
DDR_CKE0_DIMMA7
DDR_A_BS#28
DDR_A_BS#08 DDR_A_WE#8
DDR_A_CAS#8
M_ODT17
DDR_CS1_DIMMA#7
M_CLK_DDR07
M_CLK_DDR#07
DDR_CKE1_DIMMA7
DDR_A_BS#18
DDR_A_RAS#8
DDR_CS0_DIMMA#7
M_CLK_DDR#17
M_ODT07
V_DDR_MCH_REF7,14,44
ICH_SMBDATA4,14,15,18,21,25,27 ICH_SMBCLK4,14,15,18,21,25,27
M_CLK_DDR17
DDR_THERM#7,14
+1.8V
+0.9V
+3VS
+1.8V
+1.8V
+0.9V
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
DDRII-SODIMM SLOT1
1352Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"
Layout Note:
Place near JP34
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
REVERSE
SO-DIMM A
Top side
C91
0.1U_0402_16V4Z
1
2
C84
0.1U_0402_16V4Z
1
2
C97
2.2U_0805_16V4Z
1
2
RP1756_0404_4P2R_5%
14 23
C111
0.1U_0402_16V4Z
1
2
RP1656_0404_4P2R_5%
14 23
C110
0.1U_0402_16V4Z
1
2
RP1956_0404_4P2R_5%
14 23
RP9
56_0404_4P2R_5%
1 4
2 3
RP1356_0404_4P2R_5%
14 23
C462
2.2U_0805_16V4Z
1
2
C463
2.2U_0805_16V4Z
1
2
RP7
56_0404_4P2R_5%
1 4
2 3
C83
0.1U_0402_16V4Z
1
2
C115
0.1U_0402_16V4Z
1
2
C92
0.1U_0402_16V4Z
1
2
C95
0.1U_0402_16V4Z
1
2
C82
0.1U_0402_16V4Z
1
2
C467
2.2U_0805_16V4Z
1
2
RP15
56_0404_4P2R_5%
1 4
2 3
C96
0.1U_0402_16V4Z
1
2
C105
0.1U_0402_16V4Z
1
2
RP1456_0404_4P2R_5%
14 23
RP10
56_0404_4P2R_5%
1 4
2 3
R40
10K_0402_5%
12
C464
2.2U_0805_16V4Z
1
2
JP9
FOX_ASOA426-M4R-TR
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
RP11
56_0404_4P2R_5%
1 4
2 3
C93
0.1U_0402_16V4Z
1
2
C113
0.1U_0402_16V4Z
1
2
RP8
56_0404_4P2R_5%
1 4
2 3
R38
10K_0402_5%
12
RP1256_0404_4P2R_5%
14 23
C461
2.2U_0805_16V4Z
1
2
RP1856_0404_4P2R_5%
14 23
C78
0.1U_0402_16V4Z
1
2
C81
0.1U_0402_16V4Z
1
2
C80
0.1U_0402_16V4Z
1
2
C114
0.1U_0402_16V4Z
1
2
C112
0.1U_0402_16V4Z
1
2
C79
0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
DDR_B_MA1
DDR_B_BS#0
DDR_B_CAS#
DDR_B_MA0
DDR_B_RAS#
DDR_B_MA3
DDR_B_MA10
DDR_B_BS#2
DDR_CS2_DIMMB#
DDR_B_BS#1
DDR_CKE2_DIMMB
DDR_B_MA4
DDR_B_MA9
DDR_B_MA2
DDR_B_MA5
DDR_B_MA12
DDR_B_MA8
M_ODT3
DDR_CS3_DIMMB# M_ODT2
DDR_B_MA13
DDR_B_WE#
DDR_B_DQS#4
DDR_B_D14
DDR_B_DQS4
DDR_B_BS#2
DDR_B_D57
DDR_B_MA2
DDR_CKE2_DIMMB
DDR_B_D8
DDR_B_D1
DDR_B_DM3
ICH_SMBDATA
DDR_B_D52
DDR_B_D45
DDR_B_MA3
DDR_B_D37
DDR_B_D59
DDR_B_D40
DDR_B_D6
DDR_B_MA7
DDR_B_D13
DDR_B_D5
DDR_B_D61
DDR_B_DQS#0
DDR_CS3_DIMMB#
M_ODT3
DDR_B_MA11
DDR_B_D46
DDR_B_WE#
DDR_B_D2
DDR_B_D11
DDR_B_MA10
DDR_B_D55
DDR_B_D35
DDR_B_D41
DDR_B_DQS5
M_ODT2
DDR_B_DQS2
DDR_B_DQS#7
DDR_B_MA6
DDR_B_D9
DDR_B_D44
DDR_B_D63
DDR_B_DM7
DDR_B_BS#0
DDR_B_MA5
DDR_B_D56
DDR_B_D4
DDR_B_DQS#3
DDR_B_D10
DDR_B_D12
DDR_B_D22
DDR_B_D48
DDR_B_D36
DDR_B_DQS7
DDR_B_D42
DDR_B_D33
DDR_CKE3_DIMMB
DDR_B_DQS0
DDR_B_D43
DDR_B_MA1
DDR_B_MA8
DDR_B_DQS#2
DDR_B_DQS#5
DDR_B_MA12
DDR_B_DQS3
DDR_B_RAS#
DDR_B_MA4
DDR_B_DM5
DDR_B_D34
ICH_SMBCLK
DDR_B_D47
DDR_B_D7
DDR_B_MA13
DDR_B_D32
DDR_B_DQS1
DDR_B_BS#1
DDR_B_D62
DDR_B_DQS#6
DDR_B_D54
DDR_B_DM4
DDR_B_DQS6
DDR_B_DQS#1
DDR_B_D49
DDR_B_MA9
DDR_B_MA0
DDR_B_D3
DDR_B_D15
DDR_B_CAS#
DDR_B_D23
DDR_CS2_DIMMB#
DDR_B_DM0
DDR_B_DM1
DDR_B_D0
V_DDR_MCH_REF
DDR_B_DM6
DDR_B_D60
DDR_B_D58
DDR_B_D53
DDR_B_DM2
DDR_B_D50
DDR_B_D51
DDR_B_D39
DDR_B_D38
DDR_B_D31
DDR_B_D30 DDR_B_D27
DDR_B_D29
DDR_B_D25
DDR_B_D24 DDR_B_D28
DDR_B_D26
DDR_B_D19
DDR_B_D17
DDR_B_D20 DDR_B_D16DDR_B_D21 DDR_B_D18
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_B_MA6
DDR_B_MA11
DDR_B_MA7
DDR_THERM#
DDR_B_DQS#[0..7]8
DDR_B_DQS[0..7]8
DDR_B_D[0..63]8
DDR_B_MA[0..13]8
DDR_B_DM[0..7]8
DDR_CKE3_DIMMB7
DDR_CS2_DIMMB#7
V_DDR_MCH_REF7,13,44
ICH_SMBCLK4,13,15,18,21,25,27 ICH_SMBDATA4,13,15,18,21,25,27
DDR_B_WE#8
DDR_B_BS#18
DDR_B_RAS#8
DDR_B_CAS#8
M_ODT37
DDR_CKE2_DIMMB7
DDR_CS3_DIMMB#7
DDR_B_BS#28
DDR_B_BS#08
M_ODT27
M_CLK_DDR27
M_CLK_DDR#27
M_CLK_DDR37
M_CLK_DDR#37
DDR_THERM#7,13
+0.9V
+1.8V
+3VS
+3VS
+1.8V
+1.8V
+0.9V
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
DDRII-SODIMM SLOT2
1452Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
SO-DIMM B
STANDARD
Bottom side
Layout Note:
Place near JP34
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"
5/16
5/16
RP2
56_0404_4P2R_5%
1 4
2 3
RP3
56_0404_4P2R_5%
1 4
2 3
C106
0.1U_0402_16V4Z
1
2
C94
0.1U_0402_16V4Z
1
2
C476
0.1U_0402_16V4Z
1
2
C453
0.1U_0402_16V4Z
1
2
C454
0.1U_0402_16V4Z
1
2
C103
0.1U_0402_16V4Z
1
2
C86
0.1U_0402_16V4Z
1
2
C109
2.2U_0805_16V4Z
1
2
R33
10K_0402_5%
1 2
RP556_0404_4P2R_5%
14 23
C87
0.1U_0402_16V4Z
1
2
C475
0.1U_0402_16V4Z
1
2
RP656_0404_4P2R_5%
14 23
RP3356_0404_4P2R_5%
14 23
RP156_0404_4P2R_5%
14 23
RP37
56_0404_4P2R_5%
1 4
2 3
RP35
56_0404_4P2R_5%
1 4
2 3
C471
0.1U_0402_16V4Z
1
2
C89
0.1U_0402_16V4Z
1
2
C460
2.2U_0805_16V4Z
1
2
RP456_0404_4P2R_5%
14 23
RP31
56_0404_4P2R_5%
14 23
R34
10K_0402_5%
12
C466
2.2U_0805_16V4Z
1
2
JP29
FOX_ASOA426-M2RN-7F
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SA0 198
SA1 200
C477
0.1U_0402_16V4Z
1
2
C90
0.1U_0402_16V4Z
1
2
C99
2.2U_0805_16V4Z
1
2
C88
0.1U_0402_16V4Z
1
2
C473
0.1U_0402_16V4Z
1
2
C85
0.1U_0402_16V4Z
1
2
RP36
56_0404_4P2R_5%
1 4
2 3
RP3256_0404_4P2R_5%
14 23
C472
0.1U_0402_16V4Z
1
2
C455
0.1U_0402_16V4Z
1
2
C107
2.2U_0805_16V4Z
1
2
RP34
56_0404_4P2R_5%
1 4
2 3
C108
2.2U_0805_16V4Z
1
2
C474
0.1U_0402_16V4Z
1
2
5 4 3 2
2
1
1
DD
CC
BB
AA
CK_VDD_REF
CK_VDD_48
CK_VDD_48
CK_VDD_REF
CLKREF1
FSA CLK_48M_CB
CLKREF1
H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#
CLK_ENABLE#
CLK_PCI_ICH PCI_ICH
PCI_CLK3
CLKREF0
CLK_14M_SIO
FSA
ICH_SMBDATA
ICH_SMBCLK
PCI_EC
CLK_CPU_BCLK
CPU_BCLK#
CPU_XDP
CLK_MCH_BCLK#
CLK_CPU_XDP
CPU_BCLK
CLK_MCH_BCLK
MCH_BCLK#
MCH_BCLK
CLK_CPU_BCLK#
CLK_XTAL_IN
CLK_XTAL_OUT
CLKREQA#
CLK_CPU_XDP
CLK_CPU_XDP#
CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_LOM
CLK_PCIE_LOM#
PCI_PCM
PCI_ICH PCI_MINI
CLK_PCIE_ICH#PCIE_ICH#
CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_MXM
CLK_PCIE_MXM#
PCIE_MXM
PCIE_MXM#
CLK_CPU_XDP#
CLK_PCIE_MXM#
CLK_PCIE_MXM
CLK_PCIE_ICH#
CLK_PCIE_ICH
CLK_PCIE_DOCK#
CLK_PCIE_DOCK
PCI_MINI
CLK_14M_KBC
CLK_14M_ICH
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
CLK_48M_ICH
CLKIREF
PCIE_SATA
PCIE_SATA# CLK_PCIE_SATA#
CLK_PCIE_SATA CLK_PCIE_SATA
CLK_PCIE_SATA#
FSB
PCI_CLK5
FSB
PCIE_DOCK CLK_PCIE_DOCK
CLK_PCIE_DOCK#PCIE_DOCK#
MCH_3GPLL
MCH_3GPLL#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
PCIE_MCARD
PCIE_MCARD#
CLKREQC#
CPPE#CLKREQB#
CLKIREF
PCI_CLK3
CPU_XDP#
CLKREQD#
CLK_PCIE_LOM#
CLK_PCIE_LOM
PCIE_LOM#
PCIE_LOM
CPU_BSEL25
MCH_CLKSEL27
CPU_BSEL15
MCH_CLKSEL17
CPU_BSEL05
MCH_CLKSEL07 CLK_48M_CB24
CLK_48M_ICH21
H_STP_PCI#21 H_STP_CPU#21
CLK_PCI_ICH19
CLK_14M_SIO31
ICH_SMBDATA4,13,14,18,21,25,27
ICH_SMBCLK4,13,14,18,21,25,27
CLK_CPU_BCLK#4
CLK_CPU_XDP4
CLK_CPU_BCLK4
CLK_CPU_XDP#4
CLK_MCH_BCLK7
CLK_MCH_BCLK#7
CLKREQA#18,25
CLK_PCIE_ICH21
CLK_PCIE_ICH#21
CLK_PCIE_MXM#18
CLK_PCIE_MXM18
CLK_PCI_PCM23
CLK_PCI_EC33
CLK_14M_KBC33
CLK_14M_ICH21
CPPE#19,35
CLK_ENABLE#37,45
CLKREQD#27
CLK_PCIE_SATA20
CLK_PCIE_SATA#20
CLK_PCI_TCG32
CLK_PCIE_DOCK35
CLK_PCIE_DOCK#35
CLK_MCH_3GPLL7
CLK_MCH_3GPLL#7
CLK_PCIE_MCARD27
CLK_PCIE_MCARD#27
CLKREQC#7
CLK_PCI_SIO31
CLK_PCI_DB27
CLK_PCIE_LOM25
CLK_PCIE_LOM#25
+3VS
+CK_VDD_MAIN2
+CK_VDD_MAIN1
+3VS
+VCCP
+VCCP
+VCCP
+3VS
+3VS
+3VS +3VS
+CK_VDD_MAIN1
+3VS
+3VS
+CK_VDD_DP
+3VS
+VCCP
+CK_VDD_DP
+CK_VDD_DP
+3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Clock generator
1552Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
1
1000
CLKSEL1
100
0
PCI
MHz
133
0
Table : ICS954306
SRC
MHz
33.3
CPU
MHz
CLKSEL2
33.31
FSLA
CLKSEL0
166
FSLC
1
FSLB
Place near U25
Place these components
near each pin within 40
mils.
Place crystal within
500 mils of CK410
CLK_Ra
CLK_Rb
CLK_Rc
CLK_Rd
CLK_Re
CLK_Rf
CLK_Rc
Stuff
CLK_Rf
CLK_Ra
CLK_Re
CLK_Re
Stuff
CLK_Ra
FSB Frequency Selet:
No Stuff
CLK_Rb
No Stuff
533MHz CLK_Rf
CLK_Rc
CLK_Re
CLK_Rd
CLK_Rf
CLK_Ra
CLK_Rd
CLK_Rc
CPU Driven
No Stuff
CLK_Rb
Stuff
CLK_Rd
CLK_Rb
667MHz
*
(Default)
LCD(Low)/SRC(High)
clock select
High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHzLow:Pin44/45 = CPUCLK2_ITP
High:Pin44/45 = CLKREQ
Pin44/45 function select
*
*
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.
When this time, docking PCI express will not work.
L
Routing the trace at least 10mil
L
Routing the trace at least 10mil
L
If LP Chip stuff, all 49.9_0402
could be removed .
11/14
11/14
11/21
C447
0.1U_0402_16V4ZDP@
1
2
R47724_0402_5%
1 2
C457
10U_0805_10V4Z
1
2
R46549.9_0402_1%@
1 2
Y6
14.31818MHZ_20P_6X1430004201
12
R46249.9_0402_1%@12
R565
0_0402_5%
1 2
C450
0.1U_0402_16V4Z
1
2
R575
0_0402_5%
1 2
C465
0.1U_0402_16V4Z
1
2
R534
33_0402_5%
12
R550
8.2K_0402_5%
12
C43927P_0402_50V8J
12
R454
1_0805_1%
1 2
R51010K_0402_5%@
12
R492
0_0402_5%
1 2
R560
56_0402_5%
@
1 2
R4550_0402_5%NOXDP@
12
R489
33_0402_5%
12
R55449.9_0402_1%@
1 2
R4724.7K_0402_1%LPNO@ 1 2
R56849.9_0402_1%@
1 2
R51812_0402_5%
12
C44027P_0402_50V8J
12
R48224_0402_5%
1 2
R539
0_0402_5%
@
12
R56349.9_0402_1%@
1 2
R50710K_0402_5%
12
R46349.9_0402_1%@12
R55924_0402_5%
1 2
C448
0.1U_0402_16V4Z
1
2R45749.9_0402_1%@12
R48724_0402_5%
1 2
R56249.9_0402_1%@
1 2
R46649.9_0402_1%@
1 2
R54124_0402_5%
1 2
R54224_0402_5%
1 2
R54024_0402_5%
1 2
R47624_0402_5%
1 2
R45110K_0402_5%NOXDP@
12
R490
1K_0402_5%
1 2
R474
0_0402_5%DP@ 12
R55324_0402_5%
1 2
R501
10K_0402_5%NOXDP@
12
R49612_0402_5%
12
R46949.9_0402_1%@
1 2
R494
8.2K_0402_5%
12
R45849.9_0402_1%@12
J14
PAD-No SHORT 2x2m@
2 1
C470
0.1U_0402_16V4Z
1
2
R53112_0402_5%DB@
12
R508
0_0805_5%DP@
1 2
R5170_0402_5%
1 2
R46049.9_0402_1%@12
R537
10K_0402_5%@
12
R46110K_0402_5%NOXDP@
12
R48324_0402_5%
1 2
R5270_0402_5%
1 2
R55224_0402_5%
1 2
R4530_0805_5%
1 2
R51310K_0402_5%
12
R53333_0402_5% 12
R5020_0805_5%
1 2
R576
1K_0402_5%
1 2
R48033_0402_5%XDP@
1 2
C449
.01U_0402_16V7K
1
2
R535
10K_0402_5%
12
R4790_0402_5%NOXDP@
12
C496
10U_0805_10V4Z
1
2
R54324_0402_5%
1 2
C430
0.1U_0402_16V4Z
1
2
R564
1K_0402_5%
1 2
R45949.9_0402_1%@12
R53210K_0402_5%@12
R566
1K_0402_5%
1 2
C452
10U_0805_10V4Z
1
2
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
U30
ICS954306BGLFT_TSSOP64
*SEL_PCI1/PCICLK3
1
**SEL_SATA1/PCICLK4
2
**SEL_SATA2/PCICLK5
3
GND
4
VDDPCI
5
PCI/SRC_STOP#
8
PCICLK6
6
**SEL_LCDCLK#/PCICLK_F1
7
FSLA/USB_48MHz
11
SATACLKT 28
DOTT_96MHz
13
VDD48
10
Vtt_PwrGd#/PD
9
SRCCLKC3 27
SRCCLKT3 26
SATACLKC 29
GND
17
GND
12
SRCCLKC1 21
SRCCLKT1 20
LCDCLK_SSC/SRCCLKC0 19
LCDCLK_SST/SRCCLKT0 18
SRCCLKT2 22
CPUCLKC0 51
CPU_STOP#
61
REF0/PCICLK1
60
FSLC/TEST_SEL/REF1
59
VDDREF
55
VDDCPU
50
VDD
16
FSLB/TEST_MODE
15
DOTC_96MHz
14
X2 56
X1 57
SCLK
53
CPUCLKT0 52
*REQ_SEL/PCICLK2
62
*CLKREQB# 63
*CLKREQA# 64
GNDSRC
40
SATA1/SRCCLKC4 31
SATA1/SRCCLKT4 30
SDATA
54
CPUCLKT1 49
CPUCLKC1 48
VDDSRC
24
GNDSRC
25
GNDCPU
47
SRCCLKC2 23
IREF
46
*CPUCLKT2_ITP/CLKREQC# 45
*CPUCLKC2_ITP/CLKREQD# 44
SRCCLKT8 43
SRCCLKC8 42
GNDSATA
32
VDDSRC
41
GND
58
SRCCLKT7 39
SRCCLKC7 38
SRCCLKT6 37
SRCCLKC6 36
SATA2/SRCCLKT5 35
SATA2/SRCCLKC5 34
VDDSATA
33
C495
0.1U_0402_16V4Z
1
2
R504
10K_0402_5%XDP@
12
R46749.9_0402_1%@
1 2
R48424_0402_5%
1 2
R55112_0402_5%
12
R491
1K_0402_5%
1 2
R51933_0402_5%
12
R55649.9_0402_1%@12
R506
0_0805_5%NODP@
1 2
R53812_0402_5%
12
R49812_0402_5%
12
C451
.01U_0402_16V7K
1
2
R52833_0402_5%
12
C469
0.1U_0402_16V4Z
1
2
R47824_0402_5%
1 2
R56749.9_0402_1%@
1 2
R536
10K_0402_5%@
12
R55749.9_0402_1%@12
R493
0_0402_5%
@
12
R48133_0402_5%XDP@
1 2
C468
.01U_0402_16V7K
1
2
R46849.9_0402_1%@
1 2
R48624_0402_5%
1 2
R48524_0402_5%
1 2
R549
300_0402_5%
12
R47524_0402_5%
1 2
R46449.9_0402_1%@
1 2
R55824_0402_5%
1 2
R548
2.2_0805_1%
1 2
R55549.9_0402_1%@
1 2
R561
1K_0402_5%
12
A B C D
D
E
E
11
22
33
44
RED_R
GREEN_R
BLUE_R
M_CRMA_R
D_DDCCLK
D_DDCDATA
M_DDCCLK
M_DDCDATA
RED
GREEN
BLUE
M_COMP_R
HSYNC D_HSYNC
VSYNC D_VSYNC
GREEN
BLUE
RED
M_LUMA_RM_LUMA
M_CRMA
M_COMP
M_DDCDATA18
M_DDCCLK18
M_HSYNC18
M_VSYNC18
D_HSYNC35
D_VSYNC35
D_DDCDATA35
D_DDCCLK35
RED35
GREEN35
BLUE35
M_LUMA18,35
M_CRMA18,35
M_COMP18,35
+CRTVDD+RCRT_VCC
+3VS
+5VS
+CRTVDD +CRTVDD
+5VS
+3VS
+5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
CRT & TVout Connector
1652Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
W=40mils
CRT Connector
L
Place cloce to MXM connector JP39
L
Place cloce to TV-Out connector JP1
L
Place cloce to MXM connector JP39
TV-Out Connector
L
Place cloce to TV-Out connector JP1
11/17
U24
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R31
0_0603_5%
1 2
R5290_0603_5%
1 2
G
DS
Q67
BSS138_SOT23
2
1 3
C488
18P_0402_50V8J@
1
2
R445
2.2K_0402_5%
12
R450
2.2K_0402_5%
1 2
C71
5P_0402_50V8C
@
1
2
U23
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
F1
1.1A_6VDC_FUSE
21
R29
0_0603_5%
1 2
R26
0_0603_5%
1 2
C478
18P_0402_50V8J@
1
2
R310
0_0603_5%
1 2
R5160_0603_5%
1 2
G
DS
Q68
BSS138_SOT23
2
1 3
C325
5P_0402_50V8C@
1
2
C77
5P_0402_50V8C
@
1
2
C294
0.1U_0402_16V4Z
1 2
R666
150_0402_1%
12
D8
DAN217_SC59@
2
31
D6
DAN217_SC59@
2
31
C74
5P_0402_50V8C
@
1
2
R446
2.2K_0402_5%
12
C75
18P_0402_50V8J@
1
2
JP10
SUYIN_33007SR-07T1-C
1
2
3
4
5
6
7
C459
18P_0402_50V8J@
1
2
R5450_0603_5%
1 2
R665
150_0402_1%
12
R306
51K_0402_5%
1 2
D7
DAN217_SC59@
2
31
R664
150_0402_1%
12
JP7
FOX_DZ11A91-L7
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
R312
0_0603_5%
1 2
C293
0.1U_0402_16V4Z
1 2
R308
51K_0402_5%
1 2
R449
2.2K_0402_5%
1 2
C420
0.1U_0402_16V4Z
1
2
C73
18P_0402_50V8J@
1
2
C76
18P_0402_50V8J@
1
2
D3
CH491D_SC59
2 1
C326
5P_0402_50V8C@
1
2
5 4 3 2
2
1
1
DD
CC
BB
AA
ALS_EN
LID_SW#
M_ENAVDD
LID_SW#
M_LCD_CLK18 M_LCD_DAT18
INV_PWM33
M_ENAVDD18
M_TXB2+18
M_TXB2-18
M_TXB1-18
M_TXB1+18
M_TXB0+18
M_TXB0-18
M_TXBCLK-18
M_TXBCLK+18
M_TXACLK+18
M_TXACLK-18
M_TXA2-18
M_TXA2+18
M_TXA1+18
M_TXA1-18
M_TXA0-18
M_TXA0+18
M_PWM18
M_ENBLT18
LID_SW#21,34
ALS_EN19
+3VALWLCDVDD
LCDVDD
LCDVDD
+3VS
+5VS_INV
+5VS_INV
+5VS
+3VS
B+
B+_LCD
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
LCD CONN.
1752Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
LCD POWER CIRCUITMXM LVDS CONN
R80
100K_0402_5%
1 2
G
D
S
Q55
2N7002_SOT23 2
13
J1
PAD-SHORT 2x2m
2 1 C288
0.1U_0402_16V4Z
1
2
Q56
DTC124EK_SC59
2
13
U11A
SN74LVC08APW_TSSOP14
A
1
B
2O3
P14
G
7
R315
47K_0402_5%
1 2
G
D
S
Q13
BSS138_SOT23
2
13
G
DS
Q1
AO3413_SOT23
2
1 3
R86
100K_0402_5%
1 2
C298
0.047U_0402_16V7K
1 2
C287
68P_0402_50V8J
12
10K
47K
Q10
DTA114YKA_SC59
2
13
C12
4.7U_0805_10V4Z
1
2
R309
1M_0402_5%
1 2
JP3
ACES_87216-5002
11
33
55
77
99
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
41 41
42
42
43 43
44
44
45 45
46
46
47 47
48
48
49 49
50
50
C286
0.1U_0603_50V4Z
12
C289
4.7U_0805_10V4Z@
1
2
J2
PAD-No SHORT 2x2m@
2 1
L13
KC FBM-L11-201209-221LMA30T_0805
1 2 R307
100_0402_1%
12
5 4 3 2
2
1
1
DD
CC
BB
AA
PEG_M_TXN1
PEG_M_TXP1
PEG_RXP7
PEG_RXN6
PEG_RXP5
PEG_RXN3
PEG_RXN15
PEG_RXP15
PEG_RXN14
PEG_RXP14
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXP10
PEG_RXN9
PEG_RXN8
PEG_M_TXP12
PEG_M_TXN11
PEG_M_TXP11
PEG_M_TXN10
PEG_M_TXP10
PEG_M_TXN9
PEG_M_TXP9
PEG_M_TXN8
PEG_M_TXP8
PEG_M_TXN15
PEG_M_TXP15
PEG_M_TXN14
PEG_M_TXP14
PEG_M_TXN13
PEG_M_TXP13
PEG_M_TXN12
PEG_M_TXP7
PEG_M_TXN7
PEG_M_TXP6
PEG_M_TXP4
PEG_M_TXN4
PEG_M_TXP3
PEG_M_TXN3
PEG_M_TXP2
PEG_M_TXN2
MXM_CRMA
MXM_LUMA
MXM_COMP
M_RED
M_GRN
M_BLU
PEG_M_TXN0
PEG_M_TXP0
PEG_M_TXN6
MXM_CD0#
PEG_RXP4
PEG_RXN13
PEG_RXP6
PEG_RXN4
PEG_RXP11
PEG_RXP8
PEG_RXP9
PEG_RXP3
PEG_RXP12
PEG_RXN2
PEG_RXN5
PEG_RXN7
PEG_RXP2
PEG_RXP13
DVI_TX0-
DVI_TX1-
DVI_TX1+
PEG_RXN1
DVI_TX0+
DVI_CLK-
M_DDCCLK
PEG_RXP0
DVI_TX2+
M_HSYNC
CLK_PCIE_MXM
VGA_RST#
CLK_PCIE_MXM#
M_VSYNC
DVI_TX2-
DVI_DETECT
M_DDCDATA
PEG_RXP1
PEG_RXN0
DVI_CLK+
SLP_S3#
MXM_THERM#
PEG_M_TXN5
PEG_M_TXP5
D_RED
M_GRN
D_BLUE
M_RED RED_LL
D_GREEN
M_BLU BLUE_LL
GREEN_LL
MXM_COMP
MXM_CRMA
MXM_LUMA
ICH_SMBDATA
ICH_SMBCLK MXM_SMBDATA
MXM_SMBCLK
MXM_COMP
MXM_CRMA
MXM_LUMA M_LUMA
M_COMP
M_CRMA
MXM_CD0#
PEG_RXP[0..15]9
PEG_RXN[0..15]9
PEG_M_TXN[0..15]9
PEG_M_TXP[0..15]9
VGA_RST#21
M_LCD_CLK17
M_LCD_DAT17
M_ENBLT17
M_ENAVDD17
M_HSYNC16 M_VSYNC16
M_DDCDATA16 M_DDCCLK16
DVI_DDC_CLK35
PWR_GD33,36,37,45,47
DVI_DDC_DAT35
DVI_CLK-35 DVI_CLK+35
DVI_TX0-35 DVI_TX0+35
DVI_TX1-35 DVI_TX1+35
DVI_DETECT35
CLK_PCIE_MXM#15 CLK_PCIE_MXM15
MXM_CD0#21
M_TXB2+17
M_TXB2-17
M_TXB1-17
M_TXB1+17
M_TXB0+17
M_TXB0-17
M_TXA2-17
M_TXA2+17
M_TXA1+17
M_TXA1-17
M_TXA0-17
M_TXA0+17
M_TXACLK+17
M_TXACLK-17
M_TXBCLK-17
M_TXBCLK+17
M_PWM17
DVI_TX2-35 DVI_TX2+35
SLP_S3#21,25,27,28,29,33,35,36,40,43,44
MXM_THERM#21
D_BLUE35
D_RED35
D_GREEN35
ICH_SMBDATA4,13,14,15,21,25,27 ICH_SMBCLK4,13,14,15,21,25,27
M_LUMA16,35
M_CRMA16,35
M_COMP16,35
MXM_CD1#21,47
CLKREQA#15,25
ADP_PRES25,33,40,41,42,47
+1.8VS
+3VS
+5VS
+2.5VS
B+ +1.8VS
+5VALW
+3VS
+3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
MXM III CONN
1852Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
CRT Termination/EMI Filter
Place those components as close
as MXMIII connector within 500 mils.
TV-Out Termination/EMI Filter
L
Place cloce to MXM connector JP39
L
Place those components as close as
MXMIII connector within 500 mils.
MXM Address:100_1100
9/15
L6
HLC0603CSCCR11JT_0603
1 2
C292
4.7U_0805_10V4Z
1
2
R3130_0402_5%
1 2
L9
CHB1608U301_0603
1 2
R316
150_0402_1%
12
L2
HLC0603CSCC39NJT_0603
1 2
R317
150_0402_1%
12
L8
CHB1608U301_0603
1 2
R314
150_0402_1%
12
C7
18P_0402_50V8J
1
2
L1
HLC0603CSCCR11JT_0603
1 2
R10
150_0402_1%@
12
R303
8.2K_0402_5%@
1 2
C13
82P_0402_50V8J
1
2
C14
82P_0402_50V8J
1
2
L4
HLC0603CSCC39NJT_0603
1 2
R11
150_0402_1%@
12
C11
0.1U_0603_50V4Z
1
2
C19
82P_0402_50V8J
1
2
R311 0_0402_5%@1 2
R3190_0402_5%
1 2
L3
HLC0603CSCCR11JT_0603
1 2
R305
8.2K_0402_5%@1 2
JP5A
ACES_88990-2D28_GF
PWR_SRC
1
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
GND
17
GND
19
GND
21
GND
23
PEX_RX15#
25
PEX_RX15
27
GND
29
PEX_RX14#
31
PEX_RX14
33
GND
35
PEX_RX13#
37
PEX_RX13
39
GND
41
PEX_RX12#
43
PEX_RX12
45
GND
47
PEX_RX11#
49
PEX_RX11
51
GND
53
PEX_RX10#
55
PEX_RX10
57
GND
59
PEX_RX9#
61
PEX_RX9
63
GND
65
PEX_RX8#
67
PEX_RX8
69
GND
71
PEX_RX7#
73
PEX_RX7
75
GND
77
PEX_RX6#
79
PEX_RX6
81
GND
83
PEX_RX5#
85
PEX_RX5
87
GND
89
PEX_RX4#
91
PEX_RX4
93
GND
95
PEX_RX3#
97
PEX_RX3
99
GND
101
PEX_RX2#
103
PEX_RX2
105
GND
107
1V8RUN 2
1V8RUN 4
1V8RUN 6
1V8RUN 8
1V8RUN 10
1V8RUN 12
1V8RUN 14
RUNPWROK 16
5VRUN 18
GND 20
GND 22
GND 24
PRSNT2# 26
PEX_TX15# 28
PEX_TX15 30
GND 32
PEX_TX14# 34
PEX_TX14 36
GND 38
PEX_TX13# 40
PEX_TX13 42
GND 44
PEX_TX12# 46
PEX_TX12 48
GND 50
PEX_TX11# 52
PEX_TX11 54
GND 56
PEX_TX10# 58
PEX_TX10 60
GND 62
PEX_TX9# 64
PEX_TX9 66
GND 68
PEX_TX8# 70
PEX_TX8 72
GND 74
PEX_TX7# 76
PEX_TX7 78
GND 80
PEX_TX6# 82
PEX_TX6 84
GND 86
PEX_TX5# 88
PEX_TX5 90
GND 92
PEX_TX4# 94
PEX_TX4 96
GND 98
PEX_TX3# 100
PEX_TX3 102
GND 104
PEX_TX2# 106
PEX_TX2 108
JP5B
ACES_88990-2D28_GF
PEX_RX1#
109
PEX_RX1
111
GND
113
PEX_RX0#
115
PEX_RX0
117
GND
119
PEX_REFCLK#
121
PEX_REFCLK
123
CLK_REQ#
125
PEX_RST#
127
RSVD
129
RSVD
131
SMB_DAT
133
SMB_CLK
135
THERM#
137
VGA_HSYNC
139
VGA_VSYNC
141
DDCA_CLK
143
DDCA_DAT
145
IGP_UCLK#
147
IGP_UCLK
149
GND
151
RSVD
153
RSVD
155
RSVD
157
IGP_UTX2#
159
IGP_UTX2
161
GND
163
IGP_UTX1#
165
IGP_UTX1
167
GND
169
IGP_UTX0#
171
IGP_UTX0
173
GND
175
IGP_LCLK#/DVI_B_CLK#
177
IGP_LCLK/DVI_B_CLK
179
DVI_B_HPD/GND
181
RSVD
183
RSVD
185
GND
187
IGP_LTX2#/DVI_B_TX2#
189
IGP_LTX2/DVI_B_TX2
191
GND
193
IGP_LTX1#/DVI_B_TX1#
195
IGP_LTX1/DVI_B_TX1
197
GND
199
IGP_LTX0#/DVI_B_TX0#
201
IGP_LTX0/DVI_B_TX0
203
DVI_A_HPD
205
DVI_A_CLK#
207
DVI_A_CLK
209
GND
211
DVI_A_TX2#
213
DVI_A_TX2
215
GND
217
DVI_A_TX1#
219
DVI_A_TX1
221
GND
223
DVI_A_TX0#
225
DVI_A_TX0
227
GND
229
GND 110
PEX_TX1# 112
PEX_TX1 114
GND 116
PEX_TX0# 118
PEX_TX0 120
PRSNT1# 122
TV_C/HDTV_Pr 124
GND 126
TV_Y/HDTV_Y 128
GND 130
TV_CVBS/HDTV_Pb 132
GND 134
VGA_RED 136
GND 138
VGA_GRN 140
GND 142
VGA_BLU 144
GND 146
LVDS_UCLK# 148
LVDS_UCLK 150
GND 152
LVDS_UTX3# 154
LVDS_UTX3 156
GND 158
LVDS_UTX2# 160
LVDS_UTX2 162
GND 164
LVDS_UTX1# 166
LVDS_UTX1 168
GND 170
LVDS_UTX0# 172
LVDS_UTX0 174
GND 176
LVDS_LCLK# 178
LVDS_LCLK 180
GND 182
LVDS_LTX3# 184
LVDS_LTX3 186
GND 188
LVDS_LTX2# 190
LVDS_LTX2 192
GND 194
LVDS_LTX1# 196
LVDS_LTX1 198
GND 200
LVDS_LTX0# 202
LVDS_LTX0 204
GND 206
DDCC_DAT 208
DDCC_CLK 210
LVDS_PPEN 212
LVDS_BL_BRGHT 214
LVDS_BLEN 216
DDCB_DAT 218
DDCB_CLK 220
2V5RUN 222
GND 224
3V3RUN 226
3V3RUN 228
3V3RUN 230
R2
150_0402_1%@
12
R3200_0402_5%
1 2
C2
18P_0402_50V8J
1
2
+
C9
100U_25V_M
1
2
C15
82P_0402_50V8J
1
2
C4
4.7U_0805_10V4Z
1
2
L5
HLC0603CSCC39NJT_0603
1 2
C18
82P_0402_50V8J
1
2
C3
18P_0402_50V8J
1
2
C17
82P_0402_50V8J
1
2
L7
CHB1608U301_0603
1 2
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
CLK_PCI_ICH
PCI_SERR#
PCI_DEVSEL#
PCI_PCIRST#
PCI_CBE#0
PCI_PERR#
ICH_GPIO48
PCI_PIRQG#
PCI_PIRQB#
PCI_STOP#
PCI_CBE#1
PCI_CBE#3
PCI_PIRQF#
PCI_PIRQC#
PCI_REQ2#
PCI_PIRQE#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_CBE#2
PCI_REQ1#
PCI_REQ0#
PCI_PIRQD#
PCI_PIRQA#
PCI_PAR
PCI_TRDY#
PCI_PIRQH#
PCI_RST#
PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD7
PCI_AD6
PCI_AD8
PCI_AD9
PCI_AD11
PCI_AD10
PCI_AD14
PCI_AD15
PCI_AD13
PCI_AD12
PCI_AD16
PCI_AD17
PCI_AD19
PCI_AD18
PCI_AD22
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD25
PCI_AD24
PCI_AD28
PCI_AD29
PCI_AD31
PCI_AD30
PCI_AD26
PCI_AD27
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_IRDY#
PCI_PLOCK#
PCI_SERR#
PCI_PERR#
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQH#
PCI_PIRQG#
PCI_PIRQF#
PCI_PIRQE#
PCI_REQ0#
PCI_REQ2#
CPPE#
PCI_REQ1#
ALS_EN#
PCI_GNT0#
PCI_GNT2#
PCI_REQ4#
PCI_REQ3#
PLT_RST#
ALS_EN#
ALS_EN
PCI_PLTRST#
PCI_PCIRST#
CPPE#
PCI_REQ3#
ICH_GPIO48
PCI_REQ4#
ALS_EN#
PCI_AD[0..31]23
PCI_PIRQC#23 PCI_PIRQD#23
PCI_CBE#023
PCI_CBE#123
PCI_CBE#223
PCI_CBE#323
PCI_IRDY#23
PCI_PAR23
PCI_DEVSEL#23
PCI_PERR#23
PCI_STOP#23
PCI_TRDY#23
PCI_FRAME#23
CLK_PCI_ICH15
PCI_SERR#23,33
PCI_PME#23
PCI_RST#23,24
PLT_RST#7,20,21,23,25,27,32,33
PCI_GNT2#23
PCI_REQ2#23
PCI_PIRQE#23
PCI_PIRQG#23
MCH_ICH_SYNC#7
ALS_EN17
CPPE#15,35
ACCEL_INT27
+3VS
+3VS
+3VS
+5VS
+3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
ICH7-M(1/4)
1952Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place closely pin A9
9/2
11/23
R6228.2K_0402_5%
1 2
R6168.2K_0402_5%
1 2
U9
TC7SH08FU_SSOP5@
B
1
A
2Y4
P5
G
3
R66
0_0402_5%@
12
R6078.2K_0402_5%
1 2
C145
8.2P_0402_50V@
1
2
R1058.2K_0402_5%
1 2
R6258.2K_0402_5%
1 2
R6188.2K_0402_5%
1 2
R6318.2K_0402_5%
1 2
Interrupt I/F
PCI
MISC
U10B
ICH7M_B0_BGA652
FRAME# F16
GPIO17 / GNT5# D8
TRDY# F14
STOP# F15
GPIO2 / PIRQE# G8
GPIO3 / PIRQF# F7
GPIO4 / PIRQG# F8
GPIO5 / PIRQH# G7
C/BE0# B15
C/BE1# C12
C/BE2# D12
C/BE3# C15
IRDY# A7
PAR E10
PCIRST# B18
DEVSEL# A12
PERR# C9
PLOCK# E11
SERR# B10
PIRQC#
C5
RSVD[4]
AH4
PIRQA#
A3
RSVD[5]
AD9
RSVD[2]
AD5
RSVD[3]
AG4
PIRQB#
B4
PIRQD#
B5
RSVD[1]
AE5
REQ0# D7
GNT0# E7
REQ1# C16
GNT1# D16
REQ2# C17
GNT2# D17
REQ3# E13
GNT3# F13
REQ4# / GPIO22 A13
GNT4# / GPIO48 A14
GPIO1 / REQ5# C8
AD0
E18
AD1
C18
AD2
A16
AD3
F18
AD4
E16
AD5
A18
AD6
E17
AD7
A17
AD8
A15
AD9
C14
AD10
E14
AD11
D14
AD12
B12
AD13
C13
AD14
G15
AD15
G13
AD16
E12
AD17
C11
AD18
D11
AD19
A11
AD20
A10
AD21
F11
AD22
F10
AD23
E9
AD24
D9
AD25
B9
AD26
A8
AD27
A6
AD28
C7
AD29
B6
AD30
E6
AD31
D6
RSVD[6] AE9
RSVD[7] AG8
RSVD[8] AH8
RSVD[9] F21
MCH_SYNC# AH20
PLTRST# C26
PCICLK A9
PME# B19
R1068.2K_0402_5%
1 2
R6178.2K_0402_5%
1 2
R83
1K_0402_5%SPI@
12
R676
0_0402_5%
1 2
R6138.2K_0402_5%
1 2
R6118.2K_0402_5%
1 2
R6238.2K_0402_5%
1 2
R6198.2K_0402_5%
1 2
R6268.2K_0402_5%
1 2
R675
0_0402_5%
1 2
G
D
S
Q15
2N7002_SOT23
2
13
R6278.2K_0402_5%
1 2
R6108.2K_0402_5%
1 2
U11D
SN74LVC08APW_TSSOP14
A
12
B
13 O11
P14
G
7
R621
10_0402_5% @
1 2
R6358.2K_0402_5%
1 2
R89
330_0402_5%
1 2
R71
0_0402_5%
12
R636
0_0402_5%
12
R6328.2K_0402_5%@
1 2
R6158.2K_0402_5%
1 2
R6128.2K_0402_5%
1 2
R6288.2K_0402_5%
1 2
R1078.2K_0402_5%
1 2
R6248.2K_0402_5%
1 2
5 4 3 2
2
1
1
DD
CC
BB
AA
PD_DREQ
H_A20M#
H_INIT#
H_IGNNE#
H_INTR
H_NMI
PD_D9
PD_D2
PD_D15
PD_D0
PD_IOR#
DPRSLP#
LPC_FRAME#
PD_A1
PD_D14
PD_A2
LPC_DRQ#1
PD_IOW#
AC97_SDIN1
PD_D6
PD_A0
AC97_SDOUT
PD_D13
PD_D10
PD_D8
PD_D1
PD_D7
PD_D4
LPC_AD3
AC97_RST#
PD_D12
PD_D3
THRMTRIP_ICH#
PD_D5
LPC_AD0
PD_D11
PD_DACK#
AC97_SDIN0
LPC_DRQ#0
H_DPSLP#
PD_CS#1
SM_INTRUDER#
H_CPUSLP_R#
H_PWRGOOD
H_SMI#
LPC_AD2
PD_CS#3
LPC_AD1
ICH_INTVRMEN
PD_IRQ
PD_IORDY
PD_IOR#
PD_DREQ
PD_D8
PD_D11
PD_D12
PD_D13
PD_D14
PD_D10
PD_D9
PD_D15
PD_DACK#
PDIAG#
PD_CS#3
PD_A2
FWH_INIT#
ICH_RTCX2
ICH_RTCRST#
ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
PD_IOW#
PD_IORDY
PD_IRQ
PD_A0
PD_CS#1
PD_A1
ICH_INTVRMEN
SEC_CSEL
AC97_SYNC
H_FERR#
GATEA20
KB_RST#
ICH_RTCX1
AC97_BITCLK
CLK_PCIE_SATA#
CLK_PCIE_SATA
IDE_LED#
SATA_RXN0_C
SATA_RXP0_C
SATA_TXP0_C
SATA_TXN0_C
SATA_TXN0SATA_TXN0_C
SATA_TXP0_C SATA_TXP0
SATA_RXP0
SATA_RXN0
SATA_RXP0_C
SATA_RXN0_C
IDE_DSP#
RTC2RTC1
ODD_RST#
H_STPCLK#
H_STPCLK#
SATA_TXP0
SATA_TXN0
SATA_RXN0
SATA_RXP0
AC97_SDIN028 AC97_SDIN134
LPC_AD[0..3]27,31,32,33
H_A20M#4
H_DPRSTP#4,45
H_DPSLP#4
H_FERR#4
H_PWRGOOD4
H_IGNNE#4
H_INIT#4
H_INTR4
H_SMI#4
H_NMI4
GATEA2033
KB_RST#33
H_THERMTRIP#4,7
LPC_DRQ#031
LPC_DRQ#1
LPC_FRAME#27,31,32,33
AC97_SDOUT_MDC34
AC97_SDOUT_CODEC28
AC97_SYNC_CODEC28
AC97_SYNC_MDC34
AC97_BITCLK_CODEC28
AC97_BITCLK_MDC34
AC97_RST#_CODEC28
AC97_RST#_MDC34
CLK_PCIE_SATA#15
CLK_PCIE_SATA15
PLT_RST#7,19,21,23,25,27,32,33
PLT_RST_B#27,31
H_STPCLK#4
IDE_LED#32
+3VS
+VCCP
+RTCVCC
+RTCVCC
+VCCP
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+RTCVCC
+5VS
+3VS
+3VS
+3VALW
+5VS
+RTCVCC +3VL
+3VS
+5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
ICH7-M(2/4)
2052Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place component's closely IDE CONN. JP45
W=80mils
Place component's closely IDE CONN. JP37
ODD CONN
L
R1031 must be placed close to U26.AF26
within 2" and R1030 must be placed close
to R1031 within 2".
Near ICH7(U26) side.
Near Device(JP45) side.
L
L
7/6
SATA CONN
L
L
-+
L
W=20mils
8/24
9/8
11/18
C159
1U_0603_10V4Z
1 2
R6110K_0402_5%
12
R598 0_0402_5%
12
CMOS_CLR1
SHORT PADS
1 2
T14
PAD
C98
10U_0805_10V4Z
1
2
C15718P_0402_50V8J
12
R430
100_0402_5%
1 2
C151
0.1U_0402_16V4Z
1
2
R10033_0402_5% 1 2
R103
332K_0402_1%
12
C102
0.1U_0402_16V4Z
1
2
R580_0402_5%
12
R8833_0402_5%
12
R96
10M_0402_5%
12
R5456_0402_5%
12
C1503900P_0402_50V7K
1 2
R24733_0402_5%
12
R24033_0402_5%
1 2
C1493900P_0402_50V7K
1 2
C15818P_0402_50V8J
12
C403
1U_0603_10V4Z
1
2
R6010K_0402_5%
12
R423
1K_0402_5%
1 2
R509100K_0402_5%
1 2
JP28
E&T_7651
21
C147
0.1U_0402_16V4Z
1
2
D35
CH751H-40_SC76
2 1
ZZZ
PCB-MB
R591
24.9_0402_1%
1 2
R24533_0402_5% 12
R6088.2K_0402_5%
12
R620
24.9_0402_1%
1 2
C1040.1U_0402_16V4Z
12
C1753900P_0402_50V7K
1 2
C148
10U_0805_10V4Z
1
2
C153
0.1U_0402_16V4Z
1
2
JP13
OCTEK_CDR-50DU1
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
RTC LAN SATA
AC-97/AZALIA
LPCCPU
IDE
U10A
ICH7M_B0_BGA652
RTXC1
AB1
RTCX2
AB2
RTCRST#
AA3
INTVRMEN
W4
INTRUDER#
Y5
EE_CS
W1
EE_SHCLK
Y1
EE_DOUT
Y2
EE_DIN
W3
LAN_CLK
V3
LAN_RSTSYNC
U3
LAN_RXD0
U5
LAN_RXD1
V4
LAN_RXD2
T5
LAN_TXD0
U7
LAN_TXD1
V6
LAN_TXD2
V7
ACZ_BCLK
U1
ACZ_SYNC
R6
ACZ_RST#
R5
ACZ_SDIN0
T2
ACZ_SDIN1
T3
ACZ_SDIN2
T1
ACZ_SDOUT
T4
SATALED#
AF18
SATA0RXN
AF3
SATA0RXP
AE3
SATA0TXN
AG2
SATA0TXP
AH2
SATA2RXN
AF7
SATA2RXP
AE7
SATA2TXN
AG6
SATA2TXP
AH6
SATA_CLKN
AF1
SATA_CLKP
AE1
SATARBIASN
AH10
SATARBIASP
AG10
IORDY
AG16
IDEIRQ
AH16
DDACK#
AF16
DIOW#
AH15
DIOR#
AF15
LAD0 AA6
LAD1 AB5
LAD2 AC4
LAD3 Y6
LDRQ0# AC3
LDRQ1# / GPIO23 AA5
LFRAME# AB3
A20GATE AE22
A20M# AH28
CPUSLP# AG27
TP1 / DPRSTP# AF24
TP2 / DPSLP# AH25
FERR# AG26
GPIO49 / CPUPWRGD AG24
IGNNE# AG22
INIT3_3V# AG21
INIT# AF22
INTR AF25
RCIN# AG23
SMI# AF23
NMI AH24
STPCLK# AH22
THERMTRIP# AF26
DA0 AH17
DA1 AE17
DA2 AF17
DCS1# AE16
DCS3# AD16
DD0 AB15
DD1 AE14
DD2 AG13
DD3 AF13
DD4 AD14
DD5 AC13
DD6 AD12
DD7 AC12
DD8 AE12
DD9 AF12
DD10 AB13
DD11 AC14
DD12 AF14
DD13 AH13
DD14 AH14
DD15 AC15
DDREQ AE15
D32
DAN202U_SC70
2
3
1
R63033_0402_5%
12
C156
0.1U_0402_16V4Z
1
2
JP20
OCTEK_SAT-22DN1G_NR
GND S1
A+ S2
A- S3
GND S4
B- S5
B+ S6
GND S7
V33 P1
V33 P2
V33 P3
GND P4
GND P5
GND P6
V5 P7
V5 P8
V5 P9
GND P10
GND P12
V12 P13
V12 P14
V12 P15
RSVD P11
GND 23
GND 24
T26
PAD
R102
332K_0402_1%@
12
R645
20K_0402_5%
1 2
R629
1M_0402_5%
1 2
R101
0_0402_5%@
12
R11333_0402_5% 1 2
R6094.7K_0402_5%
12
R592
56_0402_5%
12
U11B
SN74LVC08APW_TSSOP14
A
4
B
5O6
P14
G
7
R25333_0402_5% 1 2
Y1
32.768KHZ_12.5P_1TJS125BJ2A251
OUT 4
IN 1
NC
3
NC
2
BATT1
CR2025 RTC BATTERY
45@
R4994.7K_0402_5%@
1 2
R26933_0402_5% 12
C1733900P_0402_50V7K
1 2
C101
0.1U_0402_16V4Z
1
2
C100
0.1U_0402_16V4Z
1
2
R503470_0402_5%
12
R512
10K_0402_5%
12
5 4 3 2
2
1
1
DD
CC
BB
AA
LINKALERT#
OCP#
THERM_SCI#
SIRQ
PM_CLKRUN#
USB_OC#1
USB_OC#2
H_STP_PCI#
USB_OC#3
DPRSLPVR
DMI_TXN3
DMI_TXN0
USBRBIAS
DMI_TXP1
USB_OC#2
USB_OC#4
DMI_TXP2
MXM_CD0#
USB_OC#3
DMI_TXN1
DMI_RXN1
USB_OC#1
DMI_TXP3
DMI_RXP1
DMI_RXN3
CLK_PCIE_ICH
DMI_RXN2
DMI_RXN0
DMI_TXP0
DMI_RXP3
CLK_PCIE_ICH#
DMI_TXN2
DMI_RXP0
USB_OC#4
MXM_CD0#
DMI_RXP2
USB20_N7
USB20_P7
USB20_N6
USB20_P6
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
LID_SW#
DMI_IRCOMP
PCIE_C_TXP1
PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
THERM_SCI#
MXM_CD1#_R
PREP#
PCIE_C_TXP2
PCIE_C_TXN2
PCIE_RXP2
PCIE_RXN2
USB_OC#0
USB_OC#0
USB_OC#5
USB_OC#5
M24_RST#
PLT_RST#
SPI_CS#
SPI_SI
SPI_SO
SPI_CLK
ICH_SMBCLK ICH_SMB_CLK
ICH_SMB_DATAICH_SMBDATA
ICH_SMBCLK
ICH_SMBDATA
XDP_DBRESET#
M24_RST#
MXM_CD1# MXM_CD1#_R
PCIE_C_TXP4
PCIE_RXP4
PCIE_C_TXN4
PCIE_RXN4
H_STP_CPU#
ISO_PREP# BT_OFF
LID_SW#
ICH_RI#
THERM_SCI#
SIRQ
ICH_SMLINK0
SLP_S5#
RUNSCI_EC#
PLT_RST#
DPRSLPVR
CLK_48M_ICH
LP_EN#
ON/OFFBTN#
LPC_PD#
XMIT_OFF
FWH_WP#
GPIO28_SB
ICH_SMB_DATA
SLP_S3#
ISO_PREP#
LINKALERT#
ICH_LOW_BAT#
PM_BMBUSY#
XDP_DBRESET#
PWROK_ICH7
CB_IN#
PM_POK
ICH_SUSCLK
FWH_TBL#
NPCI_RST#
GPIO12_SB
PM_RSMRST#
PM_CLKRUN#
CLK_14M_ICH
ICH_PCIE_WAKE#
SLP_S4#
PWROK_ICH7
ICH_SMB_CLK
CLK_48M_ICH
SB_SPKR
LANLINK_STATUS#_SB
GPIO39_SB
ICH_SMLINK1
GPIO15_SB
GPIO9_SB
GPIO26_SB
CLK_14M_ICH
OCP#
GPIO27_SB
SPI_SI
SPI_CS#
SPI_SO
PM_CLKRUN#23,31,32,33
H_STP_PCI#15 H_STP_CPU#15
SB_SPKR28
PM_BMBUSY#7
SIRQ23,31,32,33
THERM_SCI#4
SLP_S3#18,25,27,28,29,33,35,36,40,43,44
SLP_S5#36,44
DPRSLPVR7,45
DMI_RXN07
DMI_RXP07
DMI_RXN17
DMI_RXP17
DMI_RXN27
DMI_RXP27
DMI_RXN37
DMI_RXP37
CLK_PCIE_ICH#15
CLK_PCIE_ICH15
PM_RSMRST#33
ON/OFFBTN#34
PM_POK7,33
CLK_48M_ICH15
CLK_14M_ICH15
USB20_P735
USB20_N735
USB20_N635
USB20_P635
USB20_N132
USB20_P132
USB20_N229
USB20_P229
USB20_N329
USB20_P329
USB20_N430
USB20_P430
USB20_N530
USB20_P530
USB20_N030
USB20_P030
USB_OC#1
USB_OC#229 USB_OC#329
LOW_BAT#33
XDP_DBRESET#4
OCP#4,47
PCIE_RXN125
PCIE_TXN125 PCIE_TXP125
PCIE_RXP125
PCIE_WAKE#27
MXM_THERM#18
LPC_PD#32,33
SLP_S4#44
PREP#26,35
PCIE_TXN227 PCIE_RXP227 PCIE_RXN227
PCIE_TXP227
USB_OC#430
RUNSCI_EC#33
LOM_LOW_PWR25
CABLE_DETECT25,26
LID_SW#17,34
LANLINK_STATUS#_SB25
VGA_RST#18 PLT_RST#7,19,20,23,25,27,32,33
XMIT_OFF27
BT_OFF30
MXM_CD0#18
NPCI_RST#31,33
SPI_SO32
SPI_CS#32
SPI_SI32
SPI_CLK32
ISO_PREP#35
ICH_SMBCLK4,13,14,15,18,25,27
ICH_SMBDATA4,13,14,15,18,25,27
USB_OC#530
VGATE_INTEL7,45 PM_POK7,33
DOCK_ID35
DMI_TXN07
DMI_TXP07
DMI_TXN17
DMI_TXP17
DMI_TXN27
DMI_TXP27
DMI_TXN37
DMI_TXP37
LOM_PCIE_WAKE#25
MXM_CD1#18,47
PCIE_TXP435
PCIE_RXP435 PCIE_TXN435
PCIE_RXN435
HDD_STP32
LP_EN#25
+3VALW
+3VALW
+3VS
+3VALW
+1.5VS
+3VALW
+3VL
+3VALW
V_3P3_LAN
+3VALW +3VS
+3VS
+3VALW
+5VS
+3VS
+3VALW
+3VALW
+3VALW
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
ICH7-M(3/4)
2152Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place closely pin B2 Place closely pin AC1
Within 500 mils
Within 500 mils
Need update symbol
L
R1292/R1293 should be placed
less than 100 mils from U26.
L
R1015 need be removed when ICH7M ES2 samples used,
but need be stuffed when ICH7M ES1 samples used.
L
R213,R233 change from 2.2Kohm to
10Kohm when Q23,Q24,R206,R204 stuffed.
9/14
11/14
11/14
11/22
11/21
L
R1284,R1285 and R1286 should
be placed close to U26.
T49PAD
R587
8.2K_0402_5%
1 2
R593
10K_0402_5%
1 2
R73 8.2K_0402_5%
1 2
T31PAD
G
D
S
Q14
2N7002_SOT23@
2
13
C1340.1U_0402_16V4Z 12
R606 10K_0402_5%
1 2
R58824.9_0402_1%
1 2
R82 0_0402_5%
1 2
R6390_0402_5%
1 2
C1280.1U_0603_16V7K
12
R642
10K_0402_5%
1 2
T16PAD
D14
CH751H-40_SC76
21
R84
2.2K_0402_5%@
12
R97
10K_0402_5%SPI@
1 2
R75
2.2K_0402_5%
12
R77 0_0402_5%
1 2
T27PAD D13
CH751H-40_SC76
2 1
R640_0402_5%
1 2
R586 0_0402_5%
1 2
R110
10K_0402_5%SPI@
1 2
R111
10K_0402_5%SPI@
1 2
RP20
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R81
2.2K_0402_5%
12
T29PAD
T25PAD
R604
1K_0402_5%
1 2
R644
10K_0402_5%
1 2
R603
0_0402_5%
1 2
R594 10K_0402_5%
1 2
R640
10_0402_5%@
12
R78
10K_0402_5%
12
R589 10K_0402_5%
1 2
R637
10_0402_5%@
12
C1270.1U_0603_16V7K
12
R605 0_0402_5%@1 2
J16
PAD-SHORT 2x2m
2 1
R76
10K_0402_5%
12
C541
4.7P_0402_50V8C@
1
2
G
D
S
Q11
2N7002_SOT23@
2
13
R64122.6_0402_1%
1 2
R601
8.2K_0402_5%
12
T32PAD
R74
10K_0402_5%
12
C1300.1U_0402_16V4Z 12
R590_0402_5%@
1 2
R595
10K_0402_5%
1 2
R98 47_0402_5%SPI@
1 2
C542
4.7P_0402_50V8C@
1
2
SATA
POWER MGT
SYS
SMB
GPIO
Clocks
GPIO
GPIO
U10C
ICH7M_B0_BGA652
RI#
A28
SPKR
A19
SYS_RST#
A22 SUS_STAT#
A27
GPIO0 / BM_BUSY#
AB18
GPIO26
A21
GPIO27
B21
GPIO28
E23
GPIO32 / CLKRUN#
AG18
GPIO33 / AZ_DOCK_EN#
AC19
GPIO34 / AZ_DOCK_RST#
U2
VRMPWRGD
AD22
GPIO11 / SMBALERT#
B23
SUSCLK C20
SLP_S3# B24
SLP_S4# D23
SLP_S5# F22
PWROK AA4
GPIO16 / DPRSLPVR AC22
TP0 / BATLOW# C21
PWRBTN# C23
LAN_RST# C19
RSMRST# Y4
GPIO21 / SATA0GP AF19
GPIO19 / SATA1GP AH18
GPIO36 / SATA2GP AH19
GPIO37 / SATA3GP AE19
CLK14 AC1
CLK48 B2
GPIO9 E20
GPIO10 A20
GPIO12 F19
GPIO13 E19
GPIO14 R4
GPIO15 E22
GPIO24 R3
GPIO25 D20
GPIO35 / SATAREQ# AD21
GPIO38 AD20
GPIO39 AE20
SMBCLK
C22
SMBDATA
B22
LINKALERT#
A26
SMLINK0
B25
SMLINK1
A25
GPIO18 / STPPCI#
AC20
GPIO20 / STPCPU#
AF21
WAKE#
F20
SERIRQ
AH21
THRM#
AF20
GPIO6
AC21
GPIO7
AC18
GPIO8
E21
R67
0_0402_5%
1 2
R600 10K_0402_5%
1 2
U11C
SN74LVC08APW_TSSOP14
A9
B10
O
8
P14
G
7
R643
100K_0402_5%
1 2
C1330.1U_0402_16V4Z 12
R68 10K_0402_5%@
1 2
R99 47_0402_5%SPI@
1 2
R633
10K_0402_5%
1 2
R596 10K_0402_5%
1 2
R638
10K_0402_5%
1 2
R63410K_0402_5%
1 2 R599
100K_0402_5%@
12
G
D
S
Q8
BSS138_SOT23
2
13 T28PAD
PCI-EXPRESS
DIRECT MEDIA INTERFACE
USB
SPI
U10D
ICH7M_B0_BGA652
SPI_CLK
R2
SPI_CS#
P6
SPI_ARB
P1
SPI_MOSI
P5
SPI_MISO
P2
DMI0RXN V26
DMI0RXP V25
DMI0TXN U28
DMI0TXP U27
DMI1RXN Y26
DMI1RXP Y25
DMI1TXN W28
DMI1TXP W27
DMI2RXN AB26
DMI2RXP AB25
DMI2TXN AA28
DMI2TXP AA27
DMI3RXN AD25
DMI3RXP AD24
DMI3TXN AC28
DMI3TXP AC27
DMI_CLKN AE28
DMI_CLKP AE27
DMI_ZCOMP C25
DMI_IRCOMP D25
PERn1
F26
PERp1
F25
PETn1
E28
PETp1
E27
PERn2
H26
PERp2
H25
PETn2
G28
PETp2
G27
PERn3
K26
PERp3
K25
PETn3
J28
PETp3
J27
PERn4
M26
PERp4
M25
PETn4
L28
PETp4
L27
PERn5
P26
PERp5
P25
PETn5
N28
PETp5
N27
PERn6
T25
PERp6
T24
PETn6
R28
PETp6
R27
OC0#
D3
OC1#
C4
OC2#
D5
OC3#
D4
OC4#
E5
OC5# / GPIO29
C3
OC6# / GPIO30
A2
OC7# / GPIO31
B3
USBP0N F1
USBP0P F2
USBP1N G4
USBP1P G3
USBP2N H1
USBP2P H2
USBP3N J4
USBP3P J3
USBP4N K1
USBP4P K2
USBP5N L4
USBP5P L5
USBP6N M1
USBP6P M2
USBP7N N4
USBP7P N3
USBRBIAS# D2
USBRBIAS D1
R63 10K_0402_5%
1 2
C1290.1U_0402_16V4Z 12
R6020_0402_5%@12
R79
2.2K_0402_5%@
12
T30PAD
R72
100_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
ICH_V5REF_SUS
ICH_V5REF_RUN
ICH_V5REF_RUN
ICH_V5REF_SUS
ICH_AA2
ICH_Y7
ICH_K7
ICH_C28
ICH_G20
ICH_SUSLAN
+1.5VS_DMIPLL
+3VALW
+VCCP
+3VS
+1.5VS
+RTCVCC
+3VALW
+1.5VS
+1.5VS
+3VS+5VS
+3VALW+5VALW
+3VS
+1.5VS
+1.5VS
+3VS
+3VS
+3VS
+3VALW
+3VALW
+1.5VS
+VCCP
+1.5VS
+1.5VS_DMIPLL+1.5VS_DMIPLLR
+3VS
+3VS
+1.5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
ICH7-M(4/4)
2252Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place closely pin
D28,T28,AD28.
Place closely pin AG28 within 100mlis.
Place closely pin AG5.
Place closely pin AG9.
9/15
9/15
C503
10U_0805_10V4Z
1
2
+
C131
220U 6.3V M
1
2
U10F
ICH7M_B0_BGA652
V5REF[1]
G10
V5REF[2]
AD17
V5REF_Sus
F6
Vcc1_5_B[1]
AA22
Vcc1_5_B[2]
AA23
Vcc1_5_B[3]
AB22
Vcc1_5_B[4]
AB23
Vcc1_5_B[5]
AC23
Vcc1_5_B[6]
AC24
Vcc1_5_B[7]
AC25
Vcc1_5_B[8]
AC26
Vcc1_5_B[9]
AD26
Vcc1_5_B[10]
AD27
Vcc1_5_B[11]
AD28
Vcc1_5_B[12]
D26
Vcc1_5_B[13]
D27
Vcc1_5_B[14]
D28
Vcc1_5_B[15]
E24
Vcc1_5_B[16]
E25
Vcc1_5_B[17]
E26
Vcc1_5_B[18]
F23
Vcc1_5_B[19]
F24
Vcc1_5_B[20]
G22
Vcc1_5_B[21]
G23
Vcc1_5_B[22]
H22
Vcc1_5_B[23]
H23
Vcc1_5_B[24]
J22
Vcc1_5_B[25]
J23
Vcc1_5_B[26]
K22
Vcc1_5_B[27]
K23
Vcc1_5_B[28]
L22
Vcc1_5_B[29]
L23
Vcc1_5_B[30]
M22
Vcc1_5_B[31]
M23
Vcc1_5_B[32]
N22
Vcc1_5_B[33]
N23
Vcc1_5_B[34]
P22
Vcc1_5_B[35]
P23
Vcc1_5_B[36]
R22
Vcc1_5_B[37]
R23
Vcc1_5_B[38]
R24
Vcc1_5_B[39]
R25
Vcc1_5_B[41]
T22
Vcc1_5_B[42]
T23
Vcc1_5_B[43]
T26
Vcc1_5_B[44]
T27
Vcc1_5_B[45]
T28
Vcc1_5_B[46]
U22
Vcc1_5_B[47]
U23
Vcc1_5_B[48]
V22
Vcc1_5_B[49]
V23
Vcc1_5_B[50]
W22
Vcc1_5_B[52]
Y22
Vcc1_5_B[53]
Y23
Vcc1_5_B[51]
W23
Vcc1_5_B[40]
R26
Vcc3_3[1]
B27
VccDMIPLL
AG28
VccSATAPLL
AD2
Vcc3_3[2]
AH11
Vcc1_05[1] L11
Vcc1_05[2] L12
Vcc1_05[3] L14
Vcc1_05[4] L16
Vcc1_05[6] L18
Vcc1_05[5] L17
Vcc1_05[7] M11
Vcc1_05[8] M18
Vcc1_05[9] P11
Vcc1_05[10] P18
Vcc1_05[11] T11
Vcc1_05[12] T18
Vcc1_05[13] U11
Vcc1_05[14] U18
Vcc1_05[15] V11
Vcc1_05[16] V12
Vcc1_05[17] V14
Vcc1_05[18] V16
Vcc1_05[19] V17
Vcc1_05[20] V18
Vcc3_3 / VccHDA U6
VccSus3_3/VccSusHDA R7
V_CPU_IO[1] AE23
V_CPU_IO[2] AE26
V_CPU_IO[3] AH26
Vcc3_3[3] AA7
Vcc3_3[4] AB12
Vcc3_3[5] AB20
Vcc3_3[6] AC16
Vcc3_3[7] AD13
Vcc3_3[8] AD18
Vcc3_3[9] AG12
Vcc3_3[10] AG15
Vcc3_3[11] AG19
Vcc3_3[12] A5
Vcc3_3[14] B16
Vcc3_3[15] B7
Vcc3_3[16] C10
Vcc3_3[13] B13
Vcc3_3[17] D15
Vcc3_3[18] F9
Vcc3_3[19] G11
Vcc3_3[20] G12
VccRTC W5
VccSus3_3[1] P7
VccSus3_3[2] A24
VccSus3_3[4] D19
VccSus3_3[5] D22
VccSus3_3[6] G19
VccSus3_3[3] C24
VccSus3_3[7] K3
VccSus3_3[8] K4
VccSus3_3[9] K5
VccSus3_3[10] K6
VccSus3_3[11] L1
Vcc1_5_A[19] AB17
Vcc1_5_A[20] AC17
Vcc1_5_A[21] T7
Vcc1_5_A[22] F17
Vcc1_5_A[23] G17
Vcc1_5_A[24] AB8
Vcc1_5_A[25] AC8
VccSus1_05[1] K7
Vcc1_5_A[1]
AB7
Vcc1_5_A[2]
AC6
Vcc1_5_A[3]
AC7
Vcc1_5_A[4]
AD6
Vcc1_5_A[5]
AE6
Vcc1_5_A[6]
AF5
Vcc1_5_A[7]
AF6
Vcc1_5_A[8]
AG5
Vcc1_5_A[9]
AH5
Vcc1_5_A[10]
AB10
Vcc1_5_A[11]
AB9
Vcc1_5_A[12]
AC10
Vcc1_5_A[13]
AD10
Vcc1_5_A[14]
AE10
Vcc1_5_A[15]
AF10
Vcc1_5_A[16]
AF9
Vcc1_5_A[17]
AG9
Vcc1_5_A[18]
AH9
VccSus3_3[19]
E3
VccUSBPLL
C1
VccSus1_05/VccLAN1_05[1]
AA2
VccSus1_05/VccLAN1_05[2]
Y7
VccSus3_3/VccLAN3_3[1]
V5
VccSus3_3/VccLAN3_3[2]
V1
VccSus3_3/VccLAN3_3[3]
W2
VccSus3_3/VccLAN3_3[4]
W7
Vcc3_3[21] G16
VccSus3_3[12] L2
VccSus3_3[13] L3
VccSus3_3[14] L6
VccSus3_3[15] L7
VccSus3_3[16] M6
VccSus3_3[17] M7
VccSus3_3[18] N7
VccSus1_05[2] C28
VccSus1_05[3] G20
Vcc1_5_A[26] A1
Vcc1_5_A[27] H6
Vcc1_5_A[28] H7
Vcc1_5_A[29] J6
Vcc1_5_A[30] J7
C506
0.1U_0402_16V4Z
1
2
C512
0.1U_0402_16V4Z
1 2
J18
PAD-SHORT 2x2m
21
C527
0.1U_0402_16V4Z
1
2
+
C132
220U 6.3V M
1
2
T17PAD
R584
0.5_0805_1%
1 2
C504
0.01U_0402_16V7K
1
2
C525
0.1U_0402_16V4Z
1
2
U10E
ICH7M_B0_BGA652
VSS[0]
A4
VSS[1]
A23
VSS[2]
B1
VSS[3]
B8
VSS[4]
B11
VSS[5]
B14
VSS[6]
B17
VSS[7]
B20
VSS[8]
B26
VSS[9]
B28
VSS[10]
C2
VSS[11]
C6
VSS[12]
C27
VSS[13]
D10
VSS[14]
D13
VSS[15]
D18
VSS[16]
D21
VSS[17]
D24
VSS[18]
E1
VSS[19]
E2
VSS[21]
E4
VSS[22]
E8
VSS[23]
E15
VSS[24]
F3
VSS[25]
F4
VSS[26]
F5
VSS[27]
F12
VSS[28]
F27
VSS[29]
F28
VSS[30]
G1
VSS[31]
G2
VSS[32]
G5
VSS[33]
G6
VSS[34]
G9
VSS[35]
G14
VSS[36]
G18
VSS[37]
G21
VSS[38]
G24
VSS[39]
G25
VSS[40]
G26
VSS[41]
H3
VSS[42]
H4
VSS[43]
H5
VSS[44]
H24
VSS[45]
H27
VSS[46]
H28
VSS[47]
J1
VSS[48]
J2
VSS[49]
J5
VSS[50]
J24
VSS[51]
J25
VSS[52]
J26
VSS[53]
K24
VSS[54]
K27
VSS[55]
K28
VSS[56]
L13
VSS[57]
L15
VSS[58]
L24
VSS[59]
L25
VSS[60]
L26
VSS[61]
M3
VSS[62]
M4
VSS[63]
M5
VSS[64]
M12
VSS[65]
M13
VSS[66]
M14
VSS[67]
M15
VSS[68]
M16
VSS[69]
M17
VSS[70]
M24
VSS[71]
M27
VSS[72]
M28
VSS[73]
N1
VSS[74]
N2
VSS[75]
N5
VSS[76]
N6
VSS[77]
N11
VSS[78]
N12
VSS[79]
N13
VSS[80]
N14
VSS[81]
N15
VSS[82]
N16
VSS[83]
N17
VSS[84]
N18
VSS[85]
N24
VSS[86]
N25
VSS[87]
N26
VSS[88]
P3
VSS[89]
P4
VSS[90]
P12
VSS[91]
P13
VSS[92]
P14
VSS[93]
P15
VSS[94]
P16
VSS[95]
P17
VSS[96]
P24
VSS[97]
P27
VSS[98] P28
VSS[99] R1
VSS[100] R11
VSS[101] R12
VSS[102] R13
VSS[103] R14
VSS[104] R15
VSS[105] R16
VSS[106] R17
VSS[107] R18
VSS[108] T6
VSS[109] T12
VSS[110] T13
VSS[111] T14
VSS[112] T15
VSS[113] T16
VSS[114] T17
VSS[115] U4
VSS[116] U12
VSS[117] U13
VSS[118] U14
VSS[119] U15
VSS[120] U16
VSS[121] U17
VSS[122] U24
VSS[123] U25
VSS[124] U26
VSS[125] V2
VSS[126] V13
VSS[127] V15
VSS[128] V24
VSS[129] V27
VSS[130] V28
VSS[131] W6
VSS[132] W24
VSS[133] W25
VSS[134] W26
VSS[135] Y3
VSS[136] Y24
VSS[137] Y27
VSS[138] Y28
VSS[139] AA1
VSS[140] AA24
VSS[141] AA25
VSS[142] AA26
VSS[143] AB4
VSS[144] AB6
VSS[145] AB11
VSS[146] AB14
VSS[147] AB16
VSS[148] AB19
VSS[149] AB21
VSS[150] AB24
VSS[151] AB27
VSS[152] AB28
VSS[153] AC2
VSS[154] AC5
VSS[155] AC9
VSS[156] AC11
VSS[157] AD1
VSS[158] AD3
VSS[159] AD4
VSS[160] AD7
VSS[161] AD8
VSS[162] AD11
VSS[163] AD15
VSS[164] AD19
VSS[165] AD23
VSS[166] AE2
VSS[167] AE4
VSS[168] AE8
VSS[169] AE11
VSS[170] AE13
VSS[171] AE18
VSS[172] AE21
VSS[173] AE24
VSS[174] AE25
VSS[175] AF2
VSS[176] AF4
VSS[177] AF8
VSS[178] AF11
VSS[179] AF27
VSS[180] AF28
VSS[181] AG1
VSS[182] AG3
VSS[183] AG7
VSS[184] AG11
VSS[185] AG14
VSS[186] AG17
VSS[187] AG20
VSS[188] AG25
VSS[189] AH1
VSS[190] AH3
VSS[191] AH7
VSS[192] AH12
VSS[193] AH23
VSS[194] AH27
C146
1U_0603_10V4Z
1
2
C536
0.1U_0402_16V4Z
1
2
C518
0.1U_0402_16V4Z
1
2
C5300.1U_0402_16V4Z
1 2
C517
0.1U_0402_16V4Z
1
2
C532
0.1U_0402_16V4Z
1
2
J17
PAD-No SHORT 2x2m
21
D15
CH751H-40_SC76
21
C522
0.1U_0402_16V4Z
1
2
C520
4.7U_0805_10V4Z
1 2
C529
0.1U_0402_16V4Z
1
2
R90
10_0402_5%
12
C531
0.1U_0402_16V4Z
1
2
C508
0.1U_0402_16V4Z
1
2
D17
CH751H-40_SC76
21
T13PAD
C519
1U_0603_10V4Z
1
2
T18PAD
C505
0.1U_0402_16V4Z
1
2
C528
0.1U_0402_16V4Z
1
2
C516
0.1U_0402_16V4Z
1
2
C534
0.1U_0402_16V4Z
1
2
C535
0.1U_0402_16V4Z
1
2
C511
0.1U_0402_16V4Z
1
2
C523
0.1U_0402_16V4Z
1 2
C543
0.1U_0402_16V4Z
1
2
C515
0.1U_0402_16V4Z
1
2
C537
0.1U_0402_16V4Z
1
2
T15PAD
T19PAD
C538
0.1U_0402_16V4Z
1
2
C521
0.1U_0402_16V4Z
1
2
C540
0.1U_0402_16V4Z
1
2
R585
0_0805_5%
1 2
C533
0.1U_0402_16V4Z
1
2
C507
0.1U_0402_16V4Z
1
2
R614
100_0402_5%
12
C513
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
11
22
33
44
+VDDPLL+VDD_PLL
+VDDPLL33+VDD_PLL33
XTPB0-
XTPA0-
XTPB0+
XTPBIAS0
XTPA0+
XTPB1+
XTPBIAS1
XTPB1-
X_OUT
X_OUT
MC_PWRON#
SD_CD#
SM_CD#
MS_CD#
MSD2_SDD2_SMD2
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSCLK_SDCLK_SMELWP#
MSD3_SDD3_SMD3
MSBS_SDCMD_SMWE#
SDD1_SMD5
SDD0_SMD4
SDD3_SMD7
SDWP#_SMCE#
SDCMD_SMALE
SDD2_SMD6
SDCLK_SMRE#
SMCLE
SC_CD#
SC_RST
SC_DATA
SC_OC#
+VDDPLL
FM_LED#
PCM_SPK
GRST#
PRST#
CLK_PCI_PCM
CB_PME#
PCI_AD22
PCI_CBE#2
PCI_CBE#0
PCI_CBE#3
PCI_CBE#1
PCI_AD3
PCI_AD2
PCI_AD26
PCI_AD5
PCI_AD12
PCI_AD7
PCI_AD20
PCI_AD29
PCI_AD24
PCI_AD30
PCI_AD14
PCI_AD19
PCI_AD0
PCI_AD27
PCI_AD25
PCI_AD28
PCI_AD21
PCI_AD15
PCI_AD17
PCI_AD1
PCI_AD16
PCI_AD22
PCI_AD31
PCI_AD4
PCI_AD18
PCI_AD8
PCI_AD6
PCI_AD11
PCI_AD13
PCI_AD10
PCI_AD9
PCI_AD23
PCI_AD[0..31]
PCI_CBE#[0..3]
PWR_CTRL_1/SM_R/B#
SC_RFU
PWR_CTRL_1/SM_R/B#SM_RB#
SC_FCB
SM_PHYS_WP#
SM_RB#/SC_RFU
SDWP#_SMCE#
SM_RB#
MC_PWRON#
SD_CD#MS_CD#
FM_LED#
SM_CD#
SD_CD#
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MSBS_SDCMD_SMWE#
MS_CD#
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD3_SMD7
SDD2_SMD6
SDWP#_SMCE#
SD_CD#
XD_CD#
SM_RB#
SDCLK_SMRE#
SDCMD_SMALE
SMCLE
MSCLK_SDCLK_SMELWP#
SM_CD#
SM_CD#
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
SDWP#_SMCE#
CB_PME#
XTPB0+
XTPA0-
XTPBIAS1
XTPB1+
XTPB1-
XTPBIAS0
XTPA0+
XTPB0-
MC_PWRON#
SM_RB#/SC_RFU
CLK_PCI_PCM
SM_CD#XD_CD#
XD_CD#/SM_PHYS_WP#
GRST#PRST#
SM_PHYS_WP#
MSBS_SDCMD_SMWE#
SDCLK_SMRE#
MSBS_SDCMD_SMWE#
PCM_SPK
X_IN
X_IN
SM_PHYS_WP#/SC_FCB
SM_PHYS_WP#/SC_FCB
SC_CLK SC_CLK_R
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0
MSD2_SDD2_SMD2
MSCLK_SDCLK_SMELWP#
MSBS_SDCMD_SMWE#
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
MSD3_SDD3_SMD3
SC_DATA24
SC_CD#24
SC_RST24
PCI_PIRQE#19
PCI_PIRQC#19
PCI_PIRQD#19
PCI_PIRQG#19
SIRQ21,31,32,33
PM_CLKRUN#21,31,32,33
PCM_SPK28
PLT_RST#7,19,20,21,25,27,32,33
CLK_PCI_PCM15
PCI_RST#19,24
PCI_STOP#19
PCI_TRDY#19
PCI_PAR19
PCI_IRDY#19
PCI_PERR#19
PCI_REQ2#19
PCI_GNT2#19
PCI_DEVSEL#19
PCI_SERR#19,33
PCI_FRAME#19
PCI_AD[0..31]19
PCI_CBE#[0..3]19
SC_RFU24
SC_FCB24
PCI_PME#19
XD_CD#/SM_PHYS_WP#24
SC_CLK24
+3VS_CBVCCP +3VS
+3VS
+3VS_CBPLL
+3VS
+3VS
+3VS
+SC_PWR
+3VS
+VCC_MS +VCC_SD +VCC_MS +VCC_SM_XD
+3VS
+3VS +3VS
+VCC_SM_XD
+VCC_MS+VCC_SM_XD
+3VS
+3VS+VCC_MS+3VS
+VCC_MS +VCC_SD
+VCC_SD
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
TI PCI7612 PCI/CardReader
2352Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
L
CLOSE TO CHIP
L
CLOSE TO CHIP
9/6
L
Keep +VDD_PLL33/+VDDPLL33/+VDD_PLL
/+VDDPLL at least 10 mils
9/10
9/10
L
Place the parts close to JP41
R1440_0402_5% 12
R200
1K_0402_5%
1 2
R231
43K_0402_5%
1 2
R164
10K_0402_5%
1 2
R149
10_0402_5%@
12
R148
10K_0402_5%@
12
R1230_0402_5%
1 2
C227
10U_0805_10V4Z
1
2
R13010K_0402_5%@
C168
15P_0402_50V8J@
1
2
R142 0_0402_5%7611@
1 2
R229
0_0805_5%
1 2
R165
10K_0402_5%
1 2
G
D
S
Q22
2N7002_SOT23
2
13
R230
4.7K_0402_5%@1 2
R237
1M_0402_5%@
JP17
AMP_440168-2
1
2
3
4
R136 0_0402_5%@1 2
R153 0_0402_5%7612@
1 2
C1540.01U_0402_16V7K
12
R1190_0402_5%
1 2
C2341U_0603_10V4Z
1
2
R124
0_0402_5%
1 2
5 IN 1 CONN
JP24
TAITW_R007-010-N3
SM_WP-IN / XD_WP-IN
35
SM-D4 / XD-D4
21
MS-DATA3 18
MS-DATA0 15
SD-DAT2 12
SD-DAT0 7
SD-CMD 10
MS-DATA1 14
SM-D6 / XD-D6
23
SD-DAT3 11
SD-DAT1 6
SD-WP-SW 5
#SM-ALE / XD-ALE
37
SM-D0 / XD-D0
34
SD_CLK 8
SM-D2 / XD-D2
32
SM_-VCC / XD_-VCC
29
MS-INS 17
MS-DATA2 16
MS-SCLK 19
SM-LVD
25
#SM_-RE / XD_-RE
27 MS-BS 13
SM-D5 / XD-D5
22
#SM_-CD
30
SM-D7 / XD-D7
24
SM-D1 / XD-D1
33
#SM_-CE / XD_-CE
28
#SM_R/-B / XD_R/-B
26
SM-D3 / XD-D3
31
SD-VCC 9
#SM_-WE / XD_-WE
36
MS-VCC 20
SM-CD-COM
2
SM-CLE / XD-CLE
38
GND 1
SD-CD-SW 42
SD-CD-COM 41
XD-VCC 40
XD-CD 39
SM-CD-SW
3
N/C 4
SM-WP-SW
43
GND 44
J7
PAD-SHORT 2x2m
2 1
R173
0_0805_5%
1 2
C15210U_0805_10V4Z
12
D22RB751V_SOD323@
2 1
R141 0_0402_5%
1 2
R151
43K_0402_5%
G
D
S
Q21
SI2301BDS_SOT23
2
13
R128
47K_0402_5% @
1 2
R154
47K_0402_5% @
1 2
R117
0_0402_5%
1 2
C165
10U_0805_10V4Z
1
2
R125
22K_0402_5%
1 2
R159 0_0402_5%7612@
1 2
R140 0_0402_5%
1 2
R201
56.2_0603_1%
12
R146220_0402_5% 12 R134220_0402_5% 12
G
D
S
Q20
2N7002_SOT23@
2
13
PCI7612/7412
U16B
PCI7612ZHK_PBGA257
SPKROUT H3
SUSPEND# J5
VR_EN# K2
SCL G2
SDA G3
VSSPLL
R17
VDDPLL_33 U19
VR_PORT K1
VR_PORT K19
VCCP P1
VCCP W8
VDDPLL_15 P15
R0
T18
R1
T19
XO
R18
XI
R19
SC_CD#
F3
SC_DATA
E1
SC_CLK
E2
SC_PWR_CTRL
G5 SC_OC#
F2
SC_VCC_5V
G6 SC_RST
F5
SM_CLE/SC_GPIO0
B4
SD_CLK/SM_RE#/SC_GPIO1
A4
SD_CMD/SM_ALE/SC_GPIO2
C5
SD_DAT0/SM_D4/SC_GPIO6
C6
SD_DAT1/SM_D5/SC_GPIO5
A5
SD_DAT3/SM_D7/SC_GPIO3
E6
SD_WP/SM_CE#
E7
MS_CLK/SD_CLK/SM_EL_WP#
A7
MS_BS/SD_CMD/SM_WE#
E8
MS_DATA3/SD_DAT3/SM_D3
B6
MS_DATA2/SD_DAT2/SM_D2
A6
MS_DATA1/SD_DAT1/SM_D1
C7
MS_SDIO(DATA0)/SD_DAT0/SM_D0
B7
SD_CD#
E9
MS_CD#
A8
SM_CD#
B8
MC_PWR_CTRL_0
C8
MC_PWR_CTRL_1/SM_R/B#
F8
PHY_TEST_MA
P17
TPBIAS1
W17
TPA1P
V16
TPA1N
W16
TPB1P
V15
TPB1N
W15
TPBIAS0
R13
TPA0P
V14
TPA0N
W14
TPB0P
V13
TPB0N
W13
AGND
R14
AGND
U13
AGND
U14
AVDD_33 P13
AVDD_33 P14
AVDD_33 U15
AD31 M1
AD30 M2
AD29 M3
AD28 M6
AD27 M5
AD26 N1
AD25 N2
AD24 N3
AD23 P3
AD22 R1
AD21 R2
AD20 P5
AD19 R3
AD18 T1
AD17 T2
AD16 W4
AD15 W7
AD14 R8
AD13 U8
AD12 V8
AD11 W9
AD10 V9
AD9 U9
AD8 R9
AD7 V10
AD6 U10
AD5 R10
AD4 W11
AD3 V11
AD2 U11
AD1 P11
AD0 R11
C/BE3# P2
C/BE2# U5
C/BE1# V7
C/BE0# W10
PAR U7
FRAME# R6
TRDY# W5
IRDY# V5
STOP# V6
DEVSEL# U6
IDSEL N5
PERR# R7
SERR# W6
REQ# L3
GNT# L2
MFUNC0 G1
MFUNC1 H5
MFUNC2 H2
MFUNC3 H1
MFUNC4 J1
PCLK L1
PRST# K3
GRST# K5
RI_OUT#/PME# L5
MFUNC5 J2
MFUNC6 J3
SC_FCB
E3
SC_RFU
D1
SD_DAT2/SM_D6/SC_GPIO4
B5
TEST0
P12
C242
10P_0402_50V8J
1 2
R1450_0402_5% 12
C178
10U_0805_10V4Z
1
2
L12
CHB1608U301_0603
1 2
C219
1U_0603_10V4Z
1
2
R127
10K_0402_5%
1 2
C189
270P_0603_50V8J
1
2
R1210_0402_5%
1 2
R187
56.2_0603_1%
12
R12910K_0402_5%@
R114
100K_0402_5%
1 2
C212
1U_0603_10V4Z
1
2
C241
10P_0402_50V8J
1 2
R1430_0402_5%
1 2
C2320.1U_0402_16V4Z
12
R182 0_0402_5%7611@
1 2
G
D
S
Q27
2N7002_SOT23
2
13
R131 0_0402_5%7612@
1 2
C169 1U_0603_10V4Z
1
2
C185
0.1U_0402_16V4Z
1
2
D21RB751V_SOD323@
2 1
G
D
S
Q30
2N7002_SOT23@
2
13
G
D
S
Q28
SI2301BDS_SOT23
2
13
Y2
24.576MHZ_16P_1BG24576CK1A
12
U12
TPS2061IDGN_MSOP8~N
GND
1
IN
2
OC# 5
OUT 6
OUT 8
IN
3
EN#
4
OUT 7
R91
10K_0402_5%
1 2
R116
33_0402_5%7611@1 2
C207
1U_0603_10V4Z
1
2
R115
100K_0402_5%
1 2
R195
56.2_0603_1%
12
R1320_0402_5% 12
R1200_0402_5%
1 2
R150 0_0402_5%
1 2
R161 100_0402_5%
12
R193
1K_0402_5%
1 2
C164
0.1U_0402_16V4Z
1
2
R1330_0402_5% 12
R2286.34K_0402_1%
1 2
R1220_0402_5%
1 2
R175 22_0402_5%
1 2
C230
0.01U_0402_16V7K
1
2
J6
PAD-No SHORT 2x2m
2 1
R183
56.2_0603_1%
12
R126
100K_0402_5%
1 2
C174
0.1U_0402_16V4Z
1
2
R135220_0402_5% 12
R1370_0402_5% 12
R186
5.1K_0603_1%
12
R152 0_0402_5%@
1 2
R1180_0402_5%
1 2
A B C D
D
E
E
11
22
33
44
S1_A9
S1_D0
S1_A0
S1_IORD#
S1_D5
S1_A2
S1_A5
S1_A17
S1_D3
S1_IOWR#
S1_D12
S1_D8
S1_D11
S1_D13
S1_A4
S1_A1
S1_A25
S1_A7
S1_A3
S1_D10
S1_D9
S1_D1
S1_CE2#
S1_A10
S1_A24
S1_A11
S1_A6
S1_D7
S1_D4
S1_D6
S1_OE#
S1_D15
S1_A12
S1_A8
S1_REG#
S1_CE1#
S1_A23
S1_A13
S1_A15
S1_BVD1
S1_A19
S1_RDY#
S1_WAIT#
S1_A20
S1_A21
S1_INPACK#
S1_WE#
S1_A14
S1_WP
S1_A16S1_A16_C
S1_A22
S1_BVD2
S1_RST
S1_CD1#
S1_VS1
S1_CD2#
S1_VS2
S1_D14
S1_D2
S1_A18
CB_CLK
CB_DAT
CB_LATCH
CB_CLK
CB_LATCH
CB_DAT
PCI_RST#
S1_CD2#
S1_CD1#
CPS
CLK_48M_CB
CPS
CLK_48M_CB
XD_CD#/SM_PHYS_WP#
S1_A6
S1_A12
S1_A3
S1_D5
S1_WE#
S1_A13
S1_D4
S1_D6
S1_A8
S1_A4
S1_A16_C
S1_A9
S1_A15
S1_A10
S1_D3
S1_OE#
S1_A7
S1_D7
S1_A5
S1_CE1#
S1_A11
S1_RDY#
S1_A14
S1_WAIT#
S1_CD1#
S1_D14
S1_INPACK#
S1_A24
S1_VS2
S1_A19
S1_D15
S1_IORD#
S1_A21
S1_A20
S1_VS1
S1_CE2#
S1_A17
S1_A18
S1_A25
S1_A23
S1_IOWR#
S1_RST
S1_D13
S1_D12
S1_A22
S1_D11
S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
SC_RST
SC_CLK
SC_FCB
S1_A1
S1_REG#
S1_A2
SC_RFU
SC_DATA
SC_CD#
SC_CLK SC_DATA SC_RST
CLK_48M_CB15
XD_CD#/SM_PHYS_WP#23
CB_CLK33
SC_RST23
SC_CLK23
SC_FCB23
SC_RFU23
SC_DATA23
SC_CD#23
PCI_RST#19,23
+S1_VCC+3VS
+5VS
+S1_VCC
+3VS
+S1_VPP
+SC_PWR
+S1_VCC
+S1_VPP
+3VS
+3VS
+SC_PWR
+S1_VCC
+S1_VPP
+SC_PWR
+SC_PWR
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
TI PCI7612 CB/SmartCard
2452Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Near to PCMCIA slot.
9/8
L
Place the parts close to JP9
R176
22K_0402_5%@
12
C203
0.1U_0402_16V4Z
1
2
C187
0.1U_0402_16V4Z
1
2
C201
10U_0805_10V4Z
1
2
U19
TPS2224ADBR_HTSSOP24
5V 1
5V 2
DATA
3
CLOCK
4
LATCH
5
NC 6
12V 7
AVPP
8
AVCC
9
AVCC
10 GND 11
RESET#
12
5V 24
NC 23
NC 22
SHDN#
21
12V 20
BVPP
19
BVCC
18 BVCC
17
NC 16
OC#
15 3.3V 14
3.3V 13
C170
0.1U_0402_16V4Z
1
2
C211
10U_0805_10V4Z
1
2
C218
0.1U_0402_16V4Z
1
2
R160 43K_0402_5%
1 2
C199
100P_0402_50V8J@
1
2
C184
470P_0402_50V7K@
1
2
C179
0.1U_0402_16V4Z
1
2
C195
0.1U_0402_16V4Z
1
2
R147
10_0402_5%@
12
R189 4.7K_0402_5%
1 2
R227
33_0402_5%
1 2
R169
22K_0402_5%@
12
PCI7612/7412
U16A
PCI7612ZHK_PBGA257
CAUDIO/BVD2(SPKR#)
B12
A_USB_EN#
E10
CAD31/D10
C10
CAD30/D9
A10
CAD29/D1
F11
CAD28/D8
E11
CAD27/D0
C11
CAD26/A0
B13
CAD25/A1
C13
CAD24/A2
A14
CAD23/A3
B14
CAD22/A4
B15
CAD21/A5
E14
CAD20/A6
A16
CAD19/A25
D19
CAD18/A7
E17
CAD17/A24
F15
CAD16/A17
H19
CAD15/IOWR#
J17
CAD14/A9
J15
CAD13/IORD#
J18
CAD12/A11
K15
CAD11/OE#
K17
CAD10/CE2#
K18
CAD9/A10
L15
CAD8/D15
L18
CAD7/D7
L19
CAD6/D13
M17
CAD5/D6
M18
CAD4/D12
N19
CAD3/D5
M15
CAD2/D11
N17
CAD1/D4
N18
CAD0/D3
P19
CC/BE3#/REG#
E13
CC/BE2#/A12
E18
CC/BE1#/A8
H18
CC/BE0#/CE1#
L17
CPAR/A13
H14
CFRAME#/A23
E19
CIRDY#/A15
F17
CSTOP#/A20
G18
CDEVSEL#/A21
F19
CBLOCK#/A19
H15
CPERR#/A14
G19
CSERR#/WAIT#
C12
CREQ#/INPACK#
C14
CGNT#/WE#
G17
CSTSCHG/BVD1(STSCHG#/RI#)
A12
CCLKRUN#/WP(IOIS16#)
A11
CCLK/A16
F18
CINT#/READY(IREQ#)
E12
CCD1#/CD1#
N15
CCD2#/CD2#
B11
CVS1/VS1#
A13
CVS2/VS2#
B16
GND
F7
GND
F10
GND
F13
GND
G14
GND
H6
GND
K6
GND
K14
GND
M14
GND
N6
GND
P7
GND
P9
VCC F6
VCC F9
VCC F12
VCC F14
VCC J6
VCC J14
VCC L6
VCC L14
VCC P6
VCC P8
VCC P10
VCCB A15
VCCB J19
NC A2
NC A17
NC A18
NC B1
NC B2
NC B3
NC B17
NC B18
NC B19
NC C1
NC C2
NC C3
NC C16
NC C17
NC C18
NC C19
NC D2
NC D3
NC D17
NC D18
NC N14
NC P18
NC T3
NC T17
NC U1
NC U2
NC U3
NC U4
NC U12
NC U16
NC U17
NC U18
NC V1
NC V2
NC V3
NC V4
NC V12
NC V17
NC V18
NC V19
NC W2
NC W3
NC W12
NC W18
DATA/VD2/VPPD1 B9
CLOCK/VD1/VCCD0# A9
LATCH/VD3/VPPD0 C9
CPS
R12
CLK_48
F1
CTRDY#/A22
G15
RSVD/D2 B10
RSVD/A18 H17
RSVD/D14 M19
RSVD/VD0/VCCD1# C4
XD_CD#/SM_PHYS_WP# A3
CRST#/RESET
C15
NC E5
C182
0.1U_0402_16V4Z
1
2
C210
0.1U_0402_16V4Z
1
2
R190
22K_0402_5%@
12
C228
0.1U_0402_16V4Z
1
2
C200
0.1U_0402_16V4Z
1
2
C258
0.1U_0402_16V4Z
1
2
R208
10K_0402_5%@
12
R168
22K_0402_5%@
12
C202
0.1U_0402_16V4Z
1
2
C180
56P_0402_50V8J@
1
2
R166 43K_0402_5%@
1 2
C229
0.1U_0402_16V4Z
1
2
C233
0.1U_0402_16V4Z
1
2
C235
10U_0805_10V4Z
1
2
C166
10P_0402_50V8J@
1
2
C231
100P_0402_50V8J
1 2
C197
100P_0402_50V8J
1 2
JP23
TYCO_1123088-1_LT
GND
75 GND
74 CD1#
73 D3
72 D11
71 D4
70 D12
69 D5
68 GND
67 D13
66 D6
65 D14
64 D7
63 D15
62 CE1#
61 CE2#
60 GND
59 A10
58 VS1#
57 OE#
56 IORD#
55 A11
54 IOWR#
53 A9
52 GND
51 A17
50 A8
49 A18
48 A13
47 A19
46 A14
45 A20
44 GND
43 WE#
42 A21
41 READY
40 A51/A17/VCC
39 NONE
38 A52/A18/VCCP
37 A16
36 A22
35 A15
34 GND
33 A23
32 A12
31 A24
30 A7
29 A25
28 A6
27 VS2#
26 GND
25 A5
24 RESET
23 A4
22 WAIT#
21 A3
20 INPACK#
19 A2
18 GND
17 REG#
16 A1
15 SPKR#
14 A0
13 STSCHG#
12 D0
11 D8
10 GND
9D1
8D9
7D2
6D10
5WP
4CD2#
3GND
2GND
1NONE 76
NONE 77
NONE 78
NONE 79
NONE 80
NONE 81
NONE 82
NONE 83
GND 84
NONE 85
NONE 86
NONE 87
NONE 88
NONE 89
NONE 90
NONE 91
GND 92
NONE 93
NONE 94
NONE 95
NONE 96
I/O 97
NONE 98
NONE 99
GND 100
VCC 101
NONE 102
NONE 103
NONE 104
NONE 105
RST 106
DET2 107
GND 108
VPP 109
CLK 110
NONE 111
GND 112
NONE 113
NONE 114
DET1 115
RFU4 116
NONE 117
GND 118
RFU8 119
NONE 120
NONE 121
NONE 122
NONE 123
NONE 124
NONE 125
GND 126
NONE 127
NONE 128
NONE 129
NONE 130
NONE 131
NONE 132
NONE 133
GND 134
NONE 135
NONE 136
NONE 137
NONE 138
NONE 139
NONE 140
NONE 141
GND 142
NONE 143
NONE 144
NONE 145
NONE 146
NONE 147
NONE 148
GND 149
GND 150
5 4 3 2
2
1
1
DD
CC
BB
AA
VAUX_1.2_CTL
REGSUP12
LOM_WAKE#
LP_EN#
LOM_LOW_PWR
CABLE_DETECT
5751_GPIO1
ICH_LAN_SMBDATA
ICH_LAN_SMBCLK
5751_EEDAT
5751_EECLK
ICH_LAN_SMBDATA
ICH_LAN_SMBCLK
LAN_ACT#
LANLINK_STATUS#
XTALI
XTALO
CLK_PCIE_LOM#
CLK_PCIE_LOM
LOM_WAKE#
PCIE_C_RXN1
PCIE_C_RXP1
REGSUP12
VAUX_1.2_CTL
LOM_LOW_PWR
LAN_TX1+
LAN_TX0+
LAN_TX2-
LAN_TX0-
LAN_TX1-
LAN_TX2+
LAN_TX3+
LAN_TX3-
5751_GPIO1
5751_EECLK
5751_EEDAT
ICH_SMBDATA
ICH_SMBCLK
ICH_LAN_SMBDATA
ICH_LAN_SMBCLKICH_SMBCLK
ICH_SMBDATA
LP_EN#
PLT_RST#_LAN
PLT_RST#_LAN
NIC_PD
NIC_PD
NIC_PD_N
NIC_PD#
NIC_PD
NIC_PD_N
NIC_PD_N
LANLINK_STATUS#
SLP_S3#18,21,27,28,29,33,35,36,40,43,44
ADP_PRES18,33,40,41,42,47
LP_EN#21
LOM_LOW_PWR21
CABLE_DETECT21,26
LAN_ACT#26,35
LANLINK_STATUS#26,35
CLK_PCIE_LOM#15
CLK_PCIE_LOM15
PCIE_TXP121
PCIE_TXN121
PCIE_RXN121
PCIE_RXP121
LAN_TX3+26
LAN_TX3-26
LAN_TX2+26
LAN_TX2-26
LAN_TX1+26
LAN_TX1-26
LAN_TX0+26
LAN_TX0-26
ICH_SMBDATA4,13,14,15,18,21,27
ICH_SMBCLK4,13,14,15,18,21,27
PLT_RST#7,19,20,21,23,27,32,33
NIC_PD26
LOM_PCIE_WAKE#21
CLKREQA#15,18
LANLINK_STATUS#_SB21
V_3P3_LAN
+3VALW
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
+3VALW
+3VS
V_2P5_LAN
V_3P3_LAN
V_2P5_LAN
V_3P3_LAN
V_1P2_LAN
V_3P3_LAN
+5VS
+3VS
V_3P3_LAN
V_1P2_LAN
+3VS V_3P3_LAN
V_3P3_LAN +3VS
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
+3VALW
V_3P3_LAN
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
BCM5753M
2552Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Layout Notice : Place as close
chip as possible.
L
Place close U6 pin M13
L
Place close U6 pin N13
CKT Notice : CABLE IN, CABLE_DETECT=0
CABLE OUT, CABLE_DETECT=1
L
Must having maximized
copper under pin 2 & 4 of Q13
Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC
5/16
9/7
11/15
9/7
9/13
11/14
11/21
11/21
11/21
11/21
11/18
11/18
11/18 11/18
11/21
11/23
R405
1K_0402_5%
12
R680
0_0402_5%@1 2
C352
0.1U_0402_16V4Z
1
2
R407
4.7K_0402_5%
1 2
R663
10K_0402_5%
12
R347200_0402_1%
12
R426
0_0402_5%@
1 2
J10
PAD-NO SHORT 2x2m
21
C364
10U_1206_6.3V6M@
1
2
R19
47K_0402_5%
12
R64810K_0402_5%@
1 2
R364
4.7K_0402_5%
12
R326
4.7K_0402_5%@
1 2
G
D
S
Q108
BSS84_SOT23@
2
13
C550
0.1U_0402_16V7K
1
2
G
D
S
Q5
2N7002_SOT23
2
13
R424
10K_0402_5%12
G
D
S
Q4
2N7002_SOT23
2
13
G
D
S
Q65
2N7002_SOT23@
2
13
R678
10K_0402_5%
12
C344
0.1U_0402_16V4Z
1 2
R373
1.2K_0402_1%
1 2
G
D
S
Q76
2N7002_SOT23@
2
13
R391
10K_0402_5%
1 2
U38
SN74LVC1G17DBVR_SOT23-5
O4
I
2
P5
G
3
NC 1
G
D
S
Q3
2N7002_SOT23
2
13
G
D
S
Q57
SI2301BDS_SOT23
2
1 3
R6550_0402_5%@
1 2
R3371K_0402_5%@
1 2
C304
4.7U_0805_10V4Z
1
2
R658
0_0402_5%@
12
C400
0.1U_0402_16V4Z
1
2
R3661K_0402_5%@
1 2
C334
27P_0402_50V8J
1
2
G
DS
Q782N7002_SOT23
2
1 3
C342
0.1U_0402_16V4Z
1 2
C358
0.1U_0402_16V4Z
1
2
C357
0.1U_0402_16V4Z
1
2
C309
0.1U_0402_16V4Z
1
2
R21
0_0402_5%@
12
R660
0_0402_5%@
12
R646
10K_0402_5%
12
R659
0_0402_5%
12
R335
4.7K_0402_5%
12
R3670_0402_5%
1 2
R3284.7K_0402_5%
12
R679
10K_0402_5%
1 2
U27
SN74LVC1G17DBVR_SOT23-5@
O
4I2
P5
G
3
NC
1
C308
0.1U_0402_16V4Z
1
2
R425
10K_0402_5%
12
R662121K_0402_1%
1 2
C307
0.1U_0402_16V4Z
1
2
C544
0.1U_0402_16V7K@
1
2
Y4
25MHZ_16P_XSL025000FK1H
1 2
G
D
S
Q66
2N7002_SOT23
2
13
R361
2.2K_0402_5%@
12
R20
4.7K_0402_5%
12
R668
0_0402_5%
1 2
R667
10K_0402_5%@12
R673
10K_0402_5%
12
U28
AT24C256_SO8
A0
1
A1
2
NC
3
GND
4
VCC 8
WP 7
SCL 6
SDA 5
R3360_0402_5%
1 2
D36
RB751V_SOD323 @
2 1
Media
Misc
BCM5753
Power
Hot Plug
PCI-ETEST
LED
Bias
Clock
Control
Support
Regulator
Control
U25A
BCM5753KFBG C0_FPBGA196~D
GPIO0_TST_CLKOUT
J10
GPIO1
J12
SMB_CLK
D9
SMB_DATA
D8
EECLK
H10
EEDATA
J11
SI
F11
SCLK
D10
SO
E10
CS#
D11
PWR_IND#
H2
ATTN_IND#
J2
ATTN_BTTN#
B3
LINKLED#
B10
SPD100LED#
C10
SPD1000LED#
B11
TRAFFICLED#
C9
XTALI
M10
XTALO
N10
REFCLK_SEL C4
TRD3+ C12
TRD3- C13
TRD2+ D12
TRD2- D13
TRD1+ E12
TRD1- E13
TRD0+ F12
TRD0- F13
LOW_PWR J5
REGSUP12 L13
REGCTL12 K12
REGSEN12 K13
REGOUT25 N13
REGSUP25 M13
PCIE_TXDN N4
PCIE_TXDP M4
PCIE_RXDN M8
PCIE_RXDP N8
WAKE# B5
REFCLK- M6
REFCLK+ N6
PCIE_TST D7
PERST# C2
RDAC B9
TCK C6
TDI G4
TDO C5
TMS F4
TRST# E5
R6540_0402_5%
1 2
G
D
S
Q107
BSS84_SOT23@
2
1 3
C303
0.1U_0402_16V4Z
1
2
R6570_0402_5%@
1 2
R330
0_0402_5%@
12
C300
10U_0805_6.3V6M
1
2
G
D
S
Q60
2N7002_SOT23@
2
13
R656 100K_0402_5%@1 2
R404
1K_0402_5%
12
+
C372
68U_B2_4VM
1
2
C396
0.1U_0402_16V4Z@
1
2
Q54
BCP69_SOT223
1
2
4
3
R661 0_0402_5%
1 2
C376
0.1U_0402_16V4Z
12
C331
27P_0402_50V8J
1
2
C379
0.1U_0402_16V4Z@
1 2
R406
1K_0402_5%
12
C306
4.7U_0805_10V4Z
1
2
R416
100K_0402_5%@
1 2
D341N4148_SOD80
1 2
C299
0.1U_0402_16V4Z
1
2
G
D
S
Q2
SI2301BDS_SOT23
2
13
R329
220K_0402_5%
12
R345
10K_0402_5%
12
R334
2.2K_0402_5%@
12
C366
4.7U_0805_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
MDO3-
MDO3+
LAN_TX3-
LAN_TX3+
LAN_TX2+
LAN_TX2-
LAN_TX1+
LAN_TX0+
LAN_TX0-
LAN_TX1-
MCT3
MCT2
LAN_TX0+
LAN_TX0-
TRM_CT
TRM_CT
TRM_CT
LAN_TX1-
LAN_TX1+
LAN_TX2-
LAN_TX2+
LAN_TX3-
LAN_TX3+
MDO2-
MDO2+
MDO0+
MDO0-
MDO1-
MDO1+
CABLE_DETECT
MDO2-
MDO2+
MDO1-
MDO1+
MDO0+
MDO0-
MDO3+
MDO3-
LAN_ACT#
LANLINK_STATUS#
LAN_AUXPWR
VMAINPRSNT
LAN_ACT#_R
LANLINK_STATUS#_R
MCT0
MCT1 VMAINPRSNT VMAINPRSNT_R
TRM_CT
LAN_TX3+25
LAN_TX0-25
LAN_TX1+25
LAN_TX3-25
LAN_TX2+25
LAN_TX1-25
LAN_TX0+25
LAN_TX2-25
CABLE_DETECT21,25
MDO2-35 MDO2+35
MDO1-35
MDO3-35 MDO3+35
MDO1+35
MDO0-35 MDO0+35
LANLINK_STATUS#25,35 LAN_ACT#25,35
PREP#21,35
NIC_PD25
V_3P3_LAN_LED
V_3P3_LAN V_3P3_LAN_LED
V_2P5_LAN V_1P2_LAN
AVDD1
XTALVDD
AVDD2
V_2P5_LAN
V_1P2_LAN
AVDDL
GPHY_PLLVDD
PCIE_PLLVDD
PCIE_SDS_VDD
V_2P5_LAN
V_1P2_LAN
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
AVDDL
AVDD2
AVDD1
GPHY_PLLVDD
PCIE_PLLVDD
V_2P5_LAN XTALVDD
PCIE_SDS_VDD
V_3P3_LAN
+3VS
V_2P5_LAN
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Magnetic & RJ45/RJ11
2652Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Layout Notice : Place
termination as close as
BCM5753M as possible
To RJ-45 CONN.
Layout Notice : Filter place as close
chip as possible.
Layout Notice : 1.2V decoupling CAP.
Place as close chip as possible.
L
T59 , T60 place together
L
Keep JP5.1/2/3 at least 10mils
11/14
11/14
9/10
11/22
C355
0.1U_0402_16V4Z
1
2
BCM5753
Digial power
Analog
power
PLL
GND
BIAS
Don't care
Disconnected
U25B
BCM5753KFBG C0_FPBGA196~D
VDDIO_0
A2
VDDIO_1
A6
VDDIO_2
A10
VDDP_0
B6
VDDP_1
H4
VDDP_2
M12
AVDDL_0
G11
AVDDL_1
G12
AVDD_0
B12
AVDD_1
G13
PCIE_PLLVDD
L7
GPHY_PLLVDD
H13
DC_31 P3
DC_32 P4
DC_33 P5
DC_34 P6
DC_35 P7
DC_36 P8
DC_37 P9
DC_38 P10
DC_39 P13
BIASVDD B13
VDDC_0
E6
VDDC_1
E7
VDDC_2
E8
VDDC_3
E9
VDDC_4
J6
VDDC_5
J7
VDDC_6
J9
VDDC_7
K5
VSS_0 A3
VSS_1 A8
VSS_2 A12
VSS_3 A14
VSS_4 B1
VSS_5 C1
VSS_6 C3
VSS_7 C11
VSS_8 F1
VSS_9 F5
VSS_10 F6
VSS_11 F7
VSS_12 F8
VSS_13 F9
VSS_14 F10
VSS_15 G5
VSS_16 G6
VSS_17 G7
VSS_18 G8
VSS_19 G9
VSS_20 G10
VSS_21 H6
VSS_22 H7
VSS_23 H8
VSS_24 H9
VSS_25 J1
VSS_26 M3
VSS_27 M7
NC_0
A1
NC_1
A4
NC_2
A5
NC_3
A7
NC_4
A9
NC_5
B2
NC_6
B7
DC_0 A11
DC_1 A13
DC_2 B14
DC_3 C14
DC_4 D6
DC_5 D14
DC_6 E3
DC_7 E14
DC_8 F14
DC_9 G14
DC_10 H5
DC_11 H14
DC_12 J8
DC_13 J14
DC_14 K4
DC_15 K6
DC_16 K7
DC_17 K8
DC_18 K9
DC_19 K10
DC_20 K14
DC_21 L6
DC_22 L10
DC_23 L12
DC_24 L14
DC_25 M11
DC_26 M14
DC_27 N5
DC_28 N11
DC_29 N12
DC_30 N14
VDDIO_3
B4
VDDIO_4
D3
VDDIO_5
E11
VDDIO_6
G2
VDDIO_7
H11
VDDIO_8
K3
VDDIO_9
M2
VDDIO_10
P12
VSS_28 N1
VSS_29 N7
VSS_30 P11
VSS_31 P14
NC_7
B8
NC_8
C8
NC_9
D1
NC_10
D2
NC_11
D4
NC_12
D5
NC_13
E1
NC_14
E2
NC_15
E4
NC_16
F2
NC_17
F3
NC_18
G1
NC_19
G3
NC_20
H1
NC_21
H3
NC_22
J3
NC_23
J4
NC_24
K1
NC_25
K2
NC_26
K11
NC_27
L1
NC_28
L2
NC_29
L3
NC_30
L4
NC_31
L8
NC_32
L9
NC_33
L11
NC_34
M1
NC_35
M5
NC_36
M9
NC_37
N2
NC_38
N3
XTALVDD
J13
VAUXPRSNT
C7
VMAINPRSNT
H12
PCIE_SDSVDD
L5
NC_39
N9
NC_40
P1
NC_41
P2
R13150_0402_5%
1 2
L16
BLM11A601S_0603
1 2
R322
75_0402_1%
12
R3744.7K_0402_5%@
1 2
C39
0.1U_0402_16V4Z
1
2
C353
0.1U_0402_16V4Z
1
2
R38649.9_0402_1%
1 2
T21
PAD
R38349.9_0402_1%
1 2
C16
0.1U_0402_16V4Z
1
2
T20
PAD
JP4
ACES_87212-1400
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
R6530_0402_5%
1 2
C302
1000P_1808_3KV7K
1 2
C10
0.1U_0402_16V4Z
1
2
C44
0.1U_0402_16V4Z
1
2
R38449.9_0402_1%
1 2
C323
0.1U_0402_16V4Z
1
2
L15
BLM11A601S_0603
12
R38949.9_0402_1%
1 2
R392
0_0603_5%12
R380
100K_0402_5%
12
C327
0.1U_0402_16V4Z
1
2
C27
4.7U_0805_10V4Z
1
2
G
D
S
Q63
2N7002_SOT23
2
13
R321
75_0402_1%
12
R38249.9_0402_1%
1 2
C346
0.1U_0402_16V7K
12
C370
4.7U_0805_10V4Z 1
2
C3630.1U_0402_16V4Z
1 2
R318
75_0402_1%
12
L18
BLM11A601S_0603
12
G
D
S
Q64
FDN338P_SOT23
2
13
C356
0.1U_0402_16V4Z
1
2
R324
4.7K_0402_5%@
1 2
C335
0.1U_0402_16V4Z
1
2
C347
0.1U_0402_16V7K
12
R38549.9_0402_1%
1 2
C332
0.1U_0402_16V4Z
1
2
C321
0.1U_0402_16V4Z
1
2
R3581K_0402_5% 1 2
R3274.7K_0402_5%@
1 2
C313
4.7U_0805_10V4Z
1
2
R376
0_0603_5%12
C354
0.1U_0402_16V4Z
1
2
C340
0.1U_0402_16V4Z 1
2
R393
0_0603_5%12
R323
75_0402_1%
12
R164.7K_0402_5%@
1 2
C40
0.1U_0402_16V4Z
1
2
C301
1000P_1808_3KV7K
1 2
R672
0_0603_5%
1 2
C311
0.1U_0402_16V4Z
1
2
C21
0.1U_0402_16V4Z
1
2
C3600.1U_0402_16V4Z
1 2
R38849.9_0402_1%
1 2
G
D
S
Q106 BSS84_SOT23
@
2
1 3
C312
0.1U_0402_16V4Z
1
2
C369
4.7U_0805_10V4Z
1
2
C345
0.1U_0402_16V7K
12
R12150_0402_5%
1 2
C3620.1U_0402_16V4Z
1 2
C348
0.1U_0402_16V7K
12
L17
BLM11A601S_0603
12
R325
10K_0402_5%
12
1:1
1:1
1:1
1:1
T22
24HST1041A-3B_24P
TCT1
1
TD1+
2
TD1-
3
TCT2
4
TD21+
5
TD2-
6
TCT3
7
TD3+
8
TD3-
9
TCT4
10
TD4+
11
TD4-
12 MX4- 13
MX3- 16
MCT3 18
MX2- 19
MX2+ 20
MCT2 21
MX1- 22
MX1+ 23
MCT1 24
MX4+ 14
MCT4 15
MX3+ 17
C3610.1U_0402_16V4Z
1 2
C310
0.1U_0402_16V4Z
1
2
R38749.9_0402_1%
1 2
C36
4.7U_0805_10V4Z 1
2
L10
BLM11A601S_0603
12
C351
0.1U_0402_16V4Z
1
2
A B C D
D
E
E
11
22
33
44
XMIT_OFF#
PCIE_TXN2
CH_DATA
WP_LED#
WW_LED#
CH_CLK
XMIT_OFF#
CLK_PCIE_MCARD
WL_LED#
PCIE_TXP2
CLK_PCIE_MCARD#
PCIE_WAKE#
CLKREQD#
PCIE_C_RXP2
PCIE_C_RXN2PCIE_RXN2
PCIE_RXP2
PLT_RST_B#
DB_LPC_RST#
DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0
CLK_PCI_DB
DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0
DB_PWR_LED#
DB_NUM_LED#
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0 DB_LPC_RST#
DB_PWR
DB_CAPS_LED#
DB_PWR_LED#
DB_NUM_LED#NUM_LED#
CAPS_LED#
STB_LED#
WW_LED#
WP_LED#
WL_LED#
DB_PWR
DB_CAPS_LED#
SLP_S3#
XMIT_OFF21
PCIE_WAKE#21
CLK_PCIE_MCARD15 CLK_PCIE_MCARD#15
PLT_RST#7,19,20,21,23,25,32,33
ICH_SMBCLK4,13,14,15,18,21,25
ICH_SMBDATA4,13,14,15,18,21,25PCIE_TXN221 PCIE_TXP221
WL_LED#32
CLKREQD#15
PCIE_RXP221 PCIE_RXN221
ICH_SMBDATA4,13,14,15,18,21,25
ICH_SMBCLK4,13,14,15,18,21,25
ACCEL_INT19
USB20_P1_R_MC32
USB20_N1_R_MC32
PLT_RST_B#20,31
CLK_PCI_DB15
LPC_FRAME#20,31,32,33 LPC_AD320,31,32,33 LPC_AD220,31,32,33 LPC_AD120,31,32,33 LPC_AD020,31,32,33
NUM_LED#33,34 CAPS_LED#33,34 STB_LED#32,33,35
SLP_S3#18,21,25,28,29,33,35,36,40,43,44
CH_CLK30
CH_DATA30
+1.5VS+3VS
+3VALW
+1.5VS +3VS_MINI
+3VALW
+3VS +3VS_ACL
+3VS_ACL
+3VS_ACL_IO
+3VS_ACL_IO
+3VS_ACL
+3VS_ACL
+3VL
+3VALW +3VS_MINI
+3VS
+3VALW
+3VS
+3VS_MINI
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Mini-Card/Mini-PCI/Accelerometer
2752Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Mini-Express Card
L
Must be placed in the center of the system.
5/26
pin29 is the center EMI pad which STMicro
recommended not to be connected
L
Must be placed close to JP44.
8/30
9/8
9/8
11/22
9/12
9/12
Mini-Card Stand Off
9/16
R515
100K_0402_5% @ 1 2
C167
0.01U_0402_16V7K
1
2
R5200_0402_5%DB@
1 2
R4950_0402_5%DB@
1 2
H29
HOLE_MC
1
R5000_0402_5%@
1 2
R56
0_0805_5%@
1 2
R48
10K_0402_5%ACCEL@1 2
G
D
S
Q70
SI2301BDS_SOT23@
2
13
C214
0.01U_0402_16V7K
1
2
R4880_0402_5%DB@
1 2
R4970_0402_5%@
1 2
C493
4.7U_0805_10V4Z
1
2
D11
CH751H-40_SC76ACCEL@
2 1
C135
10U_0805_6.3V6MACCEL@
1
2
C494
4.7U_0805_10V4Z
1
2
R45
0_0402_5%ACCEL@ 12
R505
0_0805_5%
1 2
R546 0_0402_5%
1 2
J12
PAD-No SHORT 2x2m
2 1
C492
0.01U_0402_16V7K
1
2
R5470_0402_5%
1 2
R55
0_0603_5%ACCEL@
1 2
R44
0_0402_5%ACCEL@ 12 U6
LIS3LV02DQ_QFN28ACCEL@
Vdd 19
NC5
15 NC4
14
NC6
21
GND
17
GND
2Vdd 3
Reserved1
4
GND
5
NC3
8NC2
7NC1
1
PADDLE
29
NC7
22
NC8
23
NC9
24
NC10
25
NC11
26
NC12
27
NC13
28
Reserved2
18
Reserved3
20
RDY/INT 6
SDO 9
SDA/SDI/SDO 10
Vdd_IO 11
SCL/SPC 12
CS 13
CK 16
JP30
FOX_AS0B226-S40N-7F
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
GND1
53
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 54
R430_0402_5%
12
R5110_0603_5%DB@
1 2
R104
0_0402_5%
12
J11
PAD-SHORT 2x2m
2 1
R50
0_0402_5%ACCEL@
12
C489
0.1U_0402_16V4Z
1
2
C121
0.1U_0402_16V4ZACCEL@
1
2
G
D
S
Q71
2N7002_SOT23@
2
13
G
D
S
Q17
2N7002_SOT23@
2
13
R5440_0402_5%DB@
1 2
C136
0.01U_0402_16V7K@
1
2
R5300_0402_5%DB@
1 2
R112
100K_0402_5%@
12
R92
10K_0402_5%@
12
R5140_0402_5%DB@
1 2
C171
0.1U_0402_16V4Z
1
2
R4710_0402_5%DB@
1 2
R4560_0402_5%DB@
1 2
R4520_0402_5%DB@
1 2
C217
0.01U_0402_16V7K
1
2
C491
0.1U_0402_16V4Z
1
2
H28
HOLE_MC
1
A B C D E F
F
G
G
H
H
11
22
33
44
MONO_IN_HD
SENSE_A SENSE_A_A
SENSE_A_C
LINE_IN_SENSE
SENSE_A_B
SENSE_A
PORT_A_SNS
SENSE_B
PIN44
AFILT3
AFILT4
MONO_IN_HD
PIN42
PIN40
PIN33
CODEC_REF
+3VS_CODEC
MIC1_C
MIC2_C
DLINE_IN_RC_R
DLINE_IN_RC_L
AFILT1
AFILT2
INT_MICR_C
AC97_SDIN0_CODEC
AUD_REF
DLINE_IN_R_R
INT_MICL_C
DLINE_IN_R_L
PCM_SPK23
SB_SPKR21
SLP_S3#18,21,25,27,29,33,35,36,40,43,44
SENSE_A_A29
SENSE_A_B29
LINE_IN_SENSE35
AC97_SDIN020
AC97_RST#_CODEC20
DLINE_IN_R35
MIC129
DLINE_IN_L35
LINE_OUTR29
LINE_OUTL29
MIC229
R_HP29
L_HP29
AC97_SDOUT_CODEC20
AC97_SYNC_CODEC20
AC97_BITCLK_CODEC20
EAPD29,33
PR_INSERT#
INT_MIC29
PORT_A_SNS29
VDDA_CODEC
VDDA_CODEC
+5VAMP
VDDA_CODEC
VDDA_CODEC
VDDA_CODEC +3VS
VDDA_CODEC
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
AC97 CODEC AD1981HD
2852Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place R258 between DGND & AGND & close to U14
Place close to U14
GNDAGND
11/17
R213
49.9K_0402_1%
12
C205
0.01U_0402_16V7K 1
2
C256
1U_0603_10V4Z
1
2
C282
1U_0603_10V4Z
1
2
R286
10K_0402_1%
1 2
C249 10P_0402_25V8K@
1 2
T44PAD
C2701U_0603_10V4Z
1 2
R293
39.2K_0402_1%
1 2
T46PAD
C239
0.1U_0402_16V4Z
1
2
C2590.1U_0805_25V7M
12
T47PAD
T34PAD
R198
0_1206_5%
1 2
G
D
S
Q51
2N7002_SOT23
2
13
R2244.7K_0402_5%@
1 2
R279
150K_0402_1%
1 2
R2840_0402_5%@12
C251
0.1U_0402_16V4Z
1
2
T42PAD
R2972.67K_0402_1%
1 2
C216
0.1U_0402_16V4Z
1
2
R2414.7K_0402_5%@
1 2
T33PAD
C193
1U_0603_10V4Z
1
2
R248
10_0402_5%@
12
+
C213
22U_B_10V
1
2
L11
FBM-L10-160808-301-T_0603
1 2
R294
20K_0402_1%
1 2
T35PAD
C266
0.1U_0402_16V4Z
1
2
C2741U_0603_10V4Z
1 2
T45PAD
T37PAD
+
C198
22U_B_10V
1
2
C276
0.1U_0402_16V4Z
1 2
R296
10K_0402_5%@
12
C5450.1U_0805_25V7M
12
C250
0.1U_0402_16V4Z
1
2
C279
0.1U_0402_16V4Z
1 2
R287
10K_0402_5%
12
U17
MIC5205BM5_SOT23-5
IN
1
GND
2
EN
3OUT 5
ADJ 4
C224
0.1U_0402_16V4Z
1
2
C2731U_0603_10V4Z
1 2
R219
0_1206_5%@
12
T48PAD
C269
0.01U_0402_16V7K
1
2
R206
143K_0402_1%
12
R2264.7K_0402_5%@
12
C2751U_0603_10V4Z
1 2
T43PAD
T36PAD
C225
0.1U_0402_16V4Z
1
2
R2362.2K_0402_5%
1 2
R21810K_0402_5%
12
C2640.1U_0402_16V4Z1981HD@
1 2
R252
33_0402_5%
12
C222
10U_1206_16V4Z
1
2
R288
10K_0402_5%
12
R277
150K_0402_1%
1 2
U21
AD1981HDJSTZ-REEL_LQFP48
AUX_L
14
AUX_R
15
MIC4
17
MIC3
16
LINE_IN_L
23
LINE_IN_R
24
CD_L
18
CD_R
20
CD_GND
19
MIC1
21
MIC2
22
SENSEA
13
PCBEEP 12
LINE_OUT_L 35
LINE_OUT_R 36
MONO_OUT 37
RESET#
11
SYNC
10
BIT_CLK 6
SDATA_OUT
5
SDATA_IN 8
GPIO_2 2
GPIO_3 3
MIC_BIAS_C 29
MIC_BIAS_F 30
MIC_BIAS_B 28
VREF 27
DVDD1 1
DVDD2 9
AVDD1 25
AVDD2 38
MIC_BIAS_D 32
N/C 33
EAPD
47
SPDIFO
48
DVSS1
4
DVSS2
7
HP_LOUT_L 39
HP_LOUT_R 41
N/C 31
N/C 40
AVSS2 42
AVSS1 26
NC 45
NC 46
GPIO_0 43
GPIO_1 44
SENSEB
34
T41PAD
R283
10K_0402_5%
12
R295
100K_0402_5%
12
G
D
S
Q48
2N7002_SOT23
2
13
C2721U_0603_10V4Z
1 2
R2894.7K_0402_5%
1 2
T39PAD
T40PAD
C2831U_0603_10V4Z
1 2
R225
0_0805_5%
1 2
T38PAD
C285
0.1U_0603_50V
1
2
R2904.7K_0402_5%
12
C24710P_0402_25V8K
1 2
C2060.1U_0805_25V7M
12
R2914.7K_0402_5%
12
R2924.7K_0402_5%
1 2
C194
100P_0402_50V8J
1
2
C238
10U_1206_16V4Z
1
2
C265
0.1U_0402_16V4Z
1
2
C2840.1U_0805_25V7M
12
G
D
S
Q52
2N7002_SOT23
2
13
A B C D
D
E
E
11
22
33
44
L_SPK-
R_SPK+
R_SPK-
L_SPK+
USB20_N2_R
USB20_P2_R
USB20_N3_R
USB20_P3_R
MIC_SENSE
SLP_S5
DLINE_OUT_L
USB20_P2
USB20_N2
USB20_N3
USB20_P3
LINE_C_OUTR LINE_C_R_OUTR
LINE_C_OUTL LINE_C_R_OUTL R_SPK+
R_SPK-
L_SPK+
L_SPK-
LINE_C_R_OUTR
LINE_C_R_OUTL
MIC_SENSE
DLINE_OUT_L
SLP_S530,35,36
DLINE_OUT_L35 DLINE_OUT_R35 R_HP28
L_HP28
MIC128
MIC228
USB20_N221 USB20_P221
USB20_N321 USB20_P321
USB_OC#221 USB_OC#321
LINE_OUTR28
LINE_OUTL28
A_SD33
MUTE_LED#34
EAPD28,33
SLP_S3#18,21,25,27,28,33,35,36,40,43,44
INT_MIC28
SENSE_A_B28
PORT_A_SNS28
DOCK_HPS#35
SENSE_A_A28
+5VALW
VDDA_CODEC
+5VALW
+5VAMP+5VALW
VDDA_CODEC VDDA_CODEC
VDDA_CODEC
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
AMP & Audio Jack
2952Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
0
00
6 dB
21.6 dB
1
15.6 dB
10 dB
U39 Gain Settings
1
GAIN1
1
Av(inv)
1
GAIN0
0
To Audio / USB Board CONN
AMP. FOR INTERNAL SPEAKER
10 dB
10 dB
10 dB
10 dB
L
Keep 10 mil width
11/14
C281
0.1U_0603_25V7K_V1
1
2
R270
10K_0402_5%
1 2
D18
PACDN042_SOT23~D@
2
31
C260
0.1U_0402_16V4Z
1 2
R6490_0402_5%
1 2
R257 16.5K_0402_1%
1 2
C246
10U_1206_6.3V6M@
1
2
G
D
S
Q49
2N7002_SOT23
2
13
R285
100K_0402_5%
12
R162 0_0402_5%
12
JP25
ACES_87212-2200
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
R273
100K_0402_5%
1 2
C248
0.1U_0402_16V4Z
1
2
C278
2.2U_0603_6.3V6K
1
2
+
C252
150U_D_6.3VM@
1
2
G
D
S
Q40
2N7002_SOT23@
2
13
R220
0_1206_5%
1 2
U20
MAX9710ETP_QFN20
PGND1
6VDD 12
PVDD1 8
MUTE
4
NC1 3
OUTL- 17
OUTL+ 19
OUTR- 9
OUTR+ 7
INR
5
INL
1
BIAS 2
PVDD2 18
SHDN
14
PGND2
11
PGND3
15
PGND4
20
NC2 10
NC3 13
NC4 16
EP
21
C160
100P_0402_50V8J
1
2
D19
PACDN042_SOT23~D@
2
31
R256 16.5K_0402_1%
1 2
G
D
S
Q39
2N7002_SOT23
2
13
C208
10U_1206_6.3V6M@
1
2
C2621U_0603_10V4Z
1 2
+
C192
100U_D2_6.3VM
1 2
R170 0_0402_5%
12
G
D
S
Q37
2N7002_SOT23
2
13
R272
10K_0402_5%
1 2
R258
100K_0402_5%
12
+
C191
100U_D2_6.3VM
1 2
R217
15_0805_5%
12
C261
0.1U_0402_16V4Z
1 2
C188
0.1U_0402_16V4Z
1
2
C161
100P_0402_50V8J
1
2
C163
100P_0402_50V8J
1
2
JP19
E&T_3801-04
1
1
2
2
3
3
4
4
C162
100P_0402_50V8J
1
2
R650
1K_0402_5%
12
G
D
S
Q47
2N7002_SOT23
2
13
G
D
S
Q50
2N7002_SOT23
2
13
R207
15_0805_5%
12
R174
0_0402_5%
12
R271
0_0402_5%
12
R180 0_0402_5%12
R278
100K_0402_5%
12
R20310K_0402_5%
1 2
C240
1U_0603_10V4Z@
1
2
5 4 3 2
2
1
1
DD
CC
BB
AA
USB20_N4
USB20_P4 USB20_P5
USB20_N5
USB20_P5
USB20_N5
USB_OC#4
SLP_S5
USB20_N4_R
USB20_P4_R USB20_N5_R
USB20_P5_R
USB20_N0
USB20_P0
USB20_P4
USB20_N4
USB_OC#5SLP_S5
USB20_P0_R
USB20_N0_R
SLP_S5
USB_OC#4 USB_OC#5
BT_OFF21
BT_LED32
USB_OC#421
USB20_P521
USB20_N521
SLP_S529,35,36
USB20_P421 USB20_N421
USB_OC#521
CH_DATA27
CH_CLK27
USB20_N021
USB20_P021
+3VAUX_BT
+3VAUX_BT+3VALW
USB_VCCA+5VALW +5VALWUSB_VCCB
+5VALW
USB_VCCA USB_VCCB
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
USB I/O & BT Connector
3052Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
W=40mils
USB CONNECTOR 1
W=40mils
BT Connector
(4A,160mils ,Via NO.=8)
9/14
11/17
11/23
R677100_0402_5%
1 2
+
C118
220U 6.3V M
1
2
R70
47K_0402_5%
1 2
D10
PACDN042_SOT23~D@
2
3
1
D12
PACDN042_SOT23~D@
2
3
1
+
C126
220U 6.3V M
1
2
R490_0402_5%
12
J13
PAD-OPEN 3x3m
1 2
R510_0402_5%
12
C138
0.1U_0402_16V4Z
@
1
2
D16
PACDN042_SOT23~D@
2
3
1
C499
0.1U_0402_16V4Z
1
2
R87 0_0402_5%
12
R674100_0402_5%
1 2
U7
TPS2041BDR_SO8
GND 1
IN 2
IN 3
EN# 4
OC#
5OUT
6OUT
7OUT
8
C143
0.1U_0402_16V4Z
1
2
JP16
TYCO_1-1734062-1
VCC
1
D0-
2
D0+
3
VSS
4
VCC 5
D1- 6
D1+ 7
VSS 8
G2
10 G1 9
G3 11
G4
12
C123
1000P_0402_50V7K
1
2
C144
0.01U_0402_16V7K
1
2
C122
0.1U_0402_16V4Z
1
2
R85 0_0402_5%
12
C142
4.7U_0805_10V4Z
1
2
R520_0402_5%
12
C137
4.7U_0805_10V4Z
1
2
C498
1000P_0402_50V7K
1
2
C140
1U_0603_10V4Z
1
2
JP18
ACES_87212-0800
1
2
3
4
5
6
7
8
R530_0402_5%
12
G
D
S
Q12SI2301BDS_SOT23
2
13
U35
G548A2P1U_SO8
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
R570_0402_5% 12
R69
100K_0402_5%
12
U36
TPS2041BDR_SO8
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
A B C D
D
E
E
11
22
33
44
DCD#1
RI#1
CTS#1
DSR#1
IRRX
CLK_14M_SIOCLK_PCI_SIO
LPC_AD3
LPC_AD1
LPC_AD2
LPC_AD0
CLK_14M_SIO
LPC_FRAME#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
CTS#1
RTS#1
RI#1
TXD1
DCD#1
DTR#1
DSR#1
RXD1
SIO_PD#
SIO_GPIO11
CLK_PCI_SIO
SIRQ
LPC_DRQ#0
SIO_IRQ
PM_CLKRUN#
LPTBUSY
LPTSLCT
LPTACK#
LPTERR#
LPTPE
LPTSTB#
LPTAFD#
LPTINIT#
LPTSLCTIN#
SIO_GPIO12
SIO_PME#
PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SW_EXPCRD_RST#
SIO_GPIO11
SIO_GPIO40
SIO_GPIO10
PID1
PID0
SIO_GPIO40
LPTINIT#
LPTSLCTIN#SW_EXPCRD_RST#
SIO_IRQ
SIO_GPIO44
SIO_GPIO12
SIO_GPIO10
SIO_GPIO43
LPD3
LPD2
LPD1
LPD0
LPD4
LPD7
LPD6
LPD5
LPTACK#
LPTSLCT
LPTBUSY
LPTPE
LPTAFD#
LPTSTB#
LPTERR#
CARD_ID#
SIO_DPIO45
IRRX
SIO_RST#
CLK_14M_SIO15
LPC_AD120,27,32,33
LPC_FRAME#20,27,32,33
LPC_AD020,27,32,33
LPC_AD220,27,32,33 LPC_AD320,27,32,33
LPC_DRQ#020
SIRQ21,23,32,33
PM_CLKRUN#21,23,32,33 CLK_PCI_SIO15
LPD535
LPD635
LPD435
LPD335
LPD735
LPD035
LPD235
LPD135
LPTBUSY35
LPTPE35
LPTSLCT35
LPTERR#35
LPTACK#35
LPTINIT#35
LPTAFD#35
LPTSTB#35
LPTSLCTIN#35
DCD#135
DTR#135
CTS#135
TXD135
DSR#135
RTS#135
RXD135
RI#135
SER_SHD35
EXPCRD_RST#35
PLT_RST_B#20,27 NPCI_RST#21,33
+3VS
+3VS
+3VS
+3VS
+3VS
+5VS
+5VS_PRN
+3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
SUPER I/O LPC47N217
3152Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Base I/O Address
0 = 02Eh
1 = 04Eh*
High : Compal MXM
Low : Standard MXM
9/8
POWER
CLOCK
GPIO
LPC I/F
SERIAL I/F
FIR
PARALLEL I/F
U29
LPC47N217_STQFP64
LAD0
10
LAD1
12
LAD2
13
LAD3
14
LFRAME#
15
LDRQ#
16
PCI_RESET#
17
LPCPD#
18
CLKRUN#
19
PCI_CLK
20
SER_IRQ
21
IO_PME#
6
RXD1 62
TXD1 63
DSR1# 64
RTS1# 1
CTS1# 2
DTR1# 3
RI1# 4
DCD1# 5
IRRX2 37
IRTX2 38
IRMODE/IRRX3 39
INIT# 41
SLCTIN# 42
PD0 44
PD1 46
PD2 47
PD3 48
PD4 49
PD5 50
PD6 51
PD7 53
SLCT 55
PE 56
BUSY 57
ACK# 58
ERROR# 59
ALF# 60
STROBE# 61
GPIO40
23
GPIO41
24
GPIO42
25
GPIO43
27
GPIO44
28
GPIO45
29
GPIO46
30
GPIO47
31
GPIO10
32
GPIO11/SYSOPT
33
GPIO12/IO_SMI#
34
GPIO13/IRQIN1
35
GPIO14/IRQIN2
36
GPIO23
40
CLK14
9
VTR 7
VCC 26
VCC 54
VSS
8
VSS
22
VSS
43
VSS
52 VCC 45
VCC 11
R427
1K_0402_5%
1 2 D31
CH751H-40_SC76
21
R435
10K_0402_5%
1 2
R4031K_0402_5%
1 2
R438
10K_0402_5%
1 2
RP29
4.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R420
10_0402_5%@
12
R414
4.7K_0402_5%
1 2
R41710K_0402_5%
1 2
R422
10K_0402_5%
1 2
R428
10K_0402_5%
1 2
R4320_0402_5%@
1 2
RP27
4.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
RP25
4.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
RP26
4.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
C401
4.7U_0805_10V4Z
1
2
R436
10K_0402_5%
1 2
C399
10P_0402_25V8K
@
1
2
R8
10K_0402_5%
1 2
RP30
10K_1206_8P4R_5%
18 27 36 45 R43310K_0402_5%
1 2
R421
0_0402_5%
1 2
C383
0.1U_0402_16V4Z
1
2
R418
4.7K_0402_5%
1 2
C397
0.1U_0402_16V4Z
1
2
C391
0.1U_0402_16V4Z
1
2
RP28
4.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R434
10_0402_5%@
12
R429
10K_0402_5%
1 2
R437
10K_0402_5%
1 2
C410
18P_0402_50V8K
@
1
2
R4310_0402_5%
1 2
5 4 3 2
2
1
1
DD
CC
BB
AA
STB_LED#
IDE_LED#
AMBER_BATLED#
GREEN_BATLED#
WL_LED
BT_LED
SPI_CS#
SPI_CLK
SPI_SI
SPI_WP#
SPI_HOLD#
SPI_WP#
SPI_HOLD#
SPI_SO
WL_LED
USB20_N1
USB20_P1 USB20_N1_R
USB20_P1_R
USB20_N1_R
USB20_P1_R
USB20_N1_R_MC
USB20_P1_R_MC
SPI_CS#
SPI_CLK
SPI_SI
SPI_WP#
SPI_HOLD#
BT_LED
WL_LED
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PLT_RST#
SIRQ
PM_CLKRUN#
TPM_XTALI
TPM_XTALO
TPM_GPIO
TPM_GPIO2
CLK_PCI_TCGLPC_PD#
TPM_XTALO
TPM_XTALI
HDD_STP#
HDD_STP
LPC_FRAME#
STB_LED#27,33,35
IDE_LED#20
AMBER_BATLED#33
GREEN_BATLED#33
BT_LED30
SPI_CS#21
SPI_CLK21
SPI_SI21 SPI_SO21
WL_LED#27
USB20_P121 USB20_N121
USB20_P1_R_MC27
USB20_N1_R_MC27
WL/BT_LED34
STB_LED34
PM_CLKRUN#21,23,31,33
CLK_PCI_TCG15 SIRQ21,23,31,33
LPC_AD020,27,31,33 LPC_AD120,27,31,33 LPC_AD220,27,31,33 LPC_AD320,27,31,33
LPC_PD#21,33
HDD_STP21
LPC_FRAME#20,27,31,33 PLT_RST#7,19,20,21,23,25,27,33
CLK_TPM33
+3VL
+3VS
+3VS
+3VL
+3VL
+5VS
+3VALW
+3VALW
+3VS
+3VALW
+3VS
+3VS
+3VS +3VALW
+3VS
+3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
TCG/BIOS ROM/PS2/LED/SW
3252Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
BIOS ROM
POWER LED
HDD LED
Finger printer
AMBER GREEN
GREEN
Battery LED
BLUE LED
Wireless LED
L
R1291 should be placed less
than 100 mils from U61 & U65.
Mini-PCIE Card LED
L
Place R1365/R1366 close to JP38.2/JP38.3
and minimize the stub length.
8/23
TPM1.2 on board
Base I/O Address
*1 = 04Eh
0 = 02Eh
8/26
8/26
8/26
GREENAMBER
9/6
9/2
9/8 9/8
9/8
L
The chip must be placed on PCB easily
rework place for debug.
9/13
9/12
L
Place R1447 close to Y8.1
D27
19-22SOVGC/TR8_GRN/ORG
21
34
R234
150_0402_5%
12
R199
100K_0402_5%
1 2
10K
47K
Q44
DTA114YKA_SC59
2
1 3
SLB 9635 TT 1.2
U26
SLB 9635 TT 1.2_TSSOP28TPM1.2@
NC 1
GPIO2 2
NC 3
GND
4
VSB 5
GPIO 6
PP
7
TEST1 8
TESTB1/BADD 9
VDD 10
GND
11
NC 12
XTALI/32K IN
13
XTALO
14
CLKRUN#
15
LRESET#
16
LAD3
17
GND
18 VDD 19
LAD2
20
LCLK
21
LFRAME#
22
LAD1
23
VDD 24
GND
25
LAD0
26
SERIRQ
27 LPCPD#
28
U14
SST25LF080A_SO8-200milSPI@
S
1
VCC
8
Q2
HOLD
7
VSS 4
D
5
C
6
W
3
10K
47K
Q38
DTA114YKA_SC59
2
1 3
C349
0.1U_0402_16V4ZTPM1.2@
1
2
G
D
S
Q36
2N7002_SOT23
2
13
C394
0.1U_0402_16V4ZTPM1.2@
1
2
R401
0_0402_5%TPM1.2@ 12
10K
47K
Q46
DTA114YKA_SC59
2
1 3
R233
150_0402_5%
12
D9
PACDN042_SOT23~D@
2
3
1
R378
4.7K_0402_5%TPM1.2@
12
D30
19-22SOVGC/TR8_GRN/ORG
21
34
C350
0.1U_0402_16V4ZTPM1.2@
1
2
Y5
32.768KHZ_12.5P_1TJS125BJ2A251TPM1.2@
OUT 4
IN 1
NC
3
NC
2
R397 0_0402_5%@1 2
10K
47K
Q42
DTA114YKA_SC59
2
1 3
JP15
ACES_87212-0800
1
2
3
4
5
6
7
8
10K
47K
Q34
DTA114YKA_SC59
2
1 3
R211
100K_0402_5%
12
R46 0_0402_5%
12
D28
LTST-S110TBKT-5A
21
U13
MX25L8005MI-15G_SO8-150mil@
S
1
VCC
8
Q2
HOLD
7
VSS 4
D
5
C
6
W
3
R212
0_0402_5%@
1 2
C36518P_0402_50V8JTPM1.2@
12
R375
0_0402_5%TPM1.2@
12
C341
18P_0402_50V8JTPM1.2@
12
C392
10P_0402_50V8K@
12 R3900_0402_5%TPM1.2@ 12
R221
150_0402_5%
12
G
D
S
Q41
2N7002_SOT23
2
13
R109
47_0402_5%SPI@
1 2
R108
3.3K_0402_5%SPI@
1 2
R47 0_0402_5%12
R402
10K_0402_5%TPM1.2@
1 2
C124
0.1U_0402_16V4Z
1
2
G
D
S
Q35
2N7002_SOT23
2
13
R377
4.7K_0402_5%@12
10K
47K
Q45
DTA114YKA_SC59
2
1 3
R415
10_0402_5%@12
D29
17-21SYGC/S530-E1/TR8_GRN
21
R243
150_0402_5%
12
R95
100K_0402_5%
1 2
T23PAD
R379
4.7K_0402_5%@
12
R155
3.3K_0402_5%SPI@
1 2
R242
150_0402_5%
12
R222
150_0402_5%
12
T24PAD
C393
0.1U_0402_16V4ZTPM1.2@
1
2
R5700_0402_5%@
12
R5690_0402_5%@
12
R394
10M_0402_5%TPM1.2@
12
C172
0.1U_0402_16V4ZSPI@
1
2
5 4 3 2
2
1
1
DD
CC
BB
AA
KSO[0..13]
EA#
FAN_PWM
PM_POK
KSI3
PM_RSMRST#
VCC1_PWRGD
STB_LED#
THM_MBAY#
KBD_CLK
KSO1
LPC_AD0
KSO15
CHGCTRL
KSI4
KSO4
KSO10
CLK_14M_KBC
KSI0
PGM
ON/OFFBTN_KBC#
LPC_FRAME#
AMBER_BATLED#
KSO11
PM_CLKRUN#
PS2_DATA
BATCON
KSO9 FWP#
SIRQ
KSI5
KSO6
THM_MAIN#
KBD_DATA
KSO7
TEST
BATSELB_A#
SLP_S3#
CLK_PCI_EC
TP_CLK
KSO0
PCI_SERR#
TP_DATA
KSI1
KSO8
KSI7
LPC_AD2
FWP#
LPCPD#
KSI6
PS2_CLK
LPC_AD1
KSI2
KSO2
KSO3
KSO5
LPC_AD3
MODE
CAPS_LED#
INV_PWM
A20M
TP_CLK
TP_DATA
PS2_CLK
KBD_DATA
KBD_CLK
PS2_DATA
FWP#
CLK_PCI_EC
NUM_LED#
GREEN_BATLED#
PGM
PGM
FWP# PM_POK
NUM_LED#
RUNSCI_EC#
KBC_PWR_ON
EC_GPIO19
EC_GPIO10
TEST
KBRST#
AB1B_DATA
AB1B_CLK
AB1A_CLK
AB1A_DATA
LOW_BAT#
KSO14KSO12
KSO13
GPIO8
GPIO9
GPIO8
GPIO9
VCC1_PWRGD
KSI3
KSI2
KSI1
KSI0
KSI6
KSI4
KSI5
KSI7
AB1B_DATA
AB1A_CLK
AB1B_CLK
AB1A_DATA
VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#
CLK_14M_KBC
THM_MAIN#
KSO17
EC_GPIO13
EC_GPIO12
KSO16 EC_GPIO12
EC_GPIO13
MODE
EA#
RUNSCI_EC#
ADP_EN
EC_GPIO12
EC_GPIO12
EC_GPIO10
EC_GPIO19
S_CLK
S_CLK
PLT_RST#
CRY1
ADP_EN LPCPD#
NPCI_RST#
CRY2
PWR_GD
PWR_GD_EC
PWR_GD_EC PGD_IN
SIRQ21,23,31,32
LPC_AD320,27,31,32
LPC_AD020,27,31,32
LPC_AD220,27,31,32 LPC_AD120,27,31,32
AMBER_BATLED#32
STB_LED#27,32,35
ON/OFFBTN_KBC#34
BATCON41
THM_MBAY#46
PCI_SERR#19,23
THM_MAIN#46
KBD_DATA35 KBD_CLK35
LPC_FRAME#20,27,31,32
PM_CLKRUN#21,23,31,32
CLK_PCI_EC15
PS2_CLK35
TP_CLK34
PS2_DATA35
TP_DATA34
BATSELB_A#41
SLP_S3#18,21,25,27,28,29,35,36,40,43,44
PM_POK7,21
CLK_14M_KBC15
VCC1_PWRGD37
KB_RST#20
FAN_PWM4
CHGCTRL40,41
GATEA2020
CAPS_LED#27,34
NUM_LED#27,34
GREEN_BATLED#32
RUNSCI_EC#21
KBC_PWR_ON42
ADP_PRES18,25,40,41,42,47
INV_PWM17
AB1B_DATA46
AB1B_CLK46
AB1A_DATA46
AB1A_CLK46
LOW_BAT#21
KSO[0..13]34
KSO1434
KSO1534
KSI[0..7]34
KSO1634
KSO1734
EAPD28,29
A_SD29
PM_RSMRST#21
ADP_EN47
CB_CLK24
ADP_PS047
ADP_PS147
ADP_ID47
CLK_TPM32
NPCI_RST#21,31 PLT_RST#7,19,20,21,23,25,27,32 LPC_PD#21,32
PWR_GD18,36,37,45,47
PGD_IN37,45
+RTCVCC
+3VS
+3VL
+5VS
+3VL
+3VS
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
LPC47N1021
3352Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
AGND FILTER
1. For normal operation:
Un-install R29,R65
2. For KBC internal ROM flash:
Install R29,R65
Pin3 250 : KSO12/OUT8/KBRST
Pin49 250 -- Reset Out
Pin50 250 -- 24MHz_Out
Pin52 250 -- XOSEL
Pin56 250 -- PGM
Pin58 250 -- 32KHz_OUT
Pin82 250 -- nFWP
Pin91 250 -- nDMS_LED
BIOS debug port
Place under KB area
For KBC debugging used.
Pin57 250 -- MODEPin1 250 -- TEST Pin ( NC !! )
Pin83 250 -- nEA ( pull up !! )
R127
1021@
R977
R128
250@
R62
R78
R131
R129
L
Note: R94 must be removed when
R1354 stuff and R87 remove.
Pin34 250 -- LPCPD#
11/14
11/21
R255
10K_0402_5%
12
R192
10K_0402_5%
1 2
R2821K_0402_5%
1 2
C267
10P_0402_50V8J
1
2
R6700_0402_5%
1 2
R2020_0402_5%
1 2
C245
10P_0402_50V8K
@
1 2
Y3
32.768KHZ_12.5P_1TJS125DJ2A073
OUT 4
IN 1
NC
3
NC
2
JP22
ACES_85201-0602@
1
2
3
4
5
6
R274
10K_0402_5%
1 2
C253
0.1U_0402_16V4Z
1
2
R275 1K_0402_5%@12
C263
1U_0603_10V4Z 1
2
D25
CH751H-40_SC76
21
R246
10_0402_5%
@
1 2
J9
NO SHORT PADS
1 2
C237
10P_0402_50V8J@
1
2
C244
0.1U_0402_16V4Z
1
2
R6690_0402_5%@
1 2
R194
100K_0402_5%
1 2
R6510_0402_5%
1 2
General Purpose I/O Interface
Keyboard/Mouse Interface LPC
Bus
Power Mgmt/SIRQ
Miscellaneous
Access Bus Interface
SMSC_LPC47N250_TQFP-100P
KBC1021_TQFP100
U18
AGND
55
KSO0
17
KSO1
16
KSO2
15
KSO3
14
KSO4
13
KSO5
12
KSO6
10
KSO7
9
KSO8
7
KSO9
6
KSO10
5
KSO11
4
KSO12/GPIO00/KBRST
3
KSO13/GPIO18
2
KSI0
25
KSI1
24
KSI2
23
KSI3
22
KSI4
21
KSI5
20
KSI6
19
KSI7
18
IMCLK
26
IMDAT
27
KCLK
29
KDAT
31
EMCLK
32
EMDAT
33
CLKRUN#
44
SER_IRQ
46
PCI_CLK
43
EC_SCI#
59
LAD[3]
40
LAD[2]
39
LAD[1]
37
LAD[0]
35
LFRAME#
41
LRESET#
42
LPCPD#/GPIO23
34
XTAL1
53
XTAL2
54
VCC0
51
TEST PIN 52
GND
92
GND
79
GND
65
GND
45
GND
36
GND
28
GND
8
VCC1 11
VCC1 67
VCC1 81
VCC1 94
VCC2 30
VCC2 38
VCC2 47
OUT0 99
OUT1/IRQ8# 100
OUT7/SMI# 98
OUT8/KBRST 97
OUT9/PWM2 96
OUT10/PWM0 95
OUT11/PWM1 93
GPIO02 62
GPIO03 63
GPIO04/KSO14 64
GPIO05/KSO15 66
GPIO07/PWM3 68
GPIO08/RXD 69
GPIO09/TXD 70
GPIO11/AB2A_DATA 71
GPIO12/AB2A_CLK 72
GPIO13/AB2B_DATA 73
GPIO14/AB2B_CLK 74
GPIO15/FAN_TACH1 75
GPIO16/FAN_TACH2 76
GPIO17/A20M 77
GPIO20/PS2CLK 78
GPIO21/PS2DAT 80
AB1A_DATA 86
AB1A_CLK 87
AB1B_DATA 84
AB1B_CLK 85
PGM Strap/GPIO25 56
GPIO01 82
EA Strap#/GPIO26/KSO17 83
CLOCK 48
32KHZ_OUT/GPIO22 58
RESET_OUT#/GPIO06 49
PWRGD 61
VCC1_PWRGD 60
24MHZ_OUT/GPIO19/WINDMON 50
GPIO24/KSO16 1
GPIO27 57
DMS_LED#/GPIO10 91
BAT_LED# 88
PWR_LED#/8051TX 90
FDD_LED#/8051RX 89
RP23
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5 R185 0_0402_5%1021@
1 2
R260 33_0402_5%@1 2
R235 1K_0402_5%
12
R197
10K_0402_5%
1 2
R261 0_0402_5%
1 2
R2810_0402_5%250@
1 2
R399 0_0402_5%@1 2
R263
100K_0402_5%
1 2
R249300_0402_5%
1 2
R6520_0402_5%@
1 2
C243
0.1U_0402_16V4Z
1
2
R214 0_0402_5%
1 2
RP22
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R216
10K_0402_5%
1 2
C236
4.7U_0805_10V4Z
1
2
R238
0_0402_5%1021@
1 2
D24
CH751H-40_SC76
2 1
C226
0.1U_0402_16V4Z
1
2
C209
0.1U_0402_16V4Z
1
2
RP21
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R2761K_0402_5%@1 2
JP21
ACES_85201-0602@
1
2
3
4
5
6
R647
100K_0402_5%
1 2
C268
10P_0402_50V8J
1
2
R267 1K_0402_5%@1 2
R2800_0402_5%250@
1 2
R2230_0402_5%@
1 2
D26
CH751H-40_SC76 21
R266
120K_0402_5%
12
R232
10_0402_5%@
12
R262
10K_0402_5%
1 2
R2150_0402_5%@
1 2
C215
0.1U_0402_16V4Z
1
2
R250
100K_0402_5%
1 2
R268 10K_0402_5%250@
1 2
R251 0_0402_5%
1 2
R2040_0402_5%
1 2
C254
0.1U_0402_16V4Z
1 2
R264 0_0402_5%
1 2
RP24
4.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
C255
0.1U_0402_16V4Z
1
2
R205
10K_0402_5%
12
C257
4.7U_0805_10V4Z
1
2
R259
210K_0402_1%
1 2
R2652M_0402_5%@
1 2
C196
0.1U_0402_16V4Z
1
2
R254 1K_0402_5%@12
ON/OFF#
KSO2
MUTE_LED#
KSI5
KSI7
KSI6
STB_LED
KSI0
NUM_LED#
CAPS_LED#
KSI1
WL/BT_LED
KSI2
KSI4
AC97_RST#_MDC
AC97_SYNC_MDC
AC97_SDIN1_MDC
ON/OFFBTN#
ON/OFFBTN_KBC#
ON/OFF#
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI4
KSI7
KSI3
KSI0
KSI5
KSI1
KSI2
KSI6
KSI[0..7]
KSO2
KSO[0..17]
KSO0
KSO5
KSO7
KSO8
KSO3
KSO4
KSO6
KSO10
KSO9
KSO1
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI4
KSI7
KSI3
KSI0
KSI5
KSI1
KSI2
KSI6
KSO2
KSO0
KSO3
KSO2
KSO0
KSO5
KSO7
KSO8
KSO4
KSO3
KSO4
KSO6
KSO10
KSO9
KSO1
KSO5
KSO7
KSO8
KSO6
KSO11
KSO14
KSI7
KSI0
KSO10
KSO9
KSO12
KSO13
KSO17
KSO1
KSO15
KSO16
KSI3
KSI2
KSI4
KSI5
KSI1
KSI6
TP_CLK
SP_CLK
SP_DATA
TP_DATA
SP_DATA SP_CLK
AC97_SDOUT_MDC
AC97_BITCLK_MDC
LID_SW#
LID_SW#_2nd
LID_SW#_2nd
NUM_LED#27,33
MUTE_LED#29
CAPS_LED#27,33
WL/BT_LED32
STB_LED32
ON/OFFBTN#21
ON/OFF#35
ON/OFFBTN_KBC#33
KSI[0..7]33
KSO[0..17]33
TP_CLK33 TP_DATA33
AC97_SDIN120
AC97_SYNC_MDC20
AC97_BITCLK_MDC20AC97_RST#_MDC20
AC97_SDOUT_MDC20
LID_SW#17,21
+3VS +3VL +5VS
+3VS
+3VS
+3VALW
+3VL
+3VL
+3VL
+5VS
+5VS
+5VS +5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
MDC/KBD/ON_OFF/LID
3452Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
SWITCH BOARD.
MDC 1.5 Conn.
Power button
Update to 18x8 angelfire keyboard matrix
INT_KBD CONN.
TrackPoint CONN.T/P BOARD.
11/3
11/3
R163
100K_0402_5%
12
CP4
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
G
D
S
Q29
2N7002_SOT23
2
13
Connector for MDC Rev1.5
JP26
TYCO_1-179396-2~DMDC1.5@
GND1
1
IAC_SDATA_OUT
3
GND2
5
IAC_SYNC
7
IAC_SDATA_IN
9
IAC_RESET#
11
RES0 2
RES1 4
3.3V 6
GND3 8
GND4 10
IAC_BITCLK 12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
JP12
ACES_85203-26021
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
CP7
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
CP2
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
R239
33_0402_5%
1 2
R10_0402_5%
1 2
C220
1000P_0402_50V7K MDC1.5@
1
2
R167
100K_0402_5%
12
R179
100K_0402_5%
1 2
JP11
E&T_6700-Q08N-00R
11
33
55
77
2
24
46
68
8
C490
0.1U_0402_16V4Z
1
2
JP14
ACES_87212-0800
1
2
3
4
5
6
7
8
U15F
SN74LVC14APWLE_TSSOP14
O12
I
13
P14
G
7
C177
1U_0603_10V4Z
1
2
C183
1U_0603_10V4Z
1
2
CP3
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
R20910_0402_5%@
12
R172
100K_0402_5%
1 2
D23
RB751V_SOD323
21
CP1
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
C223
0.1U_0402_16V4ZMDC1.5@
1
2
CP6
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
C204
4.7U_0805_10V4Z@
1
2
CP5
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
C116
0.1U_0402_16V4Z
1
2
C221
10P_0402_25V8K@
1 2
JP1
ACES_88028-3000
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
23
23 21
21
17
17
19
19
25
25
27
27
29
29
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
A B C D
D
E
E
11
22
33
44
DCD#1
LAN_ACT#_DOCK
MDO0-
ON/OFF#
PWR_LED
RXD1
MDO3+
MDO3-
MDO1-
MDO1+
MDO2-
D_BLUE
DSR#1
D_BLUE
BLUE
ISO_PREP#
DVI_TX0+
DVI_TX2-
DVI_TX2+
DVI_CLK-
DVI_TX1+
DVI_TX0-
DVI_CLK+
DVI_TX1-
D_GREEN
GREEN
ISO_PREP#
RED
D_RED
ISO_PREP#
D_RED RED
LPTSTB#
D_DDCCLK
D_GREEN
D_BLUE
GREEN
BLUE
RI#1
SLP_S5#_5R
LPTAFD#
DETECT
D_RED
RTS#1
TXD1
DVI_DETECT
MDO0+
D_GREEN
DVI_DDC_DAT
DVI_DDC_CLK
CTS#1
MDO2+
DTR#1
LANLINK_STATUS#_DOCK
LPTERR#
D_DDCDATA
SLP_S5#_5R DOCK_MOD_TIP
DOCK_MOD_RING
DOCK_HPS#
CPPE#
CLK_PCIE_DOCK#
CLK_PCIE_DOCK
LPTBUSY
SER_SHD
USB20_P6
LPTSLCTIN#
LPTINIT#
PREP#
LPTACK#
LPTSLCT
DLINE_IN_R
DLINE_IN_L
DETECT
LPTPE
PCIE_TXP4
PCIE_TXN4
EXPCRD_RST#
PS2_DATA
PS2_CLK
LPD0
LPD1
LPD4
LPD2
LPD5
LPD6
LPD3
LPD7
VA_ON#
USB20_N7
USB20_N6
USB20_P7
USB20_N6_R
DOCK_MOD_TIPDOCK_MOD_RING
DLINE_OUT_L
KBD_DATA
KBD_CLK
DLINE_OUT_R
USB20_P6_R
USB20_N7_R
USB20_P7_R
LAN_ACT#_DOCK
LAN_ACT#
LANLINK_STATUS#_DOCK
LANLINK_STATUS#
PWR_LED
PCIE_C_RXP4
PCIE_C_RXN4 PCIE_RXN4
PCIE_RXP4
DOCK_ID
DOCK_ID
DOCK_ADP_SIGNAL
DOCK_ADP_SIGNAL
PREP#
D_BLUE18 BLUE16 D_GREEN18 GREEN16 D_RED18 RED16
MDO1-26
MDO1+26
MDO3-26
MDO3+26
MDO2+26 MDO2-26
MDO0-26 MDO0+26
D_VSYNC16 D_HSYNC16
DVI_DETECT18
M_COMP16,18 M_CRMA16,18 M_LUMA16,18
ON/OFF#34
D_DDCCLK16 D_DDCDATA16
RXD131
RTS#131
DCD#131 RI#131DTR#131
DSR#131
CTS#131
TXD131
LPTSTB#31 LPTAFD#31 LPTERR#31
DVI_DDC_DAT18
DVI_DDC_CLK18
DVI_TX2-18
DVI_TX1+18
DVI_TX2+18
DVI_TX1-18
DVI_CLK-18
DVI_CLK+18
DVI_TX0-18
DVI_TX0+18
SLP_S529,30,36
SER_SHD31
PREP#21,26
LPTACK#31
LPTINIT#31
LPTSLCTIN#31
LPD531 LPD431
LPD131 LPD031
LPD231 LPD331
LPD731 LPD631
LPTBUSY31 LPTPE31LPTSLCT31
KBD_DATA33
KBD_CLK33
PS2_DATA33
PS2_CLK33
CLK_PCIE_DOCK15
CLK_PCIE_DOCK#15
PCIE_TXN421
PCIE_TXP421
DOCK_HPS#29
DLINE_IN_L28
DLINE_IN_R28
DLINE_OUT_L29
DLINE_OUT_R29
CPPE#15,19
USB20_N721
USB20_P721
EXPCRD_RST#31
USB20_P621
USB20_N621
LAN_ACT#25,26
LANLINK_STATUS#25,26
STB_LED#27,32,33
SLP_S3#18,21,25,27,28,29,33,36,40,43,44
ISO_PREP#21
PCIE_RXP421
PCIE_RXN421
DOCK_ID21
DOCK_ADP_SIGNAL
ACOCP_EN#47
LINE_IN_SENSE28
DOCKVINVIN
+3VS+3VS
DOCKVIN
+3VS
+5VALW
+5VS
+3VALW V_3P3_LAN
+3VS
ADP_SIGNAL
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
Docking CONN.
3552Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
Place them close to U50/U51/U52
DOCK CONN. 184PIN
5/24
L
Note: Place C1 close to JP27.P2 pin
9/15
11/18
11/22
11/23
11/22
C5
0.1U_0402_16V4Z
1 2
L14
KC FBM-L18-453215-900LMA90T_1812
12
R352
10K_0402_5%
12
R304 0_0402_5%12
R6 0_0402_5% @
1 2
JP27A
JAE_SP03-14588-PCL03
P1G1
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
C314
1000P_0402_50V7K
1
2
C291
0.1U_0402_16V4Z
1
2
C1
22U_0805_6.3V4Z@
1 2
R9
10K_0402_5%@
1 2
C305
1000P_0402_50V7K
1
2
R299
1K_0402_1%
1 2
R357
220K_0402_5%
12
G
D
S
Q62
2N7002_SOT23
2
13
R4
0_0402_5%
1 2
JP27B
JAE_SP03-14588-PCL03
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
64
64
65
65
66
66
67
67
68
68
69
69
70
70
71
71
72
72
73
73
74
74
75
75
76
76
77
77
78
78
79
79
80
80
81
81
82
82
128 128
129 129
130 130
131 131
132 132
133 133
134 134
135 135
136 136
137 137
138 138
139 139
140 140
141 141
142 142
143 143
144 144
145 145
146 146
147 147
148 148
149 149
150 150
151 151
152 152
153 153
154 154
155 155
156 156
157 157
158 158
159 159
160 160
161 161
162 162
163 163
164 164
G2
G2
RING
RING TIP TIP
P2 P2
GND
165
GND
166
GND
167
GND
168
GND
169
GND 171
GND 172
GND 173
GND 174
GND 175
GND 176
GND
170
R34610K_0402_5%
1 2
G
D
S
Q77
2N7002_SOT23@
2
13
R300 0_0402_5%12
R671
22K_0402_5%@1 2
R7 0_0402_5%@
1 2
U1
FSA66P5X_SC70-5
A
1
B
2
GND
3
OE
4
VCC
5
R298 0_0402_5%12
G
D
S
Q59
2N7002_SOT23
2
13
U2
FSA66P5X_SC70-5
A
1
B
2
GND
3
OE
4
VCC
5
JP2
ACES_85205-0200
1
2
G
D
S
Q61
2N7002_SOT23
2
13
R372
10K_0402_5%
12
C8
0.1U_0402_16V4Z
1 2
G
D
S
Q58
2N7002_SOT23
2
13
R3
0_0402_5%
1 2
U3
FSA66P5X_SC70-5
A
1
B
2
GND
3
OE
4
VCC
5
R302
1K_0402_5%
12
R5 0_0402_5% @
1 2
R301 0_0402_5%12
C6
0.1U_0402_16V4Z
1 2
C546
1U_0603_10V6K
@
1
2
A B C D
D
E
E
11
22
33
44
SLP_S3#
RUNON RUNON
SLP_S5
SLP_S5#
SLP_S3
SLP_S3 SLP_S3 SLP_S3 SLP_S3
SLP_S3
RUNON
SLP_S3SLP_S5SLP_S5
SLP_S3
RUNON
SLP_S3#18,21,25,27,28,29,33,35,40,43,44
SLP_S5#21,44
SLP_S529,30,35
PWR_GD18,33,37,45,47
+1.8VS
+3VL
+2.5VS
+5VS+5VALW +1.8V
+5VALW
+3VS +5VS
+1.8VS
+3VS+3VALW
+0.9V +1.5VS+1.8V
B+
+1.5VS +3VS
+3VS +5VS
+3VS +5VS
+VCCP +3VALW
+3VS +3VALW
+2.5VS+2.5VALW
+VCCP +3VS
+3VALW
+3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
DC/DC Circuits
3652Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
+1.8V to +1.8VS Transfer
Discharge circuit
+3VALW to +3VS Transfer
+5VALW to +5VS Transfer
+2.5VALW to +2.5VS Transfer
G
D
S
Q9
2N7002_SOT23
2
13
C290.1U_0603_50V4Z
1 2
C280
10U_0805_10V4Z
1
2
C487
0.1U_0402_16V4Z
1
2
J3
PAD-SHORT 2x2m
21
R62
100K_0402_5%
12
R572
0_0402_5%
1 2
C1390.1U_0603_50V4Z@
1 2
G
DS
Q53
SI2306DS-T1 1N_SOT23
2
1 3
U37
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C458
10U_0805_10V4Z
1
2
R574
470_0402_5%
12
C2900.1U_0402_16V4Z
1 2
G
D
S
Q43
2N7002_SOT23
2
13
R583
470_0402_5%
12
G
D
S
Q73
2N7002_SOT23
2
13
C501
0.01UF_0402_25V7K
1
2
G
D
S
Q16
2N7002_SOT23
2
13
R573
0_0402_5%@1 2
C1550.1U_0603_50V4Z@
1 2
R582
330K_0402_5%
12
C456
10U_0805_10V4Z
1
2
R571
470_0402_5%
12
G
D
S
Q19
2N7002_SOT23
2
13
C271
0.1U_0402_16V4Z
1
2
G
D
S
Q18
2N7002_SOT23
2
13
G
D
S
Q74
2N7002_SOT23
2
13
C295
1U_0603_10V4Z
1
2
R138
470_0402_5%
12
C509
10U_0805_10V4Z
1
2
G
D
S
Q7
2N7002_SOT23
2
13
R32
470_0402_5%
12
C5260.1U_0603_50V4Z@
1 2
C514
10U_0805_10V4Z
1
2
C4190.1U_0402_16V4Z
1 2
C1410.1U_0603_50V4Z@
1 2
U22
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
R94
470_0402_5%
12
R577
470_0402_5%
12
U32
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
R93
470_0402_5%
12
C510
0.1U_0402_16V4Z
1
2
G
D
S
Q75
2N7002_SOT23
2
13
C277
10U_0805_10V4Z
1
2
C5240.1U_0603_50V4Z@
1 2
C296
1U_0603_10V4Z
1
2
R244
100K_0402_5%
12
J15
PAD-SHORT 2x2m
2 1
G
D
S
Q72
2N7002_SOT23
2
13
PWR_GD
CLK_ENABLE#
PGD_INPWR_GD
PGD_IN_1
VCC1_PWRGD33
PWR_GD18,33,36,45,47
VCCP_POK43
CLK_ENABLE#15,45
PGD_IN33,45
PGD_IN_145
+1.5VS +2.5VS+2.5VS
+3VL
+3VL
+3VL
+5VS
+3VS
+3VS+3VS
+1.8VS +3VL+3VL
+3VL
+3VL
+3VS +3VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
POK CKT
3752Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
UNUSED PARTS
CPU
L
Need be tune to
3msec time delay
11/21
11/21
E
B
C
Q25
MMBT3904_SOT23
2
3 1
E
B
C
Q26
MMBT3904_SOT23
2
3 1
H1
HOLEA
1
R181
560K_0402_5%
12
U33
SN74LVC1G17DBVR_SOT23-5
O4
I
2
P5
G
3
NC 1
R210
330_0402_5%
1 2
C176
0.1U_0402_16V4Z
1
2
FM3
1
H16
HOLEA
1
H8
HOLEA
1
H21
HOLEA
1
C186
0.1U_0402_16V4Z
1
2
H23
HOLEA
1
H26
HOLEA
1
H17
HOLEA
1
H9
HOLEA
1
CF2
1
H13
HOLEA
1
H11
HOLEA
1
CF4
1
CF11
1
C190
0.1U_0402_16V4Z
1
2
H15
HOLEA
1
D33RB751V_SOD323
21
M2
HOLEA
1
H5
HOLEA
1
R156
10K_0402_5%
12
CF6
1
U15E
SN74LVC14APWLE_TSSOP14
O10
I
11
P14
G
7
H10
HOLEA
1
H4
HOLEA
1
H19
HOLEA
1
R581
0_0402_5%@1 2
C181
0.1U_0402_16V4Z
1
2
U34
SN74LVC1G17DBVR_SOT23-5
O4
I
2
P5
G
3
NC 1
R177
180K_0402_5%
12
FM4
1
CF8
1
H12
HOLEA
1
H3
HOLEA
1
CF12
1
M1
HOLEA
1
J8
PAD-SHORT 2x2m
21
H27
HOLEA
1
G
D
S
Q33
2N7002_SOT23
2
13
R578
0_0402_5%
1 2
H25
HOLEA
1
U15A
SN74LVC14APWLE_TSSOP14
O2
I
1
P14
G
7
FM1
1
H18
HOLEA
1
FM6
1
R178
330_0402_5%
1 2
C502
0.1U_0402_16V4Z
1
2
D20
RB751V_SOD323
21
R579
0_0402_5%@1 2
R188
10K_0402_5%
12
CF1
1
H24
HOLEA
1
CF3
1
H14
HOLEA
1
H6
HOLEA
1
R580
100K_0402_5%
1 2
CF10
1
R157
330_0402_5%
1 2
R171
47K_0402_5%
1 2
G
D
S
Q23
2N7002_SOT23
2
13
PAD1
PAD-R118x71
1
R196
1K_0402_5%
1 2
C497
0.1U_0603_16V7K
1
2
CF5
1
U15D
SN74LVC14APWLE_TSSOP14
O8
I
9
P14
G
7
R184
100K_0402_5%
12
E
B
C
Q31
MMBT3904_SOT23
2
3 1
R158
330_0402_5%
1 2
H20
HOLEA
1
U15C
SN74LVC14APWLE_TSSOP14
O6
I
5
P14
G
7
C500
0.1U_0402_16V4Z
1
2
FM2
1
R139
1K_0402_5%
1 2
G
D
S
Q24
2N7002_SOT23
2
13
CF9
1
U15B
SN74LVC14APWLE_TSSOP14
O4
I
3
P14
G
7
H2
HOLEA
1
FM5
1
E
B
C
Q32
MMBT3904_SOT23
2
3 1
CF7
1
5432
2
1
1
DD
CC
BB
AA
Title
SizeDocument NumberRev
Date:Sheet of
POWER BLOCK DIAGRAM
3852Friday, November 25, 2005
AC
Adapter
in
Battery
Connector
A
Battery
Connector
B
Battery A
8 Cell Battery B
8 Cell
TPS51020
DC/DC
(3V/5V)
ISL6260&ISL6208
DC/DC
(CPU_CORE)
APL5151
LDO
(3V)
SHDN#
+3VALWP
+5VALWP
CPU_CORE
( 44A)
VCCSHDN#
PWR_GD
+5VS
BQ24703
Charger
VL
B+B+
B+
+3VLP 0.1A
+1.5VSP 4.2A
+1.05V_VCCP 6.4A
BATT_A
BATT_B
BATT
VIN
SWITCHADP_EN#
ENBL1/ENBL2
SLP_S3#
MAINPWON
B+ TPS51116
DC/DC
(+1.8VP/+0.9VSP)
VCC
+0.9VP 2A
S3/S5
SLP_S3#/SLP_S5#
+1.8VP 7A
VL
ENBL2ENBL1
MAX8743
DC/DC
(1.05V/1.5V)
VIN
SWITCHSWITCH
VL
Battery
Selector
Circuit
BATSELB_A
SWITCH
BATSELB_A#
LM358
Thermal
Protector
+5VALWP
APL5508
LDO
(2.5V)
+3VALWP
+2.5VALWP 0.4A
ABC
C
D
D
11
22
33
44
ADPIN
VIN
ADP_SIGNAL
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
DCIN
Custom
3952Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
PJP13
FOX_JPD113E-LB103-7F
SINGAL 5
PWR1 1
PWR2 2
GND2
4
GND1
3
GND_1
6
GND_2
7
GND_3
8
GND_4
9
PC1
100P_0402_50V8J
12
PC3
100P_0402_50V8J
12
PC2
1000P_0402_50V7K
12
PC4
1000P_0402_50V7K
12
PL1
FBMA-L18-453215-900LMA90T_1812
1 2
PR1
15K_0402_5%
12
ABC
C
D
D
11
22
33
44
DH_CHG
LX_CHG
ALARM
AC_CHG
AC_CHG
ACDRV#
ACDRV#
ACDET
ADP_PRES
SE_CHG+
SE_CHG-
CHG_B+
CHGCTRL33,41
ALARM41
AC_CHG41
SLP_S3#
18,21,25,27,28,29,33,35,36,43,44
ADP_EN#47
ACN47
ADP_PRES18,25,33,41,42,47
CHGLIM47
VIN
P4
BATT
P2
VL BATT BATT
BQ24703VREF
+3VL
+3VL
BQ24703VREF
+3VL
VL
P2
+3VL
1.24VREF
+3VL
P2
+3VL
BATT
B+
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
Charger
Custom
4052Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
CV=16.8V (8 CELLS LI-ION)
CC=3A
PU6
LMV431ACM5X_SOT23-5
NC 2
REF
4
NC 1
CATHODE 3
ANODE
5
PR38
3K_0402_1%
12
PR52
4.7K_0402_5%
12
PR26
0_0402_5%
12
PR31
191K_0402_1%
1 2
PR17
0_0402_5%
1 2
PR64
15K_0402_1%
12
PR35
100K_0402_1%
1 2
PC12
4.7U_1206_25V6K
12
PC17
10U_1206_25VAK
12
PR62
10K_0603_1%
12
PC22
0.1U_0402_10V6K
12
PR20
150K_0402_5%
1 2
PL2
FBM-L11-322513-151LMAT_1210
1 2
PR44
100K_0603_1%
12
PC15
1U_0603_6.3V6M
12
PR45
10K_0402_1%
12
PD32
1N4148_SOD80
@
1 2
PR16 47K_0402_5%
1 2
PR57
47K_0603_0.5%
12
PR376
0_0402_5% @
12
PQ5
AO4407_SO8
36
5
7
82
4
1
PC26
0.022U_0402_16V7K
12
PR372
0.015_2512_1%
1 2
PR15
0_0402_5%
1 2
PC205
470P_0402_50V7K
12
PC11
10U_1206_25VAK
12
PR32
100K_0402_5%
12
PC21
150P_0402_50V8J
12
PU4
SN74LVC1G17DBVR_SOT23-5
O4
I
2
P5
G
3
NC 1
PR33
0.015_2512_1%
1 2
PR58
100K_0402_5%
1 2
PC14
1U_0805_25V4Z
12
PC25
100P_0402_50V8J
12
PC18
4.7U_0805_6.3V6K
12
PL3
15U_PLC1045P-150A_3.7A_20%
1 2
PC16
4.7U_1206_25V6K
12
EC31QS04
PD8
12
PC23
4.7U_0805_10V6K
12
PQ3
AO4407_SO8
3 6
5
7
8
2
4
1
PC138
0.1U_0603_16V7K
12
PU5B
LM393DG_SO8
+
5
-
6O7
P8
G
4
PC24
0.1U_0402_16V7K
@
12
PC19
0.1U_0402_16V7K
1 2
PU5A
LM393DG_SO8
+
3
-
2O1
P8
G
4
PC10
47P_0402_50V8J
1 2
PR55
130K_0402_1%
12
PR50
10K_0603_0.1%
12
PR39
3K_0402_1%
12
PR240
2.15K_0402_1%
1 2
G
D
S
PQ12
RHU002N06_SOT323
2
13
PR41
80.6K_0402_1%
12
PR42
330K_0402_5%
1 2
PR49
12.4K_0603_0.1%
12
PR61
100_0402_5%
12
PR51
604K_0402_1%
12
PR339
1K_0402_1%
1 2
PR14
200K_0402_5%
12
PD33
1N4148_SOD80
12
47K
47K
PQ6
DTA144EUA_SC70
2
13
PQ8
SI4835BDY-T1-E3_SO8
16
5
7
82
4
3
PD6
RLZ16B_LL34
2 1
PR43
150_0402_1%
12
PR59
75K_0402_1%
12
PR56
1M_0402_5%
1 2
G
D
S
PQ91
RHU002N06_SOT323
@
2
13
PU2
BQ24703_QFN28
ENABLE
5
ACSEL
28
ALARM
19
SRSET
2
ACSET
3
IBAT
13
VREF
4
ACN
8
ACP
9
ACDET
26
ACPRES
27 VHSP 20
GND 17
BATDEP 1
BATSET 6
BATDRV# 24
BATP 12
SRN 15
SRP 16
PWM# 21
COMP
7
VCC 22
VS 18
ACDRV# 25
NC4 23
NC3 14
NC1
10
NC2
11
PR47
604K_0603_0.1%
12
PR338
100_0402_1%
12
PC20
1U_0603_6.3V6M
12
PR29
1K_0402_1%
12
PR63
47K_0402_1%@
12
PR36
100K_0402_1%
12
PQ4
AO4407_SO8
3 6
5
7
8
2
4
1
PR67
33K_0402_1%
1 2
PC198
1U_0603_6.3V6M
1 2
G
D
S
PQ13
RHU002N06_SOT323
2
13
ABC
C
D
D
11
22
33
44
ADP_PRES
BATT_IN
BATSELB_A#
BATSELB_A
BATSELB_A#
BATSELB_A#
BATT_IN
CFET_A
CFET_B
CFET_A
BATT_IN
CFET_B
BATT_IN
BATT_IN
BATSELB_A
CHGCTRL33,40
AC_CHG40
BATSELB_A#33
ALARM40
ADP_PRES18,25,33,40,42,47
BATCON33
BATT
+3VL
+3VL
BATT
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
BATT_A
BATT_B
+3VL
BATT_A
BATT_B
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
Battery selector
Custom
4152Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
G
D
S
PQ18
RHU002N06_SOT323
2
13
PR68
100_0402_5%
1 2
PU7
74LVC1G02_04_SOT353
INB
1
INA
2
P5
G
3
O4
PU14
SN74LVC1G17DBVR_SOT23-5
O4
I
2
P5
G
3
NC 1
PD14
1N4148_SOD80
12
PR85
470K_0402_5%
1 2
PD15
B540C_SMC
21
PR81
470K_0402_5%
12
PQ25
AO4407_SO8
36
5
7
82
4
1
PU10
SN74LVC1G14DCKR_SC70-5
A
2Y4
P5
NC 1
G
3
G
D
S
PQ20
RHU002N06_SOT323
2
13
PR80
470K_0402_5%
12
PR74
470K_0402_5%
12
PR72
22K_0402_5%
1 2
PD10
1N4148_SOD80
1 2
PR79
470K_0402_5%
12
PR237
100K_0402_5%
12
G
D
S
PQ34
RHU002N06_SOT323
2
13
PR73
22K_0402_5%
1 2
PR76
10K_0402_5%
12
PR71
1.5M_0402_5%
12
G
D
S
PQ23
RHU002N06_SOT323
2
13
PU13
SN74AHC1G08DCKR_SC70
IN1
1
IN2
2
G
3
O4
P5
PQ28
AO4407_SO8
36
5
7
82
4
1
PU8
74LVC1G02_04_SOT353
INB
1
INA
2
P5
G
3
O4
PD13
B540C_SMC
21
PC197
220P_0402_50V7K
12
G
D
S
PQ32
RHU002N06_SOT323
2
13
G
D
S
PQ30
RHU002N06_SOT323
2
13 PD16
1N4148_SOD80
1 2
G
D
S
PQ16
RHU002N06_SOT323
2
13
PR69
0_0402_5%
1 2
G
D
S
PQ17
RHU002N06_SOT323
2
13
G
D
S
PQ31
RHU002N06_SOT323
2
13
PR70
47K_0402_5%
1 2
PD17
RB715F_SOT323
2
31
G
D
S
PQ19
RHU002N06_SOT323
2
13
PD9
RB715F_SOT323
2
31
PQ29
PMBT2222A_SOT23-3
1
2
3
PR82
220K_0402_5%
1 2
PC30
1000P_0402_50V7K
1 2
PQ24
AO4407_SO8
3 6
5
7
8
2
4
1
G
DS
PQ15
RHU002N06_SOT323
2
1 3
PR78
10K_0402_5%
1 2
PC31
0.22U_0402_10V4Z
12
G
D
S
PQ22
RHU002N06_SOT323
2
13
PR75
470K_0402_5%
1 2
G
D
S
PQ33
RHU002N06_SOT323
2
13
PQ27
AO4407_SO8
3 6
5
7
8
2
4
1
PC29
0.1U_0603_50V4Z
12
PC27
0.1U_0402_10V6K @
12
PQ21
PMBT2222A_SOT23-3
1
2
3
G
D
S
PQ26
RHU002N06_SOT323
2
13
PU11
SN74AHC1G08DCKR_SC70
IN1
1
IN2
2
G
3
O4
P5
PU9
SN74LVC1G14DCKR_SC70-5
A
2Y4
P5
NC 1
G
3
PD12
1N4148_SOD80
1 2
PU12
SN74LVC1G17DBVR_SOT23-5
O4
I
2
P5
G
3
NC 1
PR83
470K_0402_5%
1 2
PC28
1000P_0402_50V7K
1 2
PD11
RLZ6.2C_LL34
2 1
PR87
10K_0402_5%
12
PR86
4.7K_0402_5%
12
PR77
4.7K_0402_5%
12
PR88
10K_0402_5%
1 2
PR84
10K_0402_1%
1 2
5432
2
1
1
DD
CC
BB
AA
DH_3.3V_2
BST_3.3V
LX_5V
DL_5V
DL_3.3V
DH_5V_1
DH_5V_2
BST_5V
DH_3.3V_1
LX_3.3V
ADP_PRES
+3VALW_POK
+3VALW_POK
KBC_PWR_ON33 ADP_PRES18,25,33,40,41,47
LX_5V47
MAINPWON46
B+
B++
+5VALWP
+3VALWP
+5VALWP
B++
VL
+5VALWP
VL +3VLP
VL
VL
VL
+3VALWP
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
3.3VALW/5VALW
Custom
4252Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
PC53
0.33U_0603_10V7K@
12
PU16
APL5151_SOT23-5
Vout 5
GND
2
Vin
1
SHDN#
3BP 4
PR112
330_0402_5%
12
PR111
29.4K_0402_1%
1 2
PC51
1U_0603_10V6K
12
PC40
4.7U_0805_10V4Z
12
PR90
49.9K_0402_1%
1 2
PR102
100K_0402_5%
1 2
PC44
4.7U_1206_25V6K
12
PC50
3300P_0603_50V7K
12
PC32
4700P_0603_50V7K
12
PQ101
SI2301BDS-T1-E3_SOT23-3
2
1 3
PR113
10K_0402_1%
1 2
PC46
820P_0603_50V7K
1 2
PC37
4700P_0603_50V7K
12
+
PC39
220U_D3L_6.3M_R40
1
2
G
D
S
PQ40
RHU002N06_SOT323
2
13
PR109
10K_0402_5%
1 2
PR101
0_0402_5%
1 2
PL6
10U_PLC1045-100_3.6A_20%
1 2
PR369
100K_0402_5%
12
PC52
1U_0603_10V6K
12
PC35
2.2U_1206_25V7K
12
PR108
0_0402_5%
@
1 2
G
D
S
PQ39
RHU002N06_SOT323
2
13
PR107
100K_0402_5%
12
PR104
0_0402_5%
12
PR91
330_0402_5%
12
PR103
0_0402_5%
@
1 2
PC36
0.1U_0603_50V4Z
12
PC48
4700P_0402_25V7K
12
PL4
FBM-L11-322513-151LMAT_1210
12
PR99
10K_0402_1%
1 2
PC42
0.47U_0603_10V7K
12
PQ42
SI2301BDS-T1-E3_SOT23-3
2
13
PC34
2200P_0402_50V7K
12
PR96
2.7K_0402_1%
12
PR187
154K_0603_1%
1 2
+
PC199
220U_D3L_6.3M_R40
1
2
PR335
0_0402_5%
12
PC45
2200P_0402_50V7K
12
PL5
10U_PLC1045-100_3.6A_20%
1 2
PR105
1M_0402_5%@
12
AO4912_SO8
PQ37
D2 2
G2
8
G1 3
D1/S2/K
5
D2 1
D1/S2/K
7
S1/A 4
D1/S2/K
6
PR97
17.4K_0402_1%
12
PC410.1U_0402_16V7K
1 2
PR106
1M_0402_5%
12
PR110
3.9K_0402_1%
12
PU15
TPS51020DBTR_TSSOP30
INV2
15
OUT2_D 19
COMP2
14
VBST2 16
REG5_IN
21
ENBL1
9
DDR#
6
SKIP#
4
TRIP2 23
VO2 11
OUTGND1 26
OUT1_D 27
SSTRT2
13
VIN 24
VREG5
22
GND
7
COMP1
2
PGOOD
12
SSTRT1
3
REF_X
8
ENBL2
10 OUT2_U 17
OUTGND2 20
VO1_VDDQ 5
LL1 28
TRIP1 25
LL2 18
INV1
1
OUT1_U 29
VBST1 30
PC43
0.1U_0603_50V4Z
12
PC47
820P_0603_50V7K
1 2
PR100
0_0402_5%
1 2
PC120
1500P_0402_50V7K
@
12
+
PC38
150U_D2_6.3VM_R45
1
2
G
D
S
PQ98
RHU002N06_SOT323
2
13
AO4912_SO8
PQ38
D2 2
G2
8
G1 3
D1/S2/K
5
D2 1
D1/S2/K
7
S1/A 4
D1/S2/K
6
PR115
100K_0402_5%
12
PR365
100K_0402_5%
12
PR98
12.7K_0402_1%
12
PC33
10U_1206_25VAK
12
G
D
S
PQ41
RHU002N06_SOT323
2
13
ABC
C
D
D
11
22
33
44
LX_1.05V LX_1.5V
DH_1.5V_1
BST_1.05V_1
BST_1.5V_1
VCC_MAX8743
BST_1.5V_2
DH_1.05V_1
DH_1.05V_2
BST_1.05V_2
DL_1.05V
VCC_MAX8743
DL_1.5V
DH_1.5V_2
SLP_S3# SLP_S3#
VCCP_POK37
SLP_S3#18,21,25,27,28,29,33,35,36,40,44
SLP_S3#18,21,25,27,28,29,33,35,36,40,44
B+
+5VALW
+1.05V_VCCP
+1.5VSP
MAX8743_B+
2VREF
+2.5VALWP
+3VALWP
+1.5VS
+VCCP
+1.5VSP
+1.8V
+1.8VP
+0.9V
+0.9VP
+1.05V_VCCP
+5VALWP
+3VALWP
+5VALW
+3VALW
+3VLP +3VL
+2.5VALWP +2.5VALW
+5VALW
+5VALW
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
2.5VALW/1.5VS/1.05VCCP
Custom
4352Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
1.5VSP/ +1.05V_VCCP/+2.5VALWP
(400mA,40mils ,Via NO.= 1)
(6A,240mils ,Via NO.= 12)
(7A,280mils ,Via NO.= 14)
(4A,160mils ,Via NO.=8)
(2A,80mils ,Via NO.= 4)
(100mA,20mils ,Via NO.= 1)
(3A,120mils ,Via NO.= 6)
(4.5A,180mils ,Via NO.= 9)
(400mA,40mils ,Via NO.= 1)
PR260
100K_0402_5%
12
+
PC191
330U_D2E_2.5VM
1
2
PR370
0_0402_5%@
1 2
AO4912_SO8
PQ86
D2
2G2 8
G1
3
D1/S2/K 5
D2
1
D1/S2/K 7
S1/A
4D1/S2/K 6
PR265
0_0402_5% @ 12
PJP6
PAD-OPEN 2x2m
2 1
PR332
20_0603_5%
12
PC185
4.7U_1206_25V6K
12
PR333
0_0402_5%
1 2
PJP4
PAD-OPEN 4x4m
1 2
PC57
4.7U_1206_25V6K
12
PR371
0_0402_5%@
12
PR267
100K_0402_1%
12
PJP11
PAD-OPEN 2x2m
2 1
PR327
0_0402_5%
1 2
PR259
100K_0402_5%
12
G
D
S
PQ94
RHU002N06_SOT323
2
13
PR266
100K_0402_1%
12
PR342
0_0402_5%
1 2
PR263
0_0402_5%
12
+
PC203
220U_B2_2.5VM
1
2
PQ79
AO4404_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PC200
0.001U_0402_50V7M@
12
G
D
S
PQ95
RHU002N06_SOT323
2
13
PJP2
PAD-OPEN 4x4m
1 2
PC147
0.22U_0603_10V7K
12
G
D
S
PQ92
RHU002N06_SOT323
2
13
PU28
MAX8743EEI+T_QSOP28~N
OUT2 15
BST2 19
FB2 14
CS2 16
VDD 21
UVP 9
SKIP
6
V+ 4
GND
23
ON1
11
DH1
26
LX1
27
ILIM2 13
DL1
24
VCC 22
PGOOD 7
FB1
2ON2 12
ILIM1 3
OVP
8
REF
10
LX2 17
DL2 20
TON 5
CS1
28
BST1
25
DH2 18
OUT1
1
PC195
1U_0805_16V7K
12
PR340
0_0402_5%
12
PC192
0.1U_0603_50V4Z
12
PJP3
PAD-OPEN 4x4m
1 2
PC144
0.1U_0603_50V4Z
12
PL23
FBM-L11-322513-151LMAT_1210
12
PD31
CHP202UPT_SOT323-3
2
31
PQ78
AO4702_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PR343
47K_0402_5%
1 2
PR331
0_0402_5%
1 2
PJP12
PAD-OPEN 4x4m
1 2
PR268
0_0402_5%
12
PR329
5.1K_0402_1%
12
PJP1
PAD-OPEN 3x3m
1 2
PJP7
PAD-OPEN 3x3m
1 2
PR330
0_0402_5%
1 2
G
D
S
PQ93
RHU002N06_SOT323
2
13
PC201
0.001U_0402_50V7M@
12
PR257
100K_0402_1%
12
PC72
1U_0603_10V6K
12
PL21
3.3UH_PCMC063T-3R3MN_6A_20%
1 2
PR258
5.1K_0402_1%
12
PJP5
PAD-OPEN 4x4m
1 2
PC194
0.1U_0603_50V4Z
12
PR341
47K_0402_5%
12
PC188
2200P_0402_50V7K
12
PR261
10K_0402_1%
12
PC145
4.7U_0805_6.3V6K
12
PR328
0_0402_5%
1 2
PC189
2200P_0402_50V7K
12
PC190
1U_0805_50V4Z
12
PC73
4.7U_0805_6.3V6K
12
PU20
APL5508-25DC-TRL_SOT89-3
IN
2
GND
1
OUT 3
PR262
20K_0402_1%
12
PL22
3.3UH_PCMB104E-3R3MS_11A_20%
12
PR319
0_0402_5%
12
PC186
4.7U_1206_16V4Z
12
5
5
4
4
3
3
2
2
1
1
DD
CC
BB
AA
DH_1.8V_1
BST_1.8V_1 BST_1.8V_2
DH_1.8V_2
DL_1.8V
LX_1.8V
SLP_S5#21,36
SLP_S3#18,21,25,27,28,29,33,35,36,40,43
V_DDR_MCH_REF7,13,14
SLP_S4#21
SLP_S5#21,36
+5VALWP
B+
DDR_B+
+1.8VP
+1.5VS
+0.9VP
+5VALWP
+1.8V
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
1.8V/0.9VS
B
4452Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
PC122
4.7U_0805_10V6K
12
PC127
10U_0805_10V4Z
12
PR231
0_0402_5%
1 2
PC124
10U_1206_25VAK
12
PR323
0_0402_5%@
12
PL15
FBM-L11-322513-151LMAT_1210
12
PC128
10U_0805_10V4Z
12
PC133
22P_0402_50V8J
12
PR236
0_0402_5%
12
PL16
1.8U_D104C-919AS-1R8N_9.5A_30%
1 2
PR234
0_0402_5%
12
PR324
0_0402_5%
1 2
PR230
0_0402_5%
1 2
PC137
0.001U_0402_50V7M
@
12
PC123
0.001U_0402_50V7M
12
PQ63
AO4404_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PC130
0.033U_0402_16V7K
12
PC129
22U_1206_6.3V6M
12
PR242
0_1206_5%
12
PC121
0.1U_0603_50V4Z
1 2
PC125
2200P_0402_50V7K
12
+
PC204
220U_D2_4VM
1
2
PR388
0_0402_5%
@
12
PR239
10K_0603_0.1%
12
PR238
14.3K_0603_0.1%
12
PR389
0_0402_5%
1 2
PR314
0_0402_5%
@
12
PC136
0.001U_0402_50V7M
@
12
PQ64
AO4702_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PR232
3_0402_5%
12
PR233
20K_0603_1%
12
PU27
TPS51116_HTSSOP20
GND
5
VTTGND
3
VDDQSNS
9
COMP
8
S3 11
DRVH 19
V5IN 14
MODE
6
PGND 16
VTTREF
7
PGOOD 13
VDDQSET
10
CS 15
VTT
2
VTTSNS
4
S5 12
LL 18
VBST 20
VLDOIN
1
DRVL 17
876543
3
2
2
1
1
HH
GG
FF
EE
DD
CC
BB
AA
PWM1
NTC
VSUM
VSUM
DH_CPU1
DL_CPU2
DH_CPU2
LX_CPU2
VSUM
PWM2
DL_CPU1
ISEN2
+VCC_CORE
NTC
LX_CPU1
VO
BST_CPU1_1
BST_CPU1_2
BST_CPU2_1
BST_CPU2_2
VO
ISEN1
VO
PWR_GD18,33,36,37,47
DPRSLPVR7,21
H_PSI#5
VGATE_INTEL7,21
CPU_VID05 CPU_VID15 CPU_VID25 CPU_VID35 CPU_VID45 CPU_VID55 CPU_VID65
H_PROCHOT#4
H_DPRSTP#4,20
CLK_ENABLE#15,37
PGD_IN33,37
VCCSENSE5
VSSSENSE5
PGD_IN_137
B+
+VCC_CORE
+CPU_B+
+5VS
+CPU_B+
+5VS
+3VS
+5VS
+VCC_CORE
+CPU_B+
+5VS
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
CPU_CORE
C
4552Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
PR315
100_0402_1%
12
PH2
470KB_0402_5%_ERTJ0EV474J
12
PC159
0.01U_0402_50V4Z
12
PR284
0_0402_5%
12
PR300
1.2K_0402_1%
12
PR311
1K_0402_1%
12
PU31
ISL6260CRZ-T_QFN40
VW
8
PGD_IN
2
PSI#
1
DPRSLPVR
36
DPRSTP#
37
VID6
34 VID5
33
RTN
13
FB
10
COMP
9
VSS 19
VDIFF
11
DFB
15
VO
16
ISEN3 21
OCSET 7
PWM3 25
FCCM 24
CLK_EN#
38
VR_TT#
4
RBIAS
3
NTC
5
SOFT
6
VID0
28
VID1
29
VID2
30
VID3
31
VID4
32
3V3 39
VSUM 17
VSEN
12
VR_ON
35
PWM1 27
ISEN2 22
ISEN1 23
PWM2 26
DROOP
14
VDD 20
VIN 18
PGOOD 40
PR285
0_0402_5%
12
PR283
0_0402_5%
12
PR289
0_0402_5%
12
PR297
11.5K_0402_1%
12
PC160
2200P_0402_50V7K
12
PC157
0.22U_0603_16V7K
12
PR278
147K_0402_1%
12
PQ81
FDS6688S_SO8
S
1
S
3
G
4
D8
D7
D6
D5
S
2
PQ80
SI7840DP-T1-E3_SO8
3 5
2
4
1
PC163
1U_0603_10V6K
12
PC151
2200P_0402_50V7K
12
PR303
4.53K_0402_1%
12
PR310
6.19K_0603_1%
12
PR299
0_0402_5%
12
PR270
0_0402_5%
12
PC173
1800P_0402_50V7K
1 2
PR296
0_0402_5%
12
PR272
10K_0402_1%
1 2
PR290
10K_0402_1%
1 2
PC152
10U_1206_25VAK
12
PR286
0_0402_5%
12
PR304
51K_0603_1%
12
PR288
0_0402_5%
12
PR298
180_0603_1%
12
PR275
1.91K_0603_1%
1 2
PC150
0.01U_0402_50V4Z
12
PC167
1000P_0402_50V7K
12
PH3
10KB_0603_5%_ERTJ1VR103J
12
PR292
0_0402_5%
12
PR318
0_0402_5%
@
12
PC183
330P_0402_50V7K
12
PR282
0_0402_5%
12
PR316
100_0402_1%
12
PR277
0_0402_5%
12
PR280
0_0402_5%
12
PC184
0.01U_0402_16V7K
12
PR308
1K_0402_1%
@
12
+
PC196
68U_25V_M
1
2
PR269
10_0603_5%
1 2
PC154
1U_0603_10V6K
12
PR274
5.11K_0402_1%
1 2
PC182
0.1U_0402_16V7K
12
PC156
0.01U_0402_25V7K
12
PR294 0_0402_5%
12
PU32
ISL6208CRZ-T_QFN8
BOOT 1
FCCM
6
VCC
5
PWM
2
LGATE 4
GND
3
PHASE 7
UGATE 8
PC164
0.015U_0402_16V7K
12
PC176
0.022U_0402_16V7K
1 2
PR291
499_0402_1%
12
PC162
10U_1206_25VAK
12
PQ85
FDS6688S_SO8
S
1
S
3
G
4
D8
D7
D6
D5
S
2
PR326
0_0402_5%
1 2
PR273
10_0603_5%
1 2
PC158
1U_0603_10V6K
12
PC166
0.22U_0603_16V7K
12
PL20
0.36UH_MPC1040LR36_24A_20%
1 2
PR271
10_0402_1%
1 2
PQ84
FDS6688S_SO8
S
1
S
3
G
4
D8
D7
D6
D5
S
2
PR307
6.98K_0402_1%
12
PC165
0.22U_0603_16V7K
1 2
PC161
10U_1206_25VAK
12
PQ83
SI7840DP-T1-E3_SO8
3 5
2
4
1
PC180
1000P_0402_50V7K
12
PC178
0.22U_0603_16V7K
1 2
PC177
1000P_0402_50V7K
1 2
PR279
4.22K_0603_1%
12
PR295
0_0402_5%
12
PR287
10_0402_1%
1 2
PC179
220P_0402_25V8K
1 2
PL19
0.36UH_MPC1040LR36_24A_20%
1 2
PR312
0_0402_5%
12
PR293
5.11K_0402_1%
1 2
PQ82
FDS6688S_SO8
S
1
S
3
G
4
D8
D7
D6
D5
S
2
PR281
0_0402_5%
12
PR317
0_0402_5%
@
12
PU30
ISL6208CRZ-T_QFN8
BOOT 1
FCCM
6
VCC
5
PWM
2
LGATE 4
GND
3
PHASE 7
UGATE 8
PC153
10U_1206_25VAK
12
PR301
3K_0402_1%
12
PC168
1000P_0402_50V7K
12
PL24
FBMA-L18-453215-900LMA90T_1812
1 2
PC155
0.22U_0603_16V7K
1 2
ABC
C
D
D
11
22
33
44
EC_SMC_A1
EC_SMD_A1
EC_SMC_B1
EC_SMD_B1
TS_B
EC_SMD_B
EC_SMC_B
EC_SMC_A
EC_SMD_A
AB/I_B
THM_MBAY#33
AB1B_DATA33
AB1A_CLK33
AB1A_DATA33
AB1B_CLK33
THM_MAIN#33
MAINPWON42
VMB_A
+3VL
VMB_B
BATT_A
BATT_B
+5VALW
+5VALW
+5VALW
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
BATTERY CONN
Custom
4652Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
CPU
Recovery at 43 +-3 degree C
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
PL13
FBMA-L18-453215-900LMA90T_1812
1 2
PD27
@SM05_SOT23
2
31
PR201
100_0402_5%
12
PCN3
SUYIN_20163S-06G1-K
BATT+ 1
TS 5
SMD 2
GND 6
SMC 3
B/I 4
PR200
100_0402_5%
12
PC105
0.01U_0402_50V4Z
12
PC104
1000P_0402_50V7K
12
PR185
47K_0402_1%
1 2
PC107
0.22U_0603_10V7K
12
PC110
0.01U_0402_50V4Z
12
PR191
150K_0402_1%
1 2
PR197
1K_0402_5%
1 2
PU21A
LM358ADR_SO8
+3
-2
0
1
P8
G
4
PR194
1K_0402_5%
12
G
D
S
PQ56
RHU002N06_SOT323
2
13
PR189
100_0402_5%
12
PR334
330K_0402_5%@12
PR192
2.55K_0603_1%
12
PD20
@SM05_SOT23
2
31
PR188
100_0402_5%
12
PR186
1K_0402_5%
12
PD26
SM24_SOT23 @
2
3
1
PR190
15K_0603_1%
1 2
PL14
FBMA-L18-453215-900LMA90T_1812
1 2
PR193
150K_0402_1%
12
PU21B
LM358ADR_SO8
+
5
-
607
P8
G
4
PH1
10K_TH11-3H103FT_0603_1%
12
PC108
1000P_0402_50V7K
12
PCN2
TYCO_C-1746706_6P
BATT+ 1
TS 5
SMD 2
GND 6
SMC 3
RES 4
PC106
0.1U_0402_10V6K
12
PC109
1000P_0402_50V7K
12
PR195
210K_0402_1%
1 2 PD19
SM24_SOT23 @
2
3
1
5432
2
1
1
DD
CC
BB
AA
LX_5V42
ADP_ID33
PWR_GD18,33,36,37,45
OCP#4,21
ACN40
ADP_PRES18,25,33,40,41,42
ADP_PS033
ADP_EN33
ADP_EN#40
ADP_PRES18,25,33,40,41,42
ADP_PS133
MXM_CD1#18,21
ACOCP_EN#35
CHGLIM40
VIN
ADP_SIGNAL
+3VS
+5VS
B+
+3VS
VIN
P4
+5VS
+5VS
+3VS
+3VS
ADP_SIGNAL
+3VALW
+5VS
+5VS
VIN
VIN
VIN
+3VS
+3VALW Title
SizeDocument NumberRev
Date:Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821
ADP_OCP
Custom
4752Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
PC118
1U_0805_50V4Z
12
PR383
221K_0603_1%
12
PR225
100K_0402_5%
@
1 2
PC206
3900P_0402_50V7K
12
PR249
3.9K_0402_5%
12
PC115
1U_0805_16V7K
12
G
D
S
PQ107
RHU002N06_SOT323
2
13
PU24A
LM358ADR_SO8
+3
-2
0
1
P8
G
4
PR362
1M_0402_5%
1 2
PR213
10K_0402_1%
1 2
PR368
220K_0402_5%
12
PR209
0_0402_5%
12
PR223
0_0402_5%
1 2
PR360
1M_0402_5%
1 2
PR348
10K_0402_1%
12
PR364
10K_0402_5%
12
PR211
6.81K_0402_1%
1 2
PR251
330K_0402_5%
12
PR390
47K_0402_5%
12
PC119
0.1U_0402_16V7K
12
PR378
10K_0402_5%
12
PR345
10K_0603_1%
12
PR380
1K_0402_5%
1 2
G
DS
PQ105
NDS0610_SOT23
2
1 3
G
D
S
PQ103
RHU002N06_SOT323
2
13
PR352
220K_0402_5%
12
PR217
604K_0603_1%
1 2
PD35
1N4148_SOD80
1 2
PR222
422_0603_1%
12
PR207
133K_0402_1%
12
PR210
0_0402_5%
1 2
PR214
100K_0603_0.5%
1 2
PD30
CH751H-40PT_SOD323-2@
21
PD36
CH355PT_SOD323-2
1 2
PU25A
LM393DG_SO8
+
3
-
2O1
P8
G
4
PU24B
LM358ADR_SO8
+
5
-
607
P8
G
4
PR221
10_0402_5%
12
PR381
40.2K_0402_1%
12
PR208
100K_0402_5%
1 2
PR356
71.5K_0402_1%
12
PR227
470K_0402_5%
1 2
PR220
7.87K_0402_1%
12
PR373
124K_0402_1%
1 2 PD38
CH355PT_SOD323-2
12
PR358
3.48K_0402_1%
12
G
D
S
PQ104
RHU002N06_SOT323@
2
13
PR351
47K_0402_5%
12
PD37
1N4148_SOD80
1 2
PR224
100K_0402_5%
1 2
PR361
21K_0402_1%
1 2
PR379
442K_0402_1%
12
PU34A
LM393DG_SO8
+
3
-
2O1
P8
G
4
E
B
C
PQ102
MMBT3904_SOT23
2
3 1
PU33B
LM393DG_SO8
+
5
-
6O7
P8
G
4
PR218
80.6K_0402_1%
12
PU26
LMV431ACM5X_SOT23-5
NC 2
REF
4
NC 1
CATHODE 3
ANODE
5
PC202
0.1U_0805_50V7M
12
PC116
0.22U_0603_16V7K
1 2
PR377
10K_0402_5%
12
PR344
137K_0402_1%
12
PD21
CH751H-40PT_SOD323-2
21
PR355
470K_0402_5%
12
PD34
1N4148_SOD80
1 2
G
D
S
PQ97
RHU002N06_SOT323
2
13
PR226
0_0402_5%
12
PR349
10K_0402_1%
12
PU33A
LM393DG_SO8
+
3
-
2O1
P8
G
4
47K
47K
PQ108
DTA144EUA_SC70
2
13
G
D
S
PQ100
RHU002N06_SOT323
@
2
13
PR347
22.6K_0402_1%
12
PR387
220K_0402_5%
12
PR359
10K_0402_5%
1 2
G
D
S
PQ61
RHU002N06_SOT323
2
13
G
D
S
PQ96
NDS0610_SOT23
2
13
PR252
3.9K_0402_5%
12
PU34B
LM393DG_SO8
+
5
-
6O7
P8
G
4
PR385
150K_0402_5%
12
PC207
1U_0603_10V6K
12
PR367
0_0402_5%
12
PR206
0_0402_5%
1 2
G
D
S
PQ106
RHU002N06_SOT323
@
2
13
PU25B
LM393DG_SO8
+
5
-
6O7
P8
G
4
PC117
0.027U_0603_16V7K
12
PR354
10K_0402_5%
12
E
B
C
PQ62
MMBT3904_SOT23
2
3 1
PR382
68K_0402_5%
@
12
PR386
29.4K_0402_1%
@
12
PR357
21K_0402_1%
12
PD22
CH751H-40PT_SOD323-2
21
PR216
2K_0402_5%
12
PR350
1M_0402_5%
1 2
PR353
47K_0402_5%
12
PR346
1M_0402_5%
1 2
PR212
0_0402_5%
1 2
C
B
E
PQ59
MMBT3906_SOT23
1
2
3
PR363
10K_0402_5%
12
PR384
220K_0402_5%
12
1
1
2
2
3
3
4
4
5
5
11
22
33
44
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
H/W2 EE Dept. PIR SHEET(1)
4852Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
EAL80 from Pre DB-1 Step to DB-1 Step LA-2821 REV:0.0 -> 0.1 Modify <94.03.26.~94.04.08. >
-Change Q27.2(2N7002) connection from SLP_S3 to SLP_S5. (Modify CKT&Layout)
1. Change +0.9V discharge circuit control signal from SLP_S3 to SLP_S5. <Page 36> 94.03.26.
-Del R1248 and connect TP62 to JP33.8 directly. (Modify CKT&Layout)
2. Just reserve a test pad for TPM_GPIO directly. <Page 32> 94.03.28.
-Change +3VL that connects to R1242.1 to +3VALW. (Modify CKT&Layout)
3. Change TPM1.2 +3VL Power Rail to +3VALW by Customer request. <Page 32> 94.03.28.
-Change U25.39/38 connection from CLK_PCIE_NC/CLK_PCIE_NC# to PCIE_NC/PCIE_NC#. (Modify CKT&Layout)
4. Correct U25.39/38's net name from CLK_PCIE_NC/NC# to PCIE_NC/NC# . <Page 15> 94.03.28.
-Change R117 from 100K_0402_5% to 150K_0402_1%. (Modify CKT&BOM)
5. Change the RC parts for POK Time delay request. <Page 37> 94.03.29.
-Change C87 from 0.1U_0402 to 0.47U_0603_X7R. (Modify CKT,BOM&Layout)
-Change R93,R97 from 7612@0_0402 to 0_0402; R103 from 7611@0_0402 to @0_0402. (Modify CKT&BOM)
6. Update the PCI7611MLS/PCI7612 related schematic by Vendor recommend. <Page 23,24> 94.03.29.
-Add R1308(0_0402) between U42.K3 and U42.K5; change R106 from 0_0402 to @0_0402. (Modify CKT,BOM&Layout)
-Change R1299 from 43K_0402 to @43K_0402. (Modify CKT&BOM)
7. Reserve a 68UF Cap. by LAN Chip Vendor request. <Page 25> 94.03.29.
-Reserve C976(@68U_B2_4VM) close to U6.M14. (Modify CKT,BOM&Layout)
8. Reserve two resistors(@0_0402) to isolate VGATE and VGATE_INTEL. <Page 37> 94.03.29.
-Reserve R1306(@0_0402) between PU31.40 and U45.2. (Modify CKT,BOM&Layout)
-Reserve R1307(@0_0402) between U48.4 and PR326.2. (Modify CKT,BOM&Layout)
9. Change Calistoga LVDS function power source to GND for disabling by customer recommend. <Page 10> 94.03.29.
-Change U15.B30/C30/A30 connection from +2.5VS to GND. (Modify CKT&Layout)
-Change U15.A28/B28/C28 connection from +1.5VS to GND. (Modify CKT&Layout)
-Change R1015 from 100K_0402_5% to @100K_0402_5%. (Modify CKT&BOM)
10. Remove DPRSLPVR Pull-down resistor by customer recommend. <Page 21> 94.03.29.
-Change R1284~R1286 from @10K_0402_5% to 10K_0402_5%. (Modify CKT&BOM)
11. Stuff SPI related function Pull-High resistors by customer/Intel recommend. <Page 21,32> 94.03.29.
-Reserve R1309(@0_0402_5%) between PM_EXTTS#1 and DPRSLPVR connection. (Modify CKT&Layout)
12. Reserve 0 ohm resistor for PM_EXTTS#1 and DPRSLPVR connection by Customer/Intel recommend. <Page 7,21>
94.03.29.
13. Add +1.8V discharge circuit. <Page 36> 94.03.30.
-Add R1310(470_0402_5%) and Q90(2N7002_SOT23) for +1.8V discharge schematic related. (Modify CKT,BOM&Layout)
14. Change ICH7 HD function power source to +3VS for wake on ring function from Azalia modem disabling by
customer recommend. <Page 22> 94.03.30.
-Change U26.R7 connection from +3VALW to +3VS. (Modify CKT&Layout)
-Add R1313,R1314,R1315(33_0402) for ICH7/MDC/Codec related update. (Modify CKT,BOM&Layout)
16. Update ICH7M HD Audio, Codec Chip and MDC related Schematic. <Page 20,34,36> 94.03.30.
15. Change TPM1.2 +3VL Power Rail to +3VALW by Customer request. <Page 32> 94.03.30.
-Change +3VL that connects to C193.1 to +3VALW. (Modify CKT&Layout)
-Create net name AC97_RST#_MDC, AC97_RST#_CODEC, AC97_SYNC_MDC, AC97_SYNC_CODEC,
AC97_SDOUT_MDC, AC97_SDOUT_CODEC, AC97_BITCLK_MDC, AC97_BITCLK_CODEC, AC97_SDIN0_CODEC,
AC97_SDIN1_MDC for ICH7/MDC/Codec related update. (Modify CKT&Layout)
17. Reserve 0ohm option resistors for +0.9V discharge circuit control signal SLP_S3 and SLP_S5 selecting . <Page 36>
94.03.30.
-Reserve R1311(@0_0402) to connect SLP_S5 to Q27.2. (Modify CKT&Layout)
-Add R1312(0_0402) to connect SLP_S3 to Q27.2. (Modify CKT,BOM&Layout)
18. Populate the 68UF Cap. and reserve 10UF Cap. by LAN Chip Vendor/Customer request. <Page 25> 94.03.30.
-Change C976 from @68U_B2_4VM to 68U_B2_4VM, remove C243(@10U_1206_6.3V). (Modify CKT&BOM)
19. Swapping DDR2 SO-DIMM Data Group pin definition for Layout routing smoothly. <Page 13,14> 94.03.31.
-Swapping JP34 and JP10 Data Group pin definition. (Modify CKT&Layout)
20. Correct Calistoga chip power pin connection base on CRB Rev:1.301 recommend. <Page 11> 94.04.01.
-Disconnect U15.AV1 and U15.AJ1 to +1.8V and modify the related schematic. (Modify CKT&Layout)
-Change U15.AT41/AM41 net name from MCH_AT41/MCH_AM41 to VCCSM_LF4/VCCSM_LF5. (Modify CKT&Layout)
21. Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R to meet Intel Napa ESL request. <Page 6> 94.04.01.
-Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R. (Modify CKT,BOM&Layout)
22. Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R to meet Intel request, avoid thermal risk. <Page 6>
94.04.01.
-Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R. (Modify CKT&BOM)
23. Update ICS954306 PCB Footprint for Layout routing. <Page 15> 94.04.01.
-Change U25 PCB Footprint from ICS954306_TSSOP64 to ICS954306BGLFT_TSSOP64.
(Modify CKT,BOM&Layout)
3th Netin
24. Remove the R1153 2.2Kohm pull-high resistor for leverage AF1.0 CFG9 setup. <Page 11> 94.04.01.
-Remove R1153(@2.2K_0402). (Modify CKT&BOM)
25. Add net name for USB signals layout rule create. <Page 30> 94.04.04.
-Add net names USB20_N1_R, USB20_P1_R, USB20_N4_R, USB20_P4_R, USB20_HUB_N1_R,
USB20_HUB_P1_R on JP16.6/7/2/3 JP22.4/3. (Modify CKT&Layout) 4th Netin
26. Remove the R555,R612 8.2Kohm pull-high resistors because the signals be double pulled up.
<Page 18> 94.04.04.
-Remove R555,R612(@8.2K_0402). (Modify CKT&BOM)
27. Reserve Audio mute control signals on KBC to leverage AF1.0 designing. <Page 33> 94.04.04.
-Reserve R140,R141(@0_0402) onU47.57/56 for EAPD/A_SD. (Modify CKT&Layout)
28. Correct net name for USB signals layout rule create. <Page 29,35> 94.04.04.
-Correct net names to USB20_N2_R, USB20_P2_R, USB20_N3_R, USB20_P3_R, USB20_N6_R,
USB20_P6_R, USB20_N7_R, USB20_P7_R, on JP27.1/2/4/5 JP30.2/4/6/8. (Modify CKT&Layout)
29. Add (NC@0_0402) to connect CP_USB# and NC_CPPE# for New Card function usage. <Page 24>
94.04.04.
-Add R1316(NC@0_0402) to connect CP_USB# and NC_CPPE#. (Modify CKT,BOM&Layout)
-Change R1272,R1273 from @10K_0402 to @100K_0402. (Modify CKT&BOM) 5th Netin
30. Del JP39.157's ADP_PRES connection to leverage AF1.0 and standard MXM pin definition. <Page 18>
94.04.04.
-Del JP39.157's ADP_PRES connection. (Modify CKT&Layout)
31. Reserve the circuit to control the mute to block the speaker pop on power up by customer recommend.
<Page 29> 94.04.04.
-Reserve D59(@RB751V), R613(@1M_0402), R431(@10K_0402), C93(@2.2U_0805), R439(@10K_0402),
R438(@10_0402) and the related circuit on U39.19. (Modify CKT,BOM&Layout)
Gerber Out 4/14
1 2 3 4
4
5
5
11
22
33
44
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
H/W2 EE Dept. PIR SHEET(2)
4952Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >
-Change U26.AF18 from NC to IDE_LED#. (Modify CKT&Layout)
1. Change HDD I/F from PATA to SATA. <Page 20> 94.05.10.
-Change U26.AF3 from GND to SATA_RXN0_C. (Modify CKT&Layout)
-Change U26.AE3 from GND to SATA_RXP0_C. (Modify CKT&Layout)
-Change U26.AG2 from NC to SATA_TXN0_C. (Modify CKT&Layout)
-Change U26.AH2 from NC to SATA_TXP0_C. (Modify CKT&Layout)
-Add R1256(24.9_0402_1%) between U26.AH10/AG10 and GND. (Modify CKT,BOM&Layout)
-Del R1326,R1327(NOSATA@0_0402). (Modify CKT,BOM&Layout)
2. Remove R1294(1K_0402) Pull-High to +3VS to avoid double Pull-High risk. <Page 20> 94.05.10.
-Remove R1294(@1K_0402). (Modify CKT&BOM)
-Add JP45, C955~C958(3900P_0402) and related schematic for SATA connector. (Modify CKT,BOM&Layout)
-Add U64(LIS3LV02DQ_QFN28),R1355(0_0805_5%),R1356(0_0603_5%),R1357~R1361(0_0402_5%),
R1362(10K_0402_5%),C994(0.01U_0402_16V7K),C995(0.1U_0402_16V4Z) and C996(4.7U_0805_10V4Z)
at the center of the system . (Modify CKT,BOM&Layout)
3. Add the accelerometer device LIS3LV02DQ and modify the related schematic . <Page 02,21,27,33> 94.05.11.
-Add R1364(0_0402_5%) between "ACCEL_INT#" and U26.E20(SB_GPIO9); Reserve R1363(@0_0402_5%) between
"ADP_PWRID" and U26.E20(SB_GPIO9) . (Modify CKT,BOM&Layout)
-Reserve R1354(@0_0402_5%) between "ACCEL_INT#" and U47.34(KBC_GPIO23) . (Modify CKT,BOM&Layout)
-Change R1317(NC@0_0402_5%) connection Net from "USB20_P0_HUB" to "USB20_P1_HUB" and from "USB20_P0" to
"USB20_P1" . (Modify CKT&Layout)
4. Change USB port assignments as customer request . <Page 02,21,24,30,32> 94.05.11.
-Change R1318(NC@0_0402_5%) connection Net from "USB20_N0_HUB" to "USB20_N1_HUB" and from "USB20_N0" to
"USB20_N1" . (Modify CKT&Layout)
-Change R562(0_0402_5%) connection Net from "USB20_HUB_P1_R" to "USB20_P0_R" and from "USB20_HUB_P1" to
"USB20_P0" . (Modify CKT&Layout)
-Change R586(0_0402_5%) connection Net from "USB20_HUB_N1_R" to "USB20_N0_R" and from "USB20_HUB_N1" to
"USB20_N0" . (Modify CKT&Layout)
-Change R983(NONC@0_0402_5%) connection Net from "USB20_P0" to "USB20_P1" . (Modify CKT&Layout)
-Change R982(NONC@0_0402_5%) connection Net from "USB20_N0" to "USB20_N1" . (Modify CKT&Layout)
-Change R1335(0_0402_5%) connection Net from "USB20_HUB_P2_R" to "USB20_HUB_P1_R" and from
"USB20_HUB_P2" to "USB20_HUB_P1" . (Modify CKT&Layout)
-Change R1334(0_0402_5%) connection Net from "USB20_HUB_N2_R" to "USB20_HUB_N1_R" and from
"USB20_HUB_N2" to "USB20_HUB_N1" . (Modify CKT&Layout)
-Change R1276(NC@0_0402_5%) connection Net from "USB20_P5_R" to "USB20_HUB_P2_R" and from
"USB20_P5" to "USB20_HUB_P2" . (Modify CKT&Layout)
-Change R1274(NC@0_0402_5%) connection Net from "USB20_N5_R" to "USB20_HUB_N2_R" and from
"USB20_N5" to "USB20_HUB_N2" . (Modify CKT&Layout)
-Change R607(0_0402_5%),D51.3 connection Net from "USB20_P1_R" to "USB20_P5_R" and from
"USB20_P1" to "USB20_P5" . (Modify CKT&Layout)
-Change R606(0_0402_5%),D51.2 connection Net from "USB20_N1_R" to "USB20_N5_R" and from
"USB20_N1" to "USB20_N5" . (Modify CKT&Layout)
-Change U53(NC@USB2502) pin15 connection from Net "USB_OC#0" to "USB_OC#1" . (Modify CKT&Layout)
-Change U41(TPS2041B) pin5 connection from Net "USB_OC#1" to "USB_OC#5" . (Modify CKT&Layout)
5. Change PCIE port assignments as customer request . <Page 02,21,24,25,27,35> 94.05.12.
-Change U26.K26/K25/J28/J27 to NC . (Modify CKT&Layout)
-Change C712 connection from PCIE_C_TXN3 to PCIE_C_TXN4 ; from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)
-Change C713 connection from PCIE_C_TXP3 to PCIE_C_TXP4 ; from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&Layout)
-Change C952 connection from PCIE_C_TXN4 to PCIE_C_TXN5 ; from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)
-Change C953 connection from PCIE_C_TXP4 to PCIE_C_TXP5 ; from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&Layout)
-Change C960 connection from PCIE_C_RXP3 to PCIE_C_RXP4 ; from PCIE_RXP3 to PCIE_RXP4 . (Modify CKT&Layout)
-Change JP9.A24 connection from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)
-Change JP9.A25 connection from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&Layout)
-Change R1347 connection from PCIE_C_RXN4 to PCIE_C_RXN5 ; from PCIE_RXN4 to PCIE_RXN5 . (Modify CKT&Layout)
-Change R1346 connection from PCIE_C_RXP4 to PCIE_C_RXP5 ; from PCIE_RXP4 to PCIE_RXP5 . (Modify CKT&Layout)
-Change JP30.151 connection from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)
-Change JP30.149 connection from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&Layout)
-Change C959 connection from PCIE_C_RXN3 to PCIE_C_RXN4 ; from PCIE_RXN3 to PCIE_RXN4 . (Modify CKT&Layout)
6. Change SRC clock assignments as customer request . <Page 15> 94.05.13.
-Change R1336 connection from "CLKREQB#" to "CLKREQD#"; from "CLKREQB#_MC" to "CLKREQD#_MC".
(Modify CKT&Layout)
-Change R1279.1/R1280.1/C961.1 connection from "CLKREQD#" to "CLKREQA#". (Modify CKT&Layout)
-Add R1120(NOXDP@10K_0402) from net "CLKREQC#" to +3VS pull-high . (Modify CKT,BOM&Layout)
-Change U25.39 connection from "PCIE_NC" to "PCIE_MCARD". (Modify CKT&Layout)
-Change U25.38 connection from "PCIE_NC#" to "PCIE_MCARD#". (Modify CKT&Layout)
-Change U25.37 connection from "PCIE_DOCK" to "MCH_3GPLL". (Modify CKT&Layout)
-Change U25.36 connection from "PCIE_DOCK#" to "MCH_3GPLL#". (Modify CKT&Layout)
-Change U25.26 connection from "PCIE_MCARD" to "PCIE_DOCK". (Modify CKT&Layout)
-Change U25.27 connection from "PCIE_MCARD#" to "PCIE_DOCK#". (Modify CKT&Layout)
-Change U25.22 connection from "PCIE_LOM" to "PCIE_NC". (Modify CKT&Layout)
-Change U25.23 connection from "PCIE_LOM#" to "PCIE_NC#". (Modify CKT&Layout)
-Change U25.21 connection from "MCH_3GPLL#" to "PCIE_LOM#". (Modify CKT&Layout)
-Change U25.20 connection from "MCH_3GPLL" to "PCIE_LOM". (Modify CKT&Layout)
-Change R1344.2 connection from "CLKREQB#" to "CLKREQC#". (Modify CKT&Layout)
7. Change CLKREQ assignments as customer request . <Page 07,15,24,27> 94.05.13.
15. Update the SATA supported related . <Page 20> 94.05.17.
-Change R1254 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)
-Add R1147(NOXDP@10K_0402) from net "CLKREQD#" to +3VS pull-high . (Modify CKT,BOM&Layout)
-Change R1142 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)
-Add R1366(@0_0402) between JP38.3 andto JP44.38 . (Modify CKT&Layout)
-Add R1365(@0_0402) between JP38.2 and JP44.36 . (Modify CKT&Layout)
8. Reserve test Mini-Card that supports USB interface as customer request . <Page 27,32> 94.05.13.
10. Update LAN Controller schematic related caused by chipset changed from BCM5751M to BCM5753M .
<Page 25,26> 94.05.16.
-Add R1370,R1371(0_0402) and reserve R1372,R1373(@2.2K_0402),Q92,Q93(@2N7002) for SMBus
connection . (Modify CKT,BOM&Layout)
-Change R276 from 4.7K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)
-Change R275,R289 from 47K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)
-Change R1106(10K_0402) connection from +3VS pull-high to between CLKREQB# and CPPE# .
(Modify CKT&Layout)
-Del R1336(0_0402_5%) and short directly . (Modify CKT,BOM&Layout)
-Del R1344(@0_0402_5%) and short directly . (Modify CKT&Layout)
9. Del R1344 & R1336 and short directly because of double reserved . <Page 07,27> 94.05.16.
-Update the related schematic. (Modify CKT&Layout)
-Change RP13.2 connection from DDR_B_MA6 to DDR_B_MA11 . (Modify CKT&Layout)
-Change RP11.1 connection from DDR_CKE3_DIMMB to DDR_B_MA7 . (Modify CKT&Layout)
-Change RP11.2 connection from DDR_B_MA11 to DDR_CKE3_DIMMB . (Modify CKT&Layout)
14. Swap RP11,RP13 pin connection for DDR2 shift trace routing issue improving . <Page 14> 94.05.16.
-Remove C994(@0.01U_0402), Change C996 from 4.7U_0805 to 10U_0805 . (Modify CKT,BOM&Layout)
12. Update Accelerometer related schematic by Vendor STMicro recommend . <Page 27> 94.05.16.
-Add R1367(1K_0402) from U6.H12 to +3VS . (Modify CKT,BOM&Layout)
-Add R1368(0_0402) and reserve R1369(@0_0402) for U26.AD22 connection . (Modify CKT,BOM&Layout)
13. Modify ICH7 Power_OK connection to be able to be enable same as NB . <Page 21> 94.05.16.
-Remove U37,D32,R504, and C577 . (Modify CKT,BOM&Layout)
11. Remove U37,D32,R504, and C577. Remove CLKREQA# connection from NIC to CK clock by customer
recommend . <Page 25> 94.05.16.
-Change RP13.1 connection from DDR_B_MA7 to DDR_B_MA6 . (Modify CKT&Layout)
-Delete JP23,R458,R1324,R1325,R300 . (Modify CKT,BOM&Layout)
-Add C997(10U_0805),C998~C1000(0.1U_0402) close to JP45 +3VS pins . (Modify CKT,BOM&Layout)
16. Dual design SPI ROM for SOP8-150mil/200mil package . <Page 32> 94.05.17.
-Add U65(SPI@SST25LF080A-200mil) . (Modify CKT,BOM&Layout)
17. TPM1.2 on board designing reserve related . <Page 32> 94.05.17.
-Add U66(TPM1.2@SLB9635TT),C1001~C1004(0.1U_0402),C1005,C1006(18P_0402),Y8(32.768KHz),
R1375~R1381 and related schematic update . (Modify CKT,BOM&Layout)
2nd Netin
1st Netin
1 2 3 4
4
5
5
11
22
33
44
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
H/W2 EE Dept. PIR SHEET(3)
5052Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >
-Change pin5 (VSB) to +3VALW and move C1004 to connect to pin5 . (Modify CKT&Layout)
18. Update TPM1.2 on board designing schematic. <Page 32,36> 94.05.18.
-Delete SMBus connection with R1380,R1381 on U66.2 & U66.6; Connect U66.6 to JP33.8, U66.2 to T87 .
(Modify CKT,BOM&Layout)
-Delete +3V power from JP33.4 . (Modify CKT&Layout)
-Delete +3V power reserved schematic and parts include Q91,C977,C978 . (Modify CKT,BOM&Layout)
19. Add DC/DC schematic about +2.5VALW to +2.5VS for power sequence fail issue fixed. <Page 36> 94.05.18.
-Add U67(SI4800DY_SO8),C1007,C1008,C1009 . (Modify CKT,BOM&Layout)
20. Delete MDC 1.0 Connector reserved related to save layout space . <Page 34> 94.05.18.
-Del JP25(MDC1.0 Conn),C13(0.1U_0402) . (Modify CKT,BOM&Layout)
21. Change the power source designing from +3VALW to +3VS for DB-2 LS-2712 issue fixed . <Page 34> 94.05.18.
-Change JP18.1 and JP18.3 connection from +3VALW to +3VS . (Modify CKT&Layout)
22. Change the ICH7 RTC Cap. Value for SVTP measure fail issue fixed . <Page 20> 94.05.19.
-Change C516,C528 from 18P_0402 to 10P_0402 . (Modify CKT&BOM)
3rd Netin
23. Update LAN chip schematic related by customer recommend . <Page 25> 94.05.19.
-Change R275,R289 from 1K_0402 to @1K_0402 . (Modify CKT&BOM)
-Del D32,R504,C577,U37 . (Modify CKT,BOM&Layout)
-Add R1380(0_0402) and reserve R1381(@0_0402) . (Modify CKT,BOM&Layout)
-Del C40,C45,C53,C62,C64 for +3VS power rail cancel . (Modify CKT,BOM&Layout)
24. Update KBC related designing by customer recommend . <Page 33> 94.05.20.
-Add ADP_EN to S_CLK(GPIO22) by R1385(0_0402) . (Modify CKT,BOM&Layout)
-Add ADP_ID to EC_GPIO19 by R1382(0_0402) . (Modify CKT,BOM&Layout)
-Add ADP_PS1 to EC_GPIO12 by R1383(0_0402) . (Modify CKT,BOM&Layout)
-Add ADP_PS0 to EC_GPIO10 by R1384(0_0402) . (Modify CKT,BOM&Layout)
-Remove R87(@0_0402) . (Modify CKT&BOM)
25. Update ICH7 related designing by customer recommend . <Page 21,35> 94.05.20.
-Change R1363 from 0_0402 to ACCEL@0_0402 . (Modify CKT&BOM)
-Change R1363.2 connection from ADP_PWRID to ADP_ID . (Modify CKT&Layout)
-Reserve R1386(@0_0402) from PREP2# to U26.AD20(ICH7_GPIO38) . (Modify CKT&Layout)
26. Update LAN chip schematic related by customer recommend . <Page 25> 94.05.20.
-Reserve R1387(@10K_0402) from PREP2# to +3VS . (Modify CKT&Layout)
-Change R73.1 and R36.1 connection from +3VS to V_3P3_LAN . (Modify CKT&Layout)
27. Update CardReader chip schematic related by customer recommend . <Page 23> 94.05.20.
-Del U46 and related net . (Modify CKT,BOM&Layout)
-Del R591,R593 . (Modify CKT,BOM&Layout)
-Change R594 connection to between +VCC_SD and SDWP#_SMCE# . (Modify CKT&Layout)
-Change R602 connection to between +VCC_SD and SM_RB# . (Modify CKT&Layout)
-Change JP41.36 connection to MSBS_SDCMD_SMWE# . (Modify CKT&Layout)
-Change JP41.27 connection to SDCLK_SMRE# . (Modify CKT&Layout)
-Change JP41.28 connection to SDWP#_SMCE# . (Modify CKT&Layout)
-Change JP41.26 connection to SM_RB# . (Modify CKT&Layout)
-Add R1388(0_0402) between MC_PWRON# and MC_PWRON . (Modify CKT,BOM&Layout)
-Remove Q77,D45,D46,R595,D48 . (Modify CKT&BOM)
28. Update Clock Gen. schematic related by customer recommend . <Page 15> 94.05.20.
-Del R1328,R1329,R1330,R1331,R1332 and related net . (Modify CKT,BOM&Layout)
-Change U25.15 connection to FSB . (Modify CKT&Layout)
-Change U25.16,24,41 connection to +CK_VDD_DP . (Modify CKT&Layout)
-Change C734,C735,C736 connection to +CK_VDD_DP . (Modify CKT&Layout)
-Add R1389(NODP@0_0805),R1390(DP@0_0805),C1010(10U_0805) and related net . (Modify CKT,BOM&Layout)
-Change R1352,R1333 from @0_0402 to 0_0402 . (Modify CKT,BOM&Layout)
29. Update MXM schematic related by customer recommend . <Page 18> 94.05.23.
-Reserve R1391(@0_0402) from JP39.125 to CLKREQA# . (Modify CKT&Layout)
-Add R1392(0_0402) from JP39.157 to ADP_PRES . (Modify CKT,BOM&Layout)
30. Update LAN chip schematic related by customer recommend . <Page 25> 94.05.23.
-Reserve R284(@4.7K_0402_5%) from U6.L3 to V_3P3_LAN . (Modify CKT&Layout)
-Add T59 on U6.L3 . (Modify CKT&Layout)
-Add T60 on U6.M5 . (Modify CKT&Layout)
31. Update Clock Gen. schematic related by customer recommend . <Page 15> 94.05.23.
-Reserve R1393(@0_0402_5%) from U25.46(CLKIREF) to +CK_VDD_DP . (Modify CKT&Layout)
-Reserve C1011(@0.1U_0402) from U25.46(CLKIREF) to GND . (Modify CKT&Layout)
-Reserve R1394(@10K_0402) from U25.2(PCI_EC) to +3VS . (Modify CKT&Layout)
-Remove R1353,R1333(@0_0402_5%) . (Modify CKT&BOM)
-Reserve Q94(@2N7002_SOT23) and change R1380 connection as update schematic . (Modify
CKT&Layout)
-Del R1381 and short Q29.3 to GND directly . (Modify CKT&Layout)
32. Update AC97 Codec to keep AD1981HD only schematic related by customer recommend and DFx issue
improved . <Page 15,28> 94.05.23.
-Del C391,R403,R406,R388,R158,R159,C410,C408,C401,C398,R415,R364,C397,R1085(CLK_14M_CODEC)
,R418 and short U14.42 to GNDA . (Modify CKT,BOM&Layout)
-Add T88~T101 test point on the bottom side . (Modify CKT&Layout)
33. Update ICH7 SPI I/F related schematic by customer recommend . <Page 21> 94.05.24.
-Change R1284.1,R1285.1 and R1286.1 connection from +3VS to +3VALW . (Modify CKT&Layout)
34. Update TI PCI7611MLS/PCI7612 related schematic by customer recommend . <Page 23> 94.05.24.
-Change R594.2 and R602.2 connection from +VCC_SD to +VCC_SM_XD . (Modify CKT&Layout)
-Del JP45 pin8,9,10 +3VS connection . (Modify CKT&Layout)
35. Update ICH7 SATA I/F related schematic by customer recommend . <Page 20> 94.05.24.
-Del C997~C1000 . (Modify CKT,BOM&Layout)
36. Update ICH7 PATA I/F related schematic for SATA HDD support . <Page 20> 94.05.24.
-Add R556(100K_0402) . (Modify CKT&BOM)
37. Change some Capacitors for Lead Free designing . <Page 6,18,22,30> 94.05.25.
-Remove C939(@220U_C6_6.3V) and add C983(330U_D2E_2.5V) . (Modify CKT&BOM)
-Remove C633(@47U_25V_M) and add C1013~C1017(10U_1206_25V6M) . (Modify CKT,BOM&Layout)
-Remove C671(@100U_6.3V_M) and add C1012(150U_D_6.3VM) . (Modify CKT,BOM&Layout)
-Remove C670(@220U_C6_6.3V) and add C979(330U_DD2E_2.5V) . (Modify CKT&BOM)
-Remove C1,C527(@100U_6.3V) and add CC568,C567(150U_D_6.3V) . (Modify CKT&BOM)
38. Update the Accelerometer related and install the related BOM for Accelerometer enable . <Page 19,21,27,33>
-Change the net name from ACCEL_INT# to ACCEL_INT, ACCEL#_SB to ACCEL_SB, ACCEL_INT#_KBC
to ACCEL_INT_KBC . (Modify CKT&Layout)
-Note R94 must be removed when R1354 stuff and R87 remove . (Modify CKT&BOM)
-Reserve D61,C1018,R1395,Q95 between ACCEL_INT and Q78.1 . (Modify CKT&Layout)
-Remove R1358,R1360 . (Modify CKT&BOM) 9rd Netin/BOM Transfer
39. Update Docking related schematic for Customer Smart Adaptor new function request . <Page 21,35>
-Change JP30.118 and R1387.1 net name to DOCK_ID . (Modify CKT&Layout)
-Add JP30.117(DOCK_ADP_SIGNAL) to ADP_SIGNAL by R1401(1K_0402_1%) . (Modify CKT,BOM&Layout)
40. Update AD1981HD related schematic for Vendor ADI review result . <Page 28>
-Change U18.2 connection from GND to AGND, move R258 between C551.1 and U18.2 . (Modify CKT&Layout)
-Change C409,C427,C431 from 0.1U_0402 to 0.1U_0805 . (Modify CKT,BOM&Layout)
-Add R1400(0_1206) between GND and AGND close to Codec area . (Modify CKT,BOM&Layout)
-Disconnect U14.14 and U14.15, disconnect U14.40 and U14.33 to AGND and add T102,T103,T104 on pin 14,40,33 .
(Modify CKT&Layout)
-Add R1399(0_0805) replace L36(CHB2012U121(0805)) . (Modify CKT&BOM)
-Add C1019(10P_0402) to GND . (Modify CKT,BOM&Layout)
41. Update Accelerometer related schematic for Customer review result . <Page 27>
-Remove R1355(@0_0805), add D62(ACCEL@CH751H) between U64.3/19 and +3VS . (Modify CKT,BOM&Layout)
-Del R1358 and R1360 pull-down resistors . (Modify CKT,BOM&Layout)
-Add R1398(0_0402) to GND, del U64.29 to GND connection . (Modify CKT,BOM&Layout)
42. Change the Audio Amp chip from TI TPA6017A2_TSSP20 to MAXIM MAX9710_QFN20 and update related
schematic for Customer Spec modified request . <Page 29>
-Change U39 from TPA6017A2_TSSOP20 to MAX9710ETP_QFN20 . (Modify CKT,BOM&Layout)
-Del D59,R613,R431,C93,R439,R438,C663,C664,R971~R974,C661 . (Modify CKT,BOM&Layout)
-Change C503,C502 from 0.047U to 0.1U . (Modify CKT,BOM&Layout)
-Add R1403(10K_0402) from U39.5 to C503.2, R1404(10K_0402) from U39.5 to U39.7 . (Modify CKT,BOM&Layout)
-Add R1405(10K_0402) from U39.1 to C502.2, R1406(10K_0402) from U39.1 to U39.19 . (Modify CKT,BOM&Layout)
-Add R1407(0ohm) from U39.4 to AGND;Add C1020(10U_1206) from +5VALW and GND . (Modify CKT,BOM&Layout)
-Add C1021(1U_0603) from U39.2 to AGND . (Modify CKT,BOM&Layout)
-Change C662 from @100U_6.3V to @150U_D_6.3V . (Modify CKT&Layout)
1 2 3 4
4
5
5
11
22
33
44
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
H/W2 EE Dept. PIR SHEET(4)
5152Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.30. >
43. Reserve a 0ohm resistor for time delay pass through schematic by Customer request. <Page 37> 94.05.27.
-Reserve R1402(@0_0402) between PWR_GD and PGD_IN . (Modify CKT&Layout)
-Change R38 from 100K_0402 to 47K_0402 . (Modify CKT&BOM)
44. Change the resistor value to tune the delay schematic by Customer request. <Page 37> 94.05.27.
45. Change BOM option for Intel chipset ver:A1 by Customer recommend . <Page 7,21> 94.05.27.
-Change R1309 from @0_0402 to 0_0402, remove R1015(@100K_0402) . (Modify CKT&BOM)
46. Add a 0ohm resistor for debug by Customer recommend . <Page 4,20> 94.05.27.
-Add R1408(0_0402) between U26.H22 and H_STPCLK# . (Modify CKT,BOM&Layout)
47. Add a 0.1UF CAP to improve Cut Moat issue for RGB signals . <Page 36> 94.05.27.
-Add C1022(0.1U_0603) between +3VS and +VCCP . (Modify CKT,BOM&Layout)
48. Add 10Kohm pull-high to +VCC_SM_XD for TI FAE recommend . <Page 23> 94.05.27.
-Add R1396 and R1397(10K_0402) Pull-High to +VCC_SM_XD for MSBS_SDCMD_SMWE# and SDCLK_SMRE# .
(Modify CKT,BOM&Layout)
49. Update TPM related schematic for Vendor review result . <Page 32> 94.05.27.
-Add R1409(TPM1.2@0_0402) from U66.7 to GND, remove R1379(@4.7K_0402) . (Modify CKT,BOM&Layout)
-Change C193.1 connection from +3V to +3VALW for TPM1.2 . (Modify CKT&Layout)
EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >
-Add R1440 and R1441(100K_0402) for BT_LED and WL_LED discharge . (Modify CKT,BOM&Layout)
1. Add discharge circuit for BT_LED and WL_LED to solve the LED always light on issue. <Page 32> 94.08.23.
-Remove R1209(@10K_0402) for DPRSLPVR . (Modify CKT&BOM)
2. Remove DPRSLPVR NB side PullHigh resistor for Intel document update. <Page 7> 94.08.24.
-Del JP33,R1236,R1242,R1253,C191,C192,C193 and related schematic. (Modify CKT,BOM&Layout)
3. Keep TPM1.2 on Board and Delete TPM1.1 Module Connector designing. <Page 32> 94.08.24.
-Remove R460(@4.7K_0402) and add R557(470_0402). (Modify CKT&BOM)
5. Correct ODD CSEL option setting. <Page 20> 94.08.24.
-Change U61.8, U65.8, R1287.1 and R1288.1 Power Rail from +3VS to +3VALW. (Modify CKT&Layout)
6. Correct SPI I/F Power Source for Capell_Valley_CRB_Schematics_Rev1_502.pdf update . <Page 32> 94.08.26.
7. Modify Mini-Card debug interface design for customer update . <Page 27> 94.08.30.
-Move +3VALW from pin 39 to pin 45 and move CAPS_LED# from pin 41 to pin 51. (Modify CKT&Layout)
4. Update TPM1.2 chip PCB layout footprint. <Page 32> 94.08.24.
-Change U66 PCB Footprint from SLD9630TT_TSSOP28 to SLB-9635-TT-1P2_TSSOP28. (Modify CKT&Layout)
8. Update ADI1981HD CIS symbol and PCB Footprint . <Page 28> 94.08.30.
-Update U14 CIS symbol and change PCB Footprint from AD1981B_LQFP48 to AD1981HDJSTZ-REEL_LQFP48.
(Modify CKT&Layout)
9. Change PCI-E Ports for ICH7 modify . <Page 21,24,35> 94.08.31.
-Change ExpressCard (NC) connection to port 3, Change Docking connection to port 4. (Modify CKT&Layout)
10. Update Accelerometer related design for customer request . <Page 19,21,33,36> 94.09.02.
-Del D61, C1018, R1395 & Q95. (Modify CKT&Layout)
-Add Q75, R187; change D12 to Dual LED. (Modify CKT,BOM&Layout)
-Add net HDD_STP# from GPIO19 of ICH7 to Q75. (Modify CKT&Layout)
-Install R1374 and change R1060 to no-stuff. (Modify CKT&BOM)
-Del R1363 and R1364; Add SB GPIO test pad T80,T89,T99,T106. (Modify CKT,BOM&Layout)
11. Modify Mini-Card debug interface design for customer update . <Page 27> 94.09.02.
-Remove R1435 and R1436(@0_0402). (Modify CKT&BOM)
12. Modify TI PCI7612 designing for vendor request . <Page 23> 94.09.06.
-Change R573 from 10K_0402 to 0_0402. (Modify CKT&BOM)
-Change R594,R1396 and R1397 from 10K_0402 to 100K_0402. (Modify CKT&BOM)
-Change R602 from 10K_0402 to 22K_0402. (Modify CKT&BOM)
13. Update Accelerometer related design for customer request . <Page 19,21,33,36> 94.09.02.
-Add net HDD_STP from GPIO19 of ICH7 to Q84.2. (Modify CKT&Layout)
-Add Q84(2N7002) and R1442(100K_0402) for HDD_STP. (Modify CKT,BOM&Layout)
14. Update ICH7 GPIO related design for customer request . <Page 21> 94.09.06.
-Del R1321 and R1323 related reserved schematic. (Modify CKT&Layout)
-Reserve R1443(@0_0402) for HDD_STP#. (Modify CKT&Layout)
15. Modify LAN controller related for customer request . <Page 25> 94.09.07.
-Add and change R277 from @0_0402 to 10K_0402. (Modify CKT&BOM)
-Remove R1380(@0_0402) and add Q94(2N7002). (Modify CKT&BOM)
-Change R506 pull-up to +3VALW from V_3P3_LAN. (Modify CKT&Layout)
-Add Q100(SI2301BDS), reserve R83(@0_0402) and related schematic. (Modify CKT,BOM&Layout)
16. Modify PCMCIA Connector design for M/E team request . <Page 24> 94.09.08.
-Change JP9 PCBFootprint from SLINK_AFH-1000-17A0-3_104P to TYCO_C-PT05-023-D1_150P_LT.
(Modify CKT,BOM&Layout)
17. Delete New Card, USB HUB related design for customer Spec update . <Page 15,21,24,30,31> 94.09.08.
-Delete R1272,R1273,R1274,R1275,R1276,R1277,R1278,R1279,R1280,R1282,R1316,C959,C960,C961,C962,
C963,C964,C965,C966,C967,C968,C969,C970,C971,C972,C973,U60,R535,C541,L34,C521,C529,C535,C517,
C558,C540,C559,R981,U53,Y6,R984,C22,C27,L37,R1353,R537,R539,R523,R1317,R1318,R1099,R1102,
R1100,R1103,C712,C713; Add T107. (Modify CKT,BOM&Layout)
18. Modify MiniCard related design for customer request. <Page 27> 94.09.08.
-Add Q101,Q102,R1445; Reserve R1444(@0_0805). (Modify CKT,BOM&Layout)
19. Delete FWH I/F BIOS related design for customer request. <Page 15,19,20,21,32> 94.09.08.
-Del &U21(SST49LF008A-33-4C-NH),U21,U20,R273,R278,RP42,R1125,C42,C333. (Modify CKT,BOM&Layout)
-Delete R982,R983 reserve. (Modify CKT&Layout)
-Del R279,C43 reserve. (Modify CKT&Layout)
-Add T108,T109,T110. (Modify CKT&Layout)
-Delete BIOS_SEL1 and replace with short to GND directly. (Modify CKT&Layout)
20. Wire VGA Thermal inform signal with System side for function workable. <Page 21> 94.09.09.
-Add R252(0_0402). (Modify CKT&BOM)
21. Modify MiniCard related design for customer. <Page 27> 94.09.10.
-Add J44(JUMP_43X39) and reserve J45(@JUMP_43X39) for Power Source option. (Modify CKT&Layout)
-Change R1444.1 connection from +3VALW to +3VS. (Modify CKT&Layout)
-Remove Q101,Q102,R1445 and add R1444. (Modify CKT&BOM)
22. Modify TI PCI7612 designing for vendor request . <Page 23> 94.09.10.
-Change R573.1 power connection to +SC_PWR from +5VS. (Modify CKT&Layout)
-Change power rail to R615 & R616 to +3VS from +5VS and remove both R615 & R616. (Modify CKT,BOM&Layout)
23. Modify LAN Transformer designing for customer request . <Page 26> 94.09.10.
-Change R270,R271 connection by add C333 between ground and R270/R271 . (Modify CKT,BOM&Layout)
24. Create an option to use the 32KHz clock from KBC for TPM1.2 for customer request . <Page 32,33> 94.09.10.
-Reserve R1446(@0_0402) to connect U47.58 and U66.13. (Modify CKT&Layout)
25. Delete MiniPCI Debug I/F reserve for Layout space free . <Page 19,27,32> 94.09.12.
-Del R1117,R235,R441,R447,R451,R452 and JP20. (Modify CKT,BOM&Layout)
-Del R448,C537,R437 and Q49 reserve. (Modify CKT&Layout)
-Change R1420.1 connection from +3VALW to +3VL. (Modify CKT&Layout)
-Change C292,C538,C542 power source from +3VS to +3VS_MINI. (Modify CKT&Layout)
-Add H29,H30(H_C236D157)(MiniCard Stand Off). (Modify CKT,BOM&Layout)
26. Change Jopen PAD for CIC DFx request . <Page 15> 94.09.12.
-Change J29 PCBfootprint to JUMP_43X39. (Modify CKT&Layout)
27. Change LAN chip desgin to switch LAN power with LP_EN# for customer request . <Page 25> 94.09.13.
-Install R15(4.7K_0402_5%) and no-stuff U36(@SN74LVC1G17DBVR_SOT23-5). (Modify CKT&BOM)
28. Modify TPM1.2 related design about the ADP_EN for customer request . <Page 32,33> 94.09.13.
-Reserve R1447(@0_0402) close to Y8.1. (Modify CKT&Layout)
-Reserve R1448(@0_0402) for ADP_EN. (Modify CKT&Layout)
29. Modify BT related design for customer request . <Page 30> 94.09.14.
-Change R454 to 47K from 1K. (Modify CKT&BOM)
-Reserve a 0.1uF cap (no-stuff) from R454.2 to ground. (Modify CKT&Layout)
-Add R458(0_0402) between Q100.2 and Q94.1. (Modify CKT,BOM&Layout)
30. Modify LAN chip related design for customer request . <Page 25> 94.09.14.
-Reserve R1032,C722 close to U14.6. (Modify CKT&Layout)
31. Modify BITCLK related design for EMI request . <Page 20,28,34> 94.09.14.
-Move R1028, C721 close to JP32.12; R1314,R371 close to U26.U1. (Modify CKT&Layout)
32. Modify LID_SW# related design for M/E request . <Page 34> 94.09.14.
-Add R1449 close to JP18.16. (Modify CKT,BOM&Layout)
33. Modify Clock Gen. related design for Vendor request . <Page 15> 94.09.14.
-Change R1092 from 475_0402_1% to 4.7K_0402_1%. (Modify CKT&BOM)
34. Modify NB chip CFG11 related design for Intel CRB Rev1_502 update . <Page 11> 94.09.14.
-Remove R1154(@2.2K_0402_5%). (Modify CKT&BOM)
35. Modify Smart AC Adaptor related design for customer request . <Page 11> 94.09.14.
-Change R1237 from 10K_0402 to 100K_0402. (Modify CKT&BOM)
1 2 3 4
4
5
5
11
22
33
44
Title
SizeDocument NumberRev
Date:Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2821P
0.5
H/W2 EE Dept. PIR SHEET(5)
5252Friday, November 25, 2005
2005/03/102006/03/10
Compal Electronics, Inc.
EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >
36. Add DDR2 Module Thermal inform function to NB for customer request. <Page 7,13,14> 94.09.15.
-Add R1450(0_0402) between DDR_THERM# and PM_EXTTS#0 . (Modify CKT,BOM&Layout)
37. Reserve a cap at JP30.P2 pin for +5VS of Docking for customer request. <Page 35> 94.09.15.
-Reserve C1033(@22U_0805_6.3V4Z) close to JP30.P2. (Modify CKT&Layout)
38. Delete Bulk Cap. Daul Layout design reserve for DFx request. <Page 18> 94.09.15.
-Change C633 from @47U_25V(Non-LF) to 100U_25V(250',10sec,LF); Del C1013~C1017 . (Modify CKT,BOM&Layout)
39. Remove all Clock Gen. pairs Pull-Down Resistors for LP design recommend. <Page 15> 94.09.15.
-Remove R1071,R1073,R1076,R1082,R1119,R1122,R1094,R1096,R1258,R1260,R1112,R1116,R1250,R1252,
R1124,R1127,R1134,R1137,R1238,R1239. (Modify CKT&BOM)
-Del C823(100U 6.3V M B (6.3X6.0) CV-AX),C939,C830,C806(220U_C6_6.3V_M_R15) . (Modify CKT&Layout)
-Del C979(220U_D2_2VK_R9); Change C670 to SF22001M300. (Modify CKT,BOM&Layout)
-Del C1012(150U_D_6.3VM); Change C671 to SF22001M300. (Modify CKT,BOM&Layout)
-Del C567,C568(150U_D_6.3VM); Change C1,C527 to SF22001M300. (Modify CKT,BOM&Layout)
40. Modify XMIT_OFF related design for S/W request. <Page 27> 94.09.16.
-Add R1424(0_0402) between XMIT_OFF and XMIT_OFF#. (Modify CKT,BOM&Layout)
41. Modify TI PCMCIA Controller related design for Vendor request. <Page 23,24> 94.09.16.
-Add R591(0_0402) close to U42.E2. (Modify CKT,BOM&Layout)
-Add R617~R620,R623,R624(0_0402) close to JP41. (Modify CKT,BOM&Layout)
-Reserve C369,C372,C373,R593,R599,R613,R614 close to JP9. (Modify CKT&Layout)
-Remove R565. (Modify CKT&BOM)
42. Modify Audio Codec related design to avoid a small amount of noise on pin 2 could cause the codec to power
up in a test mode. <Page 28> 94.09.21.
-Change R422 from @0_0402 to 10K_0402. (Modify CKT&BOM)
43. Modify ICH7 related design for ICH7M & 3945abg Host Interface auto-detect sequence Issue (Sighting# 80332).
<Page 21> 94.09.21.
-Change decoupling caps (C710 & C711) from 0.1uF_0402 to 0.15uF_0603). (Modify CKT,BOM&Layout)
44. Modify Clock Gen. all series termination resistors for the differential signals related design for ICS recommend.
<Page 15> 94.09.21.
-Change R1070,R1072,R1075,R1081,R1118,R1121,R1257,R1259,R1093,R1095,R1144,R1145,R1123,R1126,R1111,
R1115,R1249,R1251 from 33_0402 to 24_0402. (Modify CKT&BOM)

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